首页资源分类IC设计及制造 > NT35510规格书

NT35510规格书

已有 460221个资源

下载专区


TI最新应用解决方案

工业电子 汽车电子 个人消费电子

文档信息举报收藏

标    签: NT35510

分    享:

文档简介

手机显示屏驱动器NT35510规格书

文档预览

NT35510 One-chip Driver IC with internal GRAM for 16.7M colors 480RGB x 864 a-Si TFT LCD with CPU / RGB / MIPI / MDDI Interface or without internal CGRAM for 16.7M colors 480RGB x 1024 a-Si TFT LCD with RGB Interface V0.8 Preliminary ÁꗬꗬЉ 10/28/2011 1 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 REVISION HISTORY................................................................................................................................................8 1 DESCRIPTION ....................................................................................................................................................12 1.1 PURPOSE OF THIS DOCUMENT .............................................................................................................................12 1.2 GENERAL DESCRIPTION ......................................................................................................................................12 2 FEATURES .........................................................................................................................................................13 3 BLOCK DIAGRAM ..............................................................................................................................................15 4 PIN DESCRIPTION .............................................................................................................................................16 4.1 POWER SUPPLY PINS..........................................................................................................................................16 4.2 80-SYSTEM INTERFACE PINS...............................................................................................................................17 4.3 SPI /I2C INTERFACE PINS ...................................................................................................................................17 4.4 RGB INTERFACE PINS ........................................................................................................................................18 4.5 MIPI/MDDI INTERFACE PINS...............................................................................................................................19 4.6 INTERFACE LOGIC PINS.......................................................................................................................................20 4.7 DRIVER OUTPUT PINS .........................................................................................................................................22 4.8 DC/DC CONVERTER PINS ...................................................................................................................................23 4.9 LABC AND CABC CONTROL PINS ...............................................................................................................25 4.10 TEST PINS .....................................................................................................................................................26 5 FUNCTIONAL DESCRIPTION............................................................................................................................27 5.1 MPU INTERFACE.................................................................................................................................................27 5.1.1 Interface Type Selection .......................................................................................................................................27 5.1.2 80-series MPU Interface........................................................................................................................................28 5.1.3 Serial Interface.......................................................................................................................................................46 5.2 I2C INTERFACE ...................................................................................................................................................55 5.2.1 Slave Address of I2C.............................................................................................................................................56 5.2.2 Register Write Sequence of I2C Interface ...........................................................................................................56 5.2.3 RAM Data Write Sequence of I2C Interface.........................................................................................................56 5.2.4 Register Read Sequence of I2C Interface ...........................................................................................................60 5.2.5 RAM Data Read Sequence of I2C Interface.........................................................................................................60 5.3 MIPI INTERFACE .................................................................................................................................................64 5.3.1 Display Module Pin Configuration for DSI ..........................................................................................................65 5.3.2 Display Serial Interface (DSI) ...............................................................................................................................66 5.3.3 Memory Write/Read Format................................................................................................................................152 5.3.4 System Power-Up and Initialization...................................................................................................................159 5.4 MDDI INTERFACE .............................................................................................................................................160 5.4.1 MDDI Link Protocol by The NT35510 .................................................................................................................161 10/28/2011 2 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.4.2 MDDI Link Packet Descriptions by the NT35510 ..............................................................................................162 5.4.3 Writing Video Data to Memory Sequence..........................................................................................................172 5.4.4 Writing Register Sequence.................................................................................................................................172 5.4.5 Reading Video Data from Memory Sequence ...................................................................................................173 5.4.6 Reading Register Sequence...............................................................................................................................173 5.4.7 Hibernation Setting .............................................................................................................................................174 5.4.8 MDDI Deep Standby Mode Setting.....................................................................................................................175 5.5 INTERFACE PAUSE ............................................................................................................................................177 5.6 DATA TRANSFER BREAK AND RECOVERY ..........................................................................................................178 5.7 DISPLAY MODULE DATA TRANSFER MODES.......................................................................................................180 5.8 RGB INTERFACE...............................................................................................................................................181 5.8.1 General Description ............................................................................................................................................181 5.8.2 RGB Interface Timing Chart ...............................................................................................................................182 5.8.3 RGB Interface Mode Set .....................................................................................................................................183 5.8.4 RGB Interface Bus Width Set .............................................................................................................................187 5.9 FRAME MEMORY ...............................................................................................................................................191 5.9.1 Configuration.......................................................................................................................................................191 5.9.2 Address Counter .................................................................................................................................................192 5.9.3 Interface to Memory Write Direction..................................................................................................................193 5.9.4 Frame Memory to Display Address Mapping....................................................................................................194 5.10 TEARING EFFECT INFORMATION.......................................................................................................................195 5.10.1 Tearing Effect Output Line ...............................................................................................................................195 5.10.2 Tearing Effect Bus Trigger................................................................................................................................200 5.11 CHECKSUM.....................................................................................................................................................212 5.12 POWER ON/OFF SEQUENCE ............................................................................................................................214 5.12.1 Case 1 – RESX line is held High or Unstable by Host at Power On ..............................................................215 5.12.2 Case 2 – RESX line is held Low by host at Power On....................................................................................216 5.12.3 Uncontrolled Power Off ....................................................................................................................................216 5.13 POWER LEVEL MODES ....................................................................................................................................217 5.13.1 Definition............................................................................................................................................................217 5.13.2 Power Level Mode Flow Chart..........................................................................................................................218 5.14 RESET FUNCTION ............................................................................................................................................220 5.14.1 Register Default Value ......................................................................................................................................220 5.14.2 Output or Bi-directional (I/O) Pins ...................................................................................................................222 5.14.3 Input Pins...........................................................................................................................................................222 10/28/2011 3 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.15 SLEEP OUT-COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE ......................................223 5.15.1 Register loading Detection...............................................................................................................................223 5.15.2 Functionality Detection.....................................................................................................................................224 5.15.3 Chip Attachment Detection ..............................................................................................................................225 5.16 DISPLAY PANEL COLOR CHARACTERISTICS .....................................................................................................226 5.17 GAMMA FUNCTION ..........................................................................................................................................227 5.18 BASIC DISPLAY MODE.....................................................................................................................................228 5.19 INSTRUCTION SETTING SEQUENCE...................................................................................................................229 5.19.1 Sleep In/Out Sequence .....................................................................................................................................229 5.19.2 Deep Standby Mode Enter/Exit Sequence.......................................................................................................230 5.20 INSTRUCTION SETUP FLOW .............................................................................................................................231 5.20.1 Initializing with the Built-in Power Supply Circuits ........................................................................................231 5.20.2 Power OFF Sequence .......................................................................................................................................232 5.21 MTP WRITE SEQUENCE ..................................................................................................................................233 5.22 DYNAMIC BACKLIGHT CONTROL FUNCTION......................................................................................................234 5.22.1 PWM Control Architecture................................................................................................................................236 5.22.2 Dimming Function for LABC and Manual Brightness Control ......................................................................241 5.22.3 Dimming Function for CABC and Force PWM Function................................................................................244 5.22.4 PWM Signal Setting for CABC and LABC .......................................................................................................245 5.22.5 Content Adaptive Brightness Control (CABC)................................................................................................247 5.22.6 Ambient Light Sensor and Automatic Brightness Control (LABC)...............................................................248 5.23 COLUMN, 1-DOT, 2-DOT, 3-DOT AND 4-DOT INVERSION (VCOM DC DRIVE).....................................................255 6 COMMAND DESCRIPTIONS ...........................................................................................................................256 6.1 USER COMMAND SET........................................................................................................................................256 NOP (0000h) ..................................................................................................................................................................260 SWRESET: Software Reset (0100h) ............................................................................................................................261 RDDID: Read Display ID (0400h~0402h).....................................................................................................................262 RDNUMED: Read Number of Errors on DSI (0500h)..................................................................................................263 RDDPM: Read Display Power Mode (0A00h) .............................................................................................................264 RDDMADCTL: Read Display MADCTL (0B00h)..........................................................................................................265 RDDCOLMOD: Read Display Pixel Format (0C00h) ..................................................................................................266 RDDIM: Read Display Image Mode (0D00h) ...............................................................................................................267 RDDSM: Read Display Signal Mode (0E00h) .............................................................................................................268 RDDSDR: Read Display Self-Diagnostic Result (0F00h)...........................................................................................269 SLPIN: Sleep In (1000h) ...............................................................................................................................................270 10/28/2011 4 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 SLPOUT: Sleep Out (1100h).........................................................................................................................................272 PTLON: Partial Display Mode On (1200h) ..................................................................................................................274 NORON: Normal Display Mode On (1300h)................................................................................................................275 INVOFF: Display Inversion Off (2000h).......................................................................................................................276 INVON: Display Inversion On (2100h).........................................................................................................................277 ALLPOFF: All Pixel Off (2200h) ...................................................................................................................................278 ALLPON: All Pixel On (2300h) .....................................................................................................................................280 GAMSET: Gamma Set (2600h).....................................................................................................................................282 DISPOFF: Display Off (2800h) .....................................................................................................................................283 DISPON: Display On (2900h) .......................................................................................................................................284 CASET: Column Address Set (2A00h~2A03h) ...........................................................................................................285 RASET: Row Address Set (2B00h~2B03h) .................................................................................................................287 RAMWR: Memory Write (2C00h) .................................................................................................................................289 RAMRD: Memory Read (2E00h) ..................................................................................................................................290 PTLAR: Partial Area (3000h~3003h)............................................................................................................................291 TEOFF: Tearing Effect Line OFF (3400h)....................................................................................................................294 TEON: Tearing Effect Line ON (3500h) .......................................................................................................................295 MADCTL: Memory Data Access Control (3600h).......................................................................................................296 IDMOFF: Idle Mode Off (3800h) ...................................................................................................................................299 IDMON: Idle Mode On (3900h) .....................................................................................................................................300 COLMOD: Interface Pixel Format (3A00h)..................................................................................................................302 RAMWRC: Memory Write Continue (3C00h) ..............................................................................................................303 RAMRDC: Memory Read Continue (3E00h) ...............................................................................................................304 STESL: Set Tearing Effect Scan Line (4400h~4401h)................................................................................................305 GSL: Get Scan Line (4500h~4501h) ............................................................................................................................307 DPCKRGB: Display Clock in RGB Interface (4A00h) ................................................................................................308 DSTBON: Deep Standby Mode On (4F00h) ................................................................................................................309 WRPFD: Write Profile Value for Display (5000h~500Fh) ...........................................................................................310 WRDISBV: Write Display Brightness (5100h) ............................................................................................................ 311 RDDISBV: Read Display Brightness (5200h) .............................................................................................................312 WRCTRLD: Write CTRL Display (5300h) ....................................................................................................................313 RDCTRLD: Read CTRL Display Value (5400h) ...........................................................................................................315 WRCABC: Write Content Adaptive Brightness Control (5500h) ..............................................................................317 RDCABC: Read Content Adaptive Brightness Control (5600h) ...............................................................................318 WRHYSTE: Write Hysteresis (5700h~573Fh) .............................................................................................................319 10/28/2011 5 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 WRGAMMSET: Write Gamma Setting (5800h~5807h) ...............................................................................................321 RDFSVM: Read FS Value MSBs (5A00h) ....................................................................................................................323 RDFSVL: Read FS Value LSBs (5B00h)......................................................................................................................324 RDMFFSVM: Read Median Filter FS Value MSBs (5C00h) ........................................................................................325 RDMFFSVL: Read Median Filter FS Value LSBs (5D00h)..........................................................................................326 WRCABCMB: Write CABC minimum brightness (5E00h).........................................................................................327 RDCABCMB: Read CABC minimum brightness (5F00h) ..........................................................................................328 WRLSCC: Write Light Sensor Compensation Coefficient Value (6500h~6501h) ....................................................329 RDLSCCM: Read Light Sensor Compensation Coefficient Value MSBs (6600h) ...................................................330 RDLSCCL: Read Light Sensor Compensation Coefficient Value LSBs (6700h) .....................................................331 RDBWLB: Read Black/White Low Bits (7000h)..........................................................................................................332 RDBkx: Read Bkx (7100h) ...........................................................................................................................................333 RDBky: Read Bky (7200h) ...........................................................................................................................................334 RDWx: Read Wx (7300h)..............................................................................................................................................335 RDWy: Read Wy (7400h) ..............................................................................................................................................336 RDRGLB: Read Red/Green Low Bits (7500h) ............................................................................................................337 RDRx: Read Rx (7600h) ...............................................................................................................................................338 RDRy: Read Ry (7700h) ...............................................................................................................................................339 RDGx: Read Gx (7800h) ...............................................................................................................................................340 RDGy: Read Gy (7900h) ...............................................................................................................................................341 RDBALB: Read Blue/AColor Low Bits (7A00h) .........................................................................................................342 RDBx: Read Bx (7B00h)...............................................................................................................................................343 RDBy: Read By (7C00h)...............................................................................................................................................344 RDAx: Read Ax (7D00h) ...............................................................................................................................................345 RDAy: Read Ay (7E00h) ...............................................................................................................................................346 RDDDBS: Read DDB Start (A100h~A104h) ................................................................................................................347 RDDDBC: Read DDB Continue (A800h~A804h).........................................................................................................349 RDFCS: Read First Checksum (AA00h) .....................................................................................................................351 RDCCS: Read Continue Checksum (AF00h)..............................................................................................................352 RDID1: Read ID1 Value (DA00h)..................................................................................................................................353 RDID2: Read ID2 Value (DB00h)..................................................................................................................................354 RDID3: Read ID3 Value (DC00h)..................................................................................................................................355 7 SPECIFICATIONS.............................................................................................................................................356 7.1 ABSOLUTE MAXIMUM RATINGS..........................................................................................................................356 7.2 ESD PROTECTION LEVEL..................................................................................................................................356 10/28/2011 6 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.3 LATCH-UP PROTECTION LEVEL .........................................................................................................................356 7.4 LIGHT SENSITIVITY ............................................................................................................................................356 7.5 DC CHARACTERISTICS ......................................................................................................................................357 7.5.1 Basic Characteristics..........................................................................................................................................357 7.5.2 MIPI Characteristics ............................................................................................................................................359 7.5.3 MDDI Characteristics ..........................................................................................................................................361 7.5.4 Current Consumption in Standby Mode and DSTB Mode ...............................................................................362 7.6 AC CHARACTERISTICS......................................................................................................................................363 7.6.1 Parallel Interface Characteristics (80-Series MCU) ..........................................................................................363 7.6.2 Serial Interface Characteristics..........................................................................................................................364 7.6.3 I2C Bus Timing Characteristics .........................................................................................................................365 7.6.4 RGB Interface Characteristics ...........................................................................................................................366 7.6.5 MIPI DSI Timing Characteristics ........................................................................................................................367 7.6.6 MDDI Timing Characteristics..............................................................................................................................371 7.6.7 Reset Input Timing ..............................................................................................................................................372 8 REFERENCE APPLICATIONS.........................................................................................................................373 8.1 MICROPROCESSOR INTERFACE..........................................................................................................................373 8.2 CONNECTIONS WITH PANEL...............................................................................................................................378 10/28/2011 7 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 REVISION HISTORY Version Contents 0.00 Original - Page 9, remove 320RGB x 480 - Page 10, Features, remove 320RGB x 480 and MUX description VGHO VGLO for gate control signals, remove VDDIM/VSSIM - Page11, update power voltage range - Page12, Block diagram - Page 13 to 22 : Add : VDD_DET,DIOPWR,PSWAP,DSWAP ,VGHO,VGLO,VRGH, VREFCP,CSP,CSN,LVGL,C61P,C61N,VRGH, VREF,GOUT, Remove : VDDIM/VSSIM, VDDEL Update : MVDDL,VGL,VGH,Test pins - Page23, update IF table - Page 51 to 66 : update SPI,IM3= 1 setting in figure - Page102,103, change DSIM, DSIG bit Reg to 0xB100 - Page115,124 Add WRPFD 50h on table - Page201,modified to 480x864 memory - Page202,Remove 320x480 - Page204, update whole Frame memory table - Page205, TE map to 480 lines, DOPCTR change to B100h - Page207, tvdl TBD - Page225,226,update VDD in figure - Page227,Modes to 7 - Page232,Sout update to Gout 0.01 - Page235,Add chip attachment Detection section - Page237, update Gamma Structure - Page255,270,update FOSC, Example - Page266,update KB_CLED - Page272, Add inversion section - Page273,274, Power Architecture - Page275, update DIOPWR,VREFCP,VGMP1,VGLO - Page276,updateC61P/N,LVGL,VGLO,VRGH,VREFCP,DIOPWR, VGMP1/2,VGMN,VGSP,VGSN, - Page291, change name to RAMKP - Page306 to 312,remove 320x 480 resolution setting - Page337, 5400h Cmd add A and G bit - Page385, Absolute Max Rating for MV HV, remove VDDIM - Page386, VDDIM remove - Page387, Vdev value modified - Page402,403, Remove MVDDI in note - Page406, Remove 320 x 480, update 360x640 Sout sequence - Page173 to 181,MDDI windowless packet - Page377,379, A1,A8 cmd update - Page387 to 396, VDDI to 3.3V - Page362 to 376 70h to 7Eh cmd default value - Page28,29,30,40,41,42 MPU figure update - Page 12,274 Block and power architecture update Prepare d by Kevin Checked by SW Approved by Date Dennis 2010/02/12 Kevin SW Dennis 2010/03/17 10/28/2011 8 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 - Page 10,remove 360RGB x 640, Add 480RGBx720 - Page 11, update GPO[3:0] - Page 12, update VGHO, VGLO - Page 13, update Block Diagram - Page 18, update IM, GPO, VSEL, and EXB1T - Page 20, update VGLO,LVGL - Page 21, update VGLX,VGL_REG, Remove CP6_P/N - Page 23, update VDD_BC - Page 24, update CONTACT1~4, VSSIDUM - Page 25, update IF description table 0.02 - Page 207, update Address Counter Kevin SW Dennis 2010/04/06 - Page 235, update Resolution Data - Page 252, remove CLED_VOL - Page 271, remove KB_CLED_VOL - Page 277, add 4 dot inversion - Page 306,308,313,326 resolution update, remove nHD, add 480x720 - Page 384, update absolute voltage - Page 385, update DC spec - Page 386, update Note3,Note5 - Page 405, update resolution - Page 406, update Alignment Mark - Page 10,11,205,206,234,305,307,312,325,404, update resolution - Page 13, update Block diagram - Page 17-24, update pin description(MDDI not support DSWAP, Update TE_R,TE_L, DSTB_SEL, RESX,VSEL,VREF_PWR, I2C_SDA remove VDD_BD, ENDIOV) - Page 104,121, remove generic data type 0x24 - Page 134, update EoTP Option - Page 175, update MDDI support type 0.03 - Page 176,177, update sub frame header, link shut down packet Kevin SW Dennis 2010/05/18 - Page 179,180, update skew calibration packet, client capability packet - Page 184, update packet type is 20 - Page 209,214, update TE off,output is low, tering effect bus trigger - Page 241, update gamma to 10 bits setting - Page 276, update 3-dots inversion - Page 384, update VIH,VIL,VOH,VOL - Page 388, update hibernation wake up - Page 390,392 update Note2 - Remove pad chapter to application note 10/28/2011 9 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 - Page 14, update Block diagram of RGBBP - Page 16, update WRX/SCL/I2C_SCL, SDI/I2C_SDA - Page 19~25, update IM3 pin description,RGBBP(remove I2C_SA1) OSC_Test description, KBBC to test pin - Page 21, update VREF_PWR description - Page 26, update IM table - Page 42~44, update MPU read scription - Page 49~52, update SPI+RGB or SPI+MDDI description 0.04 - Page 60, update I2C Address - Page 181,182, update 16 bit SPI pause description Kevin SW Dennis 2010/07/27 - Page 187~189, update RGB figure - Page 200, update TE waveform in RGB mode 2 - Page 237, MTP sequence - Page 238~258, update one dimming control for LABC & CABC, remove KBBC function description - Page 260,update 0x04 Cmd, remove KBBC Cmd - Page 262, update 0xA1,0xA8 Cmd - Remove all the KBBC related function, register - Page 11, 12, 190, 191, 219, 284~287, 291, 304, 376, remove 480RGBx360 - Page 15, update MTP_PWR application voltage - Page 16, update CSX, RDX, DC/X, SDI, SDO - Page 18, update DSWAP - Page 19, correct typo for IM[3:0] in MDDI+SCL(falling edge) - Page 38 & 44, update typo for data format in table 0.05 - Page 53, update read data 8-8-8-bit only in SPI - Page 183, 184, update note for min. porch of RGB interface Kevin SW Dennis 2010/10/18 - Page 232, update MTP sequence and MTP_PWR voltage - Page 235, 236, remove PWM_ENH_OE bit (keep x2) - Page 312, 314, update typo for BCTRL and BL - Page 371, 372: update figures - Page 373: update figure, add RGB+I2C - Page 374: update figures, IM setting - Page 375: update figures, IM setting - Page 15, update DVDD typical voltage - Page 129, update typo in figure of AwER - Page 194, update typo for Hsync - Page 218, add condition of irregular power off - Page 219, 255, update command name typo of 05h command - Page 228~231, update typo in figures - Page 234, update typo for ALS in figure 5.22.1 0.1 - Page 235, update CLED_VOL bit in figure 5.22.2 Kevin SW Dennis 2010/12/24 - Page 312, 314, update typo for BCTRL & BL bits - Page 316, update typo in flow chart - Page 346, update description of parameter - Page 355, update maximum rating for VGH, VGLX - Page 358, 359, update 2 lane description in condition - Page 362, update pin name typo in figure - Page 376, update typo for CRGB condition 10/28/2011 10 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 - Page 244, update register control table for CABC 0.2 - Page 362, update sleep in and DSTB power consumption - Page 357, update source deviation max voltage 0.3 - Page 17, update CSX connection in MDDI+SPI - Page 176, 230~232, update delay time after H/W reset and SLPIN - Page 19, update LANSEL used for MIPI only - Page 20, update TE_L & TE_R application connection 0.4 - Page 55, update typo for ACK of I2C - Page 313, 315, remove typo for KBV[7:0] in command 53h & 54h - Page 357, update typical spec of source output voltage deviation - Page 17, update unused connection for CSX, WRX, RDX, DCX - Page 184, 185, update tVHS 0.5 - Page 362, update current consumption of sleep in mode - Page 366, RGB Mode, tHVPD to 0 - Page 369, CLK-POST time update to fit 1Gbps design 0.6 - Page 362, update current consumption of sleep in mode 0.7 - Page 21, DSTB_SEL description update 0.8 - Page 12,13,17,20,27,374, MPU 18 bits support Kevin SW Dennis 2011/03/18 Kevin SW Dennis 2011/03/23 Kevin SW Dennis 2011/04/19 Kevin SW Dennis 2011/05/20 Kevin SW Dennis 2011/06/13 Kevin SW Dennis 2011/09/05 Kevin SW Dennis 2011/10/26 10/28/2011 11 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 1 DESCRIPTION 1.1 Purpose of this Document This document has been created to provide complete reference specifications for the NT35510. IC design engineers should refer to these specifications when designing ICs, test engineers when testing the compliance of manufactured ICs to guarantee their performance, and application engineers when helping customers to make sure they are using this IC properly. 1.2 General Description The NT35510 device is a single-chip solution for a-Si TFT LCD that incorporates gate drivers and is capable of 480RGBx864, 480RGBx854, 480RGBx800, 480RGBx720, 480RGBx640 with internal CGRAM and 480RGB x 1024 by pass internal CGRAM. It includes a 9,953,280 bits internal memory, a timing controller with glass interface level-shifters and a glass power supply circuit.. The NT35510 supports MDDI interface, MIPI Interface, 16/18/24 bits RGB interface, 8/16//18/24-bit system interfaces, serial peripheral interfaces (SPI) and I2C interface. The specified window area can be updated selectively, so that moving pictures can be displayed simultaneously independent of the still picture area. The 480RGB x 1024 by pass CGRAM application is used for RGB interface only. The NT35510 is also able to make gamma correction settings separately for RGB dots to allow benign adjustments to panel characteristics, resulting in higher display qualities. The IC possesses internal GRAM that stores 480-RGB x 864-dot 16.77M-color images. A deep standby mode is also supported for lower power consumption. This LSI is suitable for small or medium-sized portable mobile solutions requiring long-term driving capabilities, including bi-directional pagers, digital audio players, cellular phones and handheld PDA.. 10/28/2011 12 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 2 FEATURES ◆ Single chip WVGA a-Si TFT LCD Controller/driver with Display RAM. ◆ Display resolution option - 480RGB x 1024 by pass GRAM - 480RGB x 864 with 480x24-bitsx 864 GRAM - 480RGB x 854 with 480x24-bitsx 854 GRAM - 480RGB x 800 with 480x24-bitsx 800 GRAM - 480RGB x 720 with 480x24-bitsx 720 GRAM - 480RGB x 640 with 480x24-bitsx 640 GRAM ◆ Display data RAM (frame memory): 480 x 864 x 24-bits = 9,953,280 bits ◆ Display mode (Color mode) - Full color mode: 16.7M-colors - Reduce color mode: 262K colors - Reduce color mode: 65K colors - Idle mode: 8-colors ◆ Interface - 8-/16-/18-/24-bits 80-series MPU interface - 16-bit serial peripheral interface - I2C interface - 16-/18-/24-bits RGB interface (DE mode and SYNC mode with polarity of HS/VS can be set by register) - MIPI Display Serial Interface (DSI V1.01 r11 and D-PHY V1.0, 1 clock and 1 or 2 data lane pairs) - Mobile Display Digital Interface (MDDI V1.2, 1 strobe and 1 or 2 data lane pairs) ◆ Display features - Window address functions for specifying a rectangular area on the internal RAM to write data - Individual gamma correction setting for RGB dots - Deep standby function ◆ On chip - VGHO/VGLO voltage generator for gate control signal and panel - Oscillator for display clock - Supports gate control signals to gate driver in the panel - On module color characteristics - On module checksums checking - Four GPO (General Purpose Output) pins for external control ◆ Supply voltage range - I/O supply voltage range for VDDI to VSSI: 1.65V ~ 3.3V (VDDI) or 1.1 ~ 1.3V (VDDIL) - Analog supply voltage range for VDDB/VDDA/VDDR to VSSB/VSSA/VSSR: 2.3V ~ 4.8V - MIPI/MDDI regulator supply voltage range for VDDAM to VSSAM: 2.3V ~ 4.8V 10/28/2011 13 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY ◆ Output voltage levels - Positive gate driver voltage range for VGH: AVDD+VDDB ~ 2xAVDD - AVEE - Negative gate driver voltage range for VGLX: AVEE+VCL ~ 2xAVEE-AVDD - Step-up 1 output voltage range for AVDD: 4.5 ~ 6.5V - Step-up 2 output voltage range for AVEE: -4.5 ~ -6.5V - Positive gamma high voltage range for VGMP: 3.0 ~ 6.3V (AVDD-0.3V) - Positive gamma low voltage range for VGSP: 0.0, 0.3 ~ 3.7V - Negative gamma high voltage range for VGMN: -3.0 ~ -6.3V (AVEE+0.3V) - Negative gamma low voltage range for VGSN: 0.0, -0.3 ~ -3.7V - Common electrode voltage range for VCOM: 0.0 ~ -3.5V (VCL+0.3V) - Panel voltage range for VRGH: 1.0V ~ 6.0V(AVDD-0.3V) NT35510 10/28/2011 14 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 3 BLOCK DIAGRAM PRELIMINARY WVGA Panel (a-Si GOA LCD) NT35510 S1~S1440 GOUT1~GOUT32 VGMP VGSP VGMN VGSN VREF_PWR VCOM VCOM VGHO VGLO LVGL Bias AVDD Gamma Gen. 1440 Source DA Converter Level Shift Gamma High/Low Voltage Gen. Data Latch VREF Gen. VCOM Gen VDDR DDRAM 480 x 24 x 864 Address Counter …………… Level Shift (VGHO/VGLO) VRGH Gate Output Gen. Timing Gen Charge Pump (1&2) AVDD OSC VRGH Gen DVDD DVSS EXTP CSP CSN EXTN MTP_PWR DVDD Gen PFM1/2 MTP SRAM Data Gen. Command Decoder AVDD AVEE Charge Pump (3&4&5) VGLX VGL_REG Gen VDDAM VREFCP Gen DIOPWR DIOPWR Gen VDDR MIPI/MDDI Voltage Gen MPU / RGB / Serial / I2C Interface & Data Latch (8/16/24 bit MPU, SPI, I2C, 16/18/24 bit RGB) MIPI/MDDI Interface LABC & CABC VDDI VDDR, VDDA, VDDB VDDAM VSSI VSSR, VSSA, VSSB AVSS VSSAM AVDD C11P/C11N C12P/C12N C13P/C13N C14P/C14N AVEE C21P/C21N C22P/C22N C23P/C23N C24P/C24N VRGH VCL C31P/C31N C32P/C32N VGH C41P/C41N VGLX C51P/C51N VGL VGL_REG VREFCP MVDDL MVDDA LEDON LEDPWM HSSI_DATA1_N HSSI_DATA1_P HSSI_CLK_N HSSI_CLK_P HSSI_DATA0_N HSSI_DATA0_P PSWAP DSWAP DSTB_SEL VSEL NBWSEL I2C_SA0 RGBBP LANSEL RESX PCLK DE VS HS CSX RDX WRX / SCL / I2C_SCL SDI / I2C_SDA SDO D/CX D0~D23 TE_R/L ERR IM[3:0] VGSW[3:0] GPO[3:0] 10/28/2011 15 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 4 PIN DESCRIPTION 4.1 Power Supply Pins Symbol Name Description VDDB VDDA VDDR VDD_DET DC/DC Power Analog Power Regulator Power Detection Power Power supply for DC/DC converter VDDB, VDDA and VDDR should be the same input voltage level Power supply for analog system VDDB, VDDA and VDDR should be the same input voltage level Power supply for regulator system VDDB, VDDA and VDDR should be the same input voltage level Connect to VDDB/VDDA/VDDR for detection. VDDAM VDDI DVDD DIOPWR MVDDA MVDDL VSSB VSSA VSSR VSSAM MIPI Power I/O Power Digital Voltage Dual I/O Voltage MIPI/MDDI Voltage MIPI Voltage DC/DC GND Analog GND Regulator GND MIPI GND Power supply for MIPI/MDDI analog regulator system Power supply for interface system except MIPI/MDDI interface Regulator output for logic system power (1.55V typical) Connect a capacitor for stabilization. Regulator output for dual I/O voltage system (1.2V/1.8V typical). Connect a capacitor for stabilization. Regulator output for internal MIPI/MDDI analog system (1.5V typical) Connect a capacitor for stabilization. If not use MIPI/MDDI interface, please open this pin. Regulator output for internal MIPI low power system (1.2V typical) Connect a capacitor for stabilization. If not use MIPI interface, please open this pin System ground for DC/DC converter System ground for analog system System ground for regulator system System ground for internal MIPI/MDDI analog system VSSI DVSS AVSS MTP_PWR I/O GND Digital GND Source OP GND MTP Power System ground for interface system except MIPI/MDDI interface System ground for internal digital system System ground for source OP system. MTP programming power supply pin (7.5 to 8.0V and 7.75V typical) Must be left open or connected to DVSS in normal condition. 10/28/2011 16 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 4.2 80-System Interface Pins Symbol I/O Description CSX WRX / SCL / I2C_SCL RDX D/CX D[23:0] I Chip select input pin (“Low” enable) in 80-series MPU I/F and SPI I/F. This pin is not used for I2C, MIPI, please connect to VDDI this pin. WRX: Writes strobe signal to write data when WRX is “Low” in 80-series MPU I/F. I SCL: A synchronous clock signal in SPI I/F. I2C_SCL: Serial input clock in I2C I/F. This pin is not used for MIPI I/F, please connect to VDDI this pin. I Reads strobe signal to write data when RDX is “Low” in 80-series MPU interface. This pin is not used for 16-bit SPI, I2C, MIPI or MDDI I/F, please connect to VDDI this pin. Display data / command selection in 80-series MPU I/F. I D/CX = ”0” : Command D/CX = ”1” : Display data or Parameter This pin is not used for 16-bit SPI, I2C, MIPI or MDDI I/F, please connect to VDDI this pin. 24-bit bi-directional data bus for 80-series MPU I/F and 24-bit input data bus for RGB I/F. For 8080-series MPU I/F: 8-bit interface: D[7:0] are used, D[23:8] should be connected to VSSI I/O 16-bit interface: D[15:0] are used, D[23:16] should be connected to VSSI 18-bit interface: D[17:0] are used, D[23:18] should be connected to VSSI 24-bit interface: D[23:0] are used These pins are not used for 16-bit SPI, I2C, MIPI or MDDI I/F, please connect to VSSI these pins. NOTE: “1” = VDDI level, “0” = VSSI level. 4.3 SPI /I2C Interface Pins Symbol I/O Description CSX I Chip select input pin (“Low” enable) in 80-series MPU I/F and SPI I/F. This pin is not used for I2C, MIPI, please connect to VDDI this pin.. Writes strobe signal to write data when WRX is “Low” in 80-series MPU I/F. WRX / SCL / I2C_SCL I SCL: A synchronous clock signal in SPI I/F. I2C_SCL: Serial input clock in I2C I/F. This pin is not used for MIPI I/F, please connect to VDDI this pin. SCL: Serial input signal in SPI I/F. The data is input on the rising/falling edge of the SCL signal. SDI / I2C_SDA I/O I2C_SDA: Serial input/output signal in I2C I/F. The data is input/output on the rising edge of the I2C_SCL signal. This pin is not used for 80-series MPU, MIPI or MDDI I/F, please connect to VSSI this pin. Serial output signal in SPI I/F. The data is output on the rising/falling edge of the SCL signal. If SDO O the host places the SDI line into high-impedance state during the read interval, the SDI and SDO can be tied together. This pin is not used for 80-series MPU, I2C, MIPI or MDDI I/F, please open this pin. NOTE: “1” = VDDI level, “0” = VSSI level. 10/28/2011 17 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 4.4 RGB Interface Pins Symbol I/O Description PCLK VS HS DE D[23:0] I Pixel clock signal in RGB I/F. This pin is not used for 80-series MPU, MIPI or MDDI I/F, please connect to VSSI this pin. I Vertical sync. Signal in RGB I/F. This pin is not used for 80-series MPU, MIPI or MDDI I/F, please connect to VSSI this pin. I Horizontal sync. Signal in RGB I/F. This pin is not used for 80-series MPU, MIPI or MDDI I/F, please connect to VSSI this pin. Data enable signal in RGB I/F mode 1. I This pin is not used for RGB mode 2, 80-series MPU, MIPI or MDDI I/F, please connect to VSSI this pin. 24-bit bi-directional data bus for 80-series MPU I/F and 24-bit input data bus for RGB I/F.. For RGB I/F: I/O 16-bit/pixel: D[20:16]=R[4:0], D[13:8]=G[5:0] and D[4:0]=B[4:0], connect unused pins to VSSI 18-bit/pixel: D[21:16]=R[5:0], D[13:8]=G[5:0] and D[5:0]=B[5:0], connect unused pins to VSSI 24-bit/pixel: D[23:16]=R[7:0], D[15:8]=G[7:0] and D[7:0]=B[7:0] These pins are not used for MIPI or MDDI I/F, please connect to VSSI these pins. NOTE: “1” = VDDI level, “0” = VSSI level. 10/28/2011 18 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 4.5 MIPI/MDDI Interface Pins Symbol HSSI_CLK_P HSSI_CLK_N HSSI_D0_P HSSI_D0_N HSSI_D1_P HSSI_D1_N ERR LANSEL DSWAP PSWAP I/O Description -These pins are DSI-CLK+/- differential clock signals if MIPI interface is used. -These pins are MDDI_STB_P/M differential strobe signals if MDDI interface is used. I -HSSI_CLK_P/N are differential small amplitude signals. Ensure the trace length is shortest so that the COG resistance is less than 10 ohm. -If not used, please connect these pins to VSSAM. -These pins are DSI-D0+/- differential data signals if MIPI interface is used. -These pins are MDDI_DATA0_P/M differential strobe signals if MDDI interface is used. I/O -HSSI_D0_P/N are differential small amplitude signals. Ensure the trace length is shortest so that the COG resistance is less than 10 ohm. -If not used, please connect these pins to VSSAM. -These pins are DSI-D1+/- differential data signals if MIPI interface is used. -These pins are MDDI_DATA1_P/M differential strobe signals if MDDI interface is used. I -HSSI_D1_P/N are differential small amplitude signals. Ensure the trace length is shortest so that the COG resistance is less than 10 ohm. -If not used, please connect these pins to VSSAM. CRC and ECC error output pin for MIPI interface. This pin is output low when it is not activated. O When this pin is activated, it output high if CRC/ECC error found. If not used, please open this pin. Input pin to select 1 data lane or 2 data lanes in MIPI interface. LANSEL Data Lane of MIPI/MDDI I 0 1 data lane 1 2 data lanes If not used, please connect to VSSI. Input pin to select HSSI_D0/D1 data lane sequence and polarity in high speed interface only. For MIPI interface, both DSWAP and PSWAP function are available. For MDDI interface, only PSWAP function is available. Please connect DSWAP pin to VSSI. Pin Name HSSI_D0_P HSSI_D0_N HSSI_CLK_P HSSI_CLK_N HSSI_D1_P HSSI_D1_N DSWAP=0 DSI-D0+ PSWAP=0 DSI-D0- DSI-CLK+ DSI-CLK- DSI-D1+ DSI-D1- I DSWAP=0 Input DSI-D0- DSI-D0+ DSI-CLK- DSI-CLK+ DSI-D1- DSI-D1+ PSWAP=1 MIPI Signal DSWAP=1 DSI-D1+ DSI-D1- DSI-CLK+ DSI-CLK- DSI-D0+ DSI-D0- PSWAP=0 DSWAP=1 DSI-D1- PSWAP=1 DSI-D1+ If not used, please connect to VSSI. DSI-CLK- DSI-CLK+ DSI-D0- DSI-D0+ 10/28/2011 19 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 4.6 Interface Logic Pins Symbol I/O Description RESX This signal will reset the device and must be applied to properly initialize the chip. Signal is active low. The input voltage range for RESX pin is related to DSTB_SEL and VSEL pins. Input Voltage Level (DSTB_SEL=”0”) Min. Max. Unit Logic High level input voltage 0.7xVDDI VDDI V VDDI=1.65~3.3V Logic Low level input voltage VSSI 0.3xVDDI V VDDI=1.1~1.3V Logic High level input voltage 0.88 I Logic Low level input voltage VSSI 1.35 V 0.55 V TE (TE_L) TE_R IM[3:0] RGBBP Input Voltage Level (DSTB_SEL=”1”) VDDI=1.65~3.3V Min. Max. VDDIL=1.1~1.3V Unit Min. Max. VSEL Logic High level input voltage 0.7xVDDI VDDI 1.155 1.95 V =High Logic Low level input voltage VSSI 0.3xVDDI VSSI 0.585 V VSEL Logic High level input voltage 0.88 1.35V 0.88 1.35V V =Low Logic Low level input voltage VSSI 0.55 VSSI 0.55 V Tearing effect output pin to synchronize MCU to frame writing, activated by S/W command. O When this pin is not activated, this pin is output low. TE_L and TE_R can not be connected together, choose one side for application. If not used, please open this pin. Tearing effect output pin to synchronize MCU to frame writing, activated by S/W command. O The same output signal as TE (TE_L) pin. TE_L and TE_R can not be connected together, choose one side for application. If not used, please open this pin. Interface type selection. The connections of IM[3:0] which not shown in table are invalid. IM[3:0] Display Data Command 0000 80-series 8-bit MPU I/F, D[7:0] 80-series 8-bit MPU I/F, D[7:0] 0001 80-series 16-bit MPU I/F, D[15:0] 80-series 16-bit MPU I/F, D[15:0] 0010 80-series 18-bit MPU I/F, D[17:0] 80-series 18-bit MPU I/F, D[17:0] 0010 80-series 24-bit MPU I/F, D[23:0] 80-series 24-bit MPU I/F, D[23:0] 0011 RGB I/F, D[23:0] 16-bit SPI (SCL rising edge trigger), SDI/SDO 1011 RGB I/F, D[23:0] I 0100 RGB I/F, D[23:0] 16-bit SPI (SCL falling edge trigger), SDI/SDO I2C I/F, I2C_SDA 0101 MIPI DSI, HSSI_D0_P/N, HSSI_D1_P/N MIPI DSI, HSSI_D0_P/N, HSSI_D1_P/N 0110 MDDI, HSSI_D0_P/N, HSSI_D1_P/N MDDI, HSSI_D0_P/N, HSSI_D1_P/N 16-bit SPI (SCL rising edge trigger), SDI/SDO 1110 MDDI, HSSI_D0_P/N, HSSI_D1_P/N MDDI, HSSI_D0_P/N, HSSI_D1_P/N 16-bit SPI (SCL falling edge trigger), SDI/SDO 0111 MDDI, HSSI_D0_P/N, HSSI_D1_P/N MDDI, HSSI_D0_P/N, HSSI_D1_P/N I2C I/F, I2C_SDA serial data Display data written path control in RGB interface. RGBBP=”0”, display data written to frame memory. I RGBBP=”1”, display data written to line buffer (frame memory by pass mode) When not used in other interfaces, please connect to VSSI. 10/28/2011 20 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 I2C_SA0 Select the I2C interface address from MPU. If not used, please connect to VSSI. I2C_SA0 Slave Address I 0 10011 00 1 10011 01 VSEL GPO[3:0] VGSW[3:0] EXB1T Input pin to switch the I/O voltage. This VSEL function only apply for RESX, TE, LEDPWM, LEDON, KBBC pins. The VSEL dual IO function is valid when DSTB_SEL=”1”. Output Voltage Level DSTB_SEL VDDI VSEL DIOPWR TE LEDON LEDPWM 1.65~3.3V 0 or X Off VOH=VDDI VOL=VSSI 1.1~1.3V VOH=VDDI or VDDA VOL=VSSI Low 1.2V VOH=1.2V VOH=1.2V I 1 1.65~3.3V VOL=VSSI VOL=VSSI High 1.8V VOH=VDDI or DIOPWR VOH=VDDI or VDDA VOL=VSSI VOL=VSSI Low 1.2V VOH=1.2V VOL=VSSI 1 1.1~1.3V High 1.8V VOH=1.8V VOL=VSSI VOH=1.2V VOL=VSSI VOH=1.8V VOL=VSSI The input voltage range for VSEL pin: Input Voltage Level Min. Max. Unit Logic High level input voltage 0.88 VDDI V Logic Low level input voltage VSSI 0.55 V If not used, please connect to VDDI. O General purpose output pins. The output voltage swing is VDDI to VSSI. If not used, please open these pins. I Input pin to select the different application. Input pin to select the external AVDD DC/DC voltage. EXB1T AVDD Voltage I 0 Use internal DC/DC for AVDD 1 Use external DC/DC for AVDD If not used, please connect to VSSI. NBWSEL Input pin to select the voltage sequence of V0 ~ V255. NBWSEL V0 ~ V255 voltage sequence I 0 V(00h)>V(01h)>…>V(FEh)>V(FFh) (Normally White) 1 V(00h)LP-11 2) After DSI-CLK+/- lanes are leaving Ultra Low Power Mode (ULPM, LP-00 State Code) =>LP-10 =>LP-11 (LPM). This sequence is illustrated below. From ULPM to LPM 3) After DSI-CLK+/- lanes are leaving High Speed Clock Mode (HSCM, HS-0 or HS-1 State Code) =>HS-0 =>LP-11 (LPM). This sequence and all three mode changes are illustrated below. HSCM LPM LP-11 Termination Resistor is disable DSI-CLK+ DSI-CLK- HS-0 or HS-1 HS-0 Time LP-11 DSI-CLK+ DSI-CLK- From High Speed Clock Mode (HSCM) to LPM 10/28/2011 68 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY All three mode changes are illustrated a flow chart below. SW Reset HW Reset Power On Sequence NT35510 HS-0 LP-01 LP-00 HS-0 LPM LP-11 LP-10 LP-10 LP-00 ULPM LP-00 HS-1 HS-0 Mode Change HSCM (HS Clocking) All Three Mode Change to LPM on the Flow Chart 10/28/2011 69 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.2.2.2 ULTRA LOW POWER MODE (ULPM) DSI-CLK+/- lanes can be driven to the Ultra Low power Mode (ULPM), when DSI-CLK lanes are entering LP-00 State Code. The only entering possibility is from the Low Power Mode (LPM, LP-11 State Code) =>LP-10 =>LP-00 (ULPM). This sequence is illustrated below. From LPM to ULPM The mode change is also illustrated below. SW Reset HW Reset Power On Sequence HS-0 LP-01 LP-00 HS-0 LPM LP-11 LP-10 LP-10 LP-00 ULPM LP-00 HS-1 HS-0 Mode Change HSCM (HS Clocking) Mode Change from LPM to ULPM on the Flow Chart 10/28/2011 70 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.2.2.3 HIGH SPEED CLOCK MODE (HSCM) DSI-CLK+/- lanes can be driven to the High Speed Clock Mode (HSCM), when DSI-CLK lanes are starting to work between HS-0 and HS-1 State Codes. The only entering possibility is from the Low Power Mode (LPM, LP-11 State Code) =>LP-01 =>LP-00 =>HS-0 =>HS-0/1 (HSCM). This sequence is illustrated below. From LPM to HSCM The mode change is also illustrated below. SW Reset HW Reset Power On Sequence HS-0 LP-01 LP-00 HS-0 LPM LP-11 LP-10 LP-10 LP-00 ULPM LP-00 HS-1 HS-0 Mode Change HSCM (HS Clocking) Mode Change from LPM to HSCM on the Flow Chart 10/28/2011 71 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The high speed clock (DSI-CLK+/-) is started before high speed data is sent via DSI-Dn+/- lanes. The high speed clock continues clocking after the high speed data sending has been stopped. The burst of the high speed clock consists of: o Even number of transitions o Start state is HS-0 o End state is HS-0 LPM LP-11 Termination Resistor is enable HSCM Termination Resistor is disable LPM LP-11 DSI-CLK+ DSI-CLK- LP-11 LP-01 LP-00 HS-0 THE-SKIP HS-0 LP-11 DSI-D0+ DSI-D0- LP-11 Time LP-11 DSI-CLK+ DSI-CLK- Preparation from Low Power Mode to High Speed Mode (TSOT = Start of the Transmission) TLPX THE-PREPARE HSDT DSI-D0+ DSI-D0- LP-11 LP-01 LP-00 THE-SETTLE Low Power Mode, Disable Rx Line Termination HS-0 0 00 1110 1 Rx Synchronized Tx Synchronization High Speed Mode, Enable Rx Line Termination High Speed Data Transmission TEOT LP-11 DSI-CLK+ DSI-CLK- Note DSI-D0+ DSI-D0- THE-SKIP The last load bit THE-TRAIL HS-0 or HS-1 High Speed Mode, Enable Rx Line Termination THE-EXIT Low Power Mode, Disable Rx Line Termination Note: If the last load bit Is HS-0, the transmitter changes from HS-0 to HS-1. If the last load bit Is HS-1, the transmitter changes from HS-1 to HS-0. DSI-CLK+, DSI-D0+ DSI-CLK-, DSI-D0- High Speed Clock Burst 10/28/2011 72 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.2.3 DSI-DATA LANES 5.3.2.2.3.1 GENERAL DSI-D0+/- Data Lanes can be driven in different modes which are: • Escape Mode • High-Speed Data Transmission • Bus Turnaround Request These modes and their entering codes are defined on the following table. Mode Entering Mode Sequence Escape Mode LP-11=>LP-10=>LP-00=>LP-01=>LP-00 High-Speed Data Transmission LP-11=>LP-01=>LP-00=>HS-0 Bus Turnaround Request LP-11=>LP-10=>LP-00=>LP-10=>LP-00 Notes: 1. DSI-D0+/- data lanes are used. 2. More information on section “Bus Turnaround (BTA)” Leaving Mode Sequence LP-00=>LP-10=>LP-11(Mark-1) (HS-0 or HS-1) =>LP-11 High-Z 5.3.2.2.3.2 ESCAPE MODES Data lanes (DSI-D0+/-) can be used in different Escape Modes when data lanes are in Low Power (LP) mode. These Escape Modes are used to: • Send “Low-Power Data Transmission” (LPDT) e.g. from the MCU to the display module • Drive data lanes to “Ultra-Low Power State” (ULPS) • Indicate “Remote Application Reset” (RAR), which is reset the display module • Indicate “Tearing Effect” (TEE), which is used for a TE trigger event from the display module to the MCU • Indicate “Acknowledge” (ACK), which is used for a non-error event from the display module to the MCU The basic sequence of the Escape Mode is as follow • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Escape Command (EC), which is coded, when one of the data lanes is changing from low-to-high-to-low then this changed data lane is presenting a value of the current data bit (DSI-D0+ = 1, DSI-D0- = 0) e.g. when DSI-D0- is changing from low-to-high-to-low, the receiver is latching a data bit, which value is logical 0. The receiver is using this low-to-high-to-low transition for its internal clock. • A load if it is needed • Exit Escape (Mark-1) LP-00 =>LP-10 =>LP-11 • End: LP-11 This basic construction is illustrated below: Escape Mode Entry (EME) Load Escape If needed Command Mark-1 DSI-D0+ DSI-D0- LP-11 LP-10 LP-00 LP-01 LP-00 Time LP-00 LP-10 General Escape Mode Sequence LP-11 DSI-D0+ DSI-D0- 10/28/2011 73 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The number of the different Escape Commands (EC) is eight. These eight different escape commands (EC) can be divided 2 different groups: Mode or Trigger. The MCU is informing to the display module that it is controlling data lanes (DSI-D0+/-) with the mode e.g. The MCU can inform to the display module that it can put data lanes in the low power mode. The MCU is waiting from the display module event information, which has been set by the MCU, with the trigger e.g. when the display module reaches a new V-synch, the display module sent to the MCU a TE trigger (TEE), if the MCU has been requested it. Escape commands are defined on the next table. This basic construction is illustrated below: Escape Command Command Type Mode/Trigger Entry Command Pattern (First Bit => Last Bit Transmitted) Dn D0 Low-Power Data Transmission Mode 1110 0001bin - X Ultra-Low Power Mode Mode 0001 1110bin X X Underfined-1, Note 1 Mode 1001 1111bin - - Underfined-2, Note 1 Mode 1101 1110bin - - Remote Application Reset Trigger 0110 0010bin - X Tearing Effect Trigger 0101 1101bin - X Acknowledge Trigger 0010 0001bin - X Unknow-5, Note 1 Trigger 1010 0000bin - - Notes: 1. This Escape command support has not been implemented on the display module. 2. n=1. 3. “X”=Supported 4. “-“=Not Supported 10/28/2011 74 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Low-Power Data Transmission (LPDT) The MCU can send data to the display module in Low-Power Data Transmission (LPDT) mode when data lanes are entering in Escape Mode and Low-Power Data Transmission (LPDT) command has been sent to the display module. The display module is also using the same sequence when it is sending data to the MCU. The Low Power Data Transmission (LPDT) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Low-Power Data Transmission (LPDT) command in Escape Mode: 1110 0001 (First to Last bit) • Load (Data): • One or more bytes (8 bit) • Data lanes are in pause mode when data lanes are stopped (Both lanes are low) between bytes • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry (EME) Mark-1 LP-11 LP-10 LP-00 LP-01 LP-00 LP-00 LP-10 LP-11 Escape Mode Entry (KME) Low-Power Data Transmission (LPDT) Load (Data) Mark-1 DSI-D0+ DSI-D0- LP-11 11 1 0 0 0 0 1 1 Note Time Note:Load (Data) is presenting that the first bit is logical ‘ 1’ in this example Low-Power Data Transmission (LPDT) Load Byte n Load (Data) Pause Load Byte n+1 LP-11 DSI-D0+ DSI-D0- DSI-D0+ DSI-D0- 1 1 Time 1 1 DSI-D0+ DSI-D0- Pause (Example) 10/28/2011 75 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Ultra-Low Power State (ULPS) The MCU can force data lanes in Ultra-Low Power State (ULPS) mode when data lanes are entering in Escape Mode. The Ultra-Low Power State (ULPS) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Ultra-Low Power State (ULPS) command in Escape Mode: 0001 1110 (First to Last bit) • Ultra-Low Power State (ULPS) when the MCU is keeping data lanes low • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry (EME) Mark-1 LP-11 LP-10 LP-00 LP-01 LP-00 Escape Mode Entry (EME) Ultra-Low Power State (ULPS) LP-00 LP-10 LP-11 Ultra-Low Power State Mark-1 DSI-D0+ DSI-D0- LP-11 00 0 1 1 1 1 0 Time Ultra-Low Power State (ULPS) LP-11 DSI-D0+ DSI-D0- 10/28/2011 76 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Remote Application Reset (RAR) The MCU can inform to the display module that it should be reset in Remote Application Reset (RAR) trigger when data lanes are entering in Escape Mode. The Remote Application Reset (RAR) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Remote Application Reset (RAR) command in Escape Mode: 0110 0010 (First to Last bit) • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry (EME) Mark-1 LP-11 LP-10 LP-00 LP-01 LP-00 LP-00 LP-10 LP-11 Escape Mode Entry (EME) Remote Application Reset (RAR) Mark-1 DSI-D0+ DSI-D0- LP-11 011 0 0 0 1 0 Time Remote Application Reset (RAR) LP-11 DSI-D0+ DSI-D0- 10/28/2011 77 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Tearing Effect (TEE) The display module can inform to the MCU when a tearing effect event (New V-synch) has been happen on the display module by Tearing Effect (TEE). The Tearing Effect (TEE) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Tearing Effect (TEE) trigger in Escape Mode: 0101 1101 (First to Last bit) • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry (EME) Mark-1 LP-11 LP-10 LP-00 LP-01 LP-00 LP-00 LP-10 LP-11 Escape Mode Entry (EME) Tearing Effect Trigger (TEE) Mark-1 DSI-D0+ DSI-D0- LP-11 010 1 1 1 0 1 Time Tearing Effect (TEE) LP-11 DSI-D0+ DSI-D0- 10/28/2011 78 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Acknowledge (ACK) The display module can inform to the MCU when an error has not recognized on it by Acknowledge (ACK). The Acknowledge (ACK) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Acknowledge (ACK) command in Escape Mode: 0010 0001 (First to Last bit) • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry (EME) Mark-1 LP-11 LP-10 LP-00 LP-01 LP-00 LP- LP- LP- 00 10 11 Escape Mode Entry (EME) Acknowledge (ACK) Mark-1 DSI-D0+ DSI-D0- LP-11 001 0 0 0 0 1 Time Acknowledge (ACK) LP-11 DSI-D0+ DSI-D0- 10/28/2011 79 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.2.3.3 HIGH SPEED DATA TRANSMISSION (HSDT) Entering High-Speed Data Transmission (TSOT of HSDT) The display module is entering High-Speed Data Transmission (HSDT) when Clock lanes DSI-CLK+/- have already been entered in the High-Speed Clock Mode (HSCM) by the MCU. See more information on chapter “5.3.2.2.2.3 High-Speed Clock Mode (HSCM)”. Data lanes of the display module are entering (TSOT) in the High-Speed Data Transmission (HSDT) as follows • Start: LP-11 • HS-Request: LP-01 • HS-Settle: LP-00 => HS-0 (Rx: Lane Termination Enable) • Rx Synchronization: 011101 (Tx (= MCU) Synchronization: 0001 1101) • End: High-Speed Data Transmission (HSDT) – Ready to receive High-Speed Data Load This same entering High-Speed Data Transmission (TSOT of HSDT) sequence is illustrated below Preparation from Low Power Mode to High Speed Mode (TSOT = Start of the Transmission) TLPX THE-PREPARE HSDT DSI-CLK+ DSI-CLK- DSI-D0+ DSI-D0- LP-11 LP-10 LP-00 THE-SETTLE Low Power Mode, Disable Rx Line Termination HS-0 0 00 1 11 0 1 Rx Synchronized Tx Synchronization High Speed Mode, Enable Rx Line Termination DSI-CLK+, DSI-D0+ DSI-CLK-, DSI-D0- Entering High-Speed Data Transmission (TSOT of HSDT) 10/28/2011 80 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Leaving High-Speed Data Transmission (TEOT of HSDT) The display module is leaving the High-Speed Data Transmission (TEOT of HSDT) when Clock lanes DSI-CLK+/are in the High-Speed Clock Mode (HSCM) by the MCU and this HSCM is kept until data lanes are in LP-11 mode. See more information on chapter “5.3.2.2.2.3 High-Speed Clock Mode (HSCM)”. Data lanes of the display module are leaving from the High-Speed Data Transmission (TEOT of HSDT) as follows • Start: High-Speed Data Transmission (HSDT) • Stops High-Speed Data Transmission • MCU changes to HS-1, if the last load bit is HS-0 • MCU changes to HS-0, if the last load bit is HS-1 • End: LP-11 (Rx: Lane Termination Disable) This same leaving High-Speed Data Transmission (TEOT of HSDT) sequence is illustrated below High Speed Data Transmission TEOT LP-11 DSI-CLK+ DSI-CLK- Note DSI-D0+ DSI-D0- THE-SKIP The last load bit THE-TRAIL HS-0 or HS-1 High Speed Mode, Enable Rx Line Termination THE-EXIT Low Power Mode, Disable Rx Line Termination Note: If the last load bit Is HS-0, the transmitter changes from HS-0 to HS-1. If the last load bit Is HS-1, the transmitter changes from HS-1 to HS-0. DSI-CLK+, DSI-D0+ DSI-CLK-, DSI-D0- Leaving High-Speed Data Transmission (TEOT of HSDT) 10/28/2011 81 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Burst of the High-Speed Data Transmission (HSDT) The burst of the high-speed data transmission (HSDT) can consist of one data packet or several data packets. These data packets can be Long (LPa) or Short (SPa) packets. These packets are defined on chapter “5.1.9.2.3.1 Short Packet (SPa) and Long Packet (LPa) Structures“. These different burst of the High-Speed Data Transmission (HSDT) cases are illustrated for reference purposes below. LP- 11 SoT LPa EoT LP- 11 LP- 11 SoT SPa EoT LP- 11 Single Packet in High- Speed Data Transmissions LP- 11 SoT LPa SP EoT LP- 11 LP-11 SoT SPa SPa SPa EoT LP- 11 Multiple Packets in High- Speed Data Transmission- Examples HS Transmission Examples with EoT packet disabled LP- 11 LP- 11 EoT Packet SoT LPa SPa EoT LP- 11 EoT Packet SoT SPa SPa EoT LP- 11 Single Packet in High- Speed Data Transmissions LP- 11 SoT LPa SPa LP-11 SoT SPa SPa SPa EoT Packet SPa EoT Packet SPa EoT EoT LP- 11 LP-11 Multiple Packets in High- Speed Data Transmission- Examples HS Transmission Examples with EoT packeten abled Abbreviation EoT LPa LP-11 SPa SoT Explanation End of the Transmission Long Packet Low Power Mode, Data lanes are’1’s (Stop Mode) Short Packet Start of the Transmission 10/28/2011 82 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Bus Turnaround (BTA) The MCU or display module, which is controlling DSI-D0+/- Data Lanes, can start a bus turnaround procedure when it wants information from a receiver, which can be the MCU or display module. The MCU or display module are using the same sequence when this bus turnaround procedure is used. This sequence is described for reference purposes, when the MCU wants to do the bus turnaround procedure to the display module, as follow. • Start (MCU):LP-11 • Turnaround Request (MCU): LP-11  LP-10  LP-00  LP-10  LP-00 • The MCU wait until the display module is starting to control DSI-D0+/- data lanes and the MCU stop to control DSI-D0+/- data lanes (=High-Z) • The display module changes to the stop mode: LP-00  LP-10  LP-11 The same bus turnaround .procedure (From the MCU to the display module) is illustrated below. Bus Turnaround (BTA) MCU Controls Data Lanes Turnaround Request (TAR) The MCU waits until the display module starts to control data lanes (its output drivers) when the MCU can put output drivers in the high-Z mode Display Module Controls Data Lanes LP-Request LP-11 LP-10 LP-00 LP-10 LP-00 Time LP-00 Bus Turnaround Procedure LP-00 LP-10 LP-11 DSI-D0+ DSI-D0- MCU and the display module terms are switched on above figure, if the Bus Turnaround (BTA) is from the display module to the MCU.. 10/28/2011 83 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.3 PACKET LEVEL COMMUNICATION 5.3.2.3.1 SHORT PACKET (SPa) AND LONE PACKET (LPa) STRUCTURE Short Packet (SPa) and Long Packet (LPa) are always used when data transmission is done in Low Power Data Transmission (LPDT) or High-Speed Data Transmission (HSDT) modes. The lengths of the packets are • Short Packet (SPa): 4 bytes • Long Packet (LPa): From 6 to 65,541 bytes The type (SPa or LPa) of the packet can be recognized from their package headers (PH). Packet Header (PH) Packet Data LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) Data 0 and Data 1: Packet Data (8+8 bit) ECC: Error Correction Code (8 bit) EoT: End of Transmission LP-11 SoT DI Data 0 Data 1 ECC EoT LP-11 Time Short Packet (SPa) Structure LP-11 SoT Packet Header (PH) LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) WC: Word Count (16 bit) ECC: Error Correction Code (8 bit) DI Word Count (WC) ECC Data 0, ... WC-1): Packet Data (0 – 65,535 bytes) CS: Checksum (16 bit) = Packet Footer (PF) EoT: End of Transmission Data 0 Data 1 Data WC-2 Data WC-1 Checksum (CS) Time EoT LP-11 Long Packet (LPa) Structure Note: Short Packet (SPa) Structure and Long Packet (LPa) Structure are presenting a single packet sending (= Includes LP-11, SoT and EoT for each packet sendings). The other possibility is that there is not needed SoT, EoT and LP-11 between packets if packets have sent in multiple packet format e.g. * LP-11 =>SoT =>SPa =>LPa =>SPa =>SPa =>EoT =>LP-11 * LP-11 =>SoT =>SPa =>SPa =>SPa =>EoT =>LP-11 * LP-11 =>SoT =>LPa =>LPa =>LPa =>EoT =>LP-11 10/28/2011 84 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.3.1.1 BIT ORDER OF THE BYTE ON PACKETS The bit order of the byte, what is used on packets, is that the Least Significant Bit (LSB) of the byte is sent in the first and the Most Significant Bit (MSB) of the byte is sent in the last. This same order is illustrated for reference purposes below. DI 29hex WC(Least Significant Byte) WC(Most Significant Byte) 01hex 00hex ECC 06hex 10010100100000000000000001100000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Bit Order of the Byte on Packets 5.3.2.3.1.2 BIT ORDER OF THE MULTIPLE BYTE INFORMATION ON PACKETS Byte order of the multiple bytes information, what is used on packets, is that the Least Significant (LS) Byte of the information is sent in the first and the Most Significant (MS) Byte of the information is sent in the last e.g. Word Count (WC) consists of 2 bytes (16 bits) when the LS byte is sent in the first and the MS byte is sent in the last. This same order is illustrated for reference purposes below. WC(Least Significant Byte) WC(Most Significant Byte) 01hex 00hex 1000000000000000 BBBBBBBBBBBBBBBB 0123456701234567 L ML M S SS S B BB B Time Byte Order of the Multiple Byte on Packets 10/28/2011 85 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.3.1.3 PACKET HEADER (PH) The packet header is always consisting of 4 bytes. The content of these 4 bytes are different if it is used to Short Packet (SPa) or Long Packet (LPa). Short Packet (SPa): • 1st byte: Data Identification (DI) => Identification that this is Short Packet (SPa) • 2nd and 3rd bytes: Packet Data (PD), Data 0 and 1 • 4th byte: Error Correction Code (ECC) Packet Header( PH) DI 15hex Data 0 3Ahex Data 1 07hex ECC 18hex 10101000010111001110000000011000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Header (PH) on Short Packet (SPa) Long Packet (LPa): • 1st byte: Data Identification (DI) => Identification that this is Long Packet (LPa) • 2nd and 3rd bytes: Word Count (WC) • 4th byte: Error Correction Code (ECC) Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 01hex 00hex 06hex 10010100100000000000000001100000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Header (PH) on Long Packet (LPa) 10/28/2011 86 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Data Identification (DI) Data Identification (DI) is a part of Packet Header (PH) and it consists of 2 parts: • Virtual Channel (VC), 2 bits, DI[7...6] • Data Type (DT), 6 bits, DI[5…0] The Data Identification (DI) structure is illustrated on a table below. Data Identification (DI) Structure Virtual Channel (VC) Bit 7 Bit 6 Bit 5 Data Identification (DI) Data Type (DT) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Identification (DI) is illustrated on Packet Header (PH) for reference purposes below. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 01hex 00hex 06hex 10010100100000000000000001100000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Data Identification (DI) on the Packet Header (PH) 10/28/2011 87 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Virtual Channel (VC) Virtual Channel (VC) is a part of Data Identification (DI[7…6]) structure and it is used to address where a packet is wanted to send from the MCU. Bits of the Virtual Channel (VC) are illustrated for reference purposes below. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 01hex 00hex 06hex 10010100100000000000000001100000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Virtual Channel (VC) on the Packet Header (PH) Virtual Channel (VC) can address 4 different channels for e.g. 4 different display modules. Devices are using the same virtual channel what the MCU is using to send packets to them e.g. • The MCU is using the virtual channel 0 when it sends packets to this display module • This display module is also using the virtual channel 0 when it sends packets to the MCU This functionality is illustrated below. MCU Long and Short Packets This Display Module Virtual Channel Selector DI[7:6]=VC[1...0]=00b (This display Module) Reserved Reserved Reserved Virtual Channel (VC) Configuration Virtual Channel (VC) always 0 (D[7...6]=VC[1…0]000b) when the MCU is sending “End of Transmission Packet” to the display module. See section “End of Transmission Packet (EoTP) This display module is not supporting the virtual channel selector for other device (1 to 3) when only possible virtual channel (VC[1…0]) is 00b for this display module. 10/28/2011 88 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Data Type (DT) Data Type (DT) is a part of Data Identification (DI[5…0]) structure and it is used to define a type of the used data on a packet. Bits of the Data Type (DT) are illustrated for reference purposes below. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 01hex 00hex 06hex 10010100100000000000000001100000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Data Type (DT) on the Packet Header (PH) 10/28/2011 89 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 This Data Type (DT) also defines what the used packet is: Short Packet (SPa) or Long Packet (LPa). Data Types (DT) are different from the MCU to the display module (or other devices) and vice versa. These Data Type (DT) are defined on tables below. Data Type (DT) from MCU to the Display Module (or Other Devices) Data Type Hex Data Type Binary Description Packet Size Note 08h 00 1000 End of Transmission packet Short 1 05h 00 0101 DCS WRITE, no parameters Short 15h 01 0101 DCS WRITE, 1 parameter Short 06h 00 0110 DCS READ, no parameters Short 37h 11 0111 Set Maximum Return Packet Size Short 09h 00 1001 Null Packet, no data Long 2 19h 01 1001 Blanking Packet, no data Long 2 39h 11 1001 DCS Long Write/Write_LUT Command Packet Long 01h 00 0001 Sync Event, V Sync Start Short 7 11h 01 0001 Sync Event, V Sync End Short 7 21h 10 0001 Sync Event, H Sync Start Short 7 31h 11 0001 Sync Event, H Sync End Short 7 02h 00 0010 Color mode (CM) Off Command Short 7 12h 01 0010 Color mode (CM) On Command Short 7 22h 10 0010 Shut Down Peripheral Command Short 7 32h 11 0010 Turn On Peripheral Command Short 7 13h 01 0011 Generic Short Write, 1 parameter Short 3,4,8 23h 10 0011 Generic Short Write, 2 parameter Short 3,5,8 29h 10 1001 Generic Long Write Long 3,8 14h 01 0100 Generic Read, 1 parameter Short 3,4,8 0Eh 00 1110 Packed Pixel Stream,16-bit RGB, 5-6-5 Format Long 7 1Eh 01 1110 Packed Pixel Stream,18-bit RGB, 6-6-6 Format Long 7 2Eh 10 1110 Loosely Packed Pixel Stream,18-bit RGB, 6-6-6 Format Long 7 3Eh 11 1110 Packed Pixel Stream, 24-bit RGB, 8-8-8 Format Long 7 Notes: 1. This can be used when the MCU wants to secure that there is the end of transmission in High Speed Data Transmission (HSDT) mode. 2. This can be used when the data lanes are wanted to keep in High Speed Data Transmission (HSDT) mode. 3. The receiver process packets with data type (Generic Write/Read) the same way as data type (DCS Write / Read). 4. Generic Write/Read with 1 parameter: Payload Bytes = Command + 00h. 5. Generic Write/Read with 2 parameter: Payload Bytes = Command + Parameter. 6. The receiver will ignore packets with data type that neither listed in table above nor in MIPI DSI spec. 7. The data type for Video Mode Communication: 01h, 11h, 21h, 31h, 02h,12h 22h, 32h, 0Eh, 1Eh, 2Eh, 3Eh will be disable (ignored packet) if bit DSIM of command B100h is set to “0”. 8. The data type for Generic write/read: 13h, 23h, 29h, 14h will be disable (ignored packet) if bit DSIG of command B100h is set to “0”. 10/28/2011 90 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Data Type (DT) from the Display Module (or Other Devices) to the MCU From the Display Module (or Other Devices) to the MCU Hex Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description 02h 0 0 0 0 1 0 Acknowledge with Error Report 1Ch 0 1 1 1 0 0 DCS Read Long Response 21h 1 0 0 0 0 1 DCS Read Short Response, 1 byte returned 22h 1 0 0 0 1 0 DCS Read Short Response, 2 byte returned 1Ah 0 1 1 0 1 0 Generic Read Long Response 11h 0 1 0 0 0 1 Generic Read Short Response, 1 byte returned 12h 0 1 0 0 1 0 Generic Read Short Response, 2 byte returned Short/Lng Packet Short Long Short Short Long Short Short Abbreviation AwER DCSRR-L DCSRR1-S DCSRR2-S GENRR-L GENRR1-S GENRR2-S Note Note Note Note The receiver will ignore other Data Type (DT) if they are not defined on tables: “Data Type (DT) from the MCU to the Display Module (or Other Devices)” or “ Data Type (DT) from the Display Module (or Other Devices) to the MCU”. Note: The data type for Generic write/read: 1Ah, 11h, 12 will be disable (ignored packet) if bit DSIG of command B100h is set to “0”. 10/28/2011 91 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Packet Data (PD) on the Short Packet (SPa) Packet Data (PD) of the Short Packet (SPa) is defined after Data Type (DT) of the Data Identification (DI) has indicated that Short Packet (SPa) is wanted to send. The Word Count (WC) indicates the number of Bytes of Packet of Packet Data (PD) send after the Packet Header. Packet Data (PD) of the Short Packet (SPa) consists of 2 data bytes: Data 0 and Data 1. Packet Data (PD) sending order is that Data 0 is sent in the first and the Data 1 is sent in the last. Bits of Data 1 are set to ‘0’ if the information length is 1 byte. Packet Data (PD) of the Short Packet (SPa), when the length of the information is 1 or 2 bytes are illustrated for reference purposes below, when Virtual Channel (VC) is 0. Packet Data (PD) information: • Data 0: 35hex (Display Command Set (DCS) with 1 Parameter => DI(Data Type (DT)) = 15hex) • Data 1: 01hex (DCS’s parameter) Packet Header (PH) DI Data 0 Data 1 ECC 15hex 35hex 01hex 1Ehex 10101000101011001000000001111000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) for Short Packet (SPa), 2 Bytes Information Packet Data (PD) information: • Data 0: 10hex (DCS without parameter => DI(Data Type (DT)) = 05hex) • Data 1: 00hex (Null) Packet Header (PH) DI Data 0 Data 1 ECC 05hex 10hex 00hex 2Chex 10100000000010000000000000110100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) for Short Packet (SPa), 1 Bytes Information 10/28/2011 92 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Word Count (WC) on the Long Packet (LPa) Word Count (WC) of the Long Packet (LPa) is defined after Data Type (DT) of the Data Identification (DI) has indicated that Long Packet (LPa) is wanted to send. Word Count (WC) indicates a number of the data bytes of the Packet Data (PD) what is wanted to send after Packet Header (PH) versus Packet Data (PD) of the Short Packet (SPa) is placed in the Packet Header (PH). Word Count (WC) of the Long Packet (LPa) consists of 2 bytes. These 2 bytes of the Word Count (WC) sending order is that the Least Significant (LS) Byte is sent in the first and the Most Significant (MS) Byte is sent in the last. Word Count (WC) of the Long Packet (LPa) is illustrated for reference purposes below. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 01hex 00hex 06hex 10010100100000000000000001100000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Word Count (WC) on the Long Packet (LPa) Packet Header (PH) Short Packet (SPa) LP-11 SoT DI Packet Data Data 0 Data 1 ECC LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) Data 0 and Data 1: Packet Data (8+8 bit) ECC: Error Correction Code (8 bit) EoT: End of Transmission EoT LP-11 Short Packet (SPa) Structure Time Long Packet (LPa) LP-11 SoT Packet Header (PH) LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) WC: Word Count (16 bit) ECC: Error Correction Code (8 bit) DI Word Count (WC) ECC Data 0, ... WC-1): Packet Data (0 – 65,535 bytes) CS: Checksum (16 bit) = Packet Footer (PF) EoT: End of Transmission Data 0 Data 1 Data WC-2 Data WC-1 Checksum (CS) Time EoT LP-11 Packet Data in Short and Long Packets Packet Data 10/28/2011 93 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Error Correction Code (ECC) Error Correction Code (ECC) is a part of Packet Header (PH) and its purpose is to identify an error or errors on the Packet Header (PH): The ECC protects the following field” • Short Packet (SPa): Data Identification (DI) byte (8 bits, D[0...7]), Packet Data (PD) bytes (16 bits, D[8...23]) and ECC(8 bits: P[0…7]) • Long Packet (LPa): Data Identification (DI) byte (8 bits, D[0…7]), Word Count (WC) bytes (16 bits: D[8…23]) and ECC (8 bits, P[0…7]) D[23…0] and P[7…0] are illustrated for reference purposes below. Packet Header (PH) DI Data 0 Data 1 ECC 05hex 10hex 00hex 2Chex 10100000000010000000000000110100 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15 D 16 D 17 D 18 D 19 D 20 D 21 D 22 D 23 P0 P1 P2 P3 P4 P5 P6 P7 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time D[23…0] and P[7…0] on the Short Packet (SPa) Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 01hex 00hex 06hex 10010100100000000000000001100000 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15 D 16 D 17 D 18 D 19 D 20 D 21 D 22 D 23 P0 P1 P2 P3 P4 P5 P6 P7 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time D[23…0] and P[7…0] on the Long Packet (LPa) Error Correction Code (ECC) can recognize one error or several errors and makes correction in one bit error case. 10/28/2011 94 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Bits (P[7…0]) of the Error Correction Code (ECC) are defined, where the symbol ‘^’ is presenting XOR function (Pn is ‘1’ if there is odd number of ‘1’s and Pn is ‘0’ if there is even number of ‘1’s), as follows. • P7 = 0 • P6 = 0 • P5 = D10^D11^D12^D13^D14^D15^D16^D17^D18^D19^D21^D22^D23 • P4 = D4^D5^D6^D7^D8^D9^D16^D17^D18^D19^D20^D22^D23 • P3 = D1^D2^D3^D7^D8^D9^D13^D14^D15^D19^D20^D21^D23 • P2 = D0^D2^D3^D5^D6^D9^D11^D12^D15^D18^D20^D21^D22 • P1 = D0^D1^D3^D4^D6^D8^D10^D12^D14^D17^D20^D21^D22^D23 • P0 = D0^D1^D2^D4^D5^D7^D10^D11^D13^D16^D20^D21^D22^D23 P7 and P6 are set to ‘0’ because Error Correction Code (ECC) is based on 64 bit value ([D63…0]), but this implementation is based on 24 bit value (D[23…0]). Therefore, there is only needed 6 bits (P[5…0]) for Error Correction Code (ECC). Packet Header (PH) DI Data 0 Data 1 ECC 05hex 10hex 00hex 2Chex 10100000000010000000000000110100 DDD DD D DD D D 012 45 7 10 11 13 16 D 20 D 21 D 22 D 23 P0 DD DD D D D D D D DDDD 01 34 6 8 10 12 14 17 20 21 22 23 D DD DD D DD D D DDD 0 23 56 9 11 12 15 18 20 21 22 DDD DDD DDD DDD D 123 789 13 14 15 19 20 21 23 DDDDDD DDDDD DD 456789 16 17 18 19 20 22 23 P1 P2 P3 P4 DDDDDDDDDD 10 11 12 13 14 15 16 17 18 19 DDD 21 22 23 P5 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time XOR Functionality on the Short Packet (SPa) Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 01hex 00hex 06hex 10010100100000000000000001100000 DDD DD D DD D D 012 45 7 10 11 13 16 D 20 D 21 D 22 D 23 P0 DD DD D D D D D 01 34 6 8 10 12 14 D 17 DDDD 20 21 22 23 P1 D DD DD 0 23 56 D DD D D DDD 9 11 12 15 18 20 21 22 P2 DDD 123 DDD 789 DDD 13 14 15 DDD D 19 20 21 23 P3 DDDDDD 456789 DDDDD 16 17 18 19 20 DD 22 23 P4 DDDDDDDDDD 10 11 12 13 14 15 16 17 18 19 DDD 21 22 23 P5 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time XOR Functionality on the Long Packet (LPa) 10/28/2011 95 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The transmitter (The MCU or the Display Module) is sending data bits D[23…0] and Error Correction Code (ECC) P[7…0]. The receiver (The Display module or the MCU) is calculate an Internal Error Correction Code (IECC) and compares the received Error Correction Code (ECC) and the Internal Error Correction Code (IECC). This comparison is done when each power bit of ECC and IECC have been done XOR function. The result of this function is PO[7…0]. This functionality, where the transmitter is the MCU and the receiver is the display module, is illustrated for reference purposes below. This Display Module MCU DSI Data: D[0...23] ECC: P[0...7] Internal ECC (IECC) Generator PI[0...7] XOR PO 7 XOR PO 0 Internal Error Correction Code (IECC) on the Display Module (The Receiver) The sent data bits (D[23…0]) and ECC (P[7…0]) are received correctly, if a value of the PO[7…0]) is 00h. The sent data bits (D[23…0]) and ECC (P[7…0]) are not received correctly, if a value of the PO[7…0]) is not 00h. ECC P[7…0] 11000000 03h IECC PI[7…0] 11000000 03h XOR(ECC,IECC) 0 0 0 0 0 0 0 0 =00h => No Error =>PO[7…0] L M S S B B Internal XOR Calculation between ECC and IECC Values – No Error ECC P[7…0] IECC PI[7…0] XOR(ECC,IECC) =>PO[7…0] 11000000 11110000 00110000 L M S S B B 03h 0Fh =0Ch => Error Internal XOR Calculation between ECC and IECC Values - Error The received Error Correction Code (ECC) can be 00h when the Error Correction Code (ECC) functionality is not used for data values D[23…0] on the transmitter side. 10/28/2011 96 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The number of the errors (one or more) can be defined when the value of the PO[7…0] is compared to values on the following table. One Bit Error Value of the Error Correction Code (ECC) Data Bit PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Hex D[0] 0 0 0 0 0 1 1 1 07h D[1] 0 0 0 0 1 0 1 1 0Bh D[2] 0 0 0 0 1 1 0 1 0Dh D[3] 0 0 0 0 1 1 1 0 0Eh D[4] 0 0 0 1 0 0 1 1 13h D[5] 0 0 0 1 0 1 0 1 15h D[6] 0 0 0 1 0 1 1 0 16h D[7] 0 0 0 1 1 0 0 1 19h D[8] 0 0 0 1 1 0 1 0 1Ah D[9] 0 0 0 1 1 1 0 0 1Ch D[10] 0 0 1 0 0 0 1 1 23h D[11] 0 0 1 0 0 1 0 1 25h D[12] 0 0 1 0 0 1 1 0 26h D[13] 0 0 1 0 1 0 0 1 29h D[14] 0 0 1 0 1 0 1 0 2Ah D[15] 0 0 1 0 1 1 0 0 2Ch D[16] 0 0 1 1 0 0 0 1 31h D[17] 0 0 1 1 0 0 1 0 32h D[18] 0 0 1 1 0 1 0 0 34h D[19] 0 0 1 1 1 0 0 0 38h D[20] 0 0 0 1 1 1 1 1 1Fh D[21] 0 0 1 0 1 1 1 1 2Fh D[22] 0 0 1 1 0 1 1 1 37h D[23] 0 0 1 1 1 0 1 1 3Bh One error is detected if the value of the PO[7…0] is on : One Bit Error Value of the Error Correction Code (ECC) and the receiver can correct this one bit error because this found value also defines what is a location of the corrupt bit e.g. • PO[7…0] = 0Eh • The bit of the data (D[23…0]), what is not correct, is D[3] More than one error is detected if the value of the PO[7…0] is not on: One Bit Error Value of the Error Correction Code (ECC) e.g. PO[7…0] = 0Ch. 10/28/2011 97 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.3.1.4 PACKET DATA (PD) ON THE LONG PACKET (LPa) Packet Data (PD) of the Long Packet (LPa) is defined after Packet Header (PH) of the Long Packet (LPa). The number of the data bytes is defined on chapter “Word Count (WC) on the Long Packet (LPa)”. 5.3.2.3.1.5 PACKET FOOTER (PF) ON THE LONG PACKET (LPa) Packet Footer (PF) of the Long Packet (LPa) is defined after the Packet Data (PD) of the Long Packet (LPa). The Packet Footer (PF) is a checksum value what is calculated from the Packet Data of the Long Packet (LPa). The checksum is using a 16-bit Cyclic Redundancy Check (CRC) value which is generated with a polynomial X16+X12+X5+X0 as it is illustrated below. In XOR (In,C0) C15 C14 C13 C12 C11 XOR(XOR (In,C0),C11) C10 C9 C8 C7 C6 C5 C4 XOR(XOR (In,C0),C4) C3 C2 C1 C0 16-bit Cyclic Redundancy Check (CRC) Calculation The 16-bit Cyclic Redundancy Check (CRC) generator is initialized to FFFFh before calculations. The Least Significant Bit (LSB) of the data byte of the Packet Data (PD) is the first bit what is inputted into the 16-bit Cyclic Redundancy Check (CRC). An example of the 16-bit Cyclic Redundancy Check (CRC), where the Packet Data (PD) of the Long Packet (LPa) is 01h, is illustrated (step-by-step) below. In XOR (In,C0) C15 C14 C13 C12 C11 XOR(XOR (In,C0),C11) C10 C9 C8 C7 C6 C5 C4 XOR(XOR (In,C0),C4) C3 C2 C1 C0 Step In 0 X 1 1(LSB) 2 0 3 0 4 0 5 0 6 0 7 0 8 0(MSB) 1 Byte XOR(In,C0) C15 C14 C13 C12 C11 X1 1 1 1 1 00 1 1 1 1 11 0 1 1 1 11 1 0 1 1 11 1 1 0 1 11 1 1 1 0 00 1 1 1 1 00 0 1 1 1 00 0 0 1 1 CRC Resoult 0 0 0 1 1 MSB XOR(XOR (In,C0),C11(Step-1)) C10 C9 C8 C7 C6 C5 C4 X1 1 1 1 1 1 1 11 1 1 1 1 1 1 00 1 1 1 1 1 1 00 0 1 1 1 1 1 00 0 0 1 1 1 1 00 0 0 0 1 1 1 00 0 0 0 0 1 1 11 0 0 0 0 0 0 11 1 0 0 0 0 0 1100000 CRC Calculation – Packet Data (PD) is 01h XOR(XOR (In,C0),C4(Step-1)) C3 C2 C1 C0 C0 X1 1 1 1 X 11 1 1 1 1 00 1 1 1 1 00 0 1 1 1 00 0 0 1 1 00 0 0 0 0 11 0 0 0 0 11 1 0 0 0 11 1 1 0 0 1110 LSB 10/28/2011 98 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 A value of the Packet Footer (PF) is 1E0Eh in this example. This example (Command 01h has been sent) is illustrated below. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 39hex 01hex 00hex 15hex 10011100100000000000000010101000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Packet Data (PD) Packet Footer (PF) Data 0 CRC (Least Significant Byte) CRC (Most Significant Byte) 01hex 0Ehex 1Ehex 100000000111000001111000 BBBBBBBBBBBBBBBBBBBBBBBB 012345670123456701234567 L ML ML M S SS SS S B BB BB B Packet Footer (PF) Example Time The receiver is calculated own checksum value from received Packet Data (PD). The receiver compares own checksum and the Packet Footer (PF) what the transmitter has sent. The received Packet Data (PD) and Packet Footer (PF) are correct if the own checksum of the receiver and Packet Footer (PF) are equal and vice versa the received Packet Data (PD) and Packet Footer (PF) are not correct if the own checksum of the receiver and Packet Footer (PF) are not equal. 10/28/2011 99 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.3.2 PACKET TRANSMISSIONS 5.3.2.3.2.1 PACKET FROM THE MCU TO THE DISPLAY MODULE Display Command Set (DCS) Display Command Set (DCS), which is defined on chapter “6 Instruction Description”, is used from the MCU to the display module. This Display Command Set (DCS) is always defined on the Data 0 of the Packet Data (PD), which is included in Short Packet (SPa) and Long packet (LPa) as these are illustrated below. Short Packet (SPa) Packet Header (PH) Packet Data LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) Data 0 and Data 1: Packet Data (8+8 bit) ECC: Error Correction Code (8 bit) EoT: End of Transmission LP-11 SoT DI Data 0 Data 1 ECC EoT LP-11 Short Packet (Spa) Structure Time Long Packet (LPa) LP-11 SoT Packet Header (PH) LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) WC: Word Count (16 bit) ECC: Error Correction Code (8 bit) DI Word Count (WC) ECC Data 0, ... WC-1): Packet Data (0 – 65,535 bytes) CS: Checksum (16 bit) = Packet Footer (PF) EoT: End of Transmission Data 0 Data 1 Data WC-2 Data WC-1 Checksum (CS) Time EoT LP-11 Packet Data Display Command Set (DCS) Display Command Set (DCS) on Short Packet (SPa) and Long Packet (LPa) 10/28/2011 100 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Generic Write, 1 Parameter (GENW1-S), Data Type = 01 0011 (13h) “Generic Write, 1 Parameter” (GENW1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0011b), from the MCU to the display module. The content of 2 payload bytes is “command” and 00h. These commands are defined on a table (See chapter “6 Instruction Description”) below. Command NOP (00h) SWRESET (01h) SLPIN (10h) SLPOUT (11h) PTLON (12h) NORON (13h) INVOFF (20h) INVON (21h) ALLPOFF (22h) ALLPON (23h) DISPOFF (28h) DISPON (29h) Memory Write (2Ch), Note TEOFF (34h) IDMOFF (38h) IDMON (39h) Note : Subpixel has not been written Short Packet (SPa) is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 01 0011b • Packet Data (PD) • Data 0: “Sleep In (10h)”, Display Command Set (DCS) • Data 1: Always 00hex • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Packet Header (PH) Packet Data DI Data 0 (DCS) Data 1 (Always 00hex) ECC 13hex 10hex 00hex 39hex 10100000000010000000000010011100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Generic Write, 1 Parameter (GENW1-S) - Example 10/28/2011 101 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Generic Write, 2 Parameter (GENW2-S), Data Type = 10 0011 (23h) “Generic Write, 2 Parameter” (GENW2-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 10 0011b), from the MCU to the display module. The content of 2 payload bytes is “command” and “parameter”. These commands are defined on a table (See chapter “6 Instruction Description”) below. Command GAMSET (26h) RAMWR (2Ch), Note TEON (35h) MADCTR (36h) COLMOD (3Ah) RAMWRC (3Ch), Note WRDISBV (51h) WRCTRLD (53h) WRCABC (55h) WRCABCMB (5Eh) Note:One Subpixel has been written. Short Packet (SPa) is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 10 0011b • Packet Data (PD) • Data 0: “PMCSET (3Ah)”, Display Command Set (DCS) • Data 1: 01hex, Parameter of the DCS • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Packet Header (PH) Packet Data DI Data 0 (DCS) Data 1 (Parameter) ECC 23hex 3Ahex 01hex 1Ehex 10101000010111001000000001111000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Generic Write, 2 Parameter (GENW2-S) – Example 10/28/2011 102 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Generic Write Long (GENW-L) , Data Type = 10 1001 (29h) “Generic Write Long” (GENW-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 10 1001b), from the MCU to the display module. Command (No Parameters) and Write (1 or more parameters), are defined on a table (See chapter “6 Instruction Description”) below. Command NOP (00h) , Note1 SWRESET (01h) , Note1 SLPIN (10h) , Note1 SLPOUT (11h) , Note1 PTLON (12h) , Note1 NORON (13h) , Note1 INVOFF (20h) , Note1 INVON (21h) , Note1 ALLPOFF (22h) ALLPON (23h) GAMSET (26h) , Note2 DISPOFF (28h) , Note1 DISPON (29h) , Note1 CASET (2Ah) RASET (2Bh) RAMWR (2Ch) , Note2 RGBSET (2Dh) PARLINES (30h) TEOFF (34h) , Note1 TEON (35h) , Note2 MADCTR (36h) , Note2 IDMOFF (38h) , Note1 IDMON (39h) , Note1 COLMOD (3Ah) , Note2 RAMWRC (3Ch), Note2 TEARLINE (44h) WRPFD (50h) WRDISBV (51h) , Note2 WRCTRLD (53h) WRCABC (55h) , Note2 WRHYSTE (57h) , WRGAMMSET (58h) , WRCABCMB (5Eh) WRLSLC(65h) Notes: 1. Also Short Packet (Spa) can be used; See Generic Write, 1 Parameter. 2. Also Short Packet (Spa) can be used; See Generic Write, 2 Parameter. 10/28/2011 103 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Long Packet (Lpa), when a command (No Parameter) was sent, is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 10 1001b • Word Count (WC) • Word Count (WC): 0001h • Error Correction Code (ECC) • Packet Data (PD): Data 0: “Sleep In (10h)”, Display Command Set (DCS) • Packet Footer (PF) This is defined on the Long Packet (Lpa) as follows. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 01hex 00hex 06hex 10011100100000000000000001100000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 0 10hex CRC(Least Significant Byte) CRC(Most Significant Byte) 06hex 1Fhex 000010000110000011111000 BBBBBBBBBBBBBBBBBBBBBBBB 012345670123456701234567 L ML ML M S SS SS S B BB BB B Time Generic Write Long (GENW-L) with DCS Only - Example 10/28/2011 104 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Long Packet (Lpa), when a Write (1 parameter) was sent, is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 10 1001b • Word Count (WC) • Word Count (WC): 0002h • Error Correction Code (ECC) • Packet Data (PD): • Data 0: “Gamma Set (3Ah)”, Display Command Set (DCS) • Data 1: 01hex, Parameter of the DCS • Packet Footer (PF) This is defined on the Long Packet (Lpa) as follows. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 02hex 00hex 00hex 10011100010000000000000000000000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (DCS) Data 1 (Parameter) 3Ahex 01hex 0101110010000000 BBBBBBBBBBBBBBBB 0123456701234567 L ML M S SS S B BB B Time Packet Footer (PF) CRC(Least Significant Byte) CRC(Most Significant Byte) E3hex AAhex 1100011101010101 BBBBBBBBBBBBBBBB 0123456701234567 L ML M S SS S B BB B Time Generic Long Write with DCS and 1 Parameter - Example 10/28/2011 105 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Long Packet (Lpa), when a Write (4 parameters) was sent, is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 10 1001b • Word Count (WC) • Word Count (WC): 0005h • Error Correction Code (ECC) • Packet Data (PD): • Data 0: “PARLINES (30h)”, Display Command Set (DCS) • Data 1: 00hex, 1st Parameter of the DCS, Start Column SC[15…8] • Data 2: 00hex, 2nd Parameter of the DCS, Start Column SC[7…0] • Data 3: 01hex, 3rd Parameter of the DCS, End Column EC[15…8] • Data 4: 3Fhex, 4th Parameter of the DCS, End Column EC[7…0] • Packet Footer (PF) This is defined on the Long Packet (Lpa) as follows. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 29hex 05hex 00hex 25hex 10011100101000000000000010100100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (DCS) Data 1 (1st Parameter) Data 2 (2nd Parameter) Data 3 (3rd Parameter) 30hex 00hex 00hex 01hex 00001100000000000000000010000000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 4 (4th Parameter) CRC(Least Significant Byte) CRC(Most Significant Byte) 3Fhex F5hex 34hex 110011111111101000101100 BBBBBBBBBBBBBBBBBBBBBBBB 012345670123456701234567 L ML ML M S SS SS S B BB BB B Time Generic Write Long with DCS and 4 Parameters - Example 10/28/2011 106 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Generic Read, 1 Parameter (GENR1-S) , Data Type = 01 0100 (14h) “Generic Read, 1 Parameter (GENR1-S) is always using a Short Packet (Spa), what is defined on Data Type (DT, 01 0100b), from the MCU to the display module. This command is defined on a table (See chapter “6 Instruction Description”) below. The 1st parameter (Dummy Data) is not returned as it is done in MeSSI-8/16 cases. The first returned parameter is the 2nd parameter in DSI case. Command RDNUMED (05h) RDDPM (0Ah) RDDMADCTR (0Bh) RDDCOLMOD (0Ch) RDDIM (0Dh) RDDSM (0Eh) RDDSDR (0Fh) RAMRD (2Eh), Note RAMRDC (3Eh), Note RDDISBV (52h) RDCTRLD (54h) RDCABC (56h) RDFSVM (5Ah) RDFSVL (5Bh) RDMFFSVM (5Ch) RDMFFSVL (5Dh) RDCABCMB (5Fh) RDLSCCM (66h) RDLSCCL (67h) RDBWLB (70h) RDBkx (71h) RDBky (72h) RDWx (73h) RDWy (74h) RDRGLB (75h) RDRx (76h) RDRy (77h) RDGx (78h) RDGy (79h) RDBALB (7Ah) RDBx (7Bh) RDBy (7Ch) RDAx (7Dh) RDAy (7Eh) RDDDBST (A1h) RDDDBC (A8h) RDFCS (AAh) RDCCS (AFh) RDID1 (DAh) RDID2 (DBh) RDID3 (DCh) Note: One Subpixel has been read 10/28/2011 107 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The MCU has to define to the display module, what is the maximum size of the return packet. A command, what is used for this purpose, is “Set Maximum Return Packet Size” (SMRPS-S), which Data Type (DT) is 11 0111b and which is using Short Packet (SPa) before the MCU can send “Display Command Set (DCS) Read, No Parameter” to the display module. This same sequence is illustrated for reference purposes below. Step 1: • The MCU sends “Set Maximum Return Packet Size” (Short Packet (SPa)) (SMRPS-S) to the display module when it wants to return one byte from the display module • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 11 0111b • Maximum Return Packet Size (MRPS) • Data 0: 01hex • Data 1: 00hex • Error Correction Code (ECC) Packet Header (PH) Maximum Return Packet Size(MRPS) DI MRPS(Least Significant Byte) MRPS(Most Significant Byte) ECC 37hex 01hex 00hex 1Dhex 11101100100000000000000010111000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Set Maximum Return Packet Size (SMRPS-S) - Example 10/28/2011 108 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Step 2: • The MCU wants to receive a value of the “Read ID1 (DAh)” from the display module when the MCU sends “Generic Read, 1 Parameter” to the display module • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 01 0100b • Packet Data (PD) • Data 0: “Read ID1 (DAh)”, Display Command Set (DCS) • Data 1: Always 00hex • Error Correction Code (ECC) Packet Header (PH) Packet Data (PD) DI Data 0 (DCS) Data 1 (Always 00hex) ECC 14hex DAhex 00hex 07hex 00101000010110110000000011100000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Generic Read, 1 Parameter (GENR1-S) - Example Step 3: The display module can send 2 different information to the MCU after Bus Turnaround (BTA) 1. An acknowledge with Error Report (AwER), which is using a Short Packet (SPa), if there is an error to receive a command. See section “Acknowledge with Error Report (AwER)”. 2. Information of the received command. Short Packet (SPa) or Long Packet (LPa) 10/28/2011 109 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Display Command Set (DCS) Write, No Parameter (DCSWN-S) , Data Type = 00 0101 (05h) “Display Command Set (DCS) Write, No Parameter” is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 0101b), from the MCU to the display module. These commands are defined on a table (See chapter “6 Instruction Description”) below. Command NOP (00h) SWRESET (01h) SLPIN (10h) SLPOUT (11h) PTLON (12h) NORON (13h) INVOFF (20h) INVON (21h) ALLPOFF (22h) ALLPON (23h) DISPOFF (28h) DISPON (29h) Memory Write (2Ch), Note TEOFF (34h) IDMOFF (38h) IDMON (39h) Note : Subpixel has not been written Short Packet (SPa) is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 00 0101b • Packet Data (PD) • Data 0: “Sleep In (10h)”, Display Command Set (DCS) • Data 1: Always 00hex • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Packet Header (PH) Packet Data DI Data 0 (DCS) Data 1 (Always 00hex) ECC 05hex 10hex 00hex 2Chex 10100000000010000000000000110100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Display Command Set (DCS) Write, No Parameter (DCSWN-S) - Example 10/28/2011 110 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Display Command Set (DCS) Write, 1 Parameter (DCSW1-S) , Data Type = 01 0101 (15h) “Display Command Set (DCS) Write, 1 Parameter” (DCSW1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0101b), from the MCU to the display module. These commands are defined on a table (See chapter “6 Instruction Description”) below. Command GAMSET (26h) Memory Write (2Ch), Note TEON (35h) MADCTR (36h) COLMOD (3Ah) RAMWRC (3Ch), Note WRDISBV (51h) WRCTRLD (53h) WRCABC (55h) WRCABCMB (5Eh) Note:One Subpixel has been written. Short Packet (SPa) is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 01 0101b • Packet Data (PD) • Data 0: “PMCSET (3Ah)”, Display Command Set (DCS) • Data 1: 01hex, Parameter of the DCS • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Packet Header (PH) Packet Data DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex 3Ahex 01hex 1Ehex 10101000010111001000000001111000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Display Command Set (DCS) Write, 1 Parameter (DCSW1-S) – Example 10/28/2011 111 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Display Command Set (DCS) Write Long (DCSW-L) , Data Type = 11 1001 (39h) “Display Command Set (DCS) Write Long” (DCSW-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 11 1001b), from the MCU to the display module. Command (No Parameters) and Write (1 or more parameters), are defined on a table (See chapter “6 Instruction Description”) below Command NOP (00h) , Note1 SWRESET (01h) , Note1 SLPIN (10h) , Note1 SLPOUT (11h) , Note1 PTLON (12h) , Note1 NORON (13h) , Note1 INVOFF (20h) , Note1 INVON (21h) , Note1 GAMSET (26h) , Note2 DISPOFF (28h) , Note1 DISPON (29h) , Note1 CASET (2Ah) RASET (2Bh) RAMWR (2Ch) , Note2 RGBSET (2Dh) PARLINES (30h) SCRLAR (33h) TEOFF (34h) , Note1 TEON (35h) , Note2 MADCTR (36h) , Note2 IDMOFF (38h) , Note1 IDMON (39h) , Note1 COLMOD (3Ah) , Note2 RAMWRC (3Ch), Note2 TEARLINE (44h) WRPFD (50h) WRDISBV (51h) , Note2 WRCTRLD (53h) WRCABC (55h) , Note2 WRHYSTE (57h) , WRGAMMSET (58h) , WRCABCMB (5Eh) WRLSLC(65h) Notes: 1. Also Short Packet (SPa) can be used; See_Display Command Set (DCS) Write, No Parameter. 2. Also Short Packet (SPa) can be used; See Display Command Set (DCS) Write, 1 Parameter. 10/28/2011 112 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Long Packet (LPa), when a command (No Parameter) was sent, is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 11 1001b • Word Count (WC) • Word Count (WC): 0001h • Error Correction Code (ECC) • Packet Data (PD): Data 0: “Sleep In (10h)”, Display Command Set (DCS) • Packet Footer (PF) This is defined on the Short Packet (SPa) as follows. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 39hex 01hex 00hex 15hex 10011100100000000000000010101000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 0 10hex CRC(Least Significant Byte) CRC(Most Significant Byte) 06hex 1Fhex 000010000110000011111000 BBBBBBBBBBBBBBBBBBBBBBBB 012345670123456701234567 L ML ML M S SS SS S B BB BB B Time Display Command Set (DCS) Write Long (DCSW-L) with DCS Only - Example 10/28/2011 113 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Long Packet (LPa), when a Write (1 parameter) was sent, is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 11 1001b • Word Count (WC) • Word Count (WC): 0002h • Error Correction Code (ECC) • Packet Data (PD): • Data 0: “Gamma Set (26h)”, Display Command Set (DCS) • Data 1: 01hex, Parameter of the DCS • Packet Footer (PF) This is defined on the Short Packet (SPa) as follows. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 39hex 02hex 00hex 13hex 10011100010000000000000011001000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (DCS) Data 1 (Parameter) 26hex 01hex 0110010010000000 BBBBBBBBBBBBBBBB 0123456701234567 L ML M S SS S B BB B Time Packet Footer (PF) CRC(Least Significant Byte) CRC(Most Significant Byte) D2hex 96hex 0100101101101001 BBBBBBBBBBBBBBBB 0123456701234567 L ML M S SS S B BB B Time Display Command Set (DCS) Write Long with DCS and 1 Parameter - Example 10/28/2011 114 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Long Packet (LPa), when a Write (4 parameters) was sent, is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 11 1001b • Word Count (WC) • Word Count (WC): 0005h • Error Correction Code (ECC) • Packet Data (PD): • Data 0: “PARLINES (30h)”, Display Command Set (DCS) • Data 1: 00hex, 1st Parameter of the DCS, Start Column SC[15…8] • Data 2: 00hex, 2nd Parameter of the DCS, Start Column SC[7…0] • Data 3: 01hex, 3rd Parameter of the DCS, End Column EC[15…8] • Data 4: 3Fhex, 4th Parameter of the DCS, End Column EC[7…0] • Packet Footer (PF) This is defined on the Short Packet (SPa) as follows. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 39hex 05hex 00hex 36hex 10011100101000000000000001101100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (DCS) Data 1 (1st Parameter) Data 2 (2nd Parameter) Data 3 (3rd Parameter) 30hex 00hex 00hex 01hex 00001100000000000000000010000000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 4 (4th Parameter) CRC(Least Significant Byte) CRC(Most Significant Byte) 3Fhex F5hex 34hex 110011111111101000101100 BBBBBBBBBBBBBBBBBBBBBBBB 012345670123456701234567 L ML ML M S SS SS S B BB BB B Time Display Command Set (DCS) Write Long with DCS and 4 Parameters - Example 10/28/2011 115 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Display Command Set (DCS) Read, No Parameter (DCSRN-S) , Data Type = 00 0110 (06h) “Display Command Set (DCS) Read, No Parameter” (DCSRN-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 0110b), from the MCU to the display module. These commands are defined on a table (See chapter “6 Instruction Description”) below. The 1st parameter (Dummy Data) is not returned as it is done in MeSSI-8/16 cases. The first returned parameter is the 2nd parameter in DSI case. Command RDNUMED (05h) RDDPM (0Ah) RDDMADCTR (0Bh) RDDCOLMOD (0Ch) RDDIM (0Dh) RDDSM (0Eh) RDDSDR (0Fh) RAMRD (2Eh), Note RAMRDC (3Eh), Note RDDISBV (52h) RDCTRLD (54h) RDCABC (56h) RDFSVM (5Ah) RDFSVL (5Bh) RDMFFSVM (5Ch) RDMFFSVL (5Dh) RDCABCMB (5Fh) RDLSCCM (66h) RDLSCCL (67h) RDBWLB (70h) RDBkx (71h) RDBky (72h) RDWx (73h) RDWy (74h) RDRGLB (75h) RDRx (76h) RDRy (77h) RDGx (78h) RDGy (79h) RDBALB (7Ah) RDBx (7Bh) RDBy (7Ch) RDAx (7Dh) RDAy (7Eh) RDDDBST (A1h) RDDDBC (A8h) RDFCS (AAh) RDCCS (AFh) RDID1 (DAh) RDID2 (DBh) RDID3 (DCh) 10/28/2011 116 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The MCU has to define to the display module, what is the maximum size of the return packet. A command, what is used for this purpose, is “Set Maximum Return Packet Size” (SMRPS-S), which Data Type (DT) is 11 0111b and which is using Short Packet (SPa) before the MCU can send “Display Command Set (DCS) Read, No Parameter” to the display module. This same sequence is illustrated for reference purposes below. 10/28/2011 117 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Step 1: • The MCU sends “Set Maximum Return Packet Size” (Short Packet (SPa)) (SMRPS-S) to the display module when it wants to return one byte from the display module • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 11 0111b • Maximum Return Packet Size (MRPS) • Data 0: 01hex • Data 1: 00hex • Error Correction Code (ECC) Packet Header (PH) Maximum Return Packet Size(MRPS) DI MRPS(Least Significant Byte) MRPS(Most Significant Byte) ECC 37hex 01hex 00hex 1Dhex 11101100100000000000000010111000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Set Maximum Return Packet Size (SMRPS-S) - Example Step 2: • The MCU wants to receive a value of the “Read ID1 (DAh)” from the display module when the MCU sends “Display Command Set (DCS) Read, No Parameter” to the display module • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 00 0110b • Packet Data (PD) • Data 0: “Read ID1 (DAh)”, Display Command Set (DCS) • Data 1: Always 00hex • Error Correction Code (ECC) Packet Header (PH) Packet Data (PD) DI Data 0 (DCS) Data 1 (Always 00hex) ECC 06hex DAhex 00hex 1Fhex 01100000010110110000000011111000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Display Command Set (DCS) Read, No Parameter (DCSRN-S) - Example Step 3: The display module can send 2 different information to the MCU after Bus Turnaround (BTA) 1. An acknowledge with Error Report (AwER), which is using a Short Packet (SPa), if there is an error to receive a command. See section “Acknowledge with Error Report (AwER)”. 2. Information of the received command. Short Packet (SPa) or Long Packet (LPa) 10/28/2011 118 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Null Packet, No Data (NP-L) , Data Type = 00 1001 (09h) “Null Packet, No Data” (NP-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 001001b), from the MCU to the display module. The purpose of this command is keeping data lanes in the high speed mode (HSDT), if it is needed. The display module is ignored Packet Data (PD) what the MCU is sending. Long Packet (LPa), when 5 random data bytes of the Packet Data (PD) were sent, is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 00 1001b • Word Count (WC) • Word Count (WC): 0005h • Error Correction Code (ECC) • Packet Data (PD): • Data 0: 89h (Random data) • Data 1: 23h (Random data) • Data 2: 12h (Random data) • Data 3: A2h (Random data) • Data 4: E2h (Random data) • Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 09hex 05hex 00hex 30hex 10010000101000000000000000001100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (DCS) Data 1 (1st Parameter) Data 2 (2nd Parameter) Data 3 (3rd Parameter) 89hex 23hex 12hex A2hex 10010001110001000100100001000101 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 4 (4th Parameter) CRC(Least Significant Byte) CRC (Most Significant Byte) E2hex 59hex 29hex 010001111001101010010100 BBBBBBBBBBBBBBBBBBBBBBBB 012345670123456701234567 L ML ML M S SS SS S B BB BB B Time Null Packet, No Data (NP-L) - Example 10/28/2011 119 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 End of Transmission Packet (EoTP), Data Type = 00 1000 (08h) “End of Transmission Packet” (EoTP) is always using a Short Packet (SPa), what is defined on Data Type (DT, 001000b), from the MCU to the display module. The purpose of this command is terminated the high speed mode (HPDT) properly when there is added this extra packet after the last payload packet before “End of Transmission” (EoT), which is an interface level functionality. The MCU can decide if it want to use the “End of Transmission Packet” (EoTP) or not. The NT35510 has the capability to support both: i.e. If MCU applies the EoTP, it shall report the “DSI Protocol Violation” error when the EoTP is not detected in the high speed (HS). This error reporting can be enable/disable by bit DIS_EoTP_HS of command B100h (page 0). The display module is or isn’t receiving “End of Transmission Packet” (EoTP) from the MCU during the Low Power Data Transmission (LPDT) mode before “Marked-1” (=leaving Escape mode) what ends the Low Power Data Transmission (LPDT) mode. The display module is not allowed to send “End of Transmission Packet” (EoTP) to MCU during the Low Power Data Transmission (LPDT) mode. The summary of the receiving and transmitting EoTP is listed below. Direction MCU => Display Driver Display Driver => MCU Receiving and Transmitting EoTP during LPDT Display Module (DM) in Display Module (DM) in High Speed Data Transmission (HPDT) Low Power Data Transmission (LPDT) With or Without EoTP is Supported With or Without EoTP is Supported HS Mode is not available EoTP can not be sent by (EoTP is not available) the Display Driver 10/28/2011 120 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY Short Packet (SPa) is using a fixed format as follow • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 00 1000b • Packet Data (PD): • Data 0: 0Fh • Data 1: 0Fh • Error Correction Code (ECC) • ECC: 01h Packet Header( PH) Packet Data NT35510 DI Data 0 Data 1 ECC 08hex 0Fhex 0Fhex 01hex 00010000111100001111000010000000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time End of Transmission Packet (EoTP) Some use case of the “End of Transmission Packet” (EoTP) are illustrated only for reference purpose below. Sent Packets LP-11 LP-11 SoT LPa Spa, EoTP EoT Sent Packets SoT SPa SPa Spa, EoTP EoT LP-11 LP-11 End of Transmission Packet (EoTP) - Examples 10/28/2011 121 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Sync Event (H Start, H End, V Start, V End), Data Type = xx 0001 (x1h) Sync Events are Short packets and, therefore, can time-accurately represent events like the start and end of sync pulses. As “start” and “end” are separate and distinct events, the length of sync pulses, as well as position relative to active pixel data, e.g. front and back porch display timing, may be accurately conveyed to the peripheral. The Sync Events are defined as follows: • Data Type = 00 0001 (01h) V Sync Start • Data Type = 01 0001 (11h) V Sync End • Data Type = 10 0001 (21h) H Sync Start • Data Type = 11 0001 (31h) H Sync End In order to represent timing information as accurately as possible a V Sync Start event represents the start of the VSA and also implies an H Sync Start event for the first line of the VSA. Similarly, a V Sync End event implies an H Sync Start event for the last line of the VSA.. Sync events should occur in pairs, Sync Start and Sync End, if accurate 1054 pulse-length information needs to be conveyed. Alternatively, if only a single point (event) in time is required, a single sync event (normally, Sync Start) may be transmitted to the peripheral. Sync events may be concatenated with blanking packets to convey inter-line timing accurately and avoid the overhead of switching between LPS and HS for every event. Note there is a power penalty for keeping the data line in HS mode, however. Display modules that do not need traditional sync/blanking/pixel timing should transmit pixel data in a high-speed burst then put the bus in Low Power Mode, for reduced power consumption. The recommended burst size is a scan line of pixels, which may be temporarily stored in a line buffer on the display module. Color Mode On Command, and, Data Type = 01 0010 (12h) Color Mode On is a Short packet command that switches a Video Mode display module to 8-colors mode for power saving. Color Mode Off Command, Data Type = 00 0010 (02h) Color Mode Off is a Short packet command that returns a Video Mode display module from 8-colors mode to normal display operation. Shutdown Peripheral Command, Data Type = 10 0010 (22h) Shutdown Peripheral command is a Short packet command that turns off the display in a Video Mode display module for power saving. Note the interface shall remain powered in order to receive the turn-on, or wake-up, command. Turn On Peripheral Command, Data Type = 11 0010 (32h) Turn On Peripheral command is Short packet command that turns on the display in a Video Mode display module for normal display operation. Blanking Packet (Long), Data Type = 01 1001 (19h) A Blanking packet is used to convey blanking timing information in a Long packet. Normally, the packet represents a period between active scan lines of a Video Mode display, where traditional display timing is provided from the host processor to the display module. The blanking period may have Sync Event packets interspersed between blanking segments. Like all packets, the Blanking packet contents shall be an integer number of bytes. Blanking packets may contain arbitrary data as payload. The Blanking packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes, and a two-byte checksum. 10/28/2011 122 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY Packed Pixel Stream, 16-bit Format, Long packet, Data Type = 00 1110 (0Eh) 1 byte 1 byte LSB MSB LSB MSB 0 4 5 70 2 3 7 R R G GG G B B 0 4 0 23 5 0 4 5 bits 6 bits 5 bits Pixel 1 NT35510 1 byte 2 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 byte Data Type (0Eh) Virtual Channel Word Count ECC 5 bits 6 bits 5 bits Pixel 1 5 bits 6 bits 5 bits Pixel n Checksum Data ID Packet Header Variable Size Payload Time 16-bit per Pixel – RGB Color Format, Long packet Packet Footer Packed Pixel Stream 16-Bit Format is a Long packet used to transmit image data formatted as 16-bit pixels to a Video Mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte checksum. Pixel format is five bits red, six bits green, five bits blue, in that order. Note that the “Green” component is split across two bytes. Within a color component, the LSB is sent first, the MSB last. With this format, pixel boundaries align with byte boundaries every two bytes. The total line width (displayed plus non-displayed pixels) should be a multiple of two bytes. Normally, the display module has no frame buffer of its own, so all image data shall be supplied by the host processor at a sufficiently high rate to avoid flicker or other visible artifacts. 10/28/2011 123 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY Packed Pixel Stream, 18-bit Format, Long packet, Data type = 01 1110 (1Eh) 1 byte LSB 0 5 R R 0 5 6 bits 1 byte MSB LSB 67 0 GG G 34 GB MSB 7 01 B BB 0 1 2 5 0 3 45 6 bits 6 bits Pixel 1 NT35510 1 byte 2 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte Data Type (1Eh) Virtual Channel Word Count ECC 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits Pixel 1 Pixel 2 Pixel 3 Pixel 4 Data ID Packet Header 1 byte 1 byte 1 byte Variable Size Payload (First Four Pixels Packed in Nine Bytes) Time 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 byte 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits Pixel n-3 Pixel n-2 Pixel n-1 Pixel n Checksum Variable Size Payload (Last Four Pixels Packed in Nine Bytes) Time 18-bit per Pixel (Packed)– RGB Color Format, Long packet Packet Footer Packed Pixel Stream 18-Bit Format (Packed) is a Long packet. It is used to transmit RGB image data formatted as pixels to a Video Mode display module that displays 18-bit pixels The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. Pixel format is red (6 bits), green (6 bits) and blue (6 bits), in that order. Within a color component, the LSB is sent first, the MSB last. Note that pixel boundaries only align with byte boundaries every four pixels (nine bytes). Preferably, display modules employing this format have a horizontal extent (width in pixels) evenly divisible by four, so no partial bytes remain at the end of the display line data. If the active (displayed) horizontal width is not a multiple of four pixels, the transmitter shall send additional fill pixels at the end of the display line to make the transmitted width a multiple of four pixels. The receiving peripheral shall not display the fill pixels when refreshing the display device. For example, if a display device has an active display width of 399 pixels, the transmitter should send 400 pixels in one or more packets. The receiver should display the first 399 pixels and discard the last pixel of the transmission. With this format, the total line width (displayed plus non-displayed pixels) should be a multiple of four pixels (nine bytes). 10/28/2011 124 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY Pixel Stream, 18-bit Format in Three Bytes, Long packet, Data Type = 101110 (2Eh) 1 byte 1 byte 1 byte LSB MSB LSB MSB LSB MSB 01 2 7 01 2 7 01 2 7 R RG GB B 0 50 50 5 6 bits 6 bits 6 bits Pixel 1 NT35510 1 byte 2 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte Data Type (2Eh) Virtual Channel Word Count ECC 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits Pixel 1 Pixel 2 Pixel 3 Data ID Packet Header Variable Size Payload (First Three Pixels in Nine Bytes) Time 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 byte 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits Pixel n-2 Pixel n-1 Pixel n Checksum Variable Size Payload (Last Three Pixels in Nine Bytes) Packet Footer Time 18-bit per Pixel (Loosely Packed)– RGB Color Format, Long packet In the 18-bit Pixel Loosely Packed format, each R, G, or B color component is six bits but is shifted to the upper bits of the byte, such that the valid pixel bits occupy bits [7:2] of each byte. Bits [1:0] of each payload byte representing active pixels are ignored. As a result, each pixel requires three bytes as it is transmitted across the Link. This requires more bandwidth than the “packed” format, but requires less shifting and multiplexing logic in the packing and unpacking functions on each end of the Link. This format is used to transmit RGB image data formatted as pixels to a Video Mode display module that displays 18-bit pixels. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. The pixel format is red (6 bits), green (6 bits) and blue (6 bits) in that order. Within a color component, the LSB is sent first, the MSB last. With this format, pixel boundaries align with byte boundaries every three bytes. The total line width (displayed plus non-displayed pixels) should be a multiple of three bytes. 10/28/2011 125 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY Packed Pixel Stream, 24-bit Format, Long packet, Data Type = 11 1110 (3Eh) 1 byte 1 byte 1 byte LSB MSB LSB MSB LSB MSB 0 70 70 7 R RG GB B 0 70 70 7 8 bits 8 bits 8 bits Pixel 1 NT35510 1 byte 2 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte Data Type (3Eh) Virtual Channel Word Count ECC 8 bits 8 bits 8 bits Pixel 1 8 bits 8 bits 8 bits Pixel 2 8 bits 8 bits 8 bits Pixel 3 Data ID Packet Header 1 byte 1 byte 1 byte Variable Size Payload (First Three Pixels in Nine Bytes) Time 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 byte 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits Pixel n-2 Pixel n-1 Pixel n Checksum Variable Size Payload (Last Three Pixels in Nine Bytes) Time 24-bit per Pixel – RGB Color Format, Long packet Packet Footer Packed Pixel Stream 24-Bit Format is a Long packet. It is used to transmit image data formatted as 24-bit pixels to a Video Mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. The pixel format is red (8 bits), green (8 bits) and blue (8 bits), in that order. Each color component occupies one byte in the pixel stream; no components are split across byte boundaries. Within a color component, the LSB is sent first, the MSB last. With this format, pixel boundaries align with byte boundaries every three bytes. The total line width (displayed plus non-displayed pixels) should be a multiple of three bytes. 10/28/2011 126 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.3.2.2 PACKET FROM THE DISPLAY MODULE TO THE MCU Used Packet Types The display module is always using Short Packet (SPa) or Long Packet (LPa), when it is returning information to the MCU after the MCU has requested information from the Display Module. This information can be a response of the Display Command Set (DCS) (See chapter “5.3.2.3.2.1 Display Command Set (DCS) Read, No Parameter” (DCSRN-S)) or an Acknowledge with Error Report (See chapter: “5.3.2.3.2.2 Acknowledge with Error Report (AwER)” (AwER)). The used packet type is defined on Data Type (DT). See chapter “5.3.2.3.1.3 Data Type (DT)”. A number of the return bytes are more than the maximum size of the Packet Data (PD) on Long Packet (LPa) or Short Packet (SPa) when the display module is sending return bytes in several packets until all return bytes have been sent from the display module to the MCU. It is not possible that the display module is sending return bytes in several packets even if the maximum size of the Packet Data (PD) could be sent on a packet. Both cases are illustrated for reference purposes below. Return Bytes LP-11 LPa Return Bytes LP-11 LP-11 SPa LP-11 Return Bytes on Single Packet Return Bytes LP-11 LPa SP Return Bytes LP-11 LP-11 SPa SPa SPa LP-11 Return Bytes on Several Packets – Not Possible Data Type Hex 02h 1Ch 21h 22h 1Ah 11h 12h Data Type Binary 00 0010 01 1100 10 0001 10 0010 01 1010 01 0001 01 0010 Data Types for Display Module-sourced Packets Symbol Description AwER DCSRR-L DCSRR1-S DCSRR2-S GENRR-L GENRR1-S GENRR2-S Acknowledge & Error Report DCS Long Read Response DCS Short Read Response, 1 Byte returned DCS Short Read Response, 2 Byte returned Generic Long Read Response Generic Short Read Response, 1 Byte returned Generic Short Read Response, 2 Byte returned Packet Size Short Long Short Short Long Short Short 10/28/2011 127 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The display module is return 2 packets (1st packet: Data, 2nd packet Acknowledge with Error Report ) to the MCU when the display module has received a read command. See section “Display Command Set (DCS) Read, No Parameter (DCSRN-S)” where has been detected and corrected a single bit error by the EEC (See bit 8 on Table” Acknowledge with Error Report (AwER) for Short Packet (SPa) Response”). This return packets are illustrated for reference purpose below. Return Bytes LP-11 1st SPa, Data 2nd SPa, AwER LP-11 AwER = Acknowledge with Error Report Exception when Return Bytes on Several Packet 10/28/2011 128 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Acknowledge with Error Report (AwER), Data Type = 00 0010(02h) “Acknowledge with Error Report” (AwER) is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 0010b), from the display module to the MCU. The Packet Data (PD) can include bits, which are defining the current error, when a corresponding bit is set to ‘1’, as they are defined on the following table. Acknowledge with Error Report (AwER) for Long Packet (LPa) Response Bit Description 0 SoT Error 1 SoT Sync Error 2 EoT Sync Error 3 Escape Mode Entry Command Error 4 Low-Power Transmit Sync Error 5 Any Protocol Timer Time-Out 6 False Control Error 7 Contention is Detected on the Display Module 8 ECC Error, single-bit (detected and corrected) 9 ECC Error, multi-bit (detected, not corrected) 10 Checksum Error (Long packet only) 11 DSI Data Type (DT) Not Recognized 12 DSI Virtual Channel (VC) ID Invalid 13 Invalid Transmission Length 14 Reserved, Set to ‘0’ internally 15 DSI Protocol Violation Acknowledge with Error Report (AwER) for Short Packet (SPa) Response Bit Description 0 SoT Error 1 SoT Sync Error 2 EoT Sync Error 3 Escape Mode Entry Command Error 4 Low-Power Transmit Sync Error 5 Any Protocol Timer Time-Out 6 False Control Error 7 Contention is Detected on the Display Module 8 ECC Error, single-bit (detected and corrected) 9 ECC Error, multi-bit (detected, not corrected) 10 Set to “0” internally (Only for Long Packet (LP)) 11 DSI Data Type (DT) Not Recognized 12 DSI Virtual Channel (VC) ID Invalid 13 Invalid Transmission Length 14 Reserved, Set to ‘0’ internally 15 DSI Protocol Violation These errors are only included on the last packet, which has been received from the MCU to the display module before Bus Turnaround (BTA). The display module ignores the received packet which includes error or errors. 10/28/2011 129 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY Acknowledge with Error Report (AwER) of the Short Packet (SPa) is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 00 0010b • Packet Data (PD): • Bit 8: ECC Error, single-bit (detected and corrected) • AwER: 0100h • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Packet Header( PH) Packet Data NT35510 DI 02hex AwER (Least Significant Byte) AwER (Most Significant Byte) 00hex 01hex ECC 3Ahex 01000000000000001000000001011100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Acknowledge with Error Report (AwER) – Example It is possible that the display module has received several packets, which have included errors, from the MCU before the MCU is doing Bus Turnaround (BTA). Some examples are illustrated for reference purposes below. Packets from the MCU LP-11 LPa SP LP-11 Includes an error Packets from the MCU LP-11 SPa SPa SPa LP-11 Errors Packets Includes an error 10/28/2011 130 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Therefore, there is needed a method to check if there has been errors on the previous packets. These errors of the previous packets can check “Read Display Signal Mode (0Eh)” and “Read Number of the Errors on DSI (05h)” commands. The bit D0 of the “Read Display Signal Mode (0Eh)” command has been set to ‘1’ if a received packet includes an error. The number of the packets, which are including an ECC or CRC error, are calculated on the RDNUMED register, which can read “Read Number of the Errors on DSI (05h)” command. This command also sets the RDNUMED register to 00h as well as set the bit D0 of the “Read Display Signal Mode (0Eh)” command to ‘0’ after the MCU has read the RDNUMED register from the display module. The functionality of the RDNUMED register is illustrated for reference purposes below. Start Received Information Note 1 No Is there an error? Note 2 Set RDDSM's D0 bit to "1" Set RDNUMED's P[6:0] = "7Fh"? Increment RDNUMED's P[6:0] by 1 Yes RDNUMED's P[7:0] = "80h" Notes: 1. This information can Interface or Packet Level Communication but it is always from the MCU to the display module in this case. 2. CRC or ECC error. 10/28/2011 131 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DCS Read Long Response (DCSRR-L), Data Type = 01 1100(1Ch) “DCS Read Long Response” (DCSRR-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 01 1100b), from the display module to the MCU. “DCS Read Long Response” (DCSRR-L) is used when the display module wants to response a DCS Read command, which the MCU has sent to the display module. “DCS Read Long Response” (DCSRR-L) is used when the display module wants to response a DCS Read command, which the MCU has sent to the display module. Long Packet (LPa), which includes 5 data bytes of the Packet Data (PD), is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 01 1100b • Word Count (WC) • Word Count (WC): 0005h • Error Correction Code (ECC) • Packet Data (PD): • Data 0: 89h • Data 1: 23h • Data 2: 12h • Data 3: A2h • Data 4: E2h • Packet Footer (PF) This is defined on the Long Packet (LP) as follows. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 1Chex 05hex 00hex 29hex 00111000101000000000000010010100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (DCS) Data 1 (1st Parameter) Data 2 (2nd Parameter) Data 3 (3rd Parameter) 89hex 23hex 12hex A2hex 10010001110001000100100001000101 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 4 (4th Parameter) CRC(Least Significant Byte) CRC (Most Significant Byte) E2hex 59hex 29hex 010001111001101010010100 BBBBBBBBBBBBBBBBBBBBBBBB 012345670123456701234567 L ML ML M S SS SS S B BB BB B Time DCS Read Long Response (DCSRR-L) - Example 10/28/2011 132 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DCS Read Short Response, 1 Byte Returned (DCSRR1-S), Data Type = 10 0001(21h) “DCS Read Short Response, 1 Byte Returned” (DCSRR1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 10 0001b), from the display module to the MCU. “DCS Read Short Response, 1 Byte Returned” (DCSRR1-S) is used when the display module wants to response a DCS Read command, which the MCU has sent to the display module. Short Packet (SPa) is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 10 0001b • Packet Data (PD): • Data 0: 45h • Data 1: 00h (Always) • Error Correction Code (ECC) This is defined on the Short Packet (SP) as follows. Packet Header (PH) Packet Data (PD) DI Data 0 Data 1 ECC 21hex 45hex 00hex (Always) 01hex 10000100101000100000000010000000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time DCS Read Short Response, 1 Byte Returned (DCSRR1-S) - Example 10/28/2011 133 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DCS Read Short Response, 2 Bytes Returned (DCSRR2-S), Data Type = 10 0010(22h) “DCS Read Short Response, 2 Bytes Returned” (DCSRR2-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 10 0010b), from the display module to the MCU. “DCS Read Short Response, 2 Bytes Returned” (DCSRR2-S) is used when the display module wants to response a DCS Read command, which the MCU has sent to the display module. Short Packet (SPa) is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 10 0010b • Packet Data (PD): • Data 0: 45h • Data 1: 32h • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Packet Header (PH) Packet Data (PD) DI Data 0 Data 1 ECC 22hex 45hex 32hex 0Fhex 01000100101000100100110011110000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time DCS Read Short Response, 2 Bytes Returned (DCSRR2-S) - Example 10/28/2011 134 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Generic Read Long Response (GENRR-L), Data Type = 01 1010(1Ah) “Generic Read Long Response” (GENRR-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 01 1010b), from the display module to the MCU. “Generic Read Long Response” (GENRR-L) is used when the display module wants to response a Generic Read command, which the MCU has sent to the display module. Long Packet (LPa), which includes 5 data bytes of the Packet Data (PD), is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 01 1010b • Word Count (WC) • Word Count (WC): 0005h • Error Correction Code (ECC) • Packet Data (PD): • Data 0: 89h • Data 1: 23h • Data 2: 12h • Data 3: A2h • Data 4: E2h • Packet Footer (PF) This is defined on the Long Packet (LP) as follows. Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 1Ahex 05hex 00hex 2Fhex 01011000101000000000000011110100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 Data 1 (1st Parameter) Data 2 (2nd Parameter) Data 3 (3rd Parameter) 89hex 23hex 12hex A2hex 10010001110001000100100001000101 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 4 (4th Parameter) CRC(Least Significant Byte) CRC (Most Significant Byte) E2hex 59hex 29hex 010001111001101010010100 BBBBBBBBBBBBBBBBBBBBBBBB 012345670123456701234567 L ML ML M S SS SS S B BB BB B Time Generic Read Long Response (GENRR-L) - Example 10/28/2011 135 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Generic Read Short Response, 1 Byte Returned (GENRR1-S), Data Type = 01 0001(11h) “Generic Read Short Response, 1 Byte Returned” (GENRR1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0001b), from the display module to the MCU. “Generic Read Short Response, 1 Byte Returned” (GENRR1-S) is used when the display module wants to response a Generic Read command, which the MCU has sent to the display module. Short Packet (SPa) is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 01 0001b • Packet Data (PD): • Data 0: 45h • Data 1: 00h (Always) • Error Correction Code (ECC) This is defined on the Short Packet (SP) as follows. Packet Header (PH) Packet Data (PD) DI 11hex Data 0 45hex Data 1 00hex (Always) ECC 07hex 10001000101000100000000011100000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Generic Read Short Response, 1 Byte Returned (GENRR1-S) - Example 10/28/2011 136 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Generic Read Short Response, 2 Bytes Returned (GENRR2-S), Data Type = 01 0010(12h) “Generic Read Short Response, 2 Bytes Returned” (GENRR2-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0010b), from the display module to the MCU. “Generic Read Short Response, 2 Bytes Returned” (GENRR2-S) is used when the display module wants to response a Generic Read command, which the MCU has sent to the display module. Short Packet (SPa) is defined e.g. • Data Identification (DI) • Virtual Channel (VC, DI[7…6]): 00b • Data Type (DT, DI[5…0]): 01 0010b • Packet Data (PD): • Data 0: 45h • Data 1: 32h • Error Correction Code (ECC) This is defined on the Short Packet (SP) as follows. Packet Header (PH) Packet Data (PD) DI 12hex Data 0 45hex Data 1 32hex ECC 09hex 01001000101000100100110010010000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Generic Read Short Response, 2 Bytes Returned (GENRR2-S) - Example 10/28/2011 137 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.3.3 COMMUNICATION SEQUENCES 5.3.2.3.3.1 GENERAL The communication sequences can be done on interface or packet levels between the MCU and the display module. See chapters “Interface Level Communication” and “Packet Level Communication”. This communication sequence description is for DSI data lanes and it has been assumed that the needed low level communication is done on DSI clock lanes (DSI-CLK+/-) automatically. Functions of the interface level communication is described on the following table. Interface Level Communication Interface Mode Low Power Abbreviation LP-11 LPDT ULPS RAR TEE Interface Action Description Stop state Low power data transmission Ultra-Low power state Remote application reset Tearing effect event High Speed ACK BTA HSDT Acknowledge (No error) Bus turnaround High speed data transmission Functions of the packet level communication are described on the following table. Packet Sender MCU Display Module Packet Level Communication Abbreviation Packet Size Packet Description DCSW1-S SPa DCS Write, 1 Parameter DCSWN-S SPa DCS Write, No Parameter DCSW-L LPa DCS Write, Long DCSRN-S SPa DCS Read, No Parameter SMRPS-S SPa Set maximum return packet size NP-L LPa Null packet, No data AwER SPa Acknowledge with error report DCSRR-L LPa DCS Read, Long Response DCSRR1-S SPa DCS Read, Short Response DCSRR2-S SPa DCS Read, Short Response 10/28/2011 138 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.3.3.2 SEQUENCES DCS Write, 1 Parameter Sequence A Short Packet (SPa) of “Display Command Set (DCS) Write, 1 Parameter (DCSW1-S)” is defined on chapter “Display Command Set (DCS) Write, 1 Parameter (DCSW1-S)” and example sequences, how this packet is used, is described on following tables. DCS Write, 1 Parameter Sequence - Example 1 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - 2 DCSW1-S LPDT => - - 3 - LP-11 => - - Start End DCS Write, 1 Parameter Sequence - Example 2 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSW1-S HSDT => - - 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - End DCS Write, 1 Parameter Sequence - Example 3 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSW1-S HSDT => - - 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - Interface control change from 5 - BTA <=> BTA - the MCU to the display module 6 - - <= LP-11 - If no error => goto line 8 If error => goto line 13 7 8 - - <= ACK - No error 9 - - <= LP-11 - Interface control change from 10 - BTA <=> BTA - the display module to the MCU 11 - LP-11 => - - End 12 13 - - <= LPDT AwER Error report 14 - - <= LP-11 - 15 - BTA <=> BTA - 16 - LP-11 => - - End 10/28/2011 139 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DCS Write, No Parameter Sequence A Short Packet (SPa) of “Display Command Set (DCS) Write, No Parameter (DCSWN-S)” is defined on chapter “Display Command Set (DCS) Write, No Parameter (DCSWN-S)” and example sequences, how this packet is used, is described on following tables. DCS Write, No Parameter Sequence - Example 1 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - 2 DCSWN-S LPDT => - - 3 - LP-11 => - - Start End DCS Write, No Parameter Sequence - Example 2 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSWN-S HSDT => - - 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - End DCS Write, No Parameter Sequence - Example 3 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSWN-S HSDT => - - 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - Interface control change from 5 - BTA <=> BTA - the MCU to the display module 6 - - <= LP-11 - If no error => goto line 8 If error => goto line 13 7 8 - - <= ACK - No error 9 - - <= LP-11 - Interface control change from 10 - BTA <=> BTA - the display module to the MCU 11 - LP-11 => - - End 12 13 - - <= LPDT AwER Error report 14 - - <= LP-11 - 15 - BTA <=> BTA - 16 - LP-11 => - - End 10/28/2011 140 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DCS Write Long Sequence A Long Packet (LPa) of “Display Command Set (DCS) Write Long (DCSW-L)” is defined on chapter “Display Command Set (DCS) Write Long (DCSW-L)” and example sequences, how this packet is used, is described on following tables. DCS Write, Long Sequence - Example 1 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - 2 DCSW-L LPDT => - - 3 - LP-11 => - - Start End DCS Write, Long Sequence - Example 2 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSW-L HSDT => - - 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - End DCS Write, Long Sequence - Example 3 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSW-L HSDT => - - 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - 5 - BTA <=> BTA - Interface control change from the MCU to the display module 6 - - <= LP-11 - If no error => goto line 8 If error => goto line 13 7 8 - - <= ACK - No error 9 - - <= LP-11 - 10 - BTA <=> BTA - Interface control change from the display module to the MCU 11 - LP-11 => - - End 12 13 - - <= LPDT AwER Error report 14 - - <= LP-11 - 15 - BTA <=> BTA - 16 - LP-11 => - - End 10/28/2011 141 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DCS Write, Long Sequence - Example 4 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSW-L HSDT => - - Memory Write (2Ch) 3 DCSW-L HSDT => - - Memory Write Continue(3Ch) 4 DCSW-L HSDT => - - Memory Write Continue(3Ch) 5 DCSW1-S HSDT => - - Memory Write Continue(3Ch) with 1 parameter 6 EoTP HSDT => - - End of Transmission Packet 7 - LP-11 => - - End 10/28/2011 142 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DCS Read, No Parameter Sequence A Short Packet (SPa) of “Display Command Set (DCS) Read, No Parameter (DCSRN-S)” is defined on chapter “Display Command Set (DCS) Read, No Parameter (DCSRN-S)” and example sequences, how this packet is used, is described on following tables. DCS Read, No Parameter Sequence - Example 1 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 SMRPS-S HSDT => - - Define how many data byte is wanted to read: 1 byte 3 DCSRN-S HSDT => - - wanted to get a response ID1 (DAh) 4 EoTP HSDT => - - End of Transmission Packet 5 - LP-11 => - - 6 - BTA <=> BTA - Interface control change from the MCU to the display module If no error => goto line 9 7 - - <= LP-11 - If error => goto line 14 If error is corrected by ECC => go to line 19 8 9 - - <= LPDT DCSRR1-S Responsed 1 byte return 10 - - <= LP-11 - 11 - BTA <=> BTA - Interface control change from the display module to the MCU 12 - LP-11 => - - End 13 14 - - <= LPDT AwER Error report 15 - - <= LP-11 - 16 - BTA <=> BTA - Interface control change from the display module to the MCU 17 - LP-11 => - - End 18 19 - - <= LPDT DCSRR1-S Responsed 1 byte return 20 - - <= LPDT AwER Error Report (Error is Corrected by ECC) 21 - - <= LP-11 - 22 - BTA <=> BTA - Interface control change from the display module to the MCU 23 - LP-11 => - - End 10/28/2011 143 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DCS Read, No Parameter Sequence - Example 2 MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 SMRPS-S HSDT => - - Define how many data byte is wanted to read : 200 byte 3 DCSRN-S HSDT => - - wanted to get a response "Memory Read" (2Eh) 4 EoTP HSDT => - - End of Transmission Packet 5 - LP-11 => - - 6 - BTA <=> BTA - Interface control change from the MCU to the display module If no error => goto line 8 7 - - <= LP-11 - If error => goto line 13 If error is corrected by ECC => go to line 19 8 9 - - <= LPDT DCSRR-L Responsed 200 bytes return 10 - - <= LP-11 - 11 - BTA <=> BTA - Interface control change from the display module to the MCU 12 - LP-11 => - - End 13 14 - - <= LPDT AwER Error report 15 - - <= LP-11 - 16 - BTA <=> BTA - Interface control change from the display module t to he MCU 17 - LP-11 => - - End 18 19 - - <= LPDT DCSRR-L Responsed 200 bytes return 20 - - <= LPDT AwER Error Report (Error is Corrected by ECC) 21 - - <= LP-11 - 22 - BTA <=> BTA - Interface control change from the display module to the MCU 23 - LP-11 => - - End 10/28/2011 144 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Null Packet, No Data Sequence A Long Packet (LPa) of “Null Packet, No Data (NP-L)” is defined on chapter “Null Packet, No Data (NP-L)” and example sequences, how this packet is used, is described on following tables. Null Packet, No Parameter Sequence - Example MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 NP-L HSDT => - - Only high speed data transmission is used. 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - End End of Transmission Packet A Short Packet (SPa) of “End of Transmission (EoT)” is defined on chapter “End of Transmission Packet (EoT)” and an example sequences, how this packet is used, is described on following tables. End of Transmission Packet - Example MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 NP-L HSDT => - - Only high speed data transmission is used. 2 EoTP HSDT => - - End of Transmission Packet 3 - LP-11 => - - End 10/28/2011 145 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.4 VIDEO MODE COMMUNICATION Video Mode peripherals require pixel data delivered in real time. This section specifies the format and timing of DSI traffic for this type of display module. 5.3.2.4.1 TRANSMISSION PACKET SEQUENCES DSI supports several formats, or packet sequences, for Video Mode data transmission. The peripheral’s timing requirements dictate which format is appropriate. In the following sections, Burst Mode refers to time-compression of the RGB pixel (active video) portion of the transmission. In addition, these terms are used throughout the following sections: • Non-Burst Mode with Sync Pulses – enables the peripheral to accurately reconstruct original video timing, including sync pulse widths. • Non-Burst Mode with Sync Events – similar to above, but accurate reconstruction of sync pulse widths is not required, so a single Sync Event is substituted. • Burst mode – RGB pixel packets are time-compressed, leaving more time during a scan line for LP mode (saving power) or for multiplexing other transmissions onto the DSI link. In the following figures the Blanking or Low-Power Interval (BLLP) is defined as a period during which video packets such as pixel-stream and sync event packets are not actively transmitted to the peripheral. To enable PHY synchronization the host processor should periodically end HS transmission and drive the Data Lanes to the LP state. This transition should take place at least once per frame; shown as LPM in the figures in this section. It is recommended to return to LP state once per scan-line during the horizontal blanking time. Regardless of the frequency of BLLP periods, the host processor is responsible for meeting all documented peripheral timing requirements. Note, at lower frequencies BLLP periods will approach, or become, zero, and burst mode will be indistinguishable from non-burst mode. During the BLLP the DSI Link may do any of the following: • Remain in Idle Mode with the host processor in LP-11 state and the peripheral in LP-RX • Transmit one or more non-video packets from the host processor to the peripheral using Escape Mode • Transmit one or more non-video packets from the host processor to the peripheral using HS Mode • If the previous processor-to-peripheral transmission ended with BTA, transmit one or more packets from the peripheral to the host processor using Escape Mode • Transmit one or more packets from the host processor to a different peripheral using a different Virtual Channel ID The sequence of packets within the BLLP or RGB portion of a HS transmission is arbitrary. The host processor may compose any sequence of packets, including iterations, within the limits of the packet format definitions. For all timing cases, the first line of a frame shall start with VS; all other lines shall start with HS. This is also true in the special case when VSA+VBP=0. Note that the position of synchronization packets, such as VS and HS, in time is of utmost importance since this has a direct impact on the visual performance of the display panel. Normally, RGB pixel data is sent with one full scan line of pixels in a single packet. If necessary, a horizontal scan-line of active pixels may be divided into two or more packets. However, individual pixels shall not be split across packets. 10/28/2011 146 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Transmission packet components used in the figures in this section are defined in Figure below unless otherwise specified. V S V E BL LP H S H S A H E H F P H B P R G B L P M Low Power Mode including optional BTA DSI Packet: Arbitrary sequence of pixel stream and Null Packets DSI Blanking Packet: Horizontal Back Porch DSI Blanking Packet: Horizontal Front Porch DSI Sync. Event: Horizontal Sync. End DSI Blanking Packet: Horizontal Sync. Active, No data DSI Sync. Event: Horizontal Start DSI Packet: Arbitrary sequence of non-restricted DSI packets or Low Power Mode including optional BTA. DSI Sync. Event: Packet V Sync. End. DSI Sync. Event: Packet V Sync. Start. DSI Video Mode Interface Timing Legend If a peripheral timing specification for HBP or HFP minimum period is zero, the corresponding Blanking Packet may be omitted. If the HBP or HFP maximum period is zero, the corresponding blanking packet shall be omitted. 10/28/2011 147 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.4.2 NON-BURST MODE WITH SYNC PULSES With this format, the goal is to accurately convey DPI-type timing over the DSI serial Link. This includes matching DPI pixel-transmission rates, and widths of timing events like sync pulses. Accordingly, synchronization periods are defined using packets transmitting both start and end of sync pulses. An example of this mode is shown in Figure below. tL * (VSA+VBP+VACT+VFP) tL tL tL tL tL tL tL tL V BL H BL S LP S LP V BL H BL E LP S LP H BL S LP VSA Lines VBP Lines Active Video Area H BL S LP H S BL LP H S B L L P L P M VFP Lines tL tHSA tHBP tHACT tHFP H S H S A H E H B P RGB HFP H S H S A H E H B P VACT Lines RGB HFP DSI Video Mode Interface Timing: Non-Burst Transmission with Sync Start and End Normally, periods shown as HSA (Horizontal Sync Active), HBP (Horizontal Back Porch) and HFP (Horizontal Front Porch) are filled by Blanking Packets, with lengths (including packet overhead) calculated to match the period specified by the peripheral’s data sheet. Alternatively, if there is sufficient time to transition from HS to LP mode and back again, a timed interval in LP mode may substitute for a Blanking Packet, thus saving power. 10/28/2011 148 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.4.3 NON-BURST MODE This mode is a simplification of the format described in section 5.3.2.4.2 “Non-Burst Mode with Sync Pulse” .Only the start of each synchronization pulse is transmitted. The peripheral may regenerate sync pulses as needed from each Sync Event packet received. Pixels are transmitted at the same rate as they would in a corresponding parallel display interface such as DPI-2. An example of this mode is shown in Figure below. tL * (VSA+VBP+VACT+VFP) tL tL tL tL tL tL tL tL V BL H BL S LP S LP H BL H BL S LP S LP H BL S LP VSA Lines VBP Lines Active Video Area H BL S LP H S BL LP H S B L L P L P M V S VFP Lines tL tHBP tHACT tHFP H S H B P RGB HFP H S H B P VACT Lines RGB HFP DSI Video Mode Interface Timing: Non-burst Transmission As with the previous Non-Burst Mode, if there is sufficient time to transition from HS to LP mode and back again, a timed interval in LP mode may substitute for a Blanking Packet, thus saving power. 10/28/2011 149 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.4.4 BURST MODE In this mode, blocks of pixel data can be transferred in a shorter time using a time-compressed burst format. This is a good strategy to reduce overall DSI power consumption, as well as enabling larger blocks of time for other data transmissions over the Link in either direction. There may be a line buffer or similar memory on the peripheral to accommodate incoming data at high speed. Following HS pixel data transmission, the bus goes to Low Power Mode, during which it may remain idle, i.e. the host processor remains in LP-11 state, or LP transmission may take place in either direction. If the peripheral takes control of the bus for sending data to the host processor, its transmission time shall be limited to ensure data underflow does not occur from its internal buffer memory to the display device. An example of this mode is shown in Figure below. tL * (VSA+VBP+VACT+VFP) tL tL tL tL tL tL tL tL V BL H BL S LP S LP H BL H BL S LP S LP H BL S LP VSA Lines VBP Lines Active Video Area H BL S LP H S BL LP H S B L L P L P M V S VFP Lines tL tHBP tHACT tHFP H S H B P RGB BLLP HFP H S H B P RGB VACT Lines BLLP HFP DSI Video Mode Interface Timing: Burst Transmission Similar to the Non-Burst Mode scenario, if there is sufficient time to transition from HS to LP mode and back again, a timed interval in LP mode may substitute for a Blanking Packet, thus saving power. 10/28/2011 150 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.2.4.5 PARAMETERS Below table documents the parameters used in the preceding figures. Peripheral supplier companies are responsible for specifying suitable values for all blank fields in the table. The host processor shall meet these requirements to ensure interoperability. Required Peripheral Timing Parameters Symbol Parameter BRPHY Bit rate total on all Lanes Condition Min Typ WVGA 80 - tL Line time WVGA - 19 tHBP Horizontal back porch WVGA 0.5 - tHACT Time for image data HACT Active pixels per line 2 data lane 7.68 - WVGA - 480 tHFP Horizontal front porch - 0.5 - VSA Vertical sync active - 1 - VBP Vertical back porch - 4, Note2 - VACT Active lines per frame WVGA - 864 VFP Vertical front porch - 4 - Note1: Frame rate (Typ)=60Hz Note2: VBP (min) value can change by command set. Note3: tHACT+tHFP+ tHBP ≥ tL Max 500 Note3 - Units Mbps us us us pixels us H H H H 10/28/2011 151 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.3 Memory Write/Read Format - 16 bit/pixel Writing The MCU can send to the display module a following packet. Packet Header (PH) DI WC (Least Significant Byte) WC (Most Significant Byte) ECC 39hex (DCSW-L) 03hex 00hex 36hex 10011100110000000000000001101100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Packet Data (PD) Data 0 – DCS (Note 1) Data 1 – Red, Green[0:2] Data 2 - Green[3:5], Blue 2Chex (Memory Write) 23hex 12hex 001101001100010001001000 B B B B B B B BRRRRRGGGGGGB B B B B 012345670123401234501234 L ML ML M S SS SS S B BB BB B Packet Footer (PF) CRC (Least Significant Byte) CRC (Most Significant Byte) 63hex A5hex 1100011010100101 BBBBBBBBBBBBBBBB 0123456701234567 L ML M S SS S B BB B Time Notes: 1. Memory Write (2Ch) or Memory Write Continue (3Ch) 2. It is possible that one pixel information is split in one different packets which are ending and starting as follows: RG – GB (2 packets) 3. Packet can include several pixel (Not only one pixel as in this example) One Pixel Write (DCSW-L) – Example 1 10/28/2011 152 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Packet Header (PH) Packet Data (PD) DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex (DCSW1-S) 3Chex (Memory Write Continue) 01hex - Red, Green[0:2] 21hex 10101000001111001000000010000100 B B B B B B B B B B B B B B B BRRRRRGGGB B B B B B B B 01234567012345670123401201234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Note: DCS (Data 0) can also be "Memory Write (2Ch)" command Red/Green[0:2] Subpixel Write (DCSW1-S) – Example 2 Packet Header (PH) Packet Data (PD) DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex (DCSW1-S) 3Chex (Memory Write Continue) 01hex - Green[3:5], Blue 21hex 10101000001111001000000010000100 B B B B B B B B B B B B B B B BGGGB B B B B B B B B B B B B 01234567012345673450123401234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Notes: 1. DCS (Data 0) can not be "Memory Write (2Ch)" command. It must always be "Memory Write Continue (3Ch)". 2. Previous data byte was R[0:4]G[0:2] Green[3:5]/Blue Subpixel Write (DCSW1-S) – Example 3 10/28/2011 153 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 - 24 bit/pixel Writing The MCU can send to the display module a following packet. Packet Header (PH) DI WC (Least Significant Byte) WC (Most Significant Byte) ECC 39hex (DCSW-L) 04hex 00hex 2Chex 10011100001000000000000000110100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Packet Data (PD) Data 0 – DCS (Note 1) Data 1 – Red Data 2 - Green Data 3 - Blue 2Chex (Memory Write) 23hex 12hex A2hex 00110100110001000100100001000101 B B B B B B B BRRRRRRRRGGGGGGGGB B B B B B B B 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Packet Footer (PF) CRC (Least Significant Byte) CRC (Most Significant Byte) 20hex D7hex 0000010011101011 BBBBBBBBBBBBBBBB 0123456701234567 L ML M S SS S B BB B Time Notes: 1. Memory Write (2Ch) or Memory Write Continue (3Ch) 2. It is possible that one pixel information is split in two or three different packets which are ending and starting as follows: • R - GB (2 packets) • RG - B (2 packets) • R - G - B (3 packets) 3. Packet can include several pixel (Not only one pixel as in this example) One Pixel Write (DCSW-L) - Example 1 10/28/2011 154 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Packet Header (PH) Packet Data (PD) DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex (DCSW1-S) 3Chex (Memory Write Continue) 01hex - Blue 21hex 10101000001111001000000010000100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Notes: 1. DCS (Data 0) can not be "Memory Write (2Ch)" command. It must be always be "Memory Write Continuec(3Ch)" . 2. Previous data byte was G[0:7] Blue Subpixel Write (DCSW1-S) - Example 2 Packet Header (PH) Packet Data (PD) DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex (DCSW1-S) 3Chex (Memory Write Continue) 01hex - Green 21hex 10101000001111001000000010000100 B B B B B B B B B B B B B B B BGGGGGGGGB B B B B B B B 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Notes: 1. DCS (Data 0) can not be "Memory Write (2Ch)" command. It must always be "Memory Write Continue (3Ch)". 2. Previous data byte was R[0:7] Green Subpixel Write (DCSW1-S) - Example 3 Packet Header (PH) Packet Data (PD) DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex (DCSW1-S) 2Chex (Memory Write) 01hex - Red 07hex 10101000001111001000000010000100 B B B B B B B B B B B B B B B B RRRRRRRRB B B B B B B B 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Note: DCS (Data 0) can also be "Memory Write Continue (3Ch)" command. Red subpixel Write (DCSW1-S) - Example 4 10/28/2011 155 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 - 24 bit/pixel Reading The display module can send to the MCU following packets after the MCU has a read command “Memory Read (2Eh)” or “memory Read Continue (3Eh)”. Packet Header (PH) DI WC (Least Significant Byte) WC (Most Significant Byte) ECC 1Chex (DCSRR-L) 03hex 00hex 16hex 00111000110000000000000001101000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Packet Data (PD) Data 0 – Red Data 1 - Green Data 2 - Blue 2Ehex 23hex 12hex 011101001100010001001000 RRRRRRRRGGGGGGGGB B B B B B B B 012345670123456701234567 L ML ML M S SS SS S B BB BB B Packet Footer (PF) CRC (Least Significant Byte) CRC (Most Significant Byte) DBhex 10hex 1101101100001000 BBBBBBBBBBBBBBBB 0123456701234567 L ML M S SS S B BB B Time Note: It is possible that one pixel information is split in two or three different packets: • R - GB (2 packets) • RG - B (2 packets) • R - G - B (3 packets) One Pixel Read Response (DCSRR-L) - Example 1 10/28/2011 156 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Packet Header (PH) Packet Data (PD) DI Data 0 Data 1 ECC 21hex (DCSRR1-S) 01hex - Red 00hex 14hex 10000100100000000000000000101000 B B B B B B B B RRRRRRRR B B B B B B B B B B B B B B B B 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Notes: 1. Data 1 is always "00h". 2. Previous data byte was B[0:7] Red Subpixel Response (DCSRR1-S) - Example 2 Packet Header (PH) Packet Data (PD) DI Data 0 Data 1 ECC 21hex (DCSRR1-S) 01hex - Green 00hex 14hex 10000100100000000000000000101000 B B B B B B BBGGGGGGGGBB B B B B BB BB B B B B B B 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Notes: 1. Data 1 is always "00h". 2. Previous data byte was R[0:7] Green Subpixel Response (DCSRR1-S) - Example 3 Packet Header (PH) Packet Data (PD) DI Data 0 Data 1 ECC 21hex (DCSRR1-S) 01hex - Blue 00h 14hex 10000100100000000000000000101000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Note: Data 1 is always "00h". Blue subpixel Response (DCSRR1-S) - Example 4 10/28/2011 157 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Packet Header (PH) Packet Data (PD) DI Data 0 Data 1 ECC 22hex (DCSRR2-S) 11hex - Red 50hex – Green (Pixel n) 0Ahex 01000100100010000000101001010000 B B B B B B B BRRRRRRRRGGGGGGGGB B B B B B B B 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Red and Green Subpixels Response (DCSRR2-S) - Example 5 Packet Header (PH) Packet Data (PD) DI Data 0 Data 1 ECC 21hex (DCSRR1-S) 01hex - Green 00hex 14hex 10000100100000000000000000101000 B B B B B B B BGGGGGGGGB B B B B B B B B B B B B B B B 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Note: Previous data byte was R[0:7] Green and Blue Subpixels Response (DCSRR2-S) - Example 6 Packet Header (PH) Packet Data (PD) DI Data 0 Data 1 ECC 21hex (DCSRR1-S) 01hex - Blue 00h 14hex 10000100100000000000000000101000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Note: Previous data byte G[0:7] Blue and Red Subpixels Response (DCSRR2-S) - Example 7 10/28/2011 158 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.3.4 System Power-Up and Initialization After power-on, the host processor shall observe an initialization period, tINIT, during which it shall drive a sustained Tx-Stop state (LP-11) on all Lanes of the Link. Figure below illustrates an example power-up sequence for a DSI display module. In the figure, a hardware reset (RESX) mechanism is assumed for initialization. Internally within the display module, de-assertion of RESX could happen after both IO and core voltages were ramped up. In this example, the host’s tINIT_MASTER parameter is programmed for driving LP-11 for a period longer than the sum of tRESW, tINIT_SLAVE and tINTERNAL_DELAY. The display module may ignore all Lane activities during this time. VDDI VPNL RESX tRESW MVDDA MVDDI MVDDL Rx State Machine Active DSI-CLK+ DSI-CLK- tINIT_SLAVE tINTERNAL_DELAY tINIT_MASTER DSI-D0+ DSI-D0- (tINIT_MASTER) >= (tRESW + tINIT_SLAVE + tINTERNAL_DELAY) Symbol Parameter Min Typ tINIT_MASTER MIPI Tx initialize time 5 - tRESW Reset “L” pulse width Note - tINIT_SLAVE MIPI Rx initialize time 4 - tINTERNAL_DELAY Internal delay time. Note: See section “7.6.7 Reset Input Timing” 500 - SYNC BYTE0 BYTE1 SYNC BYTE0 BYTE1 Max Units - mS - μS - mS - μS 10/28/2011 159 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.4 MDDI Interface The NT35510 supports the Mobile Display Digital Interface (MDDI) is a differential small amplitude serial interface for high-speed data transfer through the following lines: DATA0_P/M, DATA1_P/M and STB_P/M. The specifications of MDDI supported by the NT35510 meet the MDDI specifications Version 1.2 as published by the Video Electronics Standards Association (VESA). The NT35510 offers the Bi-direction Link to use for the register and display data read / write. For power saving, the NT35510 offers both Hibernation mode (Send shutdown packet), and enter deep standby mode to reduce power consumption. The NT35510 supports the MDDI Type-I and Type-II of the MDDI specifications Version 1.2 and the application diagram is illustrated as Fig. 5.4.1. Host System Hinge VDD GND [ Main Driver IC ] Display MDDI Host MDDI_STB_P/M MDDI_DATA_P/M RESX TE (Note 1) SDO SDI WRX/SCL Bi-direction Link Interface Pins MDDI Client Source Output Gate Signals IM3, IM[2:0] Fig. 5.4.1 MDDI application diagram Notes: 1. Based on the system configuration, use TE signal as the reference signal for moving picture display to avoid the tearing effect. 2. When enter to the MDDI interface from other interface, the Host needs to wait 100ms and can start to send any packet. For example wake up packet. 3. After shutting down the MDDI interface the Host needs to wait 500ns and can start to send wake up packet to wake up the MDDI link. 4. The terminal resistors are embedded between MDDI_DATA0_P/M, MDDI_DATA1_P/M and MDDI_STB_P/M. 10/28/2011 160 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.4.1 MDDI Link Protocol by The NT35510 The NT35510’s MDDI Link Protocol is in accordance with the MDDI specifications as published by VESA; refer to these specifications for more information on the MDDI Link Protocol. DO NOT send any packets that are not supported by the NT35510 into a system containing the NT35510. Supported MDDI packets are as follows: Table 5.4.1 Summary of MDDI packets supported by NT35510 NT35510 MDDI packets Link Control Packet Client Status and Control Packet Basic Media Stream Packet Packet Name Sub-frame header packet Filler packet Link Shutdown packet Reverse link encapsulation packet Round-trip delay measurement packet Forward link skew calibration packet Client capability packet Client request and status packet Register access packet Video stream packet Flexible video stream packet Windowless video stream packet Packet Type 15359 (0x3BFF) 0 69 (0x45) 65 (0x41) 82 (0x52) 83 (0x53) 66 (0x42) 70 (0x46) 146 (0x92) 16 (0x10) 20 (0x14) 22 (0x16) Direction Forward Forward/Reverse Forward Forward Forward Forward Reverse Reverse Forward/Reverse Forward Forward Forward Supported Type Type I/Type II Type I/Type II Type I/Type II Type I Only Type I/Type II Type I/Type II Type I Only Type I Only Type I/ Type II (Forward) Type I Only (Reverse) Type I/Type II Type I/Type II Type I/Type II 10/28/2011 161 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.4.2 MDDI Link Packet Descriptions by the NT35510 Sub-frame Header Packet The Sub-Frame Header Packet is the first packet of every sub-frame. Sub-frame Header Packet Packet Length Packet Type =0x3bff Unique word = 0x005a Reversed 1 Sub-frame Length Protocol Version Sub-frame Count Media-frame Count CRC 2 bytes 2 bytes 2 bytes 2 bytes 4 bytes 2 bytes 2 bytes 4 bytes 2 bytes Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 0x3bff Unique Word: unique word is 0x005a Reserved 1: not used (set to zero) Sub-frame Length: specify the number of bytes per sub-frame Protocol version: set to zero  Bit [15:2] – Reserved for future expansion. These should be set to all zero.  Bits[1:0] – Sub-frame operational mode “00” – Sub-frame lengths strictly followed. “01” – Sub-frame lengths are flexible. Sub-frame packets should be sent at the first opportunity after the sub-frame length has been transmitted. “10” – Sub-frame lengths are unlimited. No more sub-frame packets are required tobe transmitted after the first Sub-Frame packet at startup. Sub-frame Count: specify the number of sub-frame header packet Media-frame Count: specify the number of media-frames CRC: error check Filler Packet The Filler Packet is sent when no other information is available to be sent on the forward or reverse link. Filler Packet Packet Length Packet Type=0 Filler Bytes (all zero recommended) CRC 2 bytes 2 bytes (Packet_Length – 4) bytes 2 bytes Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 0 Filler Bytes: set to zero CRC: error check 10/28/2011 162 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Link Shutdown Packet The Link Shutdown Packet is sent from the host to the client to indicate that the MDDI data and strobe will be shut down and go into a low-power hibernation state. Link Shutdown Packer Packet Length Packet Type=69 CRC All Zero 2 bytes 2 bytes 2 bytes (Packet_Length – 4) bytes Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 69 CRC: error check All Zero: set to zero (Type I: size is 16 bytes, Type II: size is 32 bytes) Reverse Link Encapsulation Packet Data is transferred in the reverse direction using the Reverse Link Encapsulation Packet. Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 65 hClient ID: set to zero Reverse Link Flags:  Bit 0 – 0: No packet request 1: Host needs the Client Capability Packet  Bit 1 – 0: No packet request 1: Host needs the Client Request and Status Packet  Bit [7:2] – set to zero Reverse Rate Divisor: reverse data rate = reverse link data clock Turn-Around 1 Length: the length of Turn-Around 1 is the forward link data rate Turn-Around 2 Length: the length of Turn-Around 2 is determined by Round-trip delay of the link Parameter CRC: error check All zero: set to zero Turn-Around 1: First turn-around period Reverse Data Packets: A series of data packets transferred from the client to host Turn-Around 2: The second turn-around period 10/28/2011 163 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Round-Trip Delay Measurement Packet The Round-Trip Delay Measurement Packet is used to measure the propagation delay from the host to the client plus the delay from the client back to the host. This packet is most useful when the MDDI link is running at the maximum speed intended for a particular application. The packet may be sent in Type I mode and at a lower data rate to increase the range of the Round-Trip delay measurement. Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 82 hCilent ID: set to zero Parameter CRC: error check Guard Time 1: allow overlap of the host and client Measurement Period: a 64 bytes window to allow the client to respond All Zero: set to zero Guard Time 2: allow overlap of the measurement period by the client Fig. 5.4.2 illustrates the timing of events during the Round-Trip Delay Measurement Packet. 1 Data from Host 0 hClient ID 2 bytes Parameter CRC 2 bytes Guard Time 1 (64 bytes length) 64 bytes All Zero (2 bytes) Measurement Period (64 bytes length) Host to Client Delay 0xFF, 0xFF and 30 bytes of 0x00 sequence at ? FWD rate Guard Time 2 (64 bytes length) (next packet) Packet Length 1 Aggregate Data View at Host 0 hClient ID 2 bytes Parameter CRC 2 bytes Client to Host Delay Round Trip Delay Fig. 5.4.2 Round-Trip Delay Measurement Timing Packet Length 10/28/2011 164 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Forward Link Skew Calibration Packet This packet allows the client to calibrate itself for differences in the propagation delay of the MDDI_DATA signals with respect to the MDDI_STB signal. Without delay skew compensation the maximum data rate must be limited to account for the worst-case variation in these delays. It is recommended that this packet only be sent when the forward link data rate is configured to 50 Mbps or lower. After sending this packet to calibrate the client the data rate may be stepped up above 50 Mbps. With the data rate set too high during the skew calibration process the client might synchronize to an alias of the bit period which would cause the delay skew compensation setting to be off by more than one bit time, resulting in erroneous data clocking. The greatest possible Interface Type must be selected prior to sending the Forward Link Skew Calibration Packet so that all existing data bits are calibrated. The client must indicate its ability to support the Forward Link Skew Calibration Packet via bit 19 of Client Feature Capability Indicators field of the Client Capability Packet. Prior to performing skew calibration the host must not send data faster than the rate specified by the Pre-calibration Data Rate Capability field of the Client Capability Packet. However, after calibration is performed, the host may send data up to the rate defined by the Post-calibration Data Rate Capability field. It is recommended that the host send the Forward Link Skew Calibration Packet at regular intervals to correct changes in the relative delay between the different signal pairs due to changes in temperature. Forward Link Skew Calibration Packet Packet Length Packet Type=83 hClient ID Parameter CRC All Zero 1 Calibration Data Sequence All Zero 2 2 bytes 2 bytes 2 bytes 2 bytes 2 bytes Packet Length - 22 bytes 2 bytes Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 83 hCilent ID: set to zero Parameter CRC: error check from packet length to the hClient ID. All Zero 1: 8 bytes that contain eight 8-bit unsigned integers equal to zero. This field ensures that there will be a transition on MDDI_STB at the beginning of the Calibration Data Sequence field. It also provides sufficient time for the client core logic to change the mode of the clock recovery circuit from using the XOR of MDDI_Data0 and MDDI_STB to simply using MDDI_STB as the recovered clock. Calibration Data Sequence: a data sequence that causes the MDDI_Data signals to toggle at every data period. The length of the Calibration Data Sequence field is determined by the interface type being used on the forward link. During the Calibration Data Sequence the MDDI host controller sets all MDDI_Data signals equal to the strobe signal. The client clock recovery circuit must use only MDDI_STB rather than MDDI_STB XOR MDDI_Data0 to recover the data clock while the Calibration Data Sequence field is being received by the client. Depending on the exact phase of MDDI_STB at the beginning of the Calibration Data Sequence field the Calibration Data Sequence will be one of the following based on the interface Type being used when this packet is sent:  Type 1 – (64 byte data sequence) AAh, AAh … or 55h, 55h…  Type 2 – (128 byte data sequence) CCh, CCh … or 33h, 33h… All Zero 2: 8 bytes that contain eight 8-bit unsigned integers equal to zero. This field provides sufficient time for the client core logic to change the mode of the clock recovery circuit back to the original state, from using MDDI_STB as the recovered clock to using the XOR of MDDI_Data0 and MDDI_STB. 10/28/2011 165 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Client Capability Packet It is recommended that the client send a Client Capability Packet to the host after forward link synchronization is acquired, and it is required when requested by the host via the Reverse Link Flags in the Reverse Link Encapsulation Packet. Client Capability Packet Packet Length 2 bytes Number of Alt Display 1 bytes Packet Type=66 2 bytes cClient ID 2 bytes Protocol Version 2 bytes Min Protocol Version 2 bytes Pre-calibration Data Rate Capability 2 bytes Post-calibration Data Rate Capability 2 bytes Bitmap Width 2 bytes Bitmap Height 2 bytes Display Window Width 2 bytes Display Window Height 2 bytes Interface Type Capability 1 bytes Color Map Size 4 bytes Color Map RGB Width 2 bytes Client Feature Capability 4 bytes Audio Sample Resolution 1 bytes RGB Capability Monochrome Capability Reversed 1 Y Cb Cr Capability Bayer Capability Revered 2 2 bytes 1 bytes 1 bytes 2 bytes 2 bytes 2 bytes Max Video Frame Rate 1 bytes Min Video Frame Rate 1 bytes Min Sub-frame Rate 2 bytes Audio Buffer Depth 2 bytes Audio Channel Capability 2 bytes Audio Sample Rate Capability 2 bytes Mic Sample Resolution 1 bytes Mic Sample Rate Capability 2 bytes Keyboard Data Format 1 bytes Pointing Device Data Format 1 bytes Content Protection Type 2 bytes Mfr Name 2 bytes Product Code Revered 3 Serial Number Week of Mfr 2 bytes 2 bytes 4 bytes 1 bytes Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 66 cClient ID: set to zero Protocol Version: set to 0002h Min Protocol Version: specify the minimum protocol version (0001h) Pre-Calibration Data Rate Capability: specify the maximum data rate the client can receive (190h) Interface Type Capability: Client can function in Type 2 (2-bit) mode on the forward link (01h) Number of Alt Displays: set to zero Post-Calibration Data Rate Capability: specify the maximum data rate the client can receive (190h) Bitmap Width: specify the width of the bitmap Bitmap Height: specify the height of the bitmap Display Window Width: specify the width of the display window Display Window Height: specify the height of the display window Color Map Size: set to zero Color Map RGB Width: set to zero RGB Capability: specify the resolution of RGB format (8888h) Monochrome Capability: set to zero Reserved 1: set to zero Y Cb Cr Capability: set to zero Bayer Capability: set to zero Reserved 2: set to zero Client Feature Capability Indicators: 00CC8000h Maximum Video Frame Rate Capability: specify the maximum video frame (3Ch) Minimum Video Frame Rate Capability: specify the minimum video frame (00h) Minimum Sub-frame Rate: specify the minimum sub-frame rate (01h) Audio Buffer Depth: set to zero Audio Channel Capability: set to zero Audio Sample Rate Capability: Set to zero Audio Sample Resolution: set to zero Mic Audio Sample Resolution: set to zero Mic Sample Rate Capability: set to zero Keyboard Data Format: set to zero Pointing Device Data Format: set to zero Content Protection Type: set to zero Mfr Name: set to B9F6h Product Code: set to 5510h Reserved 3: set to zero Serial Number: set to zero Week of Manufacture: set to zero Year of Manufacture: 0Ah CRC: error check Year of Mfr 1 bytes CRC 2 bytes 10/28/2011 166 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Client Request and Status Packet The host needs a small amount of information from the client so it can configure the host-to-client link in an optimum manner. The Client Request and Status Packet is required to report errors and status to the host. Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 70 cClient ID: set to zero Reverse Link Request: specify the number of bytes the client needs in the reverse link in the next sub-frame to send information to the host. CRC Error Count: count the number of CRC errors occurred Client Status:  Bit 0 – 1: capability has changed 0: capability has not changed  Bit 1 – indicates the client has detected an error  Bit [7:2] – set to zero Client Busy Flags:  Bit 0 – bitmap block transfer function is busy  Bit 1 – bitmap area fill function is busy  Bit 2 – bitmap pattern fill function is busy  Bit 3 – the graphics subsystem is busy  Bit [15:4] – set to zero CRC: error check 10/28/2011 167 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Register Access Packet Register Access Packet is utilized when setting instruction to the NT35510. This packet cannot be used for RAM access. Register Access Packet Packet Length Packet Type =146 bClient ID Read/Write Info Register Address Parameter CRC Register Data List Register Data CRC 2 bytes 2 bytes 2 bytes 2 bytes 4 bytes 2 bytes (Packet Length – 14) bytes 2 bytes Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 146 bClient ID: set to zero Read/Write Info: Bits [15:14] Read/Write Flags 00 Write 01 Reserved 10 Read 11 Response to read Bit [13:0] – specifies the number of 32-bit register data list items to be transferred in the Register Data List Filed. Register Address: upper bits shall set to zero Parameter CRC: error check from packet length to the register address Register Data List: written (or read) registers to (from) client Register Data CRC: error check of the register data list 10/28/2011 168 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Video Stream Packet The NT35510 supports the Video Stream Packet to transfer display data including RGB data to RAM. Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 16 bClient ID: set to zero Video Data Format Descriptor [15:12] [11:8] [7:4] [3:0] Transfer pixel format 0101 0x8 0x8 0x8 Packed 24 bits pixel RGB format (R:G:B=8:8:8) 0101 0x6 0x6 0x6 Packed 18 bits pixel RGB format (R:G:B=6:6:6) 0101 0x5 0x6 0x5 Packed 16 bits pixel RGB format (R:G:B=5:6:5) Others setting disabled Pixel Data Attributes: The pixel data is written to RAM buffer of NT36551 (00C3h) X Left Edge: Specify the X coordinate of the left edge of the screen window filled by the Pixel Data field. Y Top Edge: Specify the Y coordinate of the top edge of the screen window filled by the Pixel Data field X Right Edge: Specify the X coordinate of the right edge of the window being updated. Y Bottom Edge: Specify the Y coordinate of the bottom edge of the window being updated. X Start: Specify X start address for the first pixel in the Pixel Data field below. Y Start: Specify Y start address for the first pixel in the Pixel Data field below. Pixel Count: specify the number of pixels Parameter CRC: error check from packet length to the pixel count Pixel Data: the raw video data Pixel Data CRC: error check of the pixel data Table 5.4.1 Pixel Data Format MDDI date byte D7 D6 D5 D4 D3 D2 D1 D0 Color RGB Byte n G2 G1 G0 B4 B3 B2 B1 B0 65K-Color 5:6:5 Byte n+1 R4 R3 R2 R1 R0 G5 G4 G3 (1 pixel/ 16 bits RGB format) Byte n G1 G0 B5 B4 B3 B2 B1 B0 RGB 262K-Color 6:6:6 Byte n+1 R3 R2 R1 R0 G5 G4 G3 G2 (1 pixel/ 18 bits RGB format) Byte n+2 B5 B4 B3 B2 B1 B0 R5 R4 Byte n B7 B6 B5 B4 B3 B2 B1 B0 RGB Byte n+1 G7 G6 G5 G4 G3 G2 G1 G0 16.7M-Color 8:8:8 (1 pixel/ 24 bits RGB format) Byte n+2 R7 R6 R5 R4 R3 R2 R1 R0 10/28/2011 169 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Flexible Video Stream Packet The NT35510 supports the Flexible Video Stream Packet to transfer display data including RGB data to RAM. This allows for a reduction in the number of fields sent in an environment where one or more fields are not changing values. Flexible Video Stream Packet Packet Length Packet Type=20 2 bytes 2 bytes bClient ID 2 bytes Field Present Flags 2 bytes Video Data Format Description 2 bytes Pixel Data Attributes X Left Edge Y Top Edge 2 bytes 2 bytes 2 bytes X Right Edge Y Bottom Edge X Start Y Start Pixel Count Parameter CRC Pixel Data Pixel Data CRC 2 bytes 2 bytes 2 bytes 2 bytes 2 bytes 2 bytes Packet Length – present header bytes 2 bytes Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 20 bClient ID: set to zero Field Present Flags: indicates the field in the packet is present (value “1”) or not present (value “0”). - Bit 0: indicates the presence of the Video Data Format Description Field. - Bit 1: indicates the presence of the Pixel Data Attributes Field. - Bit 2: indicates the presence of the X Left Edge Field. - Bit 3: indicates the presence of the Y Top Edge Field. - Bit 4: indicates the presence of the X Right Edge Field. - Bit 5: indicates the presence of the Y Bottom Edge Field. - Bit 6: indicates the presence of the X Start Field. - Bit 7: indicates the presence of the Y Start Field. - Bit 8: indicates the presence of the Pixel Count Field. - Bits [15:9] are all “0”. Video Data Format Descriptor [15:12] [11:8] [7:4] [3:0] Transfer pixel format 0101 0x8 0x8 0x8 Packed 24 bits pixel RGB format (R:G:B=8:8:8) 0101 0x6 0x6 0x6 Packed 18 bits pixel RGB format (R:G:B=6:6:6) 0101 0x5 0x6 0x5 Packed 16 bits pixel RGB format (R:G:B=5:6:5) Others setting disabled X Left Edge: Specify the X coordinate of the left edge of the screen window filled by the Pixel Data field. Y Top Edge: Specify the Y coordinate of the top edge of the screen window filled by the Pixel Data field X Right Edge: Specify the X coordinate of the right edge of the window being updated. Y Bottom Edge: Specify the Y coordinate of the bottom edge of the window being updated. X Start: Specify X start address for the first pixel in the Pixel Data field below. Y Start: Specify Y start address for the first pixel in the Pixel Data field below. Pixel Data Attributes: The pixel data is written to RAM buffer of NT35510 (00C3h) Pixel Count: specify the number of pixels Parameter CRC: error check from packet length to the pixel count Pixel Data: the raw video data Pixel Data CRC: error check of the pixel data 10/28/2011 170 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Windowless Video Stream Packet The NT35510 supports the Windowless Video Stream Packet to transfer display data including RGB data to RAM. This packet type assumes that full screen updates are always occurring and therefore there is no need for the window information. Windowless Video Stream Packet Packet Length Packet Type=22 bClient ID 2 bytes 2 bytes 2 bytes Video Data Format Description 2 bytes Pixel Data Attributes Pixel Count Parameter CRC 2 bytes 2 bytes 2 bytes Pixel Data Pixel Data CRC Packet Length – 14 bytes 2 bytes Packet Contents: Packet Length: packet length not including the packet length field Packet Type: packet type is 22 bClient ID: set to zero Video Data Format Descriptor [15:12] [11:8] [7:4] [3:0] Transfer pixel format 0101 0x8 0x8 0x8 Packed 24 bits pixel RGB format (R:G:B=8:8:8) 0101 0x6 0x6 0x6 Packed 18 bits pixel RGB format (R:G:B=6:6:6) 0101 0x5 0x6 0x5 Packed 16 bits pixel RGB format (R:G:B=5:6:5) Others setting disabled Pixel Data Attributes: The pixel data is written to RAM buffer of NT36551 (00C3h) Pixel Count: specify the number of pixels Parameter CRC: error check from packet length to the pixel count Pixel Data: the raw video data Pixel Data CRC: error check of the pixel data 10/28/2011 171 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.4.3 Writing Video Data to Memory Sequence In order to write video data to memory, the following sequence should be programmed. This packet should be followed by video stream packets. Video Data Transfer (Video Stream Packet) Video Data Transfer (Video Stream Packet) Video Data Transfer (Video Stream Packet) Fig. 5.4.3 Writing Video Data to Memory Sequence 5.4.4 Writing Register Sequence In order to write registers, register access packet should be used. Register access packet is used to write data to register. Command Transfer (Register Access Packet) Fig. 5.4.4 Writing Register Sequence 10/28/2011 172 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.4.5 Reading Video Data from Memory Sequence In order to read a pixel data from memory (readable one pixel only), the following sequence should be programmed. Memory read command (2E00h) is followed by reverse encapsulation packet. DDI transmits video pixel data through encapsulation packet. Please refer to VESA spec for detailed description. Round-Trip Delay Measurement Transfer (Round Trip Delay Measurement Packet) Read Memory Transfer (2E00h) (Register Access Packet) Reverse Encapsulation Transfer (Reverse Encapsulation Packet) Fig. 5.4.5 Reading Video Data from Memory Sequence Notes: 1. X addresses for memory data read is set by 2A00h and 2A01h (XS[15:0]). The parameters of 2A00h and 2A01h are stored on relative registers while command 2A00h~2A03h are executed completely. See also section “6.1 User Command Set” and Note 2. 2. Y addresses for memory data read is set by 2B00h and 2B01h (YS[15:0]). The parameters of 2B00h and 2B01h are stored on relative registers while command 2B00h~2B03h are executed completely. See also section “6.1 User Command Set” and Note 2. 5.4.6 Reading Register Sequence In order to read registers, the following sequence should be programmed. Next, register read command is followed by reverse encapsulation packet. DDI transmits register data through encapsulation packet. Please refer to VESA spec for detailed description. Round-Trip Delay Measurement Transfer (Round Trip Delay Measurement Packet) Read Register Command Transfer (Register Access Packet) Reverse Encapsulation Transfer (Reverse Encapsulation Packet) Fig. 5.4.6 Reading Register Sequence 10/28/2011 173 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.4.7 Hibernation Setting The Client MDDI of the NT35510 provides a hibernation setting. The methods for waking up the hibernation mode can be determined based on actual usage. Wake-up Condition Host-Initiated Wake-up Wake up the MDDI link by MDDI Host Note: In the Hibernation state, the data is retained in RAM and the display operation is maintained. Hibernation setting and wake-up sequence must in accordance with VESA-MDDI specifications. Hibernation setting sequence Enter Hibernation Mode Shutdown Packet In Hibernation Mode Fig. 5.4.7 Enter Hibernation Mode Sequence Hibernation Wake-up sequence In Hibernation Mode Host Initiated Wake-up Exit Hibernation Mode Fig. 5.4.8 Hibernation Wake-up Sequence 10/28/2011 174 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.4.8 MDDI Deep Standby Mode Setting The Client MDDI of the NT35510 includes a MDDI deep standby mode setting so it can enter a off state and reduce power consumption during Hibernation mode. The MDDI enters Hibernation mode when a Shutdown Packet is sent. The standby power needs of the Client MDDI can be reduced, even while the MDDI Link is maintained in Hibernation mode. When entering MDDI deep standby mode, the NT35510 stops operation rather than maintaining Hibernation mode. Input low pulse 3 msec from RESX pin to cancel deep standby mode, after which a Host-Initiated Wake-up should cancel the Hibernation mode. When in deep standby mode, instruction settings and RAM data are not stored, so they must be reset after Hibernation mode is cancelled. Follow the sequence indicated in the VESA MDDI specifications when initiating or canceling the Hibernation mode. RESET Shutdown Packet MDDI Hibernation Exit MDDI Deep Standby Mode Input low pulse more than 3 msec to pin RESX Host Initiated Host Initiated Shutdown Packet MDDI Active (Sleep-out Mode and Display On) Set SLPOUT (1100h) and Set DISPON (2900h) Set DISPOFF (2800h) and Set SLPIN (1000h) MDDI Active (Sleep-in Mode and Display Off) MDDI Deep Standby Enter MDDI Deep Standby Mode Set DSTBON (4F00h) and DSTB=1 to enter MDDI Deep Standby Mode Fig. 5.4.9 State Transitions in MDDI Deep Standby Mode Note: When the NT35510 is in the MDDI Hibernation mode or MDDI deep standby mode, both links are in the link hibernation states. 10/28/2011 175 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY MDDI Deep Standby Mode Sequence Enter Sleep-In Mode and Display Off NT35510 Delay 4 frames or more Set DSTBON (4F00h) and DSTB=1 (Register Access Packet) MDDI Deep Standby Mode Exit MDDI Deep Standby Mode (Input low pulse more the 3msec to pin RESX) Delay 4 frames or more Host Initiated and Wake Up Initial Instruction Setting and RAM Data Setting Display On Sequence Fig. 5.4.10 Enter and Exit MDDI Deep Standby Mode Sequence Note: When in MDDI Deep Standby mode, instruction settings and RAM data are not stored, so they must be reset after Hibernation mode is cancelled. 10/28/2011 176 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.5 Interface Pause By using parallel interface, it is possible when transferring a Command, Frame Memory Data or Multiple Parameter Data to invoke a pause in the data transmission. If the CSX (Chip Select Line) is released after a whole byte of a Frame Memory Data or Multiple Parameter Data has been completed, then NT35510 will wait and continue the Frame Memory Data or Parameter Data Transmission from the point where it was paused. If the CSX (Chip Select Line) is released after a whole byte of a command as been completed, then the Display Module will receive either the command’s parameters (if appropriate) or a new command when the CSX (Chip Select Line) is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter Parallel Interface Pause CSX Pause D/CX RDX WRX D[7:0] D[7:0] Command / Parameter Pause D[7:0] Command / Parameter Fig. 5.5.1 Parallel bus protocol, write mode – paused by CSX Serial Interface Pause 16-bit SPI interface does not support "Pause Mode" MIPI Interface Pause Pause can be done on DSI between Packets when they are sent to same or different receiver (Virtual Channel (VC)) e.g. 1) Same receiver: Packet 1 (VC=00) => Packet 2 (VC=00) => Packet 3 (VC=00) => … 2) Different receiver: Packet 1 (VC=00) => Packet 2 (VC=00) => Packet 3 (VC=00) => … The means that “=>” symbol means a pause on DSI. 10/28/2011 177 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.6 Data Transfer Break and Recovery If there is a break in data transmission by RESX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then NT35510 will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been High state. See the following example (See Fig. 5.6.1) If there is a break in data transmission by CSX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then NT35510 will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example (See Fig. 5.6.2) S Transmission Byte S Transmission Byte Transmission Byte RESX (Host to Driver IC) CSX (Host to Driver IC) SDI, Falling Edge (Host to Driver IC) SDI, Rising Edge (Host to Driver IC) SDI (Host to Driver IC) SDO (Driver IC to Host) 8-bit R/W D/CX H/L 0 0 0 0 0 ADD[ ADD[ 15] 14] High-Z 8-bit 8-bit R/W D/CX H/L 0 0 0 0 0 ADD[ ADD[ ADD[ ADD[ ADD ADD ADD ADD 15] 14] 13] 12] [11] [10] [9] [8] High-Z High-Z R/W = 0 for Writing Command / Address D/CX = 0 for Command / Address Transmission H/L = 1 for Command / Address High Byte Transmission Wait for more than 10 ms SCL and SDI during RESX = "L" is invalid and next byte becomes command R/W = 0 for Writing Command / Address D/CX = 0 for Command / Address Transmission H/L = 1 for Command / Address High Byte Transmission Fig. 5.6.1 Serial bus protocol, write mode – interrupted by REX S Transmission Byte RESX (Host to Driver IC) CSX (Host to Driver IC) SDI, Falling Edge (Host to Driver IC) SDI, Rising Edge (Host to Driver IC) SDI (Host to Driver IC) SDO (Driver IC to Host) 8-bit R/W D/CX H/L 0 0 0 0 0 High-Z High-Z Break R/W = 0 for Writing Command / Address D/CX = 0 for Command / Address Transmission H/L = 1 for Command / Address High Byte Transmission Transmission Byte 8-bit Transmission Byte 8-bit R/W D/CX H/L 0 0 0 0 0 ADD[ ADD[ ADD ADD ADD[ ADD ADD ADD 15] 14] [13] [12] 11] [10] [9] [8] High-Z High-Z R/W = 0 for Writing Command / Address D/CX = 0 for Command / Address Transmission H/L = 1 for Command / Address High Byte Transmission Fig. 5.6.2 Serial bus protocol, write mode – interrupted by CSX 10/28/2011 178 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Display data transfer break is illustrated for reference purposes below. Without break Command 1 Parameter 1 Parameter 2 Parameter 3 With break (See and check also exceptions*) Ignored parameters Command 1 Parameter 1 The old value is kept on the register Parameter 2 The old value is kept on the register Parameter 3 The old value is kept on the register Break Command 2 Parameter for Command 2 Break can be e.g. another command or noise pulse. Fig. 5.6.3 Break during Parameter *) See also an exception on section “6.1 User Command Set” and Note 2. The MCU can create a break condition when it is forcing DSI data lanes in the LP-11 mode The NT35510 stops to control DSI data lanes (change from a transmitter mode to a received mode) if it was controlling DSI data lanes as a transmitter when the MCU is forcing DSI data lanes in the LP-11. The break condition can be done any time when the MCU or the driver IC is controlling DSI data lanes e.g. the driver IC is sending data to the MCU. Except MIPI interface, the data transfer break mechanism illustrated for reference purposes below. Ignored parameters Command 1 Parameter 1 The new value is stored on the register Parameter 2 The old value is kept on the register Parameter 3 The old value is kept on the register Break Command 2 Parameter for Command 2 10/28/2011 179 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.7 Display Module Data Transfer Modes The NT35510 has 3 kinds of color mode for transferring data to the frame Memory. There are 16-bit color per pixel, 18-bit color per pixel and 24-bit color per pixel. The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods. Method 1 The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer is reset to the start point and the next Frame is written. Start Stop Start Frame Image Data Image Data Image Data Memory Write Frame 1 Frame 2 Frame 3 Any Command Fig. 5.7.1 Data Transfer Method 1 Method 2 Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a new Frame is downloaded. Start Stop Start Frame Image Data Any Start Frame Image Data Any Memory Write Frame 1 Command Memory Write Frame 2 Command Any Command Start Start Frame Memory Write Fig. 5.7.2 Data Transfer Method 2 with “Start Frame Memory Write” Break Image Data Start Frame Image Data Start Frame Image Data Frame 1 Memory Write Frame 2 Memory Write Frame 3 Stop Any Command Fig. 5.7.3 Data Transfer Method 2 with “Any Command” Break NOTES: 1) The Frame Memory can contain odd and even number of pixels for both Methods. Only complete pixel data will be stored in the Frame Memory. 2) “Memory Write Continue (3Ch)” or “Memory Read Continue (3Eh)” commands are not stopping writing or reading to/from the frame memory. These commands can be used if there is wanted to continue the writing or reading to/from the frame memory when “Any Command” has stopped the memory writing or reading. 3) “Any Command” can be as same as “Start Frame Memory Write”. 10/28/2011 180 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.8 RGB Interface 5.8.1 General Description For direct interface with both graphic controller and MPU, NT35510 offer RGB interface mode to display video signal. The parallel RGB interface includes: VS, HS, DE, PCLK, D[23:0]. The interface is activated after Power On sequence (See section Power On/Off Sequence) Pixel clock (PCLK) is running all the time without stopping and it is used to entering VS, HS, DE and D[23:0] states when there is a rising edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g. Sleep In –mode etc. Vertical synchronization (VS) is used to tell when there is received a new frame of the display. This is negative (“0”, low) active and its state is read to the display module by a rising edge of he PCLK signal. Horizontal synchronization (HS) is used to tell when there is received a new line of the frame. This is negative (“0”, low) active and its state is read to the display module by a rising edge of the PCLK signal. Data Enable (DE) is used to tell when there is received RGB information that should be transferred on the display. This is a positive ( “1”, high) active and its state is read to the display module by a rising edge of the PCLK signal. D[23:0] (24-bit: R7-R0, G7-G0 and B7-B0;18-bit: R5-R0, G5-G0 and B5-B0; 16-bit: R4-R0, G5-G0 and B4-B0) are used to tell what is the information of the image that is transferred on the display (When DE= “1” and there is a rising edge of PCLK). D[23:0] can be “0” (low) or “1” (high). These lines are read by a rising edge of the PCLK signal. The PCLK cycle is described in the follow figure. PCLK VS, HS, DE D[23:0] The host changes D[23:0] , VS, HS and DE lines when there is a falling edge of the PCLK Note: PCLK is an unsynchronized signal (It can be stopped) The driver read the D[23:0] , VS, HS and DE lines when there is a rising edge of the PCLK 10/28/2011 181 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.8.2 RGB Interface Timing Chart The image information must be correct on the display, when the timings are in range on the interface. However, the image information can be incorrect on the display, when timings are not out of range on the interface (Out of the range timings cannot on the host side). The correct image information must be displayed automatically (by the display module) on the next frame (vertical sync.) when there is returned from out of the range to in range interface timing. Hsync HBP HAdr HFP HFP – horizontal interval when no valid display data is sent from host to display (Hsync+HBP) – horizontal interval when no valid display data is sent from host to display Vsync VBP VAdr VFP (Vsync+VBP) – vertical interval when no valid display data is transferred from host to display (Vadr+Hadr) – period when valid display data are transferred from host to display module. VFP – vertical interval when no valid display data is transferred from host to display Fig. 5.8.1 RGB interface general timing diagram 10/28/2011 182 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.8.3 RGB Interface Mode Set RGB I/F Mode RGB Mode 1 (SYNC + DE) RGB Mode 2 (SYNC only) PCLK Used Used DE D23-D0 Used Not used Used Used VS Used Used HS Used Used Register VFP[7:0], VBP[7:0] HFP[7:0], HBP[7:0] Not used Used In RGB Mode 1, writing data to line buffer is done by PCLK and Video Data Bus (D23 to D0), when DE is high state. The external clocks (PCLK, VS and HS) are used for internal displaying clock. So, controller must always transfer PCLK, VS and HS signal to NT35510 DDI. In RGB Mode 2, back porch of Vsync VBP is defined by VBP[7:0] of RGBCTR command. And back porch of Hsync HBP is defined by HBP[7:0] of RGRCTR command. Front porch of Vsync VFP is defined by VFP[7:0] of RGBCTR command. And front porch of Hsync HFP is defined by HFP[7:0] of RGBCTR command. Note: VBP[7:0]=Vsync+VBP and HBP[7:0]=Hsync+HBP. 10/28/2011 183 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. (Vertical Back Porch) Vsync VBP VS tVHS HS DE PCLK PRELIMINARY NT35510 1 Frame Time Vertical Front Porch VFP tVHS (Horizontal Back Porch) Hsync HBP HS Valid Data Interval Horizontal Front Porch HFP PCLK DE D[23:0] Invalid Interval D1 D2 D3 D4 D5 … … … Dn-3 Dn-2 Dn-1 Dn Invalid Interval Latched Data Invalid Interval D1 D2 D3 D4 D5 … … … Dn-3 Dn-2 Dn-1 Dn Invalid Interval RAM WEN 1 Line Time Fig. 5.8.2 Video signal data writing method in RGB Mode 1 Interface Notes: 1. Constraint: V-Back Porch (Vsync+VBP)≧ 5 HS lines, V-Front-Borch (VFP) ≧ 2 HS lines Vsync+VBP+VFP (porch of RGB signal) > VBPA/B/C[7:0] (internal display back porch) H-Back Porch (Hsync+HBP)≧ 5 PCLK clocks, H-Front-Porch (HFP) ≧ 2 PCLK clocks 2. tVHS≧ 0ns 10/28/2011 184 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. VS HS DE PCLK Vertical Back Porch (VBP[7:0]) tVHS PRELIMINARY NT35510 1 Frame Time Vertical Front Porch (VFP[7:0]) tVHS Horizontal Back Porch (HBP[7:0]) HS Valid Data Interval Horizontal Front Porch (HFP[7:0]) PCLK DE D[23:0] Invalid Interval D1 D2 D3 D4 D5 … … … Dn-3 Dn-2 Dn-1 Dn Invalid Interval Latched Data Invalid Interval D1 D2 D3 D4 D5 … … … Dn-3 Dn-2 Dn-1 Dn Invalid Interval RAM WEN 1 Line Time Fig. 5.8.3 Video signal data writing method in RGB Mode 2 Interface Notes: 1. Constraint: V-Back Porch (VBP[7:0]) ≧ 5 HS lines, V-Front Porch (VFP[7:0]) ≧ 2 HS lines VBP[7:0]+VFP[7:0] (porch of RGB signal) > VBPA/B/C[7:0] (internal display back porch) H-Back Porch (HBP[7:0]) ≧ 5 PCLK clocks, H-Back Porch (HFP[7:0]) ≧ 2 PCLK clocks 2. tVHS≧ 0ns 10/28/2011 185 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 VS HS PCLK DE RGB Data bus D[23:0] Frame Data SDI/I2C_SDA Nth Frame Update frame data by RGB I/F External clock mode (N+1)th Frame (N+2)th Frame High / Low High / Low High / Low Low Don't care Don't care Don't update frame data by SDI/I2C_SDA Set ICM="1" STOP RAM Write Command (2C00h) Address Set Command (2A00h, 2B00h) Frame data Updating from SDI/I2C_SDA Internal clock mode Fig. 5.8.4 RGB with SPI Timing Sequence (Enter Internal Clock Mode, ICM=”1”) VS HS PCLK DE High / Low High / Low High / Low Low RGB Data bus D[23:0] STOP Frame Data SDI/I2C_SDA Address Set Command (2A00h, 2B00h) RAM Write Command (2C00h) Frame data Updating from SDI/I2C_SDA Internal clock mode 1st Frame 2nd Frame Don't care Don't care Don't update frame data by SDI/I2C_SDA Set ICM="0" 3rd Frame Update frame data by RGB I/F External clock mode Fig. 5.8.5 RGB with SPI Timing Sequence (Exit Internal Clock Mode, ICM=”0”) 10/28/2011 186 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.8.4 RGB Interface Bus Width Set All 3-kinds of bus width can be available during RGB interface mode (selected by the COLMOD command (3A00h): VIPF[3:0]). 3A00h D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bus Width 50h x x x R4 R3 R2 R1 R0 x x G5 G4 G3 G2 G1 G0 x x x B4 B3 B2 B1 B0 16-bit data 60h x x R5 R4 R3 R2 R1 R0 x x G5 G4 G3 G2 G1 G0 x x B5 B4 B3 B2 B1 B0 18-bit data 70h R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 24-bit data NOTES: 1. “x”: Unused RGB data bus connected with VSSI. 2. R0 is the LSB for the red component; G0 is the LSB for the green component, etc. 3. For 16-bit pixels, R primary color MSB is R4, G primary color MSB is G5 and B primary color MSB is B4. 4. For 18-bit pixels, R primary color MSB is R5, G primary color MSB is G5 and B primary color MSB is B5. 5. For 24-bit pixels, R primary color MSB is R7, G primary color MSB is G7 and B primary color MSB is B7 10/28/2011 187 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Write data for 16-bit RGB interface bus width set is shown below. VS "1" HS "1" DE "1" PCLK D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 1st Pixel R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 2nd Pixel R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 - -- B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, -Bit 0 3rd Pixel - - - ......... Rn, Bit 4 Rn, Bit 3 Rn, Bit 2 Rn, Bit 1 Rn, Bit 0 Gn, Bit 5 Gn, Bit 4 Gn, bit 3 Gn, Bit 2 Gn, Bit 1 Gn, Bit 0 Bn, Bit 4 Bn, Bit 3 Bn, Bit 2 Bn, Bit 1 Bn, Bit 0 nth Pixel 16-bit data format extends to 24-bit data format R1[4] R1[3] R1[2] R1[1] R1[0] R1[4] R1[3] R1[2] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] G1[5] G1[4] B1[4] B1[3] B1[2] B1[1] B1[0] B1[4] B1[3] B1[2] R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] Frame Memory 24-bit R1 G1 B1 R2 G2 B2 R3 G3 B3 10/28/2011 188 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Write data for 18-bit RGB interface bus width set is shown below. VS "1" HS "1" DE "1" PCLK D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 1st Pixel R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 2nd Pixel R3, Bit 5 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 -- G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 5 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 3rd Pixel - - - ......... Rn, Bit 5 Rn, Bit 4 Rn, Bit 3 Rn, Bit 2 Rn, Bit 1 Rn, Bit 0 Gn, Bit 5 Gn, Bit 4 Gn, bit 3 Gn, Bit 2 Gn, Bit 1 Gn, Bit 0 Bn, Bit 5 Bn, Bit 4 Bn, Bit 3 Bn, Bit 2 Bn, Bit 1 Bn, Bit 0 nth Pixel 18-bit data format extends to 24-bit data format R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] R1[5] R1[4] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] G1[5] G1[4] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] B1[5] B1[4] R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] Frame Memory 24-bit R1 G1 B1 R2 G2 B2 R3 G3 B3 10/28/2011 189 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Write data for 24-bit RGB interface bus width set is shown below. VS "1" HS "1" DE "1" PCLK D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R1, Bit 7 R1, Bit 6 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 7 G1, Bit 6 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 7 B1, Bit 6 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel 1 R2, Bit 7 R2, Bit 6 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 7 G2, Bit 6 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 7 B2, Bit 6 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel 2 R3, Bit 7 R3, Bit 6 R3, Bit 5 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 7 G3, Bit 6 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 7 B3, Bit 6 B3, Bit 5 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel 3 ......... Rn, Bit 7 Rn, Bit 6 Rn, Bit 5 Rn, Bit 4 Rn, Bit 3 Rn, Bit 2 Rn, Bit 1 Rn, Bit 0 Gn, Bit 7 Gn, Bit 6 Gn, Bit 5 Gn, Bit 4 Gn, bit 3 Gn, Bit 2 Gn, Bit 1 Gn, Bit 0 Bn, Bit 7 Bn, Bit 6 Bn, Bit 5 Bn, Bit 4 Bn, Bit 3 Bn, Bit 2 Bn, Bit 1 Bn, Bit 0 Pixel n R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] Frame Memory 24-bit R1 G1 B1 R2 G2 B2 R3 G3 B3 10/28/2011 190 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.9 Frame Memory 5.9.1 Configuration The NT35510 has an integrated 480 x 864 x 24-bit graphic type static RAM. This 9,953,280-bit memory allows to store on-chip a 480 x RGB x 864, 480 x RGB x 854, 480 x RGB x 800, 480 x RGB x 720 and 480 x RGB x 640 image with an 24-bit resolution (16.7M-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory. Display Panel 480 RGB x 864 MIPI I/F MCU I/F RGB I/F SPI I/F RGB-BGR Swap Row Address Counter 5/6-bit to 8-bit Host Interface Column Address Counter Latch Display Data RAM (480 x 24 x 864) Line Address Counter Scan Address Counter 10/28/2011 191 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.9.2 Address Counter The address counter sets the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 1-1-1-bit), according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM. The address pointers address the locations of RAM. When CGM[7:0]=”70h”, the address ranges are X=0 to X=479 (1DFh) and Y=0 to Y=863 (35Fh). When CGM[7:0]=”6Bh”, the address ranges are X=0 to X=479 (1DFh) and Y=0 to Y=853 (355h). When CGM[7:0]=”50h”, the address ranges are X=0 to X=479 (1DFh) and Y=0 to Y=799 (31Fh). When CGM[7:0]=”28h”, the address ranges are X=0 to X=479 (1DFh) and Y=0 to Y=719 (2CFh). When CGM[7:0]=”00h”, the address ranges are X=0 to X=479 (1DFh) and Y=0 to Y=639 (27Fh). Addresses outside these ranges are not allowed. Before writing to the RAM a window must be defined. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example, the whole display contents will be written when CGM[7:0]=”50h”, if the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=479 (1DFh), YE=799 (31Fh). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET” and “MADCTR” (see section 6 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Fig. 5.2.2 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as below: Condition Column Counter Row Counter When RAMWR/RAMRD command is accepted Return to “Start Column (XS)” Return to “Start Row (YS)” Complete Pixel Pair Read / Write action Twice Increment by 1 (First Pixel n then Pixel n+1) No change The Column counter value is larger than “End Column (XE)” Return to “Start Column (XS)” Increment by 1 The Column counter value is larger than “End Column (XE)” Return to Return to and the Row counter value is larger than “End Row (YE)” “Start Column (XS)” “Start Row (YS)” NOTE: Data is always written to the Frame Memory in the order, regardless of the Memory Write Direction set by command MADCTL (36h) bit MY, MX and MV. The write order for each pixel unit is (R, G, B) transferred from (D2, D1, D0) = (R, G, B). One pixel unit represents 1 column and 1 page counter value on the Frame Memory 10/28/2011 192 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.9.3 Interface to Memory Write Direction The resultant image for each orientation setting is illustrated below. Display Data Direction Normal MADCTR Parameter MV MX MY 000 Image in the Host (MPU) B Image in the Driver (DDRAM) H/W position (0,0) B X-Y address (0,0) X: CASET, Y: RASET E E Y-Mirror 001 B H/W position (0,0) E X-Mirror 010 B X-Y address (0,0) X: CASET, E Y: RASET B H/W position (0,0) B X-Y address (0,0) X: CASET, Y: RASET X-Mirror Y-Mirror 011 B X-Y Exchange 1 0 0 B X-Y Exchange 1 0 1 B Y-Mirror X-Y Exchange 1 1 0 B X-Mirror E E H/W position (0,0) E E H/W position (0,0) B X-Y address (0,0) X: CASET, Y: RASET E H/W position (0,0) X-Y address (0,0) X: CASET, E Y: RASET B H/W position (0,0) X-Y address (0,0) X: CASET, B Y: RASET E E B X-Y address (0,0) X: CASET, Y: RASET X-Y Exchange 1 1 1 B X-Mirror Y-Mirror E E H/W position (0,0) E E X-Y address (0,0) X: CASET, B Y: RASET NOTE: MV=D5 parameter of MADCTL command, MX=D6 parameter of MADCTL command, MY=D7 parameter of MADCTL command 10/28/2011 193 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.9.4 Frame Memory to Display Address Mapping The frame memory to display address mapping for 480RGB x 864 resolution (RSMX=RSMY=”0”) is shown below figure. The maximum address of RA/SA/CA and used source outputs are decided by bit CGM[2:0] (see command 2Ah CASET, 2Bh PASET and section 8.2). Pixel 1 Pixel 2 --------- Pixel N-1 Pixel N S1 S2 S3 S4 S5 S6 S7 S8 Source Output R0 G0 B0 R1 G1 B1 R2 G2 S1433 S1434 S1435 S1436 S1437 S1438 S1439 S1440 G477 B477 R478 G478 B478 R479 G479 B479 S1~S1440 RA (CA*) MY=0 MY=1 0 863 1 862 2 861 3 860 4 859 5 858 6 857 7 856 8 855 9 854 10 853 11 852 : : ::: : : ::: : : ::: : : ::: : : ::: : : ::: 856 7 857 6 858 5 859 4 860 3 861 2 862 1 863 0 MX=0 0 MX=1 479 RGB=0 : RGB=1 : :: :: : ::: ::::: :: :: : ::: ::::: Display Pattern Data : : : : : :: :: : ::: ::::: ::: ::::: :: :: : ::: ::::: :: :: : ::: ::::: 1 478 479 478 1 0 SA ML=0 0 1 2 3 4 5 6 7 8 9 10 11 : : : : : : 856 857 858 859 860 861 862 863 ML=1 863 862 861 860 859 858 857 856 855 854 853 852 : : : : : : 7 6 5 4 3 2 1 0 CA (RA*) RA = Row Address, CA = Column Address, SA = Scan Address, MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command PTD = Source output voltage selection for 1-bit data “0” and “1”, parameter of PWCTR5 command * RA and CA is exchange when MV = “1” 10/28/2011 194 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.10 Tearing Effect Information 5.10.1 Tearing Effect Output Line The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. 5.10.1.1 TEARING EFFECT LINE MODES Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only: t vdl t vdh Vertical time Scale tvdh = The LCD display is not updated from the Frame Memory tvdl = The LCD display is updated from the Frame Memory (except Invisible Line – see below) Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 864 H-sync pulses per field. thdl thdh V-Sync V-Sync Invisible Line 1st Line 2nd Line 863th Line 864th Line thdh = The LCD display is not updated from the Frame Memory thdl = The LCD display is updated from the Frame Memory (except Invisible Line – see above) Mode 3, this mode turn on the Tearing Effect Output signal when vertical scanning reaches line N. For reference Not belong to Mode 3 N=1 N=2 N=3 N=863 N=864 For reference Not belong to Mode 3 Mode 1 TE For reference, only one pulse tvdh is present at N-th scanning line Mode 1 TE N = The N-th scanning line which set by register N[15:0] of command STESL (44h) The TE mode selection is described as below table DOPCTR (B100h) TEOFF (34h) TEON (35h) STESL (44h) DSITE M N[15:0] TE Output 0 X X TE off (output low) 1 34h X TE off (output low) 1 35h with M=0 N[15:0]=0 TE high in V-porch region (Mode 1) 1 35h with M=0 N[15:0]≠0 TE high at N-th line (Mode 3) 1 35h with M=1 X TE high in all V-porch and H-porch region (Mode 2) 10/28/2011 195 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Bottom Line Top Line 2nd Line TE (Mode3) TE (Mode2) TE (Mode1) For reference, no H-Blanking are inside the V-Blanking tvdh For reference, no H-Blanking are inside the V-Blanking t vdh NOTE: During Sleep In Mode, the Tearing Output Pin is active Low 10/28/2011 196 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY 5.10.1.2 TEARING EFFECT LINE TIMING The Tearing Effect signal is described below: tvdl tvdh Vertical Timing NT35510 Horizontal Timing thdl thdh Table 5.10.1 AC characteristics of Tearing Effect Signal Symbol Parameter min max unit Description tvdl Vertical Timing Low Duration TBD - ms tvdh Vertical Timing High Duration 1000 - μs thdl Horizontal Timing Low Duration TBD - μs thdh Horizontal Timing High Duration TBD 500 μs Notes: 1. The timings in above table apply when MADCTL ML=0 and ML=1. 2. The signal’s rise and fall times (tr, tf) are stipulated to be equal to or less than 15ns when the maximum load is TBD Ω. The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. tr tf 0.8VDDIO 0.8VDDIO 0.2VDDIO 0.2VDDIO The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect: 10/28/2011 197 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY 5.10.1.3 EXAMPLE 1: MPU WRITE IS FASTER THAN PANEL READ. NT35510 MCU to Memory TE Output Signal 1st 120th Memory to LCD Image on LCD 1st a b 120th cd time time time Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image: Data to be sent a b c d Image on Display Panel 10/28/2011 198 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY 5.10.1.4 EXAMPLE 2: MPU WRITE IS SLOWER THAN PANEL READ. NT35510 MCU to Memory 1st 120th TE Output Signal Memory to LCD Image on LCD 1st 120th a b cd e f time time time The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position. Data to be sent a b c d e f Image on Display Panel 10/28/2011 199 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.10.2 Tearing Effect Bus Trigger A Tearing Effect Bus Trigger information supplies to the MCU a Panel synchronization trigger and this Tearing Effect Bus Trigger information can be enabled or disabled by “Tearing Effect Line On (35h)” and “Tearing Effect Line Off (34h)” commands when the only mode of the Tearing Effect Signal is V-Sync information. The driver IC is sending this trigger information in Escape Mode after the Bus Turnaround (BTA). and at a rising edge of the internal V-sync (A start of the new image frame). See section “Tearing Effect (TEE)” A Rising Edge of V-sync Internal V-sync DSI-D0 BTA TE Trigger => BTA Time MCU is Controlling Display Module is Controlling MCU is Controlling A Rising Edge of the V-sync and DSI-D0 The Tearing Effect Bus Trigger can use in both DSI case with or without the TE line when the driver IC is sending the TE trigger if it received a correct tearing effect trigger request as this is described on section “5.10.2.3 Tearing Effect Bus Trigger Sequence”. 10/28/2011 200 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.10.2.1 TEARING EFFECT BUS TRIGGER ENABLE The MCU can enable the Tearing Effect Bus Trigger on the driver IC in 2 different ways when Short Packet (SPa) or Long Packet (LPa) is used. These cases are illustrated below.: Packet Header (PH) Packet Data (PD) DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex 35hex (Tearing Effect Line On) 00hex (V-Sync) 2Fhex 101010001010110000000000 11110100 BBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBB 012345670123456701234567 01234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Tearing Effect Bus Trigger Enable (DCSW1-S) – Short Packet (SPa) Packet Header (PH) DI WC (Least Significant Byte) WC (Most Significant Byte) ECC 39hex 02hex 00hex 13hex 100111000100000000000000 01101100 BBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBB 012345670123456701234567 01234567 L ML ML ML M S SS SS SS S B BB BB BB B Packet Data (PD) Packet Footer (PF) Data 0 (DCS) Data 1 (Parameter) CRC (Least Significant Byte) CRC (Most Significant Byte) 35hex (Tearing Effect Line On) 00hex (V-Sync) A2hex 38hex 10101100000000000100010100011100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Tearing Effect Bus Trigger Enable (DCSW-L) – Long Packet (LPa) 10/28/2011 201 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.10.2.2 TEARING EFFECT BUS TRIGGER DISABLE The MCU can disable the Tearing Effect Bus Trigger on the driver IC in 2 different ways when Short Packet (SPa) or Long Packet (LPa) is used. These cases are illustrated below.: Packet Header (PH) Packet Data (PD) DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex 34hex (Tearing Effect Line Off) 00hex (V-Sync) 26hex 101010000010110000000000 01100100 BBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBB 012345670123456701234567 01234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Tearing Effect Bus Trigger Disable (DCSW1-S) – Short Packet (SPa) Packet Header (PH) DI WC (Least Significant Byte) WC (Most Significant Byte) ECC 39hex 01hex 00hex 15hex 100111001000000000000000 10101000 BBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBB 012345670123456701234567 01234567 L ML ML ML M S SS SS SS S B BB BB BB B Packet Data (PD) Packet Footer (PD) Data 0 (DCS) CRC (Least Significant Byte) CRC (Most Significant Byte) 34hex (Tearing Effect Line Off) 20hex 78hex 0010110000000100 00011110 BBBBBBBB BBBBBBBB BBBBBBBB 0123456701234567 01234567 L ML ML M S SS SS S B BB BB B Time Tearing Effect Bus Trigger Disable (DCSW-L) – Long Packet (LPa) 10/28/2011 202 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.10.2.3 TEARING EFFECT BUS TRIGGER SEQUENCES Tearing Effect Bus Trigger Enable Sequence – DCSW-L and HSDT MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSW-L HSDT => - - Tearing Effect Bus Trigger Enable 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - 5 - BTA <=> BTA - Interface control change from the MCU to the display module If no error => goto line 8 6 - - <= LP-11 - If error is corrected by ECC => goto line 19 If error => goto line 30 7 8 - - <= ACK - No Error 9 - - <= LP-11 - 10 - BTA <=> BTA - Interface control change from the display module to the MCU 11 - LP-11 => - - 12 - BTA <=> BTA - Interface control change from the MCU to the display module 13 - - <= LP-11 - 14 - - <= TEE - TE (Escape Trigger) on the next V-Sync 15 - - <= LP-11 - 16 - BTA <=> BTA - Interface control change from the display module to the MCU 17 - LP-11 => - - End 18 19 - - <= LPDT AwER Error Report 20 - - <= LP-11 - 21 - BTA <=> BTA - Interface control change from the display module to the MCU 22 - LP-11 => - - 23 - BTA <=> BTA - Interface control change from the MCU to the display module 24 - - <= LP-11 - 25 - - <= TEE - TE (Escape Trigger) on the next V-Sync 26 - - <= LP-11 - 27 - BTA <=> BTA - Interface control change from the display module to the MCU 28 - LP-11 => - - End 10/28/2011 203 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 29 30 - - <= 31 - - <= 32 - BTA <=> 33 - LP-11 => 34 - LP-11 => 35 36 - BTA <=> 37 - - <= 38 - LP-11 => 39 - BTA <=> 40 - - <= 41 - - <= 42 - - <= 43 - BTA <=> 44 - LP-11 => Notes: 1. Lines 1 ~ 17 are needed for every frame. 2. Bit 5 and Bit 7 of the AwER are applied. LPDT LP-11 BTA - - BTA LP-11 - BTA LP-11 LPDT LP-11 BTA - AwER - - - Error Report Interface control change from the display module to the MCU If the MCU is not forcing BTA => goto line 34 If the MCU is forcing BTA => goto line 35 End - - AwER - Interface control change from the MCU to the display module Dead-Lock (No TE information) The MCU is forced to start to control the interface. The display module detects Bus Connection Error (BCE) Interface control change from the MCU to the display module Error Report (Bus Connection Error (BCE) is reported) Interface control change from the display module to the MCU End 10/28/2011 204 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Tearing Effect Bus Trigger Enable Sequence – DCSW-L and LPDT MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSW-L LPDT => - - Tearing Effect Bus Trigger Enable 3 - LP-11 => - - 4 - BTA <=> BTA - Interface control change from the MCU to the display module If no error => goto line 7 5 - - <= LP-11 - If error is corrected by ECC => goto line 18 If error => goto line 29 6 7 - - <= ACK - No Error 8 - - <= LP-11 - 9 - BTA <=> BTA - Interface control change from the display module to the MCU 10 - LP-11 => - - 11 - BTA <=> BTA - Interface control change from the MCU to the display module 12 - - <= LP-11 - 13 - - <= TEE - TE (Escape Trigger) on the next V-Sync 14 - - <= LP-11 - 15 - BTA <=> BTA - Interface control change from the display module to the MCU 16 - LP-11 => - - End 17 18 - - <= LPDT AwER Error Report 19 - - <= LP-11 - 20 - BTA <=> BTA - Interface control change from the display module to the MCU 21 - LP-11 => - - 22 - BTA <=> BTA - Interface control change from the MCU to the display module 23 - - <= LP-11 - 24 - - <= TEE - TE (Escape Trigger) on the next V-Sync 25 - - <= LP-11 - 26 - BTA <=> BTA - Interface control change from the display module to the MCU 27 - LP-11 => - - End 10/28/2011 205 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 28 29 - - <= 30 - - <= 31 - BTA <=> 32 - LP-11 => 33 - LP-11 => 34 35 - BTA <=> 36 - - <= 37 - LP-11 => 38 - BTA <=> 39 - - <= 40 - - <= 41 - - <= 42 - BTA <=> 43 - LP-11 => Notes: 1. Lines 1 ~ 16 are needed for every frame. 2. Bit 5 and Bit7 of the AwER are applied. LPDT LP-11 BTA - - BTA LP-11 - BTA LP-11 LPDT LP-11 BTA - AwER - - - Error Report Interface control change from the display module to the MCU If the MCU is not forcing BTA => goto line 33 If the MCU is forcing BTA => goto line 35 End - - AwER - Interface control change from the MCU to the display module Dead-Lock (No TE information) The MCU is forced to start to control the interface. The display module detects Bus Connection Error (BCE) Interface control change from the MCU to the display module Error Report (Bus Connection Error (BCE) is reported) Interface control change from the display module to the MCU End 10/28/2011 206 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Tearing Effect Bus Trigger Enable Sequence – DCSW1-S and HSDT MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSW1-S HSDT => - - Tearing Effect Bus Trigger Enable 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - 5 - BTA <=> BTA - Interface control change from the MCU to the display module If no error => goto line 8 6 - - <= LP-11 - If error is corrected by ECC => goto line 19 If error => goto line 30 7 8 - - <= ACK - No Error 9 - - <= LP-11 - 10 - BTA <=> BTA - Interface control change from the display module to the MCU 11 - LP-11 => - - 12 - BTA <=> BTA - Interface control change from the MCU to the display module 13 - - <= LP-11 - 14 - - <= TEE - TE (Escape Trigger) on the next V-Sync 15 - - <= LP-11 - 16 - BTA <=> BTA - Interface control change from the display module to the MCU 17 - LP-11 => - - End 18 19 - - <= LPDT AwER Error Report 20 - - <= LP-11 - 21 - BTA <=> BTA - Interface control change from the display module to the MCU 22 - LP-11 => - - 23 - BTA <=> BTA - Interface control change from the MCU to the display module 24 - - <= LP-11 - 25 - - <= TEE - TE (Escape Trigger) on the next V-Sync 26 - - <= LP-11 - 27 - BTA <=> BTA - Interface control change from the display module to the MCU 28 - LP-11 => - - End 10/28/2011 207 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 29 30 - - <= 31 - - <= 32 - BTA <=> 33 - LP-11 => 34 - LP-11 => 35 36 - BTA <=> 37 - - <= 38 - LP-11 => 39 - BTA <=> 40 - - <= 41 - - <= 42 - - <= 43 - BTA <=> 44 - LP-11 => Notes: 1. Lines 1 ~ 17 are needed for every frame. 2. Bit 5 and Bit 7 of the AwER are applied. LPDT LP-11 BTA - - BTA LP-11 - BTA LP-11 LPDT LP-11 BTA - AwER - - - Error Report Interface control change from the display module to the MCU If the MCU is not forcing BTA => goto line 34 If the MCU is forcing BTA => goto line 36 End - - AwER - Interface control change from the MCU to the display module Dead-Lock (No TE information) The MCU is forced to start to control the interface. The display module detects Bus Connection Error (BCE) Interface control change from the MCU to the display module Error Report (Bus Connection Error (BCE) is reported) Interface control change from the display module to the MCU End 10/28/2011 208 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Tearing Effect Bus Trigger Enable Sequence – DCSW1-S and LPDT MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSW1-S LPDT => - - Tearing Effect Bus Trigger Enable 3 - LP-11 => - - 4 - BTA <=> BTA - Interface control change from the MCU to the display module If no error => goto line 7 5 - - <= LP-11 - If error is corrected by ECC => goto line 18 If error => goto line 29 6 7 - - <= ACK - No Error 8 - - <= LP-11 - 9 - BTA <=> BTA - Interface control change from the display module to the MCU 10 - LP-11 => - - 11 - BTA <=> BTA - Interface control change from the MCU to the display module 12 - - <= LP-11 - 13 - - <= TEE - TE (Escape Trigger) on the next V-Sync 14 - - <= LP-11 - 15 - BTA <=> BTA - Interface control change from the display module to the MCU 16 - LP-11 => - - End 17 18 - - <= LPDT AwER Error Report 19 - - <= LP-11 - 20 - BTA <=> BTA - Interface control change from the display module to the MCU 21 - LP-11 => - - 22 - BTA <=> BTA - Interface control change from the MCU to the display module 23 - - <= LP-11 - 24 - - <= TEE - TE (Escape Trigger) on the next V-Sync 25 - - <= LP-11 - 26 - BTA <=> BTA - Interface control change from the display module to the MCU 27 - LP-11 => - - End 10/28/2011 209 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 28 29 - - <= 30 - - <= 31 - BTA <=> 32 - LP-11 => 33 - LP-11 => 34 35 - BTA <=> 36 - - <= 37 - LP-11 => 38 - BTA <=> 39 - - <= 40 - - <= 41 - - <= 42 - BTA <=> 43 - LP-11 => Notes: 1. Lines 1 ~ 16 are needed for every frame. 2. Bit 5 and Bit 7 of the AwER are applied. LPDT LP-11 BTA - - BTA LP-11 - BTA LP-11 LPDT LP-11 BTA - AwER - - - Error Report Interface control change from the display module to the MCU If the MCU is not forcing BTA => goto line 33 If the MCU is forcing BTA => goto line 35 End - - AwER - Interface control change from the MCU to the display module Dead-Lock (No TE information) The MCU is forced to start to control the interface. The display module detects Bus Connection Error (BCE) Interface control change from the MCU to the display module Error Report (Bus Connection Error (BCE) is reported) Interface control change from the display module to the MCU End 10/28/2011 210 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Tearing Effect Bus Trigger Disable Sequence – DCSWN-S and LPDT MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSWN-S LPDT => - - Tearing Effect Bus Trigger Disable 3 - LP-11 => - - Tearing Effect Bus Trigger Disable Sequence – DCSWN-S and HSDT MCU Display Module Line Packet Sender Interface Mode Control Information Direction Interface Mode Control Packet Sender Comment 1 - LP-11 => - - Start 2 DCSWN-S HSDT => - - Tearing Effect Bus Trigger Disable 3 EoTP HSDT => - - End of Transmission Packet 4 - LP-11 => - - 10/28/2011 211 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.11 Checksum The display module consists of two 8-bit checksum registers, which are used checksum calculations for “User Command Set” area registers (includes the frame memory), on the display module. One of the checksum registers is “First Checksum” (FCS) and another is “Continue Checksum” (CCS). These register values are set to 00h as an initial value when there is started to calculate a new checksum. The display module is starting to calculate the new checksum after there is a write access on “User Command Set” area registers. This means that read commands are not used as a calculation starting trigger in this case. The checksum calculation is always interrupted, when there is a new write access on Nokia area registers. The checksum calculation is also started from the beginning. The result of the first finished checksum calculation is stored on the FCS register, which value is kept until there is the new write access on “User Command Set” area registers and the new checksum value is calculated in the first time again. The maximum time, when the FCS is readable, is 150ms after there is the last write access on “User Command Set” area registers. The checksum calculation is continuing after the finished first checksum calculation where the FCS has gotten the checksum value. These new checksum values are always stored on CCS register (Old value is replaced a new one) after the last Nokia area register has been calculated to the checksum. The maximum time, when the CCS is readable in the first time, is 300ms after there is the last write access on “User Command Set” area registers. There is always updated a checksum comparison bit (See section: “Read Display Self-Diagnostic Result (0Fh)” and bit D0) when there is compared FCS and CCS checksums after a new checksum value is stored on CCS. The maximum time, when the comparison has been done between FCS and CCS in the first time, is 300ms then the comparison has been done in every 150ms (this is maximum time). User can read FCS, CCS and Comparison bit D0 values. See section: “Read First Checksum (AAh)”, “Read Continue Checksum (AFh)” and ”Read Display Self-Diagnostic Result (0Fh)”. There can be an overflow during a checksum calculation. These overflow bits are not needed to store anywhere. This means that these overflow bits can be ignored by the display module. An example of the checksum calculation: - Register Values: A1h, 12h, 81h, DEh, F2h - Calculated Value: 304h (= A1h + 12h + 81h + DEh + F2h) - Ignored Bits: 3h - Stored Checksum: 04h This checksum calculation function is only running in “Sleep Out” mode and it is stopped in “Sleep In” mode. 10/28/2011 212 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Table 5.11.1 Checksum Sequence Step Note1 1 2 3 4 5 6 7 8 9 10 Time Note2 0 0 | 150ms 150ms 150ms | 300ms 300ms 300ms | 450ms 450ms 450 | 600ms 600ms etc Action Initialization Continue sum of “User Command Set” area registers Stores sum of registers on FCS register Continue sum of “User Command Set” area registers 1) Stores sum of registers on CCS register 2) Compares stored FCS and CCS value Continue sum of “User Command Set” area registers 1) Stores sum of registers on CCS register 2) Compares stored FCS and CCS value Continue sum of “User Command Set” area registers 1) Stores sum of registers on CCS register 2) Compares stored FCS and CCS value - Temporary Register Set to 00h Counting Set to 00h after value is moved to FCS register Counting Set to 00h after value is moved to CCS register Counting Set to 00h after value is moved to CCS register Counting Set to 00h after value is moved to CCS register - First Checksum Register (FCS) Set to 00h - Stores sum of “User Command Set” area registers on FCS register - - - - - - - Continue Checksum Register (CCS) Set to 00h - - - Stores sum of “User Command Set” area registers on CCS register - Stores sum of “User Command Set” area registers on CCS register - Stores sum of “User Command Set” area registers on CCS register - Comment The last write action on “User Command Set” area registers => FCS an CCS registers are initialized The first register counting is running The result of the first register counting is stored on FCS register. The result of the FCS is available to the MPU The second register counting is running The result of the comparison is stored on separated registers, which can read separated read commands. The result of the CCS and comparison result are available to the MPU The third register counting is running The result of the comparison is stored on separated registers, which can read separated read commands. The result of the CCS and comparison result are available to the MPU The fourth register counting is running The result of the comparison is stored on separated registers, which can read separated read commands. The result of the CCS and comparison result are available to the MPU Same sequence continue e.g. step 4 and 5 10/28/2011 213 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.12 Power On/Off Sequence VDDI and VDD (VDDA) can be applied in any order. VDD (VDDA) and VDDI can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VDD (VDDA) and VDDI must be powered down minimum 120msec after RESX has been released. During power off, if LCD is in the Sleep In mode, VDDI or VDD (VDDA) can be powered down minimum 0msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX. Notes: 1. There will be no damage to the display module if the power sequences are not met. 2. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. 3. There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. 4. If RESX line is not held stable by host during Power On Sequence as defined in Sections 5.12.1 and 5.12.2, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. 5. There is not a limit for Rise/Fall time on VDDI and VDD (VDDA). 6. The display module can also initialize and calibrate DSI-CLK+/- and DSI-D0+/- lanes within 5ms after LP-11 (Clock and Data Channels), VDDI and VDD (VDDA) are applied and H/W Reset is not active (5ms is as same as the Reset Cancelling Time). 10/28/2011 214 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.12.1 Case 1 – RESX line is held High or Unstable by Host at Power On If RESX line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDD (VDDA) and VDDI have been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset. VDDI tr PW = +/- no limit tfPW = +/- no limit VDD (VDDA=VDDR=VDDB) Time when the later signal rises up to 90% of its typical value. e.g. When VDD come later, this time is defined the cross point of 90% of 2.75V, not 90% of 2.4V. SCEX H or L RESX (Power down in Sleep Out mode) RESX (Power down in Sleep In mode) Time when the former signal falls down to 90% of its typical value. e.g. When VDD falls earlier, this time is defined the cross point of 90% of 2.75V, not 90% of 2.4V. tr PWCSX = +/- no limit tf PWCSX = +/- no limit tr PWRESX = + no limit 30% tf PWRESX1 = min. 120ms tr PWRESX = + no limit 30% tr PWRESX2 = min. 0ns tf PWRESX1 is appliedto RESX falling in the Sleep Out Mode. tf PWRESX2 is appliedto RESX falling in the Sleep In Mode. Note: Unless otherwise specified, timings herein show cross point at 50% of signal/powerlevel. 10/28/2011 215 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.12.2 Case 2 – RESX line is held Low by host at Power On If RESX line is held Low (and stable) by the host during Power On, then the RESX must be held low for minimum 10µsec after both VDD (VDDA) and VDDI have been applied. VDDI tr PW = +/- no limit tfPW = +/- no limit VDD (VDDA=VDDR=VDDB) Time when the later signal rises up to 90% of its typical value. e.g. When VDD come later, this time is defined the cross point of 90% of 2.75V, not 90% of 2.4V. SCEX H or L RESX (Power downin Sleep Out mode) RESX (Power downin Sleep In mode) Time when the former signal falls down to 90% of its typical value. e.g. When VDD falls earlier, this time is defined the cross point of 90% of 2.75V, not 90% of 2.4V. trPWCSX = +/- no limit tf PWCSX = +/- no limit tr PWRESX = min. 10 µ s tf PWRESX1 = min. 120ms tr PWRESX = min. 10 µ s tr PWRESX2 = min. 0ns tf PWRESX1 is appliedto RESX falling in the Sleep Out Mode. tf PWRESX2 is appliedto RESX falling in the Sleep In Mode. Note: Unless otherwise specified, timings herein show cross point at 50% of signal/powerlevel. 5.12.3 Uncontrolled Power Off The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an uncontrolled power off the display will go blank and there will not be any visible effects within 1 second on the display (blank display) and remains blank until “Power On Sequence” powers it up. 10/28/2011 216 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.13 Power Level Modes 5.13.1 Definition 7 level modes are defined they are in order of maximum power consumption to minimum power consumption: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 16.7M colors. 2. Partial Mode On, Idle Mode Off, Sleep Out In this mode, part of the display is used with maximum 16.7M colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode. In this mode, the DC/DC converter, internal oscillator and panel driver circuit are stopped. Only the MPU interface and registers are working with VDDI power supply. Contents of the frame memory can be safe or random. 6. Deep Standby Mode. In this mode, the DC/DC converter, internal oscillator and panel driver circuit are stopped. The MPU interface and registers are not working. Contents of the frame memory is random. 7. Power Off Mode In this mode, VDDI and VDDA/VDDR/VDDB are removed. NOTE: Transition between mode 1~5 is controllable by MPU commands. Mode 6 is entered for power saving with both power supplies for I/O and analog circuits and can be exited by hardware reset only (RESX=L). Mode 7 is entered only when both power supplies for I/O and analog circuits are removed. 10/28/2011 217 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY 5.13.2 Power Level Mode Flow Chart Commands: Normal display mode on = NORON Partial mode on = PTLON Idle mode off = IDMOFF Idle mode on = IDMON Sleep out = SLPOUT Sleep in = SLPIN Deep standby mode = DSTBON Power on sequence H/W reset S/W reset NORON PTLON Sleep out Normal display mode on Idle mode off SLPIN SLPOUT Sleep in Normal display mode on Idle mode off NORON PTLON IDMON IDMOFF IDMON IDMOFF Sleep out Normal display mode on Idle mode on SLPIN SLPOUT Sleep in Normal display mode on Idle mode on NT35510 RESX=L Deep Standby Mode On DSTBON DSTBON Sleep out Partial mode on Idle mode off IDMON IDMOFF SLPIN SLPOUT Sleep in Partial mode on Idle mode off IDMON IDMOFF PTLON NORON Sleep out Partial mode on Idle mode on SLPIN SLPOUT Sleep in Partial mode on Idle mode on Sleep out Sleep in DSTBON PTLON NORON DSTBON Sleep in Deep Standby NOTES: 1) There is not any abnormal visual effect when there is changing from one power mode to another power mode. 2) There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power mode 10/28/2011 218 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The following table represents the SRAM and Registers its mode state. Mode SRAM Register Sleep in mode 1 (RAMKP = 1) Sleep in mode 2 (RAMKP = 0) Deep-standby mode Reset=L Keep Loss Loss Loss Keep Keep Loss Keep (Default Value) Control Enter Exit Command Command Command Reset pin Reset (H/W) The condition for irregular power off mode is shown below. Power Off Mode VDD VDDI RESX I/O Mode 1 ON OFF High or Low Low Mode 2 OFF ON High or Low Low Note: VDD means VDDA, VDDR, VDDB and VDDAM. Power Off Condition VDD ON VDDI ON VDD ON VDDI OFF VDDOFF VDDION If VDDI turned off If VDD turned off Sleep-In Mode Power-OFF Mode1 Power-OFF Mode2 If VDDI turned on If VDD turned on 10/28/2011 219 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.14 Reset function 5.14.1 Register Default Value Table 5.14.1 Default Values for User Command Set Item RDNUMED (05h) RDDPM (0Ah) RDDMADCTR (0Bh) RDDCOLMOD (0Ch) RDDIM (0Dh) RDDSM (0Eh) RDDSDR (0Fh) Sleep In/Out (10h/11h) Partial/Normal Display (12h/13h) Display Inversion On/Off (21h/20h) All Pixel On/Off (23h/22h) Gamma setting (26h) Display On/Off (29h/28h) Column: Start Address (XS, 2Ah) CGM[7:0]=“70h” (480x864) Column: CGM[7:0]=“6Bh” (480x854) End Address CGM[7:0]=“50h” (480x800) (XE, 2Ah) CGM[7:0]=“28h” (480x720) CGM[7:0]=“00h” (480x640) Row: Start Address (YS, 2Bh) CGM[7:0]=“70h” (480x864) Row: CGM[7:0]=“6Bh” (480x854) End Address CGM[7:0]=“50h” (480x800) (YE, 2Bh) CGM[7:0]=“28h” (480x720) CGM[7:0]=“00h” (480x640) Frame memory (2Ch, 2Eh, 3Ch, 3Eh) Partial: Start Address (PSL, 30h) CGM[7:0]=“70h” (480x864) Partial: CGM[7:0]=“6Bh” (480x854) End Address CGM[7:0]=“50h” (480x800) (PEL, 30h) CGM[7:0]=“28h” (480x720) CGM[7:0]=“00h” (480x640) Tearing: On/Off (35h/34h) After Power On 00h 08h 00h 07h 00h 00h 00h In Normal Off Off 01h (GC0) Off 0000h 01DFh (479d) 01DFh (479d) 01DFh (479d) 01DFh (479d) 01DFh (479d) 0000h 035Fh (863d) 0355h (853d) 031Fh (799d) 02CFh (719d) 027Fh (639d) Random 0000h 035Fh (863d) 0355h (853d) 031Fh (799d) 02CFh (719d) 027Fh (639d) Off After Hardware Reset 00h 08h 00h 07h 00h 00h 00h In Normal Off Off 01h (GC0) Off 0000h 01DFh (479d) 01DFh (479d) 01DFh (479d) 01DFh (479d) 01DFh (479d) 0000h 035Fh (863d) 0355h (853d) 031Fh (799d) 02CFh (719d) 027Fh (639d) Random 0000h 035Fh (863d) 0355h (853d) 031Fh (799d) 02CFh (719d) 027Fh (639d) Off After Software Reset 00h 08h 00h 07h 00h 00h 00h In Normal Off Off 01h (GC0) Off 0000h 01DFh (479d) 01DFh (479d) 01DFh (479d) 01DFh (479d) 01DFh (479d) 0000h 035Fh (863d) 0355h (853d) 031Fh (799d) 02CFh (719d) 027Fh (639d) Random 0000h 035Fh (863d) 0355h (853d) 031Fh (799d) 02CFh (719d) 027Fh (639d) Off 10/28/2011 220 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Table 5.14.1 Default Values for User Command Set (Continuous) Item Memory Data Access Control (36h) (MY/MX/MV/ML/RGB/MH/RSMX/RSMY) Idle Mode On/Off (38h/39h) Interface Pixel Color Format (3Ah) Set Tearing Effect Scan Line (44h) Get Scan Line (45h) DSTB mode (4Fh) Profile Value for Display (50h) Display Brightness (51h, 52h) CTRL Display (53h, 54h) CABC Control (55h, 56h) Write Hysteresis (57h) Write Gamma Setting (58h) RDFSVM (5Ah) RDFSVL (5Bh) RDMFFSVM (5Ch) RDMFFSVL (5Dh) RDLSCCM (65h, 66h) RDLSCCL (65h, 67h) Black/White Color After MTP Characteristics (70h~74h) Before MTP Red/Green Color After MTP Characteristics (75h~79h) Before MTP Blue/AColor Color After MTP Characteristics (7Ah~7Eh) Before MTP DDB Start/Continue (A1h) After MTP Before MTP DDB Continue (A8h) After MTP Before MTP First/Continue Checksum (AAh, AFh) ID1 (DAh) After MTP ID2 (DBh) ID3 (DCh) Before MTP After Power On 00h Off 77h 0000h N/A 00h All values are FFh 00h 00h 00h All values are FFh All values are 11h 00h 00h 00h 00h 80h 00h MTP Value 00h MTP Value 00h MTP Value 00h MTP Value 00h MTP Value 00h 00h MTP Value ID1 = ”00h” ID2 = “80h” ID3 = “00h” After Hardware Reset 00h Off 77h 0000h N/A 00h All values are FFh 00h 00h 00h All values are FFh All values are 11h 00h 00h 00h 00h 80h 00h MTP Value 00h MTP Value 00h MTP Value 00h MTP Value 00h MTP Value 00h 00h MTP Value ID1 = ”00h” ID2 = “80h” ID3 = “00h” After Software Reset 00h Off 77h 0000h N/A 00h All values are FFh 00h 00h 00h All values are FFh All values are 11h 00h 00h 00h 00h 80h 00h MTP Value 00h MTP Value 00h MTP Value 00h MTP Value 00h MTP Value 00h 00h MTP Value ID1 = ”00h” ID2 = “80h” ID3 = “00h” 10/28/2011 221 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.14.2 Output or Bi-directional (I/O) Pins Output or Bi-directional pins After Power On After Hardware Reset After Software Reset HSSI_DATA0_P, HSSI_DATA0_N High-Z (Inactive) High-Z (Inactive) High-Z (Inactive) TE VSSI VSSI VSSI SDO Using SPI Not using SPI VDDI High-Z (Inactive) VDDI High-Z (Inactive) VDDI High-Z (Inactive) Source Driver Output High-Z (Inactive) High-Z (Inactive) High-Z (Inactive) GOUT1~GOUT32 AVSS AVSS AVSS NOTE: There will be no output from TE, SDO, D23-D0, HSSI_DATA0_P/N and HSSI_DATA1_P/N during Power On/Off sequence, H/W Reset and S/W Reset 5.14.3 Input Pins Input pins RESX CSX During Power On Process See Section 5.12 Input Invalid After Power On Input Valid Input Valid After Hardware Reset Input Valid Input Valid After Software Reset Input Valid Input Valid During Power Off Process See Section 5.12 Input Invalid D/CX Input Invalid Input Valid Input Valid Input Valid Input Invalid WRX (SCL / I2C_SDA) Input Invalid Input Valid Input Valid Input Valid Input Invalid RDX Input Invalid Input Valid Input Valid Input Valid Input Invalid D23 to D0 Input Invalid Input Valid Input Valid Input Valid Input Invalid SDI (I2C_SCL) Input Invalid Input Valid Input Valid Input Valid Input Invalid HS Input Invalid Input Valid Input Valid Input Valid Input Invalid VS Input Invalid Input Valid Input Valid Input Valid Input Invalid PCLK Input Invalid Input Valid Input Valid Input Valid Input Invalid DE HSSI_CLK_P, HSSI_CLK_N HSSI_DATA0_P, HSSI_DATA0_N HSSI_DATA1_P, HSSI_DATA1_N Input Invalid Input Invalid Input Valid Input Valid Input Invalid Input Valid Input Invalid Input Valid Input Valid Input Valid Input Valid Input Valid Input Valid Input Valid Input Invalid Input Invalid Input Valid Input Invalid Input Valid Input Invalid 10/28/2011 222 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.15 Sleep Out-Command and Self-Diagnostic Functions of the Display Module 5.15.1 Register loading Detection Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from EEPROM (or similar device) to registers of the display controller is working properly. There are compared factory values of the EEPROM and register values of the display controller by the display controller (1st step: Compares register and EEPROM values, 2nd step: Loads EEPROM value to register). If those both values (EEPROM and register values) are same, there is inverted (=increased by 1) a bit, which is defined in command “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of these commands is D7). If those both values are not same, this bit (D7) is not inverted (= not increased by 1) and the used TE-line is set to low (Registers, what are set by “Tearing Effect Line On (35h)” command, are keeping their current values) when it can be reactivated by “Tearing Effect Line On (35h)” command. The flow chart for this internal function is following: SPLIN (10h) Power On Sequence H/W reset S/W reset Sleep Out Mode Sleep In Mode SPLOUT (11h) RDDSDR's D7="0" Load values from EEPROM to register Compares EEPROM and register values TE-Line is set to low Note 2 No Are EEPROM and register values same? Yes D7 inverted NOTES: 1. There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DCh), by the display module. 2. This information is only used if TE line is used. 10/28/2011 223 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.15.2 Functionality Detection Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (e.g. booster voltage levels, timings, etc.). If functionality requirement is met, there is inverted (= increased by 1) a bit, which defined in command “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of these commands is D6). If functionality requirement is not same, this bit (D6) is not inverted (= not increased by 1) and the used TE-line ie set to low (Registers, what are set by “Tearing Effect Line On (35h)” command, are keeping their current values) when it can be reactivated by “Tearing Effect Line On (35h)” command. The flow chart for this internal function is following: SPLIN (10h) Power On Sequence H/W reset S/W reset Sleep Out Mode Sleep In Mode SPLOUT (11h) RDDSDR's D6="0" Check timing, voltage levels and other functionalities Is functionalitiy requirement met? Yes D6 inverted No TE-Line is set to low Note 2 NOTES: 1. There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to Sleep Out -mode, before there is possible to check if functionality requirements are met and a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep Out -mode. 2. This information is only used if TE line is used. 10/28/2011 224 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.15.3 Chip Attachment Detection Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if a chip or chips (e.g. driver, etc.) of the display module is/are attached to the circuit route of a flex foil or display glass ITO. There is inverted (= increased by 1) a bit, which is defined in command “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D5), if the chip or chips is/are attached to the circuit route of the flex or display glass. If this chip is or those chips are not attached to the circuit route of the flex or display glass, this bit (D5) is not inverted (= not increased by 1) and the used TE-line ie set to low (Registers, what are set by “Tearing Effect Line On (35h)” command, are keeping their current values) when it can be reactivated by “Tearing Effect Line On (35h)” command. The following figure is for reference purposes; how this chip attachment can be implemented e.g. there are connected together 2 bumps via route of ITO or the flex foil on 4 corners of the driver (chip). Bump Routing between bumps Through view of driver (or any chip) to bumps Routing between bumps Substrate or flex foil The flow chart for this internal function is following: SPLIN (10h) Power On Sequence H/W reset S/W reset Sleep Out Mode Sleep In Mode RDDSDR's D5="0" SLPOUT (11h) Checks, if chip is attached to route No Is chip attached to routes? Yes D5 Inverted TE-Line is set to low Note 2 NOTE: This information is only used if TE line is used. 10/28/2011 225 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.16 Display Panel Color Characteristics Color characteristics of the display panel are stored on the display module that they can be read via the used interface by the engine what is using this display panel color characteristics information to adjust a color information of the image frame, what is on the engine, to match a wanted color outlook of the image on the display panel. Used color characteristics can share 2 categories: Mandatory and Optional. The mandatory color characteristics are Black, White, Red, Green and Blue. The optional color characteristics is used if it is needed and it is called as A color (e.g. Cyan). The bits of the A color are set to ‘0’s they are not used on the display module. A read color characteristic value is based on 10 bit floating value where the MSB is 9th bit and the LSB is 0th bit. All power values of the bits are listed below: - Bit 9: 2-1 = 0.5, - Bit 8: 2-2 = 0.25, - Bit 7: 2-3 = 0.125, - Bit 6: 2-4 = 0.0625, - Bit 5: 2-5 = 0.03125, - Bit 4: 2-6 = 0.015625, - Bit 3: 2-7 = 0.007813, - Bit 2: 2-8 = 0.003906, - Bit 1: 2-9 = 0.001953, - Bit 0: 2-10 = 0.000977. The wanted value is an approximation in the most of the cases when there is used binary numbers. Therefore, there is used the nearest value what can get e.g. Rx can be: - Actual value: 0.6400, Stored value Rx[9:0] = 10 1000 1111b = 0.6396, - Actual value: 0.3300, Stored value Rx[9:0] = 01 0101 0010b = 0.3301, - Actual value: 0.3000, Stored value Rx[9:0] = 01 0011 0011b = 0.2998, - Actual value: 0.6000, Stored value Rx[9:0] = 10 0110 0101b = 0.5986, - Actual value: 0.1500, Stored value Rx[9:0] = 00 1001 1010b = 0.1504, - Actual value: 0.0600, Stored value Rx[9:0] = 00 0011 1101b = 0.0596, - Actual value: 0.3127, Stored value Rx[9:0] = 01 0100 0000b = 0.3125, - Actual value: 0.3290, Stored value Rx[9:0] = 01 0101 0001b = 0.3291. The value 0.6396 has calculated as follows: - Binary value: 10 1000 1111b - Formula: Rx[9]x0.5+Rx[8]x0.25+Rx[7]x0.125+Rx[6]x0.0625+Rx[5]x0.03125+Rx[4]x0.015625+ Rx[3]x0.007813+Rx[2]x0.003906+Rx[1]x0.001953+R[0]x0.000977 - Use: 1x0.5+0x0.25+1x0.125+0x0.0625+0x0.03125+0x0.015625+1x0.007813+1x0.003906+ 1x0.001953+1x0.000977 See also sections: “Read Black/White Low Bits (70h)”, “Read Bkx (71h)”, “Read Bky (72h)”, “Read Wx (73h)”, “Read Wy (74h)”, “Read Red/Green Low bits (75h)”, “Read Rx (76h)”, “Read Ry (77h)”, “Read Gx (78h)”, “Read Gy (79h)”, “Read Blue/AColor Low Bits (7Ah)”, “Read Bx (7Bh)”, “Read By (7Ch)”, “Read Ax (7Dh)”, “Read Ay (7Eh)”. 10/28/2011 226 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.17 Gamma Function The structure of grayscale amplifier is shown as below. The 26 voltage levels between VGMP and VGSP are determined by the gradient adjustment register, the reference adjustment register, the amplitude adjustment resister and the micro-adjustment register. VGMP V0 R V1 R V2 V254 R V255 R V256 R V257 R Rx1023 R R V510 V511 V512 V513 V766 R V767 R V768 R V769 V1021 R V1022 R V1023 VGSP 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 1024 to 1 V0~V1023 V0 V1 V3 V5 V7 V11 V15 V23 V31 V47 V63 V95 V127 V128 V160 V192 V208 V224 V232 V240 V244 V248 V250 V252 V254 V255 10/28/2011 227 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.18 Basic Display Mode The NT35510 has some basic operation modes which are Normal Display Mode, Partial Display Mode, Idle Mode, All Pixel On and All pixel Off for panel display. User can change these display modes for each other is illustrated below. Normal Display Mode All Pixel On NORON Normal display mode on Idle mode off ALLPON NORON All pixel on Idle mode off ALLPON Idle Off IDMON IDMOFF IDMON IDMOFF Idle On NORON Nomal display mode on Idle mode on ALLPON NORON All pixel on Idle mode on ALLPON NORON ALLPON PTLON ALLPOFF PTLON Partial mode on Idle mode on ALLPOFF PTLON All pixel off Idle mode on ALLPOFF IDMON Idle Off IDMOFF IDMON Idle On IDMOFF PTLON Partial mode on Idle mode off ALLPOFF PTLON All pixel off Idle mode off ALLPOFF Partial Display Mode All Pixel Off 10/28/2011 228 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.19 Instruction Setting Sequence When setting instruction to the NT35510, the sequences shown in below figures must be followed to complete the instruction setting. 5.19.1 Sleep In/Out Sequence Sleep Mode Sequence Display Off Sequence Sleep In Command (SLPIN 1000h) Delay 120ms or more Sleep Out Command (SLPOUT 1100h) Delay 120ms or more Display On Sequence 10/28/2011 229 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY 5.19.2 Deep Standby Mode Enter/Exit Sequence Deep Standby Mode Sequence Set Display Off (DSPOFF 2800h) Enter Sleep In Mode (SLPIN 1000h) Delay 4 frames or more Enter Deep Standby Mode (DSTBON 4F00h with bit DSTB="1") Exit Deep Standby Mode (Set RESX pin low pulse more than 3 msec) Delay 4 frames or more Initial Instruction Setting and SRAM Data Setting Display On Sequence NT35510 10/28/2011 230 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY 5.20 Instruction Setup Flow 5.20.1 Initializing with the Built-in Power Supply Circuits Initializing Start (Power ON) H/W Reset • Power Input: GND, VDDI, VDD (Any order) Wait until Power Stabilization • RESX = " L " Wait for more than 10µs • RESX = " H " Wait 4 frames or more Power Supply Set • SLPOUT (Sleep mode Off & OSC / Booster On) Wait 120ms or more Display Environment Set 2 (If not used, can be skipped) • INVON / INVOFF (Display Inversion / Normal Set) • PTLAR / PTLON / NORON (Partial Area Set & Partial On / Normal On Set) - PSL / PEL (Partial Start / End Lines Set) • MADCTL (Memory Data Access Control) - Row Direction (MY), Column Direction (MX), Row / Column Exchange (MV) - Vertical Refresh Order (ML) - Horizontal Refresh Order (MH) • COLMOD (Interface Pixel Format Set) Display Data Write & Display On • RASET / CASET (Roe / Column Address Set) - XS / XE (Start / End Column Address Set) - YS / YE (Start / End Row Address Set) • RAMWR (Memory Data Write) • DISPON (Display On) Initializing End NT35510 Fig. 5.20.1 Initializing with the built-in power supply circuit The initializing sequence does not have any effect on the display. The display is in its normal background color during the initializing. 10/28/2011 231 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 5.20.2 Power OFF Sequence PRELIMINARY Power OFF Start (Without H/W Reset) • DISPOFF (Display Off) • SLPIN (Sleep In) All the power supply circuit and oscillator circuit become off Wait 4 frames or more • Stop the Power Supply: VDDI and VDD Stop (Any Order) Power OFF End NT35510 Power OFF Start (With H/W Reset) • RESX = " L " Wait for more than 10µs • RESX = " H " • Stop the Power Supply: VDDI and VDD Stop (Any Order) Power OFF End Fig. 5.20.2 Power off sequence 10/28/2011 232 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 5.21 MTP Write Sequence PRELIMINARY Start Power on and normal display NT35510 RDMTP command Check related MTP_STUS1 bit = 0 (EF00h) MTP_STUS2 bit = 0 (EF01h) No End MTP was programmed Yes Adjust the MTP registers to optimal value * Refer command EDxxh for the related MTP registers MTP Programming MTPEN command (ED00h, ED01h) Set related MTP_EN1 bit = 1 Connect high voltage 7.75V to MTP_PWR pin MTPDET command (EC00h) Check MTP_DET bit = 1 7.75V is not connected to MTP_PWR pin No Yes MTPWR command (EE00h) Wait for more than 500 msec Remove high voltage 7.75V from MTP_PWR pin MTPEN command (ED00h, ED01h) Set all MTP_EN1 bit = 0 Set hardware reset MTP Programming Verify SLPOUT command (1100h) Read MTP registers all correct ? No Re-execute MTP Programming Sequence Yes End Note: The multi-times MTP must be programmed from the 1st time. (ID1/2/3, VGMP/VGSP, VGMN/VGSN, VCOM, Gamma 2.2, VGMP/VGSP LUT) 10/28/2011 233 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.22 Dynamic Backlight Control Function The NT35510 embedded Content Adaptive Brightness Control (CABC) and Light-Sensor Automatic Brightness Control (LABC) functions. Both two functions are used to generate a proper PWM signal based on internal CABC and LABC algorithms. User could apply this PWM signal to control other device(s) (Such as power IC or LED driver IC). The function combined CABC with LABC, is simply called “Full-ABC”. When the CABC and LABC functions are enabled and cooperate with external circuits (such as LED driver circuit), the power consumption of backlight will be reduced with keeping acceptable display quality. The CABC function of NT35510 is used to reduce the power consumption of display backlight. Contents adaptation means that the average gray level scale of image contents is increased while simultaneously lowering brightness of the backlight to achieve same perceived brightness. The adjusted gray level scale and thus power consumption reduction depends on the contents of the image. The display image and brightness are dynamically processed by CABC block. The availability of this function ranges from moving picture such as TV image to still picture such as menu. However, in order to gain a better display quality and reduce the power consumption of the backlight, the NT35510 internally uses NOVATEK dynamic gamma algorithm to produce an optimal backlight control based on different image contents. The LABC function of NT35510 is also applied to smoothly control the display backlight by sensing ambient light variation. This function includes several apparatus, such as “Flicker Removal Block” for eliminating external light source flicker (e.g. 50 and 60 Hz), and “Hysteresis Block” for preventing the luminance transient variation. The information of the ambient light is sent to the LABC block if user enables it. The user can read ambient light information or this information can be used for automatic brightness control by the LABC block. It is also available to control the brightness by adjusting PWM duty manually. So combined the CABC with LABC processed results, the display output brightness is: Display Backlight Brightness = LABC Backlight Brightness Ratio (or Manual Setting Ratio) x CABC Brightness Ratio Table 5.22.1 Display Brightness Output When CABC and LABC Function are Enable Example Example 1 Example 2 Example 3 A Brightness Ratio (LABC or Manual) 70% 80% 50% B Brightness Ratio (CABC or Manual) AxB Calculation Result Brightness Output of LEDPWM 50% 35% 35% 100% 80% 80% 30% 15% 15% Image Status CABC Modified CABC Modified CABC Modified 10/28/2011 234 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 One of Full-ABC applications is simply illustrated in the Fig. 5.22.1. This application is used to dynamic control the backlight power consumption. The LEDPWM is an output-type pin which can output a PWM signal to control the display backlight brightness. The “LEDON” pin can output a “Enable / Disable” signal if the external LED driver IC needs this signal. The PWM duty cycle of “LEDPWM” is determined by CABC and LABC processed results. The external LED driver ICs are necessary in order to transfer the PWM signal into driving power for LED backlight. External A/D Converter or Other Circuit Ambient Light Sensor HOST Image Data Image Histogram Analysis NVT Full-ABC Block Dynamic Backlight Control Block ( CABC + LABC Control ) PWM Duty Generation LED_PWM LED_ON LED Driver ( For Display Backlight ) LED Backlight for Display Fig. 5.22.1 One Application of Full-ABC Dynamic Backlight Brightness Control 10/28/2011 235 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.22.1 PWM Control Architecture PWM duty for LED backlight control is determined from CABC and LABC block. The below diagram illustrates the duty combination architecture and its corresponding control registers. DBV[7 : 0] (WRDISBV) LABC PWM A DB CABC PWM FORCE_CABC_DUTY[7 : 0] FORCE_CABC_PWM BCTRL Value: 0x00 0 1 0 1 RDPWM_L[7 : 0] RDPWM[7 : 0] 0 1 X PWM_DUTY_OFFSET[4 : 0] Minimum Brightness Constrain (WRCABCMB]) Several registers for dimming setting Internal Display Backlight Control + Value: 0x00 Dimming Function of ABC / Manual Brightness Control Sleep-Out Several registers for setting this block 0 1 DBV[7 : 0] (RDDISBV) BL LEDONR LEDONPOL Sleep-Out BL PWM Signal Generator for LEDPWM LEDPWPOL CLED_VOL LEDPWM_OEB CLED_VOL 0: Active high(Default) 1: Active low 0: Normal use(Default) 1: LEDPWM set Hi-Z Buffer Buffer LEDPWM LEDON Fig. 5.22.2 Internal Display Backlight Control Combined with CABC and LABC 10/28/2011 236 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 As shown in Fig. 5.22.2, the register bit “BL” is used to control the “LEDPWM” pin to output PWM signal. Normally, if user want to disable the display backlight completely and immediately, user can set “BL” = “0”. The below table shows some applications of register bit “LEDPWPOL”: BL LEDPWPOL Status of LEDPWM Pin Display Backlight Status 0 0 0 (Default) Off 0 1 1 Off 1 0 Original polarity of PWM signal On 1 1 Inversed polarity of PWM signal On In the same way, the register bits “LEDONPOL” and “BL”, are used to control the “LEDON” pin. See the below table. BL LEDONPOL Status of LEDON Pin 0 0 0 (Default) 0 1 1 1 0 LEDONR 1 1 Inversed LEDONR The setting bit “CLED_VOL” is applied to choose different output logical voltage level for LEDON, LEDPWM pins. This bit is valid when (1) DSTB_DEL=low or (2) DSTB_SEL=high, VDDI=1.65~3.3V and VSEL=high (The output level is VSSI to DIOPWR for other VDDI and VSEL conditions in DSTB_SEL=high). See below for the selection output level. CLED_VOL LEDON/LEDPWM Output Level 0 VSSI to VDDI 1 VSSI to VDDA The setting bit “BCTRL” is used to enable / disable the display backlight control functions (such as LEDPWM). When user set “BCTRL” = “0”, then the backlight will be turned off with dimming function, and the value of register DBV[7:0] (RDDISBV) will be “00h” after dimming period. BCTRL Value of DBV[7:0] (RDDISBV) Display Backlight Status 0 00h Off 1 Determined by CABC and LABC estimations On 10/28/2011 237 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The setting bit “A” is used to enable / disable the ambient light sensor and LABC functions. Sampling of ambient light started after setting the register bit “A”. First averaged value should be output for 500ms. The below table shows this function. Diver IC State A The Statue of DB ADC_EN Internal A/D Converter Display Brightness Control Sleep-In xx x Disabled Disable Sleep-Out 00 0 Disable Control by manual setting DBV[7:0] (Here means from WRDISBV) Sleep-Out 00 1 Disable Control by manual setting DBV[7:0] (Here means from WRDISBV) Sleep-Out 01 0 Disable Control by manual setting DBV[7:0] (Here means from WRDISBV) Sleep-Out 01 1 Disable Control by manual setting DBV[7:0] (Here means from WRDISBV) Sleep-Out 10 0 Disable Control by manual setting DBV[7:0] (Here means from WRDISBV) Sleep-Out 10 1 Disable Control by manual setting DBV[7:0] (Here means from WRDISBV) Sleep-Out 11 0 Disable Control by LABC function (See Note 1) Sleep-Out 11 1 Enable Control by LABC function (See Note 2) NOTES: 1. User has to write the ambient light information into the register LS[15:0] via system interface.. 2. The internal 10-bit ADC converter is enabled and the display backlight brightness is controlled automatically. 10/28/2011 238 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The setting bit “DB” is used to manual / automatic brightness control. When “DB”=”0”, the display backlight brightness can be affected by setting register DBV[7:0] (here means WRDISBV) manually. Here are listed some important applications with register bits “DB”, “A”, DBV[7:0] (WRDISBV), RDPWM[7:0], and RDPWM_L[7:0] in below table. CABC Status: Off Mode (RDPWM[7:0] will be FFh) “FORCE_CABC_PWM”=“0”, WRCABCMB[7:0] = 00h, PWM_DUTY_OFFSET[4:0]=00h, “BL”=“1”, “BCTRL”=“1”, Sleep-Out Mode DB A Value of RDPWM_L[7:0] Value of RDPWM [7:0] Display Backlight Brightness Determined by DBV[7:0] 0 0 FFh (Here means from WRDISBV) Determined by DBV[7:0] manually (Here means from WRDISBV) Determined by DBV[7:0] 0 1 FFh (Here means from WRDISBV) Determined by DBV[7:0] manually (Here means from WRDISBV) Determined by DBV[7:0] 1 0 FFh (Here means from WRDISBV) Determined by DBV[7:0] manually (Here means from WRDISBV) 1 1 Determined by LABC Function FFh Determined by LABC Function CABC Status: UI-Mode / Still-Mode / Moving-Mode “FORCE_CABC_PWM” = “0”, WRCABCMB[7:0]=00h, PWM_DUTY_OFFSET[4:0]=00h, “BL”=“1”, “BCTRL”=“1”, Sleep-Out Mode DB A Value of RDPWM_L[7: 0] Value of RDPWM [7: 0] Display Backlight Brightness Determined by DBV[7:0] 0 0 (Here means from WRDISBV) Determined by CABC Function Determined by DBV[7:0] x CABC Function (Here means DBV[7:0] from WRDISBV) Determined by DBV[7:0] 0 1 (Here means from WRDISBV) Determined by CABC Function Determined by DBV[7:0] x CABC Function (Here means DBV[7:0] from WRDISBV) Determined by DBV[7:0] 1 0 (Here means from WRDISBV) Determined by CABC Function Determined by DBV[7:0] x CABC Function (Here means DBV[7:0] from WRDISBV) 1 1 Determined by LABC Function Determined by CABC Function Determined by LABC Function x CABC Function 10/28/2011 239 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Writing the register DBV[7:0] (WRDISBV) in command address 5100h (51h for MIPI command address) is used o adjust the backlight brightness value when LABC function of the NT35510 is disabled (LABC function is disabled when register bit “A” is set as “0”). However, reading register DBV[7:0] (RDDISBV) from command address 5200h (52h for MIPI command address) is used to indicate the real PWM duty variation. The register setting CMB[7:0] is used to limit the minimum PWM duty in order to prevent the backlight brightness too dark. The register FORCE_CABC_DUTY[7:0] is used to perform a fixed PWM duty of CABC output while the register bit “FORCE_CABC_PWM” is set as “1”. The “Sleep-Out” is a flag in order to indicate the driver IC is in “Sleep-Out” mode. Here are listed some conditions when driver IC is in Sleep-In or Sleep-Out status. Driver IC Status Sleep-Out Flag CABC Function LABC Function Dimming Functions for CABC or LABC Display Backlight Status Sleep-In 0 Not Available Not Available Not Available Turn-Off Sleep-Out 1 Available Available Available Controllable The NT35510 provides one dimming function for CABC and LABC / Manual Brightness Control, and this dimming functions can be enabled / disabled by register bit DD as the following table. Enable Control for CABC Dimming Function Enable Control for LABC Dimming Function “DD” = “0” Disable Dimming Function of CABC “DD” = “0” Disable Dimming Function of LABC “DD” = “1” Enable Dimming Function of CABC “DD” = “1” Enable Dimming Function of LABC In other words, the dimming functions of CABC and LABC can be enabled / disabled together by setting register bit “DD”. 10/28/2011 240 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.22.2 Dimming Function for LABC and Manual Brightness Control A dimming function (how fast to change the brightness from old to new level and what are brightness levels during the change) is used when changing from one brightness level to another. The dimming function curves for LABC and Manual Brightness Control can be configured the same or not the same in increment and decrement directions. The basic idea is described below. Luminance DBV[7:0] Set Up Luminance Dimming Time Without Dimming Time With Dimming Fig. 5.22.3 Basic Concept of Dimming Function The NT35510 provides two types PWM duty dimming mechanism for LABC and manual brightness control. One is called “Fixed-Time Dimming”, the other is called “Fixed-Slope Dimming”. The dimming type can be selected by register bit “SEL_IN” for rising dimming (increment dimming), and bit “SEL_DE” for falling dimming (decrement dimming). SEL_IN SEL_DE Rising Dimming Type Falling Dimming Type 0 0 Fixed-Time Dimming Fixed-Time Dimming 0 1 Fixed-Time Dimming Fixed-Slope Dimming 1 0 Fixed-Slope Dimming Fixed-Time Dimming 1 1 Fixed-Slope Dimming Fixed-Slope Dimming 10/28/2011 241 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Fixed-Time Dimming Type The total dimming steps and each step time can be set by registers DMSTP_L[2:0], DM_IN[3:0], and DM_DE[3:0], respectively. These three registers can determine some characteristics of dimming curves. The Fig. 5.22.4 illustrates the “Fixed-Time” dimming curves. The unit of registers DM_IN[3:0] and DM_DE[3:0] is “frame(s) per step”. The unit of register DMSTP_L[2:0] is “step(s)” For Example: If register bits “SEL_IN” = “0” (Fixed-Time dimming for rising dimming), another register bit “SEL_DE” = “1” (Fixed-Slope dimming for falling dimming), and DM_IN[3:0] is set as 0x07 (means 8 frames time for each step) DMSTP_L[2:0] is set as 0x01 (means total dimming steps is 4 steps) So the total dimming time of “rising dimming” is 32-frames time length (8 frames x 4). Fig. 5.22.4 Fixed-Time Dimming Curve for LEDPWM 10/28/2011 242 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Fixed-Slope Dimming Type The increasing / decreasing PWM duty and each step time can be set by register STEP_IN[3:0], STEP_DE[3:0], DM_IN[3:0], and DM_DE[3:0], respectively. These three registers can determine some characteristics of dimming curves. The Fig. 5.22.5 illustrates the “Fixed-Slope” dimming curves. The unit of registers STEP_IN[3:0] and STEP_DE [3:0] is “duty ratio” (FFh is 100%, and 00h is 0%). The unit of register DM_IN[3:0] and DM_DE[3:0] is “frame(s) per step”. For Example: If register bits “SEL_IN” = “0” (Fixed-Time dimming for rising dimming), another register bit “SEL_DE” = “1” (Fixed-Slope dimming for falling dimming), and DM_DE[3:0] is set as 0x02 (means 3 frames time for each step) STEP_DE[3:0] is set as 0x05 (means PWM decrement is 5) When present PWM duty is 0x64 (100 in decimal), target PWM duty is 0x14 (20 in decimal), so the total dimming steps will be: Total dimming steps = (Present PWM Duty - Target PWM duty) / (PWM decrement) = (100 - 20) / 5 = 16 steps So total dimming time for falling dimming is 48 frames (16 Steps x 3) PWM Duty (%) PWM Duty (%) Fig. 5.22.5 Fixed-Slope Dimming Curve for LEDPWM 10/28/2011 243 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.22.3 Dimming Function for CABC and Force PWM Function The NT35510 provides “Fixed-Time” and “Fixed-Slope” dimming function for CABC and Force PWM Function. The “Fixed-Slope” dimming for all CABC mode and the “Fixed-Time” dimming for CABC Still-Mode/UI-Mode use the same registers as LABC for setting (refer to Fig. 5.22.5 and Fig. 5.22.4). The Fig. 5.22.6 and Fig. 5.22.7 illustrate the “Fixed-Time” dimming curves for CABC Still-Mode and Moving-Mode respectively. Dimming Type CABC Mode Registers for Rising Dimming Setting Registers for Falling Dimming Setting Fixed-Slope All Modes STEP_IN[3:0] and DM_IN[3:0] STEP_DE[3:0] and DM_DE[3:0] Fixed-Time Off-Mode DIM_STEP_OFF[2:0] and DM_IN[3:0] DIM_STEP_OFF[2:0] and DM_DE[3:0] Fixed-Time UI-Mode DIM_STEP_STILL[2:0] and DM_IN[3:0] DIM_STEP_STILL[2:0] and DM_DE[3:0] Fixed-Time Still-Mode DIM_STEP_STILL[2:0] and DM_IN[3:0] DIM_STEP_STILL[2:0] and DM_DE[3:0] Fixed-Time Moving-Mode DIM_STEP_MOV[2:0] and DM_IN[3:0] DIM_STEP_MOV[2:0] and DM_DE[3:0] Rising Dimming Total rising steps are determined by DIM_STEP_STILL[2:0] Target PWM Duty Falling Diming Total falling steps are determined by DIM_STEP_STILL[3:0] Present PWM Duty PWM Duty (%) PWM Duty (%) …… …… Present PWM Duty DM_IN[3:0] Time (Unit: Framee) Target PWM Duty DM_DE[3:0] Time (Unit: Frame) Fig. 5.22.6 Dimming Mechanism in CABC Still-Mode Rising Dimming Total rising steps are determined by DIM_STEP_MOV[2:0] Target PWM Duty Falling Diming Total falling steps are determined by DIM_STEP_MOV[3:0] Present PWM Duty PWM Duty (%) PWM Duty (%) …… …… Present PWM Duty DM_IN[3:0] Time (Unit: Framee) Target PWM Duty DM_DE[3:0] Time (Unit: Frame) Fig. 5.22.7 Dimming Mechanism in CABC Moving-Mode 10/28/2011 244 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.22.4 PWM Signal Setting for CABC and LABC The registers PWMDIV[7:0] and PWM_DUTY_OFFSET[4:0] can change the frequency and duty compensation of the PWM signal. The PWM operation frequency “FOSC” is “not” the real PWM frequency, the “FOSC” is used to provide clock source for the internal PWM circuit. Two PWM operation frequency can be chosen by setting register “PWMF”, and the real PWM frequency can be quickly estimated by the bellow formula. PWMF Setting PWM Operation Frequency (FOSC) Real PWM Frequency of LEDPWM 0 5 MHz PWM Frequency  5 MHz 256 PWMDIV[7 : 0] 1 10 MHz PWM Frequency  10 MHz 256  PWMDIV[7 : 0] For Example: If the “PWMDIV[7:0]” = 0x0F, and “PWMF” = “1”, then PWM Frequency  10 MHz  10 MHz  2.60 KHZ 256  PWMDIV[7 : 0] 256 15 In this condition, when PWM duty is estimated as “4” (Reading the register “DBV[7:0]” = 03h from RDDISBV), then the duty time of the PWM signal can be estimated as shown in below. PWM Duty Time  4  1  6.0 μsec 256 2.60 KHz PWM Non - Duty Time  (256  4)  1  378.6 μsec 256 2.60 KHz Duty Time = 6.0 µsec ON Duty Time = 6.0 µsec Non-duty Time = 378.6 µsec PWM Signal of LEDPWM Pin ……… OFF Time The same, when PWM frequency is 2.60 KHz, and PWM duty of LEDPWM is 256 (Reading the register “DBV[7:0]” = FFh from RDDISBV), then the duty time can be estimated as shown in below. PWM Duty Time  256  1  384.6 μsec 256 2.60 KHz 10/28/2011 245 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Because the external LED driver needs some stable time to drive the LED backlight, this necessary stable time will reduce the effective PWM duty period, so the PWM_DUTY_OFFSET[4:0] is used to compensate effective PWM duty. An example is shown in Fig. 5.22.8. When PWM duty of LEDPWM signal is 60%, the backlight brightness should be 60% of original. But user may find that the backlight brightness is 57% of original. So user can set PWM_DUTY_OFFSET[4:0] and let the backlight brightness becomes 60% of original. 60% 57% PWM_DUTYP_WOMF_FDSUETTY[4_:O0F]F=SnEoTn[4-z:e0ro] =va0lue 60% PWM Duty Ratio (%) Fig. 5.22.8 Duty Compensation of PWMLED Signal NOTE: The rising time (Tr) and falling time (Tf) of the “LEDPWM” signal are stipulated to be equal to or less than 15ns when maximum load is 30pF. 10/28/2011 246 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.22.5 Content Adaptive Brightness Control (CABC) A Content Adaptive Brightness Control (CABC) function can be used to reduce the power consumption of the luminance source. Content adaptation means that content grey level scale can be increased while simultaneously decreasing brightness of the backlight to achieve same perceived brightness. The adjusted grey level scale and thus the power consumption reduction depend on the content of the image. The NOVATek CABC algorithm can adjust the brightness of each gray level without changing the original image contents. The NOVATek CABC function provides four operation modes, and these modes can be selected by the register 5500h. See command “Write Content Adaptive Brightness Control (5500h)” (bit C[1:0]) for more information. These four modes are described as below. - Off Mode Content Adaptive Brightness Control functionality is completely turn-off. In this mode, the NT35510 will use the original Gamma 2.2 registers setting for display. And if the function of “forced PWM duty” is turn-off (i.e. “FORCE_CABC_PWM” is set as “0”), the brightness ratio of CABC is 100% (“RDPWM[7:0]” = FFh). - UI [User interface] Image Mode (UI-Mode) This mode is applied to optimize for UI image. It is kept image quality as much as possible. Target power consumption reduction ratio is 10% or less. NT35510 provides flexible configuration for UI-Mode by setting the registers CABC_UI_PWM0[7:0] ~ CABC_UI_PWM3[7:0] to setting prefer brightness. - Still Picture Mode (Still-Mode) This mode is used to gain a better display quality for still picture. Some image quality degradation would be acceptable. Ideal power consumption reduction ratio is more than 30%. The NT35510 will automatically estimate a better gamma setting and PWM duty based on different image contents, so the reduction ratio of the power consumption of backlight is not a constant ratio, this ratio will vary between 10% ~ 40% with different image contents. - Moving Image Mode (Moving-Mode) User can select this mode to keep the moving image quality and reduce the power consumption of backlight. It is focused on the biggest power reduction with image quality degradation. Idea power consumption reduction ratio is more than 30%. 10/28/2011 247 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, Version 0.8 NT35510 248 Fig. 5.22.9 LABC Architecture 5.22.6 Ambient Light Sensor and Automatic Brightness Control (LABC) The LABC function of NT35510, includes several function blocks and illustrated in below diagram. PRELIMINARY External Ambient Light Sensor External A/D Converter or Other Circuit Through Interface Internal LABC Block G bit (Register 53h (5300h)) Read ALSV[15 : 0] bit MFR_BYS bit SW1 LS[15 : 0] bit Flicker Removed × CC[15 : 0] bit SW2 Read FSV[15 : 0] bit GMASET Register 26h (2600h) 0 GC[7 : 0] HYST_EN bit SET_HYST bit HYST_OUT_VAL[3 : 0] bit Median Filter Hysteresis SW3 1 1 0 Gamma Profile Selection 1 Register 58h (5800h ~ 5807h) G01[3 : 0] bit G02[3 : 0] bit : : G16[3 : 0] bit V01[7 : 0] bit V02[7 : 0] bit : : V16[7 : 0] bit Read FFSV[15 : 0] bit 0 Display Profiles HYST_WR[3 : 0] bit Read RD_HYST_OUT[3 : 0] bit RD_GMA_SET For Selecting Gamma LABC PWM SWn SWn Switch is “ opened” (Not conductive!) Switch is “ closed” (Conductive!) GMA_SET 0x01 0x02 0x04 0x08 Gamma Curves Selection Gamma 2.2 Gamma 1.8 Gamma 2.5 Gamma 1.0 information. 10/28/2011 PRELIMINARY NT35510 5.22.6.1 50/60HZ FLICKER REMOVAL Ambient Light from Front Side is measuring white spectrum. These measured values are used as an input for “50/60 Hz flicker removal” block. “50/60 Hz flicker removal” block converts sensor values from analog to a digital if needed. Same block is for filtering external light source flicker (e.g. 50Hz and 60 Hz), which maybe present in ambient light source measurements. This functionality is possible to implement with e.g. an averaging filter, 10 samples with 220Hz sampling frequency. These samples are pipelined so that the oldest value is dropped out when a new value is entered (First In- First Out queue). Sampling of ambient light is started after receiving “Write CTRL Display (5300h)” command with applicable parameters. First averaged value is outputted for 500ms. It is copied to all registers for median filter. Luminance from sensor before it is filterd Ambient light flickering, which should be filtered Luminance from sensor after it is filterd Time Time 10/28/2011 249 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.22.6.2 LIGHT GUIDE COMPENSATION Filtered luminance value is inputted into “Apply calibration and light guide compensation” block. “Apply calibration and light guide compensation” block is to calibrate measured luminance and to compensate variation of light guide which is covered on the ambient light sensor. Compensated luminance value can be read by the user (16 bit value, see chapters: “Read MSBs of FSV Value (5A00h)” and Read LSBs of FSV Value (5B00h)” without a delay at any time. This doesn’t apply 120ms for SW / HW reset wait time and 500 ms for activated Ambient light sensing with “Write CTRL Display (5300h)” command after power on sequence. First measurement is started after the command. This means that display module must apply flicker removal, calibration and compensation into measured values within 500 ms after the activation. 500ms is the maximum sampling time of the ambient light (the same meaning as median filter input). Output is applied flicker removal, calibration and compensation. 5.22.6.3 MEDIAN FILTER Filtered luminance value is inputted into “Apply calibration and light guide compensation” block. “Apply calibration and light guide compensation” block is to calibrate measured luminance and to compensate variation of light guide which is covered on the ambient light sensor. Compensated luminance value can be read by the user (16 bit value, see chapters: “Read MSBs of FSV Value (5A00h)” and Read LSBs of FSV Value (5B00h)” without a delay at any time. This doesn’t apply 120ms for SW / HW reset wait time and 500 ms for activated Ambient light sensing with “Write CTRL Display (5300h)” command after power on sequence. First measurement is started after the command. This means that display module must apply flicker removal, calibration and compensation into measured values within 500 ms after the activation. 500ms is the maximum sampling time of the ambient light (the same meaning as median filter input). Output is applied flicker removal, calibration and compensation. Read Luminance Value Samples on the queue at n+15 Samples on the queue at n+14 Samples on the queue at n+13 65535 Samples on the queue at n+12 Time n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n+15 10/28/2011 250 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Luminance values of this example are defined on the following table. Time Read Luminance Value (0 – 65535) Time Read Luminance Value (0 – 65535) n 40960 n+8 53760 n+1 30720 n+9 40960 n+2 64000 n+10 38400 n+3 32768 n+11 51200 n+4 62720 n+12 47360 n+5 47360 n+13 51200 n+6 51200 n+14 58880 n+7 58880 n+15 53760 Queues (Read Luminance Values) of this example are defined below. An Example: Read Queued Luminance Values Time / Values of Queue Queue 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th n+6 40960 30720 64000 32768 62720 47360 51200 58880 53760 40960 38400 51200 47360 n+7 30720 64000 32768 62720 47360 51200 58880 53760 40960 38400 51200 47360 51200 n+8 64000 32768 62720 47360 51200 58880 53760 40960 38400 51200 47360 51200 58880 n+9 32768 62720 47360 51200 58880 53760 40960 38400 51200 47360 51200 58880 53760 The median filter will sort these values (Read Luminance Values) in ascending order. Sorted example values are as fellows. An Example: Sorted Queued Luminance Values Sorted Values in the Order of Magnitude Time 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th n+6 30720 32768 38400 40960 40960 47360 47360 51200 51200 53760 58880 62720 64000 n+7 30720 32768 38400 40960 47360 47360 51200 51200 51200 53760 58880 62720 64000 n+8 32768 38400 40960 47360 47360 51200 51200 51200 53760 58880 58880 62720 64000 n+9 32768 38400 40960 47360 47360 51200 51200 51200 53760 53760 58880 58880 62720 The median filter selects one of those values based on order of magnitude. Selected value is the 7th value (values highlighted on the table). 10/28/2011 251 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.22.6.4 HYTERESIS Hysteresis defines when to change between brightness values. Different values are used to define increment and decrement limits. The user can program these steps, see “Write Hysteresis (5700h)”, and “Write Profile Values for Display (5000h)”. For each step number “n”, the following values are required: • An 8-bit value (Vnn[7:0]) which sets the display brightness. • A 16-bit value (Inn[15:0]) “increment step” value. If the output value of the median filter is greater than the previous one, then the Inn values represent the transition from the step “n” to step “n + 1”. •A 16-bit value (Dnn[15:0]) “decrement step” value. If the output value of the median filter is smaller than the previous one, then the Dnn values represent the transition from the step “n” to step “n + 1”. • An 4-bit value (Gnn[3:0]) “gamma curve select” value. This uses 1-hot encoding to select which gamma curve will be used for each step. • Maximum step number (n) is 16. The bellow diagram shows a graph of hysteresis input value vs. display backlight output for an arbitrary hysteresis curve. For this graph, step 12 is before the last step in the current profile, and so doesn’t have any increment or decrement step values associated with it. Gamma G1 G2 G3 Curve (Gnn[3:0]) 255 V12 G12 G13 Brightness (Vnn[7:0]) G16[3:0] V11 V4 V3 V2 V1 0 D1 I1 D2 I2 D3 I3 D11 I11 Hysteresis Input (Inn[15:0], Dnn[15:0]) D12 I12 65535 NOTE: For the last step both increment and decrement values are set to 65535 (FFFFh). E.g. D13 and I13 are set to 65535 (FFFFh) in the case of the below diagram. 10/28/2011 252 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 This curve can be split into two separate cases, one for increasing input, and one for decreasing input. Once the hysteresis is known to be increasing or decreasing, the diagram shown in above can be separated into the two curves. Once the correct graph is chosen, it is relatively simple to go through each of the levels in turn, checking against the increment or decrement values as necessary. The following table is specified the relationship between each parameters and step number using 6 steps (6 increment and 6 decrement) for hysteresis 6. Example: Relationship between each parameters, steps and hysteresis. Step Number (n) Increment Value (Inn) Decrement Value (Dnn) Display Brightness (Vnn) 1 3840 (F00h) 2560 (A00h) 20 (14h) 2 16896 (4200h) 14336 (3800h) 40 (28h) 3 25600 (6400h) 20480 (5000h) 80 (50h) 4 35840 (8C00h) 33280 (8200h) 130 (82h) 5 48896 (BF00h) 43776 (AB00h) 200 (C8h) 6 65535 (FFFFh) 65535 (FFFFh) 0 7 x x x 8 x x x 9 x x x 10 x x x 11 x x x 12 x x x 13 x x x 14 x x x 15 x x x 16 x x x Step number of increment-value and decrement-value is 16 steps. Don’t care about the parameter values after “65535 (FFFFh)” of increment value and decrement value, e.g. “x” in the above table. The 16th increment and decrement values are always set to “65535 (FFFFh)” internally, if increment and decrement values before 16th parameters are less than “65535 (FFFFh)”. Once the hysteresis curve has been stored using the commands above, the flowchart is used to select the correct hysteresis level after getting median filter output as a reference. Supplier can decide the sequence. 10/28/2011 253 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Once the hysteresis curve has been stored using the commands above, the flowchart is used to select the correct hysteresis level after getting median filter output as a reference. Supplier can decide the sequence. Median Filter Output "Equal to" Median Filter Output is ... than the "last output" register value? "smaller than" Keep the same brightness "bigger than" Step number n = 1 Step number n = 1 Median Filter Output is larger No than increment step value In? Yes n=n+1 Median Filter Output is larger No than decrement step value Dn? Yes n=n+1 No Keep the same brightness The "n" is larger than the "last output step n" The "n" is smaller than the "last output step n" Yes Yes "Display Brightness" register value is set to "Display Brightness Vnn[7:0]" value "Gamma Curve" register value is set to "Gamma Curve Gnn[3:0]" value "Last Output" register value is set to "Median Filter Output" value No Keep the same brightness Display brightness and gamma curve are changed 10/28/2011 254 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 5.23 Column, 1-Dot, 2-Dot, 3-Dot and 4-Dot Inversion (VCOM DC Drive) The NT35510, in addition to the frame-inversion liquid crystal drive, supports the column, 1–dot, 2-dot, 3-dot and 4-dot inversion driving methods to invert the polarity of liquid crystal. The column, 1–dot, 2-dot, 3-dot and 4-dot inversion can provide a solution for improving display quality. In determining the inversion drive for the inversion cycle, check the quality of display on the liquid crystal panel. Note that setting 1-dot inversion will raise the frequency of the liquid crystal polarity inversion and increase the charging/discharging current on liquid crystal cells. 10/28/2011 255 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 6 COMMAND DESCRIPTIONS 6.1 User Command Set Table 6.1.1 User Command Set Address Parameter Instruction ACT R/W MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 Function NOP Dir W 00h 0000h SWRESET Cnd1 W 01h 0100h 0400h RDDID Dir R 04h 0401h 0402h RDNUMED Dir R 05h X RDDPM Dir R 0Ah 0A00h RDDMADCTL Dir R 0Bh 0B00h RDDCOLMOD Dir R 0Ch 0C00h RDDIM Dir R 0Dh 0D00h RDDSM Dir R 0Eh 0E00h RDDSDR Dir R 0Fh 0F00h SLPIN DVS W 10h 1000h SLPOUT Dir W 11h 1100h PTLON DVS W 12h 1200h NORON DVS W 13h 1300h INVOFF DVS W 20h 2000h INVON DVS W 21h 2100h ALLPOFF DVS W 22h 2200h ALLPON DVS W 23h 2300h GAMSET DVS W 26h 2600h DISPOFF DVS W 28h 2800h DISPON DVS W 29h 2900h 2A00h CASET 2A01h Dir W 2Ah 2A02h 2A03h 2B00h RASET 2B01h Dir W 2Bh 2B02h 2B03h RAMWR Dir W 2Ch X RAMRD Dir R 2Eh 2E00h 3000h PTLAR 3001h DVS W 30h 3002h 3003h TEOFF DVS W 34h 3400h TEON DVS W 35h 3500h MADCTL Cnd2 W 36h 3600h IDMOFF DVS W 38h 3800h IDMON DVS W 39h 3900h No Argument (0000h in MDDI I/F) No Operation No Argument (0000h in MDDI I/F) Software reset 00h ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 Read display ID 00h ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 00h ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 X P7 P6 P5 P4 P3 P2 P1 P0 Read No. of the Errors on DSI only 00h D7 D6 D5 D4 D3 D2 D1 D0 Read Display Power Mode 00h D7 D6 D5 D4 D3 D2 D1 D0 Read Display MADCTR 00h D7 D6 D5 D4 D3 D2 D1 D0 Read Display Pixel Format 00h D7 D6 D5 D4 D3 D2 D1 D0 Read Display Image Mode 00h D7 D6 D5 D4 D3 D2 D1 D0 Read Display Signal Mode 00h D7 D6 D5 D4 D3 D2 D1 D0 Read Display Self-diagnostic result No Argument (0000h in MDDI I/F) Sleep in & booster off No Argument (0000h in MDDI I/F) Sleep out & booster on No Argument (0000h in MDDI I/F) Partial mode on No Argument (0000h in MDDI I/F) Partial off (Normal) No Argument (0000h in MDDI I/F) Display inversion off (normal) No Argument (0000h in MDDI I/F) Display inversion on No Argument (0000h in MDDI I/F) All pixel off (black) No Argument (0000h in MDDI I/F) All pixel on (white) 00h GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0 Gamma curve select No Argument (0000h in MDDI I/F) Display off No Argument (0000h in MDDI I/F) Display on 00h XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS8 Column address set XS[15:0]: column start address 00h XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 XE[15:0]: column end address 00h XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE8 00h XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0 00h YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS8 Row address set YS[15:0]: row start address 00h YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 YE[15:0]: row end address 00h YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE8 00h YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 X D7 D6 D5 D4 D3 D2 D1 D0 Memory write 00h D7 D6 D5 D4 D3 D2 D1 D0 Memory read 00h PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8 Partial start/end address set PSL[15:0]: partial start address 00h PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 PEL[15:0]: partial end address 00h PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8 00h PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 No Argument (0000h in MDDI I/F) Tearing effect line off 00h - - - - - - - M Tearing effect mode set & on 00h MY MX MV ML RGB MH RSMX RSMY Memory data access control No Argument (0000h in MDDI I/F) Idle mode off No Argument (0000h in MDDI I/F) Idle mode on 10/28/2011 256 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Table 6.1.1 User Command Set (Continued) Instruction ACT R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 Function COLMOD Dir W 3Ah 3A00h 00h VIPF3 VIPF2 VIPF1 VIPF0 IFPF3 IFPF2 IFPF1 IFPF0 Interface pixel format RAMWRC Dir W 3Ch 3C00h 00h D7 D6 D5 D4 D3 D2 D1 D0 Memory write Continue RAMRDC Dir R 3Eh 3C00h 00h D7 D6 D5 D4 D3 D2 D1 D0 Memory read Continue STESL 4400h DVS W 44h 4401h 00h N15 N14 N13 N12 N11 N10 N9 N8 Set tearing effect scan line 00h N7 N6 N5 N4 N3 N2 N1 N0 4500h GSL Dir R 45h 4501h 00h N15 N14 N13 N12 N11 N10 N9 N8 Get scan line 00h N7 N6 N5 N4 N3 N2 N1 N0 DSTBON DVS W 4Fh 4F00h 00h 0 0 0 0 0 0 0 DSTB Deep standby mode on 5000h 00h V017 V016 V015 V014 V013 V012 V011 V010 Write profile value for display WRPFD 5001h DVS W 50h : 00h V027 V026 V025 V024 V023 V022 V021 V020 : : : : : : : : : 500Eh 00h V157 V156 V155 V154 V153 V152 V151 V150 500Fh 00h V167 V166 V165 V164 V163 V162 V161 V160 WRDISBV DVS W 51h 5100h 00h DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0 Write display brightness RDDISBV Dir R 52h 5200h 00h DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0 Read display brightness value WRCTRLD DVS W 53h 5300h 00h 0 0 BCTRL A DD BL DB G Write control display RDCTRLD Dir R 54h 5400h 00h 0 0 BCTRL A DD BL DB G Read control display value WRCABC DVS W 55h 5500h 00h 0 0 0 0 0 0 C1 C0 Write CABC mode RDCABC Dir R 56h 5600h 00h 0 0 0 0 0 0 C1 C0 Read CABC mode 5700h 00h I017 I016 I015 I014 I013 I012 I011 I010 Write hysteresis 5701h 00h I027 I026 I025 I024 I023 I022 I021 I020 : : : : : : : : : : 570Eh 00h I157 I156 I155 I154 I153 I152 I151 I150 WRHYSTE 570Fh DVS W 57h 5710h 00h I167 I166 I165 I164 I163 I162 I161 I160 00h D017 D016 D015 D014 D013 D012 D011 D010 5711h 00h D027 D026 D025 D024 D023 D022 D021 D020 : : : : : : : : : : 571Eh 00h D157 D156 D155 D154 D153 D152 D151 D150 571Fh 00h D167 D166 D165 D164 D163 D162 D161 D160 5800h 00h G023 G022 G021 G020 G013 G012 G011 G010 Write gamma setting 5801h 00h G043 G042 G041 G040 G033 G032 G031 G030 WRGAMMSET DVS W 58h : : : : : : : : : : 5806h 00h G143 G142 G141 G140 G133 G132 G131 G130 5807h 00h G163 G162 G161 G160 G153 G152 G151 G150 RDFSVM Dir R 5Ah 5A00h 00h FSV15 FSV14 FSV13 FSV12 FSV11 FSV10 FSV9 FSV8 Read FS value MSBs RDFSVL Dir R 5Bh 5B00h 00h FSV7 FSV6 FSV5 FSV4 FSV3 FSV2 FSV1 FSV0 Read FS value LSBs RDMFFSVM Dir R 5Ch 5C00h 00h FFSV15 FFSV14 FFSV13 FFSV12 FFSV11 FFSV10 FFSV9 FFSV8 Read median filter FS value MSBs RDMFFSVL Dir R 5Dh 5D00h 00h FFSV7 FFSV6 FFSV5 FFSV4 FFSV3 FFSV2 FFSV1 FFSV0 Read median filter FS value LSBs WRCABCMB DVS W 5Eh 5E00h 00h CMB7 CMB6 CMB5 CMB4 CMB3 CMB2 CMB1 CMB0 Write CABC minimum brightness RDCABCMB Dir R 5Fh 5F00h 00h CMB7 CMB6 CMB5 CMB4 CMB3 CMB2 CMB1 CMB0 Read CABC minimum brightness 10/28/2011 257 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Table 6.1.1 User Command Set (Continued) Instruction WRLSCC RDLSCCM RDLSCCL RDBWLB RDBkx RDBky RDWx RDWy RDRGLB RDRx RDRy RDGx RDGy RDBALB RDBx RDBy RDAx RDAy RDDDBS RDDDBC RDFCS RDCCS RDID1 RDID2 RDID3 ACT R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 Function 6500h DVS W 65h 6501h 00h CC15 CC14 CC13 CC12 CC11 CC10 CC9 CC8 Write light sensor compensation coefficient 00h CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 Dir R 66h 6600h 00h CC15 CC14 CC13 CC12 CC11 CC10 CC9 CC8 Read LSCC value MSBs Dir R 67h 6700h 00h CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 Read LSCC value LSBs Dir R 70h 7000h 00h Bkx1 Bkx0 Bky1 Bky0 Wx1 Wx0 Wy1 Wy0 Read Black/White low bit Dir R 71h 7100h 00h Bkx9 Bkx8 Bkx7 Bkx6 Bkx5 Bkx4 Bkx3 Bkx2 Read Bkx Dir R 72h 7200h 00h Bky9 Bky8 Bky7 Bky6 Bky5 Bky4 Bky3 Bky2 Read Bky Dir R 73h 7300h 00h Wx9 Wx8 Wx7 Wx6 Wx5 Wx4 Wx3 Wx2 Read Wx Dir R 74h 7400h 00h Wy9 Wy8 Wy7 Wy6 Wy5 Wy4 Wy3 Wy2 Read Wy Dir R 75h 7500h 00h Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0 Read Red/Green low bit Dir R 76h 7600h 00h Rx9 Rx8 Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Read Rx Dir R 77h 7700h 00h Ry9 Ry8 Ry7 Ry6 Ry5 Ry4 Ry3 Ry2 Read Ry Dir R 78h 7800h 00h Gx9 Gx8 Gx7 Gx6 Gx5 Gx4 Gx3 Gx2 Read Gx Dir R 79h 7900h 00h Gy9 Gy8 Gy7 Gy6 Gy5 Gy4 Gy3 Gy2 Read Gy Dir R 7Ah 7A00h 00h Bx1 Bx0 By1 By0 Ax1 Ax0 Ay1 Ay0 Read Blue/AColor low bit Dir R 7Bh 7B00h 00h Bx9 Bx8 Bx7 Bx6 Bx5 Bx4 Bx3 Bx2 Read Bx Dir R 7Ch 7C00h 00h By9 By8 By7 By6 By5 By4 By3 By2 Read By Dir R 7Dh 7D00h 00h Ax9 Ax8 Ax7 Ax6 Ax5 Ax4 Ax3 Ax2 Read Ax Dir R 7Eh 7E00h 00h Ay9 Ay8 Ay7 Ay6 Ay5 Ay4 Ay3 Ay2 Read Ay A100h 00h SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 Read DDB start A101h 00h SID15 SID14 SID13 SID12 SID11 SID10 SID9 SID8 Dir R A1h A102h 00h MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 A103h 00h MID15 MID14 MID13 MID12 MID11 MID10 MID9 MID8 A104h 00h 1 1 1 1 1 1 1 1 A800h 00h SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 Read DDB continue A801h 00h SID15 SID14 SID13 SID12 SID11 SID10 SID9 SID8 Dir R A8h A802h 00h MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 A803h 00h MID15 MID14 MID13 MID12 MID11 MID10 MID9 MID8 A804h 00h 1 1 1 1 1 1 1 1 Dir R AAh AA00h 00h FCS7 FCS6 FCS5 FCS4 FCS3 FCS2 FCS1 FCS0 Read first checksum Dir R AFh AF00h 00h CCS7 CCS6 CCS5 CCS4 CCS3 CCS2 CCS1 CCS0 Read continue checksum Dir R DAh DA00h 00h ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 Read ID1 Dir R DBh DB00h 00h ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 Read ID2 Dir R DCh DC00h 00h ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Read ID3 10/28/2011 258 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Notes: 1. The following description is indicates the executing time of instructions. No. Symbol Executing Time 1 Dir (Direct) At the received a completed instruction and parameter 2 DVS (Display Vertical Sync.) Synchronized with the next frame 3 DHS (Display Horizontal Sync.) Synchronized with the next line 4 Cnd1 (By Conditional 1) State When Sleep In Other Executing time Dir DHS 5 Cnd2 (By Conditional 2) State B7, B6, B5 B4, B3, B2, B1, B0 Executing time Dir DVS 2. In MIPI interface, parameters of the command are stores onto registers when the last parameter of the command has been received. Also, parameters of the command are not stored onto registers if there has been happen a break. See more information on the section “5.6 DATA TRANSFER RECOVERY”. This note is valid when a number of the parameters is equal or less than 32 (In case of other interfaces, parameters of command 2A00h~2A03h are stored on relative registers while command 2A00h~2A03h are executed completely and same for command 2B00h~2B03h, 3000h~3003h and 4000h~4001h). 3. When using the commands without parameter (No Argument) in MDDI interface, a dummy parameter must be followed after command address. For example, command SPLOUT can be executed as 0x11 only in MIPI, MPU and SPI interfaces but should be executed as 0x1100 + 0x0000 in MDDI interface. 10/28/2011 259 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 NOP (0000h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 NOP Write 00h 0000h No Argument (0000h in MDDI I/F) NOTE: “-” Don’t care This command is empty command. It does not have effect on the display module. Description However it can be used to terminate RAM data write, RAM data read, RAM data write continue or RAM data read continue as described in RAMWR (Memory Write), RAMRD (Memory Read), RAMWRC (Memory Write Continue) and RAMRDC (Memory Read Continue) and parameter write commands. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart - Status Power On Sequence S/W Reset H/W Reset Default Value N/A N/A N/A 10/28/2011 260 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 SWRESET: Software Reset (0100h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 SWRESET Write 01h 0100h No Argument (0000h in MDDI I/F) NOTE: “-” Don’t care When the Software Reset command is written, it causes a software reset. It resets the commands and Description parameters to their S/W Reset default values. (See default tables in each command description) The display is blank immediately. Note: The Frame Memory content is kept or not by this command. It will be necessary to wait 5msec before sending new command following software reset. The display module loads all display supplier’s factory default values to the registers during this 5msec. Restriction If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out command. Software Reset command cannot be sent during Sleep Out sequence. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset SWRESET(01h) Display whole blank screen Set Command to S/W Default Value Sleep In Mode Default Value N/A N/A N/A Host Driver Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 261 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDID: Read Display ID (0400h~0402h) Inst / Para RDDID R/W Read Address MIPI Others D[15:8] (Non-MIPI) 0400h 00h 04h 0401h 00h D7 ID17 ID27 Parameter D6 D5 D4 ID16 ID15 ID14 ID26 ID25 ID24 D3 ID13 ID23 D2 ID12 ID22 D1 ID11 ID21 D0 ID10 ID20 0402h 00h ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 NOTE: “-” Don’t care Description This read byte returns 24-bit display identification information. The 1st parameter (ID1): the module’s manufacture ID. The 2nd parameter (ID2): the module/driver version ID. The 3rd parameter (ID3): the module/driver ID. Note: Commands RDID1/2/3 (DAh, DBh, DCh) read data correspond to the parameter 1, 2, 3 of the command 04h, respectively. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDDID(04h) Send 1st Parameter ID1[7:0] Send 2nd Parameter ID2[7:0] Send 3rd Parameter ID3[7:0] After MTP MTP Values MTP Values MTP Values Default Value Before MTP ID1=00h, ID2=80h, ID3=00h ID1=00h, ID2=80h, ID3=00h ID1=00h, ID2=80h, ID3=00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 262 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDNUMED: Read Number of Errors on DSI (0500h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDNUMED Read 05h X X P7 P6 P5 P4 P3 P2 P1 P0 NOTE: “-“ Don’t care The first parameter is telling a number of the parity errors on DSI. The more detailed description of the bits is below. Description P[6..0] bits are telling a number of the parity errors. P[7] is set to “1” if there is overflow with P[6..0] bits. P[7..0] bits are set to “0”s (as well as RDDSM(0Eh)’s D0 are set “0” at the same time) after there is sent the first parameter information (= The read function is completed). See also section “Acknowledge with Error Report (AwER)” and command RDDSM 0Eh. This command is used for MIPI DSI only. It is no function for others interface operation. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h Flow Chart RDNUMED(05h) Send 1st Parameter P[7:0] = 00h RDDSM(0Eh)'s D0='0' Host Driver Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 263 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDPM: Read Display Power Mode (0A00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDDPM Read 0Ah 0A00h 00h D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care This command indicates the current status of the display as described in the table below: Bit Description Value D7 Booster Voltage Status “1”=Booster On, “0”=Booster Off D6 Idle Mode On/Off “1”=Idle Mode On, “0”=Idle Mode Off Description D5 Partial Mode On/Off D4 Sleep In/Out “1” = Partial Mode On, “0” = Partial Mode Off “1” = Sleep Out Mode, “0” = Sleep In Mode D3 Display Normal Mode On/Off “1” = Display Normal On, “0” = Display Normal Off D2 Display On/Off “1” = Display is On, “0” = Display is Off D1 Not Defined Set to “0” (not used) D0 Not Defined Set to “0” (not used) Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 08h 08h 08h Flow Chart RDDPM(0Ah) Send 1st Parameter Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 264 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDMADCTL: Read Display MADCTL (0B00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDDMADCTL Read 0Bh 0B00h 00h D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care This command indicates the current status of the display as described in the table below: Bit Description Value D7 Row Address Order (MY) “0” = Increment , “1” = Decrement D6 Column Address Order (MX) “0” = Increment , “1” = Decrement D5 Row/Column Exchange (MV) “0”= Normal , “1”= Row/column exchange Description D4 Vertical refresh Order (ML) D3 RGB-BGR Order “0” = Increment , “1” = Decrement “0” = RGB color sequence “1” = BGR color sequence D2 Horizontal refresh Order (MH) “0” = Increment , “1” = Decrement D1 Flip horizontal (RSMX) “0” = Normal , “1” = Horizontal flip D0 Flip vertical (RSMY) “0” = Normal , “1” = Vertical flip Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDDMADCTL(0Bh) Send 1st Parameter Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 265 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDCOLMOD: Read Display Pixel Format (0C00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDDCOLMOD Read 0Ch 0C00h 00h D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care This command indicates the current status of the display as described in the table below: Bit Description Value D7 Not Defined Set to “0” (not used) Description D6 ~ D4 RGB Interface Color Format “101” = 16-bit / pixel “110” = 18-bit / pixel “111” = 24-bit / pixel D3 Not Defined Set to “0” (not used) D2 ~ D0 Control Interface Color Format “101” = 16-bit / pixel “110” = 18-bit / pixel “111” = 24-bit / pixel Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDDCOLMOD(0Ch) Send 1st Parameter Default Value 07h 07h 07h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 266 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDIM: Read Display Image Mode (0D00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDDIM Read 0Dh 0D00h 00h D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care This command indicates the current status of the display as described in the table below: Bit Description Value D7 Vertical Scrolling On/Off Set to “0” (not used) D6 Horizontal Scrolling On/Off Set to “0” (not used) Description D5 Inversion On/Off D4 All Pixel On “1” = Inversion On, “0” = Inversion Off “1” = White display, “0” = Normal display D3 All Pixel Off “1” = Black display, “0” = Normal display D2 ~ D0 Gamma Curve Selection “000” = GC0, “001” = GC1 “010” = GC2, “011” = GC3 “100” to “111” = not defined Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDDIM(0Dh) Send 1st Parameter Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 267 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDSM: Read Display Signal Mode (0E00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDDSM Read 0Eh 0E00h 00h D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care This command indicates the current status of the display as described in the table below: Bit Description Value D7 Tearing Effect Line On/Off “1” = On, “0” = Off D6 Tearing Effect Line Mode “1” = Mode 2, “0” = Mode 1 D5 Horizontal Sync. (HS, RGB I/F)On/Off “1” = HS bit is “1”, “0” = HS bit is “0” Description D4 Vertical Sync. (VS, RGB I/F)On/Off “1” = VS bit is “1”, “0” = VS bit is “0” D3 Pixel Clock (PCLK, RGB I/F)On/Off “1” = PCLK line is On, “0” = PCLK line is Off D2 Data Enable (DE, RGB I/F)On/Off “1” = DE bit is “1”, “0” = DE bit is “0” D1 Not Defined Set to “0” (not used) D0 Error on DSI “1” = Error, “0” = No Error Note: Bit D5 to D2 indicate current status of the lines when this command has been sent. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDDSM(0Eh) Send 1st Parameter Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 268 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDSDR: Read Display Self-Diagnostic Result (0F00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDDSDR Read 0Fh 0F00h 00h D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care This command indicates the current status of the display as described in the table below: Bit Description Value D7 Register Loading Detection D6 Functionality Detection D5 Chip Attachment Detection See section 5.15 Description D4 Display Glass Break Detection D3 Not Defined Set to “0” (not used) D2 Not Defined Set to “0” (not used) D1 Not Defined Set to “0” (not used) D0 Checksums Comparison “0”: Checksums are the same “1”: Checksums are not the same Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDDSDR(0Fh) Send 1st Parameter Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 269 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 SLPIN: Sleep In (1000h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 SLPIN Write 10h 1000h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command causes the TFT LCD module to enter the minimum power consumption mode. In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped. Source / Gate Output Blank Display STOP Memory Scan Operation STOP Description Restriction Internal Oscillator STOP DC / DC Converter OFF Control Interface as will as memory and registers are still working and the memory keeps (RAMKP=”1”) or loses (RAMKP=”0”) its contents. User can send PCLK, HS and VS information on RGB I/F for blank display after Sleep In command and this information is valid during 2 frames after Sleep In command if there is used Normal Mode On in Sleep Out-mode. Dimming function does not work when there is changing mode from Sleep Out to Sleep In. There is used an internal oscillator for blank display. This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out Command (11h). It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Sleep In Mode Sleep In Mode Sleep In Mode 10/28/2011 270 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Flow Chart It takes about 120 msec to get into Sleep In mode (booster off state) after SLPIN command issued. The results of booster off can be check by RDDST (0Ah) command D7. SPLIN(10h) Display whole blank screen (Automatic No Effect to DISP On/OFF Command) All control signals for glass = PVDD Stop DC/DC Converter Stop Internal Oscillator Sleep In Mode Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 271 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 SLPOUT: Sleep Out (1100h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 SLPOUT Write 11h 1100h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command turns off sleep mode. In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started. Source / Gate Output STOP Blank CDP or Frame Memory Contents Description Restriction (If DISPON 29h is set) Memory Scan Operation STOP Internal Oscillator STOP START ON DC / DC Converter User can start to send PCLK, HS and VS information on RGB I/F before Sleep Out command and this information is valid at least 2 frames before Sleep Out command, if there is left Sleep In-mode to Sleep Out-mode in Normal Mode On. There is used an internal oscillator for blank display. NT35510 will do sequence control about gate control signals when sleep out. Sleep Out Mode can only be exit by the Sleep In Command (10h), S/W reset command (01h) or H/W reset. It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. NT35510 loads all default values of extended and test command to the registers during this 5msec and there cannot be any abnormal visual effect on the display image if those default and register values are same when this load is done and when the NT35510 is already Sleep Out –mode. NT35510 is doing self-diagnostic functions during this 5msec. See also section 5.15. It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Sleep In Mode Sleep In Mode Sleep In Mode 10/28/2011 272 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 It takes about 120 msec to get into Sleep In mode (booster off state) after SLPIN command issued. The results of booster off can be check by RDDST (0Ah) command D7. Flow Chart SPLOUT(11h) Start up Internal Oscillator Start up DC/DC Converter All control signals for glass are normal Display whole blank screen for 2 frames (Automatic No Effect to DISP On/OFF Command) Display CDP or Frame Memory contents in Accordance with the current command table setting Sleep In Mode Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 273 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 PTLON: Partial Display Mode On (1200h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 PTLON Write 12h 1200h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command turns on Partial mode. The partial mode window is described by the Partial Area Description command (30H) To leave Partial mode, the Normal Display Mode On command (13H) should be written. There is no abnormal visual effect during mode change between Normal mode On to Partial mode On. Restriction This command has no effect when Partial Display mode is active. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Flow Chart See Partial Area (30h) Default Value Normal Mode On Normal Mode On Normal Mode On 10/28/2011 274 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 NORON: Normal Display Mode On (1300h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 NORON Write 13h 1300h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command returns the display to normal mode. Description Normal display mode on means Partial mode off. Exit from NORON by the Partial mode On command (12h) There is no abnormal visual effect during mode change from Partial mode On to Normal mode On. Restriction This command has no effect when Normal Display mode is active. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Normal Mode On Normal Mode On Normal Mode On Flow Chart See Partial Area Definition Descriptions for details of when to use this command 10/28/2011 275 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 INVOFF: Display Inversion Off (2000h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 INVOFF Write 20h 2000h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command is used to recover from display inversion mode. This command makes no change of contents of frame memory. This command does not change any other status. (Example) Memory Display Description Restriction This command has no effect when module is already in Inversion Off mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Display Inversion off Display Inversion off Display Inversion off Flow Chart Display Inversion On Mode INVOFF(20h) Display Inversion Off Mode Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 276 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 INVON: Display Inversion On (2100h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 INVON Write 21h 2100h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command is used to enter display inversion mode. This command makes no change of contents of frame memory. This command does not change any other status. To exit from Display Inversion On, the Display Inversion Off command (20h) should be written. (Example) Memory Display Description Restriction This command has no effect when module is already in Inversion On mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Display Inversion off Display Inversion off Display Inversion off Flow Chart Display Inversion Off Mode INVON(21h) Display Inversion On Mode Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 277 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 ALLPOFF: All Pixel Off (2200h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 ALLPOFF Write 22h 2200h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command turns the display panel black in Sleep Out mode and a status of the Display On/Off register can be on or off. This command makes no change of contents of frame memory. This command does not change any other status. Memory Display Description Restriction (Example) “All Pixels On”, “Normal Display Mode On” or “Partial Mode On” commands are used to leave this mode. The display panel is showing the content of the frame memory after “Normal Display On” and “Partial Mode On” commands. This command has no effect when module is already in All Pixel Off mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value All pixel off All pixel off All pixel off 10/28/2011 278 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Flow Chart PRELIMINARY Normal Display Mode On ALLPOFF(22h) Black Display NT35510 Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 279 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 ALLPON: All Pixel On (2300h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 ALLPON Write 23h 2300h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command turns the display panel white in Sleep Out mode and a status of the Display On/Off register can be on or off. This command makes no change of contents of frame memory. This command does not change any other status. (Example) Memory Display Description Restriction “All Pixels Off”, “Normal Display Mode On” or “Partial Mode On” commands are used to leave this mode. The display panel is showing the content of the frame memory after “Normal Display On” and “Partial Mode On” commands. This command has no effect when module is already in all Pixel On mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value All pixel off All pixel off All pixel off 10/28/2011 280 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Flow Chart PRELIMINARY Normal Display Mode On ALLPON(23h) White Display NT35510 Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 281 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 GAMSET: Gamma Set (2600h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 GAMSET Write 26h 2600h 00h GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0 NOTE: “-“ Don’t care This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table. GC[7:0] Parameter Curve Selected Description 01h GC0 Gamma Curve 1 (G=2.2) 02h GC1 Reserved 04h GC2 Reserved 08h GC3 Reserved Note: All other values are undefined. Restriction Values of GC [7:0] not shown in table above are invalid and will not change the current selected gamma curve until valid is received. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset GAMSET(26h) GC[7:0] New Gamma Curve Loaded Default Value 01h 01h 01h Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 282 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DISPOFF: Display Off (2800h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 DISPOFF Write 28h 2800h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and blank page inserted. This command makes no change of contents of frame memory. This command does not change any other status. There will be no abnormal visible effect on the display. (Example) Memory Display Description Restriction This command has no effect when module is already in Display Off mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset Display On Mode DISPOFF(28h) Display Off Mode Default Value Display off Display off Display off Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 283 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DISPON: Display On (2900h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 DISPON Write 29h 2900h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command is used to recover from DISPLAY OFF mode. Output from Frame Memory is enabled. This command makes no change of contents of frame memory. This command does not change any other status. (Example) Memory Display Description Restriction This command has no effect when module is already in Display On mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Display off Display off Display off Flow Chart Display Off Mode DISPON(29h) Display On Mode Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 284 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 CASET: Column Address Set (2A00h~2A03h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 2A00h 00h XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS8 2A01h 00h XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 CASET Write 2Ah 2A02h 00h XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE8 2A03h 00h XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0 NOTE: “-“ Don’t care This command is used to define area of frame memory where MPU can access. This command makes no change on the other driver status. Each value represents one column line in the Frame Memory. (Example) XS[15:0] XE[15:0] Description Restriction XS[15:0] always must be equal to or less than XE[15:0] When XS[15:0] or XE[15:0] is greater than maximum address like below, data of out of range will be ignored. For CGM[7:0] = “70h” (480 x 864 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 863 (035Fh) For CGM[7:0] = “6Bh” (480 x 854 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 853 (0355h) For CGM[7:0] = “50h” (480 x 800 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 799 (031Fh) For CGM[7:0] = “28h” (480 x 720 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 719 (02CFh) For CGM[7:0] = “00h” (480 x 640 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 639 (027Fh) Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 10/28/2011 285 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Default For CGM[7:0] = “70h”, “6Bh”, “50h”, “28h”, “00h” , “FEh” (480x864/854/800/720/640 resolution) Status Default Value XS[15:0] XE[15:0] Power On Sequence 0000h 01DFh (479d) S/W Reset 0000h 01DFh (479d) H/W Reset 0000h 01DFh (479d) Flow Chart CASET(2Ah) 1st & 2nd Parameter XS[15:0] 3rd & 4th Parameter XE[15:0] RASET(2Bh) 1st & 2nd Parameter YS[15:0] 3rd & 4th Parameter YE[15:0] RAMWR(2Ch) Image Data D1[23:0], D2[23:0], ..., Dn[23:0] Any Command Legend If Needed Command Parameter Display Action Mode Sequential transfer 10/28/2011 286 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RASET: Row Address Set (2B00h~2B03h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 2B00h 00h YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS8 2B01h 00h YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 RASET Write 2Bh 2B02h 00h YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE8 2B03h 00h YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 NOTE: “-“ Don’t care Description This command is used to define area of frame memory where MPU can access. This command makes no change on the other driver status. Each value represents one column line in the Frame Memory. (Example) YS[15:0] Restriction YE[15:0] YS[15:0] always must be equal to or less than YE[15:0] When YS[15:0] or YE[15:0] is greater than maximum address like below, data of out of range will be ignored. For CGM[7:0] = “70h” (480 x 864 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 863 (035Fh) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) For CGM[7:0] = “6Bh” (480 x 854 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 853 (0355h) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) For CGM[7:0] = “50h” (480 x 800 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 799 (031Fh) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) For CGM[7:0] = “28h” (480 x 720 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 719 (02CFh) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) For CGM[7:0] = “00h” (480 x 640 resolution) MV = “0”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 639 (027Fh) MV = “1”: Parameter range 0 ≦ XS[15:0] ≦ XE[15:0] ≦ 479 (01DFh) Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 10/28/2011 287 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Default For CGM[7:0] = “70h”, “6Bh”, “50h”, “28h”, “00h” , “FEh” (480x864/854/800/720/640 resolution) Status YS[15:0] Default Value YE[15:0] Power On Sequence 0000h 035Fh (863d) S/W Reset 0000h 035Fh (863d) if CGM[7:0]=”70h” 0355h (853d) if CGM[7:0]=”6Bh” 031Fh (799d) if CGM[7:0]=”50h” 02CFh (719d) if CGM[7:0]=”28h” 027Fh (639d) if CGM[7:0]=”00h” 0167h (359d) if CGM[7:0]=”FEh” H/W Reset 0000h 035Fh (863d) Flow Chart CASET(2Bh) 1st & 2nd Parameter XS[15:0] 3rd & 4th Parameter XE[15:0] RASET(2Bh) 1st & 2nd Parameter YS[15:0] 3rd & 4th Parameter YE[15:0] RAMWR(2Ch) Image Data D1[23:0], D2[23:0], ..., Dn[23:0] Any Command If Needed If Needed Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 288 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RAMWR: Memory Write (2C00h) Inst / Para RAMWR R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 D[15:8] D7 D6 D5 D4 D3 D2 D1 D0 Write 2Ch 2C00h D[15:8] : : : : : : : : D[15:8] D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care Description This command is used to transfer data from MPU interface to frame memory. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTL setting Then D[23:0] is stored in frame memory and the column register and the row register incremented. Sending any other command can stop Frame Write. Restriction There is no restriction on length of parameters. No access in the frame memory in Sleep In mode Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Contents of memory is set randomly Contents of memory is set randomly Contents of memory is set randomly Flow Chart RAMWR(2Ch) Image Data D1[23:0], D2[23:0], ..., Dn[23:0] Any Command Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 289 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RAMRD: Memory Read (2E00h) Inst / Para RAMRD R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 D[15:8] D7 D6 D5 D4 D3 D2 D1 D0 Read 2Eh 2E00h D[15:8] : : : : : : : : D[15:8] D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care Description This command is used to transfer data from frame memory to MPU interface. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTR setting. Then D[23:0] is read back from the frame memory and the column register and the row register incremented Frame Read can be canceled by sending any other command. Restriction There is no restriction on length of parameters. No access in the frame memory in Sleep In mode Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Contents of memory is set randomly Contents of memory is set randomly Contents of memory is set randomly Flow Chart RAMRD(2Eh) Image Data D1[23:0], D2[23:0], ..., Dn[23:0] Any Command Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 290 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 PTLAR: Partial Area (3000h~3003h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 3000h 00h PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8 PTLAR 3001h Write 30h 3002h 00h PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 00h PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8 3003h 00h PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 NOTE: “-“ Don’t care This command defines the partial mode’s display area. There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter. If End Row > Start Row when MADCTL ML=0: Start Row Non-display Area PSL[15:0] Partial Display Area PEL[15:0] End Row Non-display Area Description If End Row > Start Row when MADCTL ML=1: End Row Non-display Area PEL[15:0] Partial Display Area PSL[15:0] Start Row Non-display Area If End Row < Start Row when MADCTL ML=0: End Row PEL[15:0] Non-display Area PSL[15:0] Start Row If End Row = Start Row then the Partial Area will be one row deep. Partial Display Area 10/28/2011 291 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Restriction PSL[15:0] and PEL[15:0] should have below range CGM[7:0] = ”70h” (480 x 864): 0 ≦ PSL[15:0], PEL[15:0] ≦ 863 (035Fh), |PEL–PSL| ≦ 863 (035Fh) CGM[7:0] = ”6Bh” (480 x 854): 0 ≦ PSL[15:0], PEL[15:0] ≦ 853 (0355h), |PEL–PSL| ≦ 853 (0355h) CGM[7:0] = ”50h” (480 x 800): 0 ≦ PSL[15:0], PEL[15:0] ≦ 799 (031Fh), |PEL–PSL| ≦ 799 (031Fh) CGM[7:0] = ”28h” (480 x 720): 0 ≦ PSL[15:0], PEL[15:0] ≦ 719 (02CFh), |PEL–PSL| ≦ 719 (02CFh) CGM[7:0] = ”00h” (480 x 640): 0 ≦ PSL[15:0], PEL[15:0] ≦ 639 (027Fh), |PEL–PSL| ≦ 639 (027Fh) Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset PSL[15:0] 0000h 0000h 0000h Default Value PEL[15:0] 035Fh (863d) if CGM[7:0] = “70h” 0355h (853d) if CGM[7:0] = “6Bh” 031Fh (799d) if CGM[7:0] = “50h” 02CFh (719d) if CGM[7:0] = “28h” 027Fh (639d) if CGM[7:0] = “00h” 0167h (359d) if CGM[7:0] = “FEh” 035Fh (863d) if CGM[7:0] = “70h” 0355h (853d) if CGM[7:0] = “6Bh” 031Fh (799d) if CGM[7:0] = “50h” 02CFh (719d) if CGM[7:0] = “28h” 027Fh (639d) if CGM[7:0] = “00h” 0167h (359d) if CGM[7:0] = “FEh” 035Fh (863d) if CGM[7:0] = “70h” 0355h (853d) if CGM[7:0] = “6Bh” 031Fh (799d) if CGM[7:0] = “50h” 02CFh (719d) if CGM[7:0] = “28h” 027Fh (639d) if CGM[7:0] = “00h” 0167h (359d) if CGM[7:0] = “FEh” 10/28/2011 292 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY 1. To Enter Partial Mode 2. To Exit Partial Mode Flow Chart PTLAR(30h) 1st & 2nd Parameter PSL[15:0] 3rd & 4th Parameter PEL[15:0] PTLON(12h) Partial Mode Partial Mode DISPOFF(28h) NORON(13h) Partial Mode Off RAMWR(2Ch) Image Data D1[23:0], D2[23:0], ..., Dn[23:0] DISPON(29h) NT35510 Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 293 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 TEOFF: Tearing Effect Line OFF (3400h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 TEOFF Write 34h 3400h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care Description This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Restriction This command has no effect when Tearing Effect output is already OFF. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Tearing Effect off Tearing Effect off Tearing Effect off Flow Chart TE Line Output ON TEOFF(34h) TE Line Output OFF Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 294 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 TEON: Tearing Effect Line ON (3500h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 TEON Write 35h 3500h 00h - - - - - - - M NOTE: “-“ Don’t care Description This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTL bit ML. The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. (“-“ = Don’t Care). When M = “0”: The Tearing Effect Output line consists of V-Blanking information only. tvdl tvdh Vertival Time Scale When M = “1”: The Tearing Effect Output line consists of both V-Blanking and H-Blinking information. tvdl tvdh Vertival Time Scale Restriction Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Lofw. This command has no effect when Tearing Effect output is already ON. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset TE Line Output OFF TEON(35h) TE Mode Parameter (M) TE Line Output ON Default Value Tearing Effect off Tearing Effect off Tearing Effect off Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 295 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 MADCTL: Memory Data Access Control (3600h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 MADCTL Write 36h 3600h 00h MY MX MV ML RGB MH RSMX RSMY NOTE: “-“ Don’t care This command defines read/write scanning direction of frame memory. This command makes no change on the other driver status. Bit NAME DESCRIPTION MY Row Address Order These 3 bits controls interface to memory write/read direction. MX Column Address Order The behavior on display after pattern changed. MV Row/Column Exchange ML Vertical Refresh Order TFT LCD Vertical refresh direction control. Immediately behavior on display. RGB RGB-BGR Order Color selector switch control “0” = RGB color sequence, “1” = BGR color sequence Immediately behavior on display Horizontal Refresh MH Order TFT LCD Horizontal refresh direction control Immediately behavior on display. RSMX Flip Horizontal Flips the display image left to right. Immediately behavior on display. Description RSMY Flip Vertical Flips the display image top to down. Immediately behavior on display. ML: Vertical Refresh Order Top-Left (0,0) ML="0" Memory Top-Left (0,0) Send 1st Send 2nd Send 3rd Display Top-Left (0,0) ML="1" Memory Send Last Top-Left (0,0) Send Last Display Send 3rd Send 2nd Send 1st 10/28/2011 296 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Top-Left (0,0) MH="0" MH: Horizontal Refresh Order Display Top-Left (0,0) MH="1" Display Send 1st Send 2nd Send 3rd Send Last Send Last Send 3rd Send 2nd Send 1st Description Top-Left (0,0) Memory Top-Left (0,0) Memory Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 10/28/2011 297 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Flow Chart PRELIMINARY MADCTL(36h) Parameter (MY, MX, MV, ML, MH) NT35510 Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 298 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 IDMOFF: Idle Mode Off (3800h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 IDMOFF Write 38h 3800h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care Description This command is used to recover from Idle mode on In the idle off mode, display panel can display maximum 16.7M colors. Restriction This command has no effect when module is already in Idle Off mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Idle Mode off Idle Mode off Idle Mode off Flow Chart Idle On Mode IDMOFF(38h) Idle Off Mode Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 299 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 IDMON: Idle Mode On (3900h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 IDMON Write 39h 3900h No Argument (0000h in MDDI I/F) NOTE: “-“ Don’t care This command is used to enter into Idle mode on. In the idle on mode, color expression is reduced. The primary and the secondary colors using MSB of each R, G, and B in Frame Memory, 8 color depth data is displayed. Memory Display Description Restriction Black Blue Red Magenta Green Cyan Yellow White Memory Contents vs. Display Colors R7R6R5R4R3R2R1R0 R7G6G5G4G3G2G1G0 B7B6B5B4B3B2B1B0 0XXXXXXX 0XXXXXXX 0XXXXXXX 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX 0XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX 1XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX 1XXXXXXX This command has no effect when module is already in Idle On mode Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Idle Mode off Idle Mode off Idle Mode off 10/28/2011 300 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Flow Chart PRELIMINARY Idle Off Mode IDMON(39h) Idle On Mode NT35510 Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 301 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 COLMOD: Interface Pixel Format (3A00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 COLMOD Write 3Ah 3A00h 00h VIPF3 VIPF2 VIPF1 VIPF0 IFPF3 IFPF2 IFPF1 IFPF0 NOTE: “-“ Don’t care This command is used to define the format of RGB picture data, which is to be transferred via the RGB or MCU interface. The formats are shown in the table: Bit NAME DESCRIPTION Description VIPF[3:0] Pixel Format for RGB Interface “0101” = 16-bit/pixel “0110” = 18-bit/pixel “0111” = 24-bit/pixel The others = not defined IFPF[3:0] Pixel Format for MCU Interface “0101” = 16-bit/pixel “0110” = 18-bit/pixel “0111” = 24-bit/pixel The others = not defined Restriction There is no visible effect until the Frame Memory is written to. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 77h 77h 77h Flow Chart 24-bit/pixel Mode COLMOD(3Ah) Parameter IFPF[3:0] = "0110" 18-bit/pixel Mode Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 302 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RAMWRC: Memory Write Continue (3C00h) Inst / Para RAMWRC R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 D[15:8] D7 D6 D5 D4 D3 D2 D1 D0 Write 3Ch 3C00h D[15:8] : : : : : : : : D[15:8] D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care Description This command is used to transfer data from MPU interface to frame memory, if there is wanted to continue memory write after “RAMWR Memory Write (2Ch)” command. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are not reset to the Start Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTL setting Then D[23:0] is stored in frame memory and the column register and the row register incremented. Sending any other command can stop Frame Write. Restriction There is no restriction on length of parameters. No access in the frame memory in Sleep In mode Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RAMWRC(3Ch) Image Data D1[23:0], D2[23:0], ..., Dn[23:0] Any Command Default Value Contents of memory is set randomly Contents of memory is set randomly Contents of memory is set randomly Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 303 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RAMRDC: Memory Read Continue (3E00h) Inst / Para RAMRDC R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 D[15:8] D7 D6 D5 D4 D3 D2 D1 D0 Read 3Eh 3E00h D[15:8] : : : : : : : : D[15:8] D7 D6 D5 D4 D3 D2 D1 D0 NOTE: “-“ Don’t care Description This command is used to transfer data from frame memory to MPU interface, if there is wanted to continue memory write after “RAMRD Memory Read (2Eh)” command. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are not reset to the Start Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTR setting. Then D[23:0] is read back from the frame memory and the column register and the row register incremented Frame Read can be canceled by sending any other command. Restriction There is no restriction on length of parameters. No access in the frame memory in Sleep In mode Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Contents of memory is set randomly Contents of memory is set randomly Contents of memory is set randomly Flow Chart RAMRDC(3Eh) Image Data D1[23:0], D2[23:0], ..., Dn[23:0] Any Command Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 304 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 STESL: Set Tearing Effect Scan Line (4400h~4401h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 4400h 00h STESL Write 44h 4401h 00h N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 NOTE: “-“ Don’t care Description This command turns on the display module’s Tearing Effect output signal on the TE signal line when the display module reaches line N. The TE signal is not affected by changing MADCTL bit ML. The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line mode. The Tearing Effect Output line consists of V-Blanking information only. tvdl tvdh Vertival Time Scale Restriction Note that STESL with N[15:0]=”000h” is equivalent to TEON with M=”0” The Tearing Effect Output line shall be active low when the display module is in Sleep in mode. This command takes affect on the frame following the current frame. Therefore, if the TE output is already on, the TE output shall continue to operate as programmed by the previous “TEON (35h)” or “STESL (44h) command” until the end of the frame. When N[15:0] is greater than maximum scanning line like below, data of out of range will be ignored. For CGM[7:0] = “70h” (480 x 864 resolution) Parameter range 0 ≦ N[15:0] ≦ 864 (0360h) For CGM[7:0] = “6Bh” (480 x 854 resolution) Parameter range 0 ≦ N[15:0] ≦ 854 (0356h) For CGM[7:0] = “50h” (480 x 800 resolution) Parameter range 0 ≦ N[15:0] ≦ 800 (0320h) For CGM[7:0] = “28h” (480 x 720 resolution) Parameter range 0 ≦ N[15:0] ≦ 720 (02D0h) For CGM[7:0] = “00h” (480 x 640 resolution) Parameter range 0 ≦ N[15:0] ≦ 640 (0280h) Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 0000h 0000h 0000h 10/28/2011 305 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Flow Chart PRELIMINARY TE Output On or Off STESL(44h) 1st Parameter: N[15:8] 2nd Parameter: N[7:0] TE Output On NT35510 Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 306 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 GSL: Get Scan Line (4500h~4501h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 4500h 00h GSL Read 45h 4501h 00h N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 NOTE: “-“ Don’t care Description This command returns the current scan line, N, used to update the display module. The total number of scan lines on display is defined as VSYNC + VBP + VADR + VFP. The first scan line is defined as the first line of V Sync and is denoted as Line 0. When in Sleep in mode, the returned value is undefined. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset GSL(45h) Send Parameter N[15:8] Send Parameter N[7:0] Default Value XXXXh XXXXh XXXXh Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 307 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DPCKRGB: Display Clock in RGB Interface (4A00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 DPCKRGB Write X 4A00h 00h 0 0 0 0 0 0 0 ICM NOTE: “-“ Don’t care This command is used to select SRAM data input path and display clock in RGB interface. Description ICM Data Write to SRAM SRAM Data Read to Display SRAM Write Clock SRAM Data Input Path Internal Display Clock 0 PCLK D[23:0] VS, HS and PCLK 1 SCL SDI Internal Oscillator Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset Default Value ICM = “0” ICM = “0” ICM = “0” Display Clock by PCLK DPCKRGB (4Ah) Parameter ICM = 1 Display Clock by Internal Oscillator Display Clock by Internal Oscillator DPCKRGB (4Ah) Parameter ICM = 0 Display Clock by PCLK Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 308 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DSTBON: Deep Standby Mode On (4F00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 DSTBON Write X 4F00h 00h 0 0 0 0 0 0 0 NOTE: “-“ Don’t care This command is used to enter deep standby mode. DSTB=”1”, enter deep standby mode. Description Notes: 1. Before setting this command, enter Sleep In Mode (1000h) and Display Off (2800h) first. User can not write this register in Sleep-Out and Display-On mode. 2. It can not exit Deep Standby Mode while setting bit DSTB from “1” to “0”. 3. To exit Deep Standby Mode, input low pulse more than 3 msec to pin RESX. Restriction - D0 DSTB Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset Sleep In and Display Off Mode DSTBM (4Fh) Parameter DSTB = 1 Deep Standby Mode Default Value DSTB = “0” DSTB = “0” DSTB = “0” Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 309 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 WRPFD: Write Profile Value for Display (5000h~500Fh) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 5000h 00h V017 V016 V015 V014 V013 V012 V011 V010 5001h 00h V027 V026 V025 V024 V023 V022 V021 V020 5002h 00h WRPFD Write 50h : 00h 500Dh 00h V037 V036 V035 V034 V033 V032 V031 V030 : : : : : : : : V147 V146 V145 V144 V143 V142 V141 V140 500Eh 00h V157 V156 V155 V154 V153 V152 V151 V150 500Fh 00h V167 V166 NOTE: “-“ Don’t care Description This command is used to define profile values for display. Restriction - V165 V164 V163 V162 V161 V160 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value FFh FFh FFh Flow Chart WRPFD(50h) 1st Parameter V01[7:0] 2nd Parameter V02[7:0] : 16th Parameter V16[7:0] Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 310 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 WRDISBV: Write Display Brightness (5100h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 WRDISBV Write 51h 5100h 00h DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0 NOTE: “-“ Don’t care This command is used to adjust brightness value. In principle relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. DBV[7:0] Brightness (Ratio) Brightness (%) Description 00h 01h 0/256 2/256 0% 0.78125% : : : FEh 255/256 99.609375% FFh 256/256 100% Restriction The display supplier cannot use this command for tuning (e.g. factory tuning, etc.). Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h Flow Chart WRDISBV(51h) Parameter DBV[7:0] New Brightness Loaded Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 311 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDISBV: Read Display Brightness (5200h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDDISBV Read 52h 5200h 00h DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0 NOTE: “-“ Don’t care This command returns brightness value. Description In principle relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h Flow Chart RDDISBV(52h) Send Parameter DBV[7:0] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 312 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 WRCTRLD: Write CTRL Display (5300h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 WRCTRLD Write 53h 5300h 00h 0 0 BCTRL A DD BL DB G NOTE: “-“ Don’t care This command is used to control ambient light, brightness and gamma setting. BCTRL: Brightness Control Block On/Off The BCTRL bit is always used to switch brightness for display with dimming effect (according to DD bit). BCTRL DESCRIPTION LEDPWM Pin 0 Off, DBV[7:0] are 00h. LEDPWPOL=”0”: keep low (0%, high level is duty) LEDPWPOL=”1”: keep high (0%, low level is duty) 1 On, DBV[7:0] are active LEDPWPOL=”0”: PWM output (high level is duty) LEDPWPOL=”1”: PWM output (low level is duty) A: LABC Block On/Off The BCTRL bit is used to control LABC block. A DESCRIPTION PWM duty for LEDPWM Pin 0 Off By DBV[7:0] of command “WRDISBV (5100h)” 1 On By LABC block DD: Display Dimming Control On/Off DD DESCRIPTION 0 Display dimming is off 1 Display dimming is on BL: Backlight Control On/Off without Dimming Effect When BL bit change from “On” to “Off”, display brightness is turned off without gradual dimming, even if dimming on (DD=”1”) is selected. Description BL 0 Off DESCRIPTION LEDON Pin LEDONPOL=”0”: output low (for high active) LEDONPOL=”1”: output high (for low active) 1 On LEDONPOL=”0”: output high (for high active) LEDONPOL=”1”: output low (for low active) DB: Display Brightness Manual/Automatic DB DESCRIPTION 0 Manual, the user has to use this setting for manual adjustment of the brightness to have an effect. 1 Automatic, information about the used brightness is included in the active profile. Note: All read and write commands are valid, but there is no effect (except registers can be changed) when write commands are used. G: Gamma Curve Manual/Automatic G DESCRIPTION 0 Manual, by GAMSET-command 1 Automatic, information about the used gamma is included in the active profile. The dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=”1”, e.g. BCTRL: 0→1 or 1→0. When the ambient light sensing off-mode (A=”0”), display brightness and gamma setting should be manual setting (DB=”0” and G=”0”). Setting values are the last one written with "Write Display Brightness (5100h)" command and GAMSET-command or the default one. When the ambient light control on, light sensor control block is always working, even if backlight off (BL=“0”) and display brightness manual (DB=”0”) are selected. 10/28/2011 313 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Status Power On Sequence S/W Reset H/W Reset Flow Chart WRCTRLD(53h) Parameter: BCTRL, A, DD, BL, DB New Control Value Loaded NT35510 Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 314 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDCTRLD: Read CTRL Display Value (5400h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDCTRLD Read 54h 5400h 00h 0 0 BCTRL A DD BL DB G NOTE: “-“ Don’t care This command returns ambient light, brightness control and gamma setting value. BCTRL: Brightness Control Block On/Off The BCTRL bit is always used to switch brightness for display with dimming effect (according to DD bit). BCTRL DESCRIPTION LEDPWM Pin 0 Off, DBV[7:0] are 00h. LEDPWPOL=”0”: PWM keep low (for high active) LEDPWPOL=”1”: PWM keep high (for low active) 1 On, DBV[7:0] are active LEDPWPOL=”0”: PWM output (high level is duty) LEDPWPOL=”1”: PWM output (low level is duty) A: LABC Block On/Off The BCTRL bit is used to control LABC block. A DESCRIPTION PWM duty for LEDPWM Pin 0 Off By DBV[7:0] of command “WRDISBV (5100h)” 1 On By LABC block DD: Display Dimming Control On/Off DD DESCRIPTION 0 Display dimming is off 1 Display dimming is on BL: Backlight Control On/Off without Dimming Effect When BL bit change from “On” to “Off”, display brightness is turned off without gradual dimming, even if dimming on (DD=”1”) is selected. Description BL 0 Off DESCRIPTION LEDON Pin LEDONPOL=”0”: PWM keep low (for high active) LEDPWPOL=”1”: PWM keep high (for low active) 1 On LEDPWPOL=”0”: PWM output (high level is duty) LEDPWPOL=”1”: PWM output (low level is duty) DB: Display Brightness Manual/Automatic DB DESCRIPTION 0 Manual, the user has to use this setting for manual adjustment of the brightness to have an effect. 1 Automatic, information about the used brightness is included in the active profile. Note: All read and write commands are valid, but there is no effect (except registers can be changed) when write commands are used. G: Gamma Curve Manual/Automatic G DESCRIPTION 0 Manual, by GAMSET-command 1 Automatic, information about the used gamma is included in the active profile. The dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=”1”, e.g. BCTRL: 0→1 or 1→0. When the ambient light sensing off-mode (A=”0”), display brightness and gamma setting should be manual setting (DB=”0” and G=”0”). Setting values are the last one written with "Write Display Brightness (5100h)" command and GAMSET-command or the default one. When the ambient light control on, light sensor control block is always working, even if backlight off (BL=“0”) and display brightness manual (DB=”0”) are selected. 10/28/2011 315 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Status Power On Sequence S/W Reset H/W Reset Flow Chart RDCTRLD(54h) Send Parameter BCTRL, A, DD, BL, DB Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 316 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 WRCABC: Write Content Adaptive Brightness Control (5500h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 WRCABC Write 55h 5500h 00h 0 0 0 0 0 0 C1 C0 NOTE: “-“ Don’t care This command is used to set parameters for image content based adaptive brightness control functionality. There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below. Description C1 C0 0 0 Off Function 0 1 User Interface Image (UI-Mode) 1 0 Still Picture Image (Still-Mode) 1 1 Moving Picture Image (Moving-Mode) Restriction This register is synchronized with V-sync by internal circuit. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset WRCABC(55h) Parameter: C[1:0] New Adaptive Image Mode Default Value 00h 00h 00h Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 317 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDCABC: Read Content Adaptive Brightness Control (5600h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDCABC Read 56h 5600h 00h 0 0 0 0 0 0 C1 C0 NOTE: “-“ Don’t care This command is used to read the settings for image content based adaptive brightness control functionality. There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below. Description C1 C0 0 0 Off Function 0 1 User Interface Image (UI-Mode) 1 0 Still Picture Image (Still-Mode) 1 1 Moving Picture Image (Moving-Mode) Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h Flow Chart RDCABC(56h) Send Parameter C[1:0] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 318 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 WRHYSTE: Write Hysteresis (5700h~573Fh) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 5700h 00h I0115 I0114 I0113 I0112 I0111 I0110 I019 I018 5701h 00h I017 I016 I015 I014 I013 I012 I011 I010 5702h 00h I0215 I0214 I0213 I0212 I0211 I0210 I029 I028 5703h 00h : 00h I027 I026 I025 I024 I023 I022 I021 I020 In15 In14 In13 In12 In11 In10 In9 In8 : 00h In7 In6 In5 In4 In3 In2 In1 In0 571Ch 00h I1515 I1514 I1513 I1512 I1511 I1510 I159 I158 571Dh 00h I157 I156 I155 I154 I153 I152 I151 I150 571Eh 00h I1615 I1614 I1613 I1612 I1611 I1610 I169 I168 571Fh 00h I167 I166 I165 I164 I163 I162 I161 I160 WRHYSTE Write 57h 5720h 00h D0115 D0114 D0113 D0112 D0111 D0110 D019 D018 5721h 00h D017 D016 D015 D014 D013 D012 D011 D010 5722h 5723h 00h D0215 D0214 D0213 D0212 D0211 D0210 D029 D028 00h D027 D026 D025 D024 D023 D022 D021 D020 : 00h Dn15 Dn14 Dn13 Dn12 Dn11 Dn10 Dn9 Dn8 : 00h Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 573Ch 00h D1515 D1514 D1513 D1512 D1511 D1510 D159 D158 573Dh 00h D157 D156 D155 D154 D153 D152 D151 D010 573Eh 00h D1615 D1614 D1613 D1612 D1611 D1610 D169 D168 573Fh 00h D167 D166 D165 D164 D163 D162 D161 D160 NOTE: “-“ Don’t care Description This command is used to define Hysteresis filter function. In[15:0] defines increment values and Dn[15:0] defines decrement values. Don’t care about the parameter values after "65535 (FFFFh)". I16[15 : 0] bits and D16[15 : 0] bits are always set to "65535 (FFFFh)" internally, if I15[15 : 0] bits and D15[15 : 0] bit are still valid and less than "65535 (FFFFh)". Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value FFh FFh FFh 10/28/2011 319 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Flow Chart PRELIMINARY WRHYSTE(57h) 1st Parameter I01[15:8] 2nd Parameter I01[7:0] : 31th Parameter I16[15:8] 32th Parameter I16[7:0] 33th Parameter D01[15:8] 34th Parameter D01[7:0] : 63th Parameter D16[15:8] 64th Parameter D16[7:0] NT35510 Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 320 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 WRGAMMSET: Write Gamma Setting (5800h~5807h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 5800h 00h G023 G022 G021 G020 G013 G012 G011 G010 5801h 00h G043 G042 G041 G040 G033 G032 G031 G030 5802h 00h G063 G062 G061 G060 G053 G052 G051 G050 5803h 00h G083 G082 G081 G080 G073 G072 G071 G070 WRGAMMSET Write 58h 5804h 00h G103 G102 G101 G100 G093 G092 G091 G090 5805h 00h G123 G122 G121 G120 G113 G112 G111 G110 5806h 00h G143 G142 G141 G140 G133 G132 G131 G130 5807h 00h G163 G162 G161 G160 G153 G152 G151 G150 NOTE: “-“ Don’t care This command is used to define gamma setting values for each luminance level. Gamma value is defined on command “Gamma Set (2600h)”. Gn[3:0] Parameter Curve Selected Description 01h 02h GC0 GC1 Gamma Curve 1 (G=2.2) Reserved 04h GC2 Reserved 08h GC3 Reserved Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 01h 01h 01h 10/28/2011 321 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Flow Chart PRELIMINARY WRGAMSET(58h) 1st Parameter G02/G01[3:0] 2nd Parameter G04/G03[3:0] : 8th Parameter G16/G15[3:0] NT35510 Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 322 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDFSVM: Read FS Value MSBs (5A00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDFSVM Read 5Ah 5A00h 00h FSV15 FSV14 FSV13 FSV12 FSV11 FSV10 FSV9 FSV8 NOTE: “-“ Don’t care Description This command returns MSBs (FSV[15:8]) of the "Front Side Ambient Light Sensor Value" after the flicker has been removed from ambient light reading. Another command for LSBs (FSV[7:0]). See the command "Read FS Value LSBs (5B00h)". When using read LSBs/MSBs command, corresponding MSBs/LSBs should be locked so that they refer to the same value when LSBs/MSBs are read. After reading both values, registers for MSBs and LSBs should be released. And that if e.g. LSBs are read and there is no MSBs read command, the next LSBs read will also update MSBs. If MSBs are read at first, the next MSBs read will update LSBs. If any other commands are received between LSBs read command and MSBs read command, the registers for MSBs and LSBs should be released. FSV[15:8] should be 00h when bit 'A' of the "Write CTRL Display (5300h)" command is "0". Note: Although FSV[15:0] is 16-bit length register, the valid value range is 0 ~ 65535 (0000h ~ FFFFh), In other words, user don't care about the parameter values over than "65535 (FFFFh)". Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDFSVM(5Ah) Send Parameter FSV[15:8] Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 323 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDFSVL: Read FS Value LSBs (5B00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDFSVL Read 5Bh 5B00h 00h FSV7 FSV6 FSV5 FSV4 FSV3 FSV2 FSV1 FSV0 NOTE: “-“ Don’t care Description This command returns LSBs (FSV[7:0]) of the "Front Side Ambient Light Sensor Value" after the flicker has been removed from ambient light reading. Another command for MSBs (FSV[15:8]). See the command "Read FS Value MSBs (5A00h)". When using read LSBs/MSBs command, corresponding MSBs/LSBs should be locked so that they refer to the same value when LSBs/MSBs are read. After reading both values, registers for MSBs and LSBs should be released. And that if e.g. LSBs are read and there is no MSBs read command, the next LSBs read will also update MSBs. If MSBs are read at first, the next MSBs read will update LSBs. If any other commands are received between LSBs read command and MSBs read command, the registers for MSBs and LSBs should be released. FSV[7:0] should be 00h when bit 'A' of the "Write CTRL Display (5300h)" command is "0". Note: Although FSV[15:0] is 16-bit length register, the valid value range is 0 ~ 65535 (0000h ~ FFFFh), In other words, user don't care about the parameter values over than "65535 (FFFFh)". Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDFSVL(5Bh) Send Parameter FSV[7:0] Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 324 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDMFFSVM: Read Median Filter FS Value MSBs (5C00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDMFFSVM Read 5Ch 5C00h 00h FFSV15 FFSV14 FFSV13 FFSV12 FFSV11 FFSV10 FFSV9 FFSV8 NOTE: “-“ Don’t care Description This command returns MSBs (FFSV[15:8]) of the "Front Side Ambient Light Sensor Value" after the median filter. Another command for LSBs (FFSV[7:0]). See the command "Read Median Filter FS Value LSBs (5D00h)". When using read LSBs/MSBs command, corresponding MSBs/LSBs should be locked so that they refer to the same value when LSBs/MSBs are read. After reading both values, registers for MSBs and LSBs should be released. And that if e.g. LSBs are read and there is no MSBs read command, the next LSBs read will also update MSBs. If MSBs are read at first, the next MSBs read will update LSBs. If any other commands are received between LSBs read command and MSBs read command, the registers for MSBs and LSBs should be released. FFSV[15:8] should be 00h when bit 'A' of the "Write CTRL Display (5300h)" command is "0". Note: Although FFSV[15:0] is 16-bit length register, the valid value range is 0 ~ 65535 (0000h ~ FFFFh), In other words, user don't care about the parameter values over than "65535 (FFFFh)". Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDMFFSVM(5Ch) Send Parameter FFSV[15:8] Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 325 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDMFFSVL: Read Median Filter FS Value LSBs (5D00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDMFFSVL Read 5Dh 5D00h 00h FFSV7 FFSV6 FFSV5 FFSV4 FFSV3 FFSV2 FFSV1 FFSV0 NOTE: “-“ Don’t care Description This command returns LSBs (FDSV[7:0]) of the "Front Side Ambient Light Sensor Value" after the median filter. Another command for MSBs (FFSV[15:8]). See the command "Read Median Filter FS Value MSBs (5C00h)". When using read LSBs/MSBs command, corresponding MSBs/LSBs should be locked so that they refer to the same value when LSBs/MSBs are read. After reading both values, registers for MSBs and LSBs should be released. And that if e.g. LSBs are read and there is no MSBs read command, the next LSBs read will also update MSBs. If MSBs are read at first, the next MSBs read will update LSBs. If any other commands are received between LSBs read command and MSBs read command, the registers for MSBs and LSBs should be released. FFSV[7:0] should be 00h when bit 'A' of the "Write CTRL Display (5300h)" command is "0". Note: Although FSV[15:0] is 16-bit length register, the valid value range is 0 ~ 65535 (0000h ~ FFFFh), In other words, user don't care about the parameter values over than "65535 (FFFFh)". Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDMFFSVL(5Dh) Send Parameter FFSV[7:0] Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 326 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 WRCABCMB: Write CABC minimum brightness (5E00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 WRCABCMB Write 5Eh 5E00h 00h CMB7 CMB6 CMB5 CMB4 CMB3 CMB2 CMB1 CMB0 NOTE: “-“ Don’t care Description This command is used to set the minimum brightness value of the display for CABC function In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the highest brightness for CABC. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h Flow Chart WRCABCMB(5Eh) Parameter CMB[7:0] New Display Luminance Value Loaded Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 327 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDCABCMB: Read CABC minimum brightness (5F00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDCABCMB Read 5Fh 5F00h 00h CMB7 CMB6 CMB5 CMB4 CMB3 CMB2 CMB1 CMB0 NOTE: “-“ Don’t care Description This command return the minimum brightness value of CABC function In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the highest brightness for CABC. CMB[7:0] is minimum brightness forCABC specified with “WRCABCMB Write CABC minimum brightness (5Eh)” command. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h Flow Chart RDCABCMB(5Fh) Send Parameter CMB[7:0] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 328 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 WRLSCC: Write Light Sensor Compensation Coefficient Value (6500h~6501h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 6500h 00h CC15 CC14 CC13 CC12 CC11 CC10 WRLSCC Write 65h 6501h 00h CC7 CC6 CC5 CC4 CC3 CC2 NOTE: “-“ Don’t care Description This command is used to send the compensation coefficient value (CC[15 : 0]). Default value for compensation coefficient is 1.0 (1000 0000 0000 0000 in binary). D1 CC9 CC1 D0 CC8 CC0 Restriction The display supplier cannot use this command for tuning (e.g. factory tuning, etc.). Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset WRLSCC(65h) 1st Parameter CC[15:8] 2nd Parameter CC[7:0] New CC Value Loaded Default Value 8000h 8000h 8000h Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 329 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDLSCCM: Read Light Sensor Compensation Coefficient Value MSBs (6600h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDLSCCM Write 66h 6600h 00h CC15 CC14 CC13 CC12 CC11 CC10 CC9 CC8 NOTE: “-“ Don’t care This command returns MSBs of the compensation coefficient value (CC[15:8]) which is stored by “Write Description Light Sensor Compensation Coefficient Value (6500h)” command. It can read MSBs/LSBs of "Light Sensor Compensation Coefficient value" with any order. Default value for compensation coefficient is 1.0 (1000 0000 0000 0000 in binary). MSBs are “1000 000”. Restriction The display supplier cannot use this command for tuning (e.g. factory tuning, etc.). Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDLSCCM(66h) Send Parameter CC[15:8] Default Value 80h 80h 80h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 330 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDLSCCL: Read Light Sensor Compensation Coefficient Value LSBs (6700h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDLSCCL Write 67h 6700h 00h CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 NOTE: “-“ Don’t care This command returns LSBs of the compensation coefficient value (CC[7:0]) which is stored by “Write Description Light Sensor Compensation Coefficient Value (6501h)” command. It can read MSBs/LSBs of "Light Sensor Compensation Coefficient value" with any order. Default value for compensation coefficient is 1.0 (1000 0000 0000 0000 in binary). MSBs are “0000 000”. Restriction The display supplier cannot use this command for tuning (e.g. factory tuning, etc.). Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDLSCCL(67h) Send Parameter CC[7:0] Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 331 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDBWLB: Read Black/White Low Bits (7000h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 RDBWLB Read 70h 7000h 00h Bkx1 Bkx0 Bky1 Bky0 Wx1 NOTE: “-“ Don’t care This command returns the lowest bits of black and white color characteristic. Description Black: Bkx and Bky White: Wx and Wy Restriction - D2 Wx0 D1 Wy1 D0 Wy0 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDBWLB(70h) Send Parameter Bkx[1:0], Bky[1:0] Wx[1:0], Wy[1:0] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 332 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDBkx: Read Bkx (7100h) Inst / Para R/W Address MIPI Others D[15:8] (Non-MIPI) D7 Parameter D6 D5 D4 RDBkx Read 71h 7100h 00h Bkx9 Bkx8 Bkx7 Bkx6 NOTE: “-“ Don’t care Description This command returns the Bkx bit (Bkx[9:2]) of black color characteristic. Restriction - D3 Bkx5 D2 Bkx4 D1 Bkx3 D0 Bkx2 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDBkx(71h) Send Parameter Bkx[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 333 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDBky: Read Bky (7200h) Inst / Para R/W Address MIPI Others D[15:8] (Non-MIPI) D7 Parameter D6 D5 D4 RDBky Read 72h 7200h 00h Bky9 Bky8 Bky7 Bky6 NOTE: “-“ Don’t care Description This command returns the Bky bit (Bky[9:2]) of black color characteristic. Restriction - D3 Bky5 D2 Bky4 D1 Bky3 D0 Bky2 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDBky(72h) Send Parameter Bky[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 334 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDWx: Read Wx (7300h) Inst / Para R/W Address MIPI Others D[15:8] (Non-MIPI) D7 Parameter D6 D5 D4 RDWx Read 73h 7300h 00h Wx9 Wx8 Wx7 Wx6 NOTE: “-“ Don’t care Description This command returns the Wx bit (Wx[9:2]) of white color characteristic. Restriction - D3 Wx5 D2 Wx4 D1 Wx3 D0 Wx2 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDWx(73h) Send Parameter Wx[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 335 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDWy: Read Wy (7400h) Inst / Para R/W Address MIPI Others D[15:8] (Non-MIPI) D7 Parameter D6 D5 D4 RDWy Read 74h 7400h 00h Wy9 Wy8 Wy7 Wy6 NOTE: “-“ Don’t care Description This command returns the Wy bit (Wy[9:2]) of white color characteristic. Restriction - D3 Wy5 D2 Wy4 D1 Wy3 D0 Wy2 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDWy(74h) Send Parameter Wy[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 336 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDRGLB: Read Red/Green Low Bits (7500h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDRGLB Read 75h 7500h 00h Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0 NOTE: “-“ Don’t care This command returns the lowest bits of red and green color characteristic. Description Red: Rx and Ry Green: Gx and Gy Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDRGLB(75h) Send Parameter Rx[1:0], Ry[1:0] Gx[1:0], Gy[1:0] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 337 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDRx: Read Rx (7600h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDRx Read 76h 7600h 00h Rx9 Rx8 Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 NOTE: “-“ Don’t care Description This command returns the Rx bit (Rx[9:2]) of red color characteristic. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDRx(76h) Send Parameter Rx[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 338 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDRy: Read Ry (7700h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDRy Read 77h 7700h 00h Ry9 Ry8 Ry7 Ry6 Ry5 Ry4 Ry3 Ry2 NOTE: “-“ Don’t care Description This command returns the Ry bit (Ry[9:2]) of red color characteristic. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDRy(77h) Send Parameter Ry[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 339 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDGx: Read Gx (7800h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDGx Read 78h 7800h 00h Gx9 Gx8 Gx7 Gx6 Gx5 Gx4 Gx3 Gx2 NOTE: “-“ Don’t care Description This command returns the Gx bit (Gx[9:2]) of green color characteristic. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDGx(78h) Send Parameter Gx[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 340 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDGy: Read Gy (7900h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDGy Read 79h 7900h 00h Gy9 Gy8 Gy7 Gy6 Gy5 Gy4 Gy3 Gy2 NOTE: “-“ Don’t care Description This command returns the Gy bit (Gy[9:2]) of green color characteristic. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDGy(79h) Send Parameter Gy[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 341 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDBALB: Read Blue/AColor Low Bits (7A00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDBALB Read 7Ah 7A00h 00h Bx1 Bx0 By1 By0 Ax1 Ax0 Ay1 Ay0 NOTE: “-“ Don’t care This command returns the lowest bits of blue and A color characteristic. Description Blue: Bx and By A: Ax and Ay Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDBALB(7Ah) Send Parameter Bx[1:0], By[1:0] Ax[1:0], Ay[1:0] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 342 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDBx: Read Bx (7B00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDBx Read 7Bh 7B00h 00h Bx9 Bx8 Bx7 Bx6 Bx5 Bx4 Bx3 Bx2 NOTE: “-“ Don’t care Description This command returns the Bx bit (Bx[9:2]) of blue color characteristic. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDBx(7Bh) Send Parameter Bx[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 343 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDBy: Read By (7C00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDBy Read 7Ch 7C00h 00h By9 By8 By7 By6 By5 By4 By3 By2 NOTE: “-“ Don’t care Description This command returns the By bit (By[9:2]) of blue color characteristic. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDBy(7Ch) Send Parameter By[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 344 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDAx: Read Ax (7D00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDAx Read 7Dh 7D00h 00h Ax9 Ax8 Ax7 Ax6 Ax5 Ax4 Ax3 Ax2 NOTE: “-“ Don’t care Description This command returns the Ax bit (Ax[9:2]) of A color characteristic. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDAx(7Dh) Send Parameter Ax[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 345 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDAy: Read Ay (7E00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDAy Read 7Eh 7E00h 00h Ay9 Ay8 Ay7 Ay6 Ay5 Ay4 Ay3 Ay2 NOTE: “-“ Don’t care Description This command returns the Ay bit (Ay[9:2]) of A color characteristic. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Flow Chart RDAy(7Eh) Send Parameter Ay[9:2] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 346 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDDBS: Read DDB Start (A100h~A104h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 A100h 00h SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 A101h 00h SID15 SID14 SID13 SID12 SID11 SID10 SID9 SID8 RDDDBS Read A1h A102h 00h MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 A103h 00h MID15 MID14 MID13 MID12 MID11 MID10 MID9 MID8 A104h 00h 1 1 1 1 1 1 1 1 NOTE: “-“ Don’t care Description This command returns the supplier identification and display module mode/revision information. Note: This information is not the same what “Read ID1 (DAh)”, “Read ID2 (DBh)” and “Read ID3 (DCh)” commands are returning. Note: Parameter 0xFF is an “Exit Code”, this means that there is no more data in the DDB block. This read sequence can be interrupted by any command and it can be continued by “Read DDB Continue (A8h)” command when the first parameter, what has been transferred, is the parameter, which has not been sent e.g. RDDDBS => 1st parameter has been sent => 2nd parameter has been sent=> interrupt => RDDDBC => 3rd parameter of the RDDDBS has been sent. SID[7:0]: LS byte of Supplier ID SID[15:8]: MS byte of Supplier ID MID[7:0]: LS byte of Supplier Elective Data such as model number MID[15:8]: MS byte of Supplier Elective Data such as model number Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h 10/28/2011 347 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Flow Chart PRELIMINARY NT35510 RDDDBS(A1h) Send Parameter S[7:0] Send Parameter S[15:8] Send Parameter MR[7:0] Send Parameter MR[15:8] Send Parameter FFh Host Driver Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 348 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDDDBC: Read DDB Continue (A800h~A804h) Inst / Para RDDDBC R/W Read Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 A800h 00h SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 A801h 00h SID15 SID14 SID13 SID12 SID11 SID10 SID9 SID8 A8h A802h 00h MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 A803h 00h MID15 MID14 MID13 MID12 MID11 MID10 MID9 MID8 A804h 00h 1 1 1 1 1 1 1 1 NOTE: “-“ Don’t care Description This command returns the supplier identification and display module mode/revision information from the point where RDDDBS command was interrupted by an other command. Note: Parameter 0xFF is an “Exit Code”, this means that there is no more data in the DDB block. Note: For use example, 1. Set maximum return packet size=3 2. Read 0xA1, return 3 bytes SID[7:0], SID[15:8], MID[7:0] 3. Read 0xA8, return 2 bytes MID[15:8] and 0xFF Restriction A Read DDB Start command (RDDDBS) should be executed at least once before a Read DDB Continue command (RDDDBC) to define the read location. Otherwise, data read with a Read DDB Continue command is undefined. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h 10/28/2011 349 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Flow Chart PRELIMINARY RDDDBC(A8h) RDDDBS Data D1[7:0], D2[7:0], ..., Dn[7:0] NT35510 Legend Command Parameter Display Action Mode Sequential transfer 10/28/2011 350 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDFCS: Read First Checksum (AA00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDFCS Read AAh AA00h 00h FCS7 FCS6 FCS5 FCS4 FCS3 FCS2 FCS1 FCS0 NOTE: “-“ Don’t care This command returns the first checksum what has been calculated from “User Command Set” area Description registers (not include “Manufacture Command Set) and the frame memory after the write access to those registers and/or frame memory has been done. Restriction It will be necessary to wait 150ms after there is the last write access on “User Command Set” area registers before there can read this checksum value. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDFCS(AAh) Send Parameter FCS[7:0] Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 351 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDCCS: Read Continue Checksum (AF00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDCCS Read AFh AF00h 00h CCS7 CCS6 CCS5 CCS4 CCS3 CCS2 CCS1 CCS0 NOTE: “-“ Don’t care This command returns the continue checksum what has been calculated continuously after the first Description checksum has calculated from “User Command Set” area registers and the frame memory after the write access to those registers and/or frame memory has been done. Restriction It will be necessary to wait 300ms after there is the last write access on “User Command Set” area registers before there can read this checksum value in the first time. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDCCS(AFh) Send Parameter CCS[7:0] Default Value 00h 00h 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 352 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDID1: Read ID1 Value (DA00h) Inst / Para R/W Address MIPI Others D[15:8] (Non-MIPI) D7 Parameter D6 D5 D4 RDID1 Read DAh DA00h 00h ID17 ID16 ID15 ID14 NOTE: “-“ Don’t care Description This read byte identifies the TFT LCD module’s manufacture ID. Restriction - D3 ID13 D2 ID12 D1 ID11 D0 ID10 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDID1(DAh) Send Parameter ID1[7:0] Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 353 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDID2: Read ID2 Value (DB00h) Inst / Para R/W Address Parameter MIPI Others D[15:8] (Non-MIPI) D7 D6 D5 D4 D3 D2 D1 D0 RDID2 Read DBh DB00h 00h ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 NOTE: “-“ Don’t care This read byte is used to track the TFT LCD module/driver version. It is changed each time a version is Description made to the display, material or construction specifications. Parameter Range: ID2 = 80h to FFh Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value After MTP Before MTP MTP Value 80h MTP Value 80h MTP Value 80h Flow Chart RDID2(DBh) Send Parameter ID2[7:0] Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 354 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 RDID3: Read ID3 Value (DC00h) Inst / Para R/W Address MIPI Others D[15:8] (Non-MIPI) D7 Parameter D6 D5 D4 RDID3 Read DCh DC00h 00h ID37 ID36 ID35 ID34 NOTE: “-“ Don’t care Description This parameter read byte identifies the TFT LCD module/driver. Restriction - D3 ID33 D2 ID32 D1 ID31 D0 ID30 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset RDID3(DCh) Send Parameter ID3[7:0] Default Value After MTP Before MTP MTP Value 00h MTP Value 00h MTP Value 00h Legend Host Driver Command Parameter Display Action Mode Sequential transfer 10/28/2011 355 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7 SPECIFICATIONS 7.1 Absolute Maximum Ratings Item Supply voltage Supply voltage (Logic) Symbol VDDA, VDDB, VDDR,VDDAM VDDI Rating Unit -0.3 ~ +5.5 V - 0.3 ~ +5.5 V Supply voltage (Logic) Supply voltage (Digital) Supply voltage (MV) Supply voltage (HV) DIOPWR DVDD AVDD-VSS AVEE-VSS VGH-VSS VGLX-VSS VGH-VGLX (VGHO-VGLO) -0.3 ~ +2.0 V -0.3 ~ +2.0 V -0.3 ~ +6.6 V +0.3 ~ -6.6 V -0.3 ~ +19.5 +0.3 ~ -19.5 V -0.3 ~ +33 Logic Input voltage range VIN - 0.3 ~ VDDI + 0.3 V Logic Output voltage range VO - 0.3 ~ VDDI + 0.3 V HSSI_CLK_P/N, Differential Input Voltage HSSI_DATA0_P/N, -0.3 ~ +1.8 V HSSI_DATA1_P/N Operating temperature range TOPR -40 ~ +85 ºC Storage Temperature range TSTG -55 ~ +125 ºC NOTE: 1. VSS means VSSA, VSSR, VSSB, AVSS and VSSAM. 2. If the absolute maximum rating of even is one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. 7.2 ESD Protection Level Model Human Body Model Machine Model Test Condition C = 100 pF, R = 1.5 kΩ C = 200 pF, R = 0.0 Ω Protection Level Unit > 2500 V > 250 V 7.3 Latch-Up Protection Level The device will not latch up at trigger current levels less than ±200 mA. 7.4 Light Sensitivity The operation of the IC will not be materially altered by incident light. 10/28/2011 356 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.5 DC Characteristics 7.5.1 Basic Characteristics Parameter Symbol Analog Operating voltage Logic Operating voltage VDD VDDI VDDIL Logic High level input voltage Logic Low level input voltage Logic High level output voltage VIH VIL VOH Logic Low level output voltage Logic High level leakage (Except MIPI/MDDI) Logic Low level leakage (Except MIPI/MDDI) Logic High level leakage (MIPI/MDDI) Logic Low level leakage (MIPI/MDDI) VOL ILIH ILIL ILIH ILIL AVDD booster voltage AVEE booster voltage VCL booster voltage VGH booster voltage AVDD AVEE VCL VGH VGLX booster voltage Voltage difference between VGH and VGLX Oscillator tolerance VGLX VGHL ∆OSC Gamma reference voltage Output offset voltage Output deviation voltage VGMP VGSP VGMN VGSN VOFSET Vdev Conditions Specification Unit MIN TYP MAX Power & Operation Voltage Operating Voltage 2.3 3.7 4.8 V I/O supply voltage 1.65 1.8 3.3 V I/O supply voltage 1.1 1.2 1.3 V Input / Output VDDI=1.65~3.3V 0.7 VDDI - VDDI V VDDI=1.65~3.3V VSSI - 0.3 VDDI V VDDI=1.65~3.3V IOH = -1.0mA 0.8 VDDI - VDDI V VDDI=1.65~3.3V IOL = +1.0mA VSSI - 0.2 VDDI V Vin=0~VDDI - - 1 µA Vin=0~VDDI -1 - - µA Vin=0~VDDAM - - 1 µA Vin=0~VDDAM -1 - DC/DC Converter Operation - 4.5 - - -6.5 - - -2.5 - AVDD - +VDDB - - AVEE - +VCL |VGH-VGLX| - - 25 ºC -5 - Source Driver - 3.0 - - 0.0 - - -6.3 - - -3.7 - - - - Sout≥4.0V, Sout≥1.0V - 20 1.0V=4.0V, Sout<=1.0V |(S0, S1, S2, …. , S1440) – Average (S0, S1, S2, …. , S1440)| <= 20mV -When 4.0V>Sout>1.0V |(S0, S1, S2, …. , S1440) – Average (S0, S1, S2, …. , S1440)| <= 10mV -Sout=V0~V255 |STarget – Average (S0, S1, S2, …. , S1440)| <= 45mV S1= S2= S3= 3.949V 3.949V 3.946V S1439= S1440= 3.953V 3.956V 3.95V 3.95V 3.95V 3.95V 3.95V Fig. 7.5.2 Source output deviation 10/28/2011 358 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.5.2 MIPI Characteristics 7.5.2.1 DC CHARACTERISTICS FOR DSI LP MODE Parameter Symbol Conditions Specification MIN TYP MAX UNIT Logic high level input voltage VIHLPCD LP-CD 450 - 1350 mV Logic low level input voltage VILLPCD LP-CD 0 - 200 mV Logic high level input voltage VIHLPRX LP-RX (CLK, D0, D1) 880 - 1350 mV Logic low level input voltage VILLPRX LP-RX (CLK, D0, D1) 0 - 550 mV Logic low level input voltage VILLPRXULP LP-RX (CLK ULP mode) 0 - 300 mV Logic high level output voltage VOHLPTX LP-TX (D0) 1.1 - 1.3 V Logic low level output voltage VOLLPTX LP-TX (D0) -50 - 50 mV Logic high level input current IIH LP-CD, LP-RX - - 10 μA Logic low level input current IIL LP-CD, LP-RX -10 - - μA Input pulse rejection SGD DSI-CLK+/-, DSI-Dn+/- (Note 3) - - 300 Vps Note 1) VDDI=1.65~3.3V, VDD=2.3 to 4.8V, VSSI=VSS=VSSAM=0V, Ta=-30 to 70 ºC (to +85 ºC no damage). VDD means VDDAM, VDDA, VDDR, VDDB and VSS means VSSAM, VSSA, VSSR, VSSB, AVSS. Note 2) DSI high speed is off. Note 3) Peak interference amplitude max. 200mV and interference frequency min. 450MHz. SGD SGD Input Fig. 7.5.3 Spike/Glitch rejection-DSI VIHLPCD, VIHLPRX VILLPCD, VILLPRX, VILLPRXULP 10/28/2011 359 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.5.2.2 DC CHARACTERISTICS FOR DSI HS MODE Parameter Symbol Conditions Specification MIN TYP MAX UNIT Input voltage common VCMCLK DSI-CLK+/-, DSI-Dn+/- (Note2, 3) 70 - 330 mV mode range VCMDATA Input voltage common mode variation (≤ 450MHz) VCMRCLKL VCMRDATAL DSI-CLK+/-, DSI-Dn+/- (Note 4) -50 - 50 mV Input voltage common mode variation (≥ 450MHz) VCMRCLKM VCMRDATAM DSI-CLK+/-, DSI-Dn+/- - - 100 mV Low-level differential input voltage threshold VTHLCLK VTHLDATA DSI-CLK+/-, DSI-Dn+/- -70 - - mV High-level differential input voltage threshold VTHHCLK VTHHDATA DSI-CLK+/-, DSI-Dn+/- - - 70 mV Single-ended input low voltage VILHS DSI-CLK+/-, DSI-Dn+/- (Note 3) -40 - - mV Single-ended input high voltage VIHHS DSI-CLK+/-, DSI-Dn+/- (Note 3) - - 460 mV Differential input termination resistor RTERM DSI-CLK+/-, DSI-Dn+/- 80 100 125 Ω Single-ended threshold voltage for termination VTERM-EN DSI-CLK+/-, DSI-Dn+/- - - 450 mV enable Termination capacitor CTERM DSI-CLK+/-, DSI-Dn+/- - - 14 pF Note 1) VDDI=1.65~3.3V, VDD=2.3 to 4.8V, VSSI=VSS=VSSAM=0V, Ta=-30 to 70 ºC (to +85 ºC no damage). VDD means VDDAM, VDDA, VDDR, VDDB and VSS means VSSAM, VSSA, VSSR, VSSB, AVSS. Note 2) Includes 50mV (-50mV to 50mV) ground difference. Note 3) Without VCMRCLKM / VCMRDATAM . Note 4) Without 50mV (-50mV to 50mV) ground difference. Note 5) Dn=D0 and D1 "1" (HS-1) "0" (HS-0) "1" (HS-1) 0V reference VTHHCLK VTHHDATA VTHLCLK VTHLDATA DSI-CLK+/-, DSI-D0+/- Undefined Undefined DSI-CLK+, DSI-D0+ VCMRCLKM VCMRDATAM DSI-CLK-, DSI-D0- VSS } VCMCLK VCMDATA } VCMRCLKL VCMRDATAL DSI-CLK+, DSI-D0+ + RTERM DSI-CLK-, DSI-D0- - HS/LP RTERMPOS RTERMNEG CTERM RTERM = RTERMPOS + RTERMNEG RTERMPOS = RTERMNEG + RTERM/2 Fig. 7.5.4 Differential voltage range, termination resistor and Common mode voltage 10/28/2011 360 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.5.3 MDDI Characteristics Parameter Symbol Conditions Specification MIN TYP MAX UNIT Differential input “High” level voltage VIT+offset VT=125mV (MDDI_DATA_P/M) - 100 125 mV (hibernation wake-up) Differential input “Low” level voltage VIT-offset VT=125mV (MDDI_DATA_P/M) 75 100 - mV (hibernation wake-up) Differential input “High” VT=0mV level voltage VIT+ (MDDI_STB_P/M, MDDI_DATA_P/M) - 0 50 mV Differential input “Low” VT=0mV level voltage VIT- (MDDI_STB_P/M, MDDI_DATA_P/M) -50 0 - mV Current consumption in Data Transfer ITrans VDDI=1.8V, VDDAM=2.85V, 1/Tbit=384Mbps, Ta=25ºC, In Video Stream Packet Transfer - TBD TBD mA Terminal impedance Zt - 80 - 125 ohm Note 1) VDDI= 1.65~3.3V, VDD=2.3 to 4.8V, VSSI=VSS=VSSAM=0V, Ta=-30 to 70 ºC (to +85 ºC no damage). VDD means VDDAM, VDDA, VDDR, VDDB and VSS means VSSAM, VSSA, VSSR, VSSB, AVSS 10/28/2011 361 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.5.4 Current Consumption in Standby Mode and DSTB Mode Parameter Symbol Conditions Specification MIN TYP MAX UNIT VDDI=1.8V, Sleep in mode (Note 1) I total VDDA=VDDB=VDDR=VDDAM=2.8V - 150 300 μA (IVPNL + IVDDI) SRAM Off, 864 lines, ta = 30ºC Deep standby mode (Note 2) VDDI=1.8V, I total VDDA=VDDB=VDDR=VDDAM=2.8V - 20 (IVPNL + IVDDI) SRAM Off, 864 lines, ta = 30 ºC 35 μA Note 1) For sleep in mode, MDDI is in hibernation mode, MIPI in stop state (LP11).RGB and MCU IF also included in it. Note 2) All IF included. 10/28/2011 362 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY 7.6 AC Characteristics 7.6.1 Parallel Interface Characteristics (80-Series MCU) NT35510 CSX D/CX WRX RDX D[23:0] VIH VIL tCS VIH V IL tAST VIH VIL tWRL tRC/tRCFM tAHT tRDH /tRDHFM tDST tDHT VIH VIL tWC t WRH tAHT tRDL /t RDLFM VIH V IL tRAT/t RATFM tODH VOH VOL VOH VOL VIH VIL Fig. 7.6.1 Parallel interface characteristics (80-Series) (VSS=VSSI=DVSS=0V, VDDI=1.65V to 3.3V, VDD=2.3V to 4.8V,Ta = -30 to 70°C) Signal Symbol Parameter MIN MAX Unit Description tWC Write cycle 33 - ns WRX tWRH Control pulse “H” duration 15 - ns tWRL Control pulse “L” duration 15 - ns tRC Read cycle (ID) 160 - ns RDX(ID) tRDH Control pulse “H” duration (ID) 90 - ns When read ID data tRDL Control pulse “L” duration (ID) 45 - ns RDX(FM) tRCFM tRDHFM tRDLFM Read cycle (FM) Control pulse “H” duration (FM) Control pulse “L” duration (FM) 400 - ns When read from frame 250 - ns memory 150 - ns D/CX Address setup time (Write) tAST Address setup time (Read) 0 - ns 10 - ns tAHT Address hole time 2 - ns tDST Data setup time 15 - ns tDHT Data hold time 10 - ns D[17:0] tRAT Read access time (ID) - 40 ns tRATFM Read access time (FM) - 150 ns tODH Output disable time 5 - ns Note 1) VDDI=1.65 to 3.3V, VDD=2.3 to 4.8V, VSS=VSSI=DVSS=0V, Ta=-30 to 70 ºC (to +85 ºC no damage) VDD means VDDA, VDDR, VDDB and VSS means VSSA, VSSR, VSSB Note 2) The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 20% and 80% of VDDI for Input signals. 10/28/2011 363 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7.6.2 Serial Interface Characteristics PRELIMINARY NT35510 CSX SCL SDA (SDI) SDA (SDO) tCSS tSCYCW / tSCYCR tCSH VIH t SLW / t SLR V IL tSHW / tSHR tSDS tSDH tf tr t ACC tOH t CHW Fig. 7.6.2 3-pin serial interface characteristics (VSS=VSSI=DVSS=0V, VDDI=1.65V to 3.3V, VDD=2.3V to 4.8V,Ta = -30 to 70°C) Signal Symbol Parameter MIN MAX Unit Description tSCYCW Serial clock cycle (Write) 100 - ns tSHW SCL “H” pulse width (Write) 40 - ns tSLW SCL “L” pulse width (Write) 40 - ns tSCYCR Serial clock cycle (Read GRAM) 300 - ns SCL tSHR SCL “H” pulse width (Read GRAM) 140 - ns tSLR SCL “L” pulse width (Read GRAM) 140 - ns tSCYCR Serial clock cycle (Read ID) 300 - ns tSHR SCL “H” pulse width (Read ID) 140 - ns tSLR SCL “L” pulse width (Read ID) 140 - ns tSDS Data setup time 20 - ns SDI (SDO) tSDH Data hold time tACC Access time 20 - ns - 120 ns tOH Output disable time 5 - ns tCHW Chip select “H” pulse width 45 - ns CSX tCSS Chip select setup time 20 - ns tCSH Chip select hold time 50 - ns Note 1) VDDI=1.65 to 3.3V, VDD=2.3 to 4.8V, VSS=VSSI=DVSS=0V, Ta=-30 to 70 ºC (to +85 ºC no damage) VDD means VDDA, VDDR, VDDB and VSS means VSSA, VSSR, VSSB Note 2) The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. 10/28/2011 364 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.6.3 I2C Bus Timing Characteristics TStaHd TStaSu TCKL TCKH I2C_SCL Tr Tf TStpSu TBusFree I2C_SDA TDatHd TDatSu START STOP Fig. 7.6.3 I2C Bus Operation (VSS=VSSI=DVSS=0V, VDDI=1.65V to 3.3V, VDD=2.3V to 4.8V,Ta = -30 to 70°C) Signal Symbol Parameter MIN MAX Unit Description TCKL+TCKL Working frequency - 400 KHz I2C_SCL TCKL I2C clock low 1300 - ns TCKH I2C clock high 600 - ns Tr I2C data rising time - 300 ns Tf I2C data falling time - 300 ns TDatHd I2C data hold time 0 900 ns I2C_SDA TDatSu TStaHd I2C data setup time I2C start condition hold time 100 - ns 600 - ns TStaSu I2C start condition setup time 600 - ns TStpSu I2C stop condition setup time 600 - ns TBusFree I2C bus free time 1300 - ns Note 1) VDDI=1.65 to 3.3V, VDD=2.3 to 4.8V, VSS=VSSI=DVSS=0V, Ta=-30 to 70 ºC (to +85 ºC no damage) VDD means VDDA, VDDR, VDDB and VSS means VSSA, VSSR, VSSB 10/28/2011 365 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7.6.4 RGB Interface Characteristics PRELIMINARY NT35510 VS HS DE PCLK D0~D23 V IH VIL tVSYNS V IH VIL tHVPD t HSYNS VIH VIL t DCSS t DCYC t VSYNH t HSYNH t DCSH tDLW tDDS t DHW tDDH Fig. 7.6.4 RGB interface characteristics (VSS=VSSI=DVSS=0V, VDDI=1.65V to 3.3V, VDD=2.3V to 4.8V,Ta = -30 to 70°C) Signal Symbol Parameter MIN TYP MAX Unit Description VS tVSYNS VSYNC setup time tVSYNH VSYNC hold time 10 - 10 - - ns - ns tHSYNS HSYNC setup time 10 - - ns HS tSCYCR HSYNC hold time 10 - - ns tHVPD HSYNC to VSYNC falling edge 0 - - ns PCLK tDCYC tDLW tDHW PCLK cycle time PCLK ″L″ pulse width PCLK ″H″ pulse width 33 - 125 ns 11 - - ns 11 - - ns fDFREQ PCLK frequency 8 - 30 MHz DE tDCSS DE setup time tDCSH DE hold Time 10 - 10 - - ns - ns D0~D23 tDDS RGB Data setup time tDDH RGB Data hold time 10 - 10 - - ns - ns Note 1) VDDI=1.65 to 3.3V, VDD=2.3 to 4.8V, VSS=VSSI=DVSS=0V, Ta=-30 to 70 ºC (to +85 ºC no damage) VDD means VDDA, VDDR, VDDB and VSS means VSSA, VSSR, VSSB Note 2) The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. 10/28/2011 366 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.6.5 MIPI DSI Timing Characteristics 7.6.5.1 HIGH SPEED MODE (VSS=VSSI=DVSS=0V, VDDI=1.65V to 3.3V, VDD=2.3V to 4.8V,Ta = -30 to 70°C) Signal Symbol DSI-CLK+/- 2xUIINST DSI-CLK+/- UIINSTA UIINSTB DSI-Dn+/- tDS DSI-Dn+/- tDH DSI-CLK+/- tDRTCLK DSI-Dn+/- tDRTDATA DSI-CLK+/- tDFTCLK DSI-Dn+/- tDFTDATA Note) Dn = D0 and D1. Parameter Double UI instantaneous UI instantaneous halfs Data to clock setup time Data to clock hold time Differential rise time for clock Differential rise time for data Differential fall time for clock Differential fall time for data MIN 4 2 0.15xUI 0.15xUI 150 150 150 150 TYP - - - MAX 25 12.5 0.3xUI 0.3xUI 0.3xUI 0.3xUI Unit Description ns ns UI = UIINSTA = UIINSTB ps ps ps ps ps ps DSI-CLK+ DSI-D0+ tDS tDH tDS tDH DSI-CLK- UIINSTA UIINSTB 2xUIINST DSI-D0DSI-CLK+ DSI-CLKFig. 7.6.4 DSI clock channel timing 0V reference tDFTCLK tDFTDATA tDRTCLK tDRTDATA 20% 60% DSI-CLK+/-, DSI-D0+/- Full HS Swing Voltage 20% Fig. 7.6.5 Rising and fall time on clock and data channel 10/28/2011 367 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.6.5.2 LOW POWER MODE (VSS=VSSI=DVSS=0V, VDDI=1.65V to 3.3V, VDD=2.3V to 4.8V,Ta = -30 to 70°C) Signal DSI-D0+/- DSI-D0+/DSI-D0+/DSI-D0+/DSI-D0+/- Symbol TLPXM TLPXD TTA-SURED TTA-GETD TTA-GOD Parameter Length of LP-00, LP-01, LP-10 or LP-11 periods MPU  Display Module Length of LP-00, LP-01, LP-10 or LP-11 periods Display Module  MPU Time-out before the MPU start driving Time to drive LP-00 by display module Time to drive LP-00 after turnaround request - MPU MIN TYP MAX Unit Description 50 - 75 ns Input 50 - 75 ns Output TLPXD - 2xTLPXD ns Output 5xTLPXD - - ns Input 4xTLPXD - - ns Output DSI-D0+ DSI-D0- MPU is Controlling TLPXM TLPXM TLPXM Control Change Display Module is Controlling TTA -SURED TLPXD TLPXD LP-11 LP-10 LP-00 LP-10 LP-00 LP-00 TTA -DETD LP-00 LP-10 LP-11 DSI-D0+ DSI-D0- Fig. 7.6.6 Bus Turnaround (BAT) from MPU to display module Timing DSI-D0+ DSI-D0- Display Module is Controlling TLPXD TLPXD TLPXD Control Change TTA -GOD TLPXM TLPXM LP-11 LP-10 LP-00 LP-10 LP-00 LP-00 LP-00 LP-10 LP-11 DSI-D0+ DSI-D0- Fig. 7.6.7 Bus Turnaround (BAT) from display module to MPU Timing 10/28/2011 368 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.6.5.3 DSI BURSTS (VSS=VSSI=DVSS=0V, VDDI=1.65V to 3.3V, VDD=2.3V to 4.8V,Ta = -30 to 70°C) Signal Symbol DSI-Dn+/- TLPX DSI-Dn+/- THS-PREPARE DSI-Dn+/- THS-TERM-EN DSI-Dn+/DSI-Dn+/- THS-SKIP THS-EXIT DSI-Dn+/- THS-TRAIL DSI-CLK+/- TCLK-POS DSI-CLK+/- TCLK-TRAIL DSI-CLK+/- THS-EXIT DSI-CLK+/- TCLK-PREPARE DSI-CLK+/- TCLK-TERM-EN DSI-CLK+/- TCLK-PREPARE + TCLK-ZERO DSI-CLK+/- TCLK-PRE Note) Dn = D0 and D1. Parameter MIN TYP MAX Low Power Mode to High Speed Mode Timing Length of any low power state period 50 - - Time to drive LP-00 to prepare 40+4xUI - for HS transmission 85+6xUI Time to enable data receiver line termination measured from - - 35+4xUI when Dn crosses VILMAX High Speed Mode to Low Power Mode Timing Time-out at display module to ignore transition period of EoT 40 - 55+4xUI Time to drive LP-11 after HS burst 100 - - Time to drive flipped differential state after last payload data bit 60+4xUI - - of a HS transmission burst High Speed Mode to/from Low Power Mode Timing Time that the MPU shall continue sending HS clock after 60+128x the last associated data lane UI - - has transition to LP mode Time to drive HS differential state after last payload clock bit 60 - - of a HS transmission burst Time to drive LP-11 after HS burst 100 - - Time to drive LP-00 to prepare for HS transmission 38 - 95 Time-out at clock lane display module to enable HS - - 38 transmission Minimum lead HS-0 drive period before starting clock 300 - - Time that the HS clock shall be driven prior to any associated data lane beginning the 8xUI - - transition from LP to HS mode Unit Description ns Input ns Input ns Input ns Input ns Input ns Input ns Input ns Input ns Input ns Input ns Input ns Input ns Input 10/28/2011 369 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 DSI_CLK+ DSI_CLK- DSI-D0+ V IHLPRX (Min) V ILLPRX (Max) TLPX THS- PREPARE THS- ZERO THS- SYNC Disconnect Terminator DSI-D0- THS- TERM-EN LP-11 LP-01 THS- SETTLE LP-00 Low Power Mode, Disable Rx Line Termination Capture 1st Data Bit THS- SKIP TEOT LP-11 THS- TRAIL THS- EXIT High Speed Mode, Enable Rx Line Termination Low Power Mode, Disable Rx Line Termination Fig. 7.6.8 Data lanes-Low Power Mode to/from High Speed Mode Timing VIHLPRX (Min) V ILLPRX (Max) DSI_CLK+ DSI_CLK- Disconnect Terminator V IHLPRX (Min) V ILLPRX (Max) DSI-D0+ DSI-D0- THS- SKIP TCLK-POST HS-0/1 T EoT TCLK-MISS TCLK-SETTLE TCLK-TERM-EN TCLK-TRAIL HS-0 T HS-EXIT LP-11 TLPX TCLK-PREPARE TCLK-ZERO LP-01 LP-00 HS-0 T CLK-PRE HS-0/1 Fig. 7.6.9 Clock lanes- High Speed Mode to/from Low Power Mode Timing T LPX THS-PREPARE 10/28/2011 370 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.6.6 MDDI Timing Characteristics (VSS=VSSI=DVSS=0V, VDDI=1.65V to 3.3V, VDD=2.3V to 4.8V,Ta = -30 to 70°C) Signal Symbol Parameter MIN TYP MAX Unit Description MDDI_STB_P/M MDDI_DATA_P/M 1/Tbit Data transfer rate - 384 450 Mbps MDDI_STB_P/M |Tskew-pair| Differential transfer input skew - MDDI_DATA_P/M - 0.05 ns MDDI_STB_P/M MDDI_DATA_P/M |Tskew-data| Data/Strobe input skew - - 0.3 ns Note) MDDI_DATA_P/M = MDDI_DATA0_P/M and MDDI_DATA1_P/M. MDDI_DATA_P / MDDI_STB_P Tskew-pair Tskew-pair MDDI_DATA_M / MDDI_STB_M Fig. 7.6.10 Skew between MDDI positive and negative signal pair MDDI_DATA_P/M MDDI_STB_P/M Tskew-data Tskew-data Fig. 7.6.11 Skew between MDDI_DATA_P/M and MDDI_STB_P/M 10/28/2011 371 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 7.6.7 Reset Input Timing Shorter than 5µs RESX Internal Status Normal Operation t RESW t REST Resetting Initial Condition (Default for H/W reset) Fig. 7.6.12 Reset input timing (VSS=VSSI=DVSS=0V, VDDI=1.65V to 3.3V, VDD=2.3V to 4.8V,Ta = -30 to 70°C) Signal Symbol Parameter tRESW Reset ″L″ pulse width (Note 1) MIN TYP MAX Unit 10 - - μs Description When reset applied RESX - - 5 ms during Sleep In Mode tREST Reset complete time (Note 2) When reset applied - - 120 ms during Sleep Out Mode Note 1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below. RESX Pulse Action Shorter than 5µs Reset Rejected Longer than 10µs Reset Between 5µs and 10µs Reset Start Note 2) During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In–mode) and then return to Default condition for H/W reset. Note 3) During Reset Complete Time, values in OTP memory will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX. Note 4) Spike Rejection also applies during a valid reset pulse as shown below: Note 5) It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120msec 10/28/2011 372 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 8 REFERENCE APPLICATIONS 8.1 Microprocessor Interface The display, which is using 80-series MPU interface, is connected to the MPU as it is illustrated below. MPU Interface Block VSSAM RESX TE WRX RDX CSX D/CX D7 to D0 VSSI Driver IC IM[3:0]=0000 HSSI_DATA1_P/N HSSI_DATA0_P/N HSSI_CLK_P/N RESX TE WRX RDX CSX D/CX D7 to D0 SDO PCLK, DE, VS, HS, SDI, D23 to D8 Fig. 8.1.1 Interfacing for 80-series 8-bit MPU by Connecting IM[3:0]=”0000” MPU Interface Block VSSAM RESX TE WRX RDX CSX D/CX D15 to D0 VSSI Driver IC IM[3:0]=0001 HSSI_DATA1_P/N HSSI_DATA0_P/N HSSI_CLK_P/N RESX TE WRX RDX CSX D/CX D15 to D0 SDO PCLK, DE, VS, HS, SDI, D23 to D16 Fig. 8.1.2 Interfacing for 80-series 16-bit MPU by Connecting IM[3:0]=”0001” 10/28/2011 373 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 MPU Interface Block VSSAM RESX TE WRX RDX CSX D/CX D17 to D0 VSSI Driver IC IM[3:0]=0010 HSSI_DATA1_P/N HSSI_DATA0_P/N HSSI_CLK_P/N RESX TE WRX RDX CSX D/CX D17 to D0 SDO PCLK, DE, VS, HS, SDI, D23 to D18 Fig. 8.1.3 Interfacing for 80-series 18-bit MPU by Connecting IM[3:0]=”0010” MPU Interface Block VSSAM RESX TE WRX RDX CSX D/CX D23 to D0 VSSI Driver IC IM[3:0]=0010 HSSI_DATA1_P/N HSSI_DATA0_P/N HSSI_CLK_P/N RESX TE WRX RDX CSX D/CX D23 to D0 SDO PCLK, DE, VS, HS, SDI Fig. 8.1.4 Interfacing for 80-series 24-bit MPU by Connecting IM[3:0]=”0010” Note: Left MVDDL and MVDDA open (not used) when using 80-series MPU interface. 10/28/2011 374 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The display, which is using RGB with 16-bit SPI interface, is connected to the MPU as it is illustrated below. MPU Interface Block VSSAM RESX TE (option) CSX SCL SDA VSSI Driver IC IM[3:0]=X011 HSSI_DATA1_P/N HSSI_DATA0_P/N HSSI_CLK_P/N RESX TE CSX SCL SDI, SDO D/CX, RDX Graphic Controller D23 to D0 D23 to D0 DE, PCLK, VSYNC, HSYNC DE, PCLK, VS, HS Fig. 8.1.5 Interfacing for RGB with SPI by Connecting IM[3:0]=”X011” The display, which is using RGB with I2C interface, is connected to the MPU as it is illustrated below. MPU Interface Block VSSAM RESX TE (option) SCL SDA VSSI Driver IC IM[3:0]=0100 HSSI_DATA1_P/N HSSI_DATA0_P/N HSSI_CLK_P/N RESX TE I2C_SCL I2C_SDA D/CX, RDX, CSX Graphic Controller D23 to D0 D23 to D0 DE, PCLK, VSYNC, HSYNC DE, PCLK, VS, HS Fig. 8.1.6 Interfacing for RGB with I2C by Connecting IM[3:0]=”0100” Note 1. Connecting D23, D22, D15, D14, D7 and D6 to VSSI when using 18-bit/pixel (VIPF[3:0]=”0110”). Connecting D23~D21, D15, D14 and D7~ D5 to VSSI when using 16-bit/pixel (VIPF[3:0]=”0101”). Note 2. Left MVDDL and MVDDA open (not used) when using RGB with SPI interface. Note 3. IM3 is used to select SCL rising or falling edge trigger for 16-bit SPI interface. 10/28/2011 375 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The display, which is using MIPI DSI and the TE line, is connected to the MPU as it is illustrated below. MPU Interface Block RESX TE VSSI DSI-D1+ / DSI-D1DSI-D0+ / DSI-D0DSI-CLK+ / DSI-CLK- Driver IC IM[3:0]=0101 RESX TE D/CX, CSX WRX, RDX SDI, D23 to D0 PCLK, HS, VS, DE SDO HSSI_DATA1_P HSSI_DATA1_N HSSI_DATA0_P HSSI_DATA0_N HSSI_CLK_P HSSI_CLK_N Fig. 8.1.7 Interfacing for MIPI DSI with TE Line by Connecting IM[3:0]=”0101” The display, which is using MIPI DSI without the TE line, is connected to the MPU as it is illustrated below. MPU Interface Block RESX VSSI DSI-D1+ / DSI-D1DSI-D0+ / DSI-D0DSI-CLK+ / DSI-CLK- Driver IC IM[3:0]=0101 RESX TE D/CX, CSX WRX, RDX SDI, D23 to D0 PCLK, HS, VS, DE SDO HSSI_DATA1_P HSSI_DATA1_N HSSI_DATA0_P HSSI_DATA0_N HSSI_CLK_P HSSI_CLK_N Fig. 8.1.8 Interfacing for MIPI DSI without TE Line by Connecting IM[3:0]=”0101” Note1. Bit DSITE should be “1”, the TE line is enabled, when using MIPI with TE line. Note2. Bit DSITE should be “0”, the TE line is disabled, when using MIPI without TE line. The command 35h TEON cannot active the separated TE line. Note3. Connecting HSSI_DATA1_P/N to VSSAM when using 1 data lane application. 10/28/2011 376 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. PRELIMINARY NT35510 The display, which is using MDDI with 16-bit SPI interface, is connected to the MPU as it is illustrated below. MPU Interface Block RESX TE VSSI SCEX SCL SDA MDDI_DATA1_P / M MDDI_DATA0_P / M MDDI_STB_P / M Driver IC IM[3:0]=X110 RESX TE D/CX, WRX, RDX PCLK, HS, VS, DE D23 to D0 SCEX SCL SDI, SDO HSSI_DATA1_P HSSI_DATA1_N HSSI_DATA0_P HSSI_DATA0_N HSSI_CLK_P HSSI_CLK_N Fig. 8.1.9 Interfacing for MDDI with 16-bit SPI by Connecting IM[3:0]=”X110” The display, which is using MDDI with I2C interface, is connected to the MPU as it is illustrated below. MPU Interface Block RESX TE VSSI SCL SDA MDDI_DATA1_P / M MDDI_DATA0_P / M MDDI_STB_P / M Driver IC IM[3:0]=0110 RESX TE D/CX, WRX, RDX SCEX, D23 to D0 PCLK, HS, VS, DE SDO SCL SDI HSSI_DATA1_P HSSI_DATA1_N HSSI_DATA0_P HSSI_DATA0_N HSSI_CLK_P HSSI_CLK_N Fig. 8.1.10 Interfacing for MDDI with I2CI by Connecting IM[3:0]=”0111” Notes: 1. Connecting HSSI_DATA1_P/N to VSSAM when using MDDI Type-I (1 data lane). 2. IM3 is used to select SCL rising or falling edge trigger when using 16-bit SPI interface. 10/28/2011 377 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.2 Connections with Panel RGB PRELIMINARY NT35510 CRL = 0 CRGB = 0 IC Bumps Down S1540 - S721 S720 - S1 P1 RGB P240 P241 - P480 CRL = 1 CRGB = 1 P1 - P240 P241 - P480 S1 - S720 S721 - S1540 IC Bumps Down IC on Bottom Side of Module IC on Top Side of Module NOTES: 1. The scan direction from top to bottom indicated in above figure means the gate control signals in forward direction (CTB = “0”). 2. The relationship between Sn output sequence and CRL/CGM[7:0] is shown below. CGM[7:0] Display Resolution Sn Output Sequence Note C0h 480RGB x 1024 70h 480RGB x 864 CRL=”0” and CRGB=”0”: 6Bh 480RGB x 854 S1(R)S2(G)S3(B)…S1438(R)S1439(G)S1440(B) 50h 480RGB x 800 CRL=”1” and CRGB=”1”: 28h 480RGB x 720 S1440(R)S1439(G)S1438(B)…S3(R)S2(G)S1(B) All S1 to S1440 are used 00h 480RGB x 640 10/28/2011 378 Version 0.8 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.

Top_arrow
回到顶部
EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。