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nrf51822

bluetooth low energy 4.0

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nRF51822 Multiprotocol Bluetooth® low energy/2.4 GHz RF System on Chip Product Specification v3.1 Key Features Applications • 2.4 GHz transceiver • -93 dBm sensitivity in Bluetooth® low energy mode • 250 kbps, 1 Mbps, 2 Mbps supported data rates • TX Power -20 to +4 dBm in 4 dB steps • TX Power -30 dBm Whisper mode • 13 mA peak RX, 10.5 mA peak TX (0 dBm) • 9.7 mA peak RX, 8 mA peak TX (0 dBm) with DC/DC • RSSI (1 dB resolution) • ARM® Cortex™-M0 32 bit processor • 275 μA/MHz running from flash memory • 150 μA/MHz running from RAM • Serial Wire Debug (SWD) • S100 series SoftDevice ready • Memory • 256 kB or 128 kB embedded flash program memory • 16 kB or 32 kB RAM • On-air compatibility with nRF24L series • Flexible Power Management • Supply voltage range 1.8 V to 3.6 V • 4.2 μs wake-up using 16 MHz RCOSC • 0.6 μA at 3 V OFF mode • 1.2 μA at 3 V in OFF mode + 1 region RAM retention • 2.6 μA at 3 V ON mode, all blocks IDLE • 8/9/10 bit ADC - 8 configurable channels • 31 General Purpose I/O Pins • One 32 bit and two 16 bit timers with counter mode • SPI Master/Slave • Low power comparator • Temperature sensor • Two-wire Master (I2C compatible) • UART (CTS/RTS) • CPU independent Programmable Peripheral Interconnect (PPI) • Quadrature Decoder (QDEC) • AES HW encryption • Real Timer Counter (RTC) • Package variants • QFN48 package, 6 x 6 mm • WLCSP package, 3.50 x 3.83 mm • WLCSP package, 3.83 x 3.83 mm • WLCSP package, 3.50 x 3.33 mm • Computer peripherals and I/O devices • Mouse • Keyboard • Multi-touch trackpad • Interactive entertainment devices • Remote control • Gaming controller • Beacons • Personal Area Networks • Health/fitness sensor and monitor devices • Medical devices • Key-fobs + wrist watches • Remote control toys Copyright © 2014 Nordic Semiconductor ASA. All rights reserved. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. nRF51822 Product Specification v3.1 Liability disclaimer Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out of the application or use of any product or circuits described herein. Life support applications Nordic Semiconductor’s products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale. Contact details For your nearest distributor, please visit www.nordicsemi.com. Information regarding product updates, downloads, and technical support can be accessed through your My Page account on our home page. Main office: Otto Nielsens veg 12 7052 Trondheim Norway Phone: +47 72 89 89 00 Fax: +47 72 89 89 89 Mailing address: Nordic Semiconductor P.O. Box 2336 7004 Trondheim Norway RoHS and REACH statement Nordic Semiconductor's products meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substances (RoHS) and the requirements of the REACH regulation (EC 1907/2006) on Registration, Evaluation, Authorization and Restriction of Chemicals. The SVHC (Substances of Very High Concern) candidate list is continually being updated. Complete hazardous substance reports, material composition reports and latest version of Nordic's REACH statement can be found on our website www.nordicsemi.com. Page 2 nRF51822 Product Specification v3.1 Datasheet Status Status Objective Product Specification (OPS) Preliminary Product Specification (PPS) Product Specification (PS) Description This product specification contains target specifications for product development. This product specification contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later. This product specification contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Revision History Date October 2014 Version 3.1 Description Added documentation for the following versions of the chip: • nRF51822-QFAC AA0 • nRF51822-QFAC Ax0 • nRF51822-CDAB AA0 • nRF51822-CDAB Ax0 • nRF51822-CFAC AA0 • nRF51822-CFAC Ax0 (The x in the build codes can be any number between 0 and 9.) Added content: • Section 2.2.2 “CDAB WLCSP ball assignment and functions” on page 13 • Section 9.2 “CDAB WLCSP package” on page 67 • Section 9.4 “CFAC WLCSP package” on page 69 Updated content: • Feature list on the front page. • Section 2.2.3 “CEAA and CFAC WLCSP ball assignment and functions” on page 16 • Section 3.2.1 “Code organization” on page 21 • Section 3.2.2 “RAM organization” on page 21 • Section 3.3 “Memory Protection Unit (MPU)” on page 22 • Section 8.2 “Power management” on page 44 • Section 8.3 “Block resource requirements” on page 48 • Section 8.12 “Analog to Digital Converter (ADC) specifications” on page 60 • Section 10.6 “Code ranges and values” on page 73 • Section 10.7 “Product options” on page 75 Page 3 nRF51822 Product Specification v3.1 Date August 2014 Version 3.0 Description Update to reflect the changes in build code: • nRF51822-QFAA Hx0 • nRF51822-CEAA Ex0 • nRF51822-QFAB Cx0 (The x in the build codes can be any number between 0 and 9.) If you are working with a previous revision of the chip, read version 2.x of the document. Added content: • Section 8.5.3 “Radio current consumption with DC/DC enabled” on page 50 • Section 11.1.1 “PCB layout example” on page 77 Updated content: • Feature list on the front page. • Section 2.1 “Block diagram” on page 10 • Section 3.2.1 “Code organization” on page 21 • Section 3.2.2 “RAM organization” on page 21 • Section 3.3 “Memory Protection Unit (MPU)” on page 22 • Section 3.4 “Power management (POWER)” on page 23 • Section 3.6 “Clock management (CLOCK)” on page 27 • Section 3.8 “Debugger support” on page 30 • Section 4.2 “Timer/counters (TIMER)” on page 32 • Chapter 5 “Instance table” on page 36 • Chapter 7 “Operating conditions” on page 38 • Section 8.1.2 “16 MHz crystal oscillator (16M XOSC)” on page 40 • Section 8.1.3 “32 MHz crystal oscillator (32M XOSC)” on page 41 • Section 8.1.4 “16 MHz RC oscillator (16M RCOSC)” on page 42 • Section 8.1.6 “32.768 kHz RC oscillator (32k RCOSC)” on page 43 • Section 8.1.7 “32.768 kHz Synthesized oscillator (32k SYNT)” on page 43 • Section 8.2 “Power management” on page 44 • Section 8.3 “Block resource requirements” on page 48 • Section 8.4 “CPU” on page 48 • Section 8.5.6 “Radio timing parameters” on page 54 • Section 8.5.7 “Antenna matching network requirements” on page 54 • Section 8.7 “Universal Asynchronous Receiver/Transmitter (UART) specifications” on page 55 • Section 8.8 “Serial Peripheral Interface Slave (SPIS) specifications” on page 56 • Section 8.12 “Analog to Digital Converter (ADC) specifications” on page 60 • Section 8.13 “Timer (TIMER) specifications” on page 61 • Section 8.15 “Temperature sensor (TEMP)” on page 61 • Section 8.22 “Non-Volatile Memory Controller (NVMC) specifications” on page 64 • Section 8.24 “Low Power Comparator (LPCOMP) specifications” on page 65 • Section 9.2 “CDAB WLCSP package” on page 67 • Section 10.7.2 “Development tools” on page 75 • Chapter 11 “Reference circuitry” on page 76 Page 4 nRF51822 Product Specification v3.1 Date October 2013 May 2013 Version 2.0 1.3 Description This version of the document will target the nRF51822 QFAA G0 revision of the chip. If you are working with a previous revision of the chip, read version 1.3 or earlier of the document. Updated the following sections: Key Feature list on the front page, Chapter 1 “Introduction” on page 9, Section 2.1 “Block diagram” on page 10, Section 2.2 “Pin assignments and functions” on page 11, Section 3.2 “Memory” on page 20, Section 3.5 “Programmable Peripheral Interconnect (PPI)” on page 26, Section 3.7 “GPIO” on page 30, Section 4.1 “2.4 GHz radio (RADIO)” on page 31, Section 4.2 “Timer/counters (TIMER)” on page 32, Section 4.3 “Real Time Counter (RTC)” on page 32, Section 4.10 “Serial Peripheral Interface (SPI/SPIS)” on page 34, Section 4.12 “Universal Asynchronous Receiver/Transmitter (UART)” on page 35, Section 4.14 “Analog to Digital Converter (ADC)” on page 35, Section 4.15 “GPIO Task Event blocks (GPIOTE)” on page 35, Chapter 5 “Instance table” on page 36, Chapter 6 “Absolute maximum ratings” on page 37, Chapter 8 “Electrical specifications” on page 39, Section 8.1 “Clock sources” on page 39, Section 8.1.2 “16 MHz crystal oscillator (16M XOSC)” on page 40, Section 8.1.3 “32 MHz crystal oscillator (32M XOSC)” on page 41, Section 8.2 “Power management” on page 44, Section 8.3 “Block resource requirements” on page 48, Section 8.7 “Universal Asynchronous Receiver/Transmitter (UART) specifications” on page 55, Section 8.9 “Serial Peripheral Interface (SPI) Master specifications” on page 57, Section 8.11 “GPIO Tasks and Events (GPIOTE) specifications” on page 59, Section 8.13 “Timer (TIMER) specifications” on page 61, Section 8.16 “Random Number Generator (RNG) specifications” on page 62, Section 8.17 “AES Electronic Codebook Mode Encryption (ECB) specifications” on page 62, Section 8.18 “AES CCM Mode Encryption (CCM) specifications” on page 62, Section 8.19 “Accelerated Address Resolver (AAR) specifications” on page 62, Section 8.21 “Quadrature Decoder (QDEC) specifications” on page 63, Section 11.1 “PCB guidelines” on page 76, Section 11.3 “QFAA QFN48 package” on page 79, and Section 11.7 “CEAA WLCSP package” on page 103. Added the following sections: Section 3.3 “Memory Protection Unit (MPU)” on page 22, Section 4.5 “AES CCM Mode Encryption (CCM)” on page 33, Section 4.6 “Accelerated Address Resolver (AAR)” on page 33, Section 4.16 “Low Power Comparator (LPCOMP)” on page 35, Section 8.5.7 “Antenna matching network requirements” on page 54, Section 8.8 “Serial Peripheral Interface Slave (SPIS) specifications” on page 56, Section 8.18 “AES CCM Mode Encryption (CCM) specifications” on page 62, Section 8.19 “Accelerated Address Resolver (AAR) specifications” on page 62, and Section 8.24 “Low Power Comparator (LPCOMP) specifications” on page 65. Updated schematics and BOMs in section 11.3 on page 61. Page 5 nRF51822 Product Specification v3.1 Date April 2013 March 2013 November 2012 Version 1.2 1.1 1.0 Description Added chip variant nRF51822-CEAA. Updated feature list on front page. Updated Section 3.2.1 on page 15, Section 3.2.2 on page 15, Chapter 6 on page 28, Section 10.4 on page 52, and Section 10.5.1 on page 53. Added Section 2.2.2 on page 10, Section 7.1 on page 29, Section 9.2 on page 50, and Section 11.3 on page 61. Removed PCB layouts in Chapter 11 on page 54. Added chip variant nRF51822-QFAB. Added 32 MHz crystal oscillator feature. Updated feature list on front page. Moved subsection ‘Calculating current when the DC/DC converter is enabled’ from chapter 8 to the nRF51 Series Reference Manual. Updated Chapter 1 on page 6, Section 2.2 on page 8, Section 3.2 on page 12, Section 3.5 on page 16, Section 3.5.1 on page 17, Section 4.2 on page 21, Chapter 5 on page 24, Section 8.1 on page 27, Section 8.1.2 on page 28, Section 8.1.5 on page 30, Section 8.2 on page 32, Section 8.3 on page 34, Section 8.5.3 on page 36, Section 8.8 on page 40, Section 8.9 on page 41, Section 8.10 on page 42, Section 8.14 on page 43, Chapter 10 on page 47, Section 11.2 on page 51, Section 11.3 on page 54, and Section 11.4 on page 57. Added Section 3.5.4 on page 19, Section 8.1.3 on page 29, and Section 11.1 on page 50. Changed from PPS to PS. Updated the feature list on the front page. Updated Table 11 on page 25, Table 12 on page 26, Table 14 on page 28, Table 15 on page 28, Table 16 on page 29, Table 17 on page 29, Table 18 on page 30, Table 19 on page 31, Table 21 on page 32, Table 22 on page 32, Table 23 on page 33,Table 27 on page 36, Table 28 on page 37, Table 29 on page 37, Table 31 on page 38, Table 32 on page 38, Table 35 on page 39, Table 38 on page 40, Table 39 on page 40, Table 55 on page 47, Figure 9 on page 48, and Table 57 on page 50. Page 6 nRF51822 Product Specification v3.1 Table of contents 1 Introduction............................................................................................................................................... 9 1.1 Required reading.............................................................................................................................................. 9 1.2 Writing conventions........................................................................................................................................ 9 2 Product overview.................................................................................................................................... 10 2.1 Block diagram .................................................................................................................................................10 2.2 Pin assignments and functions .................................................................................................................11 3 System blocks.......................................................................................................................................... 19 3.1 CPU ......................................................................................................................................................................19 3.2 Memory .............................................................................................................................................................. 20 3.3 Memory Protection Unit (MPU).................................................................................................................22 3.4 Power management (POWER) ...................................................................................................................23 3.5 Programmable Peripheral Interconnect (PPI) ......................................................................................26 3.6 Clock management (CLOCK)......................................................................................................................27 3.7 GPIO..................................................................................................................................................................... 30 3.8 Debugger support .........................................................................................................................................30 4 Peripheral blocks .................................................................................................................................... 31 4.1 2.4 GHz radio (RADIO) ...................................................................................................................................31 4.2 Timer/counters (TIMER)................................................................................................................................32 4.3 Real Time Counter (RTC) ..............................................................................................................................32 4.4 AES Electronic Codebook Mode Encryption (ECB) .............................................................................32 4.5 AES CCM Mode Encryption (CCM)............................................................................................................33 4.6 Accelerated Address Resolver (AAR) .......................................................................................................33 4.7 Random Number Generator (RNG) ..........................................................................................................33 4.8 Watchdog Timer (WDT)................................................................................................................................33 4.9 Temperature sensor (TEMP) .......................................................................................................................34 4.10 Serial Peripheral Interface (SPI/SPIS) .......................................................................................................34 4.11 Two-wire interface (TWI)..............................................................................................................................34 4.12 Universal Asynchronous Receiver/Transmitter (UART) ....................................................................35 4.13 Quadrature Decoder (QDEC)......................................................................................................................35 4.14 Analog to Digital Converter (ADC)...........................................................................................................35 4.15 GPIO Task Event blocks (GPIOTE)..............................................................................................................35 4.16 Low Power Comparator (LPCOMP)..........................................................................................................35 5 Instance table .......................................................................................................................................... 36 6 Absolute maximum ratings .................................................................................................................. 37 7 Operating conditions............................................................................................................................. 38 7.1 WLCSP light sensitivity .................................................................................................................................38 8 Electrical specifications ......................................................................................................................... 39 8.1 Clock sources ...................................................................................................................................................39 8.2 Power management......................................................................................................................................44 8.3 Block resource requirements .....................................................................................................................48 8.4 CPU ......................................................................................................................................................................48 8.5 Radio transceiver ............................................................................................................................................49 8.6 Received Signal Strength Indicator (RSSI) specifications.................................................................54 8.7 Universal Asynchronous Receiver/Transmitter (UART) specifications ........................................55 8.8 Serial Peripheral Interface Slave (SPIS) specifications .......................................................................56 Page 7 nRF51822 Product Specification v3.1 8.9 Serial Peripheral Interface (SPI) Master specifications ......................................................................57 8.10 I2C compatible Two Wire Interface (TWI) specifications..................................................................58 8.11 GPIO Tasks and Events (GPIOTE) specifications...................................................................................59 8.12 Analog to Digital Converter (ADC) specifications...............................................................................60 8.13 Timer (TIMER) specifications.......................................................................................................................61 8.14 Real Time Counter (RTC) ..............................................................................................................................61 8.15 Temperature sensor (TEMP) .......................................................................................................................61 8.16 Random Number Generator (RNG) specifications..............................................................................62 8.17 AES Electronic Codebook Mode Encryption (ECB) specifications.................................................62 8.18 AES CCM Mode Encryption (CCM) specifications ...............................................................................62 8.19 Accelerated Address Resolver (AAR) specifications...........................................................................62 8.20 Watchdog Timer (WDT) specifications ...................................................................................................63 8.21 Quadrature Decoder (QDEC) specifications .........................................................................................63 8.22 Non-Volatile Memory Controller (NVMC) specifications..................................................................64 8.23 General Purpose I/O (GPIO) specifications ............................................................................................65 8.24 Low Power Comparator (LPCOMP) specifications..............................................................................65 9 Mechanical specifications ..................................................................................................................... 66 9.1 QFN48 package ...............................................................................................................................................66 9.2 CDAB WLCSP package ..................................................................................................................................67 9.3 CEAA WLCSP package...................................................................................................................................68 9.4 CFAC WLCSP package...................................................................................................................................69 10 Ordering information ............................................................................................................................ 70 10.1 Chip marking....................................................................................................................................................70 10.2 Inner box label.................................................................................................................................................70 10.3 Outer box label................................................................................................................................................71 10.4 Order code ........................................................................................................................................................71 10.5 Abbreviations................................................................................................................................................... 72 10.6 Code ranges and values...............................................................................................................................73 10.7 Product options ..............................................................................................................................................75 11 Reference circuitry.................................................................................................................................. 76 11.1 PCB guidelines.................................................................................................................................................76 11.2 Reference design schematics.....................................................................................................................78 11.3 QFAA QFN48 package ..................................................................................................................................79 11.4 QFAB QFN48 package...................................................................................................................................85 11.5 QFAC QFN48 package...................................................................................................................................91 11.6 CDAB WLCSP package ..................................................................................................................................97 11.7 CEAA WLCSP package................................................................................................................................ 103 11.8 CFAC WLCSP package................................................................................................................................ 109 12 Glossary ..................................................................................................................................................115 Page 8 nRF51822 Product Specification v3.1 1 Introduction The nRF51822 is an ultra-low power 2.4 GHz wireless System on Chip (SoC) integrating the nRF51 series 2.4 GHz transceiver, a 32 bit ARM® Cortex™-M0 CPU, flash memory, and analog and digital peripherals. nRF51822 can support Bluetooth® low energy and a range of proprietary 2.4 GHz protocols, such as Gazell from Nordic Semiconductor. Fully qualified Bluetooth low energy stacks for nRF51822 are implemented in the S100 series of SoftDevices. The S100 series of SoftDevices are available for free and can be downloaded and installed on nRF51822 independent of your own application code. 1.1 Required reading The following documentation is available for download from www.nordicsemi.com: • nRF51 Series Reference Manual • nRF51822-PAN (Product Anomaly Notification) • PCN-092 (nRF51822 Product Change Notification) 1.2 Writing conventions This product specification follows a set of typographic rules to ensure that the document is consistent and easy to read. The following writing conventions are used: • Command, event names, and bit state conditions, are written in Lucida Console. • Pin names and pin signal conditions are written in Consolas. • File names and User Interface components are written in bold. • Internal cross references are italicized and written in semi-bold. • Placeholders for parameters are written in italic regular text font. For example, a syntax description of Connect will be written as: Connect(TimeOut, AdvInterval). • Fixed parameters are written in regular text font. For example, a syntax description of Connect will be written as: Connect(0x00F0, Interval). Page 9 2 Product overview 2.1 Block diagram Q5) QP 5$0 5$0 5$0 5$0 6:&/. 6:',2 6:'3 nRF51822 Product Specification v3.1 *3,2 3 3±3 VODYH VODYH VODYH VODYH VODYH Q5(6(7 ;& ;& ;/ ;/ $17 $17 $,1±$,1 $5()±$5() /(' $ % '$3 &38 $50 &257(;0 19,& 32:(5 :'7 33, &/2&. 5$',2 (DV\'0$ *3,27( /3&203 $'& 4'(& PDVWHU VODYH $+% 0XOWL/D\HU VODYH VODYH VODYH $3% $+%72$3% %5,'*( PDVWHU ),&5 8,&5 &2'( PDVWHU PDVWHU PDVWHU 190& 51* 57&>Q@ 7,0(5>Q@ 7(03 (&% (DV\'0$ &&0 (DV\'0$ PDVWHU $$5 (DV\'0$ 7:,>Q@ 8$57>Q@ PDVWHU 63,6>Q@ (DV\'0$ 63,>Q@ Figure 1 Block diagram 6&/ 6'$ 576 &76 7;' 5;' &61 0,62 026, 6&. 0,62 026, 6&. Page 10 2.2 Pin assignments and functions This section describes the pin assignment and the pin functions. 2.2.1 Pin assignment QFN48 nRF51822 Product Specification v3.1 48 P0.29 47 P0.28 46 P0.27 45 P0.26 44 P0.25 43 P0.24 42 P0.23 41 P0.22 40 P0.21 39 DEC1 38 XC2 37 XC1 VDD 1 DCC 2 P0.30 3 P0.00 4 P0.01 5 P0.02 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 P0.07 11 VDD 12 nNQYQR5FY1WVFF8WVN52LH1402LP82 exposed die pad 36 AVDD 35 AVDD 34 VSS 33 VSS 32 ANT2 31 ANT1 30 VDD_PA 29 DEC2 28 P0.20 27 P0.19 26 P0.18 25 P0.17 VSS 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO/nRESET 23 SWDCLK 24 Figure 2 Pin assignment - QFN48 packet Note: VV = Variant code, HP = Build code, YYWWLL = Tracking code. For more information, see Section 10.6 “Code ranges and values” on page 73. Page 11 nRF51822 Product Specification v3.1 2.2.1.1 Pin functions QFN48 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 to 22 23 24 25 to 28 29 30 31 32 33, 34 35, 36 37 38 39 Pin name VDD DCC P0.30 P0.00 AREF0 P0.01 AIN2 P0.02 AIN3 P0.03 AIN4 P0.04 AIN5 P0.05 AIN6 P0.06 AIN7 AREF1 P0.07 VDD VSS P0.08 to P0.16 SWDIO/nRESET SWDCLK P0.17 to P0.20 DEC2 VDD_PA ANT1 ANT2 VSS AVDD XC1 XC2 DEC1 Pin function Power Power Digital I/O Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Analog input Digital I/O Power Power Digital I/O Digital I/O Digital input Digital I/O Power Power output RF RF Power Power Analog input Analog output Power Description Power supply. DC/DC output voltage to external LC filter. General purpose I/O pin. General purpose I/O pin. ADC/LPCOMP reference input 0. General purpose I/O pin. ADC/LPCOMP input 2. General purpose I/O pin. ADC/LPCOMP input 3. General purpose I/O pin. ADC/LPCOMP input 4. General purpose I/O pin. ADC/LPCOMP input 5. General purpose I/O pin. ADC/LPCOMP input 6. General purpose I/O pin. ADC/LPCOMP input 7. ADC/LPCOMP reference input 1. General purpose I/O pin. Power supply. Ground (0 V)1. General purpose I/O pin. System reset (active low). Also hardware debug and flash programming I/O. Hardware debug and flash programming I/O. General purpose I/O pin. Power supply decoupling. Power supply output (+1.6 V) for on-chip RF power amp. Differential antenna connection (TX and RX). Differential antenna connection (TX and RX). Ground (0 V). Analog power supply (Radio). Connection for 16/32 MHz crystal or external 16 MHz clock reference. Connection for 16/32 MHz crystal. Power supply decoupling. Page 12 nRF51822 Product Specification v3.1 Pin Pin name Pin function Description 40 to 44 45 46 47, 48 P0.21 to P0.25 P0.26 AIN0 XL2 Digital I/O Digital I/O Analog input Analog output P0.27 AIN1 XL1 Digital I/O Analog input Analog input P0.28 and P0.29 Digital I/O General purpose I/O pin. General purpose I/O pin. ADC/LPCOMP input 0. Connection for 32.768 kHz crystal. General purpose I/O pin. ADC/LPCOMP input 1. Connection for 32.768 kHz crystal or external 32.768 kHz clock reference. General purpose I/O pin. 1. The exposed center pad of the QFN48 package must be connected to ground for proper device operation. Table 1 Pin functions QFN48 packet 2.2.2 CDAB WLCSP ball assignment and functions 1 23456789 A B C N51822 D CDABHP E F YYWWLL G H Figure 3 Ball assignment CDAB packet (top side view) Page 13 nRF51822 Product Specification v3.1 2.2.2.1 Ball functions CDAB Ball Name A1 AVDD A2 XC1 A3 XC2 A4 DEC1 A5 P0.21 A6 P0.24 P0.26 A7 AIN0 XL2 P0.27 A8 AIN1 XL1 B1 VSS B4 VSS B5 P0.22 B6 P0.23 B7 P0.28 B8 VDD B9 DCC C1 ANT2 C5 P0.25 C6 N.C. C7 P0.29 C8 P0.30 C9 P0.00 AREF0 D1 ANT1 D7 VSS D8 P0.31 D9 P0.02 AIN3 E1 VDD_PA E2 N.C. E3 N.C. P0.01 E7 AIN2 P0.04 E8 AIN5 Function Power Analog input Analog output Power Digital I/O Digital I/O Digital I/O Analog input Analog output Digital I/O Analog input Analog input Power Power Digital I/O Digital I/O Digital I/O Power Power RF Digital I/O No Connection Digital I/O Digital I/O Digital I/O Analog input RF Power Digital I/O Digital I/O Analog input Power output No Connection No Connection Digital I/O Analog input Digital I/O Analog input Description Analog power supply (Radio). Crystal connection for 16/32 MHz crystal oscillator or external 16/32 MHz crystal reference. Crystal connection for 16/32 MHz crystal. Power supply decoupling. General purpose I/O. General purpose I/O. General purpose I/O. ADC input 0. Crystal connection for 32.768 kHz crystal oscillator. General purpose I/O. ADC input 1. Crystal connection for 32.768 kHz crystal oscillator or external 32.768 kHz crystal reference. Ground (0 V). Ground (0 V). General purpose I/O. General purpose I/O. General purpose I/O. Power supply. DC/DC output voltage to external LC filter. Differential antenna connection (TX and RX). General purpose I/O. Must be soldered to PCB. General purpose I/O. General purpose I/O. General purpose I/O. ADC Reference voltage. Differential antenna connection (TX and RX). Ground (0 V). General purpose I/O. General purpose I/O. ADC input 3. Power supply output (+1.6 V) for on-chip RF power amp. Must be soldered to PCB. Must be soldered to PCB. General purpose I/O. ADC input 2. General purpose I/O. ADC input 5. Page 14 Ball Name E9 P0.03 AIN4 F1 DEC2 F2 P0.19 F3 P0.18 F4 VSS F5 N.C. F6 VSS F7 N.C. P0.06 F8 AIN7 AREF1 F9 VSS G1 P0.20 G2 SWDCLK G3 P0.17 G4 P0.14 G5 P0.13 G6 P0.10 G7 P0.07 G8 VDD P0.05 G9 AIN6 nRESET H2 SWDIO H3 P0.16 H4 P0.15 H5 P0.12 H6 P0.11 H7 P0.09 H8 P0.08 nRF51822 Product Specification v3.1 Function Digital I/O Analog input Power Digital I/O Digital I/O Power No Connection Power No Connection Digital I/O Analog input Analog input Power Digital I/O Digital input Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Power Digital I/O Analog input Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Description General purpose I/O. ADC input 4. Power supply decoupling. General purpose I/O. General purpose I/O. Ground (0 V). Must be soldered to PCB. Ground (0 V). Must be soldered to PCB. General purpose I/O. ADC input 7. ADC Reference voltage. Ground (0 V). General purpose I/O. Hardware debug and flash programming I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. Power supply. General purpose I/O. ADC input 6. System reset (active low). Hardware debug and flash programming I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. Table 2 Ball functions CDAB packet Page 15 nRF51822 Product Specification v3.1 2.2.3 CEAA and CFAC WLCSP ball assignment and functions 1 23456789 A B C N51822 D E CEAAHP F YYWWLL G H J 1 23456789 A B C N51822 D E CFACHP F YYWWLL G H J Figure 4 Ball assignment CEAA and CFAC packet (top side view) Note: HP = Buildcode, YYWWLL = Tracking code Solder balls not visible on the top side. Dot denotes A1 corner. Page 16 nRF51822 Product Specification v3.1 2.2.3.1 Ball functions CEAA and CFAC Ball Name A1 AVDD A2 XC1 A3 XC2 A4 DEC1 A5 P0.21 A6 P0.24 P0.26 A7 AIN0 XL2 P0.27 A8 AIN1 XL1 B1 VSS B4 VSS B5 P0.22 B6 P0.23 B7 P0.28 B8 VDD B9 DCC C1 ANT2 C5 P0.25 C6 N.C. C7 P0.29 C8 VSS C9 P0.00 AREF0 D1 ANT1 D7 VSS D8 P0.30 D9 P0.02 AIN3 E1 VDD_PA E2 N.C. E3 N.C. E7 N.C. E8 P0.31 P0.01 E9 AIN2 Function Power Analog input Analog output Power Digital I/O Digital I/O Digital I/O Analog input Analog output Digital I/O Analog input Analog input Power Power Digital I/O Digital I/O Digital I/O Power Power RF Digital I/O No Connection Digital I/O Power Digital I/O Analog input RF Power Digital I/O Digital I/O Analog input Power output No Connection No Connection No Connection Digital I/O Digital I/O Analog input Description Analog power supply (Radio). Crystal connection for 16/32 MHz crystal oscillator or external 16/32 MHz crystal reference. Crystal connection for 16/32 MHz crystal. Power supply decoupling. General purpose I/O. General purpose I/O. General purpose I/O. ADC input 0. Crystal connection for 32.768 kHz crystal oscillator. General purpose I/O. ADC input 1. Crystal connection for 32.768 kHz crystal oscillator or external 32.768 kHz crystal reference. Ground (0 V). Ground (0 V). General purpose I/O. General purpose I/O. General purpose I/O. Power supply. DC/DC output voltage to external LC filter. Differential antenna connection (TX and RX). General purpose I/O. Must be soldered to PCB. General purpose I/O. Ground (0 V). General purpose I/O. ADC Reference voltage. Differential antenna connection (TX and RX). Ground (0 V). General purpose I/O. General purpose I/O. ADC input 3. Power supply output (+1.6 V) for on-chip RF power amp. Must be soldered to PCB. Must be soldered to PCB. Must be soldered to PCB. General purpose I/O. General purpose I/O. ADC input 2. Page 17 Ball Name F1 DEC2 F2 P0.19 F3 N.C. F7 N.C. F8 P0.04 AIN5 F9 P0.03 AIN4 G1 P0.20 G2 P0.17 G3 N.C. G4 N.C. G5 N.C. G6 VSS G7 N.C. P0.06 G8 AIN7 AREF1 G9 VSS H1 P0.18 H2 SWDCLK H3 VSS H4 P0.14 H5 P0.13 H6 P0.10 H7 P0.07 H8 VDD P0.05 H9 AIN6 J2 SWDIO/ nRESET J3 P0.16 J4 P0.15 J5 P0.12 J6 P0.11 J7 P0.09 J8 P0.08 nRF51822 Product Specification v3.1 Function Power Digital I/O No Connection No Connection Digital I/O Analog input Digital I/O Analog input Digital I/O Digital I/O No Connection No Connection No Connection Power No Connection Digital I/O Analog input Analog input Power Digital I/O Digital input Power Digital I/O Digital I/O Digital I/O Digital I/O Power Digital I/O Analog input Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Description Power supply decoupling. General purpose I/O. Must be soldered to PCB. Must be soldered to PCB. General purpose I/O. ADC input 5. General purpose I/O. ADC input 4. General purpose I/O. General purpose I/O. Must be soldered to PCB. Must be soldered to PCB. Must be soldered to PCB. Ground (0 V). Must be soldered to PCB. General purpose I/O. ADC input 7. ADC Reference voltage. Ground (0 V). General purpose I/O. Hardware debug and flash programming I/O. Ground (0 V). General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. Power supply. General purpose I/O. ADC input 6. System reset (active low). Also Hardware debug and flash programming I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. Table 3 Ball functions for CEAA and CFAC Page 18 nRF51822 Product Specification v3.1 3 System blocks The chip contains system-level features common to all nRF51 series devices including clock control, power and reset, interrupt system, Programmable Peripheral Interconnect (PPI), watchdog, and GPIO. System blocks which have a register interface and/or interrupt vector assigned are instantiated in the device address space. The instances of system blocks, their associated ID (for those with interrupt vectors), and base addresses are found in Table 18 on page 36. Detailed functional descriptions, configuration options, and register interfaces can be found in the nRF51 Series Reference Manual. 3.1 CPU The ARM® Cortex™-M0 CPU has a 16 bit instruction set with 32 bit extensions (Thumb-2® technology) that delivers high-density code with a small-memory-footprint. By using a single-cycle 32 bit multiplier, a 3-stage pipeline, and a Nested Vector Interrupt Controller (NVIC), the ARM Cortex-M0 CPU makes program execution simple and highly efficient. The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARM Cortex-M processor series is implemented and available for M0 CPU. Code is forward compatible with ARM Cortex M3 based devices. Page 19 nRF51822 Product Specification v3.1 3.2 Memory All memory and registers are found in the same address space as shown in the Device Memory Map, see Figure 5. Devices in the nRF51 series use flash based memory in the code, FICR, and UICR regions. The RAM region is SRAM. 0xFFFFFFFF 0xE0100000 0xE0000000 reserved Private Peripheral Bus reserved 0x50000000 0x40080000 0x40000000 AHB peripherals reserved APB peripherals reserved 0x20000000 0x10001000 0x10000000 RAM reserved UICR reserved FICR reserved 0x00000000 Code Figure 5 Memory Map The embedded flash memory for program and static data can be programmed using In Application Programming (IAP) routines from RAM through the SWD interface, or in-system from a program executing from code area. The Non-Volatile Memory Controller (NVMC) is used for program/erase operations. Regions of flash memory can be protected from read, write, and erase by the Memory Protection Unit (MPU). A User Information Configuration Register (UICR) contains the lock byte for enabling readback protection to secure the IP, while individual block protection is controlled using registers which can only be cleared on chip reset. Page 20 nRF51822 Product Specification v3.1 3.2.1 Code organization Chip variant nRF51822-QFAA nRF51822-CEAA nRF51822-QFAB nRF51822-CDAB nRF51822-QFAC nRF51822-CFAC Code size 256 kB 128 kB 256 kB Page size 1024 byte 1024 byte 1024 byte No of pages 256 128 256 Table 4 Code organization 3.2.2 RAM organization RAM is divided into blocks for separate power management which is controlled by the POWER System Block. Each block is divided into two 4 kByte RAM sections with separate RAM AHB slaves. Please see the nRF51 Series Reference Manual for more information. Chip variant nRF51822-QFAA nRF51822-CEAA nRF51822-QFAB nRF51822-CDAB nRF51822-QFAC nRF51822-CFAC RAM size 16 kB 16 kB 32 kB Block Block0 Block1 Block0 Block1 Block0 Block1 Block2 Block3 Size 8 kB 8 kB 8 kB 8 kB 8 kB 8 kB 8 kB 8 kB Table 5 RAM organization How to organize the use of the RAM For the best performance we recommend the following use of the RAM AHB slaves (Note that the Crypto consists of CCM, ECB, and AAR modules): • If the Radio and Crypto buffers together are larger in size than one RAM section, the buffers should be separated so the memory used by the Radio is in one RAM section while the memory used by the Crypto is in another RAM section. • The sections used by CODE should not be combined with sections used by the Radio, Crypto, or SPI. • The Stack and Heap should be placed at the top section and should not be combined with sections used by the Radio, Crypto, or SPI. Page 21 nRF51822 Product Specification v3.1 Table 6 and Table 7 shows how memory allocated to different functions can be distributed between RAM sections for parallel access. There is a table for chip variants with 16 kB or 32 kB RAM. RAM Blocks/Sections Block0 Block1 RAM0 RAM1 RAM2 RAM3 Radio buffers x Crypto buffers x SPIS CPU buffers Stack/Heap CODE x x x x Global variables x x x x Table 6 16 kB RAM variants RAM Blocks/Sections Block0 Block1 Block2 Block3 RAM0 RAM1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 Radio buffers x (x) Crypto buffers (x) x SPIS CPU buffers Stack/Heap CODE x x x x x x x Table 7 32 kB RAM variants Global variables x x x x x x x x 3.3 Memory Protection Unit (MPU) The memory protection unit can be configured to protect all flash memory on the device from read-back, or to protect blocks of flash from over-write or erase. Chip variant nRF51822-QFAA nRF51822-CEAA nRF51822-QFAB nRF51822-CDAB nRF51822-QFAC nRF51822-CFAC Flash block size 4 kB 4 kB 4 kB Number of protectable Flash blocks 64 32 64 Table 8 MPU flash blocks Page 22 nRF51822 Product Specification v3.1 3.4 Power management (POWER) 3.4.1 Power supply nRF51 supports three different power supply alternatives: • Internal LDO setup • DC/DC converter setup • Low voltage mode setup See Table 20 on page 38 for the voltage range on the different alternatives. See Chapter 11 “Reference circuitry” on page 76 for details on the schematic used for the different power supply alternatives. 3.4.1.1 Internal LDO setup In internal LDO mode the DC/DC converter is bypassed (disabled) and the system power is generated directly from the supply voltage VDD. This mode could be used as the only option or in combination with the DC/DC converter setup. See DC/DC converter section for more details. 3.4.1.2 DC/DC converter setup The nRF51 DC/DC buck converter transforms battery voltage to lower internal voltage with minimal power loss. The converted voltage is then available for the linear regulator input. The DC/DC converter can be disabled when the supply voltage drops to the lower limit of the voltage range so the LDO can be used for low supply voltages. When enabled, the DC/DC converter operation is automatically suspended between radio events when only the low current regulator is needed internally. This feature is particularly useful for applications using battery technologies with nominal cell voltages higher than the minimum supply voltage with DC/DC enabled. The reduction in supply voltage level from a high voltage to a low voltage reduces the peak power drain from the battery. Used with a 3 V coin-cell battery, the peak current drawn from the battery is reduced by approximately 25%. 3.4.1.3 Low voltage mode setup Devices can be used in low voltage mode where a steady 1.8 V supply is available externally. Page 23 nRF51822 Product Specification v3.1 3.4.2 Power management The power management system is highly flexible with functional blocks such as the CPU, Radio Transceiver, and peripherals having separate power state control in addition to the global System ON and OFF modes. In System OFF mode, RAM can be retained and the device state can be changed to System ON through Reset, GPIO DETECT signal, or LPCOMP ANADETECT signal. When in System ON mode, all functional blocks will independently be in IDLE or RUN mode depending on needed functionality. Power management features: • Supervisor HW to manage • Power on reset • Brownout reset • Power fail comparator • System ON/OFF modes • Pin wake-up from System OFF • Reset • GPIO DETECT signal • LPCOMP ANADETECT signal • Functional block RUN/IDLE modes • RAM retention in System OFF mode (8 kB blocks) • 16 kB version will have 2 blocks • 32 kB version will have 4 blocks 3.4.2.1 System OFF mode In system OFF mode the chip is in the deepest power saving mode. The system's core functionality is powered down and all ongoing tasks are terminated. The only functionality that can be set up to be responsive is the Pin wake-up mechanism. One or more blocks of RAM can be retained while in System OFF mode. Page 24 nRF51822 Product Specification v3.1 3.4.2.2 System ON mode In system ON mode the system is fully operational and the CPU and selected peripherals can be brought into a state where they are functional and more or less responsive depending on the sub-power mode selected. There are two sub-power modes: • Low power • Constant latency Low Power In Low Power mode the automatic power management system is optimized to save power. This is done by keeping as much as possible of the system powered down. The cost of this is that you will have varying CPU wakeup latency and PPI task response. The CPU wakeup latency will be affected by the startup time of the 1V7 regulator. The PPI task response will vary depending on the resources required by the peripheral where the task originated. The resources that could be involved are: • 1V7 with the startup time t1V7 • 1V2 with the startup time t1V2 • One of the following clock sources • RC16 with the startup time tSTART,RC16 • XO16M/XO32M with the startup time the clock management system tXO1 Constant Latency In Constant Latency mode the system is optimized towards keeping the CPU latency and the PPI task response constant and at a minimum. This is secured by forcing a set of base resources on while in sleep mode. The cost is that the system will have higher power consumption. The following resources are kept active while in sleep mode: • 1V7 regulator with the standby current of I1V7 • 1V2 regulator. Here the current consumption is specified in combination with the clock source • One of the following clock sources: • RC16 with the standby current of I1V2RC16 • XO16M with the standby current of I1V2XO16 • XO32M with the standby current of I1V2XO32 1. For the clock source XO16M and XO32M we assume that the crystal is already running (standby). This will give an increase of the power consumption in sleep mode given by ISTBY,X16M / ISTBY,X32M. Page 25 nRF51822 Product Specification v3.1 3.5 Programmable Peripheral Interconnect (PPI) The Programmable Peripheral Interconnect (PPI) enables peripherals to interact autonomously with each other using tasks and events independent of the CPU. The PPI allows precise synchronization between peripherals when real-time application constraints exist and eliminates the need for CPU activity to implement behavior which can be predefined using PPI. Instance PPI Channel 0 - 15 Number of channels 16 Number of groups 4 Table 9 PPI properties The PPI system has in addition to the fully programmable peripheral interconnections, a set of channels where the event (EEP) and task (TEP) endpoints are set in hardware. These fixed channels can be individually enabled, disabled, or added to PPI channel groups in the same way as ordinary PPI channels. See the nRF51 Series Reference Manual for more information. Instance PPI Channel 20 - 31 Number of channels 12 Number of groups 4 Table 10 Pre-programmed PPI channels Page 26 nRF51822 Product Specification v3.1 3.6 Clock management (CLOCK) The advanced clock management system can source the system clocks from a range of internal or external high and low frequency oscillators and distribute them to modules based upon a module’s individual requirements. This prevents large clock trees from being active and drawing power when system modules needing this clock reference are not active. If an application enables a module that needs a clock reference without the corresponding oscillator running, the clock management system will automatically enable the RC oscillator option and provide the clock. When the module goes back to idle, the clock management will automatically set the oscillator to idle. To avoid delays involved in starting a given oscillator, or if a specific oscillator is required, the application can override the automatic oscillator management so it keeps oscillators active when no system modules require the clock reference. Clocks are only available in System ON mode and can be generated by the sources listed in Table 11. Clock Source Frequency options High Frequency Clock (HFCLK)1 Low Frequency Clock (LFCLK) External Crystal (XOSC) External clock reference3 Internal RC Oscillator (RCOSC) External Crystal (XOSC) External clock reference3 Synthesized from HFCLK Internal RC Oscillator (RCOSC) 16/32 MHz2 16 MHz 16 MHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 1. External Crystal must be used for Radio operation. 2. The HFCLK will be 16 MHz for both the 16 and 32 MHz crystal option. 3. See the nRF51 Series Reference Manual for more details on external clock reference. Table 11 Clock properties XL1 XL2 XC1 XC2 LFCLKSRC LFCLKSTART LFCLKSTOP LFCLKSTARTED 32.768 kHz crystal oscillator 32.768 kHz RC oscillator LFCLK clock control 32.768 kHz synthesizer HFCLKSRC HFCLKSTART HFCLKSTOP HFCLKSTARTED LFCLK Figure 6 Clock management 16 MHz RC oscillator 16/32 MHz crystal oscillator HFCLK clock control HFCLK Request from the rest of the system Page 27 nRF51822 Product Specification v3.1 3.6.1 16/32 MHz crystal oscillator The crystal oscillator can be controlled either by a 16 MHz or a 32 MHz external crystal. However, the system clock is always 16 MHz, see the nRF51 Series Reference Manual for more details. The crystal oscillator is designed for use with an AT-cut quartz crystal in parallel resonant mode. To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet. Figure 7 shows how the crystal is connected to the 16/32 MHz crystal oscillator. XC1 XC2 C1 C2 16/32 MHz crystal Figure 7 Circuit diagram of the 16/32 MHz crystal oscillator The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by: CL = ---C-C---1-1--'-'--+----C-C---2-2--'-'-- C1’ = C1 + C_pcb1 + C_pin C2’ = C2 + C_pcb2 + C_pin C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. C_pcb1 and C_pcb2 are stray capacitances on the PCB. C_pin is the pin input capacitance on the XC1 and XC2 pins, see Table 22 on page 40 (16 MHz) and Table 23 on page 41 (32 MHz). The load capacitors C1 and C2 should have the same value. See Chapter 11 “Reference circuitry” on page 76 for the capacitance value used for C_pcb1 and C_pcb2 in reference circuitry. For reliable operation, the crystal load capacitance, shunt capacitance, equivalent series resistance (RS,X16M/ RS,X32M), and drive level must comply with the specifications in Table 22 on page 40 (16 MHz) and Table 23 on page 41 (32 MHz). It is recommended to use a crystal with lower than maximum RS,X16M/RS,X32M if the load capacitance and/or shunt capacitance is high. This will give faster startup and lower current consumption. A low load capacitance will reduce both startup time and current consumption. Page 28 nRF51822 Product Specification v3.1 3.6.2 32.768 kHz crystal oscillator The 32.768 kHz crystal oscillator is designed for use with a quartz crystal in parallel resonant mode. To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet. Figure 8 shows how the crystal is connected to the 32.768 kHz crystal oscillator. XL1 XL2 C1 C2 32.768 kHz crystal Figure 8 Circuit diagram of the 32.768 kHz crystal oscillator The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by: CL = ---C-C---1-1--'-'--+----C-C---2-2--'-'-- C1’ = C1 + C_pcb1 + C_pin C2’ = C2 + C_pcb2 + C_pin C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. C_pcb1 and C_pcb2 are stray capacitances on the PCB. C_pin is the pin input capacitance on the XC1 and XC2 pins, see Section 8.1.5 “32.768 kHz crystal oscillator (32k XOSC)” on page 42. The load capacitors C1 and C2 should have the same value. See Chapter 11 “Reference circuitry” on page 76 for the capacitance value used for C_pcb1 and C_pcb2 in reference circuitry. 3.6.3 32.768 kHz RC oscillator The 32.768 kHz RC low frequency oscillator may be used as an alternative to the 32.768 kHz crystal oscillator. It has a frequency accuracy of less than ± 250 ppm in a stable temperature environment or when calibration is periodically performed in changing temperature environments. The 32.768 kHz RC oscillator does not require external components. Page 29 nRF51822 Product Specification v3.1 3.6.4 Synthesized 32.768 kHz clock The low frequency clock can be synthesized from the high frequency clock. This saves the cost of a crystal but increases average power consumption as the high frequency clock source will have to be active. 3.7 GPIO The general purpose I/O is organized as one port with up to 32 I/Os (dependent on package) enabling access and control of up to 32 pins through one port. Each GPIO can be accessed individually with the following user configurable features: • Input/output direction • Output drive strength • Internal pull-up and pull-down resistors • Wake-up from high or low level triggers on all pins • Trigger interrupt on all pins • All pins can be used by the PPI task/event system; the maximum number of pins that can be interfaced through the PPI at the same time is limited by the number of GPIOTE channels • All pins can be individually configured to carry serial interface or quadrature demodulator signals 3.8 Debugger support The two pin Serial Wire Debug (SWD) interface provided as a part of the Debug Access Port (DAP) offers a flexible and powerful mechanism for non-intrusive debugging of program code. Breakpoints and single stepping are part of this support. Page 30 nRF51822 Product Specification v3.1 4 Peripheral blocks Peripheral blocks which have a register interface and/or interrupt vector assigned are instantiated, one or more times, in the device address space. The instances, associated ID (for those with interrupt vectors), and base address of features are found in Table 18 on page 36. Detailed functional descriptions, configuration options, and register interfaces can be found in the nRF51 Series Reference Manual. 4.1 2.4 GHz radio (RADIO) The nRF51 series 2.4 GHz RF transceiver is designed and optimized to operate in the worldwide ISM frequency band at 2.400 to 2.4835 GHz. Radio modulation modes and configurable packet structure enable interoperability with Bluetooth® low energy (BLE), ANT™, Enhanced ShockBurst™, and other 2.4 GHz protocol implementations. The transceiver receives and transmits data directly to and from system memory for flexible and efficient packet data management. The nRF51 series transceiver has the following features: • General modulation features • GFSK modulation • Data whitening • On-air data rates • 250 kbps • 1 Mbps • 2 Mbps • Transmitter with programmable output power of +4 dBm to -20 dBm, in 4 dB steps • Transmitter whisper mode -30 dBm • RSSI function (1 dB resolution) • Receiver with integrated channel filters achieving maximum sensitivity • -96 dBm at 250 kbps • -93 dBm at 1 Mbps BLE • -90 dBm at 1 Mbps • -85 dBm at 2 Mbps • RF Synthesizer • 1 MHz frequency programming resolution • 1 MHz non-overlapping channel spacing at 1 Mbps and 250 kbps • 2 MHz non-overlapping channel spacing at 2 Mbps • Works with low-cost ± 60 ppm 16 MHz crystal oscillators • Baseband controller • EasyDMA RX and TX packet transfer directly to and from RAM • Dynamic payload length • On-the-fly packet assembly/disassembly and AES CCM payload encryption • 8 bit, 16 bit, and 24 bit CRC check (programmable polynomial and initial value) Note: EasyDMA is an integrated DMA implementation requiring no configuration to take advantage of flexible data management and avoids copying operations to and from RAM. Page 31 nRF51822 Product Specification v3.1 4.2 Timer/counters (TIMER) The timer/counter runs on the high-frequency clock source (HFCLK) and includes a 4 bit (1/2X) prescaler that can divide the HFCLK. The TIMER will start requesting the 1 MHz mode of the HFCLK for values of the prescaler that gives fTIMER less or equal to 1 MHz. If the timer module is the only one requesting the HFCLK, the system will automatically switch to using the 1 MHz mode resulting in a decrease in the current consumption. See the parameters I1v2XO16,1M, I1v2XO32,1M, I1v2RC16,1M in Table 32 on page 47 and ITIMER0/1/2,1M in Table 52 on page 61. The task/event and interrupt features make it possible to use the PPI system for timing and counting tasks between any system peripheral including any GPIO of the device. The PPI system also enables the TIMER task/event features to generate periodic output and PWM signals to any GPIO. The number of input/outputs used at the same time is limited by the number of GPIOTE channels. Instance TIMER0 TIMER1 TIMER2 Bit-width 8/16/24/32 8/16 8/16 Capture/Compare registers 4 4 4 Table 12 Timer/counter properties 4.3 Real Time Counter (RTC) The Real Time Counter (RTC) module provides a generic, low power timer on the low-frequency clock source (LFCLK). The RTC features a 24 bit COUNTER, 12 bit (1/X) prescaler, capture/compare registers, and a tick event generator for low power, tickless RTOS implementation. Instance RTC0 RTC1 Capture/Compare registers 3 4 Table 13 RTC properties 4.4 AES Electronic Codebook Mode Encryption (ECB) The ECB encryption block supports 128 bit AES block encryption. It can be used for a range of cryptographic functions like hash generation, digital signatures, and keystream generation for data encryption/decryption. ECB encryption uses EasyDMA to access system RAM for in-place operations on cleartext and ciphertext during encryption. Page 32 nRF51822 Product Specification v3.1 4.5 AES CCM Mode Encryption (CCM) Cipher Block Chaining - Message Authentication Code (CCM) Mode is an authenticated encryption algorithm designed to provide both authentication and confidentiality during data transfer. CCM combines counter mode encryption and CBC-MAC authentication. Note: The CCM terminology "Message Authentication Code (MAC)" is called the "Message Integrity Check (MIC)" in Bluetooth terminology and this document and the nRF51 Series Reference Manual are consistent with Bluetooth terminology. The CCM block generates an encrypted keystream, applies it to the input data using the XOR operation, and generates the 4 byte MIC field in one operation. The CCM and radio can be configured to work synchronously, as described in the nRF51 Series Reference Manual. The CCM will encrypt in time for transmission and decrypt after receiving bytes into memory from the Radio. All operations can complete within the packet RX or TX time. CCM on this device is implemented according to Bluetooth requirements and the algorithm as defined in IETF RFC3610, and depends on the AES-128 block cipher. A description of the CCM algorithm can also be found in the NIST Special Publication 800-38C. The Bluetooth Core Specification v4.0 describes the configuration of counter mode blocks and encryption blocks to implement compliant encryption for BLE. The CCM block uses EasyDMA to load key, counter mode blocks (including the nonce required), and to read/ write plain text and cipher text. 4.6 Accelerated Address Resolver (AAR) Accelerated Address Resolver is a cryptographic support function to implement the "Resolvable Private Address Resolution Procedure" described in the Bluetooth Core Specification v4.1. "Resolvable Private Address Generation" should be achieved using ECB and is not supported by AAR. The procedure allows two devices that share a secret key to generate and resolve a hash based on their device address. The AAR block enables real-time address resolution on incoming packets when configured according to the description in the nRF51 Series Reference Manual. This allows real-time packet filtering (whitelisting) using a list of known shared secrets (Identity Resolving Keys (IRK) in Bluetooth). The following table outlines the properties of the AAR. Instance AAR Number of IRKs supported for simultaneous resolution 8 Table 14 AAR properties 4.7 Random Number Generator (RNG) The Random Number Generator (RNG) generates true non-deterministic random numbers derived from thermal noise that are suitable for cryptographic purposes. The RNG does not require a seed value. 4.8 Watchdog Timer (WDT) A countdown watchdog timer using the low-frequency clock source (LFCLK) offers configurable and robust protection against application lock-up. The watchdog can be paused during long CPU sleep periods for low power applications and when the debugger has halted the CPU. Page 33 nRF51822 Product Specification v3.1 4.9 Temperature sensor (TEMP) The temperature sensor measures die temperature over the temperature range of the device with 0.25° C resolution. 4.10 Serial Peripheral Interface (SPI/SPIS) The SPI interfaces enable full duplex synchronous communication between devices. They support a threewire (SCK, MISO, MOSI) bi-directional bus with fast data transfers. The SPI Master can communicate with multiple slaves using individual chip select signals for each of the slave devices attached to a bus. Control of chip select signals is left to the application through use of GPIO signals. SPI Master has double buffered I/O data. The SPI Slave includes EasyDMA for data transfer directly to and from RAM allowing Slave data transfers to occur while the CPU is IDLE. The GPIOs used for each SPI interface line can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of printed circuit board space and signal routing. The SPI peripheral supports SPI mode 0, 1, 2, and 3. Instance SPI0 SPI1 SPIS1 Master/Slave Master Master Slave Table 15 SPI properties 4.11 Two-wire interface (TWI) The two-wire interface can communicate with a bi-directional wired-AND bus with two lines (SCL, SDA). The protocol makes it possible to interconnect up to 127 individually addressable devices. The interface is capable of clock stretching, supporting data rates of 100 kbps and 400 kbps. The GPIOs used for each two-wire interface line can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing. Instance TWI0 TWI1 Master/Slave Master Master Table 16 Two-wire properties Page 34 nRF51822 Product Specification v3.1 4.12 Universal Asynchronous Receiver/Transmitter (UART) The Universal Asynchronous Receiver/Transmitter offers fast, full-duplex, asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware up to 1 Mbps baud. Parity checking is supported. The GPIOs used for each UART interface line can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing. 4.13 Quadrature Decoder (QDEC) The quadrature decoder provides buffered decoding of quadrature-encoded sensor signals. It is suitable for mechanical and optical sensors with an optional LED output signal and input debounce filters. The sample period and accumulation are configurable to match application requirements. 4.14 Analog to Digital Converter (ADC) The 10 bit incremental Analog to Digital Converter (ADC) enables sampling of up to 8 external signals through a front-end multiplexer. The ADC has configurable input and reference prescaling, and sample resolution (8, 9, and 10 bit). Note: The ADC module uses the same analog inputs as the LPCOMP module (AIN0 - AIN7 and AREF0 - AREF1). Only one of the modules can be enabled at the same time. 4.15 GPIO Task Event blocks (GPIOTE) A GPIOTE block enables GPIOs on Port 0 to generate events on pin state change which can be used to carry out tasks through the PPI system. A GPIO can also be driven to change state on system events using the PPI system. Low power detection of pin state changes on Port 0 is possible when in System ON or System OFF. Instance GPIOTE Number of GPIOTE channels 4 Table 17 GPIOTE properties 4.16 Low Power Comparator (LPCOMP) In System ON, the block can generate separate events on rising and falling edges of a signal, or sample the current state of the pin as being above or below the threshold. The block can be configured to use any of the analog inputs on the device. Additionally, the low power comparator can be used as an analog wakeup source from System OFF or System ON. The comparator threshold can be programmed to a range of fractions of the supply voltage. Note: The LPCOMP module uses the same analog inputs as the ADC module (AIN0 - AIN7 and AREF0 - AREF1). Only one of the modules can be enabled at the same time. Page 35 nRF51822 Product Specification v3.1 5 Instance table The peripheral instantiation of the chip is shown in the table below. ID Base address 0 0 0 1 2 3 3 4 4 4 5 6 7 8 9 10 11 12 13 14 15 15 16 17 18 19 20 - 25 26 - 29 30 31 NA NA NA 0x40000000 0x40000000 0x40000000 0x40001000 0x40002000 0x40003000 0x40003000 0x40004000 0x40004000 0x40004000 0x40006000 0x40007000 0x40008000 0x40009000 0x4000A000 0x4000B000 0x4000C000 0x4000D000 0x4000E000 0x4000F000 0x4000F000 0x40010000 0x40011000 0x40012000 0x40013000 0x4001E000 0x4001F000 0x50000000 0x10000000 0x10001000 Peripheral POWER CLOCK MPU RADIO UART SPI TWI SPIS SPI TWI Instance POWER CLOCK MPU RADIO UART0 SPI0 TWI0 SPIS1 SPI1 TWI1 GPIOTE ADC TIMER TIMER TIMER RTC TEMP RNG ECB CCM AAR WDT RTC QDEC LPCOMP GPIOTE ADC TIMER0 TIMER1 TIMER2 RTC0 TEMP RNG ECB CCM AAR WDT RTC1 QDEC LPCOMP NVMC PPI GPIO FICR UICR NVMC PPI GPIO FICR UICR Description Power Control. Clock Control. Memory Protection Unit. 2.4 GHz Radio. Universal Asynchronous Receiver/Transmitter. SPI Master. I2C compatible Two-Wire Interface 0. SPI Slave. SPI Master. I2C compatible Two-Wire Interface 1. Unused. GPIO Task and Events. Analog to Digital Converter. Timer/Counter 0. Timer/Counter 1. Timer/Counter 2. Real Time Counter 0. Temperature Sensor. Random Number Generator. Crypto AES ECB. AES Crypto CCM. Accelerated Address Resolver. Watchdog Timer. Real Time Counter 1. Quadrature Decoder. Low Power Comparator. Reserved as software interrupt. Unused. Non-Volatile Memory Controller. Programmable Peripheral Interconnect. General Purpose Input and Output. Factory Information Configuration Registers. User Information Configuration Registers. Table 18 Peripheral instance reference Page 36 nRF51822 Product Specification v3.1 6 Absolute maximum ratings Maximum ratings are the extreme limits the chip can be exposed to without causing permanent damage. Exposure to absolute maximum ratings for prolonged periods of time may affect the reliability of the chip. Table 19 specifies the absolute maximum ratings. Symbol Parameter Min. Max. Unit Supply voltages VDD DEC2 VSS I/O pin voltage VIO Environmental QFN48 package Storage temperature MSL Moisture Sensitivity Level ESD HBM Human Body Model ESD CDM Charged Device Model Environmental WLCSP package Storage temperature MSL Moisture Sensitivity Level ESD HBM Human Body Model ESD CDM Charged Device Model Flash memory Endurance Retention Number of times an address can be written between erase cycles -0.3 +3.9 V 2 V 0 V -0.3 VDD + 0.3 V -40 +125 °C 2 4 kV 750 V -40 +125 °C 1 4 kV 500 V 20 0001 10 years at 40 °C write/erase cycles 2 times 1. Flash endurance is 20,000 erase cycles. The smallest element of flash that can be written is a 32 bit word. Table 19 Absolute maximum ratings Page 37 nRF51822 Product Specification v3.1 7 Operating conditions The operating conditions are the physical parameters that the chip can operate within as defined in Table 20. Symbol Parameter Notes Min. Typ. Max. VDD Supply voltage, internal LDO setup 1.8 3.0 3.6 VDD Supply voltage, DC/DC converter setup 2.1 3.0 3.6 VDD Supply voltage, low voltage mode setup 1 1.75 1.8 1.95 tR_VDD Supply rise time (0 V to VDD) 2 100 TA Operating temperature -25 25 75 1. DEC2 shall be connected to VDD in this mode. 2. The on-chip power-on reset circuitry may not function properly for rise times outside the specified interval. Units V V V ms °C Table 20 Operating conditions Nominal operating conditions (NOC) - conditions under which the chip is operated and tested are the typical (Typ.) values in Table 20. Extreme operating conditions (EOC) - conditions under which the chip is operated and tested are the minimum (Min.) and maximum (Max.) values in Table 20. 7.1 WLCSP light sensitivity The WLCSP package variant is sensitive to visible and near infrared light which means a final product design must shield the chip properly. The marking side is covered with a light absorbing film, while the side edges of the chip and the ball side must be protected by coating or other means. Page 38 nRF51822 Product Specification v3.1 8 Electrical specifications This chapter contains electrical specifications for device interfaces and peripherals including radio parameters and current consumption. The test levels referenced are defined in Table 21. Test level 1 2 3 4 Description Simulated, calculated, by design (specification limit) or prototype samples tested at NOC. Parameters have been verified at Test level 1 and in addition: Prototype samples tested at EOC. Parameters have been verified at Test level 2 and in addition: Production samples tested at EOC in accordance with JEDEC47. Parameters have been verified at Test level 3 and in addition: Production devices are limit tested at NOC. Table 21 Test level definitions 8.1 Clock sources 8.1.1 16/32 MHz crystal startup ISTART,XOSC Enable XOSC XOSC Ready tSTART,XOSC tSTART,X16M / tSTART,X32M Figure 9 Current drawn at oscillator startup Figure 9 shows the current drawn by the crystal oscillator (XOSC) at startup. The tSTART,XOSC period is the time needed for the oscillator to start clocking. The length of tSTART,XOSC is dependent on the crystal specifications. The period following tSTART,XOSC to the end of tSTART,X16M /tSTART,X32M is fixed. This is the debounce period where the clock stabilizes before it is made available to rest of the system. Page 39 nRF51822 Product Specification v3.1 8.1.2 16 MHz crystal oscillator (16M XOSC) Symbol Description Note Min. Typ. Max. Units Test level fNOM,X16M Crystal frequency. 16 MHz N/A fTOL,X16M Frequency tolerance.1 ±502 ppm N/A fTOL,X16M,BLE Frequency tolerance, Bluetooth low energy applications.1 ±402 ppm N/A RS,X16M Equivalent series resistance. C0 ≤ 7 pF, CL,MAX ≤ 16 pF C0 ≤ 5 pF, CL,MAX ≤ 12 pF C0 ≤ 3 pF, CL,MAX ≤ 12 pF 50 100 Ω N/A 75 150 Ω N/A 100 200 Ω N/A PD,X16M Drive level. 100 μW N/A Cpin Input capacitance on XC1 and XC2 pads. 4 pF 1 IX16M Run current for 16 MHz crystal oscillator. SMD 2520 CL = 8 pF 4703 μA 1 IX16M,1M Run current for the 16 MHz crystal oscillator when used only for a Timer SMD 2520 CL = 8pF at 1 MHz or less. 2503 μA 1 ISTBY,X16M Standby current for 16 MHz crystal oscillator.4 SMD 2520 CL = 8 pF 25 μA 1 ISTART,XOSC Startup current for 16 MHz crystal oscillator. 1.1 mA 3 tSTART,XOSC Startup time for 16 MHz crystal oscillator. SMD 2520 CL = 8 pF 400 5005 μs 2 tSTART,X16M Total startup time (tSTART,XOSC + debounce period).6 SMD 2520 CL = 8 pF 800 μs 1 1. The Frequency tolerance relates to the amount of time the radio can be in transmit mode. See Table 38 on page 51. 2. Includes initial tolerance of the crystal, drift over temperature, aging, and frequency pulling due to incorrect load capac- itance. 3. This number includes the current used by the automated power and clock management system. 4. Standby current is the current drawn by the oscillator when there are no resources requesting the 16M, meaning there is no clock management active (see Table 33 on page 48). This value will depend on type of crystal. 5. Crystals with other specification than SMD 2520 may have much longer startup times. 6. This is the time from when the crystal oscillator is powered up until its output becomes available to the system. It includes both the crystal startup time and the debounce period. Table 22 16 MHz crystal oscillator Page 40 nRF51822 Product Specification v3.1 8.1.3 32 MHz crystal oscillator (32M XOSC) Symbol Description Note Min. Typ. Max. Units Test level fNOM,X32M Crystal frequency. 32 MHz N/A fTOL,X32M Frequency tolerance.1 ±502 ppm N/A Frequency tolerance, Bluetooth low fTOL,X32M,BLE energy applications.1 ±402 ppm N/A RS,X32M Equivalent series resistance. C0 ≤ 7 pF, CL,MAX ≤ 12 pF C0 ≤ 5 pF, CL,MAX ≤ 12 pF C0 ≤ 3 pF, CL,MAX ≤ 9 pF 30 60 Ω N/A 40 80 Ω N/A 50 100 Ω N/A PD,X32M Drive level. 100 μW N/A Cpin Input capacitance on XC1 and XC2 pads. 4 pF 1 IX32M Run current for 32 MHz crystal oscillator. SMD 2520 CL = 8 pF 5003 μA 1 IX32M,1M Run current for the 32 MHz crystal oscillator when used only for a SMD 2520 CL = 8 pF Timer at 1 MHz or less. 3003 μA 1 ISTBY,X32M Standby current for 32 MHz crystal oscillator.4 SMD 2520 CL = 8 pF 30 μA 1 ISTART,XOSC Startup current for 32 MHz crystal oscillator. 1.1 mA 3 tSTART,XOSC Startup time for 32 MHz crystal oscillator. SMD 2520 CL = 8 pF 300 4005 μs 1 tSTART,X32M Total startup time (tSTART,XOSC + debounce period).6 SMD 2520 CL = 8 pF 750 μs 1 1. The Frequency tolerance relates to the amount of time the radio can be in transmit mode. See Table 38 on page 51. 2. Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capac- itance. 3. This number includes the current used by the automated power and clock management system. 4. Standby current is the current drawn by the oscillator when there are no resources requesting the 32M, meaning there is no clock management active (see Table 33 on page 48). This value will depend on type of crystal. 5. Crystals with other specification than SMD 2520 may have much longer startup times. 6. This is the time from when the crystal oscillator is powered up until its output becomes available to the system. It includes both the crystal startup time and the debounce period. Table 23 32 MHz crystal oscillator Page 41 nRF51822 Product Specification v3.1 8.1.4 16 MHz RC oscillator (16M RCOSC) Symbol Description Min. Typ. Max. Units fNOM,RC16M Nominal frequency. 16 MHz fTOL,RC16M Frequency tolerance. ±1 ±5 % IRC16M Run current for 16 MHz RC oscillator. 7501 μA IRC16M,1M Run current for 16 MHz RCOSC when used only for a Timer at 1 MHz or less. 5401 μA tSTART,RC16M Startup time for 16 MHz RC oscillator. 4.2 5.2 μs IRC16M, START Startup current for 16 MHz RC oscillator. 400 μA 1. This number includes the current used by the automated power and clock management system. Test level N/A 3 1 1 1 1 8.1.5 Table 24 16 MHz RC oscillator 32.768 kHz crystal oscillator (32k XOSC) Symbol fNOM,X32k fTOL,X32k,BLE CL,X32k C0,X32k RS,X32k PD,X32k Cpin IX32k ISTART,X32k tSTART,X32k Description Crystal frequency. Frequency tolerance, Bluetooth low energy applications. Load capacitance. Shunt capacitance. Equivalent series resistance. Drive level. Input capacitance on XL1 and XL2 pads. Run current for 32.768 kHz crystal oscillator. Startup current for 32.768 kHz crystal oscillator. Startup time for 32.768 kHz crystal oscillator. Min. Typ. Max. Units 32.768 ±250 12.5 2 50 80 1 4 0.4 1 1.3 1.8 0.3 1 kHz ppm pF pF kΩ μW pF μA μA s Test level N/A N/A N/A N/A N/A N/A 1 1 1 2 Table 25 32.768 kHz crystal oscillator Page 42 nRF51822 Product Specification v3.1 8.1.6 32.768 kHz RC oscillator (32k RCOSC) Symbol fNOM,RC32k fTOL,RC32k fTOL,CAL,RC32k IRC32k tSTART,RC32k Description Nominal frequency. Frequency tolerance. Frequency tolerance. Run current. Startup time. Note Min. Typ. Max. Units Calibration interval 4 s 32.768 kHz ±2 % ±250 ppm 0.5 0.8 1.1 μA 390 487 μs Test level N/A 3 1 1 1 Table 26 32.768 kHz RC oscillator 8.1.7 32.768 kHz Synthesized oscillator (32k SYNT) Symbol Description fNOM,SYNT32k Nominal frequency. fTOL,SYNT Frequency tolerance. ISYNT32k tSTART,SYNT32k Run and startup current for 32.768 kHz Synthesized clock including the 16M XOSC. Startup time for 32.768 kHz Synthesized clock. Note Min. Typ. Max. Units 32.768 fTOL,XO16M ±8 fTOL,XO32M ±8 kHz ppm Test level 1 1 15 μA 1 406 μs 1 Table 27 32.768 kHz Synthesized oscillator Page 43 nRF51822 Product Specification v3.1 8.2 Power management Symbol VPOF VTOL VHYST Description Note Min. Typ. Max. Units Nominal power level warning thresholds (falling supply voltage). Accuracy as defined by VTOL Threshold voltage tolerance. Threshold voltage hysteresis. VPOF = 2.1 V VPOF = 2.3 V VPOF = 2.5 V VPOF = 2.7 V 2.1 2.3 2.5 V 2.7 ±5 % 46 62 79 mV 100 Test level 2 3 3 Table 28 Power Fail Comparator Symbol Description Min. Typ. Max. Units tHOLDRESETNORMAL Hold time for reset pin when doing a pin reset.1 0.2 μs Hold time for reset pin when doing a pin reset tHOLDRESETDEBUG during debug.1,2 100 μs 1. SWDCLK pin must be kept low during reset. 2. Bit 0 in the RESET register in the power management module must be set to 1 to enable reset during debug. Test level 1 1 Table 29 Pin Reset Page 44 nRF51822 Product Specification v3.1 Power on reset time (tPOR) is the time from when the supply starts rising to when the device comes out of reset and the CPU starts. The time increases with, and is inclusive of, supply rise time from 0 V to VDD. Table 30 gives tPOR for a number of supply rise times, simulated with a linear ramp from 0 V to VDD, over the supply voltage range 1.8 V to 3.6 V. Symbol tPOR, 10 μs tPOR, 1 ms tPOR, 10 ms tPOR, 100 ms Description Power on reset time, 10 μs rise time (0 V to VDD). Power on reset time, 10 μs rise time (0 V to VDD). Power on reset time, 10 μs rise time (0 V to VDD). Power on reset time, 10 μs rise time (0 V to VDD). Note Min. Typ. Max. Units Test level 0.7 2.4 19 ms 1 1.7 3.4 20 ms 1 11 12 28 ms 1 68 101 115 ms 1 Table 30 Power on reset time The data in Figure 10 and Table 31 show measured t_POR data. Measurements were taken using the reference circuit shown in Section 11.3.1 “QFAA QFN48 schematic with internal LDO setup” on page 79 with the given supply voltage and temperature conditions. Figure 10 Power on reset time (Test level 2) VDD 1.8 3.0 3.6 Rise Time from 10% to 90% of VDD 570 μs 605 μs 635 μs Table 31 Supply rise time at sample voltages for the measured data shown in Figure 10. Page 45 nRF51822 Product Specification v3.1 Symbol IOFF IOFF, RET, 8k IOFF2ON tOFF2ON ION,16k ION,32k t1V2 I1V2XO16 I1V2XO32 I1V2RC16 I1V2XO16,1M I1V2XO32,1M I1V2RC16,1M tXO Description Note Min. Typ. Max. Units Current in SYSTEM OFF, no RAM retention. Additional current in SYSTEM OFF per retained RAM block (8 kB) OFF to CPU execute transition current. OFF to CPU execute. SYSTEM-ON base current with 16 kB RAM enabled. SYSTEM-ON base current with 32 kB RAM enabled. Startup time for 1V2 regulator. Current drawn by 1V2 regulator and 16 MHz XOSC when both are on at the same time. Current drawn by 1V2 regulator and 32 MHz XOSC when both are on at the same time. Current drawn by 1V2 regulator and 16 MHz RCOSC when both are on at the same time. For HFCLK in 1 MHz mode3. Current drawn by 1V2 regulator and 16 MHz XOSC when both are on at the same time. For HFCLK in 1 MHz mode3. Current drawn by 1V2 regulator and 32 MHz XOSC when both are on at the same time. For HFCLK in 1 MHz mode3. Current drawn by 1V2 regulator and 16 MHz RCOSC when both are on at the same time. Startup time for the clock management system when the XTAL is in standby. See Table 33 on page 48. See Table 33 on page 48. See Table 33 on page 48. See Table 33 on page 48. See Table 33 on page 48. See Table 33 on page 48. 0.61 μA 0.61 μA 400 μA 9.6 10.6 μs 2.61 μA 3.81 μA 2.3 μs 8102 μA 8402 μA 8802 μA 5202 μA 5602 μA 6302 μA 2.3 5.3 μs Test level 2 2 1 1 2 2 1 1 1 1 1 1 1 1 Page 46 nRF51822 Product Specification v3.1 Symbol Description Note Min. Typ. Max. Units Test level t1V7 I1V7 FDCDC Startup time for 1V7 regulator Current drawn by 1V7 regulator DC/DC converter current conversion factor. 2 3.6 μs 1 105 μA 2 0.654 1.24 1 1. Add 1 μA to the current value if the device is used in Low voltage mode. 2. This number includes the current used by the automated power and clock management system. 3. For details on 1 MHz mode, see Section 4.2 “Timer/counters (TIMER)” on page 32. 4. FDCDC will vary depending on VDD and internal radio current consumption (IDD). Please refer to the nRF51 Series Refer- ence Manual, v3.0 or later, for a method to calculate IDD,DCDC. See Figure 11 on page 50 for a DC/DC conversion factor chart. Table 32 Power management Page 47 nRF51822 Product Specification v3.1 8.3 Block resource requirements Block Radio UART SPIS SPI TWI GPIOTE ADC TIMER ID 1 2 4 3, 4 3, 4 6 7 8, 9, 10 Resource requirements 1V2 HFCLK1 LFCLK 1V7 x x x x x x x x x x x x x x x RTC 11, 17 x TEMP RNG ECB 12 x x 13 x x 14 x x WDT 16 x QDEC 18 x x LPCOMP 19 CPU -- x x x 1. HFCLK could be one of the following; RC16M, XO16M, or XO32M. Comment Requires HFCLK XOSC. When receiver or transmitter are STARTed. Requested when CSN asserts. Only in input mode. Requires HFCLK XOSC. Requires 1V2 when a TIMER EVENT is triggered. HFCLK will be requested if the LFCLK is synthesized from HFCLK. Requires HFCLK XOSC. HFCLK will be requested if the LFCLK is synthesized from HFCLK. No resources required. Table 33 Clock and power requirements for different blocks 8.4 CPU Symbol Description Min. Typ. Max. Units ICPU, FLASH Run current at 16 MHz (XOSC). Executing code from flash memory. ICPU, RAM Run current at 16 MHz (XOSC). Executing code from RAM. ISTART, CPU CPU startup current. tSTART, CPU IDLE to CPU execute. 1. Includes CPU, flash, 1V2, 1V7, RC16M. 2. Includes CPU, RAM, 1V2, RC16M. 3. t1V2 if 1V2 regulator is not running already. 4.11 mA 2.42 mA 600 μA 03 μs Table 34 CPU specifications Test level 2 1 1 1 Page 48 nRF51822 Product Specification v3.1 8.5 Radio transceiver 8.5.1 General radio characteristics Symbol Description Note Min. Typ. Max. Units fOP PLLres Δf250 Δf1M Δf2M ΔfBLE bpsFSK Operating frequencies. PLL programming resolution. Frequency deviation at 250 kbps. Frequency deviation at 1 Mbps. Frequency deviation at 2 Mbps. Frequency deviation at BLE. On-air data rate. 1 MHz channel spacing. 2400 2483 ±225 250 1 ±170 ±170 ±320 ±250 ±275 2000 MHz MHz kHz kHz kHz kHz kbps Table 35 General radio characteristics 8.5.2 Radio current consumption with DC/DC disabled Test level N/A N/A 2 2 2 4 N/A Symbol Description Note Min. Typ. Max. Units Test level ITX,+4dBm TX only run current at POUT = +4 dBm. 1 16 ITX,0dBm TX only run current at POUT = 0 dBm. 1 10.5 ITX,-4dBm TX only run current at POUT = -4 dBm. 1 8 ITX,-8dBm TX only run current at POUT = -8 dBm. 1 7 ITX,-12dBm TX only run current at POUT = -12 dBm. 1 6.5 ITX,-16dBm TX only run current at POUT = -16 dBm. 1 6 ITX,-20dBm TX only run current at POUT = -20 dBm. 1 5.5 ITX,-30dBm TX only run current at POUT = -30 dBm. 1 5.5 ISTART,TX TX startup current. 2 7 IRX,250 RX only run current at 250 kbps. 12.6 IRX,1M RX only run current at 1 Mbps. 13 IRX,2M RX only run current at 2 Mbps. 13.4 ISTART,RX RX startup current. 3 8.7 mA 4 mA 4 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 1 mA 1 mA 4 mA 1 mA 1 1. Valid for data rates 250 kbps, 1 Mbps, and 2 Mbps. 2. Average current consumption (at 0 dBm TX output power) for TX startup (130 μs), and when changing mode from RX to TX (130 μs). 3. Average current consumption for RX startup (130 μs), and when changing mode from TX to RX (130 μs). Table 36 Radio current consumption with DC/DC disabled (NOC, VDD = 3 V) Page 49 nRF51822 Product Specification v3.1 8.5.3 Radio current consumption with DC/DC enabled Symbol Description ITX,+4dBm TX only run current at POUT = +4 dBm. ITX,0dBm TX only run current at POUT = 0 dBm. ITX,-4dBm TX only run current at POUT = -4 dBm. ITX,-8dBm TX only run current at POUT = -8 dBm. ITX,-12dBm TX only run current at POUT = -12 dBm. ITX,-16dBm TX only run current at POUT = -16 dBm. ITX,-20dBm TX only run current at POUT = -20 dBm. ITX,-30dBm TX only run current at POUT = -30 dBm. IRX,1M RX only run current at 1 Mbps. 1. Valid for data rates 250 kbps, 1 Mbps, and 2 Mbps. Note Min. Typ. Max. Units 1 11.8 mA 1 8.0 mA 1 6.3 mA 1 5.6 mA 1 5.3 mA 1 5.0 mA 1 4.7 mA 1 4.7 mA 9.7 mA Test level 2 2 2 2 2 2 2 2 2 Table 37 Radio current consumption with DC/DC enabled (NOC, VDD = 3 V) DC/DC conversion Factor 1,100 1,000 0,900 Tx - 1 Mbit (-12 dBm) Tx - 1 Mbit (0 dBm) Rx - 1Mbit Tx - 1 Mbit (+4 dBm) Conversion Factor (FDCDC) 0,800 0,700 0,600 2,1 2,3 2,5 2,7 2,9 3,1 3,3 3,5 Supply Voltage (VDD) Figure 11 DC/DC conversion factor as function of VDD See Power chapter in the nRF51 Series Reference Manual on how to use the DC/DC conversion factor to calculate the actual power consumption. Page 50 nRF51822 Product Specification v3.1 8.5.4 Transmitter specifications Symbol PRF PRFC PRFCR PWHISP PBW2 PBW1 PBW250 PRF1.2 PRF2.2 PRF1.1 PRF2.1 PRF1.250 PRF2.250 tTX,30 tTX,60 Description Maximum output power. RF power control range. RF power accuracy. RF power whisper mode. 20 dB bandwidth for modulated carrier (2 Mbps). 20 dB bandwidth for modulated carrier (1 Mbps). 20 dB bandwidth for modulated carrier (250 kbps). 1st Adjacent Channel Transmit Power. ±2 MHz (2 Mbps). 2nd Adjacent Channel Transmit Power. ±4 MHz (2 Mbps). 1st Adjacent Channel Transmit Power. ±1 MHz (1 Mbps). 2nd Adjacent Channel Transmit Power. ±2 MHz (1 Mbps). 1st Adjacent Channel Transmit Power. ±1 MHz (250 kbps). 2nd Adjacent Channel Transmit Power. ±2 MHz (250 kbps). Maximum consecutive transmission time, fTOL < ±30 ppm. Maximum consecutive transmission time, fTOL < ±60 ppm. Min. Typ. Max. Units 4 dBm 20 24 dB ±4 dB -30 dBm 1800 2000 kHz 950 1100 kHz 700 800 kHz -20 dBc Test level 4 2 1 2 2 2 2 2 -45 dBc 2 -20 dBc 2 -40 dBc 2 -25 dBc 2 -40 dBc 2 16 ms 1 4 ms 1 Table 38 Transmitter specifications Page 51 8.5.5 Receiver specifications Symbol Description Receiver operation PRXMAX Maximum received signal strength at < 0.1% PER. PRXSENS,2M Sensitivity (0.1% BER) at 2 Mbps. PRXSENS,1M Sensitivity (0.1% BER) at 1 Mbps. PRXSENS,250k Sensitivity (0.1% BER) at 250 kbps. PSENS IT 1 Mbps BLE Receiver sensitivity: Ideal transmitter. PSENS DT 1 Mbps BLE Receiver sensitivity: Dirty transmitter.1 RX selectivity - modulated interfering signal2 2 Mbps C/ICO C/I1ST C/I co-channel. 1st ACS, C/I 2 MHz. C/I2ND 2nd ACS, C/I 4 MHz. C/I3RD 3rd ACS, C/I 6 MHz. C/I6th 6th ACS, C/I 12 MHz. C/INth Nth ACS, C/I fi > 25 MHz. 1 Mbps C/ICO C/I co-channel (1 Mbps). C/I1ST 1st ACS, C/I 1 MHz. C/I2ND 2nd ACS, C/I 2 MHz. C/I3RD 3rd ACS, C/I 3 MHz. C/I6th 6th ACS, C/I 6 MHz. C/I12th 12th ACS, C/I 12 MHz. C/INth Nth ACS, C/I fi > 25 MHz. nRF51822 Product Specification v3.1 Min. Typ. Max. Units Test level 0 dBm 1 -85 dBm 2 -90 dBm 2 -96 dBm 2 -93 dBm 2 -91 dBm 2 12 dB 2 -4 dB 2 -24 dB 2 -28 dB 2 -44 dB 2 -50 dB 2 12 dB 2 4 dB 2 -24 dB 2 -30 dB 2 -40 dB 2 -50 dB 2 -53 dB 2 Page 52 nRF51822 Product Specification v3.1 Symbol Description Min. Typ. Max. Units Test level C/ICO C/I1ST C/I2ND C/I3RD C/I6th C/I12th C/INth 250 kbps C/I co-channel. 1st ACS, C/I 1 MHz. 2nd ACS, C/I 2 MHz. 3rd ACS, C/I 3 MHz. 6th ACS, C/I fi > 6 MHz. 12th ACS, C/I 12 MHz. Nth ACS, C/I fi > 25 MHz. Bluetooth Low Energy RX selectivity 4 dB 2 -10 dB 2 -34 dB 2 -39 dB 2 -50 dB 2 -55 dB 2 -60 dB 2 C/ICO C/I co-channel. 10 C/I1ST 1st ACS, C/I 1 MHz. 1 C/I2ND 2nd ACS, C/I 2 MHz. -25 C/I3+N ACS, C/I (3+n) MHz offset [n = 0, 1, 2, . . .]. -51 C/IImage lmage blocking level. -30 C/IImage±1MHz Adjacent channel to image blocking level (±1 MHz). -31 RX intermodulation3 dB 2 dB 2 dB 2 dB 2 dB 2 dB 2 P_IMD2Mbps P_IMD1Mbps P_IMD250kbps P_IMDBLE IMD performance, 2 Mbps, 3rd, 4th, and 5th offset channel. IMD performance, 1 Mbps, 3rd, 4th, and 5th offset channel. IMD performance, 250 kbps, 3rd, 4th, and 5th offset channel. IMD performance, 1 Mbps BLE, 3rd, 4th, and 5th offset channel. -41 dBm 2 -40 dBm 2 -36 dBm 2 -39 dBm 2 1. As defined in the Bluetooth Core Specification v4.0 Volume 6: Core System Package (Low Energy Controller Volume). 2. Wanted signal level at PIN = -67 dBm. One interferer is used, having equal modulation as the wanted signal. The input power of the interferer where the sensitivity equals BER = 0.1% is presented. 3. Wanted signal level at PIN = -64 dBm. Two interferers with equal input power are used. The interferer closest in fre- quency is not modulated, the other interferer is modulated equal with the wanted signal. The input power of interferers where the sensitivity equals BER = 0.1% is presented. Table 39 Receiver specifications Page 53 nRF51822 Product Specification v3.1 8.5.6 Radio timing parameters Symbol tTXEN tTXDISABLE tRXEN tRXDISABLE tTXCHAIN tRXCHAIN Description 250 k 1 M 2 M BLE Jitter Units Time between TXEN task and READY event. 132 132 132 140 0 μs Time between DISABLE task and DISABLED event when the radio was in TX. 10 4 3 4 1 μs Time between the RXEN task and READY event. 130 130 130 138 0 μs Time between DISABLE task and DISABLED event when the radio was in RX. 0 0 0 0 1 μs TX chain delay. 5 1 0.5 1 0 μs RX chain delay. 12.5 3 2 3 0 μs Table 40 Radio timing 8.5.7 Antenna matching network requirements Symbol ZQFN48,ANT1,2 ZWLCSP,ANT1,2 Description Min. Typ. Max. Units Optimum differential impedance at 2.4 GHz seen into the matching network from pin ANT1 and 15 + j85 Ω ANT2 on the QFN48 packet. Optimum differential impedance at 2.4 GHz seen into the matching network from pin ANT1 and 12.6 + j106 Ω ANT2 on the WLCSP packet. Test level 1 1 Table 41 Optimum differential load impedance 8.6 Received Signal Strength Indicator (RSSI) specifications Symbol RSSIACC RSSIRESOLUTION RSSIPERIOD RSSICURRENT Description Note Min. Typ. Max. Units RSSI accuracy. Valid range -50 dBm to -80 dBm. ±6 dB RSSI resolution. 1 dB Sample period. 8.8 μs Current consumption in addition to IRX. 250 μA Table 42 RSSI specifications Test level 2 1 1 1 Page 54 nRF51822 Product Specification v3.1 8.7 Universal Asynchronous Receiver/Transmitter (UART) specifications Symbol IUART1M IUART115k IUART1k2 fUART tCTSH Description Note Min. Typ. Max. Units Run current at max baud rate. Run current at 115200 bps. Run current at 1200 bps. Baud rate for UART. CTS high time. 230 μA 220 μA 210 μA 1.2 1000 kbps 1 μs Table 43 UART specifications Test level 1 1 1 N/A 1 Page 55 nRF51822 Product Specification v3.1 8.8 Serial Peripheral Interface Slave (SPIS) specifications Symbol Description Min. Typ. Max. Units ISPIS125K Run current for SPI slave at 125 kbps.1 ISPIS2M Run current for SPI slave at 2 Mbps.1 fSPIS Bit rates for SPIS. 1. CSN asserted. 180 μA 183 μA 0.125 2 Mbps Table 44 SPIS specifications tCWH CSN SCK MOSI MISO tCC tCH tCL tDH tDC b7 tCSD b7 b6 tCD tCCH b0 b0 tCDZ Figure 12 SPIS timing diagram, one byte transmission, SPI Mode 0 Test level 1 1 N/A Symbol Description Note Min. Typ. Max. Units tDC Data to SCK setup. 10 ns tDH SCK to Data hold. 10 ns tCSD CSN to Data valid. Low power mode.1 Constant latency mode.1 7100 2100 ns tCD SCK to Data Valid. CLOAD = 10 pF 972 ns tCL SCK Low time. 40 ns tCH SCK High time. 40 ns tCC CSN to SCK Setup. Low power mode.1 Constant latency mode.1 7000 2000 ns tCCH Last SCK edge to CSN Hold. 2000 ns tCWH CSN Inactive time. 300 ns tCDZ CSN to Output High Z. 40 ns fSCK SCK frequency. 0.125 2 MHz tR,tF SCK Rise and Fall time. 100 ns 1. For more information on how to control the sub power modes, see the nRF51 Series Reference Manual. 2. Increases/decreases with 1.2 ns/pF load. Test level 1 1 1 1 1 1 1 1 1 1 1 1 Table 45 SPIS timing parameters Page 56 nRF51822 Product Specification v3.1 8.9 Serial Peripheral Interface (SPI) Master specifications Symbol ISPI125K ISPI4M fSPI Description Run current for SPI master at 125 kbps. Run current for SPI master at 4 Mbps. Bit rates for SPI. Min. Typ. Max. Units 180 μA 200 μA 0.125 4 Mbps Test level 1 1 N/A Table 46 SPI specifications SCK MISO MOSI tCH tCL tDH tDC b7 b7 b6 tCD b0 b0 Figure 13 SPI timing diagram, one byte transmission, SPI mode 0 Symbol Description tDC Data to SCK setup. tDH SCK to Data hold. tCD SCK to Data valid. tCL SCK Low time. tCH SCK High time. fSCK SCK Frequency. tR,tF SCK Rise and Fall time. 1. Increases/decreases with 1.2 ns/pF load. Note CLOAD = 10 pF Min. Typ. Max. Units 10 10 40 40 0.125 ns ns 971 ns ns ns 4 MHz 100 ns Test level 1 1 1 1 1 1 1 Table 47 SPI timing parameters Page 57 nRF51822 Product Specification v3.1 8.10 I2C compatible Two Wire Interface (TWI) specifications Symbol Description Note Min. Typ. Max. Units Test level I2W100K I2W400K f2W tTWI,START Run current for TWI at 100 kbps. 380 μA 1 Run current for TWI at 400 kbps. 400 μA 1 Bit rates for TWI. 100 400 kbps N/A Time from STARTRX/STARTTX task is Low power mode.1 given until start condition. Constant latency mode.1 3 1 4.4 μs 1 1. For more information on how to control the sub power modes, see the nRF51 Series Reference Manual. Table 48 TWI specifications SCL tHD_SDA tSU_DAT SDA 1/fSCL tHD_DAT tSU_STO tBUF Figure 14 SCL/SDA timing Symbol fSCL tHD_STA tSU_DAT tHD_DAT tSU_STO tBUF Description SCL clock frequency. Hold time for START and repeated START condition. Data setup time before positive edge on SCL. Data hold time after negative edge on SCL. Setup time from SCL goes high to STOP condition. Bus free time between STOP and START conditions. Standard Min. Max. Fast Min. Max. Units Test level 100 400 kHz 1 5200 1300 ns 1 300 300 ns 1 300 300 ns 1 5200 1300 ns 1 4700 1300 ns 1 Table 49 TWI timing parameters Page 58 nRF51822 Product Specification v3.1 8.11 GPIO Tasks and Events (GPIOTE) specifications Symbol IGPIOTE,IN IGPIOTE,OUT IGPIOTE,IDLE Description Min. Typ. Max. Units Run current with 1 or more GPIOTE active channels in Input mode. 22 μA Run current with 1 or more GPIOTE active channels in Output mode. 0.1 μA Run current when all channels in Idle mode. PORT event can be generated with a delay of up to t1V2. 0.1 μA Test level 1 1 1 Table 50 GPIOTE specifications Note: Setting up one or more GPIO DETECT signals to generate PORT EVENT, which can be used either as a wakeup source or to give an interrupt, will not lead to an increase of the current consumption. Page 59 nRF51822 Product Specification v3.1 8.12 Analog to Digital Converter (ADC) specifications Note: HFCLK XOSC is required to get the stated ADC accuracy. Symbol Description DNL10b Differential non-linearity (10 bit mode). INL10b Integral non-linearity (10 bit mode). VOS Offset error. eG Gain error. VREF_VBG Internal Band Gap reference voltage (VBG). VREF_VBG_ERR Internal Band Gap reference voltage error. TCREF_VBG_DRIFT Internal Band Gap reference voltage drift. VREF_EXT External reference voltage (AREF0/1). VREF_VDD_LIM Limited supply voltage range for ADC using VDD with prescaler as the reference. CONFIG.REFSEL = SupplyOneHalfPrescaling CONFIG.REFSEL = SupplyOneThirdPrescaling tADC10b Time required to convert a single sample in 10 bit mode. tADC9b Time required to convert a single sample in 9 bit mode. tADC8b Time required to convert a single sample in 8 bit mode. IADC Current drawn by ADC during conversion. ADC_ERR_1V8 ADC_ERR_2V2 ADC_ERR_2V6 ADC_ERR_3V0 ADC_ERR_3V4 Absolute error when used for battery measurement at 1.8 V, 2.2 V, 2.6 V, 3.0 V, and 3.4 V. 1. Source impedance less than 5 kΩ. 2. Internal reference, input from VDD/3, 10 bit mode. Note 1 2 Min. Typ. Max. Units <1 LSB Test level 2 2 LSB 2 -2 +2 % 2 -2 +2 % 2 1.20 V V 2 -1.5 +1.5 % 2 -200 +200 ppm/°C 2 0.83 1.2 1.3 V 1 1.7 2.6 V 1 2.5 3.6 V 1 68 μs 1 36 μs 1 20 μs 1 260 μA 1 3 LSB 2 2 LSB 2 1 LSB 2 1 LSB 2 1 LSB 2 Table 51 Analog to Digital Converter (ADC) specifications Page 60 nRF51822 Product Specification v3.1 8.13 Timer (TIMER) specifications Symbol ITIMER0/1/2 ITIMER0/1/2,1M tTIMER,START Description Note Min. Typ. Max. Units Timer current when running from HFCLK in 16 MHz mode. Timer current when running from HFCLK in 1 MHz mode. Time from START task is given until timer starts counting. 30 μA 4 μA 0.25 μs Table 52 Timer specifications Test level 1 1 1 8.14 Real Time Counter (RTC) Symbol IRTC Description Timer (LFCLK source). Min. Typ. Max. Units 0.1 μA Test level 1 Table 53 RTC 8.15 Temperature sensor (TEMP) Note: HFCLK XOSC is required to get the stated accuracy. Symbol Description ITEMP Run current for Temperature sensor. tTEMP Time required for temperature measurement. TRANGE Temperature sensor range. TACC Temperature sensor accuracy.1 TRES Temperature sensor resolution. 1. Stated temperature accuracy is valid in the range 0 to 60°C. Temperature accuracy outside the 0 to 60°C range is ± 8°C. Min. Typ. Max. Units 185 μA 35 μs -25 75 °C -4 +4 °C 0.25 °C Test level 1 1 N/A N/A 1 Table 54 Temperature sensor Page 61 nRF51822 Product Specification v3.1 8.16 Random Number Generator (RNG) specifications Symbol IRNG tRNG,RAW tRNG,UNI Description Note Min. Typ. Max. Units Run current at 16 MHz. 60 μA Run time per byte in RAW mode. Uniform distribution of 0 and 1 is not 167 guaranteed. μs Uniform distribution of 0 and 1 is Run time per byte in Uniform mode. guaranteed. Time to generate a byte 677 μs cannot be guaranteed. Table 55 Random Number Generator (RNG) specifications Test level 1 1 1 8.17 AES Electronic Codebook Mode Encryption (ECB) specifications Symbol IECB tSTARTECB, ENDECB Description Min. Typ. Max. Units Run current for ECB. Time for a 16 byte AES block encrypt. 550 μA 8.5 17 μs Table 56 ECB specifications Test level 1 1 8.18 AES CCM Mode Encryption (CCM) specifications Symbol ICCM Description Min. Typ. Max. Units Run current for CCM. 550 μA Table 57 CCM specifications Test level 1 8.19 Accelerated Address Resolver (AAR) specifications Symbol IAAR tSTART,RESOLVED Description Min. Typ. Max. Units Run current for AAR. Time for address resolution of 8 IRKs. 550 μA 68 μs Table 58 AAR specifications Test level 1 1 Page 62 nRF51822 Product Specification v3.1 8.20 Watchdog Timer (WDT) specifications Symbol IWDT tWDT Description Min. Typ. Max. Units Run current for watchdog timer. Time out interval, watchdog timer. 0.1 μA 30 μs 36 hrs Table 59 Watchdog Timer specifications Test level 1 1 8.21 Quadrature Decoder (QDEC) specifications Symbol IQDEC tSAMPLE tLED Description Note Min. Typ. Max. Units 12 μA Time between sampling signals from quadrature decoder. 128 16384 μs Time from LED is turned on to Only valid for optical signals are sampled. sensors. 0 511 μs Table 60 Quadrature Decoder specifications Test level 1 N/A N/A Page 63 nRF51822 Product Specification v3.1 8.22 Non-Volatile Memory Controller (NVMC) specifications Flash write is done by executing a program that writes one word (32 bit) consecutively after the other to the flash memory. The program doing the flash writes could be set up to run from flash or from RAM. The timing of one flash write operation depends on whether the next instructions following the flash write will be fetched from flash or from RAM. Any fetch from flash done before the write operation is finished will give tWRITE,FLASH timing. The flash memory is organized in 256 byte rows starting at CODE and UICR start address. Crossing from one row to another will affect the flash write timing when running from RAM. The time it takes to program the flash memory will depend on different parameters: • Whether the program doing the flash write is running from RAM or running from flash. • When running from RAM we will have different timing for: • First write operation. • Repeated write operations within the same row. • Repeated write operation that are crossing from one row to another. Symbol Description Note Min. Typ. Max. Units Test level tERASEALL Erase flash memory. 1, 2 22.3 ms 1 tPAGEERASEALL Erase page in flash memory. 1, 2 22.3 ms 1 tWRITE,FLASH Program running from flash. 1, 3 Write one word to flash memory. 46.3 μs 1 tWRITE,RAM,1st Program running from RAM. Write 1 the first word to flash memory. 39.3 μs 1 Program running from RAM. tWRITE,RAM,2nd Repeated writes operations following the first, within the 1 same row. 22.3 μs 1 tWRITE,RAM,3rd Program running from RAM. Repeated write operation, new 1 word is located on a different row compare to the previous write. 46.3 μs 1 1. Max timing is assuming using RC16M, worst case tolerance. 2. The CPU will be halted for the duration of NVMC operations if the CPU tries to fetch data/code from the flash memory. 3. The CPU will be halted for the duration of NVMC operations. Table 61 NVMC specifications Page 64 nRF51822 Product Specification v3.1 8.23 General Purpose I/O (GPIO) specifications Symbol Parameter (condition) VIH Input high voltage. VIL Input low voltage. VOH Output high voltage (std. drive, 0.5 mA). VOH Output high voltage (high-drive, 5 mA). VOL Output low voltage (std. drive, 0.5 mA). VOL Output low voltage (high-drive, 5 mA). RPU Pull-up resistance. RPD Pull-down resistance. 1. Maximum number of pins with 5 mA high drive is 3. Note 1 Min. 0.7 VDD VSS VDD-0.3 VDD-0.3 VSS VSS 11 11 Typ. 13 13 Table 62 General Purpose I/O (GPIO) specifications Max. VDD 0.3 VDD VDD VDD 0.3 0.3 16 16 Units V V V V V V kΩ kΩ 8.24 Low Power Comparator (LPCOMP) specifications Symbol Description Min. Typ. Max. Units ILPC Run current for LPCOMP. tLPCANADETOFF Time from VIN crossing to ANADETECT signal generated when in System OFF. tLPCANADETON Time from VIN crossing to ANADETECT signal generated when in System ON. tLPCOMPSTARTUP Startup time for the Low Power Comparator. 1. For 50 mV overdrive 0.5 μA 151 μs 151 μs 40 μs Table 63 Low power comparator specifications Test level 1 1 1 1 Page 65 nRF51822 Product Specification v3.1 9 Mechanical specifications This chapter covers the mechanical specifications for all chip variants of the nRF51822. The following table lists the cross references to the package sections describing each package variant. Package QFN48 CDAB CEAA CFAC Cross references Section 9.1 “QFN48 package” on page 66 Section 9.2 “CDAB WLCSP package” on page 67 Section 9.3 “CEAA WLCSP package” on page 68 Section 9.4 “CFAC WLCSP package” on page 69 Table 64 Cross references to package variants 9.1 QFN48 package Package QFN48 (6 x 6) Figure 15 QFN48 6 x 6 mm package A A1 A3 0.80 0.00 0.85 0.02 0.2 0.90 0.05 b D, E D2, E2 e 0.15 4.50 0.20 6.0 4.60 0.4 0.25 4.70 K L 0.20 0.35 Min. 0.40 Nom. 0.45 Max. Table 65 QFN48 dimensions in millimeters Page 66 9.2 CDAB WLCSP package nRF51822 Product Specification v3.1 Package CDAB WLCSP Figure 16 CDAB WLCSP package A A1 A3 b D E D2 E2 e K L 0.12 0.33 0.16 3.45 3.28 Min. 0.50 0.15 0.35 0.20 3.50 3.33 3.2 2.8 0.4 1.41 1.61 Nom. 0.55 0.18 0.37 0.24 3.55 3.38 Max. Table 66 CDAB WLCSP package dimensions in millimeters Page 67 9.3 CEAA WLCSP package nRF51822 Product Specification v3.1 Package CEAA WLCSP Figure 17 CEAA WLCSP package A A1 A3 b D E D2 E2 e K L 0.12 0.33 0.16 3.45 3.78 Min. 0.50 0.15 0.35 0.20 3.50 3.83 3.2 3.2 0.4 1.66 1.61 Nom. 0.55 0.18 0.37 0.24 3.55 3.88 Max. Table 67 CEAA WLCSP package dimensions in millimeters Page 68 9.4 CFAC WLCSP package nRF51822 Product Specification v3.1 Package CFAC WLCSP Figure 18 CFAC WLCSP package A A1 A3 b D E D2 E2 e K L 0.12 0.33 0.16 3.78 3.78 Min. 0.50 0.15 0.35 0.20 3.83 3.83 3.2 3.2 0.4 1.66 1.78 Nom. 0.55 0.18 0.37 0.24 3.88 3.88 Max. Table 68 CFAC WLCSP package dimensions in millimeters Page 69 nRF51822 Product Specification v3.1 10 Ordering information 10.1 Chip marking N5 1 8 2 2

Table 69 Package marking 10.2 Inner box label P/N#: NRFxxxxx-- Trace Code: QTY:

Figure 19 Inner box label Page 70 10.3 Outer box label FROM: TO: nRF51822 Product Specification v3.1 DEVICE: NRFxxxxx-- S/O No.:

CUSTOMER PO No.: WF LOT No.: Trace Code: QTY: PACKAGE COUNT: of PACKAGE WEIGHT: KGS COUNTRY OF ORIGIN: Figure 20 Outer box label 10.4 Order code n R F 5 1 8 2 2 -

- Table 70 Order code Page 71 nRF51822 Product Specification v3.1 10.5 Abbreviations Abbreviation N51/nRF51 822

Definition and Implemented Codes nRF51 series product Part code Package code Variant code Build code H - Hardware version code P - Production configuration code (production site, etc.) F - Firmware version (Only visible on shipping container label) Tracking code YY - Year code WW - Assembly week number LL - Wafer lot code Container code Table 71 Abbreviations Page 72 nRF51822 Product Specification v3.1 10.6 Code ranges and values QF CD CE CF Packet QFN WLCSP WLCSP WLCSP Size (mm) 6x6 3.50 x 3.33 3.50 x 3.83 3.83 x 3.83 Pin/Ball Count 48 56 62 62 Pitch (mm) 0.4 0.4 0.4 0.4 Table 72 Package codes AA AB AC Flash (kB) 256 128 256 RAM (kB) 16 16 32 DC/DC Bond-out YES YES YES Table 73 Variant codes [A. .Z] Description Hardware version/revision identifier (incremental) Table 74 Hardware version codes

[0. .9] [A. .Z] Description Production device identifier (incremental) Engineering device identifier (incremental) Table 75 Production version codes [A. .N, P. .Z] [0] Description Version of programmed firmware Delivered without preprogrammed firmware Table 76 Firmware version codes [12. .99] Description Production year: 2012 to 2099 Table 77 Year codes Page 73 [1. .52] Description Week of production Table 78 Week codes [AA. .ZZ] Description Wafer production lot identifier Table 79 Lot codes R7 R T Description 7” Reel 13” Reel Tray Table 80 Container codes nRF51822 Product Specification v3.1 Page 74 nRF51822 Product Specification v3.1 10.7 Product options 10.7.1 nRF ICs Order code nRF51822-QFAA-R7 nRF51822-QFAB-R7 nRF51822-QFAC-R7 nRF51822-QFAA-R nRF51822-QFAB-R nRF51822-QFAC-R nRF51822-CEAA-R7 nRF51822-CDAB-R7 nRF51822-CFAC-R7 nRF51822-CEAA-R nRF51822-CDAB-R nRF51822-CFAC-R nRF51822-QFAA-T nRF51822-QFAB-T nRF51822-QFAC-T 1. Minimum Order Quantity. MOQ1 1000 3000 1500 7000 490 10.7.2 Development tools Table 81 Order code Order code Description nRF51-DK1 nRF51-Dongle1 nRF51 Bluetooth Smart/ANT/2.4 GHz RF Development Kit nRF51 USB dongle for emulator, sniffer, firmware development 1. Uses the nRF51422-QFAC version of the chip (capable of running both Bluetooth low energy and ANT). Table 82 Development tools Page 75 nRF51822 Product Specification v3.1 11 Reference circuitry For the following reference layouts, C_pcb1 and C_pcb2, between X1 and XC1/XC2, is estimated to 0.5 pF each. The exposed center pad of the QFN48 package must be connected to supply ground for proper device operation. 11.1 PCB guidelines A well designed PCB is necessary to achieve good RF performance. A poor layout can lead to loss in performance or functionality. A qualified RF layout for the IC and its surrounding components, including matching networks, can be downloaded from www.nordicsemi.com. To ensure optimal performance it is essential that you follow the schematics- and layout references closely. Especially in the case of the antenna matching circuitry (components between device pins ANT1,ANT2, VDD_PA and the antenna), any changes to the layout can change the behavior, resulting in degradation of RF performance or a need to change component values. All the reference circuits are designed for use with a 50 ohm single end antenna. A PCB with a minimum of two layers, including a ground plane, is recommended for optimal performance. On PCBs with more than two layers, put a keep-out area on the inner layers directly below the antenna matching circuitry (components between device pins ANT1, ANT2, VDD_PA, and the antenna) to reduce the stray capacitances that influence RF performance. A matching network is needed between the differential RF pins ANT1 and ANT2 and the antenna, to match the antenna impedance (normally 50 ohm) to the optimum RF load impedance for the chip. For optimum performance, the impedance for the matching network should be set as described in Section 8.5.7 “Antenna matching network requirements” on page 54 along with the recommended QFN48 package reference circuitry from Section 11.3 “QFAA QFN48 package” on page 79 and WLCSP package reference circuitry from Section 11.7 “CEAA WLCSP package” on page 103. The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors. See the schematics for recommended decoupling capacitor values. The supply voltage for the chip should be filtered and routed separately from the supply voltages of any digital circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via hole should be used for each VSS pin. Full-swing digital data or control signals should not be routed close to the crystal or the power supply lines. Capacitive loading of full-swing digital output lines should be minimized in order to avoid radio interference. Page 76 nRF51822 Product Specification v3.1 11.1.1 PCB layout example The PCB layout shown in Figure 21 is a reference layout for the QFN package with internal LDO setup. For all available reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Top silk screen No components in bottom layer Top view Bottom view Figure 21 PCB layout example for QFN48 package with internal LDO setup Page 77 nRF51822 Product Specification v3.1 11.2 Reference design schematics The following sections covers the reference design schematics for all chip variants of the nRF51822. Table 83 lists the cross references to the package sections describing each package variant. For package QFAA QFAB QFAC CDAB CEAA CFAC See section: Section 11.3 “QFAA QFN48 package” on page 79 Section 11.4 “QFAB QFN48 package” on page 85 Section 11.5 “QFAC QFN48 package” on page 91 Section 11.6 “CDAB WLCSP package” on page 97 Section 11.7 “CEAA WLCSP package” on page 103 Section 11.8 “CFAC WLCSP package” on page 109 Table 83 Cross references to the reference design variants Page 78 nRF51822 Product Specification v3.1 11.3 QFAA QFN48 package Documentation for the QFAA QFN48 package reference circuit, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from www.nordicsemi.com. 11.3.1 QFAA QFN48 schematic with internal LDO setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF 48 P0.29 47 P0.28 46 XL1 45 XL2 44 P0.25 43 P0.24 42 P0.23 41 P0.22 40 P0.21 39 38 37 VCC_nRF 1 2 C7 P0.30 3 P0.00 4 100nF P0.01 5 P0.02 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 VCC_nRF P0.07 11 12 C11 VDD DCC P0.30 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD 100nF VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 VCC_nRF nRF51x22 AVDD AVDD VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 36 35 34 33 32 31 30 29 28 27 26 25 P0.20 P0.19 P0.18 P0.17 C9 1.0nF C5 L1 2.2pF 4.7nH L2 10nH L3 3.3nH C4 1.0pF C10 47nF C3 2.2nF U1 nRF51x22-QFAA C6 1.5pF 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO 23 SWCLK 24 GND Figure 22 QFAA QFN48 with internal LDO setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 79 nRF51822 Product Specification v3.1 11.3.1.1 Bill of Materials Designator Value Description C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% C3 2.2 nF Capacitor, X7R, ±10% C4 1.0 pF Capacitor, NP0, ±0.1 pF C5 2.2 pF Capacitor, NP0, ±0.1 pF C6 1.5 pF Capacitor, NP0, ±0.1 pF C7, C8, C11 100 nF Capacitor, X7R, ±10% C9 1.0 nF Capacitor, X7R, ±10% C10 47 nF Capacitor, X7R, ±10% L1 4.7 nH High frequency chip inductor ±5% L2 10 nH High frequency chip inductor ±5% L3 3.3 nH High frequency chip inductor ±5% U1 nRF51822-QFAA RF SoC X1 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm X2 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 QFN40P600X600X90-48N 2.5 x 2.0 mm FC-135 Table 84 QFAA QFN48 with internal LDO setup Page 80 nRF51822 Product Specification v3.1 11.3.2 QFAA QFN48 schematic with low voltage mode setup Optional C13 C1 12pF C14 X2 32.768kHz 12pF C2 X1 16MHz 12pF 12pF C8 100nF P0.29 P0.28 XL1 XL2 P0.25 P0.24 P0.23 P0.22 P0.21 VCC_1V8 1 2 C7 P0.30 3 P0.00 4 100nF P0.01 5 P0.02 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 VCC_1V8 P0.07 11 12 C11 VDD DCC P0.30 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD 100nF VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 48 47 46 45 44 43 42 41 40 39 38 37 VCC_1V8 nRF51x22 AVDD AVDD VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 36 35 34 33 32 31 30 29 28 P0.20 27 P0.19 26 P0.18 25 P0.17 U1 nRF51x22-QFAA C9 1.0nF VCC_1V8 C10 47nF C5 L1 2.2pF 4.7nH L2 10nH C3 2.2nF L3 3.3nH C4 1.0pF C6 1.5pF 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO 23 SWCLK 24 GND Figure 23 QFAA QFN48 with low voltage mode setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 81 nRF51822 Product Specification v3.1 11.3.2.1 Bill of Materials Designator Value Description C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% C3 2.2 nF Capacitor, X7R, ±10% C4 1.0 pF Capacitor, NP0, ±0.1 pF C5 2.2 pF Capacitor, NP0, ±0.1 pF C6 1.5 pF Capacitor, NP0, ±0.1 pF C7, C8, C11 100 nF Capacitor, X7R, ±10% C9 1.0 nF Capacitor, X7R, ±10% C10 47 nF Capacitor, X7R, ±10% L1 4.7 nH High frequency chip inductor ±5% L2 10 nH High frequency chip inductor ±5% L3 3.3 nH High frequency chip inductor ±5% U1 nRF51822-QFAA RF SoC X1 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm X2 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 QFN40P600X600X90-48N 2.5 x 2.0 mm FC-135 Table 85 QFAA QFN48 with low voltage mode setup Page 82 nRF51822 Product Specification v3.1 11.3.3 QFAA QFN48 schematic with DC/DC converter setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz VCC_nRF AVDD 1 L5 L4 2 15nH 10μH C12 1.0μF P0.30 3 C4.77μFPPP000...000012 4 5 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 VCC_nRF P0.07 11 12 C11 VDD DCC P0.30 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD 100nF VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 48 P0.29 47 P0.28 46 XL1 45 XL2 44 P0.25 43 P0.24 42 P0.23 41 P0.22 40 P0.21 39 38 37 C8 100nF AVDD nRF51x22 AVDD AVDD VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 36 35 34 33 32 31 30 29 28 27 26 25 P0.20 P0.19 P0.18 P0.17 C9 1.0nF C5 L1 2.2pF 4.7nH L2 10nH L3 3.3nH C4 1.0pF C10 47nF C3 2.2nF U1 nRF51x22-QFAA C6 1.5pF 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO 23 SWCLK 24 GND Figure 24 QFAA QFN48 with DC/DC converter setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 83 nRF51822 Product Specification v3.1 11.3.3.1 Bill of Materials Designator Value Description C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% C3 2.2 nF Capacitor, X7R, ±10% C4 1.0 pF Capacitor, NP0, ±0.1 pF C5 2.2 pF Capacitor, NP0, ±0.1 pF C6 1.5 pF Capacitor, NP0, ±0.1 pF C7 4.7 μF Capacitor, X5R, ±10% C8, C11 100 nF Capacitor, X7R, ±10% C9 1.0 nF Capacitor, X7R, ±10% C10 47 nF Capacitor, X7R, ±10% C12 1.0 μF Capacitor, X7R, ±10% L1 4.7 nH High frequency chip inductor ±5% L2 10 nH High frequency chip inductor ±5% L3 3.3 nH High frequency chip inductor ±5% L4 10 μH Chip inductor, IDC,min = 50 mA, ±20% L5 15 nH High frequency chip inductor ±10% U1 nRF51822-QFAA RF SoC X1 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm X2 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint 0402 0402 0402 0402 0402 0603 0402 0402 0402 0603 0402 0402 0402 0603 0402 QFN40P600X600X90-48N 2.5 x 2.0 mm FC-135 Table 86 QFAA QFN48 with DC/DC converter setup Page 84 nRF51822 Product Specification v3.1 11.4 QFAB QFN48 package Documentation for the QFAB QFN48 package reference circuit, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from www.nordicsemi.com. 11.4.1 QFAB QFN48 schematic with internal LDO setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF P0.29 P0.28 XL1 XL2 P0.25 P0.24 P0.23 P0.22 P0.21 VCC_nRF 1 2 C7 P0.30 3 P0.00 4 100nF P0.01 5 P0.02 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 VCC_nRF P0.07 11 12 C11 100nF VDD DCC P0.30 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 48 47 46 45 44 43 42 41 40 39 38 37 VCC_nRF nRF51x22 AVDD AVDD VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 36 35 34 33 32 31 30 29 28 27 26 25 P0.20 P0.19 P0.18 P0.17 C9 1.0nF C5 L1 2.2pF 4.7nH L2 10nH L3 3.3nH C4 1.0pF C10 47nF C3 2.2nF U1 nRF51x22-QFAB C6 1.5pF 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO 23 SWCLK 24 GND Figure 25 QFAB QFN48 with internal LDO setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 85 nRF51822 Product Specification v3.1 11.4.1.1 Bill of Materials Designator Value Description C1, C2, C13, C14 C3 C4 C5 C6 C7, C8, C11 C9 C10 L1 L2 L3 U1 X1 X2 12 pF 2.2 nF 1.0 pF 2.2 pF 1.5 pF 100 nF 1.0 nF 47 nF 4.7 nH 10 nH 3.3 nH nRF51822-QFAB 16 MHz 32.768 kHz Capacitor, NP0, ±2% Capacitor, X7R, ±10% Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% High frequency chip inductor ±5% High frequency chip inductor ±5% High frequency chip inductor ±5% RF SoC Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 QFN40P600X600X90-48N 2.5 x 2.0 mm FC-135 Table 87 QFAB QFN48 with internal LDO setup Page 86 nRF51822 Product Specification v3.1 11.4.2 QFAB QFN48 schematic with low voltage mode setup Optional C13 C1 12pF C14 X2 32.768kHz 12pF C2 X1 16MHz 12pF 12pF C8 100nF 48 P0.29 47 P0.28 46 XL1 45 XL2 44 P0.25 43 P0.24 42 P0.23 41 P0.22 40 P0.21 39 38 37 VCC_1V8 1 2 C7 P0.30 3 P0.00 4 100nF P0.01 5 P0.02 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 VCC_1V8 P0.07 11 12 C11 VDD DCC P0.30 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD 100nF VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 VCC_1V8 nRF51x22 AVDD AVDD VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 36 35 34 33 32 31 30 29 28 P0.20 27 P0.19 26 P0.18 25 P0.17 U1 nRF51x22-QFAB C9 1.0nF VCC_1V8 C10 47nF C5 L1 2.2pF 4.7nH L2 10nH C3 2.2nF L3 3.3nH C4 1.0pF C6 1.5pF 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO 23 SWCLK 24 GND Figure 26 QFAB QFN48 with low voltage mode setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 87 nRF51822 Product Specification v3.1 11.4.2.1 Bill of Materials Designator Value Description C1, C2, C13, C14 C3 C4 C5 C6 C7, C8, C11 C9 C10 L1 L2 L3 U1 X1 X2 12 pF 2.2 nF 1.0 pF 2.2 pF 1.5 pF 100 nF 1.0 nF 47 nF 4.7 nH 10 nH 3.3 nH nRF51822-QFAB 16 MHz 32.768 kHz Capacitor, NP0, ±2% Capacitor, X7R, ±10% Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% High frequency chip inductor ±5% High frequency chip inductor ±5% High frequency chip inductor ±5% RF SoC Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 QFN40P600X600X90-48N 2.5 x 2.0 mm FC-135 Table 88 QFAB QFN48 with low voltage mode setup Page 88 nRF51822 Product Specification v3.1 11.4.3 QFAB QFN48 schematic with DC/DC converter setup Optional C13 C1 12pF C14 X2 32.768kHz 12pF C2 X1 16MHz 12pF 12pF VCC_nRF AVDD 1 L5 L4 2 15nH 10μH C12 1.0μF P0.30 3 C4.77μFPPP000...000012 4 5 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 VCC_nRF P0.07 11 12 C11 VDD DCC P0.30 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD 100nF VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 48 P0.29 47 P0.28 46 XL1 45 XL2 44 P0.25 43 P0.24 42 P0.23 41 P0.22 40 P0.21 39 38 37 C8 100nF AVDD nRF51x22 AVDD AVDD VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 36 35 34 33 32 31 30 29 28 P0.20 27 P0.19 26 P0.18 25 P0.17 C9 1.0nF C5 L1 2.2pF 4.7nH L2 10nH L3 3.3nH C4 1.0pF C10 47nF C3 2.2nF U1 nRF51x22-QFAB C6 1.5pF 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO 23 SWCLK 24 GND Figure 27 QFAB QFN48 with DC/DC converter setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 89 nRF51822 Product Specification v3.1 11.4.3.1 Bill of Materials Designator Value Description C1, C2, C13, C14 C3 C4 C5 C6 C7 C8, C11 C9 C10 C12 L1 L2 L3 L4 L5 U1 X1 X2 12 pF 2.2 nF 1.0 pF 2.2 pF 1.5 pF 4.7 μF 100 nF 1.0 nF 47 nF 1.0 μF 4.7 nH 10 nH 3.3 nH 10 μH 15 nH nRF51822-QFAB 16 MHz 32.768 kHz Capacitor, NP0, ±2% Capacitor, X7R, ±10% Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, X5R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% High frequency chip inductor ±5% High frequency chip inductor ±5% High frequency chip inductor ±5% Chip inductor, IDC,min = 50 mA, ±20% High frequency chip inductor ±10% RF SoC Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint 0402 0402 0402 0402 0402 0603 0402 0402 0402 0603 0402 0402 0402 0603 0402 QFN40P600X600X90-48N 2.5 x 2.0 mm FC-135 Table 89 QFAB QFN48 with DC/DC converter setup Page 90 nRF51822 Product Specification v3.1 11.5 QFAC QFN48 package Documentation for the QFAC QFN48 package reference circuit, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from www.nordicsemi.com. 11.5.1 QFAC QFN48 schematic with internal LDO setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF P0.29 P0.28 XL1 XL2 P0.25 P0.24 P0.23 P0.22 P0.21 VCC_nRF 1 2 C7 P0.30 3 P0.00 4 100nF P0.01 5 P0.02 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 VCC_nRF P0.07 11 12 C11 VDD DCC P0.30 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD 100nF VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 48 47 46 45 44 43 42 41 40 39 38 37 VCC_nRF nRF51x22 AVDD AVDD VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 36 35 34 33 32 31 30 29 28 P0.20 27 P0.19 26 P0.18 25 P0.17 C9 1.0nF C5 L1 3.9pF 4.7nH L2 27nH L3 3.3nH C4 1.0pF C10 47nF C3 2.2nF U1 nRF51x22-QFAC C6 1.5pF 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO 23 SWCLK 24 GND Figure 28 QFAC QFN48 with internal LDO setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 91 nRF51822 Product Specification v3.1 11.5.1.1 Bill of Materials Designator Value Description C1, C2, C13, C14 C3 C4 C5 C6 C7, C8, C11 C9 C10 L1 L2 L3 U1 X1 X2 12 pF 2.2 nF 1.0 pF 3.9 pF 1.5 pF 100 nF 1.0 nF 47 nF 4.7 nH 27 nH 3.3 nH nRF51822-QFAC 16 MHz 32.768 kHz Capacitor, NP0, ±2% Capacitor, X7R, ±10% Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% High frequency chip inductor ±5% High frequency chip inductor ±5% High frequency chip inductor ±5% RF SoC Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 QFN40P600X600X90-48N 2.5 x 2.0 mm FC-135 Table 90 QFAC QFN48 with internal LDO setup Page 92 nRF51822 Product Specification v3.1 11.5.2 QFAC QFN48 schematic with low voltage mode setup Optional C13 C1 12pF C14 X2 32.768kHz 12pF C2 X1 16MHz 12pF 12pF C8 100nF 48 P0.29 47 P0.28 46 XL1 45 XL2 44 P0.25 43 P0.24 42 P0.23 41 P0.22 40 P0.21 39 38 37 VCC_1V8 1 2 C7 P0.30 3 P0.00 4 100nF P0.01 5 P0.02 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 VCC_1V8 P0.07 11 12 C11 100nF VDD DCC P0.30 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 VCC_1V8 nRF51x22 AVDD AVDD VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 36 35 34 33 32 31 30 29 28 P0.20 27 P0.19 26 P0.18 25 P0.17 U1 nRF51x22-QFAC C9 1.0nF VCC_1V8 C10 47nF C5 L1 3.9pF 4.7nH L2 27nH C3 2.2nF L3 3.3nH C4 1.0pF C6 1.5pF 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO 23 SWCLK 24 GND Figure 29 QFAC QFN48 with low voltage mode setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 93 nRF51822 Product Specification v3.1 11.5.2.1 Bill of Materials Designator Value Description C1, C2, C13, C14 C3 C4 C5 C6 C7, C8, C11 C9 C10 L1 L2 L3 U1 X1 X2 12 pF 2.2 nF 1.0 pF 3.9 pF 1.5 pF 100 nF 1.0 nF 47 nF 4.7 nH 27 nH 3.3 nH nRF51822-QFAC 16 MHz 32.768 kHz Capacitor, NP0, ±2% Capacitor, X7R, ±10% Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, NP0, ±0.1 pF Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% High frequency chip inductor ±5% High frequency chip inductor ±5% High frequency chip inductor ±5% RF SoC Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 QFN40P600X600X90-48N 2.5 x 2.0 mm FC-135 Table 91 QFAC QFN48 with low voltage mode setup Page 94 nRF51822 Product Specification v3.1 11.5.3 QFAC QFN48 schematic with DC/DC converter setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz VCC_nRF AVDD 1 L5 L4 2 15nH 10μH C12 1.0μF P0.30 3 C4.77μFPPP000...000012 4 5 6 P0.03 7 P0.04 8 P0.05 9 P0.06 10 VCC_nRF P0.07 11 12 C11 100nF VDD DCC P0.30 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 48 P0.29 47 P0.28 46 XL1 45 XL2 44 P0.25 43 P0.24 42 P0.23 41 P0.22 40 P0.21 39 38 37 C8 100nF AVDD nRF51x22 AVDD AVDD VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 36 35 34 33 32 31 30 29 28 27 26 25 P0.20 P0.19 P0.18 P0.17 C9 1.0nF C5 L1 3.9pF 4.7nH L2 27nH L3 3.3nH C4 1.0pF C10 47nF C3 2.2nF U1 nRF51x22-QFAC C6 1.5pF 13 P0.08 14 P0.09 15 P0.10 16 P0.11 17 P0.12 18 P0.13 19 P0.14 20 P0.15 21 P0.16 22 SWDIO 23 SWCLK 24 GND Figure 30 QFAC QFN48 with DC/DC converter setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 95 nRF51822 Product Specification v3.1 11.5.3.1 Bill of Materials Designator Value Description C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% C3 2.2 nF Capacitor, X7R, ±10% C4 1.0 pF Capacitor, NP0, ±0.1 pF C5 3.9 pF Capacitor, NP0, ±0.1 pF C6 1.5 pF Capacitor, NP0, ±0.1 pF C7 4.7 μF Capacitor, X5R, ±10% C8, C11 100 nF Capacitor, X7R, ±10% C9 1.0 nF Capacitor, X7R, ±10% C10 47 nF Capacitor, X7R, ±10% C12 1.0 μF Capacitor, X7R, ±10% L1 4.7 nH High frequency chip inductor ±5% L2 27 nH High frequency chip inductor ±5% L3 3.3 nH High frequency chip inductor ±5% L4 10 μH Chip inductor, IDC,min = 50 mA, ±20% L5 15 nH High frequency chip inductor ±10% U1 nRF51822-QFAC RF SoC X1 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm X2 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint 0402 0402 0402 0402 0402 0603 0402 0402 0402 0603 0402 0402 0402 0603 0402 QFN40P600X600X90-48N 2.5 x 2.0 mm FC-135 Table 92 QFAC QFN48 with DC/DC converter setup Page 96 nRF51822 Product Specification v3.1 11.6 CDAB WLCSP package Documentation for the CDAB WLCSP package reference circuit, including Altium Designer files, PCB layout files, and PCB production files, can be downloaded from www.nordicsemi.com. 11.6.1 CDAB WLCSP schematic with internal LDO setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF C7 P0.29 B7 P0.28 A8 XL1 A7 XL2 C5 P0.25 A6 P0.24 B6 P0.23 B5 P0.22 A5 P0.21 A4 A3 A2 VCC_nRF VCC_nRF C7 100nF VCC_nRF P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 C11 100nF B8 B9 C8 D8 C9 E7 D9 E9 E8 G9 F8 G7 G8 VDD DCC P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD B1 B4 H8 H7 G6 H6 VSS VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK VSS P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 C9 1.0nF H5 G5 nRF51x22 G4 H4 H3 AVDD VSS VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 A1 F6 F9 D7 C1 D1 E1 F1 G1 F2 F3 G3 P0.20 P0.19 P0.18 P0.17 F4 U1 nRF51x22-CDAB C10 47nF B1 B3 A3 A2 ANT2 SE ANT1 VDD_PA GND BAL-NRF02D3 A1 RF B1 C3 2.2nF SWDCLK G2 SWDIO H2 P0.16 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.09 P0.08 Figure 31 CDAB WLCSP with internal LDO setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 97 nRF51822 Product Specification v3.1 11.6.1.1 Bill of Materials Designator Value Description B1 C1, C2, C13, C14 C3 C7, C8, C11 C9 C10 U1 X1 X2 BAL-NRF02D3 ST Microelecronics, 50 Ω balun transformer for 2.45 GHz ISM 12 pF Capacitor, NP0, ±2% 2.2 nF Capacitor, X7R, ±10% 100 nF Capacitor, X7R, ±10% 1.0 nF Capacitor, X7R, ±10% 47 nF Capacitor, X7R, ±10% nRF51822-CDAB RF SoC 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint BAL-ST-WLCSP 0402 0402 0402 0402 0402 BGA62C40P9X9_383X350X55 2.5 x 2.0 mm FC-135 Table 93 CDAB WLCSP with internal LDO setup Page 98 nRF51822 Product Specification v3.1 11.6.2 CDAB WLCSP schematic with low voltage mode setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF C7 P0.29 B7 P0.28 A8 XL1 A7 XL2 C5 P0.25 A6 P0.24 B6 P0.23 B5 P0.22 A5 P0.21 A4 A3 A2 VCC_1V8 C7 100nF VCC_1V8 P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 C11 100nF B8 B9 C8 D8 C9 E7 D9 E9 E8 G9 F8 G7 G8 VDD DCC P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD B1 B4 H8 H7 G6 H6 VSS VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK VSS P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 VCC_1V8 C9 1.0nF H5 G5 nRF51x22 G4 H4 H3 AVDD VSS VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 A1 F6 F9 D7 C1 D1 E1 F1 G1 F2 F3 G3 P0.20 P0.19 P0.18 P0.17 VCC_1V8 C10 47nF B1 B3 A3 A2 ANT2 SE ANT1 VDD_PA GND BAL-NRF02D3 C3 2.2nF A1 RF B1 F4 U1 nRF51x22-CDAB SWDCLK G2 SWDIO H2 P0.16 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.09 P0.08 Figure 32 CDAB WLCSP with low voltage mode setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 99 nRF51822 Product Specification v3.1 11.6.2.1 Bill of Materials Designator Value Description B1 C1, C2, C13, C14 C3 C7, C8, C11 C9 C10 U1 X1 X2 BAL-NRF02D3 ST Microelectronics, 50 Ω balun transformer for 2.45 GHz ISM 12 pF Capacitor, NP0, ±2% 2.2 nF Capacitor, X7R, ±10% 100 nF Capacitor, X7R, ±10% 1.0 nF Capacitor, X7R, ±10% 47 nF Capacitor, X7R, ±10% nRF51822-CDAB RF SoC 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint BAL-ST-WLCSP 0402 0402 0402 0402 0402 BGA62C40P9X9_383X350X55 2.5 x 2.0 mm FC-135 Table 94 CDAB WLCSP with low voltage mode setup Page 100 nRF51822 Product Specification v3.1 11.6.3 CDAB WLCSP schematic with DC/DC converter setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF C7 P0.29 B7 P0.28 A8 XL1 A7 XL2 C5 P0.25 A6 P0.24 B6 P0.23 B5 P0.22 A5 P0.21 A4 A3 A2 AVDD L5 VCC_nRF L4 15nH 10μH C12 1.0μF C7 4.7μF VCC_nRF P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 C11 100nF B8 B9 C8 D8 C9 E7 D9 E9 E8 G9 F8 G7 G8 VDD DCC P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD B1 B4 H8 H7 G6 H6 VSS VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK VSS P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 AVDD C9 1.0nF H5 G5 nRF51x22 G4 H4 H3 AVDD VSS VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 A1 F6 F9 D7 C1 D1 E1 F1 G1 F2 F3 G3 P0.20 P0.19 P0.18 P0.17 F4 U1 nRF51x22-CDAB C10 47nF B1 B3 A3 A2 ANT2 SE ANT1 VDD_PA GND BAL-NRF02D3 A1 RF B1 C3 2.2nF SWDCLK G2 SWDIO H2 P0.16 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.09 P0.08 Figure 33 CDAB WLCSP with DC/DC converter setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 101 nRF51822 Product Specification v3.1 11.6.3.1 Bill of Materials Designator Value Description B1 C1, C2, C13, C14 C3 C7 C8, C11 C9 C10 C12 L4 L5 U1 X1 X2 BAL-NRF02D3 ST Microelectronics, 50 Ω balun transformer for 2.45 GHz ISM 12 pF Capacitor, NP0, ±2% 2.2 nF Capacitor, X7R, ±10% 4.7 μF Capacitor, X5R, ±10% 100 nF Capacitor, X7R, ±10% 1.0 nF Capacitor, X7R, ±10% 47 nF Capacitor, X7R, ±10% 1.0 μF Capacitor, X7R, ±10% 10 μH Chip inductor, IDC,min = 50 mA, ±20% 15 nH High frequency chip inductor ±10% nRF51822-CDAB RF SoC 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint BAL-ST-WLCSP 0402 0402 0603 0402 0402 0402 0603 0603 0402 BGA62C40P9X9_383X350X55 2.5 x 2.0 mm FC-135 Table 95 CDAB WLCSP with DC/DC converter setup Page 102 nRF51822 Product Specification v3.1 11.7 CEAA WLCSP package Documentation for the CEAA WLCSP package reference circuit, including Altium Designer files, PCB layout files, and PCB production files, can be downloaded from www.nordicsemi.com. 11.7.1 CEAA WLCSP schematic with internal LDO setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF C7 P0.29 B7 P0.28 A8 XL1 A7 XL2 C5 P0.25 A6 P0.24 B6 P0.23 B5 P0.22 A5 P0.21 A4 A3 A2 VCC_nRF VCC_nRF C7 100nF VCC_nRF P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 C11 100nF B8 B9 D8 E8 C9 E9 D9 F9 F8 H9 G8 H7 H8 VDD DCC P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD B1 B4 J8 J7 H6 J6 VSS VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK VSS VSS P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 C9 1.0nF J5 H5 nRF51x22 H4 J4 J3 AVDD VSS VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 A1 G6 G9 D7 C1 D1 E1 F1 G1 F2 H1 G2 P0.20 P0.19 P0.18 P0.17 H3 C8 U1 nRF51x22-CEAA C10 47nF B1 B3 A3 A2 ANT2 SE ANT1 VDD_PA GND BAL-NRF02D3 A1 RF B1 C3 2.2nF SWDCLK H2 SWDIO J2 P0.16 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.09 P0.08 Figure 34 CEAA WLCSP with internal LDO setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 103 nRF51822 Product Specification v3.1 11.7.1.1 Bill of Materials Designator Value Description B1 C1, C2, C13, C14 C3 C7, C8, C11 C9 C10 U1 X1 X2 BAL-NRF02D3 ST Microelecronics, 50 Ω balun transformer for 2.45 GHz ISM 12 pF Capacitor, NP0, ±2% 2.2 nF Capacitor, X7R, ±10% 100 nF Capacitor, X7R, ±10% 1.0 nF Capacitor, X7R, ±10% 47 nF Capacitor, X7R, ±10% nRF51822-CEAA RF SoC 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint BAL-ST-WLCSP 0402 0402 0402 0402 0402 BGA62C40P9X9_383X350X55 2.5 x 2.0 mm FC-135 Table 96 CEAA WLCSP with internal LDO setup Page 104 nRF51822 Product Specification v3.1 11.7.2 CEAA WLCSP schematic with low voltage mode setup Optional C13 12pF C14 X2 32.768kHz 12pF C1 12pF C2 12pF X1 16MHz C8 100nF VCC_1V8 C7 P0.29 B7 P0.28 A8 XL1 A7 XL2 C5 P0.25 A6 P0.24 B6 P0.23 B5 P0.22 A5 P0.21 A4 A3 A2 VCC_1V8 C7 100nF VCC_1V8 P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 C11 100nF B8 B9 D8 E8 C9 E9 D9 F9 F8 H9 G8 H7 H8 VDD DCC P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD B1 B4 J8 J7 H6 J6 VSS VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK VSS VSS P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 C9 1.0nF J5 H5 nRF51x22 H4 J4 J3 AVDD VSS VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 A1 G6 G9 D7 C1 D1 E1 F1 G1 F2 H1 G2 P0.20 P0.19 P0.18 P0.17 VCC_1V8 C10 47nF B1 B3 A3 A2 ANT2 SE ANT1 VDD_PA GND BAL-NRF02D3 C3 2.2nF A1 RF B1 H3 C8 U1 nRF51x22-CEAA SWDCLK H2 SWDIO J2 P0.16 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.09 P0.08 Figure 35 CEAA WLCSP with low voltage mode setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 105 nRF51822 Product Specification v3.1 11.7.2.1 Bill of Materials Designator Value Description B1 C1, C2, C13, C14 C3 C7, C8, C11 C9 C10 U1 X1 X2 BAL-NRF02D3 ST Microelectronics, 50 Ω balun transformer for 2.45 GHz ISM 12 pF Capacitor, NP0, ±2% 2.2 nF Capacitor, X7R, ±10% 100 nF Capacitor, X7R, ±10% 1.0 nF Capacitor, X7R, ±10% 47 nF Capacitor, X7R, ±10% nRF51822-CEAA RF SoC 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint BAL-ST-WLCSP 0402 0402 0402 0402 0402 BGA62C40P9X9_383X350X55 2.5 x 2.0 mm FC-135 Table 97 CEAA WLCSP with low voltage mode setup Page 106 nRF51822 Product Specification v3.1 11.7.3 CEAA WLCSP schematic with DC/DC converter setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF AVDD C7 P0.29 B7 P0.28 A8 XL1 A7 XL2 C5 P0.25 A6 P0.24 B6 P0.23 B5 P0.22 A5 P0.21 A4 A3 A2 AVDD L5 VCC_nRF L4 15nH 10μH C12 1.0μF C7 4.7μF VCC_nRF P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 C11 100nF B8 B9 D8 E8 C9 E9 D9 F9 F8 H9 G8 H7 H8 VDD DCC P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD B1 B4 J8 J7 H6 J6 VSS VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK VSS VSS P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 C9 1.0nF J5 H5 nRF51x22 H4 J4 J3 AVDD VSS VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 A1 G6 G9 D7 C1 D1 E1 F1 G1 F2 H1 G2 P0.20 P0.19 P0.18 P0.17 H3 C8 U1 nRF51x22-CEAA C10 47nF B1 B3 A3 A2 ANT2 SE ANT1 VDD_PA GND BAL-NRF02D3 A1 RF B1 C3 2.2nF SWDCLK H2 SWDIO J2 P0.16 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.09 P0.08 Figure 36 CEAA WLCSP with DC/DC converter setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 107 nRF51822 Product Specification v3.1 11.7.3.1 Bill of Materials Designator Value Description B1 C1, C2, C13, C14 C3 C7 C8, C11 C9 C10 C12 L4 L5 U1 X1 X2 BAL-NRF02D3 12 pF 2.2 nF 4.7 μF 100 nF 1.0 nF 47 nF 1.0 μF 10 μH 15 nH nRF51822-CEAA 16 MHz 32.768 kHz ST Microelectronics, 50 Ω balun transformer for 2.45 GHz ISM Capacitor, NP0, ±2% Capacitor, X7R, ±10% Capacitor, X5R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Chip inductor, IDC,min = 50 mA, ±20% High frequency chip inductor ±10% RF SoC Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint BAL-ST-WLCSP 0402 0402 0603 0402 0402 0402 0603 0603 0402 BGA62C40P9X9_383X350X55 2.5 x 2.0 mm FC-135 Table 98 CEAA WLCSP with DC/DC converter setup Page 108 nRF51822 Product Specification v3.1 11.8 CFAC WLCSP package Documentation for the CFAC WLCSP package reference circuit, including Altium Designer files, PCB layout files, and PCB production files, can be downloaded from www.nordicsemi.com. 11.8.1 CFAC WLCSP schematic with internal LDO setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz VCC_nRF C7 100nF VCC_nRF P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 C11 100nF B8 B9 D8 E8 C9 E9 D9 F9 F8 H9 G8 H7 H8 VDD DCC P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD B1 B4 J8 J7 H6 J6 VSS VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK VSS VSS P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 C7 P0.29 B7 P0.28 A8 XL1 A7 XL2 C5 P0.25 A6 P0.24 B6 P0.23 B5 P0.22 A5 P0.21 A4 A3 A2 C8 100nF VCC_nRF C9 1.0nF J5 H5 nRF51x22 H4 J4 J3 AVDD VSS VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 A1 G6 G9 D7 C1 D1 E1 F1 G1 F2 H1 G2 P0.20 P0.19 P0.18 P0.17 H3 C8 U1 nRF51x22-CFAC C10 47nF B1 B3 A3 A2 ANT2 SE ANT1 VDD_PA GND BAL-NRF02D3 A1 RF B1 C3 2.2nF SWDCLK H2 SWDIO J2 P0.16 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.09 P0.08 Figure 37 CFAC WLCSP with internal LDO setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 109 nRF51822 Product Specification v3.1 11.8.1.1 Bill of Materials Designator Value Description B1 C1, C2, C13, C14 C3 C7, C8, C11 C9 C10 U1 X1 X2 BAL-NRF02D3 12 pF 2.2 nF 100 nF 1.0 nF 47 nF nRF51822-CFAC 16 MHz 32.768 kHz ST Microelecronics, 50 Ω balun transformer for 2.45 GHz ISM Capacitor, NP0, ±2% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% RF SoC Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint BAL-ST-WLCSP 0402 0402 0402 0402 0402 BGA62C40P9X9_383X350X55 2.5 x 2.0 mm FC-135 Table 99 CFAC WLCSP with internal LDO setup Page 110 nRF51822 Product Specification v3.1 11.8.2 CFAC WLCSP schematic with low voltage mode setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF VCC_1V8 C7 P0.29 B7 P0.28 A8 XL1 A7 XL2 C5 P0.25 A6 P0.24 B6 P0.23 B5 P0.22 A5 P0.21 A4 A3 A2 VCC_1V8 C7 100nF VCC_1V8 P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 C11 100nF B8 B9 D8 E8 C9 E9 D9 F9 F8 H9 G8 H7 H8 VDD DCC P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD B1 B4 J8 J7 H6 J6 VSS VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK VSS VSS P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 C9 1.0nF J5 H5 nRF51x22 H4 J4 J3 AVDD VSS VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 A1 G6 G9 D7 C1 D1 E1 F1 G1 F2 H1 G2 P0.20 P0.19 P0.18 P0.17 VCC_1V8 C10 47nF B1 B3 A3 A2 ANT2 SE ANT1 VDD_PA GND BAL-NRF02D3 C3 2.2nF H3 C8 U1 nRF51x22-CFAC A1 RF B1 SWDCLK H2 SWDIO J2 P0.16 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.09 P0.08 Figure 38 CFAC WLCSP with low voltage mode setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 111 nRF51822 Product Specification v3.1 11.8.2.1 Bill of Materials Designator Value Description B1 C1, C2, C13, C14 C3 C7, C8, C11 C9 C10 U1 X1 X2 BAL-NRF02D3 ST Microelectronics, 50 Ω balun transformer for 2.45 GHz ISM 12 pF Capacitor, NP0, ±2% 2.2 nF Capacitor, X7R, ±10% 100 nF Capacitor, X7R, ±10% 1.0 nF Capacitor, X7R, ±10% 47 nF Capacitor, X7R, ±10% nRF51822-CEAA RF SoC 16 MHz Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm 32.768 kHz Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint BAL-ST-WLCSP 0402 0402 0402 0402 0402 BGA62C40P9X9_383X350X55 2.5 x 2.0 mm FC-135 Table 100 CFAC WLCSP with low voltage mode setup Page 112 nRF51822 Product Specification v3.1 11.8.3 CFAC WLCSP schematic with DC/DC converter setup Optional C13 12pF C14 12pF X2 32.768kHz C1 12pF C2 12pF X1 16MHz C8 100nF C7 P0.29 B7 P0.28 A8 XL1 A7 XL2 C5 P0.25 A6 P0.24 B6 P0.23 B5 P0.22 A5 P0.21 A4 A3 A2 AVDD AVDD L5 VCC_nRF L4 15nH 10μH C12 1.0μF C7 4.7μF VCC_nRF P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 C11 100nF B8 B9 D8 E8 C9 E9 D9 F9 F8 H9 G8 H7 H8 VDD DCC P0.30 P0.31 P0.00 P0.01 P0.02 P0.03 P0.04 P0.05 P0.06 P0.07 VDD B1 B4 J8 J7 H6 J6 VSS VSS P0.08 P0.09 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 SWDIO/nRESET SWDCLK VSS VSS P0.29 P0.28 P0.27 P0.26 P0.25 P0.24 P0.23 P0.22 P0.21 DEC1 XC2 XC1 C9 1.0nF J5 H5 nRF51x22 H4 J4 J3 AVDD VSS VSS VSS ANT2 ANT1 VDD_PA DEC2 P0.20 P0.19 P0.18 P0.17 A1 G6 G9 D7 C1 D1 E1 F1 G1 F2 H1 G2 P0.20 P0.19 P0.18 P0.17 H3 C8 U1 nRF51x22-CFAC C10 47nF B1 B3 A3 A2 ANT2 SE ANT1 VDD_PA GND BAL-NRF02D3 A1 RF B1 C3 2.2nF SWDCLK H2 SWDIO J2 P0.16 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.09 P0.08 Figure 39 CFAC WLCSP with DC/DC converter setup Note: For PCB reference layouts, see the Reference Layout section on the Downloads tab for the different chip variants on www.nordicsemi.com. Page 113 nRF51822 Product Specification v3.1 11.8.3.1 Bill of Materials Designator Value Description B1 C1, C2, C13, C14 C3 C7 C8, C11 C9 C10 C12 L4 L5 U1 X1 X2 BAL-NRF02D3 12 pF 2.2 nF 4.7 μF 100 nF 1.0 nF 47 nF 1.0 μF 10 μH 15 nH nRF51822-CFAC 16 MHz 32.768 kHz ST Microelectronics, 50 Ω balun transformer for 2.45 GHz ISM Capacitor, NP0, ±2% Capacitor, X7R, ±10% Capacitor, X5R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Capacitor, X7R, ±10% Chip inductor, IDC,min = 50 mA, ±20% High frequency chip inductor ±10% RF SoC Crystal SMD 2520, 16 MHz, 8 pF, ±40 ppm Crystal SMD FC-135, 32.768 kHz, 9 pF, ±20 ppm Footprint BAL-ST-WLCSP 0402 0402 0603 0402 0402 0402 0603 0603 0402 BGA62C40P9X9_383X350X55 2.5 x 2.0 mm FC-135 Table 101 CFAC WLCSP with DC/DC converter setup Page 114 nRF51822 Product Specification v3.1 12 Glossary Term EOC GFSK GPIO ISM MOQ NOC NVMC QDEC RF RoHS RSSI SPI TWI UART WLCSP Description Extreme Operating Conditions Gaussian Frequency-Shift Keying General Purpose Input Output Industrial Scientific Medical Minimum Order Quantity Nominal Operating Conditions Non-Volatile Memory Controller Quadrature Decoder Radio Frequency Restriction of Hazardous Substances Radio Signal Strength Indicator Serial Peripheral Interface Two-Wire Interface Universal Asynchronous Receiver Transmitter Wafer Level Chip Scale Packet Table 102 Glossary Page 115

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