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stm32f107 datasheet

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    RM0008 Reference manual STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced ARM-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as STM32F10xxx throughout the document, unless otherwise specified. The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the lowand medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx connectivity line datasheet. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical Reference Manual. Related documents Available from www.arm.com: ■ Cortex™-M3 Technical Reference Manual, available from: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf Available from www.st.com: ■ STM32F101xx STM32F103xx datasheets ■ STM32F10xxx Flash programming manual June 2009 Doc ID 13902 Rev 9 1/995 www.st.com Contents Contents RM0008 1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.1 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3.2 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3 CRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1 CRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.4 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . 54 4.1.2 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.1 Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 55 4.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2/995 Doc ID 13902 Rev 9 RM0008 Contents 4.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3.6 Auto-wakeup (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . . 62 4.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 64 4.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5 Backup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.1 BKP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2 BKP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3 BKP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.1 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.2 RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4 BKP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) . . . . . . . . . . . . . . . . . . . 68 5.4.2 RTC clock calibration register (BKP_RTCCR) . . . . . . . . . . . . . . . . . . . . 68 5.4.3 Backup control register (BKP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.4.4 Backup control/status register (BKP_CSR) . . . . . . . . . . . . . . . . . . . . . . 69 5.4.5 BKP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6 Low-, medium- and high-density reset and clock control (RCC) . . . . 74 6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Doc ID 13902 Rev 9 3/995 Contents RM0008 6.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 84 6.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . . 89 6.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . . 91 6.3.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . . 93 6.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . . 95 6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . . 97 6.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . 99 6.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.11 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7 Connectivity line devices: reset and clock control (RCC) . . . . . . . . . 104 7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.2.3 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 115 7.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4/995 Doc ID 13902 Rev 9 RM0008 Contents 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 121 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 122 AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . 125 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 126 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 128 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 130 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 AHB peripheral clock reset register (RCC_AHBRSTR) . . . . . . . . . . . . 133 Clock configuration register2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 134 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8 General-purpose and alternate-function I/Os (GPIOs and AFIOs) . . 138 8.1 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8.1.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 8.1.2 Atomic bit set or reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 8.1.3 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . 141 8.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.1.10 Analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.1.11 Peripherals’ GPIO configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8.2 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . . . . . . . . 148 8.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . . . . . . . 149 8.2.3 Port input data register (GPIOx_IDR) (x=A..G) . . . . . . . . . . . . . . . . . . 149 8.2.4 Port output data register (GPIOx_ODR) (x=A..G) . . . . . . . . . . . . . . . . 150 8.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . . . . . . . . . . . . 150 8.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) . . . . . . . . . . . . . . . . . . . 151 8.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . . . . . . . 151 8.3 Alternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . 152 8.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . 152 8.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . . . . . . . 152 8.3.3 CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 8.3.4 CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Doc ID 13902 Rev 9 5/995 Contents RM0008 8.3.5 JTAG/SWD alternate function remapping . . . . . . . . . . . . . . . . . . . . . . 153 8.3.6 ADC alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 8.3.7 Timer alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8.3.8 USART Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . 156 8.3.9 I2C1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 8.3.10 SPI1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 8.3.11 SPI3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 8.3.12 Ethernet alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . 158 8.4 AFIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8.4.1 Event control register (AFIO_EVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) . . . . . . 159 8.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) . . . . . . . . 165 8.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) . . . . . . . . 165 8.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) . . . . . . . . 166 8.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) . . . . . . . . 166 8.5 GPIO and AFIO register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 169 9.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 9.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 9.2 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 174 9.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 9.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 176 9.3 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 9.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 9.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 9.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 179 9.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 179 9.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . . 180 9.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 9.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 10 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6/995 Doc ID 13902 Rev 9 RM0008 Contents 10.1 10.2 10.3 10.4 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 10.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 10.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 10.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 10.3.4 Programmable data width, data alignment and endians . . . . . . . . . . . 186 10.3.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10.3.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 10.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 191 10.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 192 10.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1 ..7) . . . . . . 193 10.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1 ..7) . 194 10.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7) 195 10.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1 ..7) . 195 10.4.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 11.1 ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 11.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.3.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 11.3.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 11.3.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 11.3.4 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 11.3.5 Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 11.3.6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 11.3.7 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 11.3.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.3.9 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.3.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.5 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.6 Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 207 Doc ID 13902 Rev 9 7/995 Contents RM0008 11.7 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 11.8 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 11.9 Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11.9.1 Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 11.9.2 Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 11.9.3 Fast interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 11.9.4 Slow interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 11.9.5 Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 11.9.6 Independent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 11.9.7 Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 215 11.9.8 Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 215 11.9.9 Combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . . 216 11.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 11.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 11.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 11.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 11.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 11.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 11.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 225 11.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 226 11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . 226 11.12.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 227 11.12.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 227 11.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 227 11.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 228 11.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 229 11.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 229 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 230 11.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 230 11.12.15 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 12 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12.1 DAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12.3 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.3.1 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 8/995 Doc ID 13902 Rev 9 RM0008 Contents 12.4 12.5 12.3.2 DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.3.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.3.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 12.3.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 12.3.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 12.3.7 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 12.3.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 12.3.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 12.4.1 Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 240 12.4.2 Independent trigger with same LFSR generation . . . . . . . . . . . . . . . . 241 12.4.3 Independent trigger with different LFSR generation . . . . . . . . . . . . . . 241 12.4.4 Independent trigger with same triangle generation . . . . . . . . . . . . . . . 241 12.4.5 Independent trigger with different triangle generation . . . . . . . . . . . . . 242 12.4.6 Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 12.4.7 Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 242 12.4.8 Simultaneous trigger with same LFSR generation . . . . . . . . . . . . . . . 243 12.4.9 Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 243 12.4.10 Simultaneous trigger with same triangle generation . . . . . . . . . . . . . . 243 12.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 244 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 12.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 12.5.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 247 12.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 12.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 12.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 12.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 12.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 12.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 12.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Doc ID 13902 Rev 9 9/995 Contents RM0008 12.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 12.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 251 12.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 251 12.5.14 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 13 Advanced-control timers (TIM1&TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 253 13.1 TIM1&TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.2 TIM1&TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.3 TIM1&TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 13.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 13.3.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.3.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 13.3.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 13.3.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 13.3.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 13.3.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 13.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 278 13.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 13.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 282 13.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 13.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 13.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 13.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 13.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 13.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 290 13.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 13.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 13.4 TIM1&TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 13.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 294 13.4.2 TIM1&TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 295 13.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 297 13.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . 299 13.4.5 TIM1&TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 301 10/995 Doc ID 13902 Rev 9 RM0008 Contents 13.4.6 TIM1&TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 302 13.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . 304 13.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . 307 13.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . 308 13.4.10 TIM1&TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 13.4.11 TIM1&TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 13.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 311 13.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . 312 13.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . 312 13.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . 313 13.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . 313 13.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . 314 13.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . 314 13.4.19 TIM1&TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . 316 13.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . 317 13.4.21 TIM1&TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 14 General-purpose timer (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 14.1 TIMx introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 14.2 TIMx main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 14.3 TIMx functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 14.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 14.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 14.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 14.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 14.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 14.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 14.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 14.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 14.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.3.10 One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 14.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 343 14.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 14.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 14.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 346 14.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 14.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Doc ID 13902 Rev 9 11/995 Contents RM0008 14.4 TIMx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 14.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 355 14.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 356 14.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 357 14.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 360 14.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 14.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 362 14.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 363 14.4.8 Capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . . . . . 367 14.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 368 14.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 14.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 14.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 370 14.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 370 14.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 371 14.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 371 14.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 372 14.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 372 14.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 373 14.4.19 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 15 Basic timers (TIM6&TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 15.1 TIM6&TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 15.2 TIM6&TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 15.3 TIM6&TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 15.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 15.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 15.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 15.4 TIM6&TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 15.4.1 TIM6&TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 381 15.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 383 15.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . 383 15.4.4 TIM6&TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 384 15.4.5 TIM6&TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 384 15.4.6 TIM6&TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 15.4.7 TIM6&TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 12/995 Doc ID 13902 Rev 9 RM0008 Contents 15.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 385 15.4.9 TIM6&TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 16 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 16.1 RTC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 16.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 16.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 16.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 16.3.2 Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 16.3.3 Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 16.3.4 Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 16.3.5 RTC flag assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 16.4 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 16.4.1 RTC control register high (RTC_CRH) . . . . . . . . . . . . . . . . . . . . . . . . 392 16.4.2 RTC control register low (RTC_CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 393 16.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) . . . . . . . . . . . 394 16.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . . . . . . . 395 16.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) . . . . . . . . . . . . . . . . 396 16.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . . . . . . . . . . . 397 16.4.7 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 17 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 17.1 IWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 17.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 17.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 17.3.1 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 17.3.2 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 17.3.3 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 17.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 17.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 17.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 17.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 17.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 17.4.5 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 18 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Doc ID 13902 Rev 9 13/995 Contents RM0008 18.1 18.2 18.3 18.4 18.5 18.6 WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 406 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 18.6.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 18.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 407 18.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 18.6.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 19 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 409 19.1 FSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 19.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 19.3 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 19.3.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 410 19.4 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 19.4.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 19.4.2 NAND/PC Card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 19.5 NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 19.5.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 19.5.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 416 19.5.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 19.5.4 NOR Flash/PSRAM controller timing diagrams . . . . . . . . . . . . . . . . . . 417 19.5.5 Synchronous burst transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 19.5.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 19.6 NAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 19.6.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 19.6.2 NAND Flash / PC Card supported memories and transactions . . . . . . 444 19.6.3 Timing diagrams for NAND, ATA and PC Card . . . . . . . . . . . . . . . . . . 444 19.6.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 19.6.5 NAND Flash pre-wait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 19.6.6 Error correction code computation ECC (NAND Flash) . . . . . . . . . . . . 447 19.6.7 NAND Flash/PC Card controller registers . . . . . . . . . . . . . . . . . . . . . . 448 19.6.8 FSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 14/995 Doc ID 13902 Rev 9 RM0008 Contents 20 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . 456 20.1 SDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 20.2 SDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 20.3 SDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 20.3.1 SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 20.3.2 SDIO AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 20.4 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 20.4.1 Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 20.4.2 Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 20.4.3 Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 20.4.4 Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 20.4.5 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 20.4.6 Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 20.4.7 Stream access, stream write and stream read (MultiMediaCard only) 474 20.4.8 Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . 475 20.4.9 Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 20.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 20.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 20.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 20.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 20.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 20.5 Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 20.5.1 R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.5.2 R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.5.3 R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.5.4 R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.5.5 R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 20.5.6 R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 20.5.7 R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 20.5.8 R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 20.6 SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 20.6.1 SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . . 494 20.6.2 SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . . 494 20.6.3 SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 20.6.4 SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 20.7 CE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 Doc ID 13902 Rev 9 15/995 Contents RM0008 20.8 20.9 20.7.1 Command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 495 20.7.2 Command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 495 20.7.3 CE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 20.7.4 Aborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 SDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 20.9.1 SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . . 497 20.9.2 SDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . . . 497 20.9.3 SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . . 498 20.9.4 SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . . 499 20.9.5 SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . . 500 20.9.6 SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . . 500 20.9.7 SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . . 501 20.9.8 SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . . 501 20.9.9 SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . . 502 20.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 503 20.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 20.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 505 20.9.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 20.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . . 509 20.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . 510 20.9.16 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 21 Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 512 21.1 USB introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 21.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 21.3 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 21.3.1 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 21.4 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 21.4.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 21.4.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 21.4.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 21.4.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 21.4.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 21.5 USB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 21.5.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 16/995 Doc ID 13902 Rev 9 RM0008 Contents 21.5.2 21.5.3 21.5.4 Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 22 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 22.1 bxCAN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 22.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 22.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 22.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 22.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 544 22.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 22.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 22.4 bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 22.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 22.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 22.4.3 Sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 22.5 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 22.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 22.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 22.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 548 22.6 STM32F10xxx in Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 22.7 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 22.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 22.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 551 22.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 22.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 22.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 22.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 22.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 22.8 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 22.9 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 22.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 22.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 22.9.3 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 22.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 22.9.5 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 Doc ID 13902 Rev 9 17/995 Contents RM0008 23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 23.1 SPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 23.2 SPI and I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 23.2.1 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 23.2.2 I2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 23.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 23.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 23.3.2 SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 23.3.3 SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 23.3.4 Simplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 23.3.5 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 23.3.6 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 23.3.7 SPI communication using DMA (direct memory addressing) . . . . . . . 596 23.3.8 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 23.3.9 Disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 23.3.10 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 23.4 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 23.4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 23.4.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 23.4.3 23.4.4 23.4.5 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 23.4.6 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 23.4.7 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 23.4.8 I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 23.5 23.4.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 23.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 614 23.5.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 23.5.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 23.5.4 23.5.5 23.5.6 23.5.7 23.5.8 23.5.9 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 SPI Rx CRC register (SPI_RXCRCR) (not used in I2S mode) . . . . . . 619 SPI Tx CRC register (SPI_TXCRCR) (not used in I2S mode) . . . . . . . 620 SPI_I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 620 SPI_I2S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 622 18/995 Doc ID 13902 Rev 9 RM0008 Contents 23.5.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 24 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 624 24.1 I2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 24.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 24.3 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 24.3.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 24.3.2 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 24.3.3 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 24.3.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 24.3.5 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 24.3.6 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 24.3.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 24.4 24.5 24.6 24.3.8 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 I2C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 24.6.1 Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 24.6.2 Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 24.6.3 Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 644 24.6.4 Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 645 24.6.5 Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 24.6.6 Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 24.6.7 Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 24.6.8 Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 24.6.9 TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 24.6.10 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 25 Universal synchronous asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 25.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 25.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 25.3 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 25.3.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 25.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 25.3.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 Doc ID 13902 Rev 9 19/995 Contents RM0008 25.4 25.5 25.6 25.3.4 Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 25.3.5 USART receiver’s tolerance to clock deviation . . . . . . . . . . . . . . . . . . 666 25.3.6 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 25.3.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 25.3.8 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 669 25.3.9 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 25.3.10 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 674 25.3.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 25.3.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 25.3.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 679 25.3.14 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 25.6.1 Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 25.6.2 Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 25.6.3 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 25.6.4 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 25.6.5 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 25.6.6 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 25.6.7 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 691 25.6.8 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 26 USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . 694 26.1 OTG_FS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 26.2 OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 26.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 26.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 26.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 26.3 OTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 26.3.1 OTG full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 26.3.2 Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 26.4 OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 26.4.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 26.4.2 HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 26.4.3 SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 20/995 Doc ID 13902 Rev 9 RM0008 Contents 26.5 USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 26.5.1 SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 26.5.2 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 26.5.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 26.6 USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 26.6.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 26.6.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 26.6.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 26.6.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 26.7 SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 26.7.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 26.7.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 26.8 Power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 26.9 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 26.10 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 26.10.1 Peripheral Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 26.10.2 Peripheral Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 26.11 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 26.11.1 Host Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 26.11.2 Host Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 26.12 USB system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 26.13 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 26.14 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 26.14.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 26.14.2 OTG_FS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 26.14.3 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 26.14.4 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 26.14.5 OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 26.14.6 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 26.15 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 26.15.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 26.15.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 26.15.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 26.15.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 26.15.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 Doc ID 13902 Rev 9 21/995 Contents RM0008 26.15.6 Operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 26.15.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 26.15.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 27 Ethernet (ETH): media access control (MAC) with DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 27.1 Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 27.2 Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 27.2.1 MAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 27.2.2 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 27.2.3 PTP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 27.3 Ethernet pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 27.4 Ethernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . . 841 27.4.1 Station management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 27.4.2 Media-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 27.4.3 Reduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . . 847 27.4.4 MII/RMII selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 27.5 Ethernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . . 849 27.5.1 MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 27.5.2 MAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 27.5.3 MAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 27.5.4 MAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 27.5.5 MAC filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 27.5.6 MAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 27.5.7 MAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 27.5.8 Power management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 27.5.9 Precision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . . 872 27.6 Ethernet functional description: DMA controller operation . . . . . . . . . . . 878 27.6.1 Initialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 879 27.6.2 Host bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 27.6.3 Host data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880 27.6.4 Buffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880 27.6.5 DMA arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 27.6.6 Error response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 27.6.7 Tx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 27.6.8 Rx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 27.6.9 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 22/995 Doc ID 13902 Rev 9 RM0008 Contents 27.7 27.8 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 Ethernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 27.8.1 MAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 27.8.2 MMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922 27.8.3 IEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 27.8.4 DMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 27.8.5 Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946 28 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 28.1 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 28.1.1 Flash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 28.2 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 29 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 29.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 29.2 Reference ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954 29.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . 954 29.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . . 954 29.4 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 29.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 29.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 29.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . 956 29.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . . 957 29.5 STM32F10xxx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . 957 29.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 29.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 29.6.2 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 29.6.3 Cortex-M3 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 29.6.4 Cortex-M3 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 29.7 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 29.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 29.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 29.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 29.8.3 SW-DP state machine (Reset, idle states, ID code) . . . . . . . . . . . . . . 963 29.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 29.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 Doc ID 13902 Rev 9 23/995 Contents RM0008 29.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 29.9 AHB-AP (AHB access port) - valid for both JTAG-DP or SW-DP . . . . . . 965 29.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 29.11 Capability of the debugger host to connect under system reset . . . . . . 967 29.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 29.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 29.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . 968 29.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 29.14.2 Timestamp packets, synchronization and overflow packets . . . . . . . . 968 29.15 ETM (Embedded Trace Macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 29.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 29.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 29.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 29.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 29.16 MCU debug component (MCUDBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 29.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 971 29.16.2 Debug support for timers, watchdog, bxCAN and I2C . . . . . . . . . . . . . 972 29.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 29.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 29.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 29.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 29.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 29.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . . 977 29.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . . 977 29.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 29.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 29.17.8 TRACECLKIN connection inside STM32F10xxx . . . . . . . . . . . . . . . . . 978 29.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 29.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 29.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 24/995 Doc ID 13902 Rev 9 RM0008 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Flash module organization (low-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Flash module organization (medium-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Flash module organization (high-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Flash module organization (connectivity line devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 CRC calculation unit register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 BKP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Output MODE bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Advanced timers TIM1/TIM8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 General-purpose timers TIM2/3/4/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 BxCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 FSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Other IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Debug interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Debug port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 ADC1 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 154 ADC1 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 154 ADC2 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 154 ADC2 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 155 TIM5 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 TIM4 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 TIM3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 TIM2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 TIM1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 USART3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 USART2 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 USART1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 I2C1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 SPI1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 SPI3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Doc ID 13902 Rev 9 25/995 List of tables RM0008 Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. ETH remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 AFIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Vector table for connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Vector table for other STM32F10xxx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 181 Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 186 DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Summary of DMA1 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Summary of DMA2 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 External trigger for regular channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . . 208 External trigger for injected channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . 208 External trigger for regular channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 External trigger for injected channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Output control bits for complementary OCx and OCxN channels with break feature . . . . 310 TIM1&TIM8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 TIM6&TIM7 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 Watchdog timeout period (with 40 kHz input clock)Min/max IWDG timeout period at 32 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Memory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 NAND bank selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Nonmuxed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Muxed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Non muxed I/Os PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 NOR Flash/PSRAM supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 416 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 26/995 Doc ID 13902 Rev 9 RM0008 List of tables Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Programmable NAND/PC Card access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 FSMC register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 Response type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 Doc ID 13902 Rev 9 27/995 List of tables RM0008 Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. Table 194. Table 195. Table 196. Table 197. Table 198. Table 199. Table 200. Table 201. Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 Audio-frequency precision using standard 14.7456 MHz and PLL3 (connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 Error calculation for programmed baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 USART receiver ‘s tolerance when DIV_Fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 USART receiver’s tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . 667 Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 Ethernet pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 Management frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 Clock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 TX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 RX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 Frame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 Destination address filtering table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 Source address filtering table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 Receive descriptor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 Ethernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956 JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 962 28/995 Doc ID 13902 Rev 9 RM0008 List of tables Table 202. Table 203. Table 204. Table 205. Table 206. Table 207. Table 208. Table 209. Table 210. Table 211. Table 212. Table 213. Table 214. Table 215. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 Cortex-M3 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 Doc ID 13902 Rev 9 29/995 List of figures List of figures RM0008 Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 System architecture in connectivity line devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Basic structure of a standard I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 High impedance-analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ADC / DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 DMA block diagram in connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Calibration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Right alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Left alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Dual ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Injected simultaneous mode on 4 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Regular simultaneous mode on 16 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Fast interleaved mode on 1 channel in continuous conversion mode . . . . . . . . . . . . . . . 213 Slow interleaved mode on 1 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Alternate trigger: injected channel group of each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Alternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . . . . . . . . 215 Alternate + Regular simultaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Interleaved single channel with injected sequence CH11, CH12 . . . . . . . . . . . . . . . . . . . 216 Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 217 DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 237 DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 239 30/995 Doc ID 13902 Rev 9 RM0008 List of figures Figure 49. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Figure 50. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 240 Figure 51. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Figure 52. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 257 Figure 53. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 257 Figure 54. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Figure 55. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Figure 56. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Figure 57. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Figure 58. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 259 Figure 59. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 260 Figure 60. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Figure 61. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Figure 62. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Figure 63. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Figure 64. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 262 Figure 65. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 263 Figure 66. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Figure 67. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 264 Figure 68. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Figure 69. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 264 Figure 70. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 265 Figure 71. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 266 Figure 72. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 267 Figure 73. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Figure 74. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Figure 75. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Figure 76. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Figure 77. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 270 Figure 78. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Figure 79. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 271 Figure 80. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Figure 81. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Figure 82. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Figure 83. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Figure 84. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Figure 85. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Figure 86. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 278 Figure 87. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 279 Figure 88. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Figure 89. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Figure 90. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Figure 91. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Figure 92. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 287 Figure 93. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 287 Figure 94. Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Figure 95. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Figure 96. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Figure 97. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Figure 98. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Figure 99. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Figure 100. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 322 Doc ID 13902 Rev 9 31/995 List of figures RM0008 Figure 101. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 323 Figure 102. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Figure 103. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Figure 104. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Figure 105. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Figure 106. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 325 Figure 107. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 326 Figure 108. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Figure 109. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Figure 110. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Figure 111. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Figure 112. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 328 Figure 113. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 329 Figure 114. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Figure 115. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 330 Figure 116. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Figure 117. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 330 Figure 118. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 331 Figure 119. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 332 Figure 120. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Figure 121. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Figure 122. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Figure 123. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Figure 124. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 334 Figure 125. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Figure 126. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Figure 127. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Figure 128. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Figure 129. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Figure 130. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Figure 131. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Figure 132. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Figure 133. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 345 Figure 134. Example of encoder interface mode with IC1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 346 Figure 135. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Figure 136. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Figure 137. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Figure 138. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Figure 139. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Figure 140. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Figure 141. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Figure 142. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Figure 143. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 Figure 144. Triggering timer 1 and 2 with timer 1 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Figure 145. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Figure 146. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 377 Figure 147. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 377 Figure 148. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Figure 149. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Figure 150. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Figure 151. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Figure 152. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not 32/995 Doc ID 13902 Rev 9 RM0008 List of figures preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Figure 153. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Figure 154. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 381 Figure 155. RTC simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Figure 156. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . 391 Figure 157. RTC Overflow waveform example with PR=0003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 Figure 158. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 Figure 159. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 Figure 160. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 Figure 161. FSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Figure 162. Mode1 read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 Figure 163. ModeA read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Figure 164. ModeA write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Figure 165. Mode2/B read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Figure 166. Mode2 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Figure 167. ModeB write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Figure 168. ModeC read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Figure 169. ModeC write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Figure 170. ModeD read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Figure 171. Muxed read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Figure 172. Muxed write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Figure 173. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . 432 Figure 174. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 434 Figure 175. NAND/PC Card controller timing for common memory access . . . . . . . . . . . . . . . . . . . . 445 Figure 176. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Figure 177. SDIO “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Figure 178. SDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Figure 179. SDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Figure 180. SDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Figure 181. SDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Figure 182. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 Figure 183. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Figure 184. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 Figure 185. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 Figure 186. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 Figure 187. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 Figure 188. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Figure 189. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 Figure 190. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 Figure 191. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 517 Figure 192. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 Figure 193. Dual CAN block diagram (connectivity devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 Figure 194. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 Figure 195. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 Figure 196. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 Figure 197. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 Figure 198. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 Figure 199. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 Figure 200. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 Figure 201. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 Figure 202. Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 Doc ID 13902 Rev 9 33/995 List of figures RM0008 Figure 203. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Figure 204. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 Figure 205. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Figure 206. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 Figure 207. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 Figure 208. Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Figure 209. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Figure 210. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Figure 211. I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 Figure 212. I2S Phillips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . . . . . . . . . . . . . 601 Figure 213. I2S Phillips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . 601 Figure 214. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 Figure 215. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 Figure 216. I2S Phillips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 602 Figure 217. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 Figure 218. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 603 Figure 219. MSB Justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 Figure 220. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . 603 Figure 221. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 604 Figure 222. LSB Justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 Figure 223. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 Figure 224. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 Figure 225. LSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 605 Figure 226. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 Figure 227. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 Figure 228. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 606 Figure 229. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 Figure 230. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 Figure 231. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 Figure 232. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 Figure 233. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 Figure 234. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 Figure 235. Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 Figure 236. Transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 Figure 237. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 Figure 238. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 Figure 239. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 Figure 240. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 Figure 241. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 Figure 242. Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 Figure 243. Data sampling for noise detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 Figure 244. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 Figure 245. Mute mode using Address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 Figure 246. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 671 Figure 247. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 672 Figure 248. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 Figure 249. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 Figure 250. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 Figure 251. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 Figure 252. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 Figure 253. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 Figure 254. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 34/995 Doc ID 13902 Rev 9 RM0008 List of figures Figure 255. IrDA data modulation (3/16) -normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 Figure 256. Hardware flow control between 2 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 Figure 257. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 Figure 258. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 Figure 259. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 Figure 260. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 Figure 261. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 Figure 262. USB peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 Figure 263. USB host only connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 Figure 264. SOF connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 Figure 265. OTG_FS controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 Figure 266. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . 712 Figure 267. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . . 713 Figure 268. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 Figure 269. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 Figure 270. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 Figure 271. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 Figure 272. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . . 798 Figure 273. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 Figure 274. Normal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 Figure 275. Normal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 Figure 276. Receive FIFO packet read in slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 Figure 277. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 Figure 278. Slave mode bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 Figure 279. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 Figure 280. A-Device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 Figure 281. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 Figure 282. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 Figure 283. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 Figure 284. ETH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 Figure 285. SMI interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 Figure 286. MDIO timing and frame structure - Write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843 Figure 287. MDIO timing and frame structure - Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 Figure 288. Media independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 Figure 289. MII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 Figure 290. Reduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 Figure 291. RMII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 Figure 292. Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 Figure 293. Address field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 Figure 294. MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 Figure 295. Tagged MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 Figure 296. Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 Figure 297. Transmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 Figure 298. Transmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 Figure 299. Frame transmission in MMI and RMII modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 Figure 300. Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 Figure 301. Reception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 Figure 302. Reception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 Figure 303. Reception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 Figure 304. MAC core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 Figure 305. Wakeup frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 Figure 306. Networked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 Doc ID 13902 Rev 9 35/995 List of figures RM0008 Figure 307. System time update using the Fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . . 875 Figure 308. PTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 Figure 309. PPS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 Figure 310. Descriptor ring and chain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 Figure 311. TxDMA operation in Default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 Figure 312. TxDMA operation in OSF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885 Figure 313. Transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886 Figure 314. Transmit descriptor field format with IEEE1588 time stamp enabled . . . . . . . . . . . . . . . . 891 Figure 315. Receive DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896 Figure 316. Rx DMA descriptor structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 Figure 317. Receive descriptor fields format with IEEE1588 time stamp enabled. . . . . . . . . . . . . . . . 903 Figure 318. Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 Figure 319. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . . . . . . . . . 915 Figure 320. Block diagram of STM32F10xxx-level and Cortex-M3-level debug support . . . . . . . . . . . 953 Figure 321. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954 Figure 322. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 Figure 323. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 36/995 Doc ID 13902 Rev 9 RM0008 1 Documentation conventions Documentation conventions 1.1 List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value. read/clear by read Software can read this bit. Reading this bit automatically clears it to ‘0’. (rc_r) Writing ‘0’ has no effect on the bit value. read/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value. read-only write trigger (rt_w) Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on the bit value. toggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect. Reserved (Res.) Reserved bit, must be kept at reset value. 1.2 Glossary ● Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. ● Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. ● High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. ● Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. 1.3 Peripheral availability For peripheral availability and number across all STM32F10xxx sales types, please refer to the low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the connectivity line devices, STM32F105xx/STM32F107xx. Doc ID 13902 Rev 9 37/995 Memory and bus architecture 2 Memory and bus architecture RM0008 2.1 System architecture In low-, medium- and high-density devices, the main system consists of: ● Four masters: – Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) ● Four slaves: – Internal SRAM – Internal Flash memory – FSMC – AHB to APB bridges (AHB2APBx), which connect all the APB peripherals These are interconnected using a multilayer AHB bus architecture as shown in Figure 1: Figure 1. System architecture Co r t ex -M3 DMA1 Ch.1 Ch.2 Ch.7 DMA2 Ch.1 Ch.2 ICode DCode FLITF Flash DMA Bus matrix Sys tem DMA FSMC SDIO SRAM AHB system bus Reset & clock control (RCC) DMA Request Bridge 2 Bridge 1 ADC1 ADC2 ADC3 USART1 SPI1 TIM1 TIM8 GPIOA GPIOB APB2 GPIOC GPIOD GPIOE GPIOF GPIOG EXTI AFIO APB 1 DAC SPI3/I2S PWR SPI2/I2S BKP IWDG bxCAN WWDG USB RTC I2C2 TIM7 I2C1 TIM6 UART5 TIM5 UART4 TIM4 USART3 TIM3 USART2 TIM2 Ch.5 DMA request ai14800c 38/995 Doc ID 13902 Rev 9 RM0008 Memory and bus architecture In connectivity line devices the main system consists of: ● Five masters: – Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) – Ethernet DMA ● Three slaves: – Internal SRAM – Internal Flash memory – AHB to APB bridges (AHB2APBx), which connect all the APB peripherals These are interconnected using a multilayer AHB bus architecture as shown in Figure 2: Figure 2. System architecture in connectivity line devices Co r t ex -M3 DMA1 ICode DCode FLITF Sys tem DMA Reset & clock control (RCC) Flash SRAM DMA Bus matrix Ch.1 Ch.2 Ch.7 DMA2 Ch.1 Ch.2 Ch.5 DMA AHB system bus Bridge 2 Bridge 1 APB2 APB 1 DMA request ADC1 ADC2 USART1 SPI1 TIM1 GPIOA GPIOB GPIOC GPIOD GPIOE EXTI AFIO DAC SPI3/I2S PWR SPI2/I2S BKP IWDG CAN1 WWDG CAN2 RTC I2C2 TIM7 I2C1 TIM6 UART5 TIM5 UART4 TIM4 USART3 TIM3 USART2 TIM2 DMA request Ethernet MAC USB OTG FS ai15810 ICode bus This bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory instruction interface. Prefetching is performed on this bus. Doc ID 13902 Rev 9 39/995 Memory and bus architecture RM0008 Note: DCode bus This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core to the Flash memory Data interface. System bus This bus connects the system bus of the Cortex™-M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA. DMA bus This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU DCode and DMA to SRAM, Flash memory and peripherals. BusMatrix The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1 and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices, the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges). AHB peripherals are connected on system bus through a BusMatrix to allow DMA access. AHB/APB bridges (APB) The two AHB/APB bridges provide full synchronous connections between the AHB and the 2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz depending on the device). Refer to Table 1 on page 41 for the address mapping of the peripherals connected to each bridge. After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register. When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector. 2.2 40/995 Memory organization Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. For the detailed mapping of peripheral registers, please refer to the related chapters. The addressable memory space is divided into 8 main blocks, each of 512 MB. All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”). Refer to the Memory map figure in the corresponding product datasheet. Doc ID 13902 Rev 9 RM0008 Memory and bus architecture 2.3 Memory map See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 1 gives the boundary addresses of the peripherals available in all STM32F10xxx devices. Table 1. Register boundary addresses Boundary address Peripheral 0x5000 0000 - 0x5000 03FF USB OTG FS 0x4003 0000 - 0x4FFF FFFF 0x4002 8000 - 0x4002 9FFF Reserved Ethernet 0x4002 3400 - 0x4002 7FFF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2000 - 0x4002 23FF Flash memory interface 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF Reserved Reset and clock control RCC 0x4002 0800 - 0x4002 0FFF Reserved 0x4002 0400 - 0x4002 07FF DMA2 0x4002 0000 - 0x4002 03FF DMA1 0x4001 8400 - 0x4001 7FFF 0x4001 8000 - 0x4001 83FF Reserved SDIO 0x4001 4000 - 0x4001 7FFF Reserved 0x4001 3C00 - 0x4001 3FFF ADC3 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF USART1 TIM8 timer 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF TIM1 timer 0x4001 2800 - 0x4001 2BFF ADC2 0x4001 2400 - 0x4001 27FF 0x4001 2000 - 0x4001 23FF ADC1 GPIO Port G 0x4001 1C00 - 0x4001 1FFF GPIO Port F 0x4001 1800 - 0x4001 1BFF GPIO Port E 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF GPIO Port D GPIO Port C 0x4001 0C00 - 0x4001 0FFF GPIO Port B 0x4001 0800 - 0x4001 0BFF GPIO Port A 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF AFIO Bus Register map AHB Section 26.14.6 on page 778 Section 27.8.5 on page 946 Section 3.4.4 on page 52 Section 6.3.11 on page 102 AHB Section 10.4.7 on page 196 Section 10.4.7 on page 196 Section 20.9.16 on page 510 Section 11.12.15 on page 231 Section 25.6.8 on page 693 Section 13.4.21 on page 317 Section 23.5 on page 614 Section 13.4.21 on page 317 Section 11.12.15 on page 231 Section 11.12.15 on page 231 APB2 Section 8.5 on page 167 Section 8.5 on page 167 Section 8.5 on page 167 Section 8.5 on page 167 Section 8.5 on page 167 Section 8.5 on page 167 Section 8.5 on page 167 Section 9.3.7 on page 181 Section 8.5 on page 167 Doc ID 13902 Rev 9 41/995 Memory and bus architecture RM0008 Table 1. Register boundary addresses (continued) Boundary address Peripheral Bus Register map 0x4000 7800 - 0x4000 FFFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF Power control PWR 0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) 0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF bxCAN1 0x4000 6800 - 0x4000 6BFF bxCAN2 0x4000 6000(1) - 0x4000 63FF Shared USB/CAN SRAM 512 bytes 0x4000 5C00 - 0x4000 5FFF USB device FS registers 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 3FFF Reserved 0x4000 3C00 - 0x4000 3FFF SPI3/I2S 0x4000 3800 - 0x4000 3BFF SPI2/I2S 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG) 0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG) 0x4000 2800 - 0x4000 2BFF RTC 0x4000 1800 - 0x4000 27FF Reserved 0x4000 1400 - 0x4000 17FF TIM7 timer 0x4000 1000 - 0x4000 13FF TIM6 timer 0x4000 0C00 - 0x4000 0FFF TIM5 timer 0x4000 0800 - 0x4000 0BFF TIM4 timer 0x4000 0400 - 0x4000 07FF TIM3 timer 0x4000 0000 - 0x4000 03FF TIM2 timer Section 12.5.14 on page 252 Section 4.4.3 on page 65 Section 5.4.5 on page 70 Section 22.9.5 on page 583 Section 22.9.5 on page 583 Section 21.5.4 on page 540 Section 24.6.10 on page 652 Section 24.6.10 on page 652 Section 25.6.8 on page 693 Section 25.6.8 on page 693 Section 25.6.8 on page 693 APB1 Section 25.6.8 on page 693 Section 23.5 on page 614 Section 23.5 on page 614 Section 17.4.5 on page 403 Section 18.6.4 on page 408 Section 16.4.7 on page 398 Section 15.4.9 on page 386 Section 15.4.9 on page 386 Section 14.4.19 on page 373 Section 14.4.19 on page 373 Section 14.4.19 on page 373 Section 14.4.19 on page 373 1. This shared SRAM can be fully accessed only in low-, medium- and high-density devices, not in connectivity line devices. 2.3.1 Embedded SRAM The STM32F10xxx features 64 Kbytes of static SRAM. It can be accessed as bytes, halfwords (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000. 42/995 Doc ID 13902 Rev 9 RM0008 Memory and bus architecture 2.3.2 Bit banding The Cortex™-M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region. In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region. This allows single bit-band write and read operations to be performed. A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. bit_band_base is the starting address of the alias region byte_offset is the number of the byte in the bit-band region that contains the targeted bit bit_number is the bit position (0-7) of the targeted bit. Example: The following example shows how to map bit 2 of the byte located at SRAM address 0x20000300 in the alias region: 0x22006008 = 0x22000000 + (0x300*32) + (2*4). Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM address 0x20000300. Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset). For more information on Bit-Banding, please refer to the Cortex™-M3 Technical Reference Manual. Doc ID 13902 Rev 9 43/995 Memory and bus architecture RM0008 2.3.3 Embedded Flash memory The high-performance Flash memory module has the following key features: ● Density of up to 512 Kbytes ● Memory organization: the Flash memory is organized as a main block and an information block: – Main memory block of size: up to 4 Kb × 64 bits divided into 32 pages of 1 Kbyte each for low-density devices (see Table 2) up to 16 Kb × 64 bits divided into 128 pages of 1 Kbyte each for medium-density devices (see Table 3) up to 64 Kb × 64 bits divided into 256 pages of 2 Kbytes each (see Table 4) for high-density devices up to 32 Kbit × 64 bits divided into 128 pages of 2 Kbytes each (see Table 5) for connectivity line devices – Information block of size: 2360 × 64 bits for connectivity line devices (see Table 5) 258 × 64 bits for other devices (see Table 2, Table 3 and Table 4) The Flash memory interface (FLITF) features: ● Read interface with prefetch buffer (2x64-bit words) ● Option byte Loader ● Flash Program / Erase operation ● Read / Write protection Table 2. Flash module organization (low-density devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte Page 1 Page 2 0x0800 0400 - 0x0800 07FF 0x0800 0800 - 0x0800 0BFF 1 Kbyte 1 Kbyte Main memory Page 3 Page 4 0x0800 0C00 - 0x0800 0FFF 0x0800 1000 - 0x0800 13FF 1 Kbyte 1 Kbyte . . . Page 31 . . . 0x0800 7C00 - 0x0800 7FFF . . . 1 Kbyte Information block System memory Option Bytes 0x1FFF F000 - 0x1FFF F7FF 0x1FFF F800 - 0x1FFF F80F 2 Kbytes 16 44/995 Doc ID 13902 Rev 9 RM0008 Memory and bus architecture Table 2. Flash module organization (low-density devices) (continued) Block Name Base addresses Size (bytes) FLASH_ACR 0x4002 2000 - 0x4002 2003 4 FLASH_KEYR 0x4002 2004 - 0x4002 2007 4 Flash memory interface registers FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4 FLASH_SR 0x4002 200C - 0x4002 200F 4 FLASH_CR 0x4002 2010 - 0x4002 2013 4 FLASH_AR 0x4002 2014 - 0x4002 2017 4 Reserved 0x4002 2018 - 0x4002 201B 4 FLASH_OBR FLASH_WRPR 0x4002 201C - 0x4002 201F 4 0x4002 2020 - 0x4002 2023 4 Table 3. Flash module organization (medium-density devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte Main memory Page 3 Page 4 0x0800 0C00 - 0x0800 0FFF 0x0800 1000 - 0x0800 13FF 1 Kbyte 1 Kbyte . . . . . . . . . Page 127 0x0801 FC00 - 0x0801 FFFF 1 Kbyte Information block System memory Option Bytes 0x1FFF F000 - 0x1FFF F7FF 0x1FFF F800 - 0x1FFF F80F 2 Kbytes 16 FLASH_ACR 0x4002 2000 - 0x4002 2003 4 FLASH_KEYR 0x4002 2004 - 0x4002 2007 4 Flash memory interface registers FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4 FLASH_SR 0x4002 200C - 0x4002 200F 4 FLASH_CR 0x4002 2010 - 0x4002 2013 4 FLASH_AR 0x4002 2014 - 0x4002 2017 4 Reserved 0x4002 2018 - 0x4002 201B 4 FLASH_OBR FLASH_WRPR 0x4002 201C - 0x4002 201F 4 0x4002 2020 - 0x4002 2023 4 Doc ID 13902 Rev 9 45/995 Memory and bus architecture RM0008 Table 4. Flash module organization (high-density devices) Block Name Base addresses Size (bytes) Main memory Information block Flash memory interface registers Page 0 Page 1 Page 2 Page 3 . . . Page 255 System memory Option Bytes FLASH_ACR FLASH_KEYR FLASH_OPTKEYR FLASH_SR FLASH_CR FLASH_AR Reserved FLASH_OBR FLASH_WRPR 0x0800 0000 - 0x0800 07FF 0x0800 0800 - 0x0800 0FFF 0x0800 1000 - 0x0800 17FF 0x0800 1800 - 0x0800 1FFF . . . 0x0807 F800 - 0x0807 FFFF 0x1FFF F000 - 0x1FFF F7FF 0x1FFF F800 - 0x1FFF F80F 0x4002 2000 - 0x4002 2003 0x4002 2004 - 0x4002 2007 0x4002 2008 - 0x4002 200B 0x4002 200C - 0x4002 200F 0x4002 2010 - 0x4002 2013 0x4002 2014 - 0x4002 2017 0x4002 2018 - 0x4002 201B 0x4002 201C - 0x4002 201F 0x4002 2020 - 0x4002 2023 2 Kbytes 2 Kbytes 2 Kbytes 2 Kbytes . . . 2 Kbytes 2 Kbytes 16 4 4 4 4 4 4 4 4 4 46/995 Doc ID 13902 Rev 9 RM0008 Memory and bus architecture Table 5. Flash module organization (connectivity line devices) Block Name Base addresses Size (bytes) Main memory Information block Flash memory interface registers Page 0 Page 1 Page 2 Page 3 . . . Page 127 System memory Option Bytes FLASH_ACR FLASH_KEYR FLASH_OPTKEYR FLASH_SR FLASH_CR FLASH_AR Reserved FLASH_OBR FLASH_WRPR 0x0800 0000 - 0x0800 07FF 0x0800 0800 - 0x0800 0FFF 0x0800 1000 - 0x0800 17FF 0x0800 1800 - 0x0800 1FFF . . . 0x0803 F800 - 0x0803 FFFF 0x1FFF B000 - 0x1FFF F7FF 0x1FFF F800 - 0x1FFF F80F 0x4002 2000 - 0x4002 2003 0x4002 2004 - 0x4002 2007 0x4002 2008 - 0x4002 200B 0x4002 200C - 0x4002 200F 0x4002 2010 - 0x4002 2013 0x4002 2014 - 0x4002 2017 0x4002 2018 - 0x4002 201B 0x4002 201C - 0x4002 201F 0x4002 2020 - 0x4002 2023 2 Kbytes 2 Kbytes 2 Kbytes 2 Kbytes . . . 2 Kbytes 18 Kbytes 16 4 4 4 4 4 4 4 4 4 Note: For further information on the Flash memory interface registers, please refer to the STM32F10xxx Flash programming manual. Reading the Flash memory Flash memory instructions and data access are performed through the AHB bus. The prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed in the Flash memory interface, and priority is given to data access on the DCode bus. Read accesses can be performed with the following configuration options: ● Latency: number of wait states for a read operation programmed on-the-fly ● Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be replaced with a single read from the Flash memory as the size of the block matches the bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is possible as the CPU fetches one word at a time with the next word readily available in the prefetch buffer ● Half cycle: for power optimization Doc ID 13902 Rev 9 47/995 Memory and bus architecture RM0008 Note: 1 These options should be used in accordance with the Flash memory access time. The wait states represent the ratio of the SYSCLK (system clock) period to the Flash memory access time: zero wait state, if 0 < SYSCLK  24 MHz one wait state, if 24 MHz < SYSCLK  48 MHz two wait states, if 48 MHz < SYSCLK  72 MHz 2 Half cycle configuration is not available in combination with a prescaler on the AHB. The system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or the HSE but not from the PLL. 3 The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. 4 The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz. The prefetch buffer is usually switched on/off during the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator. 5 Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode instructions. The DMA provides one free cycle after each transfer. Some instructions can be performed together with DMA transfer. Note: Programming and erasing the Flash memory The Flash memory can be programmed 16 bits (half words) at a time. The Flash memory erase operation can be performed at page level or on the whole Flash area (mass-erase). The mass-erase does not affect the information blocks. To ensure that there is no over-programming, the Flash Programming and Erase Controller blocks are clocked by a fixed clock. The End of write operation (programming or erasing) can trigger an interrupt. This interrupt can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the interrupt is served only after an exit from WFI. For further information on Flash memory operations and register configurations, please refer to the STM32F10xxx Flash programming manual. 2.4 Boot configuration In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as shown in Table 6. Table 6. Boot modes Boot mode selection pins BOOT1 BOOT0 Boot mode Aliasing x 0 Main Flash memory Main Flash memory is selected as boot space 0 1 System memory System memory is selected as boot space 1 1 Embedded SRAM Embedded SRAM is selected as boot space 48/995 Doc ID 13902 Rev 9 RM0008 Memory and bus architecture Note: The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a Reset. It is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot mode. The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004. Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address 0x2000 0000 (accessed through the system bus). The Cortex-M3 CPU always fetches the reset vector on the ICode bus, which implies to have the boot space available only in the code area (typically, Flash memory). STM32F10xxx microcontrollers implement a special mechanism to be able to boot also from SRAM and not only from main Flash memory and System memory. Depending on the selected boot mode main Flash memory, System memory or SRAM is accessible as follows: ● Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x800 0000. ● Boot from System memory: the System memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in connectivity line devices, 0x1FFF F000 in other devices). ● Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000. When booting from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register. Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory with one of the available serial interfaces: ● In low-, medium- and high-density devices the bootloader is activated through the USART1 interface. For further details please refer to AN2606. ● In connectivity line devices the bootloader can be activated through one of the following interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in Device mode (DFU: device firmware upgrade). The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present. For further details, please refer to AN2662. Doc ID 13902 Rev 9 49/995 CRC calculation unit 3 CRC calculation unit RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 3.1 CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.2 CRC main features ● Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 – X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1 ● Single input/output 32-bit data register ● CRC computation done in 4 AHB clock cycles (HCLK) ● General-purpose 8-bit register (can be used for temporary storage) The block diagram is shown in Figure 3. Figure 3. CRC calculation unit block diagram AHB bus 32-bit (read access) Data register (output) CRC computation (polynomial: 0x4C11DB7) 32-bit (write access) Data register (input) ai14968 50/995 Doc ID 13902 Rev 9 RM0008 CRC calculation unit 3.3 CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: ● is used as an input register to enter new data in the CRC calculator (when writing into the register) ● holds the result of the previous CRC calculation (when reading the register) Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte). The write operation is stalled until the end of the CRC computation, thus allowing back-toback write accesses or consecutive write and read accesses. The CRC calculator can be reset to FFFF FFFFh with the RESET control bit in the CRC_CR register. This operation does not affect the contents of the CRC_IDR register. 3.4 CRC registers The CRC calculation unit contains two data registers and a control register. 3.4.1 Data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DR [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR [15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 Data register bits Used as an input register when writing new data into the CRC calculator. Holds the previous CRC calculation result when it is read. Doc ID 13902 Rev 9 51/995 CRC calculation unit RM0008 3.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 1 0 IDR[7:0] rw rw rw rw rw rw rw rw Bits 31:8 Reserved Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register. 3.4.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RESET w Bits 31:1 Bit 0 Reserved RESET bit Resets the CRC calculation unit and sets the data register to FFFF FFFFh. This bit can only be set, it is automatically cleared by hardware. 3.4.4 CRC register map The following table provides the CRC register map and reset values. Table 7. CRC calculation unit register map and reset values Offset Register 31-24 23-16 15-8 7 6 5 4 3 2 1 0 0x00 0x04 0x08 CRC_DR Reset value CRC_IDR Reset value CRC_CR Reset value Reserved Data register 0xFFFF FFFF Independent data register 0x00 Reserved Reserved 0 RESET 0 52/995 Doc ID 13902 Rev 9 RM0008 4 Power control (PWR) Power control (PWR) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 4.1 Power supplies The device requires a 2.0-to-3.6 V operating voltage supply (VDD). An embedded regulator is used to supply the internal 1.8 V digital power. The real-time clock (RTC) and backup registers can be powered from the VBAT voltage when the main VDD supply is powered off. Figure 4. Power supply overview (VSSA) VREF(from 2.4 V up to VDDA)VREF+ (VDD) VDDA (VSS) VSSA VDDA domain A/D converter Temp. sensor Reset block PLL VDD domain 1.8 V domain I/O Ring VSS Core Standby circuitry Memories VDD (Wakeup logic, digital IWDG) peripherals Voltage Regulator VBAT Low voltage detector Backup domain LSE crystal 32K osc BKP registers RCC BDCR register RTC Note: 1 VDDA and VSSA must be connected to VDD and VSS, respectively. Doc ID 13902 Rev 9 53/995 Power control (PWR) RM0008 4.1.1 4.1.2 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. ● The ADC voltage supply input is available on a separate VDDA pin. ● An isolated supply ground connection is provided on pin VSSA. When available (according to package), VREF- must be tied to VSSA. On 100-pin and 144- pin packages To ensure a better accuracy on low voltage inputs, the user can connect a separate external reference voltage ADC input on VREF+ and VREF-. The voltage on VREF+ can range from 2.4 V to VDDA. On 64-pin packages The VREF+ and VREF- pins are not available, they are internally connected to the ADC voltage supply (VDDA) and ground (VSSA). Battery backup domain To retain the content of the Backup registers and supply the RTC function when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing the RTC to operate even when the main digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the Power Down Reset embedded in the Reset block. Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR is detected, the power switch between VBAT and VDD remains connected to VBAT. During the startup phase, if VDD is established in less than tRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO) and VDD > VBAT + 0.6 V, a current may be injected into VBAT through an internal diode connected between VDD and the power switch (VBAT). If the power supply/battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin. If no external battery is used in the application, it is recommended to connect VBAT externally to VDD through a 100 nF external ceramic capacitor (for more details refer to AN2586). When the backup domain is supplied by VDD (analog switch connected to VDD), the following functions are available: ● PC14 and PC15 can be used as either GPIO or LSE pins ● PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or second output (refer to Section 5: Backup registers (BKP) on page 66) 54/995 Doc ID 13902 Rev 9 RM0008 Power control (PWR) Note: 4.1.3 Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). When the backup domain is supplied by VBAT (analog switch connected to VBAT because VDD is not present), the following functions are available: ● PC14 and PC15 can be used as LSE pins only ● PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to section Section 5.4.2: RTC clock calibration register (BKP_RTCCR) on page 68). Voltage regulator The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes. ● In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals). ● In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving contents of registers and SRAM ● In Standby Mode, the regulator is powered off. The contents of the registers and SRAM are lost except for the Standby circuitry and the Backup Domain. 4.2 4.2.1 Power supply supervisor Power on reset (POR)/power down reset (PDR) The device has an integrated POR/PDR circuitry that allows proper operation starting from/down to 2 V. The device remains in Reset mode when VDD/VDDA is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics of the datasheet. Doc ID 13902 Rev 9 55/995 Power control (PWR) Figure 5. Power on reset/power down reset waveform VDD/VDDA POR 40 mV hysteresis Temporization tRSTTEMPO RM0008 PDR Reset 4.2.2 Programmable voltage detector (PVD) You can use the PVD to monitor the VDD/VDDA power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when VDD/VDDA drops below the PVD threshold and/or when VDD/VDDA rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. Figure 6. PVD thresholds VDD/VDDA PVD threshold 100 mV hysteresis PVD output 56/995 Doc ID 13902 Rev 9 RM0008 Power control (PWR) 4.3 Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources. The STM32F10xxx devices feature three low-power modes: ● Sleep mode (CPU clock off, all peripherals including Cortex-M3 core peripherals like NVIC, SysTick, etc. are kept running) ● Stop mode (all clocks are stopped) ● Standby mode (1.8V domain powered-off) In addition, the power consumption in Run mode can be reduce by one of the following means: ● Slowing down the system clocks ● Gating the clocks to the APB and AHB peripherals when they are unused. Table 8. Low-power mode summary Mode name Entry wakeup Effect on 1.8V domain clocks Effect on VDD domain clocks Voltage regulator Sleep (Sleep now or Sleep-on exit) WFI WFE Any interrupt CPU clock OFF no effect on other None ON Wakeup event clocks or analog clock sources Stop Standby PDDS and LPDS bits + SLEEPDEEP bit + WFI or WFE PDDS bit + SLEEPDEEP bit + WFI or WFE Any EXTI line (configured in the EXTI registers) WKUP pin rising edge, RTC alarm, external reset in NRST pin, IWDG reset All 1.8V domain clocks OFF ON or in lowpower mode (depends on Power control HSI and register HSE (PWR_CR)) oscillators OFF OFF 4.3.1 Slowing down system clocks In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode. For more details refer to Section 6.3.2: Clock configuration register (RCC_CFGR). Doc ID 13902 Rev 9 57/995 Power control (PWR) RM0008 4.3.2 4.3.3 Peripheral clock gating In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. Peripheral clock gating is controlled by the AHB peripheral clock enable register (RCC_AHBENR), APB1 peripheral clock enable register (RCC_APB1ENR) and APB2 peripheral clock enable register (RCC_APB2ENR). Sleep mode Entering Sleep mode The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions. Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex-M3 System Control register: ● Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed. ● Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits the lowest priority ISR. In the Sleep mode, all I/O pins keep the same state as in the Run mode. Refer to Table 9 and Table 10 for details on how to enter Sleep mode. Exiting Sleep mode If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated either by: ● enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex-M3 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. ● or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit. Refer to Table 9 and Table 10 for more details on how to exit Sleep mode. 58/995 Doc ID 13902 Rev 9 RM0008 Power control (PWR) Table 9. Sleep-now Sleep-now mode Description Mode entry Mode exit Wakeup latency WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 0 Refer to the Cortex™-M3 System Control register. If WFI was used for entry: Interrupt: Refer to Table 53: Vector table for other STM32F10xxx devices If WFE was used for entry Wakeup event: Refer to Section 9.2.3: Wakeup event management None Table 10. Sleep-on-exit Sleep-on-exit Description Mode entry Mode exit WFI (wait for interrupt) while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 Refer to the Cortex™-M3 System Control register. Interrupt: refer to Table 53: Vector table for other STM32F10xxx devices. Wakeup latency None 4.3.4 Stop mode The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved. In the Stop mode, all I/O pins keep the same state as in the Run mode. Entering Stop mode Refer to Table 11 for details on how to enter the Stop mode. To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPDS bit of the Power control register (PWR_CR). If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished. If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished. Doc ID 13902 Rev 9 59/995 Power control (PWR) RM0008 In Stop mode, the following features can be selected by programming individual control bits: ● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 17.3 in Section 17: Independent watchdog (IWDG). ● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) ● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR). ● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR). The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0. Exiting Stop mode Refer to Table 11 for more details on how to exit Stop mode. When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock. When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced. Table 11. Stop mode Stop mode Description Mode entry WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP bit in Cortex™-M3 System Control register – Clear PDDS bit in Power Control register (PWR_CR) – Select the voltage regulator mode by configuring LPDS bit in PWR_CR Mode exit Wakeup latency Note: To enter Stop mode, all EXTI Line pending bits (in Pending register (EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues. If WFI was used for entry: Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). Refer to Table 53: Vector table for other STM32F10xxx devices on page 172. If WFE was used for entry: Any EXTI Line configured in event mode. Refer to Section 9.2.3: Wakeup event management on page 175 HSI RC wakeup time + regulator wakeup time from Low-power mode 4.3.5 Standby mode The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also 60/995 Doc ID 13902 Rev 9 RM0008 Power control (PWR) switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 4). Entering Standby mode Refer to Table 12 for more details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: ● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 17.3 in Section 17: Independent watchdog (IWDG). ● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) ● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR). ● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) Exiting Standby mode The microcontroller exits Standby mode when an external Reset (NRST pin), IWDG Reset, a rising edge on WKUP pin or an RTC alarm occurs. All registers are reset after wakeup from Standby except for Power control/status register (PWR_CSR). After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power control/status register (PWR_CSR) indicates that the MCU was in Standby mode. Refer to Table 12 for more details on how to exit Standby mode. Table 12. Standby mode Standby mode Description Mode entry Mode exit Wakeup latency WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP in Cortex™-M3 System Control register – Set PDDS bit in Power Control register (PWR_CR) – Clear WUF bit in Power Control/Status register (PWR_CSR) WKUP pin rising edge, RTC alarm, external Reset in NRST pin, IWDG Reset. Regulator start up. Reset phase I/O states in Standby mode In Standby mode, all I/O pins are high impedance except: ● Reset pad (still available) ● TAMPER pin if configured for tamper or calibration out ● WKUP pin, if enabled Doc ID 13902 Rev 9 61/995 Power control (PWR) RM0008 4.3.6 Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex™-M3 core is no longer clocked. However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 29.16.1: Debug support for low-power modes. Auto-wakeup (AWU) from low-power mode The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR): ● Low-power 32.768 kHz external crystal oscillator (LSE OSC). This clock source provides a precise time base with very low-power consumption (less than 1µA added consumption in typical conditions) ● Low-power internal RC Oscillator (LSI RC) This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption. To wakeup from Stop mode with an RTC alarm event, it is necessary to: ● Configure the EXTI Line 17 to be sensitive to rising edge ● Configure the RTC to generate the RTC alarm To wakeup from Standby mode, there is no need to configure the EXTI Line 17. 4.4 Power control registers 4.4.1 Power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DBP rw PLS[2:0] rw rw rw PVDE CSBF CWUF PDDS LPDS rw rc_w1 rc_w1 rw rw Bits 31:9 Reserved, always read as 0. 62/995 Doc ID 13902 Rev 9 RM0008 Power control (PWR) Bit 8 DBP: Disable backup domain write protection. In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1. Bits 7:5 PLS[2:0]: PVD level selection. These bits are written by software to select the voltage threshold detected by the Power Voltage Detector 000: 2.2V 001: 2.3V 010: 2.4V 011: 2.5V 100: 2.6V 101: 2.7V 110: 2.8V 111: 2.9V Note: Refer to the electrical characteristics of the datasheet for more details. Bit 4 PVDE: Power voltage detector enable. This bit is set and cleared by software. 0: PVD disabled 1: PVD enabled Bit 3 CSBF: Clear standby flag. This bit is always read as 0. 0: No effect 1: Clear the SBF Standby Flag (write). Bit 2 CWUF: Clear wakeup flag. This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write) Bit 1 PDDS: Power down deepsleep. This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the LPDS bit. 1: Enter Standby mode when the CPU enters Deepsleep. Bit 0 LPDS: Low-power deepsleep. This bit is set and cleared by software. It works together with the PDDS bit. 0: Voltage regulator on during Stop mode 1: Voltage regulator in low-power mode during Stop mode Doc ID 13902 Rev 9 63/995 Power control (PWR) RM0008 4.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWUP rw Reserved PVDO SBF r r WUF r Bits 31:9 Reserved, always read as 0. Bit 8 EWUP: Enable WKUP pin This bit is set and cleared by software. 0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the device from Standby mode. 1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin wakes-up the system from Standby mode). Note: This bit is reset by a system Reset. Bits 7:3 Reserved, always read as 0. Bit 2 PVDO: PVD output This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. 0: VDD/VDDA is higher than the PVD threshold selected with the PLS[2:0] bits. 1: VDD/VDDA is lower than the PVD threshold selected with the PLS[2:0] bits. Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set. Bit 1 SBF: Standby flag This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset) or by setting the CSBF bit in the Power control register (PWR_CR) 0: Device has not been in Standby mode 1: Device has been in Standby mode Bit 0 WUF: Wakeup flag This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset) or by setting the CWUF bit in the Power control register (PWR_CR) 0: No wakeup event occurred 1: A wakeup event was received from the WKUP pin or from the RTC alarm Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high. 64/995 Doc ID 13902 Rev 9 RM0008 Power control (PWR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DBP 8 7 6 5 PVDE 4 CSBF 3 CWUF 2 PDDS 1 LPDS 0 4.4.3 PWR register map The following table summarizes the PWR registers. Table 13. PWR register map and reset values Offset Register 0x000 0x004 PWR_CR Reset value PWR_CSR Reset value Reserved Reserved PLS[2:0] 000000000 Reserved 0 000 EWUP PVDO SBF WUF Refer to Table 1 on page 41 for the register boundary addresses. Doc ID 13902 Rev 9 65/995 Backup registers (BKP) 5 Backup registers (BKP) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to the whole STM32F10xxx family, unless otherwise specified. 5.1 BKP introduction The backup registers are forty two 16-bit registers for storing 84 bytes of user application data. They are implemented in the backup domain that remains powered on by VBAT when the VDD power is switched off. They are not reset when the device wakes up from Standby mode or by a system reset or power reset. In addition, the BKP control registers are used to manage the Tamper detection feature and RTC calibration. After reset, access to the Backup registers and RTC is disabled and the Backup domain (BKP) is protected against possible parasitic write access. To enable access to the Backup registers and the RTC, proceed as follows: ● enable the power and backup interface clocks by setting the PWREN and BKPEN bits in the RCC_APB1ENR register ● set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup registers and RTC. 5.2 BKP main features ● 20-byte data registers (in medium-density and low-density devices) or 84-byte data registers (in high-density and connectivity line devices) ● Status/control register for managing tamper detection with interrupt capability ● Calibration register for storing the RTC calibration value ● Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on TAMPER pin PC13 (when this pin is not used for tamper detection) 66/995 Doc ID 13902 Rev 9 RM0008 Backup registers (BKP) 5.3 5.3.1 Note: 5.3.2 BKP functional description Tamper detection The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper detection event resets all data backup registers. However to avoid losing Tamper events, the signal used for edge detection is logically ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before the TAMPER pin is enabled. ● When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while there was no rising edge on the TAMPER pin after TPE was set) ● When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while there was no falling edge on the TAMPER pin after TPE was set) By setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper detection event occurs. After a Tamper event has been detected and cleared, the TAMPER pin should be disabled and then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again. This prevents software from writing to the backup data registers (BKP_DRx), while the TAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection on the TAMPER pin. Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting of the data backup registers, the TAMPER pin should be externally tied to the correct level. RTC calibration For measurement purposes, the RTC clock with a frequency divided by 64 can be output on the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register (BKP_RTCCR). The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits. For more details about RTC calibration and how to use it to improve timekeeping accuracy, please refer to AN2604 "STM32F101xx and STM32F103xx RTC calibration”. Doc ID 13902 Rev 9 67/995 Backup registers (BKP) RM0008 5.4 BKP registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. 5.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 D[15:0] Backup data These bits can be written with user data. Note: The BKP_DRx registers are not reset by a System reset or Power reset or when the device wakes up from Standby mode. They are reset by a Backup Domain reset or by a TAMPER pin event (if the TAMPER pin function is activated). 5.4.2 RTC clock calibration register (BKP_RTCCR) Address offset: 0x2C Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ASOS ASOE CCO CAL[6:0] rw rw rw rw rw rw rw rw rw rw Bits 15:10 Reserved, always read as 0. Bit 9 ASOS: Alarm or second output selection When the ASOE bit is set, the ASOS bit can be used to select whether the signal output on the TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal: 0: RTC Alarm pulse output selected 1: RTC Second pulse output selected Note: This bit is reset only by a Backup domain reset. Bit 8 ASOE: Alarm or second output enable Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit. The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the ASOE bit is set. Note: This bit is reset only by a Backup domain reset. Bit 7 CCO: Calibration clock output 0: No effect 1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin. The TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted Tamper detection. Note: This bit is reset when the VDD supply is powered off. 68/995 Doc ID 13902 Rev 9 RM0008 Backup registers (BKP) Bit 6:0 CAL[6:0]: Calibration value This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses. This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20 PPM. The clock of the RTC can be slowed down from 0 to 121PPM. 5.4.3 Backup control register (BKP_CR) Address offset: 0x30 Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TPAL TPE rw rw Note: Bits 15:2 Reserved, always read as 0. Bit 1 TPAL: TAMPER pin active level 0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set). 1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set). Bit 0 TPE: TAMPER pin enable 0: The TAMPER pin is free for general purpose I/O 1: Tamper alternate I/O function is activated. Setting the TPAL and TPE bits at the same time is always safe, however resetting both at the same time can generate a spurious Tamper event. For this reason it is recommended to change the TPAL bit only when the TPE bit is reset. 5.4.4 Backup control/status register (BKP_CSR) Address offset: 0x34 Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 Reserved TIF TEF r r 6 5 4 Reserved 3 2 1 0 TPIE CTI CTE rw w w Bits 15:10 Reserved, always read as 0. Bit 9 TIF: Tamper interrupt flag This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is reset. 0: No Tamper interrupt 1: A Tamper interrupt occurred Note: This bit is reset only by a system reset and wakeup from Standby mode. Doc ID 13902 Rev 9 69/995 Backup registers (BKP) RM0008 Bit 8 TEF: Tamper event flag This bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the CTE bit. 0: No Tamper event 1: A Tamper event occurred Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the TEF bit is set. If a write to the BKP_DRx registers is performed while this bit is set, the value will not be stored. Bits 7:3 Reserved, always read as 0. Bit 2 TPIE: TAMPER pin interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register Note: 1: A Tamper interrupt does not wake up the core from low-power modes. 2: This bit is reset only by a system reset and wakeup from Standby mode. Bit 1 CTI: Clear tamper interrupt This bit is write only, and is always read as 0. 0: No effect 1: Clear the Tamper interrupt and the TIF Tamper interrupt flag. Bit 0 CTE: Clear tamper event This bit is write only, and is always read as 0. 0: No effect 1: Reset the TEF Tamper event flag (and the Tamper detector) 5.4.5 BKP register map BKP registers are mapped as 16-bit addressable registers as described in the table below: Table 14. BKP register map and reset values Offset Register 0x00 Reserved 0x04 0x08 0x0C 0x10 0x14 0x18 BKP_DR1 Reset value BKP_DR2 Reset value BKP_DR3 Reset value BKP_DR4 Reset value BKP_DR5 Reset value BKP_DR6 Reset value Reserved Reserved Reserved Reserved Reserved Reserved D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 70/995 Doc ID 13902 Rev 9 0 RM0008 Backup registers (BKP) CTE TPE Table 14. BKP register map and reset values (continued) Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x1C 0x20 0x24 0x28 0x2 0x30 0x34 0x38 BKP_DR7 Reset value BKP_DR8 Reset value BKP_DR9 Reset value BKP_DR10 Reset value BKP_RTCCR Reset value BKP_CR Reset value BKP_CSR Reset value Reserved Reserved Reserved Reserved Reserved D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] CCO ASOE ASOS 0000000000000000 CAL[6:0] 0000000000 Reserved 00 CTI TPAL TPIE TEF TIF Reserved Reserved 00 Reserved 000 0x3C Reserved 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 BKP_DR11 Reset value BKP_DR12 Reset value BKP_DR13 Reset value BKP_DR14 Reset value BKP_DR15 Reset value BKP_DR16 Reset value BKP_DR17 Reset value BKP_DR18 Reset value BKP_DR19 Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 Doc ID 13902 Rev 9 71/995 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Backup registers (BKP) RM0008 Table 14. BKP register map and reset values (continued) Offset Register 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 BKP_DR20 Reset value BKP_DR21 Reset value BKP_DR22 Reset value BKP_DR23 Reset value BKP_DR24 Reset value BKP_DR25 Reset value BKP_DR26 Reset value BKP_DR27 Reset value BKP_DR28 Reset value BKP_DR29 Reset value BKP_DR30 Reset value BKP_DR31 Reset value BKP_DR32 Reset value BKP_DR33 Reset value BKP_DR34 Reset value BKP_DR35 Reset value BKP_DR36 Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 72/995 Doc ID 13902 Rev 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0008 Backup registers (BKP) Table 14. BKP register map and reset values (continued) Offset Register 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC BKP_DR37 Reset value BKP_DR38 Reset value BKP_DR39 Reset value BKP_DR40 Reset value BKP_DR41 Reset value BKP_DR42 Reset value Reserved Reserved Reserved Reserved Reserved Reserved D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 Refer to Table 1 on page 41 for the register boundary addresses. Doc ID 13902 Rev 9 73/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 6 Low-, medium- and high-density reset and clock control (RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to low-, medium- and high-density STM32F10xxx devices. Connectivity line devices are discussed in a separate section (refer to Connectivity line devices: reset and clock control (RCC) on page 104). 6.1 6.1.1 Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 4). A system reset is generated when one of the following events occurs: 1. A low level on the NRST pin (external reset) 2. Window watchdog end of count condition (WWDG reset) 3. Independent watchdog end of count condition (IWDG reset) 4. A software reset (SW reset) (see Section : Software reset) 5. Low-power management reset (see Section : Low-power management reset) The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 6.3.10: Control/status register (RCC_CSR)). Software reset The SYSRESETREQ bit in Cortex™-M3 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the Cortex™-M3 technical reference manual for more details. Low-power management reset There are two ways to generate a low-power management reset: 74/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.1.2 6.1.3 1. Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode. 2. Reset when entering Stop mode: This type of reset is enabled by resetting NRST_STOP bit in User Option Bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode. For further information on the User Option Bytes, refer to the STM32F10xxx Flash programming manual. Power reset A power reset is generated when one of the following events occurs: 1. Power-on/power-down reset (POR/PDR reset) 2. When exiting Standby mode A power reset sets all registers to their reset values except the Backup domain (see Figure 4) These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more details, refer to Table 53: Vector table for other STM32F10xxx devices on page 172. Figure 7. Reset circuit External reset NRST VDD/VDDA RPU Filter Pulse generator (min 20 µs) System reset WWDG reset IWDG reset Power reset Software reset Low-power management reset ai16095 Backup domain reset The backup domain has two specific resets that affect only the backup domain (see Figure 4). A backup domain reset is generated when one of the following events occurs: 1. Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). 2. VDD or VBAT power on, if both supplies have previously been powered off. Doc ID 13902 Rev 9 75/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 6.2 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): ● HSI oscillator clock ● HSE oscillator clock ● PLL clock The devices have the following two secondary clock sources: ● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode. ● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real- time clock (RTCCLK) Each clock source can be switched on or off independently when it is not used, to optimize power consumption. 76/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) Figure 8. Clock tree OSC_OUT OSC_IN OSC32_IN OSC32_OUT USB Prescaler /1, 1.5 48 MHz USBCLK to USB interface I2S3CLK to I2S3 Peripheral clock enable I2S2CLK to I2S2 8 MHz HSI RC HSI /2 PLLSRC PLLMUL ..., x16 x2, x3, x4 PLL Peripheral clock enable Peripheral clock enable Peripheral clock enable 72 MHz max Clock Enable SW /8 HSI PLLCLK HSE SYSCLK AHB 72 MHz Prescaler max /1, 2..512 APB1 Prescaler /1, 2, 4, 8, 16 SDIOCLK to SDIO FSMCCLK to FSMC HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock 36 MHz max PCLK1 to APB1 Peripheral Clock peripherals Enable CSS TIM2,3,4,5,6,7 If (APB1 prescaler =1) x1 else x2 to TIM2,3,4,5,6 and 7 TIMXCLK Peripheral Clock Enable 4-16 MHz HSE OSC PLLXTPRE /2 LSE OSC 32.768 kHz /128 LSE to RTC RTCCLK APB2 Prescaler /1, 2, 4, 8, 16 72 MHz max PCLK2 peripherals to APB2 Peripheral Clock Enable TIM1 & 8 timers If (APB2 prescaler =1) x1 to TIM1 and TIM8 else x2 TIMxCLK Peripheral Clock ADC Prescaler /2, 4, 6, 8 Enable to ADC1, 2 or 3 ADCCLK 14 MHz max LSI RC 40 kHz RTCSEL[1:0] LSI to Independent Watchdog (IWDG) IWDGCLK /2 HCLK/2 To SDIO AHB interface Peripheral clock enable MCO Main /2 Clock Output MCO PLLCLK HSI HSE SYSCLK Legend: HSE = High-speed external clock signal HSI = High-speed internal clock signal LSI = Low-speed internal clock signal LSE = Low-speed external clock signal ai14752d 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet. Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2. The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock (HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8. The timer clock frequencies are automatically fixed by hardware. There are two cases: Doc ID 13902 Rev 9 77/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 6.2.1 1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected. FCLK acts as Cortex™-M3 free running clock. For more details refer to the ARM Cortex™M3 Technical Reference Manual. HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: ● HSE external crystal/ceramic resonator ● HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. Figure 9. HSE/ LSE clock sources Clock source Hardware configuration External clock OSC_OUT External source (HiZ) Crystal/Ceramic resonators OSC_IN OSC_OUT CL1 CL2 Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 25 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 9. 78/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.2.2 6.2.3 External crystal/ceramic resonator (HSE crystal) The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 9. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). The HSE Crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR). HSI clock The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input. The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator. Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at TA=25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control register (RCC_CR). If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the Clock control register (RCC_CR). The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware. The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 6.2.7: Clock security system (CSS) on page 81. PLL The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock frequency. Refer to Figure 8 and Clock control register (RCC_CR). The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL enabled, these parameters cannot be changed. An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt register (RCC_CIR). Doc ID 13902 Rev 9 79/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 6.2.4 6.2.5 Note: If the USB interface is used in the application, the PLL must be programmed to output 48 or 72 MHz. This is needed to provide a 48 MHz USBCLK. LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. The LSE crystal is switched on and off using the LSEON bit in Backup domain control register (RCC_BDCR). The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). External source (LSE bypass) In this mode, an external clock source must be provided. It must have a frequency of 32.768 kHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z. See Figure 9. LSI clock The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets. The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR). The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). LSI calibration is only available on high-density and connectivity line devices. LSI calibration The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy. This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout. 80/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.2.6 6.2.7 Note: 6.2.8 Use the following procedure to calibrate the LSI: 1. Enable TIM5 timer and configure channel4 in input capture mode 2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose. 3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or interrupt. 4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout. System clock (SYSCLK) selection After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as system clock. Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a clock failure event is sent to the break input of the advanced-control timers (TIM1 and TIM8) and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex™-M3 NMI (Non-Maskable Interrupt) exception vector. Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too. RTC clock The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain. Doc ID 13902 Rev 9 81/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 6.2.9 6.2.10 The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: ● If LSE is selected as RTC clock: – The RTC continues to work even if the VDD supply is switched off, provided the VBAT supply is maintained. ● If LSI is selected as Auto-Wakeup unit (AWU) clock: – The AWU state is not guaranteed if the VDD supply is powered off. Refer to Section 6.2.5: LSI clock on page 80 for more details on LSI calibration. ● If the HSE clock divided by 128 is used as the RTC clock: – The RTC state is not guaranteed if the VDD supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain). – The DPB bit (Disable backup domain write protection) in the Power controller register must be set to 1 (refer to Section 4.4.1: Power control register (PWR_CR)). Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 4 clock signals can be selected as the MCO clock. ● SYSCLK ● HSI ● HSE ● PLL clock divided by 2 The selection is controlled by the MCO[2:0] bits of the Clock configuration register (RCC_CFGR). 6.3 RCC registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. 82/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.3.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLL RDY r PLLON rw Reserved CSS ON rw HSE BYP rw HSE RDY r HSE ON rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSICAL[7:0] HSITRIM[4:0] Res. HSI RDY HSION r r r r r r r r rw rw rw rw rw r rw Bits 31:26 Reserved, always read as 0. Bit 25 PLLRDY: PLL clock ready flag Set by hardware to indicate that the PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: PLL enable Set and cleared by software to enable PLL. Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. 0: PLL OFF 1: PLL ON Bits 23:20 Reserved, always read as 0. Bit 19 CSSON: Clock security system enable Set and cleared by software to enable clock detector. 0: Clock detector OFF 1: Clock detector ON if external 4-25 MHz oscillator is ready. Bit 18 HSEBYP: External high-speed clock bypass Set and cleared by software in debug for bypassing the oscillator with an external clock. This bit can be written only if the external 4-25 MHz oscillator is disabled. 0: external 4-25 MHz oscillator not bypassed 1: external 4-25 MHz oscillator bypassed with external clock Bit 17 HSERDY: External high-speed clock ready flag Set by hardware to indicate that the external 4-25 MHz oscillator is stable. This bit needs 6 cycles of external 4-25 MHz oscillator clock to fall down after HSEON reset. 0: external 4-25 MHz oscillator not ready 1: external 4-25 MHz oscillator ready Doc ID 13902 Rev 9 83/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 Bit 16 HSEON: External high-speed clock enable Set and cleared by software. Cleared by hardware to stop the external 1-25MHz oscillator when entering in Stop or Standby mode. This bit cannot be reset if the external 4-25 MHz oscillator is used directly or indirectly as the system clock or is selected to become the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration These bits are initialized automatically at startup. Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC. The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ± 1%. The trimming step (Fhsitrim) is around 40 kHz between two consecutive HSICAL steps. Bit 2 Reserved, always read as 0. Bit 1 HSIRDY: Internal high-speed clock ready flag Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles. 0: internal 8 MHz RC oscillator not ready 1: internal 8 MHz RC oscillator ready Bit 0 HSION: Internal high-speed clock enable Set and cleared by software. Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby mode or in case of failure of the external 4-25 MHz oscillator used directly or indirectly as system clock. This bit cannot be reset if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock. 0: internal 8 MHz RC oscillator OFF 1: internal 8 MHz RC oscillator ON 6.3.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0  wait state  2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. 31 30 29 28 27 Reserved 15 14 ADC PRE[1:0] rw rw 13 12 11 PPRE2[2:0] rw rw rw 26 25 24 MCO[2:0] rw rw rw 10 9 8 PPRE1[2:0] rw rw rw 23 Res. 7 rw 22 21 USB PRE rw rw 6 5 HPRE[3:0] rw rw 20 19 18 PLLMUL[3:0] rw rw rw 4 3 2 SWS[1:0] rw r r 17 16 PLL PLL XTPRE SRC rw rw 1 0 SW[1:0] rw rw 84/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) Bits 31:27 Reserved, always read as 0. Bits 26:24 MCO: Microcontroller clock output Set and cleared by software. 0xx: No clock 100: System clock (SYSCLK) selected 101: HSI clock selected 110: HSE clock selected 111: PLL clock divided by 2 selected Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. When the System Clock is selected to output to the MCO pin, make sure that this clock does not exceed 50 MHz (the maximum I/O speed). Bit 22 USBPRE: USB prescaler Set and cleared by software to generate 48 MHz USB clock. This bit must be valid before enabling the USB clock in the RCC_APB1ENR register. This bit can’t be reset if the USB clock is enabled. 0: PLL clock is divided by 1.5 1: PLL clock is not divided Bits 21:18 PLLMUL: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 72 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4 0011: PLL input clock x 5 0100: PLL input clock x 6 0101: PLL input clock x 7 0110: PLL input clock x 8 0111: PLL input clock x 9 1000: PLL input clock x 10 1001: PLL input clock x 11 1010: PLL input clock x 12 1011: PLL input clock x 13 1100: PLL input clock x 14 1101: PLL input clock x 15 1110: PLL input clock x 16 1111: PLL input clock x 16 Bit 17 PLLXTPRE: HSE divider for PLL entry Set and cleared by software to divide HSE before PLL entry. This bit can be written only when PLL is disabled. 0: HSE clock not divided 1: HSE clock divided by 2 Bit 16 PLLSRC: PLL entry clock source Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled. 0: HSI oscillator clock / 2 selected as PLL input clock 1: HSE oscillator clock selected as PLL input clock Doc ID 13902 Rev 9 85/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 Bits 14:14 ADCPRE: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PLCK2 divided by 2 01: PLCK2 divided by 4 10: PLCK2 divided by 6 11: PLCK2 divided by 8 Bits 13:11 PPRE2: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB high-speed clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 10:8 PPRE1: APB low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB low-speed clock (PCLK1). Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain. 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 7:4 HPRE: AHB prescaler Set and cleared by software to control the division factor of the AHB clock. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. Refer to Reading the Flash memory on page 47 section for more details. Bits 3:2 SWS: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: HSI oscillator used as system clock 01: HSE oscillator used as system clock 10: PLL used as system clock 11: not applicable 86/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.3.3 Bits 1:0 SW: System clock switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). 00: HSI selected as system clock 01: HSE selected as system clock 10: PLL selected as system clock 11: not allowed Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 15 14 13 Reserved 28 27 26 25 24 23 Reserved CSSC w 12 11 10 9 8 7 PLL HSE HSI RDYIE RDYIE RDYIE LSE RDYIE LSI RDYIE CSSF rw rw rw rw rw r 22 21 Reserved 6 5 Reserved 20 19 18 17 16 PLL HSE HSI LSE LSI RDYC RDYC RDYC RDYC RDYC w w w w w 4 3 2 1 0 PLL HSE HSI LSE LSI RDYF RDYF RDYF RDYF RDYF r r r r r Bits 31:24 Reserved, always read as 0. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bits 22:21 Reserved, always read as 0. Bit 20 PLLRDYC: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 0: No effect 1: PLLRDYF cleared Bit 19 HSERDYC: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0: No effect 1: HSERDYF cleared Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. 0: No effect 1: HSIRDYF cleared Doc ID 13902 Rev 9 87/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 16 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: LSIRDYF cleared Bits 15:13 Reserved, always read as 0. Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 4-25 MHz oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 8 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the external 4-25 MHz oscillator. Cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bits 6:5 Reserved, always read as 0. Bit 4 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock 88/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.3.4 Bit3 HSERDYF: HSE ready interrupt flag Set by hardware when External Low Speed clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the external 4-25 MHz oscillator 1: Clock ready interrupt caused by the external 4-25 MHz oscillator Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set. Cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the external 32 kHz oscillator 1: Clock ready interrupt caused by the external 32 kHz oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the internal RC 40 kHz oscillator 1: Clock ready interrupt caused by the internal RC 40 kHz oscillator APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 15 14 13 ADC3 USART1 TIM8 RST RST RST rw rw rw 12 SPI1 RST rw 27 11 TIM1 RST rw 26 25 10 9 ADC2 ADC1 RST RST rw rw 24 23 Reserved 8 7 IOPG IOPF RST RST rw rw 22 6 IOPE RST rw 21 5 IOPD RST rw 20 4 IOPC RST rw 19 3 IOPB RST rw 18 2 IOPA RST rw 17 1 Res. Res. 16 0 AFIO RST rw Bits 31:16 Reserved, always read as 0. Bit 15 ADC3RST: ADC3 interface reset Set and cleared by software. 0: No effect 1: Reset ADC3 interface Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Doc ID 13902 Rev 9 89/995 Low-, medium- and high-density reset and clock control (RCC) Bit 13 TIM8RST: TIM8 timer reset Set and cleared by software. 0: No effect 1: Reset TIM8 timer Bit 12 SPI1RST: SPI 1 reset Set and cleared by software. 0: No effect 1: Reset SPI 1 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bit 10 ADC2RST: ADC 2 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 2 interface Bit 9 ADC1RST: ADC 1 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 1 interface Bit 8 IOPGRST: IO port G reset Set and cleared by software. 0: No effect 1: Reset IO port G Bit 7 IOPFRST: IO port F reset Set and cleared by software. 0: No effect 1: Reset IO port F Bit 6 IOPERST: IO port E reset Set and cleared by software. 0: No effect 1: Reset IO port E Bit 5 IOPDRST: IO port D reset Set and cleared by software. 0: No effect 1: Reset I/O port D Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset I/O port B 90/995 Doc ID 13902 Rev 9 RM0008 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.3.5 Bit 2 IOPARST: I/O port A reset Set and cleared by software. 0: No effect 1: Reset I/O port A Bit 1 Reserved, always read as 0. Bit 0 AFIORST: Alternate function I/O reset Set and cleared by software. 0: No effect 1: Reset Alternate Function APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 Reserved 15 SPI3 RST rw 14 SPI2 RST rw 29 28 27 26 DAC RST PWR RST BKP RST Res. rw rw rw 13 12 11 10 Reserved WWD GRST rw 25 CAN RST rw 9 24 Res. 8 23 USB RST rw 7 Reserved 22 I2C2 RST rw 6 21 I2C1 RST rw 5 TIM7 RST rw 20 UART 5 RST rw 4 TIM6 RST rw 19 18 17 UART USART USART 4 3 2 RST RST RST rw rw rw 3 2 1 TIM5 RST TIM4 RST TIM3 RST rw rw rw 16 Res. 0 TIM2 RST rw Bits 31:30 Reserved, always read as 0. Bit 29 DACRST: DAC interface reset Set and cleared by software. 0: No effect 1: Reset DAC interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset power interface Bit 27 BKPRST: Backup interface reset Set and cleared by software. 0: No effect 1: Reset backup interface Bit 26 Reserved, always read as 0. Bit 25 CANRST: CAN reset Set and cleared by software. 0: No effect 1: Reset CAN Bit 24 Reserved, always read as 0. Doc ID 13902 Rev 9 91/995 Low-, medium- and high-density reset and clock control (RCC) Bit 23 USBRST: USB reset Set and cleared by software. 0: No effect 1: Reset USB Bit 22 I2C2RST: I2C 2 reset Set and cleared by software. 0: No effect 1: Reset I2C 2 Bit 21 I2C1RST: I2C 1 reset Set and cleared by software. 0: No effect 1: Reset I2C 1 Bit 20 UART5RST: USART 5 reset Set and cleared by software. 0: No effect 1: Reset USART 5 Bit 19 UART4RST: USART 4 reset Set and cleared by software. 0: No effect 1: Reset USART 4 Bit 18 USART3RST: USART 3 reset Set and cleared by software. 0: No effect 1: Reset USART 3 Bit 17 USART2RST: USART 2 reset Set and cleared by software. 0: No effect 1: Reset USART 2 Bits 16 Reserved, always read as 0. Bit 15 SPI3RST: SPI 3 reset Set and cleared by software. 0: No effect 1: Reset SPI 3 Bit 14 SPI2RST: SPI 2 reset Set and cleared by software. 0: No effect 1: Reset SPI 2 Bits 13:12 Reserved, always read as 0. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:6 Reserved, always read as 0. 92/995 Doc ID 13902 Rev 9 RM0008 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.3.6 Note: Bit 5 TIM7RST: Timer 7 reset Set and cleared by software. 0: No effect 1: Reset timer 7 Bit 4 TIM6RST: Timer 6 reset Set and cleared by software. 0: No effect 1: Reset timer 6 Bit 3 TIM5RST: Timer 5 reset Set and cleared by software. 0: No effect 1: Reset timer 5 Bit 2 TIM4RST: Timer 4 reset Set and cleared by software. 0: No effect 1: Reset timer 4 Bit 1 TIM3RST: Timer 3 reset Set and cleared by software. 0: No effect 1: Reset timer 3 Bit 0 TIM2RST: Timer 2 reset Set and cleared by software. 0: No effect 1: Reset timer 2 AHB peripheral clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SDIO EN rw Res. FSMC EN rw Res. CRCE N rw Res. FLITF EN rw Res. SRAM DMA2 DMA1 EN EN EN rw rw rw Bits 31:11 Reserved, always read as 0. Doc ID 13902 Rev 9 93/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 Bit 10 SDIOEN: SDIO clock enable Set and cleared by software. 0: SDIO clock disabled 1: SDIO clock enabled Bits 9 Reserved, always read as 0. Bit 8 FSMCEN: FSMC clock enable Set and cleared by software. 0: FSMC clock disabled 1: FSMC clock enabled Bit 7 Reserved, always read as 0. Bit 6 CRCEN: CRC clock enable Set and cleared by software. 0: CRC clock disabled 1: CRC clock enabled Bit 5 Reserved, always read as 0. Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode Bit 3 Reserved, always read as 0. Bit 2 SRAMEN: SRAM interface clock enable Set and cleared by software to disable/enable SRAM interface clock during Sleep mode. 0: SRAM interface clock disabled during Sleep mode. 1: SRAM interface clock enabled during Sleep mode Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disabled 1: DMA2 clock enabled Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled 94/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.3.7 Note: APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished. When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 ADC3 USAR TIM8 EN T1EN EN rw rw rw 12 SPI1 EN rw 11 TIM1 EN rw 10 ADC2 EN rw 9 ADC1 EN rw 8 IOPG EN rw 7 IOPF EN rw 6 IOPE EN rw 5 IOPD EN rw 4 IOPC EN rw 3 IOPB EN rw 2 IOPA EN rw 1 Res. 0 AFIO EN rw Bits 31:16 Reserved, always read as 0. Bit 15 ADC3EN: ADC 3 interface clock enable Set and cleared by software. 0: ADC 3 interface clock disabled 1: ADC 3 interface clock enabled Bit 14 USART1EN: USART1 clock enable Set and cleared by software. 0: USART1 clock disabled 1: USART1 clock enabled Bit 13 TIM8EN: TIM8 Timer clock enable Set and cleared by software. 0: TIM8 timer clock disabled 1: TIM8 timer clock enabled Bit 12 SPI1EN: SPI 1 clock enable Set and cleared by software. 0: SPI 1 clock disabled 1: SPI 1 clock enabled Bit 11 TIM1EN: TIM1 Timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled Doc ID 13902 Rev 9 95/995 Low-, medium- and high-density reset and clock control (RCC) Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bit 8 IOPGEN: I/O port G clock enable Set and cleared by software. 0: I/O port G clock disabled 1: I/O port G clock enabled Bit 7 IOPFEN: I/O port F clock enable Set and cleared by software. 0: I/O port F clock disabled 1: I/O port F clock enabled Bit 6 IOPEEN: I/O port E clock enable Set and cleared by software. 0: I/O port E clock disabled 1: I/O port E clock enabled Bit 5 IOPDEN: I/O port D clock enable Set and cleared by software. 0: I/O port D clock disabled 1: I/O port D clock enabled Bit 4 IOPCEN: I/O port C clock enable Set and cleared by software. 0: I/O port C clock disabled 1:I/O port C clock enabled Bit 3 IOPBEN: I/O port B clock enable Set and cleared by software. 0: I/O port B clock disabled 1:I/O port B clock enabled Bit 2 IOPAEN: I/O port A clock enable Set and cleared by software. 0: I/O port A clock disabled 1:I/O port A clock enabled Bit 1 Reserved, always read as 0. Bit 0 AFIOEN: Alternate function I/O clock enable Set and cleared by software. 0: Alternate Function I/O clock disabled 1:Alternate Function I/O clock enabled RM0008 96/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.3.8 Note: APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished. When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 Reserved Res. 15 14 SPI3 SPI2 EN EN rw rw 29 28 DAC PWR EN EN rw rw 13 12 Reserved Res. 27 BKP EN rw 11 WWD GEN rw 26 Res. Res. 10 25 CAN EN rw 9 24 Res. Res. 8 23 USB EN rw 7 Reserved Res. 22 I2C2 EN rw 6 21 20 19 18 17 16 I2C1 UART5E UART4 USART USART EN N EN 3EN 2EN Res. rw rw rw rw rw Res. 5 4 3 2 1 0 TIM7 EN TIM6 EN TIM5 EN TIM4 EN TIM3 EN TIM2 EN rw rw rw rw rw rw Bits 31:30 Reserved, always read as 0. Bit 29 DACEN: DAC interface clock enable Set and cleared by software. 0: DAC interface clock disabled 1: DAC interface clock enable Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enable Bit 27 BKPEN: Backup interface clock enable Set and cleared by software. 0: Backup interface clock disabled 1: Backup interface clock enabled Bit 26 Reserved, always read as 0. Bit 25 CANEN: CAN clock enable Set and cleared by software. 0: CAN clock disabled 1: CAN clock enabled Bit 24 Reserved, always read as 0. Bit 23 USBEN: USB clock enable Set and cleared by software. 0: USB clock disabled 1: USB clock enabled Doc ID 13902 Rev 9 97/995 Low-, medium- and high-density reset and clock control (RCC) Bit 22 I2C2EN: I2C 2 clock enable Set and cleared by software. 0: I2C 2 clock disabled 1: I2C 2 clock enabled Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: USART 5 clock enable Set and cleared by software. 0: USART 5 clock disabled 1: USART 5 clock enabled Bit 19 UART4EN: USART 4 clock enable Set and cleared by software. 0: USART 4 clock disabled 1: USART 4 clock enabled Bit 18 USART3EN: USART 3 clock enable Set and cleared by software. 0: USART 3 clock disabled 1: USART 3 clock enabled Bit 17 USART2EN: USART 2 clock enable Set and cleared by software. 0: USART 2 clock disabled 1: USART 2 clock enabled Bits 16 Reserved, always read as 0. Bit 15 SPI3EN: SPI 3 clock enable Set and cleared by software. 0: SPI 3 clock disabled 1: SPI 3 clock enabled Bit 14 SPI2EN: SPI 2 clock enable Set and cleared by software. 0: SPI 2 clock disabled 1: SPI 2 clock enabled Bits 13:12 Reserved, always read as 0. Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bits 10:6 Reserved, always read as 0. Bit 5 TIM7EN: Timer 7 clock enable Set and cleared by software. 0: Timer 7 clock disabled 1: Timer 7 clock enabled 98/995 Doc ID 13902 Rev 9 RM0008 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.3.9 Note: Bit 4 TIM6EN: Timer 6 clock enable Set and cleared by software. 0: Timer 6 clock disabled 1: Timer 6 clock enabled Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled 1: Timer 5 clock enabled Bit 2 TIM4EN: Timer 4 clock enable Set and cleared by software. 0: Timer 4 clock disabled 1: Timer 4 clock enabled Bit 1 TIM3EN: Timer 3 clock enable Set and cleared by software. 0: Timer 3 clock disabled 1: Timer 3 clock enabled Bit 0 TIM2EN: Timer 2 clock enable Set and cleared by software. 0: Timer 2 clock disabled 1: Timer 2 clock enabled Backup domain control register (RCC_BDCR) Address offset: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0  wait state  3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are writeprotected and the DBP bit in the Power control register (PWR_CR) has to be set before these can be modified. Refer to Section 5 on page 66 for further information. These bits are only reset after a Backup domain Reset (see Section 6.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BDRST rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC EN rw Reserved RTCSEL[1:0] rw rw Reserved LSE BYP rw LSE RDY r LSEON rw Bits 31:17 Reserved, always read as 0. Doc ID 13902 Rev 9 99/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, always read as 0. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset them. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by 128 used as RTC clock Bits 7:3 Reserved, always read as 0. Bit 2 LSEBYP: External low-speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 0: External 32 kHz oscillator not ready 1: External 32 kHz oscillator ready Bit 0 LSEON: External low-speed oscillator enable Set and cleared by software. 0: External 32 kHz oscillator OFF 1: External 32 kHz oscillator ON 100/995 Doc ID 13902 Rev 9 RM0008 Low-, medium- and high-density reset and clock control (RCC) 6.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0  wait state  3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR WWDG IWDG SFT POR PIN RSTF RSTF RSTF RSTF RSTF RSTF rw rw rw rw rw rw Res. RMVF rw Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LSI RDY r LSION rw Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a Low-power management reset occurs. Cleared by writing to the RMVF bit. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Low-power management reset. Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent watchdog reset flag Set by hardware when an independent watchdog reset from VDD domain occurs. Cleared by writing to the RMVF bit. 0: No watchdog reset occurred 1: Watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs. Cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred Doc ID 13902 Rev 9 101/995 Low-, medium- and high-density reset and clock control (RCC) RM0008 Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 Reserved, always read as 0. Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, always read as 0. Bit 1 LSIRDY: Internal low-speed oscillator ready Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 internal RC 40 kHz oscillator clock cycles. 0: Internal RC 40 kHz oscillator not ready 1: Internal RC 40 kHz oscillator ready Bit 0 LSION: Internal low-speed oscillator enable Set and cleared by software. 0: Internal RC 40 kHz oscillator OFF 1: Internal RC 40 kHz oscillator ON 6.3.11 RCC register map The following table gives the RCC register map and the reset values. Table 15. RCC register map and reset values Offset Register 9 HSIRDY 1 Reserved 2 3 4 5 6 7 8 10 11 12 13 14 15 PLLSRC HSEON 16 PLLXTPRE HSERDY 17 HSEBYP 18 CSSON 19 20 21 22 23 PLL ON 24 PLL RDY 25 26 27 28 29 30 31 0x000 RCC_CR Reset value 0x004 RCC_CFGR Reset value Reserved Reserved HSICAL[7:0] HSITRIM[4:0] 00 00000000000010000 11 USBPRE Reserved Reserved MCO [2:0] PLLMUL[3:0] ADC PRE [1:0] PPRE2 [2:0] PPRE1 [2:0] HPRE[3:0] SWS SW [1:0] [1:0] 000 00000000000000000000000 CSSC Reserved PLLRDYC HSERDYC HSIRDYC LSERDYC LSIRDYC Reserved PLLRDYIE HSERDYIE HSIRDYIE LSERDYIE LSIRDYIE CSSF Reserved PLLRDYF HSERDYF HSIRDYF LSERDYF LSIRDYF 0x008 RCC_CIR Reset value Reserved 0 00000 000000 00000 0x00C RCC_APB2RSTR Reset value Reserved 00000000000000 0 0x010 RCC_APB1RSTR Reser ved Reset value 000 0 0000000 00 Reserved 0 000000 ADC3RST USART1RST TIM8RST SPI1RST TIM1RST ADC2RST ADC1RST IOPGRST IOPFRST IOPERST IOPDRST IOPCRST IOPBRST IOPARST Reserved AFIORST DACRST PWRRST BKPRST Reserved CANRST Reserved USBRST I2C2RST I2C1RST UART5RST UART4RST USART3RST USART2RST Reserved SPI3RST SPI2RST Reserved WWDGRST TM7RST TM6RST TM5RST TIM4RST TIM3RST TIM2RST HSION 0 102/995 Doc ID 13902 Rev 9 103/995 Doc ID 13902 Rev 9 Refer to Table 1 on page 41 for the register boundary addresses. 00 0 Reset value 0 0 0 0 1 1 Reserved 0x024 RCC_CSR LPWRSTF WWDGRSTF IWDGRSTF SFTRSTF PORRSTF PINRSTF Reserved RMVF LSIRDY LSION 000 Reserved RTC SEL [1:0] 00 00 RCC_BDCR Reset value Reserved Reserved 0x020 BDRST RTCEN LSEBYP LSERDY LSEON 000000 0 00 0000000 0 000 Reset value Reserved 0x01C RCC_APB1ENR Reserved DACEN PWREN BKPEN Reserved CANEN Reserved USBEN I2C2EN I2C1EN UART5EN UART4EN USART3EN USART2EN Reserved SPI3EN SPI2EN Reserved WWDGEN TIM7EN TIM6EN TIM5EN TIM4EN TIM3EN TIM2EN 0 00000000000000 0x018 RCC_APB2ENR Reset value 0x014 RCC_AHBENR Reset value Reserved ADC3EN USART1EN TIM8EN SPI1EN TIM1EN ADC2EN ADC1EN IOPGEN IOPFEN IOPEEN IOPDEN IOPCEN IOPBEN IOPAEN Reserved AFIOEN 100 1 0 0 0 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 SDIOEN 10 Reserved 9 FSMCEN 8 Reserved 7 CRCEN 6 Reserved 5 FLITFEN 4 Reserved 3 SRAMEN 2 DM2AEN 1 DM1AEN 0 Table 15. RCC register map and reset values (continued) Offset Register Low-, medium- and high-density reset and clock control (RCC) RM0008 Connectivity line devices: reset and clock control (RCC) RM0008 7 Connectivity line devices: reset and clock control (RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to all connectivity line devices, unless otherwise specified. 7.1 7.1.1 Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 4). A system reset is generated when one of the following events occurs: 1. A low level on the NRST pin (external reset) 2. Window watchdog end of count condition (WWDG reset) 3. Independent watchdog end of count condition (IWDG reset) 4. A software reset (SW reset) (see Section : Software reset) 5. Low-power management reset (see Section : Low-power management reset) The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 7.3.10: Control/status register (RCC_CSR)). Software reset The SYSRESETREQ bit in Cortex™-M3 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the Cortex™-M3 technical reference manual for more details. 104/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) 7.1.2 7.1.3 Low-power management reset There are two ways to generate a low-power management reset: 1. Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode. 2. Reset when entering Stop mode: This type of reset is enabled by resetting NRST_STOP bit in User Option Bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode. For further information on the User Option Bytes, refer to the STM32F10xxx Flash programming manual. Power reset A power reset is generated when one of the following events occurs: 1. Power-on/power-down reset (POR/PDR reset) 2. When exiting Standby mode A power reset sets all registers to their reset values except the Backup domain (see Figure 4) These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more details, refer to Table 53: Vector table for other STM32F10xxx devices on page 172. Figure 10. Reset circuit VDD/VDDA External reset NRST RPU Filter System reset Pulse generator (min 20 µs) WWDG reset IWDG reset Power reset Software reset Low-power management reset ai16095 Backup domain reset The backup domain has two specific resets that affect only the backup domain (see Figure 4). A backup domain reset is generated when one of the following events occurs: 1. Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). 2. VDD or VBAT power on, if both supplies have previously been powered off. Doc ID 13902 Rev 9 105/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.2 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): ● HSI oscillator clock ● HSE oscillator clock ● PLL clock The devices have the following two secondary clock sources: ● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode. ● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real- time clock (RTCCLK) Each clock source can be switched on or off independently when it is not used, to optimize power consumption. 106/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Figure 11. Clock tree 40 kHz LSI RC OSC32_IN OSC32_OUT 32.768 kHz LSE OSC to independent watchdog IWDGCLK LSI to RTC LSE RTCCLK /128 RTCSEL[1:0] HSE CSS OSC_IN OSC_OUT XT1 to MCO 3-25 MHz HSE OSC to Flash prog. IF FLITFCLK 8 MHz HSI RC /2 /1,2,3.... ..../15, /16 PREDIV1 PLLSCR PREDIV1SCR HSI PLLMUL x4, x5,... x9, PLLCLK x6.5 SW PLLVCO USB prescaler /2,3 SYSCLK system clock PREDIV2 PLL2MUL x8, x9,... x14, x16, x20 OTGFSCLK 48 MHz to USB OTG FS to I2S2 interface /1,2,3.... ..../15, /16 PLL3MUL PLL2CLK to MCO x8, x9,... x14, x16, x20 PLL3VCO to I2S3 interface PLL3CLK to MCO MCO MCO[3:0] HSE HSI PLLCLK/2 PLL2CLK PLL3CLK/2 PLL3CLK XT1 SYSCLK 72 MHz max. (see note1) AHB prescaler /1,/2 ../512 HCLK to AHB bus, core memory and DMA /2 APB1 prescaler /1, 2, 4, 8, 16 to Cortex System timer FCLK Cortex free running clock 36 MHz max Peripheral clock enable PCLK1 to APB1 peripherals TIM2,3,4,5,6,7 If(APB1 prescaler =1) x1 else x2 Peripheral clock enable to TIM2,3,4,5, 6&7 TIMxCLK Ethernet PHY ETH_MII_TX_CLK ETH_MII_RX_CLK /2, /20 APB2 prescaler /1, 2, 4, 8, 16 72 MHz max Peripheral clock enable PCLK2 to APB2 peripherals MACTXCLK MII_RMII_SEL in AFIO_MAPR MACRXCLK to Ethernet MAC MACRMIICLK TIM1 If(APB2 prescaler =1) x1 else x2 Peripheral clock enable to TIM1 TIMxCLK ADC prescaler ADCCLK /2, 4, 6, 8 14 MHz max to ADC1,2 ai15699c 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz. 2. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet. The advanced clock controller features 3 PLLs to provide a high degree of flexibility to the application in the choice of the external crystal or oscillator to run the core and peripherals at the highest frequency and guarantee the appropriate frequency for the Ethernet and USB OTG FS. A single 25 MHz crystal can clock the entire system and all peripherals including the Ethernet and USB OTG FS peripherals. In order to achieve high-quality audio performance, an audio crystal can be used. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy. For more details about clock configuration for applications requiring Ethernet, USB OTG FS and/or I2S (audio), please refer to "Appendix A Applicative block diagrams" in your connectivity line device datasheet. Doc ID 13902 Rev 9 107/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.2.1 Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz. All peripheral clocks are derived from the system clock (SYSCLK) except: ● The Flash memory programming interface clock which is always the HSI clock ● The USB OTG FS 48MHz clock which is derived from the PLL VCO clock ● The I2S2 and I2S3 clocks which can also be derived from the PLL3 VCO clock (selection by software) ● The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external PHY. For further information on Ethernet configuration, please refer to Section 27.4.4: MII/RMII selection. The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock (HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8. The timer clock frequencies are automatically fixed by hardware. There are two cases: 1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected. FCLK acts as Cortex™-M3 free running clock. For more details refer to the ARM Cortex™M3 Technical Reference Manual. HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: ● HSE external crystal/ceramic resonator ● HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. 108/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Figure 12. HSE/ LSE clock sources Clock source Hardware configuration External clock OSC_OUT External source (HiZ) 7.2.2 OSC_IN OSC_OUT Crystal/ceramic resonators CL1 CL2 Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 50 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 12. External crystal/ceramic resonator (HSE crystal) The 3 to 25 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 12. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). The HSE Crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR). HSI clock The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input. The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator. Doc ID 13902 Rev 9 109/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.2.3 7.2.4 Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control register (RCC_CR). If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the Clock control register (RCC_CR). The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware. The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 112. PLLs The main PLL provides a frequency multiplier starting from one of the following clock sources: ● HSI clock divided by 2 ● HSE or PLL2 clock through a configurable divider Refer to Figure 11 and Clock control register (RCC_CR). PLL2 and PLL3 are clocked by HSE through a specific configurable divider. Refer to Figure 11 and Clock configuration register2 (RCC_CFGR2) The configuration of each PLL (selection of clock source, predivision factor and multiplication factor) must be done before enabling the PLL. Each PLL should be enabled after its input clock becomes stable (ready flag). Once the PLL is enabled, these parameters can not be changed. When changing the entry clock source of the main PLL, the original clock source must be switched off only after the selection of the new clock source (done through bit PLLSRC in the Clock configuration register (RCC_CFGR)). An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt register (RCC_CIR). LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. The LSE crystal is switched on and off using the LSEON bit in Backup domain control register (RCC_BDCR). The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). 110/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) 7.2.5 7.2.6 External source (LSE bypass) In this mode, an external clock source must be provided. It must have a frequency of 32.768 kHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z. See Figure 12. LSI clock The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets. The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR). The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). LSI calibration The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy. This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout. Use the following procedure to calibrate the LSI: 1. Enable TIM5 timer and configure channel4 in input capture mode 2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose. 3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or interrupt. 4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout. System clock (SYSCLK) selection After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as the system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as system clock. Doc ID 13902 Rev 9 111/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.2.7 Note: 7.2.8 7.2.9 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex™-M3 NMI (Non-Maskable Interrupt) exception vector. Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock directly or through PLL2, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If the HSE oscillator clock is the clock entry of the PLL (directly or through PLL2) used as system clock when the failure occurs, the PLL is disabled too. RTC clock The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain. The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: ● If LSE is selected as RTC clock: – The RTC continues to work even if the VDD supply is switched off, provided the VBAT supply is maintained. ● If LSI is selected as Auto-Wakeup unit (AWU) clock: – The AWU state is not guaranteed if the VDD supply is powered off. Refer to Section 7.2.5: LSI clock on page 111 for more details on LSI calibration. ● If the HSE clock divided by 128 is used as RTC clock: – The RTC state is not guaranteed if the VDD supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain). – The DPB bit (Disable backup domain write protection) in the Power controller register must be set to 1 (refer to Section 4.4.1: Power control register (PWR_CR)). Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. 112/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) 7.2.10 Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 8 clock signals can be selected as the MCO clock. ● SYSCLK ● HSI ● HSE ● PLL clock divided by 2 selected ● PLL2 clock selected ● PLL3 clock divided by 2 selected ● XT1 external 3-25 MHz oscillator clock selected (for Ethernet) ● PLL3 clock selected (for Ethernet) The selected clock to output onto MCO must not exceed 50 MHz (the maximum I/O speed). The selection is controlled by the MCO[3:0] bits of the Clock configuration register (RCC_CFGR). 7.3 7.3.1 RCC registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access 31 30 Reserved 15 14 r r 29 28 27 26 25 24 23 PLL3 RDY PLL3 ON PLL2 RDY PLL2 ON PLLRDY PLLON r rw r rw r rw 13 12 11 10 9 8 7 HSICAL[7:0] r r r r r r rw 22 21 20 19 18 17 16 Reserved 6 5 4 HSITRIM[4:0] rw rw rw CSSON HSEBYP HSERDY HSEON rw rw r rw 3 2 1 0 HSIRDY HSION Res. rw r rw Bits 31:30 Reserved, always read as 0. Bit 29 PLL3RDY: PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked. 0: PLL3 unlocked 1: PLL3 locked Doc ID 13902 Rev 9 113/995 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 28 PLL3ON: PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode. 0: PLL3 OFF 1: PLL3 ON Bit 27 PLL2RDY: PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked. 0: PLL2 unlocked 1: PLL2 locked Bit 26 PLL2ON: PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode. This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). 0: PLL2 OFF 1: PLL2 ON Bit 25 PLLRDY: PLL clock ready flag Set by hardware to indicate that the PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: PLL enable Set and cleared by software to enable PLL. Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. Software must disable the USB OTG FS clock before clearing this bit. 0: PLL OFF 1: PLL ON Bits 23:20 Reserved, always read as 0. Bit 19 CSSON: Clock security system enable Set and cleared by software to enable clock detector. 0: Clock detector OFF 1: Clock detector ON if external 3-25 MHz oscillator is ready. Bit 18 HSEBYP: External high-speed clock bypass Set and cleared by software in debug for bypassing the oscillator with an external clock. This bit can be written only if the external 3-25 MHz oscillator is disabled. 0: external 3-25 MHz oscillator not bypassed 1: external 3-25 MHz oscillator bypassed with external clock Bit 17 HSERDY: External high-speed clock ready flag Set by hardware to indicate that the external 3-25 MHz oscillator is stable. This bit needs 6 cycles of external 3-25 MHz oscillator clock to fall down after HSEON reset. 0: external 3-25 MHz oscillator not ready 1: external 3-25 MHz oscillator ready 114/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) 7.3.2 Bit 16 HSEON: External high-speed clock enable Set and cleared by software. Cleared by hardware to stop the external 3-25MHz oscillator when entering Stop or Standby mode. This bit can not be reset if the external 3-25 MHz oscillator is used directly or indirectly as system clock or is selected to become the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration These bits are initialized automatically at startup. Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC. The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ± 1%. The trimming step (Fhsitrim) is around 40 kHz between two consecutive HSICAL steps. Bit 2 Reserved, always read as 0. Bit 1 HSIRDY: Internal high-speed clock ready flag Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles. 0: Internal 8 MHz RC oscillator not ready 1: Internal 8 MHz RC oscillator ready Bit 0 HSION: Internal high-speed clock enable Set and cleared by software. Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby mode or in case of failure of the external 3-25 MHz oscillator used directly or indirectly as system clock. This bit can not be cleared if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock. 0: Internal 8 MHz RC oscillator OFF 1: Internal 8 MHz RC oscillator ON Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0  wait state  2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during a clock source switch. 31 30 29 28 27 Reserved rw 15 14 13 12 11 ADC PRE[1:0] PPRE2[2:0] rw rw rw rw rw 26 25 24 MCO[3:0] rw rw rw 10 9 8 PPRE1[2:0] rw rw rw 23 Res. 7 rw 22 21 OTGF SPRE rw rw 6 5 HPRE[3:0] rw rw 20 19 18 PLLMUL[3:0] rw rw rw 4 3 2 SWS[1:0] rw r r 17 16 PLL PLL XTPRE SRC rw rw 1 0 SW[1:0] rw rw Bits 31:27 Reserved, always read as 0. Doc ID 13902 Rev 9 115/995 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 26:24 MCO[3:0]: Microcontroller clock output Set and cleared by software. 00xx: No clock 0100: System clock (SYSCLK) selected 0101: HSI clock selected 0110: HSE clock selected 0111: PLL clock divided by 2 selected 1000: PLL2 clock selected 1001: PLL3 clock divided by 2 selected 1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet) 1011: PLL3 clock selected (for Ethernet) Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. The selected clock to output onto the MCO pin must not exceed 50 MHz (the maximum I/O speed). Bit 22 OTGFSPRE: USB OTG FS prescaler Set and cleared by software to generate the 48 MHz USB OTG FS clock. This bit must be valid before enabling the OTG FS clock in the RCC_APB1ENR register. This bit can not be cleared if the OTG FS clock is enabled. 0: PLL VCO clock is divided by 3 1: PLL VCO clock is divided by 2 Bits 21:18 PLLMUL[3:0]: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. They can be written only when PLL is disabled. 000x: Reserved 0010: PLL input clock x 4 0011: PLL input clock x 5 0100: PLL input clock x 6 0101: PLL input clock x 7 0110: PLL input clock x 8 0111: PLL input clock x 9 10xx: Reserved 1100: Reserved 1101: PLL input clock x 6.5 111x: Reserved Caution: The PLL output frequency must not exceed 72 MHz. Bit 17 PLLXTPRE: LSB of division factor PREDIV1 Set and cleared by software to select the least significant bit of the PREDIV1 division factor. It is the same bit as bit(0) in the RCC_CFGR2 register, so modifying bit(0) in the RCC_CFGR2 register changes this bit accordingly. If bits[3:1] in register RCC_CFGR2 are not set, this bit controls if PREDIV1 divides its input clock by 2 (PLLXTPRE=1) or not (PLLXTPRE=0). This bit can be written only when PLL is disabled. Bit 16 PLLSRC: PLL entry clock source Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled. 0: HSI oscillator clock / 2 selected as PLL input clock 1: Clock from PREDIV1 selected as PLL input clock Note: When changing the main PLL’s entry clock source, the original clock source must be switched off only after the selection of the new clock source. 116/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Bits 14:14 ADCPRE[1:0]: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PLCK2 divided by 2 01: PLCK2 divided by 4 10: PLCK2 divided by 6 11: PLCK2 divided by 8 Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB High speed clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 10:8 PPRE1[2:0]: APB Low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB Low speed clock (PCLK1). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Caution: Software must configure these bits ensure that the frequency in this domain does not exceed 36 MHz. Bits 7:4 HPRE[3:0]: AHB prescaler Set and cleared by software to control AHB clock division factor. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. Refer to the section Reading the Flash memory on page 47 for more details. Bits 3:2 SWS[1:0]: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: HSI oscillator used as system clock 01: HSE oscillator used as system clock 10: PLL used as system clock 11: Not applicable Doc ID 13902 Rev 9 117/995 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 1:0 SW[1:0]: System clock Switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). 00: HSI selected as system clock 01: HSE selected as system clock 10: PLL selected as system clock 11: Not allowed 7.3.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CSSC PLL3 RDYC PLL2 RDYC PLL RDYC HSE RDYC HSI RDYC LSE RDYC LSI RDYC w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PLL3 PLL2 PLL HSE HSI LSE RDYIE RDYIE RDYIE RDYIE RDYIE RDYIE LSI RDYIE CSSF PLL3 RDYF PLL2 RDYF PLL RDYF HSE RDYF HSI RDYF rw rw rw rw rw rw rw r r r r r r LSE RDYF r LSI RDYF r Bits 31:24 Reserved, always read as 0. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bit 22 PLL3RDYC: PLL3 Ready Interrupt Clear This bit is set by software to clear the PLL3RDYF flag. 0: No effect 1: Clear PLL3RDYF flag Bit 21 PLL2RDYC: PLL2 Ready Interrupt Clear This bit is set by software to clear the PLL2RDYF flag. 0: No effect 1: Clear PLL2RDYF flag Bit 20 PLLRDYC: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 0: No effect 1: Clear PLLRDYF flag Bit 19 HSERDYC: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0: No effect 1: Clear HSERDYF flag 118/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set by software to clear the HSIRDYF flag. 0: No effect 1: Clear HSIRDYF flag Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: Clear LSERDYF flag Bit 16 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: Clear LSIRDYF flag Bit 15 Reserved, always read as 0. Bit 14 PLL3RDYIE: PLL3 Ready Interrupt Enable Set and cleared by software to enable/disable interrupt caused by PLL3 lock. 0: PLL3 lock interrupt disabled 1: PLL3 lock interrupt enabled Bit 13 PLL2RDYIE: PLL2 Ready Interrupt Enable Set and cleared by software to enable/disable interrupt caused by PLL2 lock. 0: PLL2 lock interrupt disabled 1: PLL2 lock interrupt enabled Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 3-25 MHz oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 8 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled Doc ID 13902 Rev 9 119/995 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the external 3-25 MHz oscillator. It is cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bit 6 PLL3RDYF: PLL3 Ready Interrupt flag Set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software setting the PLL3RDYC bit. 0: No clock ready interrupt caused by PLL3 lock 1: Clock ready interrupt caused by PLL3 lock Bit 5 PLL2RDYF: PLL2 Ready Interrupt flag Set by hardware when the PLL2 locks and PLL2RDYDIE is set. It is cleared by software setting the PLL2RDYC bit. 0: No clock ready interrupt caused by PLL2 lock 1: Clock ready interrupt caused by PLL2 lock Bit 4 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit3 HSERDYF: HSE ready interrupt flag Set by hardware when External Low Speed clock becomes stable and HSERDYIE is set. It is cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the external 3-25 MHz oscillator 1: Clock ready interrupt caused by the external 3-25 MHz oscillator Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is set. It is cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYIE is set. It is cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the external 32 kHz oscillator 1: Clock ready interrupt caused by the external 32 kHz oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when Internal Low Speed clock becomes stable and LSIRDYIE is set. It is cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the internal RC 40 kHz oscillator 1: Clock ready interrupt caused by the internal RC 40 kHz oscillator 120/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) 7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 15 14 13 Res. USART1 RST rw Res. 12 SPI1 RST rw 11 TIM1 RST rw 10 ADC2 RST rw 9 ADC1 RST rw 24 23 Reserved 8 7 Reserved 22 21 20 19 18 17 16 6 IOPE RST rw 5 IOPD RST rw 4 IOPC RST rw 3 IOPB RST rw 2 IOPA RST rw 1 Res. 0 AFIO RST rw Bits 31:15 Reserved, always read as 0. Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 Reserved, always read as 0. Bit 12 SPI1RST: SPI 1 reset Set and cleared by software. 0: No effect 1: Reset SPI 1 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bit 10 ADC2RST: ADC 2 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 2 interface Bit 9 ADC1RST: ADC 1 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 1 interface Bits 8:7 Reserved, always read as 0. Bit 6 IOPERST: I/O port E reset Set and cleared by software. 0: No effect 1: Reset I:O port E Bit 5 IOPDRST: I/O port D reset Set and cleared by software. 0: No effect 1: Reset I/O port D Doc ID 13902 Rev 9 121/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.3.5 Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset I/O port B Bit 2 IOPARST: I/O port A reset Set and cleared by software. 0: No effect 1: Reset I/O port A Bit 1 Reserved, always read as 0. Bit 0 AFIORST: Alternate function I/O reset Set and cleared by software. 0: No effect 1: Reset Alternate Function APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 Reserved 15 SPI3 RST rw 14 SPI2 RST rw DAC RST PWR RST BKP CAN2 CAN1 RST RST RST Reserved rw rw rw rw rw 13 12 11 10 9 8 7 Reserved WWD GRST rw Reserved 22 I2C2 RST rw 6 21 I2C1 RST rw 5 TIM7 RST rw 20 UART 5 RST rw 4 TIM6 RST rw 19 18 17 UART USART USART 4 3 2 RST RST RST rw rw rw 3 2 1 TIM5 RST TIM4 RST TIM3 RST rw rw rw 16 Res. 0 TIM2 RST rw Bits 31:30 Reserved, always read as 0. Bit 29 DACRST: DAC interface reset Set and cleared by software. 0: No effect 1: Reset DAC interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset power interface 122/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 27 BKPRST: Backup interface reset Set and cleared by software. 0: No effect 1: Reset backup interface Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: No effect 1: Reset CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software. 0: No effect 1: Reset CAN1 Bits 24:23 Reserved, always read as 0. Bit 22 I2C2RST: I2C 2 reset Set and cleared by software. 0: No effect 1: Reset I2C 2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C 1 Bit 20 UART5RST: USART 5 reset Set and cleared by software. 0: No effect 1: Reset USART 5 Bit 19 UART4RST: USART 4 reset Set and cleared by software. 0: No effect 1: Reset USART 4 Bit 18 USART3RST: USART 3 reset Set and cleared by software. 0: No effect 1: Reset USART 3 Bit 17 USART2RST: USART 2 reset Set and cleared by software. 0: No effect 1: Reset USART 2 Bits 16 Reserved, always read as 0. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI 3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 Doc ID 13902 Rev 9 123/995 Connectivity line devices: reset and clock control (RCC) Bits 13:12 Reserved, always read as 0. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:6 Reserved, always read as 0. Bit 5 TIM7RST: Timer 7 reset Set and cleared by software. 0: No effect 1: Reset timer 7 Bit 4 TIM6RST: Timer 6 reset Set and cleared by software. 0: No effect 1: Reset timer 6 Bit 3 TIM5RST: Timer 5 reset Set and cleared by software. 0: No effect 1: Reset timer 5 Bit 2 TIM4RST: Timer 4 reset Set and cleared by software. 0: No effect 1: Reset timer 4 Bit 1 TIM3RST: Timer 3 reset Set and cleared by software. 0: No effect 1: Reset timer 3 Bit 0 TIM2RST: Timer 2 reset Set and cleared by software. 0: No effect 1: Reset timer 2 RM0008 124/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) 7.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access 31 30 29 28 27 15 14 13 12 11 ETHM ACTX EN ETHM ACEN Res. OTGF SEN rw rw rw 26 25 24 23 22 21 20 19 18 17 16 Reserved ETH MACR XEN rw 10 9 8 7 6 5 4 3 2 1 0 Reserved CRCEN Res. FLITFE N Res. SRAM DMA2 EN EN DMA1 EN rw rw rw rw rw Bits 31:17 Reserved, always read as 0. Bit 16 ETHMACRXEN: Ethernet MAC RX clock enable Set and cleared by software. 0: Ethernet MAC RX clock disabled 1: Ethernet MAC RX clock enabled Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled. Bit 15 ETHMACTXEN: Ethernet MAC TX clock enable Set and cleared by software. 0: Ethernet MAC TX clock disabled 1: Ethernet MAC TX clock enabled Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled. Bit 14 ETHMACEN: Ethernet MAC clock enable Set and cleared by software. Selection of PHY interface (MII/RMII) must be done before enabling the MAC clock. 0: Ethernet MAC clock disabled 1: Ethernet MAC clock enabled Bit 13 Reserved, always read as 0. Bit 12 OTGFSEN: USB OTG FS clock enable Set and cleared by software. 0: USB OTG FS clock disabled 1: USB OTG FS clock enabled Bits 11:7 Reserved, always read as 0. Bit 6 CRCEN: CRC clock enable Set and cleared by software. 0: CRC clock disabled 1: CRC clock enabled Bit 5 Reserved, always read as 0. Doc ID 13902 Rev 9 125/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.3.7 Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode Bit 3 Reserved, always read as 0. Bit 2 SRAMEN: SRAM interface clock enable Set and cleared by software to disable/enable SRAM interface clock during Sleep mode. 0: SRAM interface clock disabled during Sleep mode 1: SRAM interface clock enabled during Sleep mode Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disabled 1: DMA2 clock enabled Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished. 31 30 29 28 27 26 25 15 14 13 Res. USAR T1EN rw Res. 12 SPI1 EN rw 11 TIM1 EN rw 10 ADC2 EN rw 9 ADC1 EN rw 24 23 Reserved 8 7 Reserved 22 21 20 19 18 17 16 6 IOPE EN rw 5 IOPD EN rw 4 IOPC EN rw 3 IOPB EN rw 2 IOPA EN rw 1 Res. 0 AFIO EN rw Bits 31:15 Reserved, always read as 0. Bit 14 USART1EN: USART1 clock enable Set and cleared by software. 0: USART1 clock disabled 1: USART1 clock enabled Bit 13 Reserved, always read as 0. Bit 12 SPI1EN: SPI 1 clock enable Set and cleared by software. 0: SPI 1 clock disabled 1: SPI 1 clock enabled 126/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 11 TIM1EN: TIM1 Timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bits 8:7 Reserved, always read as 0. Bit 6 IOPEEN: I/O port E clock enable Set and cleared by software. 0: I/O port E clock disabled 1: I/O port E clock enabled Bit 5 IOPDEN: I/O port D clock enable Set and cleared by software. 0: I/O port D clock disabled 1: I/O port D clock enabled Bit 4 IOPCEN: I/O port C clock enable Set and cleared by software. 0: I/O port C clock disabled 1:I/O port C clock enabled Bit 3 IOPBEN: I/O port B clock enable Set and cleared by software. 0: I/O port B clock disabled 1:I/O port B clock enabled Bit 2 IOPAEN: I/O port A clock enable Set and cleared by software. 0: I/O port A clock disabled 1:I/O port A clock enabled Bit 1 Reserved, always read as 0. Bit 0 AFIOEN: Alternate function I/O clock enable Set and cleared by software. 0: Alternate Function I/O clock disabled 1:Alternate Function I/O clock enabled Doc ID 13902 Rev 9 127/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished. 31 30 Reserved 15 SPI3 EN rw 14 SPI2 EN rw 29 28 DAC PWR EN EN rw rw 13 12 Reserved 27 26 25 24 23 BKP EN rw CAN2 CAN1 EN EN rw rw Reserved 11 10 9 8 7 WWD GEN rw Reserved 22 I2C2 EN rw 6 21 20 19 18 17 I2C1 UART5E UART4 USART USART EN N EN 3EN 2EN rw rw rw rw rw 5 4 3 2 1 TIM7 EN TIM6 EN TIM5 EN TIM4 EN TIM3 EN rw rw rw rw rw 16 Res. 0 TIM2 EN rw Bits 31:30 Reserved, always read as 0. Bit 29 DACEN: DAC interface clock enable Set and cleared by software. 0: DAC interface clock disabled 1: DAC interface clock enable Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enable Bit 27 BKPEN: Backup interface clock enable Set and cleared by software. 0: Backup interface clock disabled 1: Backup interface clock enabled Bit 26 CAN2EN: CAN2 clock enable Set and cleared by software. 0: CAN2 clock disabled 1: CAN2 clock enabled Bit 25 CAN1EN: CAN1 clock enable Set and cleared by software. 0: CAN1 clock disabled 1: CAN1 clock enabled Bits 24:23 Reserved, always read as 0. Bit 22 I2C2EN: I2C 2 clock enable Set and cleared by software. 0: I2C 2 clock disabled 1: I2C 2 clock enabled 128/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: USART 5 clock enable Set and cleared by software. 0: USART 5 clock disabled 1: USART 5 clock enabled Bit 19 UART4EN: USART 4 clock enable Set and cleared by software. 0: USART 4 clock disabled 1: USART 4 clock enabled Bit 18 USART3EN: USART 3 clock enable Set and cleared by software. 0: USART 3 clock disabled 1: USART 3 clock enabled Bit 17 USART2EN: USART 2 clock enable Set and cleared by software. 0: USART 2 clock disabled 1: USART 2 clock enabled Bits 16 Reserved, always read as 0. Bit 15 SPI3EN: SPI 3 clock enable Set and cleared by software. 0: SPI 3 clock disabled 1: SPI 3 clock enabled Bit 14 SPI2EN: SPI 2 clock enable Set and cleared by software. 0: SPI 2 clock disabled 1: SPI 2 clock enabled Bits 13:12 Reserved, always read as 0. Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bits 10:6 Reserved, always read as 0. Bit 5 TIM7EN: Timer 7 clock enable Set and cleared by software. 0: Timer 7 clock disabled 1: Timer 7 clock enabled Bit 4 TIM6EN: Timer 6 clock enable Set and cleared by software. 0: Timer 6 clock disabled 1: Timer 6 clock enabled Doc ID 13902 Rev 9 129/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.3.9 Note: Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled 1: Timer 5 clock enabled Bit 2 TIM4EN: Timer 4 clock enable Set and cleared by software. 0: Timer 4 clock disabled 1: Timer 4 clock enabled Bit 1 TIM3EN: Timer 3 clock enable Set and cleared by software. 0: Timer 3 clock disabled 1: Timer 3 clock enabled Bit 0 TIM2EN: Timer 2 clock enable Set and cleared by software. 0: Timer 2 clock disabled 1: Timer 2 clock enabled Backup domain control register (RCC_BDCR) Address: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0  wait state  3, word, half-word and byte access Wait states are inserted in the case of successive accesses to this register. LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are writeprotected and the DBP bit in the Power control register (PWR_CR) has to be set before these can be modified. Refer to Section 5 on page 66 for further information. These bits are only reset after a Backup domain Reset (see Section 7.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BDRST rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC EN rw Reserved RTCSEL[1:0] rw rw Reserved LSE BYP rw LSE RDY r LSEON rw Bits 31:17 Reserved, always read as 0. Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain 130/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, always read as 0. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset the RTCSEL[1:0] bits. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by 128 used as RTC clock Bits 7:3 Reserved, always read as 0. Bit 2 LSEBYP: External Low Speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External Low Speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low speed oscillator clock cycles 0: External 32 kHz oscillator not ready 1: External 32 kHz oscillator ready Bit 0 LSEON: External Low Speed oscillator enable Set and cleared by software. 0: External 32 kHz oscillator OFF 1: External 32 kHz oscillator ON Doc ID 13902 Rev 9 131/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0  wait state  3, word, half-word and byte access Wait states are inserted in the case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR WWDG IWDG SFT POR PIN RSTF RSTF RSTF RSTF RSTF RSTF rw rw rw rw rw rw Res. RMVF rw Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LSI RDY r LSION rw Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a Low-power management reset occurs. It is cleared by writing to the RMVF bit. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Section : Low-power management reset. Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. It is cleared by writing to the RMVF bit. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent watchdog reset flag Set by hardware when an independent watchdog reset from VDD domain occurs. It is cleared by writing to the RMVF bit. 0: No watchdog reset occurred 1: Watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. It is cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. It is cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 Reserved, always read as 0. 132/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, always read as 0. Bit 1 LSIRDY: Internal low speed oscillator ready Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 internal 40 kHz RC oscillator clock cycles. 0: Internal RC 40 kHz oscillator not ready 1: Internal RC 40 kHz oscillator ready Bit 0 LSION: Internal low speed oscillator enable Set and cleared by software. 0: Internal RC 40 kHz oscillator OFF 1: Internal RC 40 kHz oscillator ON 7.3.11 AHB peripheral clock reset register (RCC_AHBRSTR) Address offset: 0x28 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. ETHMAC RST rw Res. OTGFS RST rw Reserved Bits 31:15 Reserved, always read as 0. Bit 14 ETHMACRST Ethernet MAC reset Set and cleared by software. 0: No effect 1: Reset ETHERNET MAC Bit 13 Reserved, always read as 0. Bit 12 OTGFSRST USB OTG FS reset Set and cleared by software. 0: No effect 1: Reset USB OTG FS Bits 11:0 Reserved, always read as 0. Doc ID 13902 Rev 9 133/995 Connectivity line devices: reset and clock control (RCC) RM0008 7.3.12 Clock configuration register2 (RCC_CFGR2) Address offset: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 15 14 13 12 PLL3MUL[3:0] rw rw rw rw 27 26 25 24 Reserved 11 10 9 8 PLL2MUL[3:0] rw rw rw rw 23 22 21 20 7 6 5 4 PREDIV2[3:0] rw rw rw rw 19 18 17 16 I2S3S I2S2S PREDI RC RC V1SRC rw rw rw 3 2 1 0 PREDIV1[3:0] rw rw rw rw 7 Bits 31:19 Reserved, always read as 0. Bit 18 I2S3SRC: I2S3 clock source Set and cleared by software to select I2S3 clock source. This bit must be valid before enabling I2S3 clock. 0: System clock (SYSCLK) selected as I2S3 clock entry 1: PLL3 VCO clock selected as I2S3 clock entry Bit 17 I2S2SRC: I2S2 clock source Set and cleared by software to select I2S2 clock source. This bit must be valid before enabling I2S2 clock. 0: System clock (SYSCLK) selected as I2S2 clock entry 1: PLL3 VCO clock selected as I2S2 clock entry Bit 16 PREDIV1SRC: PREDIV1 entry clock source Set and cleared by software to select PREDIV1 clock source. This bit can be written only when PLL is disabled. 0: HSE oscillator clock selected as PREDIV1 clock entry 1: PLL2 selected as PREDIV1 clock entry Bits 15:12 PLL3MUL[3:0]: PLL3 Multiplication Factor Set and cleared by software to control PLL3 multiplication factor. These bits can be written only when PLL3 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL3 clock entry x 8 0111: PLL3 clock entry x 9 1000: PLL3 clock entry x 10 1001: PLL3 clock entry x 11 1010: PLL3 clock entry x 12 1011: PLL3 clock entry x 13 1100: PLL3 clock entry x 14 1101: Reserved 1110: PLL3 clock entry x 16 1111: PLL3 clock entry x 20 134/995 Doc ID 13902 Rev 9 RM0008 Connectivity line devices: reset and clock control (RCC) Bits 11:8 PLL2MUL[3:0]: PLL2 Multiplication Factor Set and cleared by software to control PLL2 multiplication factor. These bits can be written only when PLL2 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL2 clock entry x 8 0111: PLL2 clock entry x 9 1000: PLL2 clock entry x 10 1001: PLL2 clock entry x 11 1010: PLL2 clock entry x 12 1011: PLL2 clock entry x 13 1100: PLL2 clock entry x 14 1101: Reserved 1110: PLL2 clock entry x 16 1111: PLL2 clock entry x 20 Bits 7:4 PREDIV2[3:0]: PREDIV2 division factor Set and cleared by software to select PREDIV2 division factor. These bits can be written only when both PLL2 and PLL3 are disabled. 0000: PREDIV2 input clock not divided 0001: PREDIV2 input clock divided by 2 0010: PREDIV2 input clock divided by 3 0011: PREDIV2 input clock divided by 4 0100: PREDIV2 input clock divided by 5 0101: PREDIV2 input clock divided by 6 0110: PREDIV2 input clock divided by 7 0111: PREDIV2 input clock divided by 8 1000: PREDIV2 input clock divided by 9 1001: PREDIV2 input clock divided by 10 1010: PREDIV2 input clock divided by 11 1011: PREDIV2 input clock divided by 12 1100: PREDIV2 input clock divided by 13 1101: PREDIV2 input clock divided by 14 1110: PREDIV2 input clock divided by 15 1111: PREDIV2 input clock divided by 16 Doc ID 13902 Rev 9 135/995 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor Set and cleared by software to select PREDIV1 division factor. These bits can be written only when PLL is disabled. Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the RCC_CFGR register changes Bit(0) accordingly. 0000: PREDIV1 input clock not divided 0001: PREDIV1 input clock divided by 2 0010: PREDIV1 input clock divided by 3 0011: PREDIV1 input clock divided by 4 0100: PREDIV1 input clock divided by 5 0101: PREDIV1 input clock divided by 6 0110: PREDIV1 input clock divided by 7 0111: PREDIV1 input clock divided by 8 1000: PREDIV1 input clock divided by 9 1001: PREDIV1 input clock divided by 10 1010: PREDIV1 input clock divided by 11 1011: PREDIV1 input clock divided by 12 1100: PREDIV1 input clock divided by 13 1101: PREDIV1 input clock divided by 14 1110: PREDIV1 input clock divided by 15 1111: PREDIV1 input clock divided by 16 7.3.13 RCC register map The following table gives the RCC register map and the reset values. Table 16. RCC register map and reset values Offset Register 0x000 0x004 RCC_CR Reset value Reser ved 000000 Reserved HSICAL[7:0] HSITRIM[4:0] 0000xxxxxxxx10000 11 Reserved OTGFSPRE PLLXTPRE PLLSRC RCC_CFGR Reserved MCO [3:0] PLLMUL [3:0] ADC PRE [1:0] PPRE2 [2:0] PPRE1 [2:0] HPRE[3:0] SWS SW [1:0] [1:0] Reset value 0000 00000000000000000000000 CSSC PLL3RDYC PLL2RDYC PLLRDYC HSERDYC HSIRDYC LSERDYC LSIRDYC Reserved PLL3RDYIE PLL2RDYIE PLLRDYIE HSERDYIE HSIRDYIE LSERDYIE LSIRDYIE CSSF PLL3RDYF PLL2RDYF PLLRDYF HSERDYF HSIRDYF LSERDYF LSIRDYF 0x008 RCC_CIR Reset value Reserved 00000000 000000000000000 0x00C RCC_APB2RSTR Reset value Reserved 0 0000 00000 0 0x010 RCC_APB1RSTR Reser ved Reset value 00000 000000 00 Reserved 0 000000 Reserved USART1RST Reserved SPI1RST TIM1RST ADC2RST ADC1RST Reserved IOPERST IOPDRST IOPCRST IOPBRST IOPARST Reserved AFIORST DACRST PWRRST BKPRST CAN2RST CAN1RST Reserved I2C2RST I2C1RST UART5RST UART4RST USART3RST USART2RST Reserved SPI3RST SPI2RST Reserved WWDGRST TM7RST TM6RST TM5RST TIM4RST TIM3RST TIM2RST 31 30 PLL3 RDY 29 PLL3 ON 28 PLL2 RDY 27 PLL2 ON 26 PLL RDY 25 PLLON 24 23 22 21 20 CSSON 19 HSEBYP 18 HSERDY 17 HSEON 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Reserved 2 HSIRDY 1 HSION 0 136/995 Doc ID 13902 Rev 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ETHMACRXEN 16 ETHMACTXEN 15 ETHMACEN 14 Reserved 13 OTGFSEN 12 11 10 9 8 7 CRCEN 6 Reserved 5 FLITFEN 4 Reserved 3 SRAMEN 2 DM2AEN 1 DM1AEN 0 RM0008 Connectivity line devices: reset and clock control (RCC) Table 16. RCC register map and reset values (continued) Offset Register Reserved USART1EN Reserved SPI1EN TIM1EN ADC2EN ADC1EN Reserved IOPEEN IOPDEN IOPCEN IOPBEN IOPAEN Reserved AFIOEN 0x014 RCC_AHBENR Reserved Reserved Reset value 000 0 0 1 100 0x018 RCC_APB2ENR Reset value Reserved 0 0000 00000 0 0x01C RCC_APB1ENR Reser ved Reset value 00000 000000 00 0 0x020 RCC_BDCR Reset value Reserved 00 Reserved Reserved RTC SEL [1:0] 00 000000 Reserved 000 DACEN PWREN BKPEN CAN2EN CAN1EN Reserved I2C2EN I2C1EN UART5EN UART4EN USART3EN USART2EN Reserved SPI3EN SPI2EN Reserved WWDGEN TIM7EN TIM6EN TIM5EN TIM4EN TIM3EN TIM2EN BDRST RTCEN LSEBYP LSERDY LSEON LPWRSTF WWDGRSTF IWDGRSTF SFTRSTF PORRSTF PINRSTF Reserved RMVF LSIRDY LSION 0x024 RCC_CSR Reset value 0 0 0 0 1 1 0 Reserved 00 ETHMACRST Reserved OTGFSRST 0x028 RCC_AHBSTR Reserved Reserved Reset value 0 0 I2S3SRC I2S2SRC PREDIV1SRC 0x02C RCC_CFGR2 Reserved PLL3MUL [3:0] PLL2MUL [3:0] PREDIV2[3:0] PREDIV1[3:0] Reset value 0000000000000000000 Refer to Table 1 on page 41 for the register boundary addresses. Doc ID 13902 Rev 9 137/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 8 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to the whole STM32F10xxx family, unless otherwise specified. 8.1 GPIO functional description Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register (GPIOx_LCKR). Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes: ● Input floating ● Input pull-up ● Input-pull-down ● Analog Input ● Output open-drain ● Output push-pull ● Alternate function push-pull ● Alternate function open-drain Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words (half-word or byte accesses are not allowed). The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the modify access. Figure 13 shows the basic structure of an I/O Port bit. 138/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 13. Basic structure of a standard I/O port bit Bit set/reset registers Output data register Input data register To on-chip peripheral Read Write Analog Input Alternate Function Input on/off TTL Schmitt trigger Input driver Output driver Read/write From on-chip peripheral Alternate Function Output Output control VDD on/off on/off VSS VDD P-MOS N-MOS VSS Push-pull, open-drain or disabled Figure 14. Basic structure of a five-volt tolerant I/O port bit VDD Protection diode I/O pin Protection diode VSS ai14781 Bit set/reset registers Output data register Input data register To on-chip peripheral Read Write Analog Input Alternate Function Input on/off TTL Schmitt trigger Input driver Output driver Read/write From on-chip peripheral Alternate Function Output Output control VDD on/off on/off VSS VDD P-MOS N-MOS VSS Push-pull, open-drain or disabled 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. VDD_FT(1) I/O pin Protection diode VSS ai14782 Doc ID 13902 Rev 9 139/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 17. Port bit configuration table Configuration mode CNF1 CNF0 General purpose output Alternate Function output Input Push-pull Open-drain Push-pull Open-drain Analog input Input floating Input pull-down Input pull-up 0 0 1 0 1 1 0 0 1 1 0 MODE1 MODE0 01 10 11 see Table 18 00 PxODR register 0 or 1 0 or 1 don’t care don’t care don’t care don’t care 0 1 Table 18. Output MODE bits MODE[1:0] 00 01 10 11 Meaning Reserved Max. output speed 10 MHz Max. output speed 2 MHz Max. output speed 50 MHz 8.1.1 8.1.2 General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and the I/O ports are configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b). The JTAG pins are in input PU/PD after reset: PA15: JTDI in PU PA14: JTCK in PD PA13: JTMS in PU PB4: JNTRST in PU When configured as output, the value written to the Output Data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in Push-Pull mode or Open-Drain mode (only the N-MOS is activated when outputting 0). The Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every APB2 clock cycle. All GPIO pins have an internal weak pull-up and weak pull-down which can be activated or not when configured as input. Atomic bit set or reset There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify only one or several bits in a single atomic APB2 write access. This is achieved by programming to ‘1’ the Bit Set/Reset Register (GPIOx_BSRR, 140/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.1.3 8.1.4 Note: 8.1.5 8.1.6 or for reset only GPIOx_BRR) to select the bits you want to modify. The unselected bits will not be modified. External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode. For more information on external interrupts, refer to: ● Section 9.2: External interrupt/event controller (EXTI) on page 174 and ● Section 9.2.3: Wakeup event management on page 175. Alternate functions (AF) It is necessary to program the Port Bit Configuration Register before using a default alternate function. ● For alternate function inputs, the port must be configured in Input mode (floating, pull- up or pull-down) and the input pin must be driven externally. It is also possible to emulate the AFI input pin by software by programming the GPIO controller. In this case, the port should be configured in Alternate Function Output mode. And obviously, the corresponding port should not be driven externally as it will be driven by the software using the GPIO controller. ● For alternate function outputs, the port must be configured in Alternate Function Output mode (Push-Pull or Open-Drain). ● For bidirectional Alternate Functions, the port bit must be configured in Alternate Function Output mode (Push-Pull or Open-Drain). In this case the input driver is configured in input floating mode If you configure a port bit as Alternate Function Output, this disconnects the output register and connects the pin to the output signal of an on-chip peripheral. If software configures a GPIO pin as Alternate Function Output, but peripheral is not activated, its output is not specified. Software remapping of I/O alternate functions To optimize the number of peripheral I/O functions for different device packages, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the corresponding registers (refer to AFIO registers on page 158. In that case, the alternate functions are no longer mapped to their original assignations. GPIO locking mechanism The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence has been applied on a port bit, it is no longer possible to modify the value of the port bit until the next reset. Doc ID 13902 Rev 9 141/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 8.1.7 Input configuration When the I/O Port is programmed as Input: ● The Output Buffer is disabled ● The Schmitt Trigger Input is activated ● The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating): ● The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle ● A read access to the Input Data Register obtains the I/O State. The Figure 15 on page 142 shows the Input Configuration of the I/O Port bit. Figure 15. Input floating/pull up/pull down configurations Read Write Read/write Bit set/reset registers Output data register Input data register on TTL Schmitt trigger input driver output driver VDD on/off on/off VSS VDD or VDD_FT(1) protection diode I/O pin protection diode VSS 8.1.8 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. ai14783 Output configuration When the I/O Port is programmed as Output: ● The Output Buffer is enabled: – Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register leaves the port in Hi-Z. (the P-MOS is never activated) – Push-Pull Mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register activates the P-MOS. ● The Schmitt Trigger Input is activated. ● The weak pull-up and pull-down resistors are disabled. ● The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle ● A read access to the Input Data Register gets the I/O state in open drain mode ● A read access to the Output Data register gets the last written value in Push-Pull mode The Figure 16 on page 143 shows the Output configuration of the I/O Port bit. 142/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 16. Output configuration Bit set/reset registers Output data register Input data register 8.1.9 Read Write on TTL Schmitt trigger Input driver VDD or VDD_FT(1) Protection diode I/O pin Read/write Output driver Output control VDD P-MOS N-MOS Push-pull or VSS Open-drain Protection diode VSS ai14784 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. Alternate function configuration When the I/O Port is programmed as Alternate Function: ● The Output Buffer is turned on in Open Drain or Push-Pull configuration ● The Output Buffer is driven by the signal coming from the peripheral (alternate function out) ● The Schmitt Trigger Input is activated ● The weak pull-up and pull-down resistors are disabled. ● The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle ● A read access to the Input Data Register gets the I/O state in open drain mode ● A read access to the Output Data register gets the last written value in Push-Pull mode The Figure 17 on page 144 shows the Alternate Function Configuration of the I/O Port bit. Also, refer to Section 8.4: AFIO registers on page 158 for further information. A set of Alternate Function I/O registers allow you to remap some alternate functions to different pins. Refer to Doc ID 13902 Rev 9 143/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Figure 17. Alternate function configuration 8.1.10 Bit set/reset registers Output data register Input data register To on-chip peripheral Alternate Function Input Read Write on TTL Schmitt trigger Input driver Output driver Read/write From on-chip peripheral Alternate Function Output Output control VDD P-MOS N-MOS VSS push-pull or open-drain 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. VDD or VDD_FT(1) Protection diode I/O pin Protection diode VSS ai14785 Analog input configuration When the I/O Port is programmed as Analog Input Configuration: ● The Output Buffer is disabled. ● The Schmitt Trigger Input is de-activated providing zero consumption for every analog value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0). ● The weak pull-up and pull-down resistors are disabled. ● Read access to the Input Data Register gets the value “0”. The Figure 18 on page 144 shows the High impedance-Analog Input Configuration of the I/O Port bit. Figure 18. High impedance-analog input configuration Bit set/reset registers Output data register Input data register To on-chip peripheral Read Analog Input Write off 0 TTL Schmitt trigger Input driver VDD or VDD_FT(1) Protection diode I/O pin Read/write Protection diode VSS From on-chip peripheral ai14786 144/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.1.11 Peripherals’ GPIO configurations Table 19 to Table 29 give the GPIO configurations of the device peripherals. Table 19. Advanced timers TIM1/TIM8 TIM1/8 pinout configuration TIM1/8_CHx Input capture channel x Output compare channel x TIM1/8_CHxN TIM1/8_BKIN Complementary output channel x Break input TIM1/8_ETR External trigger timer input GPIO configuration Input floating Alternate function push-pull Alternate function push-pull Input floating Input floating Table 20. General-purpose timers TIM2/3/4/5 TIM2/3/4 pinout Configuration TIM2/3/4/5_CHx TIM2/3/4/5_ETR Input capture channel x Output compare channel x External trigger timer input GPIO configuration Input floating Alternate function push-pull Input floating Table 21. USARTs USART pinout Configuration USARTx_TX USARTx_RX USARTx_CK USARTx_RTS USARTx_CTS Full duplex Half duplex synchronous mode Full duplex Half duplex synchronous mode Synchronous mode Hardware flow control Hardware flow control GPIO configuration Alternate function push-pull Alternate function push-pull Input floating / Input pull-up Not used. Can be used as a general IO Alternate function push-pull Alternate function push-pull Input floating/ Input pull-up Table 22. SPI SPI pinout Configuration GPIO configuration Master SPIx_SCK Slave Alternate function push-pull Input floating Full duplex / Master Alternate function push-pull Full duplex / slave Input floating / Input pull-up SPIx_MOSI Simplex bidirectional data wire / Master Alternate function push-pull Simplex bidirectional data wire/ Slave Not used. Can be used as a GPIO Doc ID 13902 Rev 9 145/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 22. SPI (continued) SPI pinout Configuration GPIO configuration Full duplex / Master Input floating / Input pull-up Full Duplex / slave Alternate function push-pull SPIx_MISO Simplex bidirectional data wire / Master Not used. Can be used as a GPIO Simplex bidirectional data wire/ Slave Alternate function push-pull Hardware Master /Slave Input floating/ Input pull-up / Input pull-down SPIx_NSS Hardware Master/ NSS output enabled Alternate function push-pull Software Not used. Can be used as a GPIO Table 23. I2S I2S pinout I2Sx_ WS I2Sx_CK I2Sx_SD I2Sx_MCK Configuration Master Slave Master Slave Transmitter Receiver Master Slave GPIO configuration Alternate function push-pull Input floating Alternate function push-pull Input floating Alternate function push-pull Input floating/ Input pull-up/ Input pull-down Alternate function push-pull Not used. Can be used as a GPIO Table 24. I2C interface I2C pinout Configuration I2Cx_SCL I2C clock I2Cx_SDA I2C Data I/O GPIO configuration Alternate function open drain Alternate function open drain Table 25. BxCAN BxCAN pinout CAN_TX (Transmit data line) CAN_RX (Receive data line) GPIO configuration Alternate function push-pull Input floating / Input pull-up Table 26. USB USB pinout USB_DM / USB_DP GPIO configuration As soon as the USB is enabled, these pins are connected to the USB internal transceiver automatically. 146/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 27. SDIO SDIO pinout SDIO_CK SDIO_CMD SDIO[D7:D0] GPIO configuration Alternate function push-pull Alternate function push-pull Alternate function push-pull The GPIO configuration of the ADC inputs should be analog. Figure 19. ADC / DAC ADC/DAC pin ADC/DAC GPIO configuration Analog input Table 28. FSMC FSMC pinout FSMC_A[25:0] FSMC_D[15:0] FSMC_CK FSMC_NOE FSMC_NWE FSMC_NE[4:1] FSMC_NCE[3:2] FSMC_NCE4_1 FSMC_NCE4_2 FSMC_NWAIT FSMC_CD FSMC_NIOS16, FSMC_INTR FSMC_INT[3:2] FSMC_NL FSMC_NBL[1:0] FSMC_NIORD, FSMC_NIOWR FSMC_NREG GPIO configuration Alternate function push-pull Alternate function push-pull Alternate function push-pull Alternate function push-pull Input floating/ Input pull-up Input floating Alternate function push-pull Alternate function push-pull Table 29. Other IOs Pins Alternate function TAMPER-RTC pin MCO RTC output Tamper event input Clock output EXTI input lines External input interrupts GPIO configuration Forced by hardware when configuring the BKP_CR and BKP_RTCCR registers Alternate function push-pull Input floating / input pull-up / input pull-down Doc ID 13902 Rev 9 147/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 8.2 8.2.1 GPIO registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. Port configuration register low (GPIOx_CRL) (x=A..G) Address offset: 0x00 Reset value: 0x4444 4444 31 30 CNF7[1:0] rw rw 15 14 CNF3[1:0] rw rw 29 28 MODE7[1:0] rw rw 13 12 MODE3[1:0] rw rw 27 26 CNF6[1:0] rw rw 11 10 CNF2[1:0] rw rw 25 24 MODE6[1:0] rw rw 9 8 MODE2[1:0] rw rw 23 22 CNF5[1:0] rw rw 7 6 CNF1[1:0] rw rw 21 20 MODE5[1:0] rw rw 5 4 MODE1[1:0] rw rw 19 18 CNF4[1:0] rw rw 3 2 CNF0[1:0] rw rw 17 16 MODE4[1:0] rw rw 1 0 MODE0[1:0] rw rw Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 0 .. 7) 23:22, 19:18, 15:14, These bits are written by software to configure the corresponding I/O port. 11:10, 7:6, 3:2 Refer to Table 17: Port bit configuration table on page 140. In input mode (MODE[1:0]=00): 00: Analog input mode 01: Floating input (reset state) 10: Input with pull-up / pull-down 11: Reserved In output mode (MODE[1:0] >00): 00: General purpose output push-pull 01: General purpose output Open-drain 10: Alternate function output Push-pull 11: Alternate function output Open-drain Bits 29:28, 25:24, MODEy[1:0]: Port x mode bits (y= 0 .. 7) 21:20, 17:16, 13:12, These bits are written by software to configure the corresponding I/O port. 9:8, 5:4, 1:0 Refer to Table 17: Port bit configuration table on page 140. 00: Input mode (reset state) 01: Output mode, max speed 10 MHz. 10: Output mode, max speed 2 MHz. 11: Output mode, max speed 50 MHz. 148/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) Address offset: 0x04 Reset value: 0x4444 4444 31 30 CNF15[1:0] rw rw 15 14 CNF11[1:0] rw rw 29 28 MODE15[1:0] rw rw 13 12 MODE11[1:0] rw rw 27 26 CNF14[1:0] rw rw 11 10 CNF10[1:0] rw rw 25 24 MODE14[1:0] rw rw 9 8 MODE10[1:0] rw rw 23 22 CNF13[1:0] rw rw 7 6 CNF9[1:0] rw rw 21 20 MODE13[1:0] rw rw 5 4 MODE9[1:0] rw rw 19 18 CNF12[1:0] rw rw 3 2 CNF8[1:0] rw rw 17 16 MODE12[1:0] rw rw 1 0 MODE8[1:0] rw rw Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 8 .. 15) 23:22, 19:18, 15:14, These bits are written by software to configure the corresponding I/O port. 11:10, 7:6, 3:2 Refer to Table 17: Port bit configuration table on page 140. In input mode (MODE[1:0]=00): 00: Analog input mode 01: Floating input (reset state) 10: Input with pull-up / pull-down 11: Reserved In output mode (MODE[1:0] >00): 00: General purpose output push-pull 01: General purpose output Open-drain 10: Alternate function output Push-pull 11: Alternate function output Open-drain Bits 29:28, 25:24, MODEy[1:0]: Port x mode bits (y= 8 .. 15) 21:20, 17:16, 13:12, These bits are written by software to configure the corresponding I/O port. 9:8, 5:4, 1:0 Refer to Table 17: Port bit configuration table on page 140. 00: Input mode (reset state) 01: Output mode, max speed 10 MHz. 10: Output mode, max speed 2 MHz. 11: Output mode, max speed 50 MHz. 8.2.3 Port input data register (GPIOx_IDR) (x=A..G) Address offset: 0x08h Reset value: 0x0000 XXXX 31 30 29 28 27 26 25 15 14 13 12 11 10 IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 r r r r r r 9 IDR9 r 24 23 Reserved 8 7 IDR8 IDR7 r r 22 6 IDR6 r 21 5 IDR5 r 20 4 IDR4 r 19 3 IDR3 r 18 2 IDR2 r 17 1 IDR1 r 16 0 IDR0 r Bits 31:16 Reserved, always read as 0. Bits 15:0 IDRy[15:0]: Port input data (y= 0 .. 15) These bits are read only and can be accessed in Word mode only. They contain the input value of the corresponding I/O port. Doc ID 13902 Rev 9 149/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 8.2.4 Port output data register (GPIOx_ODR) (x=A..G) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 15 14 13 12 11 10 9 ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 rw rw rw rw rw rw rw 24 23 Reserved 8 7 ODR8 ODR7 rw rw 22 6 ODR6 rw 21 5 ODR5 rw 20 4 ODR4 rw 19 3 ODR3 rw 18 2 ODR2 rw 17 1 ODR1 rw 16 0 ODR0 rw Bits 31:16 Reserved, always read as 0. Bits 15:0 ODRy[15:0]: Port output data (y= 0 .. 15) These bits can be read and written by software and can be accessed in Word mode only. Note: For atomic bit set/reset, the ODR bits can be individually set and cleared by writing to the GPIOx_BSRR register (x = A .. G). 8.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 w w w w w w w w w w w w w w w w Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. 0: No action on the corresponding ODRx bit 1: Reset the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority. Bits 15:0 BSy: Port x Set bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. 0: No action on the corresponding ODRx bit 1: Set the corresponding ODRx bit 150/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. 0: No action on the corresponding ODRx bit 1: Reset the corresponding ODRx bit 8.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit it is no longer possible to modify the value of the port bit until the next reset. Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH). Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 15 14 13 12 11 10 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 rw rw rw rw rw rw 25 24 23 Reserved 9 LCK9 rw 8 LCK8 rw 7 LCK7 rw 22 6 LCK6 rw 21 5 LCK5 rw 20 4 LCK4 rw 19 3 LCK3 rw 18 2 LCK2 rw 17 1 LCK1 rw 16 LCKK rw 0 LCK0 rw Bits 31:17 Reserved Doc ID 13902 Rev 9 151/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bit 16 LCKK[16]: Lock key This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. GPIOx_LCKR register is locked until an MCU reset occurs. LOCK key writing sequence: Write 1 Write 0 Write 1 Read 0 Read 1 (this read is optional but confirms that the lock is active) Note: During the LOCK Key Writing sequence, the value of LCK[15:0] must not change. Any error in the lock sequence will abort the lock. Bits 15:0 LCKy: Port x Lock bit y (y= 0 .. 15) These bits are read write but can only be written when the LCKK bit is 0. 0: Port configuration not locked 1: Port configuration locked. 8.3 Alternate function I/O and debug configuration (AFIO) To optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin package, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the AF remap and debug I/O configuration register (AFIO_MAPR) on page 159. In this case, the alternate functions are no longer mapped to their original assignations. 8.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O PC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the GP IOs function. Note: 1 The PC14/PC15 GPIO functionality is lost when the 1.8 V domain is powered off (by entering standby mode) or when the backup domain is supplied by VBAT (VDD no more supplied). In this case the IOs are set in analog input mode. 2 Refer to the note on IO usage restrictions in Section 4.1.2 on page 54. 8.3.2 Note: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1 by programming the PD01_REMAP bit in the AF remap and debug I/O configuration register (AFIO_MAPR). This remap is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping). The external interrupt/event function is not remapped. PD0 and PD1 cannot be used for external interrupt/event generation on 36-, 48- and 64-pin packages. 152/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.3.3 8.3.4 CAN1 alternate function remapping The CAN signals can be mapped on Port A, Port B or Port D as shown in Table 30. For port D, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages. Table 30. CAN1 alternate function remapping Alternate function(1) CAN_REMAP[1:0] = “00” CAN_REMAP[1:0] = “10” (2) CAN_REMAP[1:0] = “11”(3) CAN1_RX or CAN_RX PA11 PB8 PD0 CAN1_TX or CAN_RX PA12 PB9 PD1 1. CAN1_RX and CAN1_TX in connectivity line devices; CAN_RX and CAN_TX in other devices with a single CAN interface. 2. Remap not available on 36-pin package 3. This remapping is available only on 100-pin and 144-pin packages, when PD0 and PD1 are not remapped on OSC-IN and OSC-OUT. CAN2 alternate function remapping CAN2 is available in connectivity line devices. The external signal can be remapped as shown in Chapter Table 31. Table 31. CAN2 alternate function remapping Alternate function CAN2_REMAP = “0” CAN2_RX PB12 CAN2_TX PB13 CAN2_REMAP = “1” PB5 PB6 8.3.5 JTAG/SWD alternate function remapping The debug interface signals are mapped on the GPIO ports as shown in Table 32. Table 32. Debug interface signals Alternate function JTMS / SWDIO JTCK / SWCLK JTDI JTDO / TRACESWO JNTRST TRACECK TRACED0 TRACED1 TRACED2 TRACED3 GPIO port PA13 PA14 PA15 PB3 PB4 PE2 PE3 PE4 PE5 PE6 Doc ID 13902 Rev 9 153/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 8.3.6 To optimize the number of free GPIOs during debugging, this mapping can be configured in different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O configuration register (AFIO_MAPR). Refer to Table 33 Table 33. Debug port mapping SWJ _CFG [2:0] Available debug ports SWJ I/O pin assigned PA13 / JTMS/ SWDIO PA14 / JTCK/S WCLK PA15 / JTDI PB3 / JTDO/ TRACE SWO PB4/ NJTRST 000 Full SWJ (JTAG-DP + SW-DP) (Reset state) X X X X X 001 Full SWJ (JTAG-DP + SW-DP) but without JNTRST X X X x free 010 JTAG-DP Disabled and SW-DP Enabled X X free free(1) free 100 JTAG-DP Disabled and SW-DP Disabled free free free free free Other Forbidden 1. Released only if not using asynchronous trace. ADC alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Table 34. ADC1 external trigger injected conversion alternate function remapping(1) Alternate function ADC1_ETRGINJ_REMAP = 0 ADC1_ETRGINJ_REMAP = 1 ADC1 external trigger injected conversion ADC1 external trigger injected conversion is connected to EXTI15 1. Remap available only for high-density devices. ADC1 external trigger injected conversion is connected to TIM8_CH4 Table 35. ADC1 external trigger regular conversion alternate function remapping(1) Alternate function ADC1_ETRGREG_REMAP = 0 ADC1_ETRGREG_REMAP = 1 ADC1 external trigger regular conversion ADC1 external trigger regular conversion is connected to EXTI11 ADC1 external trigger regular conversion is connected to TIM8_TRGO 1. Remap available only for high-density devices. Table 36. ADC2 external trigger injected conversion alternate function remapping(1) Alternate function ADC2_ETRGINJ_REMAP = 0 ADC2_ETRGINJ_REMAP = 1 ADC2 external trigger injected conversion ADC2 external trigger injected conversion is connected to EXTI 15 ADC2 external trigger injected conversion is connected to TIM8_CH4 1. Remap available only for high-density devices. 154/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 37. ADC2 external trigger regular conversion alternate function remapping(1) Alternate function ADC2_ETRGREG_REG = 0 ADC2_ETRGREG_REG = 1 ADC2 external trigger regular conversion ADC2 external trigger regular conversion is connected to EXTI11 ADC2 external trigger regular conversion is connected to TIM8_TRGO 1. Remap available only for high-density devices. 8.3.7 Timer alternate function remapping Timer 4 channels 1 to 4 can be remapped from Port B to Port D. Other timer remapping possibilities are listed in Table 40 to Table 42. Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Table 38. TIM5 alternate function remapping(1) Alternate function TIM5CH4_IREMAP = 0 TIM5CH4_IREMAP = 1 TIM5_CH4 TIM5 Channel4 is connected to PA3 LSI internal clock is connected to TIM5_CH4 input for calibration purpose. 1. Remap available only for high-density and connectivity line devices. Table 39. TIM4 alternate function remapping Alternate function TIM4_REMAP = 0 TIM4_CH1 PB6 TIM4_CH2 PB7 TIM4_CH3 PB8 TIM4_CH4 PB9 1. Remap available only for 100-pin and for 144-pin package. TIM4_REMAP = 1(1) PD12 PD13 PD14 PD15 Table 40. TIM3 alternate function remapping Alternate function TIM3_REMAP[1:0] = TIM3_REMAP[1:0] = TIM3_REMAP[1:0] = “00” (no remap) “10” (partial remap) “11” (full remap) (1) TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 PA6 PB4 PC6 PA7 PB5 PC7 PB0 PC8 PB1 PC9 1. Remap available only for 64-pin, 100-pin and 144-pin packages. Doc ID 13902 Rev 9 155/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 8.3.8 Table 41. TIM2 alternate function remapping TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: Alternate function 0] = “00” (no 0] = “01” (partial 0] = “10” (partial 0] = “11” (full remap) remap) remap) (1) remap) (1) TIM2_CH1_ETR(2) PA0 PA15 PA0 PA15 TIM2_CH2 PA1 PB3 PA1 PB3 TIM2_CH3 PA2 PB10 TIM2_CH4 PA3 PB11 1. Remap not available on 36-pin package. 2. TIM_CH1 and TIM_ETR share the same pin but cannot be used at the same time (which is why we have this notation: TIM2_CH1_ETR). Table 42. TIM1 alternate function remapping Alternate functions mapping TIM1_REMAP[1:0] = TIM1_REMAP[1:0] = TIM1_REMAP[1:0] = “00” (no remap) “01” (partial remap) “11” (full remap) (1) TIM1_ETR TIM1_CH1 TIM1_CH2 TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM1_CH1N TIM1_CH2N TIM1_CH3N PA12 PA8 PA9 PA10 PB12 (2) PB13 (2) PB14 (2) PB15 (2) PA11 PA6 PA7 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15 PE8 PE10 PE12 1. Remap available only for 100-pin and 144-pin packages. 2. Remap not available on 36-pin package. USART Alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Table 43. USART3 remapping Alternate function USART3_REMAP[1:0] = “00” (no remap) USART3_REMAP[1:0] = “01” (partial remap) (1) USART3_REMAP[1:0] = “11” (full remap) (2) USART3_TX USART3_RX USART3_CK USART3_CTS USART3_RTS PB10 PB11 PB12 PB13 PB14 PC10 PC11 PC12 PD8 PD9 PD10 PD11 PD12 1. Remap available only for 64-pin, 100-pin and 144-pin packages 2. Remap available only for 100-pin and 144-pin packages. 156/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 44. USART2 remapping Alternate functions USART2_REMAP = 0 USART2_CTS PA0 USART2_RTS PA1 USART2_TX PA2 USART2_RX PA3 USART2_CK PA4 1. Remap available only for 100-pin and 144-pin packages. USART2_REMAP = 1(1) PD3 PD4 PD5 PD6 PD7 Table 45. USART1 remapping Alternate function USART1_TX USART1_RX USART1_REMAP = 0 PA9 PA10 USART1_REMAP = 1 PB6 PB7 8.3.9 8.3.10 I2C1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 46. I2C1 remapping Alternate function I2C1_SCL I2C1_SDA 1. Remap not available on 36-pin package. I2C1_REMAP = 0 PB6 PB7 I2C1_REMAP = 1 (1) PB8 PB9 SPI1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 47. SPI1 remapping Alternate function SPI1_NSS SPI1_SCK SPI1_MISO SPI1_MOSI SPI1_REMAP = 0 PA4 PA5 PA6 PA7 SPI1_REMAP = 1 PA15 PB3 PB4 PB5 8.3.11 SPI3 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR). This remap is available only in connectivity line devices. Doc ID 13902 Rev 9 157/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 48. SPI3 remapping Alternate function SPI3_NSS SPI3_SCK SPI3_MISO SPI3_MOSI SPI3_REMAP = 0 PA15 PB3 PB4 PB5 SPI3_REMAP = 1 PA4 PC10 PC11 PC12 8.3.12 Ethernet alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Ethernet is available only in connectivity line devices. Table 49. ETH remapping Alternate function RX_DV-CRS_DV RXD0 RXD1 RXD2 RXD3 ETH_REMAP = 0 PA7 PC4 PC5 PB0 PB1 ETH_REMAP = 1 PD8 PD9 PD10 PD11 PD12 8.4 Note: AFIO registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. To read/write the AFIO_EVCR,AFIO_MAPR and AFIO_EXTICRX registers, the AFIO clock should first be enabled. Refer to Section 6.3.7: APB2 peripheral clock enable register (RCC_APB2ENR). 8.4.1 Event control register (AFIO_EVCR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EVOE PORT[2:0] PIN[3:0] rw rw rw rw rw rw rw rw Bits 31:8 Reserved Bit 7 EVOE: Event output enable Set and cleared by software. When set the EVENTOUT Cortex output is connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits. 158/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 6:4 PORT[2:0]: Port selection Set and cleared by software. Select the port used to output the Cortex EVENTOUT signal. Note: The EVENTOUT signal output capability is not extended to ports PF and PG. 000: PA selected 001: PB selected 010: PC selected 011: PD selected 100: PE selected Bits 3:0 PIN[3:0]: Pin selection (x = A .. E) Set and cleared by software. Select the pin used to output the Cortex EVENTOUT signal. 0000: Px0 selected 0001: Px1 selected 0010: Px2 selected 0011: Px3 selected ... 1111: Px15 selected 8.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) Address offset: 0x04 Reset value: 0x0000 0000 Memory map and bit definitions for low-, medium- and high-density devices: 31 30 29 28 27 26 25 24 Reserved SWJ_ CFG[2:0] w w w 15 14 13 12 11 10 9 8 PD01_ CAN_REMAP TIM4_ TIM3_REMAP TIM2_REMAP REMAP [1:0] REMAP [1:0] [1:0] rw rw rw rw rw rw rw rw 23 22 21 20 19 18 17 16 Reserved ADC2_ ETRGR EG_RE MAP ADC2_ ETRGIN J_REM AP ADC1_ ETRGR EG_RE MAP ADC1_ ETRGIN J_REM AP TIM5CH 4_IREM AP rw rw rw rw rw 7 6 5 4 3 2 1 0 TIM1_REMAP [1:0] USART3_ REMAP[1:0] USART 2_ REMAP USART 1_ REMAP I2C1_ REMAP SPI1_ REMAP rw rw rw rw rw rw rw rw Bits 31:27 Reserved Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration These bits are write-only (when read, the value is undefined). They are used to configure the SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex debug port. The default state after reset is SWJ ON without trace. This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS / JTCK pin. 000: Full SWJ (JTAG-DP + SW-DP): Reset State 001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST 010: JTAG-DP Disabled and SW-DP Enabled 100: JTAG-DP Disabled and SW-DP Disabled Other combinations: no effect Bits 23:21 Reserved Doc ID 13902 Rev 9 159/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 20 ADC2_ETRGREG_REMAP: ADC 2 external trigger regular conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger regular conversion. When this bit is reset, the ADC2 external trigger regular conversion is connected to EXTI11. When this bit is set, the ADC2 external event regular conversion is connected to TIM8_TRGO. Bits 19 ADC2_ETRGINJ_REMAP: ADC 2 external trigger injected conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger injected conversion. When this bit is reset, the ADC2 external trigger injected conversion is connected to EXTI15. When this bit is set, the ADC2 external event injected conversion is connected to TIM8_Channel4. Bits 18 ADC1_ETRGREG_REMAP: ADC 1 external trigger regular conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC1 External trigger regular conversion. When reset the ADC1 External trigger regular conversion is connected to EXTI11. When set the ADC1 External Event regular conversion is connected to TIM8 TRGO. Bits 17 ADC1_ETRGINJ_REMAP: ADC 1 External trigger injected conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC1 External trigger injected conversion. When reset the ADC1 External trigger injected conversion is connected to EXTI15. When set the ADC1 External Event injected conversion is connected to TIM8 Channel4. Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to TIM5_CH4 input for calibration purpose. Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping). 0: No remapping of PD0 and PD1 1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT, Bits 14:13 CAN_REMAP[1:0]: CAN alternate function remapping These bits are set and cleared by software. They control the mapping of alternate functions CAN_RX and CAN_TX in devices with a single CAN interface. 00: CAN_RX mapped to PA11, CAN_TX mapped to PA12 01: Not used 10: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) 11: CAN_RX mapped to PD0, CAN_TX mapped to PD1 Bit 12 TIM4_REMAP: TIM4 remapping This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the GPIO ports. 0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) 1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) Note: TIM4_ETR on PE0 is not re-mapped. 160/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01: Not used 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) Note: TIM3_ETR on PE0 is not re-mapped. Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports. 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports. 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 10: not used 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) Bits 5:4 USART3_REMAP[1:0]: USART3 remapping These bits are set and cleared by software. They control the mapping of USART3 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 10: not used 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) Bit 3 USART2_REMAP: USART2 remapping This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) Bit 2 USART1_REMAP: USART1 remapping This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports. 0: No remap (TX/PA9, RX/PA10) 1: Remap (TX/PB6, RX/PB7) Bit 1 I2C1_REMAP: I2C1 remapping This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate functions on the GPIO ports. 0: No remap (SCL/PB6, SDA/PB7) 1: Remap (SCL/PB8, SDA/PB9) Doc ID 13902 Rev 9 161/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bit 0 SPI1_REMAP: SPI1 remapping This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) Memory map and bit definitions for connectivity line devices: 31 Res. 15 30 29 28 PTP_P PS_RE MAP TIM2IT R1_ IREMA P SPI3_ REMAP rw rw rw 14 13 12 27 Res. 11 26 25 24 23 22 21 20 SWJ_ CFG[2:0] MII_RMI CAN2_ ETH_R I_SEL REMAP EMAP w w w rw rw rw 10 9 8 7 6 5 4 PD01_ CAN1_REMAP TIM4_ TIM3_REMAP TIM2_REMAP TIM1_REMAP REMAP [1:0] REMAP [1:0] [1:0] [1:0] USART3_ REMAP[1:0] rw rw rw rw rw rw rw rw rw rw rw rw 19 18 17 16 Reserved TIM5CH 4_IREM AP rw 3 2 1 0 USART 2_ REMAP USART 1_ REMAP I2C1_ REMAP SPI1_ REMAP rw rw rw rw Bit 31 Reserved Bit 30 PTP_PPS_REMAP: Ethernet PTP PPS remapping This bit is set and cleared by software. It enables the Ethernet MAC PPS_PTS to be output on the PB5 pin. 0: PTP_PPS not output on PB5 pin. 1: PTP_PPS is output on PB5 pin. Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 29 TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping This bit is set and cleared by software. It controls the TIM2_ITR1 internal mapping. 0: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. 1: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 28 SPI3_REMAP: SPI3 remapping This bit is set and cleared by software. It controls the mapping of SPI3 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) 1: Remap (NSS/PA4, SCK/PC10, MISO/PC11, MOSI/PC12) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 27 Reserved Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration These bits are write-only (when read, the value is undefined). They are used to configure the SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex debug port. The default state after reset is SWJ ON without trace. This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS / JTCK pin. 000: Full SWJ (JTAG-DP + SW-DP): Reset State 001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST 010: JTAG-DP Disabled and SW-DP Enabled 100: JTAG-DP Disabled and SW-DP Disabled Other combinations: no effect 162/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 23 MII_RMII_SEL: MII or RMII selection This bit is set and cleared by software. It configures the Ethernet MAC internally for use with an external MII or RMII PHY. 0: Configure Ethernet MAC for connection with an MII PHY 1: Configure Ethernet MAC for connection with an RMII PHY Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 22 CAN2_REMAP: CAN2 I/O remapping This bit is set and cleared by software. It controls the CAN2_TX and CAN2_RX pins. 0: No remap (CAN2_RX/PB12, CAN2_TX/PB13) 1: Remap (CAN2_RX/PB5, CAN2_TX/PB6) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 21 ETH_REMAP: Ethernet MAC I/O remapping This bit is set and cleared by software. It controls the Ethernet MAC connections with the PHY. 0: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) 1: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bits 20:17 Reserved Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to TIM5_CH4 input for calibration purpose. Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping). 0: No remapping of PD0 and PD1 1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT, Bits 14:13 CAN1_REMAP[1:0]: CAN1 alternate function remapping These bits are set and cleared by software. They control the mapping of alternate functions CAN1_RX and CAN1_TX. 00: CAN1_RX mapped to PA11, CAN1_TX mapped to PA12 01: Not used 10: CAN1_RX mapped to PB8, CAN1_TX mapped to PB9 (not available on 36-pin package) 11: CAN1_RX mapped to PD0, CAN1_TX mapped to PD1 Bit 12 TIM4_REMAP: TIM4 remapping This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the GPIO ports. 0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) 1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) Note: TIM4_ETR on PE0 is not re-mapped. Doc ID 13902 Rev 9 163/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01: Not used 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) Note: TIM3_ETR on PE0 is not re-mapped. Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports. 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports. 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 10: not used 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) Bits 5:4 USART3_REMAP[1:0]: USART3 remapping These bits are set and cleared by software. They control the mapping of USART3 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 10: not used 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) Bit 3 USART2_REMAP: USART2 remapping This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) Bit 2 USART1_REMAP: USART1 remapping This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports. 0: No remap (TX/PA9, RX/PA10) 1: Remap (TX/PB6, RX/PB7) Bit 1 I2C1_REMAP: I2C1 remapping This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate functions on the GPIO ports. 0: No remap (SCL/PB6, SDA/PB7) 1: Remap (SCL/PB8, SDA/PB9) 164/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.4.3 Bit 0 SPI1_REMAP: SPI1 remapping This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) External interrupt configuration register 1 (AFIO_EXTICR1) Address offset: 0x08 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3) These bits are written by software to select the source input for EXTIx external interrupt. Refer to Section 9.2.5: External interrupt/event line mapping on page 176 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 8.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) Address offset: 0x0C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin Doc ID 13902 Rev 9 165/995 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 8.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) Address offset: 0x10 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 8.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) Address offset: 0x14 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 166/995 Doc ID 13902 Rev 9 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.5 GPIO and AFIO register maps Refer to Table 1 on page 41 for the register boundary addresses. The following tables give the GPIO and AFIO register map and the reset values. Table 50. GPIO register map and reset values Offset Register 0 1 2 3 4 6 5 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x00 GPIOx_CRL CNF7 MODE7 CNF6 MODE6 CNF5 MODE5 CNF4 MODE4 CNF3 MODE3 CNF2 MODE2 CNF1 MODE1 CNF0 MODE0 [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] 0x04 Reset value GPIOx_CRH Reset value 01 0 0 01 0 0 01 0 0 0 1 0 0 01 0 0 01 0 0 01 0 0 01 0 0 CNF 15 [1:0] MODE1 5 [1:0] CNF 14 [1:0] MODE1 4 [1:0] CNF 13 [1:0] MODE1 3 [1:0] CNF 12 [1:0] MODE1 2 [1:0] CNF 11 [1:0] MODE1 1 [1:0] CNF 10 [1:0] MODE1 0 [1:0] CNF 9 [1:0] MODE9 [1:0] CNF 8 [1:0] MODE8 [1:0] 01 0 0 01 0 0 01 0 0 0 1 0 0 01 0 0 01 0 0 01 0 0 01 0 0 0x08 GPIOx_IDR Reset value Reserved IDR[15:0]l 00 0 0 00 0 0 00 0 0 00 0 0 0x0C GPIOx_ODR Reset value Reserved ODR[15:0] 00 0 0 00 0 0 00 0 0 00 0 0 0x10 GPIOx_BSRR BR[15:0] BSR[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 GPIOx_BRR Reset value Reserved BR[15:0] 00 0 0 00 0 0 00 0 0 00 0 0 LCKK 0x18 GPIOx_LCKR Reset value Reserved LCK[15:0] 0 00 0 0 00 0 0 00 0 0 00 0 0 Table 51. AFIO register map and reset values Offset Register 19 20 21 22 23 24 25 26 27 28 29 30 31 0x00 AFIO_EVCR Reset value Reserved 18 17 16 15 14 13 12 11 10 9 8 7 EVOE 6 5 4 3 PORT[2:0] PIN[3:0] 0000000 2 1 SPI1_REMAP I2C1_REMAP USART1_REMAP USART2_REMAP USART3_REMAP[0] USART3_REMAP[1] TIM1_REMPAP[0] TIM1_REMPAP[1] TIM2_REMPAP[0] TIM2_REMPAP[1] TIM3_REMPAP[0] TIM3_REMPAP[1] TIM4_REMPAP CAN1_REMAP[0] CAN1_REMAP[1] PD01_REMAP TIM5CH4_IREMAP ADC1_ETRGINJ_REMAP ADC1_ETRGREG_REMAP ADC2_ETRGINJ_REMAP ADC2_ETRGREG_REMAP SWJ_CFG[0] SWJ_CFG[1] SWJ_CFG[2] 0x04 AFIO_MAPR low-, mediumand high-density devices Reserved Reserved SPI1_REMAP Reset value 000 CAN2_REMAP MII_RMII_SEL SWJ_CFG[0] SWJ_CFG[1] SWJ_CFG[2] Reserved SPI3_REMAP TIM2ITR1_IREMAP PTP_PPS_REMAP Reserved 0x04 AFIO_MAPR connectivity line devices Reset value 0x08 AFIO_EXTICR1 Reset value 0x0C AFIO_EXTICR2 Reset value 000 000000 Reserved Reserved ETH_REMAP Reserved TIM5CH4_IREMAP PD01_REMAP CAN1_REMAP[1] CAN1_REMAP[0] TIM4_REMPAP TIM3_REMPAP[1] TIM3_REMPAP[0] TIM2_REMPAP[1] TIM2_REMPAP[0] 0000000000000000 00000000000000000 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] 0000000000000000 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] 0000000000000000 TIM1_REMPAP[1] TIM1_REMPAP[0] USART3_REMAP[1] USART3_REMAP[0] USART2_REMAP USART1_REMAP I2C1_REMAP 0 Doc ID 13902 Rev 9 167/995 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 51. AFIO register map and reset values (continued) Offset Register 0x10 0x14 AFIO_EXTICR3 Reset value AFIO_EXTICR4 Reset value Reserved Reserved EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] 0000000000000000 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] 0000000000000000 Refer to Table 1 on page 41 for the register boundary addresses. 168/995 Doc ID 13902 Rev 9 RM0008 9 Interrupts and events Interrupts and events Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to the whole STM32F10xxx family, unless otherwise specified. 9.1 9.1.1 9.1.2 Nested vectored interrupt controller (NVIC) Features ● 68 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) ● 16 programmable priority levels (4 bits of interrupt priority are used) ● Low-latency exception and interrupt handling ● Power management control ● Implementation of System Control Registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming see Chap 5 Exceptions & Chap 8 Nested Vectored Interrupt Controller of the ARM Cortex™-M3 Technical Reference Manual. SysTick calibration value register The SysTick calibration value is fixed to 9000, which gives a reference time base of 1 ms with the SysTick clock set to 9 MHz (max HCLK/8). Interrupt and exception vectors Table 52 and Table 53 are the vector tables for connectivity line and other STM32F10xxx devices, respectively. Position Priority Table 52. Vector table for connectivity line devices Type of priority Acronym Description Address - - - -3 fixed Reset -2 fixed NMI Reserved Reset Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. 0x0000_0000 0x0000_0004 0x0000_0008 Doc ID 13902 Rev 9 169/995 Interrupts and events RM0008 Table 52. Vector table for connectivity line devices (continued) Position Priority Type of priority Acronym Description Address -1 fixed HardFault 0 settable MemManage 1 settable BusFault 2 settable UsageFault - - - 3 settable SVCall 4 settable Debug Monitor - - - 5 settable PendSV 6 settable SysTick 0 7 settable WWDG 1 8 settable PVD 2 9 settable TAMPER 3 10 settable RTC 4 11 settable FLASH 5 12 settable RCC 6 13 settable EXTI0 7 14 settable EXTI1 8 15 settable EXTI2 9 16 settable EXTI3 10 17 settable EXTI4 11 18 settable DMA1_Channel1 12 19 settable DMA1_Channel2 13 20 settable DMA1_Channel3 14 21 settable DMA1_Channel4 15 22 settable DMA1_Channel5 16 23 settable DMA1_Channel6 17 24 settable DMA1_Channel7 18 25 settable ADC1_2 19 26 settable CAN1_TX 20 27 settable CAN1_RX0 21 28 settable CAN1_RX1 All class of fault 0x0000_000C Memory management 0x0000_0010 Pre-fetch fault, memory access fault 0x0000_0014 Undefined instruction or illegal state 0x0000_0018 Reserved 0x0000_001C 0x0000_002B System service call via SWI instruction 0x0000_002C Debug Monitor 0x0000_0030 Reserved 0x0000_0034 Pendable request for system service 0x0000_0038 System tick timer 0x0000_003C Window Watchdog interrupt 0x0000_0040 PVD through EXTI Line detection interrupt 0x0000_0044 Tamper interrupt 0x0000_0048 RTC global interrupt 0x0000_004C Flash global interrupt 0x0000_0050 RCC global interrupt 0x0000_0054 EXTI Line0 interrupt 0x0000_0058 EXTI Line1 interrupt 0x0000_005C EXTI Line2 interrupt 0x0000_0060 EXTI Line3 interrupt 0x0000_0064 EXTI Line4 interrupt 0x0000_0068 DMA1 Channel1 global interrupt 0x0000_006C DMA1 Channel2 global interrupt 0x0000_0070 DMA1 Channel3 global interrupt 0x0000_0074 DMA1 Channel4 global interrupt 0x0000_0078 DMA1 Channel5 global interrupt 0x0000_007C DMA1 Channel6 global interrupt 0x0000_0080 DMA1 Channel7 global interrupt 0x0000_0084 ADC1 and ADC2 global interrupt 0x0000_0088 CAN1 TX interrupts 0x0000_008C CAN1 RX0 interrupts 0x0000_0090 CAN1 RX1 interrupt 0x0000_0094 170/995 Doc ID 13902 Rev 9 RM0008 Interrupts and events Table 52. Vector table for connectivity line devices (continued) Position Priority Type of priority Acronym Description 22 29 settable CAN1_SCE 23 30 settable EXTI9_5 24 31 settable TIM1_BRK 25 32 settable TIM1_UP 26 33 settable TIM1_TRG_COM 27 34 settable TIM1_CC 28 35 settable TIM2 29 36 settable TIM3 30 37 settable TIM4 31 38 settable I2C1_EV 32 39 settable I2C1_ER 33 40 settable I2C2_EV 34 41 settable I2C2_ER 35 42 settable SPI1 36 43 settable SPI2 37 44 settable USART1 38 45 settable USART2 39 46 settable USART3 40 47 settable EXTI15_10 41 48 settable RTCAlarm 42 49 settable OTG_FS_WKUP CAN1 SCE interrupt EXTI Line[9:5] interrupts TIM1 Break interrupt TIM1 Update interrupt TIM1 Trigger and Commutation interrupts TIM1 Capture Compare interrupt TIM2 global interrupt TIM3 global interrupt TIM4 global interrupt I2C1 event interrupt I2C1 error interrupt I2C2 event interrupt I2C2 error interrupt SPI1 global interrupt SPI2 global interrupt USART1 global interrupt USART2 global interrupt USART3 global interrupt EXTI Line[15:10] interrupts RTC alarm through EXTI line interrupt USB On-The-Go FS Wakeup through EXTI line interrupt -- - - Reserved 50 57 settable TIM5 51 58 settable SPI3 52 59 settable UART4 53 60 settable UART5 54 61 settable TIM6 55 62 settable TIM7 56 63 settable DMA2_Channel1 57 64 settable DMA2_Channel2 58 65 settable DMA2_Channel3 TIM5 global interrupt SPI3 global interrupt UART4 global interrupt UART5 global interrupt TIM6 global interrupt TIM7 global interrupt DMA2 Channel1 global interrupt DMA2 Channel2 global interrupt DMA2 Channel3 global interrupt Address 0x0000_0098 0x0000_009C 0x0000_00A0 0x0000_00A4 0x0000_00A8 0x0000_00AC 0x0000_00B0 0x0000_00B4 0x0000_00B8 0x0000_00BC 0x0000_00C0 0x0000_00C4 0x0000_00C8 0x0000_00CC 0x0000_00D0 0x0000_00D4 0x0000_00D8 0x0000_00DC 0x0000_00E0 0x0000_00E4 0x0000_00E8 0x0000_00EC 0x0000_0104 0x0000_0108 0x0000_010C 0x0000_0110 0x0000_0114 0x0000_0118 0x0000_011C 0x0000_0120 0x0000_0124 0x0000_0128 Doc ID 13902 Rev 9 171/995 Interrupts and events RM0008 Table 52. Vector table for connectivity line devices (continued) Position Priority Type of priority Acronym Description Address 59 66 settable DMA2_Channel4 60 67 settable DMA2_Channel5 61 68 settable ETH 62 69 settable ETH_WKUP 63 70 settable CAN2_TX 64 71 settable CAN2_RX0 65 72 settable CAN2_RX1 66 73 settable CAN2_SCE 67 74 settable OTG_FS DMA2 Channel4 global interrupt DMA2 Channel5 global interrupt Ethernet global interrupt Ethernet Wakeup through EXTI line interrupt CAN2 TX interrupts CAN2 RX0 interrupts CAN2 RX1 interrupt CAN2 SCE interrupt USB On The Go FS global interrupt 0x0000_012C 0x0000_0130 0x0000_0134 0x0000_0138 0x0000_013C 0x0000_0140 0x0000_0144 0x0000_0148 0x0000_014C Table 53. Vector table for other STM32F10xxx devices Position Priority Type of priority Acronym Description Address - - - -3 fixed Reset -2 fixed NMI -1 fixed HardFault 0 settable MemManage 1 settable BusFault 2 settable UsageFault - - - 3 settable SVCall 4 settable Debug Monitor - - - 5 settable PendSV 6 settable SysTick 0 7 settable WWDG 1 8 settable PVD 2 9 settable TAMPER Reserved 0x0000_0000 Reset 0x0000_0004 Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. 0x0000_0008 All class of fault 0x0000_000C Memory management 0x0000_0010 Pre-fetch fault, memory access fault 0x0000_0014 Undefined instruction or illegal state 0x0000_0018 Reserved 0x0000_001C 0x0000_002B System service call via SWI instruction 0x0000_002C Debug Monitor 0x0000_0030 Reserved 0x0000_0034 Pendable request for system service 0x0000_0038 System tick timer 0x0000_003C Window watchdog interrupt 0x0000_0040 PVD through EXTI Line detection interrupt 0x0000_0044 Tamper interrupt 0x0000_0048 172/995 Doc ID 13902 Rev 9 RM0008 Interrupts and events Table 53. Vector table for other STM32F10xxx devices (continued) Position Priority Type of priority Acronym Description Address 3 10 settable RTC 4 11 settable FLASH 5 12 settable RCC 6 13 settable EXTI0 7 14 settable EXTI1 8 15 settable EXTI2 9 16 settable EXTI3 10 17 settable EXTI4 11 18 settable DMA1_Channel1 12 19 settable DMA1_Channel2 13 20 settable DMA1_Channel3 14 21 settable DMA1_Channel4 15 22 settable DMA1_Channel5 16 23 settable DMA1_Channel6 17 24 settable DMA1_Channel7 18 25 settable ADC1_2 19 26 settable USB_HP_CAN_ TX 20 27 settable USB_LP_CAN_ RX0 21 28 settable CAN_RX1 22 29 settable CAN_SCE 23 30 settable EXTI9_5 24 31 settable TIM1_BRK 25 32 settable TIM1_UP 26 33 settable TIM1_TRG_COM 27 34 settable TIM1_CC 28 35 settable TIM2 29 36 settable TIM3 30 37 settable TIM4 31 38 settable I2C1_EV 32 39 settable I2C1_ER 33 40 settable I2C2_EV 34 41 settable I2C2_ER RTC global interrupt Flash global interrupt RCC global interrupt EXTI Line0 interrupt EXTI Line1 interrupt EXTI Line2 interrupt EXTI Line3 interrupt EXTI Line4 interrupt DMA1 Channel1 global interrupt DMA1 Channel2 global interrupt DMA1 Channel3 global interrupt DMA1 Channel4 global interrupt DMA1 Channel5 global interrupt DMA1 Channel6 global interrupt DMA1 Channel7 global interrupt ADC1 and ADC2 global interrupt USB High Priority or CAN TX interrupts USB Low Priority or CAN RX0 interrupts CAN RX1 interrupt CAN SCE interrupt EXTI Line[9:5] interrupts TIM1 Break interrupt TIM1 Update interrupt TIM1 Trigger and Commutation interrupts TIM1 Capture Compare interrupt TIM2 global interrupt TIM3 global interrupt TIM4 global interrupt I2C1 event interrupt I2C1 error interrupt I2C2 event interrupt I2C2 error interrupt 0x0000_004C 0x0000_0050 0x0000_0054 0x0000_0058 0x0000_005C 0x0000_0060 0x0000_0064 0x0000_0068 0x0000_006C 0x0000_0070 0x0000_0074 0x0000_0078 0x0000_007C 0x0000_0080 0x0000_0084 0x0000_0088 0x0000_008C 0x0000_0090 0x0000_0094 0x0000_0098 0x0000_009C 0x0000_00A0 0x0000_00A4 0x0000_00A8 0x0000_00AC 0x0000_00B0 0x0000_00B4 0x0000_00B8 0x0000_00BC 0x0000_00C0 0x0000_00C4 0x0000_00C8 Doc ID 13902 Rev 9 173/995 Interrupts and events RM0008 Table 53. Vector table for other STM32F10xxx devices (continued) Position Priority Type of priority Acronym Description Address 35 42 settable SPI1 SPI1 global interrupt 36 43 settable SPI2 SPI2 global interrupt 37 44 settable USART1 USART1 global interrupt 38 45 settable USART2 USART2 global interrupt 39 46 settable USART3 USART3 global interrupt 40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 41 48 settable RTCAlarm RTC alarm through EXTI line interrupt 42 49 settable USBWakeup USB wakeup from suspend through EXTI line interrupt 43 50 settable TIM8_BRK TIM8 Break interrupt 44 51 settable TIM8_UP TIM8 Update interrupt 45 52 settable TIM8_TRG_COM TIM8 Trigger and Commutation interrupts 46 53 settable TIM8_CC TIM8 Capture Compare interrupt 47 54 settable ADC3 ADC3 global interrupt 48 55 settable FSMC FSMC global interrupt 49 56 settable SDIO SDIO global interrupt 50 57 settable TIM5 TIM5 global interrupt 51 58 settable SPI3 SPI3 global interrupt 52 59 settable UART4 UART4 global interrupt 53 60 settable UART5 UART5 global interrupt 54 61 settable TIM6 TIM6 global interrupt 55 62 settable TIM7 TIM7 global interrupt 56 63 settable DMA2_Channel1 DMA2 Channel1 global interrupt 57 64 settable DMA2_Channel2 DMA2 Channel2 global interrupt 58 65 settable DMA2_Channel3 DMA2 Channel3 global interrupt 59 66 settable DMA2_Channel4_5 DMA2 Channel4 and DMA2 Channel5 global interrupts 0x0000_00CC 0x0000_00D0 0x0000_00D4 0x0000_00D8 0x0000_00DC 0x0000_00E0 0x0000_00E4 0x0000_00E8 0x0000_00EC 0x0000_00F0 0x0000_00F4 0x0000_00F8 0x0000_00FC 0x0000_0100 0x0000_0104 0x0000_0108 0x0000_010C 0x0000_0110 0x0000_0114 0x0000_0118 0x0000_011C 0x0000_0120 0x0000_0124 0x0000_0128 0x0000_012C 9.2 External interrupt/event controller (EXTI) The external interrupt/event controller consists of up to 20 edge detectors in connectivity line devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each input line can be independently configured to select the type (pulse or pending) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests 174/995 Doc ID 13902 Rev 9 RM0008 Interrupts and events 9.2.1 9.2.2 Main features The EXTI controller main features are the following: ● Independent trigger and mask on each interrupt/event line ● Dedicated status bit for each interrupt line ● Generation of up to 20 software event/interrupt requests ● Detection of external signal with pulse width lower than APB2 clock period. Refer to the electrical characteristics section of the datasheet for details on this parameter. Block diagram The block diagram is shown in Figure 20. Figure 20. External interrupt/event controller block diagram AMBA APB bus PCLK2 Peripheral interface 20 20 20 20 20 Interrupt mask register Pending request register To NVIC Interrupt 20 20 Controller . 20 Software interrupt event register 20 Rising trigger selection register Falling trigger selection register 20 20 9.2.3 Pulse 20 generator 20 Edge detect Input 20 circuit Line Event mask register ai15801 Wakeup event management The STM32F10xxx is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: ● enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex-M3 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. ● or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. Doc ID 13902 Rev 9 175/995 Interrupts and events RM0008 9.2.4 9.2.5 In connectivity line devices, Ethernet wakeup events also have the WFE wakeup capability. To use an external line as a wakeup event, refer to Section 9.2.4: Functional description. Functional description To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register. To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set An interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register. Hardware interrupt selection To configure the 20 lines as interrupt sources, use the following procedure: ● Configure the mask bits of the 20 Interrupt lines (EXTI_IMR) ● Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and EXTI_FTSR) ● Configure the enable and mask bits that control the NVIC IRQ channel mapped to the External Interrupt Controller (EXTI) so that an interrupt coming from one of the 20 lines can be correctly acknowledged. Hardware event selection To configure the 20 lines as event sources, use the following procedure: ● Configure the mask bits of the 20 Event lines (EXTI_EMR) ● Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR) Software interrupt/event selection The 20 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt. ● Configure the mask bits of the 20 Interrupt/Event lines (EXTI_IMR, EXTI_EMR) ● Set the required bit of the software interrupt register (EXTI_SWIER) External interrupt/event line mapping The 112 GPIOs are connected to the 16 external interrupt/event lines in the following manner: 176/995 Doc ID 13902 Rev 9 RM0008 Figure 21. External interrupt/event GPIO mapping EXTI0[3:0] bits in AFIO_EXTICR1 register PA0 PB0 PC0 PD0 PE0 PF0 PG0 EXTI0 EXTI1[3:0] bits in AFIO_EXTICR1 register PA1 PB1 PC1 PD1 PE1 PF1 PG1 EXTI1 Interrupts and events EXTI15[3:0] bits in AFIO_EXTICR4 register PA15 PB15 PC15 PD15 PE15 PF15 PG15 EXTI15 1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO clock should first be enabled. Refer to Section 6.3.7: APB2 peripheral clock enable register (RCC_APB2ENR) for low-, medium- and high-density devices and, to Section 7.3.7: APB2 peripheral clock enable register (RCC_APB2ENR) for connectivity line devices. The four other EXTI lines are connected as follows: ● EXTI line 16 is connected to the PVD output ● EXTI line 17 is connected to the RTC Alarm event ● EXTI line 18 is connected to the USB Wakeup event ● EXTI line 19 is connected to the Ethernet Wakeup event (available only in connectivity line devices) Doc ID 13902 Rev 9 177/995 Interrupts and events RM0008 9.3 9.3.1 EXTI registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 Reserved 15 14 13 12 11 10 9 MR15 MR14 MR13 MR12 MR11 MR10 MR9 rw rw rw rw rw rw rw 24 8 MR8 rw 23 7 MR7 rw 22 6 MR6 rw 21 5 MR5 rw 20 19 18 17 16 MR19 MR18 MR17 MR16 rw rw rw rw 4 3 2 1 0 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 MRx: Interrupt Mask on line x 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. 9.3.2 Event mask register (EXTI_EMR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 Reserved 15 14 13 12 11 10 MR15 MR14 MR13 MR12 MR11 MR10 rw rw rw rw rw rw 9 MR9 rw 24 8 MR8 rw 23 7 MR7 rw 22 6 MR6 rw 21 5 MR5 rw 20 19 18 17 16 MR19 MR18 MR17 MR16 rw rw rw rw 4 3 2 1 0 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 MRx: Event Mask on line x 0: Event request from Line x is masked 1: Event request from Line x is not masked Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. 178/995 Doc ID 13902 Rev 9 RM0008 Interrupts and events 9.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TR19 TR18 rw rw TR17 rw TR16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Note: Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line. Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. The external wakeup lines are edge triggered, no glitches must be generated on these lines. If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the pending bit will not be set. Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition. 9.3.4 Falling trigger selection register (EXTI_FTSR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TR19 TR18 rw rw TR17 rw TR16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 TRx: Falling trigger event configuration bit of line x 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line. Note: Bit 19 used in connectivity line devices and is reserved otherwise. Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines. If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the pending bit will not be set. Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition. Doc ID 13902 Rev 9 179/995 Interrupts and events RM0008 9.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SWIER SWIER SWIER SWIER 19 18 17 16 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 SWIERx: Software interrupt on line x Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the interrupt is enabled on this line on the EXTI_IMR and EXTI_EMR, an interrupt request is generated. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit). Note: Bit 19 used in connectivity line devices and is reserved otherwise. 9.3.6 Pending register (EXTI_PR) Address offset: 0x14 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PR19 PR18 PR17 PR16 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 PRx: Pending bit 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. 180/995 Doc ID 13902 Rev 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0008 Interrupts and events 9.3.7 EXTI register map The following table gives the EXTI register map and the reset values. Bits 19 in all registers, are used in connectivity line devices and is reserved otherwise. Table 54. External interrupt/event controller register map and reset values Offset Register 0x00 0x04 0x08 0x0C 0x10 0x14 EXTI_IMR Reset value EXTI_EMR Reset value EXTI_RTSR Reset value EXTI_FTSR Reset value EXTI_SWIER Reset value EXTI_PR Reset value Reserved Reserved Reserved Reserved Reserved Reserved MR[19:0] 00000000000000000000 MR[19:0] 00000000000000000000 TR[19:0] 00000000000000000000 TR[19:0] 00000000000000000000 SWIER[19:0] 00000000000000000000 PR[19:0] 00000000000000000000 Refer to Table 1 on page 41 for the register boundary addresses. Doc ID 13902 Rev 9 181/995 DMA controller (DMA) 10 DMA controller (DMA) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 10.1 DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests. 10.2 DMA main features ● 12 independently configurable channels (requests): 7 for DMA1 and 5 for DMA2 ● Each of the 12 channels is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. ● Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) ● Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. ● Support for circular buffer management ● 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel ● Memory-to-memory transfer ● Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers ● Access to Flash, SRAM, peripheral SRAM, APB1, APB2 and AHB peripherals as source and destination ● Programmable number of data to be transferred: up to 65536 The block diagram is shown in Figure 22. 182/995 Doc ID 13902 Rev 9 RM0008 DMA controller (DMA) Figure 22. DMA block diagram in connectivity line devices Co r t ex -M3 ICode DCode Sys tem FLITF DMA1 Ch.1 Ch.2 DMA Reset & clock control (RCC) Flash SRAM DMA Bus matrix Ch.7 Arbiter AHB Slave DMA2 Ch.1 Ch.2 Ch.5 DMA request DMA request Bridge 2 Bridge 1 APB1 APB2 ADC1 ADC2 USART1 SPI1 TIM1 GPIOA GPIOB GPIOC GPIOD GPIOE EXTI AFIO DAC SPI3/I2S PWR SPI2/I2S BKP IWDG CAN1 WWDG CAN2 RTC I2C2 TIM7 I2C1 TIM6 UART5 TIM5 UART4 TIM4 USART3 TIM3 USART2 TIM2 DMA Arbiter AHB Slave Ethernet MAC USB OTG FS 1. The DMA2 controller is available only in high-density and connectifity line devices. 2. SPI/I2S3, UART4, TIM5, TIM6, TIM7 and DAC DMA requests are available only in high-density and connectivity line devices. 3. ADC3, SDIO and TIM8 DMA requests are available only in high-density devices. ai15811 10.3 10.3.1 DMA functional description The DMA controller performs direct memory transfer by sharing the system bus with the Cortex™-M3 core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU. DMA transactions After an event, the peripheral sends a request signal to the DMA Controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA Controller. The peripheral releases its request as soon as it gets the Acknowledge from the DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller Doc ID 13902 Rev 9 183/995 DMA controller (DMA) RM0008 10.3.2 Note: 10.3.3 release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. In summary, each DMA transfer consists of three operations: ● The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register ● The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register ● The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed. Arbiter The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences. The priorities are managed in two stages: ● Software: each channel priority can be configured in the DMA_CCRx register. There are four levels: – Very high priority – High priority – Medium priority – Low priority ● Hardware: if 2 requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4. In high-density and connectivity line devices, the DMA1 controller has priority over the DMA2 controller. DMA channels Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register which contains the amount of data items to be transferred is decremented after each transaction. Programmable data sizes Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE and MSIZE bits in the DMA_CCRx register. Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During 184/995 Doc ID 13902 Rev 9 RM0008 DMA controller (DMA) Note: transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in noncircular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled. If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers (DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase. In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address vaules from the DMA_CPARx/DMA_CMARx registers. Channel configuration procedure The following sequence should be followed to configure a DMA channelx (where x is the channel number). 1. Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event. 2. Set the memory address in the DMA_CMARx register. The data will be written to or read from this memory after the peripheral event. 3. Configure the total number of data to be transferred in the DMA_CNDTRx register. After each peripheral event, this value will be decremented. 4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register 5. Configure data transfer direction, circular mode, peripheral & memory incremented mode, peripheral & memory data size, and interrupt after half and/or full transfer in the DMA_CCRx register 6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register. As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel. Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer Complete Interrupt Enable bit (TCIE) is set. Circular mode Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register. When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral. This mode is called Memory to Memory mode. Doc ID 13902 Rev 9 185/995 DMA controller (DMA) RM0008 If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. 10.3.4 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 55: Programmable data width & endian behavior (when bits PINC = MINC = 1). Table 55. Programmable data width & endian behavior (when bits PINC = MINC = 1) Number Source port width Destination port width of data items to transfer (NDT) Source content: address / data Transfer operations Destination content: address / data 8 8 8 16 8 32 16 8 16 16 16 32 32 8 32 16 32 32 @0x0 / B0 4 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1 3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2 4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 @0x0 / B0 4 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2 3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4 4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6 @0x0 / 00B0 @0x2 / 00B1 @0x4 / 00B2 @0x6 / 00B3 @0x0 / B0 4 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4 3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8 4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC @0x0 / 000000B0 @0x4 / 000000B1 @0x8 / 000000B2 @0xC / 000000B3 @0x0 / B1B0 4 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1 3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2 4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3 @0x0 / B0 @0x1 / B2 @0x2 / B4 @0x3 / B6 @0x0 / B1B0 4 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2 3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4 4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 @0x0 / B1B0 4 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4 3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8 4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC @0x0 / 0000B1B0 @0x4 / 0000B3B2 @0x8 / 0000B5B4 @0xC / 0000B7B6 @0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0 4 @0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1 @0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2 @0xC / BFBEBDBC 4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3 @0x0 / B0 @0x1 / B4 @0x2 / B8 @0x3 / BC @0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[7:0] @0x0 4 @0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[7:0] @0x1 @0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[7:0] @0x2 @0xC / BFBEBDBC 4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[7:0] @0x3 @0x0 / B1B0 @0x2 / B5B4 @0x4 / B9B8 @0x6 / BDBC @0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0 @0x0 / B3B2B1B0 4 @0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC Addressing an AHB peripheral that does not support byte or halfword write operations When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does 186/995 Doc ID 13902 Rev 9 RM0008 DMA controller (DMA) 10.3.5 10.3.6 not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: ● To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord ● To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with HSIZE = Byte Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit APB operation in the following manner: ● an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0 ● an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0 For instance, if you want to write the APB backup registers (16-bit registers aligned to a 32bit address boundary), you must configure the memory source size (MSIZE) to “16-bit” and the peripheral destination size (PSIZE) to “32-bit”. Error management A DMA transfer error can be generated by reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag (TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error interrupt enable bit (TEIE) in the DMA_CCRx register is set. Interrupts An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility. Table 56. DMA interrupt requests Interrupt event Half-transfer Transfer complete Transfer error Event flag HTIF TCIF TEIF Enable Control bit HTIE TCIE TEIE Note: In high-density devices, DMA2 Channel4 and DMA2 Channel5 interrupts are mapped onto the same interrupt vector. In connectivity line devices, DMA2 Channel4 and DMA2 Channel5 interrupts have separate interrupt vectors. All other DMA1 and DMA2 Channel interrupts have their own interrupt vector. Doc ID 13902 Rev 9 187/995 DMA controller (DMA) RM0008 10.3.7 DMA request mapping DMA1 controller The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and USARTx[1,2,3]) are simply logically ORed before entering DMA1, this means that only one request must be enabled at a time. Refer to Figure 23: DMA1 request mapping. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. Figure 23. DMA1 request mapping Peripheral request signals ADC1 TIM2_CH3 TIM4_CH1 HW request 1 SW trigger (MEM2MEM bit) Fixed hardware priority Channel 1 High priority USART3_TX TIM1_CH1 TIM2_UP TIM3_CH3 SPI1_RX USART3_RX TIM1_CH2 TIM3_CH4 TIM3_UP SPI1_TX USART1_TX TIM1_CH4 TIM1_TRIG TIM1_COM TIM4_CH2 SPI/I2S2_RX I2C2_TX USART1_RX TIM1_UP SPI/I2S2_TX TIM2_CH1 TIM4_CH3 I2C2_RX USART2_RX TIM1_CH3 TIM3_CH1 TIM3_TRIG I2C1_TX USART2_TX TIM2_CH2 TIM2_CH4 TIM4_UP I2C1_RX Channel 1 EN bit HW request 2 Channel 2 SW trigger (MEM2MEM bit) Channel 2 EN bit HW request 3 Channel 3 SW trigger (MEM2MEM bit) Channel 3 EN bit HW request 4 SW trigger (MEM2MEM bit) Channel 4 Channel 4 EN bit HW request 5 SW trigger (MEM2MEM bit) Channel 5 Channel 5 EN bit HW REQUEST 6 SW TRIGGER (MEM2MEM bit) Channel 6 Channel 6 EN bit HW request 7 SW trigger (MEM2MEM bit) Channel 7 Channel 7 EN bit internal DMA1 request Low priority Table 57 lists the DMA requests for each channel. 188/995 Doc ID 13902 Rev 9 RM0008 DMA controller (DMA) Table 57. Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 SPI/I2S ADC1 SPI1_RX SPI1_TX SPI/I2S2_RX SPI/I2S2_TX USART I2C USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX I2C2_TX I2C2_RX I2C1_TX I2C1_RX TIM1 TIM1_CH1 TIM1_CH2 TIM1_CH4 TIM1_TRIG TIM1_COM TIM1_UP TIM1_CH3 TIM2 TIM2_CH3 TIM2_UP TIM2_CH1 TIM2_CH2 TIM2_CH4 TIM3 TIM3_CH3 TIM3_CH4 TIM3_UP TIM3_CH1 TIM3_TRIG TIM4 TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_UP Note: DMA2 controller The 5 requests from the peripherals (TIMx[5,6,7,8], ADC3, SPI/I2S3, UART4, DAC_Channel[1,2]and SDIO) are simply logically ORed before entering to the DMA2, this means that only one request must be enabled at a time. Refer to Figure 24: DMA2 request mapping. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. The DMA2 controller and its relative requests are available only in high-density and connectivity line devices. Doc ID 13902 Rev 9 189/995 DMA controller (DMA) RM0008 Figure 24. DMA2 request mapping Peripheral request signals Fixed hardware priority TIM5_CH4 TIM5_TRIG TIM8_CH3 TIM8_UP SPI/I2S3_RX TIM8_CH4 TIM8_TRIG TIM8_COM TIM5_CH3 TIM5_UP SPI/I2S3_TX TIM8_CH1 UART4_RX TIM6_UP/DAC_Channel1 TIM5_CH2 SDIO TIM7_UP/DAC_Channel2 HW request 1 SW trigger (MEM2MEM bit) HIGH PRIORITY Channel 1 Channel 1 EN bit HW request 2 Channel 2 SW trigger (MEM2MEM bit) Channel 2 EN bit HW request 3 Channel 3 SW trigger (MEM2MEM bit) Channel 3 EN bit HW request 4 Channel 4 SW trigger (MEM2MEM bit) internal DMA2 request ADC3 TIM8_CH2 TIM5_CH1 UART4_TX Channel 4 EN bit HW request 5 SW trigger (MEM2MEM bit) Channel 5 LOW PRIORITY Channel 5 EN bit Table 58 lists the DMA2 requests for each channel. Table 58. Summary of DMA2 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 ADC3(1) SPI/I2S3 SPI/I2S3_RX SPI/I2S3_TX UART4 SDIO(1) UART4_RX SDIO TIM5 TIM5_CH4 TIM5_TRIG TIM5_CH3 TIM5_UP TIM5_CH2 TIM6/ DAC_Channel1 TIM6_UP/ DAC_Channel1 TIM7/ DAC_Channel2 TIM7_UP/ DAC_Channel2 TIM8(1) TIM8_CH3 TIM8_UP TIM8_CH4 TIM8_TRIG TIM8_COM TIM8_CH1 1. ADC3, SDIO and TIM8 DMA requests are available only in high-density devices. Channel 5 ADC3 UART4_TX TIM5_CH1 TIM8_CH2 190/995 Doc ID 13902 Rev 9 RM0008 DMA controller (DMA) 10.4 Note: 10.4.1 DMA registers Refer to Section 1.1 on page 37 for a list of abbreviations used in the register descriptions. In the following registers, all bits relative to channel6 and channel7 are not relevant for DMA2 since it has only 5 channels. DMA interrupt status register (DMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 Reserved 15 14 13 TEIF4 HTIF4 TCIF4 r r r 28 12 GIF4 r 27 26 25 TEIF7 HTIF7 TCIF7 r r r 11 10 9 TEIF3 HTIF3 TCIF3 r r r 24 GIF7 r 8 GIF3 r 23 22 21 TEIF6 HTIF6 TCIF6 r r r 7 6 5 TEIF2 HTIF2 TCIF2 r r r 20 GIF6 r 4 GIF2 r 19 18 17 TEIF5 HTIF5 TCIF5 r r r 3 2 1 TEIF1 HTIF1 TCIF1 r r r 16 GIF5 r 0 GIF1 r Bits 31:28 Reserved, always read as 0. Bits 27, 23, 19, 15, TEIFx: Channel x transfer error flag (x = 1 ..7) 11, 7, 3 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel x 1: A transfer error (TE) occurred on channel x Bits 26, 22, 18, 14, HTIFx: Channel x half transfer flag (x = 1 ..7) 10, 6, 2 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel x 1: A half transfer (HT) event occurred on channel x Bits 25, 21, 17, 13, TCIFx: Channel x transfer complete flag (x = 1 ..7) 9, 5, 1 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel x 1: A transfer complete (TC) event occurred on channel x Bits 24, 20, 16, 12, GIFx: Channel x global interrupt flag (x = 1 ..7) 8, 4, 0 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel x 1: A TE, HT or TC event occurred on channel x Doc ID 13902 Rev 9 191/995 DMA controller (DMA) RM0008 10.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 Reserved 15 14 13 12 CTEIF CHTIF CTCIF CGIF 4 4 4 4 w w w w 27 26 25 CTEIF CHTIF CTCIF 7 7 7 w w w 11 10 9 CTEIF CHTIF CTCIF 3 3 3 w w w 24 CGIF 7 w 8 CGIF 3 w 23 22 21 CTEIF CHTIF CTCIF 6 6 6 w w w 7 6 5 CTEIF CHTIF CTCIF 2 2 2 w w w 20 CGIF 6 w 4 CGIF 2 w 19 18 17 CTEIF CHTIF CTCIF 5 5 5 w w w 3 2 1 CTEIF CHTIF CTCIF 1 1 1 w w w 16 CGIF 5 w 0 CGIF 1 w Bits 31:28 Reserved, always read as 0. Bits 27, 23, 19, 15, CTEIFx: Channel x transfer error clear (x = 1 ..7) 11, 7, 3 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register Bits 26, 22, 18, 14, CHTIFx: Channel x half transfer clear (x = 1 ..7) 10, 6, 2 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register Bits 25, 21, 17, 13, CTCIFx: Channel x transfer complete clear (x = 1 ..7) 9, 5, 1 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register Bits 24, 20, 16, 12, CGIFx: Channel x global interrupt clear (x = 1 ..7) 8, 4, 0 This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register 192/995 Doc ID 13902 Rev 9 RM0008 DMA controller (DMA) 10.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1 ..7) Address offset: 0x08 + 20d × Channel number Reset value: 0x0000 0000 31 30 29 28 15 14 Res. MEM2 MEM rw 13 12 PL[1:0] rw rw 27 26 11 10 MSIZE[1:0] rw rw 25 24 23 22 21 20 19 18 17 16 Reserved 9 8 7 6 5 4 3 2 1 0 PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN rw rw rw rw rw rw rw rw rw rw Bits 31:15 Reserved, always read as 0. Bit 14 MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled Bits 13:12 PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high Bits 11:10 MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bits 9:8 PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bit 7 MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled Bit 6 PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled Doc ID 13902 Rev 9 193/995 DMA controller (DMA) RM0008 Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled Bit 1 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled Bit 0 EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled 10.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1 ..7) Address offset: 0x0C + 20d × Channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NDT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, always read as 0. Bits 15:0 NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 194/995 Doc ID 13902 Rev 9 RM0008 DMA controller (DMA) 10.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7) Address offset: 0x10 + dx20 × Channel number Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address. 10.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1 ..7) Address offset: 0x14 + dx20 × Channel number Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address. Doc ID 13902 Rev 9 195/995 31 30 29 28 TEIF7 27 HTIF7 26 TCIF7 25 GIF7 24 TEIF6 23 HTIF6 22 TCIF6 21 GIF6 20 TEIF5 19 HTIF5 18 TCIF5 17 GIF5 16 TEIF4 15 HTIF4 14 TCIF4 13 GIF4 12 TEIF3 11 HTIF3 10 TCIF3 9 GIF3 8 TEIF2 7 HTIF2 6 TCIF2 5 GIF2 4 TEIF1 3 HTIF1 2 TCIF1 1 GIF1 0 CTEIF7 CHTIF 7 CTCIF7 CGIF7 CTEIF6 CHTIF 6 CTCIF6 CGIF6 CTEIF5 CHTIF 5 CTCIF5 CGIF5 CTEIF4 CHTIF 4 CTCIF4 CGIF4 CTEIF3 CHTIF 3 CTCIF3 CGIF3 CTEIF2 CHTIF 2 CTCIF2 CGIF2 CTEIF1 CHTIF 1 CTCIF1 CGIF1 DMA controller (DMA) RM0008 MEM2MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN MEM2MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN 10.4.7 DMA register map The following table gives the DMA register map and the reset values. Table 59. DMA register map and reset values Offset Register 0x000 DMA_ISR Reset value Reserved 0000000000000000000000000000 0x004 DMA_IFCR Reset value Reserved 0000000000000000000000000000 0x008 DMA_CCR1 Reserved PL [1:0] M SIZE [1:0] PSIZ E [1:0] 0x00C 0x010 0x014 0x018 Reset value DMA_CNDTR1 Reset value DMA_CPAR1 Reset value DMA_CMAR1 Reset value 000000000000000 Reserved NDT[15:0] 0000000000000000 PA[31:0] 00000000000000000000000000000000 MA[31:0] 00000000000000000000000000000000 Reserved DMA_CCR2 0x01C Reserved PL [1:0] M SIZE [1:0] PSIZ E [1:0] 0x020 0x024 0x028 0x02C Reset value DMA_CNDTR2 Reset value DMA_CPAR2 Reset value DMA_CMAR2 Reset value 000000000000000 Reserved NDT[15:0] 0000000000000000 PA[31:0] 00000000000000000000000000000000 MA[31:0] 00000000000000000000000000000000 Reserved 0x030 DMA_CCR3 Reserved PL [1:0] M SIZE [1:0] PSIZ E [1:0] 0x034 0x038 0x03C 0x040 Reset value DMA_CNDTR3 Reset value DMA_CPAR3 Reset value DMA_CMAR3 Reset value 000000000000000 Reserved NDT[15:0] 0000000000000000 PA[31:0] 00000000000000000000000000000000 MA[31:0] 00000000000000000000000000000000 Reserved 0x044 DMA_CCR4 Reserved PL [1:0] M SIZE [1:0] PSIZ E [1:0] 0x048 Reset value DMA_CNDTR4 Reset value Reserved 000000000000000 NDT[15:0] 0000000000000000 MEM2MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN MEM2MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN 196/995 Doc ID 13902 Rev 9 0 RM0008 DMA controller (DMA) EN MEM2MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN Table 59. DMA register map and reset values (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Offset Register 0x04C 0x050 0x054 DMA_CPAR4 Reset value DMA_CMAR4 Reset value PA[31:0] 00000000000000000000000000000000 MA[31:0] 00000000000000000000000000000000 Reserved TCIE HTIE TEIE DIR CIRC PINC MINC MEM2MEM 0x058 DMA_CCR5 Reserved PL [1:0] M SIZE [1:0] PSIZ E [1:0] 0x05C 0x060 0x064 0x068 Reset value DMA_CNDTR5 Reset value DMA_CPAR5 Reset value DMA_CMAR5 Reset value 000000000000000 Reserved NDT[15:0] 0000000000000000 PA[31:0] 00000000000000000000000000000000 MA[31:0] 00000000000000000000000000000000 Reserved DMA_CCR6 0x06C Reserved PL [1:0] M SIZE [1:0] PSIZ E [1:0] 0x070 0x074 0x078 0x07C Reset value DMA_CNDTR6 Reset value DMA_CPAR6 Reset value DMA_CMAR6 Reset value 000000000000000 Reserved NDT[15:0] 0000000000000000 PA[31:0] 00000000000000000000000000000000 MA[31:0] 00000000000000000000000000000000 Reserved 0x080 DMA_CCR7 Reserved PL [1:0] M SIZE [1:0] PSIZ E [1:0] 0x084 0x088 0x08C 0x090 Reset value DMA_CNDTR7 Reset value DMA_CPAR7 Reset value DMA_CMAR7 Reset value 000000000000000 Reserved NDT[15:0] 0000000000000000 PA[31:0] 00000000000000000000000000000000 MA[31:0] 00000000000000000000000000000000 Reserved MEM2MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN Refer to Table 1 on page 41 for the register boundary addresses. Doc ID 13902 Rev 9 197/995 Analog-to-digital converter (ADC) 11 Analog-to-digital converter (ADC) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to the whole STM32F10xxx family, unless otherwise specified. 11.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it measure signals from 16 external and two internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register. The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined high or low thresholds. The ADC input clock is generated from the PCLK2 clock divided by a prescaler and it must not exceed 14 MHz, refer to Figure 8: Clock tree for low-, medium- and high-density devices, and to Figure 11: Clock tree for connectivity line devices. 198/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) 11.2 Note: ADC main features ● 12-bit resolution ● Interrupt generation at End of Conversion, End of Injected conversion and Analog watchdog event ● Single and continuous conversion modes ● Scan mode for automatic conversion of channel 0 to channel ‘n’ ● Self-calibration ● Data alignment with in-built data coherency ● Channel by channel programmable sampling time ● External trigger option for both regular and injected conversion ● Discontinuous mode ● Dual mode (on devices with 2 ADCs or more) ● ADC conversion time: – STM32F103xx performance line devices: 1 µs at 56 MHz (1.17 µs at 72 MHz) – STM32F101xx access line devices: 1 µs at 28 MHz (1.55 µs at 36 MHz) – STM32F102xx USB access line devices: 1.2 µs at 48 MHz – STM32F105xx and STM32F107xx devices: 1 µs at 56 MHz (1.17 µs at 72 MHz) ● ADC supply requirement: 2.4 V to 3.6 V ● ADC input range: VREF-  VIN  VREF+ ● DMA request generation during regular channel conversion The block diagram of the ADC is shown in Figure 25. VREF-,if available (depending on package), must be tied to VSSA. 11.3 ADC functional description Figure 25 shows a single ADC block diagrams and Table 60 gives the ADC pin description. Doc ID 13902 Rev 9 199/995 Analog-to-digital converter (ADC) RM0008 Figure 25. Single ADC block diagram Flags End of conversion EOC End of injected conversion JEOC Analog watchdog event AWD Interrupt enable bits EOCIE JEOCIE AWDIE Analog watchdog Compare Result High Threshold (12 bits) Low Threshold (12 bits) ADC Interrupt to NVIC Address/data bus VREF+ VREFVDDA VSSA ADCx_IN0 Analog MUX Injected data registers (4 x 16 bits) Regular data register (16 bits) DMA request ADCx_IN1 ADCx_IN15 GPIO Ports Temp. sensor VREFINT up to 4 up to 16 Injected channels Regular channels Analog to digital converter ADCCLK JEXTSEL[2:0] bits TIM1_TRGO TIM1_CH4 TIM2_TRGO TIM2_CH1 TIM3_CH4 TIM4_TRGO JEXTRIG bit Start trigger (injected group) From ADC prescaler EXTI_15 TIM8_CH4(2) ADCx-ETRGINJ_REMAP bit EXTRI G bit EXTSEL[2:0] bits TIM1_CH1 TIM1_CH2 TIM1_CH3 TIM2_CH2 TIM3_TRGO TIM4_CH4 Start trigger (regular group) EXTI_11 TIM8_TRGO(2) ADCx_ETRGREG_REMAP bit JEXTSEL[2:0] bits TIM1_TRGO TIM1_CH4 TIM4_CH3 TIM8_CH2 TIM8_CH4 TIM5_TRGO TIM5_CH4 JEXTRIG bit Start trigger (injected group) EXTSEL[2:0] bits TIM3_CH1 TIM2_CH3 TIM1_CH3 TIM8_CH1 TIM8_TRGO TIM5_CH1 TIM5_CH3 EXTRIG bit Start trigger (regular group) Triggers for ADC3(1) ai14802d 1. ADC3 has regular and injected conversion triggers different from those of ADC1 and ADC2. 2. TIM8_CH4 and TIM8_TRGO with their corresponding remap bits exist only in High-density products. 200/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) Table 60. ADC pins Name Signal type VREF+ Input, analog reference positive VDDA VREFVSSA ADCx_IN[15:0] Input, analog supply Input, analog reference negative Input, analog supply ground Analog input signals Remarks The higher/positive reference voltage for the ADC, 2.4 V  VREF+  VDDA Analog power supply equal to VDD and 2.4 V VDDA VDD (3.6 V) The lower/negative reference voltage for the ADC, VREF- = VSSA Ground for analog power supply equal to VSS 16 analog input channels 11.3.1 11.3.2 11.3.3 ADC on-off control The ADC can be powered-on by setting the ADON bit in the ADC_CR2 register. When the ADON bit is set for the first time, it wakes up the ADC from Power Down mode. Conversion starts when ADON bit is set for a second time by software after ADC power-up time (tSTAB). You can stop conversion and put the ADC in power down mode by resetting the ADON bit. In this mode the ADC consumes almost no power (only a few µA). ADC clock The ADCCLK clock provided by the Clock Controller is synchronous with the PCLK2 (APB2 clock). The RCC controller has a dedicated programmable prescaler for the ADC clock, refer to Low-, medium- and high-density reset and clock control (RCC) on page 74 for more details. Channel selection There are 16 multiplexed channels. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions which can be done on any channel and in any order. For instance, it is possible to do the conversion in the following order: Ch3, Ch8, Ch2, Ch2, Ch0, Ch2, Ch2, Ch15. ● The regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRx registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register. ● The injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the new chosen group. Doc ID 13902 Rev 9 201/995 Analog-to-digital converter (ADC) RM0008 Note: 11.3.4 11.3.5 11.3.6 Temperature sensor/VREFINT internal channels The Temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage VREFINT is connected to ADCx_IN17. These two internal channels can be selected and converted as injected or regular channels. The sensor and VREFINT are only available on the master ADC1 peripheral. Single conversion mode In Single conversion mode the ADC does one conversion. This mode is started either by setting the ADON bit in the ADC_CR2 register (for a regular channel only) or by external trigger (for a regular or injected channel), while the CONT bit is 0. Once the conversion of the selected channel is complete: ● If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set – and an interrupt is generated if the EOCIE is set. ● If an injected channel was converted: – The converted data is stored in the 16-bit ADC_DRJ1 register – The JEOC (End Of Conversion Injected) flag is set – and an interrupt is generated if the JEOCIE bit is set. The ADC is then stopped. Continuous conversion mode In continuous conversion mode ADC starts another conversion as soon as it finishes one. This mode is started either by external trigger or by setting the ADON bit in the ADC_CR2 register, while the CONT bit is 1. After each conversion: ● If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set – An interrupt is generated if the EOCIE is set. ● If an injected channel was converted: – The converted data is stored in the 16-bit ADC_DRJ1 register – The JEOC (End Of Conversion Injected) flag is set – An interrupt is generated if the JEOCIE bit is set. Timing diagram As shown in Figure 26, the ADC needs a stabilization time of tSTAB before it starts converting accurately. After the start of ADC conversion and after 14 clock cycles, the EOC flag is set and the 16-bit ADC Data register contains the result of the conversion. 202/995 Doc ID 13902 Rev 9 RM0008 Figure 26. Timing diagram ADC_CLK SET ADON ADC power on Start 1st conversion ADC EOC tSTAB ADC Conversion Conversion Time (total conv time) Analog-to-digital converter (ADC) Start next conversion Next ADC Conversion 11.3.7 Software resets EOC bit Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by using the AWDIE bit in the ADC_CR1 register. The threshold value is independent of the alignment selected by the ALIGN bit in the ADC_CR2 register. The comparison is done before the alignment (see Section 11.5). The analog watchdog can be enabled on one or more channels by configuring the ADC_CR1 register as shown in Table 61. Figure 27. Analog watchdog guarded area Analog voltage High threshold Low threshold Guarded area HTR LTR Table 61. Analog watchdog channel selection Channels to be guarded by analog watchdog ADC_CR1 register control bits (x = don’t care) AWDSGL bit AWDEN bit JAWDEN bit None All injected channels x 0 0 0 0 1 All regular channels 0 1 0 All regular and injected channels 0 1 1 Single(1) injected channel 1 0 1 Single(1) regular channel 1 1 0 Single (1) regular or injected channel 1 1 1 1. Selected by AWDCH[4:0] bits Doc ID 13902 Rev 9 203/995 Analog-to-digital converter (ADC) RM0008 11.3.8 11.3.9 Note: Note: Scan mode This mode is used to scan a group of analog channels. Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular channels) or in the ADC_JSQR (for injected channels). A single conversion is performed for each channel of the group. After each end of conversion the next channel of the group is converted automatically. If the CONT bit is set, conversion does not stop at the last selected group channel but continues again from the first selected group channel. If the DMA bit is set, the direct memory access controller is used to transfer the converted data of regular group channels to SRAM after each EOC. The injected channel converted data is always stored in the ADC_JDRx registers. Injected channel management Triggered injection To use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the ADC_CR1 register. 1. Start conversion of a group of regular channels either by external trigger or by setting the ADON bit in the ADC_CR2 register. 2. If an external injected trigger occurs during the regular group channel conversion, the current conversion is reset and the injected channel sequence is converted in Scan once mode. 3. Then, the regular group channel conversion is resumed from the last interrupted regular conversion. If a regular event occurs during an injected conversion, it doesn’t interrupt it but the regular sequence is executed at the end of the injected sequence. Figure 28 shows the timing diagram. When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 28 ADC clock cycles (that is two conversions with a 1.5 clock-period sampling time), the minimum interval between triggers must be 29 ADC clock cycles. Auto-injection If the JAUTO bit is set, then the injected group channels are automatically converted after the regular group channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRx and ADC_JSQR registers. In this mode, external trigger on injected channels must be disabled. If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted. For ADC clock prescalers ranging from 4 to 8, a delay of 1 ADC clock period is automatically inserted when switching from regular to injected sequence (respectively injected to regular). When the ADC clock prescaler is set to 2, the delay is 2 ADC clock periods. It is not possible to use both auto-injected and discontinuous modes simultaneously. 204/995 Doc ID 13902 Rev 9 RM0008 Figure 28. Injected conversion latency Analog-to-digital converter (ADC) ADC clock Inj. event Reset ADC SOC max latency(1) 1. The maximum latency value can be found in the electrical characteristics of the STM32F101xx and STM32F103xx datasheets. 11.3.10 Discontinuous mode Note: Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n <=8) which is a part of the sequence of conversions selected in the ADC_SQRx registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADC_CR1 register. When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register. Example: n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 1st trigger: sequence converted 0, 1, 2 2nd trigger: sequence converted 3, 6, 7 3rd trigger: sequence converted 9, 10 and an EOC event generated 4th trigger: sequence converted 0, 1, 2 When a regular group is converted in discontinuous mode, no rollover will occur. When all sub groups are converted, the next trigger starts conversion of the first sub-group. In the example above, the 4th trigger reconverts the 1st sub-group channels 0, 1 and 2. Injected group This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to convert the sequence selected in the ADC_JSQR register, channel by channel, after an external trigger event. When an external trigger occurs, it starts the next channel conversions selected in the ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register. Doc ID 13902 Rev 9 205/995 Analog-to-digital converter (ADC) RM0008 Example: n = 1, channels to be converted = 1, 2, 3 1st trigger: channel 1 converted 2nd trigger: channel 2 converted 3rd trigger: channel 3 converted and EOC and JEOC events generated 4th trigger: channel 1 Note: 1 When all injected channels are converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel 1. 2 It is not possible to use both auto-injected and discontinuous modes simultaneously. 3 The user must avoid setting discontinuous mode for both regular and injected groups together. Discontinuous mode must be enabled only for one group conversion. 11.4 Calibration The ADC has an built-in self calibration mode. Calibration significantly reduces accuracy errors due to internal capacitor bank variations. During calibration, an error-correction code (digital word) is calculated for each capacitor, and during all subsequent conversions, the error contribution of each capacitor is removed using this code. Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is over, the CAL bit is reset by hardware and normal conversion can be performed. It is recommended to calibrate the ADC once at power-on. The calibration codes are stored in the ADC_DR as soon as the calibration phase ends. Note: 1 It is recommended to perform a calibration after each power-up. 2 Before starting a calibration the ADC must have been in power-off state (ADON bit = ‘0’) for at least two ADC clock cycles. Figure 29. Calibration timing diagram CLK CAL ADC Conversion Calibration ongoing tCAL Calibration Reset by Hardware Normal ADC Conversion 11.5 Data alignment ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion. Data can be left or right aligned as shown in Figure 30. and Figure 31. The injected group channels converted data value is decreased by the user-defined offset written in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit is the extended sign value. For regular group channels no offset is subtracted so only twelve bits are significant. 206/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) Figure 30. Right alignment of data Injected group SEXT SEXT SEXT SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Regular group 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 31. Left alignment of data Injected group SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 Regular group D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 00 11.6 Channel-by-channel programmable sample time ADC samples the input voltage for a number of ADC_CLK cycles which can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sample time. The total conversion time is calculated as follows: Tconv = Sampling time + 12.5 cycles Example: With an ADCCLK = 14 MHz and a sampling time of 1.5 cycles: Tconv = 1.5 + 12.5 = 14 cycles = 1µs 11.7 Note: Conversion on external trigger Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXTTRIG control bit is set then external events are able to trigger a conversion. The EXTSEL[2:0] and JEXTSEL[2:0] control bits allow the application to select decide which out of 8 possible events can trigger conversion for the regular and injected groups. When an external trigger is selected for ADC regular or injected conversion, only the rising edge of the signal can start the conversion. Doc ID 13902 Rev 9 207/995 Analog-to-digital converter (ADC) RM0008 Table 62. External trigger for regular channels for ADC1 and ADC2 Source Type EXTSEL[2:0] TIM1_CC1 event 000 TIM1_CC2 event TIM1_CC3 event TIM2_CC2 event TIM3_TRGO event TIM4_CC4 event 001 Internal signal from on-chip 010 timers 011 100 101 EXTI line11/TIM8_TRGO event(1)(2) SWSTART External pin/Internal signal from on-chip timers 110 Software control bit 111 1. The TIM8_TRGO event exists only in High-density devices. 2. The selection of the external trigger EXTI line11 or TIM8_TRGO event for regular channels is done through configuration bits ADC1_ETRGREG_REMAP and ADC2_ETRGREG_REMAP for ADC1 and ADC2, respectively. Table 63. External trigger for injected channels for ADC1 and ADC2 Source Connection type JEXTSEL[2:0] TIM1_TRGO event TIM1_CC4 event TIM2_TRGO event TIM2_CC1 event TIM3_CC4 event TIM4_TRGO event EXTI line15/TIM8_CC4 event(1)(2) JSWSTART 000 001 Internal signal from on-chip 010 timers 011 100 101 External pin/Internal signal from on-chip timers 110 Software control bit 111 1. The TIM8_CC4 event exists only in High-density devices. 2. The selection of the external trigger EXTI line15 or TIM8_CC4 event for injected channels is done through configuration bits ADC1_ETRGINJ_REMAP and ADC2_ETRGINJ_REMAP for ADC1 and ADC2, respectively. 208/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) Table 64. External trigger for regular channels for ADC3 Source Connection type TIM3_CC1 event TIM2_CC3 event TIM1_CC3 event TIM8_CC1 event TIM8_TRGO event TIM5_CC1 event TIM5_CC3 event SWSTART 000 001 010 Internal signal from on-chip timers 011 100 101 110 Software control bit 111 EXTSEL[2:0] Table 65. External trigger for injected channels for ADC3 Source Connection type TIM1_TRGO event 000 TIM1_CC4 event 001 TIM4_CC3 event TIM8_CC2 event TIM8_CC4 event TIM5_TRGO event 010 Internal signal from on-chip timers 011 100 101 TIM5_CC4 event 110 JSWSTART Software control bit 111 JEXTSEL[2:0] The software source trigger events can be generated by setting a bit in a register (SWSTART and JSWSTART in ADC_CR2). A regular group conversion can be interrupted by an injected trigger. 11.8 Note: DMA request Since converted regular channels value are stored in a unique data register, it is necessary to use DMA for conversion of more than one regular channel. This avoids the loss of data already stored in the ADC_DR register. Only the end of conversion of a regular channel generates a DMA request, which allows the transfer of its converted data from the ADC_DR register to the destination location selected by the user. Only ADC1 and ADC3 have this DMA capability. ADC2-converted data can be transferred in dual ADC mode using DMA thanks to master ADC1. Doc ID 13902 Rev 9 209/995 Analog-to-digital converter (ADC) RM0008 11.9 Note: Note: Dual ADC mode In devices with two ADCs or more, dual ADC mode can be used (see Figure 32). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0] bits in the ADC1_CR1 register. In dual mode, when configuring conversion to be triggered by an external event, the user must set the trigger for the master only and set a software trigger for the slave to prevent spurious triggers to start unwanted slave conversion. However, external triggers must be enabled on both master and slave ADCs. The following six possible modes are implemented: – Injected simultaneous mode – Regular simultaneous mode – Fast interleaved mode – Slow interleaved mode – Alternate trigger mode – Independent mode It is also possible to use the previous modes combined in the following ways: – Injected simultaneous mode + Regular simultaneous mode – Regular simultaneous mode + Alternate trigger mode – Injected simultaneous mode + Interleaved mode In dual ADC mode, to read the slave converted data on the master data register, the DMA bit must be enabled even if it is not used to transfer converted regular channel data. 210/995 Doc ID 13902 Rev 9 RM0008 Figure 32. Dual ADC block diagram(1) Analog-to-digital converter (ADC) Address/data bus Regular data register (1(216bibtsit)s) Injected data registers (4 x 16 bits) Regular channels injected channels ADC2 (Slave) internal triggers Regular data register (16 bits)(2) Injected data registers (4 x 16 bits) ADCx_IN0 ADCx_IN1 ADCx_IN15 GPIO Ports Temp. sensor VREFINT EXTI_11 Start trigger mux (regular group) Regular channels Injected channels Dual mode control ADC1 (Master) EXTI_15 Start trigger mux (injected group) 1. External triggers are present on ADC2 but are not shown for the purposes of this diagram. 2. In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted data over the entire 32 bits. Doc ID 13902 Rev 9 211/995 Analog-to-digital converter (ADC) RM0008 11.9.1 Note: Note: Injected simultaneous mode This mode converts an injected channel group. The source of external trigger comes from the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits in the ADC1_CR2 register). A simultaneous trigger is provided to ADC2. Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). At the end of conversion event on ADC1 or ADC2: ● The converted data is stored in the ADC_JDRx registers of each ADC interface. ● An JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the ADC1/ADC2 injected channels are all converted. In simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longest of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Figure 33. Injected simultaneous mode on 4 channels ADC2 ADC1 CH0 CH3 Trigger CH1 CH2 CH2 CH1 CH3 CH0 Sampling Conversion End of injected conversion on ADC1 and ADC2 11.9.2 Note: Note: Regular simultaneous mode This mode is performed on a regular channel group. The source of the external trigger comes from the regular group mux of ADC1 (selected by the EXTSEL[2:0] bits in the ADC1_CR2 register). A simultaneous trigger is provided to the ADC2. Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). At the end of conversion event on ADC1 or ADC2: ● A 32-bit DMA transfer request is generated (if DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword. ● An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when ADC1/ADC2 regular channels are all converted. In regular simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longest of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. 212/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) Figure 34. Regular simultaneous mode on 16 channels ADC1 ADC2 CH0 CH15 CH1 CH14 CH2 CH13 CH3 ... CH12 ... Trigger CH15 CH0 Sampling Conversion End of conversion on ADC1 and ADC2 11.9.3 Note: 11.9.4 Note: Fast interleaved mode This mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux of ADC1. After an external trigger occurs: ● ADC2 starts immediately and ● ADC1 starts after a delay of 7 ADC clock cycles. If CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are continuously converted. After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword. The maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap between ADC1 and ADC2 sampling phases in the event that they convert the same channel. Figure 35. Fast interleaved mode on 1 channel in continuous conversion mode ADC2 ADC1 End of conversion on ADC2 CH0 ... CH0 CH0 ... CH0 Trigger End of conversion on ADC1 7 ADCCLK cycles Sampling Conversion Slow interleaved mode This mode can be started only on a regular channel group (only one channel). The source of external trigger comes from regular channel mux of ADC1. After external trigger occurs: ● ADC2 starts immediately and ● ADC1 starts after a delay of 14 ADC clock cycles. ● ADC2 starts after a second delay of 14 ADC cycles, and so on. The maximum sampling time allowed is <14 ADCCLK cycles to avoid an overlap with the next conversion. Doc ID 13902 Rev 9 213/995 Analog-to-digital converter (ADC) RM0008 Note: 11.9.5 After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword. A new ADC2 start is automatically generated after 28 ADC clock cycles CONT bit can not be set in the mode since it continuously converts the selected regular channel. The application must ensure that no external trigger for injected channel occurs when interleaved mode is enabled. Figure 36. Slow interleaved mode on 1 channel End of conversion on ADC2 ADC2 ADC1 Trigger CH0 CH0 CH0 CH0 End of conversion on ADC1 14 ADCCLK cycles 28 ADCCLK cycles Sampling Conversion Alternate trigger mode This mode can be started only on an injected channel group. The source of external trigger comes from the injected group mux of ADC1. ● When the 1st trigger occurs, all injected group channels in ADC1 are converted. ● When the 2nd trigger arrives, all injected group channels in ADC2 are converted ● and so on. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are converted. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are converted. If another external trigger occurs after all injected group channels have been converted then the alternate trigger process restarts by converting ADC1 injected group channels. Figure 37. Alternate trigger: injected channel group of each ADC 1st trigger 3rd trigger EOC, JEOC EOC, JEOC on ADC1 on ADC1 (n)th trigger Sampling Conversion ADC1 ... ADC2 2nd trigger EOC, JEOC EOC, JEOC on ADC2 on ADC2 4th trigger (n+1)th trigger 214/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) If the injected discontinuous mode is enabled for both ADC1 and ADC2: ● When the 1st trigger occurs, the first injected channel in ADC1 is converted. ● When the 2nd trigger arrives, the first injected channel in ADC2 are converted ● and so on.... A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are converted. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are converted. If another external trigger occurs after all injected group channels have been converted then the alternate trigger process restarts. Figure 38. Alternate trigger: 4 injected channels (each ADC) in discontinuous model 1st trigger 3rd trigger 5th trigger 7th trigger JEOC on ADC1 Sampling Conversion ADC1 ADC2 2nd trigger 4th trigger 6th trigger JEOC on ADC2 8th trigger 11.9.6 11.9.7 Note: 11.9.8 Note: Independent mode In this mode the dual ADC synchronization is bypassed and each ADC interfaces works independently. Combined regular/injected simultaneous mode It is possible to interrupt simultaneous conversion of a regular group to start simultaneous conversion of an injected group. In combined regular/injected simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longest of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Combined regular simultaneous + alternate trigger mode It is possible to interrupt regular group simultaneous conversion to start alternate trigger conversion of an injected group. Figure 39 shows the behavior of an alternate trigger interrupting a regular simultaneous conversion. The injected alternate conversion is immediately started after the injected event arrives. If regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of both (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion. In combined regular simultaneous + alternate trigger mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longest of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Doc ID 13902 Rev 9 215/995 Analog-to-digital converter (ADC) Figure 39. Alternate + Regular simultaneous 1st trig RM0008 ADC1 reg ADC1 inj ADC2 reg ADC2 inj CH0 CH3 CH1 CH5 CH2 CH0 CH6 CH2 CH3 CH6 CH7 CH0 CH3 CH4 CH7 CH8 synchro not lost 2nd trig If a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored. Figure 40 shows the behavior in this case (2nd trig is ignored). Figure 40. Case of trigger occurring during injected conversion 1st trig 3rd trig ADC1 reg ADC1 inj ADC2 reg ADC2 inj CH0 CH3 CH1 CH5 CH2 CH0 CH6 2nd trig CH2 CH3 CH6 CH7 CH0 CH3 CH7 CH4 CH0 CH8 4th trig 11.9.9 Note: Combined injected simultaneous + interleaved It is possible to interrupt an interleaved conversion with an injected event. In this case the interleaved conversion is interrupted and the injected conversion starts, at the end of the injected sequence the interleaved conversion is resumed. Figure 41 shows the behavior using an example. When the ADC clock prescaler is set to 4, the interleaved mode does not recover with evenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6 ADC clock periods, instead of 7 clock periods followed by 7 clock periods. Figure 41. Interleaved single channel with injected sequence CH11, CH12 ADC1 ADC2 CH0 CH0 CH0 CH0 CH0 CH0 Sampling Conversion Trigger CH11 CH12 CH12 CH11 CH0 CH0 CH0 CH0 216/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) 11.10 Note: Temperature sensor The temperature sensor can be used to measure the ambient temperature (TA) of the device. The temperature sensor is internally connected to the ADCx_IN16 input channel which is used to convert the sensor output voltage into a digital value. The recommended sampling time for the temperature sensor is 17.1 µs. The block diagram of the temperature sensor is shown in Figure 42. When not in use, this sensor can be put in power down mode. The TSVREFE bit must be set to enable both internal channels: ADCx_IN16 (temperature sensor) and ADCx_IN17 (VREFINT) conversion. The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to 45 °C from one chip to another). The internal temperature sensor is more suited to applications that detect temperature variations instead of absolute temperatures. If accurate temperature readings are needed, an external temperature sensor part should be used. Figure 42. Temperature sensor and VREFINT channel block diagram TSVREFE control bit Address/data bus TEMPERATURE SENSOR INTERNAL POWER BLOCK VSENSE VREFINT ADCx_IN16 ADC1 ADCx_IN17 converted data Doc ID 13902 Rev 9 217/995 Analog-to-digital converter (ADC) RM0008 Note: Reading the temperature To use the sensor: 1. Select the ADCx_IN16 input channel. 2. Select a sample time of 17.1 µs 3. Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the temperature sensor from power down mode. 4. Start the ADC conversion by setting the ADON bit (or by external trigger). 5. Read the resulting VSENSE data in the ADC data register 6. Obtain the temperature using the following formula: Temperature (in °C) = {(V25 - VSENSE) / Avg_Slope} + 25. Where, V25 = VSENSE value for 25° C and Avg_Slope = Average Slope for curve between Temperature vs. VSENSE (given in mV/° C or µV/ °C). Refer to the Electrical characteristics section for the actual values of V25 and Avg_Slope. The sensor has a startup time after waking from power down mode before it can output VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADON and TSVREFE bits should be set at the same time. 11.11 Note: ADC interrupts An interrupt can be produced on end of conversion for regular and injected groups and when the analog watchdog status bit is set. Separate interrupt enable bits are available for flexibility. ADC1 and ADC2 interrupts are mapped onto the same interrupt vector. ADC3 interrupts are mapped onto a separate interrupt vector. Two other flags are present in the ADC_SR register, but there is no interrupt associated with them: ● JSTRT (Start of conversion for injected group channels) ● STRT (Start of conversion for regular group channels) Table 66. ADC interrupts Interrupt event End of conversion regular group End of conversion injected group Analog watchdog status bit is set Event flag EOC JEOC AWD Enable Control bit EOCIE JEOCIE AWDIE 218/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) 11.12 ADC registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. 11.12.1 ADC status register (ADC_SR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved STRT JSTRT JEOC EOC AWD Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 31:5 Reserved, must be kept cleared. Bit 4 STRT: Regular channel Start flag This bit is set by hardware when regular channel conversion starts. It is cleared by software. 0: No regular channel conversion started 1: Regular channel conversion has started Bit 3 JSTRT: Injected channel Start flag This bit is set by hardware when injected channel group conversion starts. It is cleared by software. 0: No injected group conversion started 1: Injected group conversion has started Bit 2 JEOC: Injected channel end of conversion This bit is set by hardware at the end of all injected group channel conversion. It is cleared by software. 0: Conversion is not complete 1: Conversion complete Bit 1 EOC: End of conversion This bit is set by hardware at the end of a group channel conversion (regular or injected). It is cleared by software or by reading the ADC_DR. 0: Conversion is not complete 1: Conversion complete Bit 0 AWD: Analog watchdog flag This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software. 0: No Analog watchdog event occurred 1: Analog watchdog event occurred Doc ID 13902 Rev 9 219/995 Analog-to-digital converter (ADC) RM0008 11.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 Reserved AWDEN JAWDEN Reserved 15 14 13 DISCNUM[2:0] rw rw rw Res. 12 11 10 9 JDISCE DISC N EN JAUTO AWD SGL rw rw rw rw rw rw Res. 8 7 6 5 4 SCAN JEOC IE AWDIE EOCIE rw rw rw rw rw 19 18 17 16 DUALMOD[3:0] rw rw rw rw 3 2 1 0 AWDCH[4:0] rw rw rw rw Bits 31:24 Reserved, must be kept cleared. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software. 0: Analog watchdog disabled on regular channels 1: Analog watchdog enabled on regular channels Bit 22 JAWDEN: Analog watchdog enable on injected channels This bit is set/reset by software. 0: Analog watchdog disabled on injected channels 1: Analog watchdog enabled on injected channels Bits 21:20 Reserved, must be kept cleared. Bits 19:16 DUALMOD[3:0]: Dual mode selection These bits are written by software to select the operating mode. 0000: Independent mode. 0001: Combined regular simultaneous + injected simultaneous mode 0010: Combined regular simultaneous + alternate trigger mode 0011: Combined injected simultaneous + fast interleaved mode 0100: Combined injected simultaneous + slow Interleaved mode 0101: Injected simultaneous mode only 0110: Regular simultaneous mode only 0111: Fast interleaved mode only 1000: Slow interleaved mode only 1001: Alternate trigger mode only Note: These bits are reserved in ADC2 and ADC3. In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. 000: 1 channel 001: 2 channels ....... 111: 8 channels 220/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) Bit 12 JDISCEN: Discontinuous mode on injected channels This bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Bit 11 DISCEN: Discontinuous mode on regular channels This bit set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic Injected Group conversion This bit set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. 0: Automatic injected group conversion disabled 1: Automatic injected group conversion enabled Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode This bit set and cleared by software to enable/disable the analog watchdog on the channel identified by the AWDCH[4:0] bits. 0: Analog watchdog enabled on all channels 1: Analog watchdog enabled on a single channel Bit 8 SCAN: Scan mode This bit is set and cleared by software to enable/disable Scan mode. In Scan mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted. 0: Scan mode disabled 1: Scan mode enabled Note: An EOC or JEOC interrupt is generated only on the end of conversion of the last channel if the corresponding EOCIE or JEOCIE bit is set Bit 7 JEOCIE: Interrupt enable for injected channels This bit is set and cleared by software to enable/disable the end of conversion interrupt for injected channels. 0: JEOC interrupt disabled 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Bit 6 AWDIE: Analog watchdog interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. In Scan mode if the watchdog thresholds are crossed, scan is aborted only if this bit is enabled. 0: Analog watchdog interrupt disabled 1: Analog watchdog interrupt enabled Bit 5 EOCIE: Interrupt enable for EOC This bit is set and cleared by software to enable/disable the End of Conversion interrupt. 0: EOC interrupt disabled 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set. Doc ID 13902 Rev 9 221/995 Analog-to-digital converter (ADC) RM0008 Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits These bits are set and cleared by software. They select the input channel to be guarded by the Analog watchdog. 00000: ADC analog input Channel0 00001: ADC analog input Channel1 .... 01111: ADC analog input Channel15 10000: ADC analog input Channel16 10001: ADC analog input Channel17 Other values reserved. Note: ADC1 analog inputs Channel16 and Channel17 are internally connected to the temperature sensor and to VREFINT, respectively. ADC2 analog inputs Channel16 and Channel17 are internally connected to VSS. ADC3 analog inputs Channel9, Channel14, Channel15, Channel16 and Channel17 are connected to VSS. 11.12.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 Reserved 15 JEXTT RIG rw Res. 14 13 12 11 JEXTSEL[2:0] ALIGN rw rw rw rw 10 9 Reserved Res. 24 23 22 21 20 TSVRE SWST JSWST EXTT FE ART ART RIG rw rw rw rw 8 7 6 5 4 DMA Reserved rw Res. 19 18 17 16 EXTSEL[2:0] Res. rw 3 RST CAL rw rw rw 2 1 0 CAL CONT ADON rw rw rw Bits 31:24 Reserved, must be kept cleared. Bit 23 TSVREFE: Temperature sensor and VREFINT enable This bit is set and cleared by software to enable/disable the temperature sensor and VREFINT channel. In devices with dual ADCs this bit is present only in ADC1. 0: Temperature sensor and VREFINT channel disabled 1: Temperature sensor and VREFINT channel enabled Bit 22 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as conversion starts. It starts a conversion of a group of regular channels if SWSTART is selected as trigger event by the EXTSEL[2:0] bits. 0: Reset state 1: Starts conversion of regular channels Bit 21 JSWSTART: Start conversion of injected channels This bit is set by software and cleared by software or by hardware as soon as the conversion starts. It starts a conversion of a group of injected channels (if JSWSTART is selected as trigger event by the JEXTSEL[2:0] bits. 0: Reset state 1: Starts conversion of injected channels 222/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) Bit 20 EXTTRIG: External trigger conversion mode for regular channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 19:17 EXTSEL[2:0]: External event select for regular group These bits select the external event used to trigger the start of conversion of a regular group: For ADC1 and ADC2, the assigned triggers are: 000: Timer 1 CC1 event 001: Timer 1 CC2 event 010: Timer 1 CC3 event 011: Timer 2 CC2 event 100: Timer 3 TRGO event 101: Timer 4 CC4 event 110: EXTI line11/TIM8_TRGO event (TIM8_TRGO is available only in high-density devices) 111: SWSTART For ADC3, the assigned triggers are: 000: Timer 3 CC1 event 001: Timer 2 CC3 event 010: Timer 1 CC3 event 011: Timer 8 CC1 event 100: Timer 8 TRGO event 101: Timer 5 CC1 event 110: Timer 5 CC3 event 111: SWSTART Bit 16 Reserved, must be kept cleared. Bit 15 JEXTTRIG: External trigger conversion mode for injected channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of an injected channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Doc ID 13902 Rev 9 223/995 Analog-to-digital converter (ADC) RM0008 Bits 14:12 JEXTSEL[2:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected group: For ADC1 and ADC2 the assigned triggers are: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 2 TRGO event 011: Timer 2 CC1 event 100: Timer 3 CC4 event 101: Timer 4 TRGO event 110: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in High-density devices) 111: JSWSTART For ADC3 the assigned triggers are: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 4 CC3 event 011: Timer 8 CC2 event 100: Timer 8 CC4 event 101: Timer 5 TRGO event 110: Timer 5 CC4 event 111: JSWSTART Bit 11 ALIGN: Data alignment This bit is set and cleared by software. Refer to Figure 30.and Figure 31. 0: Right Alignment 1: Left Alignment Bits 10:9 Reserved, must be kept cleared. Bit 8 DMA: Direct memory access mode This bit is set and cleared by software. Refer to the DMA controller chapter for more details. 0: DMA mode disabled 1: DMA mode enabled Note: Only ADC1 and ADC3 can generate a DMA request. Bits 7:4 Reserved, must be kept cleared. Bit 3 RSTCAL: Reset calibration This bit is set by software and cleared by hardware. It is cleared after the calibration registers are initialized. 0: Calibration register initialized. 1: Initialize calibration register. Note: If RSTCAL is set when conversion is ongoing, additional cycles are required to clear the calibration registers. Bit 2 CAL: A/D Calibration This bit is set by software to start the calibration. It is reset by hardware after calibration is complete. 0: Calibration completed 1: Enable calibration 224/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If set conversion takes place continuously till this bit is reset. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D converter ON / OFF This bit is set and cleared by software. If this bit holds a value of zero and a 1 is written to it then it wakes up the ADC from Power Down state. Conversion starts when this bit holds a value of 1 and a 1 is written to it. The application should allow a delay of tSTAB between power up and start of conversion. Refer to Figure 26. 0: Disable ADC conversion/calibration and go to power down mode. 1: Enable ADC and to start conversion Note: If any other bit in this register apart from ADON is changed at the same time, then conversion is not triggered. This is to prevent triggering an erroneous conversion. 11.12.4 ADC sample time register 1 (ADC_SMPR1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 Reserved Res. 15 14 13 12 11 10 9 SMP 15_0 SMP14[2:0] SMP13[2:0] rw rw rw rw rw rw rw 24 23 22 21 20 19 18 17 16 SMP17[2:0] SMP16[2:0] SMP15[2:1] rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 SMP12[2:0] SMP11[2:0] SMP10[2:0] rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept cleared. Bits 23:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Note: ADC1 analog inputs Channel16 and Channel17 are internally connected to the temperature sensor and to VREFINT, respectively. ADC2 analog input Channel16 and Channel17 are internally connected to VSS. ADC3 analog inputs Channel14, Channel15, Channel16 and Channel17 are connected to VSS. Doc ID 13902 Rev 9 225/995 Analog-to-digital converter (ADC) RM0008 11.12.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] Res. rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMP 5_0 SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept cleared. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Note: ADC3 analog input Channel9 is connected to VSS. 11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) Address offset: 0x14-0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved JOFFSETx[11:0] Res. rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept cleared. Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. The conversion result can be read from in the ADC_JDRx registers. 226/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) 11.12.7 ADC watchdog high threshold register (ADC_HTR) Address offset: 0x24 Reset value: 0x0000 0FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HT[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept cleared. Bits 11:0 HT[11:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. 11.12.8 ADC watchdog low threshold register (ADC_LTR) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LT[11:0] Res rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept cleared. Bits 11:0 LT[11:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. 11.12.9 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved L[3:0] SQ16[4:1] Res. rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQ16_0 SQ15[4:0] SQ14[4:0] SQ13[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Doc ID 13902 Rev 9 227/995 Analog-to-digital converter (ADC) RM0008 Bits 31:24 Reserved, must be kept cleared. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions ..... 1111: 16 conversions Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 16th in the conversion sequence. Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence 11.12.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SQ12[4:0] SQ11[4:0] SQ10[4:1] Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQ10_ 0 SQ9[4:0] SQ8[4:0] SQ7[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept cleared. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 12th in the sequence to be converted. Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence 228/995 Doc ID 13902 Rev 9 RM0008 Analog-to-digital converter (ADC) 11.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SQ6[4:0] SQ5[4:0] SQ4[4:1] Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept cleared. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted. Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence 11.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved JL[1:0] JSQ4[4:1] rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JSQ4_0 JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:22 Reserved, must be kept cleared. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. 00: 1 conversion 01: 2 conversions 10: 3 conversions 11: 4 conversions Doc ID 13902 Rev 9 229/995 Analog-to-digital converter (ADC) RM0008 Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence These bits are written by software with the channel number (0..17) assigned as the 4th in the sequence to be converted. Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels are converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10 00011 00011 00111 00010 means that a scan conversion will convert the following channel sequence: 7, 3, 3. (not 2, 7, 3) Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JDATA[15:0] r r r r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept cleared. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 30 and Figure 31. 11.12.14 ADC regular data register (ADC_DR) Address offset: 0x4C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC2DATA[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA[15:0] r r r r r r r r r r r r r r r r Bits 31:16 ADC2DATA[15:0]: ADC2 data – In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to Section 11.9: Dual ADC mode – In ADC2 and ADC3: these bits are not used Bits 15:0 DATA[15:0]: Regular data These bits are read only. They contain the conversion result from the regular channels. The data is left or right-aligned as shown in Figure 30 and Figure 31. 230/995 Doc ID 13902 Rev 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 STRT 4 JSTRT 3 JEOC 2 EOC 1 AWD 0 RM0008 Analog-to-digital converter (ADC) RSTCAL CAL CONT ADON 11.12.15 ADC register map The following table summarizes the ADC registers. Table 67. ADC register map and reset values Offset Register TSVREFE AWDEN SWSTART JAWDEN JSWSTART Reserved EXTTRIG 0x00 0x04 ADC_SR Reset value ADC_CR1 Reset value Reserved 00 Reserved 00000 JDISCEN DISCEN JAUTO AWD SGL SCAN JEOC IE AWDIE EOCIE DUALMOD DISC [3:0] NUM [2:0] AWDCH[4:0] 00000000000000000000 ALIGN Reserved DMA Reserved JEXTTRIG 0x08 ADC_CR2 Reserved EXTSEL [2:0] JEXTSEL [2:0] Reserved 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 Reset value 0000000 00000 0 0000 ADC_SMPR1 Sample time bits SMPx_x Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SMPR2 Sample time bits SMPx_x Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JOFR1 Reset value Reserved JOFFSET1[11:0] 000000000000 ADC_JOFR2 Reset value Reserved JOFFSET2[11:0] 000000000000 ADC_JOFR3 Reset value Reserved JOFFSET3[11:0] 000000000000 ADC_JOFR4 Reset value Reserved JOFFSET4[11:0] 000000000000 ADC_HTR Reset value Reserved HT[11:0] 000000000000 ADC_LTR Reset value Reserved LT[11:0] 000000000000 ADC_SQR1 Reset value Reserved L[3:0] Regular channel sequence SQx_x bits 000000000000000000000000 Reserved Reserved ADC_SQR2 Regular channel sequence SQx_x bits Reset value 000000000000000000000000000000 ADC_SQR3 Regular channel sequence SQx_x bits Reset value 000000000000000000000000000000 ADC_JSQR Reset value Reserved JL[1:0] Injected channel sequence JSQx_x bits 0000000000000000000000 Doc ID 13902 Rev 9 231/995 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Analog-to-digital converter (ADC) RM0008 Table 67. ADC register map and reset values (continued) Offset Register 0x3C 0x40 0x44 0x48 0x4C ADC_JDR1 Reset value ADC_JDR2 Reset value ADC_JDR3 Reset value ADC_JDR4 Reset value ADC_DR Reset value Reserved JDATA[15:0] 0000000000000000 Reserved JDATA[15:0] 0000000000000000 Reserved JDATA[15:0] 0000000000000000 Reserved JDATA[15:0] 0000000000000000 ADC2DATA[15:0] Regular DATA[15:0] 00000000000000000000000000000000 Refer to Table 1 on page 41 for the register boundary addresses. 232/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) 12 Digital-to-analog converter (DAC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to connectivity line and high-density STM32F101xx and STM32F103xx devices only. 12.1 12.2 DAC introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operation. An input reference pin VREF+ is available for better resolution. DAC main features ● Two DAC converters: one output channel each ● 8-bit or 12-bit monotonic output ● Left or right data alignment in 12-bit mode ● Synchronized update capability ● Noise-wave generation ● Triangular-wave generation ● Dual DAC channel independent or simultaneous conversions ● DMA capability for each channel ● External triggers for conversion ● Input voltage reference VREF+ The block diagram of a DAC channel is shown in Figure 43 and the pin description is given in Table 68. Doc ID 13902 Rev 9 233/995 Digital-to-analog converter (DAC) Figure 43. DAC channel block diagram RM0008 Note: EXTI_9 Trigger selectorx SWTR IGx TIM2_T RGO TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO(1) TSELx[2:0] bits DAC control register DMAENx DHRx 12- bit Control logicx DM A req ue stx TENx LFSRx trianglex MAMPx[3:0] bits WAVENx[1:0] bits 12-bit VDDA VSSA VR EF+ DO Rx 12-bit Digital-to-analog converterx DAC_ OU Tx ai14708c 1. In connectivity line devices, the TIM8_TRGO trigger is replaced by TIM3_TRGO . Table 68. DAC pins Name Signal type Remarks VREF+ VDDA VSSA DAC_OUTx Input, analog reference The higher/positive reference voltage for the DAC, positive 2.4 V  VREF+  VDDA (3.3 V) Input, analog supply Analog power supply Input, analog supply ground Ground for analog power supply Analog output signal DAC channelx analog output Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is automatically connected to the analog converter output (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN). 234/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) 12.3 12.3.1 Note: 12.3.2 12.3.3 DAC functional description DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time tWAKEUP. The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset. DAC output buffer enable The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. Each DAC channel output buffer can be enabled and disabled using the corresponding BOFFx bit in the DAC_CR register. DAC data format Depending on the selected configuration mode, the data has to be written in the specified register as described below: ● Single DAC channelx, there are three possibilities: – 8-bit right alignment: user has to load data into DAC_DHR8Rx [7:0] bits (stored into DHRx[11:4] bits) – 12-bit left alignment: user has to load data into DAC_DHR12Lx [15:4] bits (stored into DHRx[11:0] bits) – 12-bit right alignment: user has to load data into DAC_DHR12Rx [11:0] bits (stored into DHRx[11:0] bits) Depending on the loaded DAC_DHRyyyx register, the data written by the user will be shifted and stored into the DHRx (Data Holding Registerx, that are internal non-memory-mapped registers). The DHRx register will then be loaded into the DORx register either automatically, by software trigger or by an external event trigger. Doc ID 13902 Rev 9 235/995 Digital-to-analog converter (DAC) RM0008 Figure 44. Data registers in single DAC channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 ● Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0] bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits) – 12-bit left alignment: data for DAC channel1 to be loaded into DAC_DHR12LD [15:4] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12LD [31:20] bits (stored into DHR2[11:0] bits) – 12-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR12RD [11:0] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12LD [27:16] bits (stored into DHR2[11:0] bits) Depending on the loaded DAC_DHRyyyD register, the data written by the user will be shifted and stored into the DHR1 and DHR2 (Data Holding Registers, that are internal nonmemory-mapped registers). The DHR1 and DHR2 registers will then be loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger. Figure 45. Data registers in dual DAC channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14709 12.3.4 DAC conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write on DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD). Data stored into the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later. When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time of tSETTLING that depends on the power supply voltage and the analog output load. 236/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) Figure 46. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK DHR 0x1AC DOR 0x1AC tSETTLING Output voltage available on DAC_OUT pin ai14711b 12.3.5 12.3.6 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+. The analog output voltages on each DAC channel pin are determined by the following equation: DACoutput = VR E F  D-----O-----R--4095 DAC trigger selection If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possible events will trigger conversion as shown in Table 69. Table 69. External triggers Source Type Timer 6 TRGO event Timer 3 TRGO event in connectivity line devices or Timer 8 TRGO in high-density devices Timer 7 TRGO event Timer 5 TRGO event Internal signal from on-chip timers Timer 2 TRGO event Timer 4 TRGO event EXTI line9 External pin SWTRIG Software control bit TSEL[2:0] 000 001 010 011 100 101 110 111 Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register is transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs. If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Doc ID 13902 Rev 9 237/995 Digital-to-analog converter (DAC) RM0008 Note: 1 TSELx[2:0] bit cannot be changed when the ENx bit is set. 2 When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-toDAC_DORx register transfer. 12.3.7 DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests. A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred to the DAC_DORx register. In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel. The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement of the last request, then the new request will not be serviced and no error is reported 12.3.8 Noise generation In order to generate a variable-amplitude pseudonoise, a Linear Feedback Shift Register is available. The DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in the LFSR is 0xAAA. This register is updated, three APB1 clock cycles after each trigger event, following a specific calculation algorithm. Figure 47. DAC LFSR register calculation algorithm XOR X6 X4 X X0 X 12 11 10 9 8 7 6 5 4 3 2 1 0 12 NOR ai14713b The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register. If LFSR is 0x0000, a ‘1’ is injected into it (antilock-up mechanism). It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits. 238/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) Figure 48. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK DHR 0x00 DOR 0xAAA 0xD55 SWTRIG ai14714 Note: 12.3.9 DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register. The triangle counter is incremented while it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on. It is possible to reset triangle wave generation by resetting WAVEx[1:0] bits. Figure 49. DAC triangle wave generation -!-0X;=MAXAMPLITUDE $!#?$(2XBASEVALUE )NCREMENTATION $ECREMENTATION $!#?$(2XBASEVALUE  AIC Doc ID 13902 Rev 9 239/995 Digital-to-analog converter (DAC) RM0008 Figure 50. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK DHR 0xABE DOR 0xABE 0xABF 0xAC0 SWTRIG ai14714 Note: 1 DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. 2 MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed. 12.4 12.4.1 Dual DAC channel conversion To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time. Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed. All modes are described in the paragraphs below. Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits ● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three APB1 clock cycles later). When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB1 clock cycles later). 240/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) 12.4.2 12.4.3 12.4.4 Independent trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits ● Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits ● Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD or DHR8RD) When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated. Independent trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits ● Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values in the MAMP1[3:0] and MAMP2[3:0] bits ● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated. Independent trigger with same triangle generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits ● Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value in the MAMPx[3:0] bits ● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into Doc ID 13902 Rev 9 241/995 Digital-to-analog converter (DAC) RM0008 12.4.5 12.4.6 12.4.7 DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. Independent trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits ● Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits ● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register part and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. Simultaneous software start To configure the DAC in this conversion mode, the following sequence is required: ● Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively. Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits ● Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively (after three APB1 clock cycles). 242/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) 12.4.8 Simultaneous trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits ● Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits ● Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or DHR8RD) When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated. 12.4.9 Simultaneous trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits ● Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values using the MAMP1[3:0] and MAMP2[3:0] bits ● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated. 12.4.10 Simultaneous trigger with same triangle generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits ● Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value using the MAMPx[3:0] bits ● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is Doc ID 13902 Rev 9 243/995 Digital-to-analog converter (DAC) RM0008 added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. 12.4.11 Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits ● Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits ● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is updated. At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated. 12.5 DAC registers 12.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Reserved DMA EN2 MAMP2[3:0] rw rw rw rw rw 15 14 13 12 11 10 9 8 Reserved DMA EN1 MAMP1[3:0] rw rw rw rw rw 23 22 WAVE2[1:0] rw rw 7 6 WAVE1[1:0] rw rw 21 20 19 TSEL2[2:0] rw rw rw 5 4 3 TSEL1[2:0] rw rw rw 18 17 16 TEN2 BOFF2 EN2 rw rw rw 2 1 0 TEN1 BOFF1 EN1 rw rw rw Bits 31:29 Reserved. Bit 28 DMAEN2: DAC channel2 DMA enable This bit is set and cleared by software. 0: DAC channel2 DMA mode disabled 1: DAC channel2 DMA mode enabled 244/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) Bit 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ Triangle Amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ Triangle Amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ Triangle Amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ Triangle Amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ Triangle Amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ Triangle Amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ Triangle Amplitude equal to 2047  1011: Unmask bits[11:0] of LFSR/ Triangle Amplitude equal to 4095 Bit 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density devices 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9 111: Software trigger Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) Bit 18 TEN2: DAC channel2 trigger enable This bit set and cleared by software to enable/disable DAC channel2 trigger 0: DAC channel2 trigger disabled and data written into DAC_DHRx register is transferred one APB1 clock cycle later to the DAC_DOR2 register. 1: DAC channel2 trigger enabled and data transfer from DAC_DHRx register is transferred three APB1 clock cycles later to the DAC_DOR2 register. Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to DAC_DOR2 register transfer. Bit 17 BOFF2: DAC channel2 output buffer disable This bit set and cleared by software to enable/disable DAC channel2 output buffer. 0: DAC channel2 output buffer enabled 1: DAC channel2 output buffer disabled Bit 16 EN2: DAC channel2 enable This bit set and cleared by software to enable/disable DAC channel2. 0: DAC channel2 disabled 1: DAC channel2 enabled Bits 15:13 Reserved. Doc ID 13902 Rev 9 245/995 Digital-to-analog converter (DAC) RM0008 Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software. 0: DAC channel1 DMA mode disabled 1: DAC channel1 DMA mode enabled Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ Triangle Amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ Triangle Amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ Triangle Amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ Triangle Amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ Triangle Amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ Triangle Amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ Triangle Amplitude equal to 2047  1011: Unmask bits[11:0] of LFSR/ Triangle Amplitude equal to 4095 Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 000: Timer 6 TRGO event 001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density devices 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9 111: Software trigger Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) Bit 2 TEN1: DAC channel1 trigger enable This bit set and cleared by software to enable/disable DAC channel1 trigger 0: DAC channel1 trigger disabled and data written into DAC_DHRx register is transferred one APB1 clock cycle later to the DAC_DOR1 register. 1: DAC channel1 trigger enabled and data transfer from DAC_DHRx register is transferred three APB1 clock cycles later to the DAC_DOR1 register. Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to DAC_DOR1 register transfer. Bit 1 BOFF1: DAC channel1 output buffer disable This bit set and cleared by software to enable/disable DAC channel1 output buffer. 0: DAC channel1 output buffer enabled 1: DAC channel1 output buffer disabled 246/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) Bit 0 EN1: DAC channel1 enable This bit set and cleared by software to enable/disable DAC channel1. 0: DAC channel1 disabled 1: DAC channel1 enabled 12.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SWTRI SWTRI G2 G1 w w Bits 31:2 Reserved. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value is loaded to the DAC_DOR2 register. Bit 0 SWTRIG1: DAC channel1 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value is loaded to the DAC_DOR1 register. 12.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved. Bit 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel1. Doc ID 13902 Rev 9 247/995 Digital-to-analog converter (DAC) RM0008 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Reserved Bits 31:16 Reserved. Bit 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel1. Bits 3:0 Reserved. 12.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC1DHR[7:0] rw rw rw rw rw rw rw rw Bits 31:8 Reserved. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel1. 12.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 248/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) 12.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Reserved Bits 31:16 Reserved. Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 3:0 Reserved. 12.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC2DHR[7:0] rw rw rw rw rw rw rw rw Bits 31:8 Reserved. Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel2. 12.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:28 Reserved. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Doc ID 13902 Rev 9 249/995 Digital-to-analog converter (DAC) RM0008 Bits 15:12 Reserved. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel1. 12.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Reserved Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 19:16 Reserved. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel1. Bits 3:0 Reserved. 12.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC2DHR[7:0] DACC1DHR[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel2. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel1. 250/995 Doc ID 13902 Rev 9 RM0008 Digital-to-analog converter (DAC) 12.5.12 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC1DOR[11:0] r r r r r r r r r r r r Bits 31:12 Reserved. Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read only, they contain data output for DAC channel1. 12.5.13 DAC channel2 data output register (DAC_DOR2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC2DOR[11:0] r r r r r r r r r r r r Bits 31:12 Reserved. Bit 11:0 DACC2DOR[11:0]: DAC channel2 data output These bits are read only, they contain data output for DAC channel2. Doc ID 13902 Rev 9 251/995 31 30 29 DMAEN2 28 27 26 25 24 23 22 21 20 19 TEN2 18 BOFF2 17 EN2 16 15 14 13 DMAEN1 12 11 10 9 8 7 6 5 4 3 TEN1 2 BOFF1 1 EN1 0 Digital-to-analog converter (DAC) RM0008 SWTRIG2 SWTRIG1 12.5.14 DAC register map The following table summarizes the DAC registers. Table 70. DAC register map Offset Register 0x00 DAC_CR Reserved MAMP2[3:0] WAVE 2[2:0] TSEL2[2:0] Reserved MAMP1[3:0] WAVE 1[2:0] TSEL1 [2:0] Reset value 00000000 00000 0000000000000 DAC_SWTRIG 0x04 R Reserved 0x08 0x0C 0x10 0x14 0x18 0x1C Reset value DAC_DHR12R 1 Reset value DAC_DHR12L 1 Reset value DAC_DHR8R1 Reset value DAC_DHR12R 2 Reset value DAC_DHR12L 2 Reset value DAC_DHR8R2 Reserved Reserved Reserved Reserved Reserved Reserved 00 DACC1DHR[11:0] 000000000000 DACC1DHR[11:0] 000000000000 Reserved DACC1DHR[7:0] 00000000 DACC2DHR[11:0] 000000000000 DACC2DHR[11:0] 000000000000 Reserved DACC2DHR[7:0] 0x20 0x24 0x28 0x2C 0x30 DAC_DHR12R D Reset value Reserved DACC2DHR[11:0] 0000000 00000 DAC_DHR12L D DACC2DHR[11:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DAC_DHR8RD Reset value Reserved DAC_DOR1 Reset value Reserved DAC_DOR2 Reset value Reserved Reserved DACC1DHR[11:0] 000000000000 DACC1DHR[11:0] 000000000000 Reserved DACC2DHR[7:0] DACC1DHR[7:0] 0000000000000000 DACC1DOR[11:0] 000000000000 DACC2DOR[11:0] 000000000000 Note: Refer to Table 1 on page 41 for the register boundary addresses. 252/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) 13 Advanced-control timers (TIM1&TIM8) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. Low- and medium-density STM32F103xx devices, and the STM32F105xx/STM32F107xx connectivity line devices, contain one advanced-control timer (TIM1) whereas high-density STM32F103xx devices feature two advance-control timers (TIM1 and TIM8). 13.1 TIM1&TIM8 introduction The advanced-control timers (TIM1&TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The advanced-control (TIM1&TIM8) and general-purpose (TIMx) timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 13.3.20. 13.2 TIM1&TIM8 main features TIM1&TIM8 timer features include: ● 16-bit up, down, up/down auto-reload counter. ● 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65535. ● Up to 4 independent channels for: – Input Capture – Output Compare – PWM generation (Edge and Center-aligned Mode) – One-pulse mode output ● Complementary outputs with programmable dead-time ● Synchronization circuit to control the timer with external signals and to interconnect several timers together. ● Repetition counter to update the timer registers only after a given number of cycles of the counter. ● Break input to put the timer’s output signals in reset state or in a known state. Doc ID 13902 Rev 9 253/995 Advanced-control timers (TIM1&TIM8) RM0008 ● Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare – Break input ● Supports incremental (quadrature) encoder and hall-sensor cicuitry for positioning purposes ● Trigger input for external clock or cycle-by-cycle current management 254/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 51. Advanced-control timer block diagram TIMx_ETR Internal Clock (CK_INT) CK_TIM18 from RCC ETR ETRP Polarity Selection & Edge Detector & Prescaler Input Filter ITR0 ITR1 ITR2 ITR3 ITR TRC TI1F_ED ETRF Trigger Controller TRGO TGI TRGI Slave Mode Controller to other timers to DAC/ADC Reset, Enable, Up/Down, Count TIMx_CH1 TIMx_CH2 TIMx_CH3 TIMx_CH4 TIMx_BKIN XOR TI1 TI2 TI3 TI4 TI1FP1 TI2FP2 Encoder Interface U AutoReload Register Input Filter & Edge detector Input Filter & Edge detector Input Filter & Edge detector Input Filter & Edge detector Stop, Clear or Up/Down CK_PSC PSC Prescaler CK_CNT TI1FP1 TI1FP2 CC1I IC1 IC1PS U Prescaler +/- CNT COUNTER Capture/Compare 1 Register TRC CC2I TI2FP1 TI2FP2 TRC TI3FP3 TI3FP4 IC2 IC2PS U Prescaler CC3I IC3 IC3PS U Prescaler Capture/Compare 2 Register Capture/Compare 3 Register TRC CC4I TI4FP3 TI4FP4 TRC IC4 IC4PS U Prescaler Capture/Compare 4 Register REP Register UI Repetition counter U DTG registers CC1I OC1REF DTG CC2I OC2REF DTG CC3I OC3REF DTG CC4I OC4REF TIMx_CH1 output OC1 control TIMx_CH1N OC1N TIMx_CH2 output OC2 control TIMx_CH2N OC2N TIMx_CH3 output OC3 control TIMx_CH3N OC3N output control OC4 TIMx_CH4 ETRF BRK BI Polarity Selection Clock failure event from clock controller CSS (Clock Security system Notes: Reg Preload registers transferred to active registers on U event according to control bit event interrupt & DMA output Doc ID 13902 Rev 9 255/995 Advanced-control timers (TIM1&TIM8) RM0008 13.3 13.3.1 TIM1&TIM8 functional description Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: ● Counter register (TIMx_CNT) ● Prescaler register (TIMx_PSC) ● Auto-reload register (TIMx_ARR) ● Repetition counter register (TIMx_RCR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 53 and Figure 54 give some examples of the counter behavior when the prescaler ratio is changed on the fly: 256/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 52. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CEN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 02 03 Update event (UEV) Prescaler control register 0 1 Write a new value in TIMx_PSC Prescaler buffer 0 1 Prescaler counter 0 01 01 01 01 Figure 53. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CEN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 Update event (UEV) Prescaler control register 0 3 Write a new value in TIMx_PSC Prescaler buffer 0 3 Prescaler counter 0 01 23 01 23 13.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is generated at each counter overflow. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the Doc ID 13902 Rev 9 257/995 Advanced-control timers (TIM1&TIM8) RM0008 preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): ● The repetition counter is reloaded with the content of TIMx_RCR register, ● The auto-reload shadow register is updated with the preload value (TIMx_ARR), ● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 54. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Figure 55. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0034 0035 0036 0000 0001 0002 0003 Update interrupt flag (UIF) 258/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 56. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0035 0036 0000 0001 Update interrupt flag (UIF) Figure 57. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register 1F 20 00 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 58. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC CEN Timer clock = CK_CNT Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR Doc ID 13902 Rev 9 259/995 Advanced-control timers (TIM1&TIM8) RM0008 Figure 59. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CEN Timer clock = CK_CNT Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register F5 36 Auto-reload shadow register F5 36 Write a new value in TIMx_ARR Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is generated at each counter underflow. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): ● The repetition counter is reloaded with the content of TIMx_RCR register ● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) ● The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one 260/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 60. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter underflow (cnt_udf) Update event (UEV) 05 04 03 02 01 00 36 35 34 33 32 31 30 2F Update interrupt flag (UIF) Figure 61. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0002 0001 0000 0036 0035 0034 0033 Update interrupt flag (UIF) Figure 62. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0001 0000 0036 0035 Update interrupt flag (UIF) Doc ID 13902 Rev 9 261/995 Advanced-control timers (TIM1&TIM8) Figure 63. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register 20 1F 00 36 Counter underflow Update event (UEV) Update interrupt flag (UIF) RM0008 Figure 64. Counter timing diagram, update event when repetition counter is not used CK_PSC CEN Timer clock = CK_CNT Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. 262/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): ● The repetition counter is reloaded with the content of TIMx_RCR register ● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) ● The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. Figure 65. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03 Counter underflow Counter overflow Update event (UEV) Update interrupt flag (UIF) 1. Here, center-aligned mode 1 is used (for more details refer to Section 13.4: TIM1&TIM8 registers on page 294). Figure 66. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0003 0002 0001 0000 0001 0002 0003 Update interrupt flag (UIF) Doc ID 13902 Rev 9 263/995 Advanced-control timers (TIM1&TIM8) RM0008 Figure 67. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0034 0035 0036 0035 Update interrupt flag (UIF) Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow Figure 68. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register 20 1F 01 00 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 69. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC CEN Timer clock = CK_CNT Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register FD 36 Write a new value in TIMx_ARR Auto-reload active register FD 36 264/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 70. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC CEN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register FD 36 Write a new value in TIMx_ARR Auto-reload active register FD 36 13.3.3 Repetition counter Section 13.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows or underflows, where N is the value in the TIMx_RCR repetition counter register. The repetition counter is decremented: ● At each counter overflow in upcounting mode, ● At each counter underflow in downcounting mode, ● At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is 2xTck, due to the symmetry of the pattern. The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 71). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register. Doc ID 13902 Rev 9 265/995 Advanced-control timers (TIM1&TIM8) RM0008 Figure 71. Update rate examples depending on mode and TIMx_RCR register settings Counter TIMx_CNT TIMx_RCR = 0 UEV Center-aligned mode Edge-aligned mode Upcounting Downcounting TIMx_RCR = 1 UEV TIMx_RCR = 2 UEV TIMx_RCR = 3 UEV TIMx_RCR = 3 and re-synchronization UEV (by SW) (by SW) (by SW) UEV Update Event: Preload registers transferred to active registers and update interrupt generated Update Event if the repetition counter underflow occurs when the counter is equal to to the auto-reload value. 266/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) 13.3.4 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (CK_INT) ● External clock mode1: external input pin ● External clock mode2: external trigger input ETR ● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Section : Using one timer as prescaler for another timer on page 353 for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 72 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 72. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN UG CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 73. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2 Filter Edge TI2F_Rising 0 Detector TI2F_Falling 1 ITRx or TI2F or TI1F or 0xx TI1_ED 100 TI1FP1 101 TRGI TI2FP2 110 ETRF 111 ETRF encoder mode external clock mode 1 CK_PSC external clock mode 2 ICF[3:0] TIMx_CCMR1 CC2P TIMx_CCER CK_INT internal clock (internal clock) mode ECE SMS[2:0] TIMx_SMCR Doc ID 13902 Rev 9 267/995 Advanced-control timers (TIM1&TIM8) RM0008 Note: For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). 3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 74. Control circuit in external clock mode 1 TI2 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 Write TIF=0 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. The Figure 75 gives an overview of the external trigger input block. Figure 75. External trigger input block ETR pin ETR 0 1 ETP TIMx_SMCR divider /1, /2, /4, /8 ETRP fDTS filter downcounter ETPS[1:0] TIMx_SMCR ETF[3:0] TIMx_SMCR or TI2F or TI1F or encoder mode TRGI external clock mode 1 CK_PSC ETRF external clock mode 2 CK_INT internal clock (internal clock) mode ECE SMS[2:0] TIMx_SMCR 268/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 76. Control circuit in external clock mode 2 fCK_INT CNT_EN ETR ETRP ETRF Counter clock = CK_CNT = CK_PSC Counter register 34 35 36 13.3.5 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 77 to Figure 80 give an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). Doc ID 13902 Rev 9 269/995 Advanced-control timers (TIM1&TIM8) RM0008 Figure 77. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1 filter TI1F Edge TI1F_Rising 0 TI1FP1 fDTS downcounter Detector TI1F_Falling 1 TI2FP1 01 10 IC1 divider IC1PS /1, /2, /4, /8 ICF[3:0] TIMx_CCMR1 CC1P TIMx_CCER TI2F_rising 0 (from channel 2) TI2F_falling (from channel 2) 1 TRC (from slave mode 11 controller) CC1S[1:0] ICPS[1:0] TIMx_CCMR1 CC1E TIMx_CCER The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 78. Capture/compare channel 1 main circuit APB Bus read CCR1H S read CCR1L R CC1S[1] CC1S[0] IC1PS CC1E CC1G TIM1_EGR MCU-peripheral interface high (if 16-bit) low 8 8 read_in_progress write_in_progress Capture/compare preload register S write CCR1H R write CCR1L input mode capture_transfer compare_transfer output mode Capture/compare shadow register capture comparator CC1S[1] CC1S[0] OC1PE OC1PE UEV (from time TIM1_CCMR1 base unit) CNT>CCR1 Counter CNT=CCR1 270/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 79. Output stage of capture/compare channel (channel 1 to 3) ETR CNT>CCR1 Output mode OC1REF CNT=CCR1 controller ‘0’ x0 10 OC1_DT 11 Dead-time generator OC1N_DT 11 10 ‘0’ 0x 0 1 CC1P TIM1_CCER Output enable circuit OC1 0 Output OC1N enable 1 circuit OC1CE OC1M[2:0] TIM1_CCMR1 DTG[7:0] TIM1_BDTR CC1NE CC1E TIM1_CCER CC1NE CC1E TIM1_CCER CC1NP MOEOSSI OSSR TIM1_BDTR TIM1_CCER Figure 80. Output stage of capture/compare channel (channel 4) ETR To the master mode controller CNT > CCR4 Output mode OC4 REF CNT = CCR4 controller 0 1 CC4P TIM1_CCER Output enable circuit OC4 13.3.6 OC2M[2:0] TIM1_CCMR2 CC4E TIM1_CCER MOEOSSI TIM1_BDTR OIS4 TIM1_CR2 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. Doc ID 13902 Rev 9 271/995 Advanced-control timers (TIM1&TIM8) RM0008 Note: 13.3.7 The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: ● Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. ● Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. ● Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case). ● Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). ● Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. ● If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: ● The TIMx_CCR1 register gets the value of the counter on the active transition. ● CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. ● An interrupt is generated depending on the CC1IE bit. ● A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: ● Two ICx signals are mapped on the same TIx input. ● These 2 ICx signals are active on edges with opposite polarity. ● One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. 272/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): ● Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). ● Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P bit to ‘0’ (active on rising edge). ● Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). ● Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active on falling edge). ● Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). ● Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. ● Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 81. PWM input mode timing TI1 TIMx_CNT 0004 TIMx_CCR1 0000 0001 0002 0004 0003 0004 0000 TIMx_CCR2 0002 13.3.8 IC1 capture IC2 capture reset counter IC2 capture pulse width measurement IC1 capture period measurement ai15413 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Doc ID 13902 Rev 9 273/995 Advanced-control timers (TIM1&TIM8) RM0008 13.3.9 Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: ● Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. ● Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). ● Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). ● Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One Pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. Select the output mode. For example: – Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx – Write OCxPE = 0 to disable preload register – Write CCxP = 0 to select active high polarity – Write CCxE = 1 to enable the output 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 82. 274/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 82. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A 003B TIM1_CCR1 003A oc1ref=OC1 B200 B201 B201 Match detected on CCR1 Interrupt generated if enabled 13.3.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx  TIMx_CNT or TIMx_CNT  TIMx_CCRx (depending on the direction of the counter). The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. Doc ID 13902 Rev 9 275/995 Advanced-control timers (TIM1&TIM8) RM0008 PWM edge-aligned mode ● Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 257. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 83 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. Figure 83. Edge-aligned PWM waveforms (ARR=8) Counter register 0 1 2 3 4 5 6 7 8 0 1 OCXREF CCRx=4 CCxIF OCXREF CCRx=8 CCxIF OCXREF ‘1’ CCRx>8 CCxIF OCXREF ‘0’ CCRx=0 CCxIF ● Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the Downcounting mode on page 260 In PWM mode 1, the reference signal OCxRef is low as long as TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to the Center-aligned mode (up/down counting) on page 262. Figure 84 shows some center-aligned PWM waveforms in an example where: ● TIMx_ARR=8, ● PWM mode is the PWM mode 1, ● The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. 276/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 84. Center-aligned PWM waveforms (ARR=8) Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 OCxREF CCRx = 4 CCxIF OCxREF CCRx = 7 CMS=01 CMS=10 CMS=11 CCxIF CMS=10 or 11 OCxREF '1' CCRx = 8 CCxIF OCxREF '1' CCRx > 8 CMS=01 CMS=10 CMS=11 CCxIF OCxREF '0' CCRx = 0 CMS=01 CMS=10 CMS=11 CCxIF CMS=01 CMS=10 CMS=11 ai14681 Hints on using center-aligned mode: ● When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. ● Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. ● The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. Doc ID 13902 Rev 9 277/995 Advanced-control timers (TIM1&TIM8) RM0008 13.3.11 Complementary outputs and dead-time insertion The advanced-control timers (TIM1&TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register. The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 73: Output control bits for complementary OCx and OCxN channels with break feature on page 310 for more details. In particular, the dead-time is activated when switching to the IDLE state (MOE falling down to 0). Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: ● The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. ● The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge. If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated. The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples) Figure 85. Complementary output with dead-time insertion. OCxREF OCx OCxN delay delay Figure 86. Dead-time waveforms with delay greater than the negative pulse. OCxREF OCx OCxN delay 278/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 87. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCx OCxN delay Note: The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 13.4.18: TIM1&TIM8 break and deadtime register (TIMx_BDTR) on page 314 for delay calculation. Re-directing OCxREF to OCx or OCxN In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register. This allows you to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time. When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low. 13.3.12 Using the break function When using the break function, the output enable signals and inactive levels are modified according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs cannot be set both to active level at a given time. Refer to Table 73: Output control bits for complementary OCx and OCxN channels with break feature on page 310 for more details. The break source can be either the break input pin or a clock failure event, generated by the Clock Security System (CSS), from the Reset Clock Controller. For further information on the Clock Security System, refer to Section 6.2.7: Clock security system (CSS) on page 81. When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable the break function by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation. Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you Doc ID 13902 Rev 9 279/995 Advanced-control timers (TIM1&TIM8) RM0008 Note: must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. When a break occurs (selected level on the break input): ● The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit). This feature functions even if the MCU oscillator is off. ● Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable output else the enable output remains high. ● When complementary outputs are used: – The outputs are first put in reset state inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer. – If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high. ● The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set. ● If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance. Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components. The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared. The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR Register. In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows you to freeze the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). You can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to Section 13.4.18: TIM1&TIM8 break and dead-time register (TIMx_BDTR) on page 314. The LOCK bits can be written only once after an MCU reset. The Figure 88 shows an example of behavior of the outputs in response to a break. 280/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 88. Output behavior in response to a break. BREAK (MOE ) OCxREF OCx (OCxN not implemented, CCxP=0, OISx=1) OCx (OCxN not implemented, CCxP=0, OISx=0) OCx (OCxN not implemented, CCxP=1, OISx=1) OCx (OCxN not implemented, CCxP=1, OISx=0) OCx OCxN delay delay delay (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) OCx OCxN delay delay delay (CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1) OCx OCxN delay (CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1) OCx OCxN delay (CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0) OCx OCxN (CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1) Doc ID 13902 Rev 9 281/995 Advanced-control timers (TIM1&TIM8) RM0008 13.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs. This function can only be used in output compare and PWM modes, and does not work in forced mode. For example, the OCxREF signal) can be connected to the output of a comparator to be used for current handling. In this case, the ETR must be configured as follow: 1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’. 2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to ‘0’. 3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to the user needs. Figure 89 shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in PWM mode. Figure 89. Clearing TIMx OCxREF counter (CNT) (CCRx) ETRF OCxREF (OCxCE=’0’) OCxREF (OCxCE=’1’) OCREF_CLR becomes high OCREF_CLR still high 282/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) 13.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on TRGI rising edge). A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request (if the COMDE bit is set in the TIMx_DIER register). The Figure 90 describes the behavior of the OCx and OCxN outputs when a COM event occurs, in 3 different examples of programmed configurations. Figure 90. 6-step generation, COM example (OSSR=1) counter (CNT) (CCRx) OCxREF Write COM to 1 COM event OCx Example 1 OCxN OCx Example 2 OCxN OCx Example 3 OCxN CCxE=1 CCxNE=0 write OCxM to 100 OCxM=100 (forced inactive) Write CCxNE to 1 CCxE=1 and OCxM to 101 CCxNE=0 OCxM=100 (forced inactive) CCxE=1 CCxNE=0 write CCxNE to 0 and OCxM to 100 OCxM=100 (forced inactive) CCxE=1 CCxNE=0 OCxM=100 CCxE=0 CCxNE=1 OCxM=101 CCxE=1 CCxNE=0 OCxM=100 ai14910 Doc ID 13902 Rev 9 283/995 Advanced-control timers (TIM1&TIM8) RM0008 13.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: ● In upcounting: CNT < CCRx  ARR (in particular, 0 < CCRx) ● In downcounting: CNT > CCRx Figure 91. Example of one pulse mode. TI2 OC1REF OC1 Counter TIM1_ARR TIM1_CCR1 0 tDELAY tPULSE t For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: ● Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. ● TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register. ● Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register. ● TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). 284/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The tDELAY is defined by the value written in the TIMx_CCR1 register. ● The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). ● Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). Particular case: OCx fast enable: In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 13.3.16 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’ if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, you can program the input filter as well. The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 71. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, Doc ID 13902 Rev 9 285/995 Advanced-control timers (TIM1&TIM8) RM0008 repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. Table 71. Counting direction versus encoder signals Active edge Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) TI1FP1 signal Rising Falling Counting on TI1 only Counting on TI2 only Counting on TI1 and TI2 High Low High Low High Low Down Up No Count No Count Down Up Up Down No Count No Count Up Down TI2FP2 signal Rising No Count No Count Up Down Up Down Falling No Count No Count Down Up Down Up An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. The Figure 92 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: ● CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1). ● CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2). ● CC1P=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1). ● CC2P=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2). ● SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges). ● CEN=’1’ (TIMx_CR1 register, Counter enabled). 286/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Figure 92. Example of counter operation in encoder interface mode. forward jitter backward jitter forward TI1 TI2 Counter up down up Figure 93 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 93. Example of encoder interface mode with TI1FP1 polarity inverted. forward jitter backward jitter forward TI1 TI2 Counter down up down The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a real-time clock. Doc ID 13902 Rev 9 287/995 Advanced-control timers (TIM1&TIM8) RM0008 13.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture. An example of this feature used to interface Hall sensors is given in Section 13.3.18 below. 13.3.18 Interfacing with Hall sensors This is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to drive the motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as “interfacing timer” in Figure 94. The “interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3) connected through a XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register). The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a time base triggered by any change on the Hall inputs. On the “interfacing timer”, capture/compare channel 1 is configured in capture mode, capture signal is TRC (See Figure 77: Capture/compare channel (example: channel 1 input stage) on page 270). The captured value, which corresponds to the time elapsed between 2 changes on the inputs, gives information about motor speed. The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or PWM mode). This pulse is sent to the advancedcontrol timer (TIM1 or TIM8) through the TRGO output. Example: you want to change the PWM configuration of your advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. ● Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, ● Program the time base: write the TIMx_ARR to the max value (the counter must be cleared by the TI1 change. Set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors, ● Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the TIMx_CCMR1 register to ‘01’. You can also program the digital filter if needed, ● Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR1 register, ● Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to ‘101’, In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are 288/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF). The Figure 94 describes this example. Figure 94. Example of hall sensor interface TIH1 TIH2 TIH3 counter (CNT) (CCR2) Interfacing Timer CCR1 TRGO=OC2REF C7A3 C7A8 C794 C7A5 C7AB C796 advanced-control timers (TIM1&TIM8) COM OC1 OC1N OC2 OC2N OC3 OC3N Write CCxE, CCxNE and OCxM for next step Doc ID 13902 Rev 9 289/995 Advanced-control timers (TIM1&TIM8) RM0008 13.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: ● Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only). ● Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. ● Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 95. Control circuit in reset mode TI1 UG Counter clock = ck_cnt = ck_psc Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03 TIF 290/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: ● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only). ● Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. ● Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 96. Control circuit in gated mode TI1 cnt_en Counter clock = ck_cnt = ck_psc Counter register 30 31 32 33 34 TIF 35 36 37 38 Write TIF=0 Doc ID 13902 Rev 9 291/995 Advanced-control timers (TIM1&TIM8) RM0008 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: ● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only). ● Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 97. Control circuit in trigger mode TI2 cnt_en Counter clock = ck_cnt = ck_psc Counter register 34 TIF 35 36 37 38 Slave mode: external clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register. In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: 1. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. 292/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) 2. Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source – CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge only). 3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. Figure 98. Control circuit in external clock mode 2 + trigger mode TI1 CEN/CNT_EN ETR Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 13.3.20 Timer synchronization The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 14.3.15: Timer synchronization on page 349 for details. 13.3.21 Debug mode When the microcontroller enters debug mode (Cortex-M3 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 29.16.2: Debug support for timers, watchdog, bxCAN and I2C. Doc ID 13902 Rev 9 293/995 Advanced-control timers (TIM1&TIM8) RM0008 13.4 TIM1&TIM8 registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. 13.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 Reserved CKD[1:0] rw rw ARPE rw CMS[1:0] rw rw 4 3 2 1 0 DIR OPM URS UDIS CEN rw rw rw rw rw Bits 15:10 Reserved, always read as 0 Bits 9:8 CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value. Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:5 CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) Bit 4 DIR: Direction 0: Counter used as upcounter. 1: Counter used as downcounter. Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN). 294/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –Counter overflow/underflow –Setting the UG bit –Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: –Counter overflow/underflow –Setting the UG bit –Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 13.4.2 TIM1&TIM8 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res. OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 rw rw rw rw rw rw rw TI1S rw 6 5 4 MMS[2:0] rw rw rw 3 2 CCDS CCUS rw rw 1 Res. 0 CCPC rw Bit 15 Reserved, always read as 0 Bit 14 OIS4: Output Idle state 4 (OC4 output) refer to OIS1 bit Bit 13 OIS3N: Output Idle state 3 (OC3N output) refer to OIS1N bit Bit 12 OIS3: Output Idle state 3 (OC3 output) refer to OIS1 bit Bit 11 OIS2N: Output Idle state 2 (OC2N output) refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) refer to OIS1 bit Doc ID 13902 Rev 9 295/995 Advanced-control timers (TIM1&TIM8) RM0008 Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input. 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[1:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 100: Compare - OC1REF signal is used as trigger output (TRGO). 101: Compare - OC2REF signal is used as trigger output (TRGO). 110: Compare - OC3REF signal is used as trigger output (TRGO). 111: Compare - OC4REF signal is used as trigger output (TRGO). Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, always read as 0 Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output. 296/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) 13.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 15 14 13 12 11 10 9 ETP ECE ETPS[1:0] ETF[3:0] rw rw rw rw rw rw rw 8 7 6 5 4 3 MSM TS[2:0] Res. rw rw rw rw rw Res. 2 1 0 SMS[2:0] rw rw rw Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge. Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled. 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF. 01: ETRP frequency divided by 2. 10: ETRP frequency divided by 4. 11: ETRP frequency divided by 8. Doc ID 13902 Rev 9 297/995 Advanced-control timers (TIM1&TIM8) RM0008 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS. 0001: fSAMPLING=fCK_INT, N=2. 0010: fSAMPLING=fCK_INT, N=4. 0011: fSAMPLING=fCK_INT, N=8. 0100: fSAMPLING=fDTS/2, N=6. 0101: fSAMPLING=fDTS/2, N=8. 0110: fSAMPLING=fDTS/4, N=6. 0111: fSAMPLING=fDTS/4, N=8. 1000: fSAMPLING=fDTS/8, N=6. 1001: fSAMPLING=fDTS/8, N=8. 1010: fSAMPLING=fDTS/16, N=5. 1011: fSAMPLING=fDTS/16, N=6. 1100: fSAMPLING=fDTS/16, N=8. 1101: fSAMPLING=fDTS/32, N=5. 1110: fSAMPLING=fDTS/32, N=6. 1111: fSAMPLING=fDTS/32, N=8. Bit 7 MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. Bits 6:4 TS[2:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) See Table 72: TIMx Internal trigger connection on page 299 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, always read as 0. 298/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Table 72. TIMx Internal trigger connection(1) Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM1 TIM8 TIM5 TIM1 TIM2 TIM2 TIM3 TIM4 TIM4 TIM5 1. When a timer is not present in the product, the corresponding trigger ITRx is not available. 13.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res. TDE COMD CC4D CC3D CC2D CC1D E E E E E UDE BIE Res. rw rw rw rw rw rw rw rw 6 5 4 3 2 1 0 TIE COMI E CC4IE CC3IE CC2IE CC1IE UIE rw rw rw rw rw rw rw Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled. Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled. 1: COM DMA request enabled. Doc ID 13902 Rev 9 299/995 Advanced-control timers (TIM1&TIM8) Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled. Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled. 1: Break interrupt enabled. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled. 1: COM interrupt enabled. Bit 4 CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled. Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled. Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. 300/995 Doc ID 13902 Rev 9 RM0008 RM0008 Advanced-control timers (TIM1&TIM8) 13.4.5 TIM1&TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 Reserved CC4OF CC3OF CC2OF CC1OF Res. rc_w0 rc_w0 rc_w0 rc_w0 Res. 7 BIF rc_w0 6 5 4 3 2 1 TIF COMIF CC4IF CC3IF CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 0 UIF rc_w0 Bit 15:13 Reserved, always read as 0. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF: Capture/Compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 Reserved, always read as 0. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bit 5 COMIF: COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending. Bit 4 CC4IF: Capture/Compare 4 interrupt flag refer to CC1IF description Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description Doc ID 13902 Rev 9 301/995 Advanced-control timers (TIM1&TIM8) RM0008 Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. –When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. –When CNT is reinitialized by a trigger event (refer to Section 13.4.3: TIM1&TIM8 slave mode control register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 13.4.6 TIM1&TIM8 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BG TG COMG CC4G CC3G CC2G CC1G UG w w w w w w w w Bits 15:8 Reserved, always read as 0. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. 302/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output. Bit 4 CC4G: Capture/Compare 4 generation refer to CC1G description Bit 3 CC3G: Capture/Compare 3 generation refer to CC1G description Bit 2 CC2G: Capture/Compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). Doc ID 13902 Rev 9 303/995 Advanced-control timers (TIM1&TIM8) RM0008 13.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 15 OC2 CE rw 14 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2 PE OC2 FE IC2PSC[1:0] rw rw 9 8 CC2S[1:0] rw rw 7 OC1 CE rw 6 5 4 OC1M[2:0] IC1F[3:0] rw rw rw 3 2 OC1 PE OC1 FE IC1PSC[1:0] rw rw 1 0 CC1S[1:0] rw rw Output compare mode: Bit 15 OC2CE: Output Compare 2 clear enable Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). Bit 7 OC1CE: Output Compare 1 clear enable OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF Input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input 304/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=’1’). 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else inactive. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Doc ID 13902 Rev 9 305/995 Advanced-control timers (TIM1&TIM8) RM0008 Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS. 0001: fSAMPLING=fCK_INT, N=2. 0010: fSAMPLING=fCK_INT, N=4. 0011: fSAMPLING=fCK_INT, N=8. 0100: fSAMPLING=fDTS/2, N=6. 0101: fSAMPLING=fDTS/2, N=8. 0110: fSAMPLING=fDTS/4, N=6. 0111: fSAMPLING=fDTS/4, N=8. 1000: fSAMPLING=fDTS/8, N=6. 1001: fSAMPLING=fDTS/8, N=8. 1010: fSAMPLING=fDTS/16, N=5. 1011: fSAMPLING=fDTS/16, N=6. 1100: fSAMPLING=fDTS/16, N=8. 1101: fSAMPLING=fDTS/32, N=5. 1110: fSAMPLING=fDTS/32, N=6. 1111: fSAMPLING=fDTS/32, N=8. Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input. 01: capture is done once every 2 events. 10: capture is done once every 4 events. 11: capture is done once every 8 events. 306/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). 13.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OC4 CE OC4M[2:0] IC4F[3:0] OC4 PE OC4 FE IC4PSC[1:0] CC4S[1:0] OC3 CE. OC3M[2:0] IC3F[3:0] OC3 PE OC3 FE IC3PSC[1:0] CC3S[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output. 01: CC4 channel is configured as input, IC4 is mapped on TI4. 10: CC4 channel is configured as input, IC4 is mapped on TI3. 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output. 01: CC3 channel is configured as input, IC3 is mapped on TI3. 10: CC3 channel is configured as input, IC3 is mapped on TI4. 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER). Doc ID 13902 Rev 9 307/995 Advanced-control timers (TIM1&TIM8) RM0008 Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output. 01: CC4 channel is configured as input, IC4 is mapped on TI4. 10: CC4 channel is configured as input, IC4 is mapped on TI3. 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output. 01: CC3 channel is configured as input, IC3 is mapped on TI3. 10: CC3 channel is configured as input, IC3 is mapped on TI4. 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER). 13.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER) Address offset: 0x20 15 14 Reserved Res. Reset value: 0x0000 13 12 11 10 CC4P CC4E CC3N P CC3N E rw rw rw rw 9 CC3P rw 8 CC3E rw 7 CC2N P rw 6 CC2N E rw 5 CC2P rw 4 CC2E rw 3 CC1N P rw 2 CC1N E rw 1 CC1P rw 0 CC1E rw Bits 15:14 Reserved, always read as 0. Bit 13 CC4P: Capture/Compare 4 output polarity refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity refer to CC1NP description Bit 10 CC3NE: Capture/Compare 3 complementary output enable refer to CC1NE description Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description 308/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high. 1: OC1N active low. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low. CC1 channel configured as input: This bit selects whether IC1 or IC1 is used for trigger or capture operations. 0: non-inverted: capture is done on a rising edge of IC1. When used as external trigger, IC1 is non-inverted. 1: inverted: capture is done on a falling edge of IC1. When used as external trigger, IC1 is inverted. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. Doc ID 13902 Rev 9 309/995 Advanced-control timers (TIM1&TIM8) RM0008 Note: Table 73. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states(1) MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state 0 0 Output Disabled (not 0 driven by the timer) OCx=0, OCx_EN=0 Output Disabled (not driven by the timer) OCxN=0, OCxN_EN=0 0 0 Output Disabled (not 1 driven by the timer) OCx=0, OCx_EN=0 OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1 0 1 OCxREF + Polarity Output Disabled (not driven by 0 OCx=OCxREF xor CCxP, the timer) OCx_EN=1 OCxN=0, OCxN_EN=0 0 1 1X 1 0 OCREF + Polarity + dead- Complementary to OCREF (not 1 time OCREF) + Polarity + dead-time OCx_EN=1 OCxN_EN=1 Output Disabled (not Output Disabled (not driven by 0 driven by the timer) the timer) OCx=CCxP, OCx_EN=0 OCxN=CCxNP, OCxN_EN=0 1 0 Off-State (output enabled OCxREF + Polarity 1 with inactive state) OCxN=OCxREF xor CCxNP, OCx=CCxP, OCx_EN=1 OCxN_EN=1 1 1 OCxREF + Polarity Off-State (output enabled with 0 OCx=OCxREF xor CCxP, inactive state) OCx_EN=1 OCxN=CCxNP, OCxN_EN=1 1 1 OCREF + Polarity + dead- Complementary to OCREF (not 1 time OCREF) + Polarity + dead-time OCx_EN=1 OCxN_EN=1 0 0 0 0 0 1 0 1 0 1 X 0 1 0 1 1 1 1 0 Output Disabled (not driven by the timer) 1 Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP, 0 OCxN_EN=0 Then if the clock is present: OCx=OISx and OCxN=OISxN 1 after a dead-time, assuming that OISx and OISxN do not 0 correspond to OCX and OCxN both in active state. 1 Off-State (output enabled with inactive state) 0 Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP, OCxN_EN=1 Then if the clock is present: OCx=OISx and OCxN=OISxN 1 after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state 1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared. The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO and AFIO registers. 310/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) 13.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 13.4.11 TIM1&TIM8 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 13.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 13.3.1: Time-base unit on page 256 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Doc ID 13902 Rev 9 311/995 Advanced-control timers (TIM1&TIM8) RM0008 13.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 15 14 13 12 11 10 9 Reserved Res. 8 7 6 5 4 3 2 1 0 REP[7:0] rw rw rw rw rw rw rw rw Bits 15:8 Reserved, always read as 0. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: – the number of PWM periods in edge-aligned mode – the number of half PWM period in center-aligned mode. 13.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 312/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) 13.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR2[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 13.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR3[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR3[15:0]: Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). Doc ID 13902 Rev 9 313/995 Advanced-control timers (TIM1&TIM8) RM0008 13.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR4[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). 13.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR) Address offset: 0x44 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: OC and OCN outputs are disabled or forced to idle state. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). See OC/OCN enable description for more details (Section 13.4.9: TIM1&TIM8 capture/compare enable register (TIMx_CCER) on page 308). Bit 14 AOE: Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if the break input is not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 314/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 12 BKE: Break enable 0: Break inputs (BRK and CCS clock failure event) disabled 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 13.4.9: TIM1&TIM8 capture/compare enable register (TIMx_CCER) on page 308). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1 Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 13.4.9: TIM1&TIM8 capture/compare enable register (TIMx_CCER) on page 308). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). Bits 9:8 LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected. 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. Doc ID 13902 Rev 9 315/995 Advanced-control timers (TIM1&TIM8) RM0008 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 13.4.19 TIM1&TIM8 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 12 11 10 9 8 Reserved DBL[4:0] Res. rw rw rw rw rw 7 6 5 Reserved Res. 4 3 2 1 0 DBA[4:0] rw rw rw rw rw Bits 15:13 Reserved, always read as 0 Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. – If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data will be copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: – If you configure the DMA Data Size in half-words, 16-bit data will be transferred to each of the 7 registers. – If you configure the DMA Data Size in bytes, the data will aslo be transferred to 7 registers: the first register will contain the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, you also have to specify the size of data transferred by DMA. Bits 7:5 Reserved, always read as 0 316/995 Doc ID 13902 Rev 9 RM0008 Advanced-control timers (TIM1&TIM8) Bits 4:0 DBA[4:0]: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... 13.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAB[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write access to the DMAR register accesses the register located at the address: “(TIMx_CR1 address) + DBA + (DMA index)” in which: TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is the offset automatically controlled by the DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register. 13.4.21 TIM1&TIM8 register map TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 74. TIM1&TIM8 register map and reset values Offset Register 0x00 0x04 0x08 TIMx_CR1 Reset value TIMx_CR2 Reset value TIMx_SMCR Reset value Reserved Reserved Reserved 0x0C 0x10 0x14 TIMx_DIER Reset value TIMx_SR Reset value TIMx_EGR Reset value Reserved Reserved Reserved ETP CC3IE Reserved CCDS CKD [1:0] CMS [1:0] 0000000000 CCPC Reserved CCUS TI1S OIS1 OIS1N OIS2 OIS2N OIS3 OIS3N OIS4 MMS[2:0] 0000000000000 0 MSM ECE ETPS [1:0] ETF[3:0] TS[2:0] SMS[2:0] 000000000000 000 UIE CC1IE CC2IE CC4IE COMIE TIE BIE UDE CC1DE CC2DE CC3DE CC4DE COMDE TDE UIF 000000000000000 CC1G CC1IF CC2G CC2IF CC3G CC3IF CC4G CC4IF COM COMIF TIF BIF Reserved CC1OF CC2OF CC3OF CC4OF 0000 00000000 TG BG 00000000 UG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ARPE 7 6 5 DIR 4 OPM 3 URS 2 UDIS 1 CEN 0 Doc ID 13902 Rev 9 317/995 Advanced-control timers (TIM1&TIM8) RM0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OC2CE 15 14 13 12 OC2PE 11 OC2FE 10 9 8 OC1CE 7 6 5 4 OC1PE 3 OC1FE 2 1 0 Table 74. TIM1&TIM8 register map and reset values (continued) Offset Register 0x18 0x1C TIMx_CCMR1 Output Compare mode Reset value TIMx_CCMR1 Input Capture mode Reset value TIMx_CCMR2 Output Compare mode Reset value TIMx_CCMR2 Input Capture mode Reset value Reserved Reserved Reserved Reserved O24CE OC4PE OC4FE OC3CE OC3PE OC3FE OC2M [2:0] CC2S [1:0] OC1M [2:0] CC1S [1:0] 0000 IC2F[3:0] 0000 00 IC2 PSC [1:0] 00 00 CC2S [1:0] 00 0000 IC1F[3:0] 0000 00 IC1 PSC [1:0] 00 00 CC1S [1:0] 00 OC4M [2:0] CC4S [1:0] OC3M [2:0] CC3S [1:0] 0000 IC4F[3:0] 0000 00 IC4 PSC [1:0] 00 00 CC4S [1:0] 00 0000 IC3F[3:0] 0000 00 IC3 PSC [1:0] 00 00 CC3S [1:0] 00 CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E 0x20 TIMx_CCER Reset value Reserved 00000000000000 0x24 TIMx_CNT Reset value Reserved CNT[15:0] 0000000000000000 0x28 TIMx_PSC Reset value Reserved PSC[15:0] 0000000000000000 0x2C TIMx_ARR Reset value Reserved ARR[15:0] 0000000000000000 0x30 TIMx_RCR Reset value Reserved REP[7:0] 00000000 0x34 TIMx_CCR1 Reset value Reserved CCR1[15:0] 0000000000000000 0x38 TIMx_CCR2 Reset value Reserved CCR2[15:0] 0000000000000000 0x3C TIMx_CCR3 Reset value Reserved CCR3[15:0] 0000000000000000 0x40 0x44 TIMx_CCR4 Reset value TIMx_BDTR Reset value Reserved Reserved MOE AOE BKP BKE OSSR OSSI CCR4[15:0] 0000000000000000 LOCK [1:0] DT[7:0] 0000000000000000 0x48 TIMx_DCR Reset value Reserved DBL[4:0] Reserved DBA[4:0] 00000 00000 0x4C TIMx_DMAR Reset value Reserved DMAB[15:0] 0000000000000000 Refer to Table 1 on page 41 for the register boundary addresses. 318/995 Doc ID 13902 Rev 9 RM0008 14 General-purpose timer (TIMx) General-purpose timer (TIMx) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to the whole STM32F10xxx family, unless otherwise specified. 14.1 TIMx introduction The general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 14.3.15. Doc ID 13902 Rev 9 319/995 General-purpose timer (TIMx) RM0008 14.2 TIMx main features General-purpose TIMx (TIM2, TIM3, TIM4 and TIM5) timer features include: ● 16-bit up, down, up/down auto-reload counter. ● 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65535. ● Up to 4 independent channels for: – Input capture – Output compare – PWM generation (Edge and Center-aligned mode) – One-pulse mode output ● Synchronization circuit to control the timer with external signals and to interconnect several timers between them. ● Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare ● Supports incremental (quadrature) encoder and hall-sensor cicuitry for positioning purposes ● Trigger intput for external clock or cycle-by-cycle current management 320/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Figure 99. General-purpose timer block diagram TIMx_ETR Internal Clock (CK_INT) TIMxCLK from RCC ETR ETRP Polarity selection & edge detector & prescaler Input filter ITR0 ITR1 ITR2 ITR3 ITR TRC TI1F_ED ETRF TGI TRGI Trigger controller TRGO to other timers to DAC/ADC Slave mode Reset, enable, up/down, count, controller TI1FP1 TI2FP2 Encoder Interface TIMx_CH1 TIMx_CH2 TIMx_CH3 TIMx_CH4 XOR TI1 TI2 TI3 TI4 U Autoreload register Input filter & edge detector Input filter & edge detector Input filter & edge detector Input filter & edge detector Stop, clear or up/down CK_PSC TI1FP1 IC1 TI1FP2 PSC Prescaler CK_CNT CC1I IC1PS U Prescaler +/- CNT counter Capture/compare 1 register TRC CC2I TI2FP1 TI2FP2 TRC TI3FP3 TI3FP4 IC2 IC2PS U Prescaler CC3I IC3 IC3PS U Prescaler Capture/compare 2 register Capture/compare 3 register TRC CC4I TI4FP3 TI4FP4 TRC IC4 IC4PS U Prescaler Capture/compare 4 register ETRF UI U CC1I OC1REF output control OC1 CC2I OC2REF output control OC2 CC3I OC3REF output control OC3 CC4I OC4REF output control OC4 TIMx_CH1 TIMx_CH2 TIMx_CH3 TIMx_CH4 Notes: Reg Preload registers transferred to active registers on U event according to control bit event interrupt & DMA output 14.3 14.3.1 TIMx functional description Time-base unit The main block of the programmable timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: ● Counter Register (TIMx_CNT) ● Prescaler Register (TIMx_PSC): ● Auto-Reload Register (TIMx_ARR) Doc ID 13902 Rev 9 321/995 General-purpose timer (TIMx) RM0008 The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 100 and Figure 101 give some examples of the counter behavior when the prescaler ratio is changed on the fly: Figure 100. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 02 03 Update event (UEV) Prescaler control register 0 1 Write a new value in TIMx_PSC Prescaler buffer 0 1 Prescaler counter 0 01 01 01 01 322/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Figure 101. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 Update event (UEV) Prescaler control register 0 3 Write a new value in TIMx_PSC Prescaler buffer 0 3 Prescaler counter 0 01 23 01 23 14.3.2 Counter modes upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): ● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) ● The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Doc ID 13902 Rev 9 323/995 General-purpose timer (TIMx) RM0008 Figure 102. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Figure 103. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0034 0035 0036 0000 0001 0002 0003 Update interrupt flag (UIF) Figure 104. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0035 0036 0000 0001 Update interrupt flag (UIF) 324/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Figure 105. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register 1F 20 00 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 106. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR Doc ID 13902 Rev 9 325/995 General-purpose timer (TIMx) RM0008 Figure 107. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register F5 36 Auto-reload shadow register F5 36 Write a new value in TIMx_ARR Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): ● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). ● The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. 326/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Figure 108. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) Figure 109. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0002 0001 0000 0036 0035 0034 0033 Update interrupt flag (UIF) Figure 110. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0001 0000 0036 0035 Update interrupt flag (UIF) Doc ID 13902 Rev 9 327/995 General-purpose timer (TIMx) Figure 111. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register 20 1F 00 36 Counter underflow Update event (UEV) Update interrupt flag (UIF) RM0008 Figure 112. Counter timing diagram, Update event when repetition counter is not used CK_INT CNT_EN Timer clock = CK_CNT Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. 328/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): ● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). ● The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. Figure 113. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter underflow Counter overflow Update event (UEV) 04 03 02 01 00 01 02 03 04 05 06 05 04 03 Update interrupt flag (UIF) 1. Here, center-aligned mode 1 is used (for more details refer to Section 14.4.1: TIMx control register 1 (TIMx_CR1) on page 355). Figure 114. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN TImer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0003 0002 0001 0000 0001 0002 0003 Update interrupt flag (UIF) Doc ID 13902 Rev 9 329/995 General-purpose timer (TIMx) RM0008 Figure 115. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow (cnt_ovf) Update event (UEV) 0034 0035 0036 0035 Update interrupt flag (UIF) Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow Figure 116. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register 20 1F 01 00 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 117. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register FD 36 Write a new value in TIMx_ARR Auto-reload active register FD 36 330/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Figure 118. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register FD 36 Write a new value in TIMx_ARR Auto-reload active register FD 36 14.3.3 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (CK_INT) ● External clock mode1: external input pin (TIx) ● External clock mode2: external trigger input (ETR) ● Internal trigger inputs (ITRx) : using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to : Using one timer as prescaler for the another on page 350 for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 119 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Doc ID 13902 Rev 9 331/995 General-purpose timer (TIMx) Figure 119. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN UG CNT_INIT Counter clock = CK_CNT = CK_PSC COUNTER REGISTER 31 32 33 34 35 36 00 01 02 03 04 05 06 07 RM0008 Note: External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 120. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2 Filter Edge Detector ICF[3:0] TIMx_CCMR1 TI2F_Rising0 TI2F_Falling 1 ITRx or TI2F or TI1F or 001 TI1F_ED100 TI1FP1 101 TRGI TI2FP2 110 ETRF 111 ETRF encoder mode external clock mode 1 CK_PSC external clock mode 2 CC2P TIMx_CCER CK_INT internal clock (internal clock) mode ECE SMS[2:0] TIMx_SMCR For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. 3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. 332/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 121. Control circuit in external clock mode 1 TI2 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 Write TIF=0 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. The Figure 122 gives an overview of the external trigger input block. Figure 122. External trigger input block ETR pin ETR 0 1 ETP TIMx_SMCR divider ETRP /1, /2, /4, /8 CK_INT filter downcounter ETPS[1:0] TIMx_SMCR ETF[3:0] TIMx_SMCR or TI2F or TI1F or encoder mode TRGI external clock mode 1 CK_PSC ETRF external clock mode 2 CK_INT internal clock (internal clock) mode ECE SMS[2:0] TIMx_SMCR For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Doc ID 13902 Rev 9 333/995 General-purpose timer (TIMx) Figure 123. Control circuit in external clock mode 2 fMASTER CNT_EN ETR ETRP ETRF Counter clock = CK_CNT = CK_PSC Counter register 34 35 RM0008 36 14.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). The following figure gives an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). Figure 124. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1 filter TI1F Edge TI1F_Rising 0 TI1FP1 fDTS downcounter Detector TI1F_Falling 1 TI2FP1 01 10 IC1 divider IC1PS /1, /2, /4, /8 ICF[3:0] TIMx_CCMR1 CC1P TIMx_CCER TI2F_rising 0 (from channel 2) TI2F_falling (from channel 2) 1 TRC (from slave mode 11 controller) CC1S[1:0] ICPS[1:0] TIMx_CCMR1 CC1E TIMx_CCER The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. 334/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Figure 125. Capture/compare channel 1 main circuit APB Bus read CCR1H S read CCR1L R CC1S[1] CC1S[0] IC1PS CC1E CC1G TIMx_EGR MCU-peripheral interface high (if 16-bit) low 8 8 read_in_progress write_in_progress Capture/Compare Preload Register S write CCR1H R write CCR1L input mode capture_transfer compare_transfer output mode Capture/Compare Shadow Register capture comparator CC1S[1] CC1S[0] OC1PE OC1PE UEV (from time TIMx_CCMR1 base unit) CNT>CCR1 Counter CNT=CCR1 Figure 126. Output stage of capture/compare channel (channel 1) ETRF To the master mode controller CNT > CCR1 Output Mode oc1ref CNT = CCR1 Controller 0 1 CC1P TIMx_CCER Output Enable Circuit OC1 OC1M[2:0] TIMx_CCMR1 CC1E TIMx_CCER The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. Doc ID 13902 Rev 9 335/995 General-purpose timer (TIMx) RM0008 14.3.5 Note: Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: ● Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. ● Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. ● Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case). ● Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the TIMx_CCMR1 register). ● Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. ● If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: ● The TIMx_CCR1 register gets the value of the counter on the active transition. ● CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. ● An interrupt is generated depending on the CC1IE bit. ● A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. 336/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) 14.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: ● Two ICx signals are mapped on the same TIx input. ● These 2 ICx signals are active on edges with opposite polarity. ● One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): ● Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). ● Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P bit to ‘0’ (active on rising edge). ● Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). ● Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active on falling edge). ● Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). ● Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. ● Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 127. PWM input mode timing TI1 TIMx_CNT 0004 TIMx_CCR1 0000 0001 0002 0004 0003 0004 0000 TIMx_CCR2 0002 14.3.7 IC1 capture IC2 capture reset counter IC2 capture pulse width measurement IC1 capture period measurement ai15413 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. Doc ID 13902 Rev 9 337/995 General-purpose timer (TIMx) RM0008 14.3.8 To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. e.g.: CCxP=0 (OCx active high) => OCx is forced to high level. ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: ● Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. ● Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). ● Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). ● Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on ocxref and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One Pulse Mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated. 4. Select the output mode. For example, you must write OCxM=’011’, OCxPE=’0’, CCxP=’0’ and CCxE=’1’ to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high. 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 128. 338/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Figure 128. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIMx_CNT 0039 003A 003B TIMx_CCR1 003A OC1REF=OC1 B200 B201 B201 Match detected on CCR1 Interrupt generated if enabled 14.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx TIMx_CNT or TIMx_CNT TIMx_CCRx (depending on the direction of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: ● When the result of the comparison changes, or ● When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000’) to one of the PWM modes (OCxM=‘110’ or ‘111’). This allows to force the PWM by software while running. The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. Doc ID 13902 Rev 9 339/995 General-purpose timer (TIMx) RM0008 PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Section : upcounting mode on page 323. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT 8 CCxIF OCxREF ‘0’ CCRx=0 CCxIF Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting mode on page 326 In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held at ‘1’. 0% PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the ocxref/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to the Center-aligned mode (up/down counting) on page 328. Figure 130 shows some center-aligned PWM waveforms in an example where: ● TIMx_ARR=8, ● PWM mode is the PWM mode 1, ● The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. 340/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Figure 130. Center-aligned PWM waveforms (ARR=8) Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 OCxREF CCRx = 4 CCxIF OCxREF CCRx = 7 CMS=01 CMS=10 CMS=11 CCxIF CMS=10 or 11 OCxREF '1' CCRx = 8 CCxIF OCxREF '1' CCRx > 8 CMS=01 CMS=10 CMS=11 CCxIF OCxREF '0' CCRx = 0 CMS=01 CMS=10 CMS=11 CCxIF CMS=01 CMS=10 CMS=11 ai14681 Hints on using center-aligned mode: ● When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. ● Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. ● The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. Doc ID 13902 Rev 9 341/995 General-purpose timer (TIMx) RM0008 14.3.10 One pulse mode One Pulse Mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One Pulse Mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: In upcounting: CNTCCRx. Figure 131. Example of one pulse mode. TI2 OC1REF OC1 Counter TIM1_ARR TIM1_CCR1 0 tDELAY tPULSE t For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: ● Map TI2FP2 on TI2 by writing IC2S=’01’ in the TIMx_CCMR1 register. ● TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register. ● Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register. ● TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). 342/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The tDELAY is defined by the value written in the TIMx_CCR1 register. ● The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). ● Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). Particular case: OCx fast enable: In One Pulse Mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 14.3.11 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be reset by applying a High level on the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF remains low until the next update event, UEV, occurs. This function can be only used in output compare mode and PWM mode. It does not work in forced mode. For example, the OCxREF signal can be connected to the output of a comparator to be used for current handling. In this case, the ETR must be configured as follow: 1. The external trigger prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’. 2. The external clock mode 2 must be disabled: bit ECE of the TIM1_SMCR register set to ‘0’. 3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the user needs. Figure 132 shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in PWM mode. Doc ID 13902 Rev 9 343/995 General-purpose timer (TIMx) Figure 132. Clearing TIMx OCxREF counter (CNT) (CCRx) RM0008 ETRF OCxREF (OCxCE=’0’) OCxREF (OCxCE=’1’) OCREF_CLR becomes high OCREF_CLR still high 14.3.12 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’ if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, you can program the input filter as well. The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 75. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. 344/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Table 75. Counting direction versus encoder signals Active edge Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) TI1FP1 signal Rising Falling Counting on TI1 only High Low Down Up Up Down Counting on TI2 only High Low No Count No Count No Count No Count Counting on TI1 and TI2 High Low Down Up Up Down TI2FP2 signal Rising No Count No Count Up Down Up Down Falling No Count No Count Down Up Down Up An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. The Figure 133 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: ● CC1S=’01’ (TIMx_CCMR1 register, IC1FP1 mapped on TI1). ● CC2S=’01’ (TIMx_CCMR2 register, IC2FP2 mapped on TI2). ● CC1P=’0’ (TIMx_CCER register, IC1FP1 non-inverted, IC1FP1=TI1). ● CC2P=’0’ (TIMx_CCER register, IC2FP2 non-inverted, IC2FP2=TI2). ● SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges). ● CEN=’1’ (TIMx_CR1 register, Counter is enabled). Figure 133. Example of counter operation in encoder interface mode. forward jitter backward jitter forward TI1 TI2 Counter up down up Figure 134 gives an example of counter behavior when IC1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Doc ID 13902 Rev 9 345/995 General-purpose timer (TIMx) RM0008 Figure 134. Example of encoder interface mode with IC1FP1 polarity inverted. forward jitter backward jitter forward TI1 TI2 Counter down up down The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a Real-Time clock. 14.3.13 Timer input XOR function The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture. An example of this feature used to interface Hall sensors is given in Section 13.3.18 on page 288. 14.3.14 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: ● Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only). 346/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) ● Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. ● Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 135. Control circuit in reset mode TI1 UG Counter clock = CK_CNT = CK_PSC Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03 TIF Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: ● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only). ● Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. ● Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Doc ID 13902 Rev 9 347/995 General-purpose timer (TIMx) Figure 136. Control circuit in gated mode RM0008 TI1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 30 31 32 33 34 TIF Write TIF=0 35 36 37 38 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: ● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. CC2S bits are selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only). ● Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 137. Control circuit in trigger mode TI2 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 37 38 Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register. 348/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: 1. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. 2. Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source – CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge only). 3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. Figure 138. Control circuit in external clock mode 2 + trigger mode TI1 CEN/CNT_EN ETR Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 14.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode. The following figure presents an overview of the trigger selection and the master mode selection blocks. Doc ID 13902 Rev 9 349/995 General-purpose timer (TIMx) RM0008 Using one timer as prescaler for the another Figure 139. Master/Slave timer example Clock Prescaler TIMER 1 MMS TIMER 2 TS SMS UEV Counter Master mode TRGO1 ITR1 control Slave mode control CK_PSC Prescaler Input trigger selection Counter Note: Note: For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 139. To do this: ● Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is output on TRGO1 each time an update event is generated. ● To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in slave mode using ITR1 as internal trigger. You select this through the TS bits in the TIM2_SMCR register (writing TS=000). ● Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow). ● Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register). If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock the counter of timer 2. Using one timer to enable another timer In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1. Refer to Figure 139 for connections. Timer 2 counts on the divided internal clock only when OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3). ● Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register). ● Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register). ● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). ● Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register). ● Enable Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register). ● Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register). The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2 counter enable signal. 350/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Figure 140. Gating timer 2 with OC1REF of timer 1 CK_INT TIMER1-OC1REF TIMER1-CNT TIMER2-CNT TIMER 2-TIF FC 3045 FD FE FF 3046 3047 00 01 3048 Write TIF=0 In the example in Figure 140, the Timer 2 counter and prescaler are not initialized before being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting Timer 1. You can then write any value you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer 2 stops when Timer 1 is disabled by writing ‘0’ to the CEN bit in the TIM1_CR1 register: ● Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register). ● Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register). ● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). ● Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register). ● Reset Timer 1 by writing ‘1’ in UG bit (TIM1_EGR register). ● Reset Timer 2 by writing ‘1’ in UG bit (TIM2_EGR register). ● Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL). ● Enable Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register). ● Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register). ● Stop Timer 1 by writing ‘0’ in the CEN bit (TIM1_CR1 register). Doc ID 13902 Rev 9 351/995 General-purpose timer (TIMx) RM0008 Figure 141. Gating timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT 75 00 01 02 TIMER2-CNT AB 00 E7 E8 E9 TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF Write TIF=0 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 139 for connections. Timer 2 starts counting from its current value (which can be non-zero) on the divided internal clock as soon as the update event is generated by Timer 1. When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0’ to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3). ● Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register). ● Configure the Timer 1 period (TIM1_ARR registers). ● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). ● Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register). ● Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register). Figure 142. Triggering timer 2 with update of timer 1 CK_INT TIMER1-UEV TIMER1-CNT TIMER2-CNT TIMER2-CEN=CNT_EN FD FE FF 45 00 01 02 46 47 48 TIMER 2-TIF Write TIF=0 352/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) As in the previous example, you can initialize both counters before starting counting. Figure 143 shows the behavior with the same configuration as in Figure 142 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 143. Triggering timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT 75 00 01 02 TIMER2-CNT CD 00 E7 TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF E8 E9 EA Write TIF=0 Using one timer as prescaler for another timer For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 139 for connections. To do this: ● Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register). then it outputs a periodic signal on each counter overflow. ● Configure the Timer 1 period (TIM1_ARR registers). ● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). ● Configure Timer 2 in external clock mode 1 (SMS=111 in TIM2_SMCR register). ● Start Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register). ● Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register). Starting 2 timers synchronously in response to an external trigger In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of Timer 2 with the enable of Timer 1. Refer to Figure 139 for connections. To ensure the Doc ID 13902 Rev 9 353/995 General-purpose timer (TIMx) RM0008 Note: counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): ● Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register). ● Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the TIM1_SMCR register). ● Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register). ● Configure the Timer 1 in Master/Slave mode by writing MSM=’1’ (TIM1_SMCR register). ● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). ● Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register). When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on the internal clock and both TIF flags are set. In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0, but you can easily insert an offset between them by writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on timer 1. Figure 144. Triggering timer 1 and 2 with timer 1 TI1 input. CK_INT TIMER 1-TI1 TIMER1-CEN=CNT_EN TIMER 1-CK_PSC TIMER1-CNT TIMER1-TIF TIMER2-CEN=CNT_EN TIMER 2-CK_PSC TIMER2-CNT TIMER2-TIF 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04 05 06 07 08 09 14.3.16 Debug mode When the microcontroller enters debug mode (Cortex-M3 core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBGMCU module. For more details, refer to Section 29.16.2: Debug support for timers, watchdog, bxCAN and I2C. 354/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) 14.4 TIMx registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. 14.4.1 TIMx control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Reserved CKD[1:0] rw rw ARPE rw 6 5 CMS rw rw 4 3 2 1 0 DIR OPM URS UDIS CEN rw rw rw rw rw Bits 15:10 Reserved, always read as 0 Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) Bit 4 DIR: Direction 0: Counter used as upcounter. 1: Counter used as downcounter. Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN). Doc ID 13902 Rev 9 355/995 General-purpose timer (TIMx) RM0008 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one pulse mode, when an update event occurs. 14.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 Reserved 8 7 TI1S rw 6 5 4 MMS[2:0] rw rw rw 3 CCDS rw 2 1 0 Reserved Bits 15:8 Reserved, always read as 0. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input. 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section 13.3.18: Interfacing with Hall sensors on page 288 356/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Bits 6:4 MMS: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 100: Compare - OC1REF signal is used as trigger output (TRGO). 101: Compare - OC2REF signal is used as trigger output (TRGO). 110: Compare - OC3REF signal is used as trigger output (TRGO). 111: Compare - OC4REF signal is used as trigger output (TRGO). Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bits 2:0 Reserved, always read as 0 14.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 15 14 13 12 11 10 9 ETP ECE ETPS[1:0] ETF[3:0] rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 MSM TS[2:0] SMS[2:0] Res. rw rw rw rw rw rw rw rw Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge. Doc ID 13902 Rev 9 357/995 General-purpose timer (TIMx) RM0008 Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled. 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. Bits 13:12 ETPS: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF. 01: ETRP frequency divided by 2. 10: ETRP frequency divided by 4. 11: ETRP frequency divided by 8. Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS. 0001: fSAMPLING=fCK_INT, N=2. 0010: fSAMPLING=fCK_INT, N=4. 0011: fSAMPLING=fCK_INT, N=8. 0100: fSAMPLING=fDTS/2, N=6. 0101: fSAMPLING=fDTS/2, N=8. 0110: fSAMPLING=fDTS/4, N=6. 0111: fSAMPLING=fDTS/4, N=8. 1000: fSAMPLING=fDTS/8, N=6. 1001: fSAMPLING=fDTS/8, N=8. 1010: fSAMPLING=fDTS/16, N=5. 1011: fSAMPLING=fDTS/16, N=6. 1100: fSAMPLING=fDTS/16, N=8. 1101: fSAMPLING=fDTS/32, N=5. 1110: fSAMPLING=fDTS/32, N=6. 1111: fSAMPLING=fDTS/32, N=8. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 358/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). TIM1 001: Internal Trigger 1 (ITR1). TIM2 010: Internal Trigger 2 (ITR2). TIM3 011: Internal Trigger 3 (ITR3). TIM4 100: TI1 Edge Detector (TI1F_ED). 101: Filtered Timer Input 1 (TI1FP1). 110: Filtered Timer Input 2 (TI2FP2). 111: External Trigger input (ETRF). See Table 76: TIMx Internal trigger connection on page 359 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, always read as 0. Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Table 76. TIMx Internal trigger connection(1) Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM2 TIM3 TIM4 TIM5 TIM1 TIM1 TIM1 TIM2 TIM8 TIM2 TIM2 TIM3 TIM3 TIM5 TIM3 TIM4 TIM4 TIM4 TIM8 TIM8 1. When a timer is not present in the product, the corresponding trigger ITRx is not available. Doc ID 13902 Rev 9 359/995 General-purpose timer (TIMx) RM0008 14.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. TDE Res CC4 DE CC3 DE CC2 DE CC1 DE UDE Res. TIE CC4IE CC3IE CC2IE CC1IE UIE Res rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled. Bit 13 Reserved, always read as 0 Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled. Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bit 7 Reserved, always read as 0. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bit 5 Reserved, always read as 0. Bit 4 CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled. Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled. 360/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. 14.4.5 TIMx status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 Reserved CC4OF CC3OF CC2OF CC1OF rc_w0 rc_w0 rc_w0 rc_w0 8 7 Reserved 6 5 4 3 2 1 0 TIF CC4IF CC3IF CC2IF CC1IF UIF Res rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bit 15:13 Reserved, always read as 0. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8:7 Reserved, always read as 0. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bit 5 Reserved, always read as 0 Bit 4 CC4IF: Capture/Compare 4 interrupt flag refer to CC1IF description Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description Doc ID 13902 Rev 9 361/995 General-purpose timer (TIMx) RM0008 Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1 register. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity). Bit 0 UIF: Update interrupt flag –This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. –When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. –When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 14.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TG CC4G CC3G CC2G CC1G UG Res. w w w w w w Bits 15:7 Reserved, always read as 0. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. Bit 5 Reserved, always read as 0. Bit 4 CC4G: Capture/compare 4 generation refer to CC1G description Bit 3 CC3G: Capture/compare 3 generation refer to CC1G description 362/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 14.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 15 OC2 CE rw 14 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2 PE OC2 FE IC2PSC[1:0] rw rw 9 8 CC2S[1:0] rw rw 7 OC1 CE rw 6 5 4 OC1M[2:0] IC1F[3:0] rw rw rw 3 2 OC1 PE OC1 FE IC1PSC[1:0] rw rw 1 0 CC1S[1:0] rw rw Output compare mode Bit 15 OC2CE: Output compare 2 clear enable Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Doc ID 13902 Rev 9 363/995 General-purpose timer (TIMx) RM0008 Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in TIMx_CCER). Bit 7 OC1CE: Output compare 1 clear enable OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=’1’). 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else inactive. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. 364/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in TIMx_CCER). Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in TIMx_CCER). Doc ID 13902 Rev 9 365/995 General-purpose timer (TIMx) RM0008 Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS. 0001: fSAMPLING=fCK_INT, N=2. 0010: fSAMPLING=fCK_INT, N=4. 0011: fSAMPLING=fCK_INT, N=8. 0100: fSAMPLING=fDTS/2, N=6. 0101: fSAMPLING=fDTS/2, N=8. 0110: fSAMPLING=fDTS/4, N=6. 0111: fSAMPLING=fDTS/4, N=8. 1000: fSAMPLING=fDTS/8, N=6. 1001: fSAMPLING=fDTS/8, N=8. 1010: fSAMPLING=fDTS/16, N=5. 1011: fSAMPLING=fDTS/16, N=6. 1100: fSAMPLING=fDTS/16, N=8. 1101: fSAMPLING=fDTS/32, N=5. 1110: fSAMPLING=fDTS/32, N=6. 1111: fSAMPLING=fDTS/32, N=8. Note: In current silicon revision, fDTS is replaced in the formula by CK_INT when ICxF[3:0]= 1, 2 or 3. Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input. 01: capture is done once every 2 events. 10: capture is done once every 4 events. 11: capture is done once every 8 events. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in TIMx_CCER). 366/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) 14.4.8 Capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. 15 14 13 12 11 10 9 8 7 6 5 4 OC4 CE OC4M[2:0] IC4F[3:0] OC4 PE OC4 FE IC4PSC[1:0] CC4S[1:0] OC3 CE. OC3M[2:0] IC3F[3:0] rw rw rw rw rw rw rw rw rw rw rw rw Output compare mode 3 2 OC3 PE OC3 FE IC3PSC[1:0] rw rw 1 0 CC3S[1:0] rw rw Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output. 01: CC4 channel is configured as input, IC4 is mapped on TI4. 10: CC4 channel is configured as input, IC4 is mapped on TI3. 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ’0’ in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output. 01: CC3 channel is configured as input, IC3 is mapped on TI3. 10: CC3 channel is configured as input, IC3 is mapped on TI4. 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in TIMx_CCER). Doc ID 13902 Rev 9 367/995 General-purpose timer (TIMx) RM0008 Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output. 01: CC4 channel is configured as input, IC4 is mapped on TI4. 10: CC4 channel is configured as input, IC4 is mapped on TI3. 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ’0’ in TIMx_CCER). Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output. 01: CC3 channel is configured as input, IC3 is mapped on TI3. 10: CC3 channel is configured as input, IC3 is mapped on TI4. 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in TIMx_CCER). 14.4.9 TIMx capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 Reserved 13 CC4P rw 12 CC4E rw 11 10 Reserved 9 CC3P rw 8 CC3E rw 7 6 Reserved 5 CC2P rw 4 CC2E rw 3 2 Reserved 1 CC1P rw 0 CC1E rw Bits 15:14 Reserved, always read as 0. Bit 13 CC4P: Capture/Compare 4 output polarity refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description Bits 11:10 Reserved, always read as 0. Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description Bits 7:6 Reserved, always read as 0. Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description 368/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bits 3:2 Reserved, always read as 0. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low. CC1 channel configured as input: This bit selects whether IC1 or IC1 is used for trigger or capture operations. 0: non-inverted: capture is done on a rising edge of IC1. When used as external trigger, IC1 is non-inverted. 1: inverted: capture is done on a falling edge of IC1. When used as external trigger, IC1 is inverted. Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. 1: On - OC1 signal is output on the corresponding output pin. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. Table 77. Output control bit for standard OCx channels CCxE bit OCx output state 0 Output Disabled (OCx=0, OCx_EN=0) 1 OCx=OCxREF + Polarity, OCx_EN=1 Note: The state of the external I/O pins connected to the standard OCx channels depends on the OCx channel state and the GPIO and AFIO registers. 14.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value Doc ID 13902 Rev 9 369/995 General-purpose timer (TIMx) RM0008 14.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. 14.4.12 TIMx auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 14.3.1: Time-base unit on page 321 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 14.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 370/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) 14.4.14 TIMx capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR2[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 14.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR3[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR3[15:0]: Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). Doc ID 13902 Rev 9 371/995 General-purpose timer (TIMx) RM0008 14.4.16 TIMx capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR4[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR4[15:0]: Capture/Compare value 1/ if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. 2/ if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). 14.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 12 11 10 9 8 Reserved DBL[4:0] rw rw rw rw rw 7 6 5 Reserved 4 3 2 1 0 DBA[4:0] rw rw rw rw rw Bits 15:13 Reserved, always read as 0 Bits 12:8 DBL[4:0]: DMA burst length This 5-bits vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of bytes to be transferred. 00000: 1 byte, 00001: 2 bytes, 00010: 3 bytes, ... 10001: 18 bytes. Bits 7:5 Reserved, always read as 0 Bits 4:0 DBA[4:0]: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... 372/995 Doc ID 13902 Rev 9 RM0008 General-purpose timer (TIMx) 14.4.18 TIMx DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAB[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write access to the DMAR register accesses the register located at the address: “(TIMx_CR1 address) + DBA + (DMA index)” in which: TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in the TIMx_DCR register, DMA index is the offset automatically controlled by the DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register. 14.4.19 TIMx register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 78. TIMx register map and reset values Offset Register 0x00 0x04 0x08 TIMx_CR1 Reset value TIMx_CR2 Reset value TIMx_SMCR Reset value Reserved Reserved Reserved 0x0C TIMx_DIER Reset value 0x10 TIMx_SR Reset value 0x14 0x18 TIMx_EGR Reset value TIMx_CCMR1 Output Compare mode Reset value TIMx_CCMR1 Input Capture mode Reset value Reserved Reserved Reserved Reserved Reserved OC2CE ETP CKD [1:0] CMS [1:0] 0000000000 TI1S CCDS MMS[2:0] Reserved 00000 MSM ECE ETPS [1:0] ETF[3:0] TS[2:0] SMS[2:0] 000000000000 000 UIE CC1G CC1IF CC1IE OC1FE CC2G CC2IF CC2IE OC1PE CC3G CC3IF CC3IE Reserved CC4G CC4IF CC4IE Reserved Reserved Reserved TIE UDE Reserved Reserved CC1OF CC1DE CC2OF CC2DE CC3OF CC3DE CC4OF CC4DE COMDE TDE 0000000 0 00000 UIF TIF 0000 0 00000 UG TG 0 00000 OC1CE OC2FE OC2PE OC2M [2:0] CC2S [1:0] OC1M [2:0] CC1S [1:0] 0000 IC2F[3:0] 0000 00 IC2 PSC [1:0] 00 00 CC2S [1:0] 00 0000 IC1F[3:0] 0000 00 IC1 PSC [1:0] 00 00 CC1S [1:0] 00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ARPE 7 6 5 DIR 4 OPM 3 URS 2 UDIS 1 CEN 0 Doc ID 13902 Rev 9 373/995 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 O24CE 15 14 13 12 OC4PE 11 OC4FE 10 9 8 OC3CE 7 6 5 4 OC3PE 3 OC3FE 2 1 0 General-purpose timer (TIMx) RM0008 Table 78. TIMx register map and reset values (continued) Offset Register 0x1C TIMx_CCMR2 Output Compare mode Reset value TIMx_CCMR2 Input Capture mode Reset value Reserved Reserved OC4M [2:0] CC4S [1:0] OC3M [2:0] CC3S [1:0] 0000 IC4F[3:0] 0000 00 IC4 PSC [1:0] 00 00 CC4S [1:0] 00 0000 IC3F[3:0] 0000 00 IC3 PSC [1:0] 00 00 CC3S [1:0] 00 CC4P CC4E Reserved CC3P CC3E Reserved CC2P CC2E Reserved CC1P CC1E 0x20 TIMx_CCER Reset value Reserved 00 00 00 00 0x24 TIMx_CNT Reset value Reserved CNT[15:0] 0000000000000000 0x28 TIMx_PSC Reset value Reserved PSC[15:0] 0000000000000000 0x2C TIMx_ARR Reset value Reserved ARR[15:0] 0000000000000000 0x30 Reserved 0x34 0x38 0x3C 0x40 0x44 TIMx_CCR1 Reset value TIMx_CCR2 Reset value TIMx_CCR3 Reset value TIMx_CCR4 Reset value Reserved Reserved Reserved Reserved Reserved CCR1[15:0] 0000000000000000 CCR2[15:0] 0000000000000000 CCR3[15:0] 0000000000000000 CCR4[15:0] 0000000000000000 0x48 0x4C TIMx_DCR Reset value TIMx_DMAR Reset value Reserved Reserved DBL[4:0] Reserved DBA[4:0] 00000 00000 DMAB[15:0] 0000000000000000 Refer to Table 1 on page 41 for the register boundary addresses. 374/995 Doc ID 13902 Rev 9 RM0008 15 Basic timers (TIM6&TIM7) Basic timers (TIM6&TIM7) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to high-density STM32F101xx and STM32F103xx devices, and to connectivity line devices only. 15.1 TIM6&TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs. The timers are completely independent, and do not share any resources. 15.2 TIM6&TIM7 main features Basic timer (TIM6&TIM7) features include: ● 16-bit auto-reload upcounter ● 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 ● Synchronization circuit to trigger the DAC ● Interrupt/DMA generation on the update event: counter overflow Doc ID 13902 Rev 9 375/995 Basic timers (TIM6&TIM7) Figure 145. Basic timer block diagram RM0008 Internal clock (CK_INT) TIMxCLK from RCC Trigger TRGO to DAC controller Controller Reset, Enable, Count, U Auto-reload Register UI Stop, Clear or up U CK_PSC PSC Prescaler CK_CNT ± CNT COUNTER Flag Preload registers transferred to active registers on U event according to control bit event interrupt & DMA output ai14749b 15.3 15.3.1 TIM6&TIM7 functional description Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: ● Counter Register (TIMx_CNT) ● Prescaler Register (TIMx_PSC) ● Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set. Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. 376/995 Doc ID 13902 Rev 9 RM0008 Basic timers (TIM6&TIM7) Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 146 and Figure 147 give some examples of the counter behavior when the prescaler ratio is changed on the fly. Figure 146. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 02 03 Update event (UEV) Prescaler control register 0 1 Write a new value in TIMx_PSC Prescaler buffer 0 1 Prescaler counter 0 01 01 01 01 Figure 147. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 Update event (UEV) Prescaler control register 0 3 Write a new value in TIMx_PSC Prescaler buffer 0 3 Prescaler counter 0 01 23 01 23 Doc ID 13902 Rev 9 377/995 Basic timers (TIM6&TIM7) RM0008 15.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent). When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit): ● The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register) ● The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36. Figure 148. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) 378/995 Doc ID 13902 Rev 9 RM0008 Basic timers (TIM6&TIM7) Figure 149. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0034 0035 0036 0000 0001 0002 0003 Update interrupt flag (UIF) Figure 150. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0035 0036 0000 0001 Update interrupt flag (UIF) Figure 151. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register 1F 20 00 Counter overflow Update event (UEV) Update interrupt flag (UIF) Doc ID 13902 Rev 9 379/995 Basic timers (TIM6&TIM7) RM0008 Figure 152. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR Figure 153. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register F5 36 Auto-reload shadow register F5 36 Write a new value in TIMx_ARR 15.3.3 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 154 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. 380/995 Doc ID 13902 Rev 9 RM0008 Basic timers (TIM6&TIM7) Figure 154. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN UG CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 15.3.4 Debug mode When the microcontroller enters the debug mode (Cortex-M3 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 29.16.2: Debug support for timers, watchdog, bxCAN and I2C. 15.4 TIM6&TIM7 registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. 15.4.1 TIM6&TIM7 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 ARPE rw Reserved 3 OPM rw 2 URS rw 1 UDIS rw 0 CEN rw Bits 15:8 Reserved, always read as 0 Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, always read as 0 Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit). Doc ID 13902 Rev 9 381/995 Basic timers (TIM6&TIM7) RM0008 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 382/995 Doc ID 13902 Rev 9 RM0008 Basic timers (TIM6&TIM7) 15.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MMS[2:0] rw rw rw Reserved Bits 15:7 Reserved, always read as 0. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). 010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. Bits 3:0 Reserved, always read as 0 15.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Reserved UDE rw Reserved 1 0 UIE rw Bit 15:9 Reserved, always read as 0. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bit 7:1 Reserved, always read as 0. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. Doc ID 13902 Rev 9 383/995 Basic timers (TIM6&TIM7) RM0008 15.4.4 TIM6&TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UIF rc_w0 Bits 15:1 Reserved, always read as 0. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. –When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 15.4.5 TIM6&TIM7 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UG Reserved w Bits 15:1 Reserved, always read as 0. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). 15.4.6 TIM6&TIM7 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 384/995 Doc ID 13902 Rev 9 RM0008 Basic timers (TIM6&TIM7) 15.4.7 TIM6&TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. 15.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 15.3.1: Time-base unit on page 376 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Doc ID 13902 Rev 9 385/995 CEN 0 Basic timers (TIM6&TIM7) RM0008 UIE UIF 15.4.9 TIM6&TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 79. TIM6&TIM7 register map and reset values Offset Register 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x00 0x04 0x08 TIMx_CR1 Reset value TIMx_CR2 Reset value Reserved Reserved Reserved 17 16 15 14 13 12 11 10 9 8 ARPE 7 6 Reserved 5 4 0 0000 Reserved MMS[2:0] 000 OPM 3 URS 2 UDIS 1 Reserved UDE 0x0C 0x10 0x14 0x18 TIMx_DIER Reset value TIMx_SR Reset value TIMx_EGR Reset value Reserved 0 0 Reserved 0 Reserved 0 Reserved 0x1C Reserved 0x20 Reserved 0x24 0x28 0x2C TIMx_CNT Reset value TIMx_PSC Reset value TIMx_ARR Reset value Reserved Reserved Reserved CNT[15:0] 0000000000000000 PSC[15:0] 0000000000000000 ARR[15:0] 0000000000000000 Refer to Table 1 on page 41 for the register boundary addresses. UG 386/995 Doc ID 13902 Rev 9 RM0008 16 Real-time clock (RTC) Real-time clock (RTC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 16.1 RTC introduction The real-time clock is an independent timer. The RTC provides a set of continuously running counters which can be used, with suitable software, to provide a clock-calendar function. The counter values can be written to set the current time/date of the system. The RTC core and clock configuration (RCC_BDCR register) are in the Backup domain, which means that RTC setting and time are kept after reset or wakeup from Standby mode. After reset, access to the Backup registers and RTC is disabled and the Backup domain (BKP) is protected against possible parasitic write access. To enable access to the Backup registers and the RTC, proceed as follows: ● enable the power and backup interface clocks by setting the PWREN and BKPEN bits in the RCC_APB1ENR register ● set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup registers and RTC. Doc ID 13902 Rev 9 387/995 Real-time clock (RTC) RM0008 16.2 RTC main features ● Programmable prescaler: division factor up to 220 ● 32-bit programmable counter for long-term measurement ● Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least four times slower than the PCLK1 clock) ● The RTC clock source could be any of the following three: – HSE clock divided by 128 – LSE oscillator clock – LSI oscillator clock (refer to Section 6.2.8: RTC clock for details) ● Two separate reset types: – The APB1 interface is reset by system reset – The RTC Core (Prescaler, Alarm, Counter and Divider) is reset only by a Backup domain reset (see Section 6.1.3: Backup domain reset on page 75). ● Three dedicated maskable interrupt lines: – Alarm interrupt, for generating a software programmable alarm interrupt. – Seconds interrupt, for generating a periodic interrupt signal with a programmable period length (up to 1 second). – Overflow interrupt, to detect when the internal programmable counter rolls over to zero. 16.3 16.3.1 RTC functional description Overview The RTC consists of two main units (see Figure 155 on page 389). The first one (APB1 Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit registers accessible from the APB1 bus in read or write mode (for more information refer to Section 16.4: RTC registers on page 392). The APB1 interface is clocked by the APB1 bus clock in order to interface with the APB1 bus. The other unit (RTC Core) consists of a chain of programmable counters made of two main blocks. The first block is the RTC prescaler block, which generates the RTC time base TR_CLK that can be programmed to have a period of up to 1 second. It includes a 20-bit programmable divider (RTC Prescaler). Every TR_CLK period, the RTC generates an interrupt (Second Interrupt) if it is enabled in the RTC_CR register. The second block is a 32-bit programmable counter that can be initialized to the current system time. The system time is incremented at the TR_CLK rate and compared with a programmable date (stored in the RTC_ALR register) in order to generate an alarm interrupt, if enabled in the RTC_CR control register. 388/995 Doc ID 13902 Rev 9 RM0008 Real-time clock (RTC) Figure 155. RTC simplified block diagram PCLK1 APB1 bus APB1 interface not powered in Standby RTCCLK Backup domain RTC_PRL Reload RTC_DIV TR_CLK rising edge RTC prescaler 32-bit programmable counter RTC_CNT RTC_Second RTC_Overflow RTC_Alarm = RTC_ALR powered in Standby powered in Standby WKUP pin RTC_Alarm WKP_STDBY RTC_CR SECF SECIE OWF OWIE ALRF ALRIE not powered in Standby NVIC interrupt controller not powered in Standby exit Standby mode powered in Standby ai14969 Doc ID 13902 Rev 9 389/995 Real-time clock (RTC) RM0008 16.3.2 16.3.3 16.3.4 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset. Refer to Section 6.1.3 on page 75. Reading RTC registers The RTC core is completely independent from the RTC APB1 interface. Software accesses the RTC prescaler, counter and alarm values through the APB1 interface but the associated readable registers are internally updated at each rising edge of the RTC clock resynchronized by the RTC APB1 clock. This is also true for the RTC flags. This means that the first read to the RTC APB1 registers may be corrupted (generally read as 0) if the APB1 interface has previously been disabled and the read occurs immediately after the APB1 interface is enabled but before the first internal update of the registers. This can occur if: ● A system reset or power reset has occurred ● The MCU has just woken up from Standby mode (see Section 4.3: Low-power modes) ● The MCU has just woken up from Stop mode (see Section 4.3: Low-power modes) In all the above cases, the RTC core has been kept running while the APB1 interface was disabled (reset, not clocked or unpowered). Consequently when reading the RTC registers, after having disabled the RTC APB1 interface, the software must first wait for the RSF bit (Register Synchronized Flag) in the RTC_CRL register to be set by hardware. Note that the RTC APB1 interface is not affected by WFI and WFE low-power modes. Configuring RTC registers To write in the RTC_PRL, RTC_CNT, RTC_ALR registers, the peripheral must enter Configuration Mode. This is done by setting the CNF bit in the RTC_CRL register. In addition, writing to any RTC register is only enabled if the previous write operation is finished. To enable the software to detect this situation, the RTOFF status bit is provided in the RTC_CR register to indicate that an update of the registers is in progress. A new value can be written to the RTC registers only when the RTOFF status bit value is ’1’. Configuration procedure: 1. Poll RTOFF, wait until its value goes to ‘1’ 2. Set the CNF bit to enter configuration mode 3. Write to one or more RTC registers 4. Clear the CNF bit to exit configuration mode 5. Poll RTOFF, wait until its value goes to ‘1’ to check the end of the write operation. The write operation only executes when the CNF bit is cleared; it takes at least three RTCCLK cycles to complete. 390/995 Doc ID 13902 Rev 9 RM0008 Real-time clock (RTC) 16.3.5 RTC flag assertion The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update of the RTC Counter. The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0000. The RTC_Alarm and RTC Alarm flag (ALRF) (see Figure 156) are asserted on the last RTC Core clock cycle before the counter reaches the RTC Alarm value stored in the Alarm register increased by one (RTC_ALR + 1). The write operation in the RTC Alarm and RTC Second flag must be synchronized by using one of the following sequences: ● Use the RTC Alarm interrupt and inside the RTC interrupt routine, the RTC Alarm and/or RTC Counter registers are updated. ● Wait for SECF bit to be set in the RTC Control register. Update the RTC Alarm and/or the RTC Counter register. Figure 156. RTC second and alarm waveform example with PR=0003, ALARM=00004 RTCCLK RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 RTC_Second RTC_CNT 0000 0001 0002 0003 0004 0005 RTC_ALARM ALRF (not powered in Standby) 1 RTCCLK can be cleared by software Figure 157. RTC Overflow waveform example with PR=0003 RTCCLK RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 RTC_Second RTC_CNT FFFFFFFB FFFFFFFC FFFFFFFD FFFFFFFE FFFFFFFF 0000 RTC_Overflow OWF (not powered in Standby) 1 RTCCLK can be cleared by software Doc ID 13902 Rev 9 391/995 Real-time clock (RTC) RM0008 16.4 16.4.1 RTC registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. RTC control register high (RTC_CRH) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OWIE ALRIE SECIE rw rw rw Bits 15:3 Reserved, forced by hardware to 0. Bit 2 OWIE: Overflow interrupt enable 0: Overflow interrupt is masked. 1: Overflow interrupt is enabled. Bit 1 ALRIE: Alarm interrupt enable 0: Alarm interrupt is masked. 1: Alarm interrupt is enabled. Bit 0 SECIE: Second interrupt enable 0: Second interrupt is masked. 1: Second interrupt is enabled. These bits are used to mask interrupt requests. Note that at reset all interrupts are disabled, so it is possible to write to the RTC registers to ensure that no interrupt requests are pending after initialization. It is not possible to write to the RTC_CRH register when the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 16.3.4 on page 390). The RTC functions are controlled by this control register. Some bits must be written using a specific configuration procedure (see Configuration procedure:). 392/995 Doc ID 13902 Rev 9 RM0008 Real-time clock (RTC) 16.4.2 RTC control register low (RTC_CRL) Address offset: 0x04 Reset value: 0x0020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RTOFF r CNF rw RSF OWF ALRF SECF rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:6 Reserved, forced by hardware to 0. Bit 5 RTOFF: RTC operation OFF With this bit the RTC reports the status of the last write operation performed on its registers, indicating if it has been completed or not. If its value is ‘0’ then it is not possible to write to any of the RTC registers. This bit is read only. 0: Last write operation on RTC registers is still ongoing. 1: Last write operation on RTC registers terminated. Bit 4 CNF: Configuration flag This bit must be set by software to enter in configuration mode so as to allow new values to be written in the RTC_CNT, RTC_ALR or RTC_PRL registers. The write operation is only executed when the CNF bit is reset by software after has been set. 0: Exit configuration mode (start update of RTC registers). 1: Enter configuration mode. Bit 3 RSF: Registers synchronized flag This bit is set by hardware at each time the RTC_CNT and RTC_DIV registers are updated and cleared by software. Before any read operation after an APB1 reset or an APB1 clock stop, this bit must be cleared by software, and the user application must wait until it is set to be sure that the RTC_CNT, RTC_ALR or RTC_PRL registers are synchronized. 0: Registers not yet synchronized. 1: Registers synchronized. Bit 2 OWF: Overflow flag This bit is set by hardware when the 32-bit programmable counter overflows. An interrupt is generated if OWIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect. 0: Overflow not detected 1: 32-bit programmable counter overflow occurred. Bit 1 ALRF: Alarm flag This bit is set by hardware when the 32-bit programmable counter reaches the threshold set in the RTC_ALR register. An interrupt is generated if ALRIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect. 0: Alarm not detected 1: Alarm detected Bit 0 SECF: Second flag This bit is set by hardware when the 32-bit programmable prescaler overflows, thus incrementing the RTC counter. Hence this flag provides a periodic signal with a period corresponding to the resolution programmed for the RTC counter (usually one second). An interrupt is generated if SECIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect. 0: Second flag condition not met. 1: Second flag condition met. Doc ID 13902 Rev 9 393/995 Real-time clock (RTC) RM0008 The functions of the RTC are controlled by this control register. It is not possible to write to the RTC_CR register while the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 16.3.4 on page 390). Note: 1 Any flag remains pending until the appropriate RTC_CR request bit is reset by software, indicating that the interrupt request has been granted. 2 At reset the interrupts are disabled, no interrupt requests are pending and it is possible to write to the RTC registers. 3 The OWF, ALRF, SECF and RSF bits are not updated when the APB1 clock is not running. 4 The OWF, ALRF, SECF and RSF bits can only be set by hardware and only cleared by software. 5 If ALRF = 1 and ALRIE = 1, the RTC global interrupt is enabled. If EXTI Line 17 is also enabled through the EXTI Controller, both the RTC global interrupt and the RTC Alarm interrupt are enabled. 6 If ALRF = 1, the RTC Alarm interrupt is enabled if EXTI Line 17 is enabled through the EXTI Controller in interrupt mode. When the EXTI Line 17 is enabled in event mode, a pulse is generated on this line (no RTC Alarm interrupt generation). 16.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) The Prescaler Load registers keep the period counting value of the RTC prescaler. They are write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. RTC prescaler load register high (RTC_PRLH) Address offset: 0x08 Write only (see Section 16.3.4 on page 390) Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PRL[19:16] w w w w Bits 15:4 Reserved, forced by hardware to 0. Bits 3:0 PRL[19:16]: RTC prescaler reload value high These bits are used to define the counter clock frequency according to the following formula: fTR_CLK = fRTCCLK/(PRL[19:0]+1) Caution: The zero value is not recommended. RTC interrupts and flags cannot be asserted correctly. 394/995 Doc ID 13902 Rev 9 RM0008 Real-time clock (RTC) RTC prescaler load register low (RTC_PRLL) Address offset: 0x0C Write only (see Section 16.3.4 on page 390) Reset value: 0x8000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRL[15:0] w w w w w w w w w w w w w w w w Note: Bits 15:0 PRL[15:0]: RTC prescaler reload value low These bits are used to define the counter clock frequency according to the following formula: fTR_CLK = fRTCCLK/(PRL[19:0]+1) If the input clock frequency (fRTCCLK) is 32.768 kHz, write 7FFFh in this register to get a signal period of 1 second. 16.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) During each period of TR_CLK, the counter inside the RTC prescaler is reloaded with the value stored in the RTC_PRL register. To get an accurate time measurement it is possible to read the current value of the prescaler counter, stored in the RTC_DIV register, without stopping it. This register is read-only and it is reloaded by hardware after any change in the RTC_PRL or RTC_CNT registers. RTC prescaler divider register high (RTC_DIVH) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RTC_DIV[19:16] r r r r Bits 15:4 Reserved Bits 3:0 RTC_DIV[19:16]: RTC clock divider high RTC prescaler divider register low (RTC_DIVL) Address offset: 0x14 Reset value: 0x8000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_DIV[15:0] r r r r r r r r r r r r r r r r Bits 15:0 RTC_DIV[15:0]: RTC clock divider low Doc ID 13902 Rev 9 395/995 Real-time clock (RTC) RM0008 16.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the TR_CLK time reference, generated by the prescaler. RTC_CNT registers keep the counting value of this counter. They are write-protected by bit RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. A write operation on the upper (RTC_CNTH) or lower (RTC_CNTL) registers directly loads the corresponding programmable counter and reloads the RTC Prescaler. When reading, the current value in the counter (system date) is returned. RTC counter register high (RTC_CNTH) Address offset: 0x18 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_CNT[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 RTC_CNT[31:16]: RTC counter high Reading the RTC_CNTH register, the current value of the high part of the RTC Counter register is returned. To write to this register it is necessary to enter configuration mode (see Section 16.3.4: Configuring RTC registers on page 390). RTC counter register low (RTC_CNTL) Address offset: 0x1C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 RTC_CNT[15:0]: RTC counter low Reading the RTC_CNTL register, the current value of the lower part of the RTC Counter register is returned. To write to this register it is necessary to enter configuration mode (see Section 16.3.4: Configuring RTC registers on page 390). 396/995 Doc ID 13902 Rev 9 RM0008 Real-time clock (RTC) 16.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) When the programmable counter reaches the 32-bit value stored in the RTC_ALR register, an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. RTC alarm register high (RTC_ALRH) Address offset: 0x20 Write only (see Section 16.3.4 on page 390) Reset value: 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_ALR[31:16] w w w w w w w w w w w w w w w w Bits 15:0 RTC_ALR[31:16]: RTC alarm high The high part of the alarm time is written by software in this register. To write to this register it is necessary to enter configuration mode (see Section 16.3.4: Configuring RTC registers on page 390). RTC alarm register low (RTC_ALRL) Address offset: 0x24 Write only (see Section 16.3.4 on page 390) Reset value: 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_ALR[15:0] w w w w w w w w w w w w w w w w Bits 15:0 RTC_ALR[15:0]: RTC alarm low The low part of the alarm time is written by software in this register. To write to this register it is necessary to enter configuration mode (see Section 16.3.4: Configuring RTC registers on page 390). Doc ID 13902 Rev 9 397/995 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 OWIE 2 ALRIE 1 SECIE 0 Real-time clock (RTC) RM0008 RTOFF CNF RSF OWF ALRF SECF 16.4.7 RTC register map RTC registers are mapped as 16-bit addressable registers as described in the table below: Table 80. RTC register map and reset values Offset Register 0x000 0x004 0x008 RTC_CRH Reset value RTC_CRL Reset value RTC_PRLH Reset value Reserved Reserved Reserved 000 100000 PRL[19:16] 0000 0x00C RTC_PRLL Reset value Reserved PRL[15:0] 1000000000000000 0x010 RTC_DIVH Reset value Reserved DIV[31:16] 0000000000000000 0x014 0x018 0x01C 0x020 RTC_DIVL Reset value RTC_CNTH Reset value RTC_CNTL Reset value RTC_ALRH Reset value Reserved Reserved Reserved Reserved DIV[15:0] 1000000000000000 CNT[13:16] 0000000000000000 CNT[15:0] 0000000000000000 ALR[31:16] 1111111111111111 0x024 RTC_ALRL Reset value Reserved ALR[15:0] 1111111111111111 Refer to Table 1 on page 41 for the register boundary addresses. 398/995 Doc ID 13902 Rev 9 RM0008 17 Independent watchdog (IWDG) Independent watchdog (IWDG) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 17.1 IWDG introduction The STM32F10xxx has two embedded watchdog peripherals which offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value. The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. The window watchdog (WWDG) clock is prescaled from the APB1 clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior. The IWDG is best suited to applications which require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy constraints. The WWDG is best suited to applications which require the watchdog to react within an accurate timing window. For further information on the window watchdog, refer to Section 18 on page 404. 17.2 IWDG main features ● Free-running downcounter ● clocked from an independent RC oscillator (can operate in Standby and Stop modes) ● Reset (if watchdog activated) when the downcounter value of 0x000 is reached 17.3 IWDG functional description Figure 158 shows the functional blocks of the independent watchdog module. When the independent watchdog is started by writing the value 0xCCCC in the Key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. Doc ID 13902 Rev 9 399/995 Independent watchdog (IWDG) RM0008 17.3.1 17.3.2 17.3.3 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and will generate a reset unless the Key register is written by the software before the counter reaches end of count. Register access protection Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you must first write the code 0x5555 in the IWDG_KR register. A write access to this register with a different value will break the sequence and register access will be protected again. This implies that it is the case of the reload operation (writing 0xAAAA). A status register is available to indicate that an update of the prescaler or the down-counter reload value is on going. Debug mode When the microcontroller enters debug mode (Cortex-M3 core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module. For more details, refer to Section 29.16.2: Debug support for timers, watchdog, bxCAN and I2C. Figure 158. Independent watchdog block diagram 1.8 V voltage domain Prescaler register IWDG_PR Status register IWDG_SR Reload register IWDG_RLR Key register IWDG_KR LSI 8-bit (40 kHz) prescaler VDD voltage domain 12-bit reload value 12-bit downcounter IWDG RESET Note: The watchdog function is implemented in the VDD voltage domain that is still functional in Stop and Standby modes. Table 81. Watchdog timeout period (with 40 kHz input clock)Min/max IWDG timeout period at 32 kHz (LSI) (1) Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= 0x000 Max timeout (ms) RL[11:0]= 0xFFF /4 0 0.1 /8 1 0.2 /16 2 0.4 /32 3 0.8 /64 4 1.6 /128 5 3.2 /256 6 (or 7) 6.4 409.6 819.2 1638.4 3276.8 6553.6 13107.2 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. 400/995 Doc ID 13902 Rev 9 RM0008 Independent watchdog (IWDG) The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy. For more details refer to LSI calibration on page 80. 17.4 IWDG registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. 17.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved KEY[15:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w w w w w w w w w Bits 31:16 Reserved, read as 0. Bits 15:0 KEY[15:0]: Key value (write only, read 0000h) These bits must be written by software at regular intervals with the key value AAAAh, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 5555h to enables access to the IWDG_PR and IWDG_RLR registers (see Section 17.3.2) Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected) 17.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved PR[2:0] rw rw rw Bits 31:3 Reserved, read as 0. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected seeSection 17.3.2. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. 000: divider /4 001: divider /8 010: divider /16 011: divider /32 100: divider /64 101: divider /128 110: divider /256 111: divider /256 Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset. Doc ID 13902 Rev 9 401/995 Independent watchdog (IWDG) RM0008 17.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RL[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, read as 0. Bits11:0 RL[11:0]: Watchdog counter reload value These bits are write access protected see Section 17.3.2. They are written by software to define the value to be loaded in the watchdog counter each time the value AAAAh is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to Table 81. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on this register. For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset. 17.4.4 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved RVU PVU rr Bits 31:2 Reserved Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset. Bit 0 PVU: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset. Note: If several reload values or prescaler values are used by application, it is mandatory to wait until RVU bit is reset before changing the reload value and to wait until PVU bit is reset before changing the prescaler value. However, after updating the prescaler and/or the reload value it is not necessary to wait until RVU or PVU is reset before continuing code execution (even in case of low-power mode entry, the write operation is taken into account and will complete) 402/995 Doc ID 13902 Rev 9 0 RM0008 Independent watchdog (IWDG) 17.4.5 IWDG register map The following table gives the IWDG register map and reset values. Table 82. IWDG register map and reset values Offset Register 21 22 23 24 25 26 27 28 29 30 31 0x00 0x04 0x08 IWDG_KR Reset value IWDG_PR Reset value IWDG_RLR Reset value Reserved Reserved 0x0C IWDG_SR Reset value 20 19 18 17 16 15 14 13 12 11 10 9 KEY[15:0] 0000000000000000 Reserved PR[2:0] 000 RL[11:0] 111111111111 RVU Reserved 00 8 7 6 5 4 3 2 1 PVU Refer to Table 1 on page 41 for the register boundary addresses. Doc ID 13902 Rev 9 403/995 Window watchdog (WWDG) 18 Window watchdog (WWDG) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 18.1 WWDG introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window. 18.2 WWDG main features ● Programmable free-running downcounter ● Conditional reset – Reset (if watchdog activated) when the downcounter value becomes less than 40h – Reset (if watchdog activated) if the downcounter is reloaded outside the window (see Figure 160) ● Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when the downcounter is equal to 40h. Can be used to reload the counter and prevent WWDG reset 18.3 WWDG functional description If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the 7-bit downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T6 becomes cleared), it initiates a reset. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. 404/995 Doc ID 13902 Rev 9 RM0008 Window watchdog (WWDG) Figure 159. Watchdog block diagram RESET Watchdog configuration register (WWDG_CFR) - W6 W5 W4 W3 W2 W1 W0 comparator = 1 when T6:0 > W6:0 CMP Write WWDG_CR Watchdog control register (WWDG_CR) WDGA T6 PCLK1 (from RCC clock controller) T5 T4 T3 T2 T1 T0 6-bit downcounter (CNT) WDG prescaler (WDGTB) Note: The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0: ● Enabling the watchdog: The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. ● Controlling the downcounter: This downcounter is free-running: It counts down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register (see Figure 160). The Configuration register (WWDG_CFR) contains the high limit of the window: To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x3F. Figure 160 describes the window watchdog process. Another way to reload the counter is to use the early wakeup interrupt (EWI). This interrupt is enabled by setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value 40h, this interrupt is generated and the corresponding interrupt service routine (ISR) can be used to reload the counter to prevent WWDG reset. This interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). Doc ID 13902 Rev 9 405/995 Window watchdog (WWDG) RM0008 18.4 How to program the watchdog timeout Figure 160 shows the linear relationship between the 6-bit value to be loaded in the watchdog counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in Figure 160. Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 160. Window watchdog timing diagram T[6:0] CNT downcounter W[6:0] 3Fh time Refresh not allowed Refresh window T6 bit Reset The formula to calculate the timeout value is given by: TWWDG = TPCLK1  4096  2WDGTB  T5:0 + 1 ; ms  where: TWWDG: WWDG timeout TPCLK1: APB1 clock period measured in ms Min-max timeout value @36 MHz (PCLK1) WDGTB Min timeout value 0 113 µs 1 227 µs 2 455 µs 3 910 µs Max timeout value 7.28 ms 14.56 ms 29.12 ms 58.25 ms 18.5 Debug mode When the microcontroller enters debug mode (Cortex-M3 core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to Section 29.16.2: Debug support for timers, watchdog, bxCAN and I2C. 406/995 Doc ID 13902 Rev 9 RM0008 Window watchdog (WWDG) 18.6 18.6.1 WWDG registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x7F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WDGA T6 T5 T4 T3 T2 T1 T0 rs rw rw rw rw rw rw rw Bits 31:8 Reserved Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB) PCLK1 cycles. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). 18.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x7F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWI WDG WDG TB1 TB0 W6 W5 W4 W3 W2 W1 W0 rs rw rw rw rw rw rw rw rw rw Bit 31:10 Reserved Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 40h. This interrupt is only cleared by hardware after a reset. Doc ID 13902 Rev 9 407/995 Window watchdog (WWDG) RM0008 Bits 8:7 WDGTB[1:0]: Timer base The time base of the prescaler can be modified as follows: 00: CK Counter Clock (PCLK1 div 4096) div 1 01: CK Counter Clock (PCLK1 div 4096) div 2 10: CK Counter Clock (PCLK1 div 4096) div 4 11: CK Counter Clock (PCLK1 div 4096) div 8 Bits 6:0 W[6:0]: 7-bit window value These bits contain the window value to be compared to the downcounter. 18.6.3 Status register (WWDG_SR) Address offset: 0x08 Reset value: 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF rc_w0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 WDGA 7 6 5 4 3 2 1 0 Bit 31:1Reserved Bit 0 EWIF: Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 40h. It must be cleared by software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not enabled. 18.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 83. WWDG register map and reset values Offset Register 0x00 WWDG_CR Reset value 0x04 0x08 WWDG_CFR Reset value WWDG_SR Reset value Reserved Reserved Reserved EWI WDGTB1 WDGTB0 T[6:0] 01111111 W[6:0] 0001111111 0 Refer to Table 1 on page 41 for the register boundary addresses. EWIF 408/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) 19 Flexible static memory controller (FSMC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to high-density devices only. 19.1 FSMC main features The FSMC block is able to interface with synchronous and asynchronous memories and 16bit PC memory cards. Its main purpose is to: ● Translate the AHB transactions into the appropriate external device protocol ● Meet the access timing requirements of the external devices All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique chip select. The FSMC performs only one access at a time to an external device. The FSMC has the following main features: ● Interfaces with static memory-mapped devices including: – Static random access memory (SRAM) – Read-only memory (ROM) – NOR Flash memory – PSRAM (4 memory banks) ● Two banks of NAND Flash with ECC hardware that checks up to 8 Kbytes of data ● 16-bit PC Card compatible devices ● Supports burst mode access to synchronous devices (NOR Flash and PSRAM) ● 8- or 16-bit wide databus ● Independent chip select control for each memory bank ● Independent configuration for each memory bank ● Programmable timings to support a wide range of devices, in particular: – Programmable wait states (up to 15) – Programmable bus turnaround cycles (up to 15) – Programmable output enable and write enable delays (up to 15) – Independent read and write timings and protocol, so as to support the widest variety of memories and timings ● Write enable and byte lane select outputs for use with PSRAM and SRAM devices ● Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to external 16-bit or 8-bit devices Doc ID 13902 Rev 9 409/995 Flexible static memory controller (FSMC) RM0008 ● Write FIFO, 16 words long, each word 32 bits wide. This makes it possible to write to slow memories and free the AHB quickly for other transactions. If a new transaction is started to the FSMC, first the FIFO is drained The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, it is possible to change the settings at any time. 19.2 Block diagram The FSMC consists of four main blocks: ● The AHB interface (including the FSMC configuration registers) ● The NOR Flash/PSRAM controller ● The NAND Flash/PC Card controller ● The external device interface The block diagram is shown in Figure 19.3. 19.3 19.3.1 AHB interface The AHB slave interface enables internal CPUs and other bus master peripherals to access the external static memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The AHB clock (HCLK) is the reference clock for the FSMC. Supported memories and transactions General transaction rules The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers. Therefore, some simple transaction rules must be followed: ● AHB transaction size and memory data size are equal There is no issue in this case. ● AHB transaction size is greater than the memory size In this case, the FSMC splits the AHB transaction into smaller consecutive memory accesses in order to meet the external data width. ● AHB transaction size is smaller than the memory size Asynchronous transfers may or not be consistent depending on the type of external device. – Asynchronous accesses to devices that have the byte select feature (SRAM, ROM, PSRAM). In this case, the FSMC allows read/write transactions and accesses the right data through its byte lanes BL[1:0] – Asynchronous accesses to devices that do not have the byte select feature (NOR and NAND Flash 16-bit). 410/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) This situation occurs when a byte access is requested to a 16-bit wide Flash memory. Clearly, the device cannot be accessed in byte mode (only 16-bit words can be read from/written to the Flash memory) therefore: a) Write transactions are not allowed b) Read transactions are allowed (the controller reads the entire 16-bit memory word and uses the needed byte only). Configuration registers The FSMC can be configured using a register set. See Section 19.5.6, for a detailed description of the NOR Flash/PSRAM controller registers. See Section 19.6.7, for a detailed description of the NAND Flash/PC Card registers. 19.4 External device address mapping From the FSMC point of view, the external memory is divided into 4 fixed-size banks of 256 Mbytes each (Refer to Figure 161): ● Bank 1 used to address up to 4 NOR Flash or PSRAM memory devices. This bank is split into 4 NOR/PSRAM regions with 4 dedicated Chip Select. ● Banks 2 and 3 used to address NAND Flash devices (1 device per bank) ● Bank 4 used to address a PC Card device For each bank the type of memory to be used is user-defined in the Configuration register. Figure 161. FSMC memory banks A ddres s Banks Supported memory type 6000 0000h 6FF F FFF Fh 7000 0000h 7FF F FFF Fh 8000 0000h 8FF F FFF Fh 9000 0000h 9FF F FFF Fh Bank 1 4 × 64 MB Bank 2 4 × 64 MB Bank 3 4 × 64 MB Bank 4 4 × 64 MB NOR / PSRAM NAND Flash PC Card ai14719 Doc ID 13902 Rev 9 411/995 Flexible static memory controller (FSMC) RM0008 19.4.1 19.4.2 NOR/PSRAM address mapping HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 84. Table 84. NOR/PSRAM bank selection HADDR[27:26](1) Selected bank 00 Bank 1 NOR/PSRAM 1 01 Bank 1 NOR/PSRAM 2 10 Bank 1 NOR/PSRAM 3 11 Bank 1 NOR/PSRAM 4 1. HADDR are internal AHB address lines that are translated to external memory. HADDR[25:0] contain the external memory address. Since HADDR is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the following table. Table 85. External memory address Memory width(1) Data address issued to the memory Maximum memory capacity (bits) 8-bit 16-bit HADDR[25:0] HADDR[25:1] >> 1 64 Mbytes x 8 = 512 Mbit 64 Mbytes/2 x 16 = 512 Mbit 1. In case of a 16-bit external memory width, the FSMC will internally use HADDR[25:1] to generate the address for external memory FSMC_A[24:0]. Whatever the external memory width (16-bit or 8-bit), FSMC_A[0] should be connected to external memory address A[0]. Wrap support for NOR Flash/PSRAM Each NOR Flash/PSRAM memory bank can be configured to support wrap accesses. On the memory side, two cases must be considered depending on the access mode: asynchronous or synchronous. ● Asynchronous mode: in this case, wrap accesses are fully supported as long as the address is supplied for every single access. ● Synchronous mode: in this case, the FSMC issues the address only once, and then the burst transfer is sequenced by the FSMC clock CLK. Some NOR memories support linear burst with wrap-around accesses, in which a fixed number of words is read from consecutive addresses modulo N (N is typically 8 or 16 and can be programmed through the NOR Flash configuration register). In this case, it is possible to set the memory wrap mode identical to the AHB master wrap mode. Otherwise, in the case when the memory wrap mode and the AHB master wrap mode cannot be set identically, wrapping should be disabled (through the appropriate bit in the FSMC configuration register) and the wrap transaction split into two consecutive linear transactions. NAND/PC Card address mapping In this case, three banks are available, each of them divided into memory spaces as indicated in Table 86. 412/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Table 86. Memory mapping and timing registers Start address End address FSMC Bank Memory space Timing register 0x9C00 0000 0x9FFF FFFF I/O 0x9800 0000 0x9BFF FFFF Bank 4 - PC card Attribute 0x9000 0000 0x93FF FFFF Common 0x8800 0000 0x8000 0000 0x8BFF FFFF Attribute Bank 3 - NAND Flash 0x83FF FFFF Common 0x7800 0000 0x7000 0000 0x7BFF FFFF Attribute Bank 2- NAND Flash 0x73FF FFFF Common FSMC_PIO4 (0xB0) FSMC_PATT4 (0xAC) FSMC_PMEM4 (0xA8) FSMC_PATT3 (0x8C) FSMC_PMEM3 (0x88) FSMC_PATT2 (0x6C) FSMC_PMEM2 (0x68) For NAND Flash memory, the common and attribute memory spaces are subdivided into three sections (see in Table 87 below) located in the lower 256 Kbytes: ● Data section (first 64 Kbytes in the common/attribute memory space) ● Command section (second 64 Kbytes in the common / attribute memory space) ● Address section (next 128 Kbytes in the common / attribute memory space) Table 87. NAND bank selections Section name HADDR[17:16] Address section 1X Command section 01 Data section 00 Address range 0x020000-0x03FFFF 0x010000-0x01FFFF 0x000000-0x0FFFF The application software uses the 3 sections to access the NAND Flash memory: ● To send a command to NAND Flash memory: the software must write the command value to any memory location in the command section. ● To specify the NAND Flash address that must be read or written: the software must write the address value to any memory location in the address section. Since an address can be 4 or 5 bytes long (depending on the actual memory size), several consecutive writes to the address section are needed to specify the full address. ● To read or write data: the software reads or writes the data value from or to any memory location in the data section. Since the NAND Flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations. Doc ID 13902 Rev 9 413/995 Flexible static memory controller (FSMC) RM0008 19.5 NOR Flash/PSRAM controller The FSMC generates the appropriate signal timings to drive the following types of memories: ● Asynchronous SRAM and ROM – 8-bit – 16-bit – 32-bit ● PSRAM (Cellular RAM) – Asynchronous mode – Burst mode ● NOR Flash – Asynchronous mode or burst mode – Multiplexed or nonmultiplexed The FSMC outputs a unique chip select signal NE[4:1] per bank. All the other signals (addresses, data and control) are shared. For synchronous accesses, the FSMC issues the clock (CLK) to the selected external device. This clock is a submultiple of the HCLK clock. The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured by means of dedicated registers (see Section 19.6.7). The programmable memory parameters include access timings (see Table 88) and support for wrap and wait management (for PSRAM and NOR Flash accessed in burst mode). Table 88. Programmable NOR/PSRAM access parameters Parameter Function Access mode Unit Min. Max. Address setup Duration of the address setup phase Asynchronous AHB clock cycle (HCLK) 1 16 Address hold Duration of the address hold phase Asynchronous, muxed I/Os AHB clock cycle (HCLK) 2 16 Data setup Duration of the data setup phase Asynchronous AHB clock cycle (HCLK) 2 256 Bust turn Duration of the bus turnaround phase Asynchronous and AHB clock cycle synchronous read (HCLK) 1 16 Clock divide ratio Number of AHB clock cycles (HCLK) to build one memory Synchronous clock cycle (CLK) AHB clock cycle (HCLK) 1 16 Data latency Number of clock cycles to issue to the memory before the first data of the burst Synchronous Memory clock cycle (CLK) 2 17 19.5.1 External memory interface signals Table 89, Table 90 and Table 91 list the signals that are typically used to interface NOR Flash and PSRAM. 414/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Note: Prefix “N”. specifies the associated signal as active low. NOR Flash, nonmultiplexed I/Os Table 89. Nonmuxed I/O NOR Flash FSMC signal name I/O CLK O A[25:0] O D[15:0] I/O NE[x] O NOE O NWE O NWAIT I Function Clock (for synchronous burst) Address bus Bidirectional data bus Chip select, x = 1..4 Output enable Write enable NOR Flash wait input signal to the FSMC NOR Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines). NOR Flash, multiplexed I/Os Table 90. Muxed I/O NOR Flash FSMC signal name I/O Function CLK O Clock (for synchronous burst) A[25:16] O Address bus AD[15:0] I/O 16-bit multiplexed, bidirectional address/data bus NE[x] NOE O Chip select, x = 1..4 O Output enable NWE O Write enable NL(=NADV) O Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) NWAIT I NOR Flash wait input signal to the FSMC NOR-Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines). PSRAM Table 91. Non muxed I/Os PSRAM FSMC signal name I/O Function CLK O Clock (for synchronous burst) A[25:0] O Address bus D[15:0] I/O Data bidirectional bus Doc ID 13902 Rev 9 415/995 Flexible static memory controller (FSMC) RM0008 Table 91. Non muxed I/Os PSRAM (continued) FSMC signal name I/O Function NE[x] O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM)) NOE O Output enable NWE NL(= NADV) O Write enable O Address valid PSRAM input (memory signal name: NADV) NWAIT I PSRAM wait input signal to the FSMC NBL[1] O Upper byte enable (memory signal name: NUB) NBL[0] O Lowed byte enable (memory signal name: NLB) 19.5.2 PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines). Supported memories and transactions Table 92 below displays the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the FSMC appear in gray. Table 92. NOR Flash/PSRAM supported memories and transactions Device Mode R/W AHB data size Memory data size Allowed/ not allowed Comments Asynchronous R 8 16 Y Asynchronous W 8 16 N Asynchronous R 16 16 Y Asynchronous W 16 NOR Flash Asynchronous R 32 (muxed I/Os and nonmuxed Asynchronous W 32 I/Os) Asynchronous page R - 16 Y 16 Y 16 Y 16 N Split into 2 FSMC accesses Split into 2 FSMC accesses Mode is not supported Synchronous R 8 16 N Synchronous R 16 16 Y Synchronous R 32 16 Y 416/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Table 92. NOR Flash/PSRAM supported memories and transactions (continued) Device Mode R/W AHB data size Memory data size Allowed/ not allowed Comments Asynchronous R 8 16 Y Asynchronous W 8 16 Y Use of byte lanes NBL[1:0] Asynchronous R 16 Asynchronous W 16 16 Y 16 Y Asynchronous R 32 PSRAM (muxed I/Os Asynchronous W 32 and nonmuxed I/Os) Asynchronous page R - 16 Y 16 Y 16 N Split into 2 FSMC accesses Split into 2 FSMC accesses Mode is not supported Synchronous R 8 16 N Synchronous R 16 Synchronous R 32 16 Y 16 Y Synchronous W 8 16 Y Use of byte lanes NBL[1:0] Synchronous W 16/32 16 Y SRAM and ROM Asynchronous R Asynchronous W 8 / 16 / 32 8 / 16 / 32 8 / 16 Y 8 / 16 Y Use of byte lanes NBL[1:0] Use of byte lanes NBL[1:0] 19.5.3 19.5.4 General timing rules Signals synchronization ● All controller output signals change on the rising edge of the internal clock (HCLK) ● In synchronous write mode (PSRAM devices), the output data changes on the falling edge of the memory clock (CLK) NOR Flash/PSRAM controller timing diagrams Asynchronous static memories (NOR Flash, SRAM) ● Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory ● The FSMC always samples the data before de-asserting the chip select signal NE. This guarantees that the memory data-hold timing constraint is met (chip enable high to data transition, usually 0 ns min.) ● When extended mode is set, it is possible to mix modes A, B, C and D in read and write (it is for instance possible to read in mode A and write in mode B). Doc ID 13902 Rev 9 417/995 Flexible static memory controller (FSMC) Mode 1 - SRAM/CRAM Figure 162. Mode1 read accesses Memory transaction A[25:0] NBL[1:0] RM0008 NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK HCLK cycles cycles Data sampled Data strobe ai14720c Mode1 write accessesThe one HCLK cycle at the end of the write transaction helps Memory transaction A[25:0] NBL[1:0] NEx NOE NWE 1HCLK D[15:0] data driven by FSMC (ADDSET +1) HCLK cycles (DATAST + 1) HCLK cycles ai14721c guarantee the address and data hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the DATAST value must be greater than zero (DATAST > 0). 418/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Table 93. Bit number 31-15 14-10 9 8 7 6 5-4 3-2 1 0 FSMC_BCRx bit fields Bit name Value to set WAITPOL BURSTEN FACCEN MWID MTYP MUXEN MBKEN 0x0000 0x0 Meaningful only if bit 15 is 1 0x0 As needed As needed, exclude 10 (NOR Flash) 0x0 0x1 Table 94. FSMC_TCRx bit fields Bit number Bit name Value to set 31-16 0x0000 15-8 DATAST Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST+3 HCLK cycles for read accesses). This value cannot be 0 (minimum is 1). 7-4 0x0 3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) . Doc ID 13902 Rev 9 419/995 Flexible static memory controller (FSMC) Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 163. ModeA read accesses Memory transaction A[25:0] NBL[1:0] RM0008 NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK HCLK cycles cycles Data sampled Data strobe ai14722c Figure 164. ModeA write accesses Memory transaction A[25:0] NBL[1:0] NEx NOE NWE 1HCLK D[15:0] data driven by FSMC (ADDSET +1) HCLK cycles (DATAST + 1) HCLK cycles ai14721c The differences compared with mode1 are the toggling of NOE and the independent read and write timings. 420/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Table 95. FSMC_BCRx bit fields Bit number Bit name Value to set 31-16 0x0000 15 0x0 14 EXTMOD 0x1 13-10 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 - 6 FACCEN - 5-4 MWID As needed 3-2 MTYP As needed, exclude 10 (NOR Flash) 1 MUXEN 0x0 0 MBKEN 0x1 Table 96. FSMC_TCRx bit fields Bit number Bit name Value to set 31-30 0x0 29-28 ACCMOD 0x0 27-16 0x000 15-8 DATAST Duration of the second access phase (DATAST+3 HCLK cycles) in read. This value cannot be 0 (minimum is 1) 7-4 0x0 3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in read. Table 97. FSMC_BWTRx bit fields Bit number Bit name Value to set 31-30 29-28 27-16 15-8 7-4 3-0 ACCMOD DATAST ADDSET 0x0 0x0 0x000 Duration of the second access phase (DATAST+1 HCLK cycles) in write. This value cannot be 0 (minimum is 1). 0x0 Duration of the first access phase (ADDSET+1 HCLK cycles) in write Doc ID 13902 Rev 9 421/995 Flexible static memory controller (FSMC) Mode 2/B - NOR Flash Figure 165. Mode2/B read accesses Memory transaction A[25:0] NADV RM0008 NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK HCLK cycles cycles Data sampled Data strobe ai14724c Figure 166. Mode2 write accesses Memory transaction A[25:0] NADV NEx NOE NWE 1HCLK D[15:0] (ADDSET +1) HCLK cycles data driven by FSMC (DATAST + 1) HCLK cycles ai14723b 422/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Figure 167. ModeB write accesses Memory transaction A[25:0] NADV NEx NOE NWE 1HCLK D[15:0] (ADDSET +1) HCLK cycles data driven by FSMC (DATAST + 1) HCLK cycles ai15110b The differences with mode1 are the toggling of NADV and the independent read and write timings when extended mode is set (Mode B). Table 98. FSMC_BCRx bit fields Bit number Bit name Value to set 31-15 14 13-10 9 8 7 6 5-4 3-2 1 0 EXTMOD WAITPOL BURSTEN FACCEN MWID MTYP MUXEN MBKEN 0x0000 0x1 for mode B, 0x0 for mode 2 0x0 Meaningful only if bit 15 is 1 0x0 0x1 As needed 10 (NOR Flash) 0x0 0x1 Doc ID 13902 Rev 9 423/995 Flexible static memory controller (FSMC) RM0008 Table 99. FSMC_TCRx bit fields Bit number Bit name Value to set 31-30 29-28 27-16 15-8 7-4 3-0 ACCMOD DATAST ADDSET 0x0 0x1 if extended mode is set 0x000 Duration of the access second phase (DATAST+3 HCLK cycles) in read. This value can not be 0 (minimum is 1) 0x0 Duration of the access first phase (ADDSET+1 HCLK cycles) in read. Table 100. FSMC_BWTRx bit fields Bit number Bit name Value to set 31-30 0x0 29-28 ACCMOD 0x1 if extended mode is set 27-16 0x000 15-8 DATAST Duration of the access second phase (DATAST+1 HCLK cycles) in write. This value can not be 0 (minimum is 1). 7-4 0x0 3-0 ADDSET Duration of the access first phase (ADDSET+1 HCLK cycles) in write. Note: The FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its content is don’t care. 424/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Mode C - NOR Flash - OE toggling Figure 168. ModeC read accesses Memory transaction A[25:0] NADV NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK HCLK cycles cycles Data sampled Data strobe ai14725c Figure 169. ModeC write accesses Memory transaction A[25:0] NADV NEx NOE NWE 1HCLK D[15:0] data driven by FSMC (ADDSET +1) HCLK cycles (DATAST + 1) HCLK cycles ai14723b The differences compared with mode1 are the toggling of NOE and NADV and the independent read and write timings. Doc ID 13902 Rev 9 425/995 Flexible static memory controller (FSMC) RM0008 Table 101. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-15 14 13-10 9 8 7 6 5-4 3-2 1 0 EXTMOD WAITPOL BURSTEN FACCEN MWID MTYP MUXEN MBKEN 0x0000 0x1 0x0 Meaningful only if bit 15 is 1 0x0 1 As needed 0x02 (NOR Flash) 0x0 0x1 Table 102. FSMC_TCRx bit fields Bit No. Bit name Value to set 31-30 0x0 29-28 27-16 ACCMOD 0x2 0x000 15-8 7-4 DATAST Duration of the second access phase (DATAST+3 HCLK cycles) in read. This value cannot be 0 (minimum is 1) 0x0 3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in read. Table 103. FSMC_BWTRx bit fields Bit No. Bit name Value to set 31-30 0x0 29-28 27-16 ACCMOD 0x2 0x000 15-8 7-4 DATAST Duration of the second access phase (DATAST+1 HCLK cycles) in write. This value cannot be 0 (minimum is 1) 0x0 3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in write. 426/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Mode D - asynchronous access with extended address Figure 170. ModeD read accesses Memory transaction A[25:0] NADV NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK (ADDHLD + 1) HCLK cycles cycles HCLK cycles Data sampled Data strobe ai14726c ModeD write accessesThe differences with mode1 are the toggling of NADV, NOE that Memory transaction A[25:0] NADV NEx NOE NWE 1HCLK D[15:0] data driven by FSMC (ADDSET +1) HCLK cycles (ADDHLD + 1) HCLK cycles (DATAST + 1) HCLK cycles ai14727c goes on toggling after NADV changes and the independent read and write timings. Doc ID 13902 Rev 9 427/995 Flexible static memory controller (FSMC) RM0008 Table 104. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-15 14 13-10 9 8 7 6 5-4 3-2 1 0 EXTMOD WAITPOL BURSTEN FACCEN MWID MTYP MUXEN MBKEN 0x0000 0x1 0x0 Meaningful only if bit 15 is 1 0x0 Set according to memory support As needed As needed 0x0 0x1 Table 105. FSMC_TCRx bit fields Bit No. Bit name Value to set 31-30 0x0 29-28 27-16 ACCMOD 0x2 0x000 15-8 7-4 DATAST ADDHLD Duration of the second access phase (DATAST+3 HCLK cycles) in read. This value cannot be 0 (minimum is 1) Duration of the middle phase of the read access (ADDHLD+1 HCLK cycles) 3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in read. Table 106. FSMC_BWTRx bit fields Bit No. Bit name Value to set 31-30 0x0 29-28 ACCMOD 0x2 27-16 0x000 15-8 DATAST Duration of the second access phase (DATAST+1 HCLK cycles) in write. This value cannot be 0 (minimum is 1) 7-4 ADDHLD Duration of the middle phase of the write access (ADDHLD+1 HCLK cycles) 3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in write. 428/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Mode muxed - asynchronous access muxed NOR Flash Figure 171. Muxed read accesses Memory transaction A[25:16] NADV NEx NOE NWE High AD[15:0] Lower address 1HCLK cycle data driven by memory (ADDSET +1) HCLK cycles (DATAST + 1) 2 HCLK (BUSTURN + 1)(1) HCLK cycles cycles HCLK cycles (ADDHLD + 1) HCLK cycles Data sampled Data strobe ai14728c 1. The bus turnaround delay (BUSTURN + 1) and the delay between side-by-side transactions overlap, so BUSTURN  5 has not impact. Figure 172. Muxed write accesses Memory transaction A[25:16] NADV NEx NOE NWE 1HCLK AD[15:0] Lower address data driven by FSMC (ADDSET +1) ADDHLD HCLK cycles HCLK cycles (DATAST + 2) HCLK cycles ai14729c The difference with mode D is the drive of the lower address byte(s) on the databus. Doc ID 13902 Rev 9 429/995 Flexible static memory controller (FSMC) RM0008 Table 107. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-15 14 13-10 9 8 7 6 5-4 3-2 1 0 EXTMOD WAITPOL BURSTEN FACCEN MWID MTYP MUXEN MBKEN 0x0000 0x0 0x0 Meaningful only if bit 15 is 1 0x0 0x1 As needed 0x2 (NOR) 0x1 0x1 Table 108. FSMC_TCRx bit fields Bit No. Bit name Value to set 31-20 0x0000 19-16 BUSTURN Duration of the last phase of the access (BUSTURN+1 HCLK) 15-8 7-4 3-0 DATAST ADDHLD ADDSET Duration of the second access phase (DATAST+3 HCLK cycles for read accesses and DATAST+1 HCLK cycles for write accesses). This value cannot be 0 (minimum is 1) Duration of the middle phase of the access (ADDHLD+1 HCLK cycles).This value cannot be 0 (minimum is 1). Duration of the first access phase (ADDSET+1 HCLK cycles). 19.5.5 Synchronous burst transactions The memory clock, CLK, is a submultiple of HCLK according to the value of parameter CLKDIV. NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FSMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse. 430/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Caution: Data latency versus NOR Flash latency The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR Flash configuration register. The FSMC does not include the clock cycle when NADV is low in the data latency count. Some NOR Flash memories include the NADV Low cycle in the data latency count, so the exact relation between the NOR Flash latency and the FMSC DATLAT parameter can be either of: ● NOR Flash latency = DATLAT + 2 ● NOR Flash latency = DATLAT + 3 Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FSMC samples the data and waits long enough to evaluate if the data are valid. Thus the FSMC detects when the memory exits latency and real data are taken. Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FSMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access. Single-burst transfer When the selected bank is configured in synchronous burst mode, if an AHB single-burst transaction is requested, the FSMC performs a burst transaction of length 1 (if the AHB transfer is 16-bit), or length 2 (if the AHB transfer is 32-bit) and de-assert the chip select signal when the last data is strobed. Clearly, such a transfer is not the most efficient in terms of cycles (compared to an asynchronous read). Nevertheless, a random asynchronous access would first require to reprogram the memory access mode, which would altogether last longer. Wait management For synchronous burst NOR Flash, NWAIT is evaluated after the programmed latency period, (DATALAT+1) CLK clock cycles. If NWAIT is sensed active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is sensed inactive (high level when WAITPOL = 0, low level when WAITPOL = 1). When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0). During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid, and does not consider the data valid. There are two timing configurations for the NOR Flash NWAIT signal in burst mode: ● Flash memory asserts the NWAIT signal one data cycle before the wait state (default after reset) ● Flash memory asserts the NWAIT signal during the wait state These two NOR Flash wait state configurations are supported by the FSMC, individually for each chip select, thanks to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3). Doc ID 13902 Rev 9 431/995 Flexible static memory controller (FSMC) Figure 173. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK RM0008 CLK A[25:16] addr[25:16] NEx NOE NWE High NADV NWAIT (WAITCFG = 0) NWAIT (WAITCFG = 1) A/D[15:0] DATALAT CLK cycles Addr[15:0] data inserted wait state data data data 1 clock 1 clock cycle cycle Data strobes Data strobes ai14730 1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. Table 109. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-20 19 18-15 14 13 12 CBURSTRW EXTMOD WAITEN WREN 0x0000 No effect on synchronous read 0x0 0x0 When high, the first data after latency period is taken as always valid, regardless of the wait from memory value no effect on synchronous read 432/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Table 109. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set 11 WAITCFG to be set according to memory 10 WRAPMOD to be set according to memory 9 WAITPOL to be set according to memory 8 BURSTEN 0x1 7 FWPRLVL Set to protect memory from accidental write access 6 FACCEN Set according to memory support 5-4 MWID As needed 3-2 MTYP 1 MUXEN 0x1 or 0x2 As needed 0 MBKEN 0x1 Table 110. FSMC_TCRx bit fields Bit No. Bit name Value to set 27-24 DATLAT Data latency 23-20 CLKDIV 0x0 to get CLK = HCLK (not supported) 0x1 to get CLK = 2 × HCLK 19-16 15-8 7-4 3-0 BUSTURN DATAST ADDHLD ADDSET no effect no effect no effect no effect Doc ID 13902 Rev 9 433/995 Flexible static memory controller (FSMC) Figure 174. Synchronous multiplexed write mode - PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK CLK A[25:16] addr[25:16] RM0008 NEx NOE Hi-Z NWE NADV NWAIT (WAITCFG = 0) DATALAT CLK cycles inserted wait state A/D[15:0] Addr[15:0] data data data data 1 CLK 1 CLK cycle cycle 1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. ai14731c 434/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Table 111. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-20 19 18-15 14 13 12 11 10 9 8 7 6 5-4 3-2 1 0 CBURSTRW EXTMOD WAITEN WREN WAITCFG WRAPMOD WAITPOL BURSTEN FWPRLVL FACCEN MWID MTYP MUXEN MBKEN 0x0000 0x1 0x0 0x0 When high, the first data after latency period is taken as always valid, regardless of the wait from memory value no effect on synchronous read 0x0 to be set according to memory to be set according to memory no effect on synchronous write Set to protect memory from accidental writes Set according to memory support As needed 0x1 As needed 0x1 Table 112. FSMC_TCRx bit fields Bit No. Bit name Value to set 31-30 - 0x0 27-24 DATLAT Data latency 23-20 19-16 CLKDIV BUSTURN 0 to get CLK = HCLK (not supported) 1 to get CLK = 2 × HCLK No effect 15-8 DATAST No effect 7-4 ADDHLD No effect 3-0 ADDSET No effect Doc ID 13902 Rev 9 435/995 Flexible static memory controller (FSMC) RM0008 19.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DX This register contains the control information of each memory bank, used for SRAMs, ROMs and asynchronous or burst NOR Flash memories. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBURSTRW EXTMOD WAITEN WREN WAITCFG WRAPMOD WAITPOL BURSTEN Reserved FACCEN MWID MTYP MUXEN MBKEN Reserved Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 19 CBURSTRW: Write burst enable. For Cellular RAM, the bit enables synchronous burst protocol during write operations. For Flash memory access in burst mode, this bit enables/disables the wait state insertion via the NWAIT signal. The enable bit for the synchronous burst protocol during read access is the BURSTEN bit in the FSMC_BCRx register. 0: Write operations are always performed in asynchronous mode 1: Write operations are performed in synchronous mode. Bit 15 Reserved. Bit 14 EXTMOD: Extended mode enable. This bit enables the FSMC to program inside the FSMC_BWTR register, so it allows different timings for read and write. 0: values inside FSMC_BWTR register are not taken into account (default after reset) 1: values inside FSMC_BWTR register are taken into account Bit 13 WAITEN: Wait enable bit. For Flash memory access in burst mode, this bit enables/disables wait-state insertion via the NWAIT signal: 0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period) 1: NWAIT signal is enabled (its level is taken into account after the programmed Flash latency period to insert wait states if asserted) (default after reset) Bit 12 WREN: Write enable bit. This bit indicates whether write operations are enabled/disabled in the bank by the FSMC: 0: Write operations are disabled in the bank by the FSMC, an AHB error is reported, 1: Write operations are enabled for the bank by the FSMC (default after reset). Bit 11 WAITCFG: Wait timing configuration. For memory access in burst mode, the NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 0: NWAIT signal is active one data cycle before wait state (default after reset), 1: NWAIT signal is active during wait state (not for Cellular RAM). 436/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Bit 10 WRAPMOD: Wrapped burst mode support. Defines whether the controller will or not split an AHB burst wrap access into two linear accesses. Valid only when accessing memories in burst mode 0: Direct wrapped burst is not enabled (default after reset), 1: Direct wrapped burst is enabled. Bit 9 WAITPOL: Wait signal polarity bit. Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode: 0: NWAIT active low (default after reset), 1: NWAIT active high. Bit 8 BURSTEN: Burst enable bit. Enables the burst access mode for the memory. Valid only with synchronous burst memories: 0: Burst access mode disabled (default after reset) 1: Burst access mode enable Bit 7 Reserved. Bit 6 FACCEN: Flash access enable Enables NOR Flash memory access operations. 0: Corresponding NOR Flash memory access is disabled 1: Corresponding NOR Flash memory access is enabled (default after reset) Bits 5:4 MWID: Memory databus width. Defines the external memory device width, valid for all type of memories. 00: 8 bits, 01: 16 bits (default after reset), 10: reserved, do not use, 11: reserved, do not use. Bits 3:2 MTYP: Memory type. Defines the type of external memory attached to the corresponding memory bank: 00: SRAM, ROM (default after reset for Bank 2...4) 01: PSRAM (Cellular RAM: CRAM) 10: NOR Flash(default after reset for Bank 1) 11: reserved Bit 1 MUXEN: Address/data multiplexing enable bit. When this bit is set, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories: 0: Address/Data nonmultiplexed 1: Address/Data multiplexed on databus (default after reset) Bit 0 MBKEN: Memory bank enable bit. Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. 0: Corresponding memory bank is disabled 1: Corresponding memory bank is enabled Doc ID 13902 Rev 9 437/995 Flexible static memory controller (FSMC) RM0008 SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) Address offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, ROMs and NOR Flash memories. If the EXTMOD bit is set in the FSMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FSMC_BWTRx registers). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 29:28 ACCMOD: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D Bits 27:24 DATLAT (see note below bit descriptions): Data latency (for synchronous burst NOR Flash) For NOR Flash with synchronous burst mode enabled, defines the number of memory clock cycles (+2) to issue to the memory before getting the first data: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of CRAM, this field must be set to 0 0000: Data latency of 2 CLK clock cycles for first burst access 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) Bits 23:20 CLKDIV: Clock divide ratio (for CLK signal) Defines the period of CLK clock output signal, expressed in number of HCLK cycles: 0000: Reserved 0001: CLK period = 2 × HCLK periods 0010: CLK period = 3 × HCLK periods 1111: CLK period = 16 × HCLK periods (default value after reset) In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. Bits 19:16 BUSTURN: Bus turnaround phase duration These bits are written by software to introduce the bus turnaround delay after a read access (only from multiplexed NOR Flash memory) to avoid bus contention if the controller needs to drive addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the minimum if the memory system does not include multiplexed memories or if the slowest memory does not take more than 6 HCLK clock cycles to put the databus in Hi-Z state: 0000: BUSTURN phase duration = 1 × HCLK clock cycle ... 1111: BUSTURN phase duration = 16 × HCLK clock cycles (default value after reset) 438/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Bits 15:8 DATAST: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 162 to Figure 172), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 2 × HCLK clock cycles 0000 0010: DATAST phase duration = 3 × HCLK clock cycles ... 1111 1111: DATAST phase duration = 256 × HCLK clock cycles (default value after reset) For each memory type and access mode data-phase duration, please refer to the respective figure (Figure 162 to Figure 172). Example: Mode1, read access, DATAST=1: Data-phase duration= DATAST+3 = 4 HCLK clock cycles. Bits 7:4 ADDHLD: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 170 to Figure 172), used in mode D and multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration = 2 × HCLK clock cycle 0010: ADDHLD phase duration = 3 × HCLK clock cycle ... 1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset) For each access mode address-hold phase duration, please refer to the respective figure (Figure 170 to Figure 172). Example: ModeD, read access, ADDHLD=1: Address-hold phase duration = ADDHLD + 1 =2 HCLK clock cycles. Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. Bits 3:0 ADDSET: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 162 to Figure 172), used in SRAMs, ROMs and asynchronous NOR Flash: 0000: ADDSET phase duration = 1 × HCLK clock cycle ... 1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset) For each access mode address setup phase duration, please refer to the respective figure (refer to Figure 162 to Figure 172). Example: Mode2, read access, ADDSET=1: Address setup phase duration = ADDSET + 1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to prolong the latency as needed. With PSRAMs (CRAMs) the filed DATLAT must be set to 0, so that the FSMC exits its latency phase soon and starts sampling NWAIT from memory, then starts to read or write when the memory is ready. This method can be used also with the latest generation of synchronous Flash memories that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the specific Flash memory being used). Doc ID 13902 Rev 9 439/995 Flexible static memory controller (FSMC) RM0008 SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) Address offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, ROMs and NOR Flash memories. When the EXTMOD bit is set in the FSMC_BCRx register, then this register is active for write access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. ACCM OD DATLAT CLKDIV rw rw rw rw rw rw rw rw rw rw Reserved DATAST ADDHLD ADDSET rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 29:28 ACCMOD: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D Bits 27:24 DATLAT: Data latency (for synchronous burst NOR Flash). For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles (+2) to issue to the memory before getting the first data: 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access ... 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods Note: In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. Note: In case of CRAM, this field must be set to 0 Bits 23:20 CLKDIV: Clock divide ratio (for CLK signal). Defines the period of CLK clock output signal, expressed in number of HCLK cycles: 0000: Reserved 0001 CLK period = 2 × HCLK periods 0010 CLK period = 3 × HCLK periods 1111: CLK period = 16 × HCLK periods (default value after reset) In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. Bits 19:16 Reserved Bits 15:8 DATAST: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 162 to Figure 172), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 2 × HCLK clock cycles 0000 0010: DATAST phase duration = 3 × HCLK clock cycles ... 1111 1111: DATAST phase duration = 16 × HCLK clock cycles (default value after reset) 440/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Bits 7:4 ADDHLD: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 170 to Figure 172), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses: 0000: Reserved 0001: ADDHLD phase duration = 2 × HCLK clock cycle 0010: ADDHLD phase duration = 3 × HCLK clock cycle ... 1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset) Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. Bits 3:0 ADDSET: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 170 to Figure 172), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash: 0000: ADDSET phase duration = 1 × HCLK clock cycle ... 1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset) Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 19.6 NAND Flash/PC Card controller The FSMC generates the appropriate signal timings to drive the following types of device: ● NAND Flash – 8-bit – 16-bit ● 16-bit PC Card compatible devices The NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support NAND Flash devices. Bank 4 supports PC Card devices. Each bank is configured by means of dedicated registers (Section 19.6.7). The programmable memory parameters include access timings (shown in Table 113) and ECC configuration. Doc ID 13902 Rev 9 441/995 Flexible static memory controller (FSMC) RM0008 Table 113. Programmable NAND/PC Card access parameters Parameter Function Access mode Unit Min. Max. Memory setup time Number of clock cycles (HCLK) to set up the address before the command assertion Read/Write AHB clock cycle (HCLK) 1 256 Memory wait Minimum duration (HCLK clock cycles) of the command assertion Read/Write AHB clock cycle (HCLK) 2 256 Number of clock cycles (HCLK) Memory hold to hold the address (and the data in case of a write access) after Read/Write AHB clock cycle (HCLK) 1 255 the command de-assertion Memory databus high-Z Number of clock cycles (HCLK) during which the databus is kept in high-Z state after the start of a write access Write AHB clock cycle (HCLK) 0 255 19.6.1 Caution: Note: External memory interface signals The following tables list the signals that are typically used to interface NAND Flash and PC Card. When using a PC Card or a CompactFlash in I/O mode, the NIOS16 input pin must remain at ground level during the whole operation, otherwise the FSMC may not operate properly. This means that the NIOS16 input pin must not be connected to the card, but directly to ground (only 16-bit accesses are allowed). Prefix “N”. specifies the associated signal as active low. 8-bit NAND Flash t Table 114. 8-bit NAND Flash FSMC signal name I/O Function A[17] A[16] D[7:0] NCE[x] NOE(= NRE) NWE NWAIT/INT[3:2] O NAND Flash address latch enable (ALE) signal O NAND Flash command latch enable (CLE) signal I/O 8-bit multiplexed, bidirectional address/data bus O Chip select, x = 2, 3 O Output enable (memory signal name: read enable, NRE) O Write enable I NAND Flash ready/busy input signal to the FSMC There is no theoretical capacity limitation as the FSMC can manage as many address cycles as needed. 442/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) 16-bit NAND Flash Table 115. 16-bit NAND Flash FSMC signal name I/O Function A[17] A[16] D[15:0] NCE[x] NOE(= NRE) NWE NWAIT/INT[3:2] O NAND Flash address latch enable (ALE) signal O NAND Flash command latch enable (CLE) signal I/O 16-bit multiplexed, bidirectional address/data bus O Chip select, x = 2, 3 O Output enable (memory signal name: read enable, NRE) O Write enable I NAND Flash ready/busy input signal to the FSMC There is no theoretical capacity limitation as the FSMC can manage as many address cycles as needed. Table 116. 16-bit PC Card FSMC signal name I/O Function A[10:0] O Address bus NIOS16 I Data transfer width in I/O space (16-bit transfer only) NIORD O Output enable for I/O space NIOWR NREG O Write enable for I/O space O Register signal indicating if access is in Common or Attribute space D[15:0] I/O Bidirectional databus NCE4_1 O Chip select 1 NCE4_2 O Chip select 2 (indicates if access is 16-bit or 8-bit) NOE NWE O Output enable O Write enable NWAIT INTR I PC Card wait input signal to the FSMC (memory signal name IORDY) I PC Card interrupt to the FSMC (only for PC Cards that can generate an interrupt) CD I PC Card presence detection Doc ID 13902 Rev 9 443/995 Flexible static memory controller (FSMC) RM0008 19.6.2 NAND Flash / PC Card supported memories and transactions Table 117 below shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash / PC Card controller appear in gray. Table 117. Supported memories and transactions Device Mode R/W AHB data size Memory data size Allowed/ not allowed Comments Asynchronous R 8 8 Y Asynchronous W 8 8 Asynchronous R 16 8 NAND 8-bit Asynchronous W 16 8 Y Y Split into 2 FSMC accesses Y Split into 2 FSMC accesses Asynchronous R 32 8 Y Split into 4 FSMC accesses Asynchronous W 32 8 Y Split into 4 FSMC accesses Asynchronous R 8 16 Y Asynchronous W 8 16 N Asynchronous R 16 16 Y NAND 16-bit Asynchronous W 16 16 Y Asynchronous R 32 16 Y Split into 2 FSMC accesses Asynchronous W 32 16 Y Split into 2 FSMC accesses 19.6.3 Timing diagrams for NAND, ATA and PC Card Each PC Card/CompactFlash and NAND Flash memory bank is managed through a set of registers: ● Control register: FSMC_PCRx ● Interrupt status register: FSMC_SRx ● ECC register: FSMC_ECCRx ● Timing register for Common memory space: FSMC_PMEMx ● Timing register for Attribute memory space: FSMC_PATTx ● Timing register for I/O space: FSMC_PIOx Each timing configuration register contains three parameters used to define number of HCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access, plus one parameter that defines the timing for starting driving the databus in the case of a write. Figure 175 shows the timing parameter definitions for common memory accesses, knowing that Attribute and I/O (only for PC Card) memory space access timings are similar. 444/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Figure 175. NAND/PC Card controller timing for common memory access HCLK A[25:0] NCEx(2) NREG, High NIOW, NIOR NWE, NOE(1) write_data MEMxSET + 1 MEMxHIZ + 1 MEMxWAIT + 1 MEMxHOLD + 1 read_data Valid ai14732c 1. NOE remains high (inactive) during write access. NWE remains high (inactive) during read access. 2. NCEx goes low as soon as NAND access is requested and remains low until a different memory bank is accessed. 19.6.4 NAND Flash operations The command latch enable (CLE) and address latch enable (ALE) signals of the NAND Flash device are driven by some address signals of the FSMC controller. This means that to send a command or an address to the NAND Flash memory, the CPU has to perform a write to a certain address in its memory space. A typical page read operation from the NAND Flash device is as follows: 1. Program and enable the corresponding memory bank by configuring the FSMC_PCRx and FSMC_PMEMx (and for some devices, FSMC_PATTx, see Section 19.6.5: NAND Flash pre-wait functionality on page 446) registers according to the characteristics of the NAND Flash (PWID bits for the databus width of the NAND Flash, PTYP = 1, PWAITEN = 1, PBKEN = 1, see section Common memory space timing register 2..4 (FSMC_PMEM2..4) on page 450 for timing configuration). 2. The CPU performs a byte write in the common memory space, with data byte equal to one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The CLE input of the NAND Flash is active during the write strobe (low pulse on NWE), thus the written byte is interpreted as a command by the NAND Flash. Once the command is latched by the NAND Flash device, it does not need to be written for the following page read operations. 3. The CPU can send the start address (STARTAD) for a read operation by writing four bytes (or three for smaller capacity devices), STARTAD[7:0], then STARTAD[16:9], STARTAD[24:17] and finally STARTAD[25] for 64 Mb x 8 bit NAND Flash) in the common memory or attribute space. The ALE input of the NAND Flash device is active during the write strobe (low pulse on NWE), thus the written bytes are interpreted as Doc ID 13902 Rev 9 445/995 Flexible static memory controller (FSMC) RM0008 19.6.5 the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the FSMC, which can be used to implement the prewait functionality needed by some NAND Flash memories (see details in Section 19.6.5: NAND Flash pre-wait functionality on page 446). 4. The controller waits for the NAND Flash to be ready (R/NB signal high) to become active, before starting a new access (to same or another memory bank). While waiting, the controller maintains the NCE signal active (low). 5. The CPU can then perform byte read operations in the common memory space to read the NAND Flash page (data field + Spare field) byte by byte. 6. The next NAND Flash page can be read without any CPU command or address write operation, in three different ways: – by simply performing the operation described in step 5 – a new random address can be accessed by restarting the operation at step 3 – a new command can be sent to the NAND Flash device by restarting at step 2 NAND Flash pre-wait functionality Some NAND Flash devices require that, after writing the last part of the address, the controller wait for the R/NB signal to go low as shown in Figure 176. Figure 176. Access to non ‘CE don’t care’ NAND-Flash NCE must stay low NCE CLE ALE NWE High NOE tR I/O[7:0] 0x00 A7-A0 A16-A9 A24-A17 A25 tWB R/NB (1) (2) (3) (4) (5) ai14733 1. CPU wrote byte 0x00 at address 0x7001 0000. 2. CPU wrote byte A7~A0 at address 0x7002 0000. 3. CPU wrote byte A16~A9 at address 0x7002 0000. 4. CPU wrote byte A24~A17 at address 0x7002 0000. 5. CPU wrote byte A25 at address 0x7802 0000: FSMC performs a write access using FSMC_PATT2 timing definition, where ATTHOLD  7 (providing that (7+1) × HCLK = 112 ns > tWB max). This guarantees that NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where NCE is not don’t care). 446/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) 19.6.6 When this functionality is needed, it can be guaranteed by programming the MEMHOLD value to meet the tWB timing, however any CPU read or write access to the NAND Flash then has the hold delay of (MEMHOLD + 1) HCLK cycles inserted from the rising edge of the NWE signal to the next access. To overcome this timing constraint, the attribute memory space can be used by programming its timing register with an ATTHOLD value that meets the tWB timing, and leaving the MEMHOLD value at its minimum. Then, the CPU must use the common memory space for all NAND Flash read and write accesses, except when writing the last address byte to the NAND Flash device, where the CPU must write to the attribute memory space. Error correction code computation ECC (NAND Flash) The FSMC PC-Card controller includes two error correction code computation hardware blocks, one per memory bank. They are used to reduce the host CPU workload when processing the error correction code by software in the system. These two registers are identical and associated with bank 2 and bank 3, respectively. As a consequence, no hardware ECC computation is available for memories connected to bank 4. The error correction code (ECC) algorithm implemented in the FSMC can perform 1-bit error correction and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read from or written to NAND Flash. The ECC modules monitor the NAND Flash databus and read/write signals (NCE and NWE) each time the NAND Flash memory bank is active. The functional operations are: ● When access to NAND Flash is made to bank 2 or bank 3, the data present on the D[15:0] bus is latched and used for ECC computation. ● When access to NAND Flash occurs at any other address, the ECC logic is idle, and does not perform any operation. Thus, write operations for defining commands or addresses to NAND Flash are not taken into account for ECC computation. Once the desired number of bytes has been read from/written to the NAND Flash by the host CPU, the FSMC_ECCR2/3 registers must be read in order to retrieve the computed value. Once read, they should be cleared by resetting the ECCEN bit to zero. To compute a new data block, the ECCEN bit must be set to one in the FSMC_PCR2/3 registers. Doc ID 13902 Rev 9 447/995 Flexible static memory controller (FSMC) RM0008 ECCEN PTYP PBKEN PWAITEN Reserved 19.6.7 NAND Flash/PC Card controller registers PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) Address offset: 0xA0000000 + 0x40 + 0x20 * (x – 1), x = 2..4 Reset value: 0x0000 0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ECCPS TAR TCLR Res. PWID rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 19:17 ECCPS: ECC page size. Defines the page size for the extended ECC: 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes Bits 16:13 TAR: ALE to RE delay. Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 4) × THCLK where THCLK is the HCLK clock period 0000: 1 HCLK cycle (default) 1111: 16 HCLK cycles Note: SET is MEMSET or ATTSET according to the addressed space. Bits 12:9 TCLR: CLE to RE delay. Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 4) × THCLK where THCLK is the HCLK clock period 0000: 1 HCLK cycle (default) 1111: 16 HCLK cycles Note: SET is MEMSET or ATTSET according to the addressed space. Bits 8:7 Reserved. Bits 6 ECCEN: ECC computation logic enable bit 0: ECC logic is disabled and reset (default after reset), 1: ECC logic is enabled. Bits 5:4 PWID: Databus width. Defines the external memory device width. 00: 8 bits (default after reset) 01: 16 bits (mandatory for PC Card) 10: reserved, do not use 11: reserved, do not use Bit 3 PTYP: Memory type. Defines the type of device attached to the corresponding memory bank: 0: PC Card, CompactFlash, CF+ or PCMCIA 1: NAND Flash (default after reset) 448/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Bit 2 PBKEN: PC Card/NAND Flash memory bank enable bit. Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus 0: Corresponding memory bank is disabled (default after reset) 1: Corresponding memory bank is enabled Bit 1 PWAITEN: Wait feature enable bit. Enables the Wait feature for the PC Card/NAND Flash memory bank: 0: disabled 1: enabled Note: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx bits must be programmed to a value higher than tv(IORDY-NOE)/THCLK + 4, where tv(IORDY-NOE) is the maximum time taken by NWAIT to go low once NOE is low. Bit 0 Reserved. FIFO status and interrupt register 2..4 (FSMC_SR2..4) Address offset: 0xA000 0000 + 0x44 + 0x20 * (x-1), x = 2..4 Reset value: 0x0000 0040 This register contains information about FIFO status and interrupt. The FSMC has a FIFO that is used when writing to memories to store up to16 words of data from the AHB. This is used to quickly write to the AHB and free it for transactions to peripherals other than the FSMC, while the FSMC is draining its FIFO into the memory. This register has one of its bits that indicates the status of the FIFO, for ECC purposes. The ECC is calculated while the data are written to the memory, so in order to read the correct ECC the software must wait until the FIFO is empty. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FEMPT IFEN ILEN IREN IFS ILS IRS Bit 6 FEMPT: FIFO empty. Read-only bit that provides the status of the FIFO 0: FIFO not empty 1: FIFO empty Bit 5 IFEN: Interrupt falling edge detection enable bit 0: Interrupt falling edge detection request disabled 1: Interrupt falling edge detection request enabled Bit 4 ILEN: Interrupt high-level detection enable bit 0: Interrupt high-level detection request disabled 1: Interrupt high-level detection request enabled Bit 3 IREN: Interrupt rising edge detection enable bit 0: Interrupt rising edge detection request disabled 1: Interrupt rising edge detection request enabled r rw rw rw rw rw rw Doc ID 13902 Rev 9 449/995 Flexible static memory controller (FSMC) RM0008 Bit 2 IFS: Interrupt falling edge status The flag is set by hardware and reset by software. 0: No interrupt falling edge occurred 1: Interrupt falling edge occurred Bit 1 ILS: Interrupt high-level status The flag is set by hardware and reset by software. 0: No Interrupt high-level occurred 1: Interrupt high-level occurred Bit 0 IRS: Interrupt rising edge status The flag is set by hardware and reset by software. 0: No interrupt rising edge occurred 1: Interrupt rising edge occurred Common memory space timing register 2..4 (FSMC_PMEM2..4) Address offset: Address: 0xA000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4 Reset value: 0xFCFC FCFC Each FSMC_PMEMx (x = 2..4) read/write register contains the timing information for PC Card or NAND Flash memory bank x, used for access to the common memory space of the 16-bit PC Card/CompactFlash, or to access the NAND Flash for command, address write access and data read/write access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MEMHIZx MEMHOLDx MEMWAITx MEMSETx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 MEMHIZx: Common memory x databus HiZ time Defines the number of HCLK (+1 only for NAND) clock cycles during which the databus is kept in HiZ after the start of a PC Card/NAND Flash write access to common memory space on socket x. Only valid for write transaction: 0000 0000: (0x00) 0 HCLK cycle (for PC Card) / 1 HCLK cycle (for NAND Flash) 1111 1111: (0xFF) 255 HCLK cycles (for PC Card) / 256 HCLK cycles (for NAND Flash) (default value after reset) Bits 23:16 MEMHOLDx: Common memory x hold time Defines the number of HCLK clock cycles to hold address (and data for write access) after the command deassertion (NWE, NOE), for PC Card/NAND Flash read or write access to common memory space on socket x: 0000 0000: reserved 0000 0001: 1 HCLK cycle 1111 1111: 255 HCLK cycles (default value after reset) Bits 15:8 MEMWAITx: Common memory x wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for PC Card/NAND Flash read or write access to common memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK: 0000 0000: reserved 0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT) 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) 450/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) Bits 7:0 MEMSETx: Common memory x setup time Defines the number of HCLK (+1 for PC Card, +2 for NAND) clock cycles to set up the address before the command assertion (NWE, NOE), for PC Card/NAND Flash read or write access to common memory space on socket x: 0000 0000: 1 HCLK cycle (for PC Card) / HCLK cycles (for NAND Flash) 1111 1111: 256 HCLK cycles (for PC Card) / 257 HCLK cycles (for NAND Flash) - (default value after reset) Attribute memory space timing registers 2..4 (FSMC_PATT2..4) Address offset: 0xA000 0000 + 0x4C + 0x20 * (x – 1), x = 2..4 Reset value: 0xFCFC FCFC Each FSMC_PATTx (x = 2..4) read/write register contains the timing information for PC Card/CompactFlash or NAND Flash memory bank x. It is used for 8-bit accesses to the attribute memory space of the PC Card/CompactFlash (every AHB transaction is split up into a sequence of 8-bit transactions), or to access the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section 19.6.5: NAND Flash pre-wait functionality). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATTHIZx ATTHOLDx ATTWAITx ATTSETx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 ATTHIZx: Attribute memory x databus HiZ time Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a PC CARD/NAND Flash write access to attribute memory space on socket x. Only valid for write transaction: 0000 0000: 0 HCLK cycle 1111 1111: 255 HCLK cycles (default value after reset) Bits 23:16 ATTHOLDx: Attribute memory x hold time Defines the number of HCLK clock cycles to hold address (and data for write access) after the command deassertion (NWE, NOE), for PC Card/NAND Flash read or write access to attribute memory space on socket x 0000 0000: reserved 0000 0001: 1 HCLK cycle 1111 1111: 255 HCLK cycles (default value after reset) Bits 15:8 ATTWAITx: Attribute memory x wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for PC Card/NAND Flash read or write access to attribute memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK: 0000 0000: reserved 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) (default value after reset) Doc ID 13902 Rev 9 451/995 Flexible static memory controller (FSMC) RM0008 Bits 7:0 ATTSETx: Attribute memory x setup time Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory space on socket x: 0000 0000: 1 HCLK cycle 1111 1111: 256 HCLK cycles (default value after reset) I/O space timing register 4 (FSMC_PIO4) Address offset: 0xA000 0000 + 0xB0 Reset value: 0xFCFCFCFC The FSMC_PIO4 read/write registers contain the timing information used to gain access to the I/O space of the 16-bit PC Card/CompactFlash. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOHIZx IOHOLDx IOWAITx IOSETx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 IOHIZx: I/O x databus HiZ time Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a PC Card write access to I/O space on socket x. Only valid for write transaction: 0000 0000: 0 HCLK cycle 1111 1111: 255 HCLK cycles (default value after reset) Bits 23:16 IOHOLDx: I/O x hold time Defines the number of HCLK clock cycles to hold address (and data for write access) after the command deassertion (NWE, NOE), for PC Card read or write access to I/O space on socket x: 0000 0000: reserved 0000 0001: 1 HCLK cycle 1111 1111: 255 HCLK cycles (default value after reset) Bits 15:8 IOWAITx: I/O x wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, SMNOE), for PC Card read or write access to I/O space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK: 0000 0000: reserved, do not use this value 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) Bits 7:0 IOSETx: I/O x setup time Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for PC Card read or write access to I/O space on socket x: 0000 0000: 1 HCLK cycle 1111 1111: 256 HCLK cycles (default value after reset) 452/995 Doc ID 13902 Rev 9 RM0008 Flexible static memory controller (FSMC) ECC result registers 2/3 (FSMC_ECCR2/3) Address offset: 0xA000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3 Reset value: 0x0000 0000 These registers contain the current error correction code value computed by the ECC computation modules of the FSMC controller (one module per NAND Flash memory bank). When the CPU reads the data from a NAND Flash memory page at the correct address (refer to Section 19.6.6: Error correction code computation ECC (NAND Flash)), the data read from or written to the NAND Flash are processed automatically by ECC computation module. At the end of X bytes read (according to the ECCPS field in the FSMC_PCRx registers), the CPU must read the computed ECC value from the FSMC_ECCx registers, and then verify whether these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it if applicable. The FSMC_ECCRx registers should be cleared after being read by setting the ECCEN bit to zero. For computing a new data block, the ECCEN bit must be set to one. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ECCx r Bits 31:0 ECCx: ECC result This field provides the value computed by the ECC computation logic. Table 118 hereafter describes the contents of these bit fields. Table 118. ECC result relevant bits ECCPS[2:0] Page size in bytes 000 256 001 512 010 1024 011 2048 100 4096 101 8192 ECC bits ECC[21:0] ECC[23:0] ECC[25:0] ECC[27:0] ECC[29:0] ECC[31:0] Doc ID 13902 Rev 9 453/995 Flexible static memory controller (FSMC) 19.6.8 FSMC register map The following table summarizes the FSMC registers. Table 119. FSMC register map Offset Register 16 17 18 CBURSTRW 19 20 21 22 23 24 25 26 27 28 29 30 31 0xA000 FSMC_BCR1 0000 Reset value 0xA000 0008 FSMC_BCR2 Reserved Reserved Reserved Reserved 15 EXTMOD 14 WAITEN 13 WREN 12 WAITCFG 11 WRAPMOD 10 WAITPOL 9 BURSTEN 8 Reserved 7 FACCEN 6 5 MWID 4 3 MTYP 2 MUXEN 1 RM0008 MBKEN 0 MTYP MUXEN MBKEN MWID MTYP MUXEN MBKEN MWID FACCEN FACCEN FACCEN Reserved Reserved Reserved BURSTEN BURSTEN BURSTEN WAITPOL WAITPOL WAITPOL WRAPMOD WRAPMOD WRAPMOD WAITCFG WAITCFG WAITCFG WREN WREN WAITEN WAITEN WAITEN EXTMOD EXTMOD EXTMOD CBURSTRW CBURSTRW CBURSTRW 0xA000 0010 FSMC_BCR3 Reserved Reserved MTYP MUXEN MBKEN MWID WREN FEMPT FEMPT FEMPT ECCEN ECCEN ECCEN IFEN IFEN IFEN ILEN ILEN ILEN IREN IREN IREN PTYP PTYP PTYP IFS IFS IFS PBKEN PBKEN PBKEN ILS ILS ILS PWAITEN PWAITEN PWAITEN IRS IRS IRS Reserved Reserved Reserved 0xA000 0018 FSMC_BCR4 Reserved 0xA000 0004 FSMC_BTR1 Res. ACCM OD 0xA000 000C FSMC_BTR2 Res. ACCM OD 0xA000 0014 FSMC_BTR3 Res. ACCM OD 0xA000 001C FSMC_BTR4 Res. ACCM OD 0xA000 0104 FSMC_BWTR1 Res. ACCM OD 0xA000 010C FSMC_BWTR2 Res. ACCM OD 0xA000 0114 FSMC_BWTR3 Res. ACCM OD 0xA000 011C FSMC_BWTR4 Res. ACCM OD DATLAT DATLAT DATLAT DATLAT DATLAT DATLAT DATLAT DATLAT 0xA000 0060 FSMC_PCR2 Reserved Reserved CLKDIV CLKDIV CLKDIV CLKDIV CLKDIV CLKDIV CLKDIV CLKDIV BUSTURN BUSTURN BUSTURN BUSTURN Reserved Reserved Reserved Reserved DATAST DATAST DATAST DATAST DATAST DATAST DATAST DATAST ECCPS TAR TCLR ADDHLD ADDHLD ADDHLD ADDHLD ADDHLD ADDHLD ADDHLD ADDHLD ADDSET ADDSET ADDSET ADDSET ADDSET ADDSET ADDSET ADDSET Res. PWID 0xA000 0080 FSMC_PCR3 Reserved ECCPS TAR TCLR Res. PWID 0xA000 00A0 FSMC_PCR4 0xA000 0064 FSMC_SR2 0xA000 0084 FSMC_SR3 0xA000 00A4 FSMC_SR4 0xA000 0068 FSMC_PMEM2 0xA000 0088 FSMC_PMEM3 Reserved MEMHIZx MEMHIZx ECCPS TAR TCLR Res. PWID Reserved Reserved Reserved MEMHOLDx MEMHOLDx MEMWAITx MEMWAITx MEMSETx MEMSETx 454/995 Doc ID 13902 Rev 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0008 Flexible static memory controller (FSMC) Table 119. FSMC register map (continued) Offset Register 0xA000 00A8 FSMC_PMEM4 0xA000 006C FSMC_PATT2 0xA000 008C FSMC_PATT3 0xA000 00AC FSMC_PATT4 0xA000 00B0 FSMC_PIO4 0xA000 0054 FSMC_ECCR2 0xA000 0074 FSMC_ECCR3 MEMHIZx ATTHIZx ATTHIZx ATTHIZx IOHIZx MEMHOLDx ATTHOLDx ATTHOLDx ATTHOLDx IOHOLDx ECCx ECCx MEMWAITx ATTWAITx ATTWAITx ATTWAITx IOWAITx MEMSETx ATTSETx ATTSETx ATTSETx IOSETx Note: Refer to Table 1 on page 41 for the register boundary addresses. Doc ID 13902 Rev 9 455/995 Secure digital input/output interface (SDIO) 20 Secure digital input/output interface (SDIO) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to high-density performance line devices only. 20.1 SDIO main features The SD/SDIO MMC card host interface (SDIO) provides an interface between the AHB peripheral bus and MultiMediaCards (MMCs), SD memory cards, SDIO cards and CE-ATA devices. The MultiMediaCard system specifications are available through the MultiMediaCard Association website at www.mmca.org, published by the MMCA technical committee. SD memory card and SD I/O card system specifications are available through the SD card Association website at www.sdcard.org. CE-ATA system specifications are available through the CE-ATA workgroup website at www.ce-ata.org. The SDIO features include the following: ● Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit ● Full compatibility with previous versions of MultiMediaCards (forward compatibility) ● Full compliance with SD Memory Card Specifications Version 2.0 ● Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit ● Full support of the CE-ATA features (full compliance with CE-ATA digital protocol Rev1.1) ● Data transfer up to 48 MHz for the 8 bit mode ● Data and command output enable signals to control external bidirectional drivers. Note: 1 The SDIO does not have an SPI-compatible communication mode. 2 The SD memory card protocol is a superset of the MultiMediaCard protocol as defined in the MultiMediaCard system specification V2.11. Several commands required for SD memory devices are not supported by either SD I/O-only cards or the I/O portion of combo cards. Some of these commands have no use in SD I/O devices, such as erase commands, and thus are not supported in the SDIO. In addition, several commands are different between SD memory cards and SD I/O cards and thus are not supported in the SDIO. For details refer to SD I/O card Specification Version 1.0. CE-ATA is supported over the MMC electrical interface using a protocol that utilizes the existing MMC access primitives. The interface electrical and signaling definition is as defined in the MMC reference. 456/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) The MultiMediaCard/SD bus connects cards to the controller. The current version of the SDIO supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. 20.2 SDIO bus topology Communication over the bus is based on command and data transfers. The basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response transaction. These types of bus transaction transfer their information directly within the command or response structure. In addition, some operations have a data token. Data transfers to/from SD/SDIO memory cards are done in data blocks. Data transfers to/from MMC are done data blocks or streams. Data transfers to/from the CE-ATA Devices are done in data blocks. Figure 177. SDIO “no response” and “no data” operations From host to card(s) From host to card From card to host SDIO_CMD Command Command Response SDIO_D Operation (no response) Operation (no data) ai14734 Figure 178. SDIO (multiple) block read operation From host to card From card to host data from card to host SDIO_CMD Command Response Stop command stops data transfer Command Response SDIO_D Data block crc Data block crc Block read operation Multiple block read operation Data block crc Data stop operation ai14735 Doc ID 13902 Rev 9 457/995 Secure digital input/output interface (SDIO) Figure 179. SDIO (multiple) block write operation From host to card From card to host Data from host to card SDIO_CMD Command Response RM0008 Stop command stops data transfer Command Response Note: SDIO_D Optional cards Busy. Needed for CE-ATA Busy Data block crc Busy Data block crc Busy Block write operation Multiple block write operation Data stop operation ai14737 The SDIO will not send any data as long as the Busy signal is asserted (SDIO_D0 pulled low). Figure 180. SDIO sequential read operation From host to card(s) From card to host Data from card to host SDIO_CMD Command Response Stop command stops data transfer Command Response SDIO_D Data stream Data transfer operation Figure 181. SDIO sequential write operation From host to card(s) From card to host Data from host to card SDIO_CMD Command Response Data stop operation ai14738 Stop command stops data transfer Command Response SDIO_D Data stream Data transfer operation Data stop operation ai14739 458/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 20.3 SDIO functional description The SDIO consists of two parts: ● The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. ● The AHB interface accesses the SDIO adapter registers, and generates interrupt and DMA request signals. Figure 182. SDIO block diagram Interrupts and DMA request AHB bus SDIO AHB interface SDIO adapter SDIO_CK SDIO_CMD SDIO_D[7:0] HCLK/2 SDIOCLK ai14740 By default SDIO_D0 is used for data transfer. After initialization, the host can change the databus width. If a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be used for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0 can be used. If an SD or SD I/O card is connected to the bus, data transfer can be configured by the host to use SDIO_D0 or SDIO_D[3:0]. All data lines are operating in push-pull mode. SDIO_CMD has two operational modes: ● Open-drain for initialization (only for MMCV3.31 or previous) ● Push-pull for command transfer (SD/SD I/O card MMC4.2 use push-pull drivers also for initialization) SDIO_CK is the clock to the card: one bit is transferred on both command and data lines with each clock cycle. The clock frequency can vary between 0 MHz and 20 MHz (for a MultiMediaCard V3.31), between 0 and 48 MHz for a MultiMediaCard V4.0/4.2, or between 0 and 25 MHz (for an SD/SD I/O card). The SDIO uses two clock signals: ● SDIO adapter clock (SDIOCLK = HCLK) ● AHB bus clock (HCLK/2) The signals shown in Table 120 are used on the MultiMediaCard/SD/SD I/O card bus. Doc ID 13902 Rev 9 459/995 Secure digital input/output interface (SDIO) RM0008 Table 120. SDIO I/O definitions Pin Direction Description SDIO_CK SDIO_CMD SDIO_D[7:0] Output Bidirectional Bidirectional MultiMediaCard/SD/SDIO card clock. This pin is the clock from host to card. MultiMediaCard/SD/SDIO card command. This pin is the bidirectional command/response signal. MultiMediaCard/SD/SDIO card data. These pins are the bidirectional databus. 20.3.1 SDIO adapter Figure 183 shows a simplified block diagram of an SDIO adapter. Figure 183. SDIO adapter SDIO adapter Control unit SDIO_CK Card bus To AHB interface Adapter registers FIFO Command path Data path SDIO_CMD SDIO_D[7:0] Note: HCLK/2 SDIOCLK ai14740 The SDIO adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card. It consists of five subunits: ● Adapter register block ● Control unit ● Command path ● Data path ● Data FIFO The adapter registers and FIFO use the AHB bus clock domain (HCLK/2). The control unit, command path and data path use the SDIO adapter clock domain (SDIOCLK). Adapter register block The adapter register block contains all system registers. This block also generates the signals that clear the static flags in the multimedia card. The clear signals are generated when 1 is written into the corresponding bit location in the SDIO Clear register. 460/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Control unit The control unit contains the power management functions and the clock divider for the memory card clock. There are three power phases: ● power-off ● power-up ● power-on Figure 184. Control unit Control unit Power management Adapter registers Clock management SDIO_CK To command and data path ai14804 The control unit is illustrated in Figure 184. It consists of a power management subunit and a clock management subunit. The power management subunit disables the card bus output signals during the power-off and power-up phases. The clock management subunit generates and controls the SDIO_CK signal. The SDIO_CK output can use either the clock divide or the clock bypass mode. The clock output is inactive: ● after reset ● during the power-off or power-up phases ● if the power saving mode is enabled and the card bus is in the Idle state (eight clock periods after both the command and data path subunits enter the Idle phase) Command path The command path unit sends commands to and receives responses from the cards. Doc ID 13902 Rev 9 461/995 Secure digital input/output interface (SDIO) Figure 185. SDIO adapter command path RM0008 To control unit Status flag Control logic Command timer Adapter registers CMD Argument CMD Shift register To AHB interface Response registers SDIO_CMDin CRC SDIO_CMDout ai14805 ● Command path state machine (CPSM) – When the command register is written to and the enable bit is set, command transfer starts. When the command has been sent, the command path state machine (CPSM) sets the status flags and enters the Idle state if a response is not required. If a response is required, it waits for the response (see Figure 186 on page 463). When the response is received, the received CRC code and the internally generated code are compared, and the appropriate status flags are set. 462/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Figure 186. Command path state machine (CPSM) On reset CPSM Enabled and pending command CPSM disabled Idle CE-ATA Command Completion signal received or CPSM disabled or Command CRC failed Wait_CPL Response received or disabled or command CRC failed Response Received in CE-ATA mode and no interrupt and wait for CE-ATA Command Completion signal enabled Pend Last Data Enabled and command start CPSM disabled or no response CPSM Disabled or command timeout Receive Send Response started Note: Note: Wait for response Wait Response Received in CE-ATA mode and no interrupt and wait for CE-ATA Command Completion signal disabled ai14806b When the Wait state is entered, the command timer starts running. If the timeout is reached before the CPSM moves to the Receive state, the timeout flag is set and the Idle state is entered. The command timeout has a fixed value of 64 SDIO_CK clock periods. If the interrupt bit is set in the command register, the timer is disabled and the CPSM waits for an interrupt request from one of the cards. If a pending bit is set in the command register, the CPSM enters the Pend state, and waits for a CmdPend signal from the data path subunit. When CmdPend is detected, the CPSM moves to the Send state. This enables the data counter to trigger the stop command transmission. The CPSM remains in the Idle state for at least eight SDIO_CK periods to meet the NCC and NRC timing constraints. NCC is the minimum delay between two host commands, and NRC is the minimum delay between the host command and the card response. Doc ID 13902 Rev 9 463/995 Secure digital input/output interface (SDIO) RM0008 Figure 187. SDIO command transfer SDIO_CK State Idle SDIO_CMD Hi-Z Command Send Wait Controller drives Hi-Z Response at least 8 SDIO_CK cycles Command Receive Idle Send Card drives Hi-Z Controller drives ai14707 ● Command format – Command: a command is a token that starts an operation. Command are sent from the host either to a single card (addressed command) or to all connected cards (broadcast command are available for MMC V3.31 or previous). Commands are transferred serially on the CMD line. All commands have a fixed length of 48 bits. The general format for a command token for MultiMediaCards, SD-Memory cards and SDIO-Cards is shown in Table 121. CE-ATA commands are an extension of MMC commands V4.2, and so have the same format. The command path operates in a half-duplex mode, so that commands and responses can either be sent or received. If the CPSM is not in the Send state, the SDIO_CMD output is in the Hi-Z state, as shown in Figure 187 on page 464. Data on SDIO_CMD are synchronous with the rising edge of SDIO_CK. Table shows the command format. Table 121. Command format Bit position Width 47 1 46 1 [45:40] 6 [39:8] 32 [7:1] 7 0 1 Value 0 1 1 Description Start bit Transmission bit Command index Argument CRC7 End bit Note: – Response: a response is a token that is sent from an addressed card (or synchronously from all connected cards for MMC V3.31 or previous), to the host as an answer to a previously received command. Responses are transferred serially on the CMD line. The SDIO supports two response types. Both use CRC error checking: ● 48 bit short response ● 136 bit long response If the response does not contain a CRC (CMD1 response), the device driver must ignore the CRC failed status. 464/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Table 122. Short response format Bit position Width 47 1 46 1 [45:40] 6 [39:8] 32 [7:1] 7 0 1 Value 0 0 1 Description Start bit Transmission bit Command index Argument CRC7(or 1111111) End bit Table 123. Long response format Bit position Width 135 1 134 1 [133:128] 6 [127:1] 127 0 1 Value 0 0 111111 1 Description Start bit Transmission bit Reserved CID or CSD (including internal CRC7) End bit The command register contains the command index (six bits sent to a card) and the command type. These determine whether the command requires a response, and whether the response is 48 or 136 bits long (see Section 20.9.4 on page 499). The command path implements the status flags shown in Table 124: Table 124. Command path status flags Flag Description CMDREND Set if response CRC is OK. CCRCFAIL Set if response CRC fails. CMDSENT Set when command (that does not require response) is sent CTIMEOUT Response timeout. CMDACT Command transfer in progress. The CRC generator calculates the CRC checksum for all bits before the CRC code. This includes the start bit, transmitter bit, command index, and command argument (or card status). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long response format. Note that the start bit, transmitter bit and the six reserved bits are not used in the CRC calculation. The CRC checksum is a 7-bit value: CRC[6:0] = Remainder [(M(x) * x7) / G(x)] G(x) = x7 + x3 + 1 M(x) = (start bit) * x39 + ... + (last bit before CRC) * x0, or M(x) = (start bit) * x119 + ... + (last bit before CRC) * x0 Doc ID 13902 Rev 9 465/995 Secure digital input/output interface (SDIO) RM0008 Data path The data path subunit transfers data to and from cards. Figure 188 shows a block diagram of the data path. Figure 188. Data path Data path To control unit Status flag Control logic Data timer Data FIFO Transmit Receive Shift register SDIO_Din[7:0] CRC SDIO_Dout[7:0] ai14808 The card databus width can be programmed using the clock control register. If the 4-bit wide bus mode is enabled, data is transferred at four bits per clock cycle over all four data signals (SDIO_D[3:0]). If the 8-bit wide bus mode is enabled, data is transferred at eight bits per clock cycle over all eight data signals (SDIO_D[7:0]). If the wide bus mode is not enabled, only one bit per clock cycle is transferred over SDIO_D0. Depending on the transfer direction (send or receive), the data path state machine (DPSM) moves to the Wait_S or Wait_R state when it is enabled: ● Send: the DPSM moves to the Wait_S state. If there is data in the transmit FIFO, the DPSM moves to the Send state, and the data path subunit starts sending data to a card. ● Receive: the DPSM moves to the Wait_R state and waits for a start bit. When it receives a start bit, the DPSM moves to the Receive state, and the data path subunit starts receiving data from a card. Data path state machine (DPSM) The DPSM operates at SDIO_CK frequency. Data on the card bus signals is synchronous to the rising edge of SDIO_CK. The DPSM has six states, as shown in Figure 189: Data path state machine (DPSM). 466/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Figure 189. Data path state machine (DPSM) On reset DPSM disabled Disabled or FIFO underrun or end of data or CRC fail Idle Disabled or CRC fail or timeout DPSM enabled and Read Wait Started and SD I/O mode enabled Enable and not send Read Wait Busy Disabled or end of data Not busy Enable and send Disabled or Rx FIFO empty or timeout or start bit error Wait_R ReadWait Stop Data received and Read Wait Started and SD I/O mode enabled End of packet Wait_S Disabled or CRC fail End of packet or end of data or FIFO overrun Send Data ready Start bit Receive ai14809b ● Idle: the data path is inactive, and the SDIO_D[7:0] outputs are in Hi-Z. When the data control register is written and the enable bit is set, the DPSM loads the data counter with a new value and, depending on the data direction bit, moves to either the Wait_S or the Wait_R state. ● Wait_R: if the data counter equals zero, the DPSM moves to the Idle state when the receive FIFO is empty. If the data counter is not zero, the DPSM waits for a start bit on SDIO_D. The DPSM moves to the Receive state if it receives a start bit before a timeout, and loads the data block counter. If it reaches a timeout before it detects a start bit, or a start bit error occurs, it moves to the Idle state and sets the timeout status flag. ● Receive: serial data received from a card is packed in bytes and written to the data FIFO. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: – In block mode, when the data block counter reaches zero, the DPSM waits until it receives the CRC code. If the received code matches the internally generated CRC code, the DPSM moves to the Wait_R state. If not, the CRC fail status flag is set and the DPSM moves to the Idle state. – In stream mode, the DPSM receives data while the data counter is not zero. When the counter is zero, the remaining data in the shift register is written to the data FIFO, and the DPSM moves to the Wait_R state. If a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the Idle state: ● Wait_S: the DPSM moves to the Idle state if the data counter is zero. If not, it waits until the data FIFO empty flag is deasserted, and moves to the Send state. Doc ID 13902 Rev 9 467/995 Secure digital input/output interface (SDIO) RM0008 Note: The DPSM remains in the Wait_S state for at least two clock periods to meet the NWR timing requirements, where NWR is the number of clock cycles between the reception of the card response and the start of the data transfer from the host. ● Send: the DPSM starts sending data to a card. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: – In block mode, when the data block counter reaches zero, the DPSM sends an internally generated CRC code and end bit, and moves to the Busy state. – In stream mode, the DPSM sends data to a card while the enable bit is high and the data counter is not zero. It then moves to the Idle state. If a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the Idle state. ● Busy: the DPSM waits for the CRC status flag: – If it does not receive a positive CRC status, it moves to the Idle state and sets the CRC fail status flag. – If it receives a positive CRC status, it moves to the Wait_S state if SDIO_D0 is not low (the card is not busy). If a timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag and moves to the Idle state. The data timer is enabled when the DPSM is in the Wait_R or Busy state, and generates the data timeout error: – When transmitting data, the timeout occurs if the DPSM stays in the Busy state for longer than the programmed timeout period – When receiving data, the timeout occurs if the end of the data is not true, and if the DPSM stays in the Wait_R state for longer than the programmed timeout period. ● Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines. They are stored in a FIFO of 32 words, each word is 32 bits wide. Table 125. Data token format Description Start bit Data Block Data 0 - Stream Data 0 - CRC16 yes no End bit 1 1 Data FIFO The data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit. The FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic. Because the data FIFO operates in the AHB clock domain (HCLK/2), all signals from the subunits in the SDIO clock domain (SDIOCLK) are resynchronized. 468/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Depending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or receive enabled. TXACT and RXACT are driven by the data path subunit and are mutually exclusive: – The transmit FIFO refers to the transmit logic and data buffer when TXACT is asserted – The receive FIFO refers to the receive logic and data buffer when RXACT is asserted ● Transmit FIFO: Data can be written to the transmit FIFO through the AHB interface when the SDIO is enabled for transmission. The transmit FIFO is accessible via 32 sequential addresses. The transmit FIFO contains a data output register that holds the data word pointed to by the read pointer. When the data path subunit has loaded its shift register, it increments the read pointer and drives new data out. If the transmit FIFO is disabled, all status flags are deasserted. The data path subunit asserts TXACT when it transmits data. Table 126. Transmit FIFO status flags Flag Description TXFIFOF TXFIFOE TXFIFOHE TXDAVL TXUNDERR Set to high when all 32 transmit FIFO words contain valid data. Set to high when the transmit FIFO does not contain valid data. Set to high when 8 or more transmit FIFO words are empty. This flag can be used as a DMA request. Set to high when the transmit FIFO contains valid data. This flag is the inverse of the TXFIFOE flag. Set to high when an underrun error occurs. This flag is cleared by writing to the SDIO Clear register. ● Receive FIFO When the data path subunit receives a word of data, it drives the data on the write databus. The write pointer is incremented after the write operation completes. On the read side, the contents of the FIFO word pointed to by the current value of the read pointer is driven onto the read databus. If the receive FIFO is disabled, all status flags are deasserted, and the read and write pointers are reset. The data path subunit asserts RXACT when it receives data. Table 127 lists the receive FIFO status flags. The receive FIFO is accessible via 32 sequential addresses. Doc ID 13902 Rev 9 469/995 Secure digital input/output interface (SDIO) RM0008 Table 127. Receive FIFO status flags Flag Description RXFIFOF RXFIFOE RXFIFOHF RXDAVL RXOVERR Set to high when all 32 receive FIFO words contain valid data Set to high when the receive FIFO does not contain valid data. Set to high when 8 or more receive FIFO words contain valid data. This flag can be used as a DMA request. Set to high when the receive FIFO is not empty. This flag is the inverse of the RXFIFOE flag. Set to high when an overrun error occurs. This flag is cleared by writing to the SDIO Clear register. 20.3.2 SDIO AHB interface The AHB interface generates the interrupt and DMA requests, and accesses the SDIO adapter registers and the data FIFO. It consists of a data path, register decoder, and interrupt/DMA logic. SDIO interrupts The interrupt logic generates an interrupt request signal that is asserted when at least one of the selected status flags is high. A mask register is provided to allow selection of the conditions that will generate an interrupt. A status flag generates the interrupt request if a corresponding mask flag is set. SDIO/DMA interface: procedure for data transfers between the SDIO and memory In the example shown, the transfer is from the SDIO host controller to an MMC (512 bytes using CMD24 (WRITE_BLOCK). The SDIO FIFO is filled by data stored in a memory using the DMA controller. 1. Do the card identification process 2. Increase the SDIO_CK frequency 3. Select the card by sending CMD7 4. Configure the DMA2 as follows: a) Enable DMA2 controller and clear any pending interrupts b) Program the DMA2_Channel4 source address register with the memory location’s base address and DMA2_Channel4 destination address register with the SDIO_FIFO register address c) Program DMA2_Channel4 control register (memory increment, not peripheral increment, peripheral and source width is word size) d) Enable DMA2_Channel4 470/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 5. Send CMD24 (WRITE_BLOCK) as follows: a) Program the SDIO data length register (SDIO data timer register should be already programmed before the card identification process) b) Program the SDIO argument register with the address location of the card where data is to be transferred c) Program the SDIO command register: CmdIndex with 24 (WRITE_BLOCK); WaitResp with ‘1’ (SDIO card host waits for a response); CPSMEN with ‘1’ (SDIO card host enabled to send a command). Other fields are at their reset value. d) Wait for SDIO_STA[6] = CMDREND interrupt, then program the SDIO data control register: DTEN with ‘1’ (SDIO card host enabled to send data); DTDIR with ‘0’ (from controller to card); DTMODE with ‘0’ (block data transfer); DMAEN with ‘1’ (DMA enabled); DBLOCKSIZE with 0x9 (512 bytes). Other fields are don’t care. e) Wait for SDIO_STA[10] = DBCKEND 6. Check that no channels are still enabled by polling the DMA Enabled Channel Status register. 20.4 20.4.1 20.4.2 20.4.3 Card functional description Card identification mode While in card identification mode the host resets all cards, validates the operation voltage range, identifies cards and sets a relative card address (RCA) for each card on the bus. All data communications in the card identification mode use the command line (CMD) only. Card reset The GO_IDLE_STATE command (CMD0) is the software reset command and it puts the MultiMediaCard and SD memory in the Idle state. The IO_RW_DIRECT command (CMD52) resets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the highimpedance state and the cards are initialized with a default relative card address (RCA=0x0001) and with a default driver stage register setting (lowest speed, highest driving current capability). Operating voltage range validation All cards can communicate with the SDIO card host using any operating voltage within the specification range. The supported minimum and maximum VDD values are defined in the operation conditions register (OCR) on the card. Cards that store the card identification number (CID) and card specific data (CSD) in the payload memory are able to communicate this information only under data-transfer VDD conditions. When the SDIO card host module and the card have incompatible VDD ranges, the card is not able to complete the identification cycle and cannot send CSD data. For this purpose, the special commands, SEND_OP_COND (CMD1), SD_APP_OP_COND (ACMD41 for SD Memory), and IO_SEND_OP_COND (CMD5 for SD I/O), are designed to provide a mechanism to identify and reject cards that do not match the VDD range desired by the SDIO card host. The SDIO card host sends the required VDD voltage window as the operand of these commands. Cards that cannot perform data transfer in the specified range disconnect from the bus and go to the inactive state. Doc ID 13902 Rev 9 471/995 Secure digital input/output interface (SDIO) RM0008 20.4.4 By using these commands without including the voltage range as the operand, the SDIO card host can query each card and determine the common voltage range before placing outof-range cards in the inactive state. This query is used when the SDIO card host is able to select a common voltage range or when the user requires notification that cards are not usable. Card identification process The card identification process differs for MultiMediaCards and SD cards. For MultiMediaCard cards, the identification process starts at clock rate Fod. The SDIO_CMD line output drivers are open-drain and allow parallel card operation during this process. The registration process is accomplished as follows: 1. The bus is activated. 2. The SDIO card host broadcasts SEND_OP_COND (CMD1) to receive operation conditions. 3. The response is the wired AND operation of the operation condition registers from all cards. 4. Incompatible cards are placed in the inactive state. 5. The SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards. 6. The active cards simultaneously send their CID numbers serially. Cards with outgoing CID bits that do not match the bits on the command line stop transmitting and must wait for the next identification cycle. One card successfully transmits a full CID to the SDIO card host and enters the Identification state. 7. The SDIO card host issues SET_RELATIVE_ADDR (CMD3) to that card. This new address is called the relative card address (RCA); it is shorter than the CID and addresses the card. The assigned card changes to the Standby state, it does not react to further identification cycles, and its output switches from open-drain to push-pull. 8. The SDIO card host repeats steps 5 through 7 until it receives a timeout condition. For the SD card, the identification process starts at clock rate Fod, and the SDIO_CMD line output drives are push-pull drivers instead of open-drain. The registration process is accomplished as follows: 1. The bus is activated. 2. The SDIO card host broadcasts SD_APP_OP_COND (ACMD41). 3. The cards respond with the contents of their operation condition registers. 4. The incompatible cards are placed in the inactive state. 5. The SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards. 6. The cards send back their unique card identification numbers (CIDs) and enter the Identification state. 7. The SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an address. This new address is called the relative card address (RCA); it is shorter than the CID and addresses the card. The assigned card changes to the Standby state. The SDIO card host can reissue this command to change the RCA. The RCA of the card is the last assigned value. 8. The SDIO card host repeats steps 5 through 7 with all active cards. For the SD I/O card, the registration process is accomplished as follows: 472/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 20.4.5 20.4.6 1. The bus is activated. 2. The SDIO card host sends IO_SEND_OP_COND (CMD5). 3. The cards respond with the contents of their operation condition registers. 4. The incompatible cards are set to the inactive state. 5. The SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an address. This new address is called the relative card address (RCA); it is shorter than the CID and addresses the card. The assigned card changes to the Standby state. The SDIO card host can reissue this command to change the RCA. The RCA of the card is the last assigned value. Block write During block write (CMD24 - 27) one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block by the host. A card supporting block write is always able to accept a block of data defined by WRITE_BL_LEN. If the CRC fails, the card indicates the failure on the SDIO_D line and the transferred data are discarded and not written, and all further transmitted blocks (in multiple block write mode) are ignored. If the host uses partial blocks whose accumulated length is not block aligned and, block misalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card will detect the block misalignment error before the beginning of the first misaligned block. (ADDRESS_ERROR error bit is set in the status register). The write operation will also be aborted if the host tries to write over a write-protected area. In this case, however, the card will set the WP_VIOLATION bit. Programming of the CID and CSD registers does not require a previous block length setting. The transferred data is also CRC protected. If a part of the CSD or CID register is stored in ROM, then this unchangeable part must match the corresponding part of the receive buffer. If this match fails, then the card reports an error and does not change any register contents. Some cards may require long and unpredictable times to write a block of data. After receiving a block of data and completing the CRC check, the card begins writing and holds the SDIO_D line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS command (CMD13) at any time, and the card will respond with its status. The READY_FOR_DATA status bit indicates whether the card can accept new data or whether the write process is still in progress. The host may deselect the card by issuing CMD7 (to select a different card), which will place the card in the Disconnect state and release the SDIO_D line(s) without interrupting the write operation. When reselecting the card, it will reactivate busy indication by pulling SDIO_D to low if programming is still in progress and the write buffer is unavailable. Block read In Block read mode the basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks whose start and end addresses are entirely contained within one physical block (as defined by READ_BL_LEN) may also be transmitted. A CRC is appended to the end of each block, ensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a block read and after completing the transfer, the card returns to the Transfer state. CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. Doc ID 13902 Rev 9 473/995 Secure digital input/output interface (SDIO) RM0008 20.4.7 The host can abort reading at any time, within a multiple block operation, regardless of its type. Transaction abort is done by sending the stop transmission command. If the card detects an error (for example, out of range, address misalignment or internal error) during a multiple block read operation (both types) it stops the data transmission and remains in the data state. The host must than abort the operation by sending the stop transmission command. The read error is reported in the response to the stop transmission command. If the host sends a stop transmission command after the card transmits the last block of a multiple block operation with a predefined number of blocks, it is responded to as an illegal command, since the card is no longer in the data state. If the host uses partial blocks whose accumulated length is not block-aligned and block misalignment is not allowed, the card detects a block misalignment error condition at the beginning of the first misaligned block (ADDRESS_ERROR error bit is set in the status register). Stream access, stream write and stream read (MultiMediaCard only) In stream mode, data is transferred in bytes and no CRC is appended at the end of each block. Stream write (MultiMediaCard only) WRITE_DAT_UNTIL_STOP (CMD20) starts the data transfer from the SDIO card host to the card, beginning at the specified address and continuing until the SDIO card host issues a stop command. When partial blocks are allowed (CSD parameter WRITE_BL_PARTIAL is set), the data stream can start and stop at any address within the card address space, otherwise it can only start and stop at block boundaries. Because the amount of data to be transferred is not determined in advance, a CRC cannot be used. When the end of the memory range is reached while sending data and no stop command is sent by the SD card host, any additional transferred data are discarded. The maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register: Maximumspeed= MIN(TRANSPEED,---8----------2---w-----r--i--t--e----b---l--l--e---n---------–---N-----S----A-----C-----) TAAC  R2WFACTOR ● Maximumspeed = maximum write frequency ● TRANSPEED = maximum data transfer rate ● writebllen = maximum write data block length ● NSAC = data read access time 2 in CLK cycles ● TAAC = data read access time 1 ● R2WFACTOR = write speed factor If the host attempts to use a higher frequency, the card may not be able to process the data and stop programming, set the OVERRUN error bit in the status register, and while ignoring all further data transfer, wait (in the receive data state) for a stop command. The write operation is also aborted if the host tries to write over a write-protected area. In this case, however, the card sets the WP_VIOLATION bit. 474/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 20.4.8 Stream read (MultiMediaCard only) READ_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer. This command instructs the card to send its data, starting at a specified address, until the SDIO card host sends STOP_TRANSMISSION (CMD12). The stop command has an execution delay due to the serial command transmission and the data transfer stops after the end bit of the stop command. When the end of the memory range is reached while sending data and no stop command is sent by the SDIO card host, any subsequent data sent are considered undefined. The maximum clock frequency for a stream read operation is given by the following equation and uses fields of the card specific data register. Maximumspeed= MIN(TRANSPEED,---8-T----A-----2A---r-C--e---a----d--R--b--2-l--l-W-e---n--F----A---–-C--N---T--S--O--A---R--C-----) ● Maximumspeed = maximum read frequency ● TRANSPEED = maximum data transfer rate ● readbllen = maximum read data block length ● writebllen = maximum write data block length ● NSAC = data read access time 2 in CLK cycles ● TAAC = data read access time 1 ● R2WFACTOR = write speed factor If the host attempts to use a higher frequency, the card is not able to sustain data transfer. If this happens, the card sets the UNDERRUN error bit in the status register, aborts the transmission and waits in the data state for a stop command. Erase: group erase and sector erase The erasable unit of the MultiMediaCard is the erase group. The erase group is measured in write blocks, which are the basic writable units of the card. The size of the erase group is a card-specific parameter and defined in the CSD. The host can erase a contiguous range of Erase Groups. Starting the erase process is a three-step sequence. First the host defines the start address of the range using the ERASE_GROUP_START (CMD35) command, next it defines the last address of the range using the ERASE_GROUP_END (CMD36) command and, finally, it starts the erase process by issuing the ERASE (CMD38) command. The address field in the erase commands is an Erase Group address in byte units. The card ignores all LSBs below the Erase Group size, effectively rounding the address down to the Erase Group boundary. If an erase command is received out of sequence, the card sets the ERASE_SEQ_ERROR bit in the status register and resets the whole sequence. If an out-of-sequence (neither of the erase commands, except SEND_STATUS) command received, the card sets the ERASE_RESET status bit in the status register, resets the erase sequence and executes the last command. If the erase range includes write protected blocks, they are left intact and only nonprotected blocks are erased. The WP_ERASE_SKIP status bit in the status register is set. Doc ID 13902 Rev 9 475/995 Secure digital input/output interface (SDIO) RM0008 The card indicates that an erase is in progress by holding SDIO_D low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card. 20.4.9 Wide bus selection or deselection Wide bus (4-bit bus width) operation mode is selected or deselected using SET_BUS_WIDTH (ACMD6). The default bus width after power-up or GO_IDLE_STATE (CMD0) is 1 bit. SET_BUS_WIDTH (ACMD6) is only valid in a transfer state, which means that the bus width can be changed only after a card is selected by SELECT/DESELECT_CARD (CMD7). 20.4.10 Protection management Three write protection methods for the cards are supported in the SDIO card host module: 1. internal card write protection (card responsibility) 2. mechanical write protection switch (SDIO card host module responsibility only) 3. password-protected card lock operation Internal card write protection Card data can be protected against write and erase. By setting the permanent or temporary write-protect bits in the CSD, the entire card can be permanently write-protected by the manufacturer or content provider. For cards that support write protection of groups of sectors by setting the WP_GRP_ENABLE bit in the CSD, portions of the data can be protected, and the write protection can be changed by the application. The write protection is in units of WP_GRP_SIZE sectors as specified in the CSD. The SET_WRITE_PROT and CLR_WRITE_PROT commands control the protection of the addressed group. The SEND_WRITE_PROT command is similar to a single block read command. The card sends a data block containing 32 write protection bits (representing 32 write protect groups starting at the specified address) followed by 16 CRC bits. The address field in the write protect commands is a group address in byte units. The card ignores all LSBs below the group size. Mechanical write protect switch A mechanical sliding tab on the side of the card allows the user to set or clear the write protection on a card. When the sliding tab is positioned with the window open, the card is write-protected, and when the window is closed, the card contents can be changed. A matched switch on the socket side indicates to the SDIO card host module that the card is write-protected. The SDIO card host module is responsible for protecting the card. The position of the write protect switch is unknown to the internal circuitry of the card. Password protect The password protection feature enables the SDIO card host module to lock and unlock a card with a password. The password is stored in the 128-bit PWD register and its size is set in the 8-bit PWD_LEN register. These registers are non-volatile so that a power cycle does not erase them. Locked cards respond to and execute certain commands. This means that the SDIO card host module is allowed to reset, initialize, select, and query for status, however it is not allowed to access data on the card. When the password is set (as indicated by a nonzero value of PWD_LEN), the card is locked automatically after power-up. As with the CSD and CID register write commands, the lock/unlock commands are available in the transfer state only. In this state, the command does not include an address argument and 476/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) the card must be selected before using it. The card lock/unlock commands have the structure and bus transaction types of a regular single-block write command. The transferred data block includes all of the required information for the command (the password setting mode, the PWD itself, and card lock/unlock). The command data block size is defined by the SDIO card host module before it sends the card lock/unlock command, and has the structure shown in Table 141. The bit settings are as follows: ● ERASE: setting it forces an erase operation. All other bits must be zero, and only the command byte is sent ● LOCK_UNLOCK: setting it locks the card. LOCK_UNLOCK can be set simultaneously with SET_PWD, however not with CLR_PWD ● CLR_PWD: setting it clears the password data ● SET_PWD: setting it saves the password data to memory ● PWD_LEN: it defines the length of the password in bytes ● PWD: the password (new or currently used, depending on the command) The following sections list the command sequences to set/reset a password, lock/unlock the card, and force an erase. Setting the password 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode, the 8-bit PWD_LEN, and the number of bytes of the new password. When a password replacement is done, the block size must take into account that both the old and the new passwords are sent with the command. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (SET_PWD = 1), the length (PWD_LEN), and the password (PWD) itself. When a password replacement is done, the length value (PWD_LEN) includes the length of both passwords, the old and the new one, and the PWD field includes the old password (currently used) followed by the new password. 4. When the password is matched, the new password and its size are saved into the PWD and PWD_LEN fields, respectively. When the old password sent does not correspond (in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the password is not changed. The password length field (PWD_LEN) indicates whether a password is currently set. When this field is nonzero, there is a password set and the card locks itself after power-up. It is possible to lock the card immediately in the current power session by setting the LOCK_UNLOCK bit (while setting the password) or sending an additional command for card locking. Doc ID 13902 Rev 9 477/995 Secure digital input/output interface (SDIO) RM0008 Resetting the password 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode, the 8-bit PWD_LEN, and the number of bytes in the currently used password. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (CLR_PWD = 1), the length (PWD_LEN) and the password (PWD) itself. The LOCK_UNLOCK bit is ignored. 4. When the password is matched, the PWD field is cleared and PWD_LEN is set to 0. When the password sent does not correspond (in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the password is not changed. Locking a card 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode (byte 0 in Table 141), the 8-bit PWD_LEN, and the number of bytes of the current password. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 1), the length (PWD_LEN), and the password (PWD) itself. 4. When the password is matched, the card is locked and the CARD_IS_LOCKED status bit is set in the card status register. When the password sent does not correspond (in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the lock fails. It is possible to set the password and to lock the card in the same sequence. In this case, the SDIO card host module performs all the required steps for setting the password (see Setting the password on page 477), however it is necessary to set the LOCK_UNLOCK bit in Step 3 when the new password command is sent. When the password is previously set (PWD_LEN is not 0), the card is locked automatically after power on reset. An attempt to lock a locked card or to lock a card that does not have a password fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register. Unlocking the card 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit cardlock/unlock mode (byte 0 in Table 141), the 8-bit PWD_LEN, and the number of bytes of the current password. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 0), the length (PWD_LEN), and the password (PWD) itself. 4. When the password is matched, the card is unlocked and the CARD_IS_LOCKED status bit is cleared in the card status register. When the password sent is not correct in size and/or content and does not correspond to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the card remains locked. 478/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) The unlocking function is only valid for the current power session. When the PWD field is not clear, the card is locked automatically on the next power-up. An attempt to unlock an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register. Forcing erase If the user has forgotten the password (PWD content), it is possible to access the card after clearing all the data on the card. This forced erase operation erases all card data and all password data. 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Set the block length (SET_BLOCKLEN, CMD16) to 1 byte. Only the 8-bit card lock/unlock byte (byte 0 in Table 141) is sent. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data byte on the data line including the 16-bit CRC. The data block indicates the mode (ERASE = 1). All other bits must be zero. 4. When the ERASE bit is the only bit set in the data field, all card contents are erased, including the PWD and PWD_LEN fields, and the card is no longer locked. When any other bits are set, the LOCK_UNLOCK_FAILED error bit is set in the card status register and the card retains all of its data, and remains locked. An attempt to use a force erase on an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register. 20.4.11 Card status register The response format R1 contains a 32-bit field named card status. This field is intended to transmit the card status information (which may be stored in a local status register) to the host. If not specified otherwise, the status entries are always related to the previously issued command. Table 128 defines the different entries of the status. The type and clear condition fields in the table are abbreviated as follows: Type: ● E: error bit ● S: status bit ● R: detected and set for the actual command response ● X: detected and set during command execution. The SDIO card host must poll the card by issuing the status command to read these bits. Clear condition: ● A: according to the card current state ● B: always related to the previous command. Reception of a valid command clears it (with a delay of one command) ● C: clear by read Doc ID 13902 Rev 9 479/995 Secure digital input/output interface (SDIO) RM0008 Table 128. Card status Bits Identifier 31 ADDRESS_ OUT_OF_RANGE 30 ADDRESS_MISALIGN 29 BLOCK_LEN_ERROR 28 ERASE_SEQ_ERROR 27 ERASE_PARAM 26 WP_VIOLATION 25 CARD_IS_LOCKED 24 LOCK_UNLOCK_ FAILED 23 COM_CRC_ERROR 22 ILLEGAL_COMMAND 21 CARD_ECC_FAILED 20 CC_ERROR Type Value Description Clear condition ’0’= no error ERX ’1’= error ’0’= no error ’1’= error ’0’= no error ’1’= error ’0’= no error ’1’= error EX ’0’= no error ’1’= error The command address argument was out of the allowed range for this card. A multiple block or stream read/write C operation is (although started in a valid address) attempting to read or write beyond the card capacity. The commands address argument (in accordance with the currently set block length) positions the first data block misaligned to the card physical blocks. A multiple block read/write operation C (although started with a valid address/block-length combination) is attempting to read or write a data block which is not aligned with the physical blocks of the card. Either the argument of a SET_BLOCKLEN command exceeds the maximum value allowed for the card, or the previously defined block length is illegal for the current command (e.g. the C host issues a write command, the current block length is smaller than the maximum allowed value for the card and it is not allowed to write partial blocks) An error in the sequence of erase commands occurred. C An invalid selection of erase groups for erase occurred. C EX ’0’= no error ’1’= error Attempt to program a write-protected block. C SR ‘0’ = card unlocked ‘1’ = card locked When set, signals that the card is locked by the host A EX ’0’= no error ’1’= error Set when a sequence or password error has been detected in lock/unlock card C command ER ’0’= no error ’1’= error The CRC check of the previous command failed. B ER ’0’= no error ’1’= error Command not legal for the card state B EX ’0’= success ’1’= failure Card internal ECC was applied but failed to correct the data. C ER ’0’= no error ’1’= error (Undefined by the standard) A card error occurred, which is not related to the host C command. 480/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Table 128. Card status (continued) Bits Identifier Type Value Description Clear condition 19 ERROR EX ’0’= no error ’1’= error (Undefined by the standard) A generic card error related to the (and detected during) execution of the last host C command (e.g. read or write failures). 18 Reserved 17 Reserved Can be either of the following errors: – The CID register has already been written and cannot be overwritten 16 CID/CSD_OVERWRITE E X ’0’= no error ‘1’= error – The read-only section of the CSD does C not match the card contents – An attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made 15 WP_ERASE_SKIP EX ’0’= not protected Set when only partial address space ’1’= protected was erased due to existing write C 14 CARD_ECC_DISABLED S X 13 ERASE_RESET 12:9 CURRENT_STATE SR 8 READY_FOR_DATA SR 7 SWITCH_ERROR EX 6 Reserved 5 APP_CMD SR 4 Reserved for SD I/O Card ’0’= enabled ’1’= disabled The command has been executed without using the internal ECC. A ’0’= cleared ’1’= set An erase sequence was cleared before executing because an out of erase sequence command was received C (commands other than CMD35, CMD36, CMD38 or CMD13) 0 = Idle 1 = Ready 2 = Ident 3 = Stby 4 = Tran 5 = Data 6 = Rcv 7 = Prg 8 = Dis The state of the card when receiving the command. If the command execution causes a state change, it will be visible to the host in the response on the next B command. The four bits are interpreted as a binary number between 0 and 15. 9 = Btst 10-15 = reserved ’0’= not ready ‘1’ Corresponds to buffer empty signalling on = ready the bus ’0’= no error ’1’= switch error If set, the card did not switch to the expected mode as requested by the SWITCH command B ‘0’ = Disabled ‘1’ = Enabled The card will expect ACMD, or an indication that the command has been C interpreted as ACMD Doc ID 13902 Rev 9 481/995 Secure digital input/output interface (SDIO) RM0008 Table 128. Card status (continued) Bits Identifier Type Value 3 AKE_SEQ_ERROR ER ’0’= no error ’1’= error 2 Reserved for application specific commands 1 Reserved for manufacturer test mode 0 Description Error in the sequence of the authentication process Clear condition C 20.4.12 SD status register The SD status contains status bits that are related to the SD memory card proprietary features and may be used for future application-specific usage. The size of the SD Status is one data block of 512 bits. The contents of this register are transmitted to the SDIO card host if ACMD13 is sent (CMD55 followed with CMD13). ACMD13 can be sent to a card in transfer state only (card is selected). Table 129 defines the different entries of the SD status register. The type and clear condition fields in the table are abbreviated as follows: Type: ● E: error bit ● S: status bit ● R: detected and set for the actual command response ● X: detected and set during command execution. The SDIO card Host must poll the card by issuing the status command to read these bits Clear condition: ● A: according to the card current state ● B: always related to the previous command. Reception of a valid command clears it (with a delay of one command) ● C: clear by read Table 129. SD status Bits Identifier Type Value 511: 510 DAT_BUS_WIDTH S R ’00’= 1 (default) ‘01’= reserved ‘10’= 4 bit width ‘11’= reserved 509 SECURED_MODE S R ’0’= Not in the mode ’1’= In Secured Mode 508: 496 Reserved Description Clear condition Shows the currently defined databus width that was defined by A SET_BUS_WIDTH command Card is in Secured Mode of operation (refer to the “SD A Security Specification”). 482/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Table 129. SD status (continued) Bits Identifier Type Value Description Clear condition In the future, the 8 LSBs will ’00xxh’= SD Memory Cards as be used to define different defined in Physical Spec Ver1.01- variations of an SD memory 2.00 (’x’= don’t care). The card (each bit will define 495: 480 SD_CARD_TYPE S R following cards are currently different SD types). The 8 A defined: MSBs will be used to define ’0000’= Regular SD RD/WR Card. SD Cards that do not comply ’0001’= SD ROM Card with current SD physical layer specification. 479: 448 SIZE_OF_PROTE CT ED_AREA SR Size of protected area (See below) (See below) A 447: 440 SPEED_CLASS SR Speed Class of the card (See below) (See below) A Performance of move indicated by 439: 432 PERFORMANCE_ MOVE SR 1 [MB/s] step. (See below) A (See below) 431:428 AU_SIZE Size of AU SR (See below) (See below) A 427:424 Reserved 423:408 ERASE_SIZE SR Number of AUs to be erased at a time (See below) A Timeout value for erasing areas 407:402 ERASE_TIMEOUT S R specified by (See below) A UNIT_OF_ERASE_AU 401:400 ERASE_OFFSET SR Fixed offset value added to erase time. (See below) A 399:312 Reserved 311:0 Reserved for Manufacturer SIZE_OF_PROTECTED_AREA Setting this field differs between standard- and high-capacity cards. In the case of a standard-capacity card, the capacity of protected area is calculated as follows: Protected area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN. SIZE_OF_PROTECTED_AREA is specified by the unit in MULT*BLOCK_LEN. In the case of a high-capacity card, the capacity of protected area is specified in this field: Protected area = SIZE_OF_PROTECTED_AREA SIZE_OF_PROTECTED_AREA is specified by the unit in bytes. SPEED_CLASS This 8-bit field indicates the speed class and the value can be calculated by PW/2 (where PW is the write performance). Doc ID 13902 Rev 9 483/995 Secure digital input/output interface (SDIO) RM0008 Table 130. Speed class code field SPEED_CLASS 00h 01h 02h 03h 04h – FFh Class 0 Class 2 Class 4 Class 6 Reserved Value definition PERFORMANCE_MOVE This 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] steps. If the card does not move used RUs (recording units), Pm should be considered as infinity. Setting the field to FFh means infinity. Table 131. Performance move field PERFORMANCE_MOVE 00h Not defined 01h 1 [MB/sec] 02h 02h 2 [MB/sec] --------- --------- FEh 254 [MB/sec] FFh Infinity Value definition AU_SIZE This 4-bit field indicates the AU size and the value can be selected in the power of 2 base from 16 KB. Table 132. AU_SIZE field AU_SIZE 00h 01h 02h 03h 04h 05h 06h 07h 08h Not defined 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB 2 MB Value definition 484/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Table 132. AU_SIZE field AU_SIZE 09h Ah – Fh 4 MB Reserved Value definition The maximum AU size, which depends on the card capacity, is defined in Table 133. The card can be set to any AU size between RU size and maximum AU size. Table 133. Maximum AU size Capacity 16 MB-64 MB Maximum AU Size 512 KB 128 MB-256 MB 512 MB 1 MB 2 MB 1 GB-32 GB 4 MB ERASE_SIZE This 16-bit field indicates NERASE. When NERASE numbers of AUs are erased, the timeout value is specified by ERASE_TIMEOUT (Refer to ERASE_TIMEOUT). The host should determine the proper number of AUs to be erased in one operation so that the host can show the progress of the erase operation. If this field is set to 0, the erase timeout calculation is not supported. Table 134. Erase size field ERASE_SIZE Value definition 0000h 0001h 0002h 0003h --------FFFFh Erase timeout calculation is not supported. 1 AU 2 AU 3 AU --------65535 AU ERASE_TIMEOUT This 6-bit field indicates TERASE and the value indicates the erase timeout from offset when multiple AUs are being erased as specified by ERASE_SIZE. The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the implementation. Determining ERASE_TIMEOUT determines the ERASE_SIZE. Table 135. Erase timeout field ERASE_TIMEOUT Value definition 00 Erase timeout calculation is not supported. 01 1 [sec] 02 2 [sec] 03 3 [sec] Doc ID 13902 Rev 9 485/995 Secure digital input/output interface (SDIO) RM0008 Table 135. Erase timeout field (continued) ERASE_TIMEOUT --------- --------- 63 63 [sec] Value definition ERASE_OFFSET This 2-bit field indicates TOFFSET and one of four values can be selected. This field is meaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 136. Erase offset field ERASE_OFFSET 0h 1h 2h 3h 0 [sec] 1 [sec] 2 [sec] 3 [sec] Value definition 20.4.13 SD I/O mode SD I/O interrupts To allow the SD I/O card to interrupt the MultiMediaCard/SD module, an interrupt function is available on a pin on the SD interface. Pin 8, used as SDIO_D1 when operating in the 4-bit SD mode, signals the cards interrupt to the MultiMediaCard/SD module. The use of the interrupt is optional for each card or function within a card. The SD I/O interrupt is levelsensitive, which means that the interrupt line must be held active (low) until it is either recognized and acted upon by the MultiMediaCard/SD module or deasserted due to the end of the interrupt period. After the MultiMediaCard/SD module has serviced the interrupt, the interrupt status bit is cleared via an I/O write to the appropriate bit in the SD I/O card’s internal registers. The interrupt output of all SD I/O cards is active low and the MultiMediaCard/SD module provides pull-up resistors on all data lines (SDIO_D[3:0]). The MultiMediaCard/SD module samples the level of pin 8 (SDIO_D/IRQ) into the interrupt detector only during the interrupt period. At all other times, the MultiMediaCard/SD module ignores this value. The interrupt period is applicable for both memory and I/O operations. The definition of the interrupt period for operations with single blocks is different from the definition for multipleblock data transfers. SD I/O suspend and resume Within a multifunction SD I/O or a card with both I/O and memory functions, there are multiple devices (I/O and memory) that share access to the MMC/SD bus. To share access to the MMC/SD module among multiple devices, SD I/O and combo cards optionally implement the concept of suspend/resume. When a card supports suspend/resume, the MMC/SD module can temporarily halt a data transfer operation to one function or memory (suspend) to free the bus for a higher-priority transfer to a different function or memory. After this higher-priority transfer is complete, the original transfer is resumed (restarted) where it left off. Support of suspend/resume is optional on a per-card basis. To perform the 486/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) suspend/resume operation on the MMC/SD bus, the MMC/SD module performs the following steps: 1. Determines the function currently using the SDIO_D [3:0] line(s) 2. Requests the lower-priority or slower transaction to suspend 3. Waits for the transaction suspension to complete 4. Begins the higher-priority transaction 5. Waits for the completion of the higher priority transaction 6. Restores the suspended transaction SD I/O ReadWait The optional ReadWait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The ReadWait operation allows the MMC/SD module to signal a card that it is reading multiple registers (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing the MMC/SD module to send commands to any function within the SD I/O device. To determine when a card supports the ReadWait protocol, the MMC/SD module must test capability bits in the internal card registers. The timing for ReadWait is based on the interrupt period. 20.4.14 Commands and responses Application-specific and general commands The SD card host module system is designed to provide a standard interface for a variety of applications types. In this environment, there is a need for specific customer/application features. To implement these features, two types of generic commands are defined in the standard: application-specific commands (ACMD) and general commands (GEN_CMD). When the card receives the APP_CMD (CMD55) command, the card expects the next command to be an application-specific command. ACMDs have the same structure as regular MultiMediaCard commands and can have the same CMD number. The card recognizes it as ACMD because it appears after APP_CMD (CMD55). When the command immediately following the APP_CMD (CMD55) is not a defined application-specific command, the standard command is used. For example, when the card has a definition for SD_STATUS (ACMD13), and receives CMD13 immediately following APP_CMD (CMD55), this is interpreted as SD_STATUS (ACMD13). However, when the card receives CMD7 immediately following APP_CMD (CMD55) and the card does not have a definition for ACMD7, this is interpreted as the standard (SELECT/DESELECT_CARD) CMD7. To use one of the manufacturer-specific ACMDs the SD card Host must perform the following steps: 1. Send APP_CMD (CMD55) The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set and an ACMD is now expected. 2. Send the required ACMD The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set and that the accepted command is interpreted as an ACMD. When a non-ACMD is sent, it is handled by the card as a normal MultiMediaCard command and the APP_CMD bit in the card status register stays clear. When an invalid command is sent (neither ACMD nor CMD) it is handled as a standard MultiMediaCard illegal command error. Doc ID 13902 Rev 9 487/995 Secure digital input/output interface (SDIO) RM0008 The bus transaction for a GEN_CMD is the same as the single-block read or write commands (WRITE_BLOCK, CMD24 or READ_SINGLE_BLOCK,CMD17). In this case, the argument denotes the direction of the data transfer rather than the address, and the data block has vendor-specific format and meaning. The card must be selected (in transfer state) before sending GEN_CMD (CMD56). The data block size is defined by SET_BLOCKLEN (CMD16). The response to GEN_CMD (CMD56) is in R1b format. Command types Both application-specific and general commands are divided into the four following types: ● broadcast command (BC): sent to all cards; no responses returned. ● broadcast command with response (BCR): sent to all cards; responses received from all cards simultaneously. ● addressed (point-to-point) command (AC): sent to the card that is selected; does not include a data transfer on the SDIO_D line(s). ● addressed (point-to-point) data transfer command (ADTC): sent to the card that is selected; includes a data transfer on the SDIO_D line(s). Command formats See Table 121 on page 464 for command formats. Commands for the MultiMediaCard/SD module Table 137. Block-oriented write commands CMD index Type Argument Response format Abbreviation Description CMD23 ac [31:16] set to 0 [15:0] number R1 of blocks SET_BLOCK_COUNT Defines the number of blocks which are going to be transferred in the multiple-block read or write command that follows. CMD24 adtc [31:0] data address R1 WRITE_BLOCK Writes a block of the size selected by the SET_BLOCKLEN command. CMD25 adtc [31:0] data address R1 Continuously writes blocks of data until a STOP_TRANSMISSION WRITE_MULTIPLE_BLOCK follows or the requested number of blocks has been received. CMD26 adtc [31:0] stuff bits R1 PROGRAM_CID CMD27 adtc [31:0] stuff bits R1 PROGRAM_CSD Programming of the card identification register. This command must be issued only once per card. The card contains hardware to prevent this operation after the first programming. Normally this command is reserved for manufacturer. Programming of the programmable bits of the CSD. 488/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Table 138. Block-oriented write protection commands CMD index Type Argument Response format Abbreviation CMD28 ac [31:0] data address R1b SET_WRITE_PROT CMD29 ac [31:0] data address R1b [31:0] write CMD30 adtc protect data R1 address CMD31 Reserved CLR_WRITE_PROT SEND_WRITE_PROT Description If the card has write protection features, this command sets the write protection bit of the addressed group. The properties of write protection are coded in the cardspecific data (WP_GRP_SIZE). If the card provides write protection features, this command clears the write protection bit of the addressed group. If the card provides write protection features, this command asks the card to send the status of the write protection bits. Table 139. Erase commands CMD index Type Argument Response format Abbreviation Description CMD32 ... Reserved. These command indexes cannot be used in order to maintain backward compatibility with older versions of the MultiMediaCard. CMD34 CMD35 ac [31:0] data address R1 Sets the address of the first erase ERASE_GROUP_START group within a range to be selected for erase. CMD36 ac [31:0] data address R1 ERASE_GROUP_END Sets the address of the last erase group within a continuous range to be selected for erase. CMD37 Reserved. This command index cannot be used in order to maintain backward compatibility with older versions of the MultiMediaCards CMD38 ac [31:0] stuff bits R1 ERASE Erases all previously selected write blocks. Table 140. I/O mode commands CMD index Type Argument Response format Abbreviation Description CMD39 ac [31:16] RCA [15:15] register write flag [14:8] register R4 address [7:0] register data FAST_IO Used to write and read 8-bit (register) data fields. The command addresses a card and a register and provides the data for writing if the write flag is set. The R4 response contains data read from the addressed register. This command accesses application-dependent registers that are not defined in the MultiMediaCard standard. Doc ID 13902 Rev 9 489/995 Secure digital input/output interface (SDIO) RM0008 Table 140. I/O mode commands (continued) CMD index Type Argument Response format Abbreviation Description CMD40 bcr [31:0] stuff bits R5 CMD41 Reserved GO_IRQ_STATE Places the system in the interrupt mode. Table 141. Lock card CMD index Type Argument Response format Abbreviation CMD42 adtc [31:0] stuff bits R1b CMD43 ... Reserved CMD54 LOCK_UNLOCK Description Sets/resets the password or locks/unlocks the card. The size of the data block is set by the SET_BLOCK_LEN command. Table 142. Application-specific commands CMD index Type Argument Response format Abbreviation Description CMD55 ac [31:16] RCA R1 [15:0] stuff bits APP_CMD Indicates to the card that the next command bits is an application specific command rather than a standard command [31:1] stuff bits CMD56 adtc [0]: RD/WR Used either to transfer a data block to the card or to get a data block from the card for general purpose/application-specific commands. The size of the data block shall be set by the SET_BLOCK_LEN command. CMD57 ... CMD59 CMD60 ... CMD63 Reserved. Reserved for manufacturer. 20.5 Response formats All responses are sent via the MCCMD command line SDIO_CMD. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depends on the response type. A response always starts with a start bit (always 0), followed by the bit indicating the direction of transmission (card = 0). A value denoted by x in the tables below indicates a variable entry. All responses, except for the R3 response type, are protected by a CRC. Every command code word is terminated by the end bit (always 1). There are five types of responses. Their formats are defined as follows: 490/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 20.5.1 R1 (normal response command) Code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). The status of the card is coded in 32 bits. Table 143. R1 response Bit position Width (bits 47 1 0 46 1 0 [45:40] 6 X [39:8] 32 X [7:1] 7 X 0 1 1 Value Description Start bit Transmission bit Command index Card status CRC7 End bit 20.5.2 20.5.3 R1b It is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands based on its state prior to the command reception. R2 (CID, CSD register) Code length = 136 bits. The contents of the CID register are sent as a response to the CMD2 and CMD10 commands. The contents of the CSD register are sent as a response to CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response. The card indicates that an erase is in progress by holding MCDAT low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card. Table 144. R2 response Bit position Width (bits 135 1 134 1 [133:128] 6 [127:1] 127 0 1 Value 0 0 ‘111111’ X 1 Description Start bit Transmission bit Command index Card status End bit 20.5.4 R3 (OCR register) Code length: 48 bits. The contents of the OCR register are sent as a response to CMD1. The level coding is as follows: restricted voltage windows = low, card busy = low. Doc ID 13902 Rev 9 491/995 Secure digital input/output interface (SDIO) RM0008 Table 145. R3 response Bit position Width (bits 47 1 46 1 [45:40] 6 [39:8] 32 [7:1] 7 0 1 Value 0 0 ‘111111’ X ‘1111111’ 1 Description Start bit Transmission bit Reserved OCR register Reserved End bit 20.5.5 R4 (Fast I/O) Code length: 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its content. Table 146. R4 response Bit position 47 46 [45:40] [31:16] [39:8] Argument field [15:8] [7:0] [7:1] 0 Width (bits 1 1 6 16 8 8 7 1 Value 0 0 ‘111111’ X X X ‘1111111’ 1 Description Start bit Transmission bit Reserved RCA register address read register contents CRC7 End bit 20.5.6 R4b For SD I/O only: an SDIO card receiving the CMD5 will respond with a unique SDIO response R4. The format is: Table 147. R4b response Bit position Width (bits 47 1 0 46 1 0 [45:40] 6 x 39 16 X [38:36] 3 X [39:8] Argument field 35 1 X [34:32] 3 X [31:8] 24 X Value Description Start bit Transmission bit Reserved Card is ready Number of I/O functions Present memory Stuff bits I/O ORC 492/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Table 147. R4b response (continued) Bit position Width (bits [7:1] 7 X 0 1 1 Value Description Reserved End bit 20.5.7 Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands. This I/O enable of the function within the I/O card will remain set until a reset, power cycle or CMD52 with write to I/O reset is received by the card. Note that an SD memory-only card may respond to a CMD5. The proper response for a memory-only card would be Present memory = 1 and Number of I/O functions = 0. A memory-only card built to meet the SD Memory Card specification version 1.0 would detect the CMD5 as an illegal command and not respond. The I/O aware host will send CMD5. If the card responds with response R4, the host determines the card’s configuration based on the data contained within the R4 response. R5 (interrupt request) Only for MultiMediaCard. Code length: 48 bits. If the response is generated by the host, the RCA field in the argument will be 0x0. Table 148. R5 response Bit position 47 46 [45:40] Width (bits 1 1 6 Value 0 0 ‘111111’ [31:16] 16 X [39:8] Argument field [15:0] 16 X [7:1] 7 X 0 1 1 Description Start bit Transmission bit CMD40 RCA [31:16] of winning card or of the host Not defined. May be used for IRQ data CRC7 End bit 20.5.8 R6 Only for SD I/O. The normal response to CMD3 by a memory device. It is shown in Table 149. Table 149. R6 response Bit position Width (bits) Value Description 47 46 [45:40] 1 0 Start bit 1 0 Transmission bit 6 ‘101000’ CMD40 Doc ID 13902 Rev 9 493/995 Secure digital input/output interface (SDIO) RM0008 Table 149. R6 response (continued) Bit position Width (bits) Value Description [39:8] Argument field [31:16] 16 [15:0] 16 X RCA [31:16] of winning card or of the host X Not defined. May be used for IRQ data [7:1] 7 X CRC7 0 1 1 End bit The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case, the 16 bits of response are the SD I/O-only values: ● Bit [15] COM_CRC_ERROR ● Bit [14] ILLEGAL_COMMAND ● Bit [13] ERROR ● Bits [12:0] Reserved 20.6 20.6.1 20.6.2 SDIO I/O card-specific operations The following features are SD I/O-specific operations: ● SDIO read wait operation by SDIO_D2 signalling ● SDIO read wait operation by stopping the clock ● SDIO suspend/resume operation (write and read suspend) ● SDIO interrupts The SDIO supports these operations only if the SDIO_DCTRL[11] bit is set, except for read suspend that does not need specific hardware implementation. SDIO I/O read wait operation by SDIO_D2 signalling It is possible to start the readwait interval before the first block is received: when the data path is enabled (SDIO_DCTRL[0] bit set), the SDIO-specific operation is enabled (SDIO_DCTRL[11] bit set), read wait starts (SDI0_DCTRL[10] =0 and SDI_DCTRL[8] =1) and data direction is from card to SDIO (SDIO_DCTRL[1] = 1), the DPSM directly moves from Idle to Readwait. In Readwait the DPSM drives SDIO_D2 to 0 after 2 SDIO_CK clock cycles. In this state, when you set the RWSTOP bit (SDIO_DCTRL[9]), the DPSM remains in Wait for two more SDIO_CK clock cycles to drive SDIO_D2 to 1 for one clock cycle (in accordance with SDIO specification). The DPSM then starts waiting again until it receives data from the card. The DPSM will not start a readwait interval while receiving a block even if read wait start is set: the readwait interval will start after the CRC is received. The RWSTOP bit has to be cleared to start a new read wait operation. During the readwait interval, the SDIO can detect SDIO interrupts on SDIO_D1. SDIO read wait operation by stopping SDIO_CK If the SDIO card does not support the previous read wait method, the SDIO can perform a read wait by stopping SDIO_CK (SDIO_DCTRL is set just like in the method presented in Section 20.6.1, but SDIO_DCTRL[10] =1): DSPM stops the clock two SDIO_CK cycles after the end bit of the current received block and starts the clock again after the read wait start bit is set. 494/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 20.6.3 20.6.4 As SDIO_CK is stopped, any command can be issued to the card. During a read/wait interval, the SDIO can detect SDIO interrupts on SDIO_D1. SDIO suspend/resume operation While sending data to the card, the SDIO can suspend the write operation. the SDIO_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend command. The CPSM analyzes the response and when the ACK is received from the card (suspend accepted), it acknowledges the DPSM that goes Idle after receiving the CRC token of the current block. The hardware does not save the number of the remaining block to be sent to complete the suspended operation (resume). The write operation can be suspended by software, just by disabling the DPSM (SDIO_DCTRL[0] =0) when the ACK of the suspend command is received from the card. The DPSM enters then the Idle state. To suspend a read: the DPSM waits in the Wait_r state as the function to be suspended sends a complete packet just before stopping the data transaction. The application continues reading RxFIFO until the FIF0 is empty, and the DPSM goes Idle automatically. SDIO interrupts SDIO interrupts are detected on the SDIO_D1 line once the SDIO_DCTRL[11] bit is set. 20.7 20.7.1 20.7.2 CE-ATA specific operations The following features are CE-ATA specific operations: ● sending the command completion signal disable to the CE-ATA device ● receiving the command completion signal from the CE-ATA device ● signaling the completion of the CE-ATA command to the CPU, using the status bit and/or interrupt. The SDIO supports these operations only for the CE-ATA CMD61 command, that is, if SDIO_CMD[14] is set. Command completion signal disable Command completion signal disable is sent 8 bit cycles after the reception of a short response if the ‘enable CMD completion’ bit, SDIO_CMD[12], is not set and the ‘not interrupt Enable’ bit, SDIO_CMD[13], is set. The CPSM enters the Pend state, loading the command shift register with the disable sequence “00001” and, the command counter with 43. Eight cycles after, a trigger moves the CPSM to the Send state. When the command counter reaches 48, the CPSM becomes Idle as no response is awaited. Command completion signal enable If the ‘enable CMD completion’ bit SDIO_CMD[12] is set and the ‘not interrupt Enable’ bit SDIO_CMD[13] is set, the CPSM waits for the command completion signal in the Waitcpl state. Doc ID 13902 Rev 9 495/995 Secure digital input/output interface (SDIO) RM0008 20.7.3 20.7.4 When ‘0’ is received on the CMD line, the CPSM enters the Idle state. No new command can be sent for 7 bit cycles. Then, for the last 5 cycles (out of the 7) the CMD line is driven to ‘1’ in push-pull mode. CE-ATA interrupt The command completion is signaled to the CPU by the status bit SDIO_STA[23]. This static bit can be cleared with the clear bit SDIO_ICR[23]. The SDIO_STA[23] status bit can generate an interrupt on each interrupt line, depending on the mask bit SDIO_MASKx[23]. Aborting CMD61 If the command completion disable signal has not been sent and CMD61 needs to be aborted, the command state machine must be disabled. It then becomes Idle, and the CMD12 command can be sent. No command completion disable signal is sent during the operation. 20.8 HW flow control The HW flow control functionality is used to avoid FIFO underrun (TX mode) and overrun (RX mode) errors. The behavior is to stop SDIO_CK and freeze SDIO state machines. The data transfer is stalled while the FIFO is unable to transmit or receive data. Only state machines clocked by SDIOCLK are frozen, the AHB interface is still alive. The FIFO can thus be filled or emptied even if flow control is activated. To enable HW flow control, the SDIO_CLKCR[14] register bit must be set to 1. After reset Flow Control is disabled. 20.9 SDIO registers The device communicates to the system via 32-bit-wide control registers accessible via AHB. 496/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 20.9.1 SDIO power control register (SDIO_POWER) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PWRC TRL rw rw Bits 31:2 Reserved, always read as 0. [1:0] PWRCTRL: Power supply control bits. These bits are used to define the current functional state of the card clock: 00: Power-off: the clock to card is stopped. 01: Reserved 10: Reserved power-up 11: Power-on: the card is clocked. Note: 20.9.2 After a data write, data cannot be written to this register for seven HCLK clock periods. SDI clock control register (SDIO_CLKCR) Address offset: 0x04 Reset value: 0x0000 0000 The SDIO_CLKCR register controls the SDIO_CK output clock. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HWFC_EN NEGEDGE BYPASS PWRSAV CLKEN Reserved WID BUS CLKDIV rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:15 Reserved, always read as 0. Bit 14 HWFC_EN: HW Flow Control enable 0b: HW Flow Control is disabled 1b: HW Flow Control is enabled When HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt signals, please see SDIO Status register definition in Section 20.9.11. Bit 13 NEGEDGE:SDIO_CK dephasing selection bit 0b: SDIO_CK generated on the rising edge of the master clock SDIOCLK 1b: SDIO_CK generated on the falling edge of the master clock SDIOCLK Bits 12:11 WIDBUS: Wide bus mode enable bit 00: Default bus mode: SDIO_D0 used 01: 4-wide bus mode: SDIO_D[3:0] used 10: 8-wide bus mode: SDIO_D[7:0] used Doc ID 13902 Rev 9 497/995 Secure digital input/output interface (SDIO) RM0008 Bit 10 BYPASS: Clock divider bypass enable bit 0: Disable bypass: SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal. 1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal. Bit 9 PWRSAV: Power saving configuration bit For power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting PWRSAV: 0: SDIO_CK clock is always enabled 1: SDIO_CK is only enabled when the bus is active Bit 8 CLKEN: Clock enable bit 0: SDIO_CK is disabled 1: SDIO_CK is enabled Bits 7:0 CLKDIV: Clock divide factor This field defines the divide factor between the input clock (SDIOCLK) and the output clock (SDIO_CK): SDIO_CK frequency = SDIOCLK / [CLKDIV + 2]. Note: 1 While the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK frequency must be less than 400 kHz. 2 The clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards. 3 After a data write, data cannot be written to this register for seven HCLK clock periods. SDIO_CK can also be stopped during the read wait interval for SD I/O cards: in this case the SDIO_CLKCR register does not control SDIO_CK. 20.9.3 SDIO argument register (SDIO_ARG) Address offset: 0x08 Reset value: 0x0000 0000 The SDIO_ARG register contains a 32-bit command argument, which is sent to a card as part of a command message. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMDARG rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 CMDARG: Command argument Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. 498/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 20.9.4 SDIO command register (SDIO_CMD) Address offset: 0x0C Reset value: 0x0000 0000 The SDIO_CMD register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CE-ATACMD nIEN ENCMDcompl SDIOSuspend CPSMEN WAITPEND WAITINT WAITRESP CMDINDEX Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:15 Reserved, always read as 0. Bit 14 ATACMD: CE-ATA command If ATACMD is set, the CPSM transfers CMD61. Bit 13 nIEN: not Interrupt Enable if this bit is 0, interrupts in the CE-ATA device are enabled. Bit 12 ENCMDcompl: Enable CMD completion If this bit is set, the command completion signal is enabled. Bit 11 SDIOSuspend: SD I/O suspend command If this bit is set, the command to be sent is a suspend command (to be used only with SDIO card). Bit 10 CPSMEN: Command path state machine (CPSM) Enable bit If this bit is set, the CPSM is enabled. Bit 9 WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal). If this bit is set, the CPSM waits for the end of data transfer before it starts sending a command. Bit 8 WAITINT: CPSM waits for interrupt request If this bit is set, the CPSM disables command timeout and waits for an interrupt request. Bits 7:6 WAITRESP: Wait for response bits They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 00: No response, expect CMDSENT flag 01: Short response, expect CMDREND or CCRCFAIL flag 10: No response, expect CMDSENT flag 11: Long response, expect CMDREND or CCRCFAIL flag Bit 5:0 CMDINDEX: Command index The command index is sent to the card as part of a command message. Note: 1 After a data write, data cannot be written to this register for seven HCLK clock periods. 2 MultiMediaCards can send two kinds of response: short responses, 48 bits long, or long responses,136 bits long. SD card and SD I/O card can send only short responses, the Doc ID 13902 Rev 9 499/995 Secure digital input/output interface (SDIO) RM0008 20.9.5 argument can vary according to the type of response: the software will distinguish the type of response according to the sent command. CE-ATA devices send only short responses. SDIO command response register (SDIO_RESPCMD) Address offset: 0x10 Reset value: 0x0000 0000 The SDIO_RESPCMD register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RESPCMD rrrrrr Bits 31:6 Reserved, always read as 0. Bits 5:0 RESPCMD: Response command index Read-only bit field. Contains the command index of the last command response received. 20.9.6 SDIO response 1..4 register (SDIO_RESPx) Address offset: (0x10 + (4 × x)); x = 1..4 Reset value: 0x0000 0000 The SDIO_RESP1/2/3/4 registers contain the status of a card, which is part of the received response. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARDSTATUSx rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr Bits 31:0 CARDSTATUSx: see Table 150. The Card Status size is 32 or 127 bits, depending on the response type. Table 150. Response type and SDIO_RESPx registers Register Short response Long response SDIO_RESP1 Card Status[31:0] Card Status [127:96] SDIO_RESP2 Unused Card Status [95:64] SDIO_RESP3 Unused Card Status [63:32] SDIO_RESP4 Unused Card Status [31:1]0b The most significant bit of the card status is received first. The SDIO_RESP3 register LSB is always 0b. 500/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 20.9.7 SDIO data timer register (SDIO_DTIMER) Address offset: 0x24 Reset value: 0x0000 0000 The SDIO_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDIO_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATATIME rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 DATATIME: Data timeout period Data timeout period expressed in card bus clock periods. Note: 20.9.8 A data transfer must be written to the data timer register and the data length register before being written to the data control register. SDIO data length register (SDIO_DLEN) Address offset: 0x28 Reset value: 0x0000 0000 The SDIO_DLEN register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATALENGTH rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:25 Reserved, always read as 0. Bits 24:0 DATALENGTH: Data length value Number of data bytes to be transferred. Note: For a block data transfer, the value in the data length register must be a multiple of the block size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the data length register before being written to the data control register. Doc ID 13902 Rev 9 501/995 Secure digital input/output interface (SDIO) RM0008 20.9.9 SDIO data control register (SDIO_DCTRL) Address offset: 0x2C Reset value: 0x0000 0000 The SDIO_DCTRL register control the data path state machine (DPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDIOEN RWMOD RWSTOP RWSTART DMAEN DTMODE DTDIR DTEN Reserved DBLOCKSIZE rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, always read as 0. Bit 11 SDIOEN: SD I/O enable functions If this bit is set, the DPSM performs an SD I/O-card-specific operation. Bit 10 RWMOD: Read wait mode 0: Read Wait control stopping SDIO_CK 1: Read Wait control using SDIO_D2 Bit 9 RWSTOP: Read wait stop 0: Read wait in progress if RWSTART bit is set 1: Enable for read wait stop if RWSTART bit is set Bit 8 RWSTART: Read wait start If this bit is set, read wait operation starts. Bits 7:4 DBLOCKSIZE: Data block size Define the data block length when the block data transfer mode is selected: 0000: (0 decimal) lock length = 20 = 1 byte 0001: (1 decimal) lock length = 21 = 2 bytes 0010: (2 decimal) lock length = 22 = 4 bytes 0011: (3 decimal) lock length = 23 = 8 bytes 0100: (4 decimal) lock length = 24 = 16 bytes 0101: (5 decimal) lock length = 25 = 32 bytes 0110: (6 decimal) lock length = 26 = 64 bytes 0111: (7 decimal) lock length = 27 = 128 bytes 1000: (8 decimal) lock length = 28 = 256 bytes 1001: (9 decimal) lock length = 29 = 512 bytes 1010: (10 decimal) lock length = 210 = 1024 bytes 1011: (11 decimal) lock length = 211 = 2048 bytes 1100: (12 decimal) lock length = 212 = 4096 bytes 1101: (13 decimal) lock length = 213 = 8192 bytes 1110: (14 decimal) lock length = 214 = 16384 bytes 1111: (15 decimal) reserved Bit 3 DMAEN: DMA enable bit 0: DMA disabled. 1: DMA enabled. 502/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Bit 2 DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer. 0: Block data transfer. 1: Stream data transfer. Bit 1 DTDIR: Data transfer direction selection 0: From controller to card. 1: From card to controller. [0] DTEN: Data transfer enabled bit Data transfer starts if 1b is written to the DTEN bit. Depending on the direction bit, DTDIR, the DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at the beginning of the transfer. It is not necessary to clear the enable bit after the end of a data transfer but the SDIO_DCTRL must be updated to enable a new data transfer Note: After a data write, data cannot be written to this register for seven HCLK clock periods. 20.9.10 SDIO data counter register (SDIO_DCOUNT) Address offset: 0x30 Reset value: 0x0000 0000 The SDIO_DCOUNT register loads the value from the data length register (see SDIO_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and the data status end flag, DATAEND, is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATACOUNT rrrrrrrrrrrrrrrrrrrrrrrrr Bits 31:25 Reserved, always read as 0. Bits 24:0 DATACOUNT: Data count value When this bit is read, the number of remaining data bytes to be transferred is returned. Write has no effect. Note: This register should be read only when the data transfer is complete. Doc ID 13902 Rev 9 503/995 Secure digital input/output interface (SDIO) RM0008 20.9.11 SDIO status register (SDIO_STA) Address offset: 0x34 Reset value: 0x0000 0000 The SDIO_STA register is a read-only register. It contains two types of flag: ● Static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by writing to the SDIO Interrupt Clear register (see SDIO_ICR) ● Dynamic flags (bits [21:11]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and deasserted as data while written to the FIFO) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CEATAEND SDIOIT RXDAVL TXDAVL RXFIFOE TXFIFOE RXFIFOF TXFIFOF RXFIFOHF TXFIFOHE RXACT TXACT CMDACT DBCKEND STBITERR DATAEND CMDSENT CMDREND RXOVERR TXUNDERR DTIMEOUT CTIMEOUT DCRCFAIL CCRCFAIL Res. rrrrrrrrrrrrrrrrrrrrrrrr Bits 31:24 Reserved, always read as 0. Bit 23 CEATAEND: CE-ATA command completion signal received for CMD61 Bit 22 SDIOIT: SDIO interrupt received Bit 21 RXDAVL: Data available in receive FIFO Bit 20 TXDAVL: Data available in transmit FIFO Bit 19 RXFIFOE: Receive FIFO empty Bit 18 TXFIFOE: Transmit FIFO empty When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words. Bit 17 RXFIFOF: Receive FIFO full When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full. Bit 16 TXFIFOF: Transmit FIFO full Bit 15 RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO Bit 14 TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into the FIFO Bit 13 RXACT: Data receive in progress Bit 12 TXACT: Data transmit in progress Bit 11 CMDACT: Command transfer in progress Bit 10 DBCKEND: Data block sent/received (CRC check passed) Bit 9 STBITERR: Start bit not detected on all data signals in wide bus mode Bit 8 DATAEND: Data end (data counter, SDIDCOUNT, is zero) Bit 7 CMDSENT: Command sent (no response required) Bit 6 CMDREND: Command response received (CRC check passed) Bit 5 RXOVERR: Received FIFO overrun error 504/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Bit 4 TXUNDERR: Transmit FIFO underrun error Bit 3 DTIMEOUT: Data timeout Bit 2 CTIMEOUT: Command response timeout The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods. Bit 1 DCRCFAIL: Data block sent/received (CRC check failed) Bit 0 CCRCFAIL: Command response received (CRC check failed) 20.9.12 SDIO interrupt clear register (SDIO_ICR) Address offset: 0x38 Reset value: 0x0000 0000 The SDIO_ICR register is a write-only register. Writing a bit with 1b clears the corresponding bit in the SDIO_STA Status register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CEATAENDC SDIOITC DBCKENDC STBITERRC DATAENDC CMDSENTC CMDRENDC RXOVERRC TXUNDERRC DTIMEOUTC CTIMEOUTC DCRCFAILC CCRCFAILC Reserved rw rw Reserved Bits 31:24 Reserved, always read as 0. Bit 23 CEATAENDC: CEATAEND flag clear bit Set by software to clear the CEATAEND flag. 0: CEATAEND not cleared 1: CEATAEND cleared Bit 22 SDIOITC: SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 0: SDIOIT not cleared 1: SDIOIT cleared Bits 21:11 Reserved, always read as 0. Bit 10 DBCKENDC: DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 0: DBCKEND not cleared 1: DBCKEND cleared Bit 9 STBITERRC: STBITERR flag clear bit Set by software to clear the STBITERR flag. 0: STBITERR not cleared 1: STBITERR cleared Bit 8 DATAENDC: DATAEND flag clear bit Set by software to clear the DATAEND flag. 0: DATAEND not cleared 1: DATAEND cleared rw rw rw rw rw rw rw rw rw rw rw Doc ID 13902 Rev 9 505/995 Secure digital input/output interface (SDIO) Bit 7 CMDSENTC: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 0: CMDSENT not cleared 1: CMDSENT cleared Bit 6 CMDRENDC: CMDREND flag clear bit Set by software to clear the CMDREND flag. 0: CMDREND not cleared 1: CMDREND cleared Bit 5 RXOVERRC: RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 0: RXOVERR not cleared 1: RXOVERR cleared Bit 4 TXUNDERRC: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 0: TXUNDERR not cleared 1: TXUNDERR cleared Bit 3 DTIMEOUTC: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 0: DTIMEOUT not cleared 1: DTIMEOUT cleared Bit 2 CTIMEOUTC: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 0: CTIMEOUT not cleared 1: CTIMEOUT cleared Bit 1 DCRCFAILC: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 0: DCRCFAIL not cleared 1: DCRCFAIL cleared Bit 0 CCRCFAILC: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0: CCRCFAIL not cleared 1: CCRCFAIL cleared RM0008 506/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) 20.9.13 SDIO mask register (SDIO_MASK) Address offset: 0x3C Reset value: 0x0000 0000 The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CEATAENDIE SDIOITIE RXDAVLIE TXDAVLIE RXFIFOEIE TXFIFOEIE RXFIFOFIE TXFIFOFIE RXFIFOHFIE TXFIFOHEIE RXACTIE TXACTIE CMDACTIE DBCKENDIE STBITERRIE DATAENDIE CMDSENTIE CMDRENDIE RXOVERRIE TXUNDERRIE DTIMEOUTIE CTIMEOUTIE DCRCFAILIE CCRCFAILIE Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, always read as 0. Bit 23 CEATAENDIE: CE-ATA command completion signal received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the CE-ATA command completion signal. 0: CE-ATA command completion signal received interrupt disabled 1: CE-ATA command completion signal received interrupt enabled Bit 22 SDIOITIE: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 0: SDIO Mode Interrupt Received interrupt disabled 1: SDIO Mode Interrupt Received interrupt enabled Bit 21 RXDAVLIE: Data available in Rx FIFO interrupt enable Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Rx FIFO. 0: Data available in Rx FIFO interrupt disabled 1: Data available in Rx FIFO interrupt enabled Bit 20 TXDAVLIE: Data available in Tx FIFO interrupt enable Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Tx FIFO. 0: Data available in Tx FIFO interrupt disabled 1: Data available in Tx FIFO interrupt enabled Bit 19 RXFIFOEIE: Rx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO empty. 0: Rx FIFO empty interrupt disabled 1: Rx FIFO empty interrupt enabled Bit 18 TXFIFOEIE: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 0: Tx FIFO empty interrupt disabled 1: Tx FIFO empty interrupt enabled Bit 17 RXFIFOFIE: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 0: Rx FIFO full interrupt disabled 1: Rx FIFO full interrupt enabled Doc ID 13902 Rev 9 507/995 Secure digital input/output interface (SDIO) RM0008 Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO full. 0: Tx FIFO full interrupt disabled 1: Tx FIFO full interrupt enabled Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 0: Rx FIFO half full interrupt disabled 1: Rx FIFO half full interrupt enabled Bit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 0: Tx FIFO half empty interrupt disabled 1: Tx FIFO half empty interrupt enabled Bit 13 RXACTIE: Data receive acting interrupt enable Set and cleared by software to enable/disable interrupt caused by data being received (data receive acting). 0: Data receive acting interrupt disabled 1: Data receive acting interrupt enabled Bit 12 TXACTIE: Data transmit acting interrupt enable Set and cleared by software to enable/disable interrupt caused by data being transferred (data transmit acting). 0: Data transmit acting interrupt disabled 1: Data transmit acting interrupt enabled Bit 11 CMDACTIE: Command acting interrupt enable Set and cleared by software to enable/disable interrupt caused by a command being transferred (command acting). 0: Command acting interrupt disabled 1: Command acting interrupt enabled Bit 10 DBCKENDIE: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 0: Data block end interrupt disabled 1: Data block end interrupt enabled Bit 9 STBITERRIE: Start bit error interrupt enable Set and cleared by software to enable/disable interrupt caused by start bit error. 0: Start bit error interrupt disabled 1: Start bit error interrupt enabled Bit 8 DATAENDIE: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 0: Data end interrupt disabled 1: Data end interrupt enabled Bit 7 CMDSENTIE: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 0: Command sent interrupt disabled 1: Command sent interrupt enabled 508/995 Doc ID 13902 Rev 9 RM0008 Secure digital input/output interface (SDIO) Bit 6 CMDRENDIE: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 0: Command response received interrupt disabled 1: command Response Received interrupt enabled Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 0: Rx FIFO overrun error interrupt disabled 1: Rx FIFO overrun error interrupt enabled Bit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 0: Tx FIFO underrun error interrupt disabled 1: Tx FIFO underrun error interrupt enabled Bit 3 DTIMEOUTIE: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 0: Data timeout interrupt disabled 1: Data timeout interrupt enabled Bit 2 CTIMEOUTIE: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 0: Command timeout interrupt disabled 1: Command timeout interrupt enabled Bit 1 DCRCFAILIE: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 0: Data CRC fail interrupt disabled 1: Data CRC fail interrupt enabled Bit 0 CCRCFAILIE: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0: Command CRC fail interrupt disabled 1: Command CRC fail interrupt enabled 20.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) Address offset: 0x48 Reset value: 0x0000 0000 The SDIO_FIFOCNT register contains the remaining number of words to be written to or read from the FIFO. The FIFO counter loads the value from the data length register (see SDIO_DLEN) when the data transfer enable bit, DTEN, is set in the data control register (SDIO_DCTRL register) and the DPSM is at the Idle state. If the data length is not wordaligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFOCOUNT rrrrrrrrrrrrrrrrrrrrrrrr Bits 31:24 Reserved, always read as 0. Bits 23:0 FIFOCOUNT: Remaining number of words to be written to or read from the FIFO. Doc ID 13902 Rev 9 509/995 Secure digital input/output interface (SDIO) RM0008 20.9.15 SDIO data FIFO register (SDIO_FIFO) Address offset: 0x80 Reset value: 0x0000 0000 The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIF0Data rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 FIFOData: Receive and transmit FIFO data The FIFO data occupies 32 entries of 32-bit words, from address: SDIO base + 0x080 to SDIO base + 0xFC. 20.9.16 SDIO register map The following table summarizes the SDIO registers. Table 151. SDIO register map Offset Register 0x00 SDIO_POWER 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved 17 16 CLKDIV CLKEN PWRSAV BYPASS WIDBUS NEGEDGE HWFC_EN Reserved 0x04 SDIO_CLKCR 0x08 SDIO_ARG 0x0C SDIO_CMD 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 SDIO_RESPCM D SDIO_RESP1 SDIO_RESP2 SDIO_RESP3 SDIO_RESP4 SDIO_DTIMER SDIO_DLEN 0x2C SDIO_DCTRL 0x30 SDIO_DCOUNT 0x34 SDIO_STA Reserved Reserved Reserved CE-ATACMD nIEN ENCMDcompl SDIOSuspend CPSMEN WAITPEND WAITINT WAITRESP CMDINDEX CMDARG Reserved CARDSTATUS1 CARDSTATUS2 CARDSTATUS3 CARDSTATUS4 DATATIME DATALENGTH DATACOUNT RESPCMD Reserved SDIOEN RWMOD RWSTOP RWSTART DBLOCKSIZE DMAEN DTMODE DTDIR DTEN PWRCTRL 1 0 CEATAEND SDIOIT RXDAVL TXDAVL RXFIFOE TXFIFOE RXFIFOF TXFIFOF RXFIFOHF TXFIFOHE RXACT TXACT CMDACT DBCKEND STBITERR DATAEND CMDSENT CMDREND RXOVERR TXUNDERR DTIMEOUT CTIMEOUT DCRCFAIL CCRCFAIL Reserved 510/995 Doc ID 13902 Rev 9 RM0008 Table 151. SDIO register map (continued) Offset Register 0x38 SDIO_ICR 0x3C SDIO_MASK 0x48 SDIO_FIFOCNT 0x80 SDIO_FIFO Note: Reserved Refer to Table 1 on page 41 for the register boundary addresses. 31 30 29 Reserved Reserved 28 27 26 25 24 CEATAENDIE CEATAENDC 23 SDIOITIE SDIOITC 22 Doc ID 13902 Rev 9 RXDAVLIE 21 TXDAVLIE 20 RXFIFOEIE 19 TXFIFOEIE 18 Secure digital input/output interface (SDIO) FIFOCOUNT FIF0Data RXFIFOFIE TXFIFOFIE 17 Reserved 16 RXFIFOHFIE 15 TXFIFOHEIE 14 RXACTIE 13 TXACTIE 12 CMDACTIE 11 DBCKENDIE DBCKENDC 10 STBITERRIE STBITERRC 9 DATAENDIE DATAENDC 8 CMDSENTIE CMDSENTC 7 CMDRENDIE CMDRENDC 6 RXOVERRIE RXOVERRC 5 TXUNDERRIE TXUNDERRC 4 DTIMEOUTIE DTIMEOUTC 3 511/995 CTIMEOUTIE CTIMEOUTC 2 DCRCFAILIE DCRCFAILC 1 CCRCFAILIE CCRCFAILC 0 Universal serial bus full-speed device interface (USB) RM0008 21 Universal serial bus full-speed device interface (USB) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the STM32F103xx performance line and STM32F102xx USB access line families only. 21.1 USB introduction The USB peripheral implements an interface between a full-speed USB 2.0 bus and the APB1 bus. USB suspend/resume are supported which allows to stop the device clocks for low-power consumption. 21.2 Note: USB main features ● USB specification version 2.0 full-speed compliant ● Configurable number of endpoints from 1 to 8 ● Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted (NRZI) encoding/decoding and bit-stuffing ● Isochronous transfers support ● Double-buffered bulk/isochronous endpoint support ● USB Suspend/Resume operations ● Frame locked clock pulse generation The USB and CAN share a dedicated 512-byte SRAM memory for data transmission and reception, and so they cannot be used concurrently (the shared SRAM is accessed through CAN and USB exclusively). The USB and CAN can be used in the same application but not at the same time. 21.3 USB functional description Figure 190 shows the block diagram of the USB peripheral. 512/995 Doc ID 13902 Rev 9 RM0008 Universal serial bus full-speed device interface (USB) Figure 190. USB peripheral block diagram DP DM Analog transceiver USB clock (48 MHz) PCLK1 USB Suspend timer Packet buffer interface RX-TX Control S.I.E. Clock recovery Endpoint selection Endpoint registers Control registers & logic Interrupt registers & logic Endpoint registers Arbiter Packet buffer memory Register mapper Interrupt mapper APB1 wrapper APB1 interface PCLK1 APB1 bus IRQs to NVIC The USB peripheral provides an USB compliant connection between the host PC and the function implemented by the microcontroller. Data transfer between the host PC and the system memory occurs through a dedicated packet buffer memory accessed directly by the USB peripheral. The size of this dedicated buffer memory must be according to the number of endpoints used and the maximum packet size. This dedicated memory is sized to 512 bytes and up to 16 mono-directional or 8 bidirectional endpoints can be used.The USB peripheral interfaces with the USB host, detecting token packets, handling data transmission/reception, and processing handshake packets as required by the USB standard. Transaction formatting is performed by the hardware, including CRC generation and checking. Each endpoint is associated with a buffer description block indicating where the endpoint related memory area is located, how large it is or how many bytes must be transmitted. When a token for a valid function/endpoint pair is recognized by the USB peripheral, the related data transfer (if required and if the endpoint is configured) takes place. The data buffered by the USB peripheral is loaded in an internal 16 bit register and memory access to the dedicated buffer is performed. When all the data has been transferred, if needed, the Doc ID 13902 Rev 9 513/995 Universal serial bus full-speed device interface (USB) RM0008 21.3.1 proper handshake packet over the USB is generated or expected according to the direction of the transfer. At the end of the transaction, an endpoint-specific interrupt is generated, reading status registers and/or using different interrupt response routines. The microcontroller can determine: ● Which endpoint has to be served ● Which type of transaction took place, if errors occurred (bit stuffing, format, CRC, protocol, missing ACK, over/underrun, etc.) Special support is offered to Isochronous transfers and high throughput bulk transfers, implementing a double buffer usage, which allows to always have an available buffer for the USB peripheral while the microcontroller uses the other one. The unit can be placed in low-power mode (SUSPEND mode), by writing in the control register, whenever required. At this time, all static power dissipation is avoided, and the USB clock can be slowed down or stopped. The detection of activity at the USB inputs, while in low-power mode, wakes the device up asynchronously. A special interrupt source can be connected directly to a wakeup line to allow the system to immediately restart the normal clock generation and/or support direct clock start/stop. Description of USB blocks The USB peripheral implements all the features related to USB interfacing, which include the following blocks: ● Serial Interface Engine (SIE): The functions of this block include: synchronization pattern recognition, bit-stuffing, CRC generation and checking, PID verification/generation, and handshake evaluation. It must interface with the USB transceivers and uses the virtual buffers provided by the packet buffer interface for local data storage,. This unit also generates signals according to USB peripheral events, such as Start of Frame (SOF), USB_Reset, Data errors etc. and to Endpoint related events like end of transmission or correct reception of a packet; these signals are then used to generate interrupts. ● Timer: This block generat