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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER D Low Supply-Voltage Range, 1.8 V . . . 3.6 V D Ultralow-Power Consumption: − Active Mode: 280 µA at 1 MHz, 2.2V − Standby Mode: 1.6 µA − Off Mode (RAM Retention): 0.1 µA D Five Power-Saving Modes D Wake-Up From Standby Mode in less than 6 µs D 16-Bit RISC Architecture, 125-ns Instruction Cycle Time D 12-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature D 16-Bit Timer_B With Seven Capture/Compare-With-Shadow Registers D 16-Bit Timer_A With Three Capture/Compare Registers D On-Chip Comparator D Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse SLAS272F − JULY 2000 − REVISED JUNE 2004 D Serial Communication Interface (USART), Functions as Asynchronous UART or Synchronous SPI Interface − Two USARTs (USART0, USART1) — MSP430x14x(1) Devices − One USART (USART0) — MSP430x13x Devices D Family Members Include: − MSP430F133: 8KB+256B Flash Memory, 256B RAM − MSP430F135: 16KB+256B Flash Memory, 512B RAM − MSP430F147, MSP430F1471†: 32KB+256B Flash Memory, 1KB RAM − MSP430F148, MSP430F1481†: 48KB+256B Flash Memory, 2KB RAM − MSP430F149, MSP430F1491†: 60KB+256B Flash Memory, 2KB RAM D Available in 64-Pin Quad Flat Pack (QFP) and 64-pin QFN D For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide, Literature Number SLAU049 † The MSP430F14x1 devices are identical to the MSP430F14x devices with the exception that the ADC12 module is not implemented. description The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 µs. The MSP430x13x and the MSP430x14x(1) series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter (not implemented on the MSP430F14x1 devices), one or two universal serial synchronous/asynchronous communication interfaces (USART), and 48 I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process and transmit the data to a host system. The timers make the configurations ideal for industrial control applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code and hardware-compatible family solution. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2000 − 2004, Texas Instruments Incorporated • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 TA −40°C to 85°C AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFP (PAG) MSP430F133IPM MSP430F135IPM MSP430F147IPM MSP430F1471IPM MSP430F148IPM MSP430F1481IPM MSP430F149IPM MSP430F1491IPM MSP430F133IPAG MSP430F135IPAG MSP430F147IPAG MSP430F148IPAG MSP430F149IPAG pin designation, MSP430F133, MSP430F135 PM, PAG, RTD PACKAGE (TOP VIEW) PLASTIC 64-PIN QFN (RTD) MSP430F133IRTD MSP430F135IRTD MSP430F147IRTD MSP430F1471IRTD MSP430F148IRTD MSP430F1481IRTD MSP430F149IRTD MSP430F1491IRTD AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH P5.6/ACLK P5.5/SMCLK DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 VREF+ XIN XOUT VeREF+ VREF−/VeREF− P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.3 P5.2 P5.1 P5.0 P4.7/TBCLK P4.6 P4.5 P4.4 P4.3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7 P3.6 P3.5/URXD0 P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6/ADC12CLK P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER pin designation, MSP430F147, MSP430F148, MSP430F149 SLAS272F − JULY 2000 − REVISED JUNE 2004 PM, PAG, RTD PACKAGE (TOP VIEW) AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH P5.6/ACLK P5.5/SMCLK DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 VREF+ XIN XOUT VeREF+ VREF−/VeREF− P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0 P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6/ADC12CLK P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 pin designation, MSP430F1471, MSP430F1481, MSP430F1491 PM, RTD PACKAGE (TOP VIEW) AVCC DVSS AVSS P6.2 P6.1 P6.0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH P5.6/ACLK P5.5/SMCLK DVCC P6.3 P6.4 P6.5 P6.6 P6.7 Reserved XIN XOUT DVSS DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0 P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6 P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 functional block diagrams MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 MSP430x13x XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6 ROSC XT2IN XT2OUT TMS TCK TDI/TCLK TDO/TDI Oscillator System Clock ACLK 16KB Flash SMCLK 8KB Flash 512B RAM ADC12 256B RAM 12-Bit 8 Channels <10µs Conv. MCLK CPU Incl. 16 Reg. Test MAB,M1A6BB,it16-Bit JTAG Emulation Module MDBM, D1B6 ,B1it6-Bit 4 8 8 8 8 88 I/O Port 1/2 16 I/Os, with Interrupt Capability I/O Port 3/4 16 I/Os I/O Port 5/6 16 I/Os MAB, 4 Bit MCB Bus Conv MDB, 8 Bit Watchdog Timer 15/16-Bit Timer_B3 3 CC Reg Shadow Reg Timer_A3 3 CC Reg POR Comparator A USART0 UART Mode SPI Mode MSP430x14x XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6 ROSC XT2IN XT2OUT TMS TCK TDI/TCLK TDO/TDI Oscillator System Clock ACLK 60KB Flash SMCLK 48KB Flash 32KB Flash 2KB RAM 2KB RAM 1KB RAM ADC12 12-Bit 8 Channels <10µs Conv. MCLK CPU Incl. 16 Reg. Test MAB,M1A6BB,it16-Bit JTAG 8 8 8 8 88 I/O Port 1/2 16 I/Os, with Interrupt Capability I/O Port 3/4 16 I/Os I/O Port 5/6 16 I/Os MAB, 4 Bit MCB Emulation Module 4 Hardware Multiplier MPY, MPYS MAC,MACS MDBM, D1B6 ,B1it6-Bit Bus Conv MDB, 8 Bit Watchdog Timer 15/16-Bit Timer_B7 7 CC Reg Shadow Reg Timer_A3 3 CC Reg POR Comparator A USART0 USART1 UART Mode UART Mode SPI Mode SPI Mode • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 functional block diagrams (continued) MSP430x14x1 XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6 ROSC XT2IN XT2OUT TMS TCK TDI/TCLK TDO/TDI Oscillator System Clock ACLK 60KB Flash SMCLK 48KB Flash 32KB Flash 2KB RAM 2KB RAM 1KB RAM MCLK CPU Incl. 16 Reg. Test MAB,M1A6BB,it16-Bit JTAG 8 8 8 8 88 I/O Port 1/2 16 I/Os, with Interrupt Capability I/O Port 3/4 16 I/Os I/O Port 5/6 16 I/Os MAB, 4 Bit MCB Emulation Module 4 Hardware Multiplier MPY, MPYS MAC,MACS MDBM, D1B6 ,B1it6-Bit Bus Conv MDB, 8 Bit Watchdog Timer 15/16-Bit Timer_B7 7 CC Reg Shadow Reg Timer_A3 3 CC Reg POR Comparator A USART0 USART1 UART Mode UART Mode SPI Mode SPI Mode 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER Terminal Functions SLAS272F − JULY 2000 − REVISED JUNE 2004 MSP430x13x, MSP430x14x TERMINAL NAME NO. AVCC 64 AVSS 62 DVCC 1 DVSS 63 P1.0/TACLK 12 P1.1/TA0 13 P1.2/TA1 14 P1.3/TA2 15 P1.4/SMCLK 16 P1.5/TA0 17 P1.6/TA1 18 P1.7/TA2 19 P2.0/ACLK 20 P2.1/TAINCLK 21 P2.2/CAOUT/TA0 22 P2.3/CA0/TA1 23 P2.4/CA1/TA2 24 P2.5/ROSC 25 P2.6/ADC12CLK 26 P2.7/TA0 27 P3.0/STE0 28 P3.1/SIMO0 29 P3.2/SOMI0 30 P3.3/UCLK0 31 P3.4/UTXD0 32 P3.5/URXD0 33 P3.6/UTXD1† 34 P3.7/URXD1† 35 P4.0/TB0 36 P4.1/TB1 37 P4.2/TB2 38 P4.3/TB3† 39 P4.4/TB4† 40 P4.5/TB5† 41 P4.6/TB6† 42 P4.7/TBCLK 43 P5.0/STE1† 44 P5.1/SIMO1† 45 P5.2/SOMI1† 46 P5.3/UCLK1† 47 P5.4/MCLK 48 P5.5/SMCLK 49 † 14x devices only I/O DESCRIPTION Analog supply voltage, positive terminal. Supplies the analog portion of the analog-to-digital converter. Analog supply voltage, negative terminal. Supplies the analog portion of the analog-to-digital converter. Digital supply voltage, positive terminal. Supplies all digital parts. Digital supply voltage, negative terminal. Supplies all digital parts. I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output I/O General-purpose digital I/O pin/SMCLK signal output I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/ I/O General-purpose digital I/O pin/ACLK output I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency I/O General-purpose digital I/O pin/conversion clock – 12-bit ADC I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output I/O General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode I/O General-purpose digital I/O/USART0 clock: external input − UART or SPI mode, output – SPI mode I/O General-purpose digital I/O pin/transmit data out – USART0/UART mode I/O General-purpose digital I/O pin/receive data in – USART0/UART mode I/O General-purpose digital I/O pin/transmit data out – USART1/UART mode I/O General-purpose digital I/O pin/receive data in – USART1/UART mode I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input I/O General-purpose digital I/O pin/slave transmit enable – USART1/SPI mode I/O General-purpose digital I/O pin/slave in/master out of USART1/SPI mode I/O General-purpose digital I/O pin/slave out/master in of USART1/SPI mode I/O General-purpose digital I/O pin/USART1 clock: external input − UART or SPI mode, output – SPI mode I/O General-purpose digital I/O pin/main system clock MCLK output I/O General-purpose digital I/O pin/submain system clock SMCLK output • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 Terminal Functions (Continued) MSP430x13x, MSP430x14x (continued) TERMINAL NAME NO. P5.6/ACLK 50 P5.7/TBOUTH 51 P6.0/A0 59 P6.1/A1 60 P6.2/A2 61 P6.3/A3 2 P6.4/A4 3 P6.5/A5 4 P6.6/A6 5 P6.7/A7 6 RST/NMI 58 TCK 57 TDI/TCLK 55 TDO/TDI 54 TMS 56 VeREF+ 10 VREF+ 7 VREF−/VeREF− 11 XIN 8 XOUT 9 XT2IN 53 XT2OUT 52 QFN Pad NA I/O DESCRIPTION I/O General-purpose digital I/O pin/auxiliary clock ACLK output I/O General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B7: TB0 to TB6 I/O General-purpose digital I/O pin/analog input a0 – 12-bit ADC I/O General-purpose digital I/O pin/analog input a1 – 12-bit ADC I/O General-purpose digital I/O pin/analog input a2 – 12-bit ADC I/O General-purpose digital I/O pin/analog input a3 – 12-bit ADC I/O General-purpose digital I/O pin/analog input a4 – 12-bit ADC I/O General-purpose digital I/O pin/analog input a5 – 12-bit ADC I/O General-purpose digital I/O pin/analog input a6 – 12-bit ADC I/O General-purpose digital I/O pin/analog input a7 – 12-bit ADC I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). I Test clock. TCK is the clock input port for device programming test and bootstrap loader start (in Flash devices). I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. I/O Test data output port. TDO/TDI data output or programming data input terminal I Test mode select. TMS is used as an input port for device programming and test. I Input for an external reference voltage to the ADC O Output of positive terminal of the reference voltage in the ADC I Negative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. O Output terminal of crystal oscillator XT1 I Input port for crystal oscillator XT2. Only standard crystals can be connected. O Output terminal of crystal oscillator XT2 NA QFN package pad connection to DVSS recommended. 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER Terminal Functions SLAS272F − JULY 2000 − REVISED JUNE 2004 MSP430x14x1 TERMINAL NAME NO. AVCC 64 AVSS 62 DVCC 1 DVSS 63 P1.0/TACLK 12 P1.1/TA0 13 P1.2/TA1 14 P1.3/TA2 15 P1.4/SMCLK 16 P1.5/TA0 17 P1.6/TA1 18 P1.7/TA2 19 P2.0/ACLK 20 P2.1/TAINCLK 21 P2.2/CAOUT/TA0 22 P2.3/CA0/TA1 23 P2.4/CA1/TA2 24 P2.5/ROSC 25 P2.6 26 P2.7/TA0 27 P3.0/STE0 28 P3.1/SIMO0 29 P3.2/SOMI0 30 P3.3/UCLK0 31 P3.4/UTXD0 32 P3.5/URXD0 33 P3.6/UTXD1 34 P3.7/URXD1 35 P4.0/TB0 36 P4.1/TB1 37 P4.2/TB2 38 P4.3/TB3 39 P4.4/TB4 40 P4.5/TB5 41 P4.6/TB6 42 P4.7/TBCLK 43 P5.0/STE1 44 P5.1/SIMO1 45 P5.2/SOMI1 46 P5.3/UCLK1 47 P5.4/MCLK 48 P5.5/SMCLK 49 I/O DESCRIPTION Analog supply voltage, positive terminal. Analog supply voltage, negative terminal. Digital supply voltage, positive terminal. Supplies all digital parts. Digital supply voltage, negative terminal. Supplies all digital parts. I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output I/O General-purpose digital I/O pin/SMCLK signal output I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output I/O General-purpose digital I/O pin/ACLK output I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency I/O General-purpose digital I/O pin I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output I/O General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode I/O General-purpose digital I/O/USART0 clock: external input − UART or SPI mode, output – SPI mode I/O General-purpose digital I/O pin/transmit data out – USART0/UART mode I/O General-purpose digital I/O pin/receive data in – USART0/UART mode I/O General-purpose digital I/O pin/transmit data out – USART1/UART mode I/O General-purpose digital I/O pin/receive data in – USART1/UART mode I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input I/O General-purpose digital I/O pin/slave transmit enable – USART1/SPI mode I/O General-purpose digital I/O pin/slave in/master out of USART1/SPI mode I/O General-purpose digital I/O pin/slave out/master in of USART1/SPI mode I/O General-purpose digital I/O pin/USART1 clock: external input − UART or SPI mode, output – SPI mode I/O General-purpose digital I/O pin/main system clock MCLK output I/O General-purpose digital I/O pin/submain system clock SMCLK output • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 Terminal Functions (Continued) MSP430x14x1 (continued) TERMINAL NAME NO. P5.6/ACLK 50 P5.7/TBOUTH 51 P6.0 59 P6.1 60 P6.2 61 P6.3 2 P6.4 3 P6.5 4 P6.6 5 P6.7 6 RST/NMI 58 TCK 57 TDI/TCLK 55 TDO/TDI 54 TMS 56 DVSS 10 Reserved 7 DVSS 11 XIN 8 XOUT 9 XT2IN 53 XT2OUT 52 QFN Pad NA I/O DESCRIPTION I/O General-purpose digital I/O pin/auxiliary clock ACLK output I/O General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B7: TB0 to TB6 I/O General-purpose digital I/O pin I/O General-purpose digital I/O pin I/O General-purpose digital I/O pin I/O General-purpose digital I/O pin I/O General-purpose digital I/O pin I/O General-purpose digital I/O pin I/O General-purpose digital I/O pin I/O General-purpose digital I/O pin I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). I Test clock. TCK is the clock input port for device programming test and bootstrap loader start (in Flash devices). I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. I/O Test data output port. TDO/TDI data output or programming data input terminal I Test mode select. TMS is used as an input port for device programming and test. I Connect to DVSS Reserved, do not connect externally I Connect to DVSS I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. O Output terminal of crystal oscillator XT1 I Input port for crystal oscillator XT2. Only standard crystals can be connected. O Output terminal of crystal oscillator XT2 NA QFN package pad connection to DVSS recommended. 10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2. SLAS272F − JULY 2000 − REVISED JUNE 2004 Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 1. Instruction Word Formats Dual operands, source-destination Single operands, destination only Relative jump, un/conditional e.g. ADD R4,R5 e.g. CALL R8 e.g. JNE R4 + R5 −−−> R5 PC −−>(TOS), R8−−> PC Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX Register FF MOV Rs,Rd Indexed F F MOV X(Rn),Y(Rm) Symbolic (PC relative) F F MOV EDE,TONI Absolute F F MOV &MEM,&TCDAT Indirect F MOV @Rn,Y(Rm) Indirect autoincrement F MOV @Rn+,Rm Immediate NOTE: S = source F MOV #X,TONI D = destination EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI OPERATION R10 −−> R11 M(2+R5)−−> M(6+R6) M(EDE) −−> M(TONI) M(MEM) −−> M(TCDAT) M(R10) −−> M(Tab+R6) M(R10) −−> R11 R10 + 2−−> R10 #45 −−> M(TONI) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode AM; − All clocks are active D Low-power mode 0 (LPM0); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled D Low-power mode 1 (LPM1); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode D Low-power mode 2 (LPM2); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active D Low-power mode 3 (LPM3); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active D Low-power mode 4 (LPM4); − CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped 12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External Reset Watchdog Flash memory WDTIFG KEYV (see Note 1) Reset 0FFFEh 15, highest NMI NMIIFG (see Notes 1 & 4) (Non)maskable Oscillator Fault OFIFG (see Notes 1 & 4) (Non)maskable 0FFFCh 14 Flash memory access violation ACCVIFG (see Notes 1 & 4) (Non)maskable Timer_B7 (see Note 5) TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13 Timer_B7 (see Note 5) TBCCR1 to 6 CCIFGs, TBIFG (see Notes 1 & 2) Maskable 0FFF8h 12 Comparator_A CAIFG Maskable 0FFF6h 11 Watchdog timer WDTIFG Maskable 0FFF4h 10 USART0 receive URXIFG0 Maskable 0FFF2h 9 USART0 transmit UTXIFG0 Maskable 0FFF0h 8 ADC12 (see Note 6) ADC12IFG (see Notes 1 & 2) Maskable 0FFEEh 7 Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6 Timer_A3 TACCR1 CCIFG, TACCR2 CCIFG, TAIFG (see Notes 1 & 2) Maskable 0FFEAh 5 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 & 2) Maskable 0FFE8h 4 USART1 receive URXIFG1 Maskable 0FFE6h 3 USART1 transmit UTXIFG1 0FFE4h 2 I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (see Notes 1 & 2) Maskable 0FFE2h 1 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. 4. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it. 5. Timer_B7 in MSP430x14x(1) family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interrupt flags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs. 6. ADC12 is not implemented on the 14x1 devices. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 13 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable 1 and 2 Address 7 6 5 4 3 0h UTXIE0 URXIE0 ACCVIE NMIIE rw-0 rw-0 rw-0 rw-0 2 1 0 OFIE WDTIE rw-0 rw-0 WDTIE: OFIE: NMIIE: ACCVIE: URXIE0: UTXIE0: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator-fault-interrupt enable Nonmaskable-interrupt enable Flash access violation interrupt enable USART0: UART and SPI receive-interrupt enable USART0: UART and SPI transmit-interrupt enable Address 7 6 5 4 3 2 1 0 01h UTXIE1 URXIE1 rw-0 rw-0 URXIE1: UTXIE1: USART1: UART and SPI receive-interrupt enable USART1: UART and SPI transmit-interrupt enable interrupt flag register 1 and 2 Address 7 6 5 4 3 02h UTXIFG0 URXIFG0 NMIIFG rw-1 rw-0 rw-0 2 1 0 OFIFG WDTIFG rw-1 rw-(0) WDTIFG: OFIFG: NMIIFG: URXIFG0: UTXIFG0: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power up or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI pin USART0: UART and SPI receive flag USART0: UART and SPI transmit flag Address 7 6 5 4 3 2 1 0 03h UTXIFG1 URXIFG1 rw-1 rw-0 URXIFG1: USART1: UART and SPI receive flag UTXIFG1: USART1: UART and SPI transmit flag 14 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 module enable registers 1 and 2 Address 7 6 5 4 3 2 1 0 04h UTXE0 URXE0 USPIE0 rw-0 rw-0 URXE0: UTXE0: USPIE0: USART0: UART receive enable USART0: UART transmit enable USART0: SPI (synchronous peripheral interface) transmit and receive enable Address 7 6 5 4 3 2 1 0 05h UTXE1 URXE1 USPIE1 rw-0 rw-0 URXE1: UTXE1: USPIE1: USART1: UART receive enable USART1: UART transmit enable USART1: SPI (synchronous peripheral interface) transmit and receive enable Legend: rw: rw-0: Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset by PUC. SFR Bit Not Present in Device memory organization Memory Main: interrupt vector Main: code memory Information memory Boot memory RAM Peripherals Size Flash Flash Size Flash Size ROM Size 16-bit 8-bit 8-bit SFR MSP430F133 8KB 0FFFFh − 0FFE0h 0FFFFh − 0E000h 256 Byte 010FFh − 01000h 1KB 0FFFh − 0C00h 256 Byte 02FFh − 0200h 01FFh − 0100h 0FFh − 010h 0Fh − 00h MSP430F135 16KB 0FFFFh − 0FFE0h 0FFFFh − 0C000h 256 Byte 010FFh − 01000h 1KB 0FFFh − 0C00h 512 Byte 03FFh − 0200h 01FFh − 0100h 0FFh − 010h 0Fh − 00h MSP430F147 MSP430F1471 32KB 0FFFFh − 0FFE0h 0FFFFh − 08000h 256 Byte 010FFh − 01000h 1KB 0FFFh − 0C00h 1KB 05FFh − 0200h 01FFh − 0100h 0FFh − 010h 0Fh − 00h MSP430F148 MSP430F1481 48KB 0FFFFh − 0FFE0h 0FFFFh − 04000h 256 Byte 010FFh − 01000h 1KB 0FFFh − 0C00h 2KB 09FFh − 0200h 01FFh − 0100h 0FFh − 010h 0Fh − 00h MSP430F149 MSP430F1491 60KB 0FFFFh − 0FFE0h 0FFFFh − 01100h 256 Byte 010FFh − 01000h 1KB 0FFFh − 0C00h 2KB 09FFh − 0200h 01FFh − 0100h 0FFh − 010h 0Fh − 00h bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. BSL Function Data Transmit Data Receive PM, PAG & RTD Package Pins 13 - P1.1 22 - P2.2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 15 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory. D New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. 8 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 16 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 32 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 48 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 60 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh Segment 0 w/ Interrupt Vectors Segment 1 Segment 2 Main Memory 0E400h 0E3FFh 0E200h 0E1FFh 0E000h 010FFh 01080h 0107Fh 01000h 0C400h 0C3FFh 0C200h 0C1FFh 0C000h 010FFh 01080h 0107Fh 01000h 08400h 083FFh 08200h 081FFh 08000h 010FFh 01080h 0107Fh 01000h 04400h 043FFh 04200h 041FFh 04000h 010FFh 01080h 0107Fh 01000h 01400h 013FFh 01200h 011FFh 01100h 010FFh 01080h 0107Fh 01000h Segment n-1 Segment n Segment A Segment B Information Memory 16 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049. digital I/O There are six 8-bit I/O ports implemented—ports P1 through P6: D All individual I/O bits are independently programmable. D Any combination of input, output, and interrupt conditions is possible. D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. D Read/write access to port-control registers is supported by all instructions. oscillator and system clock The clock system in the MSP430x13x and MSP43x14x(1) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the following clock signals: D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. hardware multiplier (MSP430x14x and MSP430x14x1 Only) The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16, 16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. USART0 The MSP430x13x and the MSP430x14x(1) have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. USART1 (MSP430x14x and MSP430x14x1 Only) The MSP430x14x(1) has a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. Operation of USART1 is identical to USART0. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 17 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 comparator_A The primary function of the comparator_A module is to support precision slope analog−to−digital conversions, battery−voltage supervision, and monitoring of external analog signals. ADC12 (Not implemented in the MSP430x14x1) The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Input Pin Number 12 - P1.0 21 - P2.1 13 - P1.1 22 - P2.2 14 - P1.2 15 - P1.3 Device Input Signal TACLK ACLK SMCLK TAINCLK TA0 TA0 DVSS DVCC TA1 CAOUT (internal) DVSS DVCC TA2 ACLK (internal) DVSS DVCC Timer_A3 Signal Connections Module Input Name Module Block TACLK ACLK SMCLK Timer INCLK CCI0A CCI0B GND CCR0 VCC CCI1A CCI1B GND CCR1 VCC CCI2A CCI2B GND CCR2 VCC Module Output Signal NA TA0 TA1 TA2 Output Pin Number 13 - P1.1 17 - P1.5 27 - P2.7 14 - P1.2 18 - P1.6 23 - P2.3 ADC12 (internal) 15 - P1.3 19 - P1.7 24 - P2.4 timer_B3 (MSP430x13x Only) Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. 18 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 timer_B7 (MSP430x14x and MSP430x14x1 Only) Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_B3/B7 Signal Connections† Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal 43 - P4.7 TBCLK TBCLK ACLK ACLK Timer NA SMCLK SMCLK 43 - P4.7 TBCLK INCLK 36 - P4.0 TB0 CCI0A 36 - P4.0 TB0 CCI0B CCR0 TB0 DVSS GND DVCC VCC 37 - P4.1 TB1 CCI1A 37 - P4.1 TB1 CCI1B CCR1 TB1 DVSS GND DVCC VCC 38 - P4.2 TB2 CCI2A 38 - P4.2 TB2 CCI2B CCR2 TB2 DVSS GND DVCC VCC 39 - P4.3 TB3 CCI3A 39 - P4.3 TB3 CCI3B CCR3 TB3 DVSS GND DVCC VCC 40 - P4.4 TB4 CCI4A 40 - P4.4 TB4 CCI4B CCR4 TB4 DVSS GND DVCC VCC 41 - P4.5 TB5 CCI5A 41 - P4.5 TB5 CCI5B CCR5 TB5 DVSS GND DVCC VCC 42 - P4.6 TB6 CCI6A ACLK (internal) CCI6B CCR6 TB6 DVSS GND DVCC VCC † Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only). Output Pin Number 36 - P4.0 ADC12 (internal) 37 - P4.1 ADC12 (internal) 38 - P4.2 39 - P4.3 40 - P4.4 41 - P4.5 42 - P4.6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 19 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog Timer control WDTCTL 0120h Timer_B7/ Timer_B3 (see Note 1) Timer_B interrupt vector Timer_B control Capture/compare control 0 TBIV TBCTL TBCCTL0 011Eh 0180h 0182h Capture/compare control 1 TBCCTL1 0184h Capture/compare control 2 TBCCTL2 0186h Capture/compare control 3 TBCCTL3 0188h Capture/compare control 4 TBCCTL4 018Ah Capture/compare control 5 TBCCTL5 018Ch Capture/compare control 6 TBCCTL6 018Eh Timer_B register TBR 0190h Capture/compare register 0 TBCCR0 0192h Capture/compare register 1 TBCCR1 0194h Capture/compare register 2 TBCCR2 0196h Capture/compare register 3 TBCCR3 0198h Capture/compare register 4 TBCCR4 019Ah Capture/compare register 5 TBCCR5 019Ch Capture/compare register 6 TBCCR6 019Eh Timer_A3 Timer_A interrupt vector TAIV 012Eh Timer_A control TACTL 0160h Capture/compare control 0 TACCTL0 0162h Capture/compare control 1 TACCTL1 0164h Capture/compare control 2 TACCTL2 0166h Reserved 0168h Reserved 016Ah Reserved 016Ch Reserved 016Eh Timer_A register TAR 0170h Capture/compare register 0 TACCR0 0172h Capture/compare register 1 TACCR1 0174h Capture/compare register 2 TACCR2 0176h Reserved 0178h Reserved 017Ah Reserved 017Ch Reserved 017Eh Hardware Multiplier (MSP430x14x and MSP430x14x1 only) Sum extend Result high word Result low word Second operand SUMEXT RESHI RESLO OP2 013Eh 013Ch 013Ah 0138h Multiply signed +accumulate/operand1 MACS 0136h Multiply+accumulate/operand1 MAC 0134h Multiply signed/operand1 MPYS 0132h Multiply unsigned/operand1 MPY 0130h NOTE 1: Timer_B7 in MSP430x14x(1) family has 7 CCRs, Timer_B3 in MSP430x13x family has 3 CCRs. 20 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 peripheral file map (continued) PERIPHERALS WITH WORD ACCESS (CONTINUED) Flash Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h ADC12 (Not implemented in the MSP430x14x1) Conversion memory 15 Conversion memory 14 Conversion memory 13 ADC12MEM15 ADC12MEM14 ADC12MEM13 015Eh 015Ch 015Ah Conversion memory 12 ADC12MEM12 0158h Conversion memory 11 ADC12MEM11 0156h Conversion memory 10 ADC12MEM10 0154h Conversion memory 9 ADC12MEM9 0152h Conversion memory 8 ADC12MEM8 0150h Conversion memory 7 ADC12MEM7 014Eh Conversion memory 6 ADC12MEM6 014Ch Conversion memory 5 ADC12MEM5 014Ah Conversion memory 4 ADC12MEM4 0148h Conversion memory 3 ADC12MEM3 0146h Conversion memory 2 ADC12MEM2 0144h Conversion memory 1 ADC12MEM1 0142h Conversion memory 0 ADC12MEM0 0140h Interrupt-vector-word register ADC12IV 01A8h Inerrupt-enable register ADC12IE 01A6h Inerrupt-flag register ADC12IFG 01A4h Control register 1 ADC12CTL1 01A2h Control register 0 ADC12CTL0 01A0h ADC memory-control register15 ADC12MCTL15 08Fh ADC memory-control register14 ADC12MCTL14 08Eh ADC memory-control register13 ADC12MCTL13 08Dh ADC memory-control register12 ADC12MCTL12 08Ch ADC memory-control register11 ADC12MCTL11 08Bh ADC memory-control register10 ADC12MCTL10 08Ah ADC memory-control register9 ADC12MCTL9 089h ADC memory-control register8 ADC12MCTL8 088h ADC memory-control register7 ADC12MCTL7 087h ADC memory-control register6 ADC12MCTL6 086h ADC memory-control register5 ADC12MCTL5 085h ADC memory-control register4 ADC12MCTL4 084h ADC memory-control register3 ADC12MCTL3 083h ADC memory-control register2 ADC12MCTL2 082h ADC memory-control register1 ADC12MCTL1 081h ADC memory-control register0 ADC12MCTL0 080h • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 21 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 peripheral file map (continued) USART1 (MSP430x14x and MSP430x14x1 only) USART0 Comparator_A Basic Clock Port P6 Port P5 Port P4 Port P3 Port P2 PERIPHERALS WITH BYTE ACCESS Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control Comparator_A port disable Comparator_A control2 Comparator_A control1 Basic clock system control2 Basic clock system control1 DCO clock frequency control Port P6 selection Port P6 direction Port P6 output Port P6 input Port P5 selection Port P5 direction Port P5 output Port P5 input Port P4 selection Port P4 direction Port P4 output Port P4 input Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 selection Port P2 interrupt enable Port P2 interrupt-edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input U1TXBUF U1RXBUF U1BR1 U1BR0 U1MCTL U1RCTL U1TCTL U1CTL U0TXBUF U0RXBUF U0BR1 U0BR0 U0MCTL U0RCTL U0TCTL U0CTL CAPD CACTL2 CACTL1 BCSCTL2 BCSCTL1 DCOCTL P6SEL P6DIR P6OUT P6IN P5SEL P5DIR P5OUT P5IN P4SEL P4DIR P4OUT P4IN P3SEL P3DIR P3OUT P3IN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 07Fh 07Eh 07Dh 07Ch 07Bh 07Ah 079h 078h 077h 076h 075h 074h 073h 072h 071h 070h 05Bh 05Ah 059h 058h 057h 056h 037h 036h 035h 034h 033h 032h 031h 030h 01Fh 01Eh 01Dh 01Ch 01Bh 01Ah 019h 018h 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 22 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 peripheral file map (continued) Port P1 Special Functions PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P1 selection P1SEL Port P1 interrupt enable P1IE Port P1 interrupt-edge select P1IES Port P1 interrupt flag P1IFG Port P1 direction P1DIR Port P1 output P1OUT Port P1 input P1IN SFR module enable 2 ME2 SFR module enable 1 ME1 SFR interrupt flag2 IFG2 SFR interrupt flag1 IFG1 SFR interrupt enable2 IE2 SFR interrupt enable1 IE1 026h 025h 024h 023h 022h 021h 020h 005h 004h 003h 002h 001h 000h absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 23 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 recommended operating conditions PARAMETER MIN NOM MAX UNITS Supply voltage during program execution, VCC (AVCC = DVCC = VCC) MSP430F13x, MSP430F14x(1) 1.8 3.6 V Supply voltage during flash memory programming, VCC (AVCC = DVCC = VCC) Supply voltage, VSS (AVSS = DVSS = VSS) Operating free-air temperature range, TA MSP430F13x, MSP430F14x(1) 2.7 0.0 MSP430x13x MSP430x14x(1) −40 3.6 V 0.0 V 85 °C LFXT1 crystal frequency, f(LFXT1) (see Notes 1 and 2) LF selected, XTS=0 Watch crystal XT1 selected, XTS=1 Ceramic resonator XT1 selected, XTS=1 Crystal 32768 450 1000 Hz 8000 kHz 8000 kHz XT2 crystal frequency, f(XT2) Ceramic resonator Crystal 450 1000 8000 kHz 8000 Processor frequency (signal MCLK), f(System) VCC = 1.8 V DC VCC = 3.6 V DC 4.15 MHz 8 NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1MΩ resistor from XOUT to VSS is recommended when VCC < 2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15MHz at VCC ≥ 2.2 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8MHz at VCC ≥ 2.8 V. 2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal. f (MHz) ÎÎÎÎÎÎÎÎÎÎ 8.0 MHz Supply voltage range, ’F13x/’F14x(1), during program execution ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 4.15 MHz Supply voltage range, ’F13x/’F14x(1), during flash memory programming 1.8 V 2.7 V 3 V 3.6 V Supply Voltage − V Figure 1. Frequency vs Supply Voltage, MSP430F13x or MSP430F14x(1) 24 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AVCC + DVCC excluding external current PARAMETER TEST CONDITIONS MIN NOM MAX UNIT I(AM) Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) TA = −40°C to 85°C VCC = 2.2 V VCC = 3 V 280 350 µA 420 560 I(AM) Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 4 096 Hz, f(ACLK) = 4,096 Hz XTS=0, SELM=(0,1) XTS=0, SELM=3 TA = −40°C to 85°C VCC = 2.2 V VCC = 3 V 2.5 7 µA 9 20 Low-power mode, (LPM0) I(LPM0) (see Note 1) Low-power mode, (LPM2), I(LPM2) f(MCLK) = f (SMCLK) = 0 MHz, f(ACLK) = 32.768 Hz, SCG0 = 0 TA = −40°C to 85°C TA = −40°C to 85°C VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V 32 45 µA 55 70 11 14 µA 17 22 TA = −40°C 0.8 1.5 I(LPM3) Low-power mode, (LPM3) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 (see Note 2) TA = 25°C TA = 85°C TA = −40°C TA = 25°C VCC = 2.2 V VCC = 3 V 0.9 1.5 µA 1.6 2.8 1.8 2.2 1.6 1.9 µA TA = 85°C 2.3 3.9 TA = −40°C 0.1 0.5 I(LPM4) Low-power mode, (LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 TA = 25°C TA = 85°C TA = −40°C TA = 25°C VCC = 2.2 V VCC = 3 V 0.1 0.5 µA 0.8 2.5 0.1 0.5 0.1 0.5 µA TA = 85°C 0.8 2.5 NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. Timer_B is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with ACLK selected. Current consumption of active mode versus system frequency, F-version I(AM) = I(AM) [1 MHz] × f(System) [MHz] Current consumption of active mode versus supply voltage, F-version I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 25 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6 PARAMETER VIT+ Positive-going input threshold voltage VIT− Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ − VIT−) TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN TYP MAX UNIT 1.1 1.5 V 1.5 1.9 0.4 0.9 V 0.90 1.3 0.3 1.1 V 0.5 1 standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI PARAMETER TEST CONDITIONS MIN VIL Low-level input voltage VIH High-level input voltage VCC = 2.2 V / 3 V VSS 0.8×VCC TYP MAX VSS+0.6 VCC UNIT V V inputs Px.x, TAx, TBx PARAMETER t(int) External interrupt timing t(cap) Timer_A, Timer_B capture timing TEST CONDITIONS Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag, (see Note 1) TA0, TA1, TA2 TB0, TB1, TB2, TB3, TB4, TB5, TB6 (see Note 2) VCC 2.2 V/3 V 2.2 V 3V 2.2 V 3V MIN TYP MAX UNIT 1.5 cycle 62 ns 50 62 ns 50 f(TAext) f(TBext) Timer_A, Timer_B clock frequency externally applied to pin TACLK, TBCLK, INCLK: t(H) = t(L) 2.2 V 3V 8 MHz 10 f(TAint) f(TBint) NOTES: Timer_A, Timer_B clock frequency SMCLK or ACLK signal selected 2.2 V 3V 8 MHz 10 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. 2. Seven capture/compare registers in ’x14x(1) and three capture/compare registers in ’x13x. leakage current (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX Ilkg(P1.x) Leakage Port P1 V(P1.x) (see Note 2) ±50 Ilkg(P2.x) current (see Port P2 V(P2.3) V(P2.4) (see Note 2) VCC = 2.2 V/3 V ±50 Ilkg(P6.x) Note 1) Port P6 V(P6.x) (see Note 2) ±50 NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor. UNIT nA 26 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P3, P4, P5, and P6 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH(max) = −1 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC VOH High-level output voltage IOH(max) = −6 mA, IOH(max) = −1 mA, VCC = 2.2 V, VCC = 3 V, See Note 2 See Note 1 VCC−0.6 VCC−0.25 VCC V VCC IOH(max) = −6 mA, VCC = 3 V, See Note 2 VCC−0.6 VCC IOL(max) = 1.5 mA, VCC = 2.2 V, See Note 1 VSS VSS+0.25 VOL Low-level output voltage IOL(max) = 6 mA, IOL(max) = 1.5 mA, VCC = 2.2 V, VCC = 3 V, See Note 2 See Note 1 VSS VSS VSS+0.6 V VSS+0.25 IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6 NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±6 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±24 mA to satisfy the maximum specified voltage drop. output frequency PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fTAx fACLK, fMCLK, fSMCLK tXdc TA0..2, TB0−TB6, Internal clock source, SMCLK signal applied (see Note 1) CL = 20 pF P5.6/ACLK, P5.4/MCLK, P5.5/SMCLK CL = 20 pF Duty cycle of output frequency, P2.0/ACLK CL = 20 pF, VCC = 2.2 V / 3 V P1.4/SMCLK, CL = 20 pF, VCC = 2.2 V / 3 V fACLK = fLFXT1 = fXT1 fACLK = fLFXT1 = fLF fACLK = fLFXT1/n fSMCLK = fLFXT1 = fXT1 fSMCLK = fLFXT1 = fLF fSMCLK = fLFXT1/n fSMCLK = fDCOCLK DC fSystem MHz fSystem 40% 30% 40% 35% 50%− 15 ns 50%− 15 ns 50% 50% 50% 60% 70% 60% 65% 50%− 15 ns 50%− 15 ns NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK frequencies can be different. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 27 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P3, P4, P5, and P6 (continued) I OL − Low-Level Output Current − mA TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 16 VCC = 2.2 V 14 P2.7 TA = 25°C 12 TA = 85°C 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 VOL − Low-Level Output Voltage − V Figure 2 I OL − Low-Level Output Current − mA TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 25 VCC = 3 V P2.7 TA = 25°C 20 TA = 85°C 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL − Low-Level Output Voltage − V Figure 3 I OH − High-Level Output Current − mA TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 VCC = 2.2 V P2.7 −2 −4 −6 −8 −10 TA = 85°C −12 TA = 25°C −14 0.0 0.5 1.0 1.5 2.0 2.5 VOH − High-Level Output Voltage − V Figure 4 I OH − High-Level Output Current − mA TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 VCC = 3 V P2.7 −5 −10 −15 −20 TA = 85°C −25 TA = 25°C −30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output Voltage − V Figure 5 28 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER t(LPM3) Delay time TEST CONDITIONS f = 1 MHz f = 2 MHz f = 3 MHz VCC = 2.2 V/3 V MIN TYP MAX UNIT 6 6 µs 6 RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRAMh CPU HALTED (see Note 1) 1.6 V NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition. Comparator_A (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(DD) I(Refladder/Refdiode) V(IC) Common-mode input voltage CAON=1, CARSEL=0, CAREF=0 CAON=1, CARSEL=0, CAREF=1/2/3, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 CAON =1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V 25 40 µA 45 60 30 50 µA 45 71 0 VCC−1 V V(Ref025) Voltage @ 0.25 VCC node VCC PCA0=1, CARSEL=1, CAREF=1, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 2.2 V/3 V 0.23 0.24 0.25 V(Ref050) Voltage @ 0.5VCC node VCC PCA0=1, CARSEL=1, CAREF=2, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 2.2 V/3 V 0.47 0.48 0.5 V(RefVT) (see Figure 6) PCA0=1, CARSEL=1, CAREF=3, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 TA = 85°C VCC = 2.2 V VCC = 3 V 390 480 400 490 540 mV 550 V(offset) Offset voltage See Note 2 VCC = 2.2 V/3 V −30 30 mV Vhys Input hysteresis CAON=1 VCC = 2.2 V/3 V 0 0.7 1.4 mV t(response LH) TA = 25°C, Overdrive 10 mV, Without filter: CAF=0 TA = 25°C, Overdrive 10 mV, With filter: CAF=1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V 130 210 80 150 1.4 1.9 0.9 1.5 300 ns 240 3.4 µs 2.6 t(response HL) TA = 25°C, Overdrive 10 mV, Without filter: CAF=0 TA = 25°C, Overdrive 10 mV, With filter: CAF=1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V 130 210 80 150 1.4 1.9 0.9 1.5 300 ns 240 3.4 µs 2.6 NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 29 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 650 650 VCC = 3 V VCC = 2.2 V 600 600 Typical 550 Typical 550 V(REFVT) − Reference Volts −mV V(REFVT) − Reference Volts −mV 500 500 450 450 400 −45 −25 −5 15 35 55 75 95 TA − Free-Air Temperature − °C Figure 6. V(RefVT) vs Temperature, VCC = 3 V 0 V VCC 01 CAON 400 −45 −25 −5 15 35 55 75 95 TA − Free-Air Temperature − °C Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V CAF V+ + V− _ Low Pass Filter 0 0 1 1 To Internal Modules CAOUT τ ≈ 2.0 µs Figure 8. Block Diagram of Comparator_A Module Set CAIFG Flag Overdrive V− VCAOUT 400 mV V+ t(response) Figure 9. Overdrive Definition 30 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) PUC/POR PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(POR_Delay) VPOR V(min) Internal time delay to release POR VCC threshold at which POR release delay time begins (see Note 1) VCC threshold required to generate a POR (see Note 2) TA = −40°C TA = 25°C TA = 85°C VCC |dV/dt| ≥ 1V/ms VCC = 2.2 V/3 V 150 250 µs 1.4 1.8 V 1.1 1.5 V 0.8 1.2 V 0.2 V t(reset) NOTES: RST/NMI low time for PUC/POR Reset is accepted internally 2 µs 1. VCC rise time dV/dt ≥ 1V/ms. 2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less than −1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms. V VCC V POR − V V POR V (min) 2 1.8 1.8 1.6 1.4 1.4 1.2 1 0.8 0.6 0.4 0.2 0 −40 POR No POR POR t Figure 10. Power-On Reset (POR) vs Supply Voltage 1.5 1.2 25°C −20 0 20 40 60 TA − Temperature − °C Figure 11. VPOR vs Temperature 1.2 0.8 80 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 31 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) DCO (see Note 1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT f(DCO03) f(DCO13) f(DCO23) f(DCO33) f(DCO43) f(DCO53) f(DCO63) f(DCO73) f(DCO47) Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V 0.08 0.08 0.14 0.14 0.22 0.22 0.37 0.37 0.61 0.61 1 1 1.6 1.69 2.4 2.7 fDCO40 × 1.7 0.12 0.13 0.19 0.18 0.30 0.28 0.49 0.47 0.77 0.75 1.2 1.3 1.9 2.0 2.9 3.2 fDCO40 × 2.1 0.15 0.16 0.23 0.22 0.36 0.34 0.59 0.56 0.93 0.90 1.5 1.5 2.2 2.29 3.4 3.65 fDCO40 × 2.5 MHz MHz MHz MHz MHz MHz MHz MHz MHz f(DCO77) S(Rsel) S(DCO) Dt DV Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C SR = fRsel+1 / fRsel SDCO = fDCO+1 / fDCO Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 2) Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 2) VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V 4 4.4 1.35 1.07 −0.31 −0.33 0 4.5 4.9 1.65 1.12 −0.36 −0.38 5 4.9 MHz 5.4 2 1.16 −0.40 %/°C −0.43 10 %/V NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System). 2. This parameter is not production tested. Max ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ fDCO_7Min 1 f DCOCLK Frequency Variance Max f DCO_0 Min ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 2.2 3 VCC − V 01234567 DCO Figure 12. DCO Characteristics 32 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics D Individual devices have a minimum and maximum operation frequency. The specified parameters for fDCOx0 to fDCOx7 are valid for all devices. D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps with Rsel1, ... Rsel6 overlaps with Rsel7. D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO. D Modulation control bits MOD0 to MOD4 select how often fDCO+1 is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to f(DCO) × (2MOD/32 ). DCO when using ROSC (see Note 1) PARAMETER TEST CONDITIONS fDCO, DCO output frequency Rsel = 4, DCO = 3, MOD = 0, DCOR = 1, TA = 25°C VCC 2.2 V 3V MIN NOM MAX UNIT 1.8±15% MHz 1.95±15% MHz Dt, Temperature drift Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V ±0.1 Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V 10 NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C. crystal oscillator, LFXT1 oscillator (see Note 1) %/°C %/V PARAMETER TEST CONDITIONS MIN NOM MAX UNIT CXIN Integrated input capacitance XTS=0; LF oscillator selected VCC = 2.2 V/3 V XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V 12 pF 2 CXOUT Integrated output capacitance XTS=0; LF oscillator selected VCC = 2.2 V/3 V XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V 12 pF 2 VIL Input levels at XIN VIH VCC = 2.2 V/3 V (see Note 2) VSS 0.8 × VCC 0.2 × VCC V VCC V NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator. crystal oscillator, XT2 oscillator (see Note 1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT CXT2IN Input capacitance VCC = 2.2 V/3 V 2 pF CXT2OUT Output capacitance VCC = 2.2 V/3 V 2 pF VIL Input levels at XT2IN VIH VCC = 2.2 V/3 V (see Note 2) VSS 0.8 × VCC 0.2 × VCC V VCC V NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator. USART0, USART1 (see Note 1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT t(τ) USART0/1: deglitch time VCC = 2.2 V VCC = 3 V 200 430 800 ns 150 280 500 NOTE 1: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t(τ) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0/1 line. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 33 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT AVCC and DVCC are connected together AVCC Analog supply voltage AVSS and DVSS are connected together 2.2 V(AVSS) = V(DVSS) = 0 V V(P6.x/Ax) Analog input voltage range (see Note 2) All P6.0/A0 to P6.7/A7 terminals. Analog inputs selected in ADC12MCTLx register and P6Sel.x=1 0 ≤ x ≤ 7; V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC) 0 3.6 V VAVCC V IADC12 Operating supply current into AVCC terminal (see Note 3) fADC12CLK = 5.0 MHz ADC12ON = 1, REFON = 0 SHT0=0, SHT1=0, ADC12DIV=0 2.2 V 3V 0.65 1.3 mA 0.8 1.6 IREF+ Operating supply current into AVCC terminal (see Note 4) fADC12CLK = 5.0 MHz ADC12ON = 0, REFON = 1, REF2_5V = 1 fADC12CLK = 5.0 MHz ADC12ON = 0, REFON = 1, REF2_5V = 0 3V 2.2 V 3V 0.5 0.8 mA 0.5 0.8 mA 0.5 0.8 CI † Input capacitance Only one terminal can be selected at one time, P6.x/Ax 2.2 V 40 pF RI† Input MUX ON resistance 0V ≤ VAx ≤ VAVCC 3V 2000 Ω † Not production tested, limits verified by design NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter. 2. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results. 3. The internal reference supply current is not included in current consumption parameter IADC12. 4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. 12-bit ADC, external reference (see Note 1) PARAMETER VeREF+ Positive external reference voltage input VREF− /VeREF− Negative external reference voltage input TEST CONDITIONS VeREF+ > VREF−/VeREF− (see Note 2) VeREF+ > VREF−/VeREF− (see Note 3) MIN NOM MAX UNIT 1.4 VAVCC V 0 1.2 V (VeREF+ − Differential external VREF−/VeREF−) reference voltage input VeREF+ > VREF−/VeREF− (see Note 4) 1.4 VAVCC V IVeREF+ Static input current 0V ≤VeREF+ ≤ VAVCC 2.2 V/3 V ±1 µA IVREF−/VeREF− Static input current 0V ≤ VeREF− ≤ VAVCC 2.2 V/3 V ±1 µA NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. 34 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, built-in reference VREF+ AVCC(min) IVREF+ IL(VREF)+ † PARAMETER TEST CONDITIONS Positive built-in reference voltage output AVCC minimum voltage, Positive built-in reference active REF2_5V = 1 for 2.5 V IVREF+ ≤ IVREF+max REF2_5V = 0 for 1.5 V IVREF+ ≤ IVREF+max REF2_5V = 0, IVREF+ ≤ 1mA REF2_5V = 1, IVREF+ ≤ 0.5mA REF2_5V = 1, IVREF+ ≤ 1mA Load current out of VREF+ terminal 3V 2.2 V/3 V 2.2 V 3V Load-current regulation VREF+ terminal IVREF+ = 500 µA +/− 100 µA Analog input voltage ~0.75 V; REF2_5V = 0 IVREF+ = 500 µA ± 100 µA Analog input voltage ~1.25 V; REF2_5V = 1 2.2 V 3V 3V MIN NOM 2.4 2.5 1.44 1.5 2.2 VREF+ + 0.15 VREF+ + 0.15 0.01 MAX UNIT 2.6 V 1.56 V −0.5 mA −1 ±2 LSB ±2 ±2 LSB IDL(VREF) +‡ Load current regulation VREF+ terminal IVREF+ =100 µA → 900 µA, CVREF+=5 µF, ax ~0.5 x VREF+ 3V Error of conversion result ≤ 1 LSB 20 ns CVREF+ TREF+† Capacitance at pin VREF+ (see Note 1) Temperature coefficient of built-in reference REFON =1, 0 mA ≤ IVREF+ ≤ IVREF+max IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ 1 mA 2.2 V/3 V 2.2 V/3 V 5 10 µF ±100 ppm/°C tREFON† Settle time of internal reference voltage (see Figure 13 and Note 2) IVREF+ = 0.5 mA, CVREF+ = 10 µF, VREF+ = 1.5 V, VAVCC = 2.2 V 17 ms † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 µF tantalum and 100 nF ceramic. NOTES: 2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load. CVREF+ 100 µF 10 µF tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in µF 1 µF 0 1 ms 10 ms 100 ms tREFON Figure 13. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+ • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 35 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 From Power + Supply − 10 µ F 100 nF DVCC DVSS + − Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 10 µ F 100 nF + − 10 µ F Apply External + Reference − 100 nF AVCC MSP430F13x AVSS MSP430F14x VREF+ or VeREF+ VREF−/VeREF− 10 µ F 100 nF Figure 14. Supply Voltage and Reference Voltage Design VREF−/VeREF− External Supply From Power + Supply − 10 µ F 100 nF DVCC DVSS Apply External Reference [VeREF+] or Use Internal Reference [VREF+] + − 10 µ F 100 nF + − AVCC MSP430F13x AVSS MSP430F14x VREF+ or VeREF+ Reference Is Internally Switched to AVSS 10 µ F 100 nF VREF−/VeREF− Figure 15. Supply Voltage and Reference Voltage Design VREF−/VeREF− = AVSS, Internally Connected 36 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, timing parameters PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fADC12CLK For specified performance of ADC12 linearity parameters 2.2V/ 3V 0.45 5 6.3 MHz fADC12OSC Internal ADC12 oscillator ADC12DIV=0, fADC12CLK=fADC12OSC 2.2 V/ 3V 3.7 6.3 MHz tCONVERT Conversion time CVREF+ ≥ 5 µF, Internal oscillator, fADC12OSC = 3.7 MHz to 6.3 MHz 2.2 V/ 3V 2.06 3.51 µs External fADC12CLK from ACLK, MCLK or SMCLK: ADC12SSEL ≠ 0 13×ADC12DIV× 1/fADC12CLK µs tADC12ON‡ Turn on settling time of the ADC (see Note 1) 100 ns RS = 400 Ω, RI = 1000 Ω, 3V 1220 tSample‡ Sampling time CI = 30 pF ns τ = [RS + RI] x CI;(see Note 2) 2.2 V 1400 † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already settled. 2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance. 12-bit ADC, linearity parameters PARAMETER TEST CONDITIONS MIN NOM MAX UNIT 1.4 V ≤ (VeREF+ − VREF−/VeREF−) min ≤ 1.6 V EI Integral linearity error 1.6 V < (VeREF+ − VREF−/VeREF−) min ≤ [V(AVCC)] 2.2 V/3 V ED Differential linearity error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−), CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 2.2 V/3 V EO Offset error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−), Internal impedance of source RS < 100 Ω, 2.2 V/3 V CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) EG Gain error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−), CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ET Total unadjusted error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−), CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±2 ±1.7 LSB ±1 LSB ±2 ±4 LSB ±1.1 ±2 LSB ±2 ±5 LSB • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 37 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, temperature sensor and built-in VMID PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ISENSOR Operating supply current into AVCC terminal (see Note 1) REFON = 0, INCH = 0Ah, ADC12ON=NA, TA = 25_C 2.2 V 3V 40 120 µA 60 160 VSENSOR† ADC12ON = 1, INCH = 0Ah, TA = 0°C 2.2 V 3V 986 986±5% mV 986 986±5% TCSENSOR† ADC12ON = 1, INCH = 0Ah 2.2 V 3V 3.55 3.55±3% mV/°C 3.55 3.55±3% tSENSOR(sample)† Sample time required if channel 10 is selected (see Note 2) ADC12ON = 1, INCH = 0Ah, 2.2 V Error of conversion result ≤ 1 LSB 3 V 30 30 µs IVMID Current into divider at channel 11 (see Note 3) ADC12ON = 1, INCH = 0Bh 2.2 V 3V NA µA NA VMID AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh, VMID is ~0.5 x VAVCC 2.2 V 3V 1.1 1.1±0.04 V 1.5 1.50±0.04 tVMID(sample) Sample time required if channel ADC12ON = 1, INCH = 0Bh, 2.2 V 1400 11 is selected (see Note 4) Error of conversion result ≤ 1 LSB 3 V 1220 ns † Not production tested, limits characterized NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal is high). Therefore it includes the constant current through the sensor and the reference. 2. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on). 3. No additional current is needed. The VMID is used during sampling. 4. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. 38 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Flash Memory PARAMETER VCC(PGM/ ERASE) Program and Erase supply voltage TEST CONDITIONS VCC MIN NOM MAX UNIT 2.7 3.6 V fFTG IPGM IERASE tCPT tCMErase Flash Timing Generator frequency Supply current from DVCC during program Supply current from DVCC during erase Cumulative program time Cumulative mass erase time Program/Erase endurance see Note 1 see Note 2 257 476 kHz 2.7 V/ 3.6 V 3 5 mA 2.7 V/ 3.6 V 3 7 mA 2.7 V/ 3.6 V 4 ms 2.7 V/ 3.6 V 200 104 105 ms cycles tRetention Data retention duration TJ = 25°C 100 years tWord Word or byte program time 35 tBlock, 0 Block program time for 1st byte or word 30 tBlock, 1-63 tBlock, End Block program time for each additional byte or word Block program end-sequence wait time see Note 3 21 6 tFTG tMass Erase Mass erase time 5297 tSeg Erase Segment erase time 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG). JTAG Interface PARAMETER TEST CONDITIONS VCC fTCK TCK input frequency see Note 1 2.2 V 3V RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions. MIN NOM MAX UNIT 0 5 MHz 0 10 MHz 25 60 90 kΩ JTAG Fuse (see Note 1) PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7V IFB Supply current into TDI/TCLK during fuse blow 100 mA tFB Time to blow fuse 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 39 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION input/output schematic port P1, P1.0 to P1.7, input/output with Schmitt-trigger P1SEL.x P1DIR.x 0 Direction Control From Module 1 0 P1OUT.x Module X OUT 1 Pad Logic P1.0/TACLK .. P1.7/TA2 P1IN.x EN Module X IN D P1IRQ.x P1IE.x EN Q P1IFG.x Set Interrupt Edge Select Interrupt Flag P1IES.x P1SEL.x PnSel.x PnDIR.x Dir. CONTROL FROM MODULE P1Sel.0 P1DIR.0 P1DIR.0 P1Sel.1 P1DIR.1 P1DIR.1 P1Sel.2 P1DIR.2 P1DIR.2 P1Sel.3 P1DIR.3 P1DIR.3 P1Sel.4 P1DIR.4 P1DIR.4 P1Sel.5 P1DIR.5 P1DIR.5 P1Sel.6 P1DIR.6 P1DIR.6 P1Sel.7 P1DIR.7 † Signal from or to Timer_A P1DIR.7 PnOUT.x P1OUT.0 P1OUT.1 P1OUT.2 P1OUT.3 P1OUT.4 P1OUT.5 P1OUT.6 P1OUT.7 MODULE X OUT DVSS Out0 signal† Out1 signal† Out2 signal† SMCLK Out0 signal† Out1 signal† Out2 signal† PnIN.x P1IN.0 P1IN.1 P1IN.2 P1IN.3 P1IN.4 P1IN.5 P1IN.6 P1IN.7 MODULE X IN TACLK† CCI0A† CCI1A† CCI2A† unused unused unused unused PnIE.x PnIFG.x PnIES.x P1IE.0 P1IE.1 P1IE.2 P1IE.3 P1IE.4 P1IE.5 P1IE.6 P1IE.7 P1IFG.0 P1IFG.1 P1IFG.2 P1IFG.3 P1IFG.4 P1IFG.5 P1IFG.6 P1IFG.7 P1IES.0 P1IES.1 P1IES.2 P1IES.3 P1IES.4 P1IES.5 P1IES.6 P1IES.7 40 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER APPLICATION INFORMATION SLAS272F − JULY 2000 − REVISED JUNE 2004 input/output schematic (continued) port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger P2SEL.x P2DIR.x Direction Control From Module 0 0: Input 1 1: Output P2OUT.x 0 Module X OUT 1 P2IN.x Pad Logic EN Module X IN D P2IRQ.x P2IE.x EN Q P2IFG.x Set Interrupt Flag Interrupt Edge Select P2IES.x P2SEL.x x: Bit Identifier 0 to 2, 6, and 7 for Port P2 Bus Keeper CAPD.X P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.6/ADC12CLK P2.7/TA0 Dir. CONTROL PnSel.x PnDIR.x FROM MODULE PnOUT.x P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 † Signal from Comparator_A ‡ Signal to Timer_A § Signal from Timer_A ¶ ADC12CLK signal is output of the 12-bit ADC module MODULE X OUT ACLK DVSS CAOUT† ADC12CLK¶ Out0 signal§ PnIN.x P2IN.0 P2IN.1 P2IN.2 P2IN.6 P2IN.7 MODULE X IN unused INCLK‡ CCI0B‡ unused unused PnIE.x PnIFG.x PnIES.x P2IE.0 P2IE.1 P2IE.2 P2IE.6 P2IE.7 P2IFG.0 P2IFG.1 P2IFG.2 P2IFG.6 P2IFG.7 P2IES.0 P2IES.1 P2IES.2 P2IES.6 P2IES.7 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 41 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION input/output schematic (continued) port P2, P2.3 to P2.4, input/output with Schmitt-trigger P2SEL.3 P2DIR.3 Direction Control From Module P2OUT.3 Module X OUT 0: Input 0 1: Output 1 Pad Logic 0 1 P2.3/CA0/TA1 P2IN.3 EN Module X IN D Bus Keeper P2IRQ.3 P2IE.3 EN Q P2IFG.3 Set Interrupt Edge Select Interrupt Flag P2IES.3 P2SEL.3 Comparator_A CAF CAPD.3 CAEX P2CA CAREF + CCI1B To Timer_A3 P2IRQ.4 P2SEL.4 Interrupt P2IES.4 Flag CAREF P2IFG.4 Q Set P2IE.4 EN Edge Select Interrupt − Reference Block CAPD.4 Module X IN D EN P2IN.4 Bus Keeper Module X OUT P2OUT.4 From Module Direction Control P2DIR.4 P2SEL.4 1 0 Pad Logic 1 0 1: Output 0: Input PnSel.x PnDIR.x P2Sel.3 P2DIR.3 P2Sel.4 P2DIR.4 † Signal from Timer_A DIRECTION CONTROL FROM MODULE P2DIR.3 P2DIR.4 PnOUT.x MODULE X OUT PnIN.x P2OUT.3 P2OUT.4 Out1 signal† Out2 signal† P2IN.3 P2IN.4 MODULE X IN unused unused P2.4/CA1/TA2 PnIE.x PnIFG.x PnIES.x P2IE.3 P2IFG.3 P2IES.3 P2IE.4 P2IFG.4 P2IES.4 42 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION input/output schematic (continued) port P2, P2.5, input/output with Schmitt-trigger and Rosc function for the basic clock module P2SEL.5 P2DIR.5 0: Input 0 1: Output Pad Logic Direction Control From Module 1 P2OUT.5 0 Module X OUT 1 P2.5/Rosc P2IN.5 Module X IN P2IRQ.5 EN D P2IE.5 EN Q P2IFG.5 Set Edge Select Interrupt Bus Keeper Internal to Basic Clock Module VCC 01 Interrupt Flag P2IES.5 P2SEL.5 DCOR CAPD.5 to DC Generator DCOR: Control Bit From Basic Clock Module If it Is Set, P2.5 Is Disconnected From P2.5 Pad PnSel.x P2Sel.5 PnDIR.x P2DIR.5 DIRECTION CONTROL FROM MODULE P2DIR.5 PnOUT.x MODULE X OUT PnIN.x P2OUT.5 DVSS P2IN.5 MODULE X IN unused PnIE.x PnIFG.x PnIES.x P2IE.5 P2IFG.5 P2IES.5 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 43 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION input/output schematic (continued) port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger P3SEL.x P3DIR.x Direction Control From Module P3OUT.x Module X OUT 0: Input 0 1: Output 1 Pad Logic 0 1 P3.0/STE0 P3.4/UTXD0 P3.5/URXD0 P3.6/UTXD1‡ P3.7/URXD1¶ P3IN.x EN Module X IN D x: Bit Identifier, 0 and 4 to 7 for Port P3 PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT P3Sel.0 P3DIR.0 DVSS P3OUT.0 P3Sel.4 P3DIR.4 DVCC P3OUT.4 P3Sel.5 P3DIR.5 DVSS P3OUT.5 P3Sel.6 P3DIR.6 DVCC P3OUT.6 P3Sel.7 P3DIR.7 DVSS P3OUT.7 † Output from USART0 module ‡ Output from USART1 module in x14x(1) configuration, DVSS in x13x configuration § Input to USART0 module ¶ Input to USART1 module in x14x(1) configuration, unused in x13x configuration DVSS UTXD0† DVSS UTXD1‡ DVSS PnIN.x P3IN.0 P3IN.4 P3IN.5 P3IN.6 P3IN.7 MODULE X IN STE0 Unused URXD0§ Unused URXD1¶ 44 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER APPLICATION INFORMATION input/output schematic (continued) SLAS272F − JULY 2000 − REVISED JUNE 2004 port P3, P3.1, input/output with Schmitt-trigger SYNC MM STC STE P3SEL.1 P3DIR.1 DCM_SIMO P3OUT1 (SI)MO0 From USART0 0: Input 0 1: Output 1 Pad Logic 0 1 P3.1/SIMO0 P3IN.1 EN SI(MO)0 D To USART0 port P3, P3.2, input/output with Schmitt-trigger SYNC MM STC STE P3SEL.2 P3DIR.2 DCM_SOMI P3OUT.2 SO(MI)0 From USART0 0: Input 0 1: Output 1 Pad Logic 0 1 P3.2/SOMI0 P3IN.2 EN (SO)MI0 D To USART0 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 45 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION input/output schematic (continued) port P3, P3.3, input/output with Schmitt-trigger SYNC MM STC STE P3SEL.3 P3DIR.3 DCM_UCLK P3OUT.3 UCLK.0 From USART0 0: Input 0 1: Output 1 Pad Logic 0 1 P3.3/UCLK0 P3IN.3 EN UCLK0 D To USART0 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always an input. SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode). 46 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER APPLICATION INFORMATION input/output schematic (continued) port P4, P4.0 to P4.6, input/output with Schmitt-trigger P4SEL.x P4DIR.x Direction Control From Module w Module X IN P5SEL.7 P4OUT.x Module X OUT 0: Input 0 1: Output 1 Pad Logic 0 1 SLAS272F − JULY 2000 − REVISED JUNE 2004 P4.0/TB0 .. P4.6/TB6 TBOUTHiZ P4IN.x EN Module X IN D x: bit identifier, 0 to 6 for Port P4 PnSel.x PnDIR.x P4Sel.0 P4Sel.1 P4Sel.2 P4Sel.3 P4Sel.4 P4Sel.5 P4Sel.6 † Signal from Timer_B ‡ Signal to Timer_B § From P5.7 P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6 DIRECTION CONTROL FROM MODULE P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6 Bus Keeper PnOUT.x P4OUT.0 P4OUT.1 P4OUT.2 P4OUT.3 P4OUT.4 P4OUT.5 P4OUT.6 MODULE X OUT Out0 signal† Out1 signal† Out2 signal† Out3 signal† Out4 signal† Out5 signal† Out6 signal† PnIN.x P4IN.0 P4IN.1 P4IN.2 P4IN.3 P4IN.4 P4IN.5 P4IN.6 MODULE X IN CCI0A / CCI0B‡ CCI1A / CCI1B‡ CCI2A / CCI2B‡ CCI3A / CCI3B‡ CCI4A / CCI4B‡ CCI5A / CCI5B‡ CCI6A‡ • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 47 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION input/output schematic (continued) port P4, P4.7, input/output with Schmitt-trigger P4SEL.7 P4DIR.7 0: Input 0 1: Output 1 Pad Logic 0 P4OUT.7 DVSS 1 P4.7/TBCLK P4IN.7 EN Timer_B, D TBCLK port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt-trigger P5SEL.x P5DIR.x Direction Control From Module P5OUT.x Module X OUT 0: Input 0 1: Output 1 Pad Logic 0 1 P5.0/STE1 P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH P5IN.x EN Module X IN D x: Bit Identifier, 0 and 4 to 7 for Port P5 PnSel.x PnDIR.x Dir. CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN P5Sel.0 P5DIR.0 DVSS P5OUT.0 DVSS P5IN.0 STE.1 P5Sel.4 P5DIR.4 DVCC P5OUT.4 MCLK P5IN.4 unused P5Sel.5 P5DIR.5 DVCC P5OUT.5 SMCLK P5IN.5 unused P5Sel.6 P5DIR.6 DVCC P5OUT.6 ACLK P5IN.6 unused P5Sel.7 P5DIR.7 DVSS P5OUT.7 DVSS P5IN.7 TBOUTHiZ NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B7. 48 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER APPLICATION INFORMATION input/output schematic (continued) port P5, P5.1, input/output with Schmitt-trigger SYNC MM STC STE P5SEL.1 P5DIR.1 DCM_SIMO P5OUT.1 (SI)MO1 From USART1 0: Input 0 1: Output 1 Pad Logic 0 1 SLAS272F − JULY 2000 − REVISED JUNE 2004 P5.1/SIMO1 P5IN.1 EN SI(MO)1 D To USART1 port P5, P5.2, input/output with Schmitt-trigger SYNC MM STC STE P5SEL.2 P5DIR.2 DCM_SOMI P5OUT.2 SO(MI)1 From USART1 0: Input 0 1: Output 1 Pad Logic 0 1 P5.2/SOMI1 P5IN.2 EN (SO)MI1 To USART1 D • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 49 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION input/output schematic (continued) port P5, P5.3, input/output with Schmitt-trigger SYNC MM STC STE P5SEL.3 P5DIR.3 DCM_SIMO P5OUT.3 UCLK1 From USART1 0: Input 0 1: Output 1 Pad Logic 0 1 P5.3/UCLK1 P5IN.3 EN UCLK1 D To USART1 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction is always input. SPI, slave mode: The clock applied to UCLK1 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode). 50 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION input/output schematic (continued) port P6, P6.0 to P6.7, input/output with Schmitt-trigger P6SEL.x P6DIR.x Direction Control From Module 0 0: Input 1 1: Output 0 P6OUT.x Module X OUT 1 Pad Logic P6.0 .. P6.7 P6IN.x EN Module X IN D Bus Keeper From ADC To ADC Note: Not implemented in the MSP430x14x1 devices x: Bit Identifier, 0 to 7 for Port P6 NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 µA. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12. PnSel.x PnDIR.x DIR. CONTROL FROM MODULE PnOUT.x P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 P6Sel.3 P6DIR.3 P6DIR.3 P6OUT.3 P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 P6Sel.6 P6DIR.6 P6DIR.6 P6OUT.6 P6Sel.7 P6DIR.7 P6DIR.7 P6OUT.7 NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module. MODULE X OUT DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS PnIN.x P6IN.0 P6IN.1 P6IN.2 P6IN.3 P6IN.4 P6IN.5 P6IN.6 P6IN.7 MODULE X IN unused unused unused unused unused unused unused unused • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 51 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger TDO Controlled by JTAG JTAG Controlled by JTAG TDI Controlled by JTAG TDO/TDI DVCC DVCC Test & Emulation Module TMS TCK Fuse Burn & Test Fuse TDI/TCLK DVCC DVCC TMS TCK During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry 52 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER SLAS272F − JULY 2000 − REVISED JUNE 2004 APPLICATION INFORMATION JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 16). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITF ITDI/TCLK Figure 16. Fuse Check Mode Current: MSP430F13x, MSP430F14x(1) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 53 PACKAGE OPTION ADDENDUM www.ti.com 30-Apr-2009 PACKAGING INFORMATION Orderable Device MSP430A009IPMR MSP430F133IPAG MSP430F133IPM MSP430F133IPMR MSP430F133IRTDR MSP430F133IRTDT MSP430F135IPAG MSP430F135IPM MSP430F135IPMR MSP430F135IRTDR MSP430F135IRTDT MSP430F1471IPM MSP430F1471IPMR MSP430F1471IPMRG MSP430F1471IPMRG4 MSP430F1471IRTDR MSP430F1471IRTDT MSP430F147IPAG MSP430F147IPM MSP430F147IPMR MSP430F147IPMR-KAM MSP430F147IPMRG4 MSP430F147IRTDR MSP430F147IRTDT MSP430F1481IPM Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type LQFP Package Drawing PM TQFP PAG LQFP PM LQFP PM QFN RTD QFN RTD TQFP PAG LQFP PM LQFP PM QFN RTD QFN RTD LQFP PM LQFP PM LQFP PM LQFP PM QFN RTD QFN RTD TQFP PAG LQFP PM LQFP PM LQFP PM LQFP PM QFN RTD QFN RTD LQFP PM Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Qty 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR no Sb/Br) 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR no Sb/Br) 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 TBD Call TI Call TI 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR no Sb/Br) 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-Apr-2009 Orderable Device MSP430F1481IPMR MSP430F1481IRTDR MSP430F1481IRTDT MSP430F148IPAG MSP430F148IPM MSP430F148IPMR MSP430F148IRTDR MSP430F148IRTDT MSP430F1491IPM MSP430F1491IPMG4 MSP430F1491IPMR MSP430F1491IPMRG4 MSP430F1491IRTDR MSP430F1491IRTDT MSP430F149IPAG MSP430F149IPAGR MSP430F149IPM MSP430F149IPMG4 MSP430F149IPMR MSP430F149IPMRG4 MSP430F149IRTDR MSP430F149IRTDT Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type LQFP Package Drawing PM QFN RTD QFN RTD TQFP PAG LQFP PM LQFP PM QFN RTD QFN RTD LQFP PM LQFP PM LQFP PM LQFP PM QFN RTD QFN RTD TQFP PAG TQFP PAG LQFP PM LQFP PM LQFP PM LQFP PM QFN RTD QFN RTD Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Qty 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR no Sb/Br) 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR no Sb/Br) 64 1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR no Sb/Br) 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 30-Apr-2009 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PAG (S-PQFP-G64) 0,50 48 49 0,27 0,17 33 0,08 M 32 MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PLASTIC QUAD FLATPACK 64 1 1,05 0,95 1,20 MAX 17 16 7,50 TYP 10,20 SQ 9,80 12,20 11,80 SQ 0,05 MIN Seating Plane 0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 0,13 NOM 0,25 0,75 0,45 Gage Plane 0°– 7° 4040282 / C 11/96 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 PM (S-PQFP-G64) 0,50 48 49 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PLASTIC QUAD FLATPACK 0,27 0,08 M 0,17 33 32 64 17 0,13 NOM 1 1,45 1,35 16 7,50 TYP 10,20 9,80 SQ 12,20 11,80 SQ 1,60 MAX 0,25 0,05 MIN 0,75 0,45 Seating Plane 0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. May also be thermally enhanced plastic with leads connected to the die pads. Gage Plane 0°– 7° 4040152 / C 11/96 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DLP® Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee® Solutions amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2009, Texas Instruments Incorporated

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