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CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 1 Chapter 1 Homework Solutions 1.1-1 Using Eq. (1) of Sec 1.1, give the base-10 value for the 5-bit binary number 11010 (b4 b3 b2 b1 b0 ordering). From Eq. (1) of Sec 1.1 we have N ∑ bN-1 2-1 + b N-2 2-2 + bN-3 2-3 + ...+ b0 2-N = bN-i2-i i=1 1 × 2-1 + 1× 2-2 + 0 × 2-3 + 1 × 2-4 + 0 × 2-5 = 1 2 + 1 4 + 0 8 + 1 16 + 0 32 16 + 8 + 0 + 2 + 0 26 13 = 32 = 32 = 16 1.1-2 Process the sinusoid in Fig. P1.2 through an analog sample and hold. The sample points are given at each integer value of t/T. Amplitude 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sample times 1 2 3 4 5 6 7 8 9 10 11 _t_ T Figure P1.1-2 1.1-3 Digitize the sinusoid given in Fig. P1.2 according to Eq. (1) in Sec. 1.1 using a four-bit digitizer. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sample times Amplitude 1110 1100 1111 1101 1010 1000 0110 1000 0101 0011 0010 0010 1 2 3 4 5 6 7 8 9 10 11 _t_ T Figure P1.1-3 The figure illustrates the digitized result. At several places in the waveform, the digitized value must resolve a sampled value that lies equally between two digital values. The resulting digitized value could be either of the two values as illustrated in the list below. Sample Time 0 1 2 3 4 5 6 7 8 9 10 11 4-bit Output 1000 1100 1110 1111 or 1110 1101 1010 0110 0011 0010 or 0001 0010 0101 1000 1.1-4 Use the nodal equation method to find vout/vin of Fig. P1.4. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 3 A B R1 R2 vin R3 v1 gmv1 R4 vout Node A: Figure P1.1-4 0 = G1(v1-vin) + G3(v1) + G2(v1 - vout) v1(G1 + G2 + G3) - G2(vout) = G1(vin) Node B: 0 = G2(vout-v1) + gm1(v1) + G4( vout) v1(gm1 - G2) + vout (G2 + G4) = 0 G1+G2 +G3 gm1 - G2 G1vin 0 vout = G1+G2 +G3 gm1 - G2 - G2 G2 + G4 vout vin = G1 (G2 - gm1) G1 G2 + G1 G4 + G2 G4 + G3 G2 + G3 G4 + G2 gm1 1.1-5 Use the mesh equation method to find vout/vin of Fig. P1.4. R1 R2 vin ia R3 v1 gmv1 R4 vout ib ic Figure P1.1-5 0 = -vin + R1(ia + ib + ic) + R3(ia) CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 4 0 = -vin + R1(ia + ib + ic) + R2(ib + ic) + vout ic = vout R4 ib = gm v1 = gm ia R3 0 = -vin + R1ia + gm ia R3 + vout R4 + R3ia 0 = -vin + R1ia + gm ia R3 + vout R4 + R2 gm ia R3 + vout R4 + vout vin = ia (R1 + R3 + gm R1 R2) + vout R1 R4 vin = ia (R1 + gm R1 R3 + gm R2 R3) + vout R1 + R2+ R4 R4 vout = R1+R3 + gm R1 R3 R1+ gm R1 R3 + gm R2 R3 vin vin R1+ R3 + gm R1 R3 R1+ gm R1 R3 + gm R2 R3 R1/ R4 (R1+ R2+R4) / R4 vin R3 R4 (1 - gm R2) vout = 2 2 (R1 + R3 + gm R1 R3) (R1 + R2 + R4) - (R1 + gmR1 R3 + gmR1 R2 R3) vin R3 R4 (1 - gm R2) vout = R1R2 + R1R4 + R1R3 + R2R3 + R3R4 + gm R1 R3 R4 vout vin = R3 R4 (1 - gm R2) R1R2 + R1R4 + R1R3 + R2R3 + R3R4 + gm R1 R3 R4 1.1-6 Use the source rearrangement and substitution concepts to simplify the circuit shown in Fig. P1.6 and solve for iout/iin by making chain-type calculations only. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 5 i R2 iin R1 v1 rmi R3 iout i R2 iin R1 v1 rmi rmi R3 iout i R2 iin R1 v1 R-rm rmi R3 iout iout = -rm R3 i i= R + R1 R1 - rm iin iout iin = -rm R1/R3 R + R1 - rm Figure P1.1-6 1.1-7 Find v2/v1 and v1/i1 of Fig. P1.7. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 6 i1 gm(v1-v2) v1 RL v2 Figure P1.1-7 v2 v1 = gm (v1 - v2) RL v2 (1 + gm RL ) = gm RL v1 v2 gm RL v1 = 1 + gm RL v2 = i1 RL substituting for v2 yields: i1 RL v1 = gm RL 1 + gm RL v1 i1 = RL( 1 + gm RL gm RL ) v1 i1 = RL + 1 gm 1.1-8 Use the circuit-reduction technique to solve for vout/vin of Fig. P1.8. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 7 Av(vin - v1) vin R1 v1 N1 Avv1 R2 vout N2 Avvin vin R1 v1 R2 vout Multiply R1 by (Av + 1) Figure P1.1-8a Avvin vin v1 R1(Av+1) -Avvin R2 vout = R2 + R1(Av+1) vout vin = -Av R2 R2 + R1(Av+1) Figure P1.1-8b R2 vout CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 8 vout vin = -Av -Av + 1 R2 R2 Av + 1 + R1 As Av approaches infinity, vout vin = -R2 R1 1.1-9 Use the Miller simplification concept to solve for vout/vin of Fig. A-3 (see Appendix A). R1 R3 rmia vin ia R2 v1 ib vout K = vout v1 = -rm ia iaR2 = -rm R2 Z1 = R3 1 + rm R2 R3 -rm R2 Z2 = - rm R2 - 1 Figure P1.1-9a (Figure A-3 Mesh analysis.) CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 9 Z2 = rm R3 R2 rm R2 + 1 = R3 R2 rm + 1 R1 rmia vin ia R2 Z1 Z2 vout ia = vin (R2 || Z1) 1 (R2 || Z1) + R1 R2 vout = -rm ia Figure P1.1-9b vout = -vin rm (R2 || (R2 || Z1) + Z1) R1 R12 vout vin = -rm (R2 (R2 || || Z1) Z1) + R1 R12 vout vin = -rm R3 (R1R2 + R1R3 + R1rm + R2R3) 1.1-10 Find vout/iin of Fig. A-12 and compare with the results of Example A-1. iin R1 v1 R'2 gmv1 R3 vout Figure P1.1-10 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 10 v1 = iin (R1 || R2' ) vout = -gmv1 R3 = -gm R3 iin (R1 || R'2) vout iin = -gm R3(R1 || R'2) R'2 = R2 1 + gm R3 R1R2 R1 || R'2 = 1 + gm R3 (1 + gm R3) R1 + R2 1 + gm R3 R1 || R'2 = R1R2 (1 + gm R3) R1 + R2 vout iin = -gm R1 R2R3 R1+ R2+ R3+ gm R1R3 The A.1-1 result is: vout iin = R1 R3 - gm R1 R2R3 R1+ R2+ R3+ gm R1R3 if gmR2 >> 1 then the results are the same. 1.1-11 Use the Miller simplification technique described in Appendix A to solve for the output resistance, vo/io, of Fig. P1.4. Calculate the output resistance not using the Miller simplification and compare your results. R1 R2 vin R3 v1 gmv1 R4 vout Figure P1.1-11a CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 11 Zo with Miller K = -gm R4 Z2 = -R2 -gm gm R4 R4 -1 = R2 gm R4 1 + gm R4 gm R2 R24 1 + gm R4 Z0 = R4 || Z2 = (1 + gm R4) R4 + gm R2 R24 1 + gm R4 Z0 = R4 || Z2 = gm R2 R24 R4 + gm R4 ( R4 + R2) Zo without Miller R1||R3 v1 R2 gmv1 iT R4 vT Figure P1.1-11b v1 = (R1 || R3) i + gmv1 - RvT4 v1 [1 + gm (R1 || R3)] = ( R1 || R3 ) iT + - RvT4 (1) v1 = (R1 || R3) (iT R4 + - vT) R4 [1 + gm (R1 || R3)] CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 12 (2) v1 = vT (R1 || R3) R1 || R3 + R2 Equate (1) and (2) vT (R1 || R3) (R1 || R3) (iT R4 - vT) R1 || R3 + R2 = R4 [1 + gm (R1 || R3)] vT R1 || R3 + R2 = iT R4 - vT R4 [1 + gm (R1 || R3)] vT R4 [1 + gm (R1 || R3)] + R2+ R1||R3 = iT R4 (R2+ R1||R3) Z0 = R4 (R2+ R1||R3 ) R2 + R4 + gm R4(R1||R3) + R1||R3 R4 R2 + R1R3R4 R1 + R3 Z0 = R2 + R4 + gm R4R1 R3 + R1+R3 R1 R3 Z0 = R4 R2 (R1 + R3) + R1R3R4 (R2 + R4) (R1 + R3) + R1R3 + gm R1R3 R4 R1 R2 R4 + R2R3 R4 + R1R3R4 Z0 = R1 R2 + R2 R3 + R3R4 + R1R4 + R1R3 + gm R1R3 R4 1.1-12 Consider an ideal voltage amplifier with a voltage gain of Av = 0.99. A resistance R = 50 kΩ is connected from the output back to the input. Find the input resistance of this circuit by applying the Miller simplification concept. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002 13 i R=50K v1 0.99v1 vout Figure P1.1-12 R Rin = 1 - K K = 0.99 50 KΩ Rin = 1 - 0.99 = 50 K Ω 0.01 = 5 Meg Ω CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 1 Chapter 2 Homework Solutions Problem 2.1-1 List the five basic MOS fabrication processing steps and give the purpose or function of each step. Oxidation: Combining oxygen and silicon to form silicondioxide (SiO2). Resulting SiO2 formed by oxidation is used as an isolation barrier (e.g., between gate polysilicon and the underlying channel) and as a dielectric (e.g., between two plates of a capacitor). Diffusion: Movement of impurity atoms from one location to another (e.g., from the silicon surface to the bulk to form a diffused well region). Ion Implantation: Firing ions into an undoped region for the purpose of doping it to a desired concentration level. Specific doping profiles are achievable with ion implantation which cannot be achieved by diffusion alone. Deposition: Depositing various films on to the wafer. Used to deposit dielectrics which cannot be grown because of the type of underlying material. Deposition methods are used to lay down polysilicon, metal, and the dielectric between them. Etching: Removal of material sensitive to the etch process. For example, etching is used to eliminate unwanted polysilicon after it has been laid out by deposition. Problem 2.1-2 What is the difference between positive and negative photoresist and how is photoresist used? Positive: Exposed resist changes chemically so that it can dissolve upon exposure to light. Unexposed regions remain intact. Negative: Unexposed resist changes chemically so that it can dissolve upon exposure to light. Exposed regions remain intact. Photoresist is used as a masking layer which is paterned appropriately so that certain underlying regions are exposed to the etching process while those regions covered by photoresist are resistant to etching. Problem 2.1-3 Illustrate the impact on source and drain diffusions of a 7° angle off perpendicular ion implant. Assume that the thickness of polysilicon is 8000 Å and that out diffusion from point of ion impact is 0.07 µm. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 2 Ion implantation 7o Polysilicon Gate Implanted ions No overlap of gate to diffusion (a) Polysilicon Gate (b) Polysilicon Gate After ion implantation After diffusion Polysilicon Gate Significant overlap of polysilicon to gate Implanted ions diffused (c) Figure P2.1-3 Problem 2.1-4 What is the function of silicon nitride in the CMOS fabrication process described in Section 2.1 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 3 The primary purpose of silicon nitride is to provide a barrier to oxygen so that when deposited and patterned on top of silicon, silicon dioxide does not form below where the silicon nitride exists. Problem 2.1-5 Give typical thickness for the field oxide (FOX), thin oxide (TOX), n+ or p+, p-well, and metal 1 in units of µm. FOX: ~ 1 µm TOX: ~ 0.014 µm for an 0.8 µm process N+/p+: ~ 0.2 µm Well: ~ 1.2 µm Metal 1: ~ 0.5 µm Problem 2.2-1 Repeat Example 2.2-1 if the applied voltage is -2 V. NA = 5 × 1015/cm3, ND = 1020/cm3 φo = kT q ln NAnN2i D = 1.381×10-23×300 1.6×10-19 ln 5×1015×1020 (1.45×1010)2 = 0.9168 xn= q2NεsDi((φNoA−v+DN)NDA)1/2 = 2×111.7.6××81.805-149××1100-1240 ((05.9×1160815++2.100) 250×)10151/2 = 43.5×10-12 m xp = −2qεNsiA(φ(No A− +vDN)ND)D1/2 = 2×11.16.×7×108-.1895×45××1100-1145 ((05.9×1160815++2.100) 2100)201/2 = −0.869 µm xd = xn − xp = 0 + 0.869 µm = 0.869 µm Cj0 = dQj dvD = A 2(NεAsiq+NNADN)D(φo)1/2 Cj0 = 1×10-3×1×10-3 11.7×8.8524(×51×01-0141×5+11.6××11002-01)9×(05.×911071)5×1×10201/2 = 21.3 fF CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 4 Cj0 = 1 Cj0 − vφD01/2 = 1 21.3 fF − 0.-92171/2 = 11.94 fF Problem 2.2-2 Develop Eq. (2.2-9) using Eqs. (2.2-1), (2.2-7), and (2.2-8). Eq. 2.2-1 xd = xn − xp Eq. 2.2-7 xn = 2qεNsiD(φ(No A− +vDN)ND)A1/2 Eq. 2.2-8 xp = − 2qεNsiA(φ(No A− +vDN)ND)D1/2 xd = 2εsi(φo − vD)NA2 + 2εsi(φo − vD)ND21/2 qNA ND (NA + ND) xd = (φo − vD)1/2 2εsiNA2 + ND2 1/2 qNA ND (NA + ND) Assuming that 2NA ND << (NA + ND)2 Then xd = (φo − vD)1/2 qN2AεsNi(DNA(N+AN+DN) 2D)1/2 1/2 xd = (φo − vD)1/2 2εsiq(NNAA + ND) ND Problem 2.2-3 Redevelop Eqs. (2.2-7) and (2.2-8) if the impurity concentration of a pn junction is given by Fig. 2.2-2 rather than the step junction of Fig. 2.2-1(b). CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 5 Referring to Figure P2.2-3 ND - NA (cm-3) ND 0 x ND - NA = ax -NA ρ(x) qND xp 0 xn x -qNA E(x) x E0 V(x) φ0− vD x xd Figure P2.2-3 Using Poisson’s equation in one dimension d2V dx2 = - ρ(x) ε ρ(x)= qax , when xp < x < xn d2V dx2 = - qax ε E(x) = - dV dx = qa 2ε x2 + C1 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 6 E(xp) = E(xn) = 0 then qa 2 0 = 2ε xp + C1 C1 = - qa 2ε x2p E(x) = qa 2ε x2 − qa 2ε x2p = qa 2ε x2 − x2p The voltage across the junction is given as xn xn V = − ⌡⌠E(x)dx = −q2aε ⌡⌠ x2 - x2p dx xp xp V= −q2aε x33 − x2p x xn xp V= −q2aε x33n − x2p xn − x33p − x2p xp V= − qa 2ε x3n 3 − x2p xn − x3p13 − 1 = − qa 2ε x3n 3 − x2p xn + 2 3 x3p Since -xp = xn V= − qa 2ε −x33p + 3 xp + 23 3 xp = − qa 2ε x3p−13 + 1+ 2 3 = − qa 2ε x3p43 V= − 2qa 3ε x3p V represents the barrier potential across the junction, φ0 − VD. Therefore CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 7 φ0 − VD = 2qa 3ε x3p xp = − xn = 23qεa1/3 (φ0 − VD)1/3 Problem 2.2-4 Plot the normalized reverse current, iRA/iR, versus the reverse voltage vR of a silicon pn diode which has BV = 12 V and n = 6. iRA iR = 1 − 1 (vR/BV)n 12 10 8 iRA/iR 6 4 2 0 0 2 4 6 8 10 12 14 VR Figure P2.2-4 Problem 2.2-5 What is the breakdown voltage of a pn junction with NA = ND = 1016/cm3? CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 8 BV ≅ εsi(NA + ND) 2qNAND Em2ax BV ≅ 11.7×8.854×10-14 (1016 + 1016) 2×1.6×10-19×1016 ×1016 (3×105)2 = 58.27 volts Problem 2.2-6 What change in vD of a silicon pn diode will cause an increase of 10 (an order of magnitude) in the forward diode current? iD = Is exp vVDt − 1 ≅ Is exp vVDt 10 iD iD = Is exp vVDt1 Is exp vVDt2 = exp vVDt1 exp vVDt2 = exp vD1V- tvD2 10 = exp vD1V- tvD2 Vt ln(10) = vD1- vD2 25.9 mV × 2.303 = 59.6 mV = vD1- vD2 vD1- vD2 = 59.6 mV Problem 2.3-1 Explain in your own words why the magnitude of the threshold voltage in Eq. (2.3-19) increases as the magnitude of the source-bulk voltage increases (The source-bulk pn diode remains reversed biased.) Considering an n-channel device, as the gate voltage increases relative to the bulk, the region under the gate will begin to invert. What happens near the source? If the source is at the same potential as the bulk, then the region adjacent to the edge of the source inverts as the rest of the bulk region under the gate inverts. However, if the source is at a higher potential than the bulk, then a greater gate voltage is required to overcome the electric field induced by the source. While a portion of the region under the gate still inverts, there is no path of current flow to the source because the gate voltage is not large enough to invert right at the source edge. Once CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 9 the gate is greater than the source and increasing, then the region adjacent to the source can begin to invert and thus provide a current path into the channel. Problem 2.3-2 If VSB = 2 V, find the value of VT for the n-channel transistor of Ex. 2.3-1. 2φF = -0.940 γ = 0.577 VT0 = 0.306 VT = VT0 + γ ( |−2φF + vSB| − |−2φF|) VT = 0.306 + 0.577 ( |0.940 + 2| − |0.940|) = 0.736 volts VT = 0.736 volts Problem 2.3-3 Re-derive Eq. (2.3-27) given that VT is not constant in Eq. (2.3-22) but rather varies linearly with v(y) according to the following equation. VT = VT0 + a v(y) << correction to book L vDS vDS ⌡⌠iD dy = ⌡⌠WµnQI(y) dv(y) = ⌡⌠WµnCox[vGS − v(y) − VT(y)] dv(y) 0 0 0 VT(y)= VT0 + a v(y) vDS iD L = ⌡⌠WµnCox[vGS − v(y) − VT0 − a v(y)] dv(y) 0 vDS iD L = WµnCox ⌠ ⌡ [vGS − VT0 − v(y) (1 + a)] dv(y) 0 v(y) 2vDS iD L = WµnCox (vGS − VT0 )v(y) − (1 + a) 2 0 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 10 iD = WµnCox L (vGS − VT0 ) vDS − (1 + a) vDS 2 2 Problem 2.3-4 If the mobility of an electron is 500 cm2/(V⋅s) and the mobility of a hole is 200 cm2/(V⋅s), compare the performance of an n-channel with a p-channel transistor. In particular, consider the value of the transconductance parameter and speed of the MOS transistor. Since K’ = µCox, the transconductance of an n-channel transistor will be 2.5 time greater than the transconductance of a p-channel transistor. Remember that mobility will degrade as a function of terminal conditions so transconductance will degrade as well. The speed of a circuit is determined in a large part by the capacitance at the terminals and the transconductance. When terminal capacitances are equal for an n-channel and p-channel transistor of the same dimensions, the higher transconductance of the n-channel results in a faster circuit. Problem 2.3-5 Using Ex. 2.3-1 as a starting point, calculate the difference in threshold voltage between two devices whose gate-oxide is different by 5% (i.e., tox = 210 Å). φF(substrate) = −0.0259 ln 3× 1.45 1×0116010 = −0.377 V φF(gate) = 0.0259 ln 4× 1.45 ×10110910 = 0.563 V φMS = φF(substrate) − φF(gate) = −0.940 V. Cox = εox/tox = 3.9 × 8.854 × 10-14 210 × 10-8 = 1.644 × 10-7 F/cm2 1/2 Qb0 = − 2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 × 2 × 0.377 × 3 × 1016 = − 8.66 × 10-8 C/cm2. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 11 Qb0 Cox = −8.66 1.644 × × 10-8 10-7 = −0.5268 V Qss Cox = 1010 × 1.60 × 10-19 1.644 × 10-7 = 9.73 × 10-3 V VT0 = − 0.940 + 0.754 + 0.5268 − 9.73 × 10-3 = 0.331 V γ = 2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 1.644 × 10-7 × 3 × 1016 1/2 = 0.607 V1/2 Problem 2.3-6 Repeat Ex. 2.3-1 using NA = 7 × 1016 cm-3, gate doping, ND = 1 × 1019 cm-3. φF(substrate) = −0.0259 ln 7× 1.45 1×0116010 = −0.3986 V φF(gate) = 0.0259 ln 1× 1.45 ×10110910 = 0.527 V φMS = φF(substrate) − φF(gate) = −0.9256 V. Cox = εox/tox = 3.9 × 8.854 × 10-14 200 × 10-8 = 1.727 × 10-7 F/cm2 1/2 Qb0 = − 2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 × 2 × 0.3986 × 7 × 1016 = − 13.6 × 10-8 C/cm2. Qb0 Cox = −13.6 1.727 × × 10-8 10-7 = −0.7875 V CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 12 Qss Cox = 1010 × 1.60 × 10-19 1.727 × 10-7 = 9.3 × 10-3 V VT0 = − 0.9256 + 0.797 + 0.7875 − 9.3 × 10-3 = 0.6496 V γ = 2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 1.727 × 10-7 × 7 × 1016 1/2 = 0.882 V1/2 Problem 2.4-1 Given the component tolerances in Table 2.4-1, design the simple lowpass filter illustrated in Fig P2.4-1 to minimize the variation in pole frequency over all process variations. Pole frequency should be designed to a nominal value of 1MHz. You must choose the appropriate capacitor and resistor type. Explain your reasoning. Calculate the variation of pole frequency over process using the design you have chosen. R vin C vout Figure P2.4.1 - To minimize distortion, we would choose minimum voltage coefficient for resistor and capacitor. - To minimize variation, we choose components with the lowest tolerance. The obvious choice for the resistor is Polysilicon. The obvious choice for the capacitor is the MOS capacitor. Thus we have the following: We want ω-3dB=2π×106 = 1/RC C = 2.2 fF/µm2 to 2.7 fF/µm2 ; R = 20 Ω/! to 40 Ω/! Nominal values are C = 2.45 fF/µm2 ; R = 30 Ω/! CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 13 In order to minimize total area used, you can do the following: Set resistor width to 5µm (choosing a different width is OK). Define: N = the number of squares for the resistor AC = area for the capacitor. Then: R = N × 30 C = AC × C’ (use C’ to avoid confusion) We want: 1 RC = 2π×106 Total area = Atot= N×25+AC Atot = 25×N + 1.59×106 N To minimize area, set ∂Atot ∂N = 25 − 1.59×106 N2 = 0 N = 252 ⇒ AC = 6308 µm2 Nominal values for R and C: R = 7.56 kΩ ; C = 15.45 pF Minimum values for R and C: R = 5.04 kΩ ; C = 13.88 pF Maximum values for R and C: R = 10.08 kΩ ; C = 17.03 pF 1 Max pole frequency = (2π)(5.04k) (13.88pF) ⇒ 2.275 MHz 1 Min pole frequency = (2π)(10.08k) (17.03pF) ⇒ 927 kHz Problem 2.4-2 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 14 List two sources of error that can make the actual capacitor, fabricated using a CMOS process, differ from its designed value. Sources of error are: - Variations in oxide thickness between the capacitor plates - Dimensional variations of the plates due to the tolerance in - Etch - Mask - Registration error (between layers) Problem 2.4-3 What is the purpose of the n+ implantation in the capacitor of Fig. 2.4-1(a)? The implant is required to form a diffusion with a doping similar to that of the drain and source. As the voltage across the capacitor varies, depleting the bottom plate of carriers causes the capacitor to have a voltage coefficient which can have a bad effect on analog performance. With a highly-doped diffusion below the top plate, voltage coefficient is minimized. Problem 2.4-4 Consider the circuit in Fig. P2.4-4. Resistor R1 is an n-well resistor with a nominal value of 10 kΩ when the voltage at both terminals is 3 V. The input voltage, vin, is a sine wave with an amplitude of 2 VPP and a dc component of 3 V. Under these conditions, the value of R1 is given as R1 = Rnom 1 + Kvin + vout 2 where Rnom is 10K and the coefficient K is the voltage coefficient of an n-well resistor and has a value of 10K ppm/V. Resistor R2 is an ideal resistor with a value of 10 kΩ. Derive a time-domain expression for vout. Assume that there are no frequency dependencies. TBD Problem 2.4-5 Repeat problem 21 using a P+ diffused resistor for R1. Assume that a P+ resistor’s voltage coefficient is 200 ppm/V. The n-well in which R1 lies, is tied to a 5 volt supply. TBD Problem 2.4-6 Consider problem 2.4-5 again but assume that the n-well in which R1 lies is not connected to a 5 volt supply, but rather is connected as shown in Fig. P2.4-6. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 15 R1 n+ vin Rn-well R2 vout FOX FOX p- substrate n-well p+ diffusion Figure P2.4-6 Voltage effects a resistor’s value when the voltage between any point along the current path in the resistor and the material in which it lies. The voltage difference causes a depletion region to form in the resistor, thus increasing its resistance. This idea is illustrated in the diagram below. p+ diffusion V1 I VDD + Vx - Voltage difference n-well causes depletion region narrowing the current path + 0 Volts - VDD x In order to keep the depletion region from varying along the direction of the current path, the potential of the material below the p+ diffusion (n-well in this case) must vary in the same way as the potential of the p+ diffusion. This is accomplished by causing current to flow in the underlying material (n-well) in parallel with the current in the p+ diffusion as illustrated below. Rp+ V1 ∆Vp+ Rn-well Vx Ip+ p+ diffusion VDD ∆Vn-well In-well n-well VDD x CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 16 It is easy to see that if ∆Vp+ = ∆Vn-well then Vx = 0. Thus by attaching the n-well in parallel with the desired current path, the effects of voltage coefficient of the p+ material are eliminated. There is a second-order effect due to the fact that the n-well resistor will have a voltage coefficient due to the underlying material (p- substrate) tied to ground. Even with this non-ideal effect, significant improvement is achieved by this method. Problem 2.5-1 Assume vD = 0.7 V and find the fractional temperature coefficient of Is and vD. 1 Is dIs dT = 3 T + 1 T VGo Vt = 3 300 + 1 300 1.205 0.0259 = 0.1651 dvD dT = − VGo 1.942 × T 10-3 vD − 3Vt T = − 1.20350−0 0.7 − 3×0.0259 300 = 1.942 × 10-3 1 vD dvD dT = 1.942 × 0.7 10-3 = 2.775 × 10-3 Problem 2.5-2 Plot the noise voltage as a function of the frequency if the thermal noise is 100 nV/ Hz and the junction of the 1/f and thermal noise (the 1/f noise corner) is 10,000 Hz. 10 µV/ Hz noise 1 µV/ Hz voltage 100 nV/ Hz 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz frequency Problem 2.6-1 Given the polysilicon resistor in Fig. P2.6-1 with a resistivity of ρ = 8×10-4 Ω-cm, calculate the resistance of the structure. Consider only the resistance between contact edges. ρs = 50 Ω/ ❑ Fix problem: Eliminate . ρs = 50 Ω/ ❑ because it conflicts with ρ = 8×10-4 Ω-cm CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 17 R = ρL WT = 8×10-4 × 3×10-4 1×10-4 × 8000×10-8 = 30 Ω Problem 2.6-2 Given that you wish to match two transistors having a W/L of 100µm/0.8µm each. Sketch the layout of these two transistors to achieve the best possible matching. Best matching is achieved using the following principles: - unit matching - common centroid - photolithographic invariance Metal 2 0.8 µm Via 1 25 µm Metal 1 Metal 2 Figure P2.6-2 Problem 2.6-3 Assume that the edge variation of the top plate of a capacitor is 0.05µm and that capacitor top plates are to be laid out as squares. It is desired to match two equal capacitors to an accuracy of 0.1%. Assume that there is no variation in oxide thickness. How large would the capacitors have to be to achieve this matching accuracy? Since capacitance is dominated by the area component, ignore the perimeter (fringe) component in this analysis. The units in the analysis that follows is micrometers. C = CAREA (d ± 0.05)2 where d is one (both) sides of the square capacitor. C1 C1 = (d + 0.05)2 (d − 0.05)2 = 1.001 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 18 C1 C1 = (d + 0.05)2 (d − 0.05)2 = 1.001 d2 + 0.1d + 0.052 = 1.001d2 − 0.1d + 0.052 Solving this quadratic yields d = 200.1 Problem 2.6-4 Show that a circular geometry minimizes perimeter-to-area ratio for a given area requirement. In your proof, compare against rectangle and square. Acircle = π r2 Asquare = d2 if Asquare = Acircle then r = d π π Pcircle Psquare = 2d π 4d = π 2 <1 Ideally, Cperimeter C area = 0, so since Pcircle Psquare < 1, the impact of perimeter on a circle is less than on a square. Problem 2.6-5 Show analytically how the Yiannoulos-path technique illustrated in Fig. 2.6-5 maintains a constant area-to-perimeter ratio with non-integer ratios. Area of one unit is: Au = L2 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 19 Total area = N × Au Total periphery = 2(N + 1) CTotal = KA × N × Au + KP × 2(N + 1) where KA and KP represent area and perimeter capacitance (per unit area and per unit length) respectively. Consider two capacitors with different numbers of units but drawn following the template shown in Fig. 2.6-5(a). Their ratio would be One unit L L Figure P2.6-5 (a) C1 KA × N1 × Au + KP × 2(N1 + 1) C2 = KA × N2 × Au + KP × 2(N2 + 1) The ratio of the area and peripheral components by themselves are CC12AREA = KA × N1 × Au KA × N2 × Au = N1 N2 CC12PER = KP × 2(N1 + 1) KP × 2(N2 + 1) = N1 + 1 N2 + 1 N1 N2 + + 1 1 ≠ N1 N2 unless N1= N2 Therefore, the structure in Fig. P2.6-5(a) cannot achieve constant area to perimeter ratio. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 20 Consider Fig. P2.6-5(b). One unit Figure P2.6-5 (b) Total area = (N + 1) × Au Total periphery = 2(N + 1) (as before) Notice what has happened. By adding the extra unit area, two peripheral units are eliminated but two additional ones are added resulting in no change in total periphery. However, one additional area has been added. Thus C1 KA × (N1 + 1) × Au + KP × 2(N1 + 1) C2 = KA × (N2 + 1) × Au + KP × 2(N2 + 1) The ratio of the area and peripheral components by themselves are CC12AREA = KA × (N1 + 1) × Au KA × (N2 + 1) × Au = N1 + 1 N2 + 1 CC12PER = KP × 2(N1 + 1) KP × 2(N2 + 1) = N1 + 1 N2 + 1 N1 N2 + + 1 1 = N1 + 1 N2 + 1 !!! Problem 2.6-6 Design an optimal layout of a matched pair of transistors whose W/L are 8µm/1µm. The matching should be photolithographic invariant as well as common centroid. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 21 Metal 2 1 µm Via 1 2 µm Metal 1 Metal 2 Figure P2.6-6 Problem 2.6-7 Figure P2.6-7 illustrates various ways to implement the layout of a resistor divider. Choose the layout that BEST achieves the goal of a 2:1 ratio. Explain why the other choices are not optimal. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 22 B B 2R R A A B (a) A (b) B B B A (c) A A (d) (e) B 2x A x (f) Figure P2.6-7 Option A suffers the following: - Orientation of the 2R resistor is partly orthogonal to the 1R resistor. Matched resistors should have the same orientation. - Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes should surround all active resistors. Option B suffers the following: - Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes should surround all active resistors. - Resistors do not share a common centroid as they should. Option C suffers the following: - Resistors do not share a common centroid as they should. - Uncertainty is introduced with the additional notch at the contact head. Option D suffers the following: CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 23 - Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes should surround all active resistors. Option E suffers the following: - Nothing Option F suffers the following: - Violates the unit-matching principle - Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes should surround all active resistors. - Resistors do not share a common centroid as they should. Unit Matching Etch Comp. Orientation (a) Yes No No (b) Yes No Yes (c) Yes Yes Yes (d) Yes No Yes (e) Yes Yes Yes (f) No No Yes Common Centroid Yes No No Yes Yes No Clearly, option (e) is the best choice. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 1 Chapter 3 Homework Solutions Problem 3.1-1 Sketch to scale the output characteristics of an enhancement n-channel device if VT = 0.7 volt and ID = 500 µA when VGS = 5 V in saturation. Choose values of VGS = 1, 2, 3, 4, and 5 V. Assume that the channel modulation parameter is zero. 6.00E-04 5.00E-04 4.00E-04 IDS 3.00E-04 2.00E-04 1.00E-04 0.00E+00 0 1 2 3 4 5 6 VGS Problem 3.1-2 Sketch to scale the output characteristics of an enhancement p-channel device if VT = -0.7 volt and ID = -500 µA when VGS = -1, -2, -3, -4, and -6 V. Assume that the channel modulation parameter is zero. 0.00E+00 -1.00E-04 -2.00E-04 IDS -3.00E-04 -4.00E-04 -5.00E-04 -6.00E-04 -6 -5 -4 -3 -2 -1 0 VGS CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 2 Problem 3.1-3 In Table 3.1-2, why is γP greater than γN for a n-well, CMOS technology? The expression for γ is: γ= 2εsi q NSUB Cox Because γ is a function of substrate doping, a higher doping results in a larger value for γ. In general, for an nwell process, the well has a greater doping concentration than the substrate and therefore devices in the well will have a larger γ. Problem 3.1-4 A large-signal model for the MOSFET which features symmetry for the drain and source is given as iD = K' W L [(vGS − VTS)2 u(vGS − VTS)] − [(vGD − VTD)2 u(vGD − VTD)] where u(x) is 1 if x is greater than or equal to zero and 0 if x is less than zero (step function) and VTX is the threshold voltage evaluated from the gate to X where X is either S (Source) or D (Drain). Sketch this model in the form of iD versus vDS for a constant value of vGS (vGS > VTS) and identify the saturated and nonsaturated regions. Be sure to extend this sketch for both positive and negative values of vDS. Repeat the sketch of iD versus vDS for a constant value of vGD (vGD > VTD). Assume that both VTS and VTD are positive. K'(W/L)(vGS-VTS)2 vGS-VTS<0 vGS-VTS>0 vGD constant vGS constant vGD-VTD>0 vGD-VTD<0 -K'(W/L)(vGD-VTD)2 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 3 Problem 3.1-5 Equation (3.1-12) and Eq. (3.1-18) describe the MOS model in nonsaturation and saturation region, respectively. These equations do not agree at the point of transition between saturation and nonsaturation regions. For hand calculations, this is not an issue, but for computer analysis, it is. How would you change Eq. (3.1-18) so that it would agree with Eq. (3.1-12) at vDS = vDS (sat)? iD = K' W L (vGS − VT) − vD2 S vDS (3.1-12) iD = K' W 2L (vGS − VT)2(1 + λvDS), 0 < (vGS − VT) ≤ vDS (3.1-18) What happens to Eq. 3.1-12 at the point where saturation occurs? iD = K' W L (vGS − VT) − vDS2(sat) vDS(sat) vDS (sat)= vGS − VT then iD = K' W L (vGS − VT) vDS(sat) − v2DS2(sat) iD = K' W L (vGS − VT) (vGS − VT) − (vGS − 2 VT)2 iD = K' W L ( vGS − VT) 2 − (vGS − 2 VT)2= K' W L (vGS − 2 VT)2 iD = K' W L (vGS − 2 VT)2 which is not equal to Eq.(3.1-18) because of the channel-length modulation term. Since Eq. (3.1-18) is valid only during saturation when vDS > vDS(sat) we can subtract vDS(sat) from the vDS in the channel-length modulation term. Doing this results in the following modification of Eq. (3.1-18). CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 4 iD = K' W 2L (vGS − VT)2 1 + λ (vDS − vDS(sat)) , 0 < (vGS − VT) ≤ vDS When vDS = vDS(sat) , this expression agrees with the non-saturation equation at the point of transition into saturation. Beyond saturation, channel-length modulation is applied to the difference in vDS and vDS(sat) . Problem 3.2-1 Using the values of Tables 3.1-1 and 3.2-1, calculate the values of CGB, CGS, and CGD for a MOS device which has a W of 5 µm and an L of 1 µm for all three regions of operation. We will need LD in these calculations. LD can be approximated from the value given for CGSO in Table 3.2-1. LD = 220 × 10-12 24.7 × 10-4 ≅ 89 × 10-9 Off CGB = C2 + 2C5 = Cox(Weff)(Leff) + 2CGBO(Leff) Weff = 5 µm Leff = 1 µm - 2×89 nm = 822 × 10-9 CGB = 24.7 × 10-4 × (5× 10-6)( 822 × 10-9) + 2×700 × 10-12×822 × 10-9 CGB = 11.3 × 10-15 F CGS = C1 ≅ Cox(LD)(Weff) = CGSO(Weff) CGS = ( 220 × 10-12) ( 5 × 10-6) = 1.1 × 10-15 CGD = C2 ≅ Cox(LD)(Weff) = CGDO(Weff) CGD = ( 220 × 10-12) ( 5 × 10-6)= 1.1 × 10-15 Saturation CGB = 2C5 = CGBO (Leff) CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 5 CGB = 700 × 10-12 (822 × 10-9) = 575 × 10-18 CGS = CGSO(Weff) + 0.67Cox(Weff)(Leff) CGS = 220 × 10-12 × 5 × 10-6 + 0.67 × 24.7 × 10-4 × 822 × 10-9 × 5 × 10-6 CGS = 7.868 × 10-15 CGD = C3 ≅ Cox(LD)(Weff) = CGDO(Weff) CGD = CGDO(Weff) = 220 × 10-12 × 5 × 10-6 = 1.1 × 10-15 Nonsaturated CGB = 2C5 = CGBO (Leff) CGB = CGBO (Leff) = 700 × 10-12 × 822 × 10-9 = 574 × 10-18 CGS = (CGSO + 0.5CoxLeff)Weff CGS = (220 × 10-12 + 0.5 × 24.7 × 10-4 × 822 × 10-9) × 5 × 10-6 = 6.18 × 10-15 CGD = (CGDO + 0.5CoxLeff)Weff CGD = (220 × 10-12 + 0.5 × 24.7 × 10-4 × 822 × 10-9) × 5 × 10-6 = 6.18 × 10-15 Problem 3.2-2 Find CBX at VBX = 0 V and 0.75 V of Fig. P3.7 assuming the values of Table 3.2-1 apply to the MOS device where FC = 0.5 and PB = 1 V. Assume the device is n-channel and repeat for a p-channel device. Change problem to read: “|VBX |= 0 V and 0.75 V (with the junction always reverse biased)…” Active Area 1.6µm 0.8µm 2.0µm Metal Polysilicon Figure P3.2-2 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 6 AX = 1.6 × 10-6 × 2.0 × 10-6 = 3.2 × 10-12 PX = 2×1.6 × 10-6 + 2.0 × 2.0 × 10-6 = 7.2 × 10-6 NMOS case: CBX = (CJ)(AX) 1 − vPBBXMJ + (CJSW)(PX) 1 − vPBBXMJSW CBX = (770 × 10-6)( 3.2 × 10-12) 1 − P0BMJ + (380 × 1 10-12)( 7.2 × 10-6) − P0BMJSW = 5.2 × 10-15 PMOS case: CBX = (560 × 10-6)( 3.2 × 10-12) 1 − P0BMJ + (350 × 1 10-12)( 7.2 × 10-6) − P0BMJSW = 4.31 × 10-15 |vBX | = 0.75 volts reverse biased NMOS case: CBX = (CJ)(AX) 1 − vPBBXMJ + (CJSW)(PX) 1 − vPBBXMJSW , CBX = (770 × 1 10-6)( 3.2 × 10-12) − -01.75 0.5 + (380 × 1 10-12)( 7.2 × 10-6) − -01.75 0.38 CBX = 2.464 × 10-15 1.323 + 2.736 × 10-15 1.237 = 4.07 × 10-15 PMOS case: CBX = (560 × 1 10-6)( 3.2 × 10-12) − -01.75 0.5 + (350 × 1 10-12)( 7.2 × 10-6) − -01.75 0.35 CBX = 1.79 × 10-15 1.323 + 2.52 × 10-15 1.216 = 3.425 × 10-15 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 7 Problem 3.2-3 Calculate the value of CGB, CGS, and CGD for an n-channel device with a length of 1 µm and a width of 5 µm. Assume VD = 2 V, VG = 2.4 V, and VS = 0.5 V and let VB = 0 V. Use model parameters from Tables 3.1-1, 3.1-2, and 3.2-1. LD = 220 × 10-12 24.7 × 10-4 ≅ 89 × 10-9 Leff = L - 2 × LD = 1 × 10-6 − 2 × 89 × 10-9 = 822 × 10-9 VT = VT0 + γ [ 2|φF| + vSB − 2|φF|] VT = 0.7 + 0.4 [ 0.7 + 0.5 − 0.7] = 0.803 vGS − vT =2.4 − 0.5 − 0.803 = 1.096 < vDS thus saturation region CGB = CGBO x Leff = 700 × 10-12 × 822 × 10-9 = 0.575 fF CGS = CGSO(Weff) + 0.67Cox(Weff)(Leff) CGS = 220 × 10-12 × 5 × 10-6 + 0.67 × 24.7 × 10-4 × 822 × 10-9 × 5 × 10-6 CGS = 7.868 × 10-15 CGD = C3 ≅ Cox(LD)(Weff) = CGDO(Weff) CGD = CGDO(Weff) = 220 × 10-12 × 5 × 10-6 = 1.1 × 10-15 Problem 3.3-1 Calculate the transfer function vout(s)/vin(s) for the circuit shown in Fig. P3.3-1. The W/L of M1 is 2µm/0.8µm and the W/L of M2 is 4µm/4µm. Note that this is a smallsignal analysis and the input voltage has a dc value of 2 volts. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 W/L = 2/0.8 5 Volts M1 vIN = 2V(dc) + 1mV(rms) W/L = 4/4 + M2 vout - vIN = 2V(dc) + 1mV(rms) 8 RM1 + CM2 vout - Figure P3.3-1 Figure P3.3-1b vout(s) vIN (s) = 1/SCM2 RM1 + 1/SCM2 = 1 SCM2RM1 + 1 VT1 = VT0 + γ [ 2|φF| + vSB − 2|φF|] VT1 = 0.7 + 0.4 [ 0.7 + 2.0 − 0.7] = 1.02 RM1 = 1 K'(W/L)M1 (vGS1 − VT1) = 1.837 kΩ CM2 = WM2 × LM2 × Cox = 4 × 10-6 × 4 × 10-6 × 24.7 × 10-4 = 39.52 × 10-15 RM1CM2 = 1.837 kΩ × 39.52 × 10-15 = 72.6 × 10-12 vout(s) vIN (s) == 1 S 13.77 × 109 + 1 Problem 3.3-2 Design a low-pass filter patterened after the circuit in Fig. P3.3-1 that achieves a -3dB frequency of 100 KHz. 1 2πRC = 100,000 There is more than one answer to this problem because there are two free parameters. Use the resistance from Problem 3.3-1. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 9 RM1 = 1.837 kΩ 1 CM2 = 2π ×1.837× 103×1 × 105 = 866.4 pF Choose W = L CM2 = WM2 × LM2 × Cox = W2M2 × 24.7 × 10-4 = 866.4 × 10-12 W2M2 = 350.8 × 10-9 WM2 = 592 × 10-6 Problem 3.3-3 Repeat Examples 3.3-1 and 3.3-2 if the W/L ratio is 100 µm/10 µm. Problem correction: Assume λ = 0.01. Repeat of Example 3.3-1 N-Channel Device gm = (2K'W/L)|ID| gm = 2×110 × 10-6 ×10 × 50 × 10-6 = 332 × 10-6 gmbs = gm 2(2|φF| γ + VSB)1/2 gmbs = 332 × 10-6 0.4 2(0.7+2.0)1/2 = 40.4 × 10-6 gds = ID λ gds = 50 × 10-6 × 0.01 = 500 × 10-9 P-Channel Device gm = (2K'W/L)|ID| CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 10 gm = 2×50 × 10-6 ×10 × 50 × 10-6 = 224 × 10-6 gmbs = gm 2(2|φF| γ + VSB)1/2 gmbs = 224 × 10-6 0.57 2(0.8+2.0)1/2 = 38.2 × 10-6 gds = ID λ gds = 50 × 10-6 × 0.01 = 500 × 10-9 Repeat of Example 3.3-2 N-Channel Device gm = βVDS = 110 × 10-6 × 10× 1 = 1.1 × 10-3 gmbs = βγVDS 2(2|φF | + VSB)1/2 = 110 × 10-6 ×0.4 ×1× 2(0.7+2)1/2 10 = 134 × 10-6 VT = VT0 + γ [ 2|φF| + vSB − 2|φF|] VT = 0.7 + 0.4 [ 0.7 + 2.0 − 0.7] = 1.02 gds = β(VGS − VT − VDS) = 10 ×110 × 10-6 (5 − 1.02 − 1) = 3.28 × 10-3 P-Channel Device gm = βVDS = 50 × 10-6 × 10× 1 = 500 × 10-6 gmbs = βγVDS 2(2|φF | + VSB)1/2 = 50 × 10-6 ×0.57 ×1× 2(0.8+2)1/2 10 = 85.2 × 10-6 |VT| = |VT0| + γ [ 2|φF| + vBS − 2|φF|] |VT| = 0.7 + 0.57 [ 0.8 + 2.0 − 0.8] = 1.144 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 11 gds = β(VGS − VT − VDS) = 10 ×50 × 10-6 (5 − 1.144− 1) = 1.428 × 10-3 Problem 3.3-4 Find the complete small-signal model for an n-channel transistor with the drain at 4 V, gate at 4 V, source at 2 V, and the bulk at 0 V. Assume the model parameters from Tables 3.1-1, 3.1-2, and 3.2-1, and W/L = 10 µm/1 µm. VT = VT0 + γ [ 2|φF| + vSB − 2|φF|] VT = 0.7 + 0.4 [ 0.7 + 2.0 − 0.7] = 1.02 ID = K'W 2L ( vGS − vT ) 2 (1 + λ vDS) = 110 × 10-6 2 ×10 (2 - 1.02)2(1 + 0.4×2) = 570 × 10-6 gm = (2K'W/L)|ID| gm = 2×110 × 10-6 ×10 × 570 × 10-6 = 1.12 × 10-3 gmbs = gm 2(2|φF| γ + VSB)1/2 gmbs = 1.12 × 10-3 0.4 2(0.7+2.0)1/2 = 136 × 10-6 gds = ID λ gds = 570 × 10-6 × 0.04 = 22.8 × 10-9 LD = 220 × 10-12 24.7 × 10-4 ≅ 89 × 10-9 Leff = L - 2 × LD = 1 × 10-6 − 2 × 89 × 10-9 = 822 × 10-9 CGB = CGBO x Leff = 700 × 10-12 × 822 × 10-9 = 0.575 fF CGS = CGSO(Weff) + 0.67Cox(Weff)(Leff) CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 12 CGS = 220 × 10-12 × 10 × 10-6 + 0.67 × 24.7 × 10-4 × 822 × 10-9 × 10 × 10-6 CGS = 15.8 × 10-15 CGD = CGDO(Weff) CGD = CGDO(Weff) = 220 × 10-12 × 10 × 10-6 = 2.2 × 10-15 Problem 3.3-5 Consider the circuit in Fig P3.3-5. It is a parallel connection of n mosfet transistors. Each transistor has the same length, L, but each transistor can have a different width, W. Derive an expression for W and L for a single transistor that replaces, and is equivalent to, the multiple parallel transistors. The expression for drain current in saturation is: ID = K'W 2L ( vGS − vT ) 2 (1 + λ vDS) For multiple transistors with the same drain, gate, and source voltage, the drain current can be expressed simply as ID(i) = WL i ( vGS − vT ) 2 (1 + λ vDS) The drain current in each transistor is additive to the total current, thus ∑ 2 ID(TOTAL) = ( vGS − vT ) (1 + λ vDS) WL i Since the lengths are the same, we have ∑ ID(TOTAL) = 1 L( vGS − vT ) 2 (1 + λ vDS) Wi Problem 3.3-6 Consider the circuit in Fig P3.3-6. It is a series connection of n mosfet transistors. Each transistor has the same width, W, but each transistor can have a different length, L. Derive an expression for W and L for a single transistor that replaces, and is equivalent to, the multiple parallel transistors. When using the simple model, you must ignore body effect. Error in problem statement : replace “parallel” with “series” CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 13 Mn M2 M1 Figure P3.3-6 Assume that all devices are in the non-saturation region. Consider the case for two transistors in series as illustrated below. v2 M2 v1 vG v2 vG M1 M3 The drain current in M1 is i1 = K'W L (vGS − VT) vDS − v2D2 S i1 = β1 (vGS − VT) v1 − v21 2 = β1 (vG − VT) v1 − v21 2 i1 = β1 Von v1 − v221 where CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 14 Von = vG − VT v1 = Von − V o2n − 2i1 β1 2 v1 = 2Von − 2Von V o2n − 2i1 β1 − 2i1 β1 The drain current in M2 is i2 = β2 (vG − v1 − VT)( v2 − v1) − ( v2 − 2 v1)2 i2 = β2 ( Von − v1)( v2 − v1) − ( v2 − 2 v1)2 i2 = β2 Von v2 − Vonv1 + 2 v1 2 − v22 2 Substitue the earlier expression for v1 and equate the drain currents (drain currents must be equal) i2 = β1 β2 β1 + β2 Von v2 − v22 2 The expression for the current in M3 is i3 = β3 (vGS − VT) v2 − v222 = β3 Von v2 − v222 The drain current in M3 must be equivalent to the drain current in M1 and M2, thus β3 = β1 β2 β1 + β2 = 1 β1 + 1 -1 β2 = L1 K'W1 + KL'W2 2-1 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 15 Since the widths are equal and the transconductances are equal β3 = 1 K'W (L1 + L2) This analysis is easily extended to address any number of transistors (repeat the analysis with M3 and another transistor in series with it—two at a time) i ∑ LEQUIVALENT = Li 0 Problem 3.5-1 Calculate the value for VON for n MOS transistor in weak inversion assuming that fs and fn can be approximated to be unity (1.0). Assume (from Level 1 parameters): GAMMA = 0.4 PHI = 0.7 COX = 24.7 × 10-4 F/m2 vSB = 0 NFS = 7 × 1015 (m-2) from Table 3.4-1 von = VT + fast where fast = kT q 1 + q × NFS COX + GAMMA × fs (PHI + vSB)1/2 + 2(PHI + vSB) fn (PHI + vSB) if fs = fn =1 fast = kT q 1 + q × NFS COX + GAMMA × (PHI + vSB)1/2 + 2(PHI + vSB) (PHI + vSB) fast = 0.0259 1 + 1.6 × 10-19 × 7 × 1015 0.4 × (0.7 + 0)1/2 + (0.7 24.7 × 10-4 + 2(0.7 + 0) + 0) CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 16 fast = 0.0259 (1 + .453 + 0.739) = 56.77 × 10-3 von = VT + fast =0.0259 + 56.77 × 10-3 = 82.67 × 10-3 Problem 3.5-2 Develop an expression for the small signal transconductance of a MOS device operating in weak inversion using the large signal expression of Eq. (3.5-5). iD ≅ W L IDO exp n(vkGTS/q) gm = ∂ID ∂VGS = W L n(k1T/q)IDO exp n(vkGTS/q) = ID n(kT/q) Problem 3.5-3 Another way to approximate the transition from strong inversion to weak inversion is to find the current at which the weak-inversion transconductance and the strong-inversion transconductance are equal. Using this method and the approximation for drain current in weak inversion (Eq. (3.5-5)), derive an expression for drain current at the transition between strong and weak inversion. gm = W L n(k1T/q)IDO exp vGS n(kT/q) = (2K'W/L)ID WL 2 n(k1T/q)2 I D2O exp 2vGS n(kT/q) = (2K'W/L)ID ID = 21K' WL IDO 2 n(kT/q) exp 2vGS n(kT/q) ID = 21K' IDO n(k1T/q)2 exp vGS n(kT/q) × WL IDO exp vGS n(kT/q) ID = 21K' IDO n(k1T/q)2 exp n(vkGTS/q) × ID 2 2K' [n(kT/q)] = IDO exp vGS n(kT/q) = ID W/L CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 17 W 2 ID = 2K' L [n(kT/q)] Problem 3.6-1 Consider the circuit illustrated in Fig. P3.6-1. (a) Write a SPICE netlist that describes this circuit. (b) Repeat part (a) with M2 being 2µm/1µm and it is intended that M3 and M2 are ratio matched, 1:2. Part (a) Problem 3.6-1 (a) M1 2 1 0 0 nch W=1u L=1u M2 2 3 4 4 pch w=1u L=1u M3 3 3 4 4 pch w=1u L=1u R1 3 0 50k Vin 1 0 dc 1 Vdd 4 0 dc 5 .MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 .MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 .op .end Part (b) Problem 3.6-1 (b) M1 2 1 0 0 nch W=1u L=1u M2 2 3 4 4 pch w=1u L=1u M=2 M3 3 3 4 4 pch w=1u L=1u R1 3 0 50k Vin 1 0 dc 1 Vdd 4 0 dc 5 .MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 .MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 .op .end Problem 3.6-2 Use SPICE to perform the following analyses on the circuit shown in Fig. P3.6-1: (a) Plot vOUT versus vIN for the nominal parameter set shown. (b) Separately, vary K' and VT by +10% and repeat part (a)—four simulations. Parameter N-Channel P-Channel VT 0.7 -0.7 K' 110 50 l 0.04 0.05 Units V µA/V2 V-1 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 18 VDD = 5 V W/L = 1µ/1µ R =50kΩ 4 3 M3 vIN W/L = 1µ/1µ M2 2 vOUT 1 M1 W/L = 1µ/1µ Figure P3.6-1 Problem 3.6-2 M1 2 1 0 0 nch W=1u L=1u M2 2 3 4 4 pch w=1u L=1u M3 3 3 4 4 pch w=1u L=1u R1 3 0 50k Vin 1 0 dc 1 Vdd 4 0 dc 5 *.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04 *.MODEL pch PMOS VTO=-0.7 KP=50U LAMBDA=0.05 * *.MODEL nch NMOS VTO=0.77 KP=110U LAMBDA=0.04 *.MODEL pch PMOS VTO=-0.7 KP=50U LAMBDA=0.05 * *.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04 *.MODEL pch PMOS VTO=-0.77 KP=50U LAMBDA=0.05 * *.MODEL nch NMOS VTO=0.7 KP=121U LAMBDA=0.04 *.MODEL pch PMOS VTO=-0.7 KP=50U LAMBDA=0.05 * .MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04 .MODEL pch PMOS VTO=-0.7 KP=55U LAMBDA=0.05 .dc vin 0 5 .1 .probe .end CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 19 4V V OUT 2V K' =121u N K' = 55u P V = 0.77 TN V = -0.77 TP 0V 0V 2V V 4V IN Problem 3.6-3 Use SPICE to plot i2 as a function of v2 when i1 has values of 10, 20, 30, 40, 50, 60, and 70 µA for Fig. P3.6-3. The maximum value of v2 is 5 V. Use the model parameters of VT = 0.7 V and K' = 110 µA/V2 and λ = 0.01 V-1. Repeat with λ = 0.04 V-1. i1 W/L = 10µm/2µm M1 i2 + v2 W/L = 10µm/2µm M2 − Figure P3.6-3 p3.6-3 M1 1 1 0 0 nch M2 2 1 0 0 nch I1 0 1 DC 0 V1 3 0 DC 0 V_I2 3 2 DC 0 l = 2u l = 2u w = 10u w = 10u .MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.01 GAMMA = 0.4 PHI = 0.7 *.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04 GAMMA = 0.4 PHI = 0.7 .dc V1 0 5 .1 I1 10u 80u 10u .END CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 20 Lambda = 0.01 80uA 60uA I2 40uA 10uA I2= 70uA I2= 60uA I2= 50uA I2= 40uA I2= 30uA I2= 20uA I2= 10uA 0 1 2 3 4 5 V2 Lambda = 0.04 80uA 60uA I2 40uA 10uA I1= 70uA I1= 60uA I1= 50uA I1= 40uA I1= 30uA I1= 20uA I1= 10uA 0 1 2 3 4 5 V2 Problem 3.6-4 Use SPICE to plot iD as a channel transistor with VT f=un1ctVio,nKo'f=vD1S10foµr Ava/Vlu2e,s aonfdvlG=S = 1, 2, 3, 4 and 5 V for an n0.04 V-1. Show how SPICE can be used to generate and plot these curves simultaneously as illustrated by Fig. 3.1-3. p3.6-4 M1 2 3 0 0 nch l = 1u w = 5u CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 21 VGS 3 0 DC 0 VDS 4 0 DC 0 V_IDS 4 2 DC 0 .MODEL nch NMOS VTO=1 KP=110U .dc VDS 0 5 .1 VGS 0 5 1 .END LAMBDA=0.01 GAMMA = 0.4 PHI = 0.7 VGS= 5 4mA IDS VGS= 4 2mA VGS= 3 VGS= 2 0 0 1 2 3 4 5 VDS Problem 3.6-5 Repeat Example 3.6-1 if the transistor of Fig. 3.6-5 is a PMOS having the model parameters given in Table 3.1-2. p3.6-5 V_IDS 5 2 DC 0 VGS 3 0 DC 0 VDS 5 0 DC 0 M1 2 3 0 0 pch l = 1u w = 5u .MODEL pch PMOS VTO=-0.7 KP=50U .dc VDS 0 -5 -.1 VGS 0 -5 -1 .END LAMBDA=0.051 GAMMA = 0.57 PHI = 0.8 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 22 0mA -1mA IDS -2mA VGS= -2 VGS= -3 VGS= -4 VGS= -5 -3mA -5 -4 -3 -2 -1 0 VDS Problem 3.6-6 Repeat Examples 3.6-2 through 3.6-4 for the circuit of Fig. 3.6-2 if R1 = 200 KΩ. 4V VOUT 2V 0V 0V 2V 4V VIN CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 23 AC Analysis 40 20 vdb(2) 0 -20 e2 e4 e6 e8 Frequency 0 vp(2) -45 -90 e2 e4 e6 e8 Frequency Transient Analysis CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 4V V(2) 2V 0V 0 2us 4us 24 6us CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 1 Chapter 4 Homework Solutions Problem 4.1-1 Using SPICE, generate a set of parametric I-V curves similar to Fig. 4.1-3 for a transistor with a W/L = 10/1. Use model parameters from Table 3.1-2. 10.0 5.0 I (mA) VG = 5 V VG = 4 V VG = 3 V VG = 2 V VG = 1 V VG 2.5 I A B V1 0.0 -2.5 0.0 2.5 V1 (volts) Figure P4.1-1 Problem 4.1-2 The circuit shown in Fig. P4.1-2 illustrates a single-channel MOS resistor with a W/L of 2µm/1µm. Using Table 3.1-2 model parameters, calculate the small-signal on resistance of the MOS transistor at various values for VS and fill in the table below. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 2 5 Volts I = 0.0 VS Figure P4.1-2 The equation for threshold voltage with absolute values so that it can be applied to nchannel or p-channel transistors without confusion. |VT |= |VT0 | + γ 2|φF| + |vSB| − 2|φF| rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = L K'W(|VGS| − |VT|) (when VDS= 0) For n-channel device, VT0 = 0.7 γ = 0.4 2|φF| = 0.7 The table below shows the value of VGS and VSB for each value of VS VS (volts) 0.0 1.0 2.0 3.0 4.0 5.0 Using VS = 0, calculate VT VGS (volts) 5 4 3 2 1 0 VSB (volts) 0 1 2 3 4 5 |VT |= |VT0 | + γ 2|φF| + |vSB| − 2|φF| = 0.7 + 0.4[ 0.7 + 0.0 − 0.7] = 0.7 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 3 Calculate ron rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 110µ × 1 2(5 − 0.7 − 0) = 1057 Ω Repeat for VS = 1 |VT | = 0.7 + 0.4[ 0.7 + 1.0 − 0.7] = 0.887 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 110µ × 1 2(4 − 0.887 − 0) = 1460 Ω Repeat for VS = 2 |VT | = 0.7 + 0.4[ 0.7 + 2.0 − 0.7] = 1.023 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 110µ × 1 2(3 − 1.023 − 0) = 2299 Ω Repeat for VS = 3 |VT | = 0.7 + 0.4[ 0.7 + 3.0 − 0.7] = 1.135 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 110µ × 1 2(2 − 1.135 − 0) = 5253 Ω Repeat for VS = 4 |VT | = 0.7 + 0.4[ 0.7 + 4.0 − 0.7] = 1.233 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 110µ × 2(1 1 − 1.233 − 0) = -19549 Ω The negative sign means that the device is off due to the fact that VGS < VT Thus rON = infinity Repeat for VS = 5 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 4 |VT | = 0.7 + 0.4[ 0.7 + 5.0 − 0.7] = 1.320 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 110µ × 1 2(0 − 1.320 − 0) = -3442 Ω The negative sign means that the device is off due to the fact that VGS < VT Thus rON = infinity Summary: VS (volts) 0.0 1.0 2.0 3.0 4.0 5.0 R (ohms) 1057 1460 2299 5253 infinity infinity Problem 4.1-3 The circuit shown in Fig. P4.1-3 illustrates a single-channel MOS resistor with a W/L of 4µm/1µm. Using Table 3.1-2 model parameters, calculate the small-signal on resistance of the MOS transistor at various values for VS and fill in the table below. Note that the most positive supply voltage is 5 volts. 5 Volts I = 0.0 VS Figure P4.1-3 The equation for threshold voltage with absolute values so that it can be applied to nchannel or p-channel transistors without confusion. |VT |= |VT0 | + γ 2|φF| + |vSB| − 2|φF| CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 5 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) For p-channel device, |VT0 | = 0.7 K' = 50µ γ = 0.57 2|φF| = 0.8 The table below shows the value of VGS and VSB for each value of VS VS (volts) 0.0 1.0 2.0 3.0 4.0 5.0 Using VS = 5, calculate VT VGS (volts) 0 1 2 3 4 5 VBS (volts) 5 4 3 2 1 0 |VT |= |VT0 | + γ 2|φF| + |vSB| − 2|φF| = 0.7 + 0.57[ 0.8 + 0.0 − 0.8] = 0.7 Calculate ron rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 50µ × 1 4(5 − 0.7 − 0) = 1163 Ω Repeat for VS = 4 |VT | = 0.7 + 0.57[ 0.8 + 1.0 − 0.8] = 0.955 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 50µ × 4(4 1 − 0.955 − 0) = 1642 Ω Repeat for VS = 3 |VT | = 0.7 + 0.57[ 0.8 + 2.0 − 0.8] = 1.144 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 6 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 50µ × 4(3 1 − 1.144 − 0) = 2694 Ω Repeat for VS = 2 |VT | = 0.7 + 0.4[ 0.8 + 3.0 − 0.8] = 1.301 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 50µ × 4(2 1 − 1.301 − 0) = 7145 Ω Repeat for VS = 1 |VT | = 0.7 + 0.57[ 0.8 + 4.0 − 0.8] = 1.439 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 50µ × 4(1 1 − 1.439 − 0) = -11390 Ω The negative sign means that the device is off due to the fact that VGS < VT Thus rON = infinity Repeat for VS = 0 |VT | = 0.7 + 0.57[ 0.8 + 5.0 − 0.8] = 1.563 rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = 50µ × 4(0 1 − 1.563 − 0) = 3199 Ω The negative sign means that the device is off due to the fact that VGS < VT Thus rON = infinity Summary: CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 7 VS (volts) 0.0 1.0 2.0 3.0 4.0 5.0 R (ohms) infinity infinity 7145 2694 1642 1163 Problem 4.1-4 The circuit shown in Fig. P4.3 illustrates a complementary MOS resistor with an nchannel W/L of 2µm/1µm and a p-channel W/L of 4µm/1µm. Using Table 3.1-2 model parameters, calculate the small-signal on resistance of the complementary MOS resistor at various values for VS and fill in the table below. Note that the most positive supply voltage is 5 volts. 5 Volts I = 0.0 VS Figure P4.3 Summary for n-channel device from Problem 4.1-2: VS (volts) 0.0 1.0 2.0 3.0 4.0 5.0 R (ohms) 1057 1460 2299 5253 infinity infinity Summary for p-channel device from Problem 4.1-3: CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 8 VS (volts) 0.0 1.0 2.0 3.0 4.0 5.0 R (ohms) infinity infinity 7145 2694 1642 1163 Table showing both and their parallel combination: VS (volts) 0.0 1.0 2.0 3.0 4.0 5.0 R (ohms), n-channel 1057 1460 2299 5253 infinity infinity R (ohms), p-channel infinity infinity 7145 2694 1642 1163 R (ohms), parallel 1057 1460 1739 1781 1642 1163 Problem 4.1-5 For the circuit in Figure P4.1-5(a) assume that there are NO capacitance parasitics associated with M1. The voltage source vin is a small-signal value whereas voltage source Vdc has a dc value of 3 volts. Design M1 to achieve the frequency response shown in Figure P4.1-5(b). CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 9 5 Volts vin Vdc 0 dB -6 dB vout/vin -12 dB -18 dB -24 dB M1 2 pF vout (a) 2.5 MHz 5 MHz 10 MHz 20 MHz 40 MHz 80 MHz 160 MHz (b) Figure P4.4 f(-3 dB) = 20 MHz, thus w = 40π M rad/s Note that since no dc current flows through the transistor, the dc value of the drain-source voltage is zero. rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = L K'W(|VGS| − |VT|) Then 1 RC = K'W(|VGS| LC − |VT|) = 40 π Μ rad/s CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 10 W L = C × 40 π K'(|VGS| × 106 − |VT|) Calculate VT due to the back bias. VT = VT0 + γ |2φf| + |vbs| - |2φf| = 0.7 + 0.4 0.7 + 3.0 - 0.7 = 1.135 W L = 40 π 110 × × 106 × 2 × 10-12 10-6 (2 − 1.135) = 2.64 Problem 4.1-6 Using the result of Problem 4, calculate the frequency response resulting from changing the gate voltage of M1 to 4.5 volts. Draw a Bode diagram of the resulting frequency response. rON = 1 ∂ID/∂VDS = K'W(|VGS| L − |VT| − |VDS|) = L K'W(|VGS| − |VT|) Calculate VT due to the back bias (same as previous problem). VT = VT0 + γ |2φf| + |vbs| − |2φf| = 0.7 + 0.4 0.7 + 3.0 − 0.7 = 1.135 rON = 1 ∂ID/∂VDS = L K'W(|VGS| − |VT|) rON = 110 × 10-6 × 1 2.64(4.5 − 3 − 1.135) == 9434 Ω ω(-3 dB) = 1 rONC = 1 9.434 × 103 × 2 × 10-12 = 53 × 106 rad/s f(-3 dB) = 8.44 × 106 Hz CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 11 0 dB -6 dB vout/vin -12 dB -18 dB -24 dB 2.5 MHz 5 MHz 10 MHz 20 MHz 40 MHz 80 MHz 160 MHz 8.44 MHz Figure P4.1-6 Problem 4.1-7 Consider the circuit shown in Fig. P4.1-7 Assume that the slow regime of charge injection is valid for this circuit. Initially, the charge on C1 is zero. Calculate vOUT at time t1 after φ1 pulse occurs. Assume that CGS0 and CGD0 are both 5 fF. C1=30 fF. You cannot ignore body effect. L = 1.0 µm and W = 5.0 µm. 5V φ1 0V t1 φ1 M1 2.0 C1 vout CHANGE PROBLEM: Figure P4.1-7 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 12 Use model parameters from Table 3.1-2 and 3.2-1 as required U = 5 × 108 The equation for the slow regime is given as Verror = W · CGD0 + CL Cchannel 2 π U CL 2β + W · CGD0 CL (VS + VT − VL ) and VS = 2.0 volts VL = 0.0 volts VT is calculated below The source of the transistor is at 2.0 volts, so the threshold for the switch must be calculated with a back-gate bias of 2.0 volts. VT = VT0 + γ |2φf| + |vbs| − |2φf| = 0.7 + 0.4 0.7 + 2.0 − 0.7 = 1.023 VT = 1.023 Cchannel = W × L × Cox = 5 × 10-6 × 1 × 10-6 × 24.7 × 10-4 = 12.35 × 10-15 F VHT = VH − VS − VT = 5 − 2 − 1.023 = 1.98 Verify slow regime: βV2HT 2CL = 110 × 10-6 × 3.91 2 × 30 × 10-15 = 7.17 × 109 >> 5 × 108 thus slow regime Verror = W · CGD0 + CL Cchannel 2 π U CL 2β + W · CGD0 CL (VS + VT − VL ) Verror = 5 × 10-6 × 220 × 10-12 + 30 × 10-15 12.35 × 2 10-15 × CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 13 × π × 5 × 108 × 30 × 10-15 2×110 × 10-6 + 5 × 10-6 30 · 220 × 10-12 × 10-15 (2 + 1.023 − 0 ) = 0.223 Vout(t1) = 2.0 − Verror = 2.0 − 0.223 = 1.777 Problem 4.1-8 In Problem 4.1-7, how long must φ1 remain high for C1 to charge up to 99% of the desired final value (2.0 volts)? rON = 1 ∂ID/∂VDS = L K'W(|VGS| − |VT|) rON = 5 × 110 × 1 10-6 × (3 − 1.135) = 972.3 Ω rON C1 = 972.3 × 30 × 10-15 = 29.2 ps vO(t) C1 = 2 × ( 1 − e-t/RC ) = 0.99 × 2.0 e-t/RC ) = 0.01 t = −RC ln(0.01) = 134.3 ps Problem 4.1-9 In Problem 4.1-7, the charge feedthrough could be reduced by reducing the size of M1. What impact does reducing the size (W/L) of M1 have on the requirements on the width of the φ1 pulse width? The width of φ1 must increase since a decrease in size (and thus feedthrough) increases resistance and thus the time required to charge the capacitor to the desired final value. Problem 4.1-10 Considering charge feedthrough due to slow regime only, will reducing the magnitude of the φ1 pulse impact the resulting charge feedthrough? What impact does reducing the magnitude of the φ1 pulse have on the accuracy of the voltage transfer to the output? CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 14 Reducing the magnitude does not effect the result of feedthrough in the slow regime because all of the charge except residual channel charge (at the point where the device turns off) returns to the voltage source. Decreasing the magnitude does effect the accuracy because the time required to charge the capacitor is increased due to higher resistance when the device is on. Problem 4.1-11 Repeat Example 4.1-1 with the following conditions. Calculate the effect of charge feedthrough on the circuit shown in Fig. 4.1-9 where Vs = 1.5 volts, CL = 150 fF, W/L = 1.6µm/0.8µm, and VG is given for two cases illustrated below. The fall time is 0.1ns instead of 8ns. Case 1: 0.1ns fall time VT = VT0 + γ |2φf| + |vbs| − |2φf| = 0.7 + 0.4 0.7 + 1.5 − 0.7 = 0.959 VHT = VH − VS − VT = 5 − 1.5 − 0.959 = 2.541 U = VH t = 0.1 5 × 10-9 = 50 × 109 βVH2 T 2CL = 2×110 × 10-6 × 2.5412 2 × 150 × 10-15 = 4.735 × 109 << 50 × 109 thus fast mode Cchannel = W × L × Cox = 1.6 × 10-6 × 0.8 × 10-6 × 24.7 × 10-4 = 3.162 × 10-15 F Verror = W·CGD0 + Cchannel 2 CL VHT − β VH3T 6U CL + W·CGD0 CL (VS + VT − VL ) Verror = 1.6 × 10-6 × 220 × 10-12 + 150 × 10-15 3.162 × 2 10-15 2.541 − 220 × 10-6 × 2.5413 6×50 ×109 ×150 × 10-15 + + 1.6 × 10-6 150 ×·220 × × 10-15 10-12 (1.5 + 0.96 − 0 ) Verror = (12.89 × 10-3) (2.46) + 1.267 × 10-3 = 32.98 × 10-3 Vout(t1) = 2.0 − Verror = 2.0 − 32.98 × 10-3 = 1.967 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 15 Case 2: 8ns fall time VT = VT0 + γ |2φf| + |vbs| - |2φf| = 0.7 + 0.4 0.7 + 1.5 - 0.7 = 0.959 VHT = VH − VS − VT = 5 - 1.5 - 0.959 = 2.541 vG = VH − Ut U = VH t = 8 5 × 10-9 = 625 × 106 βVH2 T 2CL = 2×110 2× × 10-6 × 6.457 150 × 10-15 = 4.735 × 109 >> 625 × 106 thus slow regime Verror = W · CGD0 + CL Cchannel 2 π U CL 2β + W · CGD0 CL (VS + VT − VL ) and VS = 1.5 volts VL = 0.0 volts Cchannel = W × L × Cox = 1.6 × 10-6 × 0.8 × 10-6 × 24.7 × 10-4 = 3.162 × 10-15 F Verror = W · CGD0 + CL Cchannel 2 π U CL 2β + W · CGD0 CL (VS + VT − VL ) Verror = 1.6 × 10-6 × 220 × 10-12 + 150 × 10-15 3.162 × 2 10-15 × Error! Vout(t1) = 2.0 − Verror = 2.0 − 0.0163 = 1.984 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 16 Problem 4.1-12 Figure P4.1-12 illustrates a circuit that contains a charge-cancellation scheme. Design the size of M2 to minimize the effects of charge feedthrough. Assume slow regime. 5V φ1 0V t1 φ1 φ1 M1 M2 2.0 C1 vout Figure P4.1-12 When U is small, the expression for the charge feedthrough due to M1 in the slow regime can be approximated as Verror = W · CGD0 + CL Cchannel 2 π U CL 2β + W · CGD0 CL (VS + VT − VL ) Verror ≅ W · CGD0 CL (VS + VT − VL ) Because M2 is driven by the inversion of φ1 , charge is injected in the opposite direction from that of M1. The charge injected is due to the overlap capacitance and due to the channel capacitance. The overlap capacitance from the drain or source is simply Coverlap = W · CGD0 Because both the drain and the source are involved, the charge injected from both must be added. Capacitance due to the channel once M2 channel inverts is simply CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 17 Cchannel = W · L · Cox Consider the voltage on C1 due to charge injected from the overlap and the channel separately. The error voltage due to overlap is approximated to be Verror_overlap ≅ 2 · W · CGD0 CL (VS + VT − VL ) Notice the factor of “2” to account for the overlap from the drain and the source. The error voltage due to the channel is approximated to be Verror_channel ≅ Cchannel CL (5 − VS − VT ) where the “5” comes from the maximum value of φ1 . If VL is zero, then the total error voltage due to M2 alone is approximately Verror_M2 ≅ 2 · W2 · CGD0 CL (VS + VT ) + Cchannel CL (5 − VS − VT ) Since the error voltage due to M2 is in the opposite direction to that due to M1 then to minimize the overall effect due to charge injection, the error due to M1 and M2 should be made equal. Therefore W1 · CGD0 CL (VS + VT ) = 2 · W2 · CGD0 CL (VS + VT ) + Cchannel CL (5 − VS − VT ) (W1 · CGD0) (VS + VT ) = (2 · W2 · CGD0) (VS + VT ) + Cchannel_M2 (5 − VS − VT ) (W1 · CGD0) (VS + VT ) = (2 · W2 · CGD0) (VS + VT ) + W2 L2COX (5 − VS − VT ) W1 = 2 · W2 + W2 L2COX CGD0 (5 − VS − VT (VS + VT ) ) W1 = W2 2 + L2COX (5 − VS CGD0 (VS + − VT VT ) ) CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 18 W2 = W1 2 + L2COX (5 − VS CGD0 (VS + − VT VT ) ) -1 Design L2 to be the minimum allowed device length and calculate W2. Problem 4.3-1 Figure P4.3-1 illustrates a source-degenerated current source. Using Table 3.1-2 model parameters calculate the output resistance at the given current bias. 2/1 VGG 100K 10 µA + vOUT - Figure P4.3-1 The small-signal model of this circuit is shown below gmvgs gmbsvbs + r vs - First calculate dc terminal conditions. iout + rds vout - CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 19 ID = 10 µA VS = ID × R = 10 × 10-6 × 100 × 103 = 1 volt VS = VSB rout = vout iout = r + rds + [(gm + gmbs)rds]r ≅ (gmrds)r gm ≅ (2K'W/L)|ID| = 2× 110×10-6 ×2/1 × 10×10-6 = 66.3 ×10-6 gmbs = gm 2(2|φF| γ + VSB)1/2 = 66.3×10-6 0.4 2(0.7 + 1)1/2 = 10.17×10-6 gds ≅ ID λ = 10×10-6 × 0.04 = 400×10-9 rds = 1 gds = 2.5×106 thus rout = 100 × 103 + 2.5×106 + [(66.3 ×10-6 + 10.17×10-6) 2.5×106] 100 × 103 = 21.7×106 rout = 21.7×106 Problem 4.3-2 Calculate the minimum output voltage required to keep device in saturation in Problem 4.3-1. The minimum voltage across drain and source while remaining in saturation is VON VON = 2iD β = 2 × 10 ×10-6 2 × 110 ×10-6 = 10 110 = 0.302 The minimum drain voltage is VD(min) = VS(min) + VON = 1 + 0.302 = 1.302 Problem 4.3-3 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 20 Using the cascode circuit shown in Fig. P4.3-3, design the W/L of M1 to achieve the same output resistance as the circuit in Fig. P4.3-1. Ignore body effect. 10 µA + 2/1 VGC M2 vOUT M1 - Figure P4.3-3 rDS1 = 1 gm1 1 gm = 100 kΩ gm1 = 1 100 kΩ ≅ 2K'(W/L)1ID = 2× 110×10-6 × 10×10-6 (W/L)1 WL1 = 10-5 2 1 2× 110×10-6 × 10×10-6 = 22 From the previous problem, gm2 = 66.3 ×10-6 rds2 = 2.5×106 Note that the terminal conditions of M2 must change in order to support the larger gate voltage required on M1. This will be addressed in the next problem. Problem 4.3-4 Calculate the minimum output voltage required to keep device in saturation in Problem 4.3-3. Compare this result with that of Problem 4.3-2. Which circuit is a better choice in most cases? CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 21 First calculate the gate voltage of M1 VGS1 = 2ID K'(W/L) + VT = 20 110 µ µ (1/22) + 0.7 = 2.7 From Problem 4.3-2, VON2 = 0.302 Therefore, the minimum output voltage to keep devices in saturation is Vout(min) = VGS1+ VON2 = 2.7 + .302 = 3.02 In for the circuit in problem 4.3-2, the minimum output voltage is lower than the circuit in 4.3-3 and is thus generally a better choice. Problem 4.3-5 Calculate the output resistance and the minimum output voltage, while maintaining all devices in saturation, for the circuit shown in Fig. P4.3-5. Assume that IOUT is actually 10µA. Simulate this circuit using SPICE LEVEL 3 model (Table 3.4-1) and determine the actual output current, IOUT . Use Table 3.1-2 for device model information. 10 µA iOUT M2 5/1 M4 5/1 M1 M3 + vOUT 5/1 5/1 - Figure P4.3-5 First calculate node voltages and currents. Assume a near perfect current mirror so that the current in all devices is 10 µA. Calculate node voltages. VGS3 = VG3 = 2iD β + VT = 2 × 10 ×10-6 5 × 110 ×10-6 + 0.7 = 20 550 + 0.7 = 0.891 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 22 VSB2 = VG3 = 0.891 VDS1 = VG3 + VGS4 − VGS2 because all devices are matched. gm2 = gm4 ≅ (2K'W/L)|ID| = 2× 110×10-6 ×5/1 × 10×10-6 = 104.9 ×10-6 gmbs2 =gmbs4 = gm2 2(2|φF| γ + VSB)1/2 = 104.9 ×10-6 2(0.7 0.4 + 0.891)1/2 = 16.63×10-6 rout = vout iout = rds1 + rds2 + [(gm2 + gmbs2)rds2] rds1 gds1 = gds2 ≅ ID λ = 10×10-6 × 0.04 = 400×10-9 rds1 =rds2 = 1 gds = 2.5×106 rout = rds1 + rds2 + [(gm2 + gmbs2)rds2] rds1 = 2.5×106+ 2.5×106 rout = 2.5×106+ 2.5×106 + [(104.9 ×10-6 + 16.63×10-6) 2.5×106] 2.5×106 rout = 764×106 Spice Simulation 5 VPLUS IBIAS 10 µA iOUT 4 M2 5/1 M4 5/1 3 M1 1 M3 5/1 5/1 2 VOUT Problem 4.3-5 M4 4 4 3 0 nch w=5u l=1u M3 3 3 0 0 nch w=5u l=1u M2 2 4 1 0 nch w=5u l=1u Spice simulation circuit CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 23 m1 1 3 0 0 nch w=5u l=1u ibias 5 4 10u vplus 5 0 5 vout 2 0 3 .op .model nch NMOS + LEVEL = 3 + VTO = 0.70 + UO = 660 + TOX = 1.40E-08 + NSUB = 3E+16 + XJ = 2.0e-7 + LD = 1.6E-08 + NFS = 7e+11 + VMAX = 1.8e5 + DELTA = 2.40 + ETA = 0.1 + KAPPA = 0.15 + THETA = 0.1 + CGDO = 2.20E-10 + CGSO = 2.20E-10 + CGBO = 7.00E-10 + MJ = 0.50 + CJSW = 3.50E-10 + MJSW = 0.38 .model pch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ .end PMOS = = = = = = = = = = = = = = = = = 3 -0.70 210 1.40E-08 6.00e16 2.0e-7 1.5E-08 6E+11 2.00e5 1.25 0.1 2.5 0.1 2.20E-10 2.20E-10 7.00E-10 0.50 DC Operating Point Analysis, 27 deg C Fri Aug 30 23:00:34 2002 ------------------------------------------------------------------------ >>> i(vout) = -1.0157e-005 i(vplus) = -1.0000e-005 v(0) = 0.0000e+000 v(1) = 8.5259e-001 v(2) = 3.0000e+000 v(3) = 8.1511e-001 v(4) = 1.7609e+000 v(5) = 5.0000e+000 Problem 4.3-6 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 24 Calculate the output resistance, and the minimum output voltage, while maintaining all devices in saturation, for the circuit shown in Fig. P4.3-6. Assume that IOUT is actually 10µA. Simulate this circuit using SPICE Level 3 model (Table 3.4-1) and determine the actual output current, IOUT . Use Table 3.1-2 for device model information. 10 µA 10 µA M4 1/1 M3 4/1 iOUT M2 4/1 M1 + vOUT 4/1 - Figure P4.3-6 First calculate node voltages and currents. Assume a near perfect current mirror so that the current in all devices is 10 microamps. Calculate node voltages. VGS4 = VG4 = 2iD β + VT = 2 × 10 ×10-6 1 × 110 ×10-6 + 0.7 = 20 110 + 0.7 = 1.126 VGS3 = VG3 = 2iD β + VT = 2 × 10 ×10-6 4 × 110 ×10-6 + 0.7 = 20 440 + 0.7 = 0.913 -- VGS of M2 must be solved taking into account the back-bias voltage and its effect on threshold voltage. The following equations relate to M2 terminals (subscripts dropped for simplicity) VGS = VG − VS = 2iD β + VT0 + γ |2φf| + vSB − |2φf| Noting that the bulk terminal is ground we get VG − VS = 2iD β + VT0 + γ |2φf| + vS − | 2φf| CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 25 VG − VS − 2iD β − VT0 + γ |2φf| = γ |2φf| + vS VG − 2iD β − VT0 + γ |2φf| − VS = γ |2φf| + vS A − VS = γ |2φf| + vS where A = VG − 2iD β − VT0 + γ |2φf| (A − VS)2 = γ2 |2φf| + vS A2 − 2AVS + 2 VS = γ2 |2φf| + vS V2S − VS( 2A + γ2) + A2 − γ2|2φf| = 0 Now solving numerically: A = VG − 2iD β − VT0 + γ |2φf| = 1.126 − 20 440 − 0.7 + 0.4 0.7 = 0.5475 V2S − VS [2(0.5475) + 0.42] + 0.54752 − 0.42( 0.7 ) = 0 2 VS − VS (1.255) + 0.1877 = 0 VS = 0.1736 VON = 2iD β = 20 440 = 0.2132 VOUT (min) = VON + VS = 0.2132 + 0.1736 = 0.3868 Small signal calculation of output resistance: gm1 = gm2 ≅ (2K'W/L)|ID| = 2× 110×10-6 ×4/1 × 10×10-6 = 93.81 ×10-6 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 26 gmbs2 = gm2 2(2|φF| γ + VSB)1/2 = 93.81 ×10-6 2(0.7 0.4 + 0.1736)1/2 = 20.07×10-6 rout = vout iout = rds1 + rds2 + [(gm2 + gmbs2)rds2] rds1 gds1 = gds2 ≅ ID λ = 10×10-6 × 0.04 = 400×10-9 rds1 =rds2 = 1 gds = 2.5×106 rout = rds1 + rds2 + [(gm2 + gmbs2)rds2] rds1 = 2.5×106+ 2.5×106 rout = 2.5×106+ 2.5×106 + [(93.81 ×10-6 + 20.07×10-6) 2.5×106] 2.5×106 rout = 717×106 Spice Simulation 5 VPLUS 10 µA IBIAS1 10 µA 3 IBIAS2 M4 1/1 4 M3 4/1 iOUT M2 4/1 1 M1 2 VOUT 4/1 Spice simulation circuit Problem 4.3-6 M4 3 3 0 0 nch w=1u l=1u M3 4 4 0 0 nch w=4u l=1u M2 2 3 1 0 nch w=4u l=1u m1 1 4 0 0 nch w=4u l=1u ibias1 5 3 10u ibias2 5 4 10u vplus 5 0 5 vout 2 0 3 .op CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 27 .model nch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ + CJSW + MJSW NMOS = = = = = = = = = = = = = = = = = = = 3 0.70 660 1.40E-08 3E+16 2.0e-7 1.6E-08 7e+11 1.8e5 2.40 0.1 0.15 0.1 2.20E-10 2.20E-10 7.00E-10 0.50 3.50E-10 0.38 .model pch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ .end PMOS = = = = = = = = = = = = = = = = = 3 -0.70 210 1.40E-08 6.00e16 2.0e-7 1.5E-08 6E+11 2.00e5 1.25 0.1 2.5 0.1 2.20E-10 2.20E-10 7.00E-10 0.50 Problem 4.3-6 DC Operating Point Analysis, 27 deg C Mon Sep 02 16:24:37 2002 ------------------------------------------------------------------------ >>> i(vout) = -8.1815e-006 i(vplus) = -2.0000e-005 v(0) = 0.0000e+000 v(1) = 3.2664e-001 v(2) = 3.0000e+000 v(3) = 1.1450e+000 v(4) = 8.4156e-001 v(5) = 5.0000e+000 Problem 4.3-7 Design M3 and M4 of Fig. P4.3-7 so that the output characteristics are identical to the circuit shown in Fig. P4.3-6. It is desired that IOUT is ideally 10µA. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 28 5µA 5µA M4 M3 iOUT M2 4/1 M1 + vOUT 4/1 - Figure P4.3-7 By comparison with the circuit in P4.3-6, the output transistors are identical but the bias currents are halved. In order to achieve the same gate voltages on M1 and M2, the W/L of M3 and M4 must be half of those in Fig P4.3-6. This is illustrated in the following equations. VGS = 2iD K'(W/L) + VT VGS (5µA) = 2(5µA) K'(W/L)5µA + VT = VGS (10µA) = 2(5µA) K'(W/L)5µA = 2(10µA) K'(W/L)10µA 5µA (W/L)5µA = 10µA (W/L)10µA (W/L)10µA (W/L)5µA = 10µA 5µA = 2 (W/L)10µA = 2(W/L)5µA Thus for Fig. 4.3-7 (W/L)4 = 1/2 (W/L)3 = 2/1 Problem 4.3-8 2(10µA) K'(W/L)10µA + VT CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 29 For the circuit shown in Fig. P4.3-8, determine IOUT by simulating it using SPICE Level 3 model (Table 3.4-1). Use Table 3.1-2 for device model information. Compare the results with the SPICE results from Problem 4.3-6. 10 µA 10 µA M4 1/1 4/1 M3 iOUT M2 4/1 M1 + vOUT 4/1 4/1 - Figure P4.3-8 5 VPLUS IBIAS2 IBIAS1 10 µA 10 µA 4 3 M5 M4 1/1 6 M3 4/1 iOUT M2 4/1 1 M1 2 VOUT 4/1 Problem 4.3-8 M5 4 3 6 0 nch w=4u l=1u M4 3 3 0 0 nch w=1u l=1u M3 6 4 0 0 nch w=4u l=1u M2 2 3 1 0 nch w=4u l=1u m1 1 4 0 0 nch w=4u l=1u ibias1 5 3 10u ibias2 5 4 10u vplus 5 0 5 vout 2 0 3 Spice simulation circuit CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 30 .op .model nch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ + CJSW + MJSW NMOS = = = = = = = = = = = = = = = = = = = 3 0.70 660 1.40E-08 3E+16 2.0e-7 1.6E-08 7e+11 1.8e5 2.40 0.1 0.15 0.1 2.20E-10 2.20E-10 7.00E-10 0.50 3.50E-10 0.38 .model pch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ .end PMOS = = = = = = = = = = = = = = = = = 3 -0.70 210 1.40E-08 6.00e16 2.0e-7 1.5E-08 6E+11 2.00e5 1.25 0.1 2.5 0.1 2.20E-10 2.20E-10 7.00E-10 0.50 Problem 4.3-8 DC Operating Point Analysis, 27 deg C Mon Sep 02 18:01:39 2002 ------------------------------------------------------------------------ i(vout) = -1.0233e-005 i(vplus) = -2.0000e-005 v(0) = 0.0000e+000 v(1) = 3.0942e-001 v(2) = 3.0000e+000 v(3) = 1.1450e+000 v(4) = 8.6342e-001 v(5) = 5.0000e+000 v(6) = 2.4681e-001 Notice that the output current is more accurate than that simulated in problem 4.3-6. This is because M3 and M1 have more closely matched terminal conditions. Problem 4.4-1 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 31 Consider the simple current mirror illustrated in Fig. P4.20. Over process, the absolute variations of physical parameters are as follows: Width variation +/- 5% Length variation +/- 5% K’ variation +/- 5% VT variation +/- 5mV Assuming that the drain voltages are identical, what is the minimum and maximum output current measured over the process variations given above. 20 µA iO 3/1 + VDS1 - M1 + VGS - 3/1 M2 + VDS2 - Figure P4.4-1 iD = K' W L (vGS − VT )2 and vGS = 2iD K'(W/L) + VT Thus, combining these expressions for the circuit in Fig. P4.4-1, iO = K'2 WL 2 (vGS2 − VT2 )2 iO = K'2 WL 2 2×20×10-6 K'1(W/L)1 2 + VT1 − VT2 Minimum and Maximum occurs under the following conditions K'1 K'2 (W/L)1 (W/L)2 VT1 VT2 iO(min) Max Min Max Min Min Max CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 iO(max) Min Max Min Max Max 32 Min Substituting in the expression for drain current yields: K'1 K'2 (W/L)1 (W/L)2 27.82 µ 115.5 µ 104.5 µ 3.316 2.714 56.93 µ 104.5 µ 115.5 µ 2.714 3.316 VT1 0.695 0.705 VT2 0.705 0.695 Problem 4.4-2 Consider the circuit in Fig. P4.21 where a single MOS diode (M2) drives two current mirrors (M1 and M3). A signal (vsig) is present at the drain of M3 (due to other circuitry not shown). What is the effect of vsig on the signal at the drain of M1, vOUT ? Derive the transfer function vsig(s)/ vOUT(s). You must take into account the gate-drain capacitance of M3 but you can ignore the gate-drain capacitance of M1. Given that IBIAS=10µA, W/L of all transistors is 2µm/1µm, and using the data from Table 3.1-2 and Table 3.2-1, calculate vOUT for vsig =100mV at 1MHz. IBIAS IBIAS IBIAS + vOUT M1 M2 - vsig M3 Figure P4.4-2 The small-signal model for Fig. 4.4-2 is CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 33 Cgd3 vg1 vsig gm3vgs3 r3 Cgs1+Cgs2 1/gm2 gm1vg1 vOUT r1 Cgd3 vsig vg1 Z gm1vg1 vOUT r1 vg1 = vsig Z + Z 1/sCgd3 vOUT = -gm1 r1 vg1 = -gm1 r1 Z +Z1v/ssiCg gd3 vOUT vsig = -gm1 r1 s s Cgd3 (Cgd3+Cgs1+Cgs2) + gm1 vvOsUigT((ωω)) = -gm1 r1 ω Cgd3 [ω (Cgd3+Cgs1+Cgs2)]2 + g2m1 The transfer function has the following poles and zeros. ωp = Cgd3 + gm1 Cgs1 + Cgs2 ωz = gm1 Cgd3 r1 = 1 λid = 0.04 × 1 10 × 10-6 = 2.5 × 106 gm1 = 2K'(W/L)iD = 2 × 110 × 10-6 × 2× 10 × 10-6 = 66.33 × 10-6 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 34 Cgs1 = 2 3 Cox × W × L + CGSO × W = 3.29 fF + 0.44 fF = 3.73 fF Cgs1 = Cgs2 Cgd3 = CGSO × W = 0.44 fF Substituting numerical values yields: vvOsUigT((ωω)) = 66.33 × 10-6 × 2.5 × 106 × × 6.28 × 106 × 0.44 × 10-15 [6.28 × 106 (0.44 × 10-15+ 3.73 × 10-15+ 3.73 × 10-15)]2 + (66.33 × 10-6)2 vvOsUigT((ωω)) = 6.91 × 10-3 at ω = 6.28 Mrps For vsig = 100 mV vOUT = vsig × 6.91 × 10-3 = 100 × 10-3 × 6.91 × 10-3 = 691 µV Problem 4.5-1 Show that the sensitivity of the reference circuit shown in Fig. 4.5-2(b) is unity. βP 2 VDD − VREF − | VTP | 2 = βN 2 2 VREF − VTN ββPN1/2 VDD − VREF − | VTP | = VREF − VTN ββPN1/2 VDD − | VTP | + VTN VREF = 1 + ββPN 1/2 When: βP = βN , | VTP | = VTN then CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 35 VDD VREF = 2 ∂VREF ∂ VDD = ?? Use a small-signal model to simplify analysis. VDD gmp + gmn VREF - ∂VREF ∂VDD = vREF vDD Figure P4.5-1 ∂VREF ∂VDD = 1/gmN 1/gmN + 1/gmP = gmP gmN + gmP ∂VREF ∂VDD = 2βP 2βP ID + ID 2βN ID = ID = 1/2 ID + ID VREF S = ∂∂VVRDEDF VVRDEDF = 11//22 = 1 VDD Problem 4.5-2 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 36 Fig P4.5-2 illustrates a reference circuit that provides an interesting reference voltage output. Derive a symbolic expression fo VREF . 5 volts I M4 M3 4/1 1/1 4/1 M1 M2 VREF 4/1 Fig. P4.5-2 VGS1 + VGS3 − VGS4 = VREF VREF = VON1 + VT1 + VON3 + VT3 − VON4 − VT4 VT4 = VT3 VON1 = VON3 VON4 = 2VON3 VREF = 2VON1 + VT1 + VT3 − 2VON1 − VT3 = VT1 VREF = VT1 Problem 4.5-3 Figure P4.5-3 illustrates a current reference. The W/L of M1 and M2 is 100/1. The resistor is made from n-well and its nominal value is 400kΩ at 25 °C. Using Table 3.1-2 and an n-well resistor with a sheet resistivity of 1kΩ/sq. ± 40% and temperature coefficient of 8000 ppm/°C, calculate the total variation of output current seen over process, temperature of 0 to 70 °C, and supply voltage variation of ± 10%. Assume that the temperature coefficient of the threshold voltage is –2.3 mV/°C. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 37 5 volts R Iout M1 M2 Fig. P4.5-3 VDD − IREF = 2IRβEF+ VT R 1 R 2IREF β = VDD − R VT − IREF Define V = VDD − VT 2IREF β = (V − IREF R)2 IR2EF R2 − 2IREF VR + 1 β + V2 = 0 IR2EF − 2IREF V R + 1 βR2 + V2 R2 = 0 IREF = V R + 1 βR2 ± 1 R 2V 1 βR + β2R2 IREF = VDD − R VT + 1 βR2 ± 1 R 2(VDD − βR VT) + 1 β2R2 Rmin (25°C) = 500kΩ × (1 − 0.4) = 300kΩ Rmax (25°C) = 500kΩ × (1 + 0.4) = 700kΩ R(T) = R(T0) × (1 + TC×∆T) CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 38 Rmin(0 °C) = Rmin(25 C) × ( 1 + 8000×10-6 × -25) = 300 × 0.8 = 240kΩ Rmax(70 °C) = Rmax(25 C) × ( 1 + 8000×10-6 × 45) = 700 × 1.36 = 952kΩ VT(min) (25°C) = 0.7 − 0.15 = 0.55 VT(max) (25°C) = 0.7 + 0.15 = 0.85 VT(min) (70°C) = 0.55 − 45 × 0.0023 = 0.4465 VT(max) (0°C) = 0.85 + 25 × 0.0023 = 0.9075 K'(max) (25°C) = 110 × 10-6 × 1.1 = 121 × 10-6 K'(min) (25°C) = 110 × 10-6 × 0.9 = 99 × 10-6 K' (T) = K' (T0) × T -1.5 T0 K'(min) (70°C) = 99 × 10-6 × 324938-1.5 = 80.17 × 10-6 K'(max) (0°C) = 121 × 10-6 × 227938-1.5 = 138 × 10-6 Minimum and Maximum occurs under the following conditions K' VT VDD R IREF(min) Max Max Min Max IREF(max) Min Min Max Min K' VT VDD R IREF(min) 80.17 × 10-6 0.9075 4.5 952 K IREF(max) 138 × 10-6 0.4465 5.5 240 K CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 39 Plugging in these minimums and maximums yields the following over process and temperature: IREF(min) = 3.81 × 10-6 IREF(max) = 21.3 × 10-6 Problem 4.5-4 Figure 4.5-4 illustrates a current reference circuit. Assume that M3 and M4 are identical in size. The sizes of M1 and M2 are different. Derive a symbolic expression for the output current Iout . VDD M4 M3 R M2 M1 Iout M5 Fig. P4.5-4 Assume that M3 and M4 make a perfect current mirror, as does M2 and M5. VGS2 − VGS1 + IR = 0 VT1 + VON1 − VT2 − VON2 = IR IR = VON1 − VON2 = 2iD K'(W/L)1 − 2iD K'(W/L)2 IR = 2iD K' 1 (W/L)1 − 1 (W/L)2 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 40 I= 1 R 2iD K' 1 (W/L)1 − 1 (W/L)2 Problem 4.5-5 Find the small-signal output resistance of Fig. 4.5-3(b) and Fig. 4.5-4(b). VDD VDD I R I R + R1 + R1 VREF VREF R2 R2 - - Figure 4.5-3(b) + Vπ rπ - R2 R1 R Figure 4.5-4(b) IT VT gmVπ rο CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 41 IT R1 + Vg R2 - R VT gmVg rο Part a: vπ = vt rπ rπ || R1 || R1 + R2 it = rπ || vt R1 + R2 + vt R + gm vπ + vt rο it = vt rπ || 1 R1 + R2 + 1 R + gm (rπ rπ || R1 || R1) + R2 + 1 rο vt it = R rο + rο (rπ || R1+ R rο (rπ || R2) + R rο R1 gm + R2 (rπ || ) R1) + R (rπ || R1 + R2) if rπ || R1 >> R2 then vt it = 1 gm Part b: vG = vt R2 R1 + R2 it = gm vG + vt rο + vt vt R + R1 + R2 it vt = gm R2 R1 + R2 + 1 rο + 1 1 R + R1 + R2 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 42 if R2 >> R1 then it vt = gm + 1 rο + 11 R + R2 1 1 1 if gm >> R2, gm >> rο , gm >> R then it vt = gm Problem 4.5-6 Using the reference circuit illustrated in Fig. 4.5-3(b), design a voltage reference having VREF=2.5 when VDD=5.0. Assume that IS = 1 fA and βF=100. Evaluate the sensitivity of VREF with respect to VDD. VDD I + VREF - R I1 R1 IB R2 Figure 4.5-3 (b) IR = 2.5 Choose R = 250 kΩ, I = 10µA I = I1 + IE choose IE = 1 µA, and I1 = 9 µA With β=100, base current is insignificant and will be ignored. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 43 I1 = 2.5 R1 + R2 = 9 µA = 2.5 R1 + R2 R1 + R2 = 277.8 kΩ VREF = I1 R2 + VEB 2.5 = 9 µA R2 + 0.0259 × ln11 µfAA R2 = 218.1 kΩ R1 = 59.64 kΩ VEB = VREF R1 R1+ R2 VREF = VEBR1+R1R2 = R1+R1R2Vt lnVDDR−IVSREF VREF SVDD = ∂∂VVRDEDF VVRDEDF = VVRDEDF Vt VDDR−IVS REF 1 R IS R1+R1R2 VREF SVDD = VVRDEDF Vt VDD 1 − VREF R1+R1R2 VREF S = 25.5 0.0259 21.5 25797.6.84 = 0.0965 VDD Problem 4.6-1 An improved bandgap reference generator is illustrated in Fig. P4.6-1. Assume that the devices M1 through M5 are identical in W/L. Further assume that the area ratio for the bipolar transistors is 10:1. Design the components to achieve an output reference voltage of 1.262 V. Assume that the amplifier is ideal. What advantage, if any, is there in stacking the bipolar transistors? CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 44 VDD M1 M2 M3 M4 I2 I1 + VR1 R1 - Q2b Q1b Q2a Q1a Figure P4.6-1 opamp polarity corrected + - M5 + R2 VREF Q3 - VREF T=T0 = VG0 + Vt0 (γ − α) = 1.262 @ 300 K KVt0 = VG0 − VBE0 + Vt0 (γ − α) K = RR21 ln (10) = VG0 − VBE0 + Vt0 Vt0 (γ − α) VBE0 = kT q lnIIS I = ∆VBE R1 =1 µA R1 = 0.0259 ln(10) 1 µA = 59.64 kΩ CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 45 K = 1.205 - 0.53 + 0.0259(2.2) 0.0259 = 28.26 kΩ = RR21 ln (10) R2 = 732 kΩ Stacking bipolar transistors reduces sensitivity to amplifier offset. Problem 4.6-2 In an attempt to reduce the noise output of the reference circuit shown in Fig. P4.6-1, a capacitor is placed on the gate of M5. Where should the other side of the capacitor be connected and why? The other end of the capacitor should be connected to VDD. At high frequencies, the capacitor is a small-signal short circuit. Therefore, high-frequency noise on VDD also appears at the gate of M5 and thus is not amplified by M5. If on the other hand, the capacitor was connected to ground, noise on VDD would appear as vGS of M5 and thus be amplified to the output. Problem 4.6-3 In qualitative terms, explain the effect of low Beta for the bipolar transistors in Fig. P4.6-1? In our analysis, we assume that IE = IS e(VBE/ Vt) but in reality, this is the expression for IC . If β is large, then the approximation is warranted, but if not, the performance will deviate from the ideal. Problem 4.6-4 Consider the circuit shown in Fig. P4.6-4. It is a variation of the circuit shown in Fig. P4.6-1. What is the purpose of the circuit made up of M6-M9 and Q4? This circuit performs base-current compensation so that none of the base currents in Q1b and Q2b flow into Q1a and Q2a respectively. Problem 4.6-5 Extend Example 4.6-1 to the design of a temperature-independent current based upon the circuit shown in Fig. 4.6-4. The temperature coefficient of the resistor, R4, is +1500 ppm/°C. CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 46 I2 Q2 R3 R2 I1 + VR1 - R1 Q1 opamp polarity corrected + M1 - R4 M2 IREF Figure P4.6-5 AAee12 = 10 Veb = 0.7 , R2 = R3 , Vt = 26 mV , TC4 = 1500 ppm/°C VG0 = 1.205 , γ = 3.2 , α = 1 , T0 = 27 °C Since the amp forces V + = V − , then I1 = I2 IREF = I4 + 2 I1 = VREF R4 + 2 I1 I1 = ∆Vbe R1 = 1 kT R1 q ln(10) We want ∂IREF ∂T =0 T = T0 ∂IREF ∂T = ∂∂TVRRE4F + ∂ ∂T (2 I1) ∂I1 2 ∂T = 2qK ln(10) R1 CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 47 ∂∂TVRRE4F = ∂VREF ∂T R4 − VREF R24 ∂R4 ∂T ∂R4 ∂T = ∂ ∂T (R4 + R4TC4∆T) = R4TC4 ∂VREF ∂T = K VTt00 + VBE0 − T0 VG0 + (α − γ)Vt0 T0 ∂IREF ∂T = 1 R4 K VTt00 + VBE0 − T0 VG0 + (α −Tγ0)Vt0 - VREF R4 TC4 + 2qK ln(10) R1 K= R2 R1 ln AAee12 = R2 R1 ln(10) choose R2 R1 = 10 then K = 23.03 I1 = ∆ VBE R1 = kT q ln(10) R1 = 2 µA thus R1 = 29.93 kΩ , and R2 = 299.3 kΩ assume that VREF = 1.262 and solve for R4 R4 = 2 T0 R1 Vtln(10) VG0T−0VBE0 + (γ −α)Vt0 T0 − K VTt00 + VREF TC4 T0 T0 R4 = 2 R1 Vtln(10) (VG0−VBE0) + (γ −α)Vt0 − K Vt0 + VREF TC4 T0 R4 = 250 × 103 × 0.153 = 3825 Ω CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 48 IREF = VREF R4 + 2 I1 = 4 × 10-6 + 1.262 3825 = 333.9 × 10-6 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-1 CHAPTER 5 – HOMEWORK SOLUTIONS Problem 5.1-01 Assume that M2 in Fig. 5.1-2 is replaced by a 10kΩ resistor. Use the graphical technique illustrated in this figure to obtain a voltage transfer function of M1 with a 10kΩ load resistor. What is the maximum and minimum output voltages if the input is taken from 0V to 5V? Solution A computer generated plot of this problem is shown below. 5 +5V 4 10kΩ Vout 3 Vin Μ1 2µm 1µm Vout (V) 2 1 0 0 1 2 3 4 5 Vin(V) Fig. S5.1-01 The maximum output is obviously equal to 5V. The minimum output requires the following calculation assuming that M1 is in the active region. 110x10-6·2[(5-0.7)vout – 0.5vout2] = 5- vout 10kΩ 4.3 vout - vout2 = 5-vout 2.22 → This gives, vout (min) = 4.25±4.2945 = 0.5V vout2 – 9.5 vout + 4.504 = 0 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-2 Problem 5.1-02 Using the large-signal model parameters of Table 3.1-2, use Eqs. (1) and (5) to calculate the values of vOUT(max) and vOUT(min). Compare with the results shown on Fig. 5.1-2 on the voltage transfer function curve. Solution From Eq. (5.1-1), Vout (max) can be calculated as Vout (max) = VDD − VTp = 4.3 V 5V W2 L2 = 1µm 1µm M2 ID M1 + vIN - + vOUT W1 - L1 = 2µm 1µm Fig. S5.1-02 From Eq. (5.1-5), Vout (min) can be calculated as Vout (min) = VDD − VT − (VDD − VT 1+ β2 ) β1 Vout (min) = 5 − 0.7 − (5 − 0.7) 1 + (50)(1) (110)(5) = 0.183 V Problem 5.1-03 What value of β1/β2 will give a voltage swing of 70% of VDD 5V if VT is 20% of VDD? What is the small-signal voltage gain corresponding to this value of β1/β2? Solution Given VT = 0.2VDD and (Vout (max) − Vout (min))= 0.7VDD W2 L2 = β2 M2 ID M1 + vOUT From Eq. (5.1-1) and (5.1-5) Vout (max) − Vout (min) = (VDD − VT 1+ β2 ) β1 + vIN - W1 - L1 = β1 Fig. S5.1-03 or, 0.7V DD = (VDD − 0.2VDD ) 1+ β2 β1 → 1 + β 2 β1 = 8 7 2 → β 2 β1 = 0.306 The small-signal voltage gain can be given by Av ≅ − gm1 gm 2 =− β1 = -1.8 V/V β2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-3 Problem 5.1-04 What value of Vin will give a current in the active load inverter of 100µA if W1/L1 = 5µm/1µm and W2/L2 = 2µm/1µm? For this value of V in, what is the small-signal voltage gain and output resistance? Solution Assuming M1 is operated in saturation ( ) ID1 = K ' N W L 1 Vin − VT 2 2 or, 100 µ = (110 µ )(5) (Vin − 0.7)2 2 → Vin = 1.303V 5V W2 L2 = 2µm 1µm M2 ID M1 + vIN - + vOUT W1 - L1 = 5µm 1µm Fig. S5.1-04 The small-signal gain can be given by (( )) Av ≅ − gm1 gm 2 =− KN' KP' W L L 1 W 2 = -2.345 V/V The output resistance can be given by Problem 5.1-05 Rout ≅1 gm 2 = 7.07 kΩ Repeat Ex. 5.1-1 if the drain current in M1 and M2 is 50µA. Solution From Eqs. (5.1-1) and (5.1-5) we get vOUT(max) = 4.3V 5-0.7 vOUT(min) = 5 – 0.7 - = 0.418 V 1 + (50·1/110·2) From Eq. (5.1-7) we get, vout gm1 148.3 vin = - gds1+gds2+gm2 = 2.0 + 2.5+ 70.71 = -1.972 V/V From Eq. (5.1-8) we get, 1 106 Rout = gds1+gds2+gm2 = 2.0 + 2.5 + 70.71 = 13.296 kΩ The zero is at, gm1 z1 = Cgd1 = 148.3µS 0.5ff = 2.966x1011 rads/sec → 47.2 GHz The pole is at, 1 1 p1 = -ω-3dB = Rout(Cbd1+Cbd2+Cgs2+CL) = (13.296kΩ)(1.0225pF) = 73.555x106 rads/sec. → 11.71 MHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-4 Problem 5.1-06 Assume that W/L ratios of Fig. P5.1-6 are W1/L1 = 2µm/1µm and W 2/L2 = W3/L3 = W4/L4 = 1µm/1µm. Find the dc value of V in that will give a dc current in M1 of 110µA. Calculate the small signal voltage gain and output resistance of Fig. P5.1-6 using the parameters of Table 3.1-2. Solution Assuming all transistors are in saturation and ideal current mirroring ( ) ID1 = K ' N W L 1 Vin − VT 2 2 VDD M2 M3 M4 M1 + +vIN - vOUT - Figure P5.1-6 or, 110 µ = (110 µ )(2) (Vin − 0.7)2 2 → Vin = 1.7V The small-signal voltage gain can be given by AV ≅ − gm1 gm 2 =− KN' KP' W L L 1 W 2 ID1 ID2 = -6.95 V/V where, ID3 = ID4 = 100 µA, and ID2 = 10 µA. The output resistance can be given by Rout ≅ 1 gm 2 = 31.6 kΩ 100µA CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-5 Problem 5.1-07 Find the small-signal voltage gain and the -3dB frequency in Hertz for the active-load inverter, the current source inverter and the push-pull inverter if W1 = 2µm, L1 = 1µm, W2 = 1µm, L2 = 1µm and the dc current is 50µA. Assume that Cgd1 = 4fF, Cbd1 = 10fF, Cgd2 = 4fF, Cbd2 = 10fF and CL = 1pF. VDD M2 ID vOUT VGG2 M2 ID vOUT M2 vIN ID vOUT vIN vIN M1 M1 M1 Active Current Push- PMOS Load Source Load pull Inverter Inverter Inverter Figure 5.1-1 Various types of inverting CMOS amplifiers. Solution 1. Active load inverter The output resistance can be given by Rout ≅ 1 gm 2 = 1 = 14.14 kΩ 2(50 µ)(1)(50 µ) The total output capacitance can be given by Cout = CL + Cgs2 + Cbd 2 + Cgd1 + Cbd1 = 1.029 pF The –3 dB frequency can be given by f −3 dB = 1 2πRoutCout = 10.9 MHz 2. Current-source inverter The output resistance can be given by Rout ≅ 1 gds1 + gds2 = ID 1 (λN + λP ) = 222.22 kΩ The total output capacitance can be given by Cout = CL + Cgd 2 + Cbd 2 + Cgd1 + Cbd1= 1.028 pF The –3 dB frequency can be given by f −3 dB = 1 2πRoutCout = 0.697 MHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-6 Problem 5.1-07 - Continued 3. Push-pull inverter The output resistance can be given by Rout ≅ 1 gds1 + gds2 = ID 1 (λN + λP ) = 222.22 kΩ The total output capacitance can be given by Cout = CL + Cgd 2 + Cbd 2 + Cgd1 + Cbd1= 1.028 pF The –3 dB frequency can be given by f −3 dB = 1 2πRoutCout = 0.697 MHz Problem 5.1-08 What is the small-signal voltage gain of a current-sink inverter with W1 = 2µm, L1 = 1µm, W2 = L2 = 1 µm at ID = 0.1, 5 and 100 µA? Assume that the parameters of the devices are given by Table 3.1-2. 1. I D = 0.1 µA gm1 = ID1 n pVt (0.1µ ) = (2.5)(26m) = 1.538 µS ( ) ( ) Av =− gm1 gds1 + gds2 =− gm1 ID λN + λP = - 170.9 V/V 2. I D = 5 µA gm1 = 2KP' W L ID1 1 = 31.62 = 31.62 µS ( ) ( ) Av =− gm1 gds1 + gds2 =− gm1 ID λN + λP = - 70.27 V/V 3. I D = 100 µA gm1 = 2KP' W L ID1 1 = 141.42 µS ( ) ( ) Av =− gm1 gds1 + gds2 =− gm1 ID λN + λP = -15.71 V/V 2.5V 5V W2 L2 = 2µm 1µm M2 ID M1 + vIN - + vOUT W1 - L1 = 2µm 1µm CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-7 Problem 5.1-09 A CMOS amplifier is shown. Assume M1 and M2 operate in the saturation region. a.) What value of VGG gives 100µA through M1 and M2? b.) What is the DC value of vIN? c.) What is the small signal voltage gain, vout/vin, for this amplifier? d.) What is the -3dB frequency in Hz of this amplifier if Cgd = Cgd = 5fF, Cbs = Cbd = 30fF, and CL = 500fF? Solution a) VGG = VT 2 + Vdsat2 ( ) VGG = VT 2 + 2ID2 K ' N W L 2 = 2.05 V ( ) b) Vin = VDD − VT1 − K ' P 2ID1 WL 1 = 3.406 V ( ) c) Av = vout vin =− gm1 gds1 + gds2 = -24.85 V/V ( ( ) ) d) f−3dB = 2π gds1 + gds2 Cgd1 + Cgd 2 + Cbd1 + Cbd 2 + CL = 2.51 MHz. VDD M1 vin 5µm/1µm M2 vout 1µm/1µm VGG Figure P5.1-9 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-8 Problem 5.1-10 A current-source load amplifier is shown. (a.) If CBDN VDD =CBDP = 100fF, CGDN =CGDP = 50fF, CGSN = CGSP = 100fF, and CL = 1pF, find the -3dB frequency in Hertz. M3 M2 vout (b.) If Boltzmann’s constant is 1.38x10-23 Joules/°K, find the equivalent input thermal noise voltage of this amplifier at room temperature (ignore bulk effects, η = 0). 100µA CL M1 Solutions vin All W/L's equal 10 (a.) The -3dB frequency is equivalent to the magnitude of the output pole which is given as Fig. P5.1-10 1 1 1 1 ω-3dB = RoutCout where Rout = gds1+gds2 = 100µA(0.04+0.05) = 9x10-6 = 111kΩ Cout = Cgd1+Cbd1+Cgd2+Cbd2+CL = 0.05 + 0.05 + 0.1 + 0.1 +1 pF = 1.3pF ∴ ω-3dB = 1 0.111MΩ·1.3pF = 6.923x106 rads/sec. → f-3dB = 1.102 MHz (b.) The noise voltage at the output can be written as eno 2 = en1 2 gdsg1+mg1ds22+ en2 2 gdsg1+mg2ds22 Reflecting this noise voltage back to the input gives the equivalent input noise as, 8kT eni 2 = en1 2 1 +ggmm212eenn212 = en1 2 1 + ggmm212 3gm2 8kT 3gm1 = en1 21 + ggmm21 where gm1 = 2IDKNW1 L1 = 469µS, gm2 = 2IDKPW2 L2 = 316µS, and en1 2 = 8kT 3gm1 = 8·1.38x10-23·300 3·469x10-6 = 2.354x10-17 V2/Hz eni 2 = 2.354x10-17·1.6738 = 3.94x10-17V2/Hz → eni = 6.277nV/ Hz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-9 Problem 5.1-11 Six inverters are shown. Assume that KN' = 2KP' and that λN = λP, and that the dc bias current through each inverter is equal. Qualitatively select, without using extensive calculations, which inverter(s) has/have (a.) the largest ac small signal voltage gain, (b.) the lowest ac small signal voltage gain, (c.) the highest ac output resistance, and (d.) the lowest ac output resistance. Assume all devices are in saturation. VDD M2 vIN vOUT vIN M2 vOUT M2 vOUT M2 vOUT vIN M2 VBP vOUT M2 vOUT vIN M1 vIN M1 M1 M1 vIN M1 M1 VBN Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6 Solution Figure P5.1-11 Circuit 1 Circuit 2 Circuit 3 gm gmN= 2 gmP gmP gmN= 2 gmP 1 1 Rout ≈gmN+gmbN ≈gmP+gmbP 1 ≈ gmP 0.707 =gmP+gmbP |Gain| gmP gmP 2 gmP+gmbP gmP+gmbP Circuit 4 gmP 1 ≈ gmN 0.707 ≈ gmP 1 2 Circuit 5 Circuit 6 gmN= 2 gmP gmP 1 gdsN+gdsP = 1 1 gdsN+gdsP = 1 gdsP(1+ 2) gdsP(1+ 2) 2 gmP gmP gdsP(1+ 2) gdsP(1+ 2) (a.) Circuit 5 has the highest gain. (b.) Circuit 4 has the lowest gain (assuming normal values of gm/gmb). (c.) Circuits 5 and 6 have the highest output resistance. (d.) Circuit 1 has the lowest output resistance. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-10 Problem 5.1-12 Derive the expression given in Eq. (5.1-29) for the CMOS push-pull inverter of Fig. 5.1-8. If Cgd1 = Cgd2 = 5fF, Cbd1 = Cbd2 = 50fF, CL = 10 pF, and ID = 200 µA, find the small-signal voltage gain and the −3 dB frequency if W1/L1 = W2/L2 = 5 of the CMOS push-pull inverter of Fig. 5.1-8. + Solution vIN The effective transconductance can be given by gm,eff = gm1 + gm2 = 2ID K ' N W L 1 + KP' W L 2 The output conductance can be given by gout = (gds1 + gds2 )= I D (λ1 + λ2 ) Thus, the small-signal gain becomes Av = − g m, eff g out Av = − 2 ID ( ) K ' N W L 1 λ1 + + KP' λ2 W L 2 For I D = 200 µA Av = −43.63 = -43.63 V/V The total capacitance at the output node is ( ) Ctotal = Cgd1 + Cgd 2 + Cbd1 + Cbd 2 + CL = 10.11 pF. Thus, the –3 dB frequency is f −3 dB = gout 2πCtotal = 283.36 kHz. 5V W2 L2 = 2µm 1µm M2 ID M1 + vOUT - W1 - L1 = 1µm 1µm Fig.P 5.1-12 Eq. (5.1-29) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-11 Problem 5.1-13 For the active-resistor load inverter, the current-source load inverter, and the push-pull inverter compare the active channel area assuming the length is 1µm if the gain is to be −1000 at a current of ID = 0.1 µA and the PMOS transistor has a W/L of 1. VDD M2 ID vOUT VGG2 M2 ID vOUT M2 vIN ID vOUT vIN vIN M1 M1 M1 Active Current Push- PMOS Load Source Load pull Inverter Inverter Inverter Figure 5.1-1 Various types of inverting CMOS amplifiers. Soluton Given, I D = 10 µA , and Av = −100 V/V a) Active-resistor load inverter Av ≅ − g m1 g m2 → 100 = K ’ N (W L)1 K ’ P (1) → Active area = 4546·1 + 5·1 = 4551 µm2 W1 L1 = 4546 b) Current-source load inverter Av = − (g g m1 ds1 + gds 2 ) → 100 = 2K ’ N (W L)1 I D (λ1 + λ2 )2 Active area = 3.64·1 + 5·1 = 8.64 µm2 → W1 L1 = 3.64 c) Push-pull inverter Av = − (g m1 (g ds1 + + gm2 ) gds2 ) → 100 = 2K ’ N (W L)1 + 2K ’ P (1 / 1) I D (λ1 + λ2 )2 Active area = 1.55·1 + 5·1 = 4.55 µm2 → W1 L1 = 1.55 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-12 Problem 5.1-14 For the CMOS push-pull inverter shown, find the small signal voltage gain, Av, the output resistance, Rout, and the -3dB frequency, f-3dB if ID = 200µA, W1/L1 = W2/L2 = 5, Cgd1 = Cgd2 = 5fF, Cbd1 = Cbd2 = 30fF, and CL = 10pF. vIN Solution The small-signal model for this problem is shown below. VDD M2 vOUT M1 CM iout + vin gm1vin - rds1 gm2vin + rds2 Cout vout - Fig. S5.1-14 Summing the currents at the output (ignoring the capacitors) gives, gm1vin + gds1vout + gm2vin + gds2vout = 0 Solving for the voltage gain gives, VSS Fig. P5.1-14 W1 W2 vout gm1+ gm2 2 L1 IDKN + 2 L2 IDKP 2 vin = - gds1+ gds2 = - ID(λN+λP) = - ID W1 L1 KN + W2 L2 KP λN+λP vout 2 5·110x10-6 + 5·50x10-6 vin = Av = - 200x10-6 0.05 + 0.04 = - (100)(0.436) = - 43.63V/V ∴ Av = - 43.63V/V The output resistance is found by setting vin = 0 and solving for vout/iout. Rout is simply expressed as, 1 1 1 Rout = gds1+ gds2 = ID(λN+ λP) = 200x10-6 (0.05+0.04) = 55.55kΩ ∴ Rout = 55.55kΩ From Eq. (5.1-26) we can solve for the –3dB frequency as ω-3dB = ω1 = Cgd1 + gds1 + gds2 Cgd2 + Cbd1 + Cbd2 + CL = Rout(Cgd1 + Cgd2 1 + Cbd1 + Cbd2 + CL) 1 = 55.55x10-3( 5fF + 5fF + 30fF + 30fF + 10pF ) 1 ≈ 55.55x103·10x10-12 = 1.8x106 rad/s ∴ ω-3dB = 1.8x106 rad/s → f-3dB = 286.5 kHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-13 Problem 5.2-01 Use the parameters of Table 3.1-2 to calculate the small-signal, differential-in, differential-out transconductance gmd and voltage gain Av for the n-channel input, differential amplifier when ISS = 100 µA and W1/L1 = W2/L2 = W3/L3 = W4/L4 = 1 assuming that all channel lengths are equal and have a value of 1µm. Repeat if W1/L1 = W2/L2 = 10W3/L3 = 10W4/L4 = 10. Solution Referring to Fig. 5.2-5 and given that a) W L 1 = W L 2 = W L 3 = W L 4 =1 Differential-in differential-out transconductance is given by gmd = gm1 = gm2 = KN' W L ISS 1 = 104.8 µS Small-signal voltage gain is given by ( ) ( ) Av = gm 2 gds2 + gds4 = 2gm2 ISS λ2 + λ4 = 23.31 V/V b) W L 1 = W L 2 = 10WL 3 = 10 W L 4 = 10 gmd = gm1 = gm2 = 331.4 µS ( ) Av = gm 2 gds2 + gds4 = 36.82 V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-14 Problem 5.2-02 Repeat the previous problem for the p-channel input, differential amplifier. Solution Referring to Fig. 5.2-7 and given that (a.) W L 1 = W L 2 = W L 3 = W L 4 =1 Differential-in differential-out transconductance is given by gmd = gm1 = gm2 = KP' W L ISS 1 = 70.71 µS Small-signal voltage gain is given by ( ) ( ) Av = gm 2 gds2 + gds4 = 2gm2 ISS λ2 + λ4 = 15.7 V/V (b.) W L 1 = W L 2 = 10WL 3 = 10 W L 4 = 10 gmd = gm1 = gm2 = 223.6 µS ( ) Av = gm 2 gds2 + gds4 = 24.84 V/V Problem 5.2-03 Develop the expressions for VIC(max) and VIC(min) for the p-channel input differential amplifier of Fig. 5.2-7. Solution The maximum input common-mode input is given by ( ) VIC (max) = VDD − VT1 + Vdsat1 + Vdsat5 or, ( ) ( ) VIC (max) = VDD − VT1 + K ' P IDD W L 1 + 2IDD KP' W L 5 The minimum input common-mode input is given by VIC (min) = VSS − VT1 + VT 3 + Vdsat3 or, ( ) VIC (min) = VSS − VT1 + VT 3 + IDD KN' W L 3 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-15 Problem 5.2-04 Find the maximum input common mode voltage, vIC(max) and the minimum input common mode voltage, vIC(min) of the n-channel input, differential amplifier of Fig. 5.25. Assume all transistors have a W/L of 10µm/1µm, are in saturation and ISS = 10µA. What is the input common mode voltage range for this amplifier? Solution The maximum input common-mode input is given by VIC (max) = VDD + VT1 − VT 3 −Vdsat3 or, ( ) VIC (max) = VDD + VT1 − VT 3 − KP' ISS WL 3 = 4.86 V The minimum input common-mode input is given by VIC (min) = VSS + VT1 + Vdsat1 + Vdsat5 or, ( ) ( ) VIC (min) = VSS + VT1 + K ' N ISS W L 1 + 2ISS KN' W L 5 = 0.93 V So, the input common-mode range becomes ICMR = VIC (max) − VIC (min)= 3.93 V Problem 5.2-05 Find the small signal voltage gain, vo/vi, of the circuit in the previous problem if vin = v1 - v2. If a 10pF capacitor is connected to the output to ground, what is the -3dB frequency for Vio(jω)/VIN(jω) in Hertz? (Neglect any device capacitance.) Solution Small-signal voltage gain is given by ( ) ( ) Av = gm 2 gds2 + gds4 = 2gm2 ISS λ2 + λ4 = 233.1 V/V The –3 dB frequency is given by ( ) ( ) f−3dB ≅ gds2 + gds4 2πCL = ISS λ2 + λ4 4πCL = 7.16 kHz. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-16 Problem 5.2-06 For the CMOS differential amplifier of Fig. 5.2-5, find the small signal voltage gain, vout/vin, and the output resistance, Rout, if ISS = 10µA, VDD = 2.5V and vin = vgs1-vgs2. If the gates of M1 and M2 are connected together, find the minimum and maximum common mode input voltage if all transistors must remain in saturation (ignore bulk effects). Solution Small-signal model for calculations: ++ vin -+ vgs1 vgs2 gm1vgs1 - - i3 1 rds1 rds3 gm3 gm2vgs2 i3 iout + vout rds2 rds4 - Fig. S5.2-06 1 1 Rout = gds2 + gds4 = (0.04 + 0.05)5µA = 2.22 MΩ vout = g1m+1ggmm33rrpp11 vgs1 − gm2vgs2Rout ≈ (gm1vgs1 – gm2vgs2)Rout = gm1Routvin ∴ vout vin = gm1Rout = gm2Rout , gm1= gm2 = 2·110·5·2) µS = 46.9 µS vout vin = 46.9µS·2.22MΩ = 104.1 V/V Common mode input range: Vicm(max) = VDD – VSG3 + VTN = 2.5 - 520·5·2+0.7 + 0.7 = 2.5 - 0.3162 = 2.184 V Vicm(min) = 0+VDS5(sat)+VGS1= 2·10 110·2 121·05·2+0.7 = 0.3015+0.9132 = 1.2147 V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-17 Problem 5.2-07 Find the value of the unloaded differential-transconductance gain, gmd, and the unloaded differential-voltage gain, Av, for the p-channel input differential amplifier of Fig. 5.2-7 when ISS = 10 microamperes and ISS = 1 microampere. Use the transistor parameters of Table 3.1-2. Solution Assuming all transistors have W/L = 1 a) Given, I SS = 10 µA gmd = KP' W L ISS 1 = 22.36 µS b) Given, I SS = 1 µA ( ) ( ) Av = gmd gds2 + gds4 = 2gmd = 49.69 V/V ISS λ2 + λ4 gmd = KP' W L ISS 1 = 7.07 µS ( ) ( ) Av = gmd gds2 + gds4 = 2gmd = 157.11 V/V ISS λ2 + λ4 Problem 5.2-08 What is the slew rate of the differential amplifier in the previous problem if a 100 pF capacitor is attached to the output? Solution Slew rate can be given as SR = I SS CL For I SS = 10 µA and CL = 100 pF SR = ISS = 0.1 V/µs CL For I SS = 1 µA and CL = 100 pF SR = ISS = 0.01 V/µs CL CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-18 Problem 5.2-09 Assume that the current mirror of Fig. 5.2-5 has an output current that is 5% larger than the input current. Find the small signal common-mode voltage gain assuming that ISS is 100µA and the W/L ratios are 2µm/1µm for M1, M2 and M5 and 1µm/1µm for M3 and M4. Solution Given that I D4 = (1.05)I D3 or, I D2 = (1.05)I D1 This mismatch in currents in the differential input pair will result in an input offset voltage. Now, I D1 + I D2 = I SS So, I D1 ≅ (0.49)I SS and I D2 ≅ (0.51)I SS To calculate the common-mode voltage gain, let us assume a small signal voltage vs applied to both the gates of the differential input pair. The small-signal output current iout is given by iout = (iD4 − iD2 ) where, iD 4 ≅ 0.5gds5 gm3 gm 4 v s iD2 ≅ (0.5g ds5 )vs So, ( ) ( ) iout = iD4 − iD2 = 0.5gds5 gm4 gm3 − 1v s The output conductance can be given as Thus, or, or, or, gout ≅ gds4 as M 2 and M 5 form a cascode structure. vout = iout gout ≅ gds5 gm4 2gds4 gm3 − 1v s vout = gds5 gm4 −1 vs 2gds4 gm3 ( ) vout = ISS λ5 ID4 − 1 ( ) vs ISS λ4 ID3 vout = 0.02 V/V vs Thus, the small-signal common-mode gain is approximately 0.02 V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-19 Problem 5.2-10 Use the parameters of Table 3.1-2 to calculate the differential-in-to-single-ended-output voltage gain of Fig. 5.2-9. Assume that ISS is 50 microamperes. Solution Let, the aspect ratio of all the transistors be 1. The small-signal differential-in single-ended out voltage gain is given by (( )) Av = gm1 2gm 3 = KN' 4 K ' P W L1 W L3 = 0.74 V/V Problem 5.2-11 Perform a small-signal analysis of Fig. 5.2-10 that does not ignore rds1. Compare your results with Eq. (5.2-27). Solution Referring to Fig. 5.2-10 Applying KVL ( ) ( ) vic − vgs1 = gm1vgs1 2rds5 + v o − vic − vgs1 rds1 2rds5 or, vgs1{rds1 + 2rds5 (1 + gm1rds1 )}+ vo (2rds5 )= vic (rds1 + 2rds5 ) (1) Also, applying KCL ( ) −vo 1 gm 3 + rds3 = gm1vgs1 + v o − vic − vgs1 rds1 or, v gs1 = {vic − vo (1 + gm3rds1 )} (1 + gm1rds1 ) (2) Putting Eq. (2) in Eq. (1), and assuming g m1rds1 >> 1 {vic − vo (1 + (1 + gm3rds1 g m1rds1 ) )}(2rds5 (1 + gm1rds1 ))+ vo (2rds5 )= vic (rds1 + 2rds5 ) or, − vo (gm3rds1)2rds5 = vicrds1 or, vo vic = − (g 1 m3 2rds5 ) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-20 Problem 5.2-12 Find the expressions for the maximum and minimum input voltages, vG1(max) and vG1(min) for the n-channel differential amplifier with enhancement loads shown in Fig. 5.2-9. Solution VG1(min) = VT1 + Vdsat1 + Vdsat5 or, VG1(min) = VT1 + I SS + K ’ N (W L)1 2I SS K ’ N (W L)5 VG1(max) = VDD + VT1 −VT 3 + Vdsat3 or, VG1(max) = VDD + VT1 −VT 3 + I SS K ’ P (W L)3 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-21 Problem 5.2-13 If all the devices in the differential amplifier of Fig. 5.2-9 are saturated, find the worstcase input offset voltage, VO S , if |VTi| = 1 ± 0.01 volts and β i = 10-5 ± 5 × 10-7 amperes/volt2. Assume that β1 = β2 = 10β3 = 10β4 and ∆β1 β1 = ∆β2 β2 = ∆β3 β3 = ∆β4 β4 Carefully state any assumptions that you make in working this problem. Solution Referring to the figure VGS1 = VT1 + Vdsat1 or, VGS1 = VT1 + 2I D1 β1 VGS 2 = VT 2 + Vdsat2 or, VGS 2 = VT 2 + 2I D2 β2 The input-offset voltage can de defined as VOS = VGS1 − VGS2 or, VOS = VT1 − VT 2 + 2I D1 − β1 2I D1 β2 Considering the transistors M 3 and M 4 , mismatches in these two transistors would cause an offset voltage between the output nodes. But, if it is assumed that this offset voltage between the output nodes is small as compared to the drain-to-source voltages of the transistors M1 and M 2 , then VDS1 ≅ VDS 2 Thus, it is assumed here that I D1 = I D2 = I So, the input-offset voltage becomes VOS = VT1 − VT 2 + 2I − β1 2I β2 Assuming I = 50 µA , the worst-case input offset voltage can be given by VOS = (1.01 − 0.99) + 2(50 µ) 0.95(10 µ) − 2(50 µ) 1.05(10 µ) or, VOS(max) = 0.18 V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-22 Problem 5.2-14 Repeat Example 5.2-1 for a p-channel input, differential amplifier. Solution The best way to do this problem is to use the equations for the n-channel, source-coupled pair with opposite type transistor parameters and then subtract the result from 5V. Eq. (5.2-15) gives VIC(max) = 4 − 2·50µA 99µA/V 2·1 + 0.85 + 0.55 = 4 – 1.855 + 0.55 = 2.695 volts Subtracting from 5V gives VIC(min) =5 − 2.695 = 2.305 V and Eq. (5.2-17) gives VIC(min) = 0 + 0.2 + 2·50µA 45µA/V 2·5 +0.85 = 0.2 + 1.517 = 1.717 volts Subtracting from 5 V gives, VIC(max) = 5 − 1.717 = 3.282 V Therefore, the worst-case input common-mode range is 0.978V with a nominal 5V power supply. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-23 Problem 5.2-15 Five different CMOS differential amplifier circuits are shown in Fig. P5.12-15. Use the intuitive approach of finding the small signal current caused by the application of a small signal input, vin, and write by inspection the approximate small signal output resistance, Rout, seen looking back into each amplifier and the approximate small signal, differential voltage gain, vout/vin. Your answers should be in terms of gmi and gdsi, i = 1 through 8. (If you have to work out the details by small signal model analysis, this problem will take too much time.) VDD M7 M8 M7 M8 M7 M8 M7 M8 M7 M8 VBP vOUT vOUT vOUT M5 M6 vOUT M5 M6 vOUT M3 M4 M1 M1 M1 M1 M1 VBN vIN M2 vIN M2 vIN M2 M2 M2 ISS ISS ISS ISS ISS Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Solution Figure P5.2-15 gm2 Assume gm1 = gm2 otherwise multiply the gain of circuits 1 and 2 by gm1+gm2 . Circuit Rout vout/vin 1 gm1gm2 0.5gm2 1 gds2+gm8+gds8 (gm1+gm2)(gds8+gm8+gds8) = gds2+gm8+gds8 1 2 gds2+gds8 gm1gm2 0.5gm2 (gm1+gm2)(gds2+gds8) = gds2+gds8 1 3 gds2+gds8 gm1+gm2 2(gds2+gds8) 4 1 gm6 gds6gds8 = gds6gds8+gm6gds2 gds2˚+ gm6 (gm1+gm2)˚gm6 2(gm6gds2+gds6gds8) gm4gm6 5 gds2gm6gds4˚+gm6gds4gds8 (gm1+gm2)gm4gm6 2(gds2gm6gds4˚+gm6gds4gds8) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-24 Problem 5.2-16 If the equivalent input-noise voltage of each transistor of the differential amplifier of Fig. 5.2-5 is 1nV/ Hz find the equivalent input noise voltage for this amplifier if W1/L1 = W2/L2 = 2 µm/1 µm, W3/L3 = W 4/L4 = 1 µ m/1 µm and ISS = 50 µA. What is the equivalent output noise current under these conditions? Solution From Equation. (5.2-39) ( ) ee2q = en21 + en22 + gm 3 gm1 2 en23 + en24 or, ee2q = 2en21 + gm 3 gm1 2 = 2.455en2 Given en = 1 nV / Hz Thus, eeq. = 1.567 nV/ Hz The equivalent output noise current is given by it2o = gm21ee2q or, ito = 164 fA/ Hz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-25 Problem 5.2-17 Use the small-signal model of the differential amplifier using a current mirror load given in Fig. 5.2-8(a) and solve for the ac voltage at the sources of M1 and M2 when a differential input signal, vid, is applied. What is the reason that this voltage is not zero? Solution Neglecting the current source i3 in the figure, let us assume that v g1 = −vg 2 = vid 2 Applying nodal analysis, we will get the following three equations (gm1 + gds1)vs1 = gm1vg1 + (g m3 + gds1 )vD3 (1) (gm2 + gds2 )vs1 = g m2vg2 + (gds2 + gds4 )vout (2) (gm1 + gm2 + gds1 + g ds2 − gds5 )vs1 = gm1vg1 + gm2vg2 + gds1vD3 + g ds2vout (3) Now, assuming gm >> g ds , g m1 = gm2 , g ds1 = g ds2 , and v g1 = −vg2 = vid 2 vs1 = (g m1 + gds1vD3 + g ds2vout gm2 + g ds1 + gds2 − g ds5 ) or, vs1 = g ds1vD3 + gds2vout (2gm1 + 2g ds1 − g ds5 ) Substituting from Equations (1) and (2), we get vs1 = gm10.25 − gds1 gm 3 0.75gm1 + gds12 − gm1 gm 3 − gds5 vid The value of vs1 is non-zero because the loads (M3 and M4) seen by the input transistors (M1 and M2) at their drains are different. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-26 Problem 5.2-18 The circuit shown Fig. P5.2-18 +1.5V called a folded-current mirror differential amplifier and is useful for low values of power supply. Assume that all W/L M9 M8 M6 M7 vout values of each transistor is 100. a.) Find the maximum input common mode voltage, v1 M1 M2 v2 vIC(max) and the minimum input common mode voltage, 100µA M10 vIC(min). Keep all transistors M5 M3 M4 in saturation for this problem. b.) What is the input common mode voltage range, ICMR? Fig. P5.2-18 c.) Find the small signal voltage gain, vo/vin, if vin = v1 - v2. d.) If a 10 pF capacitor is connected to the output to ground, what is the -3dB frequency for Vo(jω)/Vin(jω) in Hertz? (Neglect any device capacitance.) Solution 200 a.) v1(max) = VDD - VDS6(sat) + VTN = 1.5 - 50·100 + 0.7 = 1.5 – 0.2 + 0.7 ∴ v1(max) = 2V v1(min) = 0 + VDS5(sat) + VGS1(50µA) = 2·100 110·100 + 2·50 110·100 + 0.7 = 0.1348 + 0953 + 0.7 = 0.9302V ⇒ v1(min) = 0.9302V b.) ICMR = v1(max) - v1(min) = 1.0698V c.) Using intuitive analysis approach gives: id1 = gm1v2in ⇒ id3 = -gm1v2in ⇒ id4 =-gm1v2in Also, id2 = -gm2v2in . ∴ vout = -Rout(id2 + id4) 1 However, Rout = rds2||rds4||rds7 = gds2+gds4+gds7 ⇒ vout vin gm1 = gds2+gds4+gds7 gm1 = 2·50·110·100 = 1049µS, gds2 = gds4 = 0.04·50 = 2µS and gds7 = 0.05·100 = 5µS ∴ vout 1049 vin = 7 = 149.8V/V d.) 1 ω-3dB = Rout10pF 7x10-6 = 10x10-12 = 0.7x106 → ∴ f-3dB = 111.4kHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-27 Problem 5.2-19 Find an expression for the equivalent input noise voltage +1.5V of Fig. P5.2-18, veq2 , in terms of the small signal model M9 M8 M6 M7 parameters and the individual equivalent input noise voltages, v1 M1 M2 v2 vni2 , of each of the transistors (i = 1 through 7). Assume M1 and M2, M3 and 100µA M10 M5 M3 M4, and M6 and M7 are matched. Solution Fig. P5.2-18 Equivalent noise circuit: en62 VDD * * M6 en72 M7 v1 en12 * M1 M2 v1 * en22 M3 en32 en42 ** vout M4 vout M4 VSS S99FES6 e 2 out = (gm12 e 2 n1+ gm22 e 2 n2+ gm32 e 2 n3+ gm42 e 2 n4+ gm52 e 2 n6+ gm62 e n27)Rout2 2 2 e eq e out = (gm1Rout)2 = e 2 n1+ e 2 n2+ ggmm132( e 2 n3+ e n24)+ggmm162( e 2 n6+ e 2 n7) If M1 through M2 are matched then gm1 = gm3 and we get e 2 eq =4 e 2 n1 + 2ggmm162 e 2 n6 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-28 Problem 5.2-20 Find the small signal transfer VDD function V3(s)/Vin(s) of Fig. P5.2- 20, where Vin = V1-V2, for the M5 M6 M7 M8 capacitors shown in algebraic form (in terms of the small signal v3 model parameters and C1 capacitance). Evaluate the low- C2 C3 v4 C4 frequency gain and all zeros and v1 poles if I = 200µA and C1 = C2 = M1 M2 M3 M4 v2 C3 = C4 = 1pF. Let all W/L = 10. I Solution VBias M9 Small-signal model:L ΣiA = 0: (Gout = gds1 + gds5) 0.5gm1vin + sC1v3 + Goutv3 + gm5v6 = 0 ΣiB = 0: sC2v6 + gm6v6 = 0.5gm3vin = 0 Fig. P5.2-20 → v6 = sC0.25+gmg3m6 v6 A B gm1vin 2 rds1 rds5 C1 v3 C2 1 v6 gm5v6 gm6 rds3 rds6 gm3vin 2 From the first equation we get, v3(sC1 + Gout) + gm5 sC0.25+gmg3m6 vin + 0.5gm1vin = 0 Solving for v3 gives, v3 vin = sC-01.5+gGmo1utsC2sC+2g+m5g+m6gm6 When s → 0, v3 -gm1 vin = gds1 + gds5 gmN = 2·50µA·110x10-6·10 = 331.6µS, gmP= 2·50µA·50x10-6·10 = 223.6µS, 1 1 rdsN = 0.04·50x10-6 = 0.5MΩ, and rdsP = 0.05·50x10-6 = 0.4MΩ ∴ v3 vin = - gmN·Rout = -(331.6)(0.5||0.4) = -73.69 V/V Poles are at, p1 = -1 RoutC1 = -1 22.22kΩ·1pF = -4.5x106rad/s & p2 = -gm6 C2 = -223.6µS 1pF = -223.6 x106 rad/s A zero is at, -(gm5+ gm6) z1 = C2 -(223.6µS + 223.6µS) = 1pF = -447.2 x106 rad/s CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-29 Problem 5.2-21 For the differential-in, differential-out amplifier of Fig. 5.2-13, assume that all W/L values are equal and that each transistor has approximately the same current flowing through it. If all transistors are in the saturation region, find an algebraic expression for the voltage gain, vout/vin, and the differential output resistance, Rout, where vout = v3-v4 and vin = v1-v2. Rout is the resistance seen between the output terminals. Solution vout vin = (v3 (v1 − − v4 ) v2 ) = − g m1 (gds1 + g ds3 ) or, ( ) vout = − 2K ’ N W L 1 vin I BIAS (λ1 + λ3 )2 Considering differential output voltage swing, the output resistance can be given by Rout = (g ds1 1 + gds3 ) + (g ds2 1 + gds4 ) or, Rout = (g ds1 2 + gds3 ) = 2 I BIAS (λ1 + λ3 ) Problem 5.2-22 Derive the maximum and minimum input common mode voltage for Fig. 5.2-15 assuming all transistors remain in saturation. What is the minimum power supply voltage, VDD, that will give zero common input voltage range? Solution The minimum input common-mode voltage is given by VIC (min) = VT1 + Vdsat1 + Vdsat5 The maximum input common-mode voltage is given by VIC (max) = VDD + VT1 − Vdsat3 Assuming all the Vdsat voltages to be the same, the minimum supply voltage for zero input common mode can be given by VIC (max) − VIC (min) = 0 or, (VDD + VT1 −Vdsat3 )− (VT1 + Vdsat1 + Vdsat5 )= 0 or, VDD ≈ 3Vds(sat) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-30 Problem 5.2-23 Find the slew rate, SR, of the differential amplifier shown where the output is differential (ignore common-mode stability problems). Repeat this analysis if the two current sources, 0.5ISS, are replaced by resistors of RL. 0.5ISS VDD CL 0.5ISS Solution a.) Slew rate of the differential output amplifier with constant current source loads. +vOUT M1 M2 Under large signal swing conditions, the maximum current that can be carried by each of the two transistors M1 and M 2 is I SS . Due to the presence of constant current sources as loads, the maximum charging or discharging current through CL would be 0.5I SS . Thus, the slew rate can be given by ISS VSS Fig. P5.2-23 ISS SR = 2CL b.) Slew rate of the differential output amplifier with resistive loads. In presence of resistive loads, the maximum charging or discharging current through CL would be I SS . Thus, the slew rate can be given by ISS SR = CL CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-31 Problem 5.2-24 If all the devices in the differential amplifier shown in Fig. 5.2-5 are saturated, find the worst-case input-offset voltage VOS using the parameters of Table 3.1-2. Assume that 10(W4/L4 = 10(W3/L3) = W2/L2 = W1/L1 = 10 µ m/10 µm. State and justify any assumptions used in working this problem. Solution The offset voltage between the input terminals is given by Vos = VGS1 − VGS2 The drain current equations are I D1 = β1 2 (VGS1 − VT1 )2 I D2 = β2 2 (VGS 2 − VT 2 )2 or, Vos = VGS1 − VGS 2 = (VT 2 − VT1 )+ 2I D1 − β1 2I D2 β2 Mismatches would cause ID1 ≠ ID2. But, to simplify the problem, it can be assumed that I D1 = I D2 = 0.5I SS . Under this assumption and considering the mismatches in VT and β only, the worst-case input-offset voltage (from Table 3.1-2) can be given by Vos = 0.3 + I SS 0.9β − I SS 1.1β Assuming I SS = 100 µA Vos = 0.3 + 100µ 0.9(110µ )(10 /10) − 100µ 1.1(110µ)(10 /10) = 0.48 V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-32 Problem 5.3-01 Calculate the small-signal voltage gain for the cascode amplifier of Fig. 5.3-2 assuming that the dc value of vIN is selected to keep all transistors in saturation. Compare this value with the slope of the voltage transfer function given 2.3V in this figure. Solution The small-signal voltage gain can be approximated as Av ≅ − g m1 g ds3 or, Av ≅ − 2K ’ N (W L)1 I D3λ32 3.4V 5V M3 W3 L3 = 2µm 1µm ID M2 W2 L2 + = 2µm 1µm M1 vOUT + vIN - W1 L1 = 2µm 1µm - Fig. P5.3-2 ID is calculated from M3 as, ID = K2PL'W2 2(VSG3-|VTP|)2 = 50·(2.7-0.7)2 µA = 200µA ∴ 2KN'(W1/L1) 2·50·2 Av = IDλN2 = 200·0.05·0.05 = -20 V/V From the transfer characteristics, the small-signal gain is approximately -10 V/V. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-33 Problem 5.3-02 Show how to derive Eq. (5.3-6) from Eqs. (5.3-3) through (5.3-5). Hint: Assume that VGG2-VT2 is greater than vDS1 and express Eq. (5.3-4) as iD2 ≈ β2(VGG2-VT2)vDS2. Solve for vOUT as vDS1 + vDS2 and simplify accordingly. Solution From Eqs. (5.3-3) through (5.3-5) I D1 ≅ β1(VDD −VT1 )Vds1 I D2 ≅ β 2 (VGG2 − Vds1 − VT 2 )(Vout − Vds1 ) ( ) I D3 = 0.5β3 VDD −VGG3 − VT3 2 Assuming, when Vin is taken to VDD , the magnitudes of Vds1 and Vout are small. Equating I D1 = I D3 ( ) β1(VDD − VT1)Vds1 = 0.5β3 VDD − VGG3 − VT3 2 or, ( ) Vds1 = 0.5β 3 VDD − VGG3 − VT 3 β1(VDD − VT1 ) 2 (1) Equating I D1 = I D2 β1(VDD − VT1)Vds1 = β2 (VGG2 − Vds1 − VT 2 )(Vout − Vds1) or, (VDD −VT1 )Vds1 = (VGG2 − VT 2 )(Vout −Vds1) or, Vds1 = Vout (VGG2 − VT 2 ) (VDD + VGG2 − VT1 − VT 2 ) (2) From Eqs. (1) and (2), the minimum output voltage is given by ( ) ( ) ( ) Vout (min) = β3 2β1 VDD − VGG 3 − VT 3 2 1 VDD − VT 1 + 1 VGG 2 − VT 2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-34 Problem 5.2-03 Redrive Eq. (5.3-6) accounting for the channel modulation where pertinent. Solution From Eqs. (5.3-3) through (5.3-5) I D1 ≅ β1(VDD −VT1 )Vds1 I D2 ≅ β 2 (VGG2 − Vds1 − VT 2 )(Vout − Vds1 ) ( ) I D3 = 0.5β3 VDD − VGG3 − VT 3 2 (1 + λ3 (VDD −Vout )) Assuming, when Vin is taken to VDD , the magnitudes of Vds1 and Vout are small. Equating I D1 = I D3 ( ) β1(VDD − VT1)Vds1 = 0.5β3 VDD − VGG3 − VT 3 2 (1 + λ3 (VDD − Vout )) or, ( ) Vds1 = 0.5β 3 VDD −VGG3 − VT 3 2 (1 + λ3 (VDD β1(VDD − VT1 ) − Vout )) (1) Equating I D1 = I D2 β1(VDD − VT1)Vds1 = β2 (VGG2 − Vds1 − VT 2 )(Vout − Vds1) or, (VDD −VT1 )Vds1 = (VGG2 − VT 2 )(Vout −Vds1) or, Vds1 = Vout (VGG2 − VT 2 ) (VDD + VGG2 − VT1 − VT 2 ) (2) From Eqs. (1) and (2), assuming VDD − Vout ≅ VDD , the minimum output voltage is given by ( ) ( ) ( ) ( ) Vout (min) = β3 2β1 VDD − VGG 3 − VT 3 2 1 VDD − VT 1 + 1 VGG 2 − VT 2 1+ λ3VDD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-35 Problem 5.3-04 Show that the small signal input resistance looking in the source VDD of M2 of the cascode amplifier of Fig. 5.3-1 is equal to rds if the simple current source, M3 is replaced by a cascode current source. Solution VGG4 M4 The effective resistance of the cascoded PMOS transistors is VGG3 represented by RD3 and it is given by RD3 ≅ gm3rds3rds4 Referring to the small-signal model in the figure ( ) v1 = gm2vx + vx − v1 rds2 RD3 or, v1 = (1 + g m2rds2 )RD3 (RD3 + rds2 ) vx (1) VGG2 Vin M3 RD3 Vout M2 RS2 M1 Now ix = gm2vx + (vx − v1)+ rds2 vx rds1 VSS ix = (g m2 + gds2 + g ds1)vx − g ds2v1 ix ≅ gm2vx − gds2v1 Replacing v1 from Eq. (1) and assuming RD3 >> rds2 ix ≅ vx [gm2 (RD3 + rds2 )− RD3 gm2RD3 ] or, RS 2 = vx ix ≅ RD3 g m2 rds 2 or, RS 2 = g m3 rds3 rds4 g m2rds2 = rds CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-36 Problem 5.3-05 Show how by adding a dc current source from VDD VDD to the drain of M1 in Fig. 5.3-1 that the small- signal voltage gain can be increased. Derive an expression similar to that of Eq. (11) in terms of ID1 and ID4 where ID4 is the current of the added VGG3 M3 dc current source. If ID2 = 10 µA, what value for this current source would increase the voltage gain Vout ID4 by a factor of 10. How is the output resistance affected? Solution VGG2 M2 Assuming all the transistors are in saturation I D1 = I D2 + I D4 Av ≅ − g m1 g ds3 or, Av ≅ − 2K ’ N W L (I 1 D2 + I D4 ) ID2 2λ23 Vin M1 Fig. S5.3-05 VSS or, Av ≅ Avo 1+ ID4 I D2 where, Avo = − 2 K ’ N W L 1 I D2λ23 is the gain in absence of the current source I D4 Thus, Av = 1 + I D4 Avo I D2 The small-signal voltage gain can be increased by making I D4 >> I D2 . In order to achieve Av = 10 Avo → 10 = 1 + I D4 I D2 or, I D4 = 99I D2 = 990 µA The output resistance can be given by Rout ≅ [g m2rds2rds1 || rds3 ] The value of rds1 decreases due to increased current through M1, thus decreasing the overall output resistance. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-37 Problem 5.3-06 Assume that the dc current in each transistor in Fig. P5.3-6 is 100µA. If all transistor have a W/L of 10µm/1µm, find the small signal voltage gain, VP1 vout/vin and the small signal output resistance, Rout, if all transistors are in the saturated region. Solution This circuit is a folded cascode amplifier. The small signal analysis is best done by the schematic analysis approach. In words, vi n vin creates a current flowing into the drain of M1 of gm1vin. This current flows through M4 from drain to source back around to M1. The output voltage is simply this current times Rout. The details are: +5V M3 M2 VP2 M4 Rout vout VN2 M5 M1 VN1 M6 Fig. P5.3-6 vout = -gm1Routvin Rout ≈ [rds6(gm5rds5)]||[(rds1||rds2||rds3)(gm4rds4)] The various small signal parameters are: gmN = 2·110·100·10 = 469µS, gmP = 2·50·100·10 = 316.2µS 25V 20V rdsN = 100µA = 0.25MΩ and rdsP = 100µA = 0.2MΩ ∴ Rout ≈ 29.31MΩ||(0.0667MΩ)(63.2) = 29.31MΩ||4.216MΩ = 3.686MΩ Rout = 3.686MΩ vout vin = -(469µS)(3.686MΩ) = -1,729 V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-38 Problem 5.3-07 Six versions of a cascode amplifier are shown below. Assume that K'N = 2K'P, λP = 2λN, all W/L ratios of all devices are equal, and that all bias currents in each device are equal. Identify which circuit or circuits have the following characteristics: (a.) highest small signal voltage gain, (b.) lowest small signal voltage gain, (c.) the highest output resistance, (d.) the lowest output resistance, (e.) the lowest power dissipation, (f.) the highest Vout(max), (g.) the lowest Vout (max), (h.) the highest Vout (min), (i.) the lowest Vout (min), and (j.) the highest -3dB frequency. VDD VBP1 vIN vIN vIN VBP2 vOUT vOUT vOUT vOUT vOUT vOUT VBN2 vIN vIN vIN VBN1 Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6 Solution Figure P5.3-7 Circuit 1 gm gmN Rout ≈ rdsP Circuit 2 gmP ≈ rdsN Circuit 3 gmN R* Circuit 4 gmP R* Circuit 5 2 gmN ≈ rdsP Circuit 6 2 gmP ≈ rdsN R* = (gmP·rdsP2)||(gmN·rdsN2) Note that gmN = 2 gmP and rdsN = 2rdsP e.) Circuit 3 has the highest gain. f.) Circuit 1 has the lowest gain. g.) Circuits 3 and 4 have the highest output resistance. h.) Circuits 1 and 5 have the lowest output resistance. i.) Circuits 1-4 have the lowest power dissipation. j.) Circuits 1 and 5 have the highest Vout(max). k.) Circuit 4 has the worst (lowest) Vout(max). l.) Circuits 2 and 6 have the best (lowest) Vout(min). m.) Circuit 3 has the worst (highest) Vout(min). n.) Circuits 1 and 5 have the highest –3dB frequency because of lowest Rout. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-39 Problem 5.3-08 All W/L ratios of each transistor in the amplifier shown in Fig. P5.3-8 are 10µm/1µm. Find the numerical value of the small signal voltage gain, vout/vin, and the output resistance, M8 Rout. Solution The output resistance can be given as M7 Rout ≅ [gm2rds2rds1 || g m3rds3rds4 ] Neglecting body effects 100µA M6 g m1 = gm2 = 469 µS M5 g m3 = gm4 = 316 µS VDD M4 M3 Rout vout M2 vin M1 g ds1 = gds2 = 4 µS g ds3 = gds4 = 5 µS Thus, Rout ≅ [29.31M || 12.64M ] Figure P5.3-8 or, Rout ≈ 8.838 MΩ The small-signal voltage gain is given as vout vin = −gm1Rout = -41.42 V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-40 Problem 5.3-09 Use the Miller simplification described in Appendix A on the capacitor C2 of Fig. 5.35(b) and derive an expression for the pole, p1, assuming that the reactance of C2 at the frequency of interest is greater than R3. Compare your result with Eq. (5.3-32). Vout Vin/Rs R1 C1 (1-Av)C2 V1 gm1V1 C3 C2 Av (Av-1) R3 sC2<> 1 R3 Referring to the figure ( ) ( ) V1(s) = 1 RS R1 +s Vin (s) C1 + 1+ Av C2 (1) where, Av = gm1R3 Also, Vo (s) = −gm1V1(s) 1 R3 + sC3 ≅ −gm1V1(s) sC3 or, ( ( ) ) Vo (s) = −gm1 1 R3 + sC3 1 RS R1 +s Vin (s) C1 + 1+ Av C2 (2) The dominant pole in Eq. (2) can be expressed as ( ) ( ) p1 = R1 −1 AvC2 + C1 ≅ −1 R1 AvC2 -1 or, p1 = gm1R1R3C2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-41 Problem 5.3-10 Consider the current-source load inverter of Fig. 5.1-5 and the simple cascode amplifier of Fig. 5.3-1. If the W/L ratio for M2 is 1 µm/1 µm and for M1 is 3 µm/1 µm of Fig. 5.15, and W3/L3 = 1 µm/1 µm, W2/L2 = W1/L1 = 3 µm/1 µm for Fig. 5.3-1, compare the minimum output-voltage swing, vOUT(min) of both amplifiers if VGG2 = 0 V and VGG3 = 2.5 V when VDD = −VSS = 5 V. Solution a) Current source load inverter When Vin = VDD , it can be assumed that M1 operates in the triode region and M 2 is in saturation. Thus, ( ) β1(VDD − VSS − VT1)(Vout (min) − VSS )= 0.5β 2 VSG2 − VT 2 2 or, ( ) Vout (min) = 0.5β2 VSG2 − β1(VDD −VSS VT 2 2 −VT1 ) + VSS Assuming, VSG2 = 5 V Vout(min) = -4.85 V b) Simple cascode amplifier or, Now, Vout (min) = VSS + Vdsat1 + Vdsat 2 Vout (min) = VSS + 2I D1 + K ’ N (W L)1 2I D2 K ’ N (W L)2 ( ) I D3 = β3 2 VDD − VGG3 − VT 3 2 = 81 µA Thus, Vout(min) = -3.6 V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-42 Problem 5.3-11 Use nodal analysis techniques on the cascode amplifier of Fig. 5.3-6(b) to find vout/vin. Verify the result with Eq. (5.3-37) of Sec. 5.3. Solution Nodal analysis of cascode amplifier Applying KCL g m1vin + gds1v1 + gm2v1 + g mbs2v1 = gds2 (vout − v1 ) or, g m1vin + (gds1 + gm2 + g mbs2 + gds2 )v1 = gds2vout or, v1 = (g ds2vout (gds1 + gm2 + − gm1vin ) gmbs2 + gds2 ) (1) Again, applying KCL g ds4v4 + g ds3 (v4 − vout )+ gm3v4 + gmbs3v4 = 0 or, Also, v4 = (g m3 + g ds3 gds3 + g ds4 + gmbs3 )vout (2) (gm3 + gmbs3 )v4 + gds3 (v4 − vout )+ (gm2 + g mbs2 )v1 + gds2 (v1 − vout )= 0 or, (gm3 + g mbs3 + gds3 )v4 + (gm2 + g mbs2 + gds2 )v1 = (g ds3 + g ds4 )vout (3) Using Eqs. (1) through (3) and neglecting body effect, it can be shown that Av = − gm1gm2 gm3 (gm3gds1gds2 + g m2 g ds3g ds4 ) or, Av = − g ds1g ds2 g m2 g m1 + gds3gds4 gm3 or, Av = I D − 2K1’(W L)1 λ1λ2 + 2K ’ 2 (W L)2 λ3λ4 2K ’ 3 (W L)3 Eq. (5.3-37) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-43 Problem 5.3-12 Find the numerical value of the small signal voltage gain, vout/vin, for the circuit of Fig. P5.3-12. Assume that all devices are saturated VDD M6 M5 M4 M3 and use the parameters of Table 3.1-2. Assume 4/1 that the dc voltage drop across M7 keeps M1 in 4/1 4/1 40/1 vout saturation. M2 Solution ID3 = ID2 = 20 µA ID3 = 220 µA M7 1/1 20µA 4/1 vin M1 4/1 Now, gm1 = 440 µS and rds1 = 113.64 kΩ Fig. P5.3-12 gm2 = 132.67 µS and rds2 = 1.25 kΩ rds3 = 1 MΩ Thus, [ ] Rout = rds3 || gm r2 ds2rds1 or, Rout = [1M ||18.8M] = 950 kΩ So, Av = −gm1Rout = -418 V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-44 Problem 5.3-13 A cascoded differential amplifier is shown in VDD Fig. P5.3-13. (a) Assume all transistors are in saturation and find an algebraic expression for the small signal voltage gain, vout/vin. (b) Sketch how would you implement VBias? (Use a minimum number of transistors.) (c.) Suppose that I7+I8≠ I9. What would be M12 M11 M7 I7 M5 M3 M8 I8 M6 vout M4 the effect on this circuit and how would you I + M1 solve it? Show a schematic of your solution. You should have roughly the same gain and vi-n + M2 - VBias the same output resistance. Solution M9 M10 I9 a ) The effective transconductance is given by VSS gm,eff = gm1 2 Fig. P5.3-13 The output resistance of the cascoded output is given by Rout = gds2gds4 gm4 1 + gds6gds8 gm 6 Thus, the small-signal voltage gain is given by Av = 0.5gm1 gds2gds4 gm4 + gds6gds8 gm 6 b) The magnitude of VBIAS should be at least VGS + Vdsat . One way to implement VBIAS is shown in Fig. 6.5-1(b) of the text. c) If the currents were not equal, the voltages at the drains of M3-M5 and M4-M6 will near VDD or near the sources of M1 and M2. Either, M5-M8 or M1-M4 will not be saturated. The best way to solve this problem is through the use of common mode feedback. This is illustrated in Fig. 5.2-15 of the text. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-45 Problem 5.3-14 Design a cascode CMOS amplifier using Fig. 5.3-7 for the following specifications. VDD = 5V, Pdiss ≤ 0.5mW, |Av| ≥ 100V/V, vOUT(max) = 3.5V, vOUT(min) = 1.5V, and slew rate of greater than 5V/µs for a 5pF capacitor load. Verify your design by simulation. Solution 1.) The slew rate should be at least 5 V/µs driving a 5 pF load. So, the load current should be at least 25 µA. Let, ID3 = ID2 = ID1 = 25 µA 2.) The maximum output voltage swing should be at least 3.5 V Let, Vdsat3 = 1.5 V W L 3 = 2ID3 K V' 2 P dsat 3 = 0.44 So, let us choose W L 3 = W L 4 =1 3.) The small-signal voltage gain should be at least 100 Av ≅ −gm1rds3 or, ( ) W L 1 = Av λ3 2 ID1 2K ' N = 2.84 So, let us choose W L 1 = 3 Vdsat1 = 0.39 V 4.) The minimum output voltage swing should be greater than 1.5 V Vout (min) = Vdsat1 + Vdsat 2 or, Vdsat 2 = Vout (min) − Vdsat1 = 1.11 V or, W L 2 = 2ID2 K V' 2 N dsat 2 = 0.37 So, let us choose W L 2 =1 5.) The bias voltage VGG2 can be calculated as VGG2 = VT1 + Vdsat1 + Vdsat 2 = 1.76 V 6.) The power dissipation is given by Pdiss = ID3VDD = 0.125 mW CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-46 Problem 5.4-01 Assume that io = Ai(ip-in) of the current amplifier shown in Fig. P5.4-1. Find vout/vin and compare with Eq. (5.4-3). Solution i1 R1 Referring to the figure, i p = 0 . vs ( ) So, io = Ai ip − in = −Aiin Now, vin = i1R1 vo = −i2R2 ( ) or, vo = i1 − in R2 → vo = vin R1 + io Ai R2 i2 R2 in io ip Ai vo Current Amplifier Figure P5.4-1 −vo or, vo = vin R1 + R2 Ai R2 → R2 vo = R1 vin 1 + 1 Ai Eq. (5.4-3) Problem 5.4-02 The simple current mirror of Fig. 5.4-3 is to be used as a current amplifier. If the W/L of M1 is 1µm/1µm, design the W/L ratio of M2 to give a gain of 10. If the value of I 1 is 100µA, find the input and output resistance assuming the current sources I1 and I2 are ideal. What is the actual value of the current gain when the input current is 50µA? Solution The current gain can be expressed as (W L) Ai = (W 2 L) 1 For Ai = 10, W2 = 10 µm and L2 = 1 µm. If I1 = 100 µA, then I2 = 1000 µA. The input resistance is Rin = 1 gm1 = 6.74 kΩ The output resistance is Rout = 1 λN ID2 = 25 kΩ When I1 = 50 µA, then I2 = 500 µA and the current gain ( Ai) is still 10. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-47 Problem 5.4-03 The capacitances of M1 and M2 in Fig. P.4-3 are Cgs1=Cgs2=20fF, Cgd1=Cgd2 =5fF, and Cbd1=Cbd2=10fF. Find the low frequency current gain, iout/iin, the input resistance seen by iin, the output resistance looking into the drain of M2, and the -3dB frequency in Hz. 100µA iin VDD VDD 100µA iout M1 5µm/1µm M2 5µm 1µm RL=0 Solution iin gm1 + gds1 V1 C1 - gm1V1 iout S99E2S3 Fig. P5.4-3 (a.) Small-signal model is shown. Note that C1=Cbd1 + Cgs2 + Cgd2 + Cgs1 = 55fF, gm1=gm2 = W1 2KN· L1 I1 = 2·110·5·100 = 332µS and gds1 = λNI1 = 0.04·100µA = 4µS The current gain is, iout = gm2gm1+gidins˚1+sC1 The low frequency current gain is Ai(0) = gm2 gm1+gds1 = 332 336 = 0.988 ⇒ 1 1 Rin = gm1+gds1 = 336µS = 2.796kΩ Ai(0) = 0.988 ⇒ Rin = 2796Ω Rout = 1/gds2 = 1/gds1 = 250kΩ ⇒ Rout = 250kΩ ω-3dB = gm1+gds1 C1 = 332µS+4µS 55fF = 6.11x109 ⇒ f-3dB = 973MHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-48 Problem 5.4-04 Derive an expression for the small-signal input resistance of the current amplifier of Fig. 5.4-5(a). Assume that the current sink, I3, has a small signal resistance of rds4 in your derivation. Solution Referring to the figure vs3 = vx v g1 = vd 3 ≅ gm3 (gds3 + gds4 )v x ix Vx VDD I1 I2 M3 VGG3 M1 M2 rds4 ix = id1 + id3 or, ix = g m1vg1 + gm3vx or, ix = g m1 (g gm3 ds3 + g ds4 )v x + gm3vx or, Rin = vx ix ≅ (gds3 + g ds4 ) g m1 g m3 Problem 5.4-05 Show how to make the current accuracy of Fig. 5.4-5(a) better by modifying the circuit so that VDS1 = VDS2. Solution Referring to the figure, M3-M6 form a differential amplifier. If it is assumed that the smallsignal gain of this differential amplifier is large enough, then the bias voltages at the gates of M3 and M4 would almost be equal (because in presence of I1 large gain, the differential input ports would act as null ports). Thus, the drain bias voltages of M1 and M2 would almost be identical causing very good mirroring. It is also important to note that the bias voltage M1 at the drain of M4 could be very large as gate bias voltages for M1 and M2. One can use a PMOS differential amplifier in place of the shown NMOS differential amplifier to overcome this problem. VDD M5 M6 I2 M3 M4 M2 I3 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-49 Problem 5.4-06 Show how to use the improved high-swing current mirror of Sec. 4.4 to implement Fig. 5.4-7(a). Design the current amplifier so that the input resistance is 1kΩ and the dc bias current flowing into the input is 100µA (when no input current signal is applied) and the dc voltage at the input is 1.0V. Solution The high-swing cascode current VDD mirror, constitut-ing the transistors M1 through M4, is shown in the figure. The overall I i1 figure shows a differential current i1-i2 2I I iout amplifier. To design the high- i2 swing cascode current mirror, it is desired that i2 M3 M4 M7 M8 i1-i2 Rin = 1 kΩ or, g m1 = 1 µS or, W L 1 = W L 2 = 45.5 Let us assume M1 M2 VBias = VT + M5 M6 2VON Fig. S5.4-06 W L 3 = W L 4 = 45.5 Then, ignoring bulk effects VBIAS = VT 3 + Vdsat 3 + Vdsat1 = 1.1 V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-50 Problem 5.4-07 Show how to use the regulated cascode mirror of Sec. 4.4 to implement a single-ended input current amplifier. Calculate an algebraic expression for the small signal input and output resistance of your current amplifier. Solution iout ix vg3 M3 iin M1 vs3 M4 M2 + vgs3=(-gm1rds1)vs3 vs3 rds2 gm3vgs3 rds3 vx Referring to the figure, the current gain of the regulated cascode mirror can be expressed as (( )) Ai = iout iin ≅ W W L 2 L 4 The input resistance is given by Rin = 1 gm 4 The output resistance can be calculated as follows: ( ) vg3 = − gm1rds1 vs3 (1) ( ) Now, ix = gm3vgs3 + vx − vs3 rds3 or, ( ) ( ) ix = −gm3 gm1rds1 vs3 + vx − vs3 rds3 (2) Also, vs3 = ixrds2 (3) Using Eqs. (2) and (3), it can be shown that ( ) vx = ix gm1rds1gm r3 ds3rds2 or, ( ) Rout = vx ix = gm1rds1gm 3rds3rds2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-51 Problem 5.4-08 Find the exact expression for the small signal input resistance of the circuit shown when the output is short-circuited. Assume all transistors have identical W/L ratios, are in saturation and ignore the bulk effects. Simplify your expression by assuming that gm=100gds and that all transistors are identical. Sketch a plot of iout as a function of iin. Solution A small signal model for this problem is: gm4vgs4 Rin D2=G3=S4 D4 + rds4 - + vgs4 it vt vgs3 rds2 D3=G4 + - rds3 - gm3vgs3 I iin Rin M1 VDD I I M3 Figure P5.4-8 S2=S3 it = (gds2+gds4)vt - gm4vgs4 iout M4 M2 But, vgs4 = -gm3rds3vgs3 - vt and vgs3 = vt ∴ it = (gds2+gds4)vt + gm4(1+gm3rds3)vt Thus, Rin is Rin = vt it = 1 gds2+gds4+gm4 + gm3gm4rds3 ≈ 1 gm3gm4rds3 Sketching iout as a function of iin: i out Note that iD4 = I + iout and iD4 + iin = iD2 = iD1 = I 1 Therefore, I + iout = I - iin ⇒ iout = - iin 1 i in CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-52 Problem 5.4-09 Find the exact small signal expression for Rin for the circuit in Fig. P5.4-9. Assume VDC causes the current flow through M1 and M2 to be identical. Assume M1 and M2 are identical transistors and that the small signal rds of M5 can be ignored (do not neglect rds1 and rds2). Solution The small-signal model is shown below. We may write that, VDD Vb2 M1 Vb1 M5 M2 Rin + vin - VDD + M3 - VDC M4 vin = vd1 = (iin – gm1vgs1)rds1 + (iin+ gm2vgs2) rds2 Fig. 5.4-9 but vgs1 = - vs1 and vgs2 = vg2 – vs2 gm1vgs1 gm2vgs2 iin + D1 rds1 rds2 G2 = D3 = D4 + vin vd1 - S1=S2 vg2 G1=D2 gm2vd1 rds3 gm4vd1 rds4 - Fig. S5.4-9 ∴ vin = iin rds1 + gm1vs1rds1 + iin rds2 + gm2vg2rds2 - gm2vs2rds2 = iin rds1 + iin rds2 + gm2vg2rds2 = iin (rds1 + rds2) - gm2rds2 ggdms33++ggmd4s4 vin ∴ vin = (rds1 + rds2)iin gm2rds2(gm3+ gm4) → vin Rin = iin = (rds1 + rds2) gm2rds2(gm3+ gm4) 1 + gds3 + gds4 1 + gds3 + gds4 rds1 + rds2 or Rin = 1 + gm2rds2(gm3+ gm4)rds3||rds4 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-53 +2V Problem 5.4-10 A CMOS current amplifier is shown. Find the small signal values of the current gain, Ai = iout/iin, input resistance, Rin, and output resistance, Rout. For Rout, assume that gds2/gm6 is equal to gds1/gm5. Use the parameters of Table 3.1-3. iin Solution Since this is a new circuit, use the small signal model approach. The model for this problem is given below. iout = -(gm7v1 + gm8v2) 10/1 50µA M5 M7 100/1 Rin 10/1 M1 10/1 M3 iout M2 M4 Rout 10/1 10/1 100/1 M6 M8 10/1 50µA -2V S98FEP6 gm7i1 gm8i2 = - gm5 - gm6 gm7 gm7 = - gm5 (i1+i2) = gm5 iin → iout Ai = iin = -10 gm2vin i2 iin rds2 + i1 vin - v2 gm1vin rds1 v1 11 gm5 gm6 gm7v1 gm8v2 iout rds7 rds8 S98FES6 1 1 1 Rout = gds7+gds8 = (500µA)(0.04+0.05) = 45µS = 22.2kΩ Rin: iin = gm1vin + gm2vin + gds1(vin-v1) + gds2(vin-v2) gds1i1 gds2i2 gds1 = (gm1+gm2+gds1+gds2)vin - gm5 - gm6 = (gm1+gm2+gds1+gds2)vin - gm5 iin gds1 ∴ vin 1 + gm5 Rin = iin = gm1+gm2+gds1+gds2 , gm1 = 2KN·10·50 = 331.7µS, gds1= 2µS gm2 = 2KP·10·50 = 223.6µS, gds1= 2.5µS, and gm5 = gm2 Thus, Rin = 1 + 0.0112 331.7+223.6+2+2.5 = 1.8kΩ CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-54 Problem 5.4-11 Find the exact algebraic expression (ignoring bulk effects) for the following characteristics of the amplifier shown. VDD Express your answers in terms of gm’s and rds’s in the form of the ratio of two polynomials. (a.) The small signal voltage gain, Av = vout/vin., and current gain, Ai = iout/iin. M6 100µA M3 Rouitout vout (b.) The small signal input resistance, Rin. ∴ The small signal output resistance, Rout. Solution M2 M5 Riniin vin (a.) Small-signal model is shown below. Summing currents M4 M1 at the output node gives: gm2vin + gds2(vin-vout) = gds3vout Figure P5.4-11 vout gm2+gds2 rds3+gm2rds2rds3 or vin = gds2+gds3 = rds2+rds3 gm2vgs2 iin iout R gm2vin iin i iout + vin rds1 - rds2 rds3 + vgs2 = -vin + vout vin - - rds1 rds2 rds3 + vout - S98E2S3 (b.) The input resistance is best done by finding R and putting it in parallel with rds1. vin = (i-gm2vin)rds2 + irds3 → vin rds2+rds3 R = i = 1+gm2rds2 ∴ Rin = rds1||R = rds1||1r+dsg2m+2rrddss32 → rds1(rds2+rds3) Rin = rds1+rds2+rds3+gm2rds2rds1 rds2rds3 (c.) Rout = rds2||rds3 = rds2+rds3 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-55 Problem 5.4-12 Find the exact expression for the small signal input resistance of the circuit shown. Assume all transistors have identical W/L ratios, are in saturation and ignore the bulk effects. Simplify I your expression by assuming that gm=100gds and that all transistors are identical. Sketch a plot of iout as a function of iin. iin Solutions A small signal model for this problem is: gm4vgs4 Rin D2=G3=S4 D4 Rin M1 + rds4 - + vgs4 it vt vgs3 rds2 D3=G4 + - rds3 - gm3vgs3 S2=S3 it = (gds2+gds4)vt - gm4vgs4 But, vgs4 = -gm3rds3vgs3 - vt and vgs3 = vt ∴ it = (gds2+gds4)vt + gm4(1+gm3rds3)vt VDD I I iout M4 M3 M2 Figure P5.4-12 Thus, Rin is Rin = vt it = 1 gds2+gds4+gm4 + gm3gm4rds3 ≈ 1 gm3gm4rds3 Sketching iout as a function of iin: Note that iD4 = I + iout and iD4 + iin = iD2 = iD1 = I i out Therefore, I + iout = I - iin ⇒ iout = - iin 1 1 i in CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-56 Problem 5.5-01 Use the values of Table 3.1-2 and design the W/L ratios of M1 and M2 of Fig. 5.5-1 so that a voltage swing of ±3 volts and a slew rate of 5 volts/µs is achieved if RL = 10 kΩ and CL = 1 nF. Assume that VDD = −VSS = 5 volts and VGG2 = 2 volts. Solution ( ) ID2 = K ' P 2 W L 2 VDD − VGG2 − VT 2 2 For positive swing of the output voltage, the slew rate should be at least +5 V/µs. Thus, SR = ID2 CL ( ) Iout = ID2 = SR CL = 5 mA ( ) Now, W L 2 = KP' VDD 2ID2 − VGG2 − VT 2 2 → W L 2 ≅ 38/1 Also, for the output voltage to swing to +3 V, the load current into RL will be 0.3 mA. Since ID2 is greater than 0.3 mA, the output voltage would be greater than +3 V. For negative output voltage swing ( ) Iout = SR CL = 5 mA ID1 = −Iout + ID2 = 10 mA or, ( ) W L 1 = KN' 2ID1 VDD − VSS − VT1 2 → W L 1 = 2.1 ≅ 3/1 For Vout (min) = −3 V, Iout = −0.3 mA. Since ID1 > −Iout + ID2 , the output will be able to swing down to –3 V. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-57 Problem 5.5-02 Find the W/L of M1 for the source follower of Fig. 5.5-3a when VDD = −VSS = 5 V, VOUT = 1 V, and W2/L2 = 1 that will source 1 mA of output current. Use the parameters of Table 3.1-2. Solution Given, Vout = 1 V and VSS = −5 V So, VGS2 = 6 V ( ) ID2 = K ' N 2 W L 2 VGS 2 − VT 2 2 → ID2 = 1.55 mA Thus, ID1 = ID2 + Iout = 2.55 mA Due to body effects, the threshold voltage of M1 can be given by VT1 = VT 0 + γ 1 Vout − VSS = 1.68 V ( ) Now, W L 1 = KN' 2ID1 VDD − Vout − VT1 2 = 8.6/1 Problem 5.5-03 Find the small-signal voltage gain and output resistance of the source follower of Fig. 5.5-3b. Assume that VDD = −VSS = 5 V, VOUT = 1 V, ID = 50 µA, and the W/L ratios of both M1 and M2 are 20 µm/10 µm. Use the parameters of Table 3.1-2 where pertinent. Solution The small-signal voltage gain is given by ( ) Av = gm1 gm1 + gds1 + gds2 VT1 = VT 0 + γ 1 Vout − VSS → VT1 = 1.68 V gm1 = 2KN' W L ID1 1 → gds1 + gds2 = 4.5 µS ∴ Av = 0.943 V/V The output resistance is given by ( ) Rout = 1 gm1 + gds1 + gds2 = 6.37 kΩ gm1 = 148 µS CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-58 Problem 5.5-04 An output amplifier is shown. Assume that vIN can vary from -2.5V to +2.5V. Let KP’ = 50µA/V2, VTP = -0.7V, and λP = 0.05V-1. Ignore bulk effects. a.) Find the maximum value of vOUT, vOUT(max). +2.5V 200µA vOUT b.) Find the minimum value of vOUT, vOUT(min). vIN c.) Find the positive slew rate, SR+ when vOUT = 0V in volts/microseconds. d.) Find the negative slew rate, SR- when vOUT = 0V in volts/microseconds. 300/1 50pF 10kΩ -2.5V e.) Find the small signal output resistance (excluding the 10kΩ resistor) when vOUT = 0V. Solution ∴ When vIN = +2.5V, the transistor is shut off and vOUT(max) = 200µA·10k Ω = +2V ∴ When vIN = -2.5V, the transistor is in saturation (drain = gate) and the minimum output voltage under steady-state is, vOUT = -10kΩ(ID-200µA) = -10kΩ 50·2300(vOUT+2.5-0.7)2 - 200µA vOUT = -75(vOUT+1.8)2 +2 → vOUT2+3.6133vOUT + 3.21333 = 0 3.61333 (3.61333)2 - 4·3.21333 ∴ vOUT = - 2 ± 2 = -1.80667 ± 0.22519 It can be shown that the correct choice is vOUT(min) = -1.80667 + 0.22519 = -1.5815V c.) The positive slew rate is SR+ = 200µA 50pF = +4V/µs → SR+ = +4V/µs d.) The negative slew rate is found as follows. With vOUT = 0V, the drain current is ID = 7.5mA/V2(2.5-0.7)2 = 24.3mA Therefore, the sourcing current is 24.3mA-0.2mA = 24.1mA which gives a negative slew rate of SR- = 24.1mA 50pF = - 482V/µs → SR- = - 482V/µs e.) The output resistance, Rout, is approximately equal to 1/gm. Therefore, 1 L 1 Rout ≈ gm = 2KPIDW = = 408.2Ω 2·50·200·300 → Rout ≈ 408Ω CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-59 Problem 5.5-05 An output amplifier is shown. Assume that vIN can vary from -2.5V to +2.5V. Ignore +2.5V bulk effects. Use the parameters shown below. vIN a.) Find the maximum value of vOUT, 300µm 1µm vOUT(max). b.) Find the minimum value of vOUT, vOUT(min). 200µA 50pF c.) Find the positive slew rate, SR+ when vOUT = 0V in volts/microseconds. d.) Find the negative slew rate, SR- when -2.5V Figure P5.5-5 vOUT = 0V in volts/microseconds. e.) Find the small signal output resistance when vOUT = 0V. vOUT 10kΩ Solution (a.) When vIN = 2.5V, the transistor shuts off and vOUT(max) = 200µA·10kΩ = +2V (b.) Assume vIN = -2.5V. Therefore, the transistor is in saturation and the minimum output voltage under steady-state is, vOUT = -10kΩ(ID-200µA) = -10kΩ110x120-6·300(vOUT+2.5-0.7)2-200µA or vOUT = -165(vOUT+1.8)2 + 2V → vOUT2 + 3.6061 vOUT + 3.228 = 0 3.6061 (3.6061)2 - 4·3.228 ∴ vOUT = - 2 ± 2 = -1.8030 ± 0.1516 It can be shown that the correct choice is vOUT = -1.8030 + 0.1516 = -1.6514V Thus vOUT(min) = -1.6514V (c.) The positive slew rate is SR+ = 200µA 50pF = +4V/µs (d.) The negative slew rate is found as follows. With vOUT = 0V, the drain current is ID 110x10-6·300 = 2 (2.5-0.7)2 = 53.46mA Therefore, the sourcing current is 53.46mA - 0.2mA = 53.44mA which gives a negative slew rate of SR- = - 53.44mA 50pF = 1069V/µs (e.) The output resistance, Rout, is approximately equal to 1/gm. Therefore, 1 L 106 Rout = gm = 2KIDW = = 275.24Ω 2·110·300·200 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-60 Problem 5.5-06 For the circuit shown in Fig. P5.5-6, find the small signal voltage gain, vout/vin and the small signal output resistance, Rout. Assume that the dc value of vOUT is 0V and that the dc current through M1 and M2 is 200µA. Solution (Unfortunately the gate-source voltage is given on the schematic which causes a conflict with the problem statement of 200µA of current. We will use the 200µA in the solution.) The small-signal model for this problem is shown below. +5V vin M1 10/1 -5V M2 vout Rout -3V 10/1 -5V Fig. P5.5-6 + vgs1 gm1vgs1 gmb1vbs1 iout + rds1 rds2 vout - Fig. S5.5-6 663.3µS(0.4) gm1 = 2·110·200·10 µS = 663.3µS, gmb1 = 2 0.7 + 5 = 55.57µS, gds1 = gds2 = 0.04·200µA = 8µS Summing currents at the output, vout(gds1 + gds2) = gm1vgs1 + gmb1vbs1 = gm1vin - gm1vout - gmb1vout vout gm1 663.3 (e.) vin = gm1 + gmb1 + gds1 + gds2 = 663.3 + 55.57 + 8 + 8 = 0.9026 V/V vout Rout = iout 1 1 = gm1 + gmb1 + gds1 + gds2 = 663.3 + 55.57 + 8 + 8 = 1361Ω CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-61 Problem 5.5-07 Develop an expression for the efficiency of the source follower of Fig. 5.5-3b in terms of the maximum symmetrical peak-output voltage swing. Ignore the effects of the bulksource voltage. What is the maximum possible efficiency? Solution Efficiency (η) is expressed as Vout ( peak)2 ( ) ηmax = PRL Psup ply = 2RL VDD − VSS IQ The maximum output voltage swing is Vout (max) ≅ VDD − VT1 The minimum output voltage swing is Vout (min) ≅ VSS Assuming symmetrical maximum positive and negative output swings Vout ( peak) ≅ VDD − VT1 The quiescent current can be expressed as ( ) IQ = Vout (max) − Vout (min) 2RL or, ( ) IQ = VDD − VSS − VT1 2RL Thus, Vout ( peak)2 ( ) ( ( )( ) ) ηmax = 2RL VDD − VSS = IQ VDD − VT1 2 VDD − VSS VDD − VSS − VT1 Assuming VDD = −VSS = 5 V gives ηmax ≈ 20% CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-62 Problem 5.5-08 Find the pole and zero location of the source followers of Fig. 5.5-3a and Fig. 5.5-3b if Cgs1 = Cgd2 = 5fF and Cbs1 = Cbd2 = 30fF and CL = 1 pF. Assume the device parameters of Table 3.1-2, ID = 100 µA, W1/L1 = W2/L2 = 10 µm/10 µm, and VSB = 5 volts. Solution Cgd1 + vgs Cgs1 gm1vgs rds1 vin vout CL RL2=(gm2+gds2+gL)-1 a.) Referring to the figure The location of the zero of the follower is given by z = −gm1 = -14.9 GHz Cgs1 The location of the pole of the follower is given by ( ) p = − gm1 + gm2 + gds1 + gds2 + gL = -140.8 MHz ( ) Cgs1 + Cgs2 + Cbd1 + Cbd 2 + CL b.) Referring to the figure The location of the zero of the follower is given by z = −gm1 = -14.9 GHz Cgs1 The location of the pole of the follower is given by ( ) p = − gm1 + gds1 + gds2 + gL = -71.1 MHz ( ) Cgs1 + Cgs2 + Cbd1 + Cbd 2 + CL CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-63 Problem 5.5-09 Six versions of a source follower are shown below. Assume that K'N = 2K'P, λP = 2λN, all W/L ratios of all devices are equal, and that all bias currents in each device are equal. Neglect bulk effects in this problem and assume no external load resistor. Identify which circuit or circuits have the following characteristics: (a.) highest small-signal voltage gain, (b.) lowest small-signal voltage gain, (c.) the highest output resistance, (d.) the lowest output resistance, (e.) the highest vout(max) and (f.) the lowest vout(max). vin M1 M2 vin M1 M2 vin M1 VBP M2 VDD vout vout vout vout vout vout M2 vin M1 vin M2 vin M1 Circuit 1 Solution Circuit 2 M2 Circuit 3 M1 VBN Circuit 4 Circuit 5 VSS Circuit 6 FS02E1P1 (a.) and (b.) - Voltage gain. Small signal model: + + vout gm The voltage gain is found as: vin = gm+GL where GL is the load conductance. Therefore we get: vin - gmvin gmvout GL vout - Circuit 1 2 3 4 5 6 vout gmN gmP gmN gmP gmN gmP vin gmN+gmN gmP+gmP gmN+gmP gmP+gmN gmN+gdsN+gdsP gmP+gdsN+gdsP But gmN = 2 gmP and gdsN = 0.5gdsP, therefore Circuit 1 vout 1 vin 2 2 3 4 5 1 0.5858 0.4142 gmP 2 gmP+(gdsP+gdsN)/ 2 6 gmP gmP+gdsP+gdsN Thus, circuit 5 has the highest gain and circuit 4 the lowest gain (c.) and (d.) - Output resistance. The denominators of the first table show the following: Ckt.6 has the highest output resistance and Ckt. 1 the lowest output resistance. (e.) Assuming no current has to be provided by the output, circuits 2, 4, and 6 can pull the output to VDD. ∴ Circuits 2, 4 and 6 have the highest output swing. (f.) Assuming no current has to be provided by the output, circuits 1, 3, and 5 can pull the output to ground. ∴ Circuits 1, 3 and 5 have lowest output swing. Summary (a.) Ckt. 5 has the highest voltage gain (b.) Ckt. 4 has the lowest voltage gain (c.) Ckt. 6 has the highest output resistance (d.) Ckt. 1 has the lowest output resistance (e.) Ckts. 2,4 and 6 have the highest output (f.) Ckts. 1,3 and 5 have the lowest output CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-64 Problem 5.5-10 Show that a class B, push-pull amplifier has a maximum efficiency of 78.5% for a sinusoidal signal. Solution VBias Referring to the figure, assuming there is no cross-over distortion, the efficiency can be given by vIN VBias Vout ( peak)2 η= 2RL ( ) VDD − VSS Vout ( peak) πRL For maximum efficiency, it can be assumed vin that the output swing is symmetrical and the peak output voltage can be given by Vout ( peak) = VDD = −VSS Thus, VD2D η= 2RL ( ) VDD − VSS VD2D πRL vout vout(peak) or, η = π = 78.5% 4 id1 vout(peak)/RL VDD M1 VSS iOUT vOUT M2 VDD RL VSS Fig. S5.5-10A t t t id2 t -vout(peak)/RL CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-65 Problem 5.5-11 Assume the parameters of Table 3.1-2 are valid for the transistors of Fig. 5.5-5a. Design VBias so that M1 and M2 are working in class-B operation, i.e., M1 starts to turn on when M2 starts to turn off. VBias vIN Solution ( ) VGS1 = Vin + VBIAS − Vout VBias ( ) VGS2 = Vin − VBIAS − Vout In Class B operation, when M1 starts to turn on and M2 starts to turn off, the drain currents can be written as ID1 = ID2 + Iout or, ( ) ( ) K ' N 2 W L 1 VGS1 − VT1 2 = KP' 2 W L 2 VSG 2 − VT 2 2 + Vout RL Assuming, when Vin = 0, Vout = 0, we get ( ) ( ) K ' N 2 W L 1 VBIAS − VT1 2 = KP' 2 W L 2 VBIAS − VT 2 2 or, VBIAS − VT1 = VBIAS − VT 2 K ' P W L KN' L 2 W 1 or, VT1 − VBIAS = 1 − KP' KN' W L L 2 W 1 VT 2 KP' W L KN' L 2 W 1 VDD M1 VSS iOUT vOUT M2 VDD RL VSS Fig. S5.5-10A CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-66 Problem 5.5-12 Find an expression for the maximum and minimum output voltage swing for Fig. 5.5-5a. Solution To calculate the maximum output voltage swing, it can be assumed that the input is taken to VDD . Thus, ( ) VGS1 − VT1 = VDD + VBIAS − Vout (max) − VT1 ( ) and, VDS1 = VDD − Vout (max) ( ) ( ) So, VDS1 − VGS1 − VT1 = VBIAS − VT1 Thus, if VBIAS ≥ VT1, VDS1 ≥ (VGS1 − VT1) and M1 will be in saturation. Now, ID1 = IL or, ( ) K ' N W 2 L 1 VDD + VBIAS − Vout (max) − VT1 2 = Vout (max) RL or, ( ) Vout (max) = VDD + VBIAS − VT1 + Y ( ) ( ) ( where, Y = RLK ' N 1 W L) − 1 ( ) ( ( ) ) RLKN' 1 W L 1 2 2 + VDD + VBIAS − VT1 RLKN' W L 1 To calculate the minimum output voltage swing ID2 = −IL or, ( ) K ' P 2 W L 2 VSS − VBIAS − Vout (min) + VT 2 2 = − Vout (min) RL or, ( ) Vout (min) = VSS − VBIAS + VT 2 − Z ( ) (( ) ) where, ( Z = RLKP' 1 W L) − 2 ( ) ( ) RLKP' 1 W L 2 2 − 2 VSS − VBIAS RLK ' P W + VT 2 L 2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-67 Problem 5.5-13 Repeat the previous problem for Fig. 5.5-8. Solution Assuming M2 operate in triode region when Vin = VSS , the maximum output voltage swing can be calculated as follows: ID2 = Iout VTR2 vIN VTR1 VDD M2 iOUT M1CL RL vOUT or, Figure 5.5-8 Push-pull inverting CMOS amplifier. ( )( ) KP' W L 2 VSS − VDD + VTR 2 + VT 2 Vout (max) − VDD = Vout (max) RL or, Vout (max) = VDD ( ) 1 + KP' W L RL 2 VSS 1 − VDD + VTR 2 + VT 2 Assuming M1 operate in triode region when Vin = VDD , the minimum output voltage swing can be calculated as follows: ID1 = −Iout or, ( )( ) KN' W L 1 −VSS + VDD − VTR1 − VT1 Vout (min) − VSS = −Vout (min) RL or, Vout (min) = VSS ( ) 1 + KN' W L RL 1 1 −VSS + VDD − VTR1 − VT1 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-68 Problem 5.5-14 Given the push-pull inverting CMOS amplifier shown in Fig. 5.5-14, show how shortcircuit protection can be added to this amplifier. Note that R1 could be replaced with an active load if desired. Solution VDD VSS M9 ISC VDD VBIAS Vin M1 M3 Vout M2 VSS M7 M8 VSS VDD M5 M6 M4 ISC VSS The current source I SC in the figure represents the short circuit current whose value can be set as desired. The current through the transistors M2 and M3 need to be regulated for short circuit protection. The currents carried by M2 and M3 are mirrored into M4 and M9 respectively. When the current tends to increase in M2, the current in M4 would also increase. This would tend to increase the voltage at the drain of M5, but it will decrease the current in M5. Since the current carried by M4 and M5 are same, the gate bias of M4 as well as M2 cannot increase beyond a point where they both carry the maximum limit of the current as set by the short circuit current source. Similarly, the diode-connected transistor M9 would limit the gate bias of M3, thus limiting the output sinking current. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-69 Problem 5.5-15 If R1 = R2 of Fig. 5.5-12, find an expression for the small-signal output resistance Rout. Repeat including the influence of RL on the output resistance. Solution ( ) vg1 = vg2 = R1 R1 + R2 vx VDD or, vg1 = vg2 = 0.5vx id1 = 0.5gm1vx and, id 2 = 0.5gm2vx Now, ix = id1 + id 2 ( ) or, ix = 0.5 gm1 + gm2 vx R1 R2 (R1+R1R2)Vx id2 ix id1 Vx So, the output resistance becomes VSS ( ) Rout = vx ix = 2 gm1 + gm2 In presence of load (RL ), the output resistance will become ( ) [ ] Rout = 2 gm1 + gm2 || RL The presence of the load resistance (RL ) will tend to decrease the output resistance. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-70 Problem 5.5-16 Develop a table that expresses the dependence of the small-signal voltage gain, output resistance, and the dominant pole as a function of dc drain current for the differential amplifier of Fig. 5.2-1, the cascode amplifier of Fig. 5.3-1, the high-output-resistance cascode of Fig. 5.3-6, the inverter of Fig. 5.5-1, and the source follower of Fig. 5.5-3b. Solution Circuit Av Rout |p1| Differential Amplifier Cascode Amplifier High-Gain Cascode Amp. Inverting Amplifer Source Follower VDD M3 M4 vout VGG3 + M1 M2 vi - VGG2 VBias M5 + vin FigS5.2-05 - VDD M3 + M2 VGG4 VGG3 vout VGG2 M1 - vin M4 VDD M3 VGG2 ID vo M2 vIN Rout VDD M2 vOUT M1 vIN VGG2 VDD M1 VSS iOUT vOUT M2 VSS Fig. 5.5-3(b) M1 Figure 5.1-1 Figure 5.3-1 Fig. 5.3-6(a) 2 λΝ+λP KN'W 2IDL1 - 2KN'W1 See Eq. (5.337) L1IDλP2 Gain ∝ ID-1 -2 λΝ+λP KN'W 2IDL1 1 ∝ ID ∝ ID 1 ∝ ID ∝ ID 1 ∝ ID-1.5 ∝ ID1.5 1 ∝ ID ∝ ID Error! 1 ∝ ID ∝ ID0.5 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.6-01 Propose an implementation of the VCCS of Fig. 5.6-2(b). Solution VDD M3 M4 io + M1 vi - VBias M2 M5 FigS5.6-01 Problem 5.6-02 Propose an implementation of the VCVS of Fig. 5.6-3(b). Solution VDD M3 M4 + M1 M2 vi - M5 VBias M6 vo M7 FigS5.6-02 Page 5-71 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.6-03 Propose an implementation of the CCCS of Fig. 5.6-4(b). Solution VDD VDD VDD I i1 2I I io i2 i2 i1-i2 M1 M2 M3 M4 Page 5-72 Fig. S5.6-03 Problem 5.6-04 Propose an implementation of the CCVS of Fig. 5.6-5(b). Solution VDD VDD VDD VDD I 2I I i1 M6 i2 i2 i1-i2 vo M1 M2 M3 M4 M7 VBias Fig. S5.6-04 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-1 CHAPTER 6 – HOMEWORK SOLUTIONS Problem 6.1-01 Use the null port concept to find the voltage transfer function of the noninverting voltage amplifier shown in + Fig. P6.1-1. + - + Solution vin Let, v1 and v2 be the voltages at the non-inverting and inverting terminals respectively. Using the Null-port - R1 R2 vout - concept and assuming that the lower negative rail is at ground Figure P6.1-1 v1 = v2 = vin Applying KCL (vout − v2 ) = (v2 ) R2 R1 → (vout − vin ) = (vin ) R2 R1 or, vout vin = 1 + R2 R1 Problem 6.1-02 Show that if the voltage gain of an op amp approaches infinity that the differential input becomes a null port. Assume that the output is returned to the input by means of negative feedback. Solution Referring to the figure, in Rs the presence of negative series feedback, the differential input can be Vin written as vin = vS − fvout Vi Rin Ro Vout AvVi and, vout = Avvin fVout So, vin = vS − fAvvin or, vin = vS (1+ fAv ) For a finite value of the negative feedback factor (f ) , if the value of open-loop differential gain (Av ) tends to become infinite, then the value of the differential input voltage(vin ) would tend to become zero and become a null port. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-2 Problem 6.1-03 Show that the controlled source of Fig. 6.1-5 designated as v1/CMRR is in fact a suitable model for the common-mode behavior of the op amp. v1 CMRR Ricm IB2 vn2 v2 * VOS in2 Cid Rid v1 Ricm IB1 - Rout vout + Ideal Op Amp Figure 6.1-5 A model for a nonideal op amp showing some of the nonideal linear characteristics. Solution Referring to the figure, considering only the source representing the common-mode behavior, v1 / CMRR , the following analysis is carried out The common-mode input, vcm , is given by vcm = v1 = v2 Thus, the differential input is vid = v1 − v2 + v1 CMRR or, vid = v1 CMRR The output voltage is given by vout = Avd vid and, the common-mode rejection ratio is given by CMRR = Avd Acm where, Avd and Acm are the differential and common-mode gains respectively. Thus, vout = Avd vid = (CMRR)(Acm ) v1 CMRR or, vout = (Acm )v1 → vout = (Acm )vcm This expression proves that the source v1 / CMRR represents the common-mode behavior of the op amp. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-3 Problem 6.1-04 Show how to incorporate the PSRR effects of the op amp into the model of the nonideal effects of the op amp given in Fig. 6.1-5. Solution Referring to the figure, the sources (vdd / PSRR+ ) and (vss / PSRR− ) would model the positive PSRR and negative PSRR respectively. v1 CMRR vdd PSRR+ Ricm IB2 vn2 v2 * VOS vss PSRR- in2 Cid Rid v1 Ricm IB1 - Rout vout + Ideal Op Amp Problem 6.1-05 Replace the current mirror load of Fig. 6.1-8 with two separate current mirror and show how to recombine these currents in an output stage to get a push-pull output. How can you increase the gain of the configuration equivalent to a two-stage op amp? Solution Referring to the figure, if the aspect ratios of M3 through M6 are same and that of M7 and M8 are equal, then the small-signal gain of this configuration becomes equivalent to a two- stage op amp. The small-signal gain of this configuration is given by Av = (g gm2(gm6 + gm5 ds2 + gds4 )(gds6 + ) g ds8 ) VDD M5 M3 M4 M6 M1 M2 Vout M7 M8 VBIAS M5 VSS CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-4 Problem 6.1-06 Replace the I→I stage of Fig. 6.1-9 with a current mirror load. How would you increase the gain of this configuration to make it equivalent to a two-stage op amp? Solution In the figure, the transistor M4 is a diode-connected transistor. VBias M3 VDD M12 M13 + M1 M2 vin - M10 M11 vout VBias M4 VBias M8 M9 M5 M6 M7 V→I I→I VSS I→V Fig. S6.1-6 The gain in the above circuit is already at the level of a two-stage op amp. The gain could easily be increased by making the W/L ratio of M7 to M4 and M6 to M5 greater than one. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-5 Problem 6.2-01 Develop the expression for the dominant pole in Eq. (6.2-10) and the output pole in Eq. (6.2-11) from the transfer function of Eq. (6.2-9). Solution The transfer function is given by Equation (6.2-9). Assuming the dominant pole and the output pole are wide apart, the dominant pole, p1 , can be calculated as the root of the polynomial [1+ s{RI (CI + CC )+ RII (CII + CC )+ gmII RI RII CC }]= 0 where, the effect due to the s2 term is neglected assuming the dominant pole is a low frequency pole. p1 = {RI (C I + CC )+ RII −1 (CII + CC )+ gmII RI RII CC } Considering the most dominant term p1 ≅ {g mII −1 RI RII CC } To compute the output pole (which is assumed to be at high frequency), the polynomial with the s and s2 terms are considered. [ ] s{RI (CI + CC )+ RII (CII + CC )+ gmII RI RII CC }+ s 2{RI RII (CI CII + CI CC + CCCII )} = 0 or, p2 = − {RI (CI + CC )+ RII (CII + CC )+ gmII RI RII CC } {RI RII (CI CII + CI CC + CC CII )} or, p2 ≅ − {gmII RI RII CC } {RI RII (CC CII )} or, p2 ≅ − {gmII } {CII } CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-6 Problem 6.2-02 Fig. 6.2-7 uses asymptotic plots to illustrate the difference between an uncompensated and compensated op amp. What is the approximate value of the real phase margin using the actual curves and not the asymptotic approximations? Solution Assume that the open-loop gain can be expressed as L(jω) = s p1 -Av0 + 1 s GB + 1 where p1 is the dominant pole The magnitude and phase shift of the open-loop gain can be expressed as, | L(jω)| = Av0 pω12 + 1 ω 2 G B +1 Arg[L(jω)] = ±180° - tan-1(ω/p1) - tan-1(ω/GB) At frequencies near GB, we can simplify these expression as, | L(jω)| ≈ GB ω ω 2 G B +1 Arg[L(jω)] = ±180° - 90° - tan-1(ω/GB) = 90° - tan-1(ω/GB) The unity gain frequency is found as, GB ωο =1 → GωBο 2 + 1 (ωο/GB)4 + (ωο/GB)2-1 = 0 (ωο/GB)2 = 0.5 ± 0.5 1+4 = 0.6180 The phase margin becomes, → ωο = 0.7862GB Arg[L(jωο)] = 90° - tan-1(ωο/GB) = 90° - tan-1(0.7862) = 90° - 38.173° = 51.83° ∴ The actual phase margin is 51.83° compared to 45° estimated from the Bode plot. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-7 Problem 6.2-03 Derive the relationship for GB given in Eq. (6.2-17) of Sec. 6.2. Solution The small signal voltage gains of the two stages can be given by Av1 = gm1RI Av2 = gm2RII And, the overall small-signal voltage gain is given by Av = gm1RI gm2RII Assuming the dominant pole is much smaller than the output pole, and the Gain-bandwidth frequency is smaller than the output pole, the overall transfer function of the op amp can be approximated by a single dominant pole, p1 . Av (s) = Av 1 + s p1 where, p1 ≅ {g mII −1 RI RII CC } or, Av ( jω ) = 1 Av + jω p1 It can be seen that at ω ≅ Av p1 , Av (jω ) = 1 So, the Gain-bandwidth frequency, ωGB , is given by ω GB ≅ Av p1 = gmI CC CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-8 Problem 6.2-04 For an op amp model with two poles and one RHP zero, prove that if the zero is 10 times larger than GB, then in order to achieve a 45° phase margin, the second pole must be placed at least 1.22 times higher than GB. Solution Given, z = 10(GB) The transfer function is given by Av ( s) = 1 + Av 1 − s p1 1 s z + s p2 The phase margin, PM, can be written as PM = 180o − tan −1 GB p1 + tan −1 GB p2 + tan −1 GB z or, 45 o = 180o − 90 o + tan −1 GB p2 + 5.7o → tan−1 GB p2 = 39.3 o or, p2 = 1.22(GB) Problem 6.2-05 For an op amp model with three poles and no zero, prove that if the highest pole is 10 times GB, then in order to achieve 60° phase margin, the second pole must be placed at least 2.2 times GB. Solution The transfer function is given by Av (s) = 1 + Av s p1 1 + s p2 1 + s p3 The phase margin, PM, can be written as PM = 180o − tan −1 GB p1 + tan −1 GB p2 + tan −1 GB p3 or, 60 o = 180o − 90 o + tan −1 GB p2 + 5.7o → tan−1 GB p2 = 24.3o or, p2 = 2.2(GB) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-9 Problem 6.2-06 Derive the relationships given in Eqs. (6.2-34) through (6.2-37) in Sec. 6.2. Solution The transfer function is given by Equations (6.2-32) through (6.2-36). Now, the denominator of Equation (6.2-32) cannot be factorized readily. So, the roots of this polynomial can be determined intuitively. The zero can be calculated as 1 − s CC g mII − RzCC = 0 or, z= −1 CC RZ − 1gmII The dominant pole, p1 , is given by [1+ s{RI (CI + CC )+ RII (CII + CC )+ gmII RI RII CC + RZ CC }]= 0 where, the effect due to the s2 and higher order terms are neglected assuming the dominant pole is a low frequency pole. p1 = {RI (CI + CC )+ RII (C II −1 + CC )+ gmII RI RII CC + RZ CC } Considering the most dominant term p1 ≅ {g mII −1 RI RII CC } To compute the output pole (which is assumed to be at high frequency), the polynomial with the s and s2 terms from Equations (6.2-34) and (6.2-35) are considered. or, p2 = − {RI (CI + CC )+ RII (CII + CC )+ gmII RI RII CC + RZ CC } {RI RII (CI CII + CI CC + CC CII )+ RZ CC (RI CI + RII CII )} or, p2 ≅ − {gmII RI RII CC } {RI RII (CC CII )} or, p2 ≅ − {gmII } {CII } To compute the third pole, p4 , the polynomial with the s2 and s3 terms from Equations (6.2-35) and (6.2-36) are considered. or, p4 = − {RI RII (CI CII + CI CC + CC CII )+ RZ CC (RI CI RI RII RZ CI CII CC + RII CII )} or, p4 ≅ − {RI RII CII CC } RI RII RZ CI CII CC or, p4 ≅ −1 RZ CI CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-10 Problem 6.2-07 Physically explain why the RHP zero occurs in the Miller compensation scheme illustrated in the op amp of Fig. 6.2-8. Why does the RHP zero have a stronger influence on a CMOS op amp than on a similar type BJT op amp? Solution Referring to the figure and considering the transistor M6 , there are two paths from the input (gate) to the output (drain): inverting and non-inverting. The signal current in the inverting path is given by VDD M6 iinv = gm6vg6 The signal current in the non-inverting path is given by V1 ( ) inon−inv = v g6 − vout sCC The zero is created when iinv Cc inon-inv Vout iinv = inon−inv and iout = 0 ( ) or, gm6vg6 = vg6 − vout sCC or, vout = (− gm6 + sCC ) vg6 sCC Thus, the RHP zero is given by the numerator (− gm6 + sCC ) . The RHP zero has a stronger (degrading) influence in MOS than in BJT as gm, MOS < gm, BJT and, the RHP zero is closer to the Gain-bandwidth frequency thus decreasing the phase margin. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-11 Problem 6.2-08 A two-stage, Miller-compensated CMOS op amp has a RHP zero at 20GB, a dominant pole due to the Miller compensation, a second pole at p2 and a mirror pole at -3GB. (a) If GB is 1MHz, find the location of p2 corresponding to a 45° phase margin. (b) Assume that in part (a) that |p2| = 2GB and a nulling resistor is used to cancel p2. What is the new phase margin assuming that GB = 1MHz? (c) Using the conditions of (b), what is the phase margin if CL is increased by a factor of 4? Solution a.) Since the magnitude of the op amp is unity at GB, then let ω = GB to evaluate the phase. Phase margin= PM = 180° - tan-1G|p1B| - tan-1G|p2B| - tan-1G|p3B| - tan-1G|z1B| But, p1 = GB/Ao, p3 = -3GB and z1 = -20GB which gives PM = 45° = 180° - tan-1(Ao) - tan-1G|p2B| - tan-1(0.33)- tan-1(0.05) 45° ≈ 90° - tan-1G|p2B| - tan-1(0.33)- tan-1(0.05) = 90° - tan-1G|p2B| - 18.26° - 2.86° ∴ tan-1G|p2B| = 45° - 18.26° - 2.86° = 23.48° → GB |p2| = tan(23.84°) = 0.442 p2 = - 2.26·GB = -14.2x106 rads/sec b.) The only roots now are p1 and p3. Thus, PM = 180° - 90° - tan-1(0.33) = 90° - 18.3° = 71.7° c.) In this case, z1 is at -2GB and p2 moves to -0.5GB. Thus the phase margin is now, PM = 90° - tan-1(2) + tan-1(0.5) - tan-1(0.33) = 90°-63.43°+26.57°-18.3° = 34.4° CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.2-09 Derive Eq. (6.2-53). Solution Cc -A Page 6-12 Vi gmIIvi CII RII Vout Referring to the figure, applying KCL ( ) −Avi(s) − vout (s) sCC = gmII vi (s) + sCII + 1 RII vout (s) or, ( ) sACC + gmII v i ( s) = − sCII +1 RII + sCC vout (s) or, ( ) vout (s) = − sACC + gmII v i (s) sCII + 1 RII + sCC s + gmII or, vout (s) = − ACC ACC ( ) vi(s) CC + CII s + 1 ( ) RII CC + CII CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-13 Problem 6.2-10 For the two-stage op amp of Fig. 6.2-8, find W1/L1, W6/L6, and Cc if GB = 1 MHz, |p2| = 5 GB, z = 3 GB and CL = C2 = 20 pF. Use the parameter values of Table 3.1-2 and consider only the two-pole model of the op amp. The bias current in M5 is 40 µA and in M7 is 320 µA. Solution Given GB = 1 MHz. VDD p2 = 5GB z = 3GB CL = C2 = 20 pF Now, p2 = gm 6 C2 or, M3 M4 C3 - M1 M2 vin + Cc C1 M6 vout C2 gm6 = 628.3µS or, W L 6 = gm 2 6 2K ' P ID 6 ≅ 12.33 + VBias M5 M7 - VSS Figure 6.2-8 A two-stage op amp with various parasitic and circuit capacitances shown. RHP zero is given by z = gm6 CC or, CC = gm 6 z = 33.3pF Finally, Gain-bandwidth is given by GB = gm1 CC or, gm1 = 209.4 µS or, W L 1 = gm12 2KN' ID1 ≅ 10 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-14 Problem 6.2-11 In Fig. 6.2-13, assume that RI = 150 kΩ, RII = 100 kΩ, gmII = 500 µS, CI = 1 pF, CII = 5 pF, and Cc = 30 pF. Find the value of Rz and the locations of all roots for (a) the case where the zero is moved to infinity and (b) the case where the zero cancels the next highest pole. Solution (a.) Zero at infinity. 1 1 Rz = gmII = 500µS Rz = 2kΩ Check pole due to Rz. −1 -1 p4 = RzCI = 2kΩ·1pF = -500x106 rps or 79.58 MHz The pole at p2 is p2 ≅ CICII −gmIICc + CcCI + CcCII ≅ −gmII CII = -500µS 5pF = 100x106 rps or 15.9 MHz Therefore, p2 is the next highest pole. (b.) Zero at p2. Rz = C c +C Cc I I (1/gmII) = 30+5 30 1 500µS = 2.33kΩ Rz = 2.33kΩ CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-15 Problem 6.3-01 Express all of the relationships given in Eqs. (6.3-1) through (6.3-9) of Sec. 6.3 in terms of the large-signal model parameters and the dc values of drain current. Solution SR = I5 CC Av1 = − 2 K ’ N (W L)1 I1(λ P + λN )2 (6.3-1) (6.3-2) Av2 = − 2K ’ P (W L)6 I6(λP + λ N )2 (6.3-3) GB = 2 K ’ N (W L)1 I1 CC p2 = − 2 K ’ p (W L)6 I6 CL z1 = 2K ’ p (W L)6 I6 CC Positive CMR Vin (max) = VDD − I5 K ’ P (W L )3 − VT 03 (max) + VT1(min) Negative CMR (6.3-4) (6.3-5) (6.3-6) (6.3-7) Vin (min) = VSS + I5 + K ’ N (W L )1 2I 5 K ’ N (W L )5 + VT1(max) (6.3-8) VDS(sat) = 2IDS β (6.3-9) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-16 Problem 6.3-02 Develop the relationship given in step 5 of Table 6.3-2. Solution Referring to the figure, p3 is generated at the drain of M3 . Resistance looking into the drain of M3 is given by RIII = (g m3 + 1 g ds3 + g ds1 ) ≅ 1 g m3 The total capacitance at the drain of M3 is given by ( ) CIII = Cgs3 + Cgs4 + Cbd3 + Cbd1 + Cgd1 ≅ 2C gs3 Thus, the pole at the drain of M3 is given by p3 = −1 RIII CIII or, p3 = − gm3 2C gs3 Now, if gm3 2C gs3 > 10GB , then the contribution due to this pole on the phase margin is less than 5.7o, i.e., this pole can be neglected. Problem 6.3-03 Show that the relationship between the W/L ratios of Fig. 6.3-1 which guarantees that VSG4 = VSG6 is given by S6/S4 = 2(S7/S5) where Si = Wi/Li. Solution Let us assume that VSG4 = VSG6 (1) or, VT 4 + Vdsat4 = VT 6 + Vdsat6 → VT 4 = VT 6 So, Vdsat4 = Vdsat6 → 2I4 = 2I6 K ’ P (W L )4 K ’ P (W L)6 or, (W (W L )6 L )4 = I6 I4 = I7 I4 → (W (W L )6 L )4 = 2I 7 I5 Since, VGS5 = VGS7 , we have (W (W L )6 L )4 = (W 2 (W L )7 L)5 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-17 Problem 6.3-04 Draw a schematic of the op amp similar to Fig. 6.3-1 but using p-channel input devices. Assuming that same bias currents flow in each circuit, list all characteristics of these two circuits that might be different and tell which is better or worse than the other and by what amount (if possible). Solution In working this problem we shall assume that KN’>KP’. +5V +5V M3 M4 M6 VBias Cc M5 M7 + M1 M2 v-in M5 VBias vout vi-n vout + M1 M2 Cc M7 M3 M4 M6 Characteristic Noise Phase margin Gainbandwidth Vicm(max.) Vicm(min.) Sourcing output current Sinking output current -5V Circuit 1 -5V Circuit 2 Fig. S6.3-04 Circuit 1 Worse but not by much because the first stage gain is higher. Poorer (gmI larger but gmII is smaller) Larger (GB = gmI/Cc) Larger Smaller Large Circuit 2 Better but degraded by the lower first stage gain Better Smaller Smaller Larger Constrained Constrained Large CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-18 Problem 6.3-05 Use the op amp designed in Ex. 6.3-1 and assume that the input transistors, M1 and M2 have their bulks connected to -2.5V. How will this influence the performance of the op amp designed in Ex. 6.3-1? Use the W/L values of Ex. 6.3-1 for this problem. Wherever the performance is changed, calculate the new value of performance and compare with the old. Solution Referring to the design in Example. 6.3-1, it can be shown that the threshold voltages of the input transistors M1 and M2 are increased due to body effect(VBS ≠ 0) VBS1 = VBS 2 = −VDS5 Let us assume that VDS5 = 1 V. Then, ( ) VT1 = VT 2 = VT 0 + γ N 2φ + VSB1 − 2φ or, VT1 = VT 2 = 0.89 V Assuming that the bias currents in the various branches remain the same, the small-signal gm and gds values will remain the same. Considering all the performance specifications of the op amp, only the ICMR will be effected. The maximum input common-mode voltage can be given by Vin (max) = VDD + VT1(min) − VT3 (max) − 2I 3 K ’ P (W L)3 or, Vin (max) = 2.5 + 0.55 − (0.89 + 0.15) − 0.2 = 1.81 V The original value of Vin (max) was 2 V. The minimum input common-mode voltage can be given by Vin (min) = VSS + VT1(max) + 2I1 + K ’ N (W L)1 2I5 K ’ N (W L)5 or, Vin (min) = −2.5 + 0.89 + 0.15 + 0.3 + 0.35 = −0.81 V The original value of Vin (min) was -1 V. The new value of ICMR is 2.62 V as compared to 3 V. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-19 Problem 6.3-06 Repeat Ex. 6.3-1 for a p- channel input, two-stage op amp. Choose the same currents for the first-stage and second-stage as in Ex. + 6.3-1. vin - Solution Following the steps of Ex. 6.3-1 we have the following: + VBias - M1 M3 M5 M2 M4 VDD Cc M6 vout CL M7 Cc = 3pF, I5 = 30µA, VSS FigS6.3-06 30 x 10-6 (W/L)3 = (110x10-6)[2.5 − 2 − .85 + 0.55]2 = 6.82 → W3 = W4 = 7µm Next, we find that gm1 = (5x106)(2π)(3x10-12) = 94.25µS which gives (W/L)1 = (W/L)2 = gm12 2K’NI1 = (94.25)2 2·50·15 = 5.92 → W1= W2 = 6µm Calculating VSD5(sat) we get VDS5 = (−1) − (−2.5) − 30x10-6 50x10-6·3 - .85 = 0.203V 2(30 x 10-6) ∴ (W/L)5 = (50 x 10-6)(0.203)2 = 29.1 → W5 = 29µm Next, we find gm4 ≈ 150µS which gives gm6 S6 = S4 gm4 942.5 = 7· 150 = 43.4 ≈ 43 The output stage current is, → W6 = 43µm (942.5 x 10-6)2 I6 = (2)(110 x 10-6)(43) = 93µA ∴ (W/L)7 = (W/L)59230µµAA = 29(93/30) = 89.9 → W7 = 90µm The gain and power dissipation are identical with that in Ex. 6.3-1. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-20 Problem 6.3-07 For the p-channel input, CMOS op amp of Fig. P6.3-7, calculate the open-loop, lowfrequency differential gain, the output resistance, the power consumption, the powersupply rejection ratio at DC, the input common-mode range, the output-voltage swing, the slew rate, the common-mode rejection ratio, and the unity-gain bandwidth for a load capacitance of 20 pF. Assume the model parameters of Table 3.1-2. Design the W/L ratios of M9 and M10 to give a resistance of 1/gm6 and use the simulation program SPICE to find the phase margin and the 1% settling time for no load and for a 20 pF load. Solution Bias current calculation: VT 8 + VON 8 + I8 .RS = Vdd − Vss or, VT 8 + 2.I8 3.K / p = 5 − I8.Rs. (1) Solving for I8 quadratically gives, I8 =_36µA, I5 =_36µA, and I7 =_60µA Using the formula, gm = 2.K / W .I L and gds = λI we get, gm2 = 60µS , gds2 = 0.9µS , gds4 = 0.72µS (2) gm6 = 363µS , gds6 = 3µS , gds7 = 2.4µS (3) Small-signal open-loop gain: The small-signal voltage gain can be expressed as, AV 1 = − ( g ds2 g m2 + gds4 ) = −37 and AV 2 = − gm6 (gds6 + gds7 ) = −67 Thus, total open-loop gain is, Av = Av1·Av2 = 2489V/V (3) Output resistance: Rout = ( g ds6 1 + g ds7 ) = 185KΩ (5) Power dissipation: Pdiss = 5(36 + 36 + 60)µW = 660µW (6) ICMR: Vin,max = 2.5 − VT 1 −VON1 − VON 5 = 0.51V (7) Vin,min = −2.5 − VT1 + VT 3 + VON 3 = −2.21V (8) Output voltage swing: V0,max = 2.5 − VON 7 = 1.81V (9) Slew Rate: Slew rate under no load condition can be given as SR = I5 CC = 6V / µs CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-21 Problem 6.3-7 - Continued In presence of a load capacitor of 20 pF, slew rate would be, SR = minCI5c, I7 CL CMRR: Under perfectly balanced condition where I1 = I2 , if a small signal common-mode variation occurs at the two input terminals, the small signal currents i1 = i2 = i3 = i4 and the differential output current at node (7) is zero. So, ideally, common-mode gain would be zero and the value for CMRR would be infinity. GBW: Let us design M9 and M10 first. Both these transistors would operate in triode region and will carry zero dc current. Thus, Vds9 = Vds10 ≅ 0 . The equation of drain current in triode region is given as, ID ≅ K/W L (VGS − VT ).VDS . The on resistance of the MOS transistor in triode region of operation would be, RON = K/W L (VGS − VT ). 1 It is intended to make the effective resistance of M9 and M10 equal to gm6 . So, K’9WL99 (VGS9-VT9) + K’10WL1100 (VGS10-VT10) = gm6 (11) VD4 = VD3 = −2.5 + VT 3 + VON 3 = −1.51V Thus, VGS9 ≅ 4V and VGS10 ≅ −1V . Putting the appropriate values in (11), we can solve for the aspect ratios of M9 and M10. One of the solutions could be, K’9WL99 1 =1 and K’10WL1100 = very small (12) The dompi1na=n−t p2(og.πlde.sA4cVo+1u.CglddCs2b)e calculated as, = −1.16KHz. And the load pole would be, p2 = − gm6 2.π .CL = −2.8MHz. for a 20 pF load. It can be noted that in this problem, the product of the open-loop gain and the dominant pole is approximately equal to the load pole. Thus, the gain bandwidth is approximately equal to 2.8 MHz and the phase margin would be close to 45 degrees. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-22 Problem 6.3-08 Design the values of W and L for each transistor of the CMOS op amp in Fig. P6.3-8 to achieve a differential voltage gain of 4000. Assume that K'N = 110 µA/V2, K'P = 50 µA/V2, VTN = −VTP = 0.7 V, and λN = λP = 0.01 V-1. Also, assume that the minimum device dimension is 2 µm and choose the smallest devices possible. Design Cc and Rz to give GB = 1 MHz and to eliminate the influence of the RHP zero. How much load capacitance should this op amp be capable of driving without suffering a degradation in the phase margin? What is the slew rate of this op amp? Assume VDD = −VSS = 2.5V and RB = 100 kΩ. Solution Given Av = 4000 V/V GB = 1 MHz and z1 = ∞ For I5 = 50 µA , let us assume I8 = 40 µA Thus, VGS8 = 1 V or, W L 8 = 2I 8 K ’ N (VGS8 − VT 8 )2 ≅ 16 2 µm µm or, W = 5 W = 20 µm L 5 4 L 8 2 µm and, W = 40 µm L 7 2 µm Also, let us assume that VSG3 = VSG4 = 1.5 V or, ( ) W = W L 3 L 4 = 2I3 K ’ P VSG 3 − VT 3 2 =3 2 µm µm The aspect ratio of M6 can be calculated as W = 2 W L W L 6 L 7 W 5 L 4 → W = 12 µm L 6 2 µm or, gm6 = 245 µS In order to eliminate the RHP zero Now, Av = 2 g m1 g m6 I5I7 (λP + λ N )2 RZ =1 g m6 ≅4 KΩ CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.3-08 - Continued or, g m1 = Av I5 I7(λP + λ N )2 2 g m6 or, gm1 = 16 µS or, W L 1 = g 2 m1 K ’ N I 5 → W = 0.00145 L 1 Let us assume a more realistic value as W = W = 2 µm L 1 L 2 2 µm This will give gm1 = 74.2 µS and Av = 9090 V/V Now, CC = g m1 GB = 74.2 pF The phase margin can be approximated as PM = 180o − tan −1 GB p1 + tan −1 GB p2 Considering the worst-case phase margin to be 60 degrees 60o = 180o − 90o + tan −1 GB p2 (min) or, p2 (min) = 1.732GB = 1.732 MHz. or, CL (max) = gm6 = 141.5 p2 (min) pF Page 6-23 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-24 Problem 6.3-09 Use the electrical model parameters of the previous problem to design W3, L3, W4, L4, W5, L5, Cc, and Rz of Fig. P6.3-8 if the dc currents are increased by a factor of two and if W1 = L1 = W2 = L2 = 2 µm to obtain a low-frequency, differential-voltage gain of 5000 and a GB of 1 MHz. All devices should be in saturation under normal operating conditions and the effect of the RHP should be canceled. How much load capacitance should this op amp be able to drive before suffering a degradation in the phase margin? What is the slew rate of this op amp? Solution Given W1 = L1 = W2 = L2 = 2 µm Referring to the solution of P6.3-8 gm1 = 104.8 µS or, CC = gm1 GB = 105 pF Also, ( ) gm6 = AvI5I7 λP + λN 2gm1 2 = 190.8 µS or, W L 6 = gm 2 6 K ' P I7 = 7.2 2 µm µm and, RZ = 1 gm 6 ≅ 5.24 KΩ Now, W L 3 = W L 4 = 0.5 W L L 6 W W 7 L 5 ≅2 2 µm µm Assuming VGS5 = 1 V ( ) W L 5 = K ' N 2I5 VGS 5 − VT 5 2 ≅ 40 2 µm µm Slew rate can be expressed as SR = I5 ≅1 V / µs CC Considering the worst-case phase margin to be 60 degrees 60o = 180o − 90o + tan −1 GB p2 (min) or, p2 (min) = 1.732GB = 1.732 MHz. or, CL (max) = gm 6 p2 (min) = 110 pF CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-25 Problem 6.3-10 For the op amp shown in Fig. +2.5V P6.3-10, assume all transistors are M9 10/1 10/1 operating in the saturation region and find (a.) the dc value of I5, I7 and I8, (b.) the low frequency differential voltage gain, Avd(0), (c.) the GB in Hz, (d.) the - 1/1 I8 M3 M1 M4 10/1 M6 vo M2 Cc=5pF positive and negative slew rates, vin 10/1 (e.) the power dissipation, and (f.) + 10/1 I7 20pF the phase margin assuming that the I5 open-loop unity gain is 1MHz. M8 M5 M7 1/1 2/1 10/1 -2.5V Solution (a.) Figure P6.3-10 2·I8 5V = KP·1 + 0.7 + 2·I8 KN·1 + 0.7 ⇒ 3.6 = I8 1 25 + 1 55 ⇒ I8 = 10.75µA ∴ I8 = 10.75µA, I5 = 2I8 = 21.5µA, and I7 = 10I8 = 107.5µA (b.) Av(0) = gm1(rds2||rds4)gm6(rds6||rds7) gm1 = 2·KN·10·I8 = 153.8µS , gm6 = 2·KP·10·I7 = 327.9µS , 25 rds2 = 10.75 = 2.33MΩ, 20 20 25 rds4 = 10.75 = 1.86MΩ, rds6 = 107.5 = 0.186MΩ , and rds7 = 107.5 = 0.233MΩ . ∴ Av(0) = (153.8µS)(1.034MΩ)(327.9µS)(0.1034MΩ) = 5395 V/V gm1 153.8µS (c.) GB = Cc = 5pF = 30.76Mradians/sec = 4.90MHz I5 21.5µA (d.) Due to Cc: |SR| = Cc = 5pF = 4.3 V/µs I7-I5 86µA Due to CL: |SR| = CL = 20pF = 4.3V/µs ∴ |SR| = 4.3V/µs (e.) Power Dissipation = 5(I8+I5+I7) = 5(139.75µA) = 0.699mW (f.) Phase margin = 180° - tan-1GBG/ABv(0) - tan-1Gp2B - tan-1GzB p2 = gm6 CL = 16.395x106 rads/sec and z = gm6 Cc = 65.6x106 rads/sec ∴ Phase margin = 90° - tan-1166..32985 - tan-166.52.86 = 6 3 . 6 ° CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-26 Problem 6.3-11 A simple CMOS op amp is shown. Use the following model parameters and find the numerical value of the small signal differential voltage gain, vout/vin, output resistance, Rout, the dominant pole, p1, the unity-gainbandwidth, GB, the slew rate, SR, and the dc power dissipation. KN’=24µA/V2, KP’ = 8µA/V2, VTN = VTP = 0.75V, λN = 0.01V-1 and λP = 0.02V-1. +5V 2/1 M8 1/1 M3 vo1 M1 10µA M4 10/1 vout 20µA + vin 4/1 M2 10µA 5pF 100µA - 4/1 M7 M6 1/1 1/1 M5 5/1 -5V Solution Small signal differential voltage gain: By intuitive analysis methods, vo1 -0.5gm1 vout -gm4 vin = gds1 + gds3 and vo1 = gds4 + gds5 → vout 0.5gm1gm4 vin = (gds1+gds3)(gds4+gds5) gm1 = 2KNW1ID1 L1 = 24·2·4·10 x10-6 = 43.82µS gds1 = λNID1 = 0.01·10µA = 0.1µS, gds3 = λPID3 = 0.02·10µA = 0.2µS gm4 = 2KPW4ID4 L4 = 2·8·10·100 x10-6 = 126.5µS gds4 = λPID4 = 0.02·100µA = 2µS, gds5 = λNID5 = 0.01·100µA = 1µS ∴ vout 0.5·43.82·126.5 vin = (0.1+0.2)(1+2) = 3,079V/V Output resistance: 1 106 R out = gds4+gds5 = 1+2 = 3 3 3 k Ω Dominant pole, p1: 1 1 106 |p1| = R1C1 where R1 = gds1+gds3 = 0.1+0.2 = 3.33MΩ and C1 = Cc(1+|Av2|) = 5pF1 + gm4 gds4+gds5 = 51+1236.5 = 215.8pF 106 ∴ |p1| = 3.33·2.15.8 = 1,391 rads/sec → |p1| = 1,391 rads/sec = 221Hz 0.5·gm1 0.5·43.82x10-6 GB = Cc = 5x10-12 = 4.382Mrads/s GB=4.382 Mrads/sec=0.697MHz ID 6 10µA SR = Cc = 5pF = 2V/µs Pdiss = 10V(140µA) = 1.4mW CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-27 Problem 6.3-12 On a log-log plot with the vertical axis having a range of 10-3 to 10+3 and the horizontal axis having a range of 1 µA to 100 µA, plot the low-frequency gain Av(0), the unity-gain bandwidth GB, the power dissipation Pdiss, the slew rate SR, the output resistance Rout, the magnitude of the dominant pole |p1|, and the magnitude of the RHP zero z, all normalized to their respective values at IB = 1 µA as a function of IB from 1 µA to 100 µA for the standard two-stage CMOS op amp. Assume the current in M5 is k1IB and the output current (M6) is k2IB. Solution VDD gmI GB = Cc ∝ IBias Pdiss = (VDD+|VSS|)(1+K1+K2)IBias ∝ Ibias SR = K1IBias Cc ∝ IBias 1 1 Rout = 2λK2IBias ∝ IBias M6 M3 M4 vout - M1 M2 vin + IBias K1IBiasK2IBias M5 M7 |p1| = 1 gmIIRIRIICc ∝ IBias2 IBias ∝ IBias1.5 gmII |z| = Cc ∝ IBias Illustration of the Ibias dependence → Plot is done for normalized bias current. VSS Fig. 6.3-04D 103 Pdiss and SR |p1| 102 101 GB and z 100 10-1 10-2 Ao and Rout 10-3 1 10 IBias IBias(ref) 100 Fig. 160-05 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-28 Problem 6.3-13 Develop the expression similar to VDD Eq. (6.3-32) for the W/L ratio of M6A in Fig. P6.3-13 that will cause the right-half M11 M10 M3 M4 plane zero to cancel the output pole. M6B M6A Repeat Ex. 6.3-2 using the circuit of - M1 M2 Fig. P6.3-13 using vin the values of the transistors in Ex. + vout Cc CL 6.3-1. + VBias - M5 M7 M8 M9 VSS Solution Figure P6.3-13 Nulling resistor implemented by a MOS diode. ( ) RZ = 1 gm 6B = 1 2K ' P W L 6B I8 Now, z1 = p2 or, ( ) −1 = −gm6A CC RZ −1 gm6A CL → or, W L 6A = W L 6A I8 I7 CC + CL 2 CC Referring to Example 6.3-1 ( ) −1 = −gm6A CC 1 gm6B −1 gm6A CL (1) W L 6A = W L 6 = 94 and, From Equation (1) I8 = I9 = I10 = I11 = 15 µA W L 6B = 31.7 ≅ 32 or, gm6B = 218 µS gm6A = 945 µS RZ = 1 gm 6B = 4.59 KΩ ( ) z1 = CC −1 RZ −1 gm6A = −15 MHz. p2 = −gm 6A CL = −15 MHz. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-29 Problem 6.3-14 Use the intuitive approach presented in Sec. 5.2 to calculate the small-signal differential voltage gain of the two-stage op amp of Fig. 6.3-1. Solution Referring to the figure, the small-signal currents in the first stage can be given by id 4 = id 3 = id1 = −gm1 vin 2 and, id 2 = gm 2 vin 2 So, ( ) iout1 = id 4 − id 2 = − gm1 + gm2 vin 2 or, ( ) iout1 = − gm1 vin The small-signal output conductance of the first stage is gout1 = gds2 + gds4 Thus, the small-signal gain of the first stage becomes ( ) Av1 = −gm1 gds2 + gds4 Considering the second gain stage, the gain can be given by ( ) Av2 = −gm 6 gds6 + gds7 Thus, the overall small-signal voltage gain becomes ( )( ) Av = Av1Av2 = gm1gm 6 gds2 + gds4 gds6 + gds7 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-30 Problem 6.3-15 A CMOS op amp capable of operating from 1.5V power supply is shown. All device lengths are 1µm and are to operate in the saturation region. Design all of the W values of every transistor of this op amp to meet the following specifications. Slew rate = ±10V/µs Vout(max) = 1.25V Vout(min) = 0.75V Vic(min) = 1V Vic(max) = 2V GB = 10MHz Phase margin = 60° when the output pole = 2GB and the RHP zero = 10GB. Keep the mirror pole ≥ 10GB (Cox = 0.5fF/µm2). Your design should meet or exceed these specifications. Ignore bulk effects in this problem and summarize your W values to the nearest micron, the value of Cc(pF), and I(µA) in the following table. Use the following model parameters: KN’=24µA/V2, KP’ = 8µA/V2, VTN = - VTP = 0.75V, λN = 0.01V-1 and λP = 0.02V-1. +1.5V M10 M11 M12 M9 1.5I 1.5I I v1 M1 M2 v2 I I M8 I M5 M3 M7 Cc vout 10pF I 10I M4 M6 Solution 1.) p2=2GB ⇒ gm6/CL=2gm1/Cc and z=10GB ⇒ gm6=10gm1. ∴ C c = CL/5 = 2pF 2.) I = Cc·SR = (2x10-11)·107 = 20µA ∴ I = 2 0 µ A 3.) GB = gm1/Cc ⇒ gm1 = 20πx106·2x10-12 = 40πx10-6 = 125.67µS W1 W2 gm12 L1 = L2 = 2KN(I/2) (125.67x10-6)2 = 2·24x10-6·10x10-6 = 32.9 ⇒ W1 = W2 = 33µm 2·10 4.) Vic(min) = VDS5(sat.)+VGS1(10µA) = 1V→VDS5(sat.) = 1- 24·33 -0.75 = 0.0908 2·I 2·20 VDS5(sat) = 0.0908 = KNS5 → W5 = 24·(0.0908)2 = 201.9µm W5 = 202µm 5.) Vic(max) = VDD-VSD11(sat)+VTN = 1.5-VSD11(sat)+0.75 = 2V→VSD11(sat) = 0.25V VSD11(sat) ≤ W11=W12≥120µm 2·1.5I KP·S11 2·30 → S11 = W11 ≥ (0.25)2·8 = 120 → CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-31 Problem 6.3-15 - Continued 6.) Choose S3(S4) by satisfying Vic(max) specification then check mirror pole. Vic(max) ≥ VGS3(20µA) + VTN → VGS3(20µA) = 1.25V ≥ 2·20 S3 = S4 = (0.5)2·24 = 6.67 ⇒ W 3 = W 4 = 7 µ m 2·I KN·S3 + 0.75V 7.) Check mirror pole (p3 = gm3/CMirror). gm3 p3 = CMirror gm3 = 2·0.667·W3·L3·Cox 2·24·6.67·20x10-6 = 2·0.667·6.67·0.5x10-15 = 17.98x109 which is much greater than 10GB (0.0628x109). Therefore, W3 and W4 are OK. 8.) gm6 = 10gm1 = 1256.7µS a.) gm6 = 2KNS610I ⇒ W6 = 164.5µm b.) Vout(min) = 0.5 ⇒ VDS6(sat) = 0.5 = Therefore, use W6 = 165µm 2·10I KNS6 ⇒ W6 = 66.67µm I4 Note: For proper mirroring, S4 = I6 S6 = 8.25µm which is close enough to 7µm. 9.) Use the Vout(max) specification to design W7. 2·200µA Vout(max) = 0.25V ≥ VDS7(sat) = 8x10-6·S7 400µA ∴ S7 ≥ 8x10-6(0.25)2 ⇒ W 7 = 800µm 10.) Now to achieve the proper currents from the current source I gives, S7 S9 = S10 = 10 = 80 → W9 = W10 = 80µm and 1.5·S7 S11 = S12 = 10 = 120 → W11 = W12 = 120µm. We saw in step 5 that W11 and W12 had to be greater than 120µm to satisfy Vic(max). ∴ W11=W12=120µm 11.) Pdiss = 15I·1.5V = 300µA·1.5V = 450µW Cc I W1=W2 W3=W4 W5=W8 W6 W7 W9=W10 W11=W12 Pdiss 2pF 20µA 33µm 7µm 202µm 165µm 800µm 80µm 120µm 450µW CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-32 Problem 6.3-16 A CMOS circuit used as an output buffer for an OTA is shown. Find the value of the small signal output resistance, Rout, and from this value estimate the -3dB bandwidth if a 50pF capacitor is attached to the output. What is the maximum and minimum output voltage if a 1kΩ resistor is attached to the output? What is the quiescent power dissipation of this circuit? Use the following model parameters: KN’=24µA/V2, KP’ = 8µA/V2, VTN = - VTP = 0.75V, λN = 0.01V-1 and λP = 0.02V-1. 20 VDD = 2.5V vin + 6 M5 M9 10/1 + 8/1 M7 - 16/1 vout M8 vin - 1 5 2 M1 M2 1/5 4/2 4/2 Cc 17 1.5V 7 vout 3 4 M10 M3 M4 1/1 5/1 5/1 20/1 30 VSS = -2.5V M6 -1.5V vout t Figure P6.3-16 Solution Considering the Miller compensation path, the value of the nulling resistor implemented by M10is given by ( ) ( ) RZ = K ' N W 1 L 10 VDD − VS10 − VT10 (1) The zero created at the output is given by ( ) z1 = CC −1 RZ −1 gm6 (2) a.) When the output swings high, the voltage at the source of M10 goes low assuming the compensation capacitor tends to get short-circuited. Thus, ( ) VDD − VS10 − VT10 increases causing a decrease in the value of RZ . Also, as the voltage at the gate of M6 goes down, the current in M6 decreases causing a decrease in value of gm6. Referring to Equation (2), a decrease in both RZ and gm6 would tend to place the zero in the right half plane and it would degrade the phase margin causing the op amp to oscillate. b.) When the output swings low, the voltage at the gate of M6 and the source of M10 goes up. This decreases (VDD − VS10 ) − VT10 causing an increase in RZ . Also, as the voltage at the gate of M6 increases, the current through M6 increases causing and increase in gm6. Thus, from Equation (2), an increase in RZ and gm6 would create a LHP zero which would make the op amp more stable. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-33 Problem 6.4-01 Sketch the asymptotic frequency response of PSRR+ and PSRR- of the two-stage op amp designed in Example 6.3-1. Solution Referring to Example 6.3-1, for the positive PSRR, the poles and zeros are p1 = (GB )g ds 6 Av (0)GII = 361 Hz. z1 = GB = 5 MHz. z2 = p2 = 15 MHz. For the negative PSRR, the poles and zeros are p1 = (GB )GI g m1 = 71.6 KHz. z1 = GB = 5 MHz. z2 = p2 = 15 MHz. The magnitude of the positive and negative PSRR is shown below. 80 PSRR- 60 Magnitude (dB) 40 20 PSRR+ 0 -20 10 100 1000 10 4 10 5 10 6 10 7 10 8 Frequency (Hz) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-34 Problem 6.4-02 Find the low frequency PSRR and all roots of the positive and negative power supply rejection ratio performance for the twostage op amp of Fig. P6.3-9. Solution +1.5V M9 10/1 10/1 1/1 M3 M4 I8 100/1 M6 vo - M1 M2 Cc=5pF vin 10/1 + 10/1 I7 20pF I5 M8 M5 M7 1/1 2/1 10/1 -1.5V Referring to the figure VDD − VSS = VT 8 + VT 9 + or, I8 = 60 µA 2I8 + K ’ N (W L)8 Figure P6.3-10 2I 8 K ’ P (W L )9 Now, gm1 = 363.3 µS , gds2 = 2.4 µS , gds4 = 3 µS , gm6 = 774.6 µS , gds6 = 30 µS and gds7 = 24 µS ∴ Av1 = 67.3 and Av2 = 14.3 For the positive PSRR, the low frequency PSRR is PSRR+ = Av (0)GII = 1737 g ds6 and poles and zeros are p1 = (GB )g ds 6 Av (0)GII = 6.66 KHz, z1 = GB = 11.6 MHz. and z2 = p2 = 6.2 MHz. For the negative PSRR, the low frequency PSRR is given by PSRR− = Av (0)GII = 2171 g ds7 and the poles and zeros are p1 = (GB )GI g m1 = 172.4 KHz, z1 = GB = 11.6 MHz and z2 = p2 = 6.2 MHz. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-35 Problem 6.4-03 Repeat the analysis of the positive PSRR of Fig. 6.4-2 if the Miller compensation circuitry of Fig. 6.2-15(a) is used. Compare the low frequency magnitude and roots with those of the positive PSRR for Fig. 6.4-2. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-36 Problem 6.4-04 In Fig. P6.4-4, find vout/vground and identify the low-frequency gain and the roots. This represents the case where a noisy ac ground can influence the noise performance of the two-stage op amp. M3 M4 M1 M2 M6 VDD Cc vout CL vground + VBias M5 - M7 VSS Figure P6.4-4 Solution Let, vdd = −vss = v ground 2 and, v5 be the small-signal ac voltage at the drain of M5. Applying nodal analysis ( ( ) ( ) ( )) gm2 vout − v5 + gm5vss + gds2 vdd − v5 − gm1v5 + gds1 v1 − v5 rds5 = v5 or, ( ( ) ) v5 = gm 2vout + gds2vdd + gm 5vss gm1 + gm2 (1) Now, ( ( ) ( ) ( )) ( ( ) ( )) gm2 vout − v5 + gds2 vdd − v5 + gm1v5 + gds3 vdd − v1 = gds1 v1 − v5 + sCC v1 − vout or, ( ) ( ) ( ) gm2 + sCC vout + gds2 + gds3 vdd = gds1 + gds3 + sCC v1 (2) Also, ( ( ) ) ( ( ) ( ) ( )) sCC v1 − vout + gm7vss = gds6 vout − vdd + gds7 vout − vss + sCLvout + gm6 v1 − vdd Using vdd = −vss, we get ( ) ( ( )) ( ) gm6 − gm7 + gds6 − gds7 vdd = gds6 + gds7 + s CC + CL vout + gm6 − sCC v1(3) Using Equations (2) and (3) gives the low frequency PSRR as ( ) vout v ground = GI 2gmI gmII gds6 − gds7 − gm7 −1 The zero is ( ( ) ) z1 ≅ − CC GI gds6 − gds7 − gm7 GI + gm6 − gm7 + gds6 − gds7 The two poles are same as given by the zeros of Equation (6.4-14) in the text. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.4-05 Repeat the analysis of Fig. 6.4-2 and Fig. 6.4-4 for the + VDD p-channel input, two-stage VBias op amp shown in Fig. P6.4- - M5 5. Solution TBD M1 M2 Cc M3 M4 VSS Figure P6.4-5 Page 6-37 M7 vout CL M6 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-38 Problem 6.5-01 Assume that in Fig. 6.5-1(a) that the currents in M1 and M2 are 50µA and the W/L values of the NMOS transistors are 10 and of the PMOS transistors are 5. What is the value of VBias that will cause the drain-source voltage of M1 and M2 to be equal to Vds(sat)? Design the value of R. to keep the source-drain voltage of M3 and M4 equal to Vsd(sat). Find an expression for the small-signal voltage gain of vo1/vin for Fig. 6.5-1(a). Solution VBIAS = VT , MC1 + Vdsat, MC1 + Vdsat ,M1 or, VBIAS = VT , MC1 + Ignoring bulk effects 2I1 + K ’ N W L C1 2 I1 K ’ N W L 1 VBIAS = 1.3V Now, VG,C3 = VT ,C3 + Vdsat ,C3 + Vdsat3 VG3 = VT 3 + Vdsat3 And, IR = VG,C3 − VG3 = Vdsat,C3 or, R= 2 IKP' W L C3 = 12.65kΩ The output impedance is given by [ ] [ ] Rout = gm,C 4rds,C 4rds4 || gm,C 2rds,C 2rds2 Rout = 19.38 MΩ The small-signal voltage gain is given by Av = -gm,C2Rout = -6248 V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-39 Problem 6.5-02 If the W/L values of M1, M2, MC1 and MC2 in Fig. 6.5-1(b) are 10 and the currents in M1 and M2 are 50µA, find the W/L values of MB1 through MB5 that will cause the drainsource voltage of M1 and M2 to be equal to Vds(sat). Assume that MB3 = MB4 and the current through MB5 is 5µA. What will be the current flowing through M5? Solution Let, IB5 = 5 µA VT , B5 + Vdsat, B5 = VT ,C1 + Vdsat ,C1 + Vdsat1 or, VT , B5 + 2 I B5 K ’ N (W L )B5 = VT ,C1 + 2I1 + K ’ N (W L)C1 2 I1 K ’ N (W L)1 Ignoring bulk effects, and assuming I1 = 50 µA W = 1 L B5 4 The aspect ratios of the transistors MB1 through MB4 can be chosen (assumed) to be 1. The total current through M5 is 110 µA . Problem 6.5-03 In Fig. 6.5-1(a), find the small-signal impedance to ac ground looking into the sources of MC2 and MC4 assuming there is no capacitance attached to the output. Assume the capacitance to ground at these nodes is 0.2pF. What is the value of the poles at the sources of MC3 and MC4? Repeat if a capacitor of 10pF is attached to the output. Solution Let, C1 and CL be the capacitances at the source of MC2 (and MC4) and the output respectively. The impedance looking between the drain of M4 and Vdd (ac ground), Z4 , be Z4 = 1 (gds4 + sC1 ) The impedance looking between the drain of MC4 and Vdd (ac ground), ZC 4 , be ZC 4 = (g ds 4 1 + sC1)gds,C 4 gm,C 4 + sC L Thus, the impedance looking between the source of MC2 and Vdd (ac ground), Z S,C 2 , can be expressed as ZS ,C 2 = 1 rds,C 2 + Z C4 + gm,C2rds,C 2 || 1 sC1 or, ZS ,C 2 ≅ ZC 4 gm,C2rds,C 2 || 1 sC1 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-40 Problem 6.5-03 - Continued or, ZS ,C 2 = 1 g m, C2 (g ds 4 + sC1 )g ds,C 4 gm,C 4gds ,C2 +s gm,C2 gds ,C2 CL + sC1 or, ZS ,C 2 = gm, C2 gds4 gds,C4 gm,C 4gds,C 2 + 1 s gm,C 2 gds,C 2 CL + 1+ gm,C 2gds ,C4 gm,C 4gds ,C2 C1 Similarly, the impedance looking from the source of MC4 to ac ground, ZS,C 4 , can be expressed as ZS ,C 4 = gm, C4 gds2 gds,C2 gm,C 2gds,C 4 + 1 s gm,C 4 gds,C 4 CL + 1+ gm,C 4gds ,C2 gm,C 2gds ,C4 C1 Referring to problem 6.5-3, we have gm,C 4 = gm4 = 158.1 µS gm,C 2 = gm2 = 331.7 µS gds,C 4 = gds4 = 2.5 µS gds,C 2 = gds2 = 2 µS When CL = 0 ( ) ZS,C2 = 6.6 ×10 −6 1 + s 0.72 ×10−12 Ω ( ) ZS,C4 = 0.76 ×10 − 6 1 +s 0.27 ×10 −12 Ω When CL = 10 pF ( ) ZS,C2 = 6.6 ×10 −6 1 + s 1659 ×10−12 Ω ( ) ZS,C4 = 0.76 ×10 − 6 + 1 s 632.7 ×10 −12 Ω CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-41 Problem 6.5-04 Repeat Example 6.5-1 to find new values of W1 and W2 which will give a voltage gain of 10,000. Solution From Example 6.5-1 Rout = 25 MΩ Thus, for Av = 10,000 g m1 = Av Rout = 400 µS or, W = W = g 2 m1 = 14.5 L 1 L 2 2K ’ N I1 1 Problem 6.5-05 Find the differential-voltage gain of Fig. 6.5-1(a) where the output is taken at the drains of MC2 and MC4, W1/L1 = W2/L2 = 10 µm/1 µm, WC1/LC1 = WC2/LC2 = WC3/LC3 = WC4/LC4 = 1 µm/1 µm, W3/L3 = W4/L4 = 1 µm/1 µm, and I5 = 100 µA. Use the model parameters of Table 3.1-2 . Ignore the bulk effects. Solution I5 = 100 µA gm1 = gm2 = 331.67 µS gm,C 2 = 104.8 µS gm,C 4 = 70.7 µS rds ,C4 = rds4 = 400 KΩ rds ,C2 = rds2 = 500 KΩ The output impedance is given by [ ] [ ] Rout = gm,C 2rds,C 2rds2 || gm,C 4rds,C 4rds4 or, Rout = [26.2M ]|| [11.3M ]= 7.9MΩ So, A v = −gm2Rout = −2620V /V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-42 Problem 6.5-06 A CMOS op amp that uses a 5V power supply is shown. All transistor lengths are 1µm and operate in the saturation region. Design all of the W values of every transistor of this op amp to meet the following specifications. Use the following model parameters: KN’=110µA/V2, KP’=50µA/V2, VTN=0.7V, VTP=-0.7V, λN=0.04V-1 and λP=0.05V-1. Slew rate = ±10V/µs Vic(min) = 1.5V Vout(max) = 4V Vic(max) = 4V Vout(min) = 1V GB = 10MHz Your design should meet or exceed these specifications. Ignore bulk effects and summarize your W values to the nearest micron, the bias current, I5(µA), the power dissipation, the differential voltage gain, Avd, and VBP and VBN in the following table. Assume that Vbias is whatever value necessary to give I5. W1=W2 W3=W4=W6 W9=W10 W5 I5(µA) =W7=W8 =W11 Avd VBP VBN Pdiss 89.75 40 18.2 13.75 250µA 17,338V/V 3.3V 1.7V 2.5mW VDD = 5V M8 M3 M4 M6 v2 I9 M9 M1 M2 VBias I5 M5 VBP M7 v1 I10 VBN M11 vout 25pF M10 S01FEP2 Solution Since W3 =W4 =W6 =W7 =W8 and W9 =W10 =W11, then I5 is the current available to charge the 25pF load capacitor. Therefore, dvOUT I5 = C dt = 25pF(10V/µs) = 250µA Note that normally, I10 = I9 = 125µA. However, for the following calculations we will use I6 or I10 equal to 250µA for the following vOUT(max/min) calculations. vOUT(max) = 4V ⇒ 0.5 = W 6 = W 7 = 40 = W 3 = W 4 = W 8 2I5 KP'(W6/L6) = 2I5 KP'(W6/L6) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-43 Problem 6.5-07 Verify Eqs. (6.5-4) through (6.5-8) of Sec. 6.5 for the two-stage op amp of Fig. 6.5-3 having a cascode second stage. If the second stage bias current is 50 µA and W6/L6 =WC6/LC6 = WC7/LC7 = W7/L7 = 1 µm/1 µm, what is the output resistance of this amplifier using the parameters of Table 3.1-2? Solution From intuitive analysis, it can be shown that ( ) Av1 = − gm1 gds2 + gds4 For the second gain stage, the output resistance of the cascode stage can be given by [ ] [ ] RII = gm,C r6 ds,C 6rds6 || gm,C 7rds,C 7rds7 or, Av2 = −gm6RII ( ){[ ] [ ]} Thus, Av = Av1Av2 = gds2 + gds4 gm1gm 6 gm,C 6rds,C 6rds6 || gm,C r7 ds,C 7rds7 For, I7 = 50 µA RII = [11.3M] || [26.2M] = 7.9MΩ CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-44 Problem 6.5-08 Verify Eqs. (6.5-9) through (6.5-11) of Sec. 6.5 assuming that M3 = M4 = M6 = M8 and M9 = M10 = M11 = M12 and give an expression for the overall differential-voltage gain of Fig. 6.5-4. Solution Solving the circuit intuitively The effective transconductance of the first stage gmI = gm1 2 The effective conductance of the first stage gI = gm3 The effective transconductance of the second stage ( ) gmII = gm6 + gm11 The effective conductance of the second stage Now, or, gII = gds6gds7 gm 7 + gds11gds12 gm12 Av1 = − gm1 2gm 3 ( ) Av2 = − gm6 + gds6gds7 gm7 + gm11 gds11gds12 gm12 ( ) Av = gm1 gm 6 + gm11 2gm 3 gds6gds7 gm 7 + gds11gds12 gm12 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-45 Problem 6.5-09 An internallycompensated, cascode VDD = 5V op amp is shown in M10 Fig. P6.5.-9. (a) Derive an expression for the common-mode M5 M6 input range. (b) Find W1/L1, W2/L2, W3/L3, and W4/L4 when IBIAS is 80 µA and the input 60/10 M11 M3 IBias M4 Cc CMR is −3.5 V to 3.5 - M1 M2 V. Use K'N = 25 vin µA/V2, K'p = 11 µA/V2 and |VT| = 0.8 to 1.0 V. + 60/10 M12 I7 M7 30/10 Solution VSS = -5V The minimum input Figure P6.5-9 common-mode voltage can be given by Vin (min) = VSS + VT1(max) − Vdsat1 − Vdsat 7 M8 vout CL M9 ( ) ( ) Vin (min) = VSS + VT1(max) − K ' N I7 W L 1 − 2I7 KN' W L 7 (1) The maximum input common-mode voltage can be given by Vin (max) = VDD + VT1(min) − VT 5(max) − Vdsat3 − Vdsat5 ( ) ( ) Vin (max) = VDD + VT1(min) − VT 5(max) − KP' I7 W L 3 − I7 KP' W L 5 (2) The input common-mode range is given by ICMR = Vin (max) − Vin (min) which can be derived from Equations (1) and (2). Given I7 = 40 µA, Vin (min) = −2.5 V and (W L) = 3, from Equation (1) 7 W L 1 = W L 2 = 64 10 µm µm Also, for I7 = 40 µA, Vin (max) = 3.5 V and assuming (W L) = 6, from Equation (2) 5 W L 3 = W L 4 = 135 10 µm µm CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-46 Problem 6.5-10 Develop an expression for the small-signal differentialvoltage gain and output resistance of the cascode op amp of Fig. P6.5-9. 60/10 M10 M11 VDD = 5V M5 M6 M3 IBias M4 Cc Solution - The output resistance of the vin first gain stage is + Rout1 ≅ rds 6 So, 60/10 M12 M1 M2 I7 M7 30/10 Av1 = − gm1Rout1 = − gm1rds6 VSS = -5V Figure P6.5-9 The output resistance of the second gain stage is Rout 2 = (g ds8 1 + gds9 ) So, Av2 = − gm8Rout 2 = − (g g ds8 m8 +g ds 9 ) The overall small-signal gain is Av = Av1Av2 or, Av = g m1 g m8 gds6(gds8 + gds9 ) or, Av = 8K ’ N K ’ P (W L)1 (W L )8 I7I9 (λ P + λN )2 λP2 The small-signal output resistance is given by Rout = Rout 2 = (g ds8 1 + gds9 ) M8 vout CL M9 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-47 Problem 6.5-11 Verify the upper input common mode range of Ex. 6.5-2, step 6.) for the actual value of S3 = S4 of 40. Solution The maximum input common-mode voltage is given by Vin (max) = VDD + VT1(min) − VT 3(max) − Vdsat3 or, Vin (max) = VDD + VT1(min) − VT 3(max) − 2I3 K ’ P (W L)3 or, Vin (max) = 1.98V Problem 6.5-12 Repeat Example 6.5-2 if the differential input pair are PMOS transistors (i.e. all NMOS transistors become PMOS and all PMOS transistors become NMOS and the power supplies are reversed). VDD VBIAS M5 M13 M10 M6 M1 M2 M4 M3 M9 R1 M8 R2 M14 M15 M7 Vout CL M12 M11 VSS Solution To satisfy the slew rate I6 = I7 = I12 = I11 = 250 µA and let I5 = 100 µA The maximum output voltage is 1.5 V Vdsat6 = Vdsat7 = 0.5 V → S6 = S7 = S9 = S10 = 40 Similarly, considering the minimum output voltage as –1.5 V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-48 Problem 6.5-12 - Continued Vdsat11 = Vdsat12 = 0.5 V → S11 = S12 = S14 = S15 = 18.2 The value of R1 and R2 can be calculated as R1 = Vdsat7 I8 =2 KΩ and, R2 = Vdsat12 I15 =2 KΩ Now, g m1 = kRII 2g m 3 Av (gm6 + gm8 ) and, k = S6 S4 = 2.5 and RII ≅ 11 MΩ Thus, gm1 = 107.9 µS Also, g m1 = k 2g m (g m6 3GB + gm8 ) = 149 µS So, let us choose gm1 = 149 µS . → S1 = S2 = 4.4 But for this value of S1 = S2 = 4.4 , from the expression of maximum input common- mode voltage, we will get Vdsat5 = 0.025 V which is too small. So let us choose S1 = S2 = 20 This, from the expression of Vin (max) , will give S5 = 27.7 Or, S13 = 1.25S5 = 34.6 and, S8 = 2.5S3 = 40 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-49 Problem 6.5-13 A CMOS op amp that uses a 5V power supply is shown. All VDD = 5V transistor lengths are 1µm and operate in the saturation region. Design all of the W values of M8 M3 M4 every transistor of this op amp to meet the following specifications: Slew rate = ±10V/µs, Vout(max) = 4V, Vout(min) = 1V, Vic(min) = 1.5V, Vic(max) = 4V and GB = 10MHz. Your design should v2 M1 M2 I9 VBias I5 M5 VBP v1 I10 VBN meet or exceed these specifications. Ignore bulk M9 effects and summarize your W values to the nearest micron, the bias current, I5(µA), the power dissipation, the differential Figure P6.5-13 voltage gain, Avd, and VBP and VBN in the table shown. Solution M6 M7 vout M11 25pF M10 1.) I5 = CL·SR = 250µA 2.) gm1 = GB·CL·= 20πx106·25pF = 1,570.8µS ⇒ W1 (1.570x10-3)2 L1 = 2·110·125x10-6 = 90 2ID 2·250 3.) W3=W4=W6=W7=W8 = K’(VDS(sat))2 = 50·0.25 = 40 (assumed ID of 250µA worst case) 2ID 2·250 4.) W9=W10=W11 = K’(VDS(sat))2 = 110·0.25 = 18 (assumed ID of 250µA worst case) 5.) Vicm(min) = VDS5(sat) + VGS1 → VDS5(sat) = 1.5 - (0.159+0.7) = 0.6411V ∴ W5 = 2ID K’(VDS(sat))2 = 2·250 110·0.64112 = 11 6.) Avd = gm1Rout gmN = 704µS, rdsN = 0.2MΩ, gmP = 707µS, rdsN = 0.16MΩ Rout ≈ gmN· rdsN2|| gmP· rdsP2 = 28.14MΩ||18.1ΜΩ = 11ΜΩ ∴ Avd = 1.57mS·11MΩ = 17,329V/V 7.) VBP = 5-VDSP(sat) + VGSP(sat) = 5-0.5+0.5+0.7 = 3.3V VBN = VDSP(sat) + VGSP(sat) = 0.5+0.5+0.7 = 1.7V 8.) Pdiss = 5(250µA + 250µA) = 2.5mW W1=W2 W3=W4=W6 =W7=W8 90 40 W9=W10 W5 I5(µA) Avd =W11 VBP VBN Pdiss 18 11 250µA 17,324V/V 3.3V 1.7V 2.5mW CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-50 Problem 6.5-14 Repeat Example 6.5-3 if the differential input pair are PMOS transistors (i.e. all NMOS transistors become PMOS and all PMOS transistors become NMOS and the power supplies are reversed). VDD VBIAS M3 M12 M10 M11 M1 M2 R1 M13 M14 M8 R2 M6 M4 M9 Vout CL M7 M5 VSS Solution I3 = 100 µA and, I4 = I5 = 125 µA Given, Vout (max) = 2 V → Vdsat9 = Vdsat11 = 0.25 V Considering worst-case peak sourcing current of 125 µA S8 = S9 = S10 = S11 = 80 Given, Vout (min) = −2 V → Vdsat7 = Vdsat5 = 0.25 V Considering worst-case peak sinking current of 125 µA I5 = 125 µA and I7 = 25 µA S6 = S7 = S13 = 7.3 And, S4 = S5 = S14 = 36.4 R1 = Vdsat7 I14 =2 KΩ and R2 = Vdsat9 I10 =2 KΩ From gain-bandwidth S1 = S2 = (GB )2 C 2 L K ’ P I3 = 79 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-51 Problem 6.5-14 - Continued Considering Vin (max) = 1 V Vdsat3 = 0.43 V → S3 = 21.6 The minimum input common-mode voltage is Vin (min) = VSS − VT1(min) + Vdsat4 = −2.8 V Finally, S12 = 1.25S3 = 27 The small-signal gain is Av = ((22++2kk))gmI RII k = R9(gds2 + gds4) (g m7rds7 ) where, R9 = 55 MΩ gmI = 628.3 µS , gm7 = 347 µS , gds7 = 3 µS , gds4 = 5 µS , gds2 = 2.5 µS So, k = 3.96 RII = 12 MΩ or, Av = 4364 V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-52 Problem 6.5-15 This problem deals with the op amp shown in Fig. P6.5-15. All M14 device lengths are +3V M3 M4 1.5I 1.5I 1µm, the slew rate M15 is ±10V/µs, the GB M6 M7 is 10MHz, the maximum output I voltage is +2V, the minimum output voltage is -2V, and v1 I v2 0.5I M1 0.5I M2 I I M8 M9 the input common I mode range is from M13 -1V to +2V. M12 I M5 M10 M11 Design all W values of all transistors in this op amp. Your design must meet or -3V Figure P6.5-15 exceed the specifications. When calculating the maximum or minimum output voltages, divide the voltage drop across series transistors equally. Ignore bulk effects in this problem. When you have completed your design, find the value of the small signal differential voltage gain, Avd = vout/vid, where vid = v1-v2 and the small signal output resistance, Rout. Solution vout 10pF 1.) The slew rate will specify I. ∴ I = C·SR = 10-11·107 = 10-4 = 100µA. 2.) Use GB to define W1 and W2. gm1 GB = C → gm1 = GB·C = 2πx107·10-11 = 628µS ∴ W1 = gm12 2KN(0.5I) (628)2 = 2·110·50 = 35.85 ⇒ W 1 = W 2 = 36µm 3.) Design W15 to give VT+2VON bias for M6 and M7. VON = 0.5V will meet the desired maximum output voltage specification. Therefore, VSG15 = VON15 + |VT| = 2(0.5V) + |VT| 2I 2·100 ∴ W15 = KPVON152 = 50·12 = 4µm 2I → VON15 = 1V = KPW15 ⇒ W 15 = 4µm 4.) Design W3, W4, W6 and W7 to have a saturation voltage of 0.5V with 1.5I current. 2(1.5I) 2·150 W3 =W4 =W6 =W7 = KPVON2 = 50·0.52 = 24µm ⇒ W3 =W4 =W6 =W7 = 24µm CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-53 Problem 6.5-15 – Continued 5.) Next design W8, W9, W10 and W11 to meet the minimum output voltage specification. Note that we have not taken advantage of smallest minimum output voltage because a normal cascode current mirror is used which has a minimum voltage across it of VT + 2VON. Therefore, setting VT + 2VON = 1V gives VON = 0.15V. Using worst case current, we choose 1.5I. Therefore, 2(1.5I) 2·150 W8 =W9 =W10 =W11 = KNVON2 = 110·0.152 = 121µm ⇒ W8 =W9 =W10 =W11 = 121µm 6.) Check the maximum ICM voltage. Vic(max) = VDD + VSD3(sat) + VTN = 3V – 0.5 + 0.7 = 3.2V which exceeds spec. 7.) Use the minimum ICM voltage to design W5. 2·50 Vic(min) = VSS + VDS5(sat) + VGS1 = -3 + VDS5(sat) + 110·36+0.7 = -1V 2I ∴ VDS5(sat) = 1.141 → W5 = KN VDS5(sat)2 = 1.39µm = 1.4µm Also, let W12 =W13 =W5 ⇒ W12 =W13 =W5 = 1.4µm 8.) W14 is designed as I14 I W14 = W3 I3 = 24µm 1.5I = 16µm ⇒ W 14 = 16µm Now, calculate the op amp small-signal performance. Rout ≈ rds11gm9rds9||gm7rds7(rds2||rds4) 25V gm9 = 2KN·I·W9 = 1632µS, rds9 = rds11 = 100µA = 0.25MΩ, 20V 25V gm7 = 2KP·I·W7 = 490µS, rds7 = 100µA = 0.2MΩ, rd2 = 50µA = 0.5MΩ 20V rds4 = 150µA = 0.1333MΩ ∴ Rout ≈ 102ΜΩ||10.31ΜΩ = 9.3682ΜΩ Avd = 2+k 2+2k gm1Rout, 102MΩ k = (rds2||rds4)gm7rds7 = 9.888, gm1 = KN·I·W1 = 629µS ∴ Avd = (0.5459)(629µS)(9.3682MΩ) = 3,217V/V ⇒ Avd = 3,217V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-54 Problem 6.5-16 The small signal resistances looking into the sources of M6 and M7 of Fig. P6.5-15 will be different based on what we learned for the cascode amplifier of Chapter 5. Assume that the capacitance from each of these nodes (sources of M6 and M7) are identical and determine the influence of these poles on the small-signal differential frequency response. Solution The resistance looking from the output to Vss is RD9 ≅ gm9rds9rds11 The resistance looking at the source of M7 is RB = (rds7 + RD9 ) (1 + gm7rds7 ) or, RB ≅ (g m 9 rds9 rds11 ) (gm7rds7 ) (1) The resistance looking from the drain of M8 to Vss is RD8 = 1 g m8 + 1 g m10 The resistance looking at the source of M6 is RA = (rds6 + RD8 ) (1 + gm6rds6 ) → RB ≅ 1 g m6 (2) The poles at the sources of M6 and M7 are pA =− 1 RAC ≅ − gm6 C and pB =− 1 RBC ≅ − 1 rdsC Both of these poles will appear as output poles in the overall voltage transfer function. Problem 6.6-01 How large could the offset voltage in Fig. 6.6-1 be before this method of measuring the open-loop response would be useless if the open-loop gain is 5000 V/V and the power supplies are ±2.5V? Solution Given, VDD − VSS = 5 V, and Av = 5000 V/V Therefore, the offset voltage should be less than Vos < (VDD −VSS Av ) or, Vos < 1 mV CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-55 Problem 6.6-02 Develop the closed-loop frequency response for op amp circuit shown which is used to measure the open-loop frequency reasponse. Sketch the closed-loop frequency response of the magnitude of Vout/Vin if the low frequency gain is 4000 V/V, the GB = 1MHz, R = 10MΩ, and C = 10µF. (Ignore RL and CL) VDD vIN vOUT CR CL RL VSS Solution The open-loop transfer function of the op amp is, S01E2P2 GB 2πx106 Av(s) = s +(GB/Av(0)) = s +500π The closed-loop transfer function of the op amp can be expressed as, vOUT = Av(s)R+-1(1/s/CsC)v O U T +vIN = Av(s)s+-(11/R/RCC)vOUT +vIN ∴ vOUT -[s +(1/RC)]Av(s) vI N = s +(1/RC)+Av(s)/RC Substituting, Av(s) gives, -[s +(1/RC)] = s +(1/RC) Av(s) +1/RC -(s+0.01) = s +0.01 Av(s) +0.01 vOUT -2πx106s -2πx104 -2πx106s -2πx104 -2πx106(s +0.01) vI N = (s+0.01)(s+500π)+2πx104 = s2+500πs +2πx104 = (s+41.07)(s+1529.72) The magnitude of the closed-loop frequency response is plotted below. 80 60 |Av(jω)| Magnitude, dB 40 Vout(jω) 20 Vin(jω) 0 -20 0.001 0.1 10 1000 105 107 Radian Frequency (radians/sec) S01E2S2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-56 Problem 6.6-03 Show how to modify Fig. 6.6-6 in order to measure the open-loop frequency response of the op amp under test and describe the procedure to be followed. Solution From the figure, let us change the vSET associated with the top op amp. Change in this voltage would cause a change in vI at the input of the DUT. Let, for vSET1 vI1 = vout1 AV And, for vSET 2 vI 2 = vout2 AV or, AV = (vout1 (vI1 − − vout 2 vI2 ) ) = 1000 (vout1 (vos1 − − vout 2 ) vos2 ) = 1000 ∆vout ∆vos Thus, by measuring the values of ∆vout and ∆vos while changing vSET can help in finding the value of the open-loop gain. Problem 6.6-04 A circuit is shown which is used to measure the CMRR and PSRR of an op amp. Prove that the CMRR can be vos given as + - 100kΩ 100kΩ vicm 1000 vicm CMRR = vos 10kΩ Solution vOUT The definition of the common-mode + rejection ratio is vout CMRR = AAcvmd = vid vout 10Ω vi - CL RL vicm However, in the above circuit the value of vout is the same so that we get vicm CMRR = vid But vid = vi and vos ≈ 1000vi = 1000vid ⇒ vos vid = 1000 VDD vicm VSS S99FEP7 Substituting in the previous expression gives, vicm 1000 vicm CMRR = vos = vos 1000 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-57 Problem 6.6-05 Sketch a circuit configuration suitable for simulating the following op amp characteristics: (a) slew rate, (b) transient response, (c) input CMR, (d) output voltage swing. Repeat for the measurement of the above op amp characteristics. What changes are made and why? Solution VDD Vin Vout VSS CL RL Slew rate, Transient response, and ICMR measurements VDD Vin Vout VSS CL RL Output voltage swing measurement The measurement of ICMR, Slew rate, and large-signal transient response can be measured using the buffer configuration as shown in the figure. The input applied is a railto-rail step signal, which can be used to measure the maximum and minimum input swing, the slew rate, rise and settling time. The same configuration can be used to measure the performance in simulation. This buffer configuration can also be used to measure the smallsignal transient performance. The applied input should be a small signal applied over the nominal input common-mode bias voltage, and it can be used to measure the overshoot. The maximum and minimum output voltage swing can be measured using the open-loop configuration of the op amp as shown in the figure. The input applied is a rail-to-rail step signal, which will overdrive the output to its maximum and minimum swing voltage levels. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-58 Problem 6.6-06 Using two identical op amps, show how to use SPICE in order to obtain a voltage which is proportional to CMRR rather than the inverse relationship given in Sec. 6.6. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-07 Repeat the above problem for PSRR. Solution TBD Page 6-59 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-60 Problem 6.6-08 Use SPICE to simulate the op amp of Example 6.5-2. The differential-frequency response, power dissipation, phase margin, common-mode input range, output-voltage range, slew rate, and settling time are to be simulated with a load capacitance of 20 pF. Use the model parameters of Table 3.1-2. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-61 Problem 6.6-09 Use SPICE to simulate the op amp of Example 6.5-3. The differential frequency response, power dissipation, phase margin, input common-mode range, output-voltage range, slew rate, and settling time are to be simulated with a load capacitance of 20pF. Use the model parameters of Table 3.1-2. Solution VDD 3 M14M4 M5 9 10 8 1 - M1 vin + + VBias7 - M2 6 M3 11 2 M15 M6 13 M7 5 R1 vout 12 R2 14 CL M8 M9 15 16 M10 M11 VSS 4 Figure 6.5-7 (b) The following is the SPICE source file for figure 6.5-7. * Problem 6.6-9 SPICE simulation * *Voltage gain and phase margin *VDD 3 0 DC 2.5 *VSS 0 4 DC 2.5 *VIN 30 0 DC 0 AC 1.0 *EIN+ 1 0 30 0 1 *EIN- 2 0 30 0 -1 *Output voltage swing *VDD 3 0 DC 2.5 *VSS 0 4 DC 2.5 *VIN+ 40 0 DC 0 AC 1.0 *VIN- 2 0 0 *Reg1 40 1 10K *Reg2 5 1 100K CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-62 Problem 6.6-09 - Continued *ICMR *VDD 3 0 DC 2.5 *VSS 0 4 DC 2.5 *VIN+ 1 0 DC 0 AC 1.0 *PSRR+ *VDD 3 0 DC 2.5 AC 1.0 *VSS 0 4 DC 2.5 *PSRRVDD 3 0 DC 2.5 VSS 0 4 DC 2.5 AC 1.0 VIN+ 1 0 DC 0 *Slew Rate *VDD 3 0 DC 2.5 *VSS 0 4 DC 2.5 *VIN+ 1 0 PWL(0 -1 10N -1 20N 1 2U 1 2.0001U -1 4U -1 4.0001U 1 6U 1 6.0001u + -1 8U -1 8.0001U 1 10U 1) *General *X1 1 2 3 4 5 OPAMP *Unity gain configuration X1 1 5 3 4 5 OPAMP .SUBCKT OPAMP 1 2 3 4 5 M1 8 1 6 4 NPN W=35.9u L=1u M2 9 2 6 4 NPN W=35.9u L=1u M3 6 7 4 4 NPN W=20u L=1u M4 8 11 3 3 PNP W=80u L=1u M5 9 11 3 3 PNP W=80u L=1u M6 13 12 8 8 PNP W=80u L=1u M7 5 12 9 9 PNP W=80u L=1u M8 14 13 15 4 NPN W=36.36u L=1u M9 5 13 16 4 NPN W=36.36u L=1u M10 15 14 4 4 NPN W=36.36u L=1u M11 16 14 4 4 NPN W=36.36u L=1u M12 12 7 4 4 NPN W=25u L=1u M13 11 12 10 10 PNP W=80u L=1u M14 10 11 3 3 PNP W=80u L=1u R1 11 12 2K R2 13 14 2K VBIAS 0 7 1.29 .MODEL NPN NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 .MODEL PNP PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 .ENDS *Load cap CL 5 0 20PF .OP .OPTION GMIN=1e-6 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-09 - Continued .DC VIN+ -2.5 2.5 0.1 .PRINT DC V(5) .TRAN 0.05u 10u .PRINT TRAN V(5) V(1) .AC DEC 10 1 100MEG .PRINT AC VDB(5) VP(5) .PROBE .END The simulation results are shown. Page 6-63 Result 1. Voltage gain and phase margin Result 2. Output voltage swing range CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-09 - Continued Page 6-64 Result 3. Input common-mode range Result 4. Positive power supply rejection ratio CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-09 - Continued Page 6-65 Result 5. Negative power supply rejection ratio Result 6. Slew rate CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-09 - Continued Page 6-66 Result 7. Settling time From the output file of the SPICE simulation, total power dissipation is 6mW. The following is a part of the output file. NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) -1.0000 ( 3) 2.5000 ( 4) -2.5000 ( 5) -1.0004 ( X1.6) -2.0477 ( X1.7) -1.2900 ( X1.8) 1.5876 ( X1.9) 1.5874 (X1.10) 1.7094 (X1.11) 1.3594 (X1.12) .5508 (X1.13) -.9291 (X1.14) -1.4451 (X1.15) -2.0731 (X1.16) -2.0706 VOLTAGE SOURCE CURRENTS NAME CURRENT VDD -1.218E-03 VSS -1.218E-03 VIN+ 0.000E+00 X1.VBIAS 0.000E+00 TOTAL POWER DISSIPATION 6.09E-03 WATTS CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-67 Problem 6.6-10 A possible scheme for simulating the CMRR of an op amp is shown. Find the value of Vout/Vin and show that it is approximately equal to 1/CMRR. What problems might result in the actual implementation of this V2 + vout circuit to measure CMRR? V1 Solution The model for this circuit is shown. We can S02E2P4 write that V2 VDD VSS Vcm Vout Vout = Avd(V1-V2) + AcmVcm = -AvdVout + AcmVcm Thus, Avd(V1-V2) V1 Vout(1+Avd) = AcmVcm or Vout Acm Vcm = 1+Avd ≈ Acm Avd 1 = CMRR AcmVcm S02E2S4A The potential problem with this method is that PSRR+ is not equal to PSRR-. This can be seen by moving the Vcm through the power supplies so it appears as power supply ripple as shown below. This method depends on the fact that the positive and negative power supply ripple will cancel each other. Vcm V2 + V1 vout Vcm S02E2S4B VDD VSS CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-68 Problem 6.6-11 Explain why the positive overshoot of the simulated positive step response of the op amp shown in Fig. 6.6-20(b) is smaller than the negative overshoot for the negative step response. Use the op amp values given in Ex. 6.3-1 and the information given in Tables 6.6-1 and 6.6-3. Solution Consider the following circuit and waveform: VDD = 2.5V 94/1 0.1V M6 i6 iCc iCL vout t Cc 95µA CL VBias -0.1V M7 0.1µs 0.1µs VSS = -2.5V Fig. 6.6-22 During the rise time, iCL = CL(dvout/dt )= 10pF(0.2V/0.1µs) = 20µA and iCc = 3pf(2V/µs) = 6µA ∴ i6 = 95µA + 20µA + 6µA = 121µA ⇒ gm6 = 1066µS (nominal was 942.5µS) During the fall time, iCL = CL(-dvout/dt )= 10pF(-0.2V/0.1µs) = -20µA and iCc = -3pf(2V/µs) = -6µA ∴ i6 = 95µA - 20µA - 6µA = 69µA ⇒ gm6 = 805µS The dominant pole is p1 ≈ (RIgm6RIICc)-1 where RI = 0.694MΩ, RII = 122.5kΩ and Cc = 3pF. ∴ p1(95µA) = 4,160 rads/sec, p1(121µA) = 3,678 rads/sec, and p1(69µA) = 4,870 rads/sec. Thus, the phase margin is less during the fall time than the rise time. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-69 Problem 6.7-01 Develop a macromodel for the op amp of Fig. 6.1-2 which models the low frequency gain Av(0), the unity-gain bandwidth GB, the output resistance Rout, and the output-voltage swing limits VOH and VOL. Your macromodel should be compatible with SPICE and should contain only resistors, capacitors, controlled sources, independent sources, and diodes. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-70 Problem 6.7-02 Develop a macromodel for the op amp of Fig. 6.1-2 that models the low-frequency gain Av(0), the unity-gain bandwidth GB, the output resistance Rout, and the slew rate SR. Your macromodel should be compatible with SPICE and should contain only resistors, capacitors, controlled sources, independent sources, and diodes. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-71 Problem 6.7-03 Develop a macromodel for the op amp shown in Fig. P6.7-3 that has the following properties: Avd(0)zs1 - 1 a.) Avd(s) = s p1 + 1ps2 + 1 + 1- 2 iO 3 vO Figure P6.7-3 where Avd(0) = 104,z1 = 106 rads/sec., p1 = 102 rads/sec, and p2 = 107 rads/sec. b.) Rid = 1MΩ. c.) Ro = 100Ω. d.) CMRR(0) = 80dB. Show a schematic diagram of your macromodel and identify the elements that define the model parameters Avd(0), z1, p1, p2, Rid, Ro, and CMRR(0). Your macromodel should have a minimum number of nodes. Solution The following macromodel is used to solve this problem. 1 0.5Rid 2 0.5Rid AvdR(10)(V1-V2) 5 kARvd2(0)(V1-V2) V4 R1 R2 C2 4 R1 C1 3 V5 Ro V1 V2 2Ro 2Ro Ro Fig. S6.7-03 Verifying the macromodel by solving for V3 gives, V3 = V5 + 0.5(V1+V2) = R2 V4 sR2C2+1R2 - kAvd(0) R2 (V1-V2) + Vicm = Avd(0) Vid sR2C2+1sR1C1+1 - k V i d + Vicm= ( Avd(0) sR1C1+1)(sR2C2+1) (1-ksR1C1-k)Vid + Vicm Choose R1 = 10kΩ → C1=1µF, R2 = 1Ω → C1=0.1µF, Ro = 100Ω, and Rid = 1MΩ and solve for k. (note that the polarity of k was defined in the above macromodel to make k positive). 1-ksR1C1-k = 0 → z = 1 1 R1C1k - 1 → 106 = 102(1k -1) → k ≈10-4 With these choices, the transconductance values of all controlled sources are unity except for the ones connected to the output node, node 3. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 6-72 Problem 6.7-04 Develop a macromodel suitable for SPICE of a differential, current amplifier of Fig. P6.7-4 having the following specifications: iOUT = Ai(s)[i1 - i2] where G B 106 Ai(s) = s+ωa = s+100 Rin1 = Rin2 = 10Ω Rout = 100kΩ and Rin1i1 Rout Current iOUT Amplifier Rin2 i2 Figure P6.7-4 Max|diOUT/dt| = 10A/µs. Your macromodel may use only passive components, dependent and independent sources, and diodes (i.e., no switches). Give a schematic for your macromodel and relate each component to the parameters of the macromodel. (The parameters are in bold.) Minimize the number of nodes where possible. Solution A realization is shown below along with the pertinent relationships. i1 VI1=0V 8 D1 D1 1 4 Rin1=10Ω i2 VI2=0V 104 R1 IVI1 104 R1 IVI2 2 5 Rin2=10Ω 6 7 C1 D2 R1 ISR D2 9 V6,7 Ro Ro= 100kΩ Fig. S6.7-04 dv6,7 iC1 = dt C1 → ISR = 107 C1 Choose C1 = 0.1µF ⇒ IS R = 1A iOUT 3 1 Therefore, R1C1 = 100 1 107 → R1 = 100·C1 = 102 = 100kΩ → R1 = 100kΩ Note that the voltage rate limit becomes a current rate limit because iOUT = v6,7 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-1 CHAPTER 7 – HOMEWORK SOLUTIONS Problem 7.1-01 Assume that VDD = -VSS and I17 and I20 in Fig. 7.1-2 are 100µA. Design W18/L18 and W19/L19 to get VSG18 = VGS19 = 1.5V. Design W21/L21 and W22/L22 so that the quiescent current in M21 and M22 is also 100µA. Solution Assuming VDD = −VSS = 2.5 V, and Vo = 0 V Due to bulk effects, ( ) VT = VT 0 + γ 2φ + VSB − 2φ Thus, VT19 = 0.89 V, and VT18 = 0.95 V Now, VSG18 = VT18 + 2 I18 K ’ P (W L)18 or, W = 13.5 L 18 And, VSG19 = VT19 + 2I 19 K ’ N (W L )19 or, W = 4.9 L 19 Since Vo = 0 V, VT 21 = 1.08 V, and VT 22 = 1.23 V VSG21 = VT 21 + 2I 21 K ’ N (W L)21 or, W = 10.3 L 21 And, VSG22 = VT 22 + 2I 22 K ’ P (W L )22 or, W = 55 L 22 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-2 Problem 7.1-02 Calculate the value of VA and VB in Fig. 7.1-2 and therefore the value of VC. Solution The first trip point VA is defined as the input for which M5 trips (or turns on). If it is assumed that the small-signal gain of the inverters (M1 − M 3 and M2 − M 4 ) is large, then it can be assumed that M5 will trip when M1 − M 3 are in saturation. Thus, ( ) VA = VGS1 = VT1 + β3 β1 VSG3 − VT 3 → VA = 0.9 V Similarly, it can be assumed that M6 will trip when M2 − M 4 are in saturation. Thus, ( ) VB = VGS2 = VT 2 + β4 β2 V SG 4 − VT 4 or, VA = 1.0 V So, VC = VB − VA = 0.1V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-3 Problem 7.1-03 Assume that K'N = 47 µA/V2, K'P = 17 µA/V2, VTN = 0.7 V, VTP = −0.9 V, γN = 0.85 V1/2, γP = 0.25 V1/2, 2|φF| = 0.62 V, λN = 0.05 V-1, and λP = 0.04 V-1. Use SPICE to simulate Fig. 7.1-2 and obtain the simulated equivalent of Fig. 7.1-3. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-4 Problem 7.1-04 Use SPICE to plot the total harmonic distortion (THD) of the output stage of Fig. 7.1-5 as a function of the RMS output voltage at 1 kHz for an input-stage bias current of 20 µA. Use the SPICE model parameters given in the previous problem. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-5 Problem 7.1-05 An MOS output stage is shown in Fig. P7.1-5. Draw a small-signal model and calculate the ac voltage gain at low VDD frequency. Assume that bulk effects can be neglected. Solution Referring to the figure vgs 2 = vout , and vgs1 = vin M2 M6 vout Applying nodal analysis (gds 2 + gds1)v gs4 + gm1vin + gm2vout = 0 (1) vin And, gm4vgs4 + (gm3 + gds4 )vout = 0 (2) From Equations (1) and (2) vout vin = (gm2 gm4 − gm1gm4 − (gm3 + gds4 )(gds1 + gds2 )) M5 M1 VSS Figure P7.1-5 + vgs1=vin - gm1vgs1 rds1 rds2 gm2vgs2 + vgs4 - gm4vgs4 + rds4 1/gm3 vout = vgs4 - Fig. S7.1-05A Problem 7.1-06 Find the value of the small-signal output resistance of Fig. 7.1-9 if the W values of M1 and M2 are increased from 10µm to 10µm. Use the model parameters of Table 3.1-2. What is the -3dB frequency of this buffer if CL = 10pF? Solution The loop-gain of the negative feedback loop is given by LG = − gm2 (gm6 + gm8 ) 2gm4 (gds6 + gds7 ) or, LG = −164 The output resistance can be expressed as Rout = (gds6 + gds7 )−1 1− LG or, Rout = 67.3 Ω The –3 dB frequency point is f−3dB = 1 2πRout CL or, f-3dB = 236 MHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-6 Problem 7.1-07 A CMOS circuit used as an output buffer for an OTA is shown. Find the value of the small signal output resistance, Rout, and from this value estimate the -3dB bandwidth if a 50pF capacitor is attached to the output. What is the maximum and minimum output voltage if a 1kΩ resistor is attached to the output? What is the quiescent power dissipation of this circuit? Use the following model parameters: KN’=110µA/V2, KP’ = 50µA/V2, VTN = -VTP = 0.7V, λN = 0.04V-1 and λP = 0.05V-1. Solution Use feedback concepts to calculate the output resistance, Rout. Ro Rout = 1-LG where Ro is the output resistance with the feedback open and LG is the loop gain. 1 1 106 Ro = gds6+gds7 = (λN+λP)I6 = 0.09·500 = 22.22kΩ The loop gain is, vout’ LG = vout = - 1gm2gm6 2 gm4 + gm1gm9 gm7 Ro gm1 = gm2 = 2·110·50·10 = 331.67µS, gm3 = gm4 = 2·50·50·10 = 223.6µS, gm6 = 2·50·100·500 = 2236µS and gm7 = 2·110·500·100 = 3316.7µS ∴ vout’ LG = vout = - 1-331.67·2236 2 223.6 + -331.67·3316.7 331.67 = -73.68V/V Ro Rout = 1-LG 22.22kΩ = 1+73.68 = 294.5Ω 1 1 f-3dB = 2π·Rout·50pF = 2π·294.5·50pF = 10.81MHz To get the maximum swing, we must check two limits. First, the saturation voltages of M6 and M7. 2·1000 2·1000 Vds6(sat) = 50·100 = 0.6325V and Vds7(sat) = 110·100 = 0.4264V Second, the maximum current available to the 1kΩ resistor is ±1mA which means that the output swing can only be ±1V. Therefore, maximum/minimum output = ±1V. Pdiss = 6V(650µA) = 3.9mW CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-7 Problem 7.1-08 What type of BJT is available with a bulk CMOS p-well technology? A bulk CMOS n-well technology? Solution In a bulk CMOS p-well technology, n-p-n BJTs (both substrate and lateral) are available. In a bulk CMOS n-well technology, p-n-p BJTs (both substrate and lateral) are available. Problem 7.1-09 Assume that Q10 of Fig. 7.1-11 is connected directly to the drains of M6 and M7 and that M8 and M9 are not present. Give an expression for the small-signal output resistance and compare this with Eq. (9). If the current in Q10-M11 is 500µA, the current in M6 and M7 is 100µA, and ßF = 100, use the parameters of Table 3.1-2 assuming 1µm channel lengths and calculate this resistance at room temperature. Solution Vdd M7 Cc M6 Q10 RL Vout CL M11 Vss The output resistance is Rout ≅ 1 g m10 + (1 + β F 1 )(g ds6 + gds7 ) From Equation (7.1-9) Rout ≅ 1 g m10 + 1 (1 + β F )gm9 Here, gm10 = 19.23 µS and gds6 + gds7 = 9 µS Thus, Rout = 1152 Ω CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-8 Problem 7.1-10 Find the dominant roots of the MOS follower and the BJT follower for the buffered, classA op amp of Ex. 7.1-2. Use the capacitances of Table 3.2-1. Compare these root locations with the fact that GB = 5MHz? Assume the capacitances of the BJT are Cπ = 10pf and Cµ = 1pF. Solution The model of just the output buffer of Ex. 7.1-2 is shown. VDD 100µA 1000µA V1 Cπ Vo 146/1 10µA M8 Q10 vi vo gm9(Vi-V1) R1 C1 rπ gm10(V1-Vo) R2 C2 10/1 M11 M9 90µA CL RL R1 = rds8||rds9 R2 = rds11||ro10||RL 1467/1 100pF 500Ω C1 = Cgd8+Cbd8+Cgs9+Cbs9+Cµ10 C2 = CL VSS Fig. S7.1-10 The nodal equations can be written as, gm9Vi = (gm9 + G1 + gπ10 + sCπ10 + sC1)V1 – (gπ10 + sCπ10)Vo 0 = –( gm10 + gπ10 + sCπ10)V1 + (gm10 + G2 + gπ10 + sCπ10 + sC2)Vo Solving for Vo/Vi gives, Vo Vi = gm9(gm10+ gπ10+ sCπ10) (gπ10 + sCπ10)(gm9+ G1 + G2 + sC1 + sC2) + (gm10+ G2+ sC2)(gm9+ G1 + sC1) Vo gm9(gm10+ gπ10+ sCπ10) Vi = a0 + sa1 + s2a2 where a0 = gm9gπ10 + gπ10G1 + gπ10G2 + gm9gm10 + gm10G1 + gm9G2 + G1G2 a1 = gm9Cπ10+G1Cπ10+G2Cπ10+gπ10C1+gπ10C2+gm10C1+G2C1+gm9C2+G1C2 a2 = Cπ10C1 + Cπ10C2 + C1C2 The numerical value of the small signal parameters are: 1mA gm10 = 25.9mV = 38.6mS, G2 = 2mS, gπ10 = 386µS, gm9 = 2·50·10·90 = 300µS, G1 = gds8 + gds9 = 0.05·100µA + 0.05·90µA = 9.5µS C2 = 100pF, Cπ10 = 10pF, C1 = Cgs9 + Cbs9 + Cbd8 + Cgd8 + Cµ10 Cgs9 = Cov +0.667CoxW9L9 = (220x10-12)(10x10-6) +0.667(24.7x10-4)(10x10-12) = 18.7fF CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-9 Problem 7.1-10 – Continued Cbs9 = 560x10-6(30x10-12)+350x10-12(26x10-6) = 25.9fF (Assumed area=3µmx10µm = 30µm and perimeter is 3µm+10µm+3µm+10µm = 26µm) Cbd8 = 560x10-6(438x10-12)+350x10-12(298x10-6) = 349fF Cgd8 = Cov = (220x10-12)(146x10-6) = 32.1fF ∴ C1 = 18.7fF + 25.9fF + 349fF + 32.1fF + 1000fF = 1.43pF (We have ignored any reverse bias influence on pn junction capacitors.) The dominant terms of a0 , a1, and a2 based on these values are shown in boldface above. ∴ Vo Vi ≈ gm9gm10+ gm9(gm10+ gπ10+ sCπ10) gπ10G2+s(G2Cπ10+gπ10C2+gm10C1+gm9C2)+s2C2Cπ10 Vo gm9gm10 Vi = gm9gm10+ gπ10G2 sCπ10 1 + gm10 1 + s G2Cπ10+gπ10C2+gm10C1+gm9C2 gm9gm10+ gπ10G2 + s 2 C2Cπ10 gm9gm10+ gπ10G2 Assuming negative real axis roots widely spaced gives, 1 p1 = - a -(gm9gm10+ gπ10G2) 1.235x10-5 = G2Cπ10+gπ10C2+gm10C1+gm9C2 = - 1.465 x10-13 = -84.3 x106 rads/sec. = -13.4MHz a -(G2Cπ10+gπ10C2+gm10C1+gm9C2) 1.465 x10-13 p2 = - b = C2Cπ10 = - 100x10-12·10x10-12 = -146.5 x106 rads/sec. → -23.32MHz gm10 z1 = - Cπ10 38.6x10-3 = - 10 x10-12 = -3.86 x109 rads/sec. → -614MHz We see that neither p1 or p2 is greater than 10GB if GB = 5MHz so they will deteriorate the phase margin of the amplifier of Ex. 7.1-2. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-10 Problem 7.1-11 Given the op amp in Fig. P7.111, find the quiescent currents flowing in the op amp, the smallsignal voltage gain, ignoring any loading produced by the output stage and the small-signal output resistance. Assume K'N = 25 µA/V2 and K'P = 10 µA/V2 and λ = 0.04 V-1 for both VDD 10 20µA 2 M3 60µA M1 - 8 vin 2 10 2 M4 60µA M2 8 2 14 2µA 2 M6 Q1 40µA Q2 200µA vout M8 + 2 2 M5 120µA 12 2 4 M9 2 20 M7 2 All W/L values in microns VSS Figure P7.1-11 - Solution types of MOSFETs. Assume the the BJT has a current gain of βF = 100. Solution The quiescent currents flowing in the op amp are shown on the above schematic. The small-signal model parameters for the MOSFETs are: gm1 = gm2 = 2·25·4·60 = 109.5µS and gm6 = 2·10·7·40 = 74.8µS 25x106 25x106 rds2 = rds4 = 60 = 0.4167MΩ, rds6 = rds7 = 40 = 0.625MΩ 25x106 2x10-6 and rds9 = 200 = 0.125MΩ For the two BJT’s,gm1 = 26x10-3 = 7.7µS, 101 200x10-6 101 rπ1 = 7.7µS = 1.308MΩ, gm2 = 26x10-3 = 7.7mS and rπ2 = 7.7mS = 13.08kΩ The small-signal voltage gain is Av = gm1RI gm6RII Abuff where RI = 0.4167MΩ||0.4167MΩ 0.2083ΜΩ and RII = 0.625MΩ||0.615MΩ = 0.3125MΩ. (1+βF)2rds9 10120.125MΩ Abuff = rπ1+(1+βF)[rπ2+(1+βF)rds9] = 1.3MΩ+101[13.08kΩ+101·0.125MΩ] = 0.998 ∴ Av = 109.5µS·0.2083MΩ·74.8µS·0.3125MΩ·0.998 = 532.2V/V Rout = rds9||(rπ1+RII1)/+(β1+FβF)+rπ2 = (0.3125MΩ+1.208MΩ)/101+13.08kΩ 0.125MΩ|| 101 = 0.125MΩ||288 = 287.4Ω CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-11 Problem 7.2-1 Find the GB of a two-stage op amp using Miller compensation using a nulling resistor that has 60° phase margin where the second pole is -10x106 rads/sec and two higher poles both at -100x106 rads/sec. Assume that the RHP zero is used to cancel the second pole and that the load capacitance stays constant. If the input transconductance is 500µA/V, what is the value of Cc? Solution The resulting higher-order poles are two at -100x106 radians/sec. The resulting phase margin expression is, PM = 180° - tan-1(Av(0)) - 2tan-1G10B7 = 90° - 2tan-1G10B7 = 60° ∴ 30° = 2tan-1G10B7 → G B 107 = tan(15°) = 0.2679 GB = 2.679x107 = gm1 Cc 500x10-6 → Cc = 26.79x107 = 18.66pF Problem 7.2-02 For an op amp where the second pole is smaller than any larger poles by a factor of 10, we can set the second pole at 2.2GB to get 60° phase margin. Use the pole locations determined in Example 7.2-2 and find the constant multiplying GB if p6 for 60° phase margin. Solution Referring to Example (7.2-2) p6 = −0.966 Grad/sec pA = −1.346 Grad/sec pB = −1.346 Grad/sec p8 = −3.149 Grad/sec p9 = −3.149 Grad/sec p10 = −3.5 Grad/sec For a phase margin of 60o , the contributions due to all the poles on the phase margin can be given as tan−1 GB p6 + 2 tan −1 GB pA + 2 tan −1 GB p8 + tan −1 GB p10 = 30o Solving for the value of gain-bandwidth, we get GB ≅ 0.23p6 = 35 MHz. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-12 Problem 7.2-03 What will be the phase margin of Ex. 7.2-2 if CL = 10pF? Solution The value of the output resistance from Example (7.2-2) is Rout = 19.4 MΩ Thus, the dominant pole is p1 = −1 Rout CL = 8.2 KHz. The gain-bandwidth is given by GB = Av (0) p1 = (7464)(8.2K) = 61 MHz. Considering the location of the various poles from Example (7.2-2), the phase margin becomes PM = 180o − 90o − tan −1 GB p6 + 2 tan −1 GB pA + 2 tan −1 GB p8 + tan −1 GB p10 [ { }] or, PM = 180o − 90o − 21.7o + 32o+ 14o + 6.2o or, PM = 16o CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-13 Problem 7.2-04 Use the technique of Ex. 7.2-2 to extend the GB of the cascode op amp of Ex. 6.5-2 as much as possible that will maintain 60° phase margin. What is the minimum value of CL for the maximum GB? Solution Assuming all channel lengths to be 1 µm , the total capacitance at the source of M7 is C7 = Cgs7 + Cbd7 + Cgd6 + Cbd6 → C7 = 75 + 51+ 9 + 51 = 186 fF gm7 = 707 µS Thus, the pole at the source of M7 is pS 7 = − g m7 C7 = −605 MHz. The total capacitance at the source of M12 is C12 = Cgs12 + Cbd12 + Cgd11 + Cbd11 → C12 = 34 + 29 + 4 + 29 = 96 fF gm12 = 707 µS Thus, the pole at the source of M12 is pS 12 = − g m12 C12 = −1170 MHz. The total capacitance at the drain of M4 is C4 = Cgs4 + Cgs6 + Cbd4 + Cgd2 + Cbd 2 → C4 = 43 + 75 + 21+ 3 + 19 = 161 fF gm4 = 283 µS Thus, the pole at the drain of M4 is p D4 = − g m4 C4 = −280 MHz. The total capacitance at the drain of M8 is C8 = Cgd8 + Cbd8 + Cgs10 + Cgs12 → C8 = 9 + 51+ 34 + 34 = 128 fF R2 + 1 g m10 = 3.4 KΩ Thus, the pole at the drain of M8 is p D8 = − R2 + 1 1 g m10 C8 = −366 MHz. For a phase margin of 60o , we have PM = 180o − 90 o − tan −1 GB pS 7 + tan −1 GB pS12 + tan −1 GB p D4 + tan −1 GB pD 8 Solving the above equation GB ≅ 65 MHz and Av = 6925 V/V Thus, p1 = 9.39 KHz, and CL ≥ 1.54 pF CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-14 Problem 7.2-05 For the voltage amplifier using a current mirror shown in Fig. 7.2-11, design the currents in M1, M2, M5 and M6 and the W/L ratios to give an output resistance which is at least 1MΩ and an input resistance which is less than 1kΩ. (This would allow a voltage gain of - 10 to be achieved using R1 = 10kΩ and R2 = 1MΩ. Solution Rout = (g ds6 1 + gds2 ) Let, I2 = I6 = 10 µA or, Rout = (g ds6 1 + g ds2 )= 1.1 MΩ Given, R1 = 10 KΩ , R2 = 1000 KΩ , and Av = −10 And, Av = − R 2 A0 R1(1+ A0 ) Thus, A0 = I2 I1 = 1 9 or, I2 = I6 = 10 µA and I1 = I5 = 90 µA Rin = 1 g m1 =1 KΩ or, W L 1 = 50.5 , and W L 2 = 5.6 and, W L 5 = 50.5 , and W L 6 = 5.6 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-15 Problem 7.2-06 In Ex. 7.2-3, calculate the value of the input pole of the current amplifier and compare with the magnitude of the output pole. Solution Assuming all channel lengths to be 1 µm . In this problem, A0 = 0.1 , S2 = 20 , S1 = 200 , I2 = 100 µA , and I1 = 1000 µA gm1 = 6.63 mS Thus, Rin = R3 + 1 g m1 = 451 Ω The input capacitance is Cin = Cgd5 + Cbd5 + Cgs3 + Cgs 4 + Cgd3 + Cgd4 or, Cin = 44 + 253 + 375 + 38 + 44 + 4.4 = 758 fF The input pole is given by pin =− 1 RinC in = −466 MHz which is compared to 50 MHz for the output pole. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-16 Problem 7.2-07 Add a second input to the voltage amplifier of Fig. 7.2-12 using another R1 resistor connected from this input to the input of the current amplifier. Using the configuration of Fig. P7.2-7, calculate the input resistance, output resistance, and -3dB frequency of this circuit. Assume the values for Fig. 7.2-12 as developed in Ex. 7.2-3 but let the twoR1 resistors each be 1000Ω. Solution R1 Vin R1 -Av Vin R1 -Av Vout Vout R1/(1-Av) R1(Av-1)/Av Referring to the figure, the Miller resistance, R1 , between the input and the output can be broken as shown. Here, R1 = 1 KΩ , R2 = 110 KΩ , and R3 = 0.3 KΩ The input resistance can be written as Rin = R1 + 1 R1 − Av || R3 + 1 g m1 → Rin = 1K + 1K 1+ 10 || 300 + 1 6.63m or, Rin = 1076 Ω The output resistance can be written as Rout = 1 g m12 || R1 (Av Av −1) → Rout = 636 Ω The –3 dB frequency, the pole created at the drains of M4 and M6, is given by f−3dB = 1 2πR2Co where, R2 = 110 KΩ , and Co = 105 pF. So, f-3dB = 13.87 MHz. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-17 Problem 7.2-08 Replace R1 in Fig. 7.2-12 with a differential amplifier using a current mirror load. Design the differential transconductance, gm, so that it is equal to 1/R1. Solution Vdd M7 M15 M16 M5 i1 R2 Vin M13 M14 R3 M3 VBIAS M17 M1 VSS Referring to the figure, the output current of the input transconductor, i1 , is given by i1 = gm13vin Comparing with the expression i1 = vin R1 , we get R1 = 1 g m13 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-18 Problem 7.3-01 Compare the differential output op amps of Fig. 7.3-3, 7.3-5, 7.3-6, 7.3-7, 7.3-8 and 7.310 from the viewpoint of (a.) noise, (b.) PSRR, (c.) ICMR [Vic(max) and Vic(min)], (d.) OCMR [Vo)max) and Vo(min)], (e.) SR assuming all input differential currents are identical, and (f.) power dissipation if all current of the input differential amplifiers are identical and power supplies are equal. Solution Assume that all differential amplifiers have the same bias current of ISS. VDD M7 vo1 Cc Rz vi1 VDD V+- BP M6 M3 M4 Rz Cc vo2 M1 M2 vi2 M4 M6 vo2 M15 M14 M5 M13 M7 R1 vi1 vi2 M1 M2 vo1 M5 M9 V+- BN M8 VSS Figure 7.3-3 Two-stage, Miller, differential-in, differential-out op amp. M7 vo1 VDD M3 V+- BP M4 M13 Cc Rz vi1 M1 M14 Rz Cc vi2 M2 M6 vo2 M9 M10 + M5 M12 M8 VBN - VSS Figure 7.3-6 Two-stage, Miller, differential-in, differential-out op amp with a push-pull output stage. M7 M9 vo1 M15 M13 M5 M21 VDD M3 M4 M6 M20 vi1 R2 M22 M1 M2 vi2 M19 R1 M23 VBias M11 M17 M18 M12 M8 M10 vo2 M16 M14 VSS Figure 7.3-8 Unfolded cascode op amp with differential-outputs. R2 M16 M3 M12 M8 M10 M17 M9 VBias M11 VSS Figure 7.3-5 Differential output, folded-cascode op amp. M4 M12 VDD M20 M5 M13 M14 M6 M10 vo2 Rz Cc vi1 M16 M8 M19 M7 R1 vi2 M1 M2 Rz M18 M3 VBias M9 M15 M11 Cc vo1 M17 VSS Figure 7.3-7 Two-stage, differential output, folded-cascode op amp. VDD M9 M7 M8 M10 M26 M25 M13 vo1 M15 vi1 M21 M19 R2 M1 M2 M3 M4 vi2 M24 M22 R1 M20 M14 vo2 M11 M27 M28VB+ias - M17 M5 M18 M6 M16 M23 M12 VSS Figure 7.3-10 Class AB, differential output op amp using a cross-coupled differential input stage. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-19 Problem 7.3-01 – Continued Noise PSRR ICMR Vic(max) Vic(min) OCMR Vo(max) Vo(min) SR Fig. 7.3-3 Good Poor VDD-VON VSS+ 2VON+VT VDD-VON VSS+VON ISS/Cc Fig. 7.3-5 Poor Good VDD+VT VSS+ 2VON+VT VDD-2VON VSS+2VON ISS/CL Fig. 7.3-6 Good Poor Fig. 7.3-7 Poor Good Fig. 7.3-8 Okay Good VDD-VON VSS+ 2VON+VT VDD+VT VSS+ 2VON+VT VDD-VON VSS+ 2VON+VT VDD-VON VDD-VON VDD-2VON VSS+VON VSS+VON VSS+2VON ISS/Cc ISS/CL ISS/CL Fig. 7.3-10 Poor Good VDD-VON VSS+ 3VON+2VT VDD-2VON VSS+2VON ISS/CL Problem 7.3-02 Prove that the load seen by the differential outputs of the op amps in Fig. 7.3-4 are identical. What would be the single-ended equivalent loads if CL was replaced with a resistor, RL? Solution vin + CL vod vin + 2CL vod vin + 2CL 2CL vod 2CL vin + RL vod vin + RL/2 vod RL/2 Referring to the figure, when a capacitive load of CL is driven differentially, the load capacitor can be broken into two capacitors in series, each with a magnitude of 2CL . The mid point of the connection of these two capacitors is ac ground as the output signal swings differentially. In case of a resistive load RL , it can be broken into two resistive loads in series, each resistor being RL / 2 . CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-20 Problem 7.3-03 Two differential output op amps are shown in Fig. P7.3-3. (a.) Show how to compensate these op amps. (b.) If all dc currents through all transistors is 50µA and all W/L values are 10µm/1µm, use the parameters of Table 3.1-2 and find the differential-in, differentialout small-signal voltage gain. + VDD VBias - M8 M3 M4 + VBias Rz + M1 Rz vin Cc - M2 + VBias - Cc M5 VSS (a.) M6 Rz M9 M7 + vout - M10 vout+ Cc vin+ + VBias VSS (b.) Solution a) The compensation of both the op amps are shown in the figure. b) The small-signal voltage gain of Figure P7.3-3(a) is given by Av = (g ds1 + g m1 g m6 g ds 3 )(g ds6 + gds9 ) or, Av = (332 µ )(224µ ) (4.5µ )(4.5µ ) VDD Rz Cc voutvin- Fig. S7.3-3 or, Av = 3673 V/V The small-signal voltage gain of Figure P7.3-3(b) is given by Av = gm1(gm6 + gm9 ) (gds1 + gds3)(gds6 + gds9 ) or, Av = (332 µ )(556 µ ) (4.5 µ )(4.5µ ) or, Av = 9117 V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-21 Problem 7.3-04 Comparatively evaluate the performance of the two differential output op amps of Fig. P7.3-3 with the differential output op amps of Fig. 7.3-3, 7.3-5, 7.3-6, 7.3-7, 7.3-8 and 7.3-10. Include the differential-in, differential-out voltage gain, the noise, and the PSRR. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-22 Problem 7.3-05 Fig. P7.3-5 shows a differential-in, differential-out op amp. Develop an expression for the small-signal, differential-in, differential-out voltage gain and the small-signal output resistance. VDD M8 Cc M3 M4 M6 Cc + + M1 M2 vin vout - - M9 + M5 M7 VBias - VSS Figure P7.3-5 Solution The small-signal differential voltage gain can be found by simply connecting the sources of M1 and M2 to ac ground and solving for the single-ended output assuming the full input is applied single-ended. ∴ Avdd = gm1 gm8 gm3gds8+gds9 Rout = 1 gds8+gds9 + 1 gds6+gds7 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-23 Problem 7.3-06 Use the common-mode output stabilization circuit of Fig. 7.3-13 to stabilize the differential output op amp of Fig. 7.3-3 to ground assuming that the power supplies are split around ground (VDD = |VSS|). Design a correction circuit that will function properly. Solution VDD Vo1 M1 M2 Vo2 M3 M4 VBP M11 M12 Vocm M5 VBN M9 M10 M6 M7 M8 VSS M7 + - vo1 Cc Rz vi1 VDD V+- BP M3 M4 Rz Cc M6 vo2 M1 M2 vi2 M5 M9 M8 VBN VSS Referring to the figure of the common-mode stabilizing circuit, the common-mode voltage at the output nodes vo1 and vo2 will be held close to the common-mode voltage Vocm due to negative feedback. If these two output nodes swing differential, the drain of M5 will not change and thus, the common-mode feedback circuit is non-functional. When the commonmode voltage at these two output nodes tend to change in the same direction, the negative feedback loop of M1-M5-M6-M7-M9 and M2-M5-M6-M8-M10 will reduce the variations at vo1 and vo2, respectively. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-24 Problem 7.3-07 (a.) If all transistors in Fig. 7.3-12 have a dc current of 50µA and a W/L of 10µm/1µm, find the gain of the common mode feedback loop. (b.) If the output of this amplifier is cascoded, then repeat part (a.). Solution VDD + M10 VBP M11 M7 - M6 vo1 Cc Rz M3 M4 Rz Cc vo2 vi1 M1 M2 vi2 M5 M9 V+- BN M8 VSS Figure 7.3-12 Two-stage, Miller, differential-in, differential-out op amp with common-mode stabilization. The loop gain of the common-mode feedback loop is, CMFB Loop gain ≈ - gm10 gds9 = -gm10rds9 or gm11 - gds8 = -gm11rds8 2KP’WID With ID = 50µA and W/L = 10µm/1µm, gm10 = L = 2·50·10·50) = 223.6µS, 1 25 rdsN = λNID = 50µA = 0.5MΩ 1 20 and rdsP = λPID = 50µA = 0.4MΩ ∴ CMFB Loop gain ≈ −gm10rds9 = -223.6(0.5) = -111.8V/V If the output is cascoded, the gain becomes, CMFB Loop gain with cascoding ≈ −ggmds190 gm(cascode)rds(cascode) = -gm10{[rds9 gm(cascode)rds(cascode)]||[gm7rds7 (rds10||rds10]} 2KN’WID gmP = L = 2·110·10·50) = 331.67µS = -(223.6)[(0.5·331.67·0.5)||(223.6)(0.4)(0.2)] = 223.6(14.7) = -3,290 V/V ∴ CMFB Loop gain with cascoding ≈ -3.290V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-25 Problem 7.3-08 Show how to use the common feedback circuit of Fig. 5.2-15 to stabilize the common mode output voltage of Fig. 7.3-5. What would be the approximate gain of the common mode feedback loop (in terms of gm and rds) and how would you compensate the common mode feedback loop? Solution VDD MC5 M4 MC3 MC6 M5 R1 MC4 M6 M7 R1 RCM1 vi1 M1 M2 vi2 vo1 RCM2 vo2 M3 MC1 MC2 VICM MC7 M8 VB2 M9 M10 VB1 M11 VSS Referring to the figure, the loop gain of the common-mode feedback loop can be given by LG = gm,C 2gm 4 2 gm,C 5 gds4 gds6 gm 4 + gds8gds10 gm10 The compensation of the common-mode feedback loop can be done using the output load capacitor (single-ended load capacitors to ac ground). The dominant pole of this loop would be caused at the output nodes by the large output resistance given by Rout = gds4 gds6 1 + gds8gds10 gm4 gm10 Considering the differential output load capacitance to be CL , the dominant pole of the common-mode feedback loop can be expressed as ( ) p1 = Rout 1 2CL The other poles, at the source and drain of MC3, and the source of M6, can be assumed to be large as these nodes are low impedance nodes. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-26 Problem 7.4-01 Calculate the gain, GB, SR and Pdiss for the folded cascode op amp of Fig. 6.5-7b if VDD = -VSS = 1.5V, the current in the differential amplifier pair is 50nA each and the current in the sources, M4 and M5, is 150nA. Assume the transistors are all 10µm/1µm, the load capacitor is 2pF and that n1 is 2.5 for NMOS and 1.5 for PMOS. VDD VDD M6 M7 M14 M4 I4 M5 I5 A B RA RB I1 I2 + M1 M2 vin - VB vout + vin - I1 I2 M13 M6 I6 M1 M2 R1 R2 M7 I7 R9 vout CL Cascode I3 M8 M9 Current Mirror + VBias M3 M12 M10 M11 - VSS (a) VSS (b) Figure 6.5-7 (a) Simplified version of an N-channel input, folded cascode op amp. (b) Practical version (a). Solution ID 50nA gm1 = gm2 = n1(kT/q) = 2.5·25.9mV = 0.772µS 1 and rds1 = rds2 = IDλN = 500MΩ ID 150nA gm4 = gm5 = n1(kT/q) = 1.5·25.9mV = 3.861µS 1 and rds4 = rds5 = IDλN = 133MΩ ID 100nA gm6 = gm7 = n1(kT/q) = 1.5·25.9mV = 2.574µS 1 and rds6 = rds5 = IDλN = 200MΩ ID 100nA gm8 = gm9 = gm10 = gm11 = n1(kT/q) = 2.5·25.9mV = 1.544µS 1 and rds8 = rds9 = rds10 = rds11 = IDλN = 250MΩ Gain: Av(0) = gm1Rout, Rout ≈ rds11gm9rds9||[gm7rds7(rds5||rds2)] = 96.5GΩ||34.23GΩ = 25.269GΩ ∴ Av(0) = 0.772µS·25.269GΩ = 19,508 V/V GB = gm1/CL = 386krads/sec = 61.43kHz (this assumes all other poles are greater than GB which is the case if CL makes RB approximately the same as RA at ω = GB.) SR = 100nA/2pF = 0.05V/µs Pdiss = 3V·(3·150nA) =1.35µW CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-27 Problem 7.4-02 Calculate the gain, GB, SR and Pdiss for the op amp of Fig. 7.4-3 where I5 = 100nA, all transistor widths (M1-M11) are 10µm and lengths 1µm, and VDD = -VSS = 1.5V. If the saturation voltage is 0.1V, design the W/L values of M12-M15 that achieves maximum and minimum output swing assuming the transistors M12 and M15 have 50nA. Assume that IDO = 2nA, np = 1.5, nn = 2.5 and Vt = 25mV. Solution (Solution incomplete) The small-signal gain can be expressed as Av = gm1 2gm 3 gm gm 8 9 gm 7 + gm6 Rout or, Av = gm1Rout The output resistance is given by Rout = gm10 gds10gds6 || gm11 gds11gds7 or, Rout = 96 GΩ Thus, Av = gm1Rout = 73,846 V/V Assuming Cc = 1 pF The dominant pole is p1 =− 1 RoutCc = 1.66 Hz. Thus, the gain-bandwidth becomes GB = Av (0) p1 = 122.5 KHz. The power dissipation is 0.9 µW . ( ) VSG10 = Vdsat 6 + Vdsat10 + n pVt ln W I10 = 0.236 V L 10 ID0 ( ) VGS11 = Vdsat 7 + Vdsat11 + n nVt ln W I11 = 0.26 V L 11 ID0 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-28 Problem 7.4-03 Derive Eq. (17). If A = 2, at what value of vin/nVt will iout = 5I5 or 5Ib if b=1 ? Solution Start with the following relationships: i1 + i2 = I5 + A(i2 - i1) Eq. (15) and i2 i1 = expnvVint Eq. (16) Defining iout = b(i2 - i1) solve for i2 and I1. i1 + i1 expnvVint = I5 + Ai1 expnvVint - Ai1 or i1[(1+A) +(1-A) expnvVint] = I5 → I5 i1 = (1+A) +(1-A) expnvVint Similarly for i2, I5 expnvVint i1 = (1+A) +(1-A) expnvVint I5 expnvVint-1 ∴ iout = b(i2 - I1) = iout = (i2 - I1) = (1+A) +(1-A) expnvVint Eq. (17) vin Setting iout = 5I5 and solving for nVt gives, 5[3- expnvVint] = expnvVint -1 2.667 → 16 = 6 expnvVint → expnvVint = ∴ vin nVt = ln(2.667) = 0.9808 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-29 Problem 7.4-04 Design the current boosting mirror of Fig. 7.4-6a to achieve 100µA output when M2 is saturated. Assume that i1 = 10µA and W1/L1 = 10. Find W2/L2 and the value of VDS2 where i2 = 10µA. Solution Given, S1 =10, I1 = 10 µA, and I1 = 100 µA when M2 is saturated. Thus, S2 =100 And, Vdsat1 = Vdsat2 = 0.135 V Now, in the active region of operation for M2 ID = KN' S2 Vdsat 2Vds − Vd2s 2 or, 10 µ = (100 µ)1000.135Vds − Vd2s 2 or, Vds ≅ 7mV CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-30 Problem 7.4-05 In the op amp of Fig. 7.4-7, the current boosting idea illustrated in Fig. 7.4-6 suffers from the problem that as the gate of M15 or M16 is increased to achieve current boosting, the gate-source drop of these transistors increases and prevents the vDS of the boosting transistor (M11 and M12) from reaching saturation. Show how to solve this problem and confirm your solution with simulation. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-31 Problem 7.5-01 For the transistor amplifier in Fig. P7.5-1, what is the equivalent inputnoise voltage due to thermal noise? Assume the transistor has a dc drain current of 20 µA, W/L = 150 µm/10 µm, K'N = 25 µA/V2, and RD is 100 Kilohms. Solution gm = 122 µS and, Av ≅ − gmRD = −12.2 The equivalent input thermal noise is ee2q = 8KT 3gm + 4 KTRD Av2 or, ee2q = 102.1×10−18 V 2 / Hz or, Veq(rms) ≈ 10nV/ Hz VDD RD 20µA Figure P7.5-1 Problem 7.5-02 Repeat Ex. 7.5-1 with W1 = W2 = 500µm and L1 = L2 = 0.5µm to decrease the noise by a factor of 10. Solution S1 = 500 / 0.5 , S3 = 100/ 20 Flicker noise BN = 7.36×10−22 (Vm)2 and BP = 2.02 ×10−22 (Vm)2 en21 = BP = 8.08× 10−13 fW1 L1 f V 2 / Hz So, e2eq = 2en21 1 + K ’ N BN K ’ P BP L1 L3 2 → ee2q = 1.624 ×10−12 f V 2 / Hz Thermal noise e 2n1 = 8KT 3 g m1 = 0.49 ×10 − 17 V2 / Hz e2eq = 2en21 1 + K ’NW3 L1 KP’ W1L3 → The corner frequency, fc = 150.4 KHz ee2q = 1.08 ×10−17 V 2 / Hz ( ) ( ) Considering a 100 KHz. Bandwidth Ve2q (rms) = 1.624× 10−12 ln 105 + 1.08×10−17 105 → Veq (rms) = 4.45 µV CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-32 Problem 7.5-03 Interchange all n-channel and p-channel transistors in Fig. 7.5-1 and using the W/L values designed in Example 7.5-1, find the input equivalent 1/f noise, the input equivalent thermal noise, the noise corner frequency and the rms noise in a 1Hz to 100kHz bandwidth. Solution The flicker noise is BN = 7.36×10−22 (Vm)2 and BP = 2.02 ×10−22 (Vm)2 en21 = BN = 7.36×10−12 fW1 L1 f V 2 / Hz So, e2eq = 2en21 1 + K ’ P BP K ’ N BN L1 L3 2 → ee2q = 14.72 ×10−12 f V 2 / Hz The thermal noise is e 2n1 = 8KT 3 g m1 = 1.05 ×10−17 V 2 / Hz e2eq = 2en21 1 + KP’ W3L1 K ’NW1L3 → ee2q = 2.42x10-17 V2/Hz The corner frequency is fc = 608 KHz. Considering a 100 KHz. Bandwidth Ve2q (rms) = 14.72x10-12 ln(105) + 2.42x10-17 ln(105) → Veq(rms) = 13.1 nV/ Hz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-33 Problem 7.5-04 Find the input equivalent rms noise voltage of the op amp designed in Ex. 6.3-1 of a bandwidth of 1Hz to 100kHz. Solution The input referred noise is given by e2eq = 2en21 + g m3 g m1 2 2en23 + 1 Av1 2 e2n6 Flicker noise ee2q = 2en21 + K ’ P BP K ’ N BN L1 L3 2 2e2n3 + 1 Av1 2 en26 en21 = 2.45 ×10 −10 f V 2 / Hz en23 = 1.35 ×10 −11 f V 2 / Hz en26 = 2.15 ×10−12 f V 2 / Hz Av1 = −68.5 Thus, ee2q = 4.9 ×10 − 10 f V 2 / Hz Thermal noise en21 = 1.11×10−16 V 2 / Hz e2n3 = 7.395×10−17 V 2 / Hz en26 = 1.17 ×10−17 V 2 / Hz or, ee2q = 5.58× 10−16 V 2 / Hz The corner frequency is fc = 884 KHz Considering a 100 KHz bandwidth ( ) ( ) Ve2q (rms) = 4.9 ×10−10 ln 105 + 5.58× 10−16 105 →Veq(rms) = 75.5 µV/ Hz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-34 Problem 7.5-05 Find the equivalent rms noise voltage of the op amp designed in Example 6.5-2 over a bandwidth of 1Hz to 100kHz. Use the values for KF of Example 7.5-1. Solution The circuit for this VDD amplifier is shown. The W/L ratios in microns are: M4 M6 M15 S1 = S2 = 12/1 M3 M8 M14 M7 S3 = S4 = 16/1 S5 = 7/1 M1 M2 S5 = 8.75/1 ee2q * ito2 R1 R2 M9 M12 S6 = S7 = S8 = S14 = S15 = 40/1 S9 = S10 = S11 = S12 = 18.2/1 Find the short M5 + VBias - M10 M11 M13 VSS Fig. S7.5-05 2 circuit noise current at the output, i to , due to each noise-contributing transistor in the circuit (we will not includeM7, M9, M12 and M14 because they are cascodes and their effective gm is small. The result is, 2 i to = 2gm21en21ggmm2283 + 2gm28en23 + 2gm28en28 + + 2gm211en210 where we have assumed that gm1=gm2, gm3=gm4, gm6=gm8, and gm10=gm11 and 2 en1=en2, en3=en4, en6=en8, and en10=en11. Dividing i to by the transconductance gain gives ee2q it2o = gm21gm28/gm23 = 2en21 + 2ggmm2231en23 + 2ggmm2231en28 + 2ggmm2231ggmm22181e 2 n10 The values of the various parameters are: gm1 = 251µS, gm3 = 282.5µS, gm8 = 707µS, and gm11 = 707µS. ∴ ee2q = 2en211 + 1.266eenn2231 + 2 e n8 2 en1 + eenn22110 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-35 Problem 7.5-05 – Continued 1/f Noise: Using the results of Ex. 7.5-1 we get BN = 7.36x10-22(V·m)2 and Bp = 2.02x10-22(V·m)2 en21 = BN fW1L1 7.36x10-22 = f·12x10-12 = 6.133x10-11 f V2/Hz en23 BP·f·W1L1 BP·W1L1 2.02·12 en21 = BN·f·W3L3 = BN·W3L3 = 7.36·16 = 0.2058 en28 BP·f·W1L1 BP·W1L1 2.02·12 en21 = BN·f·W8L3 = BN·W3L3 = 7.36·40 = 0.0823 en210 BN·f·W1L1 BP·W1L1 12 en21 = BN·f·W10L10 = BN·W3L3 = 18.2 = 0.6593 ∴ ee2q 6.133x10-11 =2 f [1+1.266(0.2058+0.0823+0.6593)] = 6.133x10-11 2 f 2.1995 ee2q = 2.1995x10-10 f V2/Hz Thermal noise: en21 = 8kT 3gm1 8·1.38x10-23·300 = 3·251x10-6 = 4.398x10-17 V2/Hz en23 gm1 251 en28 en210 gm1 251 en21 = gm3 = 282.4 = 0.8888 and en21 = en21 =gm8 = 707 = 0.0.355 The corner frequency is fc = 2.698x10-10/2.66x10-16 = 1.01x106 Hz. Therefore in a 1Hz to 100kHz band, the noise is 1/f. Solving for the rms value gives, 100,000 V 2 eq (rms) = ⌠2.698x10-10 ⌡ f df = 2.698x10-10[ln(100,000) – ln(1)] 1 = 3.1062x10-9 V2(rms) ∴ Veq(rms) = 55.73µV( rms) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-36 Problem 7.6-01 If the W and L of all transistor in Fig. 7.6-3 are 100µm and 1µm, respectively, find the lowest supply voltage that gives a zero value of ICMR if the dc current in M5 is 100µA. Solution I5 = 100 µA, and W L = 100 VIC (max) = VDD + VT1(min) − Vdsat3 and, VIC (min) = Vdsat1 + VT1(max) + Vdsat5 The input common-mode range is ICMR = VIC (max) − VIC (min) For ICMR=0 VDD = Vdsat1 + Vdsat 5 + Vdsat 3 + VT1(max) − VT1(min) or, VDD = 2I1 KN' S1 + 2I5 K ' N S5 + 2I3 KP' S3 + VT1(max) − VT1(min) → VDD = 0.671 V Problem 7.6-02 Repeat Problem 1 if M1 and M2 are natural MOSFETs with a VT = 0.1V and the other MOSFET parameters are given in Table 3.1-2. Solution VT1 = 0.1 V, I5 = 100 µA, and W L = 100 Let, the variation in the threshold voltage be ± 20% or, ∆VT 1 = ±0.02 V VIC (max) = VDD + VT1(min) − Vdsat3 and, VIC (min) = Vdsat1 + VT1(max) + Vdsat5 The input common-mode range is ICMR = VIC (max) − VIC (min) For ICMR=0 VDD = Vdsat1 + Vdsat 5 + Vdsat 3 + VT1(max) − VT1(min) or, VDD = 2I1 KN' S1 + 2I5 K ' N S5 + 2I3 KP' S3 + VT1(max) − VT1(min) → VDD = 0.411 V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-37 Problem 7.6-03 Repeat Problem 1 if M1 and M2 are depletion MOSFETs with a VT = -1V and the other MOSFET parameters are given in Table 3.1-2. Solution VT1 = −1 V, I5 = 100 µA , and W L = 100 Let, the variation in the threshold voltage be ± 20% or, ∆VT 1 = m0.2 V VIC (max) = VDD + VT1(min) − Vdsat3 and, VIC (min) = Vdsat1 + VT1(max) + Vdsat5 The input common-mode range is ICMR = VIC (max) − VIC (min) For ICMR=0 VDD = Vdsat1 + Vdsat 5 + Vdsat 3 + VT1(max) − VT1(min) or, VDD = 2I1 KN' S1 + 2I5 K ' N S5 + 2I3 KP' S3 + VT1(max) − VT1(min) → VDD = 0.711 V Problem 7.6-04 Find the values of Vonn and Vonp of Fig. 7.6-4 if the W and L values of all transistors are 10µm and 1µm, respectively and the bias currents in MN5 and MP5 are 100µA each. Solution Vonn = Vdsat, N 5 + VTN1(max) + Vdsat, N1 or, Vonn = 0.426 + 0.85 + 0.302 Let us assume that VDD = 2.5 V → Vonn = 1.578 V Vonp = VDD − Vdsat, P1 − Vdsat, P5 − VT, P1(max) → Vonp = 0.57 V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-38 Problem 7.6-05 Two n-channel source-coupled pairs, one using regular transistors and the other with depletion transistors having a VT = -1Vare connected with their gates common and the sources taken to individual current sinks. The transistors are modeled by Table 3.1-2 except the threshold is -1V for the depeletion transistors. Design the combined sourcecoupled pairs to achieve rail-to-rail for a 0V to 2V power supply. Try to keep the equivalent input transconductance constant over the ICMR. Show how to recombine the drain currents from each source-coupled pair in order to drive a second-stage single-ended. Solution VDD VBP M3 M4 MD3 MD4 + M1 M2 - VT=0.7 VBN M5 - MD1 MD2 + VT=-1.0 MD5 VBP M3 M4 VSS VDD + M1 M2 VT=0.7 - VBN M5 MD1 MD2 VT=-1.0 + MD5 VSS Considering the differential amplifier consisting of M1-M5, the range of the input common mode can be given by VIC (max) = VDD + VT1 − Vdsat 3 and VIC (min) = VSS + VT1 + Vdsat1 + Vdsat 5 (1) Now, considering the differential amplifier consisting of MD1-MD5, the range of the input common mode can be given by VIC (max) = VDD + VT ,D1 − Vdsat,D3 and VIC (min) = VSS + VT ,D1 + Vdsat,D1 + Vdsat,D5 (2) Let us assume that the saturation voltage (Vdsat ) of each of the transistors is equal to 0.1 V, and let VDD = 2 V Then, from Equation (1), for the transistors M1-M5 VIC (max) = 2.6 V and VIC (min) = 0.9 V From Equation (2), for the transistors MD1-MD5 Vic(max) = 0.9 V and Vic(min) = -0.8 V Since, the common-mode input range of both stages overlap, they can be joined as shown in the figure and will provide a constant gm across the rail-to-rail input range of 0-2 V. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-39 Problem 7.6-06 Show how to create current mirrors by appropriately modifying the circuits in Sec. 4.4 that will have excellent matching and a VMIN(in) = VON and VMIN(out) = VON. Solution VDD VDD I1-IB IB iin M3 M1 IB M4 M6 M5 I2 I1 IB1 iout iin IB2 IB1 I2 iout M7 M3 or M4 M6 M7 M5 M2 M1 IB2 M2 Fig. 7.6-13A Problem 7.6-07 Show how to modify Fig. 7.6-16 to compensate for the temperature range to the left of where the two characteristics cross. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-40 Problem 7.6-08 For the op amp of Ex. 7.6-1, find the output and higher order poles and increase the GB as much as possible and still maintain 60° phase margin. Assume that L1+L2+L3 = 2µm in order to calculate the bulk-source/drain depletion capacitors (assume zero voltage bias). What is the new value of GB and the value of Cc? Solution Referring to the Figure 7.6-17 and Example 7.6-1, the dominant pole is caused at the drain of M9. The second pole ( p2) is caused at the output by the load capacitor. The magnitude of this pole is given by p2 = −gm14 CL = −20 MHz. To increase the gain bandwidth, let us design the nulling resistor ( RZ ) in such a way that the LHP zero created by this resistor will cancel the load pole. The value of Cc = 2 pF. Thus, RZ = 1 gm14 +1 2πCc p2 = 4.77 KΩ We can see that the pole at the source of M6 is p6 = −1.2 GHz. The third pole ( p3) at the output is caused by the nulling resistor and is given by p3 ≅ −1 2πRZ Cgs14 = −101 MHz. In order to maintain a phase margin of 60o, the gain bandwidth can be calculated as tan−1 GB = 30o → GB = 58 MHz. p3 or, gm1 = (GB)Cc = 729 µS → W L 1 = W L 2 = 241.6 Considering the minimum input common-mode range Vdsat5 = 0.22 V → W L 5 = 7.5 Considering the maximum input common-mode range W L 3 = W L 4 = 19.2 Rest of the transistor sizes are the same as calculated in Example 7.6-1. But, the smallsignal voltage gain is 18,000 V/V CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 7-41 Problem 7.6-09 Replace M8 and M9 of Fig. 7.6-17 with a high swing cascode current mirror of Fig. 4.3-7 and repeat Ex. 7.6-1. Solution Referring to the figure and Example 7.6-1 VGS8 = 1.5 V → Vdsat 8 = 0.8 V → W L 8 = W L 9 = 0.57 ≅1 Let us assume VBIAS = 2 V. Then, Vdsat17 = 0.5 V → W L 17 + W L 18 = 1.45 The output resistance seen at the drain of M7 is ( ) Rout1 = gds18 gds9 + 1 gds7 gds4 + gds2 = 50 MΩ gm18 gm 7 Thus, the overall small-signal gain becomes 2.8 × 105 V/V. The gain bandwidth is 10 MHz. The load pole is at 20 MHz. Referring to the figure, the extra pole that would affect the phase margin the most is created at the source of M18. The resistance seen at the source of M18 can be given by ( ( ) ) [ ] RS18 = rds18 + gm 7 gds7 gds4 + 1 + gm18rds18 gds2 || rds9 → RS18 = [844K] || [1.25M] = 504 KΩ The pole at the source of M18 is ( ) p18 = RS18 −1 Cgs18 + Cbd18 + Cgd 9 + Cbd 9 ( ) → p18 = −1 (504K) 9 × 10−15 = −35 MHz It can be seen that this pole p18 would degrade the phase margin by 16o. Thus to maintain a 60o phase margin with a gain bandwidth of 10 MHz, let us use nulling resistor compensation to cancel this pole. The value of Rz can be given by RZ = 1 gm14 +1 2πCc p18 = 3.07 KΩ The pole due to the introduction of Rz is p4 = −1 RZ Cgs14 = −157 MHz This pole is large enough to affect the phase margin. Though the pole at the source of M18 has been eliminated using the nulling resistor compensation technique, the pole at the source of M7 could be dominant enough to degrade the phase margin. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-1 CHAPTER 8 – HOMEWORK SOLUTIONS Problem 8.1-01 Give the equivalent figures for Figs. 8.1-2, 8.1-4, 8.1-6 and 8.1-9 for an inverting comparator. Solution The figures for the inverting comparator are shown below. Vo VOH Vo VOH Vo VOH vp-vn VOL VIL VIH vp-vn VOL VIL VIH VOS vp-vn VOL Vo VOH tp Vin VIL t VOL VIH t CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-2 Problem 8.1-02 Use the macromodel techniques of Sec. 6.6 to model a comparator having a dc gain of 10,000 V/V, and offset voltage of 10mV, VOH = 1V, VOL = 0V, a dominant pole at -1000 radians/sec. and a slew rate of 1V/µs. Verify your macromodel by using it to simulate Ex. 8.1-1. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-3 Problem 8.1-03 Draw the first-order time response of an inverting comparator with a 20 µs propagation delay. The input is described by the following equation vin = 0 for t < 5 µs vin = 5(t − 5 µs) for 5 µs < t < 7 µs vin = 10 for t > 7 µs Solution The input and the output response of the inverting comparator are shown in the figure. Vo VOH 0.5(VOH+VOL) VOL Vin tp=20 t VIH=10 0.5(VIH+VIL) VIL=0 t 567 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-4 Problem 8.1-04 Repeat Ex. 8.1-1 if the pole of the comparator is -105 radians/sec rather than -103 radians/sec. Solution The pole location is ω c = −100 Krad/s k = Vin = 10m = 100 Vin (min) 0.1m The propagation delay is given by tp = 1 ωc ln 2k 2k − 1 or, t p = 50.1 ns (1) Considering the maximum slew rate, the propagation delay can be expressed as t ’ p = VOH −VOL 2 SR or, t ’ p = 500 ns (2) From Equations (1) and (2), the propagation delay is tp = 500 ns Problem 8.1-05 What value of Vin in Ex. 8.1-1 will give a slewing response? Solution The comparator will start to slew when the propagation delay of the comparator is dominated by its maximum slew rate (and not by the comparator’s small-signal propagation delay). VOH − VOL > 1 ln 2k 2SR ωc 2k − 1 or, ln 2k < ω c (VOH − VOL ) 2k − 1 2SR Solving for k, we get k > 1000.5 or, Vin > 100.05 mV CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-5 Problem 8.2-01 Repeat Ex. 8.2-1 for the two-stage comparator of Fig. 8.2-5. Solution The output swing levels are ( ) VOH = VDD − VDD − VG6(min) − VTP 1− ( ) 1− 2I7 β6 VDD − VG6 (min) − VTP 2 or, VOH = 2.5 − (2.5 − 0 − 0.7)1− 1− 2(234) (50)(38)(2.5 − 0 − 0.7)2 or, VOH = 2.43 V VOL = -VSS = -2.5 V The minimum input resolution is Vin (min) = VOH − VOL Av and, Av = g m1 g m 2 I1I6(λP + λN )2 = 3300 or, Vin(min) = 1.5 mV The pole locations are gds2 + gds4 p1 = CI = 1.074 MHz gds6 + gds7 p2 = CII = 0.67 MHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-6 Problem 8.2-02 If the poles of a two-stage comparator are both equal to -107 radians/sec., find the maximum slope and the time it occurs if the magnitude of the input step is 10Vin(min) and VOH -VOL = 1V. What must be the SR of this comparator to avoid slewing? Solution The response to a step response to the above comparator can be written as, vout’ = 1 – e-tn –tne-tn vout where vout’ = Av(0)Vin and tn = tp1 To find the maximum slope, differentiate twice and set to zero. dvout’ dtn = e-tn + tne-tn - e-tn = tne-tn d2vout’ dtn2 = -tne-tn + e-tn = 0 ⇒ (1-tn)e-tn = 0 ⇒ tn(max) = tp1 = 1 ∴ tn(max) = 1sec tn 1 and t(max) = |p1| = 107 = 0.1µs dvout’(max) dtn = e-1 = 0.3679 V/sec or dvout’(max) dtn = 3.679V/µs dvout’(max) dvout’(max) dt = 10(VOH-VOL)· dtn = 36.79V/µs ∴ Therefore, the slew rate of the comparator should be greater than 36.79V/µs to avoid slewing. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 8.2-03 Repeat Ex. 8.2-3 if p1 = -5x106 radians/sec. and p2 = 10x106 radians/sec. Solution Given p1 = −5 Mrad/s, and p2 = −10 Mrad/s So, m = p2 = 2 p1 When Vin = 10m k = Vin = 15.576 Vin (min) and, t p = 1 = 35.8 ns p1 mk When Vin = 100m (assuming no slewing) k = Vin = 155.76 Vin (min) and, t p = 1 = 11.3 ns p1 mk When Vin = 1 (assuming no slewing) k = Vin = 1557.6 Vin (min) and, t p = 1 = 3.58 ns p1 mk Page 8-7 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-8 Problem 8.2-04 For Fig. 8.2-5, find all of the possible initial states listed in Table 8.2-1 of the first stage output voltage and the comparator output voltage. Solution Condition: VG1 > VG2, I1 < ISS , I 2 > 0 2.1315 < Vo1 < 2.5 , and Vo2 = −2.5 Condition: VG1 >> VG2 , I1 = ISS , I2 = 0 Vo1 = 2.5 , and Vo2 = −2.5 Condition: VG1 < VG2, I1 > 0, I2 < ISS VS2 < Vo1 < VS2 + 0.3 , and Vo2 = 2.5 − 0.123 (2.5 − Vo1 − 0.7) Condition: VG1 << VG2, I1 = 0,I 2 = I SS Vo1 = −2.5 , and Vo2 = 2.47 Condition: VG2 > VG1, I1 > 0, I2 < ISS VS2 < Vo1 < VS2 + 0.3 , and Vo2 = 2.5 − 0.123 (2.5 − Vo1 − 0.7) Condition: VG2 >> VG1, I1 = 0, I2 = ISS Vo1 = −2.5 , and Vo2 = 2.47 Condition: VG2 < VG1, I1 < ISS , I2 > 0 2.1315 < Vo1 < 2.5 , and Vo2 = −2.5 Condition: VG2 << VG1, I1 = I SS , I2 = 0 Vo1 = 2.5 , and Vo2 = −2.5 Problem 8.2-05 Calculate the trip voltage for the comparator shown in Fig. 8.2-4. Use the parameters given in Table 3.1-2. Also, (W/L)2 = 100 and (W/L)1 = 10. VBIAS = 1V, VSS = 0V, and VDD = 4 V. Solution Given, VBIAS = 1 , VDD = 4 , VSS = 0 , S7 = 100 , and S7 = 10 The trip point is given by VTRP = VDD − VT 6 − or, VTRP = 1.89 V K ’ N S 7 K ’ P S6 (VBIAS − VSS − VT 7 ) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-9 Problem 8.2-06 Using Problem 8.2-5, compute the worst-case variations of the trip voltage assuming a ±10% variation on VT, K', VDD, and VBIAS. Solution The trip point is given by VTRP = VDD − VT 6 − K ’ N S 7 K ’ P S6 (VBIAS − VSS − VT 7 ) The maximum trip point can be given by VTRP (max) = 1.1VDD − 0.9VT 6 − 0.9K ’ N S 7 1.1K ’ P S 6 (0.9VBIAS − VSS − 1.1VT 7 ) or, VTRP(max) = 3.22 V The minimum trip point can be given by VTRP (min) = 0.9VDD − 1.1VT 6 − 1.1K ’ N S 7 0.9 K ’ P S 6 (1.1VBIAS −VSS − 0.9VT 7 ) or, VTRP(min) = 0.39 V Problem 8.2-07 Sketch the output response of the circuit in Problem 5, given a step input that goes from 4 to 1 volts. Assume a 10 pF capacitive load. Also assume the input has been at 4 volts for a very long time. What is the delay time from the step input to when the output changes logical (CMOS) states? Solution Let us assume VOH = 5 V and VOL = 0 V 5 vout The trip point of the second stage is 4 3.965 V. When the input makes a transition from 4 V to 1, 2.5 tro1 = (0.2 p)(3.965 − 30 µ 0)= 26.4 vin nsandt f ,out = (10 p) (2.5) 234 µ = 106.8 1 0 ns T T+133.2ns time Thus, the total propagation delay is 133.2 ns. This is also the time it takes to change the output logical states. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-10 Problem 8.2-08 Repeat Ex. 8.2-5 with vG2 constant and the waveform of Fig. 8.2-6 applied to vG1. Solution Output fall time, tr: The initial states are vo1 ≈ -2.5V and vout ≈ 2.5V. The reasoning for vo1 is interesting and should be understood. When VG1 = -2.5V and VG2 = 0V, the current in M1 is zero. This means the current is also zero in M4. Therefore, vo1 goes very negative and as M2 acts like a switch with VDS ≈0. Since the only current for M3 comes through M2 and from CI, the voltage across M3 eventually collapses and I3 becomes zero which causes vo1 ≈ -2.5V. From Example 8.2-5, the trip point of the second stage is 1.465V, therefore the rise time of the first stage is, tr1 = 0.2pF1.43605µ+A2.5 = 26.4ns The fall time of the second stage is found in Example 8.2-5 and is tf2 = 53.4ns. The total output fall time is ∴ tr = tr1 + tf2 = 79.8ns Output rise time, tr: The initial states for this analysis are vo1 ≈ 2.5V and vout ≈ -2.5V. The input stage fall time is, tf1 = 0.2pF2.53-01µ.A465 = 6.9ns The output stage rise time is found by determining the best guess for VG6. Since VG6 is going from 1.465 to –2.5V, let us approximate VG6 as VG6 ≈ 0.5(1.465-2.5) = -0.5175 ⇒ VSG6 = 2.5-(-0.5175) = 3.0175V ∴ I6 = 12KP'WL66(VSG6-|VTP|)2 = 0.5·50x10-6·38(3.0175-0.7)2 = 5102µA tr2 = 5pF5102µA2.-5234µA = 2.6ns The total output rise time is, ∴ tr = tf1 + tr2 = 9.5ns The propagation time delay of the comparator is, tp = tr + tr = 44.7ns CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-11 Problem 8.2-09 Repeat Ex. 8.3-5 using the two-stage op amp designed in Ex. 6.3-1 if the compensation capacitor is removed. Solution Let us assume the initial states as VG2 = −2.5 V Vo1 = 2.5 V Vout = −2.5 V and, CI = 0.2 pF For the rising edge of the input, VG2 = 2.5 V VTRP 2 = VDD − VT 6 + 2I7 K ' P S6 → VTRP2 = 1.6 V Thus, t fo1 = (0.2 p) (0.9V ) (30 µ) = 6 ns The minimum value of VG6 is VG6 ≅ −VGS2 = −1 V Average value of VG6 is VG 6 = − 1+ 1.6 2 = 0.3 V ( ) Thus, I6 = K ’ P S 6 2 VSG6 − VT 6 2 → So, tr,out = (5p)(1(.562−87(−.52µ.5))) = 2.36 ns I6 = 5.2875 mA Thus, total propagation delay for the rising input is t p1 = 8.36 ns For the falling edge of the input, VG2 = −2.5 V tro1 = (0.2 p )(1.6 − (− 2.5)) (30 µ ) = 27.3 ns and, t f ,out = (5 p)((925.5µ)) = 131.6 ns Thus, total propagation delay for the falling input is t p2 = 158.9 ns The average propagation delay is 83.63 ns. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 8.2-10 Repeat Ex. 8.2-6 if the propagation time is tp = 25ns. Solution Given, t p = 25 ns Let, m = 1, k = 10 or, p1 = p2 = 1 = 12.65 Mrad/s t p mk I6 = I7 = p2 C II (λ P + λN )= 752 µA or, W L 6 = 2I 6 K ’ P (Vdsat 6 )2 = 120 and, W L 7 = 2I7 K ’ N (Vdsat7 )2 = 55 Now, Av2 = 44.4 , and for Av = 4000 , we have Av1 = 90.11 In order to satisfy the propagation delay from the first stage, let us assume I1 = 40 µA The corresponding propagation delay of the first stage becomes t p1 = CI (VOH − VOL 2I 2 ) = 10 ns Now, gm1 = Av1(λP + λN )I1 or, gm1 = 324.4 µS or, W = W = 12 L 1 L 2 Also, VIC (min) = −1.25 V, and VGS1 = 0.946 V. Thus, Vdsat5 = 0.304 V or, W = 16 L 5 Assuming a VSG3 = 1.2V gives, W3 W4 L3 = L4 40 = 50(1.2-0.7)2 ≈ 4 Page 8-12 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-13 Problem 8.2-11 Design a comparator given the following requirements: Pdiss < 2 mW, VDD = 3 V, VSS = 0 V Cload = 3 pF, tprop < 1 µs, input CMR = 1.5 − 2.5 V, Av0 > 2200, and output voltage swing within 1.5 volts of either rail. Use Tables 3.1-2 and 3.3-1 with the following exceptions: λ = 0.04 for a 5 µm device length. Solution The ICMR is given as 1.5-2.5 V. Let us assume that W = W = 3 L 1 L 2 and I5 = 30 µA Considering the minimum input common-mode range VIC (min) = VSS + VT1(max) + Vdsat1 + Vdsat5 or, Vdsat5 = 0.35 V → W = 4.5 L 1 Considering the maximum input common-mode range VIC (max) = VDD + VT1(min) − VT 3(max) − Vdsat3 or, Vdsat5 = 0.2 V → W = W = 15 L 3 L 4 Let us assume W L 7 = 31.5 and I7 = 210 µA From proper mirroring of the bias currents, we get W = 210 L 6 The value of Cgs6 ≅ 348 fF. Thus, let us assume CI = 0.5 pF. The small-signal gain for this comparator is 8189 V/V. The total power dissipation is 0.81 mW. The trip point of the second stage is VTRP2 = 2.1 V For the rising edge of the input, referring to the procedure in Example 8.2-5, the propagation delay can be calculated as t fo1 = 15 ns, tr,out = 2.4 ns, and the total propagation delay t p1 = 17.4 ns For the falling edge of the input, the propagation delay can be found as tro1 = 35 ns, t f ,out = 21.4 ns, and the total propagation delayt p2 = 56.4 ns The average propagation delay is 36.9 ns, which is well below 1000 ns. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-14 Problem 8.3-01 Assume that the dc current in M5 of Fig. 8.3-1 is 100µA. If W6/L6 = 5(W4/L4) and W10/L10 = 5(W3/L3), what is the propagation time delay of this comparator if CL = 10pF and VDD = -VSS = 2V? Solution The quiescent bias currents are I6 = I7 = 250 µA Under large-signal swing conditions, the maximum sourcing and sinking currents are I6(max) = 500 µA I7(max) = 500 µA Thus, the propagation delay can be given by tp = CL 0.5(VDD − VSS IL ) or, tp = (10p) 0.5(2) (500 µ) or, tp = 20 ns CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 8-15 Problem 8.3-02 If the folded-cascode op amp shown having a small-signal voltage gain of 7464V/V is used as a comparator, find the dominant pole if CL = 5pF. If the input step is 10mV, determine whether the response is linear or slewing and find the propagation delay time. Assume the parameters of the NMOS transistors are KN’=110V/µA2, VTN = 0.7V, λN=0.04V-1 and for the PMOS transistors are KP’=110V/µA2, VTP = 0.7V, λP=0.04V-1. + 2.5V VBias 80µm/1µm - 80µm/1µm M4 I4 = 125µA M5 I5 = 125µA I1 I2 M6 M7 80µm/1µm 80µm/1µm + vin M1 36µm M2 1.3V 1µm I6 R2= - 2kΩ M8 M3 I3 = 100µA + 36µm 1µm M10 VBias - 36µm/1µm I7 I9 M9 vout CL 36µm/1µm M11 36µm/1µm -2.5V S02FEP1 Solution VOH and VOL can be found from many approaches. The easiest is simply to assume that VOH and VOL are 2.5V and –2.5V, respectively. However, no matter what the input, the values of VOH and VOL will be in the following range, (VDD-2VON)< VOH < VDD and VDD < VOH < (VSS+2VON) The reasoning is as follows, suppose Vin >0. This gives I1>I2 which gives I60). Assuming φ1 C2 that C2 is uncharged, find an expression for the VO output voltage, Vout, after the φ1 clock is + - applied. Assume that rise and fall times of the φ1 Vin C1 clock are slow enough so that the channel of the NMOS transistor switch tracks the gate voltage. - + The on and off voltages of φ1 are 10V and 0V, respectively. Evaluate the dc offset at the output if the various parameters for this problem are VT = 1V, Cgs = Cgd = 100fF, C1 = 5pF, and C2 = 1pF. Figure P9.2-8 Solution Since the problem does not give the value of Vin or the slope of the gate voltage, we shall assume that the contribution to the feedthrough due to the channel can be neglected. Therefore, the output voltage after the switch opens up can be expressed as, Vo = - C1 C2 Vin - Cgd Cgd + C1 (VT) = -5Vin - 1 11 1 = -5Vin - 11 The dc offset is 1/11V or 91mV. A closer look at the problem reveals that there will also be feedthrough during the turn-on part of the φ1 clock which should be considered. However, if we are going to consider this then we should also consider Vin how C1 was charged. It is most likely the complete circuit looks like the one shown. φ2 φ1 C1 When φ2 is turned off, the voltage across C1 is, VC1(φ2 off) = Vin - Cgd Cgd + C1 (Vin+VT) = Vin - 1 11 Vin - 1 11 C2 Vo + Fig. S9.2-08 When φ1turns on, the voltage across C1 is, VC1(φ1 on) = VC1(φ2 off) + Cgd Cgd + C1 (VT) = Vin - 1 11 Vin - 1 11 + 1 11 1 = Vin - 11 Vin Finally, when φ1turns off, the voltage across C1 is, VC1(φ1 off) = -5VC1(φ1 on) - Cgd Cgd + C1 (VT) = 5Vin - 5 11 Vin - 1 11 51 1 = - 11 Vin - 11 The dc offset is still the same as above. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-12 Problem 9.2-09 A switched-capacitor amplifier is shown. What is the φ1 CcCCCφ2C maximum clock frequency that would permit the ideal output + voltage to be reached to within 1% if the op amp has a dc gain vv111((tt)) v φ2 φ1 of 10,000 and a single dominant - pole at -100 rads/sec.? Assume ideal switches. Solution Figure P9.2-9 φ1 Cφ C v2(t) v2(t) Model at t=0+ for the φ2 phase: 104 106 where A = s ≈s 100 + 1 if ω >> 100. C C v1 + v-i Avi + vo - S9.2-12 Vo(s) = AVi(s) = A+V12(s) - Vo(s) 2 → Vo(s)1 + A 2 = A 2 V1(a) A 1 1 2 2 2 0.5x106 ∴ Vo(s) = A V1(a) = 1+ 2 1 1 V1(a) ≈ A+ 2 s 106 + 1 V1(a) = s+0.5x106 V1(a) 2 vo(t) = L-1s+00.5.5xx11006 6·Vs1 = A s B + s+0.5x106 0.5x106 | 0.5x106 | A = s+0.5x106V1 s=0 = V1 and B = s V1 s=0.5x106 = -V1 ∴ vo(t) = V1[1-e-0.5x106t] Let t = T correspond to vo(T) = 0.99V1 ∴ 0.99V1 = V1[1-e-0.5x106T] → 100 = e0.5x106T ln(100) = 0.5x106T → T = 2x10-6ln(100) = 9.21µs Assuming a square wave, T would be half the period so the minimum clock frequency would be 2 fclock(min) = T = 54.287kHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-13 Problem 9.2-10 The switched capacitor circuit in Fig. 9.2-9 is an amplifier that avoids shorting the output of the op amp to ground during the φ1 phase period. Use the clock scheme shown along with the timing and find the z-domain transfer function, Hoo(z). Sketch the magnitude and phase shift of this amplifier from zero frequency to the clock frequency, fc. φ2 φ1 C2 vin C1 φ1 φ2 C2 - φ2 φ1 + vout t n- 3 2 n-1 n- 1 2 n n+21 n+1 T Solution Fig. P9.2-13 φ1: (n-1) ≤ t/T < (n-0.5) o o o o vc1(n-1) = vin(n-1) and vc2(n-1) = vout(n-1) φ2: (n-0.5) ≤ t/T < (n) e o C1 o C2 o vout(n-0.5) = vout(n-1) + C2 vin(n-1) - C2 vout(n-1) or e C1 o vout(n-0.5) = C2 vin(n-1) voout(n-1) C2 + - C1 voout(n-1) -+ - +vion(n-1) + voeut(n-1) C2 φ1: (n) ≤ t/T < (n+0.5) o e C1 o vout(n) = vout(n-1) = C2 vin(n-1) → o Vout(z) =z-1 C1 C2 o Vin(z) → Hoo(z) = C1 C2 z-1 Substitituting z-1 by e-jωT gives Hoo(ejωT) = C1 C2 e-jωT The magnitude and phase response is given below. Magnitude C1/C2 Phase Shift 0 fc 0 0 0 fc f -360° CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-14 Problem 9.2-11 (a.) Give a schematic drawing of a switched capacitor realization of a voltage amplifier having a gain of Hoo = +10V/V using a two-phase nonoverlapping clock. Assume that the input is sampled on the φ1 and held during φ2. Use op amps, capacitors, and switches with φ1 or φ2 indicating the phase the switch is closed. (b.) Give a schematic of the circuit in (a.) that reduces the number of switches to a minimum number with the circuit working correctly. Assume the op amp is ideal. (c.) Convert the circuit of (a.) to a differential implementation using the differential-in, differential-out op amp shown in Fig. P9.2-11. -+ +- Solution a.) vin φ2 10C φ2 C vout φ1 - φ1 φ2 + Figure P9.2-11 b.) vin φ2 10C φ2 C vout - φ1 + c.) + φ2 vin φ2 F97E2S4 10C φ1 10C φ1 φ2 φ1 φ2 C -+ + +- vout C- φ2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-15 Problem 9.3-01 Over what frequency range will the integrator of Ex. 9.3-1 have a ±1° phase error? Solution Assuming the integrator frequency response can be represented as shown below. |Vout(jω)/Vin(jω)| Arg[Vout(jω)/Vin(jω)] Avd(0) dB Eq. (1) Eq. (3) 180° 135° ωI 10Avd(0) 10ωI Avd(0) GB 0 dB ωx1 =Avωd(I0)ωI ωx2 = GB 90° log10ω 45° 0° Eq. (2) ωI Avd(0) 10 10GB GB log10ω The integrator phase error on the low side of the useful band is given as, Error = 90° - tan-1ωI/AωvLd(0) = 1° → ωL = 57.29 ωI Avd(0) The integrator phase error on the high side of the useful band is given as, Error = tan-1 ωGHB = 1° GB → ωH = 57.29 If Avd(0), ωI, and GB are given, the useful range is from ωL to ωH. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-16 Problem 9.3-02 Show how Eq. (9.3-12) is developed from Fig. 9.3-4(b.). vin 2 vC1(t) 2 Solution S1 C1 S4 S2 S3 1 1 - vC2+ vout - C2 + Fig. 9.3-4(b.) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-17 Problem 9.3-03 Find the Heo(jωT) transfer function for the inverting integrator of Fig. 9.3-4b and compare vin 2 vC1(t) 2 with the Hee(jωT) transfer function. S1 C1 S4 Solution S2 S3 1 1 - vC2+ vout - C2 + Fig. 9.3-4(b.) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-18 Problem 9.3-04 An inverting, switched-capacitor integrator is shown. If the gain of the op amp is Ao, find the z-domain transfer function of this integrator. Identify the ideal part of the + transfer function and the part due to the finite op amp gain, Ao. Find an expression for the excess phase due to Ao. Vin - φ1 C1 φ2 vo Ao + C2 - vC2+ + VO Solution Let us use charge conservation to solve the problem. Figure P9.3-4 C2vC2(nT) = C2vC2[(n-1)T] – C1[vin (n-1)T + vo(nT)/Ao] or VC2(z) = z-1VC2(z) - C1 C2 z-1Vin(z) - C1 C2 Vo(z) Ao VC2(z)[1- z-1] = -α z-1Vin(z) - αVAo(oz) , where α = C1 C2 -α z-1 -α/Ao VC2(z) = 1- z-1 Vin(z) - 1- z-1 Vo(z) ∴ Vo(z) -α z-1 -α/Ao Vo(z) 1- z-1 Vo(z) = VC2(z) - Ao = 1- z-1 Vin(z) - 1- z-1 Vo(z) - Ao x 1- z-1 Vo(z)1 - z-1 + α Ao + 1 - zAo 1 = -α z-1Vin(z) ∴ H(z) = Vo(z) Vin(z) = 1- z-1 -α z-1 1+α - + Ao z-1 = -α 1- z- 1 z - 1 1 1+α - z-1 1 + Ao(1- z-1) The first bracket is the ideal term and the second bracket is the term due to Ao. To evaluate the excess phase due to Ao we replace z by ejωT. H(ejωT) = 1 1+α - z-1 = 1 (1+α) ejωT/2 ejωT/2 1 + Ao(1- z-1) 1 + Ao(ejωT/2- e-jωT/2) + Ao(ejωT/2- e-jωT/2) 1 = 1 - j 12+Aαo cos(ωTs/i2n)(ω+ Tjs/2in) (ωT/2) + j 2Ao cos(ωT/2) + jsin(ωT/2) sin(ωT/2) = 2+α 1 + Ao - 1 α → j 2Ao cot(ωT/2) Arg[H(ejωT)] = -tan-12αA1o cot(ωT/2) 2+α + Ao ∴ Excess phase = -tan-1 2 α cot(ωT/2) Ao + 4 + 2α ≈ -tan-1 2Ao α tan(ωT/2) α ≈ - 2Ao tan(ωT/2) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-19 Problem 9.3-05 For the switched-capacitor circuit shown o o find VOUT(z) as a function of V1(z), o o V2(z) , and V3(z) assuming the clock is a two-phase, nonoverlapping clock. Assume that the clock frequency is much greater than the signal bandwidth and find an approximate expression for Vout(s) in terms of V1(s), V2(s), and V3(s). Assume that the inputs are sampled and held where necessary. C1 φ2 C2 vout φ1 φ2 φ1 - +++ A1 v1 v2 v3 + --- φ2 φ1 φ2 φ1 φ2 φ1 t n- 3 n-1 n- 1 2 2 n n+ 1 2 n+1 n+ 3 2 T S02E2P4 Solution φ1, t = (n-1)T: Model: -voout(n-1+) v 1o(n-1) C1 v 3o(n-1) + C2 + voout(n-1) - φ2, t = (n-0.5)T: Model: v e out (n-0.5) = voout (n-1) - C1 C2 ve2 (n-0.5) - C1 C2 vo1 (n-1) + C1 C2 vo3 (n-1) S02E2S4A vo1(n-1)+-v3o(n--1-) voout(n-1) + v2e(n-0.5) C1 + C2 + voeut(n-0.5) - S02E2S4B φ1, t = (n)T: v o out (n) = voout (n-1) - C1 C2 ve2 (n-0.5) + C1 C2 vo1 (n-1) - C1 C2 vo3 (n-1) ∴ V o out (z) = z-1Voout (n-1) - z-0.5CC12 Ve2 (z) + z-1CC12 Vo1 (z) - z-1CC12 Vo3 (z) Replacing Ve2 (z) by z-0.5Vo2 (z) gives V o out (z) = z-1Voout (n-1) - z-1CC12 Vo2 (z) + z-1CC12 Vo1 (z) - z-1CC12 Vo3 (z) V o out (z) = - z-1 1-z-1 [-Vo1 (z) + Vo2 (z) + Vo3 (z)] Replacing 1- z-1 by sT and z-1 by 1 gives, V o out (s) = - 1 sT [-Vo1 (s) + Vo2 (s) + Vo3 (s)] ∴ V o ou t (s) = 1 sT [V o 1 (s) - V o 2 (s) - V o 3 (s)] CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-20 Problem 9.3-06 The switched capacitor circuit shown uses a two-phase, nonoverlapping clock. (1.) Find the z-domain expression for Hoo(z). (2.) Replace z by ejωT and plot the magnitude and phase of this switched capacitor circuit from 0 Hz to the clock frequency, fc, if C1 = C3 and C2 = C4. Assume that the op amps are ideal for this problem. (3.) What is the multiplicative magnitude error and additive phase error at fc/2? C1 C2 vo1 C3 C4 vout φ1 φ2 - φ1 φ1 - vin φ2 φ1 + φ2 φ2 + Solution φ2 φ1 φ2 φ1 φ2 φ1 φ2 t n-1.5 n-1 n-0.5 n n+0.5 n+1 n+1.5 T S02FEP1 (1.) φ1 (n-1≤t/T> fsignal. If + C2 = C4 = 1000pF and fc = 10kHz, find the value of C1 and C3 to implement the vin(t) - following transfer function. Vout(s) Vin(s) = -1011ss000++ 1 1 C 2 =1000pF φ2 C 1 φ2 φ1 φ1 φ2 φ1 φ2 C 4 =1000pF φ2 C 3 φ2 φ1 φ1 φ1 φ2 φ1 Solution Write the circuit as the n- 3 n-1 2 following summing integrator and replacing with z-domain models gives: n- 1 n n+ 1 n+1 n+ 3 2 2 2 Figure P9.5-10 vout(t) t T vin C1 vin C1 φ2 φ2 φ1 φ1 vout C3 φ2 φ2 φ1 φ1 C4 vout Vin(z) C2(1-z-1) - Vin(z) + C1 Vout(z) C3 Vout(z) C4(1-z-1) + Summing currents gives, C2(1-z-1)Vin(z) + C1Vin(z) + C3Vout(z) + C4(1-z-1)Vout(z) = 0 Transforming to the s-domain by 1-z-1 ≈ -sT gives, sT C2 Vin(s) + C1Vin(s) + C3Vout(s) + sT C4 Vout(s) = 0 ∴ H(s) = Vout(s) Vin(s) = sT -sT C2+C C4+C 1 3 = - C1 C3 sT C2 C1 sT C4 C3 + 1 + 1 = -1011s0s00 + 1 +1 C1 C1 C3 Therefore, C3 = 10 , TC2 = 100 and TC4 = 10 ∴ 100C2 100·1000pF C1 = fc = 10,000 = 10pF and C3 = 1pF CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-41 Problem 9.6-01 Combine Figs. 9.6-2a and 9.6-2b to form a continuous time biquad circuit. Replace the negative resistor with an inverting op amp and find the s-domain frequency response. Compare your answer with Eq. (9.6-1). Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-42 Problem 9.6-02 (a.) Use the low-Q switched capacitor biquad circuit shown to design the capacitor ratios of a lowpass second-order filter with a pole frequency of 1kHz, Q = 5 and a gain at dc of -10 if the clock frequency is 100kHz. What is the total capacitance in terms of Cu? (b.) Find the clock frequency, fc, that keeps all capacitor ratios less than 10:1. What is the total capacitance in terms of Cu for this case? Vien(z) φ2 α1C1 φ2 φ1 φ1 α2C1 C1 e V1(z) α5C2 - φ1 φ2 + α4C2 α3C2 α6C2 φ2 φ1 φ1 C2 φ2 Voeut(z) + Design Eqs: α1 = K0T ωo , α2 = |α5| = ωoT, α3 = K2, α4 = K1T, and α6 = ωoT Q . Solution (a.) H(s) = s2 -10ωo2 + ωo Qs + ω 2 o ⇒ Ko = 10ωo2, K1 = K2 = 0, ωo = 2000π, and Q = 5 ∴ α1 = 10ωo2T ωο = 10ωoT , α2 = |α5| = ωoT, α3 = α4 = 0, and α6 = ωoT Q = ωoT 5 ωoT = 2πfo fc = 2π 100 = 0.06283 ⇒ α1 = 0.6283, α2=|α5| 0.06283, α6=0.01256 1 1 1 1 Total capacitance = 0.6283 + 0.06283 + 2 + 0.01256 + 0.06283 = 115.45Cu (b.) ωο 5fc = 0.1 ⇒ fc = 2ωo = 4000π = 12.566kHz Now, α1 = 5, α2 = |α5| = 0.5, and a6 = 0.1 1 11 Total capacitance = 5 + .5 + 1 + 0.1 + 0.5 + 1 = 21C u CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-43 Problem 9.6-03 A Tow-Thomas continuous time filter is shown. Give a discrete-time realization of this filter using strays-insensitive integrators. If the clock frequency is much greater than the filter frequencies, find the coefficients, ai and bi, of the following z-domain transfer function in terms of the capacitors of the discrete-time realization. a0 + a1z-1 + a2z-2 H(z) = b0 + b1z-1 + b2z-2 Solution The development of a discrete-time realization of the Tow- Thomas continuous time filter is shown to the right. Using z-domain vin analysis, we can solve for the desired transfer function and find the coefficients. R1 R4 C1 R - + R3 R R2 C2 - vout - + + CR3 CR1 φ1 φ2 φ2 φ1 Vin CR4 C1 φ1 φ2 - φ2 φ1 + CR2 C2 φ2 φ2 - V2 φ1 φ1 + 1 Vout(z) = 1 - z- 1 vout Fig.S9.6-3 CCR14z-1Vin(z) -CCR11z-1Vout(z) +CCR13z-1V2(z) CR2/C2 and V2(z) = - 1 - z- 1Vout(z) ∴ Vout(z) = 1 1 - z- 1 CCR14z-1Vin(z) -CCR11z-1Vout(z) CR2CR3 + C1C2 1 z-1 - z- 1Vout(z) Vout(z)(1 - z-1)2 - CR1 C1 (1 - z-1) + C R2CR C1C2 3 z-1(1 - z-1) = z-1(1 - z-1)CCR14 Vin(z) Vout(z) (z-1 - z-2)CCR14 H(z) = Vin(z) = 1 + 2z-1 + z-2 + CR1 C1 - CR1 C1 z-1 + C R2CR3 C1C2 z-1 - C R2CR3 C1C2 z-2 Equating coefficients gives, CR4 CR4 CR1 CR1 CR2CR3 CR2CR3 a0 = 0, a1 = C1 , a2 = - C1 , b0 = 1 + C1 , b1 = 2 - C1 + C1C2 and b2 = 1- C1C2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-44 Problem 9.6-04 Find the z-domain transfer function H(z) = Vout(z)/Vin(z) in the form of a2z2 + a1z + a0 H(z) = b2z2 + b1z + b0 for the switched capacitor circuit shown below. Evaluate the ai's and bi's in terms of the capacitors. Next, assume that ωT << 1 and find H(s). What type of second-order circuit is this? C2 C4 φ2 φ1 φ2 C 1 φ2 + CA φ1 C 3 φ2 CB Vout Vin φ1 φ1 A1 φ2 φ1 A2 - Figure P9.6-4 Solution V1(z) = z z-1 C1 CA Vin(z) - z z-1 C2 CA Vout(z) - C4 CA Vout(z) and Vout(z) = 1 z-1 C3 CA V1(z) Where V1(z) is the output of the first integrator. If α1A = C1/CA, α3B = C3/CB, α2A = C2/CA, and α4A = C4/CA then we can write the following. Vout(z) = αz-31B - α1Az z-1 Vin(z) - α2Az z-1 Vout(z) - α4AVout(z) ∴ Vout(z)1 + α2Aα3Bz (z-1)2 +α3Bzα-14Az = α1Aα3Bz (z-1)2 Vin(z) Vout(z) -α1Aα3Bz -α1Aα3Bz H(z) = Vin(z) = (z-1)2+α2Aα3Bz+(z-1)α3Bα4A = z2+(α2Aα3B+α3Bα4A-2)z +(1-α3Bα4A) If ωT= sT<<1, then z ≈ 1 unless there are terms like (z-1) in which case z-1 ≈ sT. Therefore, α1Aα3B C1C3 1 H(s) ≈ -α1Aα3B s2T2+sTα3Bα4A+α2Aα3B = - T2 s2+sα3BTα4A+α2Aα3B = -CACB T2 s2+ s C3C4 CBCA 1 T + C2C3 CACB This circuit is a second-order bandpass transfer function. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-45 Problem 9.6-05 Find the z-domain transfer function H(z) = Vout(z)/Vin(z) in the form of H(z) = -az22z 2+ +b a1z + a0 1z + b0 for the switched capacitor circuit shown below. Evaluate the ai's and bi's in terms of the capacitors. Next, assume that ωT << 1 and find H(s). What type of circuit is this? φ2 C1 φ2 + Vin φ1 - C3 φ1 C2 φ2 CA A1 VA φ2 φ1 C4 C5 CB Vout A2 φ2 φ1 φ1 Solution For the output voltage of the first integrator, VA, we can write, VA = f1(VA,Vin,Vout) = -C1 CA z z-1 Vin - C5 CA z z-1 C4 Vout - CA Vout Similarily for the output voltage of the second integrator, Vout, we can write, Vout = f2(VA,Vin) = C2 CB 1 z-1 VA - C3 CB Vin Combining equations gives, Vout = -z (z-1)2 C2C5 CACB Vout - z C1C2 (z-1)2 CACB Vin - 1 z-1 C2C4 CACB C3 Vout - CB Vin Vout1 + z C2C5 (z-1)2CACB + z1-1CCA2CC4B = -(z-z1)2CCA1CC2B - CC3B Vin Vout(z-1)2 + (z-1)CCA2CC4B + z C2C5 CACB = -(z-1)2 C3 CB + z C1C2 CACB Vin ∴ Vout(z) Vin(z) = z2 -CCB3 z2 + C1C2 CACB - 2 CC3Bz + C3 CB + C2(C4+C5) CACB - 2z + 1 - C2C4 CACB = -az22z+2+ba1z1z++ba00 Thus, C1C2 2 C 3 C2(C4+C5) C2C4 a2=C3/CB, a1=CACB - CB , a0=C3/CB, b1= CACB - 2 and b0= 1 - CACB CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-46 Problem 9.6-06 Find the z-domain transfer function H(z) = Vout(z)/Vin(z) in the form of H(z) = -az22z 2+ +b a1z + a0 1z + b0 for the switched capacitor circuit shown below. Evaluate the ai's and bi's in terms of the capacitors. Next, assume that ωT << 1 and find H(s). What type of circuit is this? What is the pole frequency, ωo, and pole Q? φ1 C D vin G - φ2 φ2 φ1 φ1 + E φ2 B v' A - vout φ1 φ2 φ2 φ1 + Solution V’(z) = - G D z z-1 Vin(z) - C D z z-1 Vout(z) - E D Vout(z) Vout(z) = A B V’ z-1 = A B z z-1 - G D z z-1 Vin(z) - C D z z-1 Vout(z) - E D Vout(z) AG z AC z AE Vout(z) = - BD (z-1)2 Vin(z) - BD (z-1)2 Vout(z) - BD z-1 Vout(z) 1 + AE BD 1 z-1 + AC BD z (z-1)2 = - AG BD z (z-1)2 Vin(z) AG AG ∴ Vout(z) - BD z Vin(z) = (z-1)2+ABDE(z-1)+ABDCz → Vout(z) - BD z Vin(z) = z2+ABDE +ABDC-2z+1- AE BD AG AE AC AE Thus, a2˚= a0 = 0, a1 = BD, b1 = BE + BD - 2, and b0 = 1 - BD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-47 Problem 9.6-07 The switched capacitor circuit shown below realizes the following z-domain transfer function where H(z) = -ab22zz22 + + a1z + a 0 b1z + 1 a0+a1+a2 1-(b0/b2) 1+b1+b2 C6=a2/b2, C5=(a2-a0)/b2C3, C1= b2C3 , C4= C3 and C2C3 = b2 . Design a switched capacitor realization for the function -106 H(s) = s2 + 100s + 106 where the clock frequency is 10 kHz. Use the bilinear transformation, s = (2/T)[(z-1)/(z+1)], to map H(s) to H(z). Choose C2 = C3 and assume that CA = CB = 1. C5 C " 1 C2 C4 φ2 φ1 φ2 C 1 φ2 + CA φ1 C3 φ2 CB Vout Vin φ1 φ1 A1 φ2 φ1 A2 - C 6 C " 1 Solution Apply the bilinear transformation Figure P9.6-7 s = 2 T z - 1 z+1 = 2x104zz+-11 to H(s) to get, -106 H(z) = 4x108 zz+-112+200x104zz+-11zz++11+106zz++112 -106(z2+2z+1) = 4x108(z2-2z+1)+2x106(z2-1)+106(z2+2z+1) -(106z2+2x106z+106) = (4x108+2x106+106)z2+(-8x108+2x106)z+(4x108-2x106+106) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-48 Problem 9.6-07 - Continued -(106z2+2x106z+106) -(0.002506z2+0.005013z+0.002506) = 4.03x108z2-7.98x108z+3.99x108 = 1.010025z2-2.0000z+1 Now equating to the coefficients, a2 0.002506 a2-a0 C6 = b2 = 1.010025 = 0.002481, C5 = b2C3 = 0, 1+b1+b2 1+(-2)+1.010025 C2C3 = b2 = 1.010025 = 0.009925 ⇒ C2 =C3 = 0.099627 a0+b1+b2 0.002506+0.005013+0.002506 C1 = b2C3 = 1.010025·0.0099627 = 0.099633 1+(b0/b2) 1-(1/1.010025) C4 = C3 = 0.099627 = 0.099627 ∴ C1=0.099633, C2=C3=0.099627, C4=0.099627, C5=0, C6= 0.002481 Cmax/Cmin = 1/0.002625 = 403.06 Normalize all capacitors by 0.002625 to get ΣCµ = [(403.6)2+(37.953)2+37.953+37.955+1] = 958.9Cµ CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-49 Problem 9.7-01 Find the minimum order of a Butterworth and Chebyshev filter approximation to a filter with the specifications of TPB = -3dB, TSB = -40dB, and Ωn = 2.0. Solution For the Butterworth approximation, use Eq. (9.7-7) and for the Chebyshev approximation use Eq. (9.7-12), both with ε = 1. The results are shown below. Ν TSB(dB) = -10log10(1+22N) 1 -6.99 dB TSB(dB) = -10log10[1+cosh2(Ncosh-12)] -6.99 dB 2 -12.30 dB -16.99 dB 3 -18.13 dB -28.31 dB 4 -24.10 dB -39.74 dB 5 -30.11 dB -51.17 dB 6 -36.12 dB 7 -42.14 dB The minimum order for the Butterworth is 7 while the minimum order for the Chebyshev i 5 and in many cases 4 would work. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-50 Problem 9.7-02 Find the transfer function of a fifth-order, Butterworth filter approximation expressed as products of first- and second-order terms. Find the pole frequency, ωp and the Q for each second-order term. Solution From Table 9.7-1 we get, 1 T(s) = (s+1)(s2+0.61804s+1)(s2+1.84776s+1) The pole frequency and Q for a general second order term of (s2+a1s+1) is 1 ωp = 1 and Q = a1 For both second order terms, the pole frequency is 1 radian/sec. For the first second-order term, the Q = 1.61804. For the second, second-order term, the Q = 0.541196. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-51 Problem 9.7-03 Redesign the second stage of Ex. 9.7-5 using the high-Q biquad and find the total capacitance required for this stage. Compare with the example. Solution 0.9883 Tn2(sn) = sn2 + 0.1789sn + 0.9883 ⇒ ωn2 = 0.9941 and Q2 = 5.557 For the lowpass high-Q biquad, K1 = K2 = 0 ⇒ α32 = α62 = 0 and K0 = ωn22 ∴ α22 = |α52| = ωn2Tn = ωPB 0.9941 fc = 0.3123 α12 = ωn22Tn ωn2 = ωn2Tn = 0.3123 1 α42 = Q = 0.1800 Schematic of the second-stage: α22C12 α42C2 Vien(z) α12C12 C12 e V1(z) α25C22 φ2 φ1 φ2 φ1 - φ1 φ2 φ1 φ2 + φ2 φ1 C22 Voeut(z) + Total capacitance is: Figure S9.7-03 ΣC = 1 + 2(0.3123) 0.1880 + 1 0.1800 + 1 + 1 0.3123 = 10.027+4.202 = 14.229Cµ Note that this value is 17.32 when a low-Q stage is used. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-52 Problem 9.7-04 Design a cascaded, switched capacitor, 5th-order, lowpass filter using the cascaded approach based on the following lowpass, normalized prototype transfer function. 1 Hlpn(sn) = (sn+1)(sn2+0.61804sn+1)(sn2+1.61804sn+1) The passband of the filter is to 1000Hz. Use a clock frequency of 100kHz and design each stage giving the capacitor ratios as a function of the integrating capacitor (the unswitched feedback capacitor around the op amp), the maximum capacitor ratio, and the units of normalized capacitance, Cu. Give a schematic of your realization connecting your lowest Q stages first. Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution Stage 1, First-Order Stage (Use Fig. 9.5-1): α11/α21 1 T1(sn) = (snTn/α21) +1 = sn+1 ⇒ α11 = α21 and α21 = Tn α11 = α21 = Tn = ωPB fc 2000π = 100,000 = 0.06283 Cmax 1 Cmin = 0.06283 = 15.92 1 and ΣC = 2 + 0.06283 = 19.92Cµ Stage 2, Second-order Stage (Use Low-Q Lowpass Biquad): 1 T2(sn) = sn2+1.61804sn+1 ⇒ ωn2 = 1 rad/sec and Q2 = 0.61804 From the low-Q biquad relationships, K1 = K2 = 0 ⇒ α32 = α42 = 0 α22 = |α52| = ωnTn = 0.06283 Cmax 1 Cmin = 0.1017 = 9.837 and α62 = ωnTn Q2 0.06283 = 0.61804 = 0.1017 and ΣC = 2 + 1 0.06283 + 1 0.06283 + 0.1017 0.06283 + 1 = 36.45Cµ Stage 3, Second-order Stage (Use Low-Q Lowpass Biquad): 1 T3(sn) = sn2+0.61804sn+1 ⇒ ωn2 = 1 rad/sec and Q2 = 1.6180 From the low-Q biquad relationships, K1 = K2 = 0 ⇒ α33 = α43 = 0 α23 = |α53| = ωnTn = 0.06283 Cmax 1 Cmin = 0.0391 = 25.59 and α62 = ωnTn Q2 0.06283 = 1.6180 = 0.0391 and ΣC = 2 + 1 0.06283 + 1 0.0391 + 0.06283 0.0391 + 1 = 46.10Cµ CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-53 Problem 9.7-04 – Continued Schematic: α21C11 Vin α11C11 C11 φ1 φ2 φ2 φ1 + φ2 α12C12 φ1 φ2 φ2 φ1 φ1 C12 + α62C22 α52C22 φ1 φ2 φ2 φ1 α22C22 φ1 C22 φ2 + α13C13 φ2 φ2 φ1 φ1 C13 + α63C23 α53C23 φ1 φ2 φ2 φ1 α23C23 φ1 C23 φ2 - Vout + Fig. S9.7-4A SPICE File: *** HW9 PROBLEM2 (Problem 9.7-4) *** *** Node 21 and 22 are outputs VIN 1 0 DC 0 AC 1 *** STAGE1 *** XNC11 1 2 3 4 NC1 XUSCP11 3 4 5 6 USCP XPC21 5 6 3 4 PC1 XAMP11 3 4 5 6 AMP *** STAGE2 *** XPC12 5 6 7 8 PC1 XUSCP12 7 8 9 10 USCP XPC22 7 8 13 14 PC1 XAMP12 7 8 9 10 AMP XNC52 9 10 11 12 NC1 XUSCP22 11 12 13 14 USCP XPC62 11 12 13 14 PC2 XAMP22 11 12 13 14 AMP *** STAGE3 *** XPC13 13 14 15 16 PC1 XPC23 15 16 21 22 PC1 XUSCP43 15 16 21 22 USCP1 XUSCP13 15 16 17 18 USCP XAMP13 15 16 17 18 AMP XNC53 17 18 19 20 NC1 XUSCP23 19 20 21 22 USCP XAMP23 19 20 21 22 AMP *** SUB CIRCUITS *** .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=5US RDO 3 0 1K .ENDS DELAY CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-54 Problem 9.7-05 Repeat Problem 9.7-3 for a 5th-order, highpass filter having the same passband frequency. Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-55 Problem 9.7-06 Repeat Problem 9.7-3 for a 5th-order, bandpass filter having center frequency of 1000Hz and a -3dB bandwidth of 500Hz. Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-56 Problem 9.7-07 Design a switched capacitor 6th-order, bandpass filter using the cascaded approach and based on the following lowpass, normalized prototype transfer function. 2 Hlpn(sn) = (sn+1)(sn2+2sn+2) The center frequency of the bandpass filter is to be 1000Hz with a bandwidth of 100Hz. Use a clock frequency of 100kHz. Design each stage given the capacitor ratios as a function of the integrating capacitor (the unswitched feedback capacitor around the op amp), the maximum capacitor ratio and the units of normalized capacitance, Cu. Give a schematic of your realization connecting your lowest Q stages first. Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-57 Problem 9.7-08 Design a switched capacitor, third-order, highpass filter based on the lowpass normalized prototype transfer function of Problem 9.7-7. The cutoff frequency (fPB), is to be 1000Hz. Design each stage given the capacitor ratios as a function of the integrating capacitor (the unswitched feedback capacitor around the op amp), the maximum capacitor ratio and the units of normalized capacitance, Cu. Give a schematic of your realization connecting your lowest Q stages first. Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-58 Problem 9.7-09 Design a switched capacitor, third-order, highpass filter based on the following lowpass, normalized prototype transfer function. 0.5(sn2+4) Hlpn(sn) = (sn+1)(sn2+2sn+2) The cutoff frequency (fPB), is to be 1000Hz. Use a clock frequency of 100kHz. Design each stage given the capacitor ratios as a function of the integrating capacitor (the unswitched feedback capacitor around the op amp), the maximum capacitor ratio and the units of normalized capacitance, Cu. Give a schematic of your realization connecting your lowest Q stages first. Use the low-Q biquad given below for the second-order stage. The approximate s-domain transfer function for the low-Q biquad is, -α 3 s n 2 + snα4 Tn + α1α5 Tn2 Hee(sn) = sn2 + snα6 Tn + α2α5 Tn2 α2C1 Vien(z) φ2 α1C1 φ2 φ1 φ1 C1 e V1(z) α5C2 - φ1 φ2 + α4C2 α3C2 α6C2 φ2 φ1 φ1 C2 φ2 Voeut(z) + Solution Low Q, switched capacitor, biquad realization. Perform a normalized lowpass to normalized highpass transformation: Hhpn(sn) = 1 sn 0.5s1n2 + 4 + 1s1n2 + 2 sn + 2 0.5sn(4sn2+1) = (sn+1)(1+2sn+2sn2) = sns+n 1 sn2+0.25 sn2+sn+0. 5 First-order stage design: Equating currents at the inverting input of the op amp gives, α11(1-z-1)Vien (z) + α21Voe1 (z) + (1-z-1)Voe1 (z) = 0 Solving for the Hee(z) tranfer function gives, Vin α21C11 α11C11 φ2 φ1 φ1 φ2 Vo1 - C11 + S01E3S1A CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-59 Problem 9.7-09 - Continued Hee(z) = e Vo1(z) e Vin(z) | = -α11(1-z-1) α21 + (1-z-1) → Hee(sn) ≈ e Vo1(sn) e Vin(sn) | = -α11snTn α21+snTn = -α11sn α21 sn+ Tn Equating with the normalized highpass transfer function gives, α11 = 1 and α21 = Tn = ωPB fc = 2000π 100,000 = 0.06283 2 ΣCµ = 0.06283 + 1 = 32.832Cµ Next, consider the second-order stage design: Equating Hee(s) with sn2+0.25 sn2+sn+0. 5 gives, α32 = 1, α42 = 0, α12α52 = 0.25Tn2, α62=Tn = 2000π 100,000 = 0.06823 and α22α52 = Tn2 2 Let α22 = α52, then α22 = α52 = Tn = 2 ωPB 2fc = 2000π = 0.04443 2 100,000 Therefore, α12 = Tn2 4α52 = 2Tn 4 = 0.02221 ΣCµ = 1+ 0.04443 0.2221 + 1 0.02221 + 1+ 0.06283 0.04443 + 2 0.04443 = 48.025+47.4287 Total ΣCµ = 32.832 + 48.025 + 47.429 = 127.84Cµ Cmax/Cmin = 1/0.02221 = 45.025 Filter schematic: α21C11 α11C11 φ2 φ1 φ1 φ2 Vo1 - C11 Vin + α12C12 φ2 φ1 φ2 φ1 C12 + α22C12 e V1(z) α52C22 φ1 φ2 φ1 α62C22 φ2 α32C22 φ1 C22 φ2 Voeut(z) + S01E3S1B CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 9.7-09 – Continued .SUBCKT NC1 1 2 3 4 RNC1 1 0 15.916 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.06283 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.06283 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.06283 RNC2 4 0 15.916 .ENDS NC1 .SUBCKT PC1 1 2 3 4 RPC1 2 4 15.916 .ENDS PC1 .SUBCKT PC2 1 2 3 4 RPC1 2 4 9.8328 .ENDS PC2 .SUBCKT USCP 1 2 3 4 R1 1 3 1 R2 2 4 1 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 1 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 1 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 .ENDS USCP .SUBCKT USCP1 1 2 3 4 R1 1 3 1.6181 R2 2 4 1.6181 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 0.6180 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 0.6180 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 0.6180 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 0.6180 .ENDS USCP1 .SUBCKT AMP 1 2 3 4 EODD 0 3 1 0 1E6 EVEN 0 4 2 0 1E6 .ENDS AMP *** ANALYSIS *** .AC DEC 1000 10 99K .PROBE .END Page 9-60 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-61 Problem 9.7-10 Write the minimum set of state equations for each of the circuits shown below. Use voltage analogs of current (R=1Ω). The state equations should be in the form of the state variable equal to other state variables, including itself. Solution (a) V1 = 1 snC1n Vin R0n - V1 R0n - V 2 ' R0n I2 1 V2’ = snL2n (V1 - Vout) Vin Vout = 1 snC3n V2' Vout - R4n - V1 R0n + L2n + C1n V1 - C3n R4n Vout - Fig. S9.7-10A 1 ∴ V1’ = 1 [ V1 – snL1bn + snC1n Vout] sn L1bn = sn 2 + 1 [ V1 – Vout] L1bn C1bn Vin I1 L2bn C2bn + Vout R3n - Fig. S9.7-10B sn Vout 1 = snC2bn + 1 V1’-VRo4unt snL2bn = C2bn sn2 + 1 V1’-VRo4unt ∴ The simplest way to work this one is make the following transformation (see pp. 228-230 of Switched Capacitor Circuits, P.E. Allen and E.S. Sanchez, Van Nostrand Reinhold,1984). L2n R0n R0n I2 V1 L2n + + C1n+C2n C2n+C3n Vin C1n C2n C3n R3n Vout - Vin C2n Vout C2n V1 R3n Vout C1n+C2n C2n+C3n - Fig. S9.7-10C V1 = 1 sn(C1n + C2n) Vin R0n - V1 R0n - V 2 ' + C2n C1n+ C2n Vout 1 V2’ = snL2n (V1 - Vout) Vout = 1 sn(C2n + C3n) V2' -VRo3unt + C2n C2n+ C3n Vout CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-62 Problem 9.7-11 Give a continuous time and switched capacitor implementation of the following state equations. Use minimum number of components and show the values of the capacitors and the phasing of each switch (φ1 and φ2). Give capacitor values in terms of the parameters of the state equations and Ωn and fc for the switched capacitor implementations. 1 1.) V1 = sK [ -α1V1 + α2V2 - α3V3] s 2.) V1 = s2+1 [ -α1V1 + α2V2 - α3V3] 1 ∴ V1 = sK[ -α1V1 + α2V2] + α3V3 Solution 1.) V1 V2 R V3 R1=1/α1 R R2=1/α2 - C = K V1 + - R3=1/α3 + Fig. S9.7-11A V1 a1C C V1 φ2 φ2 φ1 V2 a2C + φ1 φ2 a1 = α1Tn K V3 a3C φ2 φ1 φ1 a2 = α2Tn K a3 = α3Tn K 2.) C = 1 R=1 R - - + + R3= V3 1/α3 V2 R R R=1 R1=1/α1 R R2=1/α2 C = 1 V1 - - + + V1 a1C C=1 V1 φ2 φ1 V2 a2C φ2 φ2 φ1 + φ1 φ2 φ1 φ2 TnC C = 1 TnC V3 a3C φ2 φ2 φ1 φ1 φ1 φ2 φ1 + - Fig. S9.7-11B a1 = α1Tn a2 = α2Tn a3 = α3Tn CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-63 Problem 9.7-11 - Continued 3.) V1 V2 R V3 R R1=1/α1 R R2=1/α2 - + C3= R 1/α3 C = K V1 - + - + V3 C C a3C - + V1 a1C φ1 φ2 φ2 V2 a2C φ2 φ1 φ1 C V1 - + a1 = α1Tn K a2 = α2Tn K a3 = α3 Fig. S9.7-11C CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-64 Problem 9.7-12 Find a switched capacitor, realization of the low-pass normalized RLC ladder R0n=1Ω L1n=1H L3n=2H filter shown. The cutoff frequency of the low-pass filter is 1000Hz and the clock frequency is 100kHz. Give the Vin(sn) value of all capacitors in terms of the integrating capacitor of each stage and C2n = 2F + R4n =1Ω Vout(sn) - show the correct phasing of switches. Figure P9.7-12 What is the Cmax/Cmin and the total units of capacitance for this filter? Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution The state equations are: Vs = I1Ron+sL1nI1+V2 → I1 = 1 sL1n V s - RI1Ron R -V2 → V1’= sLR1nV s V 1'R on -R -V 2 1 I1- I3 = sC2nV2 → V1’ -V3’ = sRC2nV2 → V 2 = sRC2n(V1’ -V3’) V2 = sL3n I3 + I3R4n → 1 I3 = sL3n (V2 - I3R4n) → V3’ = R sL3n V 2 - R4n R V 3' R4n But, Vout = I3R4n = V3’ R R → V3’ = R4n Vout → R4n V out = sL3n (V 2 -V out) Normalized realizations: Vs α11C1 φ1 φ2 φ2 V1' α21C1 φ2 φ1 V2 α31C1 φ2 φ1 φ1 V1' α12C2 φ1 φ2 φ2 Vout α22C2 φ2 φ1 φ1 C1 V1' + 1 V1’ ≈ sTn [α11Vs - α21V1’ - α31V2] Comparing with the first state equation: α11 R Tn = L1n → α11 = RTn L1n RΩn 1·2000π = fcL1n = 105·1 α11 = π/50 = 0.0628 = α21 Fig. S9.7-12B C2 V2 α31 Ron Tn = L1n → α31 = RonΩn fcL1n = α11 = 0.0628 1 V2 ≈ sTn [α12V1’ - α22Vout] - Comparing with the second state equation: + α12 1 Tn = RC2n → α12 = Tn RC2n Ωn = RfcC2n = 1·2000π Fig. S9.7-12C 1·2·105 α12 = π/100 = 0.0314 = α22 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-65 Problem 9.7-12 – Continued V2 α13C3 φ1 φ2 φ2 Vout α23C3 φ2 φ1 φ1 C3 Vout + Fig. S9.7-12D 1 Vout ≈ sTn [α13V2 - α23Vout] Comparing with the third state equation: α13 1 Tn = R4nL3n α13 = Tn R4nL3n = Ωn R4nfcL3n = 1·2000π 1·105 α13 = π/50 = 0.0628 = α23 Connect the above three circuits together to get the resulting filter. The Cmax/Cmin = 1/α12 = 31.83. The units of capacitances normalized to each integrating capacitor is 3 + (1/0.0628) = 18.91 for the first stage, 2 + (1/0.0314) = 33.83 for the second stage and 2 + (1/0.0628) = 17.91for the third stage. The total units of capacitance for this filter is 70.66 units. The SPICE simulation file for this filter is shown below. SPICE File for Problem 9.7-12 *** Node 13 and 14 are Switched Cap outputs *** Node 23 is RLC ladder network output VIN 1 0 DC 0 AC 1 *** V1' STAGE *** XNC11 1 2 3 4 NC1 XPC21 9 10 3 4 PC1 XPC31 5 6 3 4 PC1 XUSCP1 3 4 5 6 USCP XAMP1 3 4 5 6 AMP *** V2 STAGE *** XNC12 5 6 7 8 NC2 XPC22 13 14 7 8 PC2 XUSCP2 7 8 9 10 USCP XAMP2 7 8 9 10 AMP *** VOUT STAGE *** XNC13 9 10 11 12 NC1 XPC23 13 14 11 12 PC1 XUSCP3 11 12 13 14 USCP XAMP3 11 12 13 14 AMP *** RLC LADDER NETWORK *** R1 1 21 50 L1 21 22 7.9577E-3 C2 22 0 6.3662E-6 L3 22 23 7.9577E-3 R2 23 0 50 ************************** *** SUB CIRCUITS *** .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=5US RDO 3 0 1K .ENDS DELAY .SUBCKT NC1 1 2 3 4 RNC1 1 0 15.9155 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-66 Problem 9.7-12 – Continued XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.062832 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.062832 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.062832 RNC2 4 0 15.9155 .ENDS NC1 .SUBCKT NC2 1 2 3 4 RNC1 1 0 31.831 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.031416 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.031416 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.031416 RNC2 4 0 31.831 .ENDS NC2 .SUBCKT PC1 1 2 3 4 RPC1 2 4 15.9155 .ENDS PC1 .SUBCKT PC2 1 2 3 4 0 RPC1 2 4 31.831 .ENDS PC2 -20 .SUBCKT USCP 1 2 3 4 R1 1 3 1 R2 2 4 1 -40 Magnitude dB XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 1 -60 XUSC2 1 4 14 DELAY Switched GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY -80 Capacitor GUSC3 2 3 32 0 1 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 -100 Continuous .ENDS USCP .SUBCKT AMP 1 2 3 4 -120 Time EODD 0 3 1 0 1E6 EVEN 0 4 2 0 1E6 -140 .ENDS AMP 100 1000 10k *** ANALYSIS *** Frequency (Hz) .AC DEC 100 10 199K .PRINT AC VDB(13) VDB(14) VDB(23) VP(13) VP(14) VP(23) .END 100k CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-67 Problem 9.7-13 Design a switched capacitor realization of the low-pass prototype filter shown in Fig. 9.7-13 assuming a clock + frequency of 100 kHz. The passband Vin (sn) frequency is 1000Hz. Express each capacitor in terms of the integrating - I1 R0n=1Ω L1n = 2H C2n = 2F R3n =1Ω + Vout(s n ) - capacitor C. Be sure to show the Fig. S9.7-13A phasing of the switches using φ1 and φ2 notation. What is the total capacitance in terms of a unit capacitance, Cu? What is Cmax/Cmin? Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution The state equations are: Vin = I1Ron+sL1nI1+Vout → V1’= sLR1nV in - V 1'R on R - V o u t Vout I1 - R3n = sC2nVout → 1 R V out = sRC2n(V1’ -R3n V out) The normalized realizations for these equations are: Vin α11C1 φ1 φ2 φ2 V1' α21C1 φ2 φ1 Vout α31C1 φ2 φ1 φ1 C1 V1' + 1 V1’ ≈ sTn [α11Vin - α21V1’ - α31Vout] Comparing with the first state equation: α11 R Tn = L1n → α11 = RTn L1n RΩn 1·2000π = fcL1n = 105· 2 α11 = 0.04443 = α21 α31 Ron Tn = L1n Fig. S9.7-13B 0.04443 → α31 = RonΩn fcL1n = α11 = V1' α12C2 φ1 φ2 φ2 Vout α22C2 φ2 φ1 φ1 C2 Vout 1 Vout ≈ sTn [α12V1’ - α22Vout] - Comparing with the second state equation: + α12 Tn = 1 RC2n → α12 = Tn RC2n = Ωn RfcC2n = 1·2000π Fig. S9.7-13C 1·105· 2 α12 = 0.04443 = α22 Connect the above two circuits together to get the resulting filter. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-68 Problem 9.7-13 – Continued The Cmax/Cmin = 1/α12 = 22.508. The units of capacitances normalized to each integrating capacitor is 3 + (1/0.04443) = 25.51 for the first stage and 2 + (1/0.0314) = 24.51 for the second stage. The total units of capacitance for this filter is 50.158 units. The SPICE simulation file for this filter is shown below. SPICE File for Problem 9.7-13 *** Node 9 and 10 are Switched Cap outputs *** Node 22 is RLC ladder network output VIN 1 0 DC 0 AC 1 *** V1' STAGE *** XNC11 1 2 3 4 NC1 XPC21 5 6 3 4 PC1 XPC31 9 10 3 4 PC1 XUSCP1 3 4 5 6 USCP XAMP1 3 4 5 6 AMP *** VOUT STAGE *** XNC12 5 6 7 8 NC2 XPC22 9 10 7 8 PC2 XUSCP2 7 8 9 10 USCP XAMP2 7 8 9 10 AMP *** RLC LADDER NETWORK *** R1 1 21 50 L1 21 22 11.254E-3 C2 22 0 4.50158E-6 R2 22 0 50 ************************** *** SUB CIRCUITS *** .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=5US RDO 3 0 1K .ENDS DELAY .SUBCKT NC1 1 2 3 4 RNC1 1 0 22.5079 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.04443 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.04443 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.04443 RNC2 4 0 22.5079 .ENDS NC1 .SUBCKT NC2 1 2 3 4 RNC1 1 0 22.5079 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.04443 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.04443 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.04443 RNC2 4 0 22.5079 .ENDS NC2 .SUBCKT PC1 1 2 3 4 RPC1 2 4 22.5079 .ENDS PC1 .SUBCKT PC2 1 2 3 4 RPC1 2 4 22.5079 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 9.7-13 .ENDS PC2 .SUBCKT USCP 1 2 3 4 R1 1 3 1 R2 2 4 1 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 1 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 1 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 .ENDS USCP .SUBCKT AMP 1 2 3 4 EODD 0 3 1 0 1E6 EVEN 0 4 2 0 1E6 .ENDS AMP *** ANALYSIS *** .AC DEC 20 10 199K .PRINT AC VDB(9) VDB(10) VDB(23) VP(9) VP(10) VP(23) .END 0 Page 9-69 Magnitude dB -20 -40 -60 -80 -100 100 Switched Capacitor Continuous Time 1000 10k Frequency (Hz) 100k Fig. S9.7-13D CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-70 Problem 9.7-14 Design a switched capacitor realization of the low-pass prototype filter shown assuming a clock frequency of 100 kHz. The passband frequency is 1000Hz. Express each capacitor in terms of the integrating capacitor C. Be sure to show the phasing of the switches using φ1 and φ2 notation. What is the total capacitance in terms of a unit capacitance, Cu? What is Cmax/Cmin? Solution First normalize T by Ωn =2000π to get Tn =ΩnT = 2000π /100,000 = 0.06283 The state equations are: Vin = (I2+sC1nV1)R0n + V1 → and V1 = 1 sR0nC1n V in - V1 - R 0n R V2' V1 = I2sL2n +I2R3n → V1 = sL2n R + RR3nV2' → V2’ = R sL2n V 1 - R3n R V2' Since V2’ = Vout, we can write Vout = R sL2n V 1 - R3n R Vout Realization of the first state equation: Vin α11C1 C1 φ1 φ2 φ2 - V2' α12C1 + φ2 φ1 V1 α31C1 φ2 V1 V1(z) = 1 zn-1 [α11Vin - α21V2’ - α31V1] Let zn ≈ 1+snTn to get V1(s) = 1 snTn[α11Vin(sn) -α21V2’(sn) -α31V1(sn)] ∴ α11 = RTn R0nC1n = Ωn fcC1n = 2000π 2 105 = 0.0444 φ1 φ1 S01E3S2B Since, R = R0n, then α21 = α31 = α11 = 0.4444 Realization of the second state equation: V1 α12C2 φ1 φ2 φ2 V2' α22C2 φ2 φ1 φ1 C2 V2'=Vout Vout(z) = 1 zn-1 [α12V1 - α22V2’] + S01E3S2C Let zn ≈ 1+snTn to get Vout(s) = 1 snTn[α12V1(sn) -α22V2’(sn)] ∴ α12 = Tn L2n = Ωn fcL2n = 2000π 2 105 = 0.0444 α12 = α22 = 0.4444 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-71 Problem 9.7-14 – Continued Cmax 1 Cmin = 0.0444 = 22.508 ΣC = [(22.508+3) + (22.508+2)]Cµ = 50.0158Cµ Realization: Vin Cµ Cµ φ1 φ2 25.508Cµ φ2 φ1 - + Cµ φ1 φ2 Cµ V1 φ1 φ2 Cµ 25.508Cµ φ2 φ1 - + φ1 φ2 Vout S01E3S2D CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-72 Problem 9.7-15 Design a switched capacitor realization of the low-pass prototype filter shown below assuming a clock frequency of 100 kHz. The passband frequency is 1000Hz. Express each capacitor in terms of the integrating capacitor C. Be sure to show the phasing of the switches using φ1 and φ2 notation. What is the total capacitance in terms of a unit capacitance, Cu? What is largest Cmax/Cmin? Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution The state equations are: 1 Vin = sL1nI1 + V2 → I1 = sL1n (Vin - V2) → 1 1 V2 = sC2n (I1 – I3) → V2 = sRC2n (V1’ –V3’) → V2 = 1 sRC2n V 1 ' - R R4n V 2 R V 1’ = sL1n (V in - V 2 ) 1 I3 = sL3n (V2 - Vout) → Vout = I3R4n → R4n V out = sL3n (V 2 - V out) The normalized realizations for these equations are: Vin α11C1 C1 V1' φ1 φ2 φ2 - V2 α21C1 + φ2 φ1 φ1 Fig. S9.7-15B 1 V1’ ≈ sTn [α11Vin - α21V2] Comparing with the first state equation: α11 R Tn = L1n → α11 = RTn L1n RΩn 1·2000π = fcL1n = 105·0.5 α11 = 0.125664 = α21 V1' α12C2 φ1 φ2 φ2 Vout α22C2 φ2 φ1 φ1 C2 Vout 1 Vout ≈ sTn [α12V1’ - α22Vout] - Comparing with the second state equation: + α12 Tn = 1 RC2n → α12 = Tn RC2n = Ωn RfcC2n = 2000π Fig. S9.7-15C 105·(4/3) α12 = 0.047124 = α22 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-73 Problem 9.7-15 – Continued V2 α13C3 φ1 φ2 φ2 Vout α23C3 φ2 φ1 φ1 C3 Vout + Fig. S9.7-15D 1 Vout ≈ sTn [α13V2 - α23Vout] Comparing with the third state equation: α13 1 Tn = R4nL3n α13 = Tn R4nL3n = Ωn R4nfcL3n = 2000π 105(3/2) α13 = 0.041888 = α23 Connect the above three circuits together to get the resulting filter. The Cmax/Cmin = 1/α13 = 23.87. The units of capacitances normalized to each integrating capacitor is 2 + (1/0.126) = 9.936 for the first stage, 2 + (1/0.0471) = 23.231 for the second stage and 2 + (1/0.0419) = 25.8671for the third stage. The total units of capacitance for this filter is 59.03 units. The SPICE simulation file for this filter is shown below. SPICE File for Problem 9.7-15 *** Node 13 and 14 are Switched Cap outputs *** Node 22 is RLC ladder network output VIN 1 0 DC 0 AC 1 *** V1' STAGE *** XNC11 1 2 3 4 NC1 XPC21 9 10 3 4 PC1 XUSCP1 3 4 5 6 USCP XAMP1 3 4 5 6 AMP *** V2 STAGE *** XNC12 5 6 7 8 NC2 XPC22 13 14 7 8 PC2 XUSCP2 7 8 9 10 USCP XAMP2 7 8 9 10 AMP *** VOUT STAGE *** XNC13 9 10 11 12 NC3 XPC23 17 18 11 12 PC3 XUSCP3 11 12 13 14 USCP XAMP3 11 12 13 14 AMP *** RLC LADDER NETWORK *** L1 1 21 3.9789E-3 C2 21 0 4.2441E-6 L3 21 22 11.9366E-3 R4 22 0 50 ************************** *** SUB CIRCUITS *** .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=5US RDO 3 0 1K .ENDS DELAY .SUBCKT NC1 1 2 3 4 RNC1 1 0 7.957729 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.125664 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-74 Magnitude dB Problem 9.7-15 – Continued XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.125664 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.125664 RNC2 4 0 7.957729 .ENDS NC1 .SUBCKT NC2 1 2 3 4 RNC1 1 0 21.2206 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.047124 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.047124 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.047124 RNC2 4 0 21.2206 .ENDS NC2 .SUBCKT NC3 1 2 3 4 RNC1 1 0 23.8732 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.041888 XNC2 1 4 14 DELAY GNC2 4 1 14 0.041888 XNC3 4 0 40 DELAY GNC3 4 0 40 0.041888 RNC2 4 0 23.8732 .ENDS NC3 .SUBCKT PC1 1 2 3 4 RPC1 2 4 7.957729 .ENDS PC1 20 0 -20 -40 -60 -80 -100 -120 100 .SUBCKT PC2 1 2 3 4 RPC1 2 4 21.2206 .ENDS PC2 .SUBCKT PC3 1 2 3 4 RPC1 2 4 23.8732 .ENDS PC3 .SUBCKT USCP 1 2 3 4 R1 1 3 1 R2 2 4 1 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 1 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 1 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 .ENDS USCP .SUBCKT AMP 1 2 3 4 EODD 0 3 1 0 1E6 EVEN 0 4 2 0 1E6 .ENDS AMP *** ANALYSIS *** .AC DEC 20 10 200K .PRINT AC VDB(13) VDB(14) VDB(22) +VP(13) VP(14) VP(22) .END Switched Capacitor Continuous Time 1000 10k Frequency (Hz) 100k Fig. S9.7-15E CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-75 Problem 9.7-16 Design a switched capacitor realization of the low-pass prototype filter shown below assuming a clock frequency of 100 kHz. The passband frequency is 1000Hz. Express each capacitor in terms of the integrating capacitor C (the capacitor connected from op amp output to inverting input). Be sure to show the phasing of the switches using φ1 and φ2 notation. What is the total capacitance in terms of a unit capacitance, Cu? What is largest Cmax/Cmin? R0n=1Ω L2n= 2H Solution Normalize T = 1/fc by Ωn = 2000π + Vin + I2 C1n =1F V1 C3n =1F + R4n =1Ω Vout to get Tn = ΩnT. - - - State Equations: 1.) Vin - V1 R0n = sC1nV1 + I2 ⇒ 1 sC1nR0n Vin -V1- R0nV2' R 1 Vin V1 = sC1n (R0n V1 - R0n -I2) = or V1 = 1 sC1nR0n Vin-V1- R0nV2' R where V2' = RI2 1 R 2.) I2 = sL2n (V1 - Vout) ⇒ V 2 ' = sL2n (V1 - Vout) 3.) Vout I2 = sC3nVout + R4n ⇒ Vout = 1 sC3n I2- Vout R4n ⇒ Vout = 1 sC3nR V 2 ' - RVout R4n Realizations (Assume R = R0n = R4n): 1.) Vin φ1 α11C1 φ2 C1 φ2 V2' φ2 α11C1 A1 φ1 φ2 α11C1 V1 φ1 φ1 V1 1 V1 = zn-1 [α11Vin - α11znV2' - α11znV1] Assume sTn <<1 and let zn ≈ 1+sTn to get V1(s) ≈ α11 sTn (Vin - V2' - V1) ∴ α11 = Tn C1nR0n 2000π = 105·1 = 0.0628 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-76 Problem 9.7-16 – Continued 2.) V1 φ1 α12C2 φ2 C2 φ2 φ2 α12C2 A2 Vout φ1 φ1 1 V2' = zn-1 [α12V1 - α12znVout] V2' Assume sTn <<1 and let zn ≈ 1+sTn to get V1(s) ≈ α12 sTn (V1- Vout) ∴ α12 = RTn L2n 2000π = 105·2 = 0.0314 V2' φ1 α13C3 φ2 C3 φ2 φ2 α13C3 A3 Vout φ1 φ1 3.) 1 Vout = zn-1 [α13V2' - α13znVout] Vout Assume sTn <<1 and let zn ≈ 1+sTn to get Vout(s) ≈ α13 sTn (V2'- Vout) ∴ α12 = Tn RC3n 2000π = 105·1 = 0.0628 Final Realization is given as: Cu φ1 φ1 Cu Vin φ2 φ 2 15.91Cu φ1 A1 φ2 Cu V1 φ1 φ 2 Cu Cu φ1 Cu φ1 φ2 31.83Cu φ2 φ 1 Cu φ1 V2' φ2 A2 φ 2 15.91Cu φ1 A3 φ2 Vout The total capacitance is 70.65Cu where Cu is a unit capacitance. The largest Cmax/Cmin ratio is 31.83. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-77 Problem 9.7-17 Design a switched capacitor realization of the low-pass R0n=1Ω L1n=1Η L3n=2Η prototype filter shown below assuming a clock frequency of 200 kHz. The passband Vin(s) frequency is 1000Hz. Express C2n= 2F C4n= 1F R5n= 1Ω + Vout(s) - each capacitor in terms of the integrating capacitor C (the FigS9.7-17 capacitor connected from op amp output to inverting input). Be sure to show the phasing of the switches using φ1 and φ2 notation. What is the total capacitance in terms of a unit capacitance, Cu? What is largest Cmax/Cmin? Solution First we must normalize the clock period, T, by Ωn = 2000π to get Tn = ΩnT = Ωn/fc. The state equations for the bold variables above are: 1.) Vin = R0nI1 + sL1I1 + V2 = R0n R V1‘ + sL1 R V‘1 + V2 → V‘1 = R sL1n V in R0n - R V ‘1 - V2 1 2.) V2 = sRC2n ( V‘1 - V ‘3) R 3.) V‘3 = sL3n ( V 2 - V o u t) 4.) Vout I3 = sC4nVout + R5n → Vout = 1 sRC4n V‘3 - R R5n V o u t Realizing each of these four state equations is done as follows: 1 1.) V‘1(zn) = z n - 1 [α11Vin - α11znV2 - α11znV‘1] V‘1(s) ≈ α11 sTn [Vin - V2 - V‘1] ∴ α11 = TnR L1n = 2000π 105·1 = 0.0314 1 2.) V2(zn) = z n - 1 [α21V‘1- α21znV‘3] V2(s) ≈ α21 sTn [V‘1- V‘3] ∴ α21 = Tn RC2n = 2000π 105·2 = 0.0159 Vin α11C1 C1 V'1 φ1 φ2 φ2 - V'1 α11C1 + φ2 φ1 V2 α11C1 φ2 φ1 φ1 V'1 α21C2 C2 V2 φ1 φ2 φ2 - V'3 α21C2 + φ2 φ1 φ1 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-78 Problem 9.7-17 - Continued 1 3.) V‘3(zn) = z n - 1 [α31V2- α31znVout] V‘3(s) ≈ α31 sTn [V2- Vout] ∴ α31 = TnR L3n = 2000π 105·2 = 0.0159 1 4.) Vout(zn) = z n - 1 [α41V‘3- α41znVout] Vout(s) ≈ α41 sTn [V‘3- Vout] ∴ α41 = Tn RC4n = 2000π 105·1 = 0.0314 V2 α31C3 C3 V'3 φ1 φ2 φ2 - Vout α31C3 + φ2 φ1 φ1 V'3 α41C4 C4 Vout φ1 φ2 φ2 - Vout α41C4 + φ2 φ1 φ1 The actual filter realization is obtained by connecting the above four circuits as indicated by their terminal voltages. Total capacitance: For each stage, make the smallest capacitor equal to Cu and sum capacitors. Stage 1: 3Cu + (Cu/0.0314) = 31.8Cu + 3Cu = 34.8Cu Stage 2: 2Cu + (Cu/0.0159) = 63.7Cu + 2Cu = 65.7Cu Stage 3: 2Cu + (Cu/0.0159) = 63.7Cu + 2Cu = 65.7Cu Stage 4: 2Cu + (Cu/0.0314) = 31.8Cu + 2Cu = 33.8Cu Total capacitance = 200Cu Cmax Cmin = 63.7 SPICE File: *** HW9 PROBLEM3 (Problem 9.7-17) *** *** Node 17 and 18 are Switched Cap outputs *** Node 23 is RLC ladder network output VIN 1 0 DC 0 AC 1 *** V1' STAGE *** XNC11 1 2 3 4 NC1 XPC21 9 10 3 4 PC1 XPC31 5 6 3 4 PC1 XUSCP1 3 4 5 6 USCP XAMP1 3 4 5 6 AMP *** V2 STAGE *** XNC12 5 6 7 8 NC2 XPC22 13 14 7 8 PC2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 9.7-17 – Continued XUSCP2 7 8 9 10 USCP XAMP2 7 8 9 10 AMP *** V3' STAGE *** XNC13 9 10 11 12 NC2 XPC23 17 18 11 12 PC2 XUSCP3 11 12 13 14 USCP XAMP3 11 12 13 14 AMP *** VOUT STAGE *** XNC14 13 14 15 16 NC1 XPC24 17 18 15 16 PC1 XUSCP4 15 16 17 18 USCP XAMP4 15 16 17 18 AMP *** RLC LADDER NETWORK *** R1 1 21 50 L1 21 22 7.9577E-3 C2 22 0 6.3662E-6 L3 22 23 15.9155E-3 C4 23 0 3.1831E-6 R2 23 0 50 ************************** *** SUB CIRCUITS *** .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=2.5US RDO 3 0 1K .ENDS DELAY .SUBCKT NC1 1 2 3 4 RNC1 1 0 31.8269 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.03142 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.03142 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.03142 RNC2 4 0 31.8269 .ENDS NC1 .SUBCKT NC2 1 2 3 4 RNC1 1 0 63.6537 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.01571 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.01571 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.01571 RNC2 4 0 63.6537 .ENDS NC2 .SUBCKT PC1 1 2 3 4 RPC1 2 4 31.8269 .ENDS PC1 .SUBCKT PC2 1 2 3 4 RPC1 2 4 63.6537 .ENDS PC2 .SUBCKT USCP 1 2 3 4 R1 1 3 1 R2 2 4 1 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 1 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 1 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 .ENDS USCP .SUBCKT AMP 1 2 3 4 EODD 0 3 1 0 1E6 EVEN 0 4 2 0 1E6 .ENDS AMP *** ANALYSIS *** .AC DEC 1000 10 199K .PROBE .END Page 9-79 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-80 Problem 9.7-18 Use the low-pass, normalized prototype filter of Fig. P9.7-14 to develop a switchedcapacitor, ladder realization for a bandpass filter which has a center frequency of 1000Hz, a bandwidth of 500Hz, and a clock frequency of 100kHz. Give a schematic diagram showing all values of capacitances in terms of the integrating capacitor and the phasing of all switches. Use strays-insensitive integrators. Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution 1.) Normalize by s = BωWr p = 1000 500 p = 2p 2.) Transform the normalized circuit to bandpass using the transformation, 1 s=p+p The resulting circuit is shown. Ron = 1Ω 1 2L2n 2L2n 3.) The state equations for this bandpass circuit can be written as follows. s V1 = 2RC1n s2+1 RRon(Vin-V1)-V2' Vs 1 2C1n I2 V1 R3n =1Ω Vout 2C1n where V2’ = I2·R and R = 1. R3n Vout = R R3n V2’ = R sR 2s2L+21n (V1-Vout) = sR3n 2s2L+21n (V1-Vout) 4.) The SC realization of each second-order block is given as, V1 α3jCj φ1 φ2 φ2 φ2 Cj - + Vj φ1 V2 α4jCj φ2 α1jCj Cj φ2 α2jCj φ2 φ1 φ1 φ1 φ1 φ1 φ2 + - Fig. S9.7-18D CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-81 Problem 9.7-18 – Continued If fclock>>fr, then Vj(s) of the above realization can be written as, Vj(s) ≈ s2 + s α 1 jα 2j Tn2 αT3njV 1 -αT4njV2 where Tn = ΩnT = ωrT 5.) Comparing the state equations with the above transfer function gives, j = 1 or V1: α11α21 = Tn2 → α11 = α21 = Tn = ωrT = ωr fclock = 2πx103 105 = 0.02π α31 = α41 = α51 = Tn ωrT 2πx103 Ron2C1n = 2 = 22 2x105 = 0.0071π j = 2 or Vout: α12α22 = Tn2 → α12 = α22 = Tn = ωrT = ωr fclock = 2πx103 105 = 0.02π α32 = α42 = Tn ωrT 2πx103 Ron2L2n = 2 = 22 2x105 = 0.0071π 6.) Filter realization: Vs0.022214C1 φ1 φ2 φ2 φ1 0.0222143C1 α11 = α21 = 0.02π= 0.0628 Cj = C1 φ2 φ1 φ1 0.022214C1 0.022214C2 φ2 φ1 Vout φ2 α12 = α22 φ2 = 0.02π= 0.0628 Cj = C2 φ2 0.022214C2 φ1 φ1 Fig. S9.7-18E CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-82 Problem 9.7-18 – Continued 7.) To create the SPICE input file, the above figure needs to be expanded which is done below. Vin α31C1 C1 φ1 φ2 φ2 - V2 α11C1 + φ1 φ2 V1 V1 α32C1 C2 Vout φ1 φ2 φ2 - V4 α12C1 + φ1 φ2 Vout α51C1 α41C1 V1 φ1 φ2 φ1 φ1 φ2 Vout α42C1 φ1 φ2 φ1 V1 α21C1 C1 V2 Vout α22C2 C2 V4 φ1 φ2 - φ1 φ2 - φ2 φ1 + φ2 φ1 + 8.) The SPICE simulation file for this filter is shown below. SPICE File for Problem 9.7-18 *** Node 13 and 14 are Switched Cap outputs *** Node 23 is RLC ladder network output VIN 1 0 DC 0 AC 1 *** V1 STAGE *** XPC11 9 10 3 4 PC2 XNC31 1 2 3 4 NC1 XPC41 5 6 3 4 PC1 XPC51 13 14 3 4 PC1 XUSCP1 3 4 5 6 USCP XAMP1 3 4 5 6 AMP *** V2 STAGE *** XNC21 5 6 7 8 NC2 XUSCP2 7 8 9 10 USCP XAMP2 7 8 9 10 AMP *** VOUT STAGE *** XPC12 17 18 11 12 PC2 XNC32 5 6 11 12 NC1 XPC42 13 14 11 12 PC1 XUSCP3 11 12 13 14 USCP XAMP3 11 12 13 14 AMP *** V4 STAGE *** XNC22 13 14 15 16 NC2 XUSCP4 15 16 17 18 USCP XAMP4 15 16 17 18 AMP *** RLC LADDER NETWORK *** R0 1 21 50 C1 21 0 9.0032E-6 L1 21 0 2.8135E-3 Fig. S9.7-18F CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-83 Problem 9.7-18 – Continued L2 21 22 22.5079E-3 C2 22 23 1.125395E-6 R3 23 0 50 *** SUB CIRCUITS *** .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=5US RDO 3 0 1K .ENDS DELAY .SUBCKT NC1 1 2 3 4 RNC1 1 0 45.015816 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.022214 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.022214 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.022214 RNC2 4 0 45.015816 .ENDS NC1 .SUBCKT NC2 1 2 3 4 RNC1 1 0 15.91549 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.062832 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.062832 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.062832 RNC2 4 0 15.91549 .ENDS NC2 .SUBCKT PC1 1 2 3 4 0 RPC1 2 4 45.015816 .ENDS PC1 -10 .SUBCKT PC2 1 2 3 4 RPC1 2 4 15.91549 .ENDS PC2 -20 Magnitude dB .SUBCKT USCP 1 2 3 4 R1 1 3 1 -30 R2 2 4 1 XUSC1 1 2 12 DELAY -40 GUSC1 1 2 12 0 1 XUSC2 1 4 14 DELAY -50 GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 1 -60 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 -70 .ENDS USCP .SUBCKT AMP 1 2 3 4 EODD 0 3 1 0 1E6 EVEN 0 4 2 0 1E6 -80 100 Continuous Time 1000 10k Frequency (Hz) .ENDS AMP *** ANALYSIS *** .AC DEC 20 100 100K .PRINT AC VDB(17) VDB(18) VDB(23) VP(17) VP(17) VP(23) .END Switched Capacitor 100k Fig. S9.7-18E CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-84 Problem 9.7-19 Use the low-pass, normalized prototype filter of Fig. P9.7-13 to + develop a switched-capacitor, ladder realization for a bandpass filter which Vin (sn) has a center frequency of 1000Hz, a - R0n=1Ω L1n = 2H C2n = 2F R3n =1Ω + Vout(s n ) - bandwidth of 500Hz, and a clock frequency of 100kHz. Give a Figure P9.7-13 schematic diagram showing all values of capacitances in terms of the integrating capacitor and the phasing of all switches. Use strays-insensitive integrators. Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-85 Problem 9.7-20 Use the low-pass, normalized prototype filter shown to develop a switched-capacitor, ladder realization for a bandpass filter which has a center frequency of 1000Hz, a bandwidth of 100Hz, and a clock frequency of 100kHz. Give a schematic diagram showing all values of capacitances in terms of the integrating capacitor and the phasing of all switches. Use strays-insensitive integrators. Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Ron L2n + - Vin(s) =1Ω =2H C1n C3n R4n = = = Vout(s) R3 C2 R2 1F 1F 1Ω R1 V1 R4 R R Vo- ( ) - V o V1 = Vo+ V1 = s2 R4 s R1 R4C1 + R4sC1+ 1 R2R3C1C2 V2 R1 - C1 + - V + o + Tow-Thomas Bandpass Filter Solution The bandpass normalized filter is shown using the values of fr = 1000 Hz and BW = 100 Hz to scale the elements by 10. The state variables and the input voltage are shown in bold. Vin(s) The state equations are: Ron =1Ω L1bn = 0.1H L2bn C2bn= V1 =20H 0.05F I2 C1bn L3bn == C3bn = 10F 0.1H 10F R4n = Vout(s) 1Ω 1.) Vin - V1 R0n 1 = I2 + (sC1bn+ sL1bn) V1 → Vin R0n - V‘2 R = 1 R0n +sC1bn+ 1 sL1bn V1 s or V1 = s2 C1bnR s + R0nC1bn + 1 V2‘ L1bnC1bn - RV0inn = 0.1s s2+0.1s+1 (V2‘ - Vin) 2.) s I2 V‘2 V 2 - V o u t = R = sL2bn + 1 sC2bn = s2 L2bn 1 (V1 - Vout) → + L2bnC2bn 0.05s V‘2 = s2 + 1 (V1 - Vout) V‘2 R 0.1V‘2 3.) Vout = sC3bn + 1 sL3bn + 1 = s2 R4n + 0.01s + 1 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-86 Problem 9.7-20 - Continued Now we need to design each Tow-Thomas bandpass circuit. If R2 = R3 = 1Ω and C1 = C2 = 1F of the Tow-Thomas circuit then the transfer function becomes, s V+o Ri1 V1 = s2˚˚+ s Ri4 + 1 where i corresponds to the i-th stage Therefore the design of each stage is: Stage 1: R11 = 10Ω, R14 = 10Ω, R12 = R13 =1Ω, and C11 = C12 = 1F Stage 2: R21 = 20Ω, R24 = ∞, R22 = R23 =1Ω, and C21 = C22 = 1F Stage 3: R31 = 10Ω, R34 = 10Ω, R32 = R33 =1Ω, and C31 = C32 = 1F Next, denormalizing by 2000π and impedance denormalizing by 105 gives, - C12 R13 R12 + R11 Vin R11 C11 - R14 + R R R21 - + - C22 R23 R22 - C32 R33 R32 + + R R -C21 - + + R21 C31 R31 - R34 + R R - Vout + where R = R11 = R14 = 1MΩ, R12 = R13 = 100kΩ, and C11 = C12 = 1.59nF R = R21 = 2MΩ, R24 = ∞, R22 = R23 = 100kΩ, and C21 = C22 = 1.59nF and R = R31 = R32 = 1MΩ, R32 = R3 = 100kΩ, and C31 = C32 = 1.59nF SPICE File: *** HW9 PROBLEM4 (Problem 9.7-20) *** *** Node 13 and 14 are Switched Cap outputs *** Node 23 is RLC ladder network output VIN 1 0 DC 0 AC 1 *** V1 STAGE *** XNC41 1 2 3 4 NC41 XPC411 9 10 3 4 PC41 XPC412 5 6 3 4 PC41 XLQBQ1 3 4 5 6 LQBIQUAD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 9.7-20 – Continued *** V2' STAGE *** XNC42 5 6 7 8 NC42 XPC421 13 14 7 8 PC42 XLQBQ2 7 8 9 10 LQBIQUAD *** VOUT STAGE *** XNC43 9 10 11 12 NC41 XPC431 13 14 11 12 PC41 XLQBQ3 11 12 13 14 LQBIQUAD *** RLC LADDER NETWORK *** R1 1 21 50 C11 21 0 3.1831E-5 L11 21 0 7.9577E-4 L21 21 22 0.1592 C21 22 23 1.5915E-7 C31 23 0 3.1831E-5 L31 23 0 7.9577E-4 R2 23 0 50 ************************** *** SUB CIRCUITS *** .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=5US RDO 3 0 1K .ENDS DELAY .SUBCKT NC5 1 2 3 4 RNC1 1 0 15.916 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.06283 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.06283 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.06283 RNC2 4 0 15.916 .ENDS NC5 .SUBCKT NC41 1 2 3 4 RNC1 1 0 159.1596 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.006283 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.006283 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.006283 RNC2 4 0 159.1596 .ENDS NC41 .SUBCKT NC42 1 2 3 4 RNC1 1 0 318.2686 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.003142 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.003142 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.003142 RNC2 4 0 318.2686 .ENDS NC42 Page 9-87 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 9.7-20 – Continued .SUBCKT PC2 1 2 3 4 RPC1 2 4 15.916 .ENDS PC2 .SUBCKT PC41 1 2 3 4 RPC1 2 4 159.1596 .ENDS PC41 .SUBCKT PC42 1 2 3 4 RPC1 2 4 318.2686 .ENDS PC42 .SUBCKT USCP 1 2 3 4 R1 1 3 1 R2 2 4 1 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 1 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 1 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 .ENDS USCP .SUBCKT AMP 1 2 3 4 EODD 0 3 1 0 1E6 EVEN 0 4 2 0 1E6 .ENDS AMP .SUBCKT LQBIQUAD 5 6 7 8 XPC2 7 8 1 2 PC2 XUSCP1 1 2 3 4 USCP XAMP1 1 2 3 4 AMP XNC5 3 4 5 6 NC5 XUSCP2 5 6 7 8 USCP XAMP2 5 6 7 8 AMP .ENDS LQBIQUAD *** ANALYSIS *** .AC DEC 1000 10 99K .PROBE .END Page 9-88 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-89 Problem 9.7-21 Use the low-pass, normalized prototype filter shown to develop a switched-capacitor, ladder realization for a bandpass filter which Ron L1n L3n =1Ω =1H =1H has a center frequency of 1000Hz, a bandwidth of 100Hz, and a clock frequency of 100kHz. Give a schematic diagram Vin(s) showing all values of capacitances in terms of C2n = R4n = Vout(s) 2F 1Ω the integrating capacitor and the phasing of all switches. Use strays-insensitive integrators. Figure P9.7-21 Use SPICE to plot the frequency response (magnitude and phase) of your design and the ideal continuous time filter. Solution TBD CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-90 Problem 9.7-22 A second-order, lowpass, Sallen and Key active filter is shown along with the transfer function in terms of the components of the filter. R1 R3 C2 a.) Define n = R3/R1 and m = C4/C2 and Vin let R1 = R and C2 = C. Develop the design equations for Q and ωo if K = 1. K Vout C4 b.) Use these equations to design for a second-order, K lowpass, Butterworth antialiasing filter with a bandpass frequency of 10kHz. Let R1 = R = Vout Vin = s2+sR31C4 + 1 R1C2 R1R3C2C4 + 1 R3C2 - K R3C4 + 1 R1R3C2C4 10kΩ and find the value of C2, R3, and C4. Solution a.) The expressions for Q and ωo are ωo = 1 R1R3C2C4 ωo 1 1 1K and Q = R3C4 + R1C2 + R3C2 - R3C4 1 1 If K = 1, then ωo = R1R3C2C4 and Q = R3C4 R1C2 + R1C4 R3C2 . R3 C4 Define n = R1 and m = C2 and let R1 = R and C2 = C. Therefore, ωo2 = 1 mn(R1C2)2 ⇒ ωo = 1 = mnR1C2 1 mnRC and 1 Q= mn + m n= mn 1+ 1 n b.) A normalized Butterworth second-order lowpass function is Vout 1 Vin = s2+ 2s+1 ⇒ ωο = 1 rad/sec and Q = 0.707 Let R1 = R = 1Ω and C2 = C = 1F. ∴ mn = 1 and 2 = 1·1+ 1 n 1 = 1+ n 1 1 From the above, n = 2-1 = 2.4142 and m = 2.4142 = 0.4142 ∴ R3 = 2.4142Ω and C4 = 0.4142F Denormalizing by 104Ω and 20,000π (rads/sec) gives R1 = 10kΩ, R3 = 24.142kΩ, C1 = 1.59nF and C4 = 0.659nF CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 9-91 Problem 9.7-23 The circuit shown is to be analyzed to determine its capability to realize a second- Vin(s) R1 order transfer function with complex conjugate poles. Find the transfer function of the circuit and determine and verify the answers to the following questions: C2 R3 +1 C4 Vout(s) +1 Figure P9.7-23 1.) Is the circuit low-pass, bandpass, high-pass, or other? 2.) Find Ho, ωo, and Q in terms of R1, C2, R3, and C4. 3.) What elements would you adjust to independently tune Q and ωo? Solution a.) Vout = R3(+1(/s1C/s4C) 4)V1 = V1 sR3C4+1 V1 = R1+(R11/sC2)Vout + R1(+1(/s1C/s2C) 2)Vin = sR1C2Vout sC2R1+1 + Vin sC2R1+1 ∴ Vout = sR3C14+1ssRC12CR21V+o1ut + Vin sC2R1+1 Vout(sR3C4+1)(sR1C2+ 1) = sR1C2Vout + Vin Vout[s2R1R3C2C4 + sR1C2+ sR3C4 - sR1C2 + 1] = Vin 1 ∴ Vout 1 R1R3C2C4 Hoωο2 Vin = s2R1R3C2C4+sR3C4+1 = s2+ s R1C2 + 1= R1R3C2C4 s2+ ωQos + ωο ∴ Filter is low-pass. 1 b.) From the previous results, Ho = 1, ωo = R1R3C2C4 , and Q = ωo R1C2 = R1C2 R3C4 c.) To tune ωo but not Q, adjust the product of R1R3 (C2C4) keeping the ratio R1/R3 (C2/C4) constant. To tune Q but not ωo, adjust the ratio R1/R3 (C2/C4) keeping the product of R1R3 (C2C4) constant. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-1 CHAPTER 10 – HOMEWORK SOLUTIONS Problem 10.1-01 Plot the analog output versus the digital word input for a three-bit D/A converter that has ±1 LSB DNL and ±1 LSB INL. Assume an arbitrary analog full-scale value. Solution Below is a characteristic of a 3-bit DAC. The shaded area is not permitted in order to maintain ±1 LSB INL. 8 8 7 8 -1 LSB Analog Input Voltage 6 DNL 8 5 Actual 3-bit Characteristic 8 4 8 3 +1 LSB INL 8 +1 LSB 2 DNL 8 -1 LSB INL Ideal 3-bit Characteristic 1 8 0 8 000 001 010 011 100 101 110 111 Digital Output Code S10.1-01 Problem 10.1-02 Repeat the above problem for ±1.5 LSB DNL and ±0.5 LSB integral linearity. Solution The shaded area is not permitted in order to maintain ±0.5 LSB INL. Note that the DNL cannot exceed ±1 LSB. Analog Input Voltage 8 8 7 -1 LSB 8 DNL 6 8 5 Actual 3-bit Characteristic 8 +0.5 LSB 4 8 INL -0.5 LSB 3 8 +1 LSB INL 2 DNL Ideal 3-bit Characteristic 8 1 8 0 8 000 001 010 011 100 101 110 111 Digital Output Code S10.1-02 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-2 Problem 10.1-03 Repeat Prob. 1, for ±0.5 LSB differential linearity and ±1.5 LSB integral linearity. Solution The shaded area is not permitted in order to maintain ±1.5 LSB INL. Analog Input Voltage 8 8 7 -0.5 LSB 8 DNL 6 8 5 Actual 3-bit Characteristic 8 4 8 +1.5 LSB 3 8 INL 2 8 -1.5 LSB INL Ideal 3-bit Characteristic 1 +0.5 LSB 8 0 DNL 8 000 001 010 011 100 101 110 111 Digital Output Code S10.1-03 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-3 Problem 10.1-04 The transfer characteristics of an ideal and actual 4-bit digital-analog converter are shown in Fig. P10.1-4. Find the ±INL and ±DNL in terms of LSBs. Is the converter monotonic or not? Analog Output (Normalized to Full Scale) 16/16 15/16 14/16 13/16 12/16 11/16 10/16 9/16 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 0/16 b1 0 b2 0 b3 0 b4 0 Infinite resolution DAC characteristic +1.5LSB DNL Actual 4-bit DAC characteristic Ideal 4-bit DAC characteristic 0000000 1111111 000 11110000111 0 1100 110011001 10 10 10 10101010 Digital Input Code +1LSB INL -1.5LSB INL -2LSB DNL 1 1 1 1 S10.1-04 Solution INL: +1LSB, -2.5LSB, DNL: +1.5LSB, -2LSB, the converter is not monotonic. Problem 10.1-05 A 1V peak-to-peak sinusoidal signal is applied to an ideal 10 bit DAC which has a VREF of 5V. Find the SNR of the digitized analog output signal.). Solution A 1V peak sinusoideal signal is applied to an ideal 10 bit DAC which has a VREF of 5V. Find the SNR of the digitized analog output signal. Solution The SNRmax = 6.02dB/bit x 10bits + 1.76dB = 61.96dB The maximum output signal is 2.5V peak. Therefore, the 1V peak signal is 7.96dB smaller to give a SNR of the digitized analog output as 61.96-7.96 = 54dB ∴ SNR = 54dB CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-4 Problem 10.1-06 How much noise voltage in rms volts can a 1V reference voltage have and not cause errors in a 14-bit D/A converter? What must be the fractional temperature coefficient (ppm/°C) for the reference voltage of this D/A converter over the temperature range of 0°C to 100°C? Solution 1 1 The rms equivalent of a 1V reference voltage is 2 V. 2 Multiplying by 214 gives 1 Rms noise = 2 2·214 = 21.6µV(rms) → Rms noise = 21.6µV To be within ±0.5LSB, the voltage change must be less than or equal to 2-15. ∆V 2-15 V1 1 ∴ ppm/C° = ∆ Τ = 100C° = 2·16,384·100 = 0.3052pppm/C° → 0.3052ppm/C° Problem 10.1-07 If the quantization level of an analog-to-digital converter is ∆, prove that the rms quantization noise is given as ∆/ 12. Solution Assume the quantizer signal appears as follows. q(x) ∆/2 x -1 0 1 −∆/2 Fig. S10.1-07 The rms value of q(x) is T 1T⌡⌠q2(x)dx where q(x) = 0.5∆x and T = 2. 0 ∴ rms value of q(x) = 1 1⌠∆2 2⌡ 4 x2dx = -1 ∆2 x3 1 8 3 = -1 ∆2 8 1 3 + 1 3 = ∆ 12 rms value of q(x) = ∆/ 12 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-5 Problem 10.2-01 Find Io in terms of I1, I2, I3, and I4 for the circuit shown. Solution IOUT = I0 I1 I1 sees R to the right and R to the left so that IO U T = 2 . I2 requires the use of Norton’s theorem to see the results. 2R R IOUT R 2R 2R IOUT RRR I3 I2 I1 I0 Figure P10.2-1 R IOUT 2R I2 2R R I2 R 2R R IOUT IOUT I2 R R 2 I2 2 2R 2R R ∴ I2 IOUT = 4 S10.2-01A I3 Repeating the above process for I8 will give IOUT = IO U T = 8 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-6 Problem 10.2-02 A digital-analog converter uses the binary weighted current sinks shown. b1 is the MSB and bN is the LSB. b1 b2 bN a.) For each individual current sink, find the tolerance in ±percent necessary to keep INL less than ±0.5LSB if N = 4 assuming all other bits are ideal. I 2 I 4 I 2N b.) Considering the influence of all current sinks, what is the worst case tolerances in ±percent for each sink? Solution I ±I I a.) An LSB = 2N , therefore each sink must have the accuracy of ±0.5 LSB = 2N+1 = 32 . I/2: I 2 ± I 2N+1 = I 2 ± I 32 = I 2 1 ± 1 16 ⇒ ±1 I 16 ±100 Tolerance of 2 = 1 x100% = 16 % = ±6.25% ±1 I/4: I 4± I 32 = I 4 1 ± 1 8 ⇒ I8 ±100 Tolerance of 4 = 1 x100% = 8 % = ±12.5% Similarly, the tolerance of I/8 and I/16 are ±25% and ±50%, respectively. 2i-N The tolerance of the ith current sink = 2 x100% b.) In this case, assume that all errors add for a worst case approach. Let this error be x. Therefore we can write, I 2 + x + I 4 + x + I 8 + x + I 16 + x ≤ I 2 + I 4 + I 8 + I 16 + I 32 or I 2 + I 4 + I 8 + I 16 + 4x ≤ I 2 + I 4 + I 8 + I 16 + I 32 ⇒ I x = 4·32 = I 128 Thus the tolerances of part a.) are all decreased by a factor of 4 to give ±1.5625%, ±3.125%, ±6.25%, and ±12.5% for I/2, I/4, I/8, and I/16, respectively. I 2 ⇒ ±1.5625%, I 4 ⇒ ±3.125%, I 8 ⇒ ±6.25% and I 16 ⇒ ±12.5% 2i-N The tolerance of the ith current sink = 2N x100% CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-7 Problem 10.2-03 A 4-bit, binary weighted, voltage scaling digital-to-analog converter is shown. (a.) b1 R1 b2 R2 R0 vout - If R0 = 7R/8, R1 = 2R, R2 = 4R, R3 = 8R, VREF R4 = 16R, and VOS = 0V, sketch the digital-analog transfer curve on the plot on the next page. (b.) If R0 = R, R1 = 2R, R2 b3 R3 + + b4 R4 - VOS = 4R, R3 = 8R, R4 = 16R, and VOS = (1/15)VREF, sketch the digital-analog transfer curve on the plot shown. (c.) If R0 = R, R1 = 2R, R2 = 16R/3, R3 = 32R/5, R4 = 16R, and VOS = 0V, sketch the digital-analog transfer curve on the previous transfer curve. For this case, what is the value of DNL and INL? Is this D/A converter monotonic or not? Solutions (a.) vout = R0 Rb11 + b2 R2 + b3 R3 + Rb44 VREF = 7b1 8 2 + b2 4 + b3 8 + b4 16 VREF vout = 7 16 + 7 24 + 7 64 + 7 128 VREF 7 = 8 x ideal characteristic (b.) The equivalent circuit is given as shown. R Req = b1 b 2 b 3 b 4 2 + 4 + 8 + 16 R0 vout = Req.(VREF+VOS) + VOS b1 b2 b 3 b 4 vout = 2 + 4 + 8 + 16(VREF-VOS) + VOS VREF Req. VOS b1 b 2 b3 b 4 16VREF VREF vout = 2 + 4 + 8 + 16 15 + 15 R vout + F98E2S2B ∴ Gain error of 1/16 and offset of VREF/15. (c.) vout = R0 Rb11 + b2 R2 + b3 R3 + Rb44 VREF b1 = 2 + 3b2 16 + 5b3 32 + b4 16 VREF 16b1 = 32 + 12b2 32 + 5b3 32 + 2b4 32 VREF → Used to generate the plot on the next page ∴ INL = +0.5LSB and -1.0LSB DNL = +0.5LSB and -1.5LSB This DAC is not monotonic. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-8 Problem 10.2-3 - Continued Analog Output Voltage Normalized to VREF 16 16 15 16 14 16 13 16 12 16 11 16 10 16 9 16 8 16 7 16 6 16 5 16 INL = 4 +0.5LSB 16 3 16 1 2 15 16 1 16 0 16 0 0 0 000 001 010 16 16 + 1 15 Part (b.) DNL = -1.5LSB Ideal Finite Resolution Characteristic DNL = +0.5LSB Part (a.) Part (c.) INL = -1.0LSB 0 000011111111 0 11110000 1111 1 00110011 0011 1 01010101 0101 Digital Input Code F98E2S2 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-9 Problem 10.2-04 A 4-bit digital-to-analog converter characteristic using the DAC of Fig. P10.2-3 is shown in Fig. P10.2-4. (a.) Find the DNL and the INL of this converter. (b.) What are the values of R1 through R4, that correspond to this input-output characteristic? Find these values in terms of R0. 16/16 15/16 Ideal DAC Characteristic 14/16 13/16 Analog Output (Normalized to Full Scale) 12/16 11/16 10/16 9/16 8/16 7/16 6/16 5/16 4/16 Actual 4-bit DAC 3/16 characteristic 2/16 Ideal 4-bit DAC 1/16 characteristic 0/16 b0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Digital Input Code Solution Figure P10.2-4 (a.) INL = +0.5LSB and –2.0 LSB, DNL = +0.5LSB and –1.5LSB. (b.) Note that vOUT can be written as, vOUT = -R0 b0 R1 + b1 R2 + b2 R3 + b3 R4 VREF VREF For 0001, | vOUT| = 16 → R4 = 16 R0. 5VREF For 0010, | vOUT| = 32 → 32 R3 = 5 R0. 3VREF For 0100, | vOUT| = 16 → 16 R2 = 3 R0. VREF For 1000, | vOUT| = 2 → R1 = 2 R0 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-10 Problem 10.2-05 For the DAC of Fig. P10.2-3, design the values of R1 through R4 in terms of R0 to achieve an ideal 4-bit DAC. What value of input offset voltage, VOS, normalized to VREF will cause an error? If the op amp has a differential voltage gain of 106 Avd(s) = s˚+˚100 at what frequency or rate of conversion will an error in conversion occur due to the frequency response of the op amp? Assume that the rate of application of digital words to be converted is equivalent to the application of a sinusoidal signal of equivalent frequency. Solution The values of the resistors are R1 = 2R0, R2 = 4R0, R3 = 8R0, and R4 = 16R0. A model for the input offset voltage influence on the DAC is shown. The output voltage is, vOUT = - R REQ. VREF + R +REQ. REQ. VOS We see that the largest influence of VOS is when REQ. is minimum which is R1||R2||R3||R4 = (16/15)R. REQ. R - vOUT ∴ 1 + 1 5 16 VOS 1 ≤ 0.5LSB = 32 VREF VREF + VOS VREF ≤ 1 16 3231 = 1 62 = 0.01613 VOS Fig. S10.2-05 For the maximum conversion rate, the worst case occurs when the loop gain is smallest. The loop gain is given as LG = - R REQ. +REQ. Avd Which is minimum when REQ. = (16/15)R. The ideal output normalized toVREF is, vOUT(ideal) VREF = -RREQ. = - 15 16 The actual output normalized toVREF is, AvdR vOUT(actual) - R +R E Q . 15 - 31 15 - 31 VREF = AvdREQ. 1+ R +REQ. =1 Avd + 16 31 =s 106 + 16 31 where we have assumed that ω >> 100 rads/sec which gives Avd(s) ≈ 106/s. An error occurs when vOUT(actual) VREF 15 1 ≥ 16 - 32 29 = 32 (Actual is always less than ideal) 15 31 29 ω1m0a6x2 + 162 31 ≥ 32 → 162 31 + ω1m0a6x2 ≤ 152 322 31 29 ωmax 106 ≤ 15 31 x 3 22 29 - 162 31 = 0.1367 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-11 Problem 10.2-05- Continued ∴ ωmax ≤ 0.1367x106 rads/sec. → fmax ≤ 21.76 kHz Note that 21.76 kHz is much greater than 15.9 Hz (100 rads/sec.) so that the approximation used for Avd(s) is valid. Problem 10.2-06 An 8-bit current DAC is shown. Assume that the full scale range is 1V. (a.) Find the value of I if R = 1kΩ. (b.) Assume that all aspects of the DAC are ideal except for the op amp. If the differential voltage gain of the op amp has a single pole frequency response with a dc gain of 105. Find the unity gainbandwidth, GB, in Hz that gives a worst case conversion time of 2µs. (c.) Again assume that all aspects of the DAC are ideal except for the op amp. The op amp is ideal except for a finite slew rate. Find the minimum slew rate, SR, in V/µs that gives a worst case conversion time of 2µs. vout R - I I 2 I 4 I 128 + Solution F97E1P3 (a.) FSR = 2I·R = 1V ⇒ I = 1V/2kΩ = 500µA ∴ I = 500µA (b.) Model for part b. Ieq = all bits switched R vout R to the op amp input. - The worst case occurs Ieq + when all bits are Ieq +Vi AvVi vout switched to the op amp. ∴ Vout = AvVi = Av[RIeq - Vout] ⇒ Vout(1+Av) = AvRIeq ⇒ Vout = RIeq 1 Av + 1 RIeq or Vout(s) = s Assuming a step input gives Vout(s) = RIeq s 1 s GB + 1 GB + 1 ∴ L-1[Vout(s)] = vout(t) = RIeq[1 - e-GB·t] µ(t) Error(t) = RIeq - vout(t) ⇒ Error(T) = e-GB·T = 1/28+1 = 1/512 ⇒ eGB·T = 512 If T= 2µs, then GB is given as GB = 0.5x106 ln(512) = 3.119x106 ∴ GB= 0.496MHz (c.) Slew Rate: Want ∆V/∆T = 1V/2µs = 0.5V/µs assuming a ∆V ≈ 1V. ∴ SR = 0.5V/µs CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-12 Problem 10.2-07 What is the necessary relative accuracy of resistor ratios in order for a voltage-scaling DAC to have a 8-bit resolution? Solution Since the voltage scaling DAC has very small DNL errors, let the 8-bit accuracy requirement be determined by the INL error. INL = 2N-1∆RR ≤ 0.5 ∆R 1 2 1 1 → R ≤ 2 2N = 2N = 256 ∆R ∴ R ≤ 0.39% Problem 10.2-08 If the binary controlled switch b1 of Fig. P10.2-3 is closed at t =0, find the time it takes the output to achieve its final stage (-VREF/2) by assuming that this time is 4 times the time constant of this circuit. The differential voltage gain of the op amp is given as 106 Avd(s) = s + 1 0 . Solution The model show will be used for this solution. The transfer function for this problem can be VREF written as, R1Avd(s) Vout(s) Vin(s) = -RR01 R1+R0 R1Avd(s) = -0.5 1 + R1+R0 1 1 0.667x106 1.5 Avd(s) +1 ≈ -0.5 1.5s GB +1 = - 0.5 s+0.667x106 For a step input of magnitude VREF, we can write, t = 0+ R1 = 2R0 R0 vout + Fig. S10.2-08 Vout(s) = -0.5 0.667x106 s+0.667x106 VREF s = -0.51s - 1 s+0.667x106 VREF The inverse Laplace transform gives, vout(t) = -0.5[1-e-0.667x106t]VREF The time constant of this circuit is 1/(0.667x106) = 1.5µs which means that it will take 6µs for the DAC to convert the switch change to the output voltage. ∴ Time for conversion = 6µs. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-13 Problem 10.2-09 What is the necessary relative accuracy of capacitor ratios in order for a charge-scaling DAC to have 11-bit resolution? Solution Perfect DNL will be impossible to achieve so let us use INL to answer the question and see what the DNL is based on the INL. INL = 2N-1 ∆C C ≤ 0.5 ∆C 1 2 1 1 → C ≤ 2 2N = 2N = 2048 ∆C ∴ C ≤ 0.0488% The corresponding DNL = (2N-1) ∆C C ≈ ±1LSB CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-14 Problem 10.2-10 For the charge scaling DAC of Fig. 10.2-10, investigate the influence of a load capacitor, CL, connected in parallel with the terminating capacitor. (a.) Find an expression for vOUT as a function of C, CL, the digital bits, bi, and VREF. (b.) What kind of static error does CL introduce? (c.) What is the largest value of CL/C possible before an error is introduced in this DAC? Solution φ1 VREF C C 2 C 4 S0 S1 S2 φ2 φ2 φ2 C C C 2N-2 2N-1 2N-1 SN-2 SN-1 φ2 φ2 + CL - vOUT Terminating Capacitor Fig. S10.2-10 (a.) Charge conservation gives, CTotalvOUT = b0C + C b1 2 + C b2 4 + ··· + C b N - 22N-2 + b N - C 12N-1 VREF where CTotal = 2C + CL. vOUT = 2 C C + CL b 0 + b1 2 + b2 4 + ··· + bN-2 2N-2 + b2NN--11 VREF ∴ vOUT = 1 1 CL + 2C b20 + b1 4 + b2 8 + ··· + bN-2 2N-1 + b N2N- 1 VREF (b.) If CL << 2C, then vOUT ≈ 1 - CL 2C b20 + b1 4 + b2 8 + ··· + bN-2 2N-1 + b N2N- 1 VREF which introduces a gain error. (c.) From the previous result, the error term can be written as, CL 2C b20 + b1 4 + b2 8 + ··· + bN-2 2N-1 + bN2N- 1 VREF ≤ 1 2 VREF 2N = 0.5 LSB CL C ≤ 2N b20 + b1 4 + b2 8 1 + ··· + bN-2 2N-1 + bN2N- 1 1 ≈ 2N when all bits are 1 and N > 1. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-15 Problem 10.2-11 Express the output of the D/A converter shown in Fig. P10.2-11 during the φ2 period as a function of the digital bits, bi, the capacitors, and the reference voltage, VREF. If the op amp has an offset of VOS, how is this expression for the output changed? What kind of error will the op amp offset cause? n iΣ=1bi2n-iC = Cx φ1 C 2C 2n-2 C 2n-1 C 2nC bn bn bn-1 bn-1 b2 b2 b1 b1 + φ2 φ1 VOS φ1 b0 b0 φ2 b0 b0 -+ vOUT + VREF - Solution VOS = 0: Cx b0 = 1: vOUT = - 2nC VREF ∑ i=1 bi2n2-iC n vOUT = - 2nC VREF (b0 = 1) b0 = 0: Reverse φ1 and φ2 to get, ∑ vO U T =+ i =1 n bi 2i V R E F VREF φ1Figure s1C0.x2-11A 2nC - φ2 + vOUT Fig. S10.2-11B → ∑ vO U T =- i =1 n bi 2i V R E F (b0 = 0) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-16 Problem 10.2-11 – Continued VOS ≠ 0: At φ2 we have, From this circuit, we can write that, Cx(VREF -VOS) = 2nC(VOS – VOS – vOUT) or Cx vOUT = - 2nC (VREF – VOS) VREF ∴ ∑ vO U T = - i = 1 n bi 2i ( V R E F – VOS) and ∑ v O U T = + i = 1 n bi 2i ( V R E F – VOS) VOS causes a gain error. Cx 2nC +VOS- vOUT - + -+ VOS Fig. S10.2-11C (b0 = 1) (b0 = 0) CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-17 Problem 10.2-12 Develop the equivalent circuit of Fig. 10.2-11 from Fig. 10.2-10. Solution For each individual capacitor connected only to VREF we can write, C C C Vout = VREF 2C , Vout = VREF 4C , Vout = VREF 8C , ….. Note that the numerator consists only of the capacitances connected to VREF . If these capacitors sum up to Ceq. then the remaining capacitors must be 2C - Ceq. Therefore, we have, VREF Ceq + Vout 2C-Ceq - S10.2-12 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-18 Problem 10.2-13 If the tolerance of the capacitors in the 8-bit, binary-weighted array shown in Fig. P10.213 is ±0.5%, what would be the worst case DNL in units of LSBs and at what transition does it occur? C φ1 b1 C 2 φ2 b2 C 4 φ2 b3 C 8 φ2 b4 C 16 φ2 b5 C 32 φ2 b6 C 64 φ2 b7 C 128 φ2 b8 C 128 φ2 + vOUT - VREF Solution Figure P10.2-13 The worst case DNL occurs at the transition form 01111111 to 10000000. +DNL: Ceq Ideally, vOUT = 2C-Ceq + Ceq VREF. The worst case is found by assuming that all of the Ceq capacitors are maximu and the 2C-Ceq capacitors are minimum. However, for the above transition, the maximum, worst case positive step can be written as Max. step = vOUT (10000000) – vOUT(01111111) = VREF1.0205 - 0 . 99 2 51 - 1 128 = VREF 2 1 .005 - 0.9951 - 1 128 VREF = 2 [1.005 – 0.995(0.9922)]VREF = 0.008887VREF An LSB = VREF/256 = 0.003906VREF 0.008887 ∴ +DNL = 0.003906 - 1 = 2.275 - 1 = 1.275 LSB -DNL: For this case, let the Ceq capacitors be minimum and the 2C-Ceq capacitors be maximum. Following the same development as above gives, Min. step = vOUT (10000000) – vOUT(01111111) = VREF0.9295 - 1 . 00 2 51 - 1 128 = VREF 2 0 .995 - 1.0051 - 1 128 VREF = 2 [0.995 – 1.005(0.9922)]VREF = -0.001074VREF ∴ -0.001074 -DNL = 0.003906 - 1 = -0.2750 - 1 = -1.275 LSB CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-19 Problem 10.2-14 A binary weighted DAC using a charge amplifier is shown. At the beginning of the digital to analog conversion, all capacitors are discharged. If a bit is 1, the capacitor is connected to VREF and if the bit is 0 the capacitor is connected to ground. a.) Design CX to get vOUT = b21 + b2 4 + ··· + b2NN VREF . VREF C vOUT 2C CX 2N-1C + F97E1P2 b.) Identify the switches by bi where i = 1 is the MSB and i = N is the LSB. c.) Find the maximum component spread (largest value/smallest value) for the capacitors. d.) Is this DAC fast or slow? Why? e.) Can this DAC be nonmonotonic? f.) If the relative accuracy of the capacitors are 0.2% (regardless of capacitor sizes) what is the maximum value of N for ideal operation? Solution a.) Solving for vOUT gives vOUT = CCX + 2C CX + ··· + 2 N-1C CX VREF , therefore CX = 2NC vOUT = 1 2N + 1 2N-1 + ··· + 12VREF b.) See schematic for switch identification. which gives c.) The maximum component spread is CX/C which is Max. component spread = 2N˚ d.) This DAC should be fast because there are no floating nodes. e.) Yes, the DAC can be nonmonotonic. f.) Let Ceq be all capacitors connected to VREF. ∴ vout Ceq VREF = - Cx . For the worst case, let Ceq be Ceq + ∆Ceq and Cx be Cx - ∆Cx which gives vout’ VREF = - Ceq+∆Ceq Cx-∆Cx = - Ceq Cx 11+-∆∆CCexq//CCxeq = - Ceq Cx 1+0.002 1-0.002 = - Ceq Cx 501 499 ∴ VvRoEutF - VvoRuEt’F = Ceq Cx + 540919CCexq = 2 499 Ceq Cx ≤ 1 2N+1 The largest value of Ceq/Cx is (2N-1)/2N. 2 2N 1 ∴ 499 ≤ (2N-1)(2N+1) = 2N ⇒ (Note that N is almost equal to 8.) N=7 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-20 Problem 10.2-15 A binary weighted DAC using The circuit shown is an equivalent for the operation of a DAC. The op amp differential voltage gain, Avd(s) is modeled as Avd(0) ωa GB Avd(s) = s + ω a = s + ω a . a.) If ωa goes to infinity so that Avd(s) ≈ Avd(0), what is the minimum value of Avd(0) that will cause a ±0.5 LSB error for an 8-bit DAC? b.) If Avd(0) is larger than the value found in a.), what is the minimum conversion time for an 8-bit DAC which gives a ±0.5 LSB error if GB = 1Mhz? Solution a.) Model for the circuit: vi = C C+C vREF + C C+C vOUT vIN and vOUT = -Avi -A A ∴ vOUT = 2 vOUT - 2 vREF -A ⇒ vOUT 2 vREF = 1 + A 2 C +C vi - -Avi vOUT Setting the actual gain to -1±0.5LSB gives -0.5A 1+0.5A = -1 - 1 1 2256 -511 = 512 ⇒ 512A 511A - 2 = -511 - 2 A = 1022 ⇒ A 2 = 511 ⇒ b.) If Avd(s) ≈ -GB/s, then the s-domain transfer function can be written as Vout(s) -GB/2 -ωH VREF = s + G B / 2 = s + ω H ⇒ ωH = 2π·106 2 = π·106 The time domain output can be written as vout(t) = -1[1 - e-ωHt]VREF Setting vout(t) = -1±0.5LSB and solving for the time, T, at which this occurs gives -1 + e-ωHT = -1 + 1 512 ⇒ eωHT = 512 ⇒ ωHT = ln(512) ⇒ 6.283 T = 3.1416x106 or T = 1.9857µs CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-21 Problem 10.2-16 A charge-scaling DAC is shown in Fig. P10.2-16 that uses a C-2C ladder. All capacitors are discharged during the φ1 phase. (a.) What value of CF is required to make this DAC work correctly? (b.) Write an expression for vOUT during φ2 in terms of the bits, bi, and the reference voltage, VREF. (c.) Discuss at least two advantages and two disadvantages of this DAC compared to other types of DACs. Solution -VREF -VREF/2 -VREF/4 -VREF/8 VREF φ1 2C φ1 2C φ1 2C φ1 C φ2 C C C C b0 b1 b2 b3 φ1 - CF + vOUT (a.) C F = 2 C (b.) vOUT = b20VREF +b21VR2EF + b2VREF 2 4 + b3VREF 2 8 Fig. S10.2-16 vOUT = b0 2 + b1 4 b2 +8 + b136V R E F (c.) Advantages: 1.) Smaller area than binary-weighted DAC. 2.) Better accuracy because the components differ by only 2:1. 3.) Autozeros the offset of the op amp. Disadvantages: 1.) Has floating nodes and is sensitive to parasitics. 2.) Parasitic capacitances at the floating nodes will deteriorate the accuracy. 3.) Can be nonmonotonic. 4.) Requires a two-phase, non-overlapping clock. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-22 Problem 10.3-01 The DAC of Fig. 10.3-1 has m = 2 and k = 2. If the divisor has an incorrect value of 2, express the ±INL and the ±DNL in terms of LSBs and determine whether or not the DAC is monotonic. Repeat if the divisor is 6. Solution The general form for the output of this DAC is, vOUT b0 b1 b2 b3 VREF = 2 + 4 + 2k + 4k k = 2: vOUT b0 b1 b2 b3 VREF = 2 + 4 + 4 + 8 The result is: B0 B1 B2 B3 Ideal Actual Ideal DNL Actual DNL Ideal INL Actual INL 0 0 0 0 0.00000 0.00000 - - 0.00000 0.00000 0 0 0 1 0.06250 0.12500 0.00000 1.00000 0.00000 1.00000 0 0 1 0 0.12500 0.25000 0.00000 1.00000 0.00000 2.00000 0 0 1 1 0.18750 0.37500 0.00000 1.00000 0.00000 3.00000 0 1 0 0 0.25000 0.25000 0.00000 -3.00000 0.00000 0.00000 0 1 0 1 0.31250 0.37500 0.00000 1.00000 0.00000 1.00000 0 1 1 0 0.37500 0.50000 0.00000 1.00000 0.00000 2.00000 0 1 1 1 0.43750 0.62500 0.00000 1.00000 0.00000 3.00000 1 0 0 0 0.50000 0.50000 0.00000 -3.00000 0.00000 0.00000 1 0 0 1 0.56250 0.62500 0.00000 1.00000 0.00000 1.00000 1 0 1 0 0.62500 0.75000 0.00000 1.00000 0.00000 2.00000 1 0 1 1 0.68750 0.87500 0.00000 1.00000 0.00000 3.00000 1 1 0 0 0.75000 0.75000 0.00000 -3.00000 0.00000 0.00000 1 1 0 1 0.81250 0.87500 0.00000 1.00000 0.00000 1.00000 1 1 1 0 0.87500 1.00000 0.00000 1.00000 0.00000 2.00000 1 1 1 1 0.93750 1.12500 0.00000 1.00000 0.00000 3.00000 ∴ INL = +3LSB and 0 LSB. DNL = +1LSB and –3LSB. Nonmontonic because DNL < 1L S B. k = 6: vOUT b0 b1 b2 b3 VREF = 2 + 4 + 12 + 24 The result is on the next page: CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-23 Problem 10.3-01 – Continued B0 B1 B2 B3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Ideal 0.00000 0.06250 0.12500 0.18750 0.25000 0.31250 0.37500 0.43750 0.50000 0.56250 0.62500 0.68750 0.75000 0.81250 0.87500 0.93750 Actual 0.00000 0.04167 0.08333 0.12500 0.25000 0.29167 0.33333 0.37500 0.50000 0.54167 0.58333 0.62500 0.75000 0.79167 0.83333 0.87500 Ideal DNL Actual DNL - - 0.00000 -0.33333 0.00000 -0.33333 0.00000 -0.33333 0.00000 1.00000 0.00000 -0.33333 0.00000 -0.33333 0.00000 -0.33333 0.00000 1.00000 0.00000 -0.33333 0.00000 -0.33333 0.00000 -0.33333 0.00000 1.00000 0.00000 -0.33333 0.00000 -0.33333 0.00000 -0.33333 Ideal INL Actual INL 0.00000 0.00000 0.00000 -0.33333 0.00000 -0.66667 0.00000 -1.00000 0.00000 0.00000 0.00000 -0.33333 0.00000 -0.66667 0.00000 -1.00000 0.00000 0.00000 0.00000 -0.33333 0.00000 -0.66667 0.00000 -1.00000 0.00000 0.00000 0.00000 -0.33333 0.00000 -0.66667 0.00000 -1.00000 ∴ INL = +0LSB and -1 LSB. > -0.333LSB. DNL = +1LSB and –0.333LSB. Montonic because DNL CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-24 Problem 10.3-02 Repeat Problem 10.3-1 if the divisor is 3 and 5. Solution k=3: vOUT = b0 2 + b1 4 VREF + b2 2 + b 3 VREF 4 3 = b0 2 + b1 4 + b2 6 + b3 12 VREF B0 B1 B2 B3 Ideal Actual Ideal DNL Actual DNL Ideal INL Actual INL 0 0 0 0 0.00000 0.00000 - - 0.00000 0.00000 0 0 0 1 0.06250 0.08333 0.00000 0.33333 0.00000 0.33333 0 0 1 0 0.12500 0.16667 0.00000 0.33333 0.00000 0.66667 0 0 1 1 0.18750 0.25000 0.00000 0.33333 0.00000 1.00000 0 1 0 0 0.25000 0.25000 0.00000 -1.00000 0.00000 0.00000 0 1 0 1 0.31250 0.33333 0.00000 0.33333 0.00000 0.33333 0 1 1 0 0.37500 0.41667 0.00000 0.33333 0.00000 0.66667 0 1 1 1 0.43750 0.50000 0.00000 0.33333 0.00000 1.00000 1 0 0 0 0.50000 0.50000 0.00000 -1.00000 0.00000 0.00000 1 0 0 1 0.56250 0.58333 0.00000 0.33333 0.00000 0.33333 1 0 1 0 0.62500 0.66667 0.00000 0.33333 0.00000 0.66667 1 0 1 1 0.68750 0.75000 0.00000 0.33333 0.00000 1.00000 1 1 0 0 0.75000 0.75000 0.00000 -1.00000 0.00000 0.00000 1 1 0 1 0.81250 0.83333 0.00000 0.33333 0.00000 0.33333 1 1 1 0 0.87500 0.91667 0.00000 0.33333 0.00000 0.66667 1 1 1 1 0.93750 1.00000 0.00000 0.33333 0.00000 1.00000 From the above table, INL = +1LSB and –0LSB, DNL = +0.33LSB and –1LSB. The DAC is on the threshold of nonmonotonicity. k=5: vOUT = b0 2 + b1 4 VREF + b2 2 + b 3 VREF 4 5 = b0 2 + b1 4 + b2 10 + b3 20 VREF B0 B1 B2 B3 Ideal Actual Ideal DNL Actual DNL Ideal INL Actual INL 0 0 0 0 0.00000 0.00000 - - 0.00000 0.00000 0 0 0 1 0.06250 0.05000 0.00000 -0.20000 0.00000 -0.20000 0 0 1 0 0.12500 0.10000 0.00000 -0.20000 0.00000 -0.40000 0 0 1 1 0.18750 0.15000 0.00000 -0.20000 0.00000 -0.60000 0 1 0 0 0.25000 0.25000 0.00000 0.60000 0.00000 0.00000 0 1 0 1 0.31250 0.30000 0.00000 -0.20000 0.00000 -0.20000 0 1 1 0 0.37500 0.35000 0.00000 -0.20000 0.00000 -0.40000 0 1 1 1 0.43750 0.40000 0.00000 -0.20000 0.00000 -0.60000 1 0 0 0 0.50000 0.50000 0.00000 0.60000 0.00000 0.00000 1 0 0 1 0.56250 0.55000 0.00000 -0.20000 0.00000 -0.20000 1 0 1 0 0.62500 0.60000 0.00000 -0.20000 0.00000 -0.40000 1 0 1 1 0.68750 0.65000 0.00000 -0.20000 0.00000 -0.60000 1 1 0 0 0.75000 0.75000 0.00000 0.60000 0.00000 0.00000 1 1 0 1 0.81250 0.80000 0.00000 -0.20000 0.00000 -0.20000 1 1 1 0 0.87500 0.85000 0.00000 -0.20000 0.00000 -0.40000 1 1 1 1 0.93750 0.90000 0.00000 -0.20000 0.00000 -0.60000 From the above table, INL = +0LSB and –0.6LSB, DNL = +0.6LSB and –0.2LSB. The DAC is monotonic. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-25 Problem 10.3-03 Repeat Problem 1 if the divisor is correct (4) and the VREF for the MSB subDAC is 0.75VREF and the VREF for the LSB subDAC is 1.25VREF.) Soluiton The analog output can be written as, vOUT = b0 2 + b 1 3VREF 4 4 + b2 2 + b 3 5VREF 4 4 = 3b0 8 + 3b1 16 + 5b2 32 + 5b3 64 VREF B0 B1 B2 B3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Ideal 0.00000 0.06250 0.12500 0.18750 0.25000 0.31250 0.37500 0.43750 0.50000 0.56250 0.62500 0.68750 0.75000 0.81250 0.87500 0.93750 Actual Ideal DNL Actual DNL Ideal INL Actual INL 0.00000 - - 0.00000 0.00000 0.07813 0.00000 0.25000 0.00000 0.25000 0.15625 0.00000 0.25000 0.00000 0.50000 0.23438 0.00000 0.25000 0.00000 0.75000 0.18750 0.00000 -1.75000 0.00000 -1.00000 0.26563 0.00000 0.25000 0.00000 -0.75000 0.34375 0.00000 0.25000 0.00000 -0.50000 0.42188 0.00000 0.25000 0.00000 -0.25000 0.37500 0.00000 -1.75000 0.00000 -2.00000 0.45313 0.00000 0.25000 0.00000 -1.75000 0.53125 0.00000 0.25000 0.00000 -1.50000 0.60938 0.00000 0.25000 0.00000 -1.25000 0.56250 0.00000 -1.75000 0.00000 -3.00000 0.64063 0.00000 0.25000 0.00000 -2.75000 0.71875 0.00000 0.25000 0.00000 -2.50000 0.79688 0.00000 0.25000 0.00000 -2.25000 From the above table, INL = +0.75LSB and –3LSB, DNL = +0.25LSB and –1.75LSB. The DAC is not monotonicity. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-26 Problem 10.3-04 Find the worst case tolerance of x (∆x/x) in % that will not cause a conversion error for the DAC shown. Assume that all aspects of the DAC are ideal except for x. (Note: that the divisor is 1/x so that x is less than 1.) Solution VREF = 1V b1 3-bit b2 MSB b3 DAC VREF = 1V + Σ vOUT + The tolerance is only influenced by the bits of the LSB DAC. The ideal and actual outputs are given as, b4 b 5 b 6 vout(ideal) = x 2 + 4 + 8 b4 3-bit b5 LSB b6 DAC ÷ 1 x Fig. F97E1P1 vout(actual) = (x ± ∆x) b4 2 + b5 4 + b6 8 ∴ Worst case error = |vout(actual) - vout(ideal)| ≤ 1/27 ⇒ ∆x b4 2 + b5 4 + b6 8 ≤ 1 27 = 1 128 The tolerance is decreased if all LSB bits are 1. Therefore, ∆x 7 8 ≤ 1 128 ⇒ ∆x ≤ 8 7 1 128 = 1 112 Therefore, the factor x can be expressed as, x ± ∆x = 1 8 ± 1 112 = 14 112 ± 1 112 The tolerance of x is expressed as ±∆x ± 1 Tolerance of x = x = 14 = ±7.143% CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-27 Problem 10.3-05 The DAC of Fig. 10.3-2 has m = 3 and k = 3. Find (a.) the ideal value of the divisor of VREF designated as x. (b.) Find the largest value of x that causes a 1LSB DNL. (c.) Find the smallest value of x that b0 causes a 2LSB DNL. b1 Solution a.) vOUT = VREFb20 + b1 4 + b2 2k + b3 4k b2 k = 4 for ideal behavior. b3 b.) Let vOUT’ = vOUT when k ≠ 4. Also note that ±1LSB = 1/16 when vOUT is normalized to VREF. ∴ vOUT’ - vOUT 1 VREF = ±16 VREF 2-bit MSB +Σ DAC + VREF/k vOUT 2-bit LSB DAC Fig. S10.3-05 b0 2 + b1 4 + 1 k b2 2 + b 3 4 - b0 2 + b1 4 b2 +8 + b3 16 = 1 k -14+b22 + b3 4 1 = ±16 4 k - 1(2b2 + b3) = ±1→ 4 k = 1 ± 1 2b2 + b3 2b2 + b3±1 = 2b2 + b3 ∴ 4(2b2 + b3) k = 2b2 + b3±1 Try various combinations of b2 and b3: 4 b2 = 0 and b3 = 1 → k = 1±1 = 2, ∞ 88 b2 = 1 and b3 = 0 → k = 2±1 = 3 , 8 12 b2 = 1 and b3 = 1 → k = 3±1 = 4, 6 The smallest, largest value of k that maintains ±1LSB is 6. ∴ k = 6 (k is ideally 4 and the smallest of the maximum values is 6) c.) For DNL, the worst case occurs from X011 to X100. ∴ vOUT(X100)-vOUT(X011) VREF/16 –1 = ±2 1 4 - 1 2k 1 +4k 12 = 16 ±16 → 12 4 - k = 1±2 → 12 k = 3-(±2) 12 k = 3-(±2) = 12 or 2.4 ∴ k = 2.4 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-28 Problem 10.3-06 Show for the results of Ex. 10.3-2 that the resulting INL and DNL will be equal to –0.5LSB or less. Solution Consider only the LSBs because the error in the division factor only affects the LSB subDAC. INL: The worst case INL occurs when both b3 and b4 are on. Therefore, 1 2 + 1 6±1 4 24 = 36±1 4 24 = 6±1 5 32 = 32, 7 32 INL+(max) = Vo(actual) - Vo(ideal) = 7 32 - 6 32 = 1 32 = +0.5LSB INL-(max) = Vo(actual) - Vo(ideal) = 5 32 - 6 32 = -1 32 = -0.5LSB Therefore, the worst case INL is equal to or less than ±0.5LSB. DNL: The worst case DNL occurs when both bits of the LSB subDAC change from 1 to 0. This corresponds to a change from 0011 to 0100. If the scaling factor is 7/24 corresponding to the +1/24 tolerance, then 51 5 8 3 ∆Vo = Vo(0011) -Vo(0100) = 32 - 4 = 32 - 32 = 32 DNL+ = ∆Vo - 2 32 = 3 32 - 2 32 = 1 32 = +0.5LSB If the scaling factor is 5/24 corresponding to the -1/24 tolerance, then 71 7 8 1 ∆Vo = Vo(0011) -Vo(0100) = 32 - 4 = 32 - 32 = 32 DNL- = ∆Vo - 2 32 = 1 32 - 2 32 = -1 32 = -0.5LSB Therefore, the worst case DNL is equal to or less than ±0.5LSB. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-29 Problem 10.3-07 A 4-bit, digital-analog converter is shown in Fig. P10.3-7. When a bit is 1, the switch pertaining to that bit is connected to the op amp negative input terminal, otherwise it is connected to ground. Identify the switches by the notation b1, b2, b3, or b4 where bi corresponds to the ith bit and b1 is the MSB and b4 is the LSB. Solve for the value of Rx which will give proper digital-analog converter performance. MSB LSB vOUT R b0 b1 b2 b3 - I0 VREF I1 2R I2 4R Rx 2R I3 4R 4R + Vx S10.3-07 Solution VREF I0 I0 I0 For this circuit to operate properly, I0 = 2R , I1 = 2 , I2 = 4 , and I3 = 8 . VREF To achieve this result, Vx = - 4 . The equivalent resistance seen to ground from the right of Rx can be expressed as, REQ = 2R||(4R||4R) = 2R||2R = R ∴ R VREF Vx = R+Rx (-VREF) = - 4 ∴ Rx = 3R CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-30 Problem 10.3-08 Assume R1=R5=2R, R2=R6=4R, R3=R7=8R, R4=R8=16R and that the op amp is ideal. (a.) Find the value of R9 and R10 in terms of R which gives an ideal 8-bit digital-to-analog converter. (b.) Find the range of values of R9 in terms of R which keeps the INL ≤ ±0.5LSB. Assume that R10 has its ideal value. Clearly state any assumption you make in working this problem. (c.) Find the range of R10 in terms of R which keeps the converter monotonic. Assume that R9 has its ideal value. Clearly state any assumptions you make in working this problem. Solution (a.) R 8 = 16R and R 9 = R (b.) vOUT = VREFb20 + b1 4 + b2 8 + b3 16 + R R8 VREFb24 + b5 4 + b6 8 + b7 16 The worst case INL occurs when the bits in the MSB subDAC are zero and the bits in the LSB subDAC are one. ∴ vOUT = R R8 VREFb24 + b5 4 + b6 8 + b7 16 1 vOUT(ideal) = 16 VREFb24 + b5 4 + b6 8 + b7 16 ∴ INL = vOUT - vOUT(ideal) =VREFb24 + b5 4 + b6 8 + b7 R 16 R8 - 1 16 = 1 +2 VREF 256 512(0.9375)RR8 - 1 16 =1 → R R8 = 0.064583 → R8 = 15.4838R Also, INL = vOUT - vOUT(ideal) =VREFb24 + b5 4 + b6 8 + b7 R 16 R8 - 1 16 = - 1 2 VREF 256 512(0.9375)RR8 - 1 16 = -1 → R R8 = 0.060417 → R8 = 16.5517R ∴ 15.4838R ≤ R8 ≤ 16.5517R (c.) Worst case monotonicity occurs when the bits of the LSB subDAC go from 1 to 0. vOUT(LSBs =1) = VREF 16 1 2 + 1 4 + 1 8 + 1 16 = VREF 16 15 16 vOUT(b3=1, all others 0) = VREF R R9 1 16 Nonmonotonicity ⇒ VREF R R9 1 16 > VREF 16 15 16 → 15 R 9 < 16 R CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-31 Problem 10.3-09 Design a ten-bit, two-stage charge-scaling D/A converter similar to Fig. 10.3-4 using two five-bit sections with a capacitive attenuator between the stages. Give all capacitances in terms of C, which is the smallest capacitor of the design. Solution The result is shown below. C 16 VREF 2C C 16 C 8 C 4 C 2 C 32 C 16 C 8 C 4 C 2 C b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 + vout - Fig. S10.3-09 The design of the connecting capacitor, Cs, is done as follows, C 1 16 = 1 1 → Cs + 2C 1 1 16 Cs +2C = C 1 32 1 31 → Cs = 2C - 2C = 2C 2C ∴ Cs = 31 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-32 Problem 10.3-10 A two-stage, charge-scaling D/A converter is shown in Fig. P10.3-10. (a.) Design Cx in terms of C, the unit capacitor, to achieve a 6-bit, two-stage, charge-scaling DAC. (b.) If Cx is in error by ∆Cx, find an expression for vOUT in terms of Cx, ∆Cx, bi and VREF. (c.) If the expression for vOUT in part (b.) is given as ∑ ∑ vOUT = VREF 8 1˚-˚17∆Cx 100Cx 3 bi23-i˚+˚1˚+˚180∆CCxx˚ 6 ˚bi26-i 8 i=1 i=4 what is the accuracy of Cx necessary to avoid an error using worst case considerations. Cx Ceq + vOUT C C 2C 4C C 2C 4C - b5 b4 b3 b2 b1 b0 + VREF (The switch designated by bi is connected to VREF the ith bit is "1" and ground if the ith bit is "0".) if - Fig. S10.3-10 Solution (a.) The value of Ceq. must be C. Therefore, 11 1 C = Cx + 8C 17 8C → Cx = 8C → Cx = 7 (b.) The model for the analysis is found by using Thevenin’s equivalent circuits and is , Cx + ∆Cx vOUT 8C 7C 2 ∑bi22-i vr = 7 VREF i=0 vl vr 5 ∑ bi25-i vl = 8 VREF Fig. S10.3-10B i=3 vOUT 1 1 8C + Cx+∆Cx = 81C + 1 7C + Cx+1∆Cx vr + 81C + 1 7C 1 7C + Cx+1∆Cx vl CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-33 Problem 10.3-10 – Continued vOUT 1 1 8C + Cx(1+∆Cx/Cx ) = 81C + 1 7C + 1 Cx(1+∆C x/Cx ) vr + 81C + 1 7C + 1 7C 1 Cx(1+∆C x/Cx ) vl 8C Let Cx = 7 and ∆Cx Cx =ε ∴ vOUT 1 8C + 7 1 8C1+ε = 81C + 1 7C + 87C11+ε vr + 81C + 1 7C 1 7C + 87C11+ε vl 1 Assume that 1+ε ≈ 1-ε to get, vOUT ≈ 18 1 8 + + 1 7 7 8 + 7ε -8 7 7ε 8- 8 vr + 18 + 1 7 1 7 + 7 8 - 7ε 8 vl = 1 1 + 7ε -8 1 7ε 7- 8 vr + 1 + 1 7 1 7- 7ε 8 vl vOUT 7 = 8 - 4 98ε 4 98ε vr + 8 - 1 4 9ε 8 71 vl = 81 - 49ε 56 49ε 64 1 vr + 49ε 81 - 64 vl vOUT 7 1 = 8 1 - 49ε 56 49ε 64 v r + vl 71 - 4596ε ≈ 781 + 49 64 - 4569ε v r + 1 71 + 49ε 56 vl ∑ ∑ 7 7ε 2 bi22-i 1 49ε vOUT = 81- 64 7 V R E F + 71 + 56 i=0 5 bi25-i i=3 8 V R E F ∴ ∑ ∑ VREF 7ε vOUT = 8 1- 64 2 bi22-i + 1 + 7ε 8 i=0 5 bi25-i i=3 8 (c.) The error due to ∆Cx should be less than ±0.5LSB. Worst case is for all bits 1. ∴ - 17∆Cx 100Cx + 8 ∆ Cx 10Cx 7VREF 8 ≤ VREF 2N+1 VREF = 128 → ∆ Cx Cx ≤ 1.685% CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-34 Problem 10.3-11 If the op amps in the circuit below have a dc gain of 104 and a dominant pole at 100Hz, at what clock frequency will the effective number of bits (ENOB) = 7bits assuming that the capacitors and switches are ideal? Use a worst case approach to this problem and assume that time responses of the LSB and MSB stages add to give the overall conversion time. + VREF - C b5 b5 φ2 C/2 b6 b6 φ2 C/4 b7 b7 φ2 C/8 b8 b8 φ2 φ1 vO1 2C - + A1 - VREF + C/8 b1 C b1 φ2 C/2 b2 b2 φ2 C/4 b3 b3 φ2 C/8 b4 b4 φ2 φ1 2C + A2 + vOUT - LSB Array MSB Array F97FEP3 Solution The worst case approach assumes that all capacitors are switched into the op amp input and that both stages can be modelled approximately as shown. With a single pole model for the op amp, it can be shown that the -3dB frequency is given as follows where C1 = C2 gives the lowest -3dB frequency. t=0 2C VREF 2C vout(t) + F97FES3 ωH = GB·C2 C1+C2 = GB 2 = πx106 radians/sec ∴ vout(t) = (C1/C2)[1 - e-ωH t]VREF ENOB of 7 bits ⇒ 1 VREF VREF ±2 27 = ± 28 VREF vout(T) = VREF - 28 ∴ 1 - 1 28 = 1 - e-ωHT ⇒ eωHT = 28 ⇒ 8 8 T = ωΗ ln(2) = πx106 0.693 = 1.765µs 1 Double this time for 2 stages to Tclock = 3.53µs ⇒ fclock = Tclock = 283kHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-35 Problem 10.3-12 The DAC shown uses two identical, 2-bit DACs to achieve a 4-bit D/A converter. Give an expression for vOUT as a function of VREF and the bits, b1, b2, b3, and b4 during the φ2 phase period. The switches controlled by the bits are closed if the bit is high and open if the bit is low during the φ2 phase period. If k = 2, express the INL (in terms of a ±LSB value) and DNL (in terms of a ±LSB value) and determine whether the converter is monotonic or not. (You may use the output-input plot on the next page if you wish.) Solution During the φ2 phase the DAC can be modeled as: VREF VREF b1C 2 b2C C - vOUT vOUT (φ2) = b1 2 + b2 4 + 1 k b2 2 + b 4 4 VREF 4 + If k = 2, then VREF b3C 2 vOUT(φ2) b1 b2 b3 b4 VREF = 2 + 4 + 4 + 8 VREF b4C 4 S01E3S3 Input Digital Word 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Output for k = 4 0 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 Output for k = 2 0 2/16 4/16 6/16 4/16 6/16 8/16 10/16 8/16 10/16 12/16 14/16 12/16 14/16 16/16 18/16 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-36 Problem 10.3-12 – Continued Analog Output (Normalized to Full Scale) 16/16 15/16 14/16 13/16 Actual 4-bit DAC Characteristic 12/16 11/16 10/16 9/16 8/16 7/16 6/16 5/16 4/16 3/16 2/16 Ideal 4-bit DAC 1/16 characteristic 0/16 b1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Digital Input Code S01E3S3B The INL is +3LSB and –0LSB. The DNL is +1LSB and –3LSB. Converter is definitely not monotonic. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-37 Problem 10.3-13 An N-bit DAC consists of a voltage scaling DAC of M-bits and a charge scaling DAC of K-bits (N=M+K). The accuracy of the resistors in the M-bit voltage scaling DAC is –∆R/R. The accuracy of the binary-weighted capacitors in the charge scaling DAC is –∆C/C. Assume for this problem that INL and DNL can be expressed generally as, INL = Accuracy of component x Maximum weighting factor DNL = Accuracy of the largest component x Corresponding weighting factor where the weighting factor for the i-th bit is 2N-i+1. (a.) If the MSB bits use the M-bit voltage scaling DAC and the LSB bits use the K-bit charge scaling DAC, express the INL and DNL of the N-bit DAC in terms of M, K, N, ∆R/R, and ∆C/C. (b.) If the MSB bits use the K-bit charge scaling DAC and the LSB bits use the M-bit voltage scaling DAC, express the INL and DNL of the N-bit DAC in terms of M, K, N, ∆R/R, and ∆C/C. Solution (a.) In a M-bit voltage scaling DAC, there are 2M resistors between VREF and ground. The (2M-i)R voltage at the bottom of the i-th resistor from the top is vi = (2M-i)R + i R VREF where the iR resistors are above vi and the 2M-i resistors are below vi. The worst case INL(R) for the voltage scaling DAC is found at the midpoint where i = 2M-1 and the resistors below are all maximum positive and the resistors above are all maximum negative. Thus, 2M-1(R+∆R)VREF VREF ∆R INL(R) = v2M-1(actual) - v2M-1(ideal) = 2M-1(R+∆R) + 2M-1(R-∆R) - 2 = 2R or INL(R) = 2M 2M ∆R 2R = 2 M -1 ∆R R LSBs The worst case DNL(R) for the voltage scaling DAC is found as the maximum step size minus the ideal step size. Thus, (R±∆R)VREF R ±∆R DNL(R) = vstep(actual) - vstep(ideal) = 2MR - 2MR VREF = 2MR VREF or DNL(R) = ± ∆R VR 2MR E F22NN = ±2N 2M ∆R R = ±2K ∆R R LSBs Let us now examine the INL(C) and the DNL(C) of a K-bit binary-weighted capacitor array. The ideal output for the i-th capacitor is given as vOUT(ideal) = C/2i-1 2C VREF = VREF 2i 2K 2K 2K = 2i LSBs The actual wors-case output for the i-th capacitor is given as (C±∆C)/2i-1 VREF ∆C·VREF 2K 2K∆C vOUT(actual) = 2C VREF = 2i ± 2iC = 2 i ± 2iC LSBs CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-38 Problem 10.3-13 — Continued Therefore, the INL due to the binary-weighted capacitor array is 2K∆C 2K-i∆C INL(C) = vOUT(actual) - vOUT(ideal) = ± 2iC = ± C LSBs 2K-1∆C The worst case occurs for i = 1 which gives I N L (C ) = ± C L S B s Finally, the worst case DNL due to the binary-weighted capacitor array is found as 2K-1∆C 2K-1∆C 2K∆C DNL(C) = vOUT(1000….) - vOUT(0111….) = C + C = C LSBs The INL when the MSBs use voltage scaling and the LSBs use charge scaling is, INL = INL(R) + INL(C) = 2M - 1∆R R + 2N -1 ∆C C where the LSB of the charge scaling DAC is now VREF/2N rather than VREF/2K. The DNL when the MSBs use voltage scaling and the LSBs use charge scaling is, DNL = DNL(R) + DNL(C) = 2K ∆R R + 2 K ∆C C = 2 K ∆R R ∆C + C (b.) Fortunately we can use the above results for the case where the MSBs use the charge-scaling DAC and the LSBs use the voltage scaling DAC. For INL(R) the LSB is now VREF/2N. Therefore, 2N ∆R INL(R) = 2N 2R V REF = 2N-1 ∆R R LSBs For the INL(C), K is replaced with N to give, 2N-1∆C INL(C) = ± C LSBs For the DNL(R), the LSB is VREF/2N so that the DNL(R) for part (b.) becomes ±∆R ±∆R DNL(R) = 2NR VREF = R L S B s ) Since the MSB for the chage scaling DAC is now N, the DNL(C) becomes 2N∆C DNL(C) = C L S B s Combining the above results gives the INL and DNL for the case where the MSBs use the charge scaling DAC and the LSBs use the voltage DAC. The result is, INL = 2N-1 ∆R R + ∆C C LSBs and DNL = 2 N-1 ∆C C + ∆R R LSBs CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-39 Problem 10.3-14 Below are the formulas for INL and DNL for the case where the MSB and LSB arrays of an digital-to-analog converter are either voltage or charge scaling. n = m+k, where m is the number of bits of the MSB array and k is the number of bits of the LSB array and n is the total number of bits. Find the values of n, m, and k and tell what type of DAC (voltage MSB and charge LSB or charge MSB and voltage LSB) if ∆R/R = 1% and ∆C/C = 0.1% and both the INL and DNL of the DAC combination should each be 1LSB or less. DAC Combination INL (LSBs) DNL (LSBs) MSB voltage (m-bits) LSB charge (k-bits) 2n-1∆RR + 2k-1∆CC 2k∆RR + (2k-1)∆CC MSB charge (m-bits) LSB voltage (k-bits) Solution MSB voltage, LSB charge: 2m-1∆RR + 2n-1∆CC ∆R R + (2n-1)∆CC 1 ≥ 2n-11100 + 2k-110100 ⇒ 1000 ≥ 10·2n-1 + 2k-1 1 ≥ 2k1100 + (2k-1)10100 ⇒ 1000 ≥ 10·2k + 2k-1 ⇒ 999 11 = 90.8 ≥ 2k ⇒ k=6 Substituting this k into the first equation gives 1000 10 32 = 96.8 ≥ 2n-1 ⇒ n = 7 which gives m = 1 and k = 6. MSB charge, LSB voltage: 1 ≥ 2m-11100 + 2n-110100 ⇒ 1000 ≥ 5·2m + 2n-1 1 ≥ 1 100 + (2n-1)10100 ⇒ 1000 ≥ 10+ 2n-1 ⇒ 991 ≥ 2n ⇒ n = 9 Substituting this n into the first equation gives 1000 5 256 = 148.8 ≥ 2m ⇒ m = 7 which gives n = 9 and k = 2. Therefore, the DAC combination where the MSBs are charge scaling and the LSBs are voltage scaling gives the most bits when both INL and DNL are 1LSB. The number of bits is n = 9 with m = 7 bits of charge scaling for the MSB DAC and k = 2 bits of voltage scaling for the LSB DAC. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-40 Problem 10.3-15 The circuit shown is a double-decoder D/A converter. Find an expression for vX in terms of V1, V2, and VREF when the φ2 switches are closed. If A=1, B=0, C=1, and D=1, will the comparator output be high or low if Vanalog = 0.8VREF? D VREF B C D RR B φ2 C VAnalog A φ1 V2 C D RR D RR 0.25VREF RR 0.75VREF B 0.5VREF B φ1 C V1 A φ2 vx φ1 φ1 C 4 - φ2 + φ2 C 4 vOUT φ1 Solution Figure S10.3-15 At φ2 we have the following equivalent circuit: vAnalog C C C/4 V1 C/4 VREF 4 V2 Summing the currents to zero gives, sC(vAnalog-vx) + sC(-V1-vx) + vx sC 4 -VR4EF - v x sC + 4 (V2 - vx) = 0 or sCvAnalog - CV1 – C VREF 16 + C V2 4 = vx C+C+C4 +C4 Fig. S10.3-15A ∴ vx = C Ctotal v A n a l o g - V1 + V2 4 - V R E F 16 2 2 V2 VREF = 5 vAnalog - 5 V1 + 10 - 16 For ABCD = 1011 → V2 VREF 12VREF 12VREF 4VREF VREF vAnalog- V1 + 4 - 16 = 16 - 16 + 16 - 16 > 0 Since vx > 0, the comparator output will be low. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-41 Problem 10.3-16 A 4-bit, analog-to-digital converter is shown. Clearly explain the operation of this converter for a complete conversion in a clock period-by-clock period manner, where φ1 and φ2 are nonoverlapping clocks generated from the square ware with a period of T (i.e. φ1 occurs in 0 to T/2 and φ2 in T/2 to T, etc.). What will cause errors in the operation of this analog-to-digital converter? VREF R 3 4 VREF R 2 4 VREF R 1 4 VREF R 136VREF 4 R 126VREF 4 R 116VREF 4 R 4 φ2 C B VAnalog A φ1 B φ1 B B V1 A C VT vX φ1 - C D + φ2 D V2 To bit switches Non-overlapping D C two-phase clocks A B C D φ1 φ2 MSB LSB D Figure S10.3-16 Successive approximation register and control logic Square wave T Solution Consider the operation during a φ1-φ2 cycle. The voltage vx can be written in general as, Vanalog V1 V2 1 vx = 2 - 2 + 2 = 2 (Vanalog -V1 + V2) The operation of the ADC will proceed as follows: 1.) Period 1 (0 ≤ t ≤ T): __ _ SAR closes switches A, B , C , and D (1000) to get vx = 1 2 Vanalog - 3 8 V R E F + 1 8 VREF = 1 2 Vanalog - 1 2 V R E F _ If vx > 0, then A = 1. Otherwise, A = 0 (A =1). CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-42 Problem 10.3-16 – Continued 2.) Period 2 (T ≤ t ≤ 2T): a.) A = 1 _ _ SAR closes switches A,B , C , and D (1100) to get vx = 1 2 V an alog - VREF + 1 4 VREF 1 =2 Vanalog - 34VREF _ b.) A = 1 __ _ SAR closes switches A ,B , C , and D (0100) to get vx = 1 2 V analog - 1 2V REF + 1 4 VREF 1 =2 Vanalog - 14VREF _ If vx > 0, the B = 1 (X100). Otherwise, B = 0 (B =1) (X000). 3.) Period 3 (2T ≤ t ≤ 3T): At this point, V1, will not change since A and B are known. _ The SAR closes the appropriate A and B switches and C and D (XX10) to get vx = 1 2 V an alo g - V1+ 2 16 VREF 1 =2 V a n a l o g - V1+ 1 8 VREF _ If vx > 0, then C = 1 (XX10). Otherwise, C = 0 (C = 1) (XX00). 4.) Period 4 (3T ≤ t ≤ 4T): a.) D = 1 SAR closes switches appropriate Aand B switcheds and C, and D (XX11) to get vx = 1 2 V an alo g - V1+ 1 16 VREF _ b.) D = 1 _ SAR closes switches appropriate Aand B switcheds and C, and D (XX10) to get vx = 1 2 V an alo g - V1+ 3 16 VREF _ If vx > 0, then D = 1 (XXX1). Otherwise, D = 0 (D = 1) (XXX0). Sources of error: 1.) Op amp/comparator – gain, GB, SR, settling time (offset not a problem). 2.) Resistor and capacitor matching. 3.) Switch resistance and feedthrough. 4.) Note parasitic capacitances. 5.) Reference accuracy and stability. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-43 Problem 10.4-01 What is vC1 in Fig. 10.4-1 after the following sequence of switch closures? S4, S3, S1, S2, S1, S3, S1, S2, and S1? Solution The plots for vC1/VREF and vC2/VREF are given below. vC1/VREF 1.0 0.75 0.625 0.5 0.25 0 t/T 01234 5678 vC2/VREF 1.0 0.75 0.625 0.5 0.25 0 t/T 01234 5678 Fig. S10.4-01 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-44 Problem 10.4-02 Repeat the above problem if C1 = 1.05C2. Solution In the sharing phase, we have the following equivalent circuit: C1 C2 vout vout(i) = VC1C1+C2 + VC2C1+C2 C1 C2 VC1 VC2 1.05 1 = 2.05 VC1 + 2.05 VC2 = 0.5122VC1 + 0.4878VC2 FigS10.4-02 Sharing Phase (i) VC1(i)/VREF VC2(i)/VREF Vout(i)/VREF 1 0 0 0 2 1 0 0.5112 3 0 0.5122 0.2498 4 1 0.2498 0.6340 Thus, at the end of the conversion, the output voltage is 0.6340VREF rather than the ideal value of 0.6250VREF. Problem 10.4-03 For the serial DAC shown, every time S2 S1 the switch S2 opens, it causes the VREF voltage on C1 to be decreased by 10%. How many bits can this DAC S3 C1 C2 convert before an error occurs assuming worst case conditions and letting VREF = 1V? The analog output is taken across C2. S4 vC2 F97E1P4 Solution Worst case is for all 1’s. i VC1(ideal) VC1(act.) VC2(ideal) VC2(act.) 1 1 2 1 3 1 0.9 0.5 0.45 0.9 0.75 0.675 0.9 0.875 0.7875 VREF 2i+1 0.25 0.125 0.0625 |VC2(ideal) - OK? VC2(act.)| 0.050 Yes 0.0750 Yes 0.0875 No Error occurs at the third bit. Note that the approach is to find the ideal value of VC2 at the ith bit and then find the range that VC2 could have which is ±VREF/2i+1 and still not have an error. If the difference between the magnitude of the ideal value and actual value of VC2 exceeds VREF/2i+1 then an error will occur. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-45 Problem 10.4-04 For the serial, pipeline DAC of Fig. 10.4-3 find the ideal analog output voltage if VREF = 1V and the input is 10100110 from the MSB to the LSB. If the attenuation factors of 0.5 become 0.55, what is the analog output for this case? Solution Ignoring the delay terms,the output of Fig. 10.4-3 can be written as, Vout b1 b2 b3 b4 b5 b6 b7 VREF = b0 + 2 + 4 + 8 + 16 + 32 + 64 + 128 For 10100110 we get, Vout 1 11 1 1 1 1 VREF (ideal) = 1 - 2 + 4 - 8 - 16 + 32 + 64 - 128 128 64 32 16 8 4 2 1 77 = 128 - 128 + 128 - 128 - 128 + 128 + 128 - 128 = 128 = 0.60156 If the attenuation factor is k = 0.55, the output can be re-expressed as, Vout VREF (actual) = kb0 + k2b1 + k3b2+ k4b3+ k5b4+ k6b5+ k7b6+ 88b7 = +0.55 – 0.3025 + 0.1664 – 0.0915 – 0.0503 + 0.0277 + 0.0152 – 0.00837 = 0.3066 Problem 10.4-05 Give an implementation of the pipeline DAC of Fig. 10.4-3 using two-phase, switched capacitor circuits. Give a complete schematic with the capacitor ratios and switch phasing identified. Solution All of the stages can be represented by the following block diagram. 1 vi+1 2 Σ vi z-1 vi = (0.5vi+1 ± biVREF)z-1 which is a summing sample and hold with weighted inputs. A ±biVREF Fig. S10.4-05A possible switched-capacitor realization of the i-th stage (and all stages) is shown below. φ1 vi+1 C 2C vi φ1 φ2 - φ2 + VREF φx φy φ1 φx=φ1 φx=φ2 and and φy=φ2 φy=φ1 if if bi=1 bi=0 Fig. S10.4-5B CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-46 Problem 10.4-06 A pipeline DAC is shown. If k1 = 7/16, k2 = 5/7, and k3 = 3/5 write an expression for vOUT in terms of bi (i = 1, 2, 3) and VREF. Plot the input-output characteristic on the curve shown below and find the largest ±INL and largest ±DNL. Is the DAC monotonic or not? k3 +1 Σ +1 +1 b3 b2 k2 +1 Σ +1 b1 vOUT k1 VREF Analog Output 8/8 Actual 3-bit DAC 7/8 6/8 Ideal 3-bit DAC 5/8 +1LSB INL 4/8 +0.5LSB 3/8 DNL 2/8 -1.5LSB DNL -0.5LSB INL 1/8 Digital Word 000 001 010 011 100 101 110 111 vOUT 0/16 3/16 5/16 8/16 7/16 10/16 12/16 15/16 0/8 00001111 00110011 01010101 Digital Input Solution The output can be written as vOUT = k1(b1+k2(b2+k3b3))VREF = [k1b1 + k1k2b2 + k1k2k3b3]VREF Using the values given gives vOUT = 176b 1 + 17657b 2 + 1765735b3VREF = 176b 1 + 5 16b 2 + 136b3 VREF The values for vOUT for this DAC are shown beside the plot and have been plotted on the outputinput characteristic curve. A summary of the performance is given below. INL: +1LSB, -0.5LSB DNL: +0.5LSB, -1.5LSB DAC is nonmonotonic CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-47 Problem 10.4-07 A pipeline digital-analog converter is shown. When bi is 1, the switch is connected to VREF, otherwise it is connected to ground. Two of the 0.5 gains on the summing junctions are in error. Carefully sketch the resulting digital-analog transfer characteristic on the plot on the next page and identify the INL with respect to the infinite resolution characteristic shown and DNL. The INL and DNL should be measured on the analog axis. +1 z-1 2 Σ +5 z-1 8 Σ +3 8 z-1 Σ z-1 +1 2 Σ vOUT +1 +1 +1 b4 b3 b2 b1 0 + VREF - Figure S10.4-7A Solution Ignoring the delay terms, we can write the output voltage as, vOUT VREF = b4 2 + b 3 5 8 + b 2 3 8 + b 1 1 2 1 3 30 15 = 2b1+ 16b2 + 256b3 + 256b3 128 48 30 15 = 256b1+ 256b2 + 256b3 + 256b3 The performance is summarized in the table below (a plot can be made from the table). B0 B1 B2 B3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Ideal 0.00000 0.06250 0.12500 0.18750 0.25000 0.31250 0.37500 0.43750 0.50000 0.56250 0.62500 0.68750 0.75000 0.81250 0.87500 0.93750 Actual Ideal DNL Actual DNL 0.00000 - - 0.05859 0.00000 -0.06250 0.11719 0.00000 -0.06250 0.17578 0.00000 -0.06250 0.18750 0.00000 -0.81250 0.24609 0.00000 -0.06250 0.30469 0.00000 -0.06250 0.36328 0.00000 -0.06250 0.50000 0.00000 1.18750 0.55859 0.00000 -0.06250 0.61719 0.00000 -0.06250 0.67578 0.00000 -0.06250 0.68750 0.00000 -0.81250 0.74609 0.00000 -0.06250 0.80469 0.00000 -0.06250 0.86328 0.00000 -0.06250 Ideal INL Actual INL 0.00000 0.00000 0.00000 -0.06250 0.00000 -0.12500 0.00000 -0.18750 0.00000 -1.00000 0.00000 -1.06250 0.00000 -1.12500 0.00000 -1.18750 0.00000 0.00000 0.00000 -0.06250 0.00000 -0.12500 0.00000 -0.18750 0.00000 -1.00000 0.00000 -1.06250 0.00000 -1.12500 0.00000 -1.18750 ∴ INL = +0 LSBs, -1.1875LSBs and DNL = +1.1875LSBs, -0.8125LSBs CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-48 Problem 10.4-08 Show how Eq. (10.4-2) can be derived from Eq. (10.4-1). Also show in the block diagram of Fig. 10.4-4 how the initial zeroing of the output can be accomplished. Solution Eq. (10.4-1) can be written as ∑ ∑ ∑ ∑ N N N N bi -1z -i bi -1z -i z 1 bi -1 1 bi -1 Vout = 2i -1 = 2i -1 z = z 2i -1z i -1 = z 2i -1z i -1 i =1 i =1 i =1 i =1 ∑ ∑ N N 1 b i bi 1 =z 2izi = z 2izi i =0 i =0 where all bi have assumed to be identical as stated in the text. The summation can be recognized as a geometric series (assuming N → ∞) to give Vout = bi z 1 1-21z = bi z-1 1-0.5z-1 The output can initially be zeroed by adding a third switch to ground at the summing junction. The S/H will sample the 0V and produce Vout = 0. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-49 Problem 10.4-09 Assume that the amplifier with a gain of 0.5 in Fig. 10.4-4 has a gain error of ∆A. What is the maximum value ∆A can be in Example 10.4-2 without causing the conversion to be in error? Solution Let the amplifier gain be A. Therefore, we can write the output in general as follows. Bit from LSB to MSB 1 0 0 1 1 Vout 1 A-1 A(A-1) + 1 = A2 – A - 1 A[A(A-1) – 1] + 1 = A3 - A2 – A + 1 A{A[A(A-1) – 1] + 1} + 1 = A4 - A3 - A2 + A + 1 19 The ideal output is Vout = 16 ± 0.5LSB 2VREF VREF VREF LSB = 26 = 25 = 32 Assume VREF = 1V, therefore A4 - A3 - A2 + A + 1 ≤ 19 16 1 ± 32 38 = 32 1 ± 32 ∴ The ideal output is 1.18750 and must be between 1.15625 and 1.21875. Below is a plot of the output as a function of A. 1.25 1.2 1.15 Vout VREF 1.1 1.05 +0.5 LSB Limit -0.5 LSB Limit 1 0.95 0 Amin Amax 0.2 0.4 A 0.6 0.8 1 FigS10.4-09 From this plot, we see that A must lie between 0.205 and 0.590 in order to avoid a ±0.5LSB error. ∴ 0.205 ≤ A ≤ 0.590 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-50 Problem 10.4-10 Repeat Example 10.4-2 for the digital word 10101. Solution Let the amplifier gain be A. Therefore, we can write the output in general as follows. Bit from LSB to MSB 1 0 1 0 1 Vout 1 A-1 A(A-1) + 1 = A2 – A + 1 A[A(A-1) + 1] - 1 = A3 - A2 + A - 1 A{A[A(A-1) + 1] - 1} + 1 = A4 - A3 + A2 - A + 1 11 The ideal output is Vout = 16 ± 0.5LSB 2VREF VREF VREF LSB = 26 = 25 = 32 Assume VREF = 1V, therefore A4 - A3 - A2 + A + 1 ≤ 12 16 1 ± 32 22 = 32 1 ± 32 ∴ The ideal output is 0.6875 and must be between 0.65625 and 0.71875. Below is a plot of the output as a function of A. 1 0.95 0.9 0.85 Vout VREF 0.8 0.75 +0.5 LSB Limit 0.7 0.65 -0.5 LSB LimitAmin Amax 0 0.2 0.4 0.6 0.8 1 FigS10.4-09 From this plot, we see that A must lie between 0.41 and 0.77 in order to avoid a ±0.5LSB error. ∴ 0.41 ≤ A ≤ 0.77 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-51 Problem 10.4-11 Assume that the iterative algorithmic DAC of Fig. 10.4-4 is to convert the digital word 11001. If the gain of the 0.5 amplifier is 0.7, at which bit conversion is an error made? +VREF bi = 1 -VREF bi = 0 +1 Σ +1 Sample and hold vOUT 1 Fig. S10.4-11 2 Solution Conversion Bit Ideal Max. Ideal Min. Ideal Result for Gain No. Converted Result = 0.7 1 1(LSB) 1 1.5 0.5 1 (OK) 2 0 -(1/2) -0.25 -0.75 -0.30 (OK) 3 0 -(5/4) -1.1250 -1.375 -1.210 (OK) 4 1 (3/8) 0.4375 0.3125 0.1530 (Error) 5 1 (MSB) (19/16) 0.9062 0.8437 - The max. and min. ideal are found by taking the ideal result and adding and substracting half of the ideal bit for that conversion number. We note from the table that the error occurs in the 4th bit conversion. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-52 Problem 10.4-12 An iterative, algorithmic DAC is shown in Fig. P10.4-12. Assume that the digital word to be converted is 10011. If VREF1 =0.9VREF and VREF2 = -0.8VREF, at which bit does an error occur in the conversion of the digital word to an analog output? VREF1 ith Bit = 1 Σ VREF2 ith Bit = 0 + + Sample and hold circuit vOUT A=0.5 Solution Ideally, the output of the i-th stage should be, vOUT(i) = 0.5 vOUT(i-1) ± biVREF VREF The i-th LSB is given as 2i-1 . In this problem, the output of i-th stage is given as, vOUT(i) = 0.5 vOUT(i-1) + 0.9VREF if bi = 1 and vOUT(i) = 0.5 vOUT(i-1) - 0.8VREF if bi = 0 The performance is summarized in the following table where vOUT(i) is normalized to VREF. Conversion 0.5 LSB Bit vOUT(i) Max. Ideal Min. Ideal Actual No. Converted Ideal vOUT(i) vOUT(i) vOUT(i) 1 0.5 1 1 1.5 0.5 0.9 2 0.25 1 1.5 1.75 1.25 1.35 3 0.125 0 -0.25 -0.125 -0.375 -0.125 4 0.0625 0 -1.125 -1.0625 -1.1875 -0.8625 5 0.03125 1 0.4375 0.46875 0.40625 0.4687 5 An error occurs in the 4th bit conversion since it lies outside the maximum-minimum ideal vOUT(i). Note the 5th bit is okay. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-53 Problem 10.5-01 Plot the transfer characteristic of a 3-bit ADC that has the largest possible differential nonlinearity when the integral nonlinearity is limited to ±1LSB. What is the maximum value of the differential nonlinearity for this case?) Solution A plot is given below showing the upper and lower limits for ±1 LSB INL. The dark line on the plot shows part of the ADC characteristics that illustrates that the maximum DNL is ±2 LSB. Digital Output Code 111 110 101 100 011 010 001 000 0 8 Ideal 3-bit + 1LSB Ideal 3-bit Characteristic +2LSB DNL -2LSB DNL Ideal 3-bit - 1LSB 12 34 5 6 78 88 88 8 8 88 Analog Input Voltage Fig. S10.5-01 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-54 Problem 10.5-2 (a.) Find the ±INL and ±DNL for the 3-bit ADC shown where the INL and DNL is referenced to the analog input voltage. (Use the terminology: INLA and DNLA.) (b.) Find the ±INL and ±DNL for the 3-bit ADC shown where the INL and DNL is referenced to the digital output code. (Use the terminology: INLD and DNLD.) (c.) Is this ADC monotonic or not? Solutions Digital Output Code Infinite Resolution Characteristic 111 Actual 3-bit Characteristic 110 -1 LSB INLD +1 LSB INLA 101 +1 LSB 100 -0.5 LSB DNLA DNLD -2 LSB DNLD 011 010 -1 LSB DNLA 001 +2 LSB INLD -1.5 LSB INLA Ideal 3-bit Characteristic 000 0 1 2 3 4 5 6 7 8 8 88888888 Analog Input Voltage (a.) Refer to the characteristics above: +INLA = 1LSB -INLA = -1.5LSB +DNLA = +0.5LSB -DNLA = -1LSB (b.) Refer to the characteristics above: +INLD = 2LSB -INLD = -1LSB +DNLD = +1LSB -DNLD = -2LSB (c.) This ADC is not monotonic. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-55 Problem 10.5-03 Assume that the step response of a sample-and-hold circuit is vOUT(t) = VI(1 - e-tÆBW) where VI is the magnitude of the input step to the sample-and-hold and BW is the bandwidth of the sample-and-hold circuit in radians/sec. and is equal to 2πMradians/sec. Assume a worst case analysis and find the maximum number of bits this sample-and-hold circuit can resolve if the sampling frequency is 1MHz. (Assume that the sample-and-hold circuit has the entire period to acquire the sample.) Solution To avoid an error, the value of vOUT(t) should be within ±0.5LSB of VI. Since vOUT is always less than VI let us state the requirements as VI - vOUT(T) ≤ VREF 2N+1 ∴ VI - VI(1-e-T·BW) ≤ VREF 2N+1 → VIe-T·BW ≤ VREF 2N+1 → 2N+1 ≤ VI VREF eT·BW The worst case value is when VI = VREF. Thus, 2N+1 ≤ e2π = 535.49 → 2N ≤ 535.49 2 = 267.74 ∴ N =8 Problem 10.5-04 If the aperture jitter of the clock in an ADC is 200ps and the input signal is a 1MHz sinusoid with a peak-to-peak value of VREF, what is the number of bits that this ADC can resolve? Solution Eq. (10.8-1) gives ∆t ≤ VREF 2N+1 2π f 2 VREF 1 = 2N+1πf = 200ps 2N = 1 2·200ps·πMHz 106 = 400π = 756 ln(2N ) = ln(756) ln(756) → N = ln(2) = 9.63 ∴ N = 9bits CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-56 Problem 10.6-01 What is the conversion time in clock periods if the input to Fig. 10.6-2 is 0.25 VREF? Repeat if vin* = 0.7VREF. Solution vin* = 0.25VREF: Nout = NREFx0.25 = 0.25NREF ∴ Clock periods = NREF + 0.25NREF = 1.25NREF vin* = 0.7VREF: Nout = NREFx0.7 = 0.7NREF ∴ Clock periods = NREF + 0.7NREF = 1.7NREF Problem 10.6-02 Give a switched capacitor implementation of the positive integrator and the connection of the input and reference voltage to the integrator via switches 1 and 2 using a two-phase clock. Solution KC C vout φ1 φ2 - vin* φ2 φ1 + VREF Carry Output (when high, connect to VREF) FS10.6-02 From Chapter 9, it can be shown that, vout (t) ≈ K⌡⌠vin* dt or -K⌡⌠VREF dt depending on the carrier output. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-57 Problem 10.7-01 If the sampled, analog input applied to an 8-bit successive-approximation converter is 0.7VREF, find the output digital word. Solution Bit Trial Digital Word DVREF = 0.7VREF > Decoded b0b1b2b3b4b5b6b7 b20+b41+b82+b136+b342+b654+1b268+2b576VREF DVREF? Bit 1 10000000 2 11000000 3 10100000 4 10110000 5 10111000 6 10110100 7 10110010 8 10110011 The digital word is 1 0 1 1 0 0 1 1 0.5VREF 0.75VREF 0.625VREF 0.6875VREF 0.71875VREF 0.703125VREF 0.6953125VREF 0.69921875VREF Yes 1 No 0 Yes 1 Yes 1 No 0 No 0 Yes 1 Yes 1 Problem 10.7-02 A 4-bit, successive approximation ADC Clock is shown. Assume that VREF = 5V. Fill In in the table below when vin = 3V. 4-bit Shift Register (Each clock causes a 1 to shift right.) B1 B2 B3 B4 Successive Approximation Register (If comparator out = 1, keep guess, if comparator out = 0, change guess.) D1 D2 D3 D4 VREF 4-bit DAC Vout - Comparator vin Sample + Output and hold F97E2P1 Clock Period B1B2B3B4 1 1000 2 0100 3 0010 4 0001 Guessed D1D2D3D4 1000 1100 1010 1001 Vout 2.5V 3.75V 3.125V 2.8125V Comparator Output 1 0 0 1 Actual D1D2D3D4 1000 1000 1000 1001 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-58 Problem 10.7-03 For the successive approximation ADC shown in Fig. 10.7-7, sketch the voltage across capacitor C1 (vC1) and C2 (vC2) of Fig. 10.4-1 if the sampled analog input voltage is 0.6VREF. Assume that S2 and S3 closes in one clock period and S1 closes in the following clock period. Also, assume that one clock period exists between each successive iteration. What is the digital word out? vi*n + - + VREF - S2 S3 S1 S4 vC1+ vC2 + - C1 - C2 S1 Successive Approx- S2 imation S3 Register S4 plus control circuitry Actual digital word is 1001. i 0 b0 1 b1 2 3 b2 b3 Guess 1 11 101 1001 vGuess 0.5 0.75 0.625 0.5625 Actual 1 1.0 100 1001 Solution vC1/VREF 1.000 0.825 0.750 0.625 Vin* 0.500 0.375 0.250 0.125 0 t/T 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 vC2/VREF 1.000 S2 S1 S3 S2 S1 S2 S1 S3 S2 S1 S3 S1 S2 S1 S3 S2 S1 S3 S1 S3 S1 S2 S1 S3 0.825 0.750 S4 S4 S4 S4 0.625 Vin* 0.500 0.375 0.250 0.125 0 t/T 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Fig. 10.7-03 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-59 Problem 10.7-04 Assume that the input of Example 10.7-1 is 0.8VREF and find the digital output word to 6 bits. Solution b0: Vin (0) = 0.8VREF → b0 = 1 b1: Vin (1) = 2(0.8VREF) – VREF = +0.6VREF → b1 = 1 b2: Vin (2) = 2(0.6VREF) – VREF = +0.2VREF → b2 = 1 b3: Vin (3) = 2(0.2VREF) – VREF = -0.6VREF → b3 = 0 b4: Vin (4) = 2(-0.6VREF) + VREF = -0.2VREF → b4 = 0 b5: Vin (5) = 2(-0.2VREF) + VREF = +0.6VREF → b5 = 1 ∴ Digital output word = 1 1 1 0 0 1 Problem 10.7-05 Assume that the input of Example 10.7-1 is 0.3215VREF and find the digital output word to 8 bits. Solution b0: Vin (0) = 0.3215VREF → b0 = 1 b1: Vin (1) = 2(0.3125VREF) – VREF = -0.357VREF → b1 = 0 b2: Vin (2) = 2(-0.357VREF) + VREF = +0.286VREF → b2 = 1 b3: Vin (3) = 2(0.286VREF) – VREF = -0.428VREF → b3 = 0 b4: Vin (4) = 2(-0.428VREF) + VREF = +0.144VREF → b4 = 1 b5: Vin (5) = 2(0.144VREF) - VREF = -0.712VREF → b5 = 0 b6: Vin (6) = 2(-0.712VREF) + VREF = -0.424VREF → b4 = 0 b7: Vin (7) = 2(-0.424VREF) + VREF = +0.152VREF → b4 = 1 ∴ Digital output word = 1 0 1 0 1 0 0 1 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-60 Problem 10.7-06 Repeat Example 10.7-1 for 8 bits if the gain of two amplifiers actually have a gain of 2.1. Solution 1.50 vin* = 5.00 VREF = 0.3VREF b0: Vin (0) = 0.3VREF → b0 = 1 b1: Vin (1) = 2.1(0.3VREF ) – VREF = -0.37VREF → b1 = 0 b2: Vin (2) = 2.1(-0.37VREF ) + VREF = +0.223VREF → b2 = 1 b3: Vin (3) = 2.1(+0.223VREF ) - VREF = -0.5317VREF → b3 = 0 b4: Vin (4) = 2.1(-0.5317VREF ) + VREF = -0.0634VREF → b4 = 0 b5: Vin (5) = 2.1(-0.0634VREF ) + VREF = +0.86686VREF → b5 = 1 b6: Vin (6) = 2.1(+0.86686VREF ) - VREF = +0.820406VREF → b6 = 1 b7: Vin (7) = 2.1(+0.820406VREF ) - VREF = +0.820406VREF → The ideal digital word for Ex. 10.7-1 is 1 0 1 0 0 1 1 0 We see that the amplifier with a gain of 2.1 causes an error in the 8th bit. b6 = 1 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-61 Problem 10.7-07 Assume that Vin* = 0.7VREF is applied to the pipeline algorithmic ADC of Fig. 10.7-9 with 5 stages. All elements of the converter are ideal except for the multiplier of 2 of the first stage, given as 2(1+ε). (a.) What is the smallest magnitude of ε that causes an error, assuming that the comparator offsets, VOS , are all zero? (b.) Next, assume that the comparator offsets are all equal and nonzero. What is the smallest magnitude of the comparator offsets, VOS, that causes an error, assuming that ε is zero? MSB LSB Vin* VREF ++ VO−S 2(1+ε) z-1 V(1) Σ ±1 +- +- + + VO−S z-1 2Σ Vi-1 VO−S z-1 2 Σ Vi V(2) ±1 V(i)±1 Stage 1 Stage 2 i-th stage Solution Use the following table to solve this problem. ++ VO−S z-1 Stage N Stage No. Bit Converted V(i) V(i) with ε(ι)≠0 (MSB→LSB) 1 1 0.7 0.7 ε(i)* - V(i) with VOS=0 0.7 2 1 0.4 1.4(1+ε)-1 = 0.4+1.4ε -0.286 0.4 3 0 -0.2 2(0.4+1.4ε)−1 = −0.2+2.8ε 0.0714 -0.2 4 1 0.6 2(-0.2+2.8ε)+1 = 0.6+5.6ε -0.107 0.6 5 1 0.2 2(0.6+5.6ε)−1 = 0.2+11.2ε -0.0178 0.2 *ε(i) is calculated by setting V(i) with ε ≠ 0 to zero. From the above table we get the following results: ∴ From the fifth column, we see that the minimum |ε| is 0.0178 (b.) The minimum VOS = ±0.2V. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-62 Problem 10.7-08 The input to a pipeline algorithmic ADC is 1.5V. If the ADC is ideal and VREF = 5V, find the digital output word up to 8 bits in order of MSB to LSB. If VREF = 5.2 and the input is still 1.5V, at what bit does an error occur? Solution The iterative relationship of an algorithmic ADC is, v(i+1) = 2v(i) – biVREF where bi = 1 if bi = “1” and –1 if bi = “0”. Ideal case (VREF=5V): v(i) i 1 1.5 2 -2 3 1 4 -3 5 -1 6 3 7 1 8 -3 bi 2v(i) – biVREF 1 3 - 5 = -2 0 -4 + 5 = 1 1 2 – 5 = -3 0 -6 + 5 = -1 0 -2 + 5 = 3 1 6–5=1 1 2 – 5 = -3 0 Actual case (VREF=5.2V): v(i) i 1 1.5 2 -2.2 3 0.8 4 -3.6 5 -2.0 6 1.2 7 -2.8 8 -0.6 The error occurs at the 7th bit. bi 2v(i) – biVREF 1 3 – 5.2 = -2.2 0 -4.4 + 5.2 = 0.8 1 1.6 – 5.2 = -3.6 0 -7.2 + 5.2 = -2.0 0 -4 + 5.2 = 1.2 1 2.4 – 5.2 = -2.8 0 -5.6 + 5.2 = -0.6 0 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-63 Problem 10.7-09 If Vin* = 0.1VREF, find the digital output of an ideal, 4-stage, algorithmic pipeline ADC. Repeat if the comparators of each stage have a dc voltage offset of 0.1V. Solution Ideal: Stage i Vi-1 Vi-1 > 0? Bit i 1 0.1 Yes 1 2 0.1x2-1.0 = -0.8 No 0 3 -0.8x2+1.0 = -0.6 No 0 4 -0.6x2+1.0 = -0.2 No 0 Offset = 0.1V: Vi = 2Vi-1 - bi VREF + 0.1 Stage i Vi-1 Vi-1 > 0? Bit i 1 0.1 Yes 1 2 0.1x2-1.0+0.1 = -0.7 No 0 3 -0.7x2+1.0+0.1 = -0.3 No 0 4 -0.3x2+1.0+0.1 = +0.5 Yes 1 An error will occur in the 4th bit when Vin* = 0.1VREF and the offset voltage is 0.1V. Problem 10.7-10 Continue Example 10.7-3 out to the 10th bit and find the equivalent analog voltage. Solution vin* = 0.8VREF Va(0) = 2(0.8VREF) = 1.6VREF, 1.6 VREF > VREF ⇒ b0 = 1 Va(1) = 2(1.6VREF -VREF ) = 1.2VREF, 1.2 VREF > VREF ⇒ b1 = 1 Va(2) = 2(1.2VREF -VREF ) = 0.4VREF, 0.4 VREF < VREF ⇒ b2 = 0 Va(3) = 2(0.4VREF + 0) = 0.8VREF, (Note the ADC repeats at every 4 bits) 0.8 VREF < VREF ⇒ b3 = 0 Va(4) = 2(0.8VREF + 0) = 1.6VREF, 1.6 VREF > VREF ⇒ b4 = 1 Va(5) = 2(1.6VREF -VREF ) = 1.2VREF, 1.2 VREF > VREF ⇒ b5 = 1 Va(6) = 2(1.2VREF -VREF ) = 0.4VREF, 0.4 VREF < VREF ⇒ b6 = 0 Va(7) = 2(0.4VREF + 0) = 0.8VREF, 0.8 VREF < VREF ⇒ Repeats again. ∴ The digital output word is 1 1 0 0 1 1 0 0 1 1 0 0 …….. b7 = 0 The analog equivalent is VREF 1 2 + 1 4 + 0 8 + 0 16 + 1 32 + 1 64 + 0 128 + 0 256 + 1 512 + 1 1024 + ···· = 0.79980469VREF CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-64 Problem 10.7-11 Repeat Example 10.7-3 if the gain of two amplifier actually has a gain of 2.1. A S/H va + - VREF vc vb + Σ va > VREF ⇒ vc = VREF vin* va < VREF ⇒ vc = 0 Solution (a.) A = 2.0. Assume VREF = 1V. i va(i) va(i) > VREF? bi 1 2(0.8)=1.6 Yes 1 2 2(0.6)=1.2 Yes 1 3 2(0.2)=0.4 No 0 4 2(0.4)=0.8 No 0 5 2(0.8)=1.6 Yes 1 (b.) A = 2.1. Assume VREF = 1V. i va(i) va(i) > VREF? bi 1 2.1(0.8)=1.68 Yes 1 2 2.1(0.68)=1.428 Yes 1 3 2.1(0.428)=0.8988 No 0 4 2.1(0.8988)=1.88748 Yes 1 5 2.1(0.88748)=1.886371 Yes 1 An error occurs in the 4th bit. VREF vb(i) 0.6 0.2 0.4 0.8 0.6 vb(i) 0.68 0.428 0.8988 0.88748 0.886371 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-65 Problem 10.7-12 An algorithmic ADC is shown below where φ1 and φ2 are nonoverlapping clocks. Note that the conversion begins by connecting vin* to the input of the sample and hold during a φ2 phase. The actual conversion begins with the next phase period, φ1. The output bit is taken at each successive φ2 phase. (a.) What is the 8-bit digital output word if vin* = 0.3VREF? (b.) What is the equivalent analog of the digital output word? (c.) What is the largest value of comparator offset, VOS, before an error is caused in part (a.) if VREF = 1V? φ2 2C φ1 vin* φ2 φ1 C φ2 - C φ1 + S/H +VOS- + Bits - Out Solution φx φy φx VREF φy vC=1: φx=φ2 and φy=φ1 vC vC=0: φx=φ1 and φy=φ2 F97FEP5 (a.) Clock Period Start 1 2 3 4 5 6 7 8 Output of S/H (Normalized to VREF) 0.3V (0.3·2) - 1 = -0.4V (-0.4·2) + 1 = 0.2V (0.2·2) - 1 = -0.6V (-0.6·2) + 1 = -0.2V (-0.2·2) + 1 = 0.6V (0.6·2) -1 = 0.2V (0.2·2) - 1 = -0.6V (-0.6·2) + 1 = -0.2V vC > 0? Digital Output Yes - No 0 Yes 1 No 0 No 0 Yes 1 Yes 1 No 0 No 0 (b.) Vanalog = 1 4 + 1 32 + 1 64 VREF = 0.296875VREF (c.) In part (a.) the output of the S/H never got smaller than ±0.2VREF = ±0.2V. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-66 Problem 10.8-01 Why are only 2N-1 comparators required for a N-bit flash A/D converter? Give a logic diagram for the digital decoding network of Fig. 10.8-1 which will provide the correct digital output word. Solution (See the solution for Problem 10.22 of the first edition) Problem 10.8-02 What are the comparator outputs in order of the upper to lower if V*in is 0.6VREF for the A/D converter of Fig. 10.8-1? Solution The comparator outputs in order from the upper to lower of Fig. 10.8-1 for V*in = 0.6VREF is 1 1 1 0 0 0 0. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-67 Problem 10.8-03 Figure P10.8-3 shows a proposed implementation of the conventional 2-bit flash analog-to- digital converter (digital encoding circuitry not shown) shown on the left with the circuit on the right. Find the values of C1, C2, and C3 in terms of C that will accomplish the function of the conventional 2-bit flash analog-to-digital. Compare the performance of the two approaches from the viewpoints of comparator offset, speed of conversion, and accuracy of conversion assuming a CMOS integrated circuit implementation. VREF VI*N VI*N VREF φ1 φ2 C v1 φ1 3 4 VREF R v1 1 R 2 4 VREF v2 2 ? R 1 4 VREF v3 3 R C1 1 C v2 φ1 C2 2 C v3 φ1 Figure S10.8-3A C3 3 Solution Operation: φ1: C voi φ2: VREF C VREF Ci - +i Vin* Ci vi - voi +i Vin* Fig. S10.8-03B vi(φ2) = (Vin*-VREF)C+CCi + Ci C+Ci Vin* = Vin* - VREFC+CCi 2N-i For the conventional flash ADC, vi = Vin*- 2N VREF. For N = 2, we get 2N-i C ∴ 2N = C+Ci → Ci = i 2N-i C For N = 2, we get C1 = C/3, C2 = C, and C3 = 3C ADC Conv. Flash ADC Proposed ADC Comp. Offset ≤ ±0.5LSB Autozeroed Conv. Speed Fast Faster, comp. is simpler Accuracy Poor Better Other Aspects Equal R’s Unequal C’s, No CMRR problems CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-68 Problem 10.8-04 Two versions of a 2-bit, flash A-D converter are shown in Fig. P10.8-5. Design R1, R2, and R3 to make the right-hand version be equivalent to the left-hand version of the 2-bit flash A-D converter. Compare the performance advantages and disadvantages between the two A-D converters. VREF VIN* R 3 4 VREF 1 R 2 4 VREF 2 R 1 4 VREF 3 R E N C b0 ? O D b1 E R VREFVIN* R v1 R1 1 R v2 R2 2 R v3 R3 3 E N b0 C O D b1 E R Conventional Flash ADC Solution Proposed Flash ADC Figure S10.8-04 For the proposed ADC, the comparators must switch at Vin* = 0.75VREF, 0.5VREF and 0.25VREF for comparators, 1,2, and 3, respectively. ∴ v1 = RR+1R1Vin* - R+RR1VREF = 0 → Vin* = RR1VREF → R1 = (4/3)R v2 = RR+2R2Vin* - R+RR1VREF = 0 → Vin* = RR2VREF → R2 = 2R and v3 = RR+3R3Vin* - R+RR3VREF = 0 → Vin* = RR3VREF → R3 = 4R Comparison: Advantages Disadvantages Conventional Flash ADC Less resistor area Guaranteed monotonic All resistors are equal Vin* does not supply current Faster- Vin* directly connected Sensitive to CM effects High impedances nodes-only a disadvantage if VREF changes. Proposed Flash ADC Insensitive to CM effects Positive input grounded No high impedance nodes, fast More resistor area Can be nonmonotonic Resistor spread of 2N Vin* must supply current More noise because more resistors CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-69 Problem 10.8-05 Part of a 6-bit, flash ADC is shown. The comparators have a dominant pole at 103 radians/sec, a dc gain of 104 a slew rate of 3V/µs, and a binary output voltage of 1V and 0V. Assume that the conversion time is the time required for the comparator to go from its initial state to halfway to is final state. What is the maximum conversion rate of this ADC if VREF = 5V? Assume the resistor ladder is ideal. Solution: The output of the i-th comparator can be found by taking the inverse Laplace transform of, Vout(s) = (s/10A3o) + 1·vin*s-VRi to get, vout(t) = Ao(1 - e-103t)(vin* - VRi). The worst case occurs when VREF 5 vin*-VRi = 0.5VLSB = 27 = 128 ∴ 0.5V = 104(1 - e-103T)(5/128) → 64 5·104 = 1- e-103T or, e-103T = 1 - 64 50,000 = 0.99872 → T = 10-3 ln(1.00128) = 2.806µs ∴ Maximum conversion rate = 1 2.806µs = 0.356x106 samples/second Check the influence of the slew rate on this answer. SR = 3V/µs → ∆V ∆T = 3V/µs → ∆V = 3V/µs(2.806µs) = 8.42V > 1V Therefore, slew rate does not influence the maximum conversion rate. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-70 Problem 10.8-06 A flash ADC uses op amps as comparators. The power supply to the op amps is +5V and ground. Assume that the output swing of the op amp is from ground to +5V. The range of the analog input signal is from 1V to 4V (VREF = 3V). The op amps are ideal except that the output voltage is given as vo = 1000 (vid + VOS) + Acm vcm where vid is the differential input voltage to the op amp, Acm is the common mode gain of the op amp, vcm is the common mode input voltage to the op amp, and VOS is the dc input offset voltage of the op amp. (a.) If Acm = 1V/V and VOS = 0V, what is the maximum number of bits that can be converted by the flash ADC assuming everything else is ideal. Use a worst case approach. (b.) If Acm = 0 and VOS = 40mV, what is the maximum number of bits that can be converted by the flash ADC assuming everything else is ideal. Use a worst case approach. Solution (a.) ∆vo = 5V = 1000∆vid±1vcm Choose vcm = 4V as the worst case. ∴ 5+4 ∆vid = 1000 9 = 1000 ≤ VREF 2N+1 = 3 2N+1 2N+1 ≤ 1000·3 9 → 2N ≤ 500·3 9 = 167 → N =7 (b.) ∆vo = 5V = 1000∆vid±1000·40mV 5-(±1000·40mV) ∆vid = 1000 = 5mV –(±40mV) = 45mV (worst case) 3 ∴ 45mV ≤ 2N+1 → 2N ≤ 3 45mV → 2N ≤ 3000 2·45 = 33.33 ∴ N=5 Problem 10.8-07 For the interpolating ADC of Fig. 10.8-3, find the accuracy required for the resistors connected between VREF and ground using a worst case approach. Repeat this analysis for the eight series interpolating resistors using a worst case approach. Solution All of the resistors must have the accuracy of ±0.5LSB. This accuracy is found as INL = 2N-1 ∆R R < 0.5 If N = 3, then 22 ∆R R < 0.5 ∆R 1 → R < 8 = 12.5% CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-71 Problem 10.8-08 Assume that the input capacitance to the 8 comparators of Fig. 10.8-6 are equal. Calculate the relative delays from the output of amplifiers A1 and A2 to each of the 8 comparator inputs. Solution Solve by finding the equivalent resistance seen from each comparator, Req.(i) This resistance times the input capacitance, C, to each comparator will be proportional to the delay. Req.(1) = 0.25R + R||3R = 0.25R + 0.75R = R Req.(2) = 2R||2R = R Req.(3) = 0.25R + R||3R = 0.25R + 0.75R = R Req.(4) = R Similarly, Req.(5) = R Req.(6) = R Req.(7) = R Req.(8) = R Therefore, τ = Req.(i)C are all equal and all delays are equal. Problem 10.8-09 What number of comparators are needed for a folding and interpolating ADC that has the number of coarse bits as n1 = 3 and the number of fine bits as n2 = 4 and uses an interpolation of 4 on the fine bits? How many comparators would be needed for an equivalent 7-bit flash ADC? Solution n1 = 3 ⇒ 23-1 = 7 n2 = 4 ⇒ 24-1 = 15 Therefore, 21 comparators are needed compared with 27-1 = 127 for a 7-bit flash. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-72 Problem 10.8-10 Give a schematic for a folder having a single-ended output that varies between 1V and 3V, starts at 1V, ends at 1V and passes through 2V six times. Solution See the circuit schematic below. +VREF R 20kΩ V6 R 100µA V5 9V 20kΩ V2 R V1 R Vin Vout 3V V1 100µA V2 100µA V5 100µA + Vout - V6 100µA 2V 1V 0 V1 V2 V3 V4 V5 V6 Vin VREF Fig.S10.8-10 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-73 Problem 10.8-11 A pipeline, ADC is shown in Fig. P10.8-11. Plot the output-input characteristic of this ADC if VREF1 = 0.75VREF, VREF2 = VREF, VREF3 = 0.75VREF, VREF4 = 1.25VREF, and A = 4. Express the INL and the DNL in terms of a +LSB and a -LSB value and determine whether the converter is monotonic or not. (F93E2P2) vin(1) 2-bit ADC + 2-bit DAC -Σ vout(1) vin(2) A 2-bit ADC 2-bit vout(2) DAC VREF1 b0 b1 VREF2 Solution Observations: VREF3 b2 b3 VREF4 ∴ First stage changes at vin(1) = (3/16)VREF, (6/16)VREF, (9/16)VREF and (12/16)VREF. ∴ vout(1) = b20+ b41VREF 3.) Second stage changes at vin(2) = (3/16)VREF, (6/16)VREF, (9/16)VREF and (12/16)VREF. 4.) vin(2) = 4[vin(1) - vout(1)] or vin(1) = (1/4) vin(2) + vout(1) Value of vin(1) where a change b0 b1 vout(1 vin(2) b2 b3 Comments occurs ) 0 00 0 0 0 0 Starting point (1/4)x(3/16)=0.75/16 0 0 0 3/16 0 1 (1/4)x(6/16)=1.50/16 0 0 0 6/16 1 0 (1/4)x(9/16)=2.25/16 0 0 0 9/16 1 1 3/16 0 1 4/16 -4/16 0 0 Stage 1 switches (1/4)x(3/16)+(4/16)=4.75/16 0 1 4/16 3/16 0 1 (1/4)x(6/16)+(4/16)=5.50/16 0 1 4/16 6/16 1 0 6/16 1 0 8/16 -8/16 0 0 Stage 1 switches (1/4)x(3/16)+(8/16)=8.75/16 1 0 8/16 3/16 0 1 9/16 1 1 12/16 -12/16 0 0 Stage 1 switches (1/4)x(3/16)+(12/16)=12.75/16 1 1 12/16 3/16 0 1 (1/4)x(6/16)+(12/16)=13.50/16 1 1 12/16 6/16 1 0 (1/4)x(9/16)+(12/16)=14.25/16 1 1 12/16 9/16 1 1 Plot is on the next page. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-74 Problem 10.8-11- Continued 1111 1110 1101 1100 1011 1010 +2.0 LSB DNL +3 LSB INL Digital Output Voltage 1001 1000 0111 0110 0101 0 LSB DNL 0100 0011 -1 LSB INL 0010 0001 0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Analog Input Word Fig. S10.8-11A INL: +3LSB and –1 LSB DNL: +2LSB and 0LSB The ADC is monotonic The ADC has missing codes which are 0111, 1010, and 1011 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-75 Problem 10.8-12 A pipeline, ADC is shown below. Plot the output-input characteristic of this ADC if VREF1 = VREF2 = 0.75VREF and all else is ideal (VREF3 = VREF4 = VREF and A = 4). Express the INL and the DNL in terms of a +LSB and a -LSB value and determine whether the converter is monotonic or not. vin(1) 2-bit ADC + 2-bit DAC -Σ vin(2) A 2-bit ADC 2-bit vout(2) DAC vout(1) S01FEP1 VREF1 b1 b2 VREF2 VREF3 b3 b4 VREF4 Solution 3 6 9 12 The first stage changes when vin(1) = 16 VREF, 16 VREF, 16 VREF, and 16 VREF. 4 8 12 16 The second stage changes when vin(2) = 16 VREF, 16 VREF, 16 VREF, and 16 VREF. Therefore, vin(1) b1 b2 vout(1) vin(2) = 4vin(1)–4vout(1) b3 b4 0 0 0 0 0 0 0 1/16 0 0 0 4/16 = 1/4 0 1 2/16 0 0 0 8/16 = 2/4 1 0 3/16 0 1 3/16 12/16-12/16 = 0 0 0 4/16 0 1 3/16 16/16-12/16 = 4/16 0 1 5/16 0 1 3/16 20/16-12/16 = 8/16 1 0 6/16 1 0 6/16 24/16-24/16 = 0 0 0 7/16 1 0 6/16 28/16-24/16 = 4/16 0 1 8/16 1 0 6/16 32/16-24/16= 8/16 1 0 9/16 1 1 9/16 36/16-36/16 0 0 10/16 1 1 9/16 40/16-36/16 = 4/16 0 1 11/16 1 1 9/16 44/16-36/16 = 8/16 1 0 12/16 1 1 9/16 48/16-36/16 12/16 1 1 13/16 1 1 9/16 52/16-36/16 = 16/16 1 1 14/16 1 1 9/16 56/16-36/16 = 20/16 1 1 15/16 1 1 9/16 60/16-36/16 = 24/16 1 1 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 10.8-12 - Continued ADC Characteristic Plot: Page 10-76 Digital Output Code 1111 1110 1101 1100 1011 Ideal Finite Characteristic +INL=3LSB 1010 1001 Actual Finite Characteristic 1000 0111 +DNL=1LSB 0110 0101 0100 0011 0010 0001 0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Analog Input Voltage S01FES1 From the above plot we see that: +INL = 3LSB, -INL = 0LSB, +DNL = 1LSB and –DNL = 0LSB (Note that we cannot say that the ADC has –1LSB for –DNL when the ADC saturates.) The ADC is monotonic. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-77 Problem 10.8-13 Repeat Problem 11 if (a.) A = 2 and (b.) A = 6 and all other values of the ADC are ideal. vin(1) 2-bit ADC + 2-bit DAC -Σ vout(1) vin(2) A 2-bit ADC 2-bit vout(2) DAC VREF1 b0 b1 VREF2 Solution (a.) A = 2. Observations: VREF3 b2 b3 VREF4 ∴ First stage changes at vin(1) = (4/16)VREF, (8/16)VREF, and (12/16)VREF. ∴ vout(1) = b20+ b41VREF 3.) 2nd stage changes at vin(2) = (4/16)VREF, (8/16)VREF, and (12/16)VREF. 4.) vin(2) = 2[vin(1) - vout(1)] or vin(1) = (1/2) vin(2) + vout(1) Value of vin(1) where a change b0 b1 vout(1) vin(2) b2 b3 Comments occurs 0 00 0 0 0 0 Starting point (1/2)x(4/16)=2/16 00 0 4/16 0 1 (1/2)x(8/16)=4/16 0 1 4/16 0 0 0 Stage 1 switches (1/2)x(4/16)+(4/16)=6/16 0 1 4/16 4/16 0 1 (1/2)x(8/16)+(4/16)=8/16 1 0 8/16 0 0 0 Stage 1 switches (1/2)x(4/16)+(8/16)=10/16 1 0 8/16 4/16 0 1 (1/2)x(8/16)+(8/16)=12/16 1 1 12/16 0 0 0 Stage 1 switches (1/2)x(4/16)+(12/16)=14/16 1 1 12/16 4/16 0 1 With a gain of 2, the second stage sees vin(2) = 2[vin(1) - vout(1)]. vin(2) will never exceed 0.25VREF before the first stage output brings vin(2) back to zero. As a consequence, b2 is stuck at zero. The plot is on the next page. It can seen from the plot that INL =+0LSB and –2LSB , DNL = +2LSB and –0LSB. The ADC is monotonic. (b.) A = 6. vin(2) = 6[vin(1) - vout(1)] or vin(1) = (1/6) vin(2) + vout(1) Value of vin(1) where a change b0 b1 vout(1) vin(2) b2 b3 Comments occurs 0 00 0 0 0 0 Starting point (1/6)x(4/16)=0.667/16 00 0 4/16 0 1 (1/6)x(8/16) = 1.333/16 00 0 8/16 1 0 (1/6)x(12/16)=2/16 00 0 12/16 1 1 4/16 0 1 4/16 0 0 0 Stage 1 switches (1/6)x(4/16)+(4/16)=4.667/16 0 1 4/16 4/16 0 1 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-78 Problem 10.8-13 – Continued Value of vin(1) where a change b0 b1 vout(1) vin(2) b2 b3 Comments occurs (1/6)x(8/16)+(4/16)=5.333/16 0 1 4/16 8/16 1 0 (1/6)x(12/16)+(4/16)=6/16 0 1 4/16 12/16 1 1 8/16 1 0 8/16 0 0 0 Stage 1 switches (1/6)x(4/16)+(8/16)=8.667/16 1 0 8/16 4/16 0 1 (1/6)x(8/16)+(8/16)=9.333/16 1 0 8/16 8/16 1 0 (1/6)x(12/16)+(8/16)=10/16 1 0 8/16 12/16 1 1 12/16 1 1 12/16 0 0 0 Stage 1 switches (1/6)x(4/16)+(12/16)=12.667/16 1 1 12/16 4/16 0 1 (1/6)x(8/16)+(12/16)=13.333/16 1 1 12/16 8/16 1 0 (1/6)x(12/16)+(12/16)=14/16 1 1 12/16 12/16 1 1 It can seen from the plot below that INL =+1LSB and –0LSB, DNL = ±0LSB. The ADC is monotonic. 1111 1110 1101 1100 A=6 1011 1010 +2 LSB A=4 DNL(A=2) Digital Output Voltage 1001 1000 0111 0110 0101 +1LSB INL(A=6) A=2 -2LSB INL(A=2) 0100 0011 0010 0001 0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Analog Input Word Fig. S10.8-13B CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-79 Problem 10.8-14 For the pipeline ADC shown, the reference voltage to the DAC of the first stage is VREF ± ∆VREF. If all else is ideal, what is the smallest value of ∆VREF that will keep the INLA to within (a.) ±0.5LSB and (b.) ±1LSB? Vin(1) 2-bit ADC Vin(2) 2-bit DAC Σ Vout(1) 2-bit ADC 2-bit Vout(2) DAC Solution VREF VREF±∆VREF b1 b2 VREF VREF 4 b3 b4 4 F98E2P4 Vout(1) = Ideal ± Error = b1 2 + b2 4 VREF b1 ± 2 + b2 4 ∆VREF b1 Vout(2) = Vin(1) - Vout(1) = Vin(1) - 2 + b2 4 VREF b1 ± 2 + b2 4 ∆VREF The second stage switches at VREF/16, 2VREF/16, 3VREF/16, and 4VREF/16. Therefore the LSB is VREF/16. (a.) INLA = ±0.5LSB b1 2 + b2 4 ∆VREF ≤ ±VREF 32 When b1 and b2 are both 1 corresponds to the worst case. ∴ ∆VREF ≤ 4 3 ±VREF 32 = ±VREF 24 (b.) INLA = ±0.5LSB b1 2 + b2 4 ∆VREF ≤ ±VREF 16 ∴ ∆VREF ≤ 4 3 ±VREF 16 = ±VREF 12 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-80 Problem 10.8-15 A 4-bit ADC consisting of two, 2-bit stages (pipes) is shown. Assume that the 2-bit ADC’s and the 2-bit DAC function ideally. Also, assume that VREF = 1V. The ideal value of the scaling factor, k, is 4. Find the maximum and minimum value of k that will not cause an error in the 4-bit ADC. Express the tolerance of k in terms of a plus and minus percentage. VREF VREF VREF vin(1) 2-bit ADC 2-bit DAC + -Σ vout(1) vin(2) k 2-bit ADC Solutions b1 b2 b3 b4 b1 b 2 The input to the second ADC is vin(2) = k vin(1) - 2 + 4 . If we designate this voltage as v’in(2) when k = 4, then the difference between vin(2) and v’in(2) must be less than ±1/8 or the LSB bits will be in error. Therefore: vin(2) - v’in(2) = k vin(1) - k b1 2 + b2 4 - 4 vin(1) + 4 b1 2 + b 2 4 ≤ 1 8 If k = 4 + ∆k, then 4 vin(1)+∆k vin(1)-4 b21+b42-∆kb21+b42-4 vin(1)+4 b1 b2 2 + 4 ≤ 1 8 or ∆ kv i n ( 1 ) - b1 2 + b 2 4 ≤ 1 8 . b1 b 2 The largest value of vin(1) - 2 + 4 is 1/4 for any value of vin(1) from 0 to VREF. Therefore, ∆k 1 4 ≤ 8 ⇒ ∆k ≤ 1/2. Therefore the tolerance of k is ∆k k = ±1 2·4 = ±1 8 ⇒ ±12.5% CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-81 Problem 10.8-16 The pipeline, analog-to-digital converter shown in Fig. P10.8-16 uses two identical, ideal, twobit stages to achieve a 4-bit analog-to-digital converter. Assume that the bits, b2 and b3, have been mistakenly interchanged inside the second-stage ADC. Plot the output-input characteristics of the converter, express the INL and DNL in terms of a +LSB and a -LSB, and determine whether the converter is monotonic or not. Solution vin(1) b0 b1 vout(1) vin(2) b2 b3 0 0 0 0 0 0 0 1/16 0 0 0 1/16 1 0 2/16 0 0 0 2/16 0 1 3/16 0 0 0 3/16 1 1 4/16 0 1 4/16 0 0 0 5/16 0 1 4/16 1/16 1 0 6/16 0 1 4/16 2/16 0 1 7/16 0 1 4/16 3/16 1 1 8/16 1 0 8/16 0 0 0 9/16 1 0 8/16 1/16 1 0 10/16 1 0 8/16 2/16 0 1 11/16 1 0 8/16 3/16 1 1 12/16 1 1 12/16 0 0 0 12/16 1 1 12/16 1/16 1 0 13/16 1 1 12/16 2/16 0 1 14/16 1 1 12/16 3/16 1 1 The plot on the next page shows that the INL = ±1LSB and DNL = +1LSB and –2LSB. The ADC is not monotonic. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-82 Problem 10.8-16 – Continued Digital Output Voltage 1111 1110 1101 1100 1011 1010 1001 -1 LSB INL -2LSB DNL 1000 0111 0110 0101 +1 LSB DNL 0100 0011 0010 0001 +1 LSB INL 0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Analog Input Word Fig. S10.8-16A CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-83 Problem 10.9-01 A first-order, delta-sigma modulator is shown in Fig. P10.9-1. Find the magnitude of the output spectral noise with Vin(z) = 0 and determine the bandwidth of a 10-bit analog-to-digital converter if the sampling frequency, fs, is 10 MHz and k = 1. Repeat for k = 0.5. Solution Vin(z) + Σ - ∆ = rms value of 12 quantization noise + k z-1 +Σ Vout(z) Figure P10.9-1 From the block diagram, we can write, ∆k Vout(z) = 12 + z-1 [Vin(z) - Vout(z)] Solving for Vout(z) gives, Vout(z) = z-z1-1+k ∆ + 12 k Vin(z z-1 ) = z-1 z-1+k ∆ 12 if Vin(z) = 0 ∴ H(z) = z-1 z-1+k → H(ejωT) = ejωT -1 ejωT -1+k = ejωT/2 - e-jωT/2 ejωT/2- e-jωT/2+ke-jωT/2 H(ejωT) = 2j sin(ωT/2) + 2j sin(ωT/2) k[cos(ωT/2) - j cos(ωT/2)] = 2tan(ωT/2) (2-k)tan(ωT/2) - jk Find the bandwidth by setting |H(ejωT)|2 = 0.5. |H(ejωT)|2 = 4tan2(ωT/2) (2-k)2tan2(ωT/2) + k2 = 0.5 → 8 tan2(ωT/2) = (2-k)2 tan2(ωT/2) + k2 tan2(ωT/2)[8 – (2-k)2] = k2 → ωT/2 = tan-1 ω = 2 T tan-1 8 - k (2-k)2 = 2fs tan-1 k 8 - (2-k)2 k2 8 – (2-k)2 For k = 1, ω-3dB = 2fstan-1 1 4 = 0.927x107 rads/ sec → 1.476 MHz For k = 0.5, ω-3dB = 2fstan-1 0.5 9 = 0.411x107 rads/ sec → 0.654 MHz 8- 4 Note that the results are independent of the number of bits because H is the noise transfer function. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-84 Problem 10.9-02 The specification for an oversampled analog-to-digital converter is 16-bits with a bandwidth of 100kHz and a sampling frequency of 10MHz. (a.) What is the minimum number of loops in a Sodini modulator using a 1-bit quantizer (∆=VREF/2) that will meet this specification? (b.) If the Sodini modulator has two loops, what is the minimum number of bits for the quantizer to meet the specification? Solution The general formula for the L-th order Sodini loop is, no = ∆ 12 πL 2fBL+0.5 2L+1 fs (a.) ∆(quantizer) = 0.5VREF and an LSB = VREF 216 ∴ no = ≤ LSB ⇒ VREF 2 12 πL 2L+1 200 L+0.5 10,000 ≤ VREF 216 or 215 12 πL 2L+1 1 L+0.5 50 ≤ 1 ⇒ L≥3 (b.) ∆(quantizer) = VREF 2b , where b = no. of bits ∴ VREF no = 2b π2 12 5 1 2.5 50 ≤ VREF 216 2b ≥ 216π 12 2 5 1 2.5 50 = 4.7237 ∴ b=3 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-85 Problem 10.9-03 Draw a single-ended switched capacitor realization of everything within the dashed box of the delta-sigma modulator. Assume that the output of the 1-bit DAC is ±0.5VREF. Be sure to show the phases of the switches (φ1 and φ2). x(n) + Σ + Σ z-1 -+ Quantizer + - y(n) Solution 1-bit DAC F97FEP6 z-1 Note that the inner loop is equal to 1-z-1 which is a switched capacitor noninverting integrator. Therefore a possible realization of the dashed box is shown below. C x(n) φ1 φ2 0.5C C φ2 - φ1 + + y(n) - φy VREF φxφx φy y(n) = 1: φx=φ2 and φy=φ1 y(n) = 0: φx=φ1 and φy=φ2 F97FES6 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-86 Problem 10.9-04 The modulation noise spectral density of a second-order, 1-bit Σ∆ modulator is given as 4∆ |N(f)| = 12 2 sin2ωτ fs 4 where ∆ is the signal level out of the 1-bit quantizer and fs = (1/τ) = the sampling frequency and is 10MHz. Find the signal bandwidth, fB, in Hz if the modulator is to be used in an 18 bit oversampled ADC. Be sure to state any assumption you use in working this problem. Solution The rms noise in the band 0 to fB can be found as, fB no2 = ⌡⌠|N(f)|2df 0 16∆ 2 2 = 12 fs fB ⌡⌠sin44ωfs df 0 ω 2πf πf Assume that 4fs = 4fs = 2fs << 1 so that sin4 ω ≈ ω 4 fs 4 fs fB ∴ no2 = 8 3 ∆2 fs ⌠ 2πf 4 df ⌡4 fs 8∆ 2 = = 3 fs 1 π4 6fs 4 fB ⌡⌠ 0 f 4 df 0 = 8 3 ∆ 2π 16 4 1 5 fB fs 5 = 8 ∆ 2π 4 15 16 fB 5 fs no = 8 ∆π 2 fB 5/2 15 4 fs Assume that ∆ ≈ VREF. For an 18-bit converter, we get no ≤ VREF 218 = ∆ 218 → 8 ∆π 2 15 4 fB fs 5/2 ≤ ∆ 218 fB fs 5/2 ≤ 15 4 1 8 ∆π 2 218 = 0.555 218 = 2.117x10-6 fB fs ≤ 0.005373 → fB = 53.74 kHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-87 Problem 10.9-05 The noise power in the signal band of zero to fB of a L-th order, oversampling ADC is given as no = ∆ 12 πL 2L+1 2ffsBL+0.5 where fs is the sampling frequency. ∆ = VREF 2b and b is the number of bits of the quantizer. Find the minimum oversampling ratio, OSR (=fs/fB), for the following cases: (a.) A 1-bit quantizer, third-order loop, 16 bit oversampled ADC. (b.) A 2-bit quantizer, third-order loop, 16 bit oversampled ADC. (c.) A 3-bit quantizer, second-order loop, 16 bit oversampled ADC. Solution (a.) no = VREF 2 12 π3 7 2ffsB3.5≤ VREF 216 → ffBs 3.5 ≤ 42 π3218 = 7.9732x10-7 → fB fs ≤ 0.0181 ∴ fs fB = OSR ≥ 55.26 (b.) no = VREF 22 12 π3 7 2ffsB3.5≤ VREF 216 → ffBs 3.5 ≤ 42 π3217= 1.5946x10-6 → fB fs ≤ 0.0221 ∴ fs fB = OSR ≥ 45.33 (c.) no = VREF 23 12 π3 5 2ffsB2.5≤ VREF 216 → ffBs 2.5 ≤ 30 π2215 = 1.6936x10-5 → fB fs ≤ 0.0123 ∴ fs fB = OSR ≥ 81.00 CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-88 Problem 10.9-06 A second-order oversampled modulator is shown below. (a.) Find the noise transfer function, Y(z)/Q(z). (b.) Assume that the quantizer noise spectral density of a 1-bit Σ-∆ modulator (not necessarily the one shown below) is |N(f)| = 2VREF 12 2 sin2 ω fs 2fs where fs = 10MHz and is the sampling frequency. Find the maximum signal bandwidth, fB, in Hz if the Σ-∆ modulator is used in a 16-bit oversampled analog-to-digital converter. z-1Y(z) 1-z-1 1 1-z-1 +Σ + -z-1Y(z) S01FES2 X(z) Q(z) 1 1-z-1 +Σ+ + Σ+ Y(z) -1 z-1Y(z) z-1 Solution (a.) Y(z) = Q(z) + X(z) + z-1Y(z) + 1 1-z-1 -z-1Y(z) - z-1Y(z) 1-z-1 Y(z) = Q(z) + X(z) + z-1Y(z) - z-1 1-z-1 Y(z) - z-1 (1-z-1)2 Y(z) Y(z)1-z-1+ z-1 1-z-1 + z-1 1-2z-1+ z-2 + z-1 -z-2+z-1 (1-z-1)2 = Y(z) (1-z-1)2 = Q(z) + X(z) ∴ Y(z) = (1-z-1)2[Q(z) + X(z)] ⇒ Y(z) Q(z) = (1-z-1)2 (b.) no2 = fB ⌡⌠|N(f)|2df 0 = 4VREF2 12 fB 2 fs ⌡⌠sin4πfsfdf 0 ≈ 2VREF2 3fs fB ⌡⌠πfsf4df 0 fB no2 = 2π4VREF2 3fs5 ⌡⌠f 0 4 df = 2π4VREF2 15fs5 fB5 = 2π4VREF2 15 fB fs 5 no = 2 15 VREFπ2f B fs 5≤ VREF 216 ∴ fB fs 5/2 ≤ 15 1 1 0.2775 2 π2 216 = 216 = 4.234x10-6 fB fs ≤ (4.234x10-6)2/5 = 0.0072 ⇒ fB ≤ 70.909kHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-89 Problem 10.9-07 Find an expression for the output, Yo(z), in terms of the input, X(z), and the quantization noise sources, Q1(z) and Q2(z), for the multi-stage Σ-∆ modulator shown in Fig. P10.9-7. What is the order of this modulator? X(z) + Σ - 1 1-z-1 z-1 + Σ - Q1(z) + + Σ z-1 z-1 +Σ - 1 1-z-1 Q2(z) + + Σ z-1 Y1(z) z-1 + Σ + 1-z-1 Y2(z) Yo(z) Solution First, find Y1(z) and Y2(z). Y 1(z) = Q1(z) + 1 1-z-1 [X (z) – z -1 Y 1(z)] = Q1(z) + X(z) 1-z-1 - z-1Y1(z) 1-z-1 z-1 X(z) Y1(z)1 + 1-z-1 = Q1(z) + 1-z-1 ⇒ Y1(z) = (1-z-1)Q1(z) + X(z) Y2(z) = Q1(z) + 1 1-z-1- z-1 Y 2 (z ) - z-1Y1(z) + z-1 1-z-1 [X(z) - z-1 Y 1 (z ) ] Y2(z)1 + z-1 1-z-1 z-1X(z) z-2Y1(z) z-1Y1(z) = Q2(z) + (1-z-1)2 - (1-z-1)2 - 1-z-1 Y2(z) = (1-z-1)Q2(z) + z-1X(z) 1-z-1 - Y1(z)z - 1 + z-2 1-z-1 Y2(z) = (1-z-1)Q2(z) + z-1X(z) 1-z-1 - z-1Y1(z) 1-z-1 ∴ Yo(z) = z-1Y1(z) + (1-z-1)Y2(z) = z-1(1-z-1)Q1(z) + z-1X(z) + (1-z-1)2Q2(z)+ z-1X(z) - z-1Y1(z) = z-1(1-z-1)Q1(z) + z-1X(z) + (1-z-1)2Q2(z)+ z-1X(z) - z-1(1-z-1)Q1(z) - z-1X(z) Yo(z) = z-1X(z) + (1-z-1)2Q2(z) Therefore, the modulator is second-order. CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-90 Problem 10.9-08 Two ∆Σ first-order modulators are multiplexed as shown below. ∆Σ1 provides its 1-bit quantizer output during clock phase φ1 and ∆Σ2 provides its 1-bit quantizer output during clock phase φ2 where φ1 and φ2 are nonoverlapping clocks. The noise, no, of a general L-loop ∆ Σ modulator is no = ∆ 12 πL 2L+1 2ffSBL+0.5 (a.) Assume that the quantization level for each quantizer is ∆ = 0.5VREF and find the dynamic range in dB that would result if the clock frequency is 100MHz and the bandwidth of the resulting ADC is 1MHz. (b.) What would the dynamic range be in dB if the quantizers are 2-bit? Solution: (a.) If the ∆Σ1 modulator outputs a pulse during φ1 and the ∆Σ2 modulator outputs a pulse during φ2, then two samples occur in 10 ns which is effectively an output pulse rate of 200x106 pulses/sec which corresponds to a sampling rate of 200MHz. Therefore, VREF no = 2 12 π 3 2·100MHz1.5 200MHz = 261.8x10-6VREF ∴ VREF 106 no = 261.8 = 3819.72 ⇒ Dynamic Range = 71.64 dB (11.94bits) (b.) A two-bit quantizer gives ∆ = VREF/4. ∴ VREF no = 4 12 π 3 2·100MHz1.5 200MHz = 130.9x10-6VREF VREF 106 no = 130.9 = 7,639.4 ⇒ Dynamic Range = 77.64 dB (12.94bits) Because no is in rms volts, it is consistent to divide VREF by 2 2 to get (a.) VREF/2 no 2 3819.72 = = 1350.47 → 22 62.61 dB (b.) VREF/2 no 2 7639.4 = = 2700.9 → 22 68.61 dB CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-91 Problem 10.9-09 A first-order, 1-bit, bandpass, ∆ Σ modulator is shown in Fig. P10.9-9. Find the modulation noise spectral density, N(f), and integrate the square of the magnitude of N(f) over the X(z) +Σ bandwidth of interest (f1 to f2) and find + an expression for the noise power, no(f), in the bandwidth of interest in terms of ∆ Q(z) = 1 6fs z-2 + + Σ Y(z) 1 1+z-2 and the oversampling factor M where M = fs/(2fB). What is the value of fB for a 14 bit analog-to-digital converter using this modulator if the sampling frequency, fs, is 10MHz? fB << fo and fs = 4 fo f1 = fo- 0.5fB f2 = fo+0.5fB f1 fo f2 f fs Solution Y(z) = Q(z) + 1 1+z-2 [X(z) + z-2Y(z)] = Q(z) + X(z) 1+z-2 + z-2Y(z) 1+z-2 → Y(z) = (1+z-2)Q(z) + X(z) N(z) = | Y(z)X(z)=0 = (1+z-2)Q(z) → N(f) = N(ejωT) = (1 + e-2ωT)Q(f) N(f) = ejωT ejωT (1 + e-2ωT)Q(f) = ejωT + e-jωT ejωT Q(f) = 2 cos(ωT) ejωT ∆ = 4∆ cos(ωT) e-jωT 6fs 6fs f2 f2 no2(f) = ⌡⌠|N(f|)|2df f1 = ⌠4∆ 2 ⌡ 6fs f1 cos2(ωT)df = ∆2 3fs f2 ⌡⌠[1+ f1 cos(2ωT)]df f2 = ∆2 3fs f2 ⌡⌠ df ∆2 + 3fs ⌡⌠cos4fπs f df f1 f1 = ∆2 3fs ∆ 2 (f2-f1)+ 3fs fs 4π sin4fπs f f2 f1 = ∆2 3fs fB + ∆2 12π sin4πfsf2 - s i n 4πfsf1 ∆2 = 3fs fB + ∆2 12π 2cos2fsπ (f2+ f1 ) sin2fsπ (f2- f 1 ) = ∆2 3fs fB +1∆22πcos4πfsfosin2 πfs f B ∆2 = 3fs fB + ∆2 12π cos(π) 2 sin π fB fs = ∆2 3fs fB - ∆2 12π 2 sin πfs f B no2(f) ≈ ∆2 3fs fB - ∆2 12π 2 πfs f B - 1 6 2 πfs f B 2 + · · · ≈ ∆2 3fs fB - ∆2 3fs fB + ∆ 2π 36 2 fB fs 2 no2(f) = ∆ 2π 36 2 fB2 fs → no(f) = ∆ 6 π 2fB fs ≤ ∆ 214 ∴ 2fB fs ≤ 6 214 2/3 π = 0.003095 0.003095 ⇒ fB ≤ 2 x10MHz = 15.47kHz CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 10-92 Problem 10.9-10 A first-order, 1-bit, bandpass, delta-sigma Q(z) = ∆ modulator is shown. Find the modulation 6fs noise spectral density, N(f), and integrate square of the magnitude of N(f) over the the X(z) + I(z) Σ + Σ z-1 O(z) + +Σ Y(z) bandwidth of interest (f1 to f2) and find an +- expression for the noise power, no(f), in the z-1 bandwidth of interest in terms of ∆ and the oversampling factor M where M = fs/(2fB). z-1 What is the value of fB for a 12 bit analog-todigital converter using this modulator if the f1=fo-0.5fB f2=fo+0.5fB fB<

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