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M15T1G1664A (2C) datasheet

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  • 日期: 2017-11-09
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标签: M15T1G1664A

M15T1G1664A

(2C)

(2C)

DDR

DDR=Double Data Rate双倍速率同步动态随机存储器。严格的说DDR应该叫DDR SDRAM,人们习惯称为DDR,其中,SDRAM 是Synchronous Dynamic Random Access Memory的缩写,即同步动态随机存取存储器。

M15T1G1664A  (2C)  datasheet

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ESMT M15T1G1664A 2C DDR3L SDRAM 8M x 16 Bit x 8 Banks DDR3L SDRAM Feature cid1 Interface and Power Supply cid1 Signal Synchronization cid2 SSTL135 VDDVDDQ 135V0067V01V cid2 Write Leveling via MR settings cid2 SSTL15 VDDVDDQ 15V0075V cid2 Read Leveling via MPR cid1 JEDEC DDR3L Compliant cid2 8n Prefetch Architecture cid2 Differential Clock CK CK and Data Strobe DQS DQS cid2 Doubledata rate on DQs DQS and DM cid1 Data Integrity cid2 A......

ESMT M15T1G1664A (2C) DDR3(L) SDRAM 8M x 16 Bit x 8 Banks DDR3(L) SDRAM Feature (cid:1) Interface and Power Supply (cid:1) Signal Synchronization (cid:2) SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) (cid:2) Write Leveling via MR settings (cid:2) SSTL_15: VDD/VDDQ = 1.5V(±0.075V) (cid:2) Read Leveling via MPR (cid:1) JEDEC DDR3(L) Compliant (cid:2) 8n Prefetch Architecture (cid:2) Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) (cid:2) Double-data rate on DQs, DQS and DM (cid:1) Data Integrity (cid:2) Auto Refresh and Self Refresh Modes (cid:1) Power Saving Mode (cid:2) Partial Array Self Refresh(PASR) (cid:2) Power Down Mode (cid:1) Signal Integrity (cid:1) Programmable Functions (cid:2) CAS Latency (5/6/7/8/9/10/11/12/13) (cid:2) CAS Write Latency (5/6/7/8/9) (cid:2) Additive Latency (0/CL-1/CL-2) (cid:2) Write Recovery Time (5/6/7/8/10/12/14/16) (cid:2) Burst Type (Sequential/Interleaved) (cid:2) Burst Length (BL8/BC4/BC4 or 8 on the fly) (cid:2) Self Refresh Temperature Range(Normal/Extended) (cid:2) Output Driver Impedance (34/40) (cid:2) On-Die Termination of Rtt_Nom(20/30/40/60/120) (cid:2) On-Die Termination of Rtt_WR(60/120) (cid:2) Precharge Power Down (slow/fast) (cid:2) Configurable DS for system compatibility (cid:2) Configurable On-Die Termination (cid:2) ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) Ordering Information Product ID Max Freq. VDD Data Rate (CL-tRCD-tRP) Package Comments M15T1G1664A–BDBG2C 800MHz 1.35V/1.5V DDR3(L)-1600 (11-11-11) 96 ball BGA Pb-free M15T1G1664A–DEBG2C 933MHz 1.35V/1.5V DDR3(L)-1866 (13-13-13) 96 ball BGA Pb-free Elite Semiconductor Memory Technology Inc Publication Date : Mar. 2017 Revision : 1.1 1/140 ESMT Description M15T1G1664A (2C) The 1Gb Double-Data-Rate-3(L), DDR3(L) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration # of Bank Bank Address Auto precharge BL switch on the fly Row Address Column Address Page size M15T1G1664A 8 BA0 – BA2 A10 / AP A12 / BC A0 – A12 A0 – A9 2KB Note: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: Page size = 2 COLBITS * ORG / 8 where COLBITS = the number of column address bits ORG = the number of I/O (DQ) bits Elite Semiconductor Memory Technology Inc Publication Date : Mar. 2017 Revision : 1.1 2/140 ESMT M15T1G1664A (2C) Pin Configuration – 96 balls BGA Package < TOP View> See the balls through the package 1 2 3 4 5 6 7 8 9 VDDQ DQU5 DQU7 DQU4 VDDQ VSS VSSQ VDD VSS DQSU DQU6 VSSQ VDDQ DQU3 DQU1 DQSU DQU2 VDDQ VSSQ VDDQ DMU DQU0 VSSQ VDD VSS VSSQ DQL0 DML VSSQ VDDQ VDDQ DQL2 DQSL DQL1 DQL3 VSSQ VSSQ DQL6 DQSL VDD VSS VSSQ VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ NC VSS RAS CK VSS NC ODT VDD CAS CK VDD CKE NC CS WE A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET NC NC A8 VSS A B C D E F G H J K L M N P R T Elite Semiconductor Memory Technology Inc Publication Date : Mar. 2017 Revision : 1.1 3/140 ESMT Input / Output Functional Description M15T1G1664A (2C) Function Symbol CK, CK  Type Input CKE Input Clock: CK and CK sampled on the crossing of the positive edge of CK and negative edge of CK . are differential clock inputs. All address and control input signals are  Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must maintain to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK , ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during Self-Refresh. CS Input Chip Select: All commands are masked when CS is registered high. CS provides for external rank selection on systems with multiple memory ranks. CS is considered part of the command code. RAS , CAS , WE Input Command Inputs: RAS , CAS and WE (along with CS ) define the command being entered. DM, (DMU, DML) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. BA0 - BA2 Input Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. A10 / AP Input A0 – A12 Input Auto-Precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Address Inputs: Provide the row address for Activate commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/ BC have additional function as below.) The address inputs also provide the op-code during Mode Register Set commands. A12/ BC Input Burst Chop: A12/ BC is sampled during Read and Write commands to determine if burst chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped). ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3(L) SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS . The ODT pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT. Elite Semiconductor Memory Technology Inc Publication Date : Mar. 2017 Revision : 1.1 4/140 ESMT Symbol Type M15T1G1664A (2C) Function RESET Input Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V DQ (DQL, DQU) Input/output Data Inputs/Output: Bi-directional data bus. DQS, DQS (DQSL, DQSL , Input/output DQSU, DQSU ) Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. The data strobes DQS (DQSL, DQSU) are paired with differential signals DQS ( DQSL , DQSU ), respectively, to provide differential pair signaling to the system during both reads and writes. DDR3(L) SDRAM supports differential data strobe only and does not support single-ended. NC VDDQ VDD VSSQ VSS - No Connect: No internal electrical connection is present. Supply DQ Power Supply: 1.35V -0.067V/+0.1V & 1.5V ± 0.075V Supply Power Supply: 1.35V -0.067V/+0.1V & 1.5V ± 0.075V Supply DQ Ground Supply Ground VREFCA VREFDQ Supply Reference voltage for CA Supply Reference voltage for DQ ZQ Supply Reference pin for ZQ calibration. Note: Input only pins (BA0-BA2, A0-A12, RAS , CAS , WE , CS , CKE, ODT, and RESET ) do not supply termination. Elite Semiconductor Memory Technology Inc Publication Date : Mar. 2017 Revision : 1.1 5/140
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