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www.fairchildsemi.com AN-6076 Design and Application Guide of Bootstrap Circuit for High-Voltage Gate-Drive IC 1. Introduction The purpose of this paper is to demonstrate a systematic approach to design high-performance bootstrap gate drive circuits for high-frequency, high-power, and high-efficiency switching applications using a power MOSFET and IGBT. It should be of interest to power electronics engineers at all levels of experience. In the most of switching applications, efficiency focuses on switching losses that are mainly dependent on switching speed. Therefore, the switching characteristics are very important in most of the high-power switching applications presented in this paper. One of the most widely used methods to supply power to the high-side gate drive circuitry of the high-voltage gate-drive IC is the bootstrap power supply. This bootstrap power supply technique has the advantage of being simple and low cost. However, it has some limitations, on time of duty-cycle is limited by the requirement to refresh the charge in the bootstrap capacitor and serious problems occur when the negative voltage is presented at the source of the switching device. The most popular bootstrap circuit solutions are analyzed; including the effects of parasitic elements, the bootstrap resistor, and capacitor; on the charge of the floating supply application. 2. High-Speed Gate-Driver Circuitry 2.1 Bootstrap Gate-Drive Technique The focus of this topic is the bootstrap gate-drive circuit requirements of the power MOSFET and IGBT in various switching-mode power-conversion applications. Where input voltage levels prohibit the use of direct-gate drive circuits for high-side N-channel power MOSFET or IGBT, the principle of bootstrap gate-drive technique can be considered. This method is utilized as a gate drive and accompanying bias circuit, both referenced to the source of the main switching device. Both the driver and bias circuit swing between the two input voltage rails together with the source of the device. However, the driver and its floating bias can be implemented by low-voltage circuit elements since the input voltage is never applied across their components. The driver and the ground referenced control signal are linked by a level shift circuit that must tolerate the high-voltage difference and considerable capacitive switching currents between the floating high-side and ground-referenced low-side circuits. The high-voltage gate-drive ICs are differentiated by unique level-shift design. To maintain high efficiency and manageable power dissipation, the level-shifters should not draw any current during the on-time of the main switch. A widely used technique for these applications is called pulsed latch level translators, shown in Figure 1. Shoot-through current compensated gate driver VB UVLO PULSE GENERATOR IN HO NOISE RR CANCELLER S Q VS Figure 1. Level-Shifter in High-Side Drive IC 2.2 Bootstrap Drive Circuit Operation The bootstrap circuit is useful in a high-voltage gate driver and operates as follows. When the VS goes below the IC supply voltage VDD or is pulled down to ground (the lowside switch is turned on and the high-side switch is turned off), the bootstrap capacitor, CBOOT, charges through the bootstrap resistor, RBOOT, and bootstrap diode, DBOOT, from the VDD power supply, as shown in Figure 2. This is provided by VBS when VS is pulled to a higher voltage by the high-side switch, the VBS supply floats and the bootstrap diode reverses bias and blocks the rail voltage (the low-side switch is turned off and high-side switch is turned on) from the IC supply voltage, VDD. VDD RBOOT DBOOT VB VDD HO VS COM LO DC SUPPLY Bootstrap charge current path Bootstrap discharge current path RG1 CBOOT Q1 ILOAD LOAD RG2 Q2 Figure 2. Bootstrap Power Supply Circuit © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 www.fairchildsemi.com AN-6076 2.3 Drawback of Bootstrap Circuitry The bootstrap circuit has the advantage of being simple and low cost, but has some limitations. Duty-cycle and on time is limited by the requirement to refresh the charge in the bootstrap capacitor, CBOOT. The biggest difficulty with this circuit is that the negative voltage present at the source of the switching device during turn-off causes load current to suddenly flow in the low-side freewheeling diode, as shown in Figure 3. This negative voltage can be trouble for the gate driver’s output stage because it directly affects the source VS pin of the driver or PWM control IC and might pull some of the internal circuitry significantly below ground, as shown in Figure 4. The other problem caused by the negative voltage transient is the possibility to develop an over-voltage condition across the bootstrap capacitor. The bootstrap capacitor, CBOOT, is peak charged by the bootstrap diode, DBOOT, from VDD the power source. Since the VDD power source is referenced to ground, the maximum voltage that can build on the bootstrap capacitor is the sum of VDD and the amplitude of the negative voltage at the source terminal. DC SUPPLY HIN LIN RBOOT DBOOT VB VDD HO HIN LIN VS CIN COM LO RG1 Q1 High Side OFF CBOOT Ls1 iLoad Ls2 RG2 ifree Q2Freewheeling Path APPLICATION NOTE 2.4 Cause of Negative Voltage on VS Pin A well-known event that triggers VS go below COM (ground) is the forward biasing of the low-side freewheeling diode, as shown in Figure 5. Major issues may appear during commutation, just before the freewheeling diode starts clamping. In this case, the inductive parasitic elements, LS1 and LS2, may push VS below COM, more than as described above or normal steady-state condition. The amplitude of negative voltage is proportional to the parasitic inductances and the turn-off speed, di/dt, of the switching device; as determined by the gate drive resistor, RGATE, and input capacitance, Ciss, of switching device. It is sum of Cgs and Cgd, called Miller capacitance. VCC INPUT CDRV DBOOT VDC IN VDD GND HVIC VB CBOOT Q1 HO A B RGATE VS C LS1 C LS2 GND - VS D1 iLOAD iFree V COUT OUT Figure 5. Step-Down Converter Applications Figure 6 shows the waveforms of the high-side, N-channel MOSFET during turn-off. Figure 3. Half-Bridge Application Circuits A-Point VBS HIN t VS -COM -VS t Freewheeling Figure 4. VS Waveforms During Turn-off © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 B-Point C-Point VGS=B-C Point VDC+VGS,Miller VDC Recovery Time Figure 6. Waveforms During Turn-off www.fairchildsemi.com 2 AN-6076 2.5 Effects in the Undershoot Spike on VS Pin If undershoot exceeds the absolute maximum rating specified in the datasheet, the gate drive IC suffers damage or the high-side output is temporarily unresponsive to input transition as shown in Figure 7 and Figure 8. Figure 7 shows Latch-up case that the high-side output does not changed by input signal. In this case, short-circuit condition occur on external, main, high-side and low-side switches in half-bridge topology. INPUT OUTPUT Latch-Up Problem Figure 7. Waveforms in Case of Latch-up Figure 8 shows Missing case that the high-side output does not responded to input transition. In this case, the level shifter of the high-side gate driver suffers form a lack of the operation voltage headroom. This should be noted, but proves trivial in most applications, as the high-side in not usually required to change state immediately following a switching event. APPLICATION NOTE 2.6 Consideration of Latch-up Problem The most integrated high-voltage gate-drive ICs have parasitic diodes, which, in forward or reverse break-down, may cause parasitic SCR latch-up. The ultimate outcome of latchup often defies prediction and can range from temporary erratic operation to total device failure. The gate-drive IC may also be damaged indirectly by a chain of events following initial overstress. For example, latch-up could conceivably result in both output drivers assuming a HIGH state, causing cross-conduction followed by switch failure and, finally, catastrophic damage to the gate-drive IC. This failure mode should be considered a possible root-cause, if power transistors and/or gate-drive IC are destroyed in the application. The following theoretical extremes can be used to help explain the relationships between excessive VS undershoot and the resulting latch-up mechanism. In the first case, an "ideal bootstrap circuit" is used in which VDD is driven from a zero-ohm supply with an ideal diode feed VB, as shown in Figure 9. When the high current flowing through freewheeling diode, VS voltage is below ground level by high di/dt. This time, latch-up risk appears since internal parasitic diode, DBS of the gate driver ultimately enters conduction from VS to VB, causing the undershoot voltage to sum with VDD, causing the bootstrap capacitor to overcharge, as shown Figure 10. For example, if VDD=15 V, then VS undershoot in excess of 10V forces the floating supply above 25 V, risking breakdown in diode DBS and subsequent latch-up. VDD VB DBS INPUT COM VS Gate Driver Figure 9. Case 1: Ideal Bootstrap Circuits OUTPUT Signal Missing Problem Figure 8. Waveforms in Case of Signal Missing © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 VB VS HIGH VBS GND Figure 10. VB and VS Waveforms of Case 1 www.fairchildsemi.com 3 AN-6076 Suppose that the bootstrap supply is replaced with the ideal floating supply, as shown in Figure 11, such that VBS is fixed under all circumstances. Note that using a low impedance auxiliary supply in place of a bootstrap circuit can approach this situation. This time, latch-up risk appears if VS undershoot exceeds the VBS maximum specified in datasheet, since parasitic diode DBCOM ultimately enters conduction from COM to VB, as shown in Figure 12. VCC VCC VB DBCOM COM VS Gate Driver Figure 11. Case 2: Ideal Floating Supply VB VS VB Below COM GND Figure 12. VB and VS Waveforms of Case 2 A practical circuit is likely to fall somewhere between these two extremes, resulting in both a small increase of VBS and some VB droop below VDD, as shown in Figure 13. VB VS APPLICATION NOTE 2.7 Effect of Parasitic Inductances The amplitude of negative voltage is: VS − COM = −(VRBOOT + VFDBOOT ) − (LS1 + LS2 ) di dt (1) To reduce the slope of current flowing in the parasitic inductances to minimize the derivative terms in Equation 1. For example, if a 10 A, 25 V gate driver with 100nH parasitic inductance switches in 50 ns, the negative voltage spike between VS and ground is 20 V. 3. Design Procedure of Bootstrap Components 3.1 Select the Bootstrap Capacitor The bootstrap capacitor (CBOOT) is charged every time the low-side driver is on and the output pin is below the supply voltage (VDD) of the gate driver. The bootstrap capacitor is discharged only when the high-side switch is turned on. This bootstrap capacitor is the supply voltage (VBS) for the high circuit section. The first parameter to take into account is the maximum voltage drop that we have to guarantee when the high-side switch is in on state. The maximum allowable volt- age drop (VBOOT) depends on the minimum gate drive voltage (for the high-side switch) to maintain. If VGSMIN is the minimum gate-source voltage, the capacitor drop must be: Δ VBOOT = VDD − VF − VGSMIN (2) where: VDD = Supply voltage of gate driver [V]; and VF = Bootstrap diode forward voltage drop [V] The value of bootstrap capacitor is calculated by: CBOOT = QTOTAL ΔVBOOT (3) where QTOTAL is the total amount of the charge supplied by the capacitor. VB close to COM Increased VBS The total charge supplied by the bootstrap capacitor is calcu- GND lated by equation 4.: QTOTAL= QGATE + (ILKCAP+ ILKGS + IQBS + ILK + ILKDIODE) ⋅ tON + QLS (4) Figure 13. Typical Response of VB and VS Exactly which of the two extremes is prevalent can be checked as follows. If the VS pins undershoot spike has a time length that is on order of tenths of nanoseconds; the bootstrap capacitor, CBOOT, can become overcharged and the high-side gate-driver circuit has damage by over-voltage stress because it exceeds an absolute maximum voltage (VBSMAX) specified in datasheet. Design to a bootstrap circuit, that does not exceed the absolute maximum rating of high-side gate driver. where: QGATE = Total gate charge; ILKGS = Switch gate-source leakage current; ILKCAP = Bootstrap capacitor leakage current; IQBS = Bootstrap circuit quiescent current; ILK = Bootstrap circuit leakage current; QLS = Charge required by the internal level shifter, which is set to 3 nC for all HV gate drivers; tON = High-side switch on time; and © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 4 www.fairchildsemi.com AN-6076 ILKDIODED = Bootstrap diode leakage current. The capacitor leakage current is important only if an electrolytic capacitor is used; otherwise, this can be neglected. For example: Evaluate the bootstrap capacitor value when the external bootstrap diode used. Gate Drive IC = FAN7382 (Fairchild) Switching Device = FCP20N60 (Fairchild) Bootstrap Diode = UF4007 VDD = 15 V QGATE = 98 nC (Maximum) ILKGS = 100 nA (Maximum) ILKCAP = 0 (Ceramic Capacitor) IQBS = 120 µA (Maximum) ILK = 50 µA (Maximum) QLS = 3 nC TON = 25 µs (Duty=50% at fs=20KHz) ILKDIODE = 10 nA If the maximum allowable voltage drop on the bootstrap capacitor is 1.0V during the high side switch on state, the minimum capacitor value is calculated by Equation 3. QTotal = (98×10−9 ) + {(100 ×10−9 +120 ×10−6 + 50 ×10−6 +10 ×10−9 ) × (25×10−6 )} + (3×10−9 ) (6) = 105.2×10−9[C] The value of bootstrap capacitor is calculated as follows: CBOOT = QTOTAL ΔVBOOT = 105.2×10−9 1 ≅ 105[nF] (7) The voltage drop due to the external diode is nearly 0.7V. Assume the capacitor charging time is equal to the high-side on-time (duty cycle 50%). According to different bootstrap capacitor values, the following equation applies: ΔV B O O T = -Q----T---O----T---A----LCBOOT (8) 100nF  ΔVBOOT = 1.05 V 150nF  ΔVBOOT = 0.7 V 220nF  ΔVBOOT = 0.48 V 570nF  ΔVBOOT = 0.18 V Suggested values are within the range of 100 nF ~ 570 nF, but the right value must be selected according to the application in which the device is used. When the capacitor value is too large, the bootstrap charging time slows and the low-side on time might be not long enough to reach the bootstrap voltage. APPLICATION NOTE 3.2 Select the Bootstrap Resistor When the external bootstrap resistor is used, the resistance, RBOOT, introduces an additional voltage drop: VRBOOT = ICHARGE • R BOOT t CHARGE (5) where: ICHARGE = Bootstrap capacitor charging current; RBOOT = Bootstrap resistance; and tCHARGE = Bootstrap capacitor charging time (the low-side turn-on time). Do not exceed the ohms (typically 5~10 Ω) that increase the VBS time constant. This voltage drop of bootstrap diode must be taken into account when the maximum allowable voltage drop (VBOOT) is calculated. If this drop is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra-fast recovery diode can be used. 4. Consideration of Bootstrap Application Circuits 4.1 Bootstrap Startup Circuit The bootstrap circuit is useful in high-voltage gate driver, as shown in Figure 1. However, it has a initial startup and limited charging a bootstrap capacitor problem when the source of the main MOSFET (Q1) and the negative bias node of bootstrap capacitor (CBOOT) are sitting at the output voltage. Bootstrap diode (DBOOT) might be reverse biased at startup and main MOSFET (Q1) has a insufficient turn-off time for the bootstrap capacitor to maintain a required charge, as shown in Figure 1. In certain applications, like in battery chargers, the output voltage might be present before input power is applied to the converter. Delivering the initial charge to the bootstrap capacitor (CBOOT) might not be possible, depending on the potential difference between the supply voltage (VDD) and output voltage (VOUT) levels. Assuming there is enough voltage differential between input voltage (VDC) and output voltage (VOUT), a circuit comprised of startup resistor (RSTART), startup diode (DSTART), and Zener diode (DZ) can solve the problem, as shown in Figure 14. In this startup circuit, startup diode DSTART serves as a second bootstrap diode used for charging the bootstrap capacitor (CBOOT) at power up. Bootstrap capacitor (CBOOT) is charged to the Zener diode of DZ, which is supposed to be higher than the driver's supply voltage (VDD) during normal operation. The charge current of the bootstrap capacitor and the Zener current are limited by the startup resistor. For best efficiency, the value of startup resistor should be selected to limit the current to a low value, since the bootstrap path through the startup diode is permanently in the circuit. © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 5 www.fairchildsemi.com AN-6076 VDD RBOOT DBOOT VDC DSTART RSTART INPUT VDD VB HIN HO COM VS CBOOT DZ RGATE Q1 L D COUT VOUT Figure 14. Simple Bootstrap Startup Circuit 4.2 Resistor in Series with Bootstrap Diode In the first option, the bootstrap circuit includes a small resistor, RBOOT, in series with bootstrap diode, as shown in Figure 15. The bootstrap resistor, RBOOT, provides current limit only during a bootstrap charging period which repre- sents when the VS goes below the IC supply voltage, VCC, or is pulled down to ground (the low-side switch is turned on and the high-side switch is turned off). The bootstrap capaci- tor, CBOOT, charge through the bootstrap resistor, RBOOT, and diode, DBOOT, from the VCC power supply. The bootstrap diode must have a break-down voltage (BV) larger than VDC and a fast recovery time to minimize the amount charge feedback from the bootstrap capacitor to VCC power supply. VCC RBOOT DBOOT VDC HIN LIN VCC VB HIN HO LIN VS C1 COM LO R1 CBOOT R3 Q1 R2 Q2 R4 Load APPLICATION NOTE For example, if RBOOT=10, CBOOT=1 µF, and D=10 %; the time constant is calculated in following equation: τ = R-----B---O----O----T----⋅---C----B----O---O----T- = -1---0----⋅---1---–---6 = 100[μs] D 0.1 (10) Even with a reasonably large bootstrap capacitor and resistor, the time constant may be large. This method can mitigate the problem. Unfortunately, the series resistor does not provide a foolproof solution against an over voltage and it slows down the recharge process of the bootstrap capacitor. 4.3 Resistor Between VS and VOUT In the second option, the bootstrap circuit includes a small resistor, RVS, between VS and VOUT, as shown in Figure 16. Suggested values for RVS are in the range of some ohms. VCC VDC RBOOT DBOOT IN CDRV IN VB HVIC VCC HO GND VS CBOOT RGATE RVS Q1 VOUT L1 D1 COUT Figure 16. Adding RVS in Bootstrap Circuit The RVS works as, not only bootstrap resistor, but also turnon and turn-off resistors, as shown in Figure 17. The bootstrap resistor, turn-on, and turn-off resistors are calculated by the following equations: RBOOT∗ = RBOOT + RVS (11) Figure 15. Adding a Series Resistor with DBOOT This method has the advantage of being simple for limiting the current when the bootstrap capacitor is initially charged, but it has some limitations. Duty-cycle is limited by the requirement to refresh the charge in the bootstrap capacitor, CBOOT, and there are startup problems. Do not exceed the ohms (typically 5~10 Ω) that would increase the VBS time constant. The minimum on-time for charging the bootstrap capacitor or for refreshing its charge must be verified against this time constant. The time constant depends on the values of bootstrap resistance, capacitance, and duty cycle of switching device calculated in following equation: τ = -R----B---O----O----T----⋅---C----B----O---O----T- [s] D (9) where RBOOT is the bootstrap resistor; CBOOT is the bootstrap capacitor; and D is the duty cycle. © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 6 RON∗ = RGATE + RVS (12) ROFF∗ = RGATE + RVS (13) VCC IN CDRV RBOOT DBOOT IBCHG IN VCC VB HO ITURN-ON CBOOT RGATE GND VS ITURN-OFF RVS Q1 VOUT L1 D1 COUT Figure 17. Current Paths of Turn-on and Turn-off www.fairchildsemi.com AN-6076 4.4 Clamping Diode for VS and Relocation Gate Resistor In the third option, the bootstrap relocates a gate resistor between VS and VOUT and adds a low forward-voltage drop Schottky diode from ground to VS, as shown in Figure 18. The difference between VB and VS should be kept inside the absolute maximum specification in the datasheet and must be satisfied by the following equation: VB − VS < VBS _ abs max (14) VCC DBOOT VDC IN CDRV IN VB HVIC VCC HO GND VS CBOOT RGATE Q1 VOUT L1 DSCHT D1 COUT APPLICATION NOTE 5. Choose Current Capability HVIC The approximate maximum gate charge QG that can be switched in the indicated time for each driver current rating is calculated in Table 1: Table 1. Example HVIC Current-Drive Capability Needed Current Rating Switching Time (tSW_ON/OFF) 100 ns 50 ns Maximum Gate Charge (QG,MAX) 2A 133 nC 67 nC 4A 267 nC 133 nC 9A 600 nC 300 nC Note: 1. For a single 4 A, parallel the two channels of a dual 2 A! For example, a switching time of 100 ns is: 1 % of the converter switching period at 100 KHz; 3 % of the converter switching period at 300 KHz; etc. Figure 18. Clamping Structure 4.5 Relocated Gate Resistor; Double Purpose The gate resistor sets the turn-on and turn-off speeds in the MOSFET and provides current limiting for the Schottky diode during the negative voltage transient of the source terminal of the main switch. In additional, the bootstrap capacitor is protected against over voltage by the two diodes connected to the ends of CBOOT. The only potential hazard by this circuit is that the charging current of the bootstrap capacitor must go through gate resistor. The time constant of CBOOT and RGATE slows the recharge process, which might be a limiting factor as the PWM duty cycle. The fourth options includes relocating a gate resistor between VS and VOUT and a clamp device should be positioned between ground and VS, as shown in Figure 19, where a Zener diode and a 600 V diode are placed. The Zener volt- age must be sized according to the following rule: VB – VS < VBS, ABSMAX (15) VCC DBOOT VDC 1. Needed gate driver current ratings depend on what gate charge QG must be moved in switching time tSW-ON/OFF (because average gate current during switching is IG): I = t Q G.AV.SW G sw _ on / off (16) 2. The maximum gate charge, QG, is read from the MOSFET datasheet. If the actual gate-drive voltage VGS is different from the test condition in the specifications table, use the VGS vs. QG curve instead. Multiply the datasheet value by the number of MOSFETs in parallel. 3. tSW_ON/OFF is how fast the MOSFET should be switched. If unknown, start with 2% of the switching period tSW: tSWON, OFF = 0.02 × tSW = 0--f--S.-0--W--2-- (17) If channel (V-I) switching loss is dominated by one switching transition (turn-on or turn-off), size the driver for that transition. For clamped inductive switching (the usual case), channel switching loss for each transition is estimated as: ESW = 0.5VDS × ID × tSW Joules (18) IN CDRV IN VB HVIC VDD HO GND VS CBOOT RGATE Q1 VOUT L1 DZ D1 D2 COUT Figure 19. Clamping Structure with Zener Diode © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 where VDS and ID are maximum values during the switching interval. 4. The approximate current drive capability of gate driver may be calculated like below (1) Sourcing Current Capability (Turn-on) ISOURCE ≥ 1.5 × ------Q-----G-------tSW, ON (19) www.fairchildsemi.com 7 AN-6076 (2) Sinking Current Capability (Turn-off) ISINK ≥ 1.5 × -------Q-----G--------tSW, OFF (20) where: QG = MOSFET gate charge at VGS = VDD; tSW_ON/OFF = MOSFET switch turn-on / turn-off time; and 1.5 = empirically determined factor (influenced by delay through the driver input stages and parasitic elements). 6. Gate Resistor Design Procedure The switching speed of the output transistor can be controlled by values of turn-on and turn-off gate resistors controlling the turn-on and turn-off current of gate driver. This section describes basic rules for values of the gate resistors to obtain the desired switching time and speed by introducing the equivalent output resistor of the gate driver. Figure 20 shows the equivalent circuit of gate driver and current flow paths during the turn-on and turn-off, including a gate driver and switching devices. VDC HVIC VB Turn-On ON VBS OFF DRI VER RDRV(ON) HO VS RGATE 2 Cgd 1 Cgs dVOUT dt V OUT VDD DRI VER OFF ON VDD Turn- Off LO RDRV(OFF ) GND RG( ON) RG( OFF) 1 Cgd 2 Cgs dVOUT dt Cds APPLICATION NOTE 6.1 Sizing the Turn-On Gate Resistor Turn-on gate resistor, Rg(ON), can be chosen to obtain the desired switching time by using switching time, tsw. To determine a value of resistor using the switching time, sup- ply voltage, VDD (or VBS), equivalent on resistance (RDRV(ON)) of the gate driver, and switching device parameters (Qgs, Qgd, and Vgs(th)) are needed. The switching time is defined as the time spent to reach the end of the plateau voltage (a total Qgd + Qgd has been provided to the MOSFET gate), as shown in Figure 21. The turn-on gate resistor calculated as follows: Ig(avr) = Q-----g---s---+-----Q-----g--dtSW (21) RTOTAL = Rg(ON) + RDRV(ON) = -V----D----D-----+-----V----g---s Ig(avr) (22) where Rg(ON) is the gate on resistance and RDRV(ON) is the driver equivalent on resistance. 6.2 Output Voltage Slope Turn-on gate resistor Rg(ON) can be determined by control output slope (dVOUT/dt). While the output voltage has a nonlinear behavior, the maximum output slope can be approxi- mated by: d----V---d-O--t--U----T- = C---I--gg--d(--a-(--vo--r-f-)-f-) (23) Inserting the expression yielding Ig(avr) and rearranging: RTOTAL = C----V-g--d--D-(--o-D--f--f–-)----⋅V---d----g---V--s----d(---O-t---t-h--U---)-----T-- (24) where Cgd(off) is the Miller effect capacitor, specified as Crss in the datasheet. Figure 20. Gate Driver Equivalent Circuit Figure 21 shows the gate-charge transfer characteristics of switching device during turn-on and turn-off. Figure 21. Gate Charge Transfer Characteristics © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 6.3 Sizing the Turn-Off Gate Resistor The worst case in sizing the turn-off resistor is when the drain of the MOSFET in turn-off state is forced to commutate by external events. In this case, dV/dt of the output node induces a parasitic current through Cgd flowing in RG(OFF) and RDRV(OFF), as shown in Figure 22 The following describes how to size the turn-off resistor when the output dv/dt is caused by the companion MOSFET turning-on, as shown in Figure 22. For this reason, the off-resistance must be sized according to the application worst case. The following equation relates the MOSFET gate threshold voltage to the drain dv/dt: www.fairchildsemi.com 8 AN-6076 HVIC ON VBS OFF DRI VER VDD DRI VER OFF ON VDC VB RDRV(ON) HO VS VDD Turn-On R GATE 2 Cgd 1 Cgs dVOUT dt iLOAD Turn- Off LO RDRV(OFF ) GND RG( ON) RG( OFF) Cgd Cds Cgs Load Figure 22. Current Paths: Low-Side Switch Turned Off, High-Side Switch Turned On APPLICATION NOTE as calculated as: RTotal = VDD − VGS (th) Cgd (off ) ⋅ dVOUT dt = 15 − 5 95×10−12 ×109 = 105[Ω] (30) RDRV (ON ) = VDD I SOURCE = 15V ≈ 43[Ω] 350mA (31) The turn-on resistance value is about 62 Ω. 7.4.2 Turn-Off Gate Resistance If dVout/dt=1 V/ns, the turn-off gate resistor is calculated as: RDRV (OFF ) = VDD I SINK = 15V ≈ 23[Ω] 650mA (32) R g(off) ≤ Vgs (th ) min Cgd ⋅ dVout dt − R(drv) = 3 95 ×10−12 ×109 − 23 = 8.6 (33) V gs ( th ) ≥ {( R g (OFF ) + R DRV (OFF ) ) × i g } = {( R g (OFF ) + R ( drv ) ) × C gd dV out dt Rearranging the equation yields: R g(off) ≤ Vgs (th ) Cgd ⋅ dVout dt − R(drv) (25) (26) 6.4 Design Example Determine the turn-on and off gate resistors using the Fairchild MOSFET with FCP20N60 and gate driver with FAN7382. The power MOSFET of FCP20N60 parameters are as follows: Qgs=13.5 nC, Qgd=36 nC, Cgd=95 pF, VGS(th) =5 V, VGS(th)MIN =3 V 6.4.1 Turn-On Gate Resistance 1) If the desired switching time is 500 ns at VDD=15 V, the average gate charge current is calculated as: I g (avr ) = Qgs + Qgd tSW = 36nC +13.5nC 500ns = 99[mA] (27) RTotal = VDD − Vgs(th) I g (avr ) = 15 − 5 = 101[Ω] 99mA RDRV (ON ) = VDD I SOURCE = 15V ≈ 43[Ω] 350mA (28) (29) 8. Power Dissipation Considerations 8.1 Gate Driver Power Dissipation The total power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are comprised of the static and dynamic losses related to the switching frequency, output load capacitance on high- and low-side drivers, and supply voltage, VDD. The static losses are due to the quiescent currents from the voltage supplies VDD and ground in low-side driver and the leakage current in the level shifting stage in high-side driver, which are dependent on the voltage supplied on the VS pin and proportional to the duty cycle when only the high-side power device is turned on. The dynamic losses are defined as follows: In the low-side driver, the dynamic losses are due to two different sources. One is due to whenever a load capacitor is charged or discharged through a gate resistor, half of energy that goes into the capacitance is dissipated in the resistor. The losses in the gate drive resistance, internal and external to the gate driver, and the switching loss of the internal CMOS circuitry. Also, the dynamic losses of the high-side driver have two different sources. One is due to the level-shifting circuit and one due to the charging and discharging of the capacitance of the high side. The static losses are neglected here because the total IC power dissipation is mainly dynamic losses of gate drive IC and can be estimated as: PDGATE = 2 × CL × fs ×VDD2[W ] (34) The turn-on resistance value is about 58 Ω. 2) If dVout/dt=1 V/ns at VDD=15 V, the total gate resistor is Figure 23 shows the calculated gate driver power dissipation versus frequency and load capacitance at VDD=15 V. This plot can be used to approximate the power losses due to the- gate driver © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 9 www.fairchildsemi.com AN-6076 1 0.1 At VDD = 15V CLOAD=4400PF CLOAD=2200PF CLOAD=1000PF CLOAD=470PF Power [W] 0.01 0.1 1 10 100 1000 Switching frequency [kHz] Figure 23. Gate Driver Total Power Dissipation The bootstrap circuit power dissipation is the sum of the bootstrap diode losses and the bootstrap resistor losses if any exist. The bootstrap diode loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to switching frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor, resulting in more losses. Higher input voltages (VDC) to the half-bridge result in higher reverse recovery losses. The total IC power dissipation can be estimated by summing the gate driver losses with the bootstrap diode losses, except bootstrap resistor losses. If the bootstrap diode is within the gate driver, add an external diode in parallel with the internal bootstrap diode because the diode losses can be significant. The external diode must be placed close to the gate driver to reduce parasitic series inductance and significantly lower forward voltage drop. APPLICATION NOTE 9. General Guidelines 9.1 Printed Circuit Board Layout The layout for minimized parasitic inductances is as follows: • Direct tracks between switches with no loops or deviation. • Avoid interconnect links. These can add significant inductance. • Reduce the effect of lead-inductance by lowering package height above the PCB. • Consider co-locating both power switches to reduce track length. • Placement and routing for decoupling capacitor and gate resistors as close as possible to gate drive IC. • The bootstrap diode as close as possible to bootstrap capacitor. 9.2 Bootstrap Components The bootstrap resistor (RBOOT) must be considered in sizing the bootstrap resistance and the current developed during initial bootstrap charge. If the resistor is needed in series with the bootstrap diode, verify that VB does not fall below COM (ground), especially during startup and extremes of frequency and duty cycle. The bootstrap capacitor (CBOOT) uses a low-ESR capacitor, such as ceramic capacitor. The capacitor from VDD to COM supports both the low-side driver and bootstrap recharge. A value at least ten times higher than the bootstrap capacitor is recommended. The bootstrap diode must use a lower forward voltage drop and switching time as soon as possible for fast recovery, such as ultra-fast. 8.2 Package Thermal Resistance The circuit designer must provide: • Estimate power dissipation of gate driver package • The maximum operating junction temperature TJ, MAX,OPR, e.g., 120 °C for these drivers if derated to 80 % of TJ,MAX =150 °C. • Maximum operating lead temperature TL,MAX,OPR, approximately equal to the maximum PCB temperature underneath the driver, e.g., 100 °C. • Maximum allowable junction-to-lead thermal resistance is calculated by: θJL,max = TJ,max − TL,max PPKG (35) © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 10 www.fairchildsemi.com AN-6076 Table 2. Summary of High-Side Gate Drive Circuitry Method Basic Circuit High-Side Gate Drivers for P-Channel VCC Direct Drive VCC PWM Controller OUT GND RGATE Q1 VOUT L1 D1 COUT VOUT APPLICATION NOTE Advantages & Limitations Can be implemented if the maximum input voltage is less than the gate-to-source break down voltage of the device. Open Collector VCC VDC VCC PWM Controller OUT GND RPULL RGATE Q1 VOUT L1 D1 COUT VOUT Simple method, but is not suitable for driving MOSFET directly in a high-speed application. VDC Level-Shifted Drive VCC PWM Controller OUT R1 VCC R2 RGATE Q1 VOUT L1 RBASE QINV D1 GND High-Side Gate Drivers for N-Channel COUT VOUT VCC VDC Direct Drive VCC PWM Controller OUT GND RGATE Q1 VOUT L1 DSCHT D1 COUT VOUT Suitable for high-speed application and works seamlessly with regular PWM controller. Easiest high-side application the MOSFEF and can be driven directly by the PWM controller or by a ground referenced driver, but it must meet two conditions, as follows: V CC < V GS ,MAX and V DC < V CC − V GS ,Miller Floating Supply Gate Drive VCC VCC HO PWM Controller Opto LO VDC Floating Supply RGATE Q1 VOUT L1 RGATE Q2 COUT VOUT Cost impact of isolated supply is significant. Optocoupler tends to be relatively expensive, limited in bandwidth, and noise sensitive. GND Transformer Coupled Drive PWM Controller VCC VCC OUT1 OUT2 T1 CBLOCK RGATE RGATE VDC Q1 VOUT L1 Q2 GND COUT VOUT Gives full gate control for an indefinite period of time, but is somewhat limited in switching performance. This can be improved with added complexity. Charge Pump Drive VCC VCC PWM Controller OUT GND VDC Q1 VOUT L1 D1 COUT VOUT The turn-on times tend to be long for switching applications. Inefficiencies in the voltage multiplication circuit may require more than low stages of pumping. Bootstrap Drive VCC DBOOT VDC IN CDRV IN VB HVIC VCC HO GND VS CBOOT RGATE Q1 L1 D1 COUT VOUT Simple and inexpensive with limitations; such as, the duty cycle and on-time are both constrained by the need to refresh the bootstrap capacitor. Requires level shift, with the associated difficulties. © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 11 www.fairchildsemi.com AN-6076 Consideration Points of Bootstrap Circuit Problem APPLICATION NOTE VCC INPUT CDRV DBOOT VDC A-Point B-Point IN VCC GND HVIC VB C-Point CBOOT VBS= (VCC -VFBD ) - (-VS) Q1 HO A B RGATE VS C LS1 C LS2 GND - VS D1 VGS=B-C Point iLOAD iFree COUT VBS VDC+VGS,Miller VDC Recovery Time Negative voltage transient at high-side switch turn-off. If VS goes significantly below ground, the gate driver can have serious troubles. The amplitude of the negative voltage is proportional parasitic inductances and the turn-off speed (di/dt) of the switching device, Q1, which is determined by gate resistor, RGATE, and input capacitance, Ciss. Remedies of Bootstrap Circuit Problem Latch-up, propagation signal missing and overvoltage across the bootstrap capactor © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 12 www.fairchildsemi.com AN-6076 APPLICATION NOTE DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reason ably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2008 Fairchild Semiconductor Corporation Rev. 1.4 • 12/18/14 13 www.fairchildsemi.com

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