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REJ05G0001-0200 Power MOS FET Application Note Rev.2.00 Revision Date: August 23, 2004 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Index 1. Electrical Characteristics Definition and Usage Explanation ............................................................ 1 1.1 Absolute Maximum Ratings and Electrical Characteristics .............................................................. 1 1.1.1 Absolute Maximum Ratings........................................................................................................ 1 1.1.2 Electrical Characteristics ............................................................................................................ 2 1.2 Relationship between On-Resistance RDS(on) and Withstand Voltage VDSS...................................... 3 1.3 Saturation Voltage VDS(on)(= Id × RDS(on)) Gate Drive Voltage Dependence...................................... 4 1.3.1 On-Resistance RDS(on) Temperature Dependence...................................................................... 4 1.4 Gate Charge Amounts Qg, Qgs, Qgd............................................................................................... 5 1.4.1 Characteristics of Internal Diode between Source and Drain .................................................... 6 1.5 Internal Diode Reverse Recovery Time trr Current IDR Characteristic.............................................. 6 1.6 Transient Thermal Resistance Characteristic θch-c(t) – Pulse Width PW Characteristic ................ 7 1.7 Area of Safe Operation (ASO) .......................................................................................................... 9 1.7.1 Area of Safe Operation (ASO) Diagram ..................................................................................... 9 1.7.2 Notes on ASO in Circuit Control System.................................................................................. 10 2. Power MOS FET Destruction Mechanisms and Countermeasures ............................................... 11 2.1 Relationship between Power MOS FET Application Areas and Destruction Modes...................... 11 2.1.1 Relationship between Main Power MOS FET Application Areas and Destruction Modes....... 11 2.1.2 Power MOS FET Applications and Operating Range .............................................................. 13 2.1.3 Power MOS FET Structure....................................................................................................... 14 2.2 Avalanche Destruction .................................................................................................................... 16 2.2.1 Explanation of Avalanche Destruction...................................................................................... 16 2.2.2 Avalanche Destruction Resistance Test Circuit and Waveform............................................... 16 2.2.3 Avalanche Energy Calculation Method .................................................................................... 17 2.2.4 Classification of Avalanche Destruction Factors ...................................................................... 18 2.2.5 Avalanche Destruction Current and Energy Value................................................................... 19 2.2.6 Avalanche Destruction Current and dV/dt Resistance ............................................................. 20 2.2.7 Simple Determination Method for Avalanche Resistance Guaranteed Products..................... 20 2.2.8 Avalanche Destruction Countermeasures................................................................................ 22 2.3 ASO Destruction (Heat Radiation Design)...................................................................................... 22 2.3.1 Explanation of ASO Destruction ............................................................................................... 22 2.3.2 ASO Destruction Countermeasures ......................................................................................... 22 2.3.3 Forward Bias ASO (Area of Safe Operation) ........................................................................... 23 2.3.4 Load Shorting Resistance and Countermeasures.................................................................... 24 2.3.5 Heat Radiation Design.............................................................................................................. 24 2.4 Internal Diode Destruction .............................................................................................................. 29 2.4.1 Explanation of Internal Diode Destruction ................................................................................ 29 2.4.2 Example of Internal Diode Destruction Circuit Countermeasures............................................ 31 2.5 Destruction Due to Parasitic Oscillation.......................................................................................... 32 2.5.1 Explanation of Destruction Due to Parasitic Oscillation ........................................................... 32 2.5.2 Power MOS FET Parasitic Oscillation Mechanism .................................................................. 33 2.6 Notes on Parallel Connection ......................................................................................................... 34 2.6.1 Notes on Mounting ................................................................................................................... 34 2.6.2 Advice on Selection and Use of Power MOS FETs ................................................................. 34 2.7 Electrostatic Destruction ................................................................................................................. 35 2.7.1 Explanation of Electrostatic Destruction................................................................................... 35 2.7.2 Electrostatic Destruction Countermeasures ............................................................................. 35 2.7.3 Destruction Progression Modes after Electrostatic Destruction ............................................... 36 2.7.4 Mechanism whereby Gate Destruction Product B Come to ASO Destruction......................... 37 2.8 Usage Notes ................................................................................................................................... 38 2.8.1 Power MOS FET Main Loss Frequency Dependence and Relationship to Main Characteristics ... 38 2.8.2 Malfunction (Arm Shorting) Countermeasures in Motor Application ........................................ 38 2.8.3 Non-Isolated Synchronous Rectification Converter Low-Side Self-Turn-On Phenomenon ..... 40 3. Power MOS FET Applications ........................................................................................................ 41 3.1 Application Map .............................................................................................................................. 41 3.2 Automotive Applications.................................................................................................................. 42 3.2.1 Technological Trends in Automotive Electrical Equipment ...................................................... 42 3.2.2 Sample Automobile ABS Application ....................................................................................... 42 3.2.3 Sample Automobile Power Steering Application ...................................................................... 43 3.2.4 Sample Automobile HID Headlamp Control Application .......................................................... 43 3.3 Power Supply Applications ............................................................................................................. 44 3.3.1 Switching Power Supplies ........................................................................................................ 44 3.3.2 DC/DC Converters.................................................................................................................... 45 3.3.3 VRM (Voltage Regulator Module) ............................................................................................ 46 3.3.4 Base Station SMPS (Switch-Mode Power Supply) .................................................................. 47 3.3.5 Communication Equipment DC/DC Converter ......................................................................... 48 3.4 Motor Drive Applications ................................................................................................................. 49 3.4.1 Small Motor Drive ..................................................................................................................... 49 Power MOS FET Application Note 1. Electrical Characteristics Definition and Usage Explanation 1.1 Absolute Maximum Ratings and Electrical Characteristics 1.1.1 Absolute Maximum Ratings Figure 1.1 shows the meaning of power MOSFET absolute maximum ratings. Example of 2SK3418 Item Symbol (Ta = 25°C) Rating Unit Drain to source voltage VDSS 60 V Gate to source voltage VGSS ±20 V Drain current ID 85 A Drain peak current ID(pulse) *1 340 A Body-drain diode reverse drain current IDR 85 A Avalanche current IAP *2 60 A Avalanche energy EAR *2 308 mJ Channel dissipation Pch *3 110 W Channel temperature Tch 150 °C Thermal resistance θch-c 1.14 °C/W Notes: 1. Allowable value at PW ≤ 10µs, duty ≤ 1% 2. Allowable value at Tch = 25°C, Rg ≥ 50Ω 3. Allowable value at Tc = 25°C VDSS has correlation to on-resistance Lower for low-voltage drive component Theoretical equation for drain current ID: ID = Tchmax – Tc RDS(on)max × α × θch – c ID(pulse) uses transient thermal resistance α= 150°C RDS(on) 25°C RDS(on) Rated current of source to drain diode EAR = 1 2 L • IAP2 V(BR)DSS V(BR)DSS – VDSS Pch temperature derating: Tchmax – Tc Pch(Tx) = Pch(25°C) × Tchmax – 25 θch-c = Tchmax – Tc Pch (Determined by package and chip size) Figure 1 Power MOS FET Absolute Maximum Ratings Rev.2.00 Aug.23.2004 Page 1 of 49 REJ05G0001-0200 Power MOS FET 1. Electrical Characteristics Definition and Usage Explanation 1.1.2 Electrical Characteristics Table 1.1 shows the meaning of power MOSFET electrical characteristics. Table 1.1 Power MOS FET Electrical Characteristics (Ta = 25°C) Ratings Item Test Symbol Min Typ Max Conditions Temperature Unit Dependence Design Notes Drain to source V(BR)DSS 60 — breakdown voltage Zero gate voltage IDSS drain current —— — ID = 10mA, VGS = 0 10 VDS = 60V, VGS = 0 V z µA z Correlation to on-resistance Thermal dependence is high, but low in terms of loss Gate to source IGSS — — ±0.1 VGS = ±20V, µA — leakage current VDS = 0 For products with on-chip protective diode, several tens of nA to several µA, guaranteed value of ±10 µA Gate to source cutoff voltage Forward transfer admittance Static drain to source on state resistance 1 VGS(off) 1.0 — 2.5 VDS = 10V, ID = 1mA |Yfs| 55 90 — ID = 45A, VDS = 10V RDS(on)1 — 4.3 5.5 ID = 45A, VGS = 10V V { s { mΩ z Affects switching operation noise and switching time tr, tf Most important parameters in determining on-loss. Note that these rise together with Static drain to source on state resistance 2 RDS(on)2 — 6.0 9.0 ID = 45A, VGS = 4V mΩ z temperature. Input capacitance Ciss Output capacitance Coss — 9770 — VDS = 10V, VGS = 0, — 1340 — f = 1MHz pF — pF — VDS dependent. Drive loss indicator in analog operation VDS dependent. Affects fall time tf under light load. Reverse transfer capacitance Crss — 470 — pF — VDS dependent. Influences switching time tr, tf. Total gate charge Qg — 180 — VDD = 50V, VGS = 10V, ID = 85A nC — Characteristic that determines drive loss. Greatly dependent on gate drive voltage. Gate to source Qgs — 32 — nC — charge Gate to drain charge Qgd — 36 — nC — Characteristic that determines switching time tr, tf. Dependent on power supply voltage VDD (increases when VDD rises). Turn-on delay time td(on) — 53 — VGS = 10V, Rise time tr — 320 — ID = 45A, RL = 0.67Ω, Turn-off delay time td(off) — 700 — Rg = 50Ω ns — ns — ns — Determined by Rg, Qgd, and gate drive voltage. Influence diode onloss in inverter use. Determined by Rg, Qgd, and Vth. Fall time tf — 380 — ns — Influence surge voltage (noise) when switching off. Body-drain diode VDF forward voltage Body-drain diode trr reverse recovery time — 1.0 — IF = 85A, VGS = 0 V { — 70 — IF = 85A, ns z VGS = 0, di/dt = 50µA/µs Becomes same characteristic as on-resistance when positive bias is applied to VGS. Short-circuit current: lowers di/dt to suppress noise. Note: z: Has positive temperature coefficient, {: Has negative temperature coefficient Rev.2.00 Aug.23.2004 Page 2 of 49 REJ05G0001-0200 Power MOS FET 1. Electrical Characteristics Definition and Usage Explanation 1.2 Relationship between On-Resistance RDS(on) and Withstand Voltage VDSS Figure 1.2 shows the relationship between a withstand voltage VDSS = 20 to 100 V rated component and on-resistance RDS(on). When selecting the withstand voltage of an component, a margin should be left in the settings with respect to circuit operation conditions power supply voltage VDD and surge voltage VDS(peak) generated when switching off. As VDSS has a positive temperature characteristic with respect to temperature, the minimum temperature environment conditions for use of the component must be taken into consideration. 20 D6 (SOP-8) D7 (SOP-8) D6 (LFPAK) 10 D7 (LFPAK) 5 On-Resistance RDS(on) (mΩ) 2 VGS = 10 V 1 10 20 50 100 200 Drain to Source Voltage VDSS (V) Figure 1.2 RDS(on) – VDSS Relationship Figure 1.3 shows the V(BR)DSS temperature characteristic (taking the example of the 2SK3418). In this case, making the withstand voltage margin larger than necessary is inadvisable as it will result in higher on-resistance and greater steadystate loss. Recently, components have appeared that can handle guaranteed avalanche resistance in order to reduce this margin as much as possible and provide the benefit of lower loss. 90 Withstand Voltage V(BR)DSS (V) 80 70 60 –50 0 50 100 150 200 Case Temperature Tc (°C) Figure 1.3 V(BR)DSS – Tc Characteristics (2SK3418) Rev.2.00 Aug.23.2004 Page 3 of 49 REJ05G0001-0200 Power MOS FET 1. Electrical Characteristics Definition and Usage Explanation 1.3 Saturation Voltage VDS(on)(= Id × RDS(on)) Gate Drive Voltage Dependence This characteristic is a characteristic curve for designing at what gate drive voltage the VDS(on) area (on-resistance area) is effected in the case of a predetermined operating current Id. In the case of power MOS FETs, 10 V drive components, 4 V drive components, 4 V drive (or lower) components are produced according to the gate drive operating current. The means of achieving low-voltage drive is generally to use a thin gate oxide film (whereby the gate-source withstand voltage VGSS rating is reduced) to attain a lower VGS(off) value. VGS(off) has an approximately –5 mV/°C negative temperature coefficient (characteristic that falls approximately 0.5 V with a 100°C rise). When selecting the type of component in terms of drive voltage, it is necessary to consider the application (for example, selection of a 10 V drive component with a high VGS(off) value to cope with noise in switching power supply or motor drive applications) and the specifications of the gate drive IC or LSI to be used (such as a low-level voltage that keeps the MOS FET off). Recently, therefore, a distinction may be made between the use of 4 V drive components and 10 V drive components according to the conditions of use and application even in automotive electrical equipment. Drain to Source Saturation VDS(on) (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage 0.5 Pulse Test 0.4 0.3 ID = 50 A 0.2 0.1 20 A 10 A 0 0 4 8 12 16 20 Gate to Source Voltage VGS (V) Figure 1.4 VDS(on) – VGS Characteristics (2SK3418) 1.3.1 On-Resistance RDS(on) Temperature Dependence Figure 1.5 shows temperature dependence of on-resistance RDS(on). Power MOS FET on-resistance RDS(on) has a positive temperature characteristic. If the ratio between channel temperature rating Tch(max.) of 150°C and room temperature of 25°C (150°CRon/25°CRon) is designated α, the value is approximately 1.7 to 1.8 times for an component with a withstand voltage of 100 V or less, and approximately 2.4 to 2.5 times for an component with a withstand voltage of 500 V. It should also be noted that, as shown in the figure, RDS(on) does not rise linearly with a rise in temperature, but increases in a curvilinear shape. What this means is that, when ambient temperature Ta = 100°C, for example, if the channel temperature calculation result is that Tch = 130°C, and Ta is made 120°C (a 20°C rise), Tch does not simply rise by 20°C to become 150°C, but rises above that temperature. Therefore, when an component is used in a high-temperature environment such as automotive electrical equipment, this temperature characteristic must be carefully considered in heat radiation design. For details, refer to the power MOS FET heat radiation design example. Rev.2.00 Aug.23.2004 Page 4 of 49 REJ05G0001-0200 Power MOS FET 1. Electrical Characteristics Definition and Usage Explanation Static Drain to Source on State Resistance RDS(on) (mΩ) Static Drain to Source on State Resistance vs. Temperature 20 Pulse Test 16 12 ID = 50 A 8 4V 10, 20 A 4 VGS = 10 V 10, 20, 50 A 0 –50 0 50 100 150 200 Case Temperature Tc (°C) Figure 1.5 RDS(on) – Tc Characteristics (2SK3418) 1.4 Gate Charge Amounts Qg, Qgs, Qgd In figure 1.6(a), the point up to prescribed drive voltage VGS (=XV) is total charge amount Qg. This is the characteristic parameter that determines gate peak current ig(peak) for driving the gate and drive loss P(drive loss). Ig(peak) = Qg/t …………………………(1) P(drive loss) = f ⋅ Qg ⋅ VGS ……………(2) Qgd corresponds to mirror capacitance Crss, and depends on power supply voltage VDS. It is also a parameter that influences switching characteristics. tf ≅ (Rs + rg) ⋅ Qgd log Vgs(on) ………(3) Vgs(on) – Vth Vth Fall time tf that controls L load switching loss is expressed by equation (3). Qg and Qgd are important items in designing high-frequency operation loss. In high-frequency (f = 100 kHz or above) applications, it can be said that the smaller the Ron·Qg or Ron·Qgd product, the higher is the performance of the component. VGS (V) VDS (V) Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) XV Qg (VGS = X V) Qgs VGS Qth Qgd VDS Vth VGS(on) Gate Charge (a) Dynamic Input Characteristics 100 20 ID = 85 A 80 VGS 16 60 40 VDS 12 VDS = 50 V 25 V 10 V 8 20 VDS = 50 V 4 25 V 10 V 0 0 0 80 160 240 320 400 Gate Charge Qg (nc) (b) Figure 1.6 Input Dynamic Characteristics (2SK3418) Rev.2.00 Aug.23.2004 Page 5 of 49 REJ05G0001-0200 Power MOS FET 1. Electrical Characteristics Definition and Usage Explanation 1.4.1 Characteristics of Internal Diode between Source and Drain In a power MOSFET, a parasitic diode is provided between the source and drain. Rated current IDR of this diode is the same value as forward drain current rating ID. The characteristics of this diode show the same forward voltage characteristics as an ordinary diode in the case of zero bias of the gate drive voltage (VGS = 0). If the gate drive voltage is given positive bias (in the Nch case), as shown in Figure 1.7 there is a voltage drop determined by on-resistance RDS(on) (VSD = Id × RDS(on)) that is the same as in the forward direction, and a much lower forward voltage can be obtained even than with an SBD (Schottky barrier diode). Reverse Drain Current IDR (A) Reverse Drain Current vs. Source to Drain Voltage 100 10 V 80 5V 60 40 VGS = 0, –5 V 20 Pulse Test 0 0 0.4 0.8 1.2 1.6 2.0 Source to Drain Voltage VSD (V) Figure 1.7 IDR – VSD Characteristics (2SK3418) The benefits of such reverse-direction characteristics are actively applied in the following kinds of uses. • Load switches for preventing battery reverse connection • Switching power supply (n+1) redundant-type hot swap circuits • Motor drive circuit external diode replacement • Switching power supply secondary-side drive rectification circuits, etc. 1.5 Internal Diode Reverse Recovery Time trr Current IDR Characteristic In motor drive (power steering, starter generators, etc. in the case of electrical equipment) and switching power supply synchronous rectification applications that make positive use of a power MOSFET internal diode, there is a requirement for this reverse recovery time trr to be fast. In these applications, operationally upper arm/lower arm shorting and excess turn-on loss occur in this trr period. Generally, therefore, in the control circuitry, a dead time (longer than trr) is provided that turns off the gate signal at the time of upper/lower component switching. trr ta tb Turn-on loss particularly large in this period 0 irr 0.1irr Soft recovery characteristic desired (Assuming circuit floating inductance is made small) Figure 1.8 Reverse Recovery Time trr Waveform Rev.2.00 Aug.23.2004 Page 6 of 49 REJ05G0001-0200 Power MOS FET 1. Electrical Characteristics Definition and Usage Explanation This reverse recovery time trr shows a tendency to increase as the temperature rises. Also, the steeper di/dt at the time of recovery (area tb in figure 1.9), the more likely is the occurrence of noise, and therefore a soft recovery characteristic is desirable. Reverse recovery time trr differs greatly according to the withstand voltage of the component. In the case of a withstand voltage of 60 V or less, it is comparatively fast at a value of 40 to 60 ns. It is around 100 ns in the 100 V class, and around 300 to 600 ns in the 250 to 500 V high-withstand-voltage class. Therefore, in the high-withstandvoltage class of 250 V and above, products have been developed that have been speeded up to around 100 ns by means of lifetime control technology. 1000 500 Body-Drain Diode Reverse Recovery Time di / dt = 50 A / µs VGS = 0, Ta = 25°C Reverse Recovery Time trr (ns) 200 100 50 20 10 0.1 0.3 1 3 10 30 100 Reverse Drain Current IDR (A) Figure 1.9 trr – IDR Characteristics (2SK3418) 1.6 Transient Thermal Resistance Characteristic θch-c(t) – Pulse Width PW Characteristic Figure 1.10 shows the θch-c(t)—pulse width PW characteristic. This is a characteristic for calculating channel temperature Tch in the component operating state. Pulse width PW on the horizontal axis is the operating time, and 1 Shot Single Pulse repeat operation conditions are shown. For example, PW = 1 ms, D = 0.2 (duty cycle = 20%) means that the repetition frequency is 200 Hz (repetition cycle T = 5 ms). Generally, when channel temperature rise ∆Tch is calculated with duty cycle = 20% (D = 0,2), PW = 10 ms, and current dissipation Pd = 60 W, the following equation may be used, but since error arises as shown below, the transient thermal resistance characteristic should be used. Tch = (0.2 × Pd) × θch-c = (0.2 × 60) × 1.14 = 13.7°C When the transient thermal resistance characteristic is used, 16.5ºC error arises as shown below. Tch = Pd × θch-c(t) = 60 × 0.44 × 1.14 = 30.2°C Noamalized Transient Thermal Impedance γs (t) Noamalized Transient Thermal Impedance vs. Pulse Width 3 1 D=1 Tc = 25°C 0.5 0.3 0.2 0.1 0.1 0.05 0.03 0.02 1sh0o.0t p1ulse t3 0.01 10 µ 100 µ t1 t2(D=0.2) θch-c(t) = γs (t) • θch – c θch-c = 1.14°C/W, Tc = 25°C PDM D= PW T PW T 1m 10 m 100 m 1 10 Pulse Width PW (S) Figure 1.10 θch-c(t) – Pulse Width PW Characteristics (2SK3418) Rev.2.00 Aug.23.2004 Page 7 of 49 REJ05G0001-0200 Power MOS FET 1. Electrical Characteristics Definition and Usage Explanation Examples of channel temperature Tch calculation (2SK3418) using transient thermal resistance are shown below. • Example 1 To calculate channel temperature Tch under the following conditions: when case temperature Tc = 85°C, peak power Pd(peak)1 = 50 W, application time ts = 10 ms, 1 shot single pulse Tch1 = Tc + (Pd(peak)1) × θch-c(t1) = 85 + (50 × 0.3 × 1.14) = 102.1°C • Example 2 To calculate channel temperature Tch under the following conditions: when case temperature Tc = 85°C, operating frequency f = 2 kHz, repeat operation with duty cycle = 20%, applied power Pd(peak)2 = 50 W From the above operation, application time t2 = 100 µs, repetition cycle T = 500 µs, and D = t2/T = 0.2. Therefore: Tch2 = Tc + (Pd(peak)2) × θch-c(t2/T) = 85 + (50 × 0.22 × 1.14) = 97.54°C • Example 3 To calculate peak channel temperature Tch(peak) when peak power Pd(peak)3 = 500 W is further applied for a period of t3 = 60 µs by another circuit control system during the operation in Example 2 Tch2 = Tc + (Pd(peak)2) × θch-c(t2/T) + {(Pd(peak)3 – Pd(peak)2 × t2/T)} × θch-c(t3) = 85 + (50 × 0.22 × 1.14) + (500 – 50 × 0.2) × 0.031 × 1.14) = 85 + 12.54 + 17.32 = 114.86°C t3 Pd(peak)3 t2 Pd(peak)2 T Rev.2.00 Aug.23.2004 Page 8 of 49 REJ05G0001-0200 Power MOS FET 1. Electrical Characteristics Definition and Usage Explanation 1.7 Area of Safe Operation (ASO) 1.7.1 Area of Safe Operation (ASO) Diagram Figure 1.11 shows an area of safe operation (ASO) diagram for the 2SK3418. The ASO limited area is divided into the following 5 areas. Area (1) is an area limited by maximum rated currents IDC, ID(pulse)max. Area (2) is an area limited by on-resistance RDS(on)max [ID = VDS/RDS(on)]. Generally, this area is divided separately from the ASO area. Area (3) is an area limited by channel loss. Area (4) is the same kind of secondary breakdown area as in a bipolar transistor that appears under conditions of continuous operation or opened with a comparatively long pulse width (several ms or more). This is because, when the operating voltage increases in the same applied power line, the operating current naturally decreases, but in this small current area the output transfer characteristic (Vgs-Id characteristic) is a negative temperature characteristic. When the area becomes a large current area that entails a change to a positive temperature characteristic, this phenomenon disappears. The current value at which the temperature characteristic changes from negative to positive differs from product to product, and with products of several amperes or less this phenomenon is unlikely to occur, and this can be guaranteed with a so-called constant power line with no secondary breakdown. Area (5) is an area limited by withstand voltage VDSSmax. Drain Current ID (A) 1000 Maximum Safe Operation Area 300 100 30 10 3 Oarpe1ea2raistiloimn iitnedthPbiDsWyC=(OT1pc0e=r3ma2tsi5o°(n11C)mshso1t0)0 10 µs 4 µs RDS(on) 1 0.3 Ta = 25°C 5 0.1 0.1 0.3 1 3 10 30 100 Drain to Source Voltage VDS (V) Figure 1.11 ASO Diagram (2SK3418) Rev.2.00 Aug.23.2004 Page 9 of 49 REJ05G0001-0200 Power MOS FET 1. Electrical Characteristics Definition and Usage Explanation 1.7.2 Notes on ASO in Circuit Control System As power MOS FETs are generally used in switching applications, in normal operation they are usually used in limited area (2). A point requiring attention in circuit design is the control system sequence. Figure 1.12 shows an example of the power supply voltage and gate drive voltage sequence for a terminal electronic device when the system’s source power supply is cut. As shown by the solid lines in the figure, if the fall time until power supply voltage VDD is turned off is longer than that for gate drive voltage VGS, VGS is in an underdrive state in period t1 in the figure, and enters ASO limited area (4) or (5), making it necessary to confirm whether it is in an area of safe operation. An effective means of avoiding such an operation area is to perform sequence control so that the fall time of gate drive voltage VGS is delayed beyond supply voltage VDD as shown by the dotted lines. Power supply voltage VDD 0 System power supply down Gate drive voltage fall control time controlled to be slower than that of power supply voltage Gate drive voltage VGS 0 t1 Vth D-S operating voltage VDS 0 Enters ASO area (4) or (5) Drain operating voltage ID 0 t Figure 12 Example of Terminal Electronic Device System Power Supply Voltage and Gate Drive Voltage Sequence Rev.2.00 Aug.23.2004 Page 10 of 49 REJ05G0001-0200 Power MOS FET Application Note 2. Power MOS FET Destruction Mechanisms and Countermeasures Introduction As power MOS FETs are often used in the final output circuitry of electronic device application circuits, and are used under a wide range of conditions, circuit designers frequently have to confront the problem of unexpected component destruction. The purpose of this section is to carry out electronic circuit design with a good understanding of the mechanisms behind such destruction, and produce as far as possible problems involving heat radiation, destruction, and so forth, in mass production and in the market after design is completed, in order to use power MOS FETs effectively. 2.1 Relationship between Power MOS FET Application Areas and Destruction Modes 2.1.1 Relationship between Main Power MOS FET Application Areas and Destruction Modes Table 2.1 shows the relationship between main power MOSFET application areas and destruction modes. Power MOS FET destruction modes can be broadly be divided into the five modes shown below. Table 2.1 Relationship between Power MOSFET Application Areas and Destruction Modes Application Field Switching Power Supply Automobile (electronic components) Motor Drive Destruction Mode AC/DC(OA, Server) Application Large- power Synch- Forward Reso- parallel DC-DC ronous conver- nance Bridge connec- conver- rectifi- ter method circuit tion ter cation UPS (DCAC) Valve, Low High Machine Motor solenoid voltage voltage tool (electro- EPS ABS static start-up direct OA dischar- genera- gas (PPC, FA ge) tor injection HDD) (servo) Audio amp. 1 Avalanche destruction — 2 ASO Forward-bias ASO — — — — — — — — — — — — destruction Loss ↓ Heat ASO with short-circuit of load (Short-circuit between upper and — — — — — — lower sides) RDS(on) — Switching — Built-in Di trr — — — — — — 3 Built-in diode destruction — — — — — — 4 Destruction by parasitic oscillation — — when operating with MOS FETs connected in parallel — — — — — — 5 Gate surge or electrostatic destruction Guard against static electricity during handling (including electrostatic charges on the mounting equipment), and against external surges that reach to the circuit. Rev.2.00 Aug.23.2004 Page 11 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures (1) Avalanche destruction mode A phenomenon whereby destruction occurs if a surge voltage exceeding the rated VDSS of the component is applied between the drain and source, destruction voltage V(BR)DSS (whose value differs according to the destruction current) is reached, and a certain energy level or higher is attained. This destruction energy differs according to the individual product and operating conditions. (2) ASO (Area of Safe Operation) destruction Mostly caused by heat caused by exceeding the so-called Area of Safe Operation, in which component maximum rating drain current Id, drain-source voltage VDSS, or allowable channel dissipation Pth(W) is exceeded. Main causes of heat radiation are classified as a continuous or transient factors. 1. Continuous factors : Heat radiation due to DCASO (loss caused by DC power application) 2. Transient factors : On-resistance RDS(on) loss (RDS(on) increases at high temperatures) : Loss due to leakage current IDSS (extremely small compared with other loss) : Pulse ASO (1 shot pulse application) : Load shorting ASO : Switching loss (turn-on, turn-off)* : Internal diode trr loss (Upper/lower arm shorting loss)* All are temperature-dependent. Asterisked items also depend on operating frequency f. (3) Internal diode destruction This is a mode in which, when a parasitic diode configured between the source and drain operates, a power MOSFET parasitic bipolar transistor operates and breaks down in reverse recovery of that diode. (For details, see section 2.4, Internal Diode Destruction.) (4) Destruction due to parasitic oscillation This destruction mode is prone to occur in the case of parallel connection. (For details, see section 2.5, Destruction Due to Parasitic Oscillation, and section 2.6, Notes on Parallel Connection.) (5) Gate surge, electrostatic destruction Main types are gate overvoltage destruction caused by surge application between the gate and source from external circuitry, and gate destruction ESD (electrostatic discharge) caused by static electricity due to handling (including a charge from mounting or measuring equipment). Table 2.1 shows the importance of the above five modes in various devices and applications, and taking these points into account when designing circuits and selecting components is an effective means of preventing various problems. From this standpoint, the following considerations are important. Rev.2.00 Aug.23.2004 Page 12 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.1.2 Power MOS FET Applications and Operating Range Figure 2.1 shows the kind of operating conditions in which power MOS FET applications are used, with load inductance and operating frequency as parameters. Operating Frequency f (Hz) 10M 1M 100k Ultrasonic medical appliance High-speed, high-accuracy Graphic processing High-density, MD high-speed processing Common Needs •Saving energy •Low noise •Small and slim package Machine tool (electrostatic discharge, laser) Power supply for machine processing High-speed processing, low loss DC-DC converter (VRM, PC) (Telecommunications) Reducing voltage, loss, and noise AC-DC fL(l(olawrgsep)eed), switching power supply (Network OA, Base station) Low loss, highaccuracy control Small motor drive 10k (HDD, printer) Improving start-up f(Lh(isgmh aslpl)eed), performance, reducing loss and size Motor drive for industry (FA inverter) Automobile electronic components (ABS, injection, solenoid) Low loss, high reliability Actuator for industry 1k 1µ 10µ 100µ 1m 10m Load Inductance L (H) Figure 2.1 Power MOS FET Applications Market requirements are (1) improved energy saving, (2) lower noise (environmental considerations), (3) smaller, thinner design. With regard to the characteristics demanded of power MOS FETs, the most important characteristics and specifications naturally differ according to the field and application concerned. Consequently, a demand has recently arisen for products specific to particular applications. Rev.2.00 Aug.23.2004 Page 13 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.1.3 Power MOS FET Structure Figure 2.2 shows an N-channel power MOS FET chip and its internal structure. As shown in the figure, the internal structure of an N-channel power MOS FET chip comprises a large number of cells connected in parallel. As shown in the enlarged cell diagram, current flows in the source → drain direction (the reverse is true in a P-channel type). Gate bus lines Partially enlarged view Active region Gate Source Active region S G N+ P N– N++ D MOS FET cells are connected in parallel in the active region. D G Gate bus lines S Drain (bottom) Figure 2.2 N-Channel Power MOS FET Chip and Internal Structure Figure 2.3 shows the cross-sectional structure of an N-channel power MOS FET (with gate protection diodes). Gate Wire Protection Layer Poly-Si (Polyimide-resins) Gate Source Built-in diode Drain SiO2 P Type Layer N Type Si Epi, Layer n+ p– n+ n+ n+ n+ p– p– p– Gate protection diode Built-in Cell diode Drain current Operating region of power MOS FET Gate Regions peripheral to gate pads Drain Gate protection diode Source Symbol of MOS FET (Nch) Figure 2.3 Cross-Sectional Structure of N-Channel Power MOS FET (with Gate Protection Diodes) Figure 2.4 shows the output static characteristics and diode characteristics of a high-withstand-voltage power MOS FET (2SK1522). When a power MOS FET is used in a monitor drive, UPS (uninterruptible power supply), or similar application, the internal diode characteristics can be used effectively. The cell cross-sectional structure of a general power MOS FET plate structure is shown, together with an equivalent circuit diagram. A power MOS FET has a structure in which bipolar transistors are connected in parallel between drain and source. These transistors operate at the time of transitions, and are designed so that Rb is made small, for example, so as not to affect the MOS FET destruction tolerance. Rev.2.00 Aug.23.2004 Page 14 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures Source Gate 25 Drain Current ID (A) N+ P N– N++ Drain Cell Structure (Planar) D RDS(on) Body Diode 20 10V 15 4.5V 10 Source-Drain Voltage VSD (V) Diode Forward Voltage VF (V) 5 –2.5 –2.0 –1.5 –1.0 –0.5 0 VGS=0V –5 10V VGS=4V 0.5 1.0 1.5 2.0 2.5 Drain-Source Voltage VDS (V) –10 Reverse Current IDR (A) Body Diode Current IF (A) Cgd rg G Cgs Cds Rb Parasitic Bipolar S Transistor Equivalent Circuit Body Diode –15 –20 –25 Typical Output Characteristics (Example of 2SK1522) Figure 2.4 Output Static Characteristics and Diode Characteristics (High Withstand Voltage) Figure 2.5 shows the output static characteristics and diode characteristics of a low-withstand-voltage power MOS FET (HAT2064R) in the same way as in the previous section. Low-withstand-voltage power MOS FETs attain an ultra-low on-resistance characteristic on the order of several mΩ or less, and are therefore much smaller than a rectification Schottky barrier diode (SBD) low-VF component (VF = 0.4 to 0.5 V), and are widely used as MOS synchronous rectification components for the purpose of achieving higher efficiency of low-voltage power supplies (Vout = 3.3 V or less). Drain Current ID (A) G S 25 10V 4.5V 3.5V 20 N+ P ID N– IDR N++ D Cell Structure (Trench) D RDS(on) Body Diode 15 3.0V 10 Source-Drain Voltage VSD (V) Diode Forward Voltage VF (V) –1.0 –0.8 –0.6 –0.4 –0.2 VGS=0V Due to VGS positive bias = RDS(on) 5 2.5V VGS=0V O 0 0.2 0.4 0.6 0.8 1.0 –5 Drain-Source Voltage VDS (V) –10 Reverse Current IDR (A) Body Diode Current IF (A) Cgd rg G Cgs Cds Rb Parasitic Bipolar S Transistor Equivalent Circuit –15 Body Diode VGS=4.5V –20 10V –25 Typical Output Characteristics (Example of HAT2064R) Figure 2.5 Output Static Characteristics and Diode Characteristics (Low Withstand Voltage) Rev.2.00 Aug.23.2004 Page 15 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.2 Avalanche Destruction 2.2.1 Explanation of Avalanche Destruction Avalanche destruction is a mode in which a flyback voltage generated when dielectric load switching operation is turned off, or a spike voltage due to leakage inductance, exceeds the power MOS FET drain rated withstand voltage, entered in a destruction area, and destruction occurs. 2.2.2 Avalanche Destruction Resistance Test Circuit and Waveform Figure 2.6 shows an avalanche destruction resistance standard test circuit (a) and its operational waveform (b). (a) VGS = 10 to 15V, IAP is variable depending on pulse width Rg L IAP VDS Test sample RGS P.G (pulse generator) Rg = Rgs = 50Ω Standard Test Circuit (b) Vdss VDD VDD 0 dV/dt ID VDS(on) ta Avalanche time IAP (Avalanche Current) V(BR)DSS VDS(on) = ID · RDS(on) Voltage VDS • Current ID Waveform [Equation for calculating avalanche energy] EAR = 1 2 · L · IAP2 · V(BR)DSS V(BR)DSS – VDD Figure 2.6 Avalanche Destruction Resistance Test Circuit and Waveform Period ta in the waveform in (b) is defined as the avalanche time. The range in which drain-source peak voltage Vds(p) satisfies the condition Vdss ≤ Vds(p) < V(BR)DSS is an area in which the so-called rated voltage is exceeded but avalanche destruction has not been reached. In this kind of operation area, the avalanche area may or may not actually be entered depending on actual withstand voltage V(BR)DSS of the component, but it is advisable to select a product with guaranteed avalanche resistance. Avalanche resistance guaranteed products are all subjected to final screening by the standard circuit shown in (a). For avalanche resistance guaranteed products, avalanche current rated value IAP(A) and avalanche energy value EAR(J) are stipulated. EAR is expressed by equation (1). EAR = Pd ⋅ t = 1 2 V(BR)DSS ⋅ IAP ⋅ ta = 1 2 ⋅ L ⋅ IAP2 ⋅ V(BR)DSS V(BR)DSS – VDD (J) ………(1) Also, with regard to peak channel temperature Tch(peak) in the avalanche operation state, use within rating channel temperature Tch ≤ 150°C is necessary. An example of calculation of this channel temperature is given in another section. Rev.2.00 Aug.23.2004 Page 16 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.2.3 Avalanche Energy Calculation Method Figure 2.7 shows an avalanche test equivalent circuit. VDD Ids(t) IAP L V(BR)DSS D Ids(t) V(BR)DSS IAP L VDD e G S Figure 2.7 Avalanche Test Equivalent Circuit Avalanche energy value EAR in the equivalent circuit is expressed by equation (1). EAR = ∫ ta 0 Vds(t) ⋅ Id(t) dt ……………………(1) Vds(t) and Id(t) are as follows: Vds(t) = V(BR)DSS ……………………………(2) Id(t) = IAP – IAP ta t ……………………………(3) ta = L ⋅ IAP V(BR)DSS – VDD ………………………(4) Substituting (2) and (3) in equation (1): ( ) ( ) EAR = ∫ ta 0 V(BR)DSS IAP – IAP t ta dt = ∫ ta 0 V(BR)DSS ⋅ IAP – V(BR)DSS ⋅ IAP ⋅ t ta dt [ ] = V(BR)DSS ⋅ IAP ⋅ t – V(BR)DSS ⋅ IAP ⋅ t2 2ta ta 0 = 1 2 ⋅ V(BR)DSS ⋅ IAP ⋅ ta Substituting ta of equation (4) in the above equation: ∴ EAR = 1 2 ⋅ L ⋅ IAP2 ⋅ V(BR)DSS V(BR)DSS – VDD Rev.2.00 Aug.23.2004 Page 17 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.2.4 Classification of Avalanche Destruction Factors The following three factors, illustrated in figure 2.8, affect the avalanche destruction resistance value. (1) Limitation due to drain current Id rating (2) Limitation due to excessive channel temperature in avalanche (3) Decline of destruction resistance due to dV/dt (figure 2.6(b)) 100 •ID rating limit •Destruction caused by dv/dt 10 (ttheDemermpstearrulacAttuSiorOens)cianutsheedcbhyanonveelr- Avalanche Destruction Current IAP (A) 1 0.01 0.1 1 10 100 Inductance L (mH) Figure 2.8 Classification of Avalanche Destruction Factors Rev.2.00 Aug.23.2004 Page 18 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.2.5 Avalanche Destruction Current and Energy Value Figures 2.9 and 2.10 show actual data show how avalanche destruction current IAP and avalanche destruction energy EAR vary with the inductance L value for a high-withstand-voltage 500 V class component and low-withstand-voltage 60 V class component, respectively. The graphs show that as the inductance L value increases, destruction current IAP tends to fall, but the destruction energy EAR value tends to increase. Therefore, to see the variations in avalanche resistance, it is necessary to consider both destruction current IAP and energy value EAR. In general, it can probably be stated that an component with a small inductance value L and large destruction energy value EAR has good avalanche resistance. Test conditions: VGS = 15V, VDD = 250V, Ta = 25, 140°C Target device: 2SK1168 (500V / 15A / 0.4Ω↓ / TO-3P) 1000 10000 Avalanche Energy EAR (mJ) Avalanche Destruction Current IAP (A) 300 Destruction Current IAP 100 Destruction energy EAR 3000 1000 30 ID current rating 10 3 1 10µ Item Symbol IAP EAR Tc (°C) 25 140 25 140 Guaranteed region(Tch≤150°C) 30µ 100µ 300µ 1m 3m Inductance L (H) 300 100 30 10 10m Figure 2.9 Avalanche Destruction Current and Energy Value (High Withstand Voltage) Test conditions: VGS = 15V, VDD = 25V, Ta = 25°C Target device: 2SK2869 (60V / 20A / 45mΩ↓ / DPAK) 100 Destruction Current IAP 50 1000 500 ID rating 20 Destruction energy EAR 200 10 Guaranteed region(Tch≤150°C) 100 5 50 Avalanche Energy EAR (mJ) Avalanche Destruction Current IAP (A) 2 20 1 10µ 100µ 1m Inductance L (H) 10 10m Figure 2.10 Avalanche Destruction Current and Energy Value (Low Withstand Voltage) Rev.2.00 Aug.23.2004 Page 19 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.2.6 Avalanche Destruction Current and dV/dt Resistance The third factor, the relationship between avalanche destruction resistance and dV/dt, will now be considered. Figure 2.11 shows measured values for avalanche destruction current IAP dependence on dV/dt resistance. In a power MOS FET, as explained before, a parasitic bipolar transistor is formed between the drain and source in the structure shown in figure 2.4. As dV/dt is made steeper, a transient current flows through capacitance Cds, and this transistor is turned on, leading to a drop in destruction resistance. In the example in figure 2.11, the area in which dV/dt ≤ 10 V/µs can be called a safe area. This value differs according to the particular component. Target device: 2SK1170 (500V / 20A / 0.27Ω↓ / TO-3P) 1000 Avalanche Current IAP (A) Measured values 300 for destruction Parasitic Bip TRS 100 operates VDD = 250V, L = 100µH VGS = 15V, Ta = 25°C Rg: dv/dt is variable 30 ID current rating 15V Rg Pre Drive 10 L DUT VDD Area of safe operation 3 (Reference) P.G Test Circuit and Conditions 1 1 3 10 30 100 dV/dt (V/ns) Figure 2.11 Avalanche Destruction Current and dV/dt Resistance 2.2.7 Simple Determination Method for Avalanche Resistance Guaranteed Products A simple determination method for avalanche resistance guaranteed products is described here. The description is based on the avalanche operation waveform (1 shot period) in figure 2.12, taking the example of a 2SK2869 (60 V/20 A, 45 mΩ↓ , DPAK package) avalanche guaranteed product as the tested device. Drain to Source Voltage: 20V/DIV Drain Current: 1A/DIV Avalanche time ta Ch3 10.0mV Ch2 20.0 V M 200µs Ch1 Time t : 200µs/DIV Note: 1. ID ≤ Rated IAP max 2. Tch ≤ Rated 150°C Target device: 2SK2869 (60V / 20A / 45mΩ↓ / DPAK) Test conditions VGS = 15V, VDD = 25V, L = 5mH, Tc = 25°C, 1 shot •Channel temperature during avalanche: Tch Tch = T(S)ch + Pch × θch-c(t) = 60 + 160 × 0.3336 = 113.4°C T(S)ch: Initial channel temperature (assumed to be 60°C) Pch = 1 2 × IAP × V(BR)DSS = 1 2 × 4 × 80 = 160W θch-c(t): ta = 400ms, 2SK2869 From the transient thermal resistance characteristics, 0.3336°C/W is obtained. 11.5 V Figure 2.12 Avalanche Time and Drain-Source Voltage (Drain Current) Rev.2.00 Aug.23.2004 Page 20 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 3 Tc = 25°C Transient Thermal Resistance γs (t) 1 D=1 0.5 0.3 0.2 0.1 0.08 0.03 0.1 0.05 0.02 0.01 1 shot pulse θch-c(t) = γs(t) · θch-c θch-c = 4.17°C/W, Tc = 25°C Transient thermal resistance during avalanche time ta (ta = 400µs) θch-c(t) = γs(t) · θch-c = 0.08 × 4.17 = 0.3336°C/W PDM PW T D = PW T 0.01 10µ 100µ 400µ 1m 10m 100m 1 10 Pulse Width PW (S) Figure 2.13 2SK2869 Transient Thermal Resistance Characteristics (Data Sheet) Trial calculations have been carried out assuming that start channel temperature T(s)ch = 60°C before avalanche operation (due to the channel temperature rise caused by on-resistance RDS(on) and switching loss). For dV/dt, a range of safe operation was assumed. Therefore, the following two checkpoints should be confirmed. (1) Whether avalanche current IAP is within avalanche guarantee value current rating IAPmax (For 2SK2869 avalanche guaranteed current IAP, when L = 5 mH, IAPmax = 6.2 A (figure 2.10)) (2) Whether channel temperature Tch in avalanche operation is within the range Tchmax ≤ 150°C First, as avalanche current IAP in (1) is 4 A from the waveform, it can be confirmed that it is within avalanche rated current + IAPmax ≤ 6.2 A. Next, channel temperature Tch in avalanche operation in (2) is expressed by equation (1). Tch = T(s)ch + Pch × θch – c(t) ( ) = T(s)ch + 1 2 × IAP × V(BR)DSS × θch – c(t) …………(1) Here, θch-c(t) is transient thermal resistance, and is calculated from the 2SK2869 data sheet transient thermal resistance characteristics in figure 2.13. θch-c(t = 400 µs) when avalanche opened time ta = 400 µs can be calculated from the graph as shown below. θch – c(t = 400µs) = γ(t) × θch – c = 0.08 × 4.17 = 0.3336°C/W Therefore, substituting numeric values in equation (1) gives: ( ) Tch = T(s)ch + 1 2 × IAP × V(BR)DSS × θch – c(t) ( ) = 60 + 1 2 × 4 × 80 × 0.3336 = 113.4°C and it can be confirmed that Tch is within the Tchmax ≤ 150°C rating. Thus, it is determined that the value is within the avalanche guarantee range. When more complex conditions or components are involved, individual measures should be taken. Rev.2.00 Aug.23.2004 Page 21 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.2.8 Avalanche Destruction Countermeasures Figure 2.14 shows avalanche destruction countermeasures (methods of suppressing surge voltages). Control system Action 1 Thicken wiring Vin(DC) VGS(in) Driving circuit Action 2 Gate resistance Twisted-pair wires Action 3 CR Zener snubber diode Vout Figure 2.14 Avalanche Destruction Countermeasures In avalanche destruction, destruction is caused by a counter voltage due to floating inductance (inductance load). As a characteristic after destruction, electrodes are shorted. There are three countermeasures for avalanche destruction, as follows. (1) Make large-current path wiring as short and thick as possible to reduce floating inductance. (2) Insert a gate series resistance Rg, and suppress dV/dt. As a surge voltage occurs when switching off, surge voltages are suppressed by making the value of turn-off constant Rg large, but if the value is made too large, switching loss will increase. This should be considered when deciding on the circuit constant. (3) Insertion of CR snubber and Zener diode When a surge absorption snubber, etc., is inserted, the wiring should be made short and thick, and connection should be made directly to the power MOS FET drain and source terminals. 2.3 ASO Destruction (Heat Radiation Design) 2.3.1 Explanation of ASO Destruction ASO destruction refers to a mode in which heat radiation is caused instantaneously and locally, and destruction occurs, when an overcurrent and the used voltage are applied simultaneously due to load shorting, etc., that does not occur in normal operation. It also refers to a mode in which the channel temperature rises excessively due to continuous heat radiation, thermal runaway occurs, and destruction results, when chip heat radiation is not performed properly due to thermal mismatching or a high repetition frequency. 2.3.2 ASO Destruction Countermeasures Figure 2.15 illustrates ASO destruction and countermeasures. Vd Driving circuit Vin(DC) Action 2 Over-current protection circuit Vin R2>>(R1+R3) R2 Rg IC1 Load VGS R1 R3 Q1 10k Vds Id Action 3 Vout ID (A) Action 1 ASO guarantee ID(Pulse) IDC Operating area Rs Heat sink 0 VDS (V) Q1 : 2SK2569, 2SK2980 IC1 : HA17358 Figure 2.15 ASO Destruction (Heat Radiation Design) and Countermeasures Rev.2.00 Aug.23.2004 Page 22 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures There are three countermeasures, as follows. (1) Check inclusion within the forward bias ASO (Area of Safe Operation) guarantee, and that the temperature derating is adequate. (2) If load shorting is predicted, insert an overcurrent protection circuit. If the designed drain load current is exceeded, the voltage arose on Rs is detected, MOS FET Q1 is turned on, shorting occurs between G-S of the main power MOS FET via R3, and it is turned off. In this case the value of R3 is made larger than R1 determined as a normal switching off time constant, and is made a constant that prevents the occurrence of surge at the time of overcurrent (cutoff) protection. Alternatively, it is possible to perform cutoff control of speed at the time of cutoff in a list by means of Q1 gate resistance Rg. MOS FET gate-source drive voltage VGS in normal operation is expressed by equation (1). VGS = Vin × (R3 + R3 + 10kΩ 10kΩ) + (R1 + R2) ……………………(1) VGS is set to a value (VGS = approx. 10 V) at which a power MOS FET operates fully in the on-resistance region. Gate retention voltage VGS(cut) at the time of overcurrent cutoff is expressed by equation (2). VGS(cut) = Vin × R3 R1 + R2 + R3 ……………………………(2) VGS(cut) must be set to a value smaller than power MOS FET gate-source cutoff voltage VGS(off). The VGS(off) temperature characteristic (α = –5 mV to –7 mV/°C) is also taken into consideration. (3) Carry out radiation design allowing a sufficient margin. This is covered in the practical example of radiation design. 2.3.3 Forward Bias ASO (Area of Safe Operation) Figure 2.16 shows a forward bias ASO graph (2SK3082) and the corresponding temperature derating method. (For information on an Area of Safe Operation (ASO), refer to the description of the use of power MOS FET characteristics described earlier.) Drain Current ID (A) Derating Ratio D (%) 1000 Example: 2SK3082(60V/10A, 0.075Ω↓, LDPAK) 100 ID(pulse) rating 10 IDC rating Region limited by 1 on-resistance RDS(on) Guaranteed : Destruction line for point PW = 10µs, 75°C 10µs 100µs DC OpPeWra=tio1n0(mTc1s(m=1ss2h5o°Ct)) Tc = 25°C 0.1 0.1 1 10 100 Drain to Source Voltage VDS (V) ASO Temperature Derating D= Tch(max) – Tc Tch(max) – 25 = 150 – Tc 125 × 100 100 80 60 40 20 0 50 75 100 150 200 Case Temperature Tc (°C) Example: •Derating for PW = 10µs, Tc = 75°C 1) Guaranteed value at Tc = 25°C: Pd(25) = 1500W 2) ∴Pd(75) = Pd(25) × 0.6 = 900W Figure 2.16 Forward Bias ASO Diagram (Area of Safe Operation) With regard to the ASO temperature derating method, PW = 10 µs, Tc = 75°C derating will be described as an example. First, regarding PW = 10 µs and Tc = 25°C guarantee values, this ASO diagram gives a Pd(25) = 1500 W (= Vds × ID = 50 V × 30 A) power line. Then, as Tc = 75°C derating ratio D = 60%, Pd(75) = Pd(25) × 0.6 = 1500 × 0.6 = 900W In the ASO diagram, this is the area indicated by the PW = 10 µs, Tc = 75°C line in figure 2.16. Rev.2.00 Aug.23.2004 Page 23 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.3.4 Load Shorting Resistance and Countermeasures Figure 2.17 shows power MOS FET load shorting resistance (examples of the 2SK1518 and 2SK1522). When a power MOS FET is used in a motor drive application, if the load should short, it is necessary to be able to withstand the conditions without breaking down until the overcurrent protection circuit operates. 1. As shown in figure 2.17, this load shorting resistance is dependent on the power supply voltage VDD (≈ VDS) used, with destruction occurring in a shorter time the greater the value of VDS (as the power applied due to load shorting increases). This destruction time differs from product to product, but the overcurrent protection detection time in the event of load shorting should be set to between 1/2 and 1/3 or less of the destruction time. In the case of a power MOS FET, a setting of between 10 µs and 15 µs or less can be said to be safe. 2. Next, when load shorting occurs, as the short-circuit current an overcurrent of around 5 to 10 times the normal operation current flows, and this is cut off. A point to be noted here is the surge voltage that is generated when this overcurrent is cut off. This is showed as the waveform in figure 2.17. As a current considerably larger than the steady state current flows, it is necessary to set a cutoff turn-on time slower than the steady state on/off speed, and suppress the cutoff surge voltage to the component’s rated voltage VDSS or less. PW: Variable VGS = 10V PG Test sample Target device: 2SK1518(500V/20A, 0.27Ω↓, TO-3P) 1000 2SK1522(500V/50A, 0.11Ω↓, TO-3PL) : 2SK1522 : 2SK1518 Test conditions VGS = 10V Ta = 25°C VDD 500 Measured values for destruction Test Circuit Drain to Source Voltage VDS (V) Check that VDSS is ID not exceeded by over-voltages generated by shutdown when short- VDD circuit occurs Short circuit current shutdown VBR(DSS) Over-currents generated by short-circuit loads must be detected in less than 1/2 to 1/3 of the destruction time PW. 200 100 10 Short-circuit current 2SK1522: About 200 to 280A 2SK1518: About 80 to 120A 20 50 100 200 Pulse Width PW (µs) Example of operating voltage range 500 1000 Figure 2.17 Power MOS FET Load Shorting Resistance and Countermeasures 2.3.5 Heat Radiation Design When carrying out mounting design for power devices, it goes without saying that cooling technology — that is, how heat is to be radiated efficiently under various environmental conditions — is an important consideration, but how to perform theoretical heat calculations efficiently is also important. Examples are given here of practical heat radiation design in which the operating channel temperature of a power MOS FET can be calculated theoretically. 1. Preconditions when using a 2SK1170 (500 V/20 A, 0.27 Ω, TO-3P) are shown below. (1) Operating conditions  Ambient temperature Ta = 50°C  Operating current Id = 8A, 10A (2 conditions)  PW = 10 µs, duty = 50% max (f = 50 kHz operation)  Switching loss P(tf) = 500 W, tf period = 0.2 µs (ton loss is omitted here) Design target: Tch ≤ 120°C Rev.2.00 Aug.23.2004 Page 24 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures (2) Heat sink thermal resistance θf-a: 3 kinds: (I). 0.5°C/W, (II). 1.0°C/W, (III). 1.5°C/W (3) Mounting method: Insulating mica used, silicon grease used (θ(i) + θ(c)) = 0.8°C/W where θ(i): Insulating mica thermal resistance θ(c): Contact thermal resistance Table 2.2 Thermal Resistance of Various Transistor Packages Thermal Resistance Rth(ch-c) (°C/W) Rth(c-a) *1 (°C/W) DPAK TO-220AB Rth(ch-c) = Tj max – Tc Pch 178 80 Package LDPAK TO-220FM TO-3P TO-3PFM (See individual catalog for Pch(W)) 83.3 62.5 55 42 TO-3PL 45 (Rth(i) + No Rth(c)) insulation (°C/W) plate With silicon grease No silicon grease Mica insertion (t = 50 to 100µm) With silicon grease No silicon grease Note: 1. Reference value 0.3 to 0.6 0.3 to 0.5 0.3 to 0.5 0.4 to 0.6 0.1 to 0.2 2.0 to 2.5 1.5 to 2.0 1.5 to 2.0 1.5 to 2.0 0.5 to 0.9 — 2.0 to 2.5 — — 0.5 to 0.8 — 4.0 to 6.0 — — 2.0 to 3.0 Based on these preconditions, a design target channel temperature of Tch ≤ 120°C is set. 0.3 to 0.5 1.0 to 1.5 — — 0.1 to 0.2 0.4 to 0.5 0.5 to 0.7 1.2 to 1.5 2. In this method, allowable power dissipation characteristics under various heat radiation conditions (1) and the power dissipation PD characteristic according to a rise in the power MOS FET channel temperature (2) are calculated, and the point of intersection at which functions (1) and (2) overlap is taken as the channel temperature in the saturation state to be found. Results calculated on the basis of the above operating and environmental usage conditions are shown in figure 2.18. Power Dissipation PD (W) 50 40 Power dissipation PD(M) characteristic of power MOS FET 30 PD(M) = on-resistance loss + switching loss 20 ID = 10A θ(ch-a) = θ(ch-c) + θ(i) + θ(c) + θ(f) = 1.04 + 0.8 + 0.5 = 2.34°C/W (I). θ(f) = 0.5°C/W (II). θ(f) = 1°C/W (I) 42.7 (III). θ(f) = 1.5°C/W (II) The target is a design for B (III) Tch ≤ 120°C E 21.4 D C 10 0 10 2 ID = 8A A Allowable dissipation 1 characteristic PD(f) for three types of heat sink θ(f) at Ta = 50°C Tch – Ta PD(f) = θ(ch-a) 50 100 (120) 150 Channel Temperature Tch (°C) Figure 2.18 Channel Temperature Tch and Power Dissipation PD Rev.2.00 Aug.23.2004 Page 25 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures The procedure to reach figure 2.18 is described below. 3. With reference to the contents of the box below, allowable power dissipation characteristics under the aforementioned various heat radiation conditions (1) and the power MOS FET power dissipation characteristic (2) are calculated. In the calculation of power MOS FET power dissipation PD, power MOS FET on-resistance temperature coefficient α (coefficient when Tch = 25°C is taken as 1.0) can be read beforehand from the Ron-Tc characteristic of the individual data sheet, and that value entered on the horizontal axis as in table 2.3. Table 2.3 shows the calculation results. • Calculate and plot allowable power dissipation straight line PD(f) under each heat radiation condition ((1) in figure) First, find total thermal resistance θ(ch-a) under each heat radiation condition. θ(ch-a) = θ(ch-c) + (θ(i) + θ(c)) + θ(f) ………………(1) From equation (1), θ(ch-a) when using (I) heat sink is as follows: θ(ch-a) = 1.04 + 0.8 + 0.5 = 2.34°C/W (Similarly for (II) = 2.84°C/W, (III) = 3.34°C/W) Allowable power dissipation PD(f) is expressed by equation (2). Three points can be used for the allowable loss curve. PD(f) = Tch – Ta θ(ch-a) ………………………………………(2) Under condition (I), assuming Tch = 50, 100, 150°C gives 0W, 21.4 W, 42.7 W respectively (≈ (150 – 50)/2.34) Calculation can be performed for the 2 conditions (II) and (III) in the same way, and 3 straight lines plotted. • Calculate and plot power MOS FET power dissipation curve PD(M) ((2) in figure) Power MOS FET on-resistance RDS(on) has a positive temperature characteristic. That is to say, there is a curvilinear rise (as shown in individual catalogs) as Tch rises. When power MOS FET total power dissipation PD(M) accompanying the temperature rise when ID = 8A, 10A is found, taking this point into consideration, 2 curves can be drawn. Table 2.3 Calculation of Power MOS FET Power Dissipation PD(M) (Example of 2SK1170) Item Tch(°C) 25 40 60 80 100 120 140 150 Notes RDS(on) temperature coefficient α for Tch = 25°C 1.0 1.09 1.27 1.5 1.73 2.0 2.27 2.41 See Ron-Tc characteristic in individual data sheet MOS power dissipation On-resistance loss PON = ID2 · RDS(on)max ×α· tON T Switching loss *1 PS = tf · P(tf) T Total power dissipation PD(M) PD(M) = PON + PS ID = 8A ID = 10A ID = 8A ID = 10A 8.64 13.5 5 13.6 18.5 9.4 14.7 5 14.4 19.7 11.0 17.1 5 16.0 22.1 13.0 20.3 5 18.0 25.5 14.9 23.4 5 19.9 28.4 Note: 1. For the sake of simplicity, the same PS value is used for both ID = 8 A and 10 A. 17.3 27 5 22.3 32.0 19.6 30.6 5 24.6 35.6 20.8 32.5 Note RDS(on) temperature dependence Note operating frequency 5 dependence 25.8 See separate section for detailed calculation of R, L 37.5 load Ron loss, SW loss 4. In this way, the graph of channel temperature Tch vs power dissipation PD in figure 2.18 is created. First, plot allowable loss characteristic (1) under each heat radiation condition. As ambient temperature Ta = 50°C has been assumed, taking Tch = 50°C as the zero point (as Tch = 50°C is 0 W), and individual allowable loss characteristics can be drawn for the use of 3 kinds of heat sinks. Next, power MOS FET power dissipation (at Id = 8 A, 10 A) calculated in table 4 is drawn, completing the process. Rev.2.00 Aug.23.2004 Page 26 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 5. The way of interpreting figure 2.18 (considering the calculation results) and appropriate measures are described below. • Considering Tch-PD graph results (a) Points of intersection (B), (C), (D), and (E) represent channel temperature Tch in a state of thermal equilibrium under the respective conditions. That is to say, the only conditions that satisfy target design Tch ≤ 120°C are ID = 8 A heat radiation conditions (I) and (II). (Points (C) and (D)) (b) When point-of-intersection channel temperature Tch is 150°C or above, the maximum rating is exceeded. (c) Also, when both loss characteristic points of intersection are absent, as with the heat sink (III) condition, this means that thermal runaway*1 occurs and destruction results. Note: 1. Tch rise Ron increase Loss increase Tch rise and thermal destruction • Provision for design value Tch ≤ 120°C (a) Operating current ID is made 8 A max and heat radiation condition (I) or (II) is applied. (Design target Tch is satisfied by (C) and (D).) (b) In case of use up to operating current ID = 10 A max, the following points (combinations), etc., should be considered and a review conducted. 1) Use a heat sink with smaller thermal resistance than (I). (Improve heat radiation conditions and lower θ(cha).) 2) Lower θ(ch-c) by changing the component package. Example: TO-3P/2SK1170 → TO-3PL/2SK1629 3) Change MOS FET to a one class higher low-on-resistance component. However, with high-speed operation (f = 100 kHz or higher), switching loss P(tf) must also be considered (as there is generally a trade-off between on-resistance Ron and switching time tf). 6. Figure 2.19 gives further information on the method of use and points for attention concerning figure 2.18. Tables 2.4 and 2.5 show power MOS FET loss calculation equations and calculation methods. Figure 2.20 show the calculation method for peak channel temperature Tch(peak) and thermal resistance θchc(PW/T) in repeat operation. When the applied voltage is transient, use the transient thermal resistance θch-(t) to calculate the line indicating allowable power dissipation PD(f)(t) Under transient conditions, crossing-points (H),(J),(K),and (L) are all under 60°C while PW≤10ms even at ID = 10A. When calculating channel temperature Tch from a directly measured temperature Tc of the casing of the MOS FET, use the following equation: Tch = Tc + θch-c · PD(M) Measure the temperature at thermal equilibrium. In the diagram, move dissipation line (2) horizontally so that point (A) is at Tc and Tch(x) of (F) and (G) at Tc(x) can then be obtained. •Check that the surface of the casing of the device is in contact completely with the surface of the heat sink (minimize contact thermal resistance). •Check that there are no heat sources around the device (prevent a rise in Ta). •Check that there are no metallic particles between the insulating plate and the heat sink (prevent short-circuits between the device and heat sink fins after heating). Power Dissipation PD (W) Thermal equilibrium Transient (infinity heat sink) 50 PW = 10ms PW = 1ms 3 thermal status Tch – Ta PD(f)(t) = θch-c(t) 2 PD(f) = Tch – Ta θch-c The target is (I) 40 design for (II) Tch≤120°C B (III) 30 Total power dissipation PD(M) of power MOS FET 20 ID = 10A ID = 8A 10 A 0 10 LJ G C E D KH F 1 Thermal equilibrium(with heat sink) Allowable dissipation characteristic PD(f) Tch – Ta for three types of heat sink θ(f) at Ta = 50°C PD(f) = θ(ch-a) 50 100 (120) 150 Channel Temperature Tch (°C) Figure 2.19 Relationship between Channel Temperature Tch and Power Dissipation PD Rev.2.00 Aug.23.2004 Page 27 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures (4) Power MOS FET loss calculation Table 2.4 Power MOS FET Loss Calculation Category Resistance R load Operating Waveform tr ton tf Vds Id 0 T t No. Operation Period 1 tr period Ptr 2 ton period Pton 3 tf period Ptf Average Loss Calculation Ptr = 1 6 (Vds ⋅ Id + 2Id2 ⋅ Ron ⋅ α) tr T Smaller than term 1 and can be ignored. Pton = Id2 ⋅ Ron ⋅ α ⋅ ton T Ptf = 1 6 (Vds ⋅ Id + 2Id2 ⋅ Ron ⋅ α) tf T Inductance tr ton tf 1 tr period Ptr L load Vds Vds(p) 2 ton period Pton Ib Ia Id 0 T t 3 tf period Ptf Note: 1. α: Ron thermal coefficient (= T(×°C)/T (25°C)) Solid line Dashed line Smaller than term 1 and can be ignored. [Much smaller than item 2 or 3 and can be ignored. Pton = 1 3 (Ia2 + Ia ⋅ Ib + Ib2) Ron ⋅ α ton T Pton = 1 Ib2 ⋅ Ron ⋅ α ⋅ ton 3 T Ptf = 1 2 Vds(p) ⋅ Ib ⋅ tf T (5) Examples of power MOS FET loss calculation (for reference) Table 2.5 Examples of Power MOS FET Loss Calculation (for Reference) Category Resistance R load Ptf loss during tf period Operating Waveform tr ton tf Vds Id 0 T t Inductance L load Pton loss during ton period (Current is indicated by solid line) tr Vds Ia 0 ton Ib Id t tf Vds(p) T Loss Calculation (Ron thermal coefficient α omitted) Ptf = 1 T ∫ tf 0 Vds(t) ⋅ Id(t) dt {( ) }( ) = 1 T ∫ tf 0 Vds – Id ⋅ Ron tf t + Id ⋅ Ron – Id t + Id dt tf {( ) ( ) } = 1 T ∫ tf 0 Id2 ⋅ Ron – Id ⋅ Vds tf2 t2 + Id ⋅ Vds – 2Id2 ⋅ Ron tf t + Id2 ⋅ Ron dt [( ) ( ) ] = 1 T Id2 ⋅ Ron – Id ⋅ Vds 3tf2 t3 + Id ⋅ Vds – 2Id2 ⋅ Ron 2tf tf t2 + Id2 ⋅ Ron ⋅ t 0 ∴ Ptf = 1 6T tf(Vds ⋅ Id + 2Id2 ⋅ Ron) ≈ 1 6 Vds ⋅ Id tf T Pton = 1 T ∫ ton 0 Id2(t) ⋅ Ron dt ( ) = 1 T ∫ ton 0 Ib – Ia t + Ia ton 2 ⋅ Ron dt {( ) ( ) } = 1 T ∫ ton 0 Ia2 – 2Ia ⋅ Ib + Ib2 ton2 t2 + 2 Ib – Ia ton t ⋅ Ia + Ia2 Ron dt [{( ) ( ) } ] = 1 T Id2 ⋅ Ron – Id ⋅ Vds 3tf2 t3 + Ia ⋅ Ib – Ia2 ton ton t2 + Ia2 ⋅ t Ron 0 ∴ Pton = 1 3 (Ia2 + Ia ⋅ Ib + Ib2) Ron ton T Rev.2.00 Aug.23.2004 Page 28 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures (6) Repetition frequency Tch(peak), thermal resistance θch-c(PW/T) Tj(peak) ∆Tch(p) Channel Temperature Tch (°C) Loss Pd (W) ∆Tch(AV) Tc Case temperature Tc ∆Tch PW Pd 0 Time t (s) 0 Time t (s) Figure 2.20 Repetition Frequency Tch(peak), Thermal Resistance θch-c(PW/T) { ( ) } Tch(peak) = Tc + ∆Tch = Tc + Pd PW θch-c + 1 – PW θch-c(PW) ……………(1) T T ( )PW θch-c T = Tch(peak) – Tc = ∆Tch …………………………………………………(2) Pd Pd From equations (1) and (2): ( ) { ( ) } PW θch-c T = θch-c PW T+ PW 1– T θch-c(PW) θch-c ……………………………………(3) Normalized transient thermal resistance γs(PW) = θch-c(PW) θch-c ………………………………………………(4) Repetition ducy cycle n(%) = PW T × 100 ……………………………(5) From equations (4) and (5), thermal resistance θch-c(PW/T) for a pulse of width t = PW and perioed of one repetition T is given by equation (6): ( ) { ( ) } PW θch-c T = θch-c n n + 1– γs(PW) …………………………………………(6) 100 100 Here, θch-c is a dc thermal resistance. 2.4 Internal Diode Destruction 2.4.1 Explanation of Internal Diode Destruction Internal diode destruction is a destruction mode that occurs when the parasitic diode between the drain and source of a power MOS FET is used actively. It is limited to use in DC/AC inverters utilized in motor control, uninterruptible power supply (UPS), and similar H bridge circuits. Internal diode destruction occurs only in the above uses, and applies especially to components with a withstand voltage of 250 V or above used at high voltages, but in recent years the destruction mechanism has been clarified, and component diode destruction resistance has been improved. With most 250 to 600 V high-withstand-voltage AP3-H, AP3-HF (internal high-speed diode), and AP4-H series products, destruction countermeasures are incorporated into the component design. From an application standpoint, the AP3-H and AP5-HF series are recommended for these uses. With components with a low withstand voltage of 100 V or below, this destruction problem almost never occurs as the voltage used is also low. Rev.2.00 Aug.23.2004 Page 29 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures Figure 2.21 shows an inverter circuit using general power MOS FETs and the power MOS FET operation waveform in a full bridge circuit. In this circuit, Q1 and Q4 operate and PWM control is performed by the Q1 component. Q4 is always on during the Q1 PWM control period. When Q1 current ID1 flows and is then turned off, motor inductance L regenerative current IF flows through the Q2 internal diode. When Q1 is turned on again in this state, due to the influence of Q2 internal diode reverse recovery time trr, in this period Q1 and Q2 enter the conduction state, short-circuit current irr flows and recovers, and at the same time the internal diode voltage (VDS) also recovers. Input signal(voltage) VDD Q1 waveform PWM control Q1 (1) Current during forward rotation Q3 ID1 0 VDS1 0 Irr Current flowing through Q2 diode (current during recirculation) ID1 M IF 0 Input signal(voltage) Irr Q2 Q4 VDS2 0 (3) Current during period trr IF (2) Current during recovery Figure 2.21 Power MOS FET Operation in Full Bridge Figure 2.22 shows the structure and equivalent circuit of a power MOS FET. As shown in this figure, an internal diode is formed between the source and drain structurally, and is also called a parasitic diode. Source Gate D RDS(on) Body Diode N+ P N– N++ Drain Device Structure (N-Channel Example) Cgd Cds rg G Cgs Rb Parasitic Bipolar S Transistor Power MOS FET Equivalent Circuit Figure 2.22 Power MOS FET Component Structure and Equivalent Circuit Rev.2.00 Aug.23.2004 Page 30 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures Figure 2.23 shows the internal diode destruction mechanism. As stated earlier, internal diode destruction resistance has improved considerably, and structural measures have been taken to inhibit parasitic bipolar transistor operation, so that the problem of destruction almost never occurs during normal use. D RDS(on) Built-in diode Cgd rg G Cgs Cds iMOS iBip Rb S irr Destruction occurs while the diode voltage is recovering. iF 0 di/dt A VDD dV/dt 0 trr irr B t If di/dt changes sharply during the reverse recovery of diode, an excess recovery current flows and dV/dt rises sharply during the reverse recovery period (period B), and this makes the parasitic bipolar transistor between the drain and the source turn on in part of the cells around the gate or source electrode and may lead to destruction of the diode. When the damaged product is disassembled and examined, traces of the destruction are visible around the gate or source electrode. In P-channel products, parasitic PNP transistors have lower carrier mobility and a lower hfe than NPN transistors. Therefore, the PNP transistors do not turn on as easily and destruction more seldom occurs. Figure 2.23 Internal Diode Destruction Mechanism 2.4.2 Example of Internal Diode Destruction Circuit Countermeasures Figure 2.24 shows examples of internal diode destruction circuit countermeasures (usage precautions). 1. Increase gate resistance Rg of the MOS on the PWM control side to reduce di/dt when the diode is short-circuited, and to reduce irr (thus reducing dV/dt) 2. Reduce the wiring inductance of the circuit to reduce dV/dt and the voltage spike during diode recovery. 3. Insert a snubber circuit to reduce dV/dt and the voltage spike during diode recovery. IF NG: Before preventive action VDS OK: After preventive action VDD Action 1 Rg Action 2 Thicken wiring M Action 3 CR snubber (Between D-S) Figure 2.24 Examples of Internal Diode Destruction Circuit Countermeasures Rev.2.00 Aug.23.2004 Page 31 of 49 REJ05G0001-0200 Internal Diode Destruction Current IF (A) Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures Figure 2.25 shows actual data before and after countermeasures for internal diode destruction resistance of 500 V highwithstand-voltage components (now discontinued). AP3/AP5-HF series (high-speed diode included) After preventive action AP3-H, AP4-H AP2 series (Bfter preventive action) Test conditions: •VCC = 350 V •VGS = +15V, –10V •PW = 10µs(1shot) •Tc = 25°C 5 10 20 50 100 200 500 1000 di/dt (A/µs) 400 800 1000 2500 3500 5000 6000 dV/dt (V/µs) 1k 470 330 100 56 Gate Resistance Rg (Ω) 20 10 Note: The relationship between gate resistance Rg and di/dt or dV/dt depends on the voltage used and the wiring inductance of the application system. Check the waveform in the actual application. Figure 2.25 Internal Diode Destruction Resistance (500 V/10 A Class Examples) 2.5 Destruction Due to Parasitic Oscillation 2.5.1 Explanation of Destruction Due to Parasitic Oscillation Gate parasitic oscillation mainly occurs when power MOS FETs are connected in parallel and are directly connected without inserting a gate resistance. This parasitic oscillation occurs in a resonant circuit formed by gate-drain capacitance Cgd(Crss) and gate lead inductance Lg when the drain-source voltage is turned on and off at high speed. When the resonance condition (ωL = 1/ωC) occurs, an oscillation voltage much larger than drive voltage Vgs(in) is generated in Vgs between the gate and source, as a result of which gate destruction occurs due to a voltage exceeding the gate-source rated voltage, or the oscillation voltage when the drain-source voltage is turned on and off is superimposed on the Vgs waveform via gate-drain capacitance Cgd and positive feedback occurs, leading to oscillation destruction due to mal operation. Rev.2.00 Aug.23.2004 Page 32 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.5.2 Power MOS FET Parasitic Oscillation Mechanism Figure 2.26 shows a parallel equivalent circuit. Vds(p) D Ld RDS(on) Ld RDS(on) The voltage oscillation due to resonance changes in proportion to the selectivity Q(=ωL/R=1/ωCR) of the resonant circuit: voltage Vc generated at capacitance C is given by equation (1) and voltage VL generated at inductance L is given by equation (2). Cds Cgd Cgd Cds Vin Rb Cgs Ls Cgs Rb Ls Vin 0 T f = 1/T Vin: Supplied voltage I R L C Vc = Q · Vin QVgs(p) GS Vgs Lg: Gate lead inductance (including wiring on the board) Ls: Source lead inductance (including wiring on the board) Ld: Drain lead inductance (including wiring on the board) Resonant Circuit of R, L, and C rg: MOS gate resistance Rg: External gate resistance Vc = (1/2πfC)I = (1/ωCR)V = QV ⋅⋅⋅⋅⋅⋅⋅⋅⋅(1) Cgs: Gate-source capacitance VL = (2πfL)I = (ωL/R)V = QV ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅(2) Cgd: Gate-drain capacitance L Cds: Drain-source capacitance Here, Q = ωL/R = 1/ωCR = C Power MOSFET Equivalent Circuit R Resonance frequency fr = 1 2π LC Figure 2.25 Power MOS FET Parasitic Oscillation Mechanism When power MOS FET parallel connection is performed by means of direct connection without using a gate series resistance, a parasitic oscillation waveform appears in the gate. With this parasitic oscillation, oscillation voltage Vds(p) passes through gate-drain capacitance Cgd(Crss) due to load wiring inductance Ld when the drain-source voltage is turned on and off at high speed, and particularly when it is turned off, and a resonant circuit with gate lead inductance Lg is formed. As gate internal resistance rg of a large-current, high-speed power MOS FET is extremely small, at 1 to 2 Ω, when there is no gate external resistance Rg, oscillation circuit Q — that is √L/C/R — becomes large, and when the resonance condition occurs, a large oscillation voltage is generated between that point and Cgd(Crss) or Lg (that is to say, between the MOS gate and source), and parasitic oscillation is caused. In particular, as large-current operation is performed in the case of parallel connection, if transient current balance becomes poor when switching off, all the currents flow in one MOS FET in a period with deviation of this timing. Generally, this period is an extremely short time of several ns to several tens of ns, and therefore power MOS FET thermal stress is not a problem, but drain-source oscillation voltage Vds(p) may be logically n times greater than this or more (as Ld also appears to be larger due to the skin effect* since a high-frequency large current actually flows in a transition). Skin effect: Phenomenon whereby a high-frequency current flows only through the surface of a conductor, and not through the inner part. When current flows in a conductor, a magnetic flux is generated around the current, and as this crossing with the current, an inductance effect is produced. When a current is passed through a thick conductor that handles large currents, a magnetic flux is also generated in the conductor, and therefore the inductance effect is more intense toward the center of the conductor. Consequently, when a high-frequency current flows in a thick conductor, there is a strong inductance effect in the central part, making it difficult for current to pass through, and current deviates toward the surface of the conductor. In this case, the crosssectional area through which the current flows is reduced, and thus viewed from outside, electrical resistance — that is, inductance — appears to be large. Rev.2.00 Aug.23.2004 Page 33 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures Figure 2.27 shows parasitic oscillation and destruction countermeasures in the case of parallel connection. Thicken the wiring along large current paths to reduce the wiring inductance. Use twisted-pair wires for Vin L power-supply lines between the drain and the source. R1 Drive R2 R1 circuit A Drive R2 R1 circuit B R1 Gate and source drive circuit wiring taken from vicinity of source terminal. In case of high-frequency operation, in particular, use of mounting with drive wiring inductance made small. Insert series resistance R1 near each gate terminal. If the gate wiring becomes long and is connected in parallel, insert an additional resistor R2. Reference value: R1 = 10Ω to 100Ω R1 R2 = 2.2Ω to 4.7Ω Vout R1 R1 R1 Insert a ferrite bead in series with each gate. Figure 2.27 Parasitic Oscillation Reduction and Destruction Countermeasures 2.6 Notes on Parallel Connection Notes on mounting covering precautions concerning parallel connection, and advice on the selection and use of power MOS FET components, are given below. 2.6.1 Notes on Mounting • Low-inductance wiring • Make drain and source wiring lengths equal, and use twisted-pair wiring, etc. • Pay attention to parasitic oscillation (see attachment on parasitic oscillation countermeasures) 2.6.2 Advice on Selection and Use of Power MOS FETs Discussion and agreement with the semiconductor manufacturer are necessary. Align Vth(VGS(off)) value (higher value preferable) ⇒ Align on-resistance RDS(on) ⇒ Apply adequate gate drive voltage ⇒ (4 V drive product: VGS = 5 to 10 V, 10 V drive product: VGS = 10 to 12 V) Avoid avalanche operation as far as possible ⇒ Off-time transient current balance reduction On current balance reduction Heat radiation balance reduction Current concentration in low-withstand-voltage components Rev.2.00 Aug.23.2004 Page 34 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.7 Electrostatic Destruction 2.7.1 Explanation of Electrostatic Destruction Electrostatic destruction refers to destruction due to static electricity or a surge voltage from a human body or equipment when a product is handled or is being mounted. 2.7.2 Electrostatic Destruction Countermeasures Figure 2.28 shows countermeasures against electrostatic destruction. Action 1 1MΩ Ground the body Action 2 Gate resistance Zener diode Action 3 Gate resistance Zener diode Better result Figure 2.28 Electrostatic Destruction Countermeasures In electrostatic destruction, the gate oxide film is destroyed when static electricity or a surge voltage generated by a human body, mounting equipment, etc., is applied to a gate. Characteristics seen after destruction are a voltage drop or shorting between the gate and source, shorting between the drain and source, or increased leakage current. (See figure 2.29.) The following three methods are used as countermeasures to electrostatic destruction. (1) Earth human bodies via a 1 MΩ resistance before handling devices. (2) Ensure that equipment is properly earthed. (3) To prevent the application of gate surge voltages that may occur after board mounting, insert a gate resistance and Zener diode. Rev.2.00 Aug.23.2004 Page 35 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.7.3 Destruction Progression Modes after Electrostatic Destruction In figure 2.29, post-gate-destruction characteristic modes are broadly classified into two kinds, and their respective natures are illustrated if the respective destruction products maybe adopted to a set circuit. Damaged product A Electrostatic destruction Damaged product B Between gate and source: short-circuit Between drain and source: short-circuit Between gate and source: decrease in impedance (several hundred Ω to several kΩ) Between drain and source: increase in current leakage The product will not operate as MOS FET. The system will not operate. The product operates as MOS FET. The system operates. Operation continues with a reduced gate impedance. RDS(on) rises. More heat is generated in MOS FET. ASO destruction of the product Figure 2.29 Destruction Progression Modes after Electrostatic Destruction Figure 2.30 illustrates the characteristic modes of destruction products A and B. In the destruction product A mode, there is almost complete shorting between the gate and source and between the drain and source. In the destruction product B mode, although a certain level of resistance (several tens of Ω or more) is maintained between the gate and source, and a curve shape of standing to reverse voltage is keeping although leakage current IDSS between the drain and source is large at several hundred mA to several tens of mA. Gate Current Laekage IGSS (µA) Drain Current ID (mA) Damaged product A + (complete short-circuit) (high-voltage 500V product with gate protection diode) Good product Damaged product B Decreased impedance between G and S Damaged product A (complete short-circuit) [Scale] ID: 2mA/DIV VDSS: 100V/DIV 0 – [Scale] IGSS: 1µA/DIV VGSS: 10V/DIV – + Gate-Source Voltage VGSS (V) VGSS Waveform Damaged product B Increased current leakage IDSS channel waveform Good product Drain-Source Voltage VDSS (V) VDSS Waveform Figure 2.30 Sample Electrostatic Destruction Product VGSS and VDSS Waveforms Rev.2.00 Aug.23.2004 Page 36 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.7.4 Mechanism whereby Gate Destruction Product B Come to ASO Destruction When the destruction product A mode is temporarily incorporated in a set circuit, the circuit naturally does not operate, a short-circuit current flows between the MOS FET gate and source when power is turned on, and destruction traces increase. When a mode such as the destruction product B mode is temporarily adopted to a set circuit, since drain-source withstand voltage is maintained (although when leakage current IDSS is large, power consumption increases in the off state and causes a rise in component temperature), according to the circuit gate signal source resistance RS constant and gate-source resistance RGS immediately after destruction, a voltage with drive capability is applied between the gate and source, so that although drive voltage VGS appears to fall, switching operation is performed. This state is illustrated in figure 2.31. As the gate impedance decreases, VDS(on) increases, then the loss increases, and finally destruction occurs. 10 25 Drain-Source On-Voltage VDS(on) (V) Operating Current ID (A) 20 15 ID = 1A Non-saturation region(large loss) 10 Saturation region for on-resistance 5 (low loss) 0 0 2 4 6 8 10 Gate Driving Voltage VGS (V) VGS = RGS RS + RGS × Vin In the normal product, RGS ≈ ∞; therefore, VGS = Vin when RGS>>RS Destruction 1 0.1 Allowa(wbliethlohsesatwshinekn)mounted Ta = 25°C 0.01 10 30 100 300 1000 Operating Voltage VDS (V) RGS: G-S resistance of product B with its gate damaged RS: Signal source resistance (external) of the circuit Vin: Gate input voltage Figure 2.31 Mechanism whereby Gate Destruction Product B Reaches ASO Destruction When, for example, a destroyed product B mode gate destruction sample with gate-source resistance value RGS = 100 Ω immediately after gate destruction and drain-source leakage current IDSS = 1 mA is temporarily incorporated in an operating circuit with power supply voltage VDD = 24 V, gate input voltage Vin = 10 V, gate signal source resistance RS = 22 Ω, and on-duty D = 0.3, when the actual gate drive voltage VGS and off-time power consumption Poff of this component are calculated, VGS = 8.2 V and Poff = 16.8 mW as shown below, and generally, in the case of a logic-level drive component, the component operates adequately. VGS = RGS RS + RGS × Vin = 100 22 + 100 × 10 ≈ 8.2V Poff = VDD × IDSS × (1 – D) = 24 × 1 × 10–3 × 0.7 = 16.8mW However, as gate-source resistance value RGS of this destroyed product may well decrease further, in that process gate drive voltage VGS becomes insufficient. As a result, on-resistance increases (a complete on-resistance operation onstate is not established, and operation is performed in a state in which VDS(on) has increased as shown in figure 2.31), and power consumption increases, and eventually component ASO destruction occurs. In a case such as this, subsequent analysis of the destroyed product shows a close resemblance to thermal destruction due to exceeding of the component ASO, but it is possible that the destruction mode constituting the initial trigger was a gate destruction mode. However, it is extremely difficult to determine whether it is the latter case or not by destroyed product because destruction traces have increased. Therefore, at the very least, care must be taken in handling (including component measurement) up to embedding in a circuit. Rev.2.00 Aug.23.2004 Page 37 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.8 Usage Notes 2.8.1 Power MOS FET Main Loss Frequency Dependence and Relationship to Main Characteristics Figure 3.32 shows “power MOS FET main loss frequency dependence and relationship to main characteristics” in the case of use in a DC-DC converter. Switching loss and drive loss increase at higher frequencies. In order to make full use of component performance and reduce total loss, it is necessary to achieve a balance with onresistance loss by appropriately setting and controlling the gate drive voltage in the high-frequency region. In general, when a logic-level drive component is operated at operating frequency f = 200 to 300 kHz or below, in order to minimize on-resistance, applying a gate drive voltage VGS of around 10 V is effective from a total loss standpoint. Applying a higher voltage (for example, VGS = 15 to 17 V) is not really recommendable as drive loss only increases. At high-frequency operation of f = 500 kHz or more, reducing total loss by optimization in a gate drive voltage VGS range of 5 to 8 V is effective in achieving higher efficiency. On-Resistance R DS(on) (mΩ) MOSFET Loss P (W) DC/DC Converter Example of HAT2064R (Calculated Values) 2.0 Vin = 5V, Vout = 1.6V High Side ID = 10A Relationship between Loss and Main Characteristics 1.5 20 ID = 10A 1.0 15 Drive loss Switching loss 16 Qg = Qg 20nC(VGS = = 40nC(VGS 4.5V) = 10V) 12 0.5 10 8 5 0 0 On-resistance loss 0 10k 20k 50k 100k 200k 500k 1M 2M 12 (V) Operating Frequency f (Hz) Gate 4 to Source 8Voltage VGS In the high-frequency region (500 kHz or above), total loss is reduced by means of gate drive voltage VGS optimization. V DS 24V = 10V Gate1C0harge 20 Amount 30 Qg (nC) 4 400 Figure 2.32 Power MOS FET Main Loss Frequency Dependence and Relationship to Main Characteristics 2.8.2 Malfunction (Arm Shorting) Countermeasures in Motor Application Figure 2.33 illustrates arm shorting in a small motor drive application, and applicable countermeasures, when P-channel and N-channel MOS FETs are used in combination. This figure shows the upper P-channel MOS FET in the off state and the lower N-channel MOS FET in a chopping operating state. In figure 2.33, the voltage waveform at point A is as shown in the figure, but as the lower N-channel MOS FET is now turned on and VDD changes to 0 V, a charge current flows transiently via Crss and Ciss of the upper P-channel MOS FET, and a ∆VGS(t) = {Crss/(Ciss+Crss)}∆VDS(t) peak voltage is generated between the gate and source. When this ∆VGS(t) peak voltage exceeds Vth of the P-channel MOS FET, the upper and lower components go to the on state simultaneously, an arm short-circuit current flows, and excessively large loss is caused. Rev.2.00 Aug.23.2004 Page 38 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures In the case of use in an H bridge circuit, the other arm is also similarly susceptible to the occurrence of this phenomenon with an N-channel component. The upper/lower component shorting phenomenon at the time of this transition is liable to occur under the following conditions. 1. More likely to occur the faster the switching operation (especially turn-on time) and the steeper dV/dt 2. More likely to occur the larger signal source resistance RG (gate off-time constant) 3. More likely to occur the larger the Crss/Ciss values of the components used (KS = {Crss/(Ciss+Crss)} · VDD is a larger value than Vth of the component) 4. More likely to occur the higher power supply voltage VDD Of items 1 to 4, item 4, power supply voltage VDD is determined by the application and cannot be changed, so countermeasures are shown for remaining items 1 to 3. 1. Slow the turn-on time to suppress dV/dt (make gate resistance R1 in the figure larger). 2. Make gate off-time signal source resistance RG (MOS FET driver signal source resistance RS and off-time external resistance constant Rg) smaller, and set low impedance between the gate and source. 3. Insert capacitance C1 between the gate and source, make (KS = {Crss/(Ciss+C1+Crss)}VDD smaller, and provide a margin. Also, select an component with a small KS and high Vth. Vgs(t) Ciss VDD Crss Vgs(t) Voltage at point A VDD 0 Current ID 0 Shortcircuit current Input signal VGS 0 PWM control (f = 20kHz or more) VDD Shortcircuit current Pch Point A M dv/dt Id Nch •Sample Preventive Action R2 C1 R3 Set a lowish resistance value that does not compromise switching loss (efficiency), and insert C1 between G-S if necessary. PWM signal R1 Make resistance R1 large and suppress dv/dt at point A. VDD Pch M Nch Figure 2.33 Malfunction (Arm Shorting) Countermeasures In Motor Application Rev.2.00 Aug.23.2004 Page 39 of 49 REJ05G0001-0200 Power MOS FET 2. Power MOS FET Destruction Mechanisms and Countermeasures 2.8.3 Non-Isolated Synchronous Rectification Converter Low-Side Self-Turn-On Phenomenon In appearance, this is similar to the above-described arm shorting phenomenon. Figure 3.34 illustrates the low-side self-turn-on phenomenon in a non-isolated synchronous rectification circuit. This phenomenon occurs at the switching timing at which high-side component Q1 is turned on while low-side component Q2 is off, and when the Q2 drain-source voltage changes abruptly from VDS ≈ 0 to VDS = Vin, Ciss is charged via Crss of Q2, and Q2, which should really be off, is turned on. That is to say, when VGS(Q2) = (Crss/Ciss + Crss) × dV(t) (equation (1)) exceeds Vth of Q2, self-turn-on occurs. As a result, Q1 and Q2 become on simultaneously, and excessive loss is generated, component heat radiation and a temperature rise are caused, leading to degradation of efficiency. Regarding the low-side component characteristics, due to large-current operation, low RDS(on) design is necessary, and therefore there is a tendency for the capacitance relationship (Ciss, Crss) to be large. Regarding the high-side component characteristics, due to the design emphasizing high speed, high-speed switching characteristics are implemented, and dV/dt becomes steeper. This suggests a tendency of susceptibility to the self-turn-on phenomenon. Generally, the following two circuit countermeasures can be used. 1. Make only the high-side component turn-on time slower (suppress dV/dt). 2. Insert a capacitance C externally between the gate and source of the low-side component and (by making (KS = (Crss/Ciss + Crss) smaller) improve the self-turn-on margin. As a future trend, it is necessary to make both Ciss and Crss smaller in component design for high-frequency operation (1 MHz or above) and also make improvements that take account of the ratio of Ciss and Crss (Crss<> 1/jωCiss), and component performance can be fully exploited by means of these techniques. VDS: 10V/DIV VGS: 5V,2V/DIV •Smaller, thinner →higher frequency •Lower-voltage CPU core Narrow pulse control from hi-side Lo-side large-current operation (lower Ron) Hi-side component high-speed Hi-dV/dt control Lo-side component capacitance (Ciss, Crss) increase Conditions susceptible to self-turn-on (Both component and circuit) Tek stoppage Lo-Side VGS (2V/DIV) 1 2 Self-turn-on Hi-Side VDS Lo-Side VDS Self-turn-on (ts = approx. 10ns) M Hi-Side VGS (5V/DIV) Ch1 10.0V Ch2 10.0V M 40.0ns A Ch1 Ch3 2.00V Math 5.00V 40.0ns T 50.40% t: 40ns/DIV Self-Turn-On Waveform 20.0V Vin Hi-Side Q1 dV/dt PWM Control IC Crss PW = Vout Vin T T Vout Q2 Ciss Lo-Side VGS(Q2) = Crss Ciss + Crss dVds(t) • Lower impedance when gate is off • Reduced wiring inductance Figure 2.34 Problems in Synchronous Rectification Circuit Rev.2.00 Aug.23.2004 Page 40 of 49 REJ05G0001-0200 Power MOS FET Application Note 3. Power MOS FET Applications 3.1 Application Map Figure 3.1 shows a power MOS FET and IGBT application map. Drain Current ID (A) 500 200 100 50 20 10 5 2 10 VRM DC/DC converters Power management switches EPS control Starter generator systems ABS Solenoids Pump relays Automotive field Injector Drive IGBT EV UPS Inverters Airbags Ignition Engine control Solenoid drive Lamps Relay switching Step-up/Down DC/DC power supply control Discharge lamp Discharge/Boosting SW power supplies 20 30 50 100 200 Drain to Source Voltage VDSS (V) 500 1000 Figure 3.1 Power MOS FET and IGBT Applications Rev.2.00 Aug.23.2004 Page 41 of 49 REJ05G0001-0200 Power MOS FET 3. Power MOS FET Applications 3.2 Automotive Applications 3.2.1 Technological Trends in Automotive Electrical Equipment Figure 3.2 illustrates technological trends in automotive electrical equipment. 80-100V MOS FET M Starter M Generator 42V(rating) 58V(max.) High output 42V Load 14V(rating) DC/DC converter 16V(max.) 14V Load 42V 80-100V 14V MOS FET 42V Battery Door Mirror Keyless System Starter+Generator D7 Pch 100V (D7-L large-current detection function included) In-Vehicle LAN Thermal FET (HSOP20 etc.) (built-in protection and diagnostic functions) i mode Map information offer HID 400V D6-H VB Motor PC MPU Navigation DC/DC DVD Wireless access control DAD Video Radar Traffic Safety Support System Injector HEV Inverter 100V D7-L 5th Generation IGBT HEV Power Supply DC/DC Converter 500V AP5-H (Vin=160 to 400V → Vout=14V/80A) VSC 60V D7-L Small SMD ASV (Advanced Safety Vehicle) Figure 3.2 Technological Trends in Automotive Electrical Equipment 3.2.2 Sample Automobile ABS Application Figure 3.3 shows a sample automobile ABS application. Typical Models 2SK3135 2SK3553 Battery Power Supply System Fail-Safe IC Control CPU Charge Pump IC Lamp Typical Models 2SK2788 Hydraulic Motor Sensors Dedicated Linear IC Predriver IC Typical Models 2SK2869 2SK2926 HAT2033RJ HAT2038RJ Figure 3.3 Sample Automobile ABS Application Rev.2.00 Aug.23.2004 Page 42 of 49 REJ05G0001-0200 Power MOS FET 3. Power MOS FET Applications 3.2.3 Sample Automobile Power Steering Application Figure 3.4 shows a sample automobile power steering application. VB Battery Fail-Safe Control IC CPU Forward/Reverse Control Predriver IC Dedicated IC VB Hydraulic Valve Actuator Monitor Torque sensor Current sensor Steering Typical Models 2SK3163 2SK3136 2SK3418 Figure 3.4 Sample Automobile Power Steering Application 3.2.4 Sample Automobile HID Headlamp Control Application Figure 3.5 shows a sample automobile HID headlamp control application. 60V NMOS Reverse Connection Prevention Circuit Battery Control IC Control IC Power MOS FET HID Control IC 200 to 250V NMOS Step-Up Power Supply Circuit 500V NMOS Discharge Control Circuit Figure 3.5 Sample Automobile HID Headlamp Control Application Rev.2.00 Aug.23.2004 Page 43 of 49 REJ05G0001-0200 Power MOS FET 3.3 Power Supply Applications 3.3.1 Switching Power Supplies • Application equipment Network servers, WS (workstations), RAID Figure 3.6 shows a sample switching power supply application. 3. Power MOS FET Applications RAID Application Blocks Application MOS FET PFC PFC+PWM 500V DC/DC 500V Secondary-side 30 to 60V synchronous rectification Hot swap 20 to 30V VRM 20 to 30V * : Under development Control IC HA16142 HA16158* HA16341 HA16342 — Server (PC, Network) (N+1) Built-in Schottky diode 5V HAT2180RP 12V 2.5V PWM IC DC/DC (under 5V converter develop- ment) HAT2211RP 1.8V PFC DC/DC Secondary-side synchronous rectification Hot swap H7N0307LM × n 5V 2SK3235 × n Vin AC 2SK3235 × n PFC AUX Voltage Detector Primary IC HA16142 DC/DC Main Synchronous Current Share SW Rectification Hot Swap Secondary IC HA16342 Figure 3.6 Sample Switching Power Supply Application Rev.2.00 Aug.23.2004 Page 44 of 49 REJ05G0001-0200 Power MOS FET 3. Power MOS FET Applications 3.3.2 DC/DC Converters • Application equipment Notebook PCs, VCR cameras, on-board power supply secondary side, lithium-ion battery pack overcharging protection Figure 3.7 shows a sample DC-DC converter application. TFT Backlight Power Supply AC Adapter Charger DC/DC converter Number of MOS FETs Used Li Ion Power management TFT Backlight Total Number of DC/DC switch Power Supply MOS FETs Used 2 to 4pcs 8 to 10pcs 4 to 6pcs 1 to 2pcs 15 to 22pcs AC Adapter DC/DC Power Management Converter Switch HAT2198R × n 1.5V Lithium-Ion Battery Pack DC/DC Converter Power Supply Power Management Switch HAT1048R × 2 PWM IC HAT2195R × n Vb HAT2180RP CPU + HZM6.2Z AC Adapter Charger Monitoring IC HAT1048R HAT1072H FY7BCH-02F for main MOS driver Micro FET 2SJ576 2SK3289 Battery Pack Application Battery Cells Cellular phones (GSM, CDMA) PDCs, mini-discs 1 cell Camcorders, DSCs, DVCs 2 cells Notebook PCs 8,9 cells 4 series 2 parallel 3 series 3 parallel PWM IC Vb HAT1048R 2.5V MPU PWM IC (Power Management) 2.5V HAT2064R 2.5V Vb HAT2211RP HAT1054R 3.3V Memory Load HAT2071R Vb HAT2219R HAT1054R 5.0V HDD CD-ROM DVD Example of Lithium-Ion Battery Overcharging Protection Circuit Use Example of Notebook PC DC/DC Converter System Use Figure 3.7 Sample DC/DC Converter Application Rev.2.00 Aug.23.2004 Page 45 of 49 REJ05G0001-0200 Power MOS FET 3.3.3 VRM (Voltage Regulator Module) • Application equipment Desktop PCs, notebook PCs, network servers, WS (workstations) Figure 3.8 shows a sample VRM application. 3. Power MOS FET Applications Vin = 12V PWM Control IC Hi-Side Single Phase Vout 1.6V CPU Lo-Side Output Voltage Vout (V) CPU Carrier Frequency fc (GHz) Supply Current Iout (A) Vin = 12V PWM Control IC Multi Phase 3 Phase to 4 Phase Vout 1.3V CPU Control IC Circuit Topology 2.0 200 Vout 1.6 1.5 1.0 CPfcU(1GC.aH5rzri)eHr Figrehqu1Ee.n3ncyd 1.2 CPU Iout 150 1.1 1.0 100 Iout 0.5 Note PC Notebook PC 50 Capacity Increase 90W → 120W 0 0 2000 2001 2002 2003 2004 2005 Year Figure 3.8 Sample VRM Application Rev.2.00 Aug.23.2004 Page 46 of 49 REJ05G0001-0200 Power MOS FET 3. Power MOS FET Applications 3.3.4 Base Station SMPS (Switch-Mode Power Supply) Figure 3.9 shows a sample base station SMPS application. AC 6.6kV High-pressure change board DC48V DC/DC DC/DC Battery AC-DC Machinery room AC-DC Communication machine room AC-DC UPS Power supply room Rectifier Diode AC-DC SMPS System MOS FET Input PWM Rectifier Vin(AC) 200V PFC Control PWM IC H5N5005PL (2 to 4pcs/unit) Base Station DC/DC Main Switch C PWM IC H5N5004PL Synchronous Rectifier Control IC Hot Swap Error Voltage Detector Circuit Vout = 48V SBD H5N2507P Shunt SBD Reg IC C 2SK3228 High 500V AP5-HF(Built-in Voltage Fast Recovery Diode) 250V AP5-HF(Built-in Fast Recovery Diode) D6/D7-L Ultra Low RDS(on) Low Voltage Figure 3.9 Sample Base Station SMPS Application HA17341 Rev.2.00 Aug.23.2004 Page 47 of 49 REJ05G0001-0200 Power MOS FET 3. Power MOS FET Applications 3.3.5 Communication Equipment DC/DC Converter Figure 3.10 shows a sample communication equipment DC/DC converter application. Unit Output Voltage Vout (V) Output Current Iout (A) Current Slew Rate (A/µs) DC/DC Converter Power Supply System Power THM(Thermal Temperature Resistor) Thermistor → to MOS FET DC/DC main DC switch 48V Inrush current control circuit Lower future LSI operating voltage: 5 V, 3.3 V → 1.5 V to 2.0 V Secondary-side SBD rectification → MOS synchronous synchronous rectification system Voltage fluctuation rectifier increase detection control Vout = 1.5 to 2.0V at η = 90%↑ Control IC Shunt Reg IC Trends in Output Voltages and 2.0 Current Demand for DC/DC 200 Output Current Vout 1.6 Current Slew Rate 1.5 1.5 150 1.3 1.2 1.0 1.0 100 0.8 HAT2058R Control IC 200V to 250V AP5-H Low Ron/Qgd HAT2077R H5N2508DS Shunt regurator IC HA17L431ALP D7-L Ultra Low Ron & Low Qg/Qgd 30V/5.0mΩ/SOP-8(HAT2064R) 30V/2.9mΩ/LFPAK(HAT2099H) 0.5 50 0 0 2000 2001 2002 2003 2004 2005 Year Figure 3.10 Sample Communication Equipment DC/DC Converter Application Rev.2.00 Aug.23.2004 Page 48 of 49 REJ05G0001-0200 Power MOS FET 3. Power MOS FET Applications 3.4 Motor Drive Applications 3.4.1 Small Motor Drive • Application equipment Application Function H bridge HDD (voice coil motor) Camera motor, electronic throttle 3-phase HDD (spindle motor) PPC, printer (paper feed motor, polygon mirror) Figure 3.11 shows sample small motor drive applications. •Camera (H bridge) •PPC, Printer Laser diode Polygon mirror Toner Drum Paper feed motor +VDD M •HDD of Server, etc. (Spindle motor drive) +VDD U V W R Sense Figure 3.11 Sample Small Motor Drive Applications Rev.2.00 Aug.23.2004 Page 49 of 49 REJ05G0001-0200 Power MOS FET Application Note Publication Date: Rev.2.00, August 23, 2004 Published by: Edited by: Sales Strategic Planning Div. Renesas Technology Corp. Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd.  2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Power MOS FET Application Note

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