首页资源分类嵌入式处理器ARM MCU > STM32F10X芯片手册

STM32F10X芯片手册

已有 445500个资源

下载专区

上传者其他资源

    文档信息举报收藏

    标    签:STM32F10X系列手册STM32

    分    享:

    文档简介

    STM32F10X系列手册

    文档预览

    STM32F105xx STM32F107xx Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces Features I Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division I Memories – 64 to 256 Kbytes of Flash memory – up to 64 Kbytes of general-purpose SRAM I Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 3-to-25 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC with calibration – 32 kHz oscillator for RTC with calibration I Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers I 2 × 12-bit, 1 µs A/D converters (16 channels) – Conversion range: 0 to 3.6 V – Sample and hold capability – Temperature sensor – up to 2 MSPS in interleaved mode I 2 × 12-bit D/A converters I DMA: 12-channel DMA controller – Supported peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs I Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M3 Embedded Trace Macrocell™ I Up to 80 fast I/O ports – 51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant I CRC calculation unit, 96-bit unique ID LQFP100 14 × 14 mm LQFP64 10 × 10 mm I Up to 10 timers with pinout remap capability – Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 1 × 16-bit motor control PWM timer with dead-time generation and emergency stop – 2 × watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter – 2 × 16-bit basic timers to drive the DAC I Up to 14 communication interfaces with pinout remap capability – Up to 2 × I2C interfaces (SMBus/PMBus) – Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 3 SPIs (18 Mbit/s), 2 with a multiplexed I2S interface that offers audio class accuracy via advanced PLL schemes – 2 × CAN interfaces (2.0B Active) with 512 bytes of dedicated SRAM – USB 2.0 full-speed device/host/OTG controller with on-chip PHY that supports HNP/SRP/ID with 1.25 Kbytes of dedicated SRAM – 10/100 Ethernet MAC with dedicated DMA and SRAM (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages Table 1. Device summary Reference Part number STM32F105xx STM32F105R8, STM32F105V8 STM32F105RB, STM32F105VB STM32F105RC, STM32F105VC STM32F107xx STM32F107RB, STM32F107VB STM32F107RC, STM32F107VC September 2009 Doc ID 15274 Rev 4 1/95 www.st.com 1 Contents Contents STM32F105xx, STM32F107xx 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 13 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 13 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16 2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 Universal synchronous/asynchronous receiver transmitters (USARTs) 18 2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.20 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 19 2.3.21 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 Universal serial bus on-the-go full-speed (USB OTG FS) . . . . . . . . . . . 20 2.3.23 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.24 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.25 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.26 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.27 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.28 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Contents 2.3.29 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.3 5.1.4 5.1.5 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.1 5.3.2 5.3.3 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35 Embedded reset and power control block characteristics . . . . . . . . . . . 35 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.8 5.3.9 5.3.10 5.3.11 PLL, PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 52 5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Doc ID 15274 Rev 4 3/95 Contents STM32F105xx, STM32F107xx 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 80 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Appendix A Applicative block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A.1 USB OTG FS interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A.2 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 A.3 Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 A.4 USB OTG FS interface + Ethernet/I2S interface solutions . . . . . . . . . . . . 89 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F105xx and STM32F107xx features and peripheral counts . . . . . . . . . . . . . . . . . . 10 STM32F105xx and STM32F107xx family versus STM32F103xx family . . . . . . . . . . . . . . 11 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 35 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 38 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 38 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 HSE 3-25 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Doc ID 15274 Rev 4 5/95 List of tables STM32F105xx, STM32F107xx Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 66 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 67 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 77 LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 78 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Applicative current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 12 STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout . . . . . . . . . . . . . . 23 STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout . . . . . . . . . . . . . . . 24 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 65 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 72 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 72 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 USB OTG FS device mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Host connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 OTG connection (any protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Doc ID 15274 Rev 4 7/95 List of figures STM32F105xx, STM32F107xx Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. RMII with a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 USB OTG FS + Ethernet solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 USB OTG FS + I2S (Audio) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx 1 Introduction Introduction This datasheet provides the description of the STM32F105xx and STM32F107xx connectivity line microcontrollers. For more details on the whole STMicroelectronics STM32F10xxx family, please refer to Section 2.2: Full compatibility throughout the family. The STM32F105xx and STM32F107xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 2 Description The STM32F105xx and STM32F107xx connectivity line family incorporates the highperformance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 256 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, four general-purpose 16-bit timers plus a PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, five USARTs, an USB OTG FS and two CANs. Ethernet is available on the STM32F107xx only. The STM32F105xx and STM32F107xx connectivity line family operates in the –40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F105xx and STM32F107xx connectivity line family offers devices in two different package types: from 64 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Doc ID 15274 Rev 4 9/95 Description STM32F105xx, STM32F107xx These features make the STM32F105xx and STM32F107xx connectivity line microcontroller family suitable for a wide range of applications: G Motor drive and application control G Medical and handheld equipment G Industrial applications: PLC, inverters, printers, and scanners G Alarm systems, Video intercom, and HVAC G Home audio equipment Figure 1 shows the general block diagram of the device family. 2.1 Device overview Table 2. STM32F105xx and STM32F107xx features and peripheral counts Peripherals(1) STM32F105Rx STM32F107Rx STM32F105Vx STM32F107Vx Flash memory in Kbytes 64 SRAM in Kbytes 20 Ethernet General-purpose Timers Advanced-control Basic SPI(I2S)(2) I2C Communication interfaces USART USB OTG FS CAN GPIOs 12-bit ADC Number of channels 12-bit DAC Number of channels CPU frequency Operating voltage Operating temperatures Package 128 256 128 256 64 128 256 128 256 32 64 48 64 20 32 64 48 64 No Yes No Yes 4 1 2 3(2) 3(2) 3(2) 3(2) 2 1 2 1 5 Yes 2 51 80 2 16 2 2 72 MHz 2.0 to 3.6 V Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C LQFP64 LQFP100 1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required by the application. 2. The SPI2 and SPI3 interfaces give the flexibility to work in either the SPI mode or the I2S audio mode. 10/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Description 2.2 Full compatibility throughout the family The STM32F105xx and STM32F107xx constitute the connectivity line family whose members are fully pin-to-pin, software and feature compatible. The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density (STM32F103x4/6), medium-density (STM32F103x8/B) and high-density (STM32F103xC/D/E) performance line devices, allowing the user to try different memory densities and peripherals providing a greater degree of freedom during the development cycle. Table 3. STM32F105xx and STM32F107xx family versus STM32F103xx family(1) STM32 Low-density Medium-density device STM32F103xx devices STM32F103xx devices High-density STM32F103xx devices STM32F105xx STM32F107xx Flash size (KB) 16 32 32 64 128 256 384 512 64 128 256 128 256 RAM size (KB) 6 10 10 20 20 48 64 64 20 32 64 48 64 144 pins 100 pins 2 × USARTs 64 pins 2 × 16-bit timers 1 × SPI, 1 × I2C, USB, CAN, 1 × PWM timer 2 × ADCs 48 pins 5 × USARTs, 5 × USARTs 4 × 16-bit timers, 3 × USARTs 2 × USARTs 3 × 16-bit 2 × 16-bit timers timers 1 × SPI, 1 × I2C, 2 × SPIs, 2 × I2Cs, USB, CAN, USB, CAN, 1 × PWM timer 4 × 16-bit timers, 2 × basic timers, 2 2 × × basic I2Ss, timers, 3 2 × I2Cs, × SPIs, USB, 3 2 × × SPIs, I2Ss, CAN, 2 × PWM timers 2 × I2Cs, 3 × ADCs, 2 × DACs, USB OTG FS, 1 × SDIO, FSMC (100and 144-pin packages(2)) 2 × CANs, 1 × PWM timer, 1 × PWM 2 × ADCs 2 × ADCs, timer 2 × DACs 2 × ADCs 36 pins 5 × USARTs, 4 × 16-bit timers, 2 × basic timers, 3 × SPIs, 2 × I2S, 1 × I2C, USB OTG FS, 2 × CANs, 1 × PWM timer, 2 × ADCs, 2 × DACs, Ethernet 1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required by the application. 2. Ports F and G are not available in devices delivered in 100-pin packages. Doc ID 15274 Rev 4 11/95 Description STM32F105xx, STM32F107xx 2.3 Overview Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram TRACECLK TRACED[0:3] as AF NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as A F MII_TXD[3:0]/RMII_TXD[1:0] MII_TX_CLK/RMII_TX_CLK MII_TX_EN/RMII_TX_EN MII_RXD[3:0]/RMII_RXD[1:0] MII_RX_ER/RMII_RX_ER MII_RX_CLK/RMII_REF_CLK MII_RX_DV/RMII_CRS_DV MII_CRS MII_COL/RMII_COL MDC MDIO PPS_OUT SOF VBUS ID DM DP 80 AF PA[ 15:0] PB[ 15:0] PC[15:0] PD[15:0] PE[15:0] 4 Channels 4 compl. Channels BKIN, ETR input as AF MOSI,MISO, SCK,NSS as AF RX,TX, CTS, RTS, CK as AF 16 ADC12_INs common to ADC1 & ADC2 VREF– VREF+ TPIU ETM SW/JTAG Trace/Trig Ibus Cortex-M3 CPU Fmax: 72 MHz NVIC Dbus System GP DMA1 7 channels GP DMA2 5 channels Ethernet MAC 10/100 DMA Ethernet DPRAM 2 KB DPRAM 2 KB USB OTG FS Bus Matri x AHB Flashl obl Interface Flash 256 KB 64 bit SRAM 64 KB Reset & clock control @VDDA RC HS RC LS PLL3 PLL2 PLL PCLK1 PCLK2 HCLK FCLK PLL3 SRAM 1.25 KB EXT.IT WKUP GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E APB2 : Fmax = 72 MHz AHB to APB2 AHB to APB1 TIM1 SPI1 USART1 Temp sensor 12bi t ADC1 IF 12bit ADC2 IF @VDDA WWDG TIM6 TIM7 APB1 : Fmax = 36 MHz VDD18 Power Voltage reg. 3.3 V to 1.8 V @VDD POR Reset Int Supply supervision POR / PDR PVD @VDDA @VDD XTAL osc 3-25 MHz IWDG Standby interface @VBAT XTAL 32kHz RTC AWU Bac kup register Backup interface TIM2 TIM3 TIM4 TIM5 USART2 USART3 UART4 UART5 2x(8x16Sb Pit)I2 / I2S2(1) 2x(8x16Sb Pit)I3 / I2S3 I2C1 I2C2(1) bx CAN1 SRAM 512B bx CAN2 IF 12bit DAC1 IF 12bit DAC 2 @VDDA VDD = 2 to 3.6 V VSS NRST VDDA VSSA OSC_IN OSC_OUT VBAT=1.8 V to 3.6 V OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT 4 Channels , ETR as AF 4 Channels , ETR as AF 4 Channels , ETR as AF 4 Channel s, ETR as A F RX,TX, CTS, RTS, CK as AF RX,TX, CTS, RTS, CK as AF RX,TX as AF RX,TX as AF MOSI/SD, MISO, MCK, SCK/CK, NSS/WS as AF MOSI/SD, MISO, MCK, SCK/CK, NSS/WS as AF SCL,SDA, SMBA as AF SCL,SDA,SMBA as AF CAN1_TX as AF CAN1_RX as AF CAN2_TX as AF CAN2_RX as AF DAC_OUT1 as AF DAC_OUT2 as AF ai15411 1. TA = –40 °C to +85 °C (suffix 6, see Table 60) or –40 °C to +105 °C (suffix 7, see Table 60), junction temperature up to 105 °C or 125 °C, respectively. 2. AF = alternate function on I/O port pin. 12/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Description 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, STM32F105xx and STM32F107xx connectivity line family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. Embedded Flash memory 64 to 256 Kbytes of embedded Flash is available for storing programs and data. CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. Embedded SRAM 20 to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Nested vectored interrupt controller (NVIC) The STM32F105xx and STM32F107xx connectivity line embeds a nested vectored interrupt controller able to handle up to 67 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. G Closely coupled NVIC gives low latency interrupt processing G Interrupt entry vector table address passed directly to the core G Closely coupled NVIC core interface G Allows early processing of interrupts G Processing of late arriving higher priority interrupts G Support for tail-chaining G Processor state automatically saved G Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. Doc ID 15274 Rev 4 13/95 Description STM32F105xx, STM32F107xx 2.3.6 2.3.7 2.3.8 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 20 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines. Clocks and startup System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. Refer to Figure 48: USB OTG FS + Ethernet solution on page 89. The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In order to achieve audio class performance, an audio crystal can be used. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy error. Refer to Figure 49: USB OTG FS + I2S (Audio) solution on page 89. To configure the PLLs, please refer to Table 61 on page 90, which provides PLL configurations according to the application type. Boot modes At startup, boot pins are used to select one of three boot options: G Boot from User Flash G Boot from System Memory G Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in device mode (DFU: device firmware upgrade). For remapped signals refer to Table 5: Pin definitions. The USART peripheral operates with the internal 8 MHz oscillator (HSI), however the CAN and USB OTG FS can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present. For full details about the boot loader, please refer to AN2662. 14/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Description 2.3.9 2.3.10 2.3.11 2.3.12 Power supply schemes G VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. G VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. G VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. G MR is used in the nominal regulation mode (Run) G LPR is used in the Stop modes. G Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode. Low-power modes The STM32F105xx and STM32F107xx connectivity line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: G Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. G Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB OTG FS wakeup. Doc ID 15274 Rev 4 15/95 Description STM32F105xx, STM32F107xx Note: 2.3.13 2.3.14 G Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced control timers TIMx, DAC, I2S and ADC. In the STM32F107xx, there is a DMA controller dedicated for use with the Ethernet (see Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support for more information). RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. For more information, please refer to AN2604: “STM32F101xx and STM32F103xx RTC calibration”, available from www.st.com. 16/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Description 2.3.15 Timers and watchdogs The STM32F105xx and STM32F107xx devices include an advanced-control timer, four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the general-purpose and basic timers. Table 4. Timer feature comparison Timer Counter Counter resolution type Prescaler factor DMA request Capture/compare Complementary generation channels outputs Up, Any integer TIM1 16-bit down, between 1 Yes 4 Yes up/down and 65536 TIMx (TIM2, Up, Any integer TIM3, 16-bit down, between 1 Yes 4 No TIM4, up/down and 65536 TIM5) TIM6, TIM7 16-bit Any integer Up between 1 and 65536 Yes 0 No Advanced-control timer (TIM1) The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for: G Input capture G Output compare G PWM generation (edge or center-aligned modes) G One-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F105xx and STM32F107xx connectivity line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control timer via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. Doc ID 15274 Rev 4 17/95 Description STM32F105xx, STM32F107xx 2.3.16 2.3.17 Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: G A 24-bit down counter G Autoreload capability G Maskable system interrupt generation when the counter reaches 0. G Programmable clock source I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F105xx and STM32F107xx connectivity line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. 18/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Description 2.3.18 2.3.19 2.3.20 USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC/SDHC(a) modes. All SPIs can be served by the DMA controller. Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 96 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency with less than 0.5% accuracy error owing to the advanced clock controller (see Section 2.3.7: Clocks and startup). Please refer to the “Audio frequency precision” tables provided in the “Serial peripheral interface (SPI)” section of the STM32F10xxx reference manual. Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral not available on STM32F105xx devices. The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard media-independent interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F107xx. The STM32F107xx includes the following features: G Supports 10 and 100 Mbit/s rates G Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F105xx/STM32F107xx reference manual for details) G Tagged MAC frame support (VLAN support) G Half-duplex (CSMA/CD) and full-duplex operation G MAC control sublayer (control frames) support a. SDHC = Secure digital high capacity. Doc ID 15274 Rev 4 19/95 Description STM32F105xx, STM32F107xx 2.3.21 2.3.22 2.3.23 G 32-bit CRC generation and removal G Several address filtering modes for physical and multicast address (multicast and group addresses) G 32-bit status code for each transmitted or received frame G Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes, that is 4 Kbytes in total G Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 with the timestamp comparator connected to the TIM2 trigger input G Triggers interrupt when system time becomes greater than target time Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total) are not shared with any other peripheral. Universal serial bus on-the-go full-speed (USB OTG FS) The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG fullspeed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: G 1.25 KB of SRAM used exclusively by the endpoints (not shared with any other peripheral) G 4 bidirectional endpoints G HNP/SNP/IP inside (no need for any external resistor) G for OTG/Host modes, a power switch is needed in case bus-powered devices are connected G the SOF output can be used to synchronize the external audio DAC clock in isochronous mode G in accordance with the USB 2.0 Specification, the supported transfer speeds are: – in Host mode: full speed and low speed – in Device mode: full speed GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed 20/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Description 2.3.24 2.3.25 2.3.26 Remap capability This feature allows the use of a maximum number of peripherals in a given application. Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. This has the advantage of making board design and port usage much more flexible. For details refer to Table 5: Pin definitions; it shows the list of remappable alternate functions and the pins onto which they can be remapped. See the STM32F10xxx reference manual for software considerations. ADCs (analog-to-digital converters) Two 12-bit analog-to-digital converters are embedded into STM32F105xx and STM32F107xx connectivity line devices and each ADC shares up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: G Simultaneous sample and hold G Interleaved sample and hold G Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the standard timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: G two DAC converters: one for each output channel G 8-bit or 12-bit monotonic output G left or right data alignment in 12-bit mode G synchronized update capability G noise-wave generation G triangular-wave generation G dual DAC channel independent or simultaneous conversions G DMA capability for each channel G external triggers for conversion G input voltage reference VREF+ Doc ID 15274 Rev 4 21/95 Description STM32F105xx, STM32F107xx 2.3.27 2.3.28 2.3.29 Eight DAC trigger inputs are used in the STM32F105xx and STM32F107xx connectivity line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Embedded Trace Macrocell™ The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 22/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx 3 Pinouts and pin description Pinouts and pin description Figure 2. STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout 100 VDD_3 99 VSS_3 98 PE1 97 PE0 96 PB9 95 PB8 94 BOOT0 93 PB7 92 PB6 91 PB5 90 PB4 89 PB3 88 PD7 87 PD6 86 PD5 85 PD4 84 PD3 83 PD2 82 PD1 81 PD0 80 PC12 79 PC11 78 PC10 77 PA15 76 PA14 PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-TAMPER-RTC 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 VSS_5 10 VDD_5 11 OSC_IN 12 OSC_OUT 13 NRST 14 PC0 15 PC1 16 PC2 17 PC3 18 VSSA 19 VREF- 20 VREF+ 21 VDDA 22 PA0-WKUP 23 PA1 24 PA2 25 LQFP100 75 VDD_2 74 VSS_2 73 NC 72 PA 13 71 PA 12 70 PA 11 69 PA 10 68 PA 9 67 PA 8 66 PC9 65 PC8 64 PC7 63 PC6 62 PD15 61 PD14 60 PD13 59 PD12 58 PD11 57 PD10 56 PD9 55 PD8 54 PB15 53 PB14 52 PB13 51 PB12 PA3 26 VSS_4 27 VDD_4 28 PA4 29 PA5 30 PA6 31 PA7 32 PC4 33 PC5 34 PB0 35 PB1 36 PB2 37 PE7 38 PE8 39 PE9 40 PE10 41 PE11 42 PE12 43 PE13 44 PE14 45 PE15 46 PB10 47 PB11 48 VSS_1 49 VDD_1 50 ai14391 Doc ID 15274 Rev 4 23/95 Pinouts and pin description STM32F105xx, STM32F107xx Figure 3. STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 LQFP64 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14392 24/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Pinouts and pin description LQFP100 LQFP64 Type(1) I / O level(2) Table 5. Pins Pin definitions Pin name Main function(3) (after reset) Alternate functions(4) Default Remap 1- PE2 I/O FT 2- PE3 I/O FT 3- PE4 I/O FT 4- PE5 I/O FT 5- PE6 I/O FT 61 VBAT S 72 PC13-TAMPERRTC(5) I/O 8 3 PC14-OSC32_IN(5) I/O 94 PC15OSC32_OUT(5) I/O 10 - VSS_5 S 11 - VDD_5 S 12 5 OSC_IN I 13 6 OSC_OUT O 14 7 NRST I/O 15 8 PC0 I/O 16 9 PC1 I/O 17 10 PC2 I/O 18 11 PC3 I/O 19 12 VSSA S 20 - VREF- S 21 - VREF+ S 22 13 VDDA S 23 14 PA0-WKUP I/O 24 15 PA1 I/O 25 16 PA2 I/O PE2 PE3 PE4 PE5 PE6 VBAT PC13(6) PC14(6) PC15(6) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0 PA1 PA2 TRACECK TRACED0 TRACED1 TRACED2 TRACED3 TAMPER-RTC OSC32_IN OSC32_OUT ADC12_IN10 ADC12_IN11/ ETH_MDC ADC12_IN12/ ETH_MII_TXD2 ADC12_IN13/ ETH_MII_TX_CLK WKUP/USART2_CTS(7) ADC12_IN0/TIM2_CH1_ETR TIM5_CH1/ ETH_MII_CRS_WKUP USART2_RTS(7)/ ADC12_IN1/ TIM5_CH2 /TIM2_CH2(7)/ ETH_MII_RX_CLK/ ETH_RMII_REF_CLK USART2_TX(7)/ TIM5_CH3/ADC12_IN2/ TIM2_CH3 (7)/ ETH_MDIO Doc ID 15274 Rev 4 25/95 Pinouts and pin description STM32F105xx, STM32F107xx LQFP100 LQFP64 Type(1) I / O level(2) Table 5. Pins Pin definitions (continued) Pin name Main function(3) (after reset) Alternate functions(4) Default Remap 26 17 27 18 28 19 29 20 30 21 31 22 32 23 33 24 34 25 35 26 36 27 37 28 38 39 40 41 42 43 44 45 46 47 29 48 30 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 USART2_RX(7)/ I/O PA3 TIM5_CH4/ADC12_IN3 / TIM2_CH4(7)/ ETH_MII_COL S VSS_4 S VDD_4 I/O PA4 SPI1_NSS(7)/DAC_OUT1 / USART2_CK(7) / ADC12_IN4 I/O PA5 SPI1_SCK(7) / DAC_OUT2 / ADC12_IN5 I/O PA6 SPI1_MISO(7)/ADC12_IN6 / TIM3_CH1(7) SPI1_MOSI(7)/ADC12_IN7 / I/O PA7 TIM3_CH2(7)/ ETH_MII_RX_DV/ ETH_RMII_CRS_DV I/O PC4 ADC12_IN14 / ETH_MII_RXD0 / ETH_RMII_RXD0 I/O PC5 ADC12_IN15 / ETH_MII_RXD1 / ETH_RMII_RXD1 I/O PB0 ADC12_IN8/TIM3_CH3/ ETH_MII_RXD2 I/O PB1 ADC12_IN9 / TIM3_CH4(7)/ ETH_MII_RXD3 I/O FT PB2/BOOT1 I/O FT PE7 I/O FT PE8 I/O FT PE9 I/O FT PE10 I/O FT PE11 I/O FT PE12 I/O FT PE13 I/O FT PE14 I/O FT I/O FT PE15 PB10 I/O FT PB11 I2C2_SCL/USART3_TX(7)/ ETH_MII_RX_ER I2C2_SDA/USART3_RX(7)/ ETH_MII_TX_EN/ ETH_RMII_TX_EN SPI3_NSS TIM1_BKIN TIM1_CH1N TIM1_CH2N TIM1_CH3N TIM1_ETR TIM1_CH1N TIM1_CH1 TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM2_CH3 TIM2_CH4 26/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Pinouts and pin description LQFP100 LQFP64 Type(1) I / O level(2) Table 5. Pins Pin definitions (continued) Pin name Main function(3) (after reset) Alternate functions(4) Default Remap 49 31 50 32 51 33 52 34 53 35 54 36 55 56 57 58 - 59 60 61 62 63 37 64 38 65 39 66 40 67 41 68 42 69 43 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 S VSS_1 S VDD_1 I/O FT PB12 I/O FT PB13 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PB14 PB15 PD8 PD9 PD10 PD11 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 SPI2_NSS/I2S2_WS/ I2C2_SMBA / USART3_CK(7)/ TIM1_BKIN(7) / CAN2_RX/ ETH_MII_TXD0/ ETH_RMII_TXD0 SPI2_SCK / I2S2_CK / USART3_CTS(7)/ TIM1_CH1N / CAN2_TX / ETH_MII_TXD1/ ETH_RMII_TXD1 SPI2_MISO / TIM1_CH2N / USART3_RTS(7) SPI2_MOSI / I2S2_SD / TIM1_CH3N(7) I2S2_MCK/ I2S3_MCK USART1_CK/OTG_FS_SOF / TIM1_CH1(7)/MCO USART1_TX(7)/ TIM1_CH2(7)/ OTG_FS_VBUS USART1_RX(7)/ TIM1_CH3(7)/OTG_FS_ID USART3_TX/ ETH_MII_RX_DV USART3_RX/ ETH_MII_RX_D0 USART3_CK/ ETH_MII_RX_D1 USART3_CTS/ ETH_MII_RX_D2 TIM4_CH1 / USART3_RTS/ ETH_MII_RX_D3 TIM4_CH2 TIM4_CH3 TIM4_CH4 TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 Doc ID 15274 Rev 4 27/95 Pinouts and pin description STM32F105xx, STM32F107xx LQFP100 LQFP64 Type(1) I / O level(2) Table 5. Pins Pin definitions (continued) Pin name Main function(3) (after reset) Alternate functions(4) Default Remap 70 44 71 45 72 46 73 74 47 75 48 76 49 77 50 78 51 79 52 80 53 81 5 82 6 83 54 84 85 86 87 88 89 55 90 56 91 57 92 58 93 59 94 60 95 61 96 62 PA11 PA12 PA13 VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 I/O FT PA11 USART1_CTS / CAN1_RX / TIM1_CH4(7)/OTG_FS_DM I/O FT PA12 USART1_RTS / OTG_FS_DP / CAN1_TX(7) / TIM1_ETR(7) I/O FT JTMS-SWDIO PA13 Not connected S VSS_2 S VDD_2 I/O FT JTCK-SWCLK PA14 I/O FT JTDI SPI3_NSS / I2S3_WS TIM2_CH1_ETR / PA15 SPI1_NSS I/O FT PC10 UART4_TX USART3_TX/ SPI3_SCK I/O FT PC11 UART4_RX USART3_RX/ SPI3_MISO I/O FT PC12 I/O FT OSC_IN(8) I/O FT OSC_OUT(8) UART5_TX USART3_CK/ SPI3_MOSI CAN1_RX CAN1_TX I/O FT PD2 TIM3_ETR / UART5_RX I/O FT PD3 USART2_CTS I/O FT PD4 USART2_RTS I/O FT PD5 USART2_TX I/O FT PD6 USART2_RX I/O FT PD7 USART2_CK I/O FT JTDO SPI3_SCK / I2S3_CK PB3 / TRACESWO/ TIM2_CH2 / SPI1_SCK I/O FT NJTRST SPI3_MISO PB4 / TIM3_CH1/ SPI1_MISO I/O PB5 I/O FT PB6 I/O FT PB7 I2C1_SMBA / SPI3_MOSI / ETH_PPS_OUT / I2S3_SD I2C1_SCL(7)/TIM4_CH1(7) I2C1_SDA(7)/TIM4_CH2(7) TIM3_CH2/SPI1_MOSI/ CAN2_RX USART1_TX/CAN2_TX USART1_RX I I/O FT I/O FT BOOT0 PB8 PB9 TIM4_CH3(7)/ ETH_MII_TXD3 TIM4_CH4(7) I2C1_SCL/CAN1_RX I2C1_SDA / CAN1_TX 28/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Pinouts and pin description LQFP100 LQFP64 Type(1) I / O level(2) Table 5. Pins Pin definitions (continued) Pin name Main function(3) (after reset) Alternate functions(4) Default Remap 97 - PE0 I/O FT PE0 TIM4_ETR 98 - PE1 I/O FT PE1 99 63 VSS_3 S 100 64 VDD_3 S VSS_3 VDD_3 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. All I/Os are VDD capable. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. Doc ID 15274 Rev 4 29/95 Memory mapping STM32F105xx, STM32F107xx 4 Memory mapping The memory map is shown in Figure 4. Figure 4. Memory map 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 0xC000 0000 0xBFFF FFFF 0xB000 0000 0xAFFF FFFF 512-Mbyte block 7 Cortex-M3's internal peripherals 512-Mbyte block 6 Not used 512-Mbyte block 5 Not used 512-Mbyte block 4 Not used 0x8000 0000 0x7FFF FFFF 512-Mbyte block 3 Not used 0x6000 0000 0x5FFF FFFF 0x4000 0000 0x3FFF FFFF 0x2000 0000 0x1FFF FFFF 0x0000 0000 512-Mbyte block 2 Peripherals 512-Mbyte block 1 SRAM 512-Mbyte block 0 Code AHB APB2 APB1 Reserved USB OTG FS Reserved Ethernet Reserved CRC Reserved Flash interface Reserved RCC Reserved DMA2 DMA1 Reserved USART1 Reserved SPI1 TIM1 ADC2 ADC1 Reserved Port E Port D Port C Port B Port A EXTI AFIO Reserved DAC PWR BKP bxCAN2 bxCAN1 Reserved I2C2 I2C1 UART5 UART4 USART3 USART2 Reserved SPI3/I2S3 SPI2/I2S2 Reserved IWDG WWDG RTC Reserved TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 Reserved SRAM (aliased by bit-banding) Option bytes System memory Reserved Flash Reserved Aliased to Flash or system memory depending on BOOT pins 0x3FFF FFFF 0x2001 0000 0x2000 FFFF 0x2000 0000 0x1FFF F800 - 0x1FFF FFFF 0x1FFF B000 - 0x1FFF F7FF 0x1FFF AFFF 0x0804 0000 0x0803 FFFF 0x0800 0000 0x07FF FFFF 0x0004 0000 0x0003 FFFF 0x0000 0000 0x5000 0400 - 0x5FFF FFFF 0x5000 0000 - 0x5000 03FF 0x4003 0000 - 0x4FFF FFFF 0x4002 8000 - 0x4002 9FFF 0x4002 3400 - 0x4002 7FFF 0x4002 3000 - 0x4002 33FF 0x4002 2400 - 0x4002 2FFF 0x4002 2000 - 0x4002 23FF 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF 0x4002 0800 - 0x4002 0FFF 0x4002 0400 - 0x4002 07FF 0x4002 0000 - 0x4002 03FF 0x4001 3C00 - 0x4001 FFFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF 0x4001 2800 - 0x4001 2BFF 0x4001 2400 - 0x4001 27FF 0x4001 1C00 - 0x4001 23FF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 3FFF 0x4000 7800 - 0x4000 FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - 0x4000 67FF 0x4000 5C00 - 0x4000 63FF 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF 0x4000 5000 - 0x4000 53FF 0x4000 4C00 - 0x4000 4FFF 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF 0x4000 4000 - 0x4000 43FF 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF 0x4000 3400 - 0x4000 37FF 0x4000 3000 - 0x4000 33FF 0x4000 2C00 - 0x4000 2FFF 0x4000 2800 - 0x4000 2BFF 0x4000 1800 - 0x4000 27FF 0x4000 1400 - 0x4000 17FF 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF 0x4000 0000 - 0x4000 03FF ai15412b 30/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx 5 Electrical characteristics Electrical characteristics 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±36). Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V d VDD d 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±26). Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 5. Pin input voltage The input voltage measurement on a pin of the device is described in Figure 6. Figure 5. Pin loading conditions Figure 6. Pin input voltage C = 50 pF STM32F10xxx pin ai15664 STM32F10xxx pin VIN ai15665 Doc ID 15274 Rev 4 31/95 Electrical characteristics 5.1.6 Power supply scheme Figure 7. Power supply scheme 1.8-3.6V VBAT STM32F105xx, STM32F107xx Po wer swi tch Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) Level shifter GP I/Os VDD VDD 1/2/3/4/5 5 × 100 nF + 1 × 4.7 µF VSS 1/2/3/4/5 VDD 10 nF + 1 µF VREF 10 nF + 1 µF VDDA VREF+ VREF- VSSA O UT IO Logic IN Regulator Kernel logic (CPU, Digital & Memories) ADC Analog: RCs, PLL, ... ai14125d Caution: In Figure 7, the 4.7 µF capacitor must be connected to VDD3. 5.1.7 Current consumption measurement Figure 8. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 32/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS External main and VDD)(1) supply voltage (including VDDA –0.3 4.0 Input voltage on five volt tolerant pin(2) VIN Input voltage on any other pin(2) VSS  0.3 +5.5 V VSS 0.3 VDD+0.3 |'VDDx| Variations between different VDD power pins |VSSX VSS| Variations between all the different ground pins 50 mV 50 VESD(HBM) Electrostatic discharge voltage (human body model) see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is induced by VIN < VSS. Table 7. Current characteristics Symbol Ratings Max. Unit IVDD Total current into VDD/VDDA power lines (source)(1) 150 IVSS Total current out of VSS ground lines (sink)(1) 150 Output current sunk by any I/O and control pin IIO Output current source by any I/Os and control pin Injected current on NRST pin 25  25 mA ±5 IINJ(PIN) (2)(3) Injected current on HSE OSC_IN and LSE OSC_IN pins ±5 Injected current on any other pin(4) ±5 6IINJ(PIN)(2) Total injected current (sum of all I/O and control pins)(4) ± 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum 6IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with 6IINJ(PIN) maximum current injection on four I/O port pins of the device. Doc ID 15274 Rev 4 33/95 Electrical characteristics Table 8. Thermal characteristics Symbol Ratings TSTG TJ Storage temperature range Maximum junction temperature STM32F105xx, STM32F107xx Value Unit –65 to +150 °C 150 °C 5.3 5.3.1 Operating conditions General operating conditions Table 9. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency 0 fPCLK1 Internal APB1 clock frequency 0 fPCLK2 Internal APB2 clock frequency 0 VDD Standard operating voltage 2 VDDA(1) Analog operating voltage (ADC not used) Analog operating voltage (ADC used) 2 Must be the same potential as VDD(2) 2.4 72 36 MHz 72 3.6 V 3.6 V 3.6 VBAT PD Backup operating voltage Power dissipation at TA = 85 °C LQFP100 for suffix 6 suffix 7(3) or TA = 105 °C for LQFP64 1.8 3.6 V 434 mW 444 Ambient temperature for 6 suffix version Maximum power dissipation –40 85 Low power dissipation(4) °C –40 105 TA Ambient temperature for 7 suffix version Maximum power dissipation –40 105 Low power dissipation(4) °C –40 125 6 suffix version TJ Junction temperature range 7 suffix version –40 105 °C –40 125 1. When the ADC is used, refer to Table 51: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. 34/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics 5.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 10. Operating conditions at power-up / power-down Symbol Parameter Conditions Min VDD rise time rate 0 tVDD VDD fall time rate 20 Max Unit f µs/V f 5.3.3 Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 11. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V VPVD Programmable voltage PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V detector level selection PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V VPVDhyst(2) PVD hysteresis 100 mV VPOR/PDR Power on/power down reset threshold Falling edge Rising edge 1.8(1) 1.88 1.96 V 1.84 1.92 2.0 V VPDRhyst(2) PDR hysteresis TRSTTEMPO(2) Reset temporization 40 mV 1 2.5 4.5 ms 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. Doc ID 15274 Rev 4 35/95 Electrical characteristics STM32F105xx, STM32F107xx 5.3.4 5.3.5 Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.16 1.20 1.26 V –40 °C < TA < +85 °C 1.16 1.20 1.24 V ADC sampling time when TS_vrefint(1) reading the internal reference voltage 5.1 17.1(2) µs Internal reference voltage VRERINT(2) spread over the temperature range VDD = 3 V ±10 mV TCoeff(2) Temperature coefficient 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 10 mV 100 ppm/°C Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 8: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: G All I/O pins are in input mode with a static value at VDD or VSS (no load) G All peripherals are disabled except when explicitly mentioned G The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) G Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) G When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 36/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Table 13. Symbol Maximum current consumption in Run mode, code with data processing running from Flash Parameter Conditions fHCLK Max(1) TA = 85 °C TA = 105 °C Unit 72 MHz 68 68.4 48 MHz 49 49.2 External clock(2), all 36 MHz 38.7 38.9 peripherals enabled 24 MHz 27.3 27.9 16 MHz 20.2 20.5 IDD Supply current in Run mode 8 MHz 10.2 72 MHz 32.7 10.8 mA 32.9 48 MHz 25 25.2 External clock(3), all 36 MHz 20.3 20.6 peripherals disabled 24 MHz 14.8 15.1 16 MHz 11.2 11.7 8 MHz 6.6 7.2 1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Symbol Parameter Conditions fHCLK Max(1) TA = 85 °C TA = 105 °C Unit 72 MHz 65.5 66 48 MHz External clock(2), all 36 MHz peripherals enabled 24 MHz 45.4 46 35.5 36.1 25.2 25.6 Supply IDD current in Run mode 16 MHz 8 MHz 72 MHz 48 MHz 18 18.5 10.5 11 mA 31.4 31.9 27.8 28.2 External clock(3), all 36 MHz peripherals disabled 24 MHz 16 MHz 17.6 18.3 13.1 13.8 10.2 10.9 8 MHz 6.1 7.8 1. Based on characterization, tested in production at VDD max, fHCLK max.. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 15274 Rev 4 37/95 Electrical characteristics STM32F105xx, STM32F107xx Table 15. Symbol Maximum current consumption in Sleep mode, code running from Flash or RAM Parameter Conditions fHCLK Max(1) TA = 85 °C TA = 105 °C Unit 72 MHz 48.4 49 48 MHz 33.9 34.4 External clock(2), all 36 MHz 26.7 27.2 peripherals enabled 24 MHz 19.3 19.8 16 MHz 14.2 14.8 IDD Supply current in Sleep mode 8 MHz 8.7 72 MHz 10.1 9.1 mA 10.6 48 MHz 8.3 8.75 External clock(3), all 36 MHz 7.5 8 peripherals disabled 24 MHz 6.6 7.1 16 MHz 6 6.5 8 MHz 2.5 3 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 16. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Max Symbol Parameter Conditions VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit = 2.0 V = 2.4 V = 3.3 V 85 °C 105 °C Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode Regulator in Low Power mode, low- speed and high-speed internal RC oscillators and high-speed oscillator IDD OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON 32 33 600 1300 25 26 590 1280 3 3.8 - - µA Supply current Low-speed internal RC oscillator in Standby ON, independent watchdog OFF mode Low-speed internal RC oscillator and independent watchdog OFF, low- speed oscillator and RTC OFF 2.8 3.6 - - 1.9 2.1 5(2) 6.5(2) Backup IDD_VBAT domain supply Low-speed oscillator and RTC ON 1.1 1.2 1.4 2.1(2) 2.3(2) current 1. Typical values are measured at TA = 25 °C. 2. Based on characterization, not tested in production. 38/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Figure 9. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values Consumption (µA) 2.5 2 1.8 V 2V 1.5 2.4 V 1 3.3 V 3.6 V 0.5 0 –40 °C 25 °C 70 °C 85 °C 105 °C Temperature (°C) ai17329 Figure 10. Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values Consumption (µA) 900.00 800.00 700.00 600.00 500.00 400.00 300.00 200.00 100.00 0.00 –40 °C 25 °C 85 °C Temperature (°C) 3.6 V 3.3 V 3V 2.7 V 2.4 V 105 °C ai17122 Doc ID 15274 Rev 4 39/95 Electrical characteristics STM32F105xx, STM32F107xx Figure 11. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at different VDD values Consumption (µA) 900.00 800.00 700.00 600.00 500.00 400.00 300.00 200.00 100.00 0.00 –40 °C 25 °C 85 °C Temperature (°C) 3.6 V 3.3 V 3V 2.7 V 2.4 V 105 °C ai17123 Figure 12. Typical current consumption in Standby mode versus temperature at different VDD values Consumption (µA) 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 –40 °C 25 °C 85 °C Temperature (°C) 3.6 V 3.3 V 3V 2.7 V 2.4 V 105 °C ai17124 Typical current consumption The MCU is placed under the following conditions: G All I/O pins are in input mode with a static value at VDD or VSS (no load). G All peripherals are disabled except if it is explicitly mentioned. G The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). G Ambient temperature and VDD supply voltage conditions summarized in Table 9. G Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 40/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Table 17. Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions fHCLK All peripherals All peripherals Unit enabled(2) disabled 72 MHz 47.3 28.3 48 MHz 32 19.6 36 MHz 24.6 15.4 24 MHz 16.8 External clock(3) 16 MHz 8 MHz 11.8 5.9 4 MHz 3.7 2 MHz 2.5 Supply IDD current in Run mode 1 MHz 1.8 500 kHz 1.5 125 kHz 1.3 36 MHz 23.9 24 MHz 16.1 Running on high 16 MHz 11.1 speed internal RC 8 MHz 5.6 (HSI), AHB prescaler used to 4 MHz 3.1 reduce the 2 MHz 1.8 frequency 1 MHz 1.16 500 kHz 0.8 125 kHz 0.6 10.6 7.4 3.7 mA 2.9 2 1.53 1.3 1.2 14.8 9.7 6.7 3.8 2.1 mA 1.3 0.9 0.67 0.5 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 15274 Rev 4 41/95 Electrical characteristics STM32F105xx, STM32F107xx Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions fHCLK All peripherals All peripherals enabled(2) disabled Unit 72 MHz 28.2 48 MHz 19 36 MHz 14.7 24 MHz 10.1 16 MHz 6.7 External clock(3) 8 MHz 3.2 4 MHz 2.3 2 MHz 1.7 Supply IDD current in Sleep mode 1 MHz 1.5 500 kHz 1.3 125 kHz 1.2 36 MHz 13.7 24 MHz 9.3 16 MHz 6.3 Running on high speed internal RC 8 MHz 2.7 (HSI), AHB prescaler 4 MHz 1.6 used to reduce the frequency 2 MHz 1 1 MHz 0.8 500 kHz 0.6 125 kHz 0.5 6 4.2 3.4 2.5 2 1.3 1.2 1.16 1.1 1.05 mA 1.05 2.6 1.8 1.3 0.6 0.5 0.46 0.44 0.43 0.42 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed under the following conditions: G all I/O pins are in input mode with a static value at VDD or VSS (no load) G all peripherals are disabled unless otherwise mentioned G the given value is calculated by measuring the current consumption – with all peripherals clocked off – with one peripheral clocked on (with only the clock applied) G ambient operating temperature and VDD supply voltage conditions summarized in Table 6 42/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Table 19. Peripheral current consumption(1) Peripheral Typical consumption at 25 °C Unit ETH_MAC 5.2 AHB OTG_FS 7.7 TIM2 1.5 TIM3 1.5 TIM4 1.5 TIM5 1.5 TIM6 0.6 TIM7 0.3 APB1 SPI2 USART2 USART3 0.2 mA 0.5 0.5 UART4 0.5 UART5 0.5 I2C1 0.5 I2C2 0.5 CAN1 0.8 CAN2 0.8 DAC 0.4 GPIO A 0.5 GPIO B 0.5 GPIO C 0.5 GPIO D 0.5 APB2 GPIO E ADC1(2) ADC2(2) 0.5 mA 2.1 2.0 TIM1 1.7 SPI1 0.4 USART1 0.9 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1. Doc ID 15274 Rev 4 43/95 Electrical characteristics STM32F105xx, STM32F107xx 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fHSE_ext External user clock source frequency(1) 1 8 50 MHz VHSEH VHSEL OSC_IN input pin high level voltage OSC_IN input pin low level voltage 0.7VDD VSS VDD V 0.3VDD tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE) OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN input capacitance(1) 16 ns 20 5 pF DuCy(HSE) Duty cycle 45 55 % IL OSC_IN Input leakage current VSS d VIN d VDD ±1 µA 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 21. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fLSE_ext User External clock source frequency(1) 32.768 1000 kHz VLSEH VLSEL OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage 0.7VDD VSS VDD V 0.3VDD tw(LSE) tw(LSE) tr(LSE) tf(LSE) Cin(LSE) OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) OSC32_IN input capacitance(1) 450 ns 50 5 pF DuCy(LSE) Duty cycle 30 70 % IL OSC32_IN Input leakage current VSS d VIN d VDD ±1 µA 1. Guaranteed by design, not tested in production. 44/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Figure 13. High-speed external clock source AC timing diagram VHSEH 90% 10% VHSEL tr(HSE) tf(HSE) THSE External clock source fHSE_ext OSC _IN tW(HSE) IL STM32F10xxx Figure 14. Low-speed external clock source AC timing diagram tW(HSE) t ai14127b VLSEH VLSEL 90% 10% tr(LSE) tf(LSE) TLSE tW(LSE) tW(LSE) t External clock source fLSE_ext OSC32_IN IL STM32F10xxx ai14140c High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 3 to 25 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Doc ID 15274 Rev 4 45/95 Electrical characteristics STM32F105xx, STM32F107xx Table 22. HSE 3-25 MHz oscillator characteristics(1) (2) Symbol Parameter Conditions Min Typ Max Unit fOSC_IN Oscillator frequency 3 RF Feedback resistor Recommended load capacitance C versus equivalent serial resistance of the crystal (RS)(3) RS = 30: i2 HSE driving current VDD = 3.3 V, VIN = VSS with 30 pF load 25 MHz 200 k: 30 pF 1 mA gm Oscillator transconductance tSU(HSE(4) Startup time Startup 25 VDD is stabilized 2 mA/V ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 15). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 15. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 CL2 8 MH z resonator REXT(1) OSC_IN RF OSC_OU T Bias controlled gain fHS E STM32F10xxx ai14128b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal 46/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor 5 M: Recommended load capacitance C(2) versus equivalent serial resistance of the crystal (RS)(3) RS = 30 k: 15 pF I2 LSE driving current VDD = 3.3 V, VIN = VSS 1.4 µA gm Oscillator Transconductance tSU(LSE)(4) startup time 5 VDD is stabilized 3 µA/V s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: Caution: For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL d 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 16. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN 32.768 KH z resonator RF OSC32_OU T CL2 Bias controlled gain fLSE STM32F10xxx ai14129b Doc ID 15274 Rev 4 47/95 Electrical characteristics STM32F105xx, STM32F107xx 5.3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. High-speed internal (HSI) RC oscillator Table 24. HSI oscillator characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency User-trimmed with the RCC_CR register(2) 8 MHz 1(3) % ACCHSI Accuracy of the HSI oscillator Factorycalibrated(4) tsu(HSI)(4) HSI oscillator startup time TA = –40 to 105 °C TA = –10 to 85 °C TA = 0 to 70 °C TA = 25 °C –2 –1.5 –1.3 –1.1 1 2.5 % 2.2 % 2 % 1.8 % 2 µs IDD(HSI)(4) HSI oscillator power consumption 80 100 µA 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. Low-speed internal (LSI) RC oscillator Table 25. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI)(3) IDD(LSI)(3) Frequency LSI oscillator startup time LSI oscillator power consumption 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Min Typ Max Unit 30 40 60 kHz 85 µs 0.65 1.2 µA Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: G Stop or Standby mode: the clock source is the RC oscillator G Sleep mode: the clock source is the clock that was set before entering Sleep mode. 48/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics 5.3.8 All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 26. Low-power mode wakeup timings Symbol Parameter Typ Unit tWUSLEEP(1) Wakeup from Sleep mode 1.8 µs Wakeup from Stop mode (regulator in run mode) 3.6 tWUSTOP(1) Wakeup from Stop mode (regulator in low power mode) 5.4 µs tWUSTDBY(1) Wakeup from Standby mode 50 µs 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. PLL, PLL2 and PLL3 characteristics The parameters given in Table 27 and Table 28 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 9. Table 27. PLL characteristics Symbol Parameter Min(1) Max(1) Unit fPLL_IN PLL input clock(2) Pulse width at high level 3 12 MHz 30 ns fPLL_OUT fVCO_OUT tLOCK Jitter PLL multiplier output clock PLL VCO output PLL lock time Cycle-to-cycle jitter 18 72 MHz 36 144 MHz 350 µs 300 ps 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. Table 28. PLL2 and PLL3 characteristics Symbol Parameter Min(1) Max(1) Unit fPLL_IN PLL input clock(2) Pulse width at high level 3 5 MHz 30 ns fPLL_OUT fVCO_OUT tLOCK Jitter PLL multiplier output clock PLL VCO output PLL lock time Cycle-to-cycle jitter 40 74 MHz 80 148 MHz 350 µs 400 ps 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. Doc ID 15274 Rev 4 49/95 Electrical characteristics STM32F105xx, STM32F107xx 5.3.9 5.3.10 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 29. Flash memory characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit tprog 16-bit programming time TA –40 to +105 °C 40 52.5 70 µs tERASE Page (1 KB) erase time TA –40 to +105 °C 20 40 ms tME Mass erase time TA –40 to +105 °C 20 40 ms Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V 20 mA IDD Supply current Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 µA Vprog Programming voltage 2 3.6 V 1. Guaranteed by design, not tested in production. Table 30. Flash memory endurance and data retention Symbol Parameter Conditions Value Min(1) Typ Max Unit NEND Endurance TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 tRET Data retention 1 kcycle(2) at TA = 105 °C 10 10 kcycles(2) at TA = 55 °C 20 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. kcycles Years EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. 50/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: G Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. G FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 31. They are based on the EMS levels and classes defined in application note AN1709. Table 31. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD 3.3 V, LQFP100, TA = +25 °C, fHCLK = 75 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD 3.3 V, LQFP100, TA = +25 °C, fHCLK = 75 MHz, conforms to 4A IEC 61000-4-2 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: G Corrupted program counter G Unexpected reset G Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Doc ID 15274 Rev 4 51/95 Electrical characteristics STM32F105xx, STM32F107xx Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 32. EMI characteristics Symbol Parameter Conditions SEMI Peak level VDD 3.3 V, TA 25 °C, LQFP100 package compliant with IEC61967-2 Monitored frequency band 0.1 to 30 MHz 30 to 130 MHz 130 MHz to 1GHz SAE EMI Level Max vs. [fHSE/fHCLK] 8/48 MHz 8/72 MHz 9 9 26 13 25 31 4 4 Unit dBµV - 5.3.11 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 33. ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) VESD(CDM) Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) TA +25 °C conforming to JESD22-A114 TA +25 °C conforming to JESD22-C101 1. Based on characterization results, not tested in production. Class Maximum value(1) Unit 2 2000 V II 500 Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: G A supply overvoltage is applied to each power supply pin G A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 34. Electrical sensitivities Symbol Parameter Conditions LU Static latch-up class TA +105 °C conforming to JESD78A Class II level A 52/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics 5.3.12 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 35. I/O static characteristics Symbol Parameter Conditions Min Typ Max VIL Input low level voltage Standard IO input high level voltage VIH IO FT(1) input high level voltage TTL ports –0.5 2 2 0.8 VDD+0.5 5.5V VIL Input low level voltage CMOS ports –0.5 VIH Input high level voltage 0.65 VDD Standard IO Schmitt trigger voltage Vhys hysteresis(2) IO FT Schmitt trigger voltage hysteresis(2) 200 5% VDD(3) Ilkg Input leakage current (4) VSS d VIN d VDD Standard I/Os VIN= 5 V, I/O FT All pins except for RPU Weak pull-up equivalent PA10 resistor(5) PA10 VIN VSS 30 40 8 11 0.35 VDD VDD+0.5 r1 3 50 15 RPD Weak pull-down equivalent resistor(5) All pins except for PA10 PA10 VIN VDD 30 40 50 8 11 15 CIO I/O pin capacitance 5 1. FT = Five-volt tolerant. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). Unit V V mV mV µA k: k: pF All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters: G For VIH: – if VDD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included – if VDD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included G For VIL: – if VDD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included – if VDD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included Doc ID 15274 Rev 4 53/95 Electrical characteristics STM32F105xx, STM32F107xx Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: G The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7). G The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). Output voltage levels Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 36. Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at same time TTL port 0.4 VOH(2) Output high level voltage for an I/O pin when 8 pins are sourced at same time IIO = +8 mA 2.7 V < VDD < 3.6 V VDD–0.4 V VOL (1) Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS port IIO =+ 8mA VOH (2) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.7 V < VDD < 3.6 V 2.4 0.4 V VOL(1)(3) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +20 mA 1.3 V VOH(2)(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.7 V < VDD < 3.6 V VDD–1.3 VOL(1)(3) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +6 mA 0.4 V VOH(2)(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2 V < VDD < 2.7 V VDD–0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production. 54/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 17 and Table 37, respectively. Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 37. I/O AC characteristics(1) MODEx[1:0] bit value(1) Symbol Parameter Conditions Min Max Unit fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time CL = 50 pF, VDD = 2 V to 3.6 V fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time CL = 50 pF, VDD = 2 V to 3.6 V 2 MHz 125(3) ns 125(3) 10 MHz 25(3) ns 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V Fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V 50 MHz 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) 11 tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V 12(3) ns 5(3) tr(IO)out Output low to high level rise time CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) Pulse width of - tEXTIpw external signals detected by the EXTI controller 10 ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 17. 3. Guaranteed by design, not tested in production. Doc ID 15274 Rev 4 55/95 Electrical characteristics Figure 17. I/O AC characteristics definition STM32F105xx, STM32F107xx 90% 50% 10% 10% 50% 90% EXT ERNAL O UTP UT ON 50pF tr(I O)out tr(I O)out T Maximum fr equency is achieved if (tr + tf) d2/3) T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 35). Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 38. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST)(1) NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage –0.5 2 0.8 V VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis 200 mV RPU Weak pull-up equivalent resistor(2) VIN VSS 30 40 50 k: VF(NRST)(1) NRST Input filtered pulse 100 ns VNF(NRST)(1) NRST Input not filtered pulse VDD > 2.7 V 300 ns 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution . to the series resistance must be minimum (~10% order) 56/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Figure 18. Recommended NRST pin protection Electrical characteristics 5.3.14 External reset circuit(1) VDD NRST(2) RPU 0.1 µF Filter Internal reset STM32F10xxx ai14132c 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 38. Otherwise the reset will not be taken into account by the device. TIM timer characteristics The parameters given in Table 39 are guaranteed by design. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 39. TIMx(1) characteristics Symbol Parameter Conditions Min Max Unit tres(TIM) fEXT Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 fTIMxCLK = 72 MHz 1 13.9 0 0 fTIMxCLK/2 36 ResTIM Timer resolution 16 tCOUNTER 16-bit counter clock period 1 when internal clock is selected fTIMxCLK = 72 MHz 0.0139 65536 910 tMAX_COUNT Maximum possible count fTIMxCLK = 72 MHz 65536 × 65536 59.6 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4 and TIM5 timers. tTIMxCLK ns MHz MHz bit tTIMxCLK µs tTIMxCLK s Doc ID 15274 Rev 4 57/95 Electrical characteristics STM32F105xx, STM32F107xx 5.3.15 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9. The STM32F105xx and STM32F107xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 40. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 40. I2C characteristics Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Min Max Min Max Unit tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time 4.7 1.3 µs 4.0 0.6 250 100 0(3) 0(4) 900(3) 1000 20 + 0.1Cb 300 ns 300 300 4.0 0.6 µs 4.7 0.6 tsu(STO) Stop condition setup time 4.0 tw(STO:STA) Stop to Start condition time (bus free) 4.7 0.6 Ps 1.3 Ps Cb Capacitive load for each bus line 400 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 higher must be higher than 2 MHz to achieve the maximum standard mode than 4 MHz to achieve the maximum fast mode I2C frequency. I2C frequency. It must be 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 58/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Figure 19. I2C bus AC waveforms and measurement circuit VDD VDD I²C bus 4 .7 kΩ 4 .7 kΩ 100 Ω 100 Ω STM32F10xxx SDA SCL SD A tf(SDA) S TART S TART REPEATED tsu(STA) S TART tr(SDA) tsu(SDA) th(STA) tw(SCKL) th(SDA) S TOP tsu(STA:STO) SCL tw(SCKH) tr(SCK) tf(SCK) tsu(STO) ai14133c 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 41. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) fSCL (kHz) I2C_CCR value RP = 4.7 k: 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of r5%. For other speed ranges, the tolerance on the achieved speed r2%. These variations depend on the accuracy of the external components used to design the application. Doc ID 15274 Rev 4 59/95 Electrical characteristics STM32F105xx, STM32F107xx I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 42 for SPI or in Table 43 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 42. SPI characteristics(1) Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode Slave mode 18 MHz 18 tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF 8 ns DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 % tsu(NSS)(2) NSS setup time Slave mode 4 tPCLK th(NSS)(2) NSS hold time Slave mode 2 tPCLK tw(SCKH)(2) tw(SCKL)(2) SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 60 ttssuu((MSII))((22)) Master mode Data input setup time Slave mode 5 5 th(MI) (2) th(SI)(2) Data input hold time ta(SO)(2)(3) Data output access time Master mode Slave mode Slave mode, fPCLK = 20 MHz 5 4 ns 0 3 tPCLK tdis(SO)(2)(4) Data output disable time Slave mode 2 10 tv(SO) (2)(1) Data output valid time Slave mode (after enable edge) 25 tv(MO)(2)(1) Data output valid time Master mode (after enable edge) 5 th(SO)(2) Slave mode (after enable edge) Data output hold time 15 th(MO)(2) Master mode (after enable edge) 2 1. Remapped SPI1 characteristics to be determined. 2. Based on characterization, not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 60/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Figure 20. SPI timing diagram - slave mode and CPHA = 0 SCK Input NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tSU(NSS) tc(SCK) tw(SCKH) tw(SCKL) ta(SO) MISO OUT P UT MOSI I NPUT tsu(SI) tv(SO) MS B O UT M SB IN th(SI) th(SO) BI T6 OUT B I T1 IN Figure 21. SPI timing diagram - slave mode and CPHA = 1(1) Electrical characteristics th(NSS) tr(SCK) tf(SCK) tdis(SO) LSB OUT LSB IN ai14134c SCK Input NSS input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) MISO OUT P UT MOSI I NPUT ta(SO) tsu(SI) tc(SCK) tv(SO) MS B O UT th(SI) M SB IN th(SO) BI T6 OUT B I T1 IN 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. th(NSS) tr(SCK) tf(SCK) tdis(SO) LSB OUT LSB IN ai14135 Doc ID 15274 Rev 4 61/95 Electrical characteristics Figure 22. SPI timing diagram - master mode(1) High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tc(SCK) STM32F105xx, STM32F107xx SCK Input SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO INP UT tsu(MI) MOSI OUTU T tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) BI T6 IN B I T1 OUT th(MO) 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. tr(SCK) tf(SCK) LSB IN LSB OUT ai14136 62/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Table 43. I2S characteristics (1) Symbol Parameter Conditions Min fCK 1/tc(CK) I2S clock frequency tr(CK) tf(CK) tv(WS) (2) th(WS) (2) tsu(WS) (2) th(WS) (2) tw(CKH) (2) tw(CKL) (2) tsu(SD_MR) (2) tsu(SD_SR) (2) th(SD_MR)(2)(3) th(SD_SR) (2)(3) th(SD_MR) (2) th(SD_SR) (2) I2S clock rise and fall time WS valid time WS hold time WS setup time WS hold time CK high and low time Data input setup time Data input hold time Data input hold time tv(SD_ST) (2)(3) Data output valid time th(SD_ST) (2) Data output hold time tv(SD_MT) (2)(3) Data output valid time th(SD_MT) (2) Data output hold time Master Slave capacitive load CL = 50 pF Master Master Slave Slave Master fPCLK= TBD, presc = TBD Master receiver Slave receiver Master receiver Slave receiver Master fPCLK = TBD Slave fPCLK = TBD Slave transmitter (after enable edge) fPCLK = TBD Slave transmitter (after enable edge) Master transmitter (after enable edge) fPCLK = TBD Master transmitter (after enable edge) TBD 0 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1. TBD = to be determined. 2. Based on design simulation and/or characterization results, not tested in production. 3. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. Max TBD TBD TBD Unit MHz ns TBD TBD TBD TBD Doc ID 15274 Rev 4 63/95 Electrical characteristics STM32F105xx, STM32F107xx Figure 23. I2S slave timing diagram (Philips protocol)(1) CPOL = 0 tc(CK) CK Input CPOL = 1 WS input SDtransmit SDreceive tw(CKH) tw(CKL) th(WS) tsu(WS) LSB transmit(2) tsu(SD_SR) LSB receive(2) MSB transmit MSB receive tv(SD_ST) Bitn transmit th(SD_SR) Bitn receive th(SD_ST) LSB transmit LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 24. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output CPOL = 0 CPOL = 1 WS output SDtransmit SDreceive tc(CK) tw(CKH) tv(WS) tw(CKL) th(WS) LSB transmit(2) MSB transmit tv(SD_MT) Bitn transmit tsu(SD_MR) LSB receive(2) MSB receive th(SD_MR) Bitn receive th(SD_MT) LSB transmit LSB receive ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 64/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). Table 44. USB OTG FS startup time Symbol Parameter tSTARTUP(1) USB OTG FS transceiver startup time 1. Guaranteed by design, not tested in production. Max Unit 1 µs Table 45. USB OTG FS DC electrical characteristics Symbol Parameter Conditions Min.(1) Typ. Max.(1) Unit Input levels VDD USB OTG FS operating voltage VDI(3) Differential input sensitivity VCM(3) Differential common mode range I(USBDP, USBDM) Includes VDI range 3.0(2) 0.2 0.8 3.6 V 2.5 V VSE(3) Single ended receiver threshold Output VOL levels VOH RPD Static output level low Static output level high Pull-down resistance on PA11, PA12 Pull-down resistance on PA9 1.3 2.0 RL of 1.5 k: to 3.6 V(4) RL of 15 k: to VSS(4) 2.8 0.3 V 3.6 VIN = VDD 17 21 24 0.65 1.1 2.0 k: Pull-up resistance on PA12 RPU Pull-up resistance on PA9 VIN = VSS VIN = VSS 1.5 1.8 2.1 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 2. The STM32F105xx and STM32F107xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers Figure 25. USB OTG FS timings: definition of data signal rise and fall time Differen tial data lines VCR S Crossover points VS S tf tr ai14137 Doc ID 15274 Rev 4 65/95 Electrical characteristics STM32F105xx, STM32F107xx Table 46. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) tf Fall time(2) CL = 50 pF 4 CL = 50 pF 4 20 ns 20 ns trfm Rise/ fall time matching tr/tf 90 110 % VCRS Output signal crossover voltage 1.3 2.0 V 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). Ethernet characteristics Table 47 showns the Ethernet operating voltage. Table 47. Ethernet DC electrical characteristics Symbol Parameter Input level VDD Ethernet operating voltage 1. All the voltages are measured from the local ground potential. Min.(1) 3.0 Max.(1) 3.6 Unit V Table 48 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 26 shows the corresponding timing diagram. Figure 26. Ethernet SMI timing diagram ETH_MDC tMDC td(MDIO) ETH_MDIO(O) tsu(MDIO) ETH_MDIO(I) th(MDIO) ai15666c Table 48. Dynamics characteristics: Ethernet MAC signals for SMI(1) Symbol Rating Min Typ Max Unit tMDC MDC cycle time (1.71 MHz, AHB = 72 MHz) 582.8 583.3 584 ns td(MDIO) MDIO write data valid time 305.2 305.9 306.5 ns tsu(MDIO) Read data setup time TBD TBD TBD ns th(MDIO) Read data hold time TBD TBD TBD ns 1. TBD stands for to be determined. 66/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Table 49 gives the list of Ethernet MAC signals for the RMII and Figure 27 shows the corresponding timing diagram. Figure 27. Ethernet RMII timing diagram RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) RMII_RXD[1:0] RMII_CRS_DV td(TXEN) td(TXD) tih(RXD) tih(CRS) ai15667 Table 49. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Rating Min Typ Max tsu(RXD) Receive data setup time tih(RXD) Receive data hold time tsu(CRS) Carrier sense set-up time tih(CRS) Carrier sense hold time td(TXEN) Transmit enable valid delay time td(TXD) Transmit data valid delay time 1. TBD stands for to be determined. TBD TBD TBD TBD 0 0 TBD TBD TBD TBD 9.6 9.9 TBD TBD TBD TBD 21.9 21 Unit ns ns ns ns ns ns Table 50 gives the list of Ethernet MAC signals for MII and Figure 27 shows the corresponding timing diagram. Figure 28. Ethernet MII timing diagram MII_RX_CLK tsu(RXD) tsu(ER) MII_RXD[3:0] tsu(DV) MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] tih(RXD) tih(ER) tih(DV) td(TXEN) td(TXD) ai15668 Doc ID 15274 Rev 4 67/95 Electrical characteristics STM32F105xx, STM32F107xx Table 50. Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Rating Min Typ Max tsu(RXD) Receive data setup time tih(RXD) Receive data hold time tsu(DV) Data valid setup time tih(DV) Data valid hold time tsu(ER) Error setup time tih(ER) Error hold time td(TXEN) Transmit enable valid delay time td(TXD) Transmit data valid delay time 1. TBD stands for to be determined. TBD TBD TBD TBD TBD TBD 13.4 12.9 TBD TBD TBD TBD TBD TBD 15.5 16.1 TBD TBD TBD TBD TBD TBD 17.7 19.4 Unit ns ns ns ns ns ns ns ns CAN (controller area network) interface Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.16 Note: 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. It is recommended to perform a calibration after each power-up. Table 51. ADC characteristics Symbol Parameter VDDA VREF+ IVREF fADC fS(2) Power supply Positive reference voltage Current on the VREF input pin ADC clock frequency Sampling rate fTRIG(2) External trigger frequency Conditions fADC = 14 MHz Min Typ 2.4 2.4 0.6 0.05 160(1) VAIN Conversion voltage range(3) 0 (VSSA or VREFtied to ground) RAIN(2) External input impedance See Equation 1 and Table 52 for details RADC(2) Sampling switch resistance CADC(2) Internal sample and hold capacitor tCAL(2) Calibration time fADC = 14 MHz 5.9 83 Max Unit 3.6 VDDA 220(1) 14 1 823 17 V V µA MHz MHz kHz 1/fADC VREF+ V 50 k: 1 k: 8 pF µs 1/fADC 68/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Table 51. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max tlat(2) Injection trigger conversion latency tlatr(2) Regular trigger conversion latency tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) fADC = 14 MHz fADC = 14 MHz fADC = 14 MHz fADC = 14 MHz 0.214 3(4) 0.143 2(4) 0.107 17.1 1.5 239.5 0 0 1 1 18 14 to 252 (tS for sampling +12.5 for successive approximation) 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 51. Unit µs 1/fADC µs 1/fADC µs 1/fADC µs µs 1/fADC Equation 1: RAIN max formula RAIN  TS f--A---D----C----u-----C-----A---D---C-----u-----l-n---- ---2---N----+----2--- – RADC The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 52. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) 1.5 0.11 7.5 0.54 13.5 0.96 28.5 2.04 41.5 2.96 55.5 3.96 71.5 5.11 239.5 17.1 1. Based on characterization, not tested in production. 0.4 5.9 11.4 25.2 37.2 50 NA NA RAIN max (k:) Doc ID 15274 Rev 4 69/95 Electrical characteristics STM32F105xx, STM32F107xx Note: Table 53. ADC accuracy - limited test conditions(1) Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k:, VDDA = 3 V to 3.6 V TA = 25 °C Measurements made after ADC calibration 1. ADC DC accuracy values are measured after internal calibration. 2. Based on characterization, not tested in production. Typ ±1.3 ±1 ±0.5 ±0.7 ±0.8 Max(2) ±2 ±1.5 ±1.5 ±1 ±1.5 Unit LSB Table 54. Symbol ADC accuracy(1) (2) Parameter Test conditions Typ Max(3) ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k:, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration ±2 ±1.5 ±1.5 ±1 ±1.5 ±5 ±2.5 ±3 ±2 ±3 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 3. Based on characterization, not tested in production. Unit LSB ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and 6IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. 70/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics Figure 29. ADC accuracy characteristics 4095 4094 4093 7 6 5 4 3 2 1 [1LSBIDEAL =VREF+ 4096 (or VDDA depending 4096 on package)] EG (2) ET (3) (1) EO EL ED 1 LSBIDEAL (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 0 1234567 VSSA 4093 4094 4095 4096 VDDA ai14395b Figure 30. Typical connection diagram using the ADC RAIN(1) AINx VAIN Cparasitic VDD VT 0.6 V VT 0.6 V STM32F10xxx Sample and hold ADC converter RADC(1) 12-bit converter IL±1 µA CADC(1) ai14139d 1. Refer to Table 51 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. Doc ID 15274 Rev 4 71/95 Electrical characteristics STM32F105xx, STM32F107xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 31 or Figure 32, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 31. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F10xxx V REF+ (See note 1) 1 µF // 10 nF 1 µF // 10 nF V DDA V SSA/V REF(See note 1) ai14380c 1. VREF+ and VREF– inputs are available only on 100-pin packages. Figure 32. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F10xxx VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) 1. VREF+ and VREF– inputs are available only on 100-pin packages. ai14381c 72/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics 5.3.17 DAC electrical specifications Table 55. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA VREF+ VSSA RLOAD(1) Analog supply voltage 2.4 Reference supply voltage 2.4 Ground 0 Resistive load with buffer ON 5 RO(1) Impedance output with buffer OFF CLOAD(1) Capacitive load DAC_OUT Lower DAC_OUT voltage min(1) with buffer ON 0.2 DAC_OUT Higher DAC_OUT voltage max(1) with buffer ON DAC_OUT Lower DAC_OUT voltage min(1) with buffer OFF DAC_OUT Higher DAC_OUT voltage max(1) with buffer OFF IDDVREF+ DAC DC current consumption in quiescent mode (Standby mode) DAC DC current consumption IDDA in quiescent mode (Standby mode) 3.6 V 3.6 0 15 50 VDDA – 0.2 V VREF+ must always be below VDDA V k: When the buffer is OFF, the k: Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M: Maximum capacitive load at pF DAC_OUT pin (when the buffer is ON). It gives the maximum output V excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = V 3.6 V and (0x155) to (0xEAB) at VREF+ = 2.4 V 0.5 mV It gives the maximum output excursion of the DAC. VREF+ – 1LSB V With no load, worst code (0xF1C) 220 µA at VREF+ = 3.6 V in terms of DC consumption on the inputs 380 µA With no load, middle code (0x800) on the inputs With no load, worst code (0xF1C) 480 µA at VREF+ = 3.6 V in terms of DC consumption on the inputs DNL(2) INL(2) Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) ±0.5 LSB Given for the DAC in 10-bit configuration. ±2 LSB Given for the DAC in 12-bit configuration. ±1 LSB Given for the DAC in 10-bit configuration. ±4 LSB Given for the DAC in 12-bit configuration. Doc ID 15274 Rev 4 73/95 Electrical characteristics STM32F105xx, STM32F107xx Table 55. DAC characteristics (continued) Symbol Parameter Min Typ Offset(2) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Gain error(2) Gain error Settling time (full scale: for a 10-bit input code transition tSETTLING(2) between the lowest and the highest input codes when 3 DAC_OUT reaches final value ±1LSB Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) Wakeup time from off state tWAKEUP(2) (Setting the ENx bit in the 6.5 DAC Control register) Power supply rejection ratio PSRR+ (1) (to VDDA) (static DC –67 measurement 1. Guaranteed by design, not tested in production. 2. Guaranteed by characterization, not tested in production. Max ±10 ±3 ±12 ±0.5 Unit Comments mV Given for the DAC in 12-bit configuration LSB Given for the DAC in 10-bit at VREF+ = 3.6 V LSB Given for the DAC in 12-bit at VREF+ = 3.6 V % Given for the DAC in 12bit configuration 4 µs CLOAD d 50 pF, RLOAD t 5 k: 1 MS/s CLOAD d 50 pF, RLOAD t 5 k: CLOAD d 50 pF, RLOAD t 5 k: 10 µs input code between lowest and highest possible ones. –40 dB No RLOAD, CLOAD = 50 pF Figure 33. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) 12-bit digital to analog converter DACx_OUT R LOAD C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 74/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Electrical characteristics 5.3.18 Temperature sensor characteristics Table 56. TS characteristics Symbol Parameter Min Typ TL(1) VSENSE linearity with temperature Avg_Slope(1) Average slope V25(1) Voltage at 25 °C tSTART(2) Startup time TS_temp(3)(2) ADC sampling time when reading the temperature r1 4.0 4.3 1.34 1.43 4 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Max Unit r2 °C 4.6 mV/°C 1.52 V 10 µs 17.1 µs Doc ID 15274 Rev 4 75/95 Package characteristics 6 Package characteristics STM32F105xx, STM32F107xx 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 76/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Package characteristics Figure 34. LQFP100, 100-pin low-profile quad flat package outline(1) 75 76 D D1 D3 51 50 0.25 mm 0.10 inch GAGE PLANE k L L1 C Figure 35. Recommended footprint(1)(2) 75 76 16.7 14.3 51 50 0.5 0.3 b E3 E1 E 100 100 Pin 1 1 identification 26 25 e 1. Drawing is not to scale. 2. Dimensions are in millimeters. SEATING PLANE C ccc C A1 A2 A 1L_ME 1 12.3 16.7 Table 57. Symbol LQPF100 – 100-pin low-profile quad flat package mechanical data millimeters inches(1) Typ Min Max Typ Min A 1.60 A1 0.05 0.15 0.002 A2 1.40 1.35 1.45 0.0551 0.0531 b 0.22 0.17 0.27 0.0087 0.0067 c 0.09 0.20 0.0035 D 16.00 15.80 16.20 0.6299 0.622 D1 14.00 13.80 14.20 0.5512 0.5433 D3 12.00 0.4724 E 16.00 15.80 16.20 0.6299 0.622 E1 14.00 13.80 14.20 0.5512 0.5433 E3 12.00 0.4724 e 0.50 0.0197 L 0.60 0.45 0.75 0.0236 0.0177 L1 1.00 0.0394 k 3.5° 0° 7° 3.5° 0° ccc 0.08 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 26 1.2 25 ai14906 Max 0.063 0.0059 0.0571 0.0106 0.0079 0.6378 0.5591 0.6378 0.5591 0.0295 7° Doc ID 15274 Rev 4 77/95 Package characteristics STM32F105xx, STM32F107xx Figure 36. LQFP64 – 64 pin low-profile quad flat package outline(1) A A2 A1 Figure 37. Recommended footprint(1)(2) 48 33 0.3 49 0.5 32 E E1 b 12.7 10.3 e 10.3 64 1 D1 c D L1 7.8 L 12.7 ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 58. Dim. LQFP64 – 64 pin low-profile quad flat package mechanical data mm inches(1) Min Typ Max Min Typ A 1.60 A1 0.05 0.15 0.0020 A2 1.35 1.40 1.45 0.0531 0.0551 b 0.17 0.22 0.27 0.0067 0.0087 c 0.09 0.20 0.0035 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197 T 0° 3.5° 7° 0° 3.5° L 0.45 0.60 0.75 0.0177 0.0236 L1 1.00 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 17 1.2 16 ai14909 Max 0.0630 0.0059 0.0571 0.0106 0.0079 7° 0.0295 78/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Package characteristics 6.2 6.2.1 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 34. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × 4JA) Where: G TA max is the maximum ambient temperature in qC, G 4JA is the package junction-to-ambient thermal resistance, in qC/W, G PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), G PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = 6(VOL × IOL) + 6((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 59. Package thermal characteristics Symbol Parameter Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch 4JA Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch Value 46 45 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Doc ID 15274 Rev 4 79/95 Package characteristics STM32F105xx, STM32F107xx 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 60: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 59 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 60: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW 80/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Package characteristics Using the values obtained in Table 59 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 60: Ordering information scheme). Figure 38. LQFP100 PD max vs. TA PD (mW) 700 600 500 400 300 200 100 0 65 75 85 95 105 115 125 135 TA (°C) Suffix 6 Suffix 7 Doc ID 15274 Rev 4 81/95 Part numbering 7 Part numbering STM32F105xx, STM32F107xx Table 60. Ordering information scheme Example: STM32 F 105 R C Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 105 = connectivity, USB OTG FS 107= connectivity, USB OTG FS & Ethernet Pin count R = 64 pins V = 100 pins Flash memory size 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory C = 256 Kbytes of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Options xxx = programmed parts TR = tape and real T 6 xxx For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 82/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Applicative block diagrams Appendix A Applicative block diagrams A.1 USB OTG FS interface solutions Figure 39. USB OTG FS device mode STM32F105xx/STM32F107xx OTG PHY USB DP Full-speed DM transceiver USB OTG Full-speed core HNP ID VBUS VSS USB Micro-B connector To host DP DM VBUS VSS SRP VDD(1) 5 V to VDD Regulator(2) 1. VDD ranges between 2 V and 3.6 V. 2. Use a regulator if you want to build a bus-powered device. ai15653b Doc ID 15274 Rev 4 83/95 Applicative block diagrams Figure 40. Host connection STM32F105xx/STM32F107xx OTG PHY USB full-speed/ low-speed transceiver USB OTG Full-speed core HNP ID STM32F105xx, STM32F107xx DP DM VBUS VSS USB Std-A connector SRP GPIO GPIO + IRQ VDD(2) Current-limited EN power distribution 5 V OVRCR switch flag STMPS2141STR(1) 1. STMPS2141STR needed only if the application has to support bus-powered devices. 2. VDD ranges between 2 V and 3.6 V. ai15654b 84/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Figure 41. OTG connection (any protocol) STM32F105xx/STM32F107xx USB OTG Full-speed core OTG PHY USB full-speed/ low-speed transceiver HNP ID Applicative block diagrams DP DM ID VBUS VSS USB Micro-AB connector A.2 SRP GPIO GPIO + IRQ VDD(2) Current-limited EN power distribution 5 V OVRCR switch flag STMPS2141STR(1) 1. STMPS2141STR needed only if the application has to support bus-powered devices. 2. VDD ranges between 2 V and 3.6 V. ai15655b Ethernet interface solutions Figure 42. MII mode using a 25 MHz crystal MCU STM32F107xx Ethernet MAC 10/100 HCLK(1) IEEE1588 PTP Timer input TIM2 trigger Timestamp comparator MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MDIO MDC PPS_OUT(2) XTAL 25 MHz OSC PLL HCLK PHY_CLK 25 MHz 1. HCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP, optional signal. Ethernet PHY 10/100 MII = 15 pins MII + MDC = 17 pins XT1 ai15656 Doc ID 15274 Rev 4 85/95 Applicative block diagrams Figure 43. RMII with a 50 MHz oscillator MCU HCLK(1) STM32F107xx Ethernet MAC 10/100 IEEE1588 PTP Timer input TIM2 trigger Timestamp comparator STM32F105xx, STM32F107xx RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK MDIO MDC Ethernet PHY 10/100 RMII = 7 pins RMII + MDC = 9 pins OSC 50 MHz /2 or /20 2.5 or 25 MHz synchronous 50 MHz PLL HCLK PHY_CLK 50 MHz XT1 1. HCLK must be greater than 25 MHz. Figure 44. RMII with a 25 MHz crystal and PHY with PLL 50 MHz ai15657 MCU HCLK(1) STM32F107xx Ethernet MAC 10/100 IEEE1588 PTP Timer input TIM2 trigger Timestamp comparator RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK MDIO MDC Ethernet PHY 10/100 RMII = 7 pins REF_CLK RMII + MDC = 9 pins XTAL 25 MHz /2 or /20 2.5 or 25 MHz synchronous 50 MHz OSC PLL HCLK PLL PHY_CLK 25 MHz XT1 1. HCLK must be greater than 25 MHz. ai15658 86/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Figure 45. RMII with a 25 MHz crystal MCU HCLK STM32F107xx Ethernet MAC 10/100 TIM2 IEEE1588 PTP Timer input trigger Time stamp comparator 50 MHz Applicative block diagrams RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK MDIO MDC Ethernet PHY 10/100 RMII = 7 pins 50 MHz RMII + MDC = 9 pins XTAL 25 MHz OSC PLLS 50 MHz XT1/XT2 NS DP83848(1) ai15659b 1. The NS DP83848 is recommended as the input jitter requirement of this PHY. It is compliant with the output jitter specification of the MCU. Doc ID 15274 Rev 4 87/95 Applicative block diagrams STM32F105xx, STM32F107xx A.3 Complete audio player solutions Two solutions are offered, illustrated in Figure 46 and Figure 47. Figure 46 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I2S accuracy on the master clock (0.5% error maximum, see the Serial peripheral interface section in the reference manual for details). Figure 46. Complete audio player solution 1 STM32F105/STM32F107 XTAL 14.7456 MHz Cortex-M3 core 72 MHz Program memory USB Mass-storage device MMC/ SDCard OTG (host mode) + PHY SPI File System Audio CODEC User application SPI GPIO I2S LCD touch screen Control buttons DAC + Audio ampli Figure 47 shows storage media to audio Codec/amplifier streaming with SOF synchronization of input/output audio streaming using a hardware Codec. ai15660 Figure 47. Complete audio player solution 2 STM32F105/STM32F107 XTAL 14.7456 MHz USB Mass-storage device SOF MMC/ SDCard Cortex-M3 core 72 MHz Program memory OTG + PHY SPI File System User application SPI GPIO I2S SOF synchronization of input/output audio streaming LCD touch screen Control buttons Audio CODEC Audio ampli ai15661 88/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Applicative block diagrams A.4 USB OTG FS interface + Ethernet/I2S interface solutions With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the Ethernet (MII/RMII) interfaces. Figure 48 illustrate the solution. Figure 48. USB OTG FS + Ethernet solution XTAL 25 MHz OSC STM32F107 Div by 5 PLL2 x8 MCU up to 72 MHz Div by 5 sel PLL x9 VCO Out x18 Div by 3 Cortex-M3 core OTG 48 MHz PHY Ethernet MCO PHY MCO sel PLL3 Up to x10 50 MHz MCLK I2S 2% accuracy error SCLK ai15662b With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the I2S (Audio) interfaces. Figure 49 illustrate the solution. Figure 49. USB OTG FS + I2S (Audio) solution XTAL 14.7456 MHz OSC STM32F105/STM32F107 Div by 4 PLL2 x12 MCU Up to 71.88 MHz Cortex-M3 core MCO MCO Div by 4 sel PLL x6.5 VCO Out x13 Div by 3 PLL3 VCO Out x40 Up to I2S 147.456 MHz OTG 47.9232 MHz PHY 0.16% accuracy error Less than 0.5% accuracy error on MCLK and SCLK MCLK SCLK ai15663b Doc ID 15274 Rev 4 89/95 Applicative block diagrams STM32F105xx, STM32F107xx Table 61. PLL configurations Application Crystal value in MHz PREDIV2 PLL2MUL (XT1) PLLSRC PREDIV1 PLLMUL USB prescaler (PLLVCO PLL3MUL output) I2Sn clock input MCO (main clock output) Ethernet only 25 /5 Ethernet + OTG 25 /5 Ethernet + OTG + basic audio 25 /5 Ethernet + OTG + Audio class 14.7456 /4 I2S(1) OTG only 8 NA OTG + basic audio 8 NA OTG + Audio class I2S(1) 14.7456 /4 PLL2ON x8 PLL2ON x8 PLL2ON x8 PLL2 PLL2 PLL2 PLL2ON x12 PLL2 PLL2OFF XT1 PLL2OFF XT1 PLL2ON x12 PLL2 Audio class I2S only(1) 14.7456 /4 PLL2ON x12 PLL2 /5 PLLON x9 NA PLL3ON x10 NA XT1 (MII) PLL3 (RMII) /5 PLLON x9 /3 PLL3ON x10 NA XT1 (MII) PLL3 (RMII) /5 PLLON x9 /3 PLL3ON x10 PLL XT1 (MII) PLL3 (RMII) /4 PLLON x6.5 /3 PLL3ON x20 PLL3 VCO Out NA ETH PHY must use its own crystal /1 PLLON x9 /3 PLL3OFF NA NA /1 PLLON x9 /3 PLL3OFF PLL NA /4 PLLON x6.5 /3 PLL3ON x20 PLL3 VCO Out NA /4 PLLON x6.5 NA PLL3ON x20 PLL3 VCO out NA 1. SYSCLK is set to be at 72 MHz except in this case where SYSCLK is at 71.88 MHz. Table 62 give the IDD run mode values that correspond to the conditions specified in Table 61. 90/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Applicative block diagrams Table 62. Applicative current consumption in Run mode, code with data processing running from Flash Symbol parameter Conditions(1) Typ(2) Max(2) Unit External clock, all peripherals enabled except ethernet, HSE = 8 MHz, fHCLK = 72 MHz, no MCO External clock, all peripherals enabled except ethernet, HSE = 14.74 MHz, fHCLK = 72 MHz, no MCO External clock, all peripherals enabled except OTG, HSE = 25 MHz, fHCLK = 72 MHz, MCO = 25 MHz External clock, all peripherals enabled, IDD Supply current in run mode HSE = 25 MHz, fHCLK = 72 MHz, MCO = 25 MHz External clock, all peripherals enabled, HSE = 25 MHz, fHCLK = 72 MHz, MCO = 50 MHz External clock, all peripherals enabled, HSE = 50 MHz(3), fHCLK = 72 MHz, no MCO External clock, only OTG enabled, HSE = 8 MHz, fHCLK = 48 MHz, no MCO External clock, only ethernet enabled, HSE = 25 MHz, fHCLK = 25 MHz, MCO = 25 MHz 1. VDD = 3.3 V. 2. Based on characterization, not tested in production. 3. External oscillator. 57 60.5 53 60.5 64 62.5 26.7 14.3 85 °C 105 °C 63 64 67 68 60.7 61 65.5 66 mA 69.7 70 67.5 68 None None None None Doc ID 15274 Rev 4 91/95 Revision history Revision history STM32F105xx, STM32F107xx Table 63. Document revision history Date Revision Changes 18-Dec-2008 1 Initial release. 20-Feb-2009 I/O information clarified on page 1. Figure 4: STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view corrected. Section 2.3.8: Boot modes updated. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column, plus small additional changes in Table 5: Pin definitions. Consumption values modified in Section 5.3.5: Supply current 2 characteristics. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. Table 27: PLL characteristics modified and Table 28: PLL2 and PLL3 characteristics added. 92/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Revision history Table 63. Document revision history (continued) Date Revision Changes 19-Jun-2009 Section 2.3.8: Boot modes and Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support updated. Section 2.3.24: Remap capability added. Figure 1: STM32F105xx and STM32F107xx connectivity line block diagram and Figure 4: Memory map updated. In Table 5: Pin definitions: – I2S3_WS, I2S3_CK and I2S3_SD default alternate functions added – small changes in signal names – Note 5 modified – ETH_MII_PPS_OUT and ETH_RMII_PPS_OUT replaced by ETH_PPS_OUT – ETH_MII_MDIO and ETH_RMII_MDIO replaced by ETH_MDIO – ETH_MII_MDC and ETH_RMII_MDC replaced by ETH_MDC Figures: Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled and Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled removed. Table 13: Maximum current consumption in Run mode, code with data processing running from Flash, Table 14: Maximum current consumption in Run mode, code with data processing running from RAM and Table 15: Maximum current consumption in Sleep mode, 3 code running from Flash or RAM are to be determined. Figure 11 and Figure 12 show typical curves. PLL1 renamed to PLL. IDD supply current in Stop mode modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 10: Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values, Figure 12: Typical current consumption in Standby mode versus temperature at different VDD values and Figure 12: Typical current consumption in Standby mode versus temperature at different VDD values updated. Table 17: Typical current consumption in Run mode, code with data processing running from Flash, Table 18: Typical current consumption in Sleep mode, code running from Flash or RAM and Table 19: Peripheral current consumption updated. fHSE_ext modified in Table 20: High-speed external user clock characteristics. Min PLL input clock (fPLL_IN), fPLL_OUT min and fPLL_VCO min modified in Table 27: PLL characteristics. ACCHSI max values modified in Table 24: HSI oscillator characteristics. Table 31: EMS characteristics and Table 32: EMI characteristics updated. Table 42: SPI characteristics updated. Modified: Figure 23: I2S slave timing diagram (Philips protocol)(1), Figure 24: I2S master timing diagram (Philips protocol)(1) and Figure 26: Ethernet SMI timing diagram. BGA100 package removed. Section 6.2: Thermal characteristics added. Small text changes. Doc ID 15274 Rev 4 93/95 Revision history STM32F105xx, STM32F107xx Table 63. Document revision history (continued) Date Revision Changes 14-Sep-2009 Document status promoted from Preliminary data to full datasheet. Number of DACs corrected in Table 3: STM32F105xx and STM32F107xx family versus STM32F103xx family. Note 4 added in Table 5: Pin definitions. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage. Values added to Table 13: Maximum current consumption in Run mode, code with data processing running from Flash, Table 14: Maximum current consumption in Run mode, code with data processing running from RAM and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Typical IDD_VBAT value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 9: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values added. Values modified in Table 17: Typical current consumption in Run mode, code with data processing running from Flash and Table 18: Typical current consumption in Sleep mode, code running from Flash or RAM. fHSE_ext min modified in Table 20: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 22: HSE 3-25 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Note 1 4 modified below Figure 15: Typical application with an 8 MHz crystal. Conditions removed from Table 26: Low-power mode wakeup timings. Standards modified in Section 5.3.10: EMC characteristics on page 50, conditions modified in Table 31: EMS characteristics. Jitter maximum values added to Table 27: PLL characteristics and Table 28: PLL2 and PLL3 characteristics. RPU and RPD modified in Table 35: I/O static characteristics. Condition added for VNF(NRST) parameter in Table 38: NRST pin characteristics. Note removed and RPD, RPU values added in Table 45: USB OTG FS DC electrical characteristics. Table 47: Ethernet DC electrical characteristics added. Parameter values added to Table 48: Dynamics characteristics: Ethernet MAC signals for SMI, Table 49: Dynamics characteristics: Ethernet MAC signals for RMII and Table 50: Dynamics characteristics: Ethernet MAC signals for MII. CADC and RAIN parameters modified in Table 51: ADC characteristics. RAIN max values modified in Table 52: RAIN max for fADC = 14 MHz. Table 55: DAC characteristics modified. Figure 33: 12-bit buffered /non-buffered DAC added. Table 62: Applicative current consumption in Run mode, code with data processing running from Flash added. Small text changes. 94/95 Doc ID 15274 Rev 4 STM32F105xx, STM32F107xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15274 Rev 4 95/95

    Top_arrow
    回到顶部
    EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。