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AR9344.pdf

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标签: AR9344

AR9344 datasheet

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NAND and SPI NOR Flash memory support 10100 Ethernet Switch with five IEEE 8023 Features 74Kc MIPS processor with 64 KB ICache and 32 KB DCache operating at up to 533 MHz External 16 or 32bit DDR1 DDR2 operating at up to 200 MHz 400 M transferssec or 16 bit SDRAM memory interface operating at up to 200 MHz Data Sheet PRELIMINARY December 2010 AR9344 HighlyIntegrated and FeatureRich IEEE 80211n 2x2 245 GHz Premium SoC for Advanced WLAN Platforms General Description The Atheros AR9344 is ......

■ NAND and SPI NOR Flash memory support ■ 10/100 Ethernet Switch with five IEEE 802.3 Features ■ 74Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache, operating at up to 533 MHz ■ External 16- or 32-bit DDR1, DDR2 operating at up to 200 MHz (400 M transfers/sec), or 16- bit SDRAM memory interface operating at up to 200 MHz Data Sheet PRELIMINARY December 2010 AR9344 Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4/5 GHz Premium SoC for Advanced WLAN Platforms General Description The Atheros AR9344 is a highly integrated and feature-rich IEEE 802.11n 2x2 2.4/5 GHz System- on-a-Chip (SoC) for advanced WLAN platforms. It includes a MIPS 74Kc processor, PCI Express 1.1 Root Complex and Endpoint interfaces, five port IEEE 802.3 Fast Ethernet Switch with MAC/ PHY, one MII/RMII/RGMII interface, one USB 2.0 MAC/PHY, and external memory interface for serial Flash, SDRAM, DDR1 or DDR2, I2S/ SPDIF-Out audio interface, SLIC VOIP/PCM interface, two UARTs, and GPIOs that can be used for LED controls or other general purpose interface configurations. The AR9344 supports 802.11n operations up to 144 Mbps for 20 MHz and 300 Mbps for 40 MHz respectively, and 802.11a/b/g data rates. Additional features include Maximal Likelihood (ML) decoding, Low-Density Parity Check (LDPC), Maximal Ratio Combining (MRC), Tx Beamforming (TxBF), and On-Chip One-Time Programmable (OTP) memory. The AR9344 PCIE Root Complex interface can be used to connect to another Atheros single-chip MAC/BB/radio for dual concurrent WLAN applications. The AR9344 supports booting from either NOR or NAND flash. If NOR flash is used as boot codestore, an additional NAND flash device can still be connected, for end-user multi- media storage and other applications. When connecting the AR9344 to an external host through the PCIE Endpoint interface, or the USB Device interface, the AR9344 can off load the host CPU from computation- intensive functions, allowing it to focus on its dedicated tasks. AR9344 System Block Diagram ■ I2S/SPDIF-out audio interface ■ SLIC for VOIP/PCM ■ One low-speed UART (115 Kbps), one high- speed UART (3 Mbps), and multiple GPIO pins for general purpose I/O ■ Optional external LNA/PA ■ 25 MHz or 40 MHz reference clock input ■ 1.2 V switching regulator ■ Advanced power management with dynamic ■ MII/RMII/RGMII interface ■ 802.3az Energy Efficient Ethernet compliant ■ Hardware-based NAT & ACL accelerators for Endpoint interfaces supported simultaneously ■ One USB 2.0 controller with built-in MAC/ PHY supports Host or Device mode ■ Boot from external CPU via PCIE, USB, xMII, eliminating need for external flash clock switching for ultra-low power modes ■ 409-pin BGA package Ethernet interface ■ Both PCI Express 1.1 Root Complex and Ethernet LAN ports ■ Fully integrated RF Front-End including PAs and LNAs © 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, Ethos®, IQUE®, No New Wires®, Orion®, PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, Install N Go™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros • 1 COMPANY CONFIDENTIAL logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice. PRELIMINARY 2 (cid:129) AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC 2 (cid:129) December 2010 Atheros Communications, Inc. COMPANY CONFIDENTIAL Table of Contents 1 Pin Descriptions .......................... 23 2 Functional Description ............... 35 2.1 Functional Block Diagram .................... 35 2.2 Bootstrap Options .................................. 37 2.3 RESET ...................................................... 38 2.4 PLL and Clock Control ......................... 39 2.4.1 Full Chip CLocking Structure ... 39 2.4.1 CPU PLL ...................................... 40 2.4.2 DDR PLL ...................................... 40 2.4.3 Audio PLL ................................... 41 2.5 MIPS Processor ....................................... 41 2.5.1 Configuration .............................. 41 2.6 Address MAP ......................................... 41 2.7 DDR Memory Controller ...................... 42 2.7.1 DDR Configurations .................. 42 2.7.2 Address Mapping ....................... 43 2.7.3 Refresh .......................................... 43 2.8 PCIE EP ................................................... 44 2.8.1 PCIE EP DMA Interface ............. 44 2.8.2 PCIE EP Descriptor Format ....... 44 2.8.3 Reset and Initialization .............. 46 2.8.4 Interrupts ..................................... 46 2.8.5 Power Management ................... 46 2.9 PCIE RC ................................................... 46 2.9.6 Power Management ................... 46 2.9.7 Interrupts ..................................... 46 2.9.8 Error Reporting Capability and Status Checking .......................... 47 2.9.9 Byte-Swap Option ...................... 47 2.9.10 Request Sizes and Payloads ...... 47 2.10 SLIC ......................................................... 47 2.10.1 Overview ..................................... 47 2.10.2 SLIC Interface .............................. 48 2.10.3 Transmit ....................................... 48 2.10.4 Receive ......................................... 48 2.10.5 SLIC Interface Signals ................ 48 2.10.6 SLIC Master and Slave Modes .. 49 2.11 Segmentation/Desegmentation/ Checksum Accelerator 50 2.12 GPIO ....................................................... 52 2.12.1 GPIO Output ............................... 53 PRELIMINARY 2.12.2 GPIO Input .................................. 55 2.13 Serial Flash SPI/ROM .......................... 56 2.13.1 SPI Operations ............................ 56 2.13.2 Write Enable ................................ 56 2.13.3 Page Program .............................. 56 2.13.4 Page Read .................................... 56 2.14 MDIO Slave Interface ........................... 57 2.15 NAND Flash Controller ....................... 57 2.15.1 Devices Supported ..................... 58 2.15.2 Programmable NAND Interface Timing .......................................... 58 2.16 High-Speed UART Interface ............... 59 2.16.1 Transmit (Tx) ............................... 59 2.16.2 Receive (Rx) ................................. 60 2.17 Low-Speed UART Interface ................ 60 2.18 USB 2.0 Interface ................................... 60 3 Ethernet Subsystem .....................61 3.1 GMAC0 and GMAC1 ............................ 61 3.1.1 External RGMII/RMII/MII Interface ....................................... 62 3.1.2 Ingress and Egress Flow of Data and Control Information ................... 63 3.2 GMAC Descriptor Structure: Rx ......... 64 3.2.1 Start Address for Packet Data (PKT_START_ADDR) ................ 64 3.2.2 Packet Size and Flags (PKT_SIZE) 64 3.2.3 Start Address Packet Data (PKT_START_ADDR) ................ 65 3.3 GMAC Descriptor Structure: Tx .......... 65 3.3.1 Start Address for Packet Data (PKT_START_ADDR) ................ 65 3.3.2 Packet Size and Flags (PKT_SIZE) 66 3.3.3 Start Address Packet Data (PKT_START_ADDR) ................ 66 3.4 NAT LUT Structure: Ingress and Egress 67 3.5 Hardware Ager: Ingress and Egress ... 68 3.6 Setup and Data/Packet Flow ............... 68 3.6.1 Ingress .......................................... 68 3.6.2 Egress ........................................... 69 Atheros Communications, Inc. COMPANY CONFIDENTIAL AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC (cid:129) 3 December 2010 (cid:129) 3 PRELIMINARY 3.7 ACL .......................................................... 70 3.7.1 ACL Data Structure .................... 70 3.7.2 Global Rules ................................ 72 3.7.3 Entry Programming ................... 73 3.7.4 ACL Programming and Software Flow .............................................. 73 3.8 Ethernet Switch ...................................... 75 3.9 Five-Port Ethernet Switch ..................... 75 3.9.1 Overview ...................................... 75 3.9.2 Basic Switch Operation .............. 76 3.9.3 Media Access Controllers (MAC) 76 3.9.4 ACL ............................................... 76 3.9.5 Register Access ............................ 77 3.9.6 LED Control ................................. 77 3.9.7 VLANs .......................................... 78 3.9.8 IEEE Port Security ...................... 78 3.9.9 Mirroring ..................................... 78 3.9.10 Broadcast/Multicast/Unknown Unicast .......................................... 78 3.9.11 IGMP/MLD Snooping ............... 78 3.9.12 Spanning Tree ............................. 79 3.9.13 MIB/Statistics Counters ............ 79 3.9.14 Atheros Header Configuration . 81 3.9.15 IEEE 802.3 Reserved Group Addresses Filtering Control ...... 81 3.9.16 PPPoE Header Removal ............ 82 4 Audio Interface ............................ 83 4.1 Overview ................................................. 83 4.2 Audio PLL ............................................... 83 4.3 I2S Interface ............................................. 84 4.3.1 External DAC .............................. 84 4.3.2 Sample Sizes and Rates .............. 84 4.3.3 Stereo Software Interface ........... 84 4.4 SPDIF INTERFACE ............................... 84 4.5 Mailbox (DMA Controller) ................... 85 4.5.1 Mailboxes ..................................... 85 4.5.2 MBOX DMA Operation ............. 85 4.5.3 Software Flow Control ............... 86 4.5.4 Mailbox Error Conditions .......... 86 4.5.5 MBOX-Specific Interrupts ......... 86 5 WLAN Medium Access Control (MAC) 87 5.1 Overview ................................................. 87 5.2 Descriptor ............................................... 87 5.3 Descriptor Format .................................. 88 5.4 Queue Control Unit (QCU) ................ 106 5.5 DCF Control Unit (DCU) .................... 106 5.5.1 DCU State Information ............ 107 5.6 Protocol Control Unit (PCU) .............. 107 6 Digital PHY Block .....................109 6.1 Overview ............................................... 109 6.2 802.11n (MIMO) Mode ........................ 109 6.2.1 Transmitter (Tx) ........................ 109 6.2.2 Receiver (Rx) ............................. 110 6.3 802.11a/b/g Legacy Mode ................. 110 6.3.1 Transmitter ................................ 110 6.3.2 Receiver ...................................... 110 7 Radio Block .................................111 7.1 Receiver (Rx) Block .............................. 112 7.2 Transmitter (Tx) Block ........................ 113 7.3 Synthesizer (SYNTH) Block ............... 114 7.4 Bias/Control (BIAS) Block ................. 114 8 Register Descriptions ................115 8.1 DDR Registers ...................................... 116 8.1.1 DRR DRAM Configuration (DDR_CONFIG) ....................... 117 8.1.2 DDR DRAM Configuration 2 (DDR_CONFIG2) ..................... 117 8.1.3 DDR Mode Value (DDR_MODE_REGISTER) ...... 117 8.1.4 DDR Extended Mode (DDR_EXTENDED_MODE_REGIS TER) ............................................ 118 8.1.5 DDR Control (DDR_CONTROL) . 118 8.1.6 DDR Refresh Control and Configuration (DDR_REFRESH) . 118 8.1.7 DDR Read Data Capture Bit Mask (DDR_RD_DATA_THIS_CYCLE) 118 8.1.8 DQS Delay Tap Control for Byte 0 (TAP_CONTROL_0) ................ 119 8.1.9 DQS Delay Tap Control for Byte 1 (TAP_CONTROL_1) ................ 119 4 (cid:129) AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC 4 (cid:129) December 2010 Atheros Communications, Inc. COMPANY CONFIDENTIAL 8.1.10 DQS Delay Tap Control for Byte 2 (TAP_CONTROL_2) ................ 119 8.1.11 DQS Delay Tap Control for Byte 3 (TAP_CONTROL_3) ................ 120 8.1.12 GMAC0 Interface Write Buffer Flush (DDR_WB_FLUSH_GMAC0) . 120 8.1.13 GMAC1 Interface Write Buffer Flush (DDR_WB_FLUSH_GMAC1) . 120 8.1.14 USB Interface Write Buffer Flush (DDR_WB_FLUSH_USB) ........ 120 8.1.15 PCIE Interface Write Buffer Flush (DDR_WB_FLUSH_PCIE) ....... 121 8.1.16 WMAC Interface Write Buffer Flush (DDR_WB_FLUSH_WMAC) .. 121 8.1.17 SRC1 Interface Write Buffer Flush (DDR_WB_FLUSH_SRC1) ...... 121 8.1.18 SRC2 Interface Write Buffer Flush (DDR_WB_FLUSH_SRC2) ...... 121 8.1.19 DDR2 Configuration (DDR_DDR2_CONFIG) ........... 122 8.1.20 DDR EMR2 (DDR_EMR2) ....... 122 8.1.21 DDR EMR3 (DDR_EMR3) ....... 122 8.1.22 AHB Master Timeout Control (AHB_MASTER_TIMEOUT_MAX) ..................................................... 122 8.1.23 AHB Timeout Current Count (AHB_MASTER_TIMEOUT_CUR NT) .............................................. 123 8.1.24 Timeout Slave Address (AHB_MASTER_TIMEOUT_SLV_ ADDR) ........................................ 123 8.1.25 DDR Controller Configuration (DDR_CTL_CONFIG) .............. 123 8.1.26 DDR Self Refresh Control .............. (DDR_SF_CTL) ......................... 124 8.1.27 Self Refresh Timer (SF_TIMER) 124 8.1.28 WMAC Flush (WMAC_FLUSH) .. 124 8.2 UART0 (Low-Speed) Registers .......... 125 8.2.1 Receive Buffer (RBR) ................ 125 8.2.2 Transmit Holding (THR) ......... 125 8.2.3 Divisor Latch Low (DLL) ........ 126 8.2.4 Divisor Latch High (DLH) ...... 126 8.2.5 Interrupt Enable (IER) .............. 126 8.2.6 Interrupt Identity (IIR) ............. 127 PRELIMINARY 8.2.7 FIFO Control (FCR) .................. 127 8.2.8 Line Control (LCR) ................... 128 8.2.9 Modem Control (MCR) ........... 128 8.2.10 Line Status (LSR) ...................... 129 8.2.11 Modem Status (MSR) ............... 129 8.3 GPIO Registers ..................................... 130 8.3.1 GPIO Output Enable (GPIO_OE) . 131 8.3.2 GPIO Input Value (GPIO_IN) 131 8.3.3 GPIO Output Value (GPIO_OUT) 131 8.3.4 GPIO Per Bit Set (GPIO_SET) . 131 8.3.5 GPIO Per Bit Clear (GPIO_CLEAR) 132 8.3.6 GPIO Interrupt Enable (GPIO_INT) 132 8.3.7 GPIO Interrupt Type (GPIO_INT_TYPE) ................... 132 8.3.8 GPIO Interrupt Polarity (GPIO_INT_POLARITY) ......... 132 8.3.9 GPIO Interrupt Pending (GPIO_INT_PENDING) .......... 133 8.3.10 GPIO Interrupt Mask (GPIO_INT_MASK) ................. 133 8.3.11 GPIO Ethernet LED Routing Select (GPIO_IN_ETH_SWITCH_LED) . 133 8.3.12 GPIO Function 0 (GPIO_OUT_FUNCTION0) .... 134 8.3.13 GPIO Function 1 (GPIO_OUT_FUNCTION1) .... 134 8.3.14 GPIO Function 2 (GPIO_OUT_FUNCTION2) .... 135 8.3.15 GPIO Function 3 (GPIO_OUT_FUNCTION3) .... 135 8.3.16 GPIO Function 4 (GPIO_OUT_FUNCTION4) .... 135 8.3.17 GPIO In Signals 0 (GPIO_IN_ENABLE0) ............. 136 8.3.18 GPIO In Signals 1 (GPIO_IN_ENABLE1) ............. 136 8.3.19 GPIO In Signals 2 (GPIO_IN_ENABLE2) ............. 136 8.3.20 GPIO In Signals 3 (GPIO_IN_ENABLE3) ............. 136 8.3.21 GPIO In Signals 4 (GPIO_IN_ENABLE4) ............. 137 Atheros Communications, Inc. COMPANY CONFIDENTIAL AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC (cid:129) 5 December 2010 (cid:129) 5
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