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    Features • High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier • High Endurance Non-volatile Memory Segments – 64K/128K/256KBytes of In-System Self-Programmable Flash – 4Kbytes EEPROM – 8Kbytes Internal SRAM – Write/Erase Cycles:10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/ 100 years at 25°C – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security • Endurance: Up to 64Kbytes Optional External Memory Space • Atmel® QTouch® library support – Capacitive touch buttons, sliders and wheels – QTouch and QMatrix® acquisition – Up to 64 sense channels • JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode – Real Time Counter with Separate Oscillator – Four 8-bit PWM Channels – Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits (ATmega1281/2561, ATmega640/1280/2560) – Output Compare Modulator – 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560) – Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560) – Master/Slave SPI Serial Interface – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby • I/O and Packages – 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560) – 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561) – 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560) – RoHS/Fully Green • Temperature Range: – -40°C to 85°C Industrial • Ultra-Low Power Consumption – Active Mode: 1MHz, 1.8V: 500µA – Power-down Mode: 0.1µA at 1.8V • Speed Grade: – ATmega640V/ATmega1280V/ATmega1281V: • 0 - 4MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V – ATmega2560V/ATmega2561V: • 0 - 2MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V – ATmega640/ATmega1280/ATmega1281: • 0 - 8MHz @ 2.7V - 5.5V, 0 - 16MHz @ 4.5V - 5.5V – ATmega2560/ATmega2561: • 0 - 16MHz @ 4.5V - 5.5V 8-bit Atmel Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash ATmega640/V ATmega1280/V ATmega1281/V ATmega2560/V ATmega2561/V Preliminary 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 1. Pin Configurations Figure 1-1. TQFP-pinout ATmega640/1280/2560 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) PK0 (ADC8/PCINT16) PK1 (ADC9/PCINT17) PK2 (ADC10/PCINT18) PK3 (ADC11/PCINT19) PK4 (ADC12/PCINT20) PK5 (ADC13/PCINT21) PK6 (ADC14/PCINT22) PK7 (ADC15/PCINT23) GND VCC PJ7 PA0 (AD0) PA1 (AD1) PA2 (AD2) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (OC0B) PG5 1 (RXD0/PCINT8) PE0 2 (TXD0) PE1 3 (XCK0/AIN0) PE2 4 (OC3A/AIN1) PE3 5 (OC3B/INT4) PE4 6 (OC3C/INT5) PE5 7 (T3/INT6) PE6 8 (CLKO/ICP3/INT7) PE7 9 VCC 10 GND 11 (RXD2) PH0 12 (TXD2) PH1 13 (XCK2) PH2 14 (OC4A) PH3 15 (OC4B) PH4 16 (OC4C) PH5 17 (OC2B) PH6 18 (SS/PCINT0) PB0 19 (SCK/PCINT1) PB1 20 (MOSI/PCINT2) PB2 21 (MISO/PCINT3) PB3 22 (OC2A/PCINT4) PB4 23 (OC1A/PCINT5) PB5 24 (OC1B/PCINT6) PB6 25 INDEX CORNER 75 PA3 (AD3) 74 PA4 (AD4) 73 PA5 (AD5) 72 PA6 (AD6) 71 PA7 (AD7) 70 PG2 (ALE) 69 PJ6 (PCINT15) 68 PJ5 (PCINT14) 67 PJ4 (PCINT13) 66 PJ3 (PCINT12) 65 PJ2 (XCK3/PCINT11) 64 PJ1 (TXD3/PCINT10) 63 PJ0 (RXD3/PCINT9) 62 GND 61 VCC 60 PC7 (A15) 59 PC6 (A14) 58 PC5 (A13) 57 PC4 (A12) 56 PC3 (A11) 55 PC2 (A10) 54 PC1 (A9) 53 PC0 (A8) 52 PG1 (RD) 51 PG0 (WR) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (OC0A/OC1C/PCINT7) PB7 (T4) PH7 (TOSC2) PG3 (TOSC1) PG4 RESET VCC GND XTAL2 XTAL1 (ICP4) PL0 (ICP5) PL1 (T5) PL2 (OC5A) PL3 (OC5B) PL4 (OC5C) PL5 PL6 PL7 (SCL/INT0) PD0 (SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (ICP1) PD4 (XCK1) PD5 (T1) PD6 (T0) PD7 2 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Figure 1-2. CBGA-pinout ATmega640/1280/2560 Top view 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K Bottom view 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K Table 1-1. CBGA-pinout ATmega640/1280/2560 1 2 3 4 5 6 7 8 9 10 A GND AREF PF0 PF2 PF5 PK0 PK3 PK6 GND VCC B AVCC PG5 PF1 PF3 PF6 PK1 PK4 PK7 PA0 PA2 C PE2 PE0 PE1 PF4 PF7 PK2 PK5 PJ7 PA1 PA3 D PE3 PE4 PE5 PE6 PH2 PA4 PA5 PA6 PA7 PG2 E PE7 PH0 PH1 PH3 PH5 PJ6 PJ5 PJ4 PJ3 PJ2 F VCC PH4 PH6 PB0 PL4 PD1 PJ1 PJ0 PC7 GND G GND PB1 PB2 PB5 PL2 PD0 PD5 PC5 PC6 VCC H PB3 PB4 RESET PL1 PL3 PL7 PD4 PC4 PC3 PC2 J PH7 PG3 PB6 PL0 XTAL2 PL6 PD3 PC1 PC0 PG1 K PB7 PG4 VCC GND XTAL1 PL5 PD2 PD6 PD7 PG0 Note: The functions for each pin is the same as for the 100 pin packages shown in Figure 1-1 on page 2. 3 2549N–AVR–05/11 Figure 1-3. Pinout ATmega1281/2561 ATmega640/1280/1281/2560/2561 64 AVCC 63 GND 62 AREF 61 PF0 (ADC0) 60 PF1 (ADC1) 59 PF2 (ADC2) 58 PF3 (ADC3) 57 PF4 (ADC4/TCK) 56 PF5 (ADC5/TMS) 55 PF6 (ADC6/TDO) 54 PF7 (ADC7/TDI) 53 GND 52 VCC 51 PA0 (AD0) 50 PA1 (AD1) 49 PA2 (AD2) (OC0B) PG5 1 (RXD0/PCINT8/PDI) PE0 2 (TXD0/PDO) PE1 3 (XCK0/AIN0) PE2 4 (OC3A/AIN1) PE3 5 (OC3B/INT4) PE4 6 (OC3C/INT5) PE5 7 (T3/INT6) PE6 8 (ICP3/CLKO/INT7) PE7 9 (SS/PCINT0) PB0 10 (SCK/ PCINT1) PB1 11 (MOSI/ PCINT2) PB2 12 (MISO/ PCINT3) PB3 13 (OC2A/ PCINT4) PB4 14 (OC1A/PCINT5) PB5 15 (OC1B/PCINT6) PB6 16 INDEX CORNER 48 PA3 (AD3) 47 PA4 (AD4) 46 PA5 (AD5) 45 PA6 (AD6) 44 PA7 (AD7) 43 PG2 (ALE) 42 PC7 (A15) 41 PC6 (A14) 40 PC5 (A13) 39 PC4 (A12) 38 PC3 (A11) 37 PC2 (A10) 36 PC1 (A9) 35 PC0 (A8) 34 PG1 (RD) 33 PG0 (WR) (OC0A/OC1C/PCINT7) PB7 17 (TOSC2) PG3 18 (TOSC1) PG4 19 RESET 20 VCC 21 GND 22 XTAL2 23 XTAL1 24 (SCL/INT0) PD0 25 (SDA/INT1) PD1 26 (RXD1/INT2) PD2 27 (TXD1/INT3) PD3 28 (ICP1) PD4 29 (XCK1) PD5 30 (T1) PD6 31 (T0) PD7 32 Note: The large center pad underneath the QFN/MLF package is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 4 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 2. Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram VCC PF7..0 PK7..0 PJ7..0 PE7..0 RESET GND XTAL1 XTAL2 PA7..0 PG5..0 Power Supervision POR / BOD & RESET Watchdog Timer Watchdog Oscillator Oscillator Circuits / Clock Generation PORT A (8) PORT G (6) PORT F (8) PORT K (8) PORT J (8) PORT E(8) JTAG EEPROM XRAM A/D Converter Internal Bandgap reference CPU Analog Comparator 16 bit T/C3 16 bit T/C5 16 bit T/C4 FLASH SRAM 16 bit T/C1 USART 0 USART 3 USART 1 PC7..0 PORT C (8) TWI SPI 8 bit T/C0 8 bit T/C2 USART 2 NOTE: Shaded parts only available in the 100-pin version. Complete functionality for the ADC,T/C4, and T/C5 only available in the 100-pin version. PORT D (8) PD7..0 PORT B (8) PORT H (8) PB7..0 PH7..0 PORT L (8) PL7..0 5 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 8 Kbytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), six flexible Timer/Counters with compare modes and PWM, 4 USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE® std. 1149.1 compliant JTAG test interface, also used for accessing the Onchip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Powersave mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheelsfunctionality into AVR microcontrollers. The patented charge-transfer signal acquisition offersrobust sensing and includes fully debounced reporting of touch keys and includes Adjacent KeySuppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 6 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1 summarizes the different configurations for the six devices. Table 2-1. Configuration Summary Device ATmega640 ATmega1280 ATmega1281 ATmega2560 ATmega2561 Flash 64KB 128KB 128KB 256KB 256KB EEPROM 4KB 4KB 4KB 4KB 4KB RAM 8KB 8KB 8KB 8KB 8KB General Purpose I/O pins 86 86 54 86 54 16 bits resolution PWM channels 12 12 6 12 6 Serial USARTs 4 4 2 4 2 ADC Channels 16 16 8 16 8 2.3 Pin Descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 78. 2.3.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 79. 2.3.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up 7 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on page 82. 2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 83. 2.3.7 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 86. 2.3.8 Port F (PF7..PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 2.3.9 Port G (PG5..PG0) Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 90. 2.3.10 Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up 8 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 92. 2.3.11 Port J (PJ7..PJ0) Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 94. 2.3.12 Port K (PK7..PK0) Port K serves as analog inputs to the A/D Converter. Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port K output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port K also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 96. 2.3.13 Port L (PL7..PL0) Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port L output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port L pins that are externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port L also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 98. 2.3.14 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System and Reset Characteristics” on page 372. Shorter pulses are not guaranteed to generate a reset. 2.3.15 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.16 XTAL2 Output from the inverting Oscillator amplifier. 9 2549N–AVR–05/11 2.3.17 AVCC 2.3.18 AREF ATmega640/1280/1281/2560/2561 AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. This is the analog reference pin for the A/D Converter. 10 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 3. Resources A comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 ppm over 20 years at 85°C or 100 years at 25°C. 6. Capacitive touch sensing The Atmel®QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. 11 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 7. AVR CPU Core 7.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 7.2 Architectural Overview Figure 7-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Instruction Register Instruction Decoder Control Lines Program Counter Status and Control 32 x 8 General Purpose Registers ALU Interrupt Unit SPI Unit Watchdog Timer Analog Comparator Direct Addressing Indirect Addressing Data SRAM EEPROM I/O Module1 I/O Module 2 I/O Module n I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. 12 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16-bit or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega640/1280/1281/2560/2561 has Extended I/O space from 0x60 - 0x1FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 7.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set Summary” on page 416 for a detailed description. 13 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 7.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the “Instruction Set Summary” on page 416. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 0x3F (0x5F) Read/Write Initial Value 7 6 5 4 3 2 1 0 I T H S V N Z C SREG R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the “Instruction Set Summary” on page 416. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Summary” on page 416 for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Summary” on page 416 for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Summary” on page 416 for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Summary” on page 416 for detailed information. 14 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Summary” on page 416 for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Summary” on page 416 for detailed information. 7.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU General Purpose Working Registers 7.5.1 General Purpose Working Registers 7 0 R0 R1 R2 … R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3 on page 16. 15 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Figure 7-3. The X-, Y-, and Z-registers 15 XH XL 0 X-register 7 07 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 07 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the “Instruction Set Summary” on page 416 for details). 7.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0200. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two for ATmega640/1280/1281 and three for ATmega2560/2561 when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two for ATmega640/1280/1281 and three for ATmega2560/2561 when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 16 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 7.6.1 RAMPZ – Extended Z-pointer Register for ELPM/SPM Bit 0x3B (0x5B) Read/Write Initial Value 7 RAMPZ7 R/W 0 6 RAMPZ6 R/W 0 5 RAMPZ5 R/W 0 4 RAMPZ4 R/W 0 3 RAMPZ3 R/W 0 2 RAMPZ2 R/W 0 1 RAMPZ1 R/W 0 0 RAMPZ0 R/W 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4. Note that LPM is not affected by the RAMPZ setting. Figure 7-4. The Z-pointer used by ELPM and SPM Bit ( Individually) Bit (Z-pointer) 7 0 RAMPZ 23 16 7 0 ZH 15 8 7 0 ZL 7 0 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. 7.6.2 EIND – Extended Indirect Register Bit 0x3C (0x5C) Read/Write Initial Value 7 EIND7 R/W 0 6 EIND6 R/W 0 5 EIND5 R/W 0 4 EIND4 R/W 0 3 EIND3 R/W 0 2 EIND2 R/W 0 1 EIND1 R/W 0 0 EIND0 R/W 0 EIND For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation of EIND, ZH, and ZL, as shown in Figure 7-5. Note that ICALL and IJMP are not affected by the EIND setting. Figure 7-5. The Indirect-pointer used by EICALL and EIJMP Bit (Individual- 7 0 ly) EIND Bit (Indirect- 23 16 pointer) 7 0 ZH 15 8 7 0 ZL 7 0 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. 7.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-6 on page 18 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. 17 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Figure 7-6. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-7. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 7.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 335 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 105. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 105 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 335. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. 18 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1< xxx ... ... ; Main program start ; Set Stack Pointer to top of RAM ; Enable interrupts When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments 0x00000 RESET: ldi r16,high(RAMEND); Main program start 0x00001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x00002 ldi r16,low(RAMEND) 0x00003 0x00004 out SPL,r16 sei ; Enable interrupts 0x00005 xxx ; .org 0x1F002 0x1F002 jmp EXT_INT0 ; IRQ0 Handler 0x1F004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x1FO70 jmp USART3_TXC ; USART3 TX Complete Handler 108 ATmega640/1280/1281/2560/2561 When the BOOTRST Fuse is programmed and the Boot section size set to 8Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org 0x0002 0x00002 jmp EXT_INT0 ; IRQ0 Handler 0x00004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x00070 jmp USART3_TXC ; USART3 TX Complete Handler ; .org 0x1F000 0x1F000 RESET: ldi r16,high(RAMEND); Main program start 0x1F001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x1F002 ldi r16,low(RAMEND) 0x1F003 0x1F004 out SPL,r16 sei ; Enable interrupts 0x1F005 xxx When the BOOTRST Fuse is programmed, the Boot section size set to 8Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments ; .org 0x1F000 0x1F000 0x1F002 jmp RESET jmp EXT_INT0 ; Reset handler ; IRQ0 Handler 0x1F004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x1F070 jmp USART3_TXC ; USART3 TX Complete Handler ; 0x1F072 RESET: ldi r16,high(RAMEND) ; Main program start 0x1F073 out SPH,r16 ; Set Stack Pointer to top of RAM 0x1F074 ldi r16,low(RAMEND) 0x1F075 0x1F076 out SPL,r16 sei ; Enable interrupts 0x1FO77 xxx 14.3 Moving Interrupts Between Application and Boot Section The MCU Control Register controls the placement of the Interrupt Vector table, see Code Example below. For more details, see “Reset and Interrupt Handling” on page 18. 2549N–AVR–05/11 109 ATmega640/1280/1281/2560/2561 Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 18.3 External Clock Source An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 18-1 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkTn pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 18-1. Tn/T0 Pin Sampling Tn clkI/O DQ LE DQ Synchronization DQ Tn_sync (To Clock Select Logic) Edge Detector 2549N–AVR–05/11 169 ATmega640/1280/1281/2560/2561 The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 18-2. Prescaler for synchronous Timer/Counters clkI/O Clear PSR10 Tn Synchronization Tn Synchronization CSn0 CSn1 CSn2 CSn0 CSn1 CSn2 TIMER/COUNTERn CLOCK SOURCE clk Tn TIMER/COUNTERn CLOCK SOURCE clk Tn 18.4 Register Description 18.4.1 GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC GTCCR Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously. 2549N–AVR–05/11 170 ATmega640/1280/1281/2560/2561 • Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters When this bit is one, Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the same prescaler and a reset of this prescaler will affect all timers. 2549N–AVR–05/11 171 ATmega640/1280/1281/2560/2561 19. Output Compare Modulator (OCM1C0A) 19.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see “Timer/Counter 0, 1, 3, 4, and 5 Prescaler” on page 169 and “8bit Timer/Counter2 with PWM and Asynchronous Operation” on page 174. Figure 19-1. Output Compare Modulator, Block Diagram Timer/Counter 1 OC1C Timer/Counter 0 OC0A Pin OC1C / OC0A / PB7 When the modulator is enabled, the two output compare channels are modulated together as shown in the block diagram (see Figure 19-1). 19.2 Description The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The outputs of the Output Compare units (OC1C and OC0A) overrides the normal PORTB7 Register when one of them is enabled (that is, when COMnx1:0 is not equal to zero). When both OC1C and OC0A are enabled at the same time, the modulator is automatically enabled. The functional equivalent schematic of the modulator is shown on Figure 19-2. The schematic includes part of the Timer/Counter units and the port B pin 7 output driver circuit. Figure 19-2. Output Compare Modulator, Schematic COMA01 Vcc COMA00 COM1C1 COM1C0 Modulator 0 ( From Waveform Generator ) DQ 1 ( From Waveform Generator ) OC1C DQ 1 Pin 0 OC1C / OC0A/ PB7 OC0A DQ DQ PORTB7 DATABUS DDRB7 2549N–AVR–05/11 172 ATmega640/1280/1281/2560/2561 When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. 19.2.1 Timing example Figure 19-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 19-3. Output Compare Modulator, Timing Diagram clk I/O OC1C (FPWM Mode) OC0A (CTC Mode) PB7 (PORTB7 = 0) PB7 (PORTB7 = 1) (Period) 1 2 3 In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated by the Output Compare unit C of the Timer/Counter1. The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is equal to the number of system clock cycles of one period of the carrier (OC0A). In this example the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure 19-3 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2 high time is one cycle longer than the period 3 high time, but the result on the PB7 output is equal in both periods. 2549N–AVR–05/11 173 ATmega640/1280/1281/2560/2561 20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B) • Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock 20.1 Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 17-12. For the actual placement of I/O pins, see “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 187. The Power Reduction Timer/Counter2 bit, PRTIM2, in “PRR0 – Power Reduction Register 0” on page 56 must be written to zero to enable Timer/Counter2 module. Figure 20-1. 8-bit Timer/Counter Block Diagram Count Clear Direction Control Logic clkTn Timer/Counter TCNTn = TOP BOTTOM Prescaler = =0 OCnA (Int.Req.) Waveform Generation TOVn (Int.Req.) T/C Oscillator clkI/O TOSC1 TOSC2 OCnA DATA BUS OCRnA = OCRnB Status flags Fixed TOP Value OCnB (Int.Req.) Waveform Generation Synchronized Status flags Synchronization Unit ASSRn asynchronous mode select (ASn) OCnB clkI/O clkASY TCCRnA TCCRnB 2549N–AVR–05/11 174 ATmega640/1280/1281/2560/2561 20.1.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and OC2B). See “Output Compare Unit” on page 180 for details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare interrupt request. 20.1.2 Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used, that is, TCNT2 for accessing Timer/Counter2 counter value and so on. The definitions in Table 20-1 are also used extensively throughout the section. Table 20-1. BOTTOM MAX TOP Definitions The counter reaches the BOTTOM when it becomes zero (0x00) The counter reaches its MAXimum when it becomes 0xFF (decimal 255) The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The assignment is dependent on the mode of operation 20.2 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Operation of Timer/Counter2” on page 184. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 186. 20.3 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 20-2 on page 176 shows a block diagram of the counter and its surrounding environment. 2549N–AVR–05/11 175 ATmega640/1280/1281/2560/2561 Figure 20-2. Counter Unit Block Diagram DATA BUS TOVn (Int.Req.) TCNTn count clear direction Control Logic clk Tn Prescaler T/C Oscillator TOSC1 TOSC2 bottom top clk I/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn top Timer/Counter clock, referred to as clkT2 in the following. Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter Control Register B (TCCR2B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 176. The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt. 20.4 Modes of Operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare match. See “Compare Match Output Unit” on page 182. For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 183. 2549N–AVR–05/11 176 ATmega640/1280/1281/2560/2561 20.4.1 Normal Mode The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 20.4.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 20-3. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 20-3. CTC Mode, Timing Diagram OCnx Interrupt Flag Set 2549N–AVR–05/11 TCNTn OCnx (Toggle) Period 1 2 3 4 (COMnx1:0 = 1) An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for 177 ATmega640/1280/1281/2560/2561 20.4.3 the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following equation: fOCnx = -2----⋅---N------⋅---(f--c1--l-k--+-_---I-/O-O----C----R----n---x----) The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. Fast PWM Mode Figure 20-4. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set 2549N–AVR–05/11 TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when WGM2:0 = 7 (see Table 20-3 on page 187). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: fOCnxPWM = -f--c---l-k--_---I-/-O--N ⋅ 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result 178 ATmega640/1280/1281/2560/2561 in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits). A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 20.4.4 Phase Correct PWM Mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when MGM22:0 = 5. In noninverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 20-5. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 20-5. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx OCnx Period (COMnx1:0 = 2) (COMnx1:0 = 3) 1 2 3 2549N–AVR–05/11 179 ATmega640/1280/1281/2560/2561 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see Table 20-4 on page 188). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: fOCnxPCPWM = -f--c---l-k--_---I-/-O--N ⋅ 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 20-5 on page 179 OCnx has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. • OCR2A changes its value from MAX, like in Figure 20-5 on page 179. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 20.5 Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the Output Compare Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (see “Modes of Operation” on page 176). Figure 20-6 on page 181 shows a block diagram of the Output Compare unit. 2549N–AVR–05/11 180 ATmega640/1280/1281/2560/2561 Figure 20-6. Output Compare Unit, Block Diagram DATA BUS OCRnx = (8-bit Comparator ) top bottom FOCn Waveform Generator TCNTn OCFnx (Int.Req.) OCnx WGMn1:0 COMnX1:0 The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is disabled the CPU will access the OCR2x directly. 20.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). 20.5.2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 20.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. 2549N–AVR–05/11 181 ATmega640/1280/1281/2560/2561 The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 20.6 Compare Match Output Unit The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the OC2x pin output source. Figure 20-7 shows a simplified schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin. Figure 20-7. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator DQ 1 OCnx 0 DQ OCnx Pin DATA BUS PORT DQ clkI/O DDR The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 187. 2549N–AVR–05/11 182 ATmega640/1280/1281/2560/2561 20.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 20-5 on page 188. For fast PWM mode, refer to Table 20-6 on page 188, and for phase correct PWM refer to Table 20-7 on page 189. A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. 20.7 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 20-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 20-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O/1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 20-9 shows the same timing data, but with the prescaler enabled. Figure 20-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn 2549N–AVR–05/11 183 ATmega640/1280/1281/2560/2561 Figure 20-10 shows the setting of OCF2A in all modes except CTC mode. Figure 20-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 20-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 20-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC) OCRnx TOP - 1 TOP BOTTOM TOP BOTTOM + 1 OCFnx 20.8 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2x, and TCCR2x. 4. To switch to asynchronous operation: Wait for TCN2UB, OCR2xUB, and TCR2xUB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. 2549N–AVR–05/11 184 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 • The CPU main clock frequency must be more than four times the Oscillator frequency. • When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the five mentioned registers have their individual temporary register, which means that, for example, writing to TCNT2 does not disturb an OCR2x write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented. • When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or TCCR2x, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if any of the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. • If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and reentering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Powersave or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2x, TCNT2, or OCR2x. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or ADC Noise Reduction mode. • When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon startup, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Powersave mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Write any value to either of the registers OCR2x or TCCR2x. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. 185 ATmega640/1280/1281/2560/2561 • During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 20.9 Timer/Counter Prescaler Figure 20-12. Prescaler for Timer/Counter2 clkI/O TOSC1 clkT2S Clear 10-BIT T/C PRESCALER AS2 clkT2S/8 clkT2S/32 clkT2S/64 clkT2S/128 clkT2S/256 clkT2S/1024 PSRASY 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. By setting the EXCLK bit in the ASSR, a 32kHz external clock can be applied. See “ASSR – Asynchronous Status Register” on page 192 for details. For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 2549N–AVR–05/11 186 ATmega640/1280/1281/2560/2561 20.10 Register Description 20.10.1 TCCR2A –Timer/Counter Control Register A Bit 7 6 5 4 3 (0xB0) COM2A1 COM2A0 COM2B1 COM2B0 – Read/Write R/W R/W R/W R/W R Initial Value 0 0 0 0 0 2 1 0 – WGM21 WGM20 TCCR2A R R/W R/W 0 0 0 • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. Table 20-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 20-2. COM2A1 0 0 1 1 Compare Output Mode, non-PWM Mode COM2A0 Description 0 Normal port operation, OC2A disconnected 1 Toggle OC2A on Compare Match 0 Clear OC2A on Compare Match 1 Set OC2A on Compare Match Table 20-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 20-3. COM2A1 0 0 1 1 Compare Output Mode, Fast PWM Mode(1) COM2A0 Description 0 Normal port operation, OC2A disconnected 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected WGM22 = 1: Toggle OC2A on Compare Match 0 Clear OC2A on Compare Match, set OC2A at BOTTOM (non-inverting mode) 1 Set OC2A on Compare Match, clear OC2A at BOTTOM (inverting mode) Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 178 for more details. Table 20-4 on page 188 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. 2549N–AVR–05/11 187 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table 20-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 0 COM2A0 0 Description Normal port operation, OC2A disconnected 0 1 1 0 WGM22 = 0: Normal Port Operation, OC2A Disconnected WGM22 = 1: Toggle OC2A on Compare Match Clear OC2A on Compare Match when up-counting Set OC2A on Compare Match when down-counting 1 1 Set OC2A on Compare Match when up-counting Clear OC2A on Compare Match when down-counting Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 179 for more details. • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver. When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. Table 20-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 20-5. COM2B1 0 0 1 1 Compare Output Mode, non-PWM Mode COM2B0 Description 0 Normal port operation, OC2B disconnected 1 Toggle OC2B on Compare Match 0 Clear OC2B on Compare Match 1 Set OC2B on Compare Match Table 20-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode. Table 20-6. COM2B1 0 0 1 1 Compare Output Mode, Fast PWM Mode(1) COM2B0 Description 0 Normal port operation, OC2B disconnected 1 Reserved 0 Clear OC2B on Compare Match, set OC2B at BOTTOM (non-inverting mode) 1 Set OC2B on Compare Match, clear OC2B at BOTTOM (inverting mode) Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 178 for more details. 188 ATmega640/1280/1281/2560/2561 Table 20-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 20-7. COM2B1 0 0 1 1 Compare Output Mode, Phase Correct PWM Mode(1) COM2B0 Description 0 Normal port operation, OC2B disconnected 1 Reserved 0 Clear OC2B on Compare Match when up-counting Set OC2B on Compare Match when down-counting 1 Set OC2B on Compare Match when up-counting Clear OC2B on Compare Match when down-counting Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 179 for more details. • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 20-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 176). Table 20-8. Waveform Generation Mode Bit Description Mode WGM2 WGM1 WGM0 Timer/Counter Mode of Operation TOP 0 0 0 0 Normal 0xFF 1 0 0 1 PWM, Phase Correct 0xFF 2 0 1 0 CTC OCRA 3 0 1 1 Fast PWM 0xFF 4 1 0 0 Reserved – 5 1 0 1 PWM, Phase Correct OCRA 6 1 1 0 Reserved – 7 1 1 1 Fast PWM OCRA Update of OCRx at Immediate TOP Immediate BOTTOM – TOP – BOTTOM TOV Flag Set on(1)(2) MAX BOTTOM MAX MAX – BOTTOM – TOP Notes: 1. MAX = 0xFF. 2. BOTTOM = 0x00. 2549N–AVR–05/11 189 ATmega640/1280/1281/2560/2561 20.10.2 TCCR2B – Timer/Counter Control Register B Bit 7 6 5 (0xB1) FOC2A FOC2B – Read/Write W W R Initial Value 0 0 0 4 3 2 1 0 – WGM22 CS22 CS21 CS20 TCCR2B R R/W R/W R/W R/W 0 0 0 0 0 • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. • Bit 6 – FOC2B: Force Output Compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the forced compare. A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the “TCCR2A –Timer/Counter Control Register A” on page 187. • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 20-9 on page 191. 2549N–AVR–05/11 190 ATmega640/1280/1281/2560/2561 Table 20-9. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkT2S/(No prescaling) 0 1 0 clkT2S/8 (From prescaler) 0 1 1 clkT2S/32 (From prescaler) 1 0 0 clkT2S/64 (From prescaler) 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 20.10.3 TCNT2 – Timer/Counter Register Bit (0xB2) Read/Write Initial Value 7 6 5 4 3 2 1 0 TCNT2[7:0] TCNT2 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. 20.10.4 OCR2A – Output Compare Register A Bit (0xB3) Read/Write Initial Value 7 6 5 4 3 2 1 0 OCR2A[7:0] OCR2A R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. 20.10.5 OCR2B – Output Compare Register B Bit (0xB4) Read/Write Initial Value 7 6 5 4 3 2 1 0 OCR2B[7:0] OCR2B R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2B pin. 2549N–AVR–05/11 191 ATmega640/1280/1281/2560/2561 20.10.6 ASSR – Asynchronous Status Register Bit (0xB6) Read/Write Initial Value 7 6 5 – EXCLK AS2 R R/W R/W 0 0 0 4 TCN2UB R 0 3 OCR2AUB R 0 2 OCR2BUB R 0 1 TCR2AUB R 0 0 TCR2BUB R 0 ASSR • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. • Bit 5 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted. • Bit 4 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 3 – OCR2AUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. • Bit 2 – OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. • Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. • Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value. If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. 2549N–AVR–05/11 192 ATmega640/1280/1281/2560/2561 The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 20.10.7 TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit (0x70) Read/Write Initial Value 7 6 5 4 – – – – R R R R 0 0 0 0 3 2 1 0 – OCIE2B OCIE2A TOIE2 TIMSK2 R R/W R/W R/W 0 0 0 0 • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, that is, when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2. • Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, that is, when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2. • Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. 20.10.8 TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x17 (0x37) – – – – – OCF2B OCF2A TOV2 TIFR2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 2 – OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. 2549N–AVR–05/11 193 ATmega640/1280/1281/2560/2561 • Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 20.10.9 GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC GTCCR Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 1 – PSRASY: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 170 for a description of the Timer/Counter Synchronization mode. 2549N–AVR–05/11 194 ATmega640/1280/1281/2560/2561 21. SPI – Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega640/1280/1281/2560/2561 and peripheral devices or between several AVR devices. The ATmega640/1280/1281/2560/2561 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 232. The Power Reduction SPI bit, PRSPI, in “PRR0 – Power Reduction Register 0” on page 56 on page 50 must be written to zero to enable SPI module. Figure 21-1. SPI Block Diagram(1) DIVIDER /2/4/8/16/32/64/128 SPI2X SPI2X 2549N–AVR–05/11 Note: 1. Refer to Figure 1-1 on page 2, and Table 13-6 on page 79 for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in Figure 21-2 on page 196. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. 195 ATmega640/1280/1281/2560/2561 Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 21-2. SPI Master-slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. 2549N–AVR–05/11 196 ATmega640/1280/1281/2560/2561 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 21-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 75. Table 21-1. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See “Alternate Functions of Port B” on page 79 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 2549N–AVR–05/11 197 ATmega640/1280/1281/2560/2561 Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. See “About Code Examples” on page 11. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 22.6.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive 2549N–AVR–05/11 216 ATmega640/1280/1281/2560/2561 buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates. 22.6.4 Receiver Error Flags The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations. None of the Error Flags can generate interrupts. The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see “Parity Bit Calculation” on page 210 and “Parity Checker” on page 217. 22.6.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 2549N–AVR–05/11 217 ATmega640/1280/1281/2560/2561 22.6.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost. 22.6.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to flush the receive buffer. Assembly Code Example(1) USART_Flush: sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRnA & (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz Serial Programming Algorithm When writing serial data to the ATmega640/1280/1281/2560/2561, data is clocked on the rising edge of SCK. When reading data from the ATmega640/1280/1281/2560/2561, data is clocked on the falling edge of SCK. See Figure 30-12 on page 353 for timing details. 2549N–AVR–05/11 350 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 To program and verify the ATmega640/1280/1281/2560/2561 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in Table 30-17 on page 352): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin PDI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the address lines 15:8. Before issuing this command, make sure the instruction Load Extended Address Byte has been used to define the MSB of the address. The extended address byte is stored until the command is re-issued, that is, the command needs only be issued for the first page, and when crossing the 64KWord boundary. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page (see Table 3016). Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte (see Table 30-16). In a chip erased device, no 0xFFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output PDO. When reading the Flash memory, use the instruction Load Extended Address Byte to define the upper address byte, which is not included in the Read Program Memory instruction. The extended address byte is stored until the command is re-issued, that is, the command needs only be issued for the first page, and when crossing the 64KWord boundary. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 30-16. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH tWD_EEPROM tWD_ERASE 4.5ms 3.6ms 9.0ms 351 ATmega640/1280/1281/2560/2561 30.8.3 Serial Programming Instruction set Table 30-17 and Figure 30-11 on page 353 describes the Instruction set. Table 30-17. Serial Programming Instruction Set Instruction Format Instruction/Operation Byte 1 Byte 2 Byte 3 Byte 4 Programming Enable $AC $53 $00 $00 Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00 Poll RDY/BSY $F0 $00 $00 data byte out Load Instructions Load Extended Address byte(1) $4D $00 Extended adr $00 Load Program Memory Page, High byte $48 $00 adr LSB high data byte in Load Program Memory Page, Low byte $40 $00 adr LSB low data byte in Load EEPROM Memory Page (page access) $C1 $00 0000 000aa data byte in Read Instructions Read Program Memory, High byte $28 adr MSB adr LSB high data byte out Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out Read EEPROM Memory $A0 0000 aaaa aaaa aaaa data byte out Read Lock bits $58 $00 $00 data byte out Read Signature Byte $30 $00 0000 000aa data byte out Read Fuse bits $50 $00 $00 data byte out Read Fuse High bits $58 $08 $00 data byte out Read Extended Fuse Bits $50 $08 $00 data byte out Read Calibration Byte $38 $00 $00 data byte out Write Instructions Write Program Memory Page $4C adr MSB adr LSB $00 Write EEPROM Memory $C0 0000 aaaa aaaa aaaa data byte in Write EEPROM Memory Page (page access) $C2 0000 aaaa aaaa 00 $00 Write Lock bits $AC $E0 $00 data byte in Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte in Notes: 1. Not all instructions are applicable for all parts. 2. a = address. 3. Bits are programmed ‘0’, unprogrammed ‘1’. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’). 5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. 2549N–AVR–05/11 352 ATmega640/1280/1281/2560/2561 Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 30-11. Figure 30-11. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 2 Adr MSB Bit 15 B Byte 3 Adr LSB 0 Byte 4 Byte 1 Byte 2 Adr MSB Bit 15 B Byte 3 Adr LSB 0 Byte 4 Page Offset Page Buffer Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 30.8.4 Serial Programming Characteristics For characteristics of the Serial Programming module, see “SPI Timing Characteristics” on page 375. Figure 30-12. Serial Programming Waveforms SERIAL DATA INPUT MSB LSB (MOSI) SERIAL DATA OUTPUT MSB LSB (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE 2549N–AVR–05/11 353 ATmega640/1280/1281/2560/2561 30.9 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in Running mode while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose. During programming the clock frequency of the TCK Input must be less than the maximum frequency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency. As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers. 30.9.1 Programming Specific JTAG Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which Data Register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 30-13 on page 355. 2549N–AVR–05/11 354 ATmega640/1280/1281/2560/2561 Figure 30-13. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 1 0 1 Capture-DR 0 1 Capture-IR 0 0 Shift-DR 0 Shift-IR 0 1 Exit1-DR 1 1 Exit1-IR 1 0 0 Pause-DR 0 Pause-IR 0 1 0 Exit2-DR 1 0 Exit2-IR 1 1 Update-DR 1 0 Update-IR 1 0 30.9.2 30.9.3 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the reset will be active as long as there is a logic “one” in the Reset Chain. The output from this chain is not latched. The active states are: • Shift-DR: The Reset Register is shifted by the TCK input PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16bit Programming Enable Register is selected as Data Register. The active states are the following: • Shift-DR: The programming enable signature is shifted into the Data Register • Update-DR: The programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid 2549N–AVR–05/11 355 ATmega640/1280/1281/2560/2561 30.9.4 30.9.5 30.9.6 30.9.7 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command • Update-DR: The programming command is applied to the Flash inputs • Run-Test/Idle: One clock cycle is generated, executing the applied command PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs of the Programming Command Register. The active states are the following: • Shift-DR: The Flash Data Byte Register is shifted by the TCK input. • Update-DR: The content of the Flash Data Byte Register is copied into a temporary register. A write sequence is initiated that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the program counter increment into the next page. PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs of the Programming Command Register. The active states are the following: • Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte Register. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. • Shift-DR: The Flash Data Byte Register is shifted by the TCK input. Data Registers The Data Registers are selected by the JTAG instruction registers described in section “Programming Specific JTAG Instructions” on page 354. The Data Registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register 2549N–AVR–05/11 356 ATmega640/1280/1281/2560/2561 30.9.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out period (refer to “Clock Sources” on page 41) after releasing the Reset Register. The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 28-2 on page 304. 30.9.9 Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 30-14. Programming Enable Register TDI D A 0xA370 = T A D Q Programming Enable ClockDR & PROG_ENABLE TDO 30.9.10 Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 30-18 on page 359. The state sequence when shifting in the programming commands is illustrated in Figure 30-16 on page 362. 2549N–AVR–05/11 357 ATmega640/1280/1281/2560/2561 Figure 30-15. Programming Command Register TDI S T R O B E S Flash EEPROM A Fuses D Lock Bits D R E S S / D A T A TDO 2549N–AVR–05/11 358 ATmega640/1280/1281/2560/2561 Table 30-18. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx (2) 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. Load Address Extended High Byte 0001011_cccccccc xxxxxxx_xxxxxxxx (10) 2c. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 2d. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2e. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 2f. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx 2g. Latch Data 0110111_00000000 xxxxxxx_xxxxxxxx 1110111_00000000 xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 2h. Write Flash Page 0110111_00000000 xxxxxxx_xxxxxxxx 0110101_00000000 xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2i. Poll for Page Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address Extended High Byte 0001011_cccccccc xxxxxxx_xxxxxxxx (10) 3c. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 3d. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 3e. Read Data Low and High Byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo Low byte High byte 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (10) 4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 4e. Latch Data 0110111_00000000 xxxxxxx_xxxxxxxx 1110111_00000000 xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 4f. Write EEPROM Page 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx (1) 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 2549N–AVR–05/11 359 ATmega640/1280/1281/2560/2561 Table 30-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (10) 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 6a. Enter Fuse Write 6b. Load Data Low Byte(6) 0100011_01000000 xxxxxxx_xxxxxxxx 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. Write Fuse Extended Byte 0111011_00000000 xxxxxxx_xxxxxxxx 0111001_00000000 xxxxxxx_xxxxxxxx (1) 0111011_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_xxxxxxxx 6d. Poll for Fuse Write Complete 6e. Load Data Low Byte(7) 0110111_00000000 xxxxxox_xxxxxxxx (2) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. Write Fuse High Byte 0110111_00000000 xxxxxxx_xxxxxxxx 0110101_00000000 xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 6g. Poll for Fuse Write Complete 6h. Load Data Low Byte(7) 0110111_00000000 xxxxxox_xxxxxxxx (2) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. Write Fuse Low Byte 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx (1) 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 6j. Poll for Fuse Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 7a. Enter Lock Bit Write 7b. Load Data Byte(9) 0100011_00100000 xxxxxxx_xxxxxxxx 0010011_11iiiiii xxxxxxx_xxxxxxxx (4) 7c. Write Lock Bits 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx (1) 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. Read Extended Fuse Byte(6) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8c. Read Fuse High Byte(7) 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 2549N–AVR–05/11 360 ATmega640/1280/1281/2560/2561 Table 30-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8d. Read Fuse Low Byte(8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8e. Read Lock Bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx (5) xxxxxxx_xxoooooo 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 9c. Read Signature Byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 11a. Load No Operation Command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is normally the case). 2. Repeat until o = “1”. 3. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse. 4. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged. 5. “0” = programmed, “1” = unprogrammed. 6. The bit mapping for Fuses Extended byte is listed in Table 30-3 on page 336. 7. The bit mapping for Fuses High byte is listed in Table 30-4 on page 337. 8. The bit mapping for Fuses Low byte is listed in Table 30-5 on page 337. 9. The bit mapping for Lock bits byte is listed in Table 30-1 on page 335. 10. Address bits exceeding PCMSB and EEAMSB (Table 30-7 on page 338 and Table 30-8 on page 338) are don’t care. 11. All TDI and TDO sequences are represented by binary digits (0b...). 2549N–AVR–05/11 361 ATmega640/1280/1281/2560/2561 Figure 30-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 1 0 1 Capture-DR 0 1 Capture-IR 0 0 Shift-DR 0 Shift-IR 0 1 Exit1-DR 1 1 Exit1-IR 1 0 0 Pause-DR 0 Pause-IR 0 1 0 Exit2-DR 1 0 Exit2-IR 1 1 Update-DR 1 0 Update-IR 1 0 30.9.11 Flash Data Byte Register The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer before executing Page Write, or to read out/verify the content of the Flash. A state machine sets up the control signals to the Flash and senses the strobe signals from the Flash, thus only the data words need to be shifted in/out. The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary register. During page load, the Update-DR state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the Program Counter increment into the next page. During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte Register during the Capture-DR state. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Cap- 2549N–AVR–05/11 362 ATmega640/1280/1281/2560/2561 ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 30-17. Flash Data Byte Register STROBES State Machine TDI ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller automatically feeds the state machine for the Flash Data Byte Register with sufficient number of clock pulses to complete its operation transparently for the user. However, if too few bits are shifted between each Update-DR state during page load, the TAP controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at least 11 TCK cycles between each Update-DR state. 30.9.12 Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 30-18 on page 359. 30.9.13 Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Programming Enable Register. 30.9.14 Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the programming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. 2549N–AVR–05/11 363 ATmega640/1280/1281/2560/2561 30.9.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 30-14 on page 348). 30.9.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 364. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address Extended High byte using programming instruction 2b. 4. Load address High byte using programming instruction 2c. 5. Load address Low byte using programming instruction 2d. 6. Load data using programming instructions 2e, 2f and 2g. 7. Repeat steps 5 and 6 for all instruction words in the page. 8. Write the page using programming instruction 2h. 9. Poll for Flash write complete using programming instruction 2i, or wait for tWLRH (refer to Table 30-14 on page 348). 10. Repeat steps 3 to 9 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b, 2c and 2d. PCWORD (refer to Table 30-7 on page 338) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGELOAD. 5. Load the entire page by shifting in all instruction words in the page byte-by-byte, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Use Update-DR to copy the contents of the Flash Data Byte Register into the Flash page location and to auto-increment the Program Counter before each new word. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2h. 8. Poll for Flash write complete using programming instruction 2i, or wait for tWLRH (refer to Table 30-14 on page 348). 9. Repeat steps 3 to 8 until all data have been programmed. 30.9.17 Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b, 3c and 3d. 4. Read data using programming instruction 3e. 5. Repeat steps 3 and 4 until all data have been read. 2549N–AVR–05/11 364 ATmega640/1280/1281/2560/2561 A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b, 3c and 3d. PCWORD (refer to Table 30-7 on page 338) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash). The Capture-DR state both captures the data from the Flash, and also auto-increments the program counter after each word is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is shifted out contains valid data. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. 30.9.18 Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed, see “Performing Chip Erase” on page 364. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address High byte using programming instruction 4b. 4. Load address Low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7. Write the data using programming instruction 4f. 8. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to Table 30-14 on page 348). 9. Repeat steps 3 to 8 until all data have been programmed. Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM. 30.9.19 Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM. 30.9.20 Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data high byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. 4. Write Fuse High byte using programming instruction 6c. 2549N–AVR–05/11 365 ATmega640/1280/1281/2560/2561 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 30-14 on page 348). 6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 30-14 on page 348). 30.9.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 30-14 on page 348). 30.9.22 Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8e. To only read Fuse High byte, use programming instruction 8b. To only read Fuse Low byte, use programming instruction 8c. To only read Lock bits, use programming instruction 8d. 30.9.23 Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address 0x00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 30.9.24 Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3. Load address 0x00 using programming instruction 10b. 4. Read the calibration byte using programming instruction 10c. 2549N–AVR–05/11 366 ATmega640/1280/1281/2560/2561 31. Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ................................................ 40.0mA DC Current VCC and GND Pins................................. 200.0mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 31.1 DC Characteristics TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition VIL Input Low Voltage,Except VCC = 1.8V - 2.4V XTAL1 and Reset pin VCC = 2.4V - 5.5V VIL1 Input Low Voltage, XTAL1 pin VCC = 1.8V - 5.5V VIL2 Input Low Voltage, RESET pin VCC = 1.8V - 5.5V Input High Voltage, VIH Except XTAL1 and RESET pins VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VIH1 Input High Voltage, XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VIH2 Input High Voltage, RESET pin VCC = 1.8V - 5.5V VOL Output Low Voltage(3), Except RESET pin IOL = 20mA, VCC = 5V IOL = 10mA, VCC = 3V VOH Output High Voltage(4), Except RESET pin IOH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) RRST RPU Reset Pull-up Resistor I/O Pin Pull-up Resistor Min. -0.5 -0.5 -0.5 -0.5 0.7VCC(2) 0.6VCC(2) 0.8VCC(2) 0.7VCC(2) 0.9VCC(2) 4.2 2.3 30 20 Typ. Max. 0.2VCC(1) 0.3VCC(1) 0.1VCC(1) 0.1VCC(1) VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.9 0.6 1 1 60 50 Units V µA kΩ 2549N–AVR–05/11 367 ATmega640/1280/1281/2560/2561 TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units Active 1MHz, VCC = 2V (ATmega640/1280/2560/1V) 0.5 0.8 Active 4MHz, VCC = 3V (ATmega640/1280/2560/1L) 3.2 5 Active 8MHz, VCC = 5V (ATmega640/1280/1281/2560/2561) Power Supply Current(5) ICC Idle 1MHz, VCC = 2V (ATmega640/1280/2560/1V) 10 14 mA 0.14 0.22 Idle 4MHz, VCC = 3V (ATmega640/1280/2560/1L) 0.7 1.1 Idle 8MHz, VCC = 5V (ATmega640/1280/1281/2560/2561) 2.7 4 Power-down mode WDT enabled, VCC = 3V WDT disabled, VCC = 3V <5 15 µA <1 7.5 VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 <10 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V 750 500 ns Notes: 1. "Max" means the highest value where the pin is guaranteed to be read as low. 2. "Min" means the lowest value where the pin is guaranteed to be read as high. 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: ATmega1281/2561: 1.)The sum of all IOL, for ports A0-A7, G2, C4-C7 should not exceed 100mA. 2.)The sum of all IOL, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA. 3.)The sum of all IOL, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA. 4.)The sum of all IOL, for ports F0-F7 should not exceed 100mA. ATmega640/1280/2560: 1.)The sum of all IOL, for ports J0-J7, A0-A7, G2 should not exceed 200mA. 2.)The sum of all IOL, for ports C0-C7, G0-G1, D0-D7, L0-L7 should not exceed 200mA. 3.)The sum of all IOL, for ports G3-G4, B0-B7, H0-B7 should not exceed 200mA. 4.)The sum of all IOL, for ports E0-E7, G5 should not exceed 100mA. 5.)The sum of all IOL, for ports F0-F7, K0-K7 should not exceed 100mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: ATmega1281/2561: 1)The sum of all IOH, for ports A0-A7, G2, C4-C7 should not exceed 100mA. 2)The sum of all IOH, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA. 3)The sum of all IOH, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA. 4)The sum of all IOH, for ports F0-F7 should not exceed 100mA. ATmega640/1280/2560: 1)The sum of all IOH, for ports J0-J7, G2, A0-A7 should not exceed 200mA. 2)The sum of all IOH, for ports C0-C7, G0-G1, D0-D7, L0-L7 should not exceed 200mA. 3)The sum of all IOH, for ports G3-G4, B0-B7, H0-H7 should not exceed 200mA. 4)The sum of all IOH, for ports E0-E7, G5 should not exceed 100mA. 2549N–AVR–05/11 368 ATmega640/1280/1281/2560/2561 5)The sum of all IOH, for ports F0-F7, K0-K7 should not exceed 100mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Values with “PRR1 – Power Reduction Register 1” enabled (0xFF). 31.2 Speed Grades Maximum frequency is depending on VCC. As shown in Figure 31-1 trough Figure 31-4 on page 370, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. 31.2.1 8MHz Figure 31-1. Maximum Frequency vs. VCC, ATmega640V/1280V/1281V/2560V/2561V 8 MHz 4 MHz Safe Operating Area 1.8V 2.7V 5.5V Figure 31-2. Maximum Frequency vs. VCC when also No-Read-While-Write Section(1), ATmega2560V/ATmega2561V, is used 8 MHz 2 MHz Safe Operating Area 1.8V 2.7V 5.5V Note: 1. When only using the Read-While-Write Section of the program memory, a higher speed can be achieved at low voltage, see “Read-While-Write and No Read-While-Write Flash Sections” on page 317 for addresses. 2549N–AVR–05/11 369 31.2.2 16 MHz ATmega640/1280/1281/2560/2561 Figure 31-3. Maximum Frequency vs. VCC, ATmega640/ATmega1280/ATmega1281 16 MHz 8 MHz Safe Operating Area 2.7V 4.5V 5.5V Figure 31-4. Maximum Frequency vs. VCC, ATmega2560/ATmega2561 16 MHz Safe Operating Area 4.5V 5.5V 2549N–AVR–05/11 370 ATmega640/1280/1281/2560/2561 31.3 Clock Characteristics 31.3.1 Calibrated Internal RC Oscillator Accuracy Table 31-1. Calibration Accuracy of Internal RC Oscillator Factory Calibration User Calibration Frequency 8.0MHz 7.3MHz - 8.1MHz VCC 3V 1.8V - 5.5V(1) 2.7V - 5.5V(2) Notes: 1. Voltage range for ATmega640V/1281V/1280V/2561V/2560V. 2. Voltage range for ATmega640/1281/1280/2561/2560. Temperature 25°C -40°C - 85°C 31.3.2 External Clock Drive Waveforms Figure 31-5. External Clock Drive Waveforms Calibration Accuracy ±10% ±1% VIH1 VIL1 31.4 External Clock Drive Table 31-2. External Clock Drive Symbol Parameter VCC = 1.8V - 5.5V Min. Max. 1/tCLCL Oscillator Frequency 0 2 tCLCL Clock Period 500 tCHCX High Time 200 tCLCX Low Time 200 tCLCH Rise Time 2.0 tCHCL Fall Time 2.0 Change in period ΔtCLCL from one clock 2 cycle to the next VCC = 2.7V - 5.5V Min. Max. 0 8 125 50 50 1.6 1.6 2 VCC = 4.5V - 5.5V Min. Max. 0 16 62.5 25 25 0.5 0.5 2 Units MHz ns μs % 2549N–AVR–05/11 371 ATmega640/1280/1281/2560/2561 31.5 System and Reset Characteristics Table 31-3. Reset, Brown-out and Internal voltage CharacteristicsCharacteristics Symbol Parameter Condition Min Typ VRST RESET Pin Threshold Voltage 0.2VCC tRST Minimum pulse width on RESET Pin VHYST Brown-out Detector Hysteresis 50 tBOD Min Pulse Width on Brown-out Reset 2 VBG Bandgap reference voltage VCC=2.7V, TA= 25°C 1.0 1.1 tBG Bandgap reference start-up time VCC=2.7V, TA= 25°C 40 IBG Bandgap reference current consumption VCC=2.7V, TA= 25°C 10 Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). Max 0.9VCC 2.5 1.2 70 Units V µs mV µs V µs µA 31.5.1 Standard Power-On Reset This implementation of power-on reset existed in early versions of ATmega640/1280/1281/2560/2561. The table below describes the characteristics of this poweron reset and it is valid for the following devices only: • ATmega640: revision A • ATmega1280: revision A • ATmega1281: revision A • ATmega2560: revision A to E • ATmega2561: revision A to E Table 31-4. Characteristics of Standard Power-On Reset. TA= -40 to +85°C. Symbol VPOT Parameter Power-on Reset Threshold Voltage (rising)(2) Power-on Reset Threshold Voltage (falling)(3) Min.(1) 0.7 0.05 Typ.(1) 1.0 0.9 Max.(1) 1.4 1.3 Units V V VPSR Power-on slope rate 0.01 4.5 V/ms Notes: 1. Values are guidelines only. 2. Threshold where device is released from reset when voltage is rising. 3. The power-on reset threshold voltage (falling) will not work unless the supply voltage has been below VPOT. 2549N–AVR–05/11 372 ATmega640/1280/1281/2560/2561 31.5.2 Enhanced Power-On Reset This implementation of power-on reset exists in newer versions of ATmega640/1280/1281/2560/2561. The table below describes the characteristics of this poweron reset and it is valid for the following devices only: • ATmega640: revision B and newer • ATmega1280: revision B and newer • ATmega1281: revision B and newer • ATmega2560: revision F and newer • ATmega2561: revision F and newer Table 31-5. Characteristics of Enhanced Power-On Reset. TA= -40 to +85°C. Symbol Parameter Min.(1) Typ.(1) Max.(1) Units Power-on Reset Threshold Voltage (rising)(2) 1.1 1.4 1.6 V VPOT Power-on Reset Threshold Voltage (falling)(3) 0.6 1.3 1.6 V VPSR Power-On Slope Rate 0.01 V/ms Notes: 1. Values are guidelines only. 2. Threshold where device is released from reset when voltage is rising. 3. The power-on reset threshold voltage (falling) will not work unless the supply voltage has been below VPOT. Table 31-6. BODLEVEL Fuse Coding(1) BODLEVEL 2:0 Fuses 111 Min VBOT Typ VBOT Max VBOT BOD Disabled Units 110 1.7 1.8 2.0 101 2.5 2.7 2.9 V 100 4.1 4.3 4.5 011 010 Reserved 001 000 Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 for 4MHz operation of ATmega640V/1280V/1281V/2560V/2561V, BODLEVEL = 101 for 8MHz operation of ATmega640V/1280V/1281V/2560V/2561V and ATmega640/1280/1281, and BODLEVEL = 100 for 16MHz operation of ATmega640/1280/1281/2560/2561. 31.6 2-wire Serial Interface Characteristics Table 31-7 on page 374 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega640/1280/1281/2560/2561 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 31-6 on page 375. 2549N–AVR–05/11 373 ATmega640/1280/1281/2560/2561 Table 31-7. 2-wire Serial Bus Requirements Symbol Parameter Condition Min VIL VIH Vhys(1) VOL(1) tr(1) tof(1) tSP(1) Ii Ci(1) fSCL Input Low-voltage Input High-voltage Hysteresis of Schmitt Trigger Inputs Output Low-voltage Rise Time for both SDA and SCL Output Fall Time from VIHmin to VILmax Spikes Suppressed by Input Filter Input Current each I/O Pin Capacitance for each I/O Pin SCL Clock Frequency 3mA sink current 10pF < Cb < 400pF(3) 0.1VCC < Vi < 0.9VCC fCK(4) > max(16fSCL, 250kHz)(5) -0.5 0.7 VCC 0.05 VCC(2) 0 20 + 0.1Cb(3)(2) 20 + 0.1Cb(3)(2) 0 -10 – 0 Rp Value of Pull-up resistor fSCL ≤ 100kHz fSCL > 100kHz V----C----C----–-----0---.--4---V--3mA V----C----C----–-----0---.--4---V--3mA fSCL ≤ 100kHz 4.0 tHD;STA Hold Time (repeated) START Condition fSCL > 100kHz 0.6 tLOW Low Period of the SCL Clock fSCL ≤ 100kHz(6) 4.7 fSCL > 100kHz(7) 1.3 tHIGH High period of the SCL clock fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 tSU;STA Set-up time for a repeated START condition fSCL > 100kHz 0.6 tHD;DAT Data hold time fSCL ≤ 100kHz 0 fSCL > 100kHz 0 tSU;DAT Data setup time fSCL ≤ 100kHz 250 fSCL > 100kHz 100 tSU;STO Setup time for STOP condition fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 tBUF Notes: Bus free time between a STOP and START fSCL ≤ 100kHz 4.7 condition fSCL > 100kHz 1.3 1. In ATmega640/1280/1281/2560/2561, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency. Max 0.3 VCC VCC + 0.5 – 0.4 300 250 50(2) 10 10 400 1----0---0----0---n---s-Cb 3----0---0-----n----sCb – – – – – – – – 3.45 0.9 – – – – – – Units V ns µA pF kHz Ω µs 2549N–AVR–05/11 374 ATmega640/1280/1281/2560/2561 5. This requirement applies to all ATmega640/1280/1281/2560/2561 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz. 7. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still, ATmega640/1280/1281/2560/2561 devices connected to the bus may communicate at full speed (400kHz) with other ATmega640/1280/1281/2560/2561 devices, as well as any other device with a proper tLOW acceptance margin. Figure 31-6. 2-wire Serial Bus Timing tof tHIGH tLOW tLOW SCL SDA tSU;STA tHD;STA tHD;DAT tSU;DAT tr tSU;STO 31.7 SPI Timing Characteristics See Figure 31-7 on page 376 and Figure 31-8 on page 376 for details. Table 31-8. SPI Timing Parameters Description Mode 1 SCK period Master 2 SCK high/low 3 Rise/Fall time 4 Setup 5 Hold 6 Out to SCK 7 SCK to out 8 SCK to out high 9 SS low to out 10 SCK period 11 SCK high/low(1) 12 Rise/Fall time 13 Setup 14 Hold 15 SCK to out 16 SCK to SS high 17 SS high to tri-state 18 SS low to SCK Master Master Master Master Master Master Master Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Min 4 • tck 2 • tck 10 tck 20 20 Typ See Table 21-5 on page 203 50% duty cycle 3.6 10 10 0.5 • tsck 10 10 15 15 10 Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12MHz - 3 tCLCL for fCK > 12MHz tBUF Max ns 1600 2549N–AVR–05/11 375 ATmega640/1280/1281/2560/2561 Figure 31-7. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 45 3 MISO (Data Input) MSB ... 7 LSB 8 MOSI (Data Output) MSB ... LSB Figure 31-8. SPI Interface Timing Requirements (Slave Mode) SS 9 SCK (CPOL = 0) SCK (CPOL = 1) 13 14 MOSI (Data Input) MSB ... 15 MISO (Data Output) MSB ... 10 16 11 11 12 LSB 17 LSB X 2549N–AVR–05/11 376 ATmega640/1280/1281/2560/2561 31.8 ADC Characteristics – Preliminary Data Table 31-9. ADC Characteristics, Singel Ended Channels Symbol Parameter Condition Resolution Single Ended Conversion Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC= 200kHz Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC = 1MHz Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC = 200kHz Noise Reduction Mode Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC = 1MHz Noise Reduction Mode Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset Error Conversion Time Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC = 200kHz Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC = 200kHz Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC= 200kHz Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC = 200kHz Free Running Conversion Clock Frequency Single Ended Conversion AVCC Analog Supply Voltage VREF VIN Reference Voltage Input Voltage Input Bandwidth VINT1 VINT2 RREF RAIN Internal Voltage Reference 1.1V Internal Voltage Reference 2.56V Reference Input Resistance Analog Input Resistance Note: 1. Values are guidelines only. Min(1) 13 50 VCC - 0.3 1.0 GND 1.0 2.4 Typ(1) 10 2.25 3 2 3 1.25 0.5 2 -2 38,5 1.1 2.56 32 100 Max(1) 2.5 260 1000 VCC + 0.3 AVCC VREF 1.2 2.8 Units Bits LSB µs kHz V kHz V kΩ MΩ 2549N–AVR–05/11 377 ATmega640/1280/1281/2560/2561 Table 31-10. ADC Characteristics, Differential Channels Symbol Parameter Condition Gain = 1× Resolution Gain = 10× Gain = 200× Absolute Accuracy(Including INL, DNL, Quantization Error, Gain and Offset Error) Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain = 1× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 10× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 200× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 1× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 10× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 200× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 1× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 10× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 200× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 1× Gain Error Gain = 10× Gain = 200× Offset Error Clock Frequency Gain = 1× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 10× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Gain = 200× VREF = 4V, VCC = 5V CLKADC = 50 - 200kHz Conversion Time Min(1) Typ(1) 8 8 7 18 Max(1) Units Bits 17 9 2.5 5 LSB 9 0.75 1.5 10 1.7 1.7 % 0.5 2 2 LSB 3 50 200 kHz 65 260 µs 2549N–AVR–05/11 378 ATmega640/1280/1281/2560/2561 Table 31-10. ADC Characteristics, Differential Channels (Continued) Symbol Parameter Condition AVCC Analog Supply Voltage VREF VIN VDIFF Reference Voltage Input Voltage Input Differential Voltage ADC Conversion Output Input Bandwidth VINT Internal Voltage Reference RREF Reference Input Resistance RAIN Analog Input Resistance Note: Values are guidelines only. Min(1) VCC - 0.3 2.7 GND -VREF/Gain -511 2.3 Typ(1) 4 2.56 32 100 Max(1) VCC + 0.3 AVCC - 0.5 VCC VREF/Gain 511 2.8 Units V LSB kHz V kΩ MΩ 31.9 External Data Memory Timing Table 31-11. External Data Memory Characteristics, 4.5 to 5.5 Volts, No Wait-state 8MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 1 tLHLL 2 tAVLL 3a tLLAX_ST Oscillator Frequency ALE Pulse Width Address Valid A to ALE Low Address Hold After ALE Low, write access 115 57.5 5 0.0 16 1.0tCLCL-10 0.5tCLCL-5(1) 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 4 tAVLLC Address Valid C to ALE Low 57.5 0.5tCLCL-5(1) 5 tAVRL Address Valid to RD Low 115 1.0tCLCL-10 6 tAVWL 7 tLLWL 8 tLLRL Address Valid to WR Low ALE Low to WR Low ALE Low to RD Low 115 47.5 47.5 67.5 67.5 1.0tCLCL-10 0.5tCLCL-15(2) 0.5tCLCL-15(2) 0.5tCLCL+5(2) 0.5tCLCL+5(2) 9 tDVRH Data Setup to RD High 40 40 10 tRLDV Read Low to Data Valid 75 1.0tCLCL-50 11 tRHDX Data Hold After RD High 0 0 12 tRLRH 13 tDVWL RD Pulse Width Data Setup to WR Low 115 42.5 1.0tCLCL-10 0.5tCLCL-20(1) 14 tWHDX Data Hold After WR High 115 1.0tCLCL-10 15 tDVWH Data Valid to WR High 125 1.0tCLCL 16 tWLWH WR Pulse Width 115 1.0tCLCL-10 Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. Unit MHz ns 2549N–AVR–05/11 379 ATmega640/1280/1281/2560/2561 Table 31-12. External Data Memory Characteristics, 4.5 to 5.5 Volts, 1 Cycle Wait-state 8MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 10 tRLDV 12 tRLRH 15 tDVWH 16 tWLWH Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 0.0 16 200 2.0tCLCL-50 240 2.0tCLCL-10 240 2.0tCLCL 240 2.0tCLCL-10 Unit MHz ns Table 31-13. External Data Memory Characteristics, 4.5 to 5.5 Volts, SRWn1 = 1, SRWn0 = 0 4MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 10 tRLDV 12 tRLRH 15 tDVWH 16 tWLWH Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 0.0 16 325 3.0tCLCL-50 365 3.0tCLCL-10 375 3.0tCLCL 365 3.0tCLCL-10 Unit MHz ns Table 31-14. External Data Memory Characteristics, 4.5 to 5.5 Volts, SRWn1 = 1, SRWn0 = 1 4MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL Oscillator Frequency 0.0 16 10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 14 tWHDX Data Hold After WR High 240 2.0tCLCL-10 15 tDVWH Data Valid to WR High 375 3.0tCLCL 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 Unit MHz ns Table 31-15. External Data Memory Characteristics, 2.7 to 5.5 Volts, No Wait-state 4MHz Oscillator Symbol Parameter Min Max 0 1/tCLCL Oscillator Frequency Variable Oscillator Min Max 0.0 8 Unit MHz 2549N–AVR–05/11 380 ATmega640/1280/1281/2560/2561 Table 31-15. External Data Memory Characteristics, 2.7 to 5.5 Volts, No Wait-state (Continued) 4MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 1 tLHLL ALE Pulse Width 235 2 tAVLL Address Valid A to ALE Low 115 3a tLLAX_ST Address Hold After ALE Low, write access 5 tCLCL-15 0.5tCLCL-10(1) 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 4 tAVLLC Address Valid C to ALE Low 115 0.5tCLCL-10(1) 5 tAVRL Address Valid to RD Low 235 1.0tCLCL-15 6 tAVWL Address Valid to WR Low 235 1.0tCLCL-15 7 tLLWL ALE Low to WR Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) 8 tLLRL ALE Low to RD Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) 9 tDVRH Data Setup to RD High 45 45 10 tRLDV Read Low to Data Valid 190 1.0tCLCL-60 11 tRHDX Data Hold After RD High 0 0 12 tRLRH RD Pulse Width 235 13 tDVWL Data Setup to WR Low 105 1.0tCLCL-15 0.5tCLCL-20(1) 14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 15 tDVWH Data Valid to WR High 250 1.0tCLCL 16 tWLWH WR Pulse Width 235 1.0tCLCL-15 Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. Unit ns Table 31-16. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 0, SRWn0 = 1 4MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 10 tRLDV 12 tRLRH 15 tDVWH 16 tWLWH Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 0.0 8 440 2.0tCLCL-60 485 2.0tCLCL-15 500 2.0tCLCL 485 2.0tCLCL-15 Unit MHz ns 2549N–AVR–05/11 381 ATmega640/1280/1281/2560/2561 Table 31-17. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 1, SRWn0 = 0 4MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 10 tRLDV 12 tRLRH 15 tDVWH 16 tWLWH Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 0.0 8 690 3.0tCLCL-60 735 3.0tCLCL-15 750 3.0tCLCL 735 3.0tCLCL-15 Unit MHz ns Table 31-18. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 1, SRWn0 = 1 4MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL Oscillator Frequency 0.0 8 10 tRLDV Read Low to Data Valid 690 3.0tCLCL-60 12 tRLRH RD Pulse Width 735 3.0tCLCL-15 14 tWHDX Data Hold After WR High 485 2.0tCLCL-15 15 tDVWH Data Valid to WR High 750 3.0tCLCL 16 tWLWH WR Pulse Width 735 3.0tCLCL-15 Figure 31-9. External Memory Timing (SRWn1 = 0, SRWn0 = 0 T1 System Clock (CLKCPU) ALE A15:8 Prev. addr. DA7:0 Prev. data T2 T3 1 4 7 2 3a 13 Address XX Address 15 Data 6 16 WR DA7:0 (XMBK = 0) RD 3b Address 5 8 9 Data 10 12 T4 14 11 Read Write Unit MHz ns 2549N–AVR–05/11 382 ATmega640/1280/1281/2560/2561 Figure 31-10. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 System Clock (CLKCPU) 1 ALE A15:8 Prev. addr. DA7:0 Prev. data 4 7 Address 2 3a 13 Address XX 15 Data 6 16 WR DA7:0 (XMBK = 0) RD 3b Address 5 10 8 9 Data 12 T5 14 11 Write Read Figure 31-11. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 System Clock (CLKCPU) ALE A15:8 Prev. addr. DA7:0 Prev. data WR DA7:0 (XMBK = 0) RD T2 T3 1 4 7 2 3a 13 Address XX 6 3b Address 5 10 8 T4 T5 Address 15 Data 16 9 Data 12 T6 14 11 Write Read 2549N–AVR–05/11 383 ATmega640/1280/1281/2560/2561 Figure 31-12. External Memory Timing (SRWn1 = 1, SRWn0 = 1)() T1 System Clock (CLKCPU) ALE A15:8 Prev. addr. DA7:0 Prev. data WR DA7:0 (XMBK = 0) RD T2 T3 1 4 7 2 3a 13 Address XX 6 3b Address 5 10 8 T4 T5 T6 T7 Address 15 Data 16 9 Data 12 14 11 Write Read The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external). 2549N–AVR–05/11 384 ATmega640/1280/1281/2560/2561 32. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements. Table 32-1 on page 390 and Table 32-2 on page 391 show the additional current consumption compared to ICC Active and ICC Idle for every I/O module controlled by the Power Reduction Register. See “Power Reduction Register” on page 54 for details. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL × VCC × f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 32.1 Active Supply Current Figure 32-1. Active Supply Current vs. frequency (0.1MHz - 1.0MHz) 2.5 ICC (m A) 2 5.5V 5.0V 1.5 4.5V 4.0V 1 3.3V 2.7V 0.5 1.8V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 2549N–AVR–05/11 385 ATmega640/1280/1281/2560/2561 Figure 32-2. Active Supply Current vs. Frequency (1MHz - 16MHz) 25 20 ICC (m A) 15 4.0V 10 3.3V 2.7V 5 1.8V 0 0 2 4 6 8 10 12 14 Frequency (MHz) 5.5V 5.0V 4.5V 16 Figure 32-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 14 85°C 12 25°C -40°C 10 ICC (mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 386 ATmega640/1280/1281/2560/2561 Figure 32-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 2.5 2 -40°C 85°C 25°C 1.5 ICC (mA) 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.7 0.6 -40°C 0.5 ICC (mA) 0.4 25°C 0.3 85°C 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 387 ATmega640/1280/1281/2560/2561 32.2 Idle Supply Current Figure 32-6. Idle Supply Current vs. Low Frequency (0.1MHz - 1.0MHz) 0.6 0.5 0.4 ICC (mA) 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Frequency (MHz) 5.5V 5.0V 4.5V 4.0V 3.3V 2.7V 1.8V 1 Figure 32-7. Idle Supply Current vs. Frequency (1MHz - 16MHz) ICC (m A) 8 7 6 5 4 4.0V 3 2 3.3V 1 2.7V 1.8V 0 0 2 4 6 8 10 12 14 Frequency (MHz) 5.5V 5.0V 4.5V 16 2549N–AVR–05/11 388 ATmega640/1280/1281/2560/2561 Figure 32-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 3.5 3 2.5 ICC (mA) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 VCC (V) 85°C 25°C -40°C 5.5 Figure 32-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) ICC (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 VCC (V) -40°C 85°C 25°C 5.5 2549N–AVR–05/11 389 ATmega640/1280/1281/2560/2561 Figure 32-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)I 0.3 0.25 -40°C 0.2 ICC (mA) 0.15 25°C 85°C 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 32.2.1 Supply Current of IO modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See “Power Reduction Register” on page 54 for details. Table 32-1. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers PRUSART3 VCC = 2V, F = 1MHz 8.0µA VCC = 3V, F = 4MHz 51µA VCC = 5V, F = 8MHz 220µA PRUSART2 8.0µA 51µA 220µA PRUSART1 8.0µA 51µA 220µA PRUSART0 8.0µA 51µA 220µA PRTWI 12µA 75µA 315µA PRTIM5 6.0µA 39µA 150µA PRTIM4 6.0µA 39µA 150µA PRTIM3 6.0µA 39µA 150µA PRTIM2 11µA 72µA 300µA PRTIM1 6.0µA 39µA 150µA PRTIM0 4.0µA 24µA 100µA PRSPI 15µA 95µA 400µA PRADC 12µA 75µA 315µA 2549N–AVR–05/11 390 ATmega640/1280/1281/2560/2561 32.2.1.1 Table 32-2. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock Additional Current consumption compared to Idle with external clock PRUSART3 3.0% 17% PRUSART2 3.0% 17% PRUSART1 3.0% 17% PRUSART0 3.0% 17% PRTWI 4.4% 24% PRTIM5 1.8% 10% PRTIM4 1.8% 10% PRTIM3 1.8% 10% PRTIM2 4.3% 23% PRTIM1 1.8% 10% PRTIM0 1.5% 8.0% PRSPI 3.3% 18% PRADC 4.5% 24% It is possible to calculate the typical current consumption based on the numbers from Table 32-1 on page 390 for other VCC and frequency settings than listed in Table 32-2. Example 1 Calculate the expected current consumption in idle mode with USART0, TIMER1, and TWI enabled at VCC = 2.0V and F = 1MHz. From Table 32-2, third column, we see that we need to add 17% for the USART0, 24% for the TWI, and 10% for the TIMER1 module. Reading from Fig- ure 32-6 on page 388, we find that the idle current consumption is ~0.15mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with USART0, TIMER1, and TWI enabled, gives: ICCtotal ≈ 0.15mA • (1 + 0.17 + 0.24 + 0.10) ≈ 0.227mA 2549N–AVR–05/11 391 ATmega640/1280/1281/2560/2561 32.3 Power-down Supply Current Figure 32-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 4 85°C 3.5 3 2.5 ICC (µA) 2 1.5 1 -40°C 25°C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 12 85°C 10 -40°C 8 25°C ICC (µA) 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 392 ATmega640/1280/1281/2560/2561 32.4 Power-save Supply Current Figure 32-13. Power-save Supply Current vs. VCgC (Watchdog Timer Disabled) 11 10 9 ICC(uA) 8 7 6 5 4 1.5 2 2.5 3 3.5 4 4.5 5 VCC (V) 25°C 5.5 Figure 32-14. Power-save Supply Current vs. VCC (Watchdog Timer Enabled) ICC (µA) 9 8 25°C 7 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 393 ATmega640/1280/1281/2560/2561 32.5 Standby Supply Current Figure 32-15. Standby Supply Current vs. VCC (Watchdog Timer Disabled) ICC (mA) 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 VCC (V) 6MHz xtal 6MHz res 4MHz res 4MHz xtal 2MHz res 2MHz xtal 1MHz res 455kHz res 32kHz xtal 5.5 32.6 Pin Pull-up Figure 32-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 40 IOP (µA) 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) 25°C 85°C -40°C 2 2549N–AVR–05/11 394 ATmega640/1280/1281/2560/2561 Figure 32-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) IOP (µA) 90 80 70 60 50 40 30 20 85°C 10 25°C 0 -40°C 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 32-18. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 100 IOP (µA) 80 60 40 20 0 0 1 2 3 4 5 VOP (V) 25°C 85°C -40°C 6 2549N–AVR–05/11 395 ATmega640/1280/1281/2560/2561 Figure 32-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 30 25 IRESET (µA) 20 15 10 5 25°C -40°C 0 85°C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 32-20. Reset pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 70 60 50 IRESET (µA) 40 30 20 10 25°C -40°C 0 85°C 0 0.5 1 1.5 2 2.5 3 VRESET (V) 2549N–AVR–05/11 396 ATmega640/1280/1281/2560/2561 Figure 32-21. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 80 IRESET (µA) 60 40 20 25°C -40°C 0 85°C 0 1 2 3 4 5 6 VRESET (V) 32.7 Pin Driver Strength Figure 32-22. I/O Pin output Voltage vs.Sink Current (VCC = 3V) VOL (V) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 85°C 25°C -40°C 5 10 15 20 25 IOL (mA) 2549N–AVR–05/11 397 ATmega640/1280/1281/2560/2561 Figure 32-23. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 85°C 0.5 25°C 0.4 -40°C VOL (V) 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (mA) Figure 32-24. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 VOH(V) 2.5 -40°C 25°C 2 85°C 1.5 1 0.5 0 0 5 10 15 20 25 IOH (mA) 2549N–AVR–05/11 398 ATmega640/1280/1281/2560/2561 Figure 32-25. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5.1 5 4.9 4.8 VOH(V) 4.7 4.6 4.5 4.4 4.3 0 -40°C 25°C 85°C 5 10 15 20 25 IOH (mA) 32.8 Pin Threshold and Hysteresis Figure 32-26. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as “1“) 3.5 -40°C 3 25°C 85°C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 399 ATmega640/1280/1281/2560/2561 Figure 32-27. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as “0“) 2.5 85°C 25°C -40°C 2 Threshold (V) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-28. I/O Pin Input Hysteresis Input Hysteresis (mV) 0.8 0.7 -40°C 0.6 0.5 25°C 0.4 85°C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 400 ATmega640/1280/1281/2560/2561 Figure 32-29. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as “1“) 2.5 -40°C 25°C 85°C 2 Threshold (V) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-30. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as “0“) 2.5 85°C 25°C -40°C 2 Threshold (V) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 401 ATmega640/1280/1281/2560/2561 Figure 32-31. Reset Pin Input Hysteresis vs. VCC 0.7 0.6 Input Hysteresis(mV) 0.5 0.4 0.3 0.2 0.1 -40°C 25°C 0 85°C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 32.9 BOD Threshold and Analog Comparator Offset Figure 32-32. BOD Threshold vs. Temperature (BOD Level is 4.3V) 4.4 4.35 Rising Vcc 4.3 Threshold (V) 4.25 Falling Vcc 4.2 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) 2549N–AVR–05/11 402 ATmega640/1280/1281/2560/2561 Figure 32-33. BOD Threshold vs. Temperature (BOD Level is 2.7V) 2.8 Rising Vcc 2.75 Threshold (V) 2.7 Falling Vcc 2.65 2.6 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 32-34. BOD Threshold vs. Temperature (BOD Level is 1.8V) 1.9 T hre shold ( V ) 1.85 Rising Vcc 1.8 Fallling Vcc 1.75 1.7 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) 2549N–AVR–05/11 403 ATmega640/1280/1281/2560/2561 32.10 Internal Oscillator Speed Figure 32-35. Watchdog Oscillator Frequency vs. VCC 128 126 -40°C 124 122 25°C FRC (kHz) 120 118 116 85°C 114 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-36. Watchdog Oscillator Frequency vs. Temperature FRC (kHz) 128 126 124 122 120 118 116 114 -60 -40 -20 0 20 40 60 Temperature (°C) 2.1V 2.7V 3.3V 4.0V 5.5V 80 100 2549N–AVR–05/11 404 ATmega640/1280/1281/2560/2561 Figure 32-37. Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.3 85°C 8.2 8.1 25°C 8 FRC (MHz) 7.9 -40°C 7.8 7.7 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-38. Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.5 5.0V 8.4 3.0V 8.3 FRC (MHz) 8.2 8.1 8 7.9 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) 2549N–AVR–05/11 405 ATmega640/1280/1281/2560/2561 Figure 32-39. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value FRC (MHz) 16 85°C 25°C 14 -40°C 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 32.11 Current Consumption of Peripheral Units Figure 32-40. Brownout Detector Current vs. VCC 30 85°C 25 25°C -40°C 20 ICC (µA) 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 406 ATmega640/1280/1281/2560/2561 Figure 32-41. ADC Current vs. VCC (AREF = AVCC) 350 300 -40°C 25°C 85°C 250 ICC (µA) 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-42. AREF External Reference Current vs. VCC 250 200 150 -40°C 25°C 85°C ICC (µA) 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 407 ATmega640/1280/1281/2560/2561 Figure 32-43. Watchdog Timer Current vs. VCC ICC (µA) 9 -40°C 8 25°C 7 85°C 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-44. Analog Comparator Current vs. VCC ICC (µA) 100 90 -40°C 80 25°C 85°C 70 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 408 ATmega640/1280/1281/2560/2561 Figure 32-45. Programming Current vs. VCC ICC (mA) 16 14 -40°C 12 10 25°C 8 85°C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 32.12 Current Consumption in Reset and Reset Pulsewidth Figure 32-46. Reset Supply Current vs VCC (0.1MHz - 1.0MHz, Excluding Current Through The Reset Pull-up) ICC (m A) 0.35 5.5V 0.3 5.0V 0.25 4.5V 0.2 4.0V 0.15 3.3V 0.1 2.7V 0.05 1.8V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 2549N–AVR–05/11 409 ATmega640/1280/1281/2560/2561 Figure 32-47. Reset Supply Current vs. VCC (1MHz - 16MHz, Excluding Current Through The Reset Pull-up) ICC (m A) 4 3.5 5.5V 5.0V 3 4.5V 2.5 2 4.0V 1.5 1 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 32-48. Minimum Reset Pulse Width vs. VCC 2500 2000 Pu lsewidth (ns) 1500 1000 500 85°C 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2549N–AVR–05/11 410 ATmega640/1280/1281/2560/2561 33. Register Summary Address (0x1FF) ... (0x13F) (0x13E) (0x13D) (0x13C) (0x13B) (0x13A) (0x139) (0x138) (0x137) (0x136) (0x135) (0x134) (0x133) (0x132) (0x131) (0x130) (0x12F) (0x12E) (0x12D) (0x12C) (0x12B) (0x12A) (0x129) (0x128) (0x127) (0x126) (0x125) (0x124) (0x123) (0x122) (0x121) (0x120) (0x11F) (0x11E) (0x11D) (0x11C) (0x11B) (0x11A) (0x119) (0x118) (0x117) (0x116) (0x115) (0x114) (0x113) (0x112) (0x111) (0x110) (0x10F) (0x10E) (0x10D) (0x10C) (0x10B) (0x10A) (0x109) (0x108) (0x107) (0x106) (0x105) (0x104) (0x103) (0x102) (0x101) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR3 UBRR3H UBRR3L Reserved UCSR3C UCSR3B UCSR3A Reserved Reserved OCR5CH OCR5CL OCR5BH OCR5BL OCR5AH OCR5AL ICR5H ICR5L TCNT5H TCNT5L Reserved TCCR5C TCCR5B TCCR5A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTL DDRL PINL PORTK DDRK PINK PORTJ DDRJ PINJ PORTH DDRH Bit 7 - - UMSEL31 RXCIE3 RXC3 - FOC5A ICNC5 COM5A1 PORTL7 DDL7 PINL7 PORTK7 DDK7 PINK7 PORTJ7 DDJ7 PINJ7 PORTH7 DDH7 Bit 6 - - UMSEL30 TXCIE3 TXC3 - FOC5B ICES5 COM5A0 PORTL6 DDL6 PINL6 PORTK6 DDK6 PINK6 PORTJ6 DDJ6 PINJ6 PORTH6 DDH6 Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 - USART3 I/O Data Register - - USART3 Baud Rate Register High Byte USART3 Baud Rate Register Low Byte - - - - - - UPM31 UPM30 USBS3 UCSZ31 UCSZ30 UCPOL3 UDRIE3 RXEN3 TXEN3 UCSZ32 RXB83 TXB83 UDRE3 FE3 DOR3 UPE3 U2X3 MPCM3 - - - - - - - - - - - - Timer/Counter5 - Output Compare Register C High Byte Timer/Counter5 - Output Compare Register C Low Byte Timer/Counter5 - Output Compare Register B High Byte Timer/Counter5 - Output Compare Register B Low Byte Timer/Counter5 - Output Compare Register A High Byte Timer/Counter5 - Output Compare Register A Low Byte Timer/Counter5 - Input Capture Register High Byte Timer/Counter5 - Input Capture Register Low Byte Timer/Counter5 - Counter Register High Byte Timer/Counter5 - Counter Register Low Byte - - - - - - FOC5C - - - - - - WGM53 WGM52 CS52 CS51 CS50 COM5B1 COM5B0 COM5C1 COM5C0 WGM51 WGM50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTL5 PORTL4 PORTL3 PORTL2 PORTL1 PORTL0 DDL5 DDL4 DDL3 DDL2 DDL1 DDL0 PINL5 PINL4 PINL3 PINL2 PINL1 PINL0 PORTK5 PORTK4 PORTK3 PORTK2 PORTK1 PORTK0 DDK5 DDK4 DDK3 DDK2 DDK1 DDK0 PINK5 PINK4 PINK3 PINK2 PINK1 PINK0 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 2549N–AVR–05/11 Page 222 227 227 239 238 238 165 165 165 165 164 164 165 165 163 163 162 160 158 104 104 104 103 103 103 103 103 103 102 103 411 ATmega640/1280/1281/2560/2561 Address (0x100) (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) Name PINH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR2 UBRR2H UBRR2L Reserved UCSR2C UCSR2B UCSR2A Reserved UDR1 UBRR1H UBRR1L Reserved UCSR1C UCSR1B UCSR1A Reserved UDR0 UBRR0H UBRR0L Reserved UCSR0C UCSR0B UCSR0A Reserved Bit 7 PINH7 - - UMSEL21 RXCIE2 RXC2 - - UMSEL11 RXCIE1 RXC1 - - UMSEL01 RXCIE0 RXC0 - Bit 6 PINH6 - - UMSEL20 TXCIE2 TXC2 - - UMSEL10 TXCIE1 TXC1 - - UMSEL00 TXCIE0 TXC0 - Bit 5 PINH5 - - UPM21 UDRIE2 UDRE2 - - UPM11 UDRIE1 UDRE1 - - UPM01 UDRIE0 UDRE0 - Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PINH4 PINH3 PINH2 PINH1 PINH0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - USART2 I/O Data Register - USART2 Baud Rate Register High Byte USART2 Baud Rate Register Low Byte - - - - - UPM20 USBS2 UCSZ21 UCSZ20 UCPOL2 RXEN2 TXEN2 UCSZ22 RXB82 TXB82 FE2 DOR2 UPE2 U2X2 MPCM2 - - - - - USART1 I/O Data Register - USART1 Baud Rate Register High Byte USART1 Baud Rate Register Low Byte - - - - - UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 FE1 DOR1 UPE1 U2X1 MPCM1 - - - - - USART0 I/O Data Register - USART0 Baud Rate Register High Byte USART0 Baud Rate Register Low Byte - - - - - UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 FE0 DOR0 UPE0 U2X0 MPCM0 - - - - - 2549N–AVR–05/11 Page 103 222 227 227 239 238 238 222 227 227 239 238 238 222 227 227 239 238 238 412 ATmega640/1280/1281/2560/2561 Address (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) Name Reserved TWAMR TWCR TWDR TWAR TWSR TWBR Reserved ASSR Reserved OCR2B OCR2A TCNT2 TCCR2B TCCR2A Reserved Reserved OCR4CH OCR4CL OCR4BH OCR4BL OCR4AH OCR4AL ICR4H ICR4L TCNT4H TCNT4L Reserved TCCR4C TCCR4B TCCR4A Reserved Reserved OCR3CH OCR3CL OCR3BH OCR3BL OCR3AH OCR3AL ICR3H ICR3L TCNT3H TCNT3L Reserved TCCR3C TCCR3B TCCR3A Reserved Reserved OCR1CH OCR1CL OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 DIDR2 Bit 7 TWAM6 TWINT TWA6 TWS7 - FOC2A COM2A1 - FOC4A ICNC4 COM4A1 - FOC3A ICNC3 COM3A1 - FOC1A ICNC1 COM1A1 ADC7D ADC15D Bit 6 TWAM5 TWEA TWA5 TWS6 EXCLK - FOC2B COM2A0 - FOC4B ICES4 COM4A0 - FOC3B ICES3 COM3A0 - FOC1B ICES1 COM1A0 ADC6D ADC14D Bit 5 Bit 4 Bit 3 Bit 2 - - - - TWAM4 TWAM3 TWAM2 TWAM1 TWSTA TWSTO TWWC TWEN 2-wire Serial Interface Data Register TWA4 TWA3 TWA2 TWA1 TWS5 TWS4 TWS3 - 2-wire Serial Interface Bit Rate Register - - - - AS2 TCN2UB OCR2AUB OCR2BUB - - - - Timer/Counter2 Output Compare Register B Timer/Counter2 Output Compare Register A Timer/Counter2 (8 Bit) - - WGM22 CS22 COM2B1 COM2B0 - - - - - - - - - - Timer/Counter4 - Output Compare Register C High Byte Timer/Counter4 - Output Compare Register C Low Byte Timer/Counter4 - Output Compare Register B High Byte Timer/Counter4 - Output Compare Register B Low Byte Timer/Counter4 - Output Compare Register A High Byte Timer/Counter4 - Output Compare Register A Low Byte Timer/Counter4 - Input Capture Register High Byte Timer/Counter4 - Input Capture Register Low Byte Timer/Counter4 - Counter Register High Byte Timer/Counter4 - Counter Register Low Byte - - - - FOC4C - - - - WGM43 WGM42 CS42 COM4B1 COM4B0 COM4C1 COM4C0 - - - - - - - - Timer/Counter3 - Output Compare Register C High Byte Timer/Counter3 - Output Compare Register C Low Byte Timer/Counter3 - Output Compare Register B High Byte Timer/Counter3 - Output Compare Register B Low Byte Timer/Counter3 - Output Compare Register A High Byte Timer/Counter3 - Output Compare Register A Low Byte Timer/Counter3 - Input Capture Register High Byte Timer/Counter3 - Input Capture Register Low Byte Timer/Counter3 - Counter Register High Byte Timer/Counter3 - Counter Register Low Byte - - - - FOC3C - - - - WGM33 WGM32 CS32 COM3B1 COM3B0 COM3C1 COM3C0 - - - - - - - - Timer/Counter1 - Output Compare Register C High Byte Timer/Counter1 - Output Compare Register C Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte - - - - FOC1C - - - - WGM13 WGM12 CS12 COM1B1 COM1B0 COM1C1 COM1C0 - - - - ADC5D ADC4D ADC3D ADC2D ADC13D ADC12D ADC11D ADC10D Bit 1 TWAM0 TWA0 TWPS1 TCR2AUB - CS21 WGM21 - CS41 WGM41 - CS31 WGM31 - CS11 WGM11 AIN1D ADC1D ADC9D Bit 0 TWIE TWGCE TWPS0 TCR2BUB - CS20 WGM20 - CS40 WGM40 - CS30 WGM30 - CS10 WGM10 AIN0D ADC0D ADC8D 2549N–AVR–05/11 Page 269 266 268 269 268 266 184 191 191 191 190 191 164 164 164 164 164 164 165 165 163 163 162 160 158 164 164 164 164 163 163 165 165 162 162 162 160 158 163 163 163 163 163 163 165 165 162 162 161 160 158 274 295 295 413 ATmega640/1280/1281/2560/2561 Address (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) Name ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved XMCRB XMCRA TIMSK5 TIMSK4 TIMSK3 TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 EICRB EICRA PCICR Reserved OSCCAL PRR1 PRR0 Reserved Reserved CLKPR WDTCSR SREG SPH SPL EIND RAMPZ Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR PCIFR Bit 7 REFS1 - ADEN XMBK SRE PCINT23 PCINT15 PCINT7 ISC71 ISC31 - PRTWI CLKPCE WDIF I SP15 SP7 SPMIE JTD OCDR7 ACD - SPIF SPIE - FOC0A COM0A1 TSM - - INT7 INTF7 - Bit 6 REFS0 ACME ADSC SRL2 PCINT22 PCINT14 PCINT6 ISC70 ISC30 - PRTIM2 WDIE T SP14 SP6 RWWSB OCDR6 ACBG - WCOL SPE - FOC0B COM0A0 - - INT6 INTF6 - Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 - - MUX5 ADTS2 ADTS1 ADTS0 ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADC Data Register High byte ADC Data Register Low byte - - - - - - - - - - - - - - - XMM2 XMM1 XMM0 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 ICIE5 - OCIE5C OCIE5B OCIE5A TOIE5 ICIE4 - OCIE4C OCIE4B OCIE4A TOIE4 ICIE3 - OCIE3C OCIE3B OCIE3A TOIE3 - - - OCIE2B OCIE2A TOIE2 ICIE1 - OCIE1C OCIE1B OCIE1A TOIE1 - - - OCIE0B OCIE0A TOIE0 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 - - - PCIE2 PCIE1 PCIE0 - - - - - - Oscillator Calibration Register PRTIM5 PRTIM4 PRTIM3 PRUSART3 PRUSART2 PRUSART1 PRTIM0 - PRTIM1 PRSPI PRUSART0 PRADC - - - - - - - - - - - - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 WDP3 WDCE WDE WDP2 WDP1 WDP0 H S V N Z C SP13 SP12 SP11 SP10 SP9 SP8 SP5 SP4 SP3 SP2 SP1 SP0 - - - - - EIND0 - - - - RAMPZ1 RAMPZ0 - - - - - - - - - - - - - - - - - - SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN - - - - - - - PUD - - IVSEL IVCE - JTRF WDRF BORF EXTRF PORF - - SM2 SM1 SM0 SE - - - - - - OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 ACO ACI ACIE ACIC ACIS1 ACIS0 - - - - - - SPI Data Register - - - - - SPI2X DORD MSTR CPOL CPHA SPR1 SPR0 General Purpose I/O Register 2 General Purpose I/O Register 1 - - - - - - Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) - - WGM02 CS02 CS01 CS00 COM0B1 COM0B0 - - WGM01 WGM00 - - - - PSRASY PSRSYNC - - EEPROM Address Register High Byte EEPROM Address Register Low Byte EEPROM Data Register EEPM1 EEPM0 EERIE EEMPE EEPE EERE General Purpose I/O Register 0 INT5 INT4 INT3 INT2 INT1 INT0 INTF5 INTF4 INTF3 INTF2 INTF1 INTF0 - - - PCIF2 PCIF1 PCIF0 Page 289 272, 290, 294 292 294 294 38 37 166 166 166 193 166 134 116 116 117 114 113 115 50 57 56 50 67 14 16 16 17 17 332 67, 110, 100, 308 308 52 301 272 204 203 202 37 37 133 133 133 132 129 170, 194 35 35 35 35 37 115 115 116 2549N–AVR–05/11 414 ATmega640/1280/1281/2560/2561 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1A (0x3A) TIFR5 - - ICF5 - OCF5C OCF5B OCF5A TOV5 166 0x19 (0x39) TIFR4 - - ICF4 - OCF4C OCF4B OCF4A TOV4 167 0x18 (0x38) TIFR3 - - ICF3 - OCF3C OCF3B OCF3A TOV3 167 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 193 0x16 (0x36) TIFR1 - - ICF1 - OCF1C OCF1B OCF1A TOV1 167 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 134 0x14 (0x34) PORTG - - PORTG5 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 102 0x13 (0x33) DDRG - - DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 102 0x12 (0x32) PING - - PING5 PING4 PING3 PING2 PING1 PING0 102 0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 101 0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 102 0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 102 0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 101 0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 101 0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 102 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 101 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 101 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 101 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 101 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 101 0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 101 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 100 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 100 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 100 0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 100 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 100 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 100 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 2549N–AVR–05/11 415 ATmega640/1280/1281/2560/2561 34. Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. SBIW Rdl,K Subtract Immediate from Word AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One’s Complement NEG Rd Two’s Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register MUL Rd, Rr Multiply Unsigned MULS Rd, Rr Multiply Signed MULSU Rd, Rr Multiply Signed with Unsigned FMUL Rd, Rr Fractional Multiply Unsigned FMULS Rd, Rr Fractional Multiply Signed FMULSU Rd, Rr Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP Indirect Jump to (Z) EIJMP Extended Indirect Jump to (Z) JMP k Direct Jump RCALL k Relative Subroutine Call ICALL Indirect Call to (Z) EICALL Extended Indirect Call to (Z) CALL k Direct Subroutine Call RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared 2549N–AVR–05/11 Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 PC ← PC + k + 1 PC ← Z PC ←(EIND:Z) PC ← k PC ← PC + k + 1 PC ← Z PC ←(EIND:Z) PC ← k PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 Flags Z, C, N, V, H Z, C, N, V, H Z, C, N, V, S Z, C, N, V, H Z, C, N, V, H Z, C, N, V, H Z, C, N, V, H Z, C, N, V, S Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V Z, C, N, V Z, C, N, V, H Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V None Z, C Z, C Z, C Z, C Z, C Z, C None None None None None None None None None I None Z, N, V, C, H Z, N, V, C, H Z, N, V, C, H None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 4 4 4 5 5 5 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 416 ATmega640/1280/1281/2560/2561 Mnemonics Operands BRVS k BRVC k BRIE k BRID k BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV Rd, Rr MOVW Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LPM LPM Rd, Z LPM Rd, Z+ ELPM ELPM Rd, Z Description Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Extended Load Program Memory Extended Load Program Memory 2549N–AVR–05/11 Operation if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X), X ← X + 1 X ← X - 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y - 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 R0 ← (RAMPZ:Z) Rd ← (RAMPZ:Z) Flags None None None None None None Z, C, N, V Z, C, N, V Z, C, N, V Z, C, N, V Z, C, N, V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1/2 1/2 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 417 ATmega640/1280/1281/2560/2561 Mnemonics Operands Description Operation ELPM Rd, Z+ SPM IN Rd, P OUT P, Rr PUSH Rr POP Rd MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK Extended Load Program Memory Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1 (Z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Rd ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Note: EICALL and EIJMP do not exist in ATmega640/1280/1281. ELPM does not exist in ATmega640. Flags None None None None None None None None None None #Clocks 3 1 1 2 2 1 1 1 N/A 2549N–AVR–05/11 418 ATmega640/1280/1281/2560/2561 35. Ordering Information 35.1 ATmega640 Speed (MHz)(2) Power Supply 8 1.8 - 5.5V 16 2.7 - 5.5V Ordering Code ATmega640V-8AU ATmega640V-8AUR(4) ATmega640V-8CU ATmega640V-8CUR(4) ATmega640-16AU ATmega640-16AUR(4) ATmega640-16CU ATmega640-16CUR(4) Package(1)(3) 100A 100A 100C1 100C1 100A 100A 100C1 100C1 Operation Range Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Speed Grades” on page 369. 3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 4. Tape & Reel 100A 100C1 Package Type 100-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 100-ball, Chip Ball Grid Array (CBGA) 2549N–AVR–05/11 419 ATmega640/1280/1281/2560/2561 35.2 ATmega1280 Speed (MHz)(2) Power Supply 8 1.8V - 5.5V 16 2.7V - 5.5V Ordering Code ATmega1280V-8AU ATmega1280V-8AUR(4) ATmega1280V-8CU ATmega1280V-8CUR(4) ATmega1280-16AU ATmega1280-16AUR(4) ATmega1280-16CU ATmega1280-16CUR(4) Package(1)(3) 100A 100A 100C1 100C1 100A 100A 100C1 100C1 Operation Range Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Speed Grades” on page 369. 3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 4. Tape & Reel 100A 100C1 Package Type 100-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 100-ball, Chip Ball Grid Array (CBGA) 2549N–AVR–05/11 420 ATmega640/1280/1281/2560/2561 35.3 ATmega1281 Speed (MHz)(2) Power Supply 8 1.8 - 5.5V 16 2.7 - 5.5V Ordering Code ATmega1281V-8AU ATmega1281V-8AUR(4) ATmega1281V-8MU ATmega1281V-8MUR(4) ATmega1281-16AU ATmega1281-16AUR(4) ATmega1281-16MU ATmega1281-16MUR(4) Package(1)(3) 64A 64A 64M2 64M2 64A 64A 64M2 64M2 Operation Range Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Speed Grades” on page 369. 3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 4. Tape & Reel 64A 64M2 Package Type 64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, 9mm × 9mm × 1.0mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 2549N–AVR–05/11 421 ATmega640/1280/1281/2560/2561 35.4 ATmega2560 Speed (MHz)(2) Power Supply 8 1.8V - 5.5V 16 4.5V - 5.5V Ordering Code ATmega2560V-8AU ATmega2560V-8AUR(4) ATmega2560V-8CU ATmega2560V-8CUR(4) ATmega2560-16AU ATmega2560-16AUR(4) ATmega2560-16CU ATmega2560-16CUR(4) Package(1)(3) 100A 100A 100C1 100C1 100A 100A 100C1 100C1 Operation Range Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Speed Grades” on page 369. 3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 4. Tape & Reel 100A 100C1 Package Type 100-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 100-ball, Chip Ball Grid Array (CBGA) 2549N–AVR–05/11 422 ATmega640/1280/1281/2560/2561 35.5 ATmega2561 Speed (MHz)(2) Power Supply 8 1.8V - 5.5V 16 4.5V - 5.5V Ordering Code ATmega1281V-8AU ATmega1281V-8AUR(4) ATmega1281V-8MU ATmega1281V-8MUR(4) ATmega1281-16AU ATmega1281-16AUR(4) ATmega1281-16MU ATmega1281-16MUR(4) Package(1)(3) 64A 64A 64M2 64M2 64A 64A 64M2 64M2 Operation Range Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Speed Grades” on page 369. 3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 4. Tape & Reel 64A 64M2 Package Type 64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, 9mm × 9mm × 1.0mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 2549N–AVR–05/11 423 36. Packaging Information 36.1 100A ATmega640/1280/1281/2560/2561 PIN 1 e PIN 1 IDENTIFIER B E1 E D1 D C 0°~7° A1 A2 L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.05 A2 0.95 D 15.75 D1 13.90 E 15.75 E1 13.90 B 0.17 C 0.09 L 0.45 e NOM MAX – 1.20 – 0.15 1.00 1.05 16.00 16.25 14.00 14.10 16.00 16.25 14.00 14.10 – 0.27 – 0.20 – 0.75 0.50 TYP NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 TITLE 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 2010-10-20 DRAWING NO. REV. 100A D 2549N–AVR–05/11 424 36.2 100C1 ATmega640/1280/1281/2560/2561 E Marked A1 Identifier D 0.12 Z SIDE VIEW TOP VIEW Øb e 0.90 TYP 0.90 TYP e 10 9 8 7 6 5 4 3 2 1 A B C D E F G H I J E1 A1 Corner D1 BOTTOM VIEW A A1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 D E D1 E1 Øb e MIN 1.10 0.30 8.90 8.90 7.10 7.10 0.35 NOM – 0.35 9.00 9.00 7.20 7.20 0.40 0.80 TYP MAX 1.20 0.40 9.10 9.10 7.30 7.30 0.45 NOTE TITLE 2325 Orchard Parkway 100C1, 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.80 mm R San Jose, CA 95131 Chip Array BGA Package (CBGA) 5/25/06 DRAWING NO. REV. 100C1 A 2549N–AVR–05/11 425 36.3 64A ATmega640/1280/1281/2560/2561 PIN 1 e PIN 1 IDENTIFIER B E1 E D1 D C 0°~7° A1 A2 L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.05 A2 0.95 D 15.75 D1 13.90 E 15.75 E1 13.90 B 0.30 C 0.09 L 0.45 e NOM MAX – 1.20 – 0.15 1.00 1.05 16.00 16.25 14.00 14.10 16.00 16.25 14.00 14.10 – 0.45 – 0.20 – 0.75 0.80 TYP NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 2010-10-20 DRAWING NO. REV. 64A C 2549N–AVR–05/11 426 36.4 64M2 ATmega640/1280/1281/2560/2561 D Marked Pin# 1 ID E TOP VIEW K L D2 Pin #1 Corner C SEATING PLANE A1 A3 A 0.08 C SIDE VIEW 1 Option A Pin #1 2 Triangle 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 K b e BOTTOM VIEW Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch (0.20 R) Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. SYMBOL A A1 A3 b D D2 E E2 e L K MIN 0.80 – 0.18 8.90 7.50 8.90 7.50 0.35 0.20 TITLE 2325 Orchard Parkway 64M2, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, R San Jose, CA 95131 7.65 mm Exposed Pad, Micro Lead Frame Package (MLF) NOM MAX 0.90 1.00 0.02 0.05 0.20 REF 0.25 0.30 9.00 9.10 7.65 7.80 9.00 9.10 7.65 7.80 0.50 BSC 0.40 0.27 0.45 0.40 NOTE 2010-10-20 DRAWING NO. REV. 64M2 E 2549N–AVR–05/11 427 ATmega640/1280/1281/2560/2561 37. Errata 37.1 ATmega640 rev. B • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.2 ATmega640 rev. A • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.3 ATmega1280 rev. B • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. 2549N–AVR–05/11 428 ATmega640/1280/1281/2560/2561 Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.4 ATmega1280 rev. A • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.5 ATmega1281 rev. B • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 2549N–AVR–05/11 429 ATmega640/1280/1281/2560/2561 37.6 ATmega1281 rev. A • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.7 ATmega2560 rev. F Not sampled. 37.8 ATmega2560 rev. E No known errata. 37.9 ATmega2560 rev. D Not sampled. 37.10 ATmega2560 rev. C • High current consumption in sleep mode 1. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.11 ATmega2560 rev. B Not sampled. 2549N–AVR–05/11 430 ATmega640/1280/1281/2560/2561 37.12 ATmega2560 rev. A • Non-Read-While-Write area of flash not functional • Part does not work under 2.4 volts • Incorrect ADC reading in differential mode • Internal ADC reference has too low value • IN/OUT instructions may be executed twice when Stack is in external RAM • EEPROM read from application code does not work in Lock Bit Mode 3 1. Non-Read-While-Write area of flash not functional The Non-Read-While-Write area of the flash is not working as expected. The problem is related to the speed of the part when reading the flash of this area. Problem Fix/Workaround - Only use the first 248K of the flash. - If boot functionality is needed, run the code in the Non-Read-While-Write area at maximum 1/4th of the maximum frequency of the device at any given voltage. This is done by writing the CLKPR register before entering the boot section of the code. 2. Part does not work under 2.4 volts The part does not execute code correctly below 2.4 volts. Problem Fix/Workaround Do not use the part at voltages below 2.4 volts. 3. Incorrect ADC reading in differential mode The ADC has high noise in differential mode. It can give up to 7 LSB error. Problem Fix/Workaround Use only the 7 MSB of the result when using the ADC in differential mode. 4. Internal ADC reference has too low value The internal ADC reference has a value lower than specified. Problem Fix/Workaround - Use AVCC or external reference. - The actual value of the reference can be measured by applying a known voltage to the ADC when using the internal reference. The result when doing later conversions can then be calibrated. 5. IN/OUT instructions may be executed twice when Stack is in external RAM If either an IN or an OUT instruction is executed directly before an interrupt occurs and the stack pointer is located in external ram, the instruction will be executed twice. In some cases this will cause a problem, for example: - If reading SREG it will appear that the I-flag is cleared. - If writing to the PIN registers, the port will toggle twice. - If reading registers with interrupt flags, the flags will appear to be cleared. 2549N–AVR–05/11 431 ATmega640/1280/1281/2560/2561 Problem Fix/Workaround There are two application work-arounds, where selecting one of them, will be omitting the issue: - Replace IN and OUT with LD/LDS/LDD and ST/STS/STD instructions. - Use internal RAM for stack pointer. 6. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 37.13 ATmega2561 rev. F Not sampled. 37.14 ATmega2561 rev. E No known errata. 37.15 ATmega2561 rev. D Not sampled. 37.16 ATmega2561 rev. C • High current consumption in sleep mode. 1. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.17 ATmega2561 rev. B Not sampled. 37.18 ATmega2561 rev. A • Non-Read-While-Write area of flash not functional • Part does not work under 2.4 Volts • Incorrect ADC reading in differential mode • Internal ADC reference has too low value • IN/OUT instructions may be executed twice when Stack is in external RAM • EEPROM read from application code does not work in Lock Bit Mode 3 2549N–AVR–05/11 432 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 1. Non-Read-While-Write area of flash not functional The Non-Read-While-Write area of the flash is not working as expected. The problem is related to the speed of the part when reading the flash of this area. Problem Fix/Workaround - Only use the first 248K of the flash. - If boot functionality is needed, run the code in the Non-Read-While-Write area at maximum 1/4th of the maximum frequency of the device at any given voltage. This is done by writing the CLKPR register before entering the boot section of the code. 2. Part does not work under 2.4 volts The part does not execute code correctly below 2.4 volts. Problem Fix/Workaround Do not use the part at voltages below 2.4 volts. 3. Incorrect ADC reading in differential mode The ADC has high noise in differential mode. It can give up to 7 LSB error. Problem Fix/Workaround Use only the 7 MSB of the result when using the ADC in differential mode. 4. Internal ADC reference has too low value The internal ADC reference has a value lower than specified. Problem Fix/Workaround - Use AVCC or external reference. - The actual value of the reference can be measured by applying a known voltage to the ADC when using the internal reference. The result when doing later conversions can then be calibrated. 5. IN/OUT instructions may be executed twice when Stack is in external RAM If either an IN or an OUT instruction is executed directly before an interrupt occurs and the stack pointer is located in external ram, the instruction will be executed twice. In some cases this will cause a problem, for example: - If reading SREG it will appear that the I-flag is cleared. - If writing to the PIN registers, the port will toggle twice. - If reading registers with interrupt flags, the flags will appear to be cleared. Problem Fix/Workaround There are two application workarounds, where selecting one of them, will be omitting the issue: - Replace IN and OUT with LD/LDS/LDD and ST/STS/STD instructions. - Use internal RAM for stack pointer. 6. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. 433 ATmega640/1280/1281/2560/2561 Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 2549N–AVR–05/11 434 ATmega640/1280/1281/2560/2561 38. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. 38.1 Rev. 2549N-05/11 1. Added Atmel QTouch Library Support and QTouch Sensing Capablity Features 2. Updated Cross-reference in “Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0” on page 68 3. Updated Assembly codes in section “USART Initialization” on page 210 4. Added “Standard Power-On Reset” on page 372. 5. Added “Enhanced Power-On Reset” on page 373. 6. Updated Figure 32-13 on page 393 7. Updated “Ordering Information” on page 419 to include Tape & Reel devices. 38.2 Rev. 2549M-09/10 1. Updated typos in Figure 26-9 on page 285 and in Figure 26-10 on page 285. 2. Note is added below Table 1-1 on page 3. 3. The values for “typical characteristics” in Table 31-9 on page 377 and Table 31-10 on page 378, has been rounded. 4. Units for tRST and tBOD in Table 31-3 on page 372 have been changed from “ns” to “µs”. 5. The figure text for Table 31-2 on page 371 has been changed. 6. Text in first column in Table 30-3 on page 336 has been changed from “Fuse Low Byte” to “Extended Fuse Byte”. 7. The text in “Power Reduction Register” on page 54 has been changed. 8. The value of the inductor in Figure 26-9 on page 285 and Figure 26-10 on page 285 has been changed to 10 µH. 9. “Port A” has been changed into “Port K” in the first paragraph of “Features” on page 275. 10. Minimum wait delay for tWD_EEPROM in Table 30-16 on page 351 has been changed from 9.0ms to 3.6ms 11. Dimension A3 is added in “64M2” on page 427. 12. Several cross-references are corrected. 13. “COM0A1:0” on page 130 is corrected to “COM0B1:0”. 14. Corrected some Figure and Table numbering. 15. Updated Section 10.6 “Low Frequency Crystal Oscillator” on page 45. 38.3 Rev. 2549L-08/07 2549N–AVR–05/11 1. Updated note in Table 10-11 on page 47. 2. Updated Table 10-3 on page 43, Table 10-5 on page 44, Table 10-9 on page 47. 3. Updated typos in “DC Characteristics” on page 367 4. Updated “Clock Characteristics” on page 371 5. Updated “External Clock Drive” on page 371. 6. Added “System and Reset Characteristics” on page 372. 435 ATmega640/1280/1281/2560/2561 7. Updated “SPI Timing Characteristics” on page 375. 8. Updated “ADC Characteristics – Preliminary Data” on page 377. 9. Updated ordering code in “ATmega640” on page 419. 38.4 Rev. 2549K-01/07 1. Updated Table 1-1 on page 3. 2. Updated “Pin Descriptions” on page 7. 3. Updated “Stack Pointer” on page 16. 4. Updated “Bit 1 – EEPE: EEPROM Programming Enable” on page 36. 5. Updated Assembly code example in “Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.” on page 63. 6: Updated “EIMSK – External Interrupt Mask Register” on page 115. 7. Updated Bit description in “PCIFR – Pin Change Interrupt Flag Register” on page 116. 8. Updated code example in “USART Initialization” on page 210. 9. Updated Figure 26-8 on page 284. 10. Updated “DC Characteristics” on page 367. 38.5 Rev. 2549J-09/06 1. 2. 3. 4. 5. 6. 38.6 Rev. 2549I-07/06 Updated “” on page 46. Updated code example in “Moving Interrupts Between Application and Boot Section” on page 109. Updated “Timer/Counter Prescaler” on page 186. Updated “Device Identification Register” on page 303. Updated “Signature Bytes” on page 338. Updated “Instruction Set Summary” on page 416. 1. Added “Data Retention” on page 11. 2. Updated Table 16-3 on page 129, Table 16-6 on page 130, Table 16-8 on page 131, Table 17-2 on page 148, Table 17-4 on page 159, Table 17-5 on page 160, Table 20-3 on page 187, Table 20-6 on page 188 and Table 20-8 on page 189. 3. Updated “Fast PWM Mode” on page 150. 38.7 Rev. 2549H-06/06 1. Updated “” on page 46. 2. Updated “OSCCAL – Oscillator Calibration Register” on page 50. 3. Added Table 31-1 on page 371. 2549N–AVR–05/11 436 ATmega640/1280/1281/2560/2561 38.8 Rev. 2549G-06/06 1. Updated “Features” on page 1. 2. Added Figure 1-2 on page 3, Table 1-1 on page 3. 3. Updated “” on page 46. 4. Updated “Power Management and Sleep Modes” on page 52. 5. Updated note for Table 12-1 on page 68. 6. Updated Figure 26-9 on page 285 and Figure 26-10 on page 285. 7. Updated “Setting the Boot Loader Lock Bits by SPM” on page 324. 8. Updated “Ordering Information” on page 419. 9. Added Package information “100C1” on page 425. 10. Updated “Errata” on page 428. 38.9 Rev. 2549F-04/06 1. Updated Figure 9-3 on page 31, Figure 9-4 on page 31 and Figure 9-5 on page 32. 2. Updated Table 20-2 on page 187 and Table 20-3 on page 187. 3. Updated Features in “ADC – Analog to Digital Converter” on page 275. 4. Updated “Fuse Bits” on page 336. 38.10 Rev. 2549E-04/06 1. Updated “Features” on page 1. 2. Updated Table 12-1 on page 62. 3. Updated note for Table 12-1 on page 62. 4. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 273. 5. Updated “Prescaling and Conversion Timing” on page 278. 5. Updated “Maximum speed vs. VCC” on page 373. 6. Updated “Ordering Information” on page 419. 38.11 Rev. 2549D-12/05 1. Advanced Information Status changed to Preliminary. 2. Changed number of I/O Ports from 51 to 54. 3. Updatet typos in “TCCR0A – Timer/Counter Control Register A” on page 129. 4. Updated Features in “ADC – Analog to Digital Converter” on page 275. 5. Updated Operation in“ADC – Analog to Digital Converter” on page 275 6. Updated Stabilizing Time in “Changing Channel or Reference Selection” on page 282. 7. Updated Figure 26-1 on page 276, Figure 26-9 on page 285, Figure 26-10 on page 285. 8. Updated Text in “ADCSRB – ADC Control and Status Register B” on page 290. 9. Updated Note for Table 4 on page 43, Table 13-15 on page 86, Table 26-3 on page 289 and Table 26-6 on page 295. 10. Updated Table 31-9 on page 377 and Table 31-10 on page 378. 11. Updated “Filling the Temporary Buffer (Page Loading)” on page 323. 12. Updated “Typical Characteristics” on page 385. 13. Updated “Packaging Information” on page 424. 14. Updated “Errata” on page 428. 2549N–AVR–05/11 437 ATmega640/1280/1281/2560/2561 38.12 Rev. 2549C-09/05 1. Updated Speed Grade in section “Features” on page 1. 2. Added “Resources” on page 11. 3. Updated “SPI – Serial Peripheral Interface” on page 195. In Slave mode, low and high period SPI clock must be larger than 2 CPU cycles. 4. Updated “Bit Rate Generator Unit” on page 247. 5. Updated “Maximum speed vs. VCC” on page 373. 6. Updated “Ordering Information” on page 419. 7. Updated “Packaging Information” on page 424. Package 64M1 replaced by 64M2. 8. Updated “Errata” on page 428. 38.13 Rev. 2549B-05/05 1. JTAG ID/Signature for ATmega640 updated: 0x9608. 2. Updated Table 13-7 on page 81. 3. Updated “Serial Programming Instruction set” on page 352. 4. Updated “Errata” on page 428. 38.14 Rev. 2549A-03/05 1. Initial version. 2549N–AVR–05/11 438 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81)(3) 3523-3551 Fax: (+81)(3) 3523-7581 © 2011 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR®, QTouch®, QMatrix®, AVR Studio® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Windows® and others are registered trademarks of Microsoft Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. 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Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 5 2.1 Block Diagram ...................................................................................................5 2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560 ...........7 2.3 Pin Descriptions .................................................................................................7 3 Resources ............................................................................................... 11 4 About Code Examples ........................................................................... 11 5 Data Retention ........................................................................................ 11 6 Capacitive touch sensing ...................................................................... 11 7 AVR CPU Core ........................................................................................ 12 7.1 Introduction ......................................................................................................12 7.2 Architectural Overview .....................................................................................12 7.3 ALU – Arithmetic Logic Unit .............................................................................13 7.4 Status Register ................................................................................................14 7.5 General Purpose Register File ........................................................................15 7.6 Stack Pointer ...................................................................................................16 7.7 Instruction Execution Timing ...........................................................................17 7.8 Reset and Interrupt Handling ...........................................................................18 8 AVR Memories ........................................................................................ 21 8.1 In-System Reprogrammable Flash Program Memory .....................................21 8.2 SRAM Data Memory ........................................................................................21 8.3 EEPROM Data Memory ..................................................................................23 8.4 I/O Memory ......................................................................................................27 9 External Memory Interface .................................................................... 28 9.1 Overview ..........................................................................................................28 9.2 Register Description ........................................................................................35 9.3 General Purpose registers ...............................................................................37 9.4 External Memory registers ...............................................................................37 10 System Clock and Clock Options ......................................................... 40 10.1 Overview ..........................................................................................................40 i 2549N–AVR–05/11 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 10.2 Clock Systems and their Distribution ...............................................................40 10.3 Clock Sources .................................................................................................41 10.4 Low Power Crystal Oscillator ...........................................................................42 10.5 Full Swing Crystal Oscillator ............................................................................44 10.6 Low Frequency Crystal Oscillator ....................................................................45 10.7 Calibrated Internal RC Oscillator .....................................................................46 10.8 128 kHz Internal Oscillator ..............................................................................47 10.9 External Clock .................................................................................................48 10.10 Clock Output Buffer .........................................................................................49 10.11 Timer/Counter Oscillator ..................................................................................49 10.12 System Clock Prescaler ..................................................................................49 10.13 Register Description ........................................................................................50 11 Power Management and Sleep Modes ................................................. 52 11.1 Sleep Modes ....................................................................................................52 11.2 Idle Mode .........................................................................................................52 11.3 ADC Noise Reduction Mode ............................................................................53 11.4 Power-down Mode ...........................................................................................53 11.5 Power-save Mode ............................................................................................53 11.6 Standby Mode .................................................................................................54 11.7 Extended Standby Mode .................................................................................54 11.8 Power Reduction Register ...............................................................................54 11.9 Minimizing Power Consumption ......................................................................54 11.10 Register Description ........................................................................................56 12 System Control and Reset .................................................................... 59 12.1 Resetting the AVR ...........................................................................................59 12.2 Reset Sources .................................................................................................59 12.3 Internal Voltage Reference ..............................................................................62 12.4 Watchdog Timer ..............................................................................................63 12.5 Register Description ........................................................................................67 13 I/O-Ports .................................................................................................. 70 13.1 Introduction ......................................................................................................70 13.2 Ports as General Digital I/O .............................................................................71 13.3 Alternate Port Functions ..................................................................................75 13.4 Register Description for I/O-Ports ..................................................................100 14 Interrupts .............................................................................................. 105 ii 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 14.1 Interrupt Vectors in ATmega640/1280/1281/2560/2561 ................................105 14.2 Reset and Interrupt Vector placement ...........................................................107 14.3 Moving Interrupts Between Application and Boot Section .............................109 14.4 Register Description ......................................................................................110 15 External Interrupts ............................................................................... 112 15.1 Pin Change Interrupt Timing ..........................................................................112 15.2 Register Description ......................................................................................113 16 8-bit Timer/Counter0 with PWM .......................................................... 118 16.1 Features ........................................................................................................118 16.2 Overview ........................................................................................................118 16.3 Timer/Counter Clock Sources .......................................................................119 16.4 Counter Unit ..................................................................................................119 16.5 Output Compare Unit .....................................................................................120 16.6 Compare Match Output Unit ..........................................................................122 16.7 Modes of Operation .......................................................................................123 16.8 Timer/Counter Timing Diagrams ...................................................................127 16.9 Register Description ......................................................................................129 17 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5) .......................... 136 17.1 Features ........................................................................................................136 17.2 Overview ........................................................................................................136 17.3 Accessing 16-bit Registers ............................................................................138 17.4 Timer/Counter Clock Sources .......................................................................141 17.5 Counter Unit ..................................................................................................142 17.6 Input Capture Unit .........................................................................................143 17.7 Output Compare Units ...................................................................................145 17.8 Compare Match Output Unit ..........................................................................147 17.9 Modes of Operation .......................................................................................148 17.10 Timer/Counter Timing Diagrams ...................................................................156 17.11 Register Description ......................................................................................158 18 Timer/Counter 0, 1, 3, 4, and 5 Prescaler ........................................... 169 18.1 Internal Clock Source ....................................................................................169 18.2 Prescaler Reset .............................................................................................169 18.3 External Clock Source ...................................................................................169 18.4 Register Description ......................................................................................170 iii 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 19 Output Compare Modulator (OCM1C0A) ........................................... 172 19.1 Overview ........................................................................................................172 19.2 Description .....................................................................................................172 20 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 174 20.1 Overview ........................................................................................................174 20.2 Timer/Counter Clock Sources .......................................................................175 20.3 Counter Unit ..................................................................................................175 20.4 Modes of Operation .......................................................................................176 20.5 Output Compare Unit .....................................................................................180 20.6 Compare Match Output Unit ..........................................................................182 20.7 Timer/Counter Timing Diagrams ...................................................................183 20.8 Asynchronous Operation of Timer/Counter2 .................................................184 20.9 Timer/Counter Prescaler ...............................................................................186 20.10 Register Description ......................................................................................187 21 SPI – Serial Peripheral Interface ......................................................... 195 21.1 SS Pin Functionality ......................................................................................200 21.2 Register Description ......................................................................................202 22 USART ................................................................................................... 205 22.1 Features ........................................................................................................205 22.2 Clock Generation ...........................................................................................206 22.3 Frame Formats ..............................................................................................209 22.4 USART Initialization .......................................................................................210 22.5 Data Transmission – The USART Transmitter ..............................................212 22.6 Data Reception – The USART Receiver .......................................................214 22.7 Asynchronous Data Reception ......................................................................218 22.8 Multi-processor Communication Mode ..........................................................221 22.9 Register Description ......................................................................................222 22.10 Examples of Baud Rate Setting .....................................................................227 23 USART in SPI Mode ............................................................................. 232 23.1 Overview ........................................................................................................232 23.2 USART MSPIM vs. SPI .................................................................................232 23.3 SPI Data Modes and Timing ..........................................................................233 23.4 Frame Formats ..............................................................................................234 23.5 Data Transfer .................................................................................................236 23.6 USART MSPIM Register Description ............................................................237 iv 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 24 2-wire Serial Interface .......................................................................... 241 24.1 Features ........................................................................................................241 24.2 2-wire Serial Interface Bus Definition ............................................................241 24.3 Data Transfer and Frame Format ..................................................................242 24.4 Multi-master Bus Systems, Arbitration and Synchronization .........................245 24.5 Overview of the TWI Module .........................................................................246 24.6 Using the TWI ................................................................................................249 24.7 Transmission Modes .....................................................................................252 24.8 Multi-master Systems and Arbitration ............................................................265 24.9 Register Description ......................................................................................266 25 AC – Analog Comparator .................................................................... 271 25.1 Analog Comparator Multiplexed Input ...........................................................271 25.2 Register Description ......................................................................................272 26 ADC – Analog to Digital Converter ..................................................... 275 26.1 Features ........................................................................................................275 26.2 Operation .......................................................................................................276 26.3 Starting a Conversion ....................................................................................277 26.4 Prescaling and Conversion Timing ................................................................278 26.5 Changing Channel or Reference Selection ...................................................282 26.6 ADC Noise Canceler .....................................................................................283 26.7 ADC Conversion Result .................................................................................288 26.8 Register Description ......................................................................................289 27 JTAG Interface and On-chip Debug System ..................................... 296 27.1 Features ........................................................................................................296 27.2 Overview ........................................................................................................296 27.3 TAP - Test Access Port .................................................................................297 27.4 Using the Boundary-scan Chain ....................................................................299 27.5 Using the On-chip Debug System .................................................................299 27.6 On-chip Debug Specific JTAG Instructions ...................................................300 27.7 Using the JTAG Programming Capabilities ...................................................301 27.8 Bibliography ...................................................................................................301 27.9 On-chip Debug Related Register in I/O Memory ...........................................301 28 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 302 28.1 Features ........................................................................................................302 28.2 System Overview ...........................................................................................302 v 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 28.3 Data Registers ...............................................................................................302 28.4 Boundary-scan Specific JTAG Instructions ...................................................304 28.5 Boundary-scan Chain ....................................................................................305 28.6 Boundary-scan Related Register in I/O Memory ...........................................308 28.7 ATmega640/1280/1281/2560/2561 Boundary-scan Order ............................308 28.8 Boundary-scan Description Language Files ..................................................308 29 Boot Loader Support – Read-While-Write Self-Programming ......... 317 29.1 Features ........................................................................................................317 29.2 Application and Boot Loader Flash Sections .................................................317 29.3 Read-While-Write and No Read-While-Write Flash Sections ........................317 29.4 Boot Loader Lock Bits ...................................................................................320 29.5 Addressing the Flash During Self-Programming ...........................................322 29.6 Self-Programming the Flash ..........................................................................323 29.7 Register Description ......................................................................................332 30 Memory Programming ......................................................................... 335 30.1 Program And Data Memory Lock Bits ...........................................................335 30.2 Fuse Bits ........................................................................................................336 30.3 Signature Bytes .............................................................................................338 30.4 Calibration Byte .............................................................................................338 30.5 Page Size ......................................................................................................338 30.6 Parallel Programming Parameters, Pin Mapping, and Commands ...............338 30.7 Parallel Programming ....................................................................................341 30.8 Serial Downloading ........................................................................................349 30.9 Programming via the JTAG Interface ............................................................354 31 Electrical Characteristics .................................................................... 367 31.1 DC Characteristics .........................................................................................367 31.2 Speed Grades ...............................................................................................369 31.3 Clock Characteristics .....................................................................................371 31.4 External Clock Drive ......................................................................................371 31.5 System and Reset Characteristics ................................................................372 31.6 2-wire Serial Interface Characteristics ...........................................................373 31.7 SPI Timing Characteristics ............................................................................375 31.8 ADC Characteristics – Preliminary Data ........................................................377 31.9 External Data Memory Timing .......................................................................379 32 Typical Characteristics ........................................................................ 385 vi 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 32.1 Active Supply Current ....................................................................................385 32.2 Idle Supply Current ........................................................................................388 32.3 Power-down Supply Current ..........................................................................392 32.4 Power-save Supply Current ...........................................................................393 32.5 Standby Supply Current ................................................................................394 32.6 Pin Pull-up .....................................................................................................394 32.7 Pin Driver Strength ........................................................................................397 32.8 Pin Threshold and Hysteresis ........................................................................399 32.9 BOD Threshold and Analog Comparator Offset ............................................402 32.10 Internal Oscillator Speed ...............................................................................404 32.11 Current Consumption of Peripheral Units ......................................................406 32.12 Current Consumption in Reset and Reset Pulsewidth ..................................409 33 Register Summary ............................................................................... 411 34 Instruction Set Summary .................................................................... 416 35 Ordering Information ........................................................................... 419 35.1 ATmega640 ...................................................................................................419 35.2 ATmega1280 .................................................................................................420 35.3 ATmega1281 .................................................................................................421 35.4 ATmega2560 .................................................................................................422 35.5 ATmega2561 .................................................................................................423 36 Packaging Information ........................................................................ 424 36.1 100A ..............................................................................................................424 36.2 100C1 ............................................................................................................425 36.3 64A ................................................................................................................426 36.4 64M2 ..............................................................................................................427 37 Errata ..................................................................................................... 428 37.1 ATmega640 rev. B .........................................................................................428 37.2 ATmega640 rev. A .........................................................................................428 37.3 ATmega1280 rev. B .......................................................................................428 37.4 ATmega1280 rev. A .......................................................................................429 37.5 ATmega1281 rev. B .......................................................................................429 37.6 ATmega1281 rev. A .......................................................................................430 37.7 ATmega2560 rev. F .......................................................................................430 37.8 ATmega2560 rev. E .......................................................................................430 vii ATmega640/1280/1281/2560/2561 37.9 ATmega2560 rev. D ......................................................................................430 37.10 ATmega2560 rev. C ......................................................................................430 37.11 ATmega2560 rev. B .......................................................................................430 37.12 ATmega2560 rev. A .......................................................................................431 37.13 ATmega2561 rev. F .......................................................................................432 37.14 ATmega2561 rev. E .......................................................................................432 37.15 ATmega2561 rev. D ......................................................................................432 37.16 ATmega2561 rev. C ......................................................................................432 37.17 ATmega2561 rev. B .......................................................................................432 37.18 ATmega2561 rev. A .......................................................................................432 38 Datasheet Revision History ................................................................ 435 38.1 Rev. 2549N-05/11 .........................................................................................435 38.2 Rev. 2549M-09/10 .........................................................................................435 38.3 Rev. 2549L-08/07 ..........................................................................................435 38.4 Rev. 2549K-01/07 ..........................................................................................436 38.5 Rev. 2549J-09/06 ..........................................................................................436 38.6 Rev. 2549I-07/06 ...........................................................................................436 38.7 Rev. 2549H-06/06 .........................................................................................436 38.8 Rev. 2549G-06/06 .........................................................................................437 38.9 Rev. 2549F-04/06 ..........................................................................................437 38.10 Rev. 2549E-04/06 ..........................................................................................437 38.11 Rev. 2549D-12/05 .........................................................................................437 38.12 Rev. 2549C-09/05 .........................................................................................438 38.13 Rev. 2549B-05/05 ..........................................................................................438 38.14 Rev. 2549A-03/05 ..........................................................................................438 Table of Contents....................................................................................... i viii 2549N–AVR–05/11 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81)(3) 3523-3551 Fax: (+81)(3) 3523-7581 © 2011 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR®, QTouch®, QMatrix®, AVR Studio® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Windows® and others are registered trademarks of Microsoft Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 2549N–AVR–05/11

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