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飞思卡尔5604 datasheet

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MPC5604B/C Microcontroller Reference Manual Devices Supported: MPC5602B MPC5602C MPC5603B MPC5603C MPC5604B MPC5604C MPC5604BCRM Rev. 8 5 May 2011 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 1 MPC5604B/C Microcontroller Reference Manual, Rev. 8 2 Freescale Semiconductor Chapter 1 Preface 1.1 Overview .........................................................................................................................................19 1.2 Audience ..........................................................................................................................................19 1.3 Guide to this reference manual ........................................................................................................19 1.4 Register description conventions ....................................................................................................22 1.5 References .......................................................................................................................................23 1.6 How to use the MPC5604B documents ..........................................................................................23 1.6.1 The MPC5604B document set ........................................................................................23 1.6.2 Reference manual content ..............................................................................................24 1.7 Using the MPC5604B .....................................................................................................................25 1.7.1 Hardware design .............................................................................................................25 1.7.2 Input/output pins .............................................................................................................26 1.7.3 Software design ..............................................................................................................27 1.7.4 Other features .................................................................................................................27 Chapter 2 Introduction 2.1 The MPC5604B microcontroller family .........................................................................................29 2.2 Features ...........................................................................................................................................29 2.2.1 MPC5604B family comparison ......................................................................................29 2.2.2 Block diagram ................................................................................................................32 2.2.3 Chip-level features ..........................................................................................................33 2.3 Packages ..........................................................................................................................................34 2.4 Developer support ...........................................................................................................................34 Chapter 3 Memory Map Chapter 4 Signal description 4.1 Introduction .....................................................................................................................................39 4.2 Package pinouts ...............................................................................................................................39 4.3 Pad configuration during reset phases .............................................................................................42 4.4 Voltage supply pins .........................................................................................................................43 4.5 Pad types .........................................................................................................................................43 4.6 System pins .....................................................................................................................................44 4.7 Functional ports ...............................................................................................................................44 4.8 Nexus 2+ pins ..................................................................................................................................61 Chapter 5 Microcontroller Boot 5.1 Boot mechanism ..............................................................................................................................63 5.1.1 Flash memory boot .........................................................................................................64 5.1.2 Serial boot mode .............................................................................................................66 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 3 5.1.3 Censorship ......................................................................................................................66 5.2 Boot Assist Module (BAM) ............................................................................................................71 5.2.1 BAM software flow ........................................................................................................71 5.2.2 LINFlex (RS232) boot ....................................................................................................79 5.2.3 FlexCAN boot ................................................................................................................80 5.3 System Status and Configuration Module (SSCM) ........................................................................82 5.3.1 Introduction ....................................................................................................................82 5.3.2 Features ...........................................................................................................................82 5.3.3 Modes of operation .........................................................................................................83 5.3.4 Memory map and register description ............................................................................83 Chapter 6 Clock Description 6.1 Clock architecture ...........................................................................................................................93 6.2 Clock gating ....................................................................................................................................94 6.3 Fast external crystal oscillator (FXOSC) digital interface ..............................................................95 6.3.1 Main features ..................................................................................................................95 6.3.2 Functional description ....................................................................................................95 6.3.3 Register description ........................................................................................................96 6.4 Slow external crystal oscillator (SXOSC) digital interface ............................................................97 6.4.1 Introduction ....................................................................................................................97 6.4.2 Main features ..................................................................................................................97 6.4.3 Functional description ....................................................................................................97 6.4.4 Register description ........................................................................................................98 6.5 Slow internal RC oscillator (SIRC) digital interface ......................................................................99 6.5.1 Introduction ....................................................................................................................99 6.5.2 Functional description ....................................................................................................99 6.5.3 Register description ......................................................................................................100 6.6 Fast internal RC oscillator (FIRC) digital interface ......................................................................101 6.6.1 Introduction ..................................................................................................................101 6.6.2 Functional description ..................................................................................................101 6.6.3 Register description ......................................................................................................102 6.7 Frequency-modulated phase-locked loop (FMPLL) .....................................................................102 6.7.1 Introduction ..................................................................................................................102 6.7.2 Overview ......................................................................................................................102 6.7.3 Features .........................................................................................................................103 6.7.4 Memory map ................................................................................................................103 6.7.5 Register description ......................................................................................................104 6.7.6 Functional description ..................................................................................................107 6.7.7 Recommendations ........................................................................................................110 6.8 Clock monitor unit (CMU) ............................................................................................................110 6.8.1 Introduction ..................................................................................................................110 6.8.2 Main features ................................................................................................................ 111 6.8.3 Block diagram .............................................................................................................. 111 6.8.4 Functional description ..................................................................................................112 MPC5604B/C Microcontroller Reference Manual, Rev. 8 4 Freescale Semiconductor 6.8.5 Memory map and register description ..........................................................................114 Chapter 7 Clock Generation Module (MC_CGM) 7.1 Overview .......................................................................................................................................119 7.2 Features .........................................................................................................................................120 7.3 Modes of Operation .......................................................................................................................121 7.3.1 Normal and Reset Modes of Operation ........................................................................121 7.4 External Signal Description ..........................................................................................................121 7.5 Memory Map and Register Definition ..........................................................................................121 7.5.1 Register Descriptions ....................................................................................................125 7.6 Functional Description ..................................................................................................................129 7.6.1 System Clock Generation .............................................................................................129 7.6.2 Output Clock Multiplexing ...........................................................................................130 7.6.3 Output Clock Division Selection ..................................................................................131 Chapter 8 Mode Entry Module (MC_ME) 8.1 Introduction ...................................................................................................................................133 8.1.1 Overview ......................................................................................................................133 8.1.2 Features .........................................................................................................................135 8.1.3 Modes of Operation ......................................................................................................135 8.2 External Signal Description ..........................................................................................................136 8.3 Memory Map and Register Definition ..........................................................................................136 8.3.1 Register Description .....................................................................................................144 8.4 Functional Description ..................................................................................................................166 8.4.1 Mode Transition Request ..............................................................................................166 8.4.2 Modes Details ...............................................................................................................167 8.4.3 Mode Transition Process ..............................................................................................172 8.4.4 Protection of Mode Configuration Registers ................................................................182 8.4.5 Mode Transition Interrupts ...........................................................................................182 8.4.6 Peripheral Clock Gating ...............................................................................................184 8.4.7 Application Example ....................................................................................................185 Chapter 9 Reset Generation Module (MC_RGM) 9.1 Introduction ...................................................................................................................................187 9.1.1 Overview ......................................................................................................................187 9.1.2 Features .........................................................................................................................188 9.1.3 Modes of operation .......................................................................................................189 9.2 External signal description ............................................................................................................190 9.3 Memory map and register definition .............................................................................................190 9.3.1 Register descriptions ....................................................................................................192 9.4 Functional Description ..................................................................................................................203 9.4.1 Reset State Machine .....................................................................................................203 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 5 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 Destructive Resets ........................................................................................................207 External Reset ...............................................................................................................207 Functional Resets ..........................................................................................................208 STANDBY Entry Sequence .........................................................................................208 Alternate Event Generation ..........................................................................................208 Boot Mode Capturing ...................................................................................................209 Chapter 10 Power Control Unit (MC_PCU) 10.1 Introduction ...................................................................................................................................211 10.1.1 Overview ......................................................................................................................211 10.1.2 Features .........................................................................................................................212 10.1.3 Modes of Operation ......................................................................................................212 10.2 External Signal Description ..........................................................................................................213 10.3 Memory Map and Register Definition ..........................................................................................213 10.3.1 Register Descriptions ....................................................................................................214 10.4 Functional Description ..................................................................................................................218 10.4.1 General .........................................................................................................................218 10.4.2 Reset / Power-On Reset ................................................................................................218 10.4.3 MC_PCU Configuration ...............................................................................................218 10.4.4 Mode Transitions ..........................................................................................................218 10.5 Initialization Information ..............................................................................................................221 10.6 Application Information ................................................................................................................221 10.6.1 STANDBY Mode Considerations ................................................................................221 Chapter 11 Voltage Regulators and Power Supplies 11.1 Voltage regulators ..........................................................................................................................223 11.1.1 High power regulator (HPREG) ...................................................................................223 11.1.2 Low power regulator (LPREG) ....................................................................................223 11.1.3 Ultra low power regulator (ULPREG) .........................................................................224 11.1.4 LVDs and POR .............................................................................................................224 11.1.5 VREG digital interface .................................................................................................224 11.1.6 Register description ......................................................................................................225 11.2 Power supply strategy ...................................................................................................................225 11.3 Power domain organization ...........................................................................................................226 Chapter 12 Wakeup Unit (WKPU) 12.1 Overview .......................................................................................................................................229 12.2 Features .........................................................................................................................................231 12.3 External signal description ............................................................................................................231 12.4 Memory map and register description ...........................................................................................231 12.4.1 Memory map ................................................................................................................231 12.4.2 NMI Status Flag Register (NSR) ..................................................................................232 MPC5604B/C Microcontroller Reference Manual, Rev. 8 6 Freescale Semiconductor 12.4.3 NMI Configuration Register (NCR) .............................................................................233 12.4.4 Wakeup/Interrupt Status Flag Register (WISR) ...........................................................234 12.4.5 Interrupt Request Enable Register (IRER) ...................................................................235 12.4.6 Wakeup Request Enable Register (WRER) ..................................................................235 12.4.7 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) .............................236 12.4.8 Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) .............................236 12.4.9 Wakeup/Interrupt Filter Enable Register (WIFER) ......................................................237 12.4.10 Wakeup/Interrupt Pullup Enable Register (WIPUER) .................................................237 12.5 Functional description ...................................................................................................................238 12.5.1 General .........................................................................................................................238 12.5.2 Non-maskable interrupts ..............................................................................................238 12.5.3 External wakeups/interrupts .........................................................................................240 12.5.4 On-chip wakeups ..........................................................................................................241 Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API) 13.1 Overview .......................................................................................................................................243 13.2 Features .........................................................................................................................................243 13.3 Device-specific information ..........................................................................................................245 13.4 Modes of operation ........................................................................................................................245 13.4.1 Functional mode ...........................................................................................................245 13.4.2 Debug mode ..................................................................................................................246 13.5 Register descriptions .....................................................................................................................246 13.5.1 RTC Supervisor Control Register (RTCSUPV) ...........................................................246 13.5.2 RTC Control Register (RTCC) .....................................................................................247 13.5.3 RTC Status Register (RTCS) ........................................................................................249 13.5.4 RTC Counter Register (RTCCNT) ...............................................................................250 13.6 RTC functional description ...........................................................................................................250 13.7 API functional description ............................................................................................................251 Chapter 14 CAN Sampler 14.1 Introduction ...................................................................................................................................253 14.2 Main features .................................................................................................................................253 14.3 Register description .......................................................................................................................254 14.3.1 Control Register (CR) ...................................................................................................254 14.3.2 Sample register n (n = 0..11) ........................................................................................255 14.4 Functional description ...................................................................................................................256 14.4.1 Enabling/Disabling the CAN sampler ..........................................................................256 14.4.2 Baud rate generation .....................................................................................................257 Chapter 15 e200z0h Core 15.1 Overview .......................................................................................................................................261 15.2 Microarchitecture summary ..........................................................................................................261 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 7 15.3 Block diagram ...............................................................................................................................263 15.4 Features .........................................................................................................................................263 15.4.1 Instruction unit features ................................................................................................264 15.4.2 Integer unit features ......................................................................................................264 15.4.3 Load/Store unit features ...............................................................................................265 15.4.4 e200z0h system bus features ........................................................................................265 15.4.5 Nexus 2+ features .........................................................................................................265 15.5 Core registers and programmer’s model .......................................................................................266 Chapter 16 Interrupt Controller (INTC) 16.1 Introduction ...................................................................................................................................269 16.2 Features .........................................................................................................................................269 16.3 Block diagram ...............................................................................................................................270 16.4 Modes of operation ........................................................................................................................271 16.4.1 Normal mode ................................................................................................................271 16.5 Memory map and register description ...........................................................................................272 16.5.1 Module memory map ...................................................................................................272 16.5.2 Register description ......................................................................................................273 16.6 Functional description ...................................................................................................................280 16.6.1 Interrupt request sources ...............................................................................................289 16.6.2 Priority management ....................................................................................................289 16.6.3 Handshaking with processor .........................................................................................291 16.7 Initialization/application information ............................................................................................293 16.7.1 Initialization flow .........................................................................................................293 16.7.2 Interrupt exception handler ...........................................................................................293 16.7.3 ISR, RTOS, and task hierarchy .....................................................................................295 16.7.4 Order of execution ........................................................................................................296 16.7.5 Priority ceiling protocol ................................................................................................297 16.7.6 Selecting priorities according to request rates and deadlines .......................................297 16.7.7 Software configurable interrupt requests ......................................................................298 16.7.8 Lowering priority within an ISR ..................................................................................299 16.7.9 Negating an interrupt request outside of its ISR ..........................................................299 16.7.10 Examining LIFO contents ............................................................................................300 Chapter 17 Crossbar Switch (XBAR) 17.1 Introduction ...................................................................................................................................301 17.2 Block diagram ...............................................................................................................................301 17.3 Overview .......................................................................................................................................302 17.4 Features .........................................................................................................................................302 17.5 Modes of operation ........................................................................................................................302 17.5.1 Normal mode ................................................................................................................302 17.5.2 Debug mode ..................................................................................................................302 17.6 Functional description ...................................................................................................................302 MPC5604B/C Microcontroller Reference Manual, Rev. 8 8 Freescale Semiconductor 17.6.1 17.6.2 17.6.3 17.6.4 17.6.5 17.6.6 Overview ......................................................................................................................302 General operation .........................................................................................................303 Master ports ..................................................................................................................303 Slave ports ....................................................................................................................304 Priority assignment .......................................................................................................304 Arbitration ....................................................................................................................304 Chapter 18 Memory Protection Unit (MPU) 18.1 Introduction ...................................................................................................................................307 18.2 Features .........................................................................................................................................308 18.3 Modes of operation ........................................................................................................................309 18.4 External signal description ............................................................................................................309 18.5 Memory map and register description ...........................................................................................309 18.5.1 Memory map ................................................................................................................309 18.5.2 Register description ......................................................................................................310 18.6 Functional description ...................................................................................................................322 18.6.1 Access evaluation macro ..............................................................................................322 18.6.2 Putting it all together and AHB error terminations ......................................................324 18.7 Initialization information ...............................................................................................................324 18.8 Application information ................................................................................................................324 Chapter 19 System Integration Unit Lite (SIUL) 19.1 Introduction ...................................................................................................................................327 19.2 Overview .......................................................................................................................................327 19.3 Features .........................................................................................................................................329 19.4 External signal description ............................................................................................................329 19.4.1 Detailed signal descriptions ..........................................................................................330 19.5 Memory map and register description ...........................................................................................331 19.5.1 SIUL memory map .......................................................................................................331 19.5.2 Register protection ........................................................................................................332 19.5.3 Register descriptions ....................................................................................................333 19.6 Functional description ...................................................................................................................350 19.6.1 Pad control ....................................................................................................................350 19.6.2 General purpose input and output pads (GPIO) ...........................................................350 19.6.3 External interrupts ........................................................................................................351 19.7 Pin muxing ....................................................................................................................................352 Chapter 20 Inter-Integrated Circuit Bus Controller Module (I2C) 20.1 Introduction ...................................................................................................................................355 20.1.1 Overview ......................................................................................................................355 20.1.2 Features .........................................................................................................................355 20.1.3 Block diagram ..............................................................................................................356 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 9 20.2 External signal description ............................................................................................................356 20.2.1 SCL ...............................................................................................................................356 20.2.2 SDA ..............................................................................................................................356 20.3 Memory map and register description ...........................................................................................356 20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.3.6 20.3.7 Module memory map ...................................................................................................356 I2C Bus Address Register (IBAD) ...............................................................................357 I2C Bus Frequency Divider Register (IBFD) ...............................................................358 I2C Bus Control Register (IBCR) .................................................................................364 I2C Bus Status Register (IBSR) ....................................................................................365 I2C Bus Data I/O Register (IBDR) ...............................................................................366 I2C Bus Interrupt Config Register (IBIC) ....................................................................367 20.4 Functional description ...................................................................................................................367 20.4.1 I-Bus protocol ...............................................................................................................367 20.4.2 Interrupts .......................................................................................................................371 20.5 Initialization/application information ............................................................................................372 20.5.1 I2C programming examples ..........................................................................................372 Chapter 21 LIN Controller (LINFlex) 21.1 Introduction ...................................................................................................................................377 21.2 Main features .................................................................................................................................377 21.2.1 LIN mode features ........................................................................................................377 21.2.2 UART mode features ....................................................................................................377 21.2.3 Features common to LIN and UART ...........................................................................377 21.3 General description .......................................................................................................................378 21.4 Fractional baud rate generation .....................................................................................................379 21.5 Operating modes ...........................................................................................................................381 21.5.1 Initialization mode ........................................................................................................382 21.5.2 Normal mode ................................................................................................................382 21.5.3 Low power mode (Sleep) .............................................................................................382 21.6 Test modes .....................................................................................................................................382 21.6.1 Loop Back mode ...........................................................................................................382 21.6.2 Self Test mode ..............................................................................................................383 21.7 Memory map and registers description .........................................................................................383 21.7.1 Memory map ................................................................................................................383 21.8 Functional description ...................................................................................................................409 21.8.1 UART mode ..................................................................................................................409 21.8.2 LIN mode ......................................................................................................................411 21.8.3 8-bit timeout counter ....................................................................................................419 21.8.4 Interrupts .......................................................................................................................421 Chapter 22 FlexCAN 22.1 Introduction ...................................................................................................................................423 22.1.1 Overview ......................................................................................................................423 MPC5604B/C Microcontroller Reference Manual, Rev. 8 10 Freescale Semiconductor 22.1.2 FlexCAN module features ............................................................................................424 22.1.3 Modes of operation .......................................................................................................425 22.2 External signal description ............................................................................................................425 22.2.1 Overview ......................................................................................................................425 22.2.2 Signal descriptions ........................................................................................................426 22.3 Memory map and register description ...........................................................................................426 22.3.1 FlexCAN memory mapping .........................................................................................426 22.3.2 Message buffer structure ..............................................................................................428 22.3.3 Rx FIFO structure .........................................................................................................431 22.3.4 Register description ......................................................................................................433 22.4 Functional description ...................................................................................................................451 22.4.1 Overview ......................................................................................................................451 22.4.2 Local priority transmission ...........................................................................................452 22.4.3 Transmit process ...........................................................................................................452 22.4.4 Arbitration process .......................................................................................................453 22.4.5 Receive process ............................................................................................................454 22.4.6 Matching process ..........................................................................................................455 22.4.7 Data coherence .............................................................................................................456 22.4.8 Rx FIFO ........................................................................................................................459 22.4.9 CAN protocol related features ......................................................................................460 22.4.10 Modes of operation details ...........................................................................................464 22.4.11 Interrupts .......................................................................................................................465 22.4.12 Bus interface .................................................................................................................465 22.5 Initialization/Application information ...........................................................................................466 22.5.1 FlexCAN initialization sequence ..................................................................................466 22.5.2 FlexCAN addressing and SRAM size configurations ..................................................467 Chapter 23 Deserial Serial Peripheral Interface (DSPI) 23.1 Introduction ...................................................................................................................................469 23.2 Features .........................................................................................................................................470 23.3 Modes of operation ........................................................................................................................471 23.3.1 Master mode .................................................................................................................471 23.3.2 Slave mode ...................................................................................................................471 23.3.3 Module Disable mode ...................................................................................................471 23.3.4 Debug mode ..................................................................................................................472 23.4 External signal description ............................................................................................................472 23.4.1 Signal overview ............................................................................................................472 23.4.2 Signal names and descriptions ......................................................................................472 23.5 Memory map and register description ...........................................................................................474 23.5.1 Memory map ................................................................................................................474 23.5.2 DSPI Module Configuration Register (DSPIx_MCR) .................................................475 23.5.3 DSPI Transfer Count Register (DSPIx_TCR) ..............................................................478 23.5.4 DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) .........................478 23.5.5 DSPI Status Register (DSPIx_SR) ...............................................................................486 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 11 23.5.6 DSPI Interrupt Request Enable Register (DSPIx_RSER) ............................................488 23.5.7 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) .......................................................490 23.5.8 DSPI POP RX FIFO Register (DSPIx_POPR) ............................................................492 23.5.9 DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) .................................................493 23.6 Functional description ...................................................................................................................494 23.6.1 Modes of operation .......................................................................................................495 23.6.2 Start and stop of DSPI transfers ...................................................................................496 23.6.3 Serial peripheral interface (SPI) configuration .............................................................497 23.6.4 DSPI baud rate and clock delay generation ..................................................................500 23.6.5 Transfer formats ...........................................................................................................503 23.6.6 Continuous serial communications clock .....................................................................511 23.6.7 Interrupt requests ..........................................................................................................514 23.6.8 Power saving features ...................................................................................................515 23.7 Initialization and application information .....................................................................................516 23.7.1 How to change queues ..................................................................................................516 23.7.2 Baud rate settings .........................................................................................................516 23.7.3 Delay settings ...............................................................................................................518 23.7.4 Calculation of FIFO pointer addresses .........................................................................518 Chapter 24 Timers 24.1 Introduction ...................................................................................................................................523 24.2 Technical overview ........................................................................................................................523 24.2.1 Overview of the STM ...................................................................................................525 24.2.2 Overview of the eMIOS ...............................................................................................525 24.2.3 Overview of the PIT .....................................................................................................527 24.3 System Timer Module (STM) .......................................................................................................527 24.3.1 Introduction ..................................................................................................................527 24.3.2 External signal description ...........................................................................................528 24.3.3 Memory map and register definition ............................................................................528 24.3.4 Functional description ..................................................................................................532 24.4 Enhanced Modular IO Subsystem (eMIOS) .................................................................................532 24.4.1 Introduction ..................................................................................................................532 24.4.2 External signal description ...........................................................................................535 24.4.3 Memory map and register description ..........................................................................535 24.4.4 Functional description ..................................................................................................547 24.4.5 Initialization/Application information ..........................................................................577 24.5 Periodic Interrupt Timer (PIT) ......................................................................................................580 24.5.1 Introduction ..................................................................................................................580 24.5.2 Features .........................................................................................................................581 24.5.3 Signal description .........................................................................................................581 24.5.4 Memory map and register description ..........................................................................581 24.5.5 Functional description ..................................................................................................586 24.5.6 Initialization and application information ....................................................................587 MPC5604B/C Microcontroller Reference Manual, Rev. 8 12 Freescale Semiconductor Chapter 25 Analog-to-Digital Converter (ADC) 25.1 Overview .......................................................................................................................................591 25.1.1 Device-specific features ...............................................................................................591 25.1.2 Device-specific implementation ...................................................................................592 25.2 Introduction ...................................................................................................................................592 25.3 Functional description ...................................................................................................................593 25.3.1 Analog channel conversion ..........................................................................................593 25.3.2 Analog clock generator and conversion timings ..........................................................597 25.3.3 ADC sampling and conversion timing .........................................................................597 25.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................599 25.3.5 Presampling ..................................................................................................................600 25.3.6 Programmable analog watchdog ..................................................................................601 25.3.7 Interrupts .......................................................................................................................602 25.3.8 External decode signals delay ......................................................................................603 25.3.9 Power-down mode ........................................................................................................603 25.3.10 Auto-clock-off mode ....................................................................................................603 25.4 Register descriptions .....................................................................................................................604 25.4.1 Introduction ..................................................................................................................604 25.4.2 Control logic registers ..................................................................................................607 25.4.3 Interrupt registers ..........................................................................................................611 25.4.4 Threshold registers .......................................................................................................618 25.4.5 Presampling registers ....................................................................................................619 25.4.6 Conversion timing registers CTR[0..2] ........................................................................622 25.4.7 Mask registers ...............................................................................................................622 25.4.8 Delay registers ..............................................................................................................627 25.4.9 Data registers ................................................................................................................628 Chapter 26 Cross Triggering Unit (CTU) 26.1 Introduction ...................................................................................................................................631 26.2 Main features .................................................................................................................................631 26.3 Block diagram ...............................................................................................................................631 26.4 Memory map and register descriptions .........................................................................................631 26.4.1 Event Configuration Registers (CTU_EVTCFGRx) (x = 0...63) .................................632 26.5 Functional description ...................................................................................................................633 26.5.1 Channel value ...............................................................................................................635 Chapter 27 Flash Memory 27.1 Introduction ...................................................................................................................................639 27.2 Main features .................................................................................................................................640 27.3 Block diagram ...............................................................................................................................640 27.4 Functional description ...................................................................................................................641 27.4.1 Module structure ...........................................................................................................641 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 13 27.4.2 Flash memory module sectorization .............................................................................642 27.4.3 TestFlash block .............................................................................................................643 27.4.4 Shadow sector ...............................................................................................................645 27.4.5 User mode operation .....................................................................................................645 27.4.6 Reset .............................................................................................................................646 27.4.7 Power-down mode ........................................................................................................647 27.4.8 Low power mode ..........................................................................................................647 27.5 Register description .......................................................................................................................648 27.5.1 CFlash register description ...........................................................................................649 27.5.2 DFlash register description ...........................................................................................680 27.6 Programming considerations .........................................................................................................703 27.6.1 Modify operation ..........................................................................................................703 27.6.2 Double word program ...................................................................................................704 27.6.3 Sector erase ...................................................................................................................706 27.7 Platform flash memory controller .................................................................................................714 27.7.1 Introduction ..................................................................................................................714 27.7.2 Memory map and register description ..........................................................................717 27.8 Functional description ...................................................................................................................726 27.8.1 Access protections ........................................................................................................727 27.8.2 Read cycles – Buffer miss ............................................................................................727 27.8.3 Read cycles – Buffer hit ...............................................................................................727 27.8.4 Write cycles ..................................................................................................................727 27.8.5 Error termination ..........................................................................................................727 27.8.6 Access pipelining ..........................................................................................................728 27.8.7 Flash error response operation ......................................................................................728 27.8.8 Bank0 page read buffers and prefetch operation ..........................................................728 27.8.9 Bank1 Temporary Holding Register .............................................................................730 27.8.10 Read-while-write functionality .....................................................................................731 27.8.11 Wait-state emulation .....................................................................................................732 Chapter 28 Static RAM (SRAM) 28.1 Introduction ...................................................................................................................................735 28.2 Low power configuration ..............................................................................................................735 28.3 Register memory map ...................................................................................................................735 28.4 SRAM ECC mechanism ................................................................................................................735 28.4.1 Access timing ...............................................................................................................736 28.4.2 Reset effects on SRAM accesses ..................................................................................737 28.5 Functional description ...................................................................................................................737 28.6 Initialization and application information .....................................................................................737 Chapter 29 Register Protection 29.1 Introduction ...................................................................................................................................741 29.2 Features .........................................................................................................................................741 MPC5604B/C Microcontroller Reference Manual, Rev. 8 14 Freescale Semiconductor 29.3 Modes of operation ........................................................................................................................742 29.4 External signal description ............................................................................................................742 29.5 Memory map and register description ...........................................................................................742 29.5.1 Memory map ................................................................................................................743 29.5.2 Register description ......................................................................................................744 29.6 Functional description ...................................................................................................................746 29.6.1 General .........................................................................................................................746 29.6.2 Change lock settings .....................................................................................................746 29.6.3 Access errors ................................................................................................................750 29.7 Reset ..............................................................................................................................................750 29.8 Protected registers .........................................................................................................................750 Chapter 30 Software Watchdog Timer (SWT) 30.1 Overview .......................................................................................................................................755 30.2 Features .........................................................................................................................................755 30.3 Modes of operation ........................................................................................................................755 30.4 External signal description ............................................................................................................756 30.5 Memory map and register description ...........................................................................................756 30.5.1 Memory map ................................................................................................................756 30.5.2 Register description ......................................................................................................757 30.6 Functional description ...................................................................................................................761 Chapter 31 Error Correction Status Module (ECSM) 31.1 Introduction ...................................................................................................................................763 31.2 Overview .......................................................................................................................................763 31.3 Features .........................................................................................................................................763 31.4 Memory map and register description ...........................................................................................763 31.4.1 Memory map ................................................................................................................763 31.4.2 Register description ......................................................................................................764 31.4.3 Register protection ........................................................................................................783 Chapter 32 IEEE 1149.1 Test Access Port Controller (JTAGC) 32.1 Introduction ...................................................................................................................................787 32.2 Block diagram ...............................................................................................................................787 32.3 Overview .......................................................................................................................................787 32.4 Features .........................................................................................................................................788 32.5 Modes of operation ........................................................................................................................788 32.5.1 Reset .............................................................................................................................788 32.5.2 IEEE 1149.1-2001 defined test modes .........................................................................788 32.6 External signal description ............................................................................................................789 32.7 Memory map and register description ...........................................................................................790 32.7.1 Instruction Register ......................................................................................................790 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 15 32.7.2 Bypass Register ............................................................................................................790 32.7.3 Device Identification Register ......................................................................................790 32.7.4 Boundary Scan Register ...............................................................................................791 32.8 Functional Description ..................................................................................................................791 32.8.1 JTAGC Reset Configuration .........................................................................................791 32.8.2 IEEE 1149.1-2001 (JTAG) Test Access Port ................................................................791 32.8.3 TAP controller state machine .......................................................................................792 32.8.4 JTAGC instructions ......................................................................................................794 32.8.5 Boundary Scan ..............................................................................................................796 32.9 e200z0 OnCE controller ................................................................................................................796 32.9.1 e200z0 OnCE Controller Block Diagram .....................................................................796 32.9.2 e200z0 OnCE Controller Functional Description ........................................................797 32.9.3 e200z0 OnCE Controller Register Description ............................................................797 32.10 Initialization/application information ............................................................................................799 Chapter 33 Nexus Development Interface (NDI) 33.1 Introduction ...................................................................................................................................801 33.2 Block diagram ...............................................................................................................................801 33.3 Features .........................................................................................................................................802 33.4 Modes of Operation .......................................................................................................................803 33.4.1 Nexus Reset ..................................................................................................................803 33.4.2 Operating Mode ............................................................................................................804 33.5 External Signal Description ..........................................................................................................804 33.5.1 Nexus Signal Reset States ............................................................................................804 33.6 Memory Map and Register Description ........................................................................................804 33.6.1 Nexus Debug Interface Registers .................................................................................805 33.6.2 Register Description .....................................................................................................806 33.7 Functional description ...................................................................................................................815 33.7.1 NPC_HNDSHK module ...............................................................................................815 33.7.2 Enabling Nexus Clients for TAP Access ......................................................................816 33.7.3 Configuring the NDI for Nexus Messaging .................................................................817 33.7.4 Programmable MCKO Frequency ................................................................................817 33.7.5 Nexus Messaging ..........................................................................................................817 33.7.6 EVTO Sharing ..............................................................................................................817 33.7.7 Debug Mode Control ....................................................................................................818 33.7.8 Ownership Trace ...........................................................................................................818 Appendix A Register Map Appendix B Revision History B.1 Changes between revisions 7 and 8 ...........................................................................................903 MPC5604B/C Microcontroller Reference Manual, Rev. 8 16 Freescale Semiconductor B.2 Changes between revisions 5 and 7 ...........................................................................................908 B.3 Changes between revisions 4 and 5 ............................................................................................910 B.4 Changes between revisions 2 and 4 ............................................................................................911 B.5 Changes between revisions 1 and 2 ............................................................................................920 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 17 MPC5604B/C Microcontroller Reference Manual, Rev. 8 18 Freescale Semiconductor Chapter 1 Preface 1.1 Overview The primary objective of this document is to define the functionality of the MPC5604B microcontroller for use by software and hardware developers. The MPC5604B is built on Power Architecture® technology and integrates technologies that are important for today’s automotive vehicle body applications. The information in this book is subject to change without notice, as described in the disclaimers on the title page. As with any technical documentation, it is the reader’s responsibility to be sure he or she is using the most recent version of the documentation. To locate any published errata or updates for this document, visit the Freescale Web site at http://www.freescale.com/. 1.2 Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MPC5604B device. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the Power Architecture. 1.3 Guide to this reference manual Table 1-1. Guide to this reference manual Chapter # Title Description Functional group 2 Introduction General overview, family description, feature list and information on how to use the reference manual in conjunction with other available documents. 3 Memory Map Memory map of all peripherals and memory. 4 Signal description Pinout diagrams and descriptions of all pads. 5 Microcontroller Boot • Boot mechanism • Describes what configuration is required by the user and what processes are involved when the microcontroller boots from flash memory or serial boot modes. • Describes censorship. • Boot Assist Module (BAM) Features of BAM code and when it's used. • System Status and Configuration Module (SSCM) Reports information about current state and configuration of the microcontroller. Introductory material Memory map Signals Boot MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 19 Table 1-1. Guide to this reference manual (continued) Chapter # Title Description Functional group 6 Clock Description 7 Clock Generation Module (MC_CGM) • Covers configuration of all of the clock sources in Clocks and power the system. • Describes the Clock Monitor Unit (CMU). (includes operating mode configuration Determines how the clock sources are used (including and how to wake up clock dividers) to generate the reference clocks for all from low power of the modules and peripherals. mode) 8 Mode Entry Module (MC_ME) Determines the clock source, memory, power and peripherals that are available in each operating mode. 9 Reset Generation Module (MC_RGM) Manages the process of entering and exiting reset, allows reset sources to be configured (including LVD's) and provides status reporting. 10 Power Control Unit (MC_PCU) Controls the power to different power domains within the microcontroller (allowing SRAM to be selectively powered in STANDBY mode). 11 Voltage Regulators and Power Information on voltage regulator implementation. Supplies Includes enable bit for 5 V LVD (see also MC_RGM). 12 Wakeup Unit (WKPU) Always-active analog block. Details configuration of 2 internal (API/RTC) and 30 external (pin) low power mode wakeup sources. 13 Real Time Clock / Autonomous Details configuration and operation of timers that are Periodic Interrupt (RTC/API) predominately used for system wakeup. 14 CAN Sampler Details on how to configure the CAN sampler which is used to capture the identifier frame of a CAN message when the microcontroller is in low power mode. 15 e200z0h Core Overview on cores. For more details consult the core reference manuals available on www.freescale.com. Core platform modules 16 Interrupt Controller (INTC) Provides the configuration and control of all of the external interrupts (non-core) that are then routed to the IVOR4 core interrupt vector. 17 Crossbar Switch (XBAR) Describes the connections of the XBAR masters and slaves on this microcontroller. 18 Memory Protection Unit (MPU) The MPU sits on the slave side of the XBAR and allows highly configurable control over all master accesses to the memory. 19 System Integration Unit Lite (SIUL) How to configure the pins or ports for input or output functions including external interrupts and DSI serialization. Ports MPC5604B/C Microcontroller Reference Manual, Rev. 8 20 Freescale Semiconductor Table 1-1. Guide to this reference manual (continued) Chapter # Title 20 Inter-Integrated Circuit Bus Controller Module (I2C) 21 LIN Controller (LINFlex) 22 FlexCAN 23 Deserial Serial Peripheral Interface (DSPI) 24 Timers • Technical overview • System Timer Module (STM) • Enhanced Modular IO Subsystem (eMIOS) • Periodic Interrupt Timer (PIT) 25 Analog-to-Digital Converter (ADC) 26 Cross Triggering Unit (CTU) 27 Flash Memory 28 Static RAM (SRAM) Description Functional group These chapters describe the configuration and operation of the various communication modules. Some of these modules support eDMA requests to fill / empty buffer queues to minimize CPU overhead. Communication modules Gives an overview of the available system timer modules showing links to other modules as well as tables detailing the external pins associated with eMIOS timer channels. A simple 32-bit free running counter with 4 compare channels with interrupt on match. It can be read at any time; this is very useful for measuring execution times. Highly configurable timer module(s) supporting PWM, output compare and input capture features. Includes interrupt and eDMA support. Set of 32-bit countdown timers that provide periodic events (which can trigger an interrupt) with automatic re-load. Details the configuration and operation of the ADC modules as well as detailing the channels that are shared between the 10-bit and 12-bit ADC. The ADC is tightly linked to the INTC, eDMA, PIT_RTI and CTU. When used in conjunction with these other modules, the CPU overhead for an ADC conversion is significantly reduced. The CTU allows an ADC conversion to be automatically triggered based on an eMIOS event (like a PWM output going high) or a PIT_RTI event with no CPU intervention. Details the code and data flash memory structure (with ECC), block sizes and the flash memory port configuration, including wait states, line buffer configuration and pre-fetch control. Details the structure of the SRAM (with ECC). There are no user configurable registers associated with the SRAM. Timer modules ADC system Memory MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 21 Table 1-1. Guide to this reference manual (continued) Chapter # Title Description Functional group 29 Register Protection Certain registers in each peripheral can be protected from further writes using the register protection mechanism detailed in this section. Registers can either be configured to be unlocked via a soft lock bit or locked unit the next reset. Integrity 30 Software Watchdog Timer (SWT) The SWT offers a selection of configurable modes that can be used to monitor the operation of the microcontroller and /or reset the device or trigger an interrupt if the SWT is not correctly serviced. The SWT is enabled out of reset. 31 Error Correction Status Module Provides information about the last reset, general (ECSM) device information, system fault information and detailed ECC error information. 32 IEEE 1149.1 Test Access Port Used for boundary scan as well as device debug. Controller (JTAGC) Debug 33 Nexus Development Interface Provides advanced debug features including non (NDI) intrusive trace capabilities. A Register Map Summarizes the registers on this microcontroller Register summary B Revision History Summarizes the changes between each successive revision of this reference manual Revision history information 1.4 Register description conventions The register information for MPC5604B is presented in: • Memory maps containing: — An offset from the module’s base address — The name and acronym/abbreviation of each register — The page number on which each register is described • Register figures • Field-description tables • Associated text The register figures show the field structure using the conventions in Figure 1-1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 22 Freescale Semiconductor R0 1 W Reserved bits R FIELD1 W FIELD2 Read-only fields R FIELD W Read/write fields R0 W FIELD1 00 FIELD2 Write-only fields R FIELD W w1c Write 1 to clear field (field will always read 0) Figure 1-1. Register figure conventions The numbering of register bits and fields on MPC5604B is as follows: • Register bit numbers, shown at the top of each figure, use the standard Power Architecture bit ordering (0, 1, 2, ...) where bit 0 is the most significant bit (MSB). • Multi-bit fields within a register use conventional bit ordering (..., 2, 1, 0) where bit 0 is the least significant bit (LSB). 1.5 References In addition to this reference manual, the following documents provide additional information on the operation of the MPC5604B: • IEEE-ISTO 5001-2003 Standard for a Global Embedded Processor Interface (Nexus) • IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan Architecture • Power Architecture Book E V1.0 (http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf) 1.6 How to use the MPC5604B documents This section: • Describes how the MPC5604B documents provide information on the microcontroller • Makes recommendations on how to use the documents in a system design 1.6.1 The MPC5604B document set The MPC5604B document set comprises: • This reference manual (provides information on the features of the logical blocks on the device and how they are integrated with each other) • The device data sheet (specifies the electrical characteristics of the device) • The device product brief The following reference documents (available online at www.freescale.com) are also available to support the CPU on this device: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 23 • Programmer’s Reference Manual for Freescale Embedded Processors • e200z0 Power Architecture Core Reference Manual • Variable-Length Encoding (VLE) Programming Environments Manual The aforementioned documents describe all of the functional and electrical characteristics of the MPC5604B microcontroller. Depending on your task, you may need to refer to multiple documents to make design decisions. However, in general the use of the documents can be divided up as follows: • Use the reference manual (this document) during software development and when allocating functions during system design. • Use the data sheet when designing hardware and optimizing power consumption. • Use the CPU reference documents when doing detailed software development in assembly language or debugging complex software interactions. 1.6.2 Reference manual content The content in this document focuses on the functionality of the microcontroller rather than its performance. Most chapters describe the functionality of a particular on-chip module, such as a CAN controller or timer. The remaining chapters describe how these modules are integrated into the memory map, how they are powered and clocked, and the pin-out of the device. In general, when an individual module is enabled for use all of the detail required to configure and operate it is contained in the dedicated chapter. In some cases there are multiple implementations of this module, however, there is only one chapter for each type of module in use. For this reason, the address of registers in each module is normally provided as an offset from a base address which can be found in Chapter 3, Memory Map. The benefit of this approach is that software developed for a particular module can be easily reused on this device and on other related devices that use the same modules. The steps to enable a module for use varies but typically these require configuration of the integration features of the microcontroller. The module will normally have to be powered and enabled at system level, then a clock may have to be explicitly chosen and finally if required the input and output connections to the external system must be configured. The primary integration chapters of the reference manual contain most of the information required to enable the modules. There are special cases where a chapter may describe module functionality and some integration features for convenience — for example, the microcontroller input/output (SIUL) module. Integration and functional content is provided in the manual as shown in Table 1-2. MPC5604B/C Microcontroller Reference Manual, Rev. 8 24 Freescale Semiconductor Table 1-2. Reference manual integration and functional content Chapter Integration content Functional content Introduction • The main features on chip — • A summary of the functions provided by each module Memory Map How the memory map is allocated, — including: • Internal RAM • Flash memory • External memory-mapped resources and the location of the registers used by the peripherals1 Signal Description How the signals from each of the modules — are combined and brought to a particular pin on a package Boot Assist Module CPU boot sequence from reset Implementation of the boot options if internal flash memory is not used Clock Description Clocking architecture of the device (which Description of operation of different clock clock is available for the system and each sources peripheral) Interrupt Controller Interrupt vector table Operation of the module Mode Entry Module Module numbering for control and status Operation of operating modes System Integration Unit Lite How input signals are mapped to individual Operation of GPIO modules including external interrupt pins Voltage regulators and Power distribution to the MCU — power supplies Wakeup Unit Allocation of inputs to the Wakeup Unit Operation of the wakeup feature 1 To find the address of a register in a particular module take the start address of the module given in the memory map and add the offset for the register given in the module chapter. 1.7 Using the MPC5604B There are many different approaches to designing a system using the MPC5604B so the guidance in this section is provided as an example of how the documents can be applied in this task. Familiarity with the MPC5604B modules can help ensure that its features are being optimally used in a system design. Therefore, the current chapter is a good starting point. Further information on the detailed features of a module are provided within the module chapters. These, combined with the current chapter, should provide a good introduction to the functions available on the MCU. 1.7.1 Hardware design The MPC5604B requires that certain pins are connected to particular power supplies, system functions and other voltage levels for operation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 25 The MPC5604B internal logic operates from 1.2 V (nominal) supplies that are normally supplied by the on-chip voltage regulator from a 5 V or 3.3 V supply. The 3.3–5 V (±10%) supply is also used to supply the input/output pins on the MCU. Chapter 4, Signal description, describes the power supply pin names, numbers and their purpose. For more detail on the voltage supply of each pin, see Chapter 11, Voltage Regulators and Power Supplies. For specifications of the voltage ranges and limits and decoupling of the power supplies see the MPC5604B data sheet. Certain pins have dedicated functions that affect the behavior of the MCU after reset. These include pins to force test or alternate boot conditions and debug features. These are described in Chapter 4, Signal description, and a hardware designer should take care that these pins are connected to allow correct operation. Beyond power supply and pins that have special functions there are also pins that have special system purposes such as oscillator and reset pins. These are also described in Chapter 4, Signal description. The reset pin is bidirectional and its function is closely tied to the reset generation module [Chapter 9, Reset Generation Module (MC_RGM)”]. The crystal oscillator pins are dedicated to this function but the oscillator is not started automatically after reset. The oscillator module is described in Chapter 6, Clock Description, along with the internal clock architecture and the other oscillator sources on chip. 1.7.2 Input/output pins The majority of the pins on the MCU are input/output pins which may either operate as general purpose pins or be connected to a particular on-chip module. The arrangement allows a function to be available on several pins. The system designer should allocate the function for the pin before connecting to external hardware. The software should then choose the correct function to match the hardware. The pad characteristics can vary depending on the functions on the pad. Chapter 4, Signal description, describes each pad type (for example, S, M, or J). Two pads may be able to carry the same function but have different pad types. The electrical specification of the pads is described in the data sheet dependent on the function enabled and the pad type. There are three modules that configure the various functions available: • System Integration Unit Lite (SIUL) • Wakeup Unit (WKPU) • 32 KHz oscillator (SXOSC) The SIUL configures the digital pin functions. Each pin has a register (PCR) in the module that allows selection of the output functions that is connected to the pin. The available settings for the PCR are described in Section 4.7, Functional ports. Inputs are selected using the PSMI registers; these are described in Chapter 19, System Integration Unit Lite (SIUL). (PSMI registers connect a module to one of several pins, whereas the PCR registers connect a pin to one of several modules). The WKPU provides the ability to cause interrupts and wake the MCU from low power modes and operates independently from the SIUL. In addition to digital I/O functions the SXOSC is a "special function" that provides a slow external crystal. The SXOSC is enabled independently from the digital I/O which means that the digital function on the pin must be disabled when the SXOSC is active. The ADC functions are enabled using the PCRs. MPC5604B/C Microcontroller Reference Manual, Rev. 8 26 Freescale Semiconductor 1.7.3 Software design Certain modules provide system integration functions, and other modules (such as timers) provide specific functions. From reset, the modules involved in configuring the system for application software are: • Boot Assist Module (BAM) — determines the selected boot source • Reset Generation Module (MC_RGM) — determines the behavior of the MCU when various reset sources are triggered and reports the source of the reset • Mode Entry Module (MC_ME) — controls which operating mode the MCU is in and configures the peripherals and clocks and power supplies for each of the modes • Power Control Unit (MC_PCU) — determines which power domains are active • Clock Generation Module (MC_CGM) — chooses the clock source for the system and many peripherals After reset, the MCU will automatically select the appropriate reset source and begin to execute code. At this point the system clock is the 16 MHz FIRC oscillator, the CPU is in supervisor mode and all the memory is available. Initialization is required before most peripherals may be used and before the SRAM can be read (since the SRAM is protected by ECC, the syndrome will generally be uninitialized after reset and reads would fail the check). Accessing disabled features causes error conditions or interrupts. A typical startup routine would involve initializing the software environment including stacks, heaps, variable initialization and so on and configuring the MCU for the application. The MC_ME module enables the modules and other features like clocks. It is therefore an essential part of the initialization and operation software. In general, the software will configure an MC_ME mode to make certain peripherals, clocks, and memory active and then switch to that mode. Chapter 6, Clock Description, includes a graphic of the clock architecture of the MCU. This can be used to determine how to configure the MC_CGM module. In general software will configure the module to enable the required clocks and PLLs and route these to the active modules. After these steps are complete it is possible to configure the input/output pins and the modules for the application. 1.7.4 Other features The MC_ME module manages low power modes and so it is likely that it will be used to switch into different configurations (module sets, clocks) depending on the application requirements. The MCU includes two other features to improve the integrity of the application: • It is possible to enable a software watchdog (SWT) immediately at reset or afterwards to help detect code runaway. • Individual register settings can be protected from unintended writes using the features of the Register Protection module. The protected registers are shown in Chapter 29, Register Protection. Other integration functionality is provided by the System Status and Configuration Module (SSCM). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 27 MPC5604B/C Microcontroller Reference Manual, Rev. 8 28 Freescale Semiconductor Chapter 2 Introduction 2.1 The MPC5604B microcontroller family The MPC5604B represents a new generation of 32-bit microcontrollers based on the Power Architecture®. It belongs to an expanding family of automotive-focused products targeted at addressing the next wave of body electronics applications within the vehicle. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. The advanced and cost-efficient host processor core of the family complies with the Power Architecture embedded category. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. See Section 2.4, Developer support, for more information. 2.2 Features This section describes the features of the MPC5604B. 2.2.1 MPC5604B family comparison Table 2-1 and Table 2-2 report the memory scaling of Code Flash and SRAM. Table 2-1. Code Flash memory scaling Memory size 256 KB 384 KB 512 KB Start address 0x00000000 0x00000000 0x00000000 End address 0x0003FFFF 0x0005FFFF 0x0007FFFF Memory size 24 KB 28 KB 32 KB 40 KB 48 KB Table 2-2. SRAM memory scaling Start address 0x40000000 0x40000000 0x40000000 0x40000000 0x40000000 End address 0x40005FFF 0x40006FFF 0x40007FFF 0x40009FFF 0x4000BFFF Table 2-3 provides a summary of the different members of the MPC5604B family. This information is intended to provide an understanding of the range of functionality offered by this family. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 29 30 Table 2-3. MPC5604B device comparison1 Introduction MPC5604B/C Microcontroller Reference Manual Rev. 8 Feature Device MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560 02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG CPU e200z0h Execution speed2 Static – up to 64 MHz Code Flash 256 KB 384 KB 512 KB Data Flash 64 KB (4 × 16 KB) RAM 24 KB 32 KB 28 KB 40 KB 32 KB 48 KB MPU 8-entry ADC 12 ch, 28 ch, 36 ch, 8 ch, 28 ch, 12 ch, 28 ch, 36 ch, 8 ch, 28 ch, 12 ch, 28 ch, 36 ch, 8 ch, 28 ch, 36 ch, 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit CTU Total timer I/O3 12 ch, eMIOS 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit Yes 56ch, 12 ch, 16-bit 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit • PWM + MC 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch + IC/OC4 • PWM + IC/OC4 • IC/OC4 SCI (LINFlex) 10 ch 0 ch 20 ch 3 ch 35 40 ch 6 ch 10 ch 0 ch 20 ch 3 ch 10 ch 0 ch 20 ch 3 ch 40 ch 6 ch 10 ch 0 ch 20 ch 3 ch 4 10 ch 0 ch 20 ch 3 ch 40 ch 6 ch 10 ch 0 ch 20 ch 3 ch 40 ch 6 ch SPI (DSPI) 2 3 2 3 2 3 2 3 2 3 2 3 CAN (FlexCAN) 26 5 6 37 5 6 37 5 6 I2C 1 32 kHz oscillator GPIO8 Yes 45 79 123 45 79 45 79 123 45 79 45 79 123 45 79 123 Debug JTAG Nexus2+ Freescale Semiconductor Freescale Semiconductor Table 2-3. MPC5604B device comparison1 (continued) Feature Device MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560 02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG Package 64 100 144 64 100 64 100 144 64 100 64 100 LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP 1 Feature set dependent on selected peripheral multiplexing—table shows example implementation 2 Based on 125 °C ambient operating temperature 3 See the eMIOS section of the device reference manual for information on the channel configuration and functions. 4 IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter 5 SCI0, SCI1 and SCI2 are available. SCI3 is not available. 6 CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available. 7 CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available. 8 I/O count based on multiplexing with peripherals 9 208 MAPBGA available only as development package for Nexus2+ 144 LQFP 64 LQFP 100 208 LQFP MAPBG A9 MPC5604B/C Microcontroller Reference Manual Rev. 8 Introduction 31 2.2.2 Block diagram Figure 2-1 shows a top-level block diagram of the MPC5604B family. JTAG port Nexus port Nexus Voltage regulator NMI Clocks FMPLL JTAG NMI SIUL e200z0h Nexus 2+ Instructions (Master) Data (Master) Interrupt requests from peripheral blocks CMU INTC MPU registers 64-bit 2 x 3 Crossbar Switch MPU SRAM 48 KB Code Flash Data Flash 512 KB 64 KB SRAM controller Flash controller (Slave) (Slave) (Slave) RTC STM SWT ECSM PIT MC_RGM MC_CGM MC_ME MC_PCU BAM SSCM Interrupt request SIUL Reset control External interrupt request IMUX GPIO and pad control 36 Ch. ADC CTU Peripheral bridge 2x eMIOS 4x LINFlex 3x DSPI I2C 6x FlexCAN WKPU I/O ... Legend: ADC Analog-to-Digital Converter BAM Boot Assist Module FlexCAN Controller Area Network CMU Clock Monitor Unit CTU Cross Triggering Unit DSPI Deserial Serial Peripheral Interface eMIOS Enhanced Modular Input Output System FMPLL Frequency-Modulated Phase-Locked Loop I2C Inter-integrated Circuit Bus IMUX Internal Multiplexer INTC Interrupt Controller JTAG JTAG controller LINFlex Serial Communication Interface (LIN support) ECSM Error Correction Status Module MC_CGM Clock Generation Module Interrupt request with ... ... ... ... wakeup functionality MC_ME Mode Entry Module MC_PCU Power Control Unit MC_RGM Reset Generation Module MPU Memory Protection Unit Nexus Nexus Development Interface (NDI) Level NMI Non-Maskable Interrupt PIT Periodic Interrupt Timer RTC Real-Time Clock SIUL System Integration Unit Lite SRAM Static Random-Access Memory SSCM System Status Configuration Module STM System Timer Module SWT Software Watchdog Timer WKPU Wakeup Unit Figure 2-1. MPC5604B block diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 32 Freescale Semiconductor 2.2.3 Chip-level features On-chip modules available within the family include the following features: • Single issue, 32-bit CPU core complex (e200z0) — Compliant with the Power Architecture™ embedded category — Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. • Up to 512 Kbytes on-chip Code Flash supported with the Flash controller • Up to 64 Kbytes on-chip Data Flash supported with the Flash controller • Up to 48 Kbytes on-chip SRAM • Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity • Interrupt controller (INTC) capable of handling 148 selectable-priority interrupt sources • Frequency-modulated phase-locked loop (FMPLL) • Crossbar switch architecture for concurrent access to peripherals, Flash, or SRAM from multiple bus masters • Boot assist module (BAM) supports internal Flash programming via a serial link (FlexCAN or LINFlex) • Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS) • 10-bit analog-to-digital converter (ADC) • Up to 3 serial peripheral interface (DSPI) modules • Up to 4 serial communication interface (LINFlex) modules — LINFlex 1, 2 and 3: Master capable — LINFlex 0: Master capable and slave capable • Up to 6 enhanced full CAN (FlexCAN) modules with 64 configurable message buffers • 1 inter-integrated circuit (I2C) module • Up to 123 configurable general purpose pins supporting input and output operations (package dependent) • Real time counter (RTC) with clock source from FIRC or SIRC supporting autonomous wake-up with 1-ms resolution with max timeout of 2 seconds — Support for RTC with clock source from SXOSC, supporting wake-up with 1-sec resolution and max timeout of 1 hour • 6 periodic interrupt timers (PIT) with 32-bit counter resolution • 1 system module timer (STM) • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus • Device/board boundary scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) • On-chip voltage regulator (VREG) for regulation of input supply for all internal levels MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 33 2.3 Packages MPC5604B family members are offered in the following package types: • 64-pin LQFP, 10mm x 10mm outline • 100-pin LQFP, 0.5mm pitch, 14mm x 14mm outline • 144-pin LQFP, 0.5mm pitch, 20mm x 20mm outline • 208 MAPBGA, 1mm ball pitch, 17mm x 17mm outline development package 2.4 Developer support The MPC5604B MCU tools and third-party developers are similar to those used for the Freescale MPC5500 product family, offering a widespread, established network of tool and software vendors. It also features a high-performance Nexus debug interface. The following development support is available: • Automotive evaluation boards (EVB) featuring CAN, LIN interfaces, and more • Compilers • Debuggers • JTAG and Nexus interfaces The following software support is available: • OSEK solutions will be available from multiple third parties • CAN and LIN drivers • AUTOSAR package MPC5604B/C Microcontroller Reference Manual, Rev. 8 34 Freescale Semiconductor Chapter 3 Memory Map Table 3-1 shows the memory map for the MPC5604B. All addresses on the device, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP block. Table 3-1. MPC5604B memory map Start address End address Size (KB) Region name 0x0000_0000 0x0000_7FFF 32 Code Flash Sector 0 0x0000_8000 0x0000_BFFF 16 Code Flash Sector 1 0x0000_C000 0x0000_FFFF 16 Code Flash Sector 2 0x0001_0000 0x0001_7FFF 32 Code Flash Sector 3 0x0001_8000 0x0001_FFFF 32 Code Flash Sector 4 0x0002_0000 0x0003_FFFF 128 Code Flash Sector 5 0x0004_0000 0x0005_FFFF 128 Code Flash Sector 6 0x0006_0000 0x0007_FFFF 128 Code Flash Sector 7 0x0008_0000 0x001F_FFFF 1536 Reserved 0x0020_0000 0x0020_3FFF 16 Code Flash Shadow Sector 0x0020_4000 0x003F_FFFF 2032 Reserved 0x0040_0000 0x0040_3FFF 16 Code Flash Test Sector 0x0040_4000 0x007F_FFFF 4080 Reserved 0x0080_0000 0x0080_3FFF 16 Data Flash Array 0 0x0080_4000 0x0080_7FFF 16 Data Flash Array 1 0x0080_8000 0x0080_BFFF 16 Data Flash Array 2 0x0080_C000 0x0080_FFFF 16 Data Flash Array 3 0x0081_0000 0x00BF_FFFF 4032 Reserved 0x00C0_0000 0x00C0_3FFF 16 Data test sector 0x00C0_4000 0x00DF_FFFF 4080 Reserved 0x0100_0000 0x1FFF_FFFF 507904 Flash Emulation Mapping 0x2000_0000 0x3FFF_FFFF 524288 Reserved for External Bus Interface 0x4000_0000 0x4000_BFFF 48 SRAM 0x4000_C000 0xC3F8_7FFF 2162160 Reserved 0xC3F8_8000 0xC3F8_BFFF 16 Code Flash A Configuration 0xC3F8_C000 0xC3F8_FFFF 16 Data Flash A Configuration 0xC3F9_0000 0xC3F9_3FFF 16 SIUL MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 35 Table 3-1. MPC5604B memory map (continued) Start address End address Size (KB) Region name 0xC3F9_4000 0xC3F9_7FFF 16 WKPU 0xC3F9_8000 0xC3F9_FFFF 32 Reserved 0xC3FA_0000 0xC3FA_3FFF 16 eMIOS_0 0xC3FA_4000 0xC3FA_7FFF 16 eMIOS_1 0xC3FA_8000 0xC3FD_7FFF 192 Reserved 0xC3FD_8000 0xC3FD_BFFF 16 SSCM 0xC3FD_C000 0xC3FD_FFFF 16 MC_ME 0xC3FE_0000 0xC3FE_3FFF 16 MC_CGM 0xC3FE_4000 0xC3FE_7FFF 16 MC_RGM 0xC3FE_8000 0xC3FE_BFFF 16 MC_PCU 0xC3FE_C000 0xC3FE_FFFF 16 RTC/API 0xC3FF_0000 0xC3FF_3FFF 16 PIT 0xC3FF4000 0xFFDF_FFFF 981040 Reserved 0xFFE0_0000 0xFFE0_3FFF 16 ADC_0 0xFFE0_4000 0xFFE2_FFFF 176 Reserved 0xFFE3_0000 0xFFE3_3FFF 16 I2C_0 0xFFE3_4000 0xFFE3_FFFF 48 Reserved 0xFFE4_0000 0xFFE4_3FFF 16 LINFlex_0 0xFFE4_4000 0xFFE4_7FFF 16 LINFlex_1 0xFFE4_8000 0xFFE4_BFFF 16 LINFlex_2 0xFFE4_C000 0xFFE4_FFFF 16 LINFlex_3 0xFFE5_0000 0xFFE6_3FFF 80 Reserved 0xFFE6_4000 0xFFE6_7FFF 16 CTU 0xFFE6_8000 0xFFE6_FFFF 32 Reserved 0xFFE7_0000 0xFFE7_3FFF 16 CAN sampler 0xFFE7_4000 0xFFE7_FFFF 48 Reserved 0xFFE8_0000 0xFFEF_FFFF 512 Mirrored range 0x3F80000–0xC3FFFFFF 0xFFF0_0000 0xFFF0_FFFF 64 Reserved 0xFFF1_0000 0xFFF1_3FFF 16 MPU 0xFFF1_4000 0xFFF3_7FFF 144 Reserved 0xFFF3_8000 0xFFF3_BFFF 16 SWT 0xFFF3_C000 0xFFF3_FFFF 16 STM 0xFFF4_0000 0xFFF4_3FFF 16 ECSM MPC5604B/C Microcontroller Reference Manual, Rev. 8 36 Freescale Semiconductor Table 3-1. MPC5604B memory map (continued) Start address End address Size (KB) 0xFFF4_4000 0xFFF4_7FFF 16 Reserved 0xFFF4_8000 0xFFF4_BFFF 16 INTC 0xFFF4_C000 0xFFF8_FFFF 272 Reserved 0xFFF9_0000 0xFFF9_3FFF 16 DSPI_0 0xFFF9_4000 0xFFF9_7FFF 16 DSPI_1 0xFFF9_8000 0xFFF9_BFFF 16 DSPI_2 0xFFF9_C000 0xFFFB_FFFF 144 Reserved 0xFFFC_0000 0xFFFC_3FFF 16 FlexCAN_0 0xFFFC_4000 0xFFFC_7FFF 16 FlexCAN_1 0xFFFC_8000 0xFFFC_BFFF 16 FlexCAN_2 0xFFFC_C000 0xFFFC_FFFF 16 FlexCAN_3 0xFFFD_0000 0xFFFD_3FFF 16 FlexCAN_4 0xFFFD_4000 0xFFFD_7FFF 16 FlexCAN_5 0xFFFD_8000 0xFFFF_BFFF 144 Reserved 0xFFFF_C000 0xFFFF_FFFF 16 BAM Region name MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 37 MPC5604B/C Microcontroller Reference Manual, Rev. 8 38 Freescale Semiconductor Chapter 4 Signal description 4.1 Introduction The following sections provide signal descriptions and related information about the functionality and configuration. 4.2 Package pinouts The LQFP pinouts and the BGA ballmap are provided in the following figures. For more information on pin multiplexing on this device, see Table 4-1 through Table 4-4. 64 PB[2] 63 PC[8] 62 PC[4] 61 PC[5] 60 PH[9] 59 PC[0] 58 VSS_LV 57 VDD_LV 56 VDD_HV 55 VSS_HV 54 PC[1] 53 PH[10] 52 PA[6] 51 PA[5] 50 PC[2] 49 PC[3] PB[3] 1 PC[9] 2 PA[2] 3 PA[1] 4 PA[0] 5 VSS_HV 6 VDD_HV 7 VSS_HV 8 RESET 9 VSS_LV 10 VDD_LV 11 VDD_BV 12 PC[10] 13 PB[0] 14 PB[1] 15 PC[6] 16 64 LQFP Top view 48 PA[11] 47 PA[10] 46 PA[9] 45 PA[8] 44 PA[7] 43 PA[3] 42 PB[15] 41 PB[14] 40 PB[13] 39 PB[12] 38 PB[11] 37 PB[7] 36 PB[6] 35 PB[5] 34 VDD_HV_ADC 33 VSS_HV_ADC PC[7] 17 PA[15] 18 PA[14] 19 PA[4] 20 PA[13] 21 PA[12] 22 VDD_LV 23 VSS_LV 24 XTAL 25 VSS_HV 26 EXTAL 27 VDD_HV 28 PB[9] 29 PB[8] 30 PB[10] 31 PB[4] 32 Figure 4-1. MPC560xB LQFP 64-pin configuration MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 39 64 PB[2] 63 PC[8] 62 PC[4] 61 PC[5] 60 PH[9] 59 PC[0] 58 VSS_LV 57 VDD_LV 56 VDD_HV 55 VSS_HV 54 PC[1] 53 PH[10] 52 PA[6] 51 PA[5] 50 PC[2] 49 PC[3] PB[3] 1 PC[9] 2 PA[2] 3 PA[1] 4 PA[0] 5 VSS_HV 6 VDD_HV 7 VSS_HV 8 RESET 9 VSS_LV 10 VDD_LV 11 VDD_BV 12 PC[10] 13 PB[0] 14 PB[1] 15 PC[6] 16 64 LQFP Top view 48 PA[11] 47 PA[10] 46 PA[9] 45 PA[8] 44 PA[7] 43 PF[14] 42 PF[15] 41 PG[0] 40 PG[1] 39 PA[3] 38 PB[15] 37 PB[14] 36 PB[11] 35 PB[7] 34 VDD_HV_ADC 33 VSS_HV_ADC PC[7] 17 PA[15] 18 PA[14] 19 PA[4] 20 PA[13] 21 PA[12] 22 VDD_LV 23 VSS_LV 24 XTAL 25 VSS_HV 26 EXTAL 27 VDD_HV 28 PB[9] 29 PB[8] 30 PB[10] 31 PB[4] 32 Figure 4-2. MPC560xC LQFP 64-pin configuration 100 PB[2] 99 PC[8] 98 PC[13] 97 PC[12] 96 PE[7] 95 PE[6] 94 PE[5] 93 PE[4] 92 PC[4] 91 PC[5] 90 PE[3] 89 PE[2] 88 PH[9] 87 PC[0] 86 VSS_LV 85 VDD_LV 84 VDD_HV 83 VSS_HV 82 PC[1] 81 PH[10] 80 PA[6] 79 PA[5] 78 PC[2] 77 PC[3] 76 PE[12] PB[3] 1 PC[9] 2 PC[14] 3 PC[15] 4 PA[2] 5 PE[0] 6 PA[1] 7 PE[1] 8 PE[8] 9 PE[9] 10 PE[10] 11 PA[0] 12 PE[11] 13 VSS_HV 14 VDD_HV 15 VSS_HV 16 RESET 17 VSS_LV 18 VDD_LV 19 VDD_BV 20 PC[11] 21 PC[10] 22 PB[0] 23 PB[1] 24 PC[6] 25 100 LQFP 75 PA[11] 74 PA[10] 73 PA[9] 72 PA[8] 71 PA[7] 70 VDD_HV 69 VSS_HV 68 PA[3] 67 PB[15] 66 PD[15] 65 PB[14] 64 PD[14] 63 PB[13] 62 PD[13] 61 PB[12] 60 PD[12] 59 PB[11] 58 PD[11] 57 PD[10] 56 PD[9] 55 PB[7] 54 PB[6] 53 PB[5] 52 VDD_HV_ADC 51 VSS_HV_ADC PC[7] 26 PA[15] 27 PA[14] 28 PA[4] 29 PA[13] 30 PA[12] 31 VDD_LV 32 VSS_LV 33 XTAL 34 VSS_HV 35 EXTAL 36 VDD_HV 37 PB[9] 38 PB[8] 39 PB[10] 40 PD[0] 41 PD[1] 42 PD[2] 43 PD[3] 44 PD[4] 45 PD[5] 46 PD[6] 47 PD[7] 48 PD[8] 49 PB[4] 50 Note: Availability of port pin alternate functions depends on product selection. Figure 4-3. LQFP 100-pin configuration (top view) MPC5604B/C Microcontroller Reference Manual, Rev. 8 40 Freescale Semiconductor 144 PB[2] 143 PC[8] 142 PC[13] 141 PC[12] 140 PE[7] 139 PE[6] 138 PH[8] 137 PH[7] 136 PH[6] 135 PH[5] 134 PH[4] 133 PE[5] 132 PE[4] 131 PC[4] 130 PC[5] 129 PE[3] 128 PE[2] 127 PH[9] 126 PC[0] 125 VSS_LV 124 VDD_LV 123 VDD_HV 122 VSS_HV 121 PC[1] 120 PH[10] 119 PA[6] 118 PA[5] 117 PC[2] 116 PC[3] 115 PG[11] 114 PG[10] 113 PE[15] 112 PE[14] 111 PG[15] 110 PG[14] 109 PE[12] PB[3] 1 PC[9] 2 PC[14] 3 PC[15] 4 PG[5] 5 PG[4] 6 PG[3] 7 PG[2] 8 PA[2] 9 PE[0] 10 PA[1] 11 PE[1] 12 PE[8] 13 PE[9] 14 PE[10] 15 PA[0] 16 PE[11] 17 VSS_HV 18 VDD_HV 19 VSS_HV 20 RESET 21 VSS_LV 22 VDD_LV 23 VDD_BV 24 PG[9] 25 PG[8] 26 PC[11] 27 PC[10] 28 PG[7] 29 PG[6] 30 PB[0] 31 PB[1] 32 PF[9] 33 PF[8] 34 PF[12] 35 PC[6] 36 144 LQFP 108 PA[11] 107 PA[10] 106 PA[9] 105 PA[8] 104 PA[7] 103 PE[13] 102 PF[14] 101 PF[15] 100 VDD_HV 99 VSS_HV 98 PG[0] 97 PG[1] 96 PH[3] 95 PH[2] 94 PH[1] 93 PH[0] 92 PG[12] 91 PG[13] 90 PA[3] 89 PB[15] 88 PD[15] 87 PB[14] 86 PD[14] 85 PB[13] 84 PD[13] 83 PB[12] 82 PD[12] 81 PB[11] 80 PD[11] 79 PD[10] 78 PD[9] 77 PB[7] 76 PB[6] 75 PB[5] 74 VDD_HV_ADC 73 VSS_HV_ADC PC[7] 37 PF[10] 38 PF[11] 39 PA[15] 40 PF[13] 41 PA[14] 42 PA[4] 43 PA[13] 44 PA[12] 45 VDD_LV 46 VSS_LV 47 XTAL 48 VSS_HV 49 EXTAL 50 VDD_HV 51 PB[9] 52 PB[8] 53 PB[10] 54 PF[0] 55 PF[1] 56 PF[2] 57 PF[3] 58 PF[4] 59 PF[5] 60 PF[6] 61 PF[7] 62 PD[0] 63 PD[1] 64 PD[2] 65 PD[3] 66 PD[4] 67 PD[5] 68 PD[6] 69 PD[7] 70 PD[8] 71 PB[4] 72 Note: Availability of port pin alternate functions depends on product selection. Figure 4-4. LQFP 144-pin configuration (top view) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A PC[8] PC[13] NC NC PH[8] PH[4] PC[5] PC[0] NC NC PC[2] NC PE[15] NC NC NC A B PC[9] PB[2] NC PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] NC PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B C PC[14] VDD_HV PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] NC PA[5] NC PE[14] PE[12] PA[9] PA[8] C D NC NC PC[15] NC PH[6] PE[4] PE[2] VDD_LV VDD_HV NC PA[6] NC PG[10] PF[14] PE[13] PA[7] D E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_HV E F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F G PE[9] PE[8] PE[10] PA[0] VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV NC NC MSEO G H VSS_HV PE[11] VDD_HV NC VSS_HV VSS_HV VSS_HV VSS_HV MDO3 MDO2 MDO0 MDO1 H J RESET VSS_LV NC NC VSS_HV VSS_HV VSS_HV VSS_HV NC NC NC NC J K EVTI NC VDD_BV VDD_LV VSS_HV VSS_HV VSS_HV VSS_HV NC PG[12] PA[3] PG[13] K L PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L M PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M N PB[1] PF[9] PB[0] NC NC PA[4] VSS_LV EXTAL VDD_HV PF[0] PF[4] NC PB[11] PD[10] PD[9] PD[11] N P PF[8] NC PC[7] NC NC PA[14] VDD_LV XTAL PB[10] PF[1] R PF[12] PC[6] PF[10] PF[11] VDD_HV PA[15] PA[13] T NC NC NC MCKO NC PF[13] PA[12] NC OSC32K _XTAL PF[3] NC OSC32K _EXTAL PF[2] PF[5] PF[7] PF[6] PD[0] PD[2] PD[1] PD[3] VDD_HV _ADC PB[6] PB[7] P PD[4] PD[7] VSS_HV _ADC PB[5] R PD[5] PD[6] PD[8] PB[4] T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: 208 MAPBGA available only as development package for Nexus 2+. NC = Not connected Figure 4-5. 208 MAPBGA configuration 4.3 Pad configuration during reset phases All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate. After power-up phase, all pads are forced to tristate with the following exceptions: • PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash. • PA[8] (ABS[0]) is pull-up. • RESET pad is driven low. This is pull-up only after PHASE2 reset completion. • JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate. • Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available). MPC5604B/C Microcontroller Reference Manual, Rev. 8 42 Freescale Semiconductor • Main oscillator pads (EXTAL, XTAL) are tristate. • Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output. 4.4 Voltage supply pins Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization. Table 4-1. Voltage supply pin descriptions Port pin Function Pin number 64 LQFP1 100 LQFP 144 LQFP 208 MAPBGA2 VDD_HV Digital supply voltage 7, 28, 56 15, 37, 70, 19, 51, 100, C2, D9, E16, 84 123 G13, H3, N9, R5 VSS_HV Digital ground 6, 8, 26, 55 14, 16, 35, 69, 83 18, 20, 49, 99, 122 G7, G8, G9, G10, H1, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10 VDD_LV VSS_LV VDD_BV 1.2V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest VSS_LV pin.3 1.2V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest VDD_LV pin.3 Internal regulator supply voltage 11, 23, 57 10, 24, 58 12 19, 32, 85 23, 46, 124 D8, K4, P7 18, 33, 86 22, 47, 125 C8, J2, N7 20 24 K3 VSS_HV_AD Reference ground and analog ground for 33 51 73 R15 C the ADC VDD_HV_AD Reference voltage and analog supply for 34 52 74 P14 C the ADC 1 Pin numbers apply to both the MPC560xB and MPC560xC packages. 2 208 MAPBGA available only as development package for Nexus2+ 3 A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details). 4.5 Pad types In the device the following types of pads are available for system pins and functional port pins: S = Slow1 M = Medium1 2 1. See the I/O pad electrical characteristics in the device datasheet for details. 2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC in Section 19.5.3.8, “Pad Configuration Registers (PCR0–PCR122)). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 43 F = Fast1 2 I = Input only with analog feature1 J = Input/Output with analog feature X = Oscillator 4.6 System pins The system pins are listed in Table 4-2. Table 4-2. System pin descriptions System pin Function I/O Pad directio typ n e RESET config. Pin number 64 LQFP1 100 LQFP 144 LQFP 208 MAPBGA2 RESET Bidirectional reset with Schmitt-Trigger characteristics and noise filter. I/O M Input, weak 9 17 21 J1 pull-up only after PHASE2 EXTAL Analog output of the oscillator amplifier I/O circuit, when the oscillator is not in bypass mode. Analog input for the clock generator when the oscillator is in bypass mode. 3 X Tristate 27 36 50 N8 XTAL Analog input of the oscillator amplifier circuit. I Needs to be grounded if oscillator is used in bypass mode. 3 X Tristate 25 34 48 P8 1 Pin numbers apply to both the MPC560xB and MPC560xC packages. 2 208 MAPBGA available only as development package for Nexus2+ 3 See the relevant section of the datasheet 4.7 Functional ports The functional port pins are listed in Table 4-3. MPC5604B/C Microcontroller Reference Manual, Rev. 8 44 Freescale Semiconductor Table 4-3. Functional port pin descriptions Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PA[0] PA[1] PA[2] PA[3] PA[4] PA[5] PA[6] PA[7] PCR[0] AF0 AF1 AF2 AF3 — PCR[1] AF0 AF1 AF2 AF3 — — PCR[2] AF0 AF1 AF2 AF3 — PCR[3] AF0 AF1 AF2 AF3 — PCR[4] AF0 AF1 AF2 AF3 — PCR[5] AF0 AF1 AF2 AF3 PCR[6] AF0 AF1 AF2 AF3 — PCR[7] AF0 AF1 AF2 AF3 — GPIO[0] E0UC[0] CLKOUT — WKUP[19]4 GPIO[1] E0UC[1] — — NMI5 WKUP[2]4 GPIO[2] E0UC[2] — — WKUP[3]4 GPIO[3] E0UC[3] — — EIRQ[0] GPIO[4] E0UC[4] — — WKUP[9]4 GPIO[5] E0UC[5] — — GPIO[6] E0UC[6] — — EIRQ[1] GPIO[7] E0UC[7] LIN3TX — EIRQ[2] SIUL I/O M eMIOS_0 I/O CGL O — — WKPU I SIUL I/O S eMIOS_0 I/O — — — — WKPU I WKPU I SIUL I/O S eMIOS_0 I/O — — — — WKPU I SIUL I/O S eMIOS_0 I/O — — — — SIUL I SIUL I/O S eMIOS_0 I/O — — — — WKPU I SIUL I/O M eMIOS_0 I/O — — — — SIUL I/O S eMIOS_0 I/O — — — — SIUL I SIUL I/O S eMIOS_0 I/O LINFlex_3 O — — SIUL I Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 5 5 12 16 G4 4 4 7 11 F3 3 3 5 9 F2 43 39 68 90 K15 20 20 29 43 N6 51 51 79 118 C11 52 52 80 119 D11 44 44 71 104 D16 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 45 Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PA[8] PA[9] PCR[8] AF0 AF1 AF2 AF3 — N/A 6 — PCR[9] AF0 AF1 AF2 AF3 N/A 6 PA[10] PCR[10] AF0 AF1 AF2 AF3 PA[11] PCR[11] AF0 AF1 AF2 AF3 PA[12] PCR[12] AF0 AF1 AF2 AF3 — PA[13] PCR[13] AF0 AF1 AF2 AF3 PA[14] PCR[14] AF0 AF1 AF2 AF3 — GPIO[8] E0UC[8] — — EIRQ[3] ABS[0] LIN3RX GPIO[9] E0UC[9] — — FAB GPIO[10] E0UC[10] SDA — GPIO[11] E0UC[11] SCL — GPIO[12] — — — SIN_0 GPIO[13] SOUT_0 — — GPIO[14] SCK_0 CS0_0 — EIRQ[4] SIUL I/O S Input, weak 45 45 72 105 C16 eMIOS_0 I/O pull-up — — — — SIUL I BAM I LINFlex_3 I SIUL I/O S Pull-down 46 46 73 106 C15 eMIOS_0 I/O — — — — BAM I SIUL I/O S eMIOS_0 I/O I2C_0 I/O — — SIUL I/O S eMIOS_0 I/O I2C_0 I/O — — SIUL — — — DSPI0 I/O S — — — I SIUL DSPI_0 — — I/O M O — — SIUL DSPI_0 DSPI_0 — SIUL I/O M I/O I/O — I Tristate Tristate Tristate Tristate Tristate 47 47 74 107 B16 48 48 75 108 B15 22 22 31 45 T7 21 21 30 44 R7 19 19 28 42 P6 MPC5604B/C Microcontroller Reference Manual, Rev. 8 46 Freescale Semiconductor Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PA[15] PCR[15] AF0 AF1 AF2 AF3 — PB[0] PCR[16] AF0 AF1 AF2 AF3 PB[1] PCR[17] AF0 AF1 AF2 AF3 — — PB[2] PCR[18] AF0 AF1 AF2 AF3 PB[3] PCR[19] AF0 AF1 AF2 AF3 — — PB[4] PCR[20] AF0 AF1 AF2 AF3 — PB[5] PCR[21] AF0 AF1 AF2 AF3 — PB[6] PCR[22] AF0 AF1 AF2 AF3 — GPIO[15] CS0_0 SCK_0 — WKUP[10]4 GPIO[16] CAN0TX — — GPIO[17] — — — WKUP[4]4 CAN0RX GPIO[18] LIN0TX SDA — GPIO[19] — SCL — WKUP[11]4 LIN0RX GPIO[20] — — — GPI[0] GPIO[21] — — — GPI[1] GPIO[22] — — — GPI[2] SIUL DSPI_0 DSPI_0 — WKPU I/O M I/O I/O — I SIUL I/O M FlexCAN_0 O — — — — SIUL I/O S — — — — — — WKPU I FlexCAN_0 I SIUL I/O M LINFlex_0 O I2C_0 I/O — — SIUL I/O S — — I2C_0 I/O — — WKPU I LINFlex_0 I SIUL — — — ADC II — — — I SIUL — — — ADC II — — — I SIUL — — — ADC II — — — I Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 18 18 27 40 R6 14 14 23 31 N3 15 15 24 32 N1 64 64 100 144 B2 1 1 1 1 C3 32 32 50 72 T16 35 — 53 75 R16 36 — 54 76 P15 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 47 Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PB[7] PCR[23] AF0 AF1 AF2 AF3 — GPIO[23] — — — GPI[3] SIUL — — — ADC II — — — I PB[8] PCR[24] AF0 AF1 AF2 AF3 — — GPIO[24] — — — ANS[0] OSC32K_XTAL7 SIUL II — — — — — — ADC I SXOSC I/O PB[9] PCR[25] AF0 GPIO[25] SIUL II AF1 — — — AF2 — — — AF3 — — — — ANS[1] ADC I — OSC32K_EXTAL7 SXOSC I/O PB[10] PCR[26] AF0 AF1 AF2 AF3 — — PB[11]8 PCR[27] AF0 AF1 AF2 AF3 — GPIO[26] — — — ANS[2] WKUP[8]4 GPIO[27] E0UC[3] — CS0_0 ANS[3] SIUL — — — ADC WKPU I/O J — — — I I SIUL I/O J eMIOS_0 I/O — — DSPI_0 I/O ADC I PB[12] PCR[28] AF0 AF1 AF2 AF3 — GPIO[28] E0UC[4] — CS1_0 ANX[0] SIUL I/O J eMIOS_0 I/O — — DSPI_0 O ADC I PB[13] PCR[29] AF0 AF1 AF2 AF3 — GPIO[29] E0UC[5] — CS2_0 ANX[1] SIUL I/O J eMIOS_0 I/O — — DSPI_0 O ADC I Tristate 37 35 55 77 P16 Tristate 30 30 39 53 R9 Tristate 29 29 38 52 T9 Tristate 31 31 40 54 P9 Tristate 38 36 59 81 N13 Tristate 39 — 61 83 M1 6 Tristate 40 — 63 85 M1 3 MPC5604B/C Microcontroller Reference Manual, Rev. 8 48 Freescale Semiconductor Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PB[14] PCR[30] AF0 AF1 AF2 AF3 — PB[15] PC[0]9 PC[1]9 PCR[31] AF0 AF1 AF2 AF3 — PCR[32] AF0 AF1 AF2 AF3 PCR[33] AF0 AF1 AF2 AF3 PC[2] PCR[34] AF0 AF1 AF2 AF3 — PC[3] PCR[35] AF0 AF1 AF2 AF3 — — — PC[4] PCR[36] AF0 AF1 AF2 AF3 — — GPIO[30] E0UC[6] — CS3_0 ANX[2] GPIO[31] E0UC[7] — CS4_0 ANX[3] GPIO[32] — TDI — GPIO[33] — TDO10 — GPIO[34] SCK_1 CAN4TX11 — EIRQ[5] GPIO[35] CS0_1 MA[0] — CAN1RX CAN4RX11 EIRQ[6] GPIO[36] — — — SIN_1 CAN3RX11 SIUL I/O J eMIOS_0 I/O — — DSPI_0 O ADC I Tristate 41 37 65 87 L16 SIUL I/O J eMIOS_0 I/O — — DSPI_0 O ADC I Tristate 42 38 67 89 L13 SIUL — JTAGC — I/O M Input, weak 59 59 87 126 A8 — pull-up I — SIUL — JTAGC — I/O M — O — Tristate 54 54 82 121 C9 SIUL I/O M DSPI_1 I/O LINFlex_4 O — — SIUL I Tristate 50 50 78 117 A11 SIUL I/O S DSPI_1 I/O ADC O — — FlexCAN_1 I FlexCAN_4 I SIUL I Tristate 49 49 77 116 B11 SIUL I/O M — — — — — — DSPI_1 I FlexCAN_3 I Tristate 62 62 92 131 B7 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 49 Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PC[5] PCR[37] AF0 AF1 AF2 AF3 — PC[6] PCR[38] AF0 AF1 AF2 AF3 PC[7] PCR[39] AF0 AF1 AF2 AF3 — — PC[8] PCR[40] AF0 AF1 AF2 AF3 PC[9] PCR[41] AF0 AF1 AF2 AF3 — — PC[10] PCR[42] AF0 AF1 AF2 AF3 PC[11] PCR[43] AF0 AF1 AF2 AF3 — — — GPIO[37] SOUT_1 CAN3TX11 — EIRQ[7] GPIO[38] LIN1TX — — GPIO[39] — — — LIN1RX WKUP[12]4 GPIO[40] LIN2TX — — GPIO[41] — — — LIN2RX WKUP[13]4 GPIO[42] CAN1TX CAN4TX11 MA[1] GPIO[43] — — — CAN1RX CAN4RX11 WKUP[5]4 SIUL I/O M DSPI1 O FlexCAN_3 O — — SIUL I SIUL I/O S LINFlex_1 O — — — — SIUL I/O S — — — — — — LINFlex_1 I WKPU I SIUL I/O S LINFlex_2 O — — — — SIUL I/O S — — — — — — LINFlex_2 I WKPU I SIUL I/O M FlexCAN_1 O FlexCAN_4 O ADC O SIUL I/O S — — — — — — FlexCAN_1 I FlexCAN_4 I WKPU I Tristate Tristate Tristate Tristate Tristate Tristate Tristate 61 61 91 130 A7 16 16 25 36 R2 17 17 26 37 P3 63 63 99 143 A1 2 2 2 2 B1 13 13 22 28 M3 — — 21 27 M4 MPC5604B/C Microcontroller Reference Manual, Rev. 8 50 Freescale Semiconductor Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PC[12] PCR[44] AF0 AF1 AF2 AF3 — PC[13] PCR[45] AF0 AF1 AF2 AF3 PC[14] PCR[46] AF0 AF1 AF2 AF3 — PC[15] PCR[47] AF0 AF1 AF2 AF3 PD[0] PCR[48] AF0 AF1 AF2 AF3 — PD[1] PCR[49] AF0 AF1 AF2 AF3 — PD[2] PCR[50] AF0 AF1 AF2 AF3 — PD[3] PCR[51] AF0 AF1 AF2 AF3 — GPIO[44] E0UC[12] — — SIN_2 GPIO[45] E0UC[13] SOUT_2 — GPIO[46] E0UC[14] SCK_2 — EIRQ[8] GPIO[47] E0UC[15] CS0_2 — GPIO[48] — — — GPI[4] GPIO[49] — — — GPI[5] GPIO[50] — — — GPI[6] GPIO[51] — — — GPI[7] SIUL I/O M eMIOS_0 I/O — — — — DSPI_2 I SIUL I/O S eMIOS_0 I/O DSPI_2 O — — SIUL I/O S eMIOS_0 I/O DSPI_2 I/O — — SIUL I SIUL I/O M eMIOS_0 I/O DSPI_2 I/O — — SIUL — — — ADC II — — — I SIUL — — — ADC II — — — I SIUL — — — ADC II — — — I SIUL — — — ADC II — — — I Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate — — 97 141 B4 — — 98 142 A2 — — 3 3 C1 — — 4 4 D3 — — 41 63 P12 — — 42 64 T12 — — 43 65 R12 — — 44 66 P13 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 51 Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PD[4] PCR[52] AF0 AF1 AF2 AF3 — PD[5] PCR[53] AF0 AF1 AF2 AF3 — PD[6] PCR[54] AF0 AF1 AF2 AF3 — PD[7] PCR[55] AF0 AF1 AF2 AF3 — PD[8] PCR[56] AF0 AF1 AF2 AF3 — PD[9] PCR[57] AF0 AF1 AF2 AF3 — PD[10] PCR[58] AF0 AF1 AF2 AF3 — PD[11] PCR[59] AF0 AF1 AF2 AF3 — GPIO[52] — — — GPI[8] GPIO[53] — — — GPI[9] GPIO[54] — — — GPI[10] GPIO[55] — — — GPI[11] GPIO[56] — — — GPI[12] GPIO[57] — — — GPI[13] GPIO[58] — — — GPI[14] GPIO[59] — — — GPI[15] SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC II — — — I II — — — I II — — — I II — — — I II — — — I II — — — I II — — — I II — — — I Tristate — — 45 67 R13 Tristate — — 46 68 T13 Tristate — — 47 69 T14 Tristate — — 48 70 R14 Tristate — — 49 71 T15 Tristate — — 56 78 N15 Tristate — — 57 79 N14 Tristate — — 58 80 N16 MPC5604B/C Microcontroller Reference Manual, Rev. 8 52 Freescale Semiconductor Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PD[12]8 PCR[60] AF0 AF1 AF2 AF3 — PD[13] PCR[61] AF0 AF1 AF2 AF3 — PD[14] PCR[62] AF0 AF1 AF2 AF3 — PD[15] PCR[63] AF0 AF1 AF2 AF3 — PE[0] PCR[64] AF0 AF1 AF2 AF3 — — PE[1] PCR[65] AF0 AF1 AF2 AF3 PE[2] PCR[66] AF0 AF1 AF2 AF3 — PE[3] PCR[67] AF0 AF1 AF2 AF3 GPIO[60] CS5_0 E0UC[24] — ANS[4] GPIO[61] CS0_1 E0UC[25] — ANS[5] GPIO[62] CS1_1 E0UC[26] — ANS[6] GPIO[63] CS2_1 E0UC[27] — ANS[7] GPIO[64] E0UC[16] — — CAN5RX11 WKUP[6]4 GPIO[65] E0UC[17] CAN5TX11 — GPIO[66] E0UC[18] — — SIN_1 GPIO[67] E0UC[19] SOUT_1 — SIUL I/O J DSPI_0 O eMIOS_0 I/O — — ADC I SIUL I/O J DSPI_1 I/O eMIOS_0 I/O — — ADC I SIUL I/O J DSPI_1 O eMIOS_0 I/O — — ADC I SIUL I/O J DSPI_1 O eMIOS_0 I/O — — ADC I SIUL I/O S eMIOS_0 I/O — — — — FlexCAN_5 I WKPU I SIUL I/O M eMIOS_0 I/O FlexCAN_5 O — — SIUL I/O M eMIOS_0 I/O — — — — DSPI_1 I SIUL I/O M eMIOS_0 I/O DSPI_1 O — — Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate — — 60 82 M1 5 — — 62 84 M1 4 — — 64 86 L15 — — 66 88 L14 — — 6 10 F1 — — 8 12 F4 — — 89 128 D7 — — 90 129 C7 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 53 Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PE[4] PCR[68] AF0 AF1 AF2 AF3 — PE[5] PCR[69] AF0 AF1 AF2 AF3 PE[6] PCR[70] AF0 AF1 AF2 AF3 PE[7] PCR[71] AF0 AF1 AF2 AF3 PE[8] PCR[72] AF0 AF1 AF2 AF3 PE[9] PCR[73] AF0 AF1 AF2 AF3 — — — PE[10] PCR[74] AF0 AF1 AF2 AF3 — PE[11] PCR[75] AF0 AF1 AF2 AF3 — — GPIO[68] E0UC[20] SCK_1 — EIRQ[9] GPIO[69] E0UC[21] CS0_1 MA[2] GPIO[70] E0UC[22] CS3_0 MA[1] GPIO[71] E0UC[23] CS2_0 MA[0] GPIO[72] CAN2TX12 E0UC[22] CAN3TX11 GPIO[73] — E0UC[23] — WKUP[7]4 CAN2RX12 CAN3RX11 GPIO[74] LIN3TX CS3_1 — EIRQ[10] GPIO[75] — CS4_1 — LIN3RX WKUP[14]4 SIUL I/O M eMIOS_0 I/O DSPI_1 I/O — — SIUL I SIUL I/O M eMIOS_0 I/O DSPI_1 I/O ADC O SIUL I/O M eMIOS_0 I/O DSPI_0 O ADC O SIUL I/O M eMIOS_0 I/O DSPI_0 O ADC O SIUL I/O M FlexCAN_2 O eMIOS_0 I/O FlexCAN_3 O SIUL I/O S — — eMIOS_0 I/O — — WKPU I FlexCAN_2 I FlexCAN_3 I SIUL I/O S LINFlex_3 O DSPI_1 O — — SIUL I SIUL I/O S — — DSPI_1 O — — LINFlex_3 I WKPU I Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate — — 93 132 D6 — — 94 133 C6 — — 95 139 B5 — — 96 140 C4 — — 9 13 G2 — — 10 14 G1 — — 11 15 G3 — — 13 17 H2 MPC5604B/C Microcontroller Reference Manual, Rev. 8 54 Freescale Semiconductor Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PE[12] PCR[76] AF0 AF1 AF2 AF3 — — PE[13] PCR[77] AF0 AF1 AF2 AF3 PE[14] PCR[78] AF0 AF1 AF2 AF3 — PE[15] PCR[79] AF0 AF1 AF2 AF3 PF[0] PCR[80] AF0 AF1 AF2 AF3 — PF[1] PCR[81] AF0 AF1 AF2 AF3 — PF[2] PCR[82] AF0 AF1 AF2 AF3 — PF[3] PCR[83] AF0 AF1 AF2 AF3 — GPIO[76] — E1UC[19]13 — SIN_2 EIRQ[11] GPIO[77] SOUT2 E1UC[20] — GPIO[78] SCK_2 E1UC[21] — EIRQ[12] GPIO[79] CS0_2 E1UC[22] — GPIO[80] E0UC[10] CS3_1 — ANS[8] GPIO[81] E0UC[11] CS4_1 — ANS[9] GPIO[82] E0UC[12] CS0_2 — ANS[10] GPIO[83] E0UC[13] CS1_2 — ANS[11] SIUL I/O S — — eMIOS_1 I/O — — DSPI_2 I SIUL I SIUL I/O S DSPI_2 O eMIOS_1 I/O — — SIUL I/O S DSPI_2 I/O eMIOS_1 I/O — — SIUL I SIUL I/O M DSPI_2 I/O eMIOS_1 I/O — — SIUL I/O J eMIOS_0 I/O DSPI_1 O — — ADC I SIUL I/O J eMIOS_0 I/O DSPI_1 O — — I I SIUL I/O J eMIOS_0 I/O DSPI_2 I/O — — ADC I SIUL I/O J eMIOS_0 I/O DSPI_2 O — — ADC I Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate — — 76 109 C14 — — — 103 D15 — — — 112 C13 — — — 113 A13 — — — 55 N10 — — — 56 P10 — — — 57 T10 — — — 58 R10 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 55 Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PF[4] PCR[84] AF0 AF1 AF2 AF3 — PF[5] PCR[85] AF0 AF1 AF2 AF3 — PF[6] PCR[86] AF0 AF1 AF2 AF3 — PF[7] PCR[87] AF0 AF1 AF2 AF3 — PF[8] PCR[88] AF0 AF1 AF2 AF3 PF[9] PCR[89] AF0 AF1 AF2 AF3 — — PF[10] PCR[90] AF0 AF1 AF2 AF3 PF[11] PCR[91] AF0 AF1 AF2 AF3 — GPIO[84] E0UC[14] CS2_2 — ANS[12] GPIO[85] E0UC[22] CS3_2 — ANS[13] GPIO[86] E0UC[23] — — ANS[14] GPIO[87] — — — ANS[15] GPIO[88] CAN3TX14 CS4_0 CAN2TX15 GPIO[89] — CS5_0 — CAN2RX15 CAN3RX14 GPIO[90] — — — GPIO[91] — — — WKUP[15]4 SIUL I/O J eMIOS_0 I/O DSPI_2 O — — ADC I SIUL I/O J eMIOS_0 I/O DSPI_2 O — — ADC I SIUL I/O J eMIOS_0 I/O — — — — ADC I SIUL — — — ADC I/O J — — — I SIUL I/O M FlexCAN_3 O DSPI_0 O FlexCAN_2 O SIUL I/O S — — DSPI_0 O — — FlexCAN_2 I FlexCAN_3 I SIUL — — — I/O M — — — SIUL — — — WKPU I/O S — — — I Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate — — — 59 N11 — — — 60 P11 — — — 61 T11 — — — 62 R11 — — — 34 P1 — — — 33 N2 — — — 38 R3 — — — 39 R4 MPC5604B/C Microcontroller Reference Manual, Rev. 8 56 Freescale Semiconductor Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PF[12] PCR[92] AF0 AF1 AF2 AF3 PF[13] PCR[93] AF0 AF1 AF2 AF3 — PF[14] PCR[94] AF0 AF1 AF2 AF3 PF[15] PCR[95] AF0 AF1 AF2 AF3 — — — PG[0] PCR[96] AF0 AF1 AF2 AF3 PG[1] PCR[97] AF0 AF1 AF2 AF3 — — PG[2] PCR[98] AF0 AF1 AF2 AF3 PG[3] PCR[99] AF0 AF1 AF2 AF3 — GPIO[92] E1UC[25] — — GPIO[93] E1UC[26] — — WKUP[16]4 GPIO[94] CAN4TX11 E1UC[27] CAN1TX GPIO[95] — — — CAN1RX CAN4RX11 EIRQ[13] GPIO[96] CAN5TX11 E1UC[23] — GPIO[97] — E1UC[24] — CAN5RX11 EIRQ[14] GPIO[98] E1UC[11] — — GPIO[99] E1UC[12] — — WKUP[17]4 SIUL I/O M eMIOS_1 I/O — — — — SIUL I/O S eMIOS_1 I/O — — — — WKPU I SIUL I/O M FlexCAN_4 O eMIOS_1 I/O FlexCAN_4 O SIUL I/O S — — — — — — FlexCAN_1 I FlexCAN_4 I SIUL I SIUL I/O M FlexCAN_5 O eMIOS_1 I/O — — SIUL I/O S — — eMIOS_1 I/O — — FlexCAN_5 I SIUL I SIUL I/O M eMIOS_1 I/O — — — — SIUL I/O S eMIOS_1 I/O — — — — WKPU I Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate — — — 35 R1 — — — 41 T6 — 43 — 102 D14 — 42 — 101 E15 — 41 — 98 E14 — 40 — 97 E13 — — — 8 E4 — — — 7 E3 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 57 Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PG[4] PCR[100] AF0 AF1 AF2 AF3 PG[5] PCR[101] AF0 AF1 AF2 AF3 — PG[6] PCR[102] AF0 AF1 AF2 AF3 PG[7] PCR[103] AF0 AF1 AF2 AF3 PG[8] PCR[104] AF0 AF1 AF2 AF3 — PG[9] PCR[105] AF0 AF1 AF2 AF3 PG[10] PCR[106] AF0 AF1 AF2 AF3 PG[11] PCR[107] AF0 AF1 AF2 AF3 PG[12] PCR[108] AF0 AF1 AF2 AF3 GPIO[100] E1UC[13] — — GPIO[101] E1UC[14] — — WKUP[18]4 GPIO[102] E1UC[15] — — GPIO[103] E1UC[16] — — GPIO[104] E1UC[17] — CS0_2 EIRQ[15] GPIO[105] E1UC[18] — SCK_2 GPIO[106] E0UC[24] — — GPIO[107] E0UC[25] — — GPIO[108] E0UC[26] — — SIUL I/O M eMIOS_1 I/O — — — — SIUL I/O S eMIOS_1 I/O — — — — WKPU I SIUL I/O M eMIOS_1 I/O — — — — SIUL I/O M eMIOS_1 I/O — — — — SIUL I/O S eMIOS_1 I/O — — DSPI_2 I/O SIUL I SIUL I/O S eMIOS_1 I/O — — DSPI_2 I/O SIUL I/O S eMIOS_0 I/O — — — — SIUL I/O M eMIOS_0 I/O — — — — SIUL I/O M eMIOS_0 I/O — — — — Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate — — — 6 E1 — — — 5 E2 — — — 30 M2 — — — 29 M1 — — — 26 L2 — — — 25 L1 — — — 114 D13 — — — 115 B12 — — — 92 K14 MPC5604B/C Microcontroller Reference Manual, Rev. 8 58 Freescale Semiconductor Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PG[13] PCR[109] AF0 AF1 AF2 AF3 PG[14] PCR[110] AF0 AF1 AF2 AF3 PG[15] PCR[111] AF0 AF1 AF2 AF3 PH[0] PCR[112] AF0 AF1 AF2 AF3 — PH[1] PCR[113] AF0 AF1 AF2 AF3 PH[2] PCR[114] AF0 AF1 AF2 AF3 PH[3] PCR[115] AF0 AF1 AF2 AF3 PH[4] PCR[116] AF0 AF1 AF2 AF3 PH[5] PCR[117] AF0 AF1 AF2 AF3 GPIO[109] E0UC[27] — — GPIO[110] E1UC[0] — — GPIO[111] E1UC[1] — — GPIO[112] E1UC[2] — — SIN1 GPIO[113] E1UC[3] SOUT1 — GPIO[114] E1UC[4] SCK_1 — GPIO[115] E1UC[5] CS0_1 — GPIO[116] E1UC[6] — — GPIO[117] E1UC[7] — — SIUL I/O M eMIOS_0 I/O — — — — SIUL I/O S eMIOS_1 I/O — — — — SIUL I/O M eMIOS_1 I/O — — — — SIUL I/O M eMIOS_1 I/O — — — — DSPI_1 I SIUL I/O M eMIOS_1 I/O DSPI_1 O — — SIUL I/O M eMIOS_1 I/O DSPI_1 I/O — — SIUL I/O M eMIOS_1 I/O DSPI_1 I/O — — SIUL I/O M eMIOS_1 I/O — — — — SIUL I/O S eMIOS_1 I/O — — — — Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate — — — 91 K16 — — — 110 B14 — — — 111 B13 — — — 93 F13 — — — 94 F14 — — — 95 F16 — — — 96 F15 — — — 134 A6 — — — 135 B6 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 59 Table 4-3. Functional port pin descriptions (continued) Pin number Port pin PCR Alternate function1 Function Peripheral I/O direction2 Pad type RESET configuration MPC560xB 64 LQFP MPC560xC 64 LQFP 100 LQFP 144 LQFP 208 MAPBGA3 PH[6] PCR[118] AF0 AF1 AF2 AF3 GPIO[118] E1UC[8] — MA[2] SIUL I/O M eMIOS_1 I/O — — ADC O Tristate — — — 136 D5 PH[7] PCR[119] AF0 AF1 AF2 AF3 GPIO[119] E1UC[9] CS3_2 MA[1] SIUL I/O M eMIOS_1 I/O DSPI_2 O ADC O Tristate — — — 137 C5 PH[8] PCR[120] AF0 AF1 AF2 AF3 GPIO[120] E1UC[10] CS2_2 MA[0] SIUL I/O M eMIOS_1 I/O DSPI_2 O ADC O Tristate — — — 138 A5 PH[9]9 PCR[121] AF0 AF1 AF2 AF3 GPIO[121] — TCK — SIUL — JTAGC — I/O S Input, weak — — 88 127 B8 — pull-up I — PH[10]9 PCR[122] AF0 AF1 AF2 AF3 GPIO[122] — TMS — SIUL — JTAGC — I/O S Input, weak — — 81 120 B9 — pull-up I — 1 Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00  AF0; PCR.PA = 01  AF1; PCR.PA = 10  AF2; PCR.PA = 11  AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”. 2 Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. 3 208 MAPBGA available only as development package for Nexus2+ 4 All WKUP pins also support external interrupt capability. See wakeup unit chapter for further details. 5 NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. 6 “Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the reference manual for details. 7 Value of PCR.IBE bit must be 0 8 Be aware that this pad is used on the MPC5607B 100-pin and 144-pin to provide VDD_HV_ADC and VSS_HV_ADC1. Therefore, you should be careful in ensuring compatibility between MPC5604B and MPC5607B. 9 Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001. MPC5604B/C Microcontroller Reference Manual, Rev. 8 60 Freescale Semiconductor 10 The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of 47–100 k should be added between the TDO pin and VDD. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin and GND instead. 11 Available only on MPC560xC versions and MPC5604B 208 MAPBGA devices 12 Not available on MPC5602B devices 13 Not available in 100 LQFP package 14 Available only on MPC5604B 208 MAPBGA devices 15 Not available on MPC5603B 144-pin devices 4.8 Nexus 2+ pins In the 208 MAPBGA package, eight additional debug pins are available (see Table 4-4). Table 4-4. Nexus 2+ pin descriptions Debug pin Function I/O direction Pad type Function after reset MCKO Message clock out O F — MDO0 Message data out 0 O M — MDO1 Message data out 1 O M — MDO2 Message data out 2 O M — MDO3 Message data out 3 O M — EVTI Event in I M Pull-up EVTO Event out O M — MSEO Message start/end out O M — 1 208 MAPBGA available only as development package for Nexus2+ Pin number 100 LQFP — — — — — — — — 144 LQFP — — — — — — — — 208 MAP BGA1 T4 H15 H16 H14 H13 K1 L4 G16 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 61 MPC5604B/C Microcontroller Reference Manual, Rev. 8 62 Freescale Semiconductor Chapter 5 Microcontroller Boot This chapter explains the process of booting the microcontroller. The following entities are involved in the boot process: • Boot Assist Module (BAM) • System Status and Configuration Module (SSCM) • Flash memory boot sectors (see Chapter 27, Flash Memory) • Memory Management Unit (MMU) 5.1 Boot mechanism This section describes the configuration required by the user, and the steps performed by the microcontroller, in order to achieve a successful boot from flash memory or serial download modes. There are 2 external pins on the microcontroller that are latched during reset and used to determine whether the microcontroller will boot from flash memory or attempt a serial download via FlexCAN or LINFlex (RS232): • FAB (Force Alternate Boot mode) on pin PA[9] • ABS (Alternate Boot Select) on pin PA[8] Table 5-1 describes the configuration options. Table 5-1. Boot mode selection Mode Flash memory boot (default mode) Serial boot (LINFlex) Serial boot (FlexCAN) FAB pin (PA[9]) 0 1 1 ABS pin (PA[8]) X 0 1 The microcontroller has a weak pull-down on PA[9] and a weak pull-up on PA[8]. This means that if nothing external is connected to these pins, the microcontroller will enter flash memory boot mode by default. In order to change the boot behavior, you should use external pullup or pulldown resistors on PA[9] and PA[8]. If there is any external circuitry connected to either pin, you must ensure that this does not interfere with the expected value applied to the pin at reset. Otherwise, the microcontroller may boot into an unexpected mode after reset. The SSCM preforms a lot of the automated boot activity including reading the latched value of the FAB (PA[9]) pin to determine whether to boot from flash memory or serial boot mode. This is illustrated in Figure 5-1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 63 SSCM reads latched values of PA[8] and PA[9] pins FAB = 0 FAB (PA[9]) value? FAB = 1 Boot from flash memory ABS = 0 ABS (PA[8]) value? ABS = 1 Serial boot (LINFlex) Serial boot (FlexCAN) Figure 5-1. Boot mode selection 5.1.1 Flash memory boot In order to sucessfully boot from flash memory, you must program two 32-bit fields into one of 5 possible boot blocks as detailed below. The entities to program are: • 16-bit Reset Configuration Half Word (RCHW), which contains: — A BOOT_ID field that must be correctly set to 0x5A in order to "validate" the boot sector • 32-bit reset vector (this is the start address of the user code) The location and structure of the boot sectors in flash memory are shown in Figure 5-2. MPC5604B/C Microcontroller Reference Manual, Rev. 8 64 Freescale Semiconductor 0x0000_0000 Boot sector 0 32 KB 0x0000_8000 0x0000_C000 0x0001_0000 Boot sector 1 16 KB Boot sector 2 16 KB Boot sector 3 32 KB 0x0001_8000 Boot sector 4 32 KB Boot sector structure Bit 0 78 15 16 0x0 (RCHW) Reserved BOOT_ID (0x5A) Reserved Bit 31 0x4 32-bit reset vector (points to start address of application code) 0x8 Application code (from offset 0x8 and onward) Code flash memory Figure 5-2. Boot sector structure The RCHW fields are described in Table 5-2. Table 5-2. RCHW field descriptions Field BOOT_ID Description Boot identifier. If BOOT_ID = 0x5A, the boot sector is considered valid and bootable. The SSCM performs a sequential search of each boot sector (starting at sector 0) for a valid BOOT_ID within the RCHW. If a valid BOOT_ID is found, the SSCM reads the boot vector address. If a valid BOOT_ID is not found, the SSCM starts the process of putting the microcontroller into static mode. Finally, the SSCM sets the e200z0h core instruction pointer to the reset vector address and starts the core running. 5.1.1.1 Static mode If no valid BOOT_ID within the RCHW was found, the SSCM sets the CPU core instruction pointer to the BAM address and the core starts to execute the code to enter static mode as follows: • The core executes the "wait" instruction which halts the core. The sequence is illustrated in Figure 5-3. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 65 SSCM searches flash boot sectors for valid BOOT_ID (0x5A) Yes Valid No BOOT_ID found? SSCM reads reset vector address SSCM transfers execution to e200z0h core which runs BAM code e200z0h core starts executing code at vector address BAM code executes wait instruction System in static mode (requires reset to recover) Figure 5-3. Flash memory boot mode sequence 5.1.1.2 Alternate boot sectors Some applications require an alternate boot sector so that the main boot code can be erased and reprogrammed in the field. When an alternate boot is needed, you can create two bootable sectors: • The valid boot sector located at the lowest address is the main boot sector. • The valid boot sector located at the next available address is the alternate boot sector. This scheme ensures that there is always one active boot sector even if the main boot sector is erased. 5.1.2 Serial boot mode Serial boot provides a mechanism to download and then execute code into the microcontroller SRAM. Code may be downloaded using either FlexCAN or LINFlex (RS232). After the SSCM has detected that serial boot mode has been requested, execution is transferred to the BAM which handles all of the serial boot mode tasks. See Section 5.2, Boot Assist Module (BAM), for more details. 5.1.3 Censorship Censorship can be enabled to protect the contents of the flash memory from being read or modified. In order to achieve this, the censorship mechanism controls access to the: • JTAG / Nexus debug interface • Serial boot mode (which could otherwise be used to download and execute code to query or modify the flash memory) MPC5604B/C Microcontroller Reference Manual, Rev. 8 66 Freescale Semiconductor To re-gain access to the flash memory via JTAG or serial boot, a 64-bit password must be correctly entered. CAUTION When censorship has been enabled, the only way to regain access is with the password. If this is forgotten or not correctly configured, then there is no way back into the device. There are two 64-bit values stored in the shadow flash which control the censorship (see Table 27-6 for a full description): • Nonvolatile Private Censorship Password registers, NVPWD0 and NVPWD1 • Nonvolatile System Censorship Control registers, NVSCC0 and NVSCC1 5.1.3.1 Censorship password registers (NVPWD0 and NVPWD1) The two private password registers combine to form a 64-bit password that should be programmed to a value known only by you. After factory test these registers are programmed as shown below: • NVPWD0 = 0xFEED_FACE • NVPWD1 = 0xCAFE_BEEF This means that even if censorship was inadvertently enabled by writing to the censorship control registers, there is an opportunity to get back into the microcontroller using the default private password of 0xFEED_FACE_CAFE_BEEF. When configuring the private password, each half word (16-bit) must contain at least one "1" and one "0". Some examples of legal and illegal passwords are shown in Table 5-3: Table 5-3. Examples of legal and illegal passwords Legal (valid) passwords 0x0001_0001_0001_0001 0xFFFE_FFFE_FFFE_FFFE 0x1XXX_X2XX_XX4X_XXX8 Illegal (invalid) passwords 0x0000_XXXX_XXXX_XXXX 0xFFFF_XXXX_XXXX_XXXX In uncensored devices it is possible to download code via LINFlex or FlexCAN (Serial Boot Mode) into internal SRAM even if the 64-bit private password stored in the flash and provided during the boot sequence is a password that does not conform to the password rules. 5.1.3.2 Nonvolatile System Censorship Control registers (NVSCC0 and NVSCC1) These registers are used together to define the censorship configuration. After factory test these registers are programmed as shown below which disables censorship: • NVSCC0 = 0x55AA_55AA • NVSCC1 = 0x55AA_55AA Each 32-bit register is split into an upper and lower 16-bit field. The upper 16 bits (the SC field) are used to control serial boot mode censorship. The lower 16 bits (the CW field) are used to control flash memory boot censorship. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 67 CAUTION If the contents of the shadow flash memory are erased and the NVSCC0,1 registers are not re-programmed to a valid value, the microcontroller will be permanently censored with no way for you to regain access. A microcontroller in this state cannot be debugged or re-flashed. 5.1.3.3 Censorship configuration The steps to configuring censorship are: 1. Define a valid 64-bit password that conforms to the password rules. 2. Using the table and flow charts below, decide what level of censorship you require and configure the NVSCC0,1 values. 3. Re-program the shadow flash memory and NVPWD0,1 and NVSCC0,1 registers with your new values. A POR is required before these will take effect. CAUTION If (NVSCC0 and NVSCC1 do not match) or (Either NVSCC0 or NVSCC1 is not set to 0x55AA) then the microcontroller will be permanently censored with no way to get back in. Table 5-4 shows all the possible modes of censorship. The red shaded areas are to be avoided as these show the configuration for a device that is permanently locked out. If you wish to enable censorship with a private password there is only one valid configuration — to modify the CW field in both NVSCC0,1 registers so they match but do not equal 0x55AA. This will allow you to enter the private password in both serial and flash boot modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 68 Freescale Semiconductor Table 5-4. Censorship configuration and truth table Boot configuration FAB pin state Control options Serial censorship Censorship control word control word (NVSCCn[SC] (NVSCCn[CW]) ) Internal flash memory state Nexus state Serial JTAG password password 0 (flash Uncensored memory boot) Private flash memory password and censored 0xXXXX AND NVSCC0 == NVSCC1 0x55AA AND NVSCC0 == NVSCC1 0x55AA AND NVSCC0 == NVSCC1 !0x55AA AND NVSCC0 == NVSCC1 Censored with no password access (lockout) 1 (serial Private flash boot) memory password and uncensored !0x55AA !0X55AA OR NVSCC0 != NVSCC1 0x55AA AND NVSCC0 == NVSCC1 Private flash memory password and censored 0x55AA AND NVSCC0 == NVSCC1 !0x55AA AND NVSCC0 == NVSCC1 Public password and uncensored !0x55AA AND NVSCC0 != NVSCC1 0X55AA AND NVSCC0 != NVSCC1 Public password and censored (lockout) !0x55AA OR NVSCC0 != NVSCC1 Enabled Enabled Enabled Enabled with password Enabled Disabled N/A NVPWD1,0 (SSCM reads flash memory1) N/A Enabled Enabled Enabled Disabled Enabled NVPWD0,1 (BAM reads flash memory1) Disabled NVPWD1,0 (SSCM reads flash memory1) Enabled Public (0xFEED_F ACE_CAFE _BEEF) Disabled Public (0xFEED_F ACE_CAFE _BEEF) = Microcontroller permanently locked out = Not applicable 1 When the SSCM reads the passwords from flash memory, the NVPWD0 and NVPWD1 password order is swapped, so you have to submit the 64-bit password as {NVPWD1, NVPWD0}. The flow charts in Figure 5-4 and Figure 5-5 provide a way to quickly check what will happen with different configurations of the NVSCC0,1 registers as well as detailing the correct way to enter the serial password. In the password examples, assume the 64-bit password has been programmed into the shadow flash memory in the order {NVPWD0, NWPWD1} and has a value of 0x01234567_89ABCDEF. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 69 FAB = 0 (Flash boot mode) NVSCC0 != NVSCC1 ? False True Censored with no password access (Locked out) Both SC and CW != 0x55AA ? False True Note: CW != 0x55AA SC = 0x55AA ? False True Censored with no password access (Locked out) Censored with private password over JTAG Uncensored JTAG password details: Enter password as {NVPWD1, NVPWD0} example – 0x89ABCDEF_01234567 Figure 5-4. Censorship control in flash memory boot mode MPC5604B/C Microcontroller Reference Manual, Rev. 8 70 Freescale Semiconductor FAB = 1 (Serial boot mode) NVSCC0 != NVSCC1 ? False True Censored with no password access (Locked out) Both SC and CW != 0x55AA ? False True Note: SC != 0x55AA CW = 0x55AA ? False True Censored with no password access (Locked out) Public password, Uncensored Serial password details: Enter public password 0xFEEDFACE_CAFEBEEF Note: CW != 0x55AA SC = 0x55AA ? False True Flash (private) password, Censored Flash (private) password, Uncensored Enter password as {NVPWD1, NVPWD0} example – 0x89ABCDEF_01234567 Enter password as {NVPWD0, NVPWD1} example – 0x01234567_89ABCDEF Figure 5-5. Censorship control in serial boot mode 5.2 Boot Assist Module (BAM) The BAM consits of a block of ROM at address 0xFFFF_C000 containing VLE firmware. The BAM provides 2 main functions: • Manages the serial download (FlexCAN or LINFlex protocols supported) including support for a serial password if censorship is enabled • Places the microcontroller into static mode if flash memory boot mode is selected and a valid BOOT_ID is not located in one of the boot sectors by the SSCM 5.2.1 BAM software flow Figure 5-6 illustrates the BAM logic flow. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 71 BAM Entry 0xFFFF_C000 Save default configuration Check boot mode at SSCM_STATUS[BMODE] Boot mode valid? No Yes Download new code and save in SRAM Restore default configuration Restore default configuration STATIC mode Execute new code Figure 5-6. BAM logic flow The initial (reset) device configuration is saved including the mode and clock configuration. This means that the serial download software running in the BAM can make changes to the modes and clocking and then restore these to the default values before running the newly downloaded application code from the SRAM. The SSCM_STATUS[BMODE] field indicates which boot mode is to be executed (see Table 5-5). This field is only updated during reset. There are 2 conditions where the boot mode is not considered valid and the BAM pushes the microcontroller into static mode after restoring the default configuration: • BMODE = 011 (flash memory boot mode). This means that the SSCM has been unable to find a valid BOOT_ID in the boot sectors so has called the BAM • BMODE = reserved In static mode a wait instruction is executed to halt the core. For the FlexCAN and LINFlex serial boot modes, the respective area of BAM code is executed to download the code to SRAM. MPC5604B/C Microcontroller Reference Manual, Rev. 8 72 Freescale Semiconductor Table 5-5. SSCM_STATUS[BMODE] values as used by BAM BMODE value 000 001 010 011 100–111 Corresponding boot mode Reserved FlexCAN_0 serial boot loader LINFlex_0 (RS232 /UART) serial boot loader Flash memory boot mode Reserved After the code has been downloaded to SRAM, the BAM code restores the initial device configuration and then transfers execution to the start address of the downloaded code. 5.2.1.1 BAM resources The BAM uses/initializes the following MCU resources: • MC_ME and MC_CGM to initialize mode and clock sources • FlexCAN_0, LINFlex _0 and the respective I/O pins when performing serial boot mode • SSCM and shadow flash memory (NVPWD0,1 and NVSCC0,1) during password check • SSCM to check the boot mode (see Table 5-5) • 4–16 MHz fast external crystal oscillator The system clock is selected directly from the 4–16 MHz fast external crystal oscillator. Thus, the external oscillator frequency defines the baud rates used for serial download (see Table 5-6). Table 5-6. Serial boot mode – baud rates FXOSC frequency (MHz) fFXOSC 8 12 16 LINFlex baud rate (baud) fFXOSC/833 9600 14400 19200 CAN bit rate (bit/s) fFXOSC/40 200K 300K 400K 5.2.1.2 Download and execute the new code From a high level perspective, the download protocol follows these steps: 1. Send the 64-bit password. 2. Send the start address, size of code to be downloaded (in bytes) and the VLE bit1. 3. Download the code. Each step must be completed before the next step starts. After the download is complete (the specified number of bytes is downloaded), the code executes from the start address. 1. Since the device supports only VLE code and not Book E code, this flag is used only for backward compatibility. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 73 The communication is done in half duplex manner, whereby the transmission from the host is followed by the microcontroller transmission mirroring the transmission back to the host: • Host sends data to the microcontroller and waits for a response. • MCU echoes to host the data received. • Host verifies if echo is correct: — If data is correct, the host can continue to send data. — If data is not correct, the host stops transmission and the microcontroller enters static mode. All multi-byte data structures are sent with MSB first. A more detailed description of these steps follows. 5.2.1.3 Censorship mode detection and serial password validation Before the serial download can commence, the BAM code must determine which censorship mode the microcontroller is in and which password to use. It does this by reading the PUB and SEC fields in the SSCM Status Register (see Section 5.3.4.1, System Status Register (SSCM_STATUS)) as shown in Table 5-7. Table 5-7. BAM censorship mode detection SSCM_STATUS register fields PUB SEC Mode Password comparison 1 0 Uncensored, public password 0xFEED_FACE_CAFE_BEEF 0 0 Uncensored, private password NVPWD0,1 from flash memory via BAM 0 1 Censored, private password NVPWD1,0 from flash memory via SSCM When censorship is enabled, the flash memory cannot be read by application code running in the BAM or in the SRAM. This means that the private password in the shadow flash memory cannot be read by the BAM code. In this case the SSCM is used to obtain the private password from the flash memory of the censored device. When the SSCM reads the private password it inverts the order of {NVPWD0, NWPWD1} so the password entered over the serial download needs to be {NVPWD1, NVPWD0}. MPC5604B/C Microcontroller Reference Manual, Rev. 8 74 Freescale Semiconductor BAM tasks BAM code is being executed (serial boot mode) Applicable password SSCM_STATUS register PUB and SEC bits are read Public password mode ? PUB = 1 Yes ? No Is censorship enabled ? SEC = 1 Yes ? No Start serial download with password Public password, Uncensored, BAM can directly check password Private password, Censored, SSCM needed to check password Private password, Uncensored, BAM can directly check password Figure 5-7. BAM censorship mode detection The first thing to be downloaded is the 64-bit password. If the password does not match the stored password, then the BAM code pushes the microcontroller into static mode. The way the password is compared with either the public or private password (depending on mode) varies depending on whether censorship is enabled as described in the following subsections. 5.2.1.3.1 Censorship disabled (private or public passwords): 1. If the public password is used, the BAM code does a direct comparison between the serial password and 0xFEED_FACE_CAFE_BEEF. 2. If the private password is used, the BAM code does a direct comparison between the serial password and the private password in flash memory, {NVPWD0, NVPWD1}. 3. If the password does not match, the BAM code immediately terminates the download and pushes the microcontroller into static mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 75 5.2.1.3.2 Censorship enabled (private password) 1. Since the flash is secured, the SSCM is required to read the private password. 2. The BAM code writes the serial password to the SSCM_PWCMPH and SSCM_PWCMPL registers. 3. The BAM code then continues with the serial download (start address, data size and data) until all the data has been copied to the SRAM. 4. In the meantime the SSCM has compared the private password in flash with the serial download password the BAM code wrote into SSCM_PWCMPH and SSCM_PWCMPL. 5. If the SSCM obtains a match in the passwords, the censorship is temporarily disabled (until the next reset). 6. The SSCM updates the status of the security (SEC) bit to reflect whether the passwords matched (SEC = 0) or not (SEC = 1) 7. Finally, the BAM code reads SEC. If SEC = 0, execution is transferred to the code in the SRAM. If SEC = 1, the BAM code forces the microcontroller into static mode. Figure 5-8 shows this in more detail. MPC5604B/C Microcontroller Reference Manual, Rev. 8 76 Freescale Semiconductor BAM tasks If any frame is received incorrectly, BAM code pushes device into static mode Censorship enabled, private password, BAM running serial boot mode Serial password received BAM writes received password to SSCM registers Upper 32-bits to SSCM_PWCMPH Lower 32-bits to SSCM_PWCMPL Start address and data length received Data download received and copied to SRAM BAM reads SSCM_STATUS[SEC] SSCM tasks SSCM compares registers to private password in flash SSCM_PWCMPH to NVPWD1 SSCM_PWCMPL to NVPWD0 If passwords match, un-censor device until next POR Update SSCM_STATUS[SEC] bit with censorship state No Is SEC bit Yes cleared ? BAM code pushes microcontroller into static mode BAM code transfers execution to user code in SRAM Figure 5-8. BAM serial boot mode flow for censorship enabled and private password With LINFlex, any receive error will result in static mode. With FlexCAN, the host will re-transmit data if there has been no acknowledgment from the microcontroller. However there could be a situation where the receiver configuration has an error which would result in static mode entry. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 77 NOTE In a censored device booting with serial boot mode, it is possible to read the content of the four 32-bit flash memory locations that make up the boot sector. For example, if the RCHW is stored at address 0x0000_0000, the reads at address 0x0000_0000, 0x0000_0004, 0x0000_0008 and 0x0000_000C will return a correct value. No other flash memory locations can be read. 5.2.1.4 Download start address, VLE bit and code size The next 8 bytes received by the microcontroller contain a 32-bit Start Address, the VLE mode bit and a 31-bit code Length as shown in Figure 5-9. START_ADDRESS[31:16] START_ADDRESS[15:0] VLE CODE_LENGTH[30:16] CODE_LENGTH[15:0] Figure 5-9. Start address, VLE bit and download size in bytes The VLE bit (Variable Length Instruction) is used to indicate whether the code to be downloaded is Book VLE or Book III-E. This device family supports only VLE = 1; the bit is used for backward compatibility. The Start Address defines where the received data will be stored and where the MCU will branch after the download is finished. The start address is 32-bit word aligned and the 2 least significant bits are ignored by the BAM code. NOTE The start address is configurable, but most not lie within the 0x4000_0000 to 0x4000_00FF address range. The Length defines how many data bytes have to be loaded. 5.2.1.5 Download data Each byte of data received is stored in the microcontroller’s SRAM, starting from the address specified in the previous protocol step. The address increments until the number of bytes of data received matches the number of bytes specified by the code length. Since the SRAM is protected by 32-bit wide Error Correction Code (ECC), the BAM code always writes bytes into SRAM grouped into 32-bit words. If the last byte received does not fall onto a 32-bit boundary, the BAM code fills any additional bytes with 0x0. MPC5604B/C Microcontroller Reference Manual, Rev. 8 78 Freescale Semiconductor Since the ECC on the SRAM has not been initialized (except for the bytes of data that have just been downloaded), an additional dummy word of 0x0000_0000 is written at the end of the downloaded data block to avoid any ECC errors during core prefetch. 5.2.1.6 Execute code The BAM code waits for the last data byte to be received. If the operating mode is censored with a private password, then the BAM reads the SSCM status register to determine whether the serial password matched the private password. If there was a password match then the BAM code restores the initial configuration and transfers execution to the downloaded code start address in SRAM. If the passwords did not match, the BAM code forces a static mode entry. NOTE The watchdog is disabled at the start of BAM code execution. In the case of an unexpected issue during BAM code execution, the microcontroller may be stalled and an external reset required to recover the microcontroller. 5.2.2 LINFlex (RS232) boot 5.2.2.1 Configuration Boot according to the LINFlex boot mode download protocol (see Section 5.2.2.2, Protocol) is performed by the LINFlex_0 module in UART (RS232) mode. Pins used are: • LIN0TX mapped on PB[2] • LIN0RX mapped on PB[3] Boot from LINFlex uses the system clock driven by the 4–16 MHz external crystal oscillator (FXOSC). The LINFlex controller is configured to operate at a baud rate = system clock frequency/833, using an 8-bit data frame without parity bit and 1 stop bit. Byte field Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Figure 5-10. LINFlex bit timing in UART mode 5.2.2.2 Protocol Table 5-8 summarizes the protocol and BAM action during this boot mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 79 Table 5-8. UART boot mode download protocol Protocol step Host sent message BAM response message Action 1 64-bit password (MSB first) 64-bit password Password checked for validity and compared against stored password. 2 32-bit store address 32-bit store address Load address is stored for future use. 3 VLE bit + 31-bit number of bytes (MSB first) VLE bit + 31-bit number of bytes (MSB first) Size of download are stored for future use. Verify if VLE bit is set to 1 4 8 bits of raw binary 8 bits of raw binary 8-bit data are packed into a 32-bit word. This word is data data saved into SRAM starting from the “Load address”. “Load address” increments until the number of data received and stored matches the size as specified in the previous step. 5 None None Branch to downloaded code 5.2.3 FlexCAN boot 5.2.3.1 Configuration Boot according to the FlexCAN boot mode download protocol (see Section 5.2.3.2, Protocol) is performed by the FlexCAN_0 module. Pins used are: • CAN0TX mapped on PB[0] • CAN0RX mapped on PB[1] NOTE When the serial download via FlexCAN is selected and the device is part of a CAN network, the serial download may stop unexpectedly if there is any other traffic on the network. To avoid this situation, ensure that no other CAN device on the network is active during the serial download process. Boot from FlexCAN uses the system clock driven by the 4–16 MHz fast external crystal oscillator. The FlexCAN controller is configured to operate at a baud rate = system clock frequency/40 (see Table 5-6 for examples of baud rate). It uses the standard 11-bit identifier format detailed in FlexCAN 2.0A specification. FlexCAN controller bit timing is programmed with 10 time quanta, and the sample point is 2 time quanta before the end, as shown in Figure 5-11. MPC5604B/C Microcontroller Reference Manual, Rev. 8 80 Freescale Semiconductor NRZ signal SYNC_SEG Time segment 1 Time segment 2 1 time quantum 7 time quanta 2 time quanta 1 bit time Transmit point Sample point 1 time quantum = 4 system clock periods Figure 5-11. FlexCAN bit timing 5.2.3.2 Protocol Table 5-9 summarizes the protocol and BAM action during this boot mode. All data are transmitted byte wise. Table 5-9. FlexCAN boot mode download protocol Protoco l Host sent message step BAM response message Action 1 CAN ID 0x011 + 64-bit password CAN ID 0x001 + 64-bit password Password checked for validity and compared against stored password 2 CAN ID 0x012 + CAN ID 0x002 + Load address is stored for future use. 32-bit store 32-bit store Size of download are stored for future use. address + VLE address + VLE Verify if VLE bit is set to 1 bit + 31-bit number of bit + 31-bit number of bytes bytes 3 CAN ID 0x013 + CAN ID 0x003 + 8-bit data are packed into 32-bit words. These words are 8 to 64 bits of raw 8 to 64 bits of raw saved into SRAM starting from the “Load address”. binary data binary data “Load address” increments until the number of data received and stored matches the size as specified in the previous step. 5 None None Branch to downloaded code MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 81 5.3 System Status and Configuration Module (SSCM) 5.3.1 Introduction The primary purpose of the SSCM is to provide information about the current state and configuration of the system that may be useful for configuring application software and for debug of the system. On microcontrollers with a separate STANDBY power domain, the System Status block is part of that domain. System Status and Configuration Module RevID Hardmacro Core Logic Bus Interface Peripheral Bus Interface System Status Password Comparator Figure 5-12. SSCM block diagram 5.3.2 Features The SSCM includes these features: • System Configuration and Status — Memory sizes/status — Microcontroller Mode and Security Status (including censorship and serial boot information) — Search Code Flash for bootable sector — Determine boot vector • Device identification information (MCU ID Registers) • Debug Status Port enable and selection • Bus and peripheral abort enable/disable MPC5604B/C Microcontroller Reference Manual, Rev. 8 82 Freescale Semiconductor 5.3.3 Modes of operation The SSCM operates identically in all system modes. 5.3.4 Memory map and register description Table 5-10 shows the memory map for the SSCM. Note that all addresses are offsets; the absolute address may be calculated by adding the specified offset to the base address of the SSCM. Table 5-10. SSCM memory map Address offset Register Location 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x10 System Status Register (SSCM_STATUS) System Memory Configuration Register (SSCM_MEMCONFIG) Reserved Error Configuration (SSCM_ERROR) Debug Status Port Register (SSCM_DEBUGPORT) Reserved Password Comparison Register High Word (SSCM_PWCMPH) Password Comparison Register Low Word (SSCM_PWCMPL) on page 83 on page 84 on page 85 on page 86 on page 87 on page 87 All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the SSCM_STATUS register is accessible by a 16-bit read/write to address ‘Base + 0x0002’, but performing a 16-bit access to ‘Base + 0x0003’ is illegal. 5.3.4.1 System Status Register (SSCM_STATUS) The System Status register is a read-only register that reflects the current state of the system. Offset:0x00 Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 PUB SEC 0 BMODE 0 0000 NXEN W Reset 0 0 0 0 0 0 0 0 0/1 0/1 0/1 0 0 0 0 0 Figure 5-13. System Status Register (SSCM_STATUS) Table 5-11. SSCM_STATUS allowed register accesses Access type 8-bit 16-bit 32-bit1 Read Write Allowed Not allowed Allowed Not allowed Allowed Not allowed MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 83 1 All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). Field NXEN PUB SEC BMODE Table 5-12. SSCM_STATUS field descriptions Description Nexus enabled Public Serial Access Status. This bit indicates whether serial boot mode with public password is allowed. 1 Serial boot mode with public password is allowed 0 Serial boot mode with private flash memory password is allowed Security Status. This bit reflects the current security state of the flash memory. 1 The flash memory is secured. 0 The flash memory is not secured. Device Boot Mode 000 Reserved 001 FlexCAN_0 Serial Boot Loader 010 LINFlex_0 Serial Boot Loader 011 Single Chip 100 Reserved 101 Reserved 110 Reserved 111 Reserved This field is only updated during reset. 5.3.4.2 System Memory Configuration Register (SSCM_MEMCONFIG) The System Memory Configuration register is a read-only register that reflects the memory configuration of the system. Offset: 0x02 Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 PRSZ PVLB DTSZ DVLD W Reset x x x x x x x x x x 1 x x x x 1 Figure 5-14. System Memory Configuration Register (SSCM_MEMCONFIG) MPC5604B/C Microcontroller Reference Manual, Rev. 8 84 Freescale Semiconductor Field PRSZ PVLB DTSZ DVLD Table 5-13. SSCM_MEMCONFIG field descriptions Description Code Flash Size 10000 128 KB 10001 256 KB 10010 384 KB 10011 512 KB Code Flash Available This bit identifies whether or not the on-chip code Flash is available in the system memory map. The Flash may not be accessible due to security limitations, or because there is no Flash in the system. 1 Code Flash is available 0 Code Flash is not available Data Flash Size 0000 No Data Flash 0011 64 KB Data Flash Valid This bit identifies whether or not the on-chip Data Flash is visible in the system memory map. The Flash may not be accessible due to security limitations, or because there is no Flash in the system. 1 Data Flash is visible 0 Data Flash is not visible Access type Read Write Table 5-14. SSCM_MEMCONFIG allowed register accesses 8-bit Allowed Not allowed 16-bit Allowed Not allowed 32-bit Allowed (also reads SSCM_STATUS register) Not allowed 5.3.4.3 Error Configuration (SSCM_ERROR) The Error Configuration register is a read-write register that controls the error handling of the system. Offset: 0x06 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAE RAE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-15. Error Configuration (SSCM_ERROR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 85 Field PAE RAE Table 5-15. SSCM_ERROR field descriptions Description Peripheral Bus Abort Enable This bit enables bus aborts on any access to a peripheral slot that is not used on the device. This feature is intended to aid in debugging when developing application code. 1 Illegal accesses to non-existing peripherals produce a Prefetch or Data Abort exception 0 Illegal accesses to non-existing peripherals do not produce a Prefetch or Data Abort exception Register Bus Abort Enable This bit enables bus aborts on illegal accesses to off-platform peripherals. Illegal accesses are defined as reads or writes to reserved addresses within the address space for a particular peripheral. This feature is intended to aid in debugging when developing application code. 1 Illegal accesses to peripherals produce a Prefetch or Data Abort exception 0 Illegal accesses to peripherals do not produce a Prefetch or Data Abort exception Transfers to Peripheral Bus resources may be aborted even before they reach the Peripheral Bus (that is, at the PBRIDGE level). In this case, bits PAE and RAE will have no effect on the abort. Table 5-16. SSCM_ERROR allowed register accesses Access type Read Write 8-bit Allowed Allowed 16-bit Allowed Allowed 32-bit Allowed Not allowed 5.3.4.4 Debug Status Port Register (SSCM_DEBUGPORT) The Debug Status Port register is used to (optionally) provide debug data on a set of pins. Offset: 0x08 0 R0 W Reset 0 Access: Read/write 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 000000000000 DEBUG_MODE 000000000000000 Figure 5-16. Debug Status Port Register (SSCM_DEBUGPORT) Table 5-17. SSCM_DEBUGPORT field descriptions Field Description DEBUG_MODE Debug Status Port Mode This field selects the alternate debug functionality for the Debug Status Port. 000 No alternate functionality selected 001 Mode 1 selected 010 Mode 2 selected 011 Mode 3 selected 100 Mode 4 selected 101 Mode 5 selected 110 Mode 6 selected 111 Mode 7 selected Table 5-18 describes the functionality of the Debug Status Port in each mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 86 Freescale Semiconductor Pin 1 Mode 1 Table 5-18. Debug status port modes Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 0 SSCM_STATUS SSCM_STATUS SSCM_MEMCONFI [0] [8] G[0] 1 SSCM_STATUS SSCM_STATUS SSCM_MEMCONFI [1] [9] G[1] 2 SSCM_STATUS SSCM_STATUS SSCM_MEMCONFI [2] [10] G[2] 3 SSCM_STATUS SSCM_STATUS SSCM_MEMCONFI [3] [11] G[3] 4 SSCM_STATUS SSCM_STATUS SSCM_MEMCONFI [4] [12] G[4] 5 SSCM_STATUS SSCM_STATUS SSCM_MEMCONFI [5] [13] G[5] 6 SSCM_STATUS SSCM_STATUS SSCM_MEMCONFI [6] [14] G[6] 7 SSCM_STATUS SSCM_STATUS SSCM_MEMCONFI [7] [15] G[7] 1 All signals are active high, unless otherwise noted SSCM_MEMCONFI G[8] SSCM_MEMCONFI G[9] SSCM_MEMCONFI G[10] SSCM_MEMCONFI G[11] SSCM_MEMCONFI G[12] SSCM_MEMCONFI G[13] SSCM_MEMCONFI G[14] SSCM_MEMCONFI G[15] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PIN[0..7] referred to in Table 5-18 equates to PC[2..9] (Pad 34..41). Table 5-19. SSCM_DEBUGPORT allowed register accesses Access type 8-bit 16-bit 32-bit1 Read Allowed Allowed Not allowed Write Allowed Allowed Not allowed 1 All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). 5.3.4.5 Password comparison registers These registers provide a means for the BAM code to unsecure the device via the SSCM if the password has been provided via serial download. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 87 Offset: 0x0C Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PWD_HI[31:16] Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PWD_HI[15:0] Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-17. Password Comparison Register High Word (SSCM_PWCMPH) Offset: 0x10 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PWD_LO[31:16] Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PWD_LO[15:0] Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-18. Password Comparison Register Low Word (SSCM_PWCMPL) Table 5-20. Password Comparison Register field descriptions Field PWD_HI PWD_LO Upper 32 bits of the password Lower 32 bits of the password Description Table 5-21. SSCM_PWCMPH/L allowed register accesses Access type 8-bit 16-bit 32-bit1 Read Allowed Allowed Allowed Write Not allowed Not allowed Allowed 1 All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). MPC5604B/C Microcontroller Reference Manual, Rev. 8 88 Freescale Semiconductor In order to unsecure the device, the password needs to be written as follows: first the upper word to the SSCM_PWCMPH register, then the lower word to the SSCM_PWCMPL register. The SSCM compares the 64-bit password entered into the SSCM_PWCMPH / SSCM_PWCMPL registers with the NVPWM[1,0] private password stored in the shadow flash. If the passwords match then the SSCM temporarily uncensors the microcontroller. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 89 MPC5604B/C Microcontroller Reference Manual, Rev. 8 90 Freescale Semiconductor ——— Clocks and power ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 91 MPC5604B/C Microcontroller Reference Manual, Rev. 8 92 Freescale Semiconductor Chapter 6 Clock Description This chapter describes the clock architectural implementation for MPC5604B. 6.1 Clock architecture System clocks are generated from three sources: • Fast external crystal oscillator 4-16 MHz (FXOSC) • Fast internal RC oscillator 16 MHz (FIRC) • Frequency modulated phase locked loop (FMPLL) Additionally, there are two low power oscillators: • Slow internal RC oscillator 128 kHz (SIRC) • Slow external crystal oscillator 32 KHz (SXOSC) The clock architecture is shown in Figure 6-1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 93 FXOSC ME__FIRCON FIRC ME__FXOSCON FXOSC (4–16 MHz) FIRC (16 MHz) /1 to /32 FXOSC_CTL[OSCDIV] /1 to /32 FIRC_TRIM[FIRCDIV] FXOSC_div FIRC_div FMPLL ME_[FMPLLON] & FMPLL_CR FMPLL (e.g. 64 MHz) SYSCLK System Clock Selector ME_ [SYSCLK] Clock Monitor Unit Reset Safe Interrupt Core Platform /1 to /16 CGM_SC_DC0 /1 to /16 CGM_SC_DC1 /1 to /16 CGM_SC_DC2 Peripheral Set 1 Peripheral Set 2 Peripheral Set 3 SXOSC SXOSC_CTL SXOSC (32 KHz) SIRC SIRC_CTL SIRC (128 kHz) /1 to /32 SXOSC_CTL[OSCDIV] /1 to /32 SIRC_CTL[SIRCDIV] SXOSC_div SIRC_clk_div FXOSC FIRC FMPLL CLKOUT Selector SXOSC_div FIRC_div SIRC_div API/RTC SIRC SWT /1, /2, /4, /8 CGM_OCDS_SC[SELDIV] CLKOUT (PA0) CGM_OCDS_SC[SELCTL] Figure 6-1. MPC5604B system clock generation 6.2 Clock gating The MPC5604B provides the user with the possibility of gating the clock to the peripherals. Table 6-1 describes for each peripheral the associated gating register address. See the ME_PCTLn section in this reference manual. Additionally, peripheral set (1, 2 or 3) frequency can be configured to be an integer (1 to 16) divided version of the main system clock. See the CGM_SC_DC0 section in this reference manual for details. Table 6-1. MPC5604B — Peripheral clock sources Peripheral RPP_Z0H Platform DSPI_n Register gating address offset (base = 0xC3FDC0C0)1 none (managed through ME mode) 4+n (n = 0..2) Peripheral set2 — 2 MPC5604B/C Microcontroller Reference Manual, Rev. 8 94 Freescale Semiconductor Table 6-1. MPC5604B — Peripheral clock sources (continued) Peripheral Register gating address offset (base = 0xC3FDC0C0)1 FlexCAN_n 16+n (n = 0..5) ADC 32 I2C 44 LINFLEX_n 48+n(n = 0..3) CTU 57 CANS 60 SIUL 68 WKUP 69 eMIOS_n 72+n (n = 0..1) RTC/API 91 PIT 92 CMU 104 1 See the ME_PCTL section in this reference manual for details. 2 “—” means undivided system clock. Peripheral set2 2 3 1 1 3 — — — 3 — — — 6.3 Fast external crystal oscillator (FXOSC) digital interface The FXOSC digital interface controls the operation of the 4–16 MHz fast external crystal oscillator (FXOSC). It holds control and status registers accessible for application. 6.3.1 Main features • Oscillator powerdown control and status reporting through MC_ME block • Oscillator clock available interrupt • Oscillator bypass mode • Output clock division factors ranging from 1, 2, 3....32 6.3.2 Functional description The FXOSC circuit includes an internal oscillator driver and an external crystal circuitry. It provides an output clock that can be provided to the FMPLL or used as a reference clock to specific modules depending on system needs. The FXOSC can be controlled by the MC_ME module. The ME_xxx_MC[FXOSCON] bit controls the powerdown of the oscillator based on the current device mode while ME_GS[S_XOSC] register provides the oscillator clock available status. After system reset, the oscillator is put into powerdown state and software has to switch on when required. Whenever the crystal oscillator is switched on from the off state, the OSCCNT counter starts and when it MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 95 reaches the value EOCV[7:0]×512, the oscillator clock is made available to the system. Also, an interrupt pending FXOSC_CTL[I_OSC] bit is set. An interrupt is generated if the interrupt mask bit M_OSC is set. The oscillator circuit can be bypassed by setting FXOSC_CTL[OSCBYP]. This bit can only be set by software. A system reset is needed to reset this bit. In this bypass mode, the output clock has the same polarity as the external clock applied on the EXTAL pin and the oscillator status is forced to ‘1’. The bypass configuration is independent of the powerdown mode of the oscillator. Table 6-2 shows the truth table of different oscillator configurations. Table 6-2. Truth table of crystal oscillator ME_xxx_MC[FXOSCON] FXOSC_CTL[OSCBYP ] XTAL EXTAL 0 0 No crystal, No crystal, High Z High Z x 1 x Ext clock FXOSC 0 EXTAL 1 0 Crystal Crystal EXTAL Gnd Ext clock EXTAL Oscillator mode Powerdown, IDDQ Bypass, OSC disabled Normal, OSC enabled Normal, OSC enabled The FXOSC clock can be further divided by a configurable factor in the range 1 to 32 to generate the divided clock to match system requirements. This division factor is specified by FXOSC_CTL[OSCDIV] field. 6.3.3 Register description Address: 0xC3FE_0000 Access: Special read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0000000 W EOCV OSCBYP1 RESET: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 I_OSC2 M_OSC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 00 W OSCDIV 0000000 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-2. Fast External Crystal Oscillator Control Register (FXOSC_CTL) 1 You can read this field, and you can write a value of “1” to it. Writing a “0” has no effect. A reset will also clear this bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 96 Freescale Semiconductor 2 You can write a value of "0" or "1" to this field. However, writing a "1" will clear this field, and writing "0" will have no effect on the field value. Field OSCBYP EOCV M_OSC OSCDIV I_OSC Table 6-3. FXOSC_CTL field descriptions Description Crystal Oscillator bypass. This bit specifies whether the oscillator should be bypassed or not. 0 Oscillator output is used as root clock 1 EXTAL is used as root clock End of Count Value. These bits specify the end of count value to be used for comparison by the oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state (OSCCNT runs on the FXOSC). This counting period ensures that external oscillator clock signal is stable before it can be selected by the system. When oscillator counter reaches the value EOCV × 512, the crystal oscillator clock interrupt (I_OSC) request is generated. The OSCCNT counter will be kept under reset if oscillator bypass mode is selected. Crystal oscillator clock interrupt mask. 0 Crystal oscillator clock interrupt is masked. 1 Crystal oscillator clock interrupt is enabled. Crystal oscillator clock division factor. This field specifies the crystal oscillator output clock division factor. The output clock is divided by the factor OSCDIV+1. Crystal oscillator clock interrupt. This bit is set by hardware when OSCCNT counter reaches the count value EOCV × 512. 0 No oscillator clock interrupt occurred. 1 Oscillator clock interrupt pending. 6.4 Slow external crystal oscillator (SXOSC) digital interface 6.4.1 Introduction The SXOSC digital interface controls the operation of the 32 KHz slow external crystal oscillator (SXOSC). It holds control and status registers accessible for application. 6.4.2 Main features • Oscillator powerdown control and status • Oscillator bypass mode • Output clock division factors ranging from 1 to 32 6.4.3 Functional description The SXOSC circuit includes an internal oscillator driver and an external crystal circuitry. It can be used as a reference clock to specific modules depending on system needs. The SXOSC can be controlled via the SXOSC_CTL register. The OSCON bit controls the powerdown while bit S_OSC provides the oscillator clock available status. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 97 After system reset, the oscillator is put to powerdown state and software has to switch on when required. Whenever the SXOSC is switched on from off state, the OSCCNT counter starts and when it reaches the value EOCV[7:0]×512, the oscillator clock is made available to the system. The oscillator circuit can be bypassed by writing SXOSC_CTL[OSCBYP] bit to ‘1’. This bit can only be set by software. A system reset is needed to reset this bit. In this bypass mode, the output clock has the same polarity as the external clock applied on the OSC32K_EXTAL pin and the oscillator status is forced to ‘1’. The bypass configuration is independent of the powerdown mode of the oscillator. Table 6-4 shows the truth table of different configurations of the oscillator. Table 6-4. SXOSC truth table SXOSC_CTL fields OSCON OSCBYP OSC32K_XTAL OSC32K_EXTAL 0 0 No crystal, High Z No crystal, High Z x 1 x External clock 1 0 Crystal Crystal Ground External clock SXOSC 0 OSC32K_EXTAL OSC32K_EXTAL OSC32K_EXTAL Oscillator MODE Powerdown, IDDQ Bypass, OSC disabled Normal, OSC enabled Normal, OSC enabled The SXOSC clock can be further divided by a configurable factor in the range 1 to 32 to generate the divided clock to match system requirements. This division factor is specified by SXOSC_CTL[OSCDIV] field. 6.4.4 Register description Address: 0xC3FE_0040 Access: Special read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0000000 W EOCV RESET: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 OSCBYP1 S_OSC OSCON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000 OSCDIV 000000 W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-3. Slow External Crystal Oscillator Control Register (SXOSC_CTL) 1 You can read this field, and you can write a value of “1” to it. Writing a “0” has no effect. A reset will also clear this bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 98 Freescale Semiconductor Table 6-5. SXOSC_CTL field descriptions Field OSCBYP EOCV OSCDIV S_OSC OSCON Description Crystal Oscillator bypass. This bit specifies whether the oscillator should be bypassed or not. 0 Oscillator output is used as root clock. 1 OSC32K_EXTAL is used as root clock. End of Count Value. This field specifies the end of count value to be used for comparison by the oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state. This counting period ensures that external oscillator clock signal is stable before it can be selected by the system. When oscillator counter reaches the value EOCV × 512, the crystal oscillator status (S_OSC) is set. The OSCCNT counter will be kept under reset if oscillator bypass mode is selected. Crystal oscillator clock division factor. This field specifies the crystal oscillator output clock division factor. The output clock is divided by the factor OSCDIV + 1. Crystal oscillator status. 0 Crystal oscillator output clock is not stable. 1 Crystal oscillator is providing a stable clock. Crystal oscillator enable. 0 Crystal oscillator is switched off. 1 Crystal oscillator is switched on. NOTE The 32 KHz slow external crystal oscillator is by default always ON, but can be configured OFF in standby by setting the OSCON bit. 6.5 Slow internal RC oscillator (SIRC) digital interface 6.5.1 Introduction The SIRC digital interface controls the 128 kHz slow internal RC oscillator (SIRC). It holds control and status registers accessible for application. 6.5.2 Functional description The SIRC provides a low frequency (fSIRC) clock of 128 kHz requiring very low current consumption. This clock can be used as the reference clock when a fixed base time is required for specific modules. SIRC is always on in all device modes except STANDBY mode. In STANDBY mode, it is controlled by SIRC_CTL[SIRCON_STDBY] bit. The clock source status is updated in SIRC_CTL[S_SIRC] bit. The SIRC clock can be further divided by a configurable division factor in the range from 1 to 32 to generate the divided clock to match system requirements. This division factor is specified by SIRC_CTL[SIRCDIV] bits. The SIRC output frequency can be trimmed using SIRC_CTL[SIRCTRIM]. After a power-on reset, the SIRC is trimmed using a factory test value stored in test flash memory. However, after a power-on reset MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 99 the test flash memory value is not visible at SIRC_CTL[SIRCTRIM] and this field shows a value of zero. Therefore, be aware that the SIRC_CTL[SIRCTRIM] does not reflect the current trim value until you have written to this field. Pay particular attention to this feature when you initiate a read-modify-write operation on SIRC_CTL, because a SIRCTRIM value of zero may be unintentionally written back and this may alter the SIRC frequency. In this case, you should calibrate the SIRC using the CMU or be sure that you only write to the upper 16 bits of this SIRC_CTL. In this oscillator, two's complement trimming method is implemented. So the trimming code increases from –16 to 15. As the trimming code increases, the internal time constant increases and frequency reduces. Please refer to device datasheet for average frequency variation of the trimming step. 6.5.3 Register description Address: 0xC3FE_0080 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 W SIRCTRIM RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S_SIRC SIRCON_STDBY 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000 000 000 SIRCDIV W RESET: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Figure 6-4. Low Power RC Control Register (SIRC_CTL) Table 6-6. SIRC_CTL field descriptions Field SIRCTRIM SIRCDIV Description SIRC trimming bits. This field corresponds (via two’s complement) to a trim factor of –16 to +15. A +1 change in SIRCTRIM decreases the current frequency by SIRCTRIM (see the device data sheet). A –1 change in SIRCTRIM increases the current frequency by SIRCTRIM (see the device data sheet). SIRC clock division factor. This field specifies the SIRC oscillator output clock division factor. The output clock is divided by the factor SIRCDIV+1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 100 Freescale Semiconductor Table 6-6. SIRC_CTL field descriptions (continued) Field Description S_SIRC SIRC clock status. 0 SIRC is not providing a stable clock. 1 SIRC is providing a stable clock. SIRCON_STDBY SIRC control in STANDBY mode. 0 SIRC is switched off in STANDBY mode. 1 SIRC is switched on in STANDBY mode. 6.6 Fast internal RC oscillator (FIRC) digital interface 6.6.1 Introduction The FIRC digital interface controls the 16 MHz fast internal RC oscillator (FIRC). It holds control and status registers accessible for application. 6.6.2 Functional description The FIRC provides a high frequency (fFIRC) clock of 16 MHz. This clock can be used to accelerate the exit from reset and wakeup sequence from low power modes of the system. It is controlled by the MC_ME module based on the current device mode. The clock source status is updated in ME_GS[S_RC]. Please refer to the MC_ME chapter for further details. The FIRC can be further divided by a configurable division factor in the range from 1 to 32 to generate the divided clock to match system requirements. This division factor is specified by RC_CTL[RCDIV] bits. The FIRC output frequency can be trimmed using FIRC_CTL[FIRCTRIM]. After a power-on reset, the FIRC is trimmed using a factory test value stored in test flash memory. However, after a power-on reset the test flash memory value is not visible at FIRC_CTL[FIRCTRIM], and this field will show a value of zero. Therefore, be aware that the FIRC_CTL[FIRCTRIM] field does not reflect the current trim value until you have written to it. Pay particular attention to this feature when you initiate a read-modify-write operation on FIRC_CTL, because a FIRCTRIM value of zero may be unintentionally written back and this may alter the FIRC frequency. In this case, you should calibrate the FIRC using the CMU or ensure that you write only to the upper 16 bits of this FIRC_CTL. In this oscillator, two's complement trimming method is implemented. So the trimming code increases from –32 to 31. As the trimming code increases, the internal time constant increases and frequency reduces. Please refer to device datasheet for average frequency variation of the trimming step. During STANDBY mode entry process, the FIRC is controlled based on ME_STANDBY_MC[RCON] bit. This is the last step in the standby entry sequence. On any system wake-up event, the device exits STANDBY mode and switches on the FIRC. The actual powerdown status of the FIRC when the device is in standby is provided by RC_CTL[FIRCON_STDBY] bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 101 6.6.3 Register description Address: 0xC3FE_0060 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 W FIRCTRIM RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 W FIRCDIV 00000000 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-5. FIRC Oscillator Control Register (FIRC_CTL) Table 6-7. FIRC_CTL field descriptions Field FIRCTRIM FIRCDIV Description FIRC trimming bits. This field corresponds (via two’s complement) to a trim factor of –16 to +15. A +1 change in FIRCTRIM decreases the current frequency by FIRCTRIM (see the device data sheet). A –1 change in SIRCTRIM increases the current frequency by FIRCTRIM (see the device data sheet). FIRC clock division factor. This field specifies the FIRC oscillator output clock division factor. The output clock is divided by the factor FIRCDIV+1. 6.7 Frequency-modulated phase-locked loop (FMPLL) 6.7.1 Introduction This section describes the features and functions of the FMPLL module implemented in the device. 6.7.2 Overview The FMPLL enables the generation of high speed system clocks from a common 4–16 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor and output clock divider ratio are all software configurable. MPC5604B has one FMPLL that can generate the system clock and takes advantage of the FM mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 102 Freescale Semiconductor NOTE The user must take care not to program device with a frequency higher than allowed (no hardware check). The FMPLL block diagram is shown in Figure 6-6. FXOSC IDF BUFFER Charge Pump Low Pass Filter VCO NDIV Loop Frequency Divider Figure 6-6. FMPLL block diagram PHI ODF 6.7.3 Features The FMPLL has the following major features: • Input clock frequency 4 MHz – 16 MHz • Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz • Frequency divider (FD) for reduced frequency operation without forcing the FMPLL to relock • Frequency modulated FMPLL — Modulation enabled/disabled through software — Triangle wave modulation • Programmable modulation depth — ±0.25% to ±4% deviation from center spread frequency1 — 0.5% to +8% deviation from down spread frequency — Programmable modulation frequency dependent on reference frequency • Self-clocked mode (SCM) operation • 4 available modes — Normal mode — Progressive clock switching — Normal mode with frequency modulation — Powerdown mode 6.7.4 Memory map2 Table 6-8 shows the memory map of the FMPLL. 1. Spread spectrum should be programmed in line with maximum datasheet frequency figures. 2. FMPLL_x are mapped through the ME_CGM register slot MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 103 Address offset 0x0 0x4 Table 6-8. FMPLL memory map Base address: 0xC3FE_00A0 Register Control Register (CR) Modulation Register (MR) Location on page 104 on page 106 6.7.5 Register description The FMPLL operation is controlled by two registers. Those registers can be accessed and written in supervisor mode only. 6.7.5.1 Control Register (CR) Offset: 0x0 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 IDF W 0 ODF NDIV Reset 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0000000 0 0 1 EN_PLL_SW UNLOCK_ONCE I_LOCK S_LOCK PLL_FAIL_MASK PLL_FAIL_FLAG W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 6-7. Control Register (CR) Table 6-9. CR field descriptions Field IDF ODF NDIV EN_PLL_SW Description The value of this field sets the FMPLL input division factor as described in Table 6-10. The value of this field sets the FMPLL output division factor as described in Table 6-11. The value of this field sets the FMPLL loop division factor as described in Table 6-12. This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially is divided by 8, and then progressively decreases until it reaches divide-by-1. 0 Progressive clock switching disabled. 1 Progressive clock switching enabled. Note: Progressive clock switching should not be used if a non-changing clock is needed, such as for serial communications, until the division has finished. MPC5604B/C Microcontroller Reference Manual, Rev. 8 104 Freescale Semiconductor Table 6-9. CR field descriptions (continued) Field Description UNLOCK_ONCE This bit is a sticking indication of FMPLL loss of lock condition. UNLOCK_ONCE is set when the FMPLL loses lock. Whenever the FMPLL reacquires lock, UNLOCK_ONCE remains set. Only a power-on reset clears this bit. I_LOCK This bit is set by hardware whenever there is a lock/unlock event. S_LOCK This bit is an indication of whether the FMPLL has acquired lock. 0: FMPLL unlocked 1: FMPLL locked Note: PLL_FAIL_MASK This bit is used to mask the pll_fail output. 0 pll_fail not masked. 1 pll_fail masked. PLL_FAIL_FLAG This bit is asynchronously set by hardware whenever a loss of lock event occurs while FMPLL is switched on. It is cleared by software writing ‘1’. Table 6-10. Input divide ratios IDF[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Input divide ratios Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10 Divide by 11 Divide by 12 Divide by 13 Divide by 14 Divide by 15 Clock Inhibit MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 105 Table 6-11. Output divide ratios ODF[1:0] 00 01 10 11 Output divide ratios Divide by 2 Divide by 4 Divide by 8 Divide by 16 Table 6-12. Loop divide ratios NDIV[6:0] 0000000–0011111 0100000 0100001 0100010 ... 1011111 1100000 1100001–1111111 Loop divide ratios — Divide by 32 Divide by 33 Divide by 34 ... Divide by 95 Divide by 96 — 6.7.5.2 Modulation Register (MR) Offset: 0x4 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 W MOD_PERIOD STRB_BYPASS SPRD_SEL RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FM_EN 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R INC_STEP W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-8. Modulation Register (MR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 106 Freescale Semiconductor Table 6-13. MR field descriptions Field Description STRB_BYPASS Strobe bypass. The STRB_BYPASS signal is used to bypass the strobe signal used inside FMPLL to latch the correct values for control bits (INC_STEP, MOD_PERIOD and SPRD_SEL). 0 Strobe is used to latch FMPLL modulation control bits 1 Strobe is bypassed. In this case control bits need to be static. The control bits must be changed only when FMPLL is in powerdown mode. SPRD_SEL Spread type selection. The SPRD_SEL controls the spread type in Frequency Modulation mode. 0 Center SPREAD 1 Down SPREAD MOD_PERIOD Modulation period. The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following formula: modperiod= -------f--r--e--f-----4  fmod where: fref: represents the frequency of the feedback divider fmod: represents the modulation frequency FM_EN Frequency Modulation Enable. The FM_EN enables the frequency modulation. 0 Frequency modulation disabled 1 Frequency modulation enabled INC_STEP Increment step. The INC_STEP field is the binary equivalent of the value incstep derived from following formula: incstep = round1---0---2-0---1--5----–5----1-----M------O-m---D--d---P----E--M--R----DI---O--F--D--- where: md: represents the peak modulation depth in percentage (Center spread -- pk-pk=+/-md, Downspread -- pk-pk=-2×md) MDF: represents the nominal value of loop divider (CR[NDIV]) 6.7.6 Functional description 6.7.6.1 Normal mode In Normal Mode the FMPLL inputs are driven by the CR. This means that, when the FMPLL is in lock state, the FMPLL output clock (PHI) is derived by the reference clock (XOSC) through this relation: phi= c----lI--kD---i--Fn-------N-O----DD-----IF--V--- where the value of IDF, NDIV and ODF are set in the CR and can be derived from Table 6-10, Table 6-11 and Table 6-12. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 107 Table 6-14. FMPLL lookup table Crystal frequency FMPLL output (MHz) frequency (MHz) 8 32 64 80 16 32 64 80 40 32 64 80 CR field values IDF ODF NDIV 0 2 32 0 2 64 0 1 40 1 2 32 1 2 64 1 1 40 4 2 32 4 2 64 3 1 32 VCO frequency (MHz) 256 512 320 256 512 320 256 512 320 6.7.6.2 Progressive clock switching Progressive clock switching allows to switch the system clock to FMPLL output clock stepping through different division factors. This means that the current consumption gradually increases and, in turn, voltage regulator response is improved. This feature can be enabled by programming CR[EN_PLL_SW] bit. When enabled, the system clock is switched to divided PHI. The FMPLL_clk divider is then progressively decreased to the target divider as shown in Table 6-15. Table 6-15. Progressive clock switching on pll_select rising edge Number of FMPLL output clock cycles 8 16 32 onward FMPLL_clk frequency (FMPLL output clock frequency) (FMPLL output clock frequency)/8 (FMPLL output clock frequency)/4 (FMPLL output clock frequency)/2 FMPLL output clock frequency FMPLL output clock Division factors of 8, 4, 2 or 1 FMPLL_clk Figure 6-9. FMPLL output clock division flow during progressive switching MPC5604B/C Microcontroller Reference Manual, Rev. 8 108 Freescale Semiconductor 6.7.6.3 Normal mode with frequency modulation The FMPLL default mode is without frequency modulation enabled. When frequency modulation is enabled, however, two parameters must be set to generate the desired level of modulation: the PERIOD, and the STEP. The modulation waveform is always a triangle wave and its shape is not programmable. FM mode is activated in two steps: 1. Configure the FM mode characteristics: MOD_PERIOD, INC_STEP. 2. Enable the FM mode by programming bit FM_EN of the MR to ‘1’. FM mode can only be enabled when FMPLL is in lock state. There are two ways to latch these values inside the FMPLL, depending on the value of bit STRB_BYPASS in the MR. If STRB_BYPASS is low, the modulation parameters are latched in the FMPLL only when the strobe signal goes high for at least two cycles of CLKIN clock. The strobe signal is automatically generated in the FMPLL digital interface when the modulation is enabled (FM_EN goes high) if the FMPLL is locked (S_LOCK = 1) or when the modulation has been enabled (FM_EN = 1) and FMPLL enters lock state (S_LOCK goes high). If STRB_BYPASS is high, the strobe signal is bypassed. In this case, control bits (MOD_PERIOD[12:0], INC_STEP[14:0], SPREAD_CONTROL) need to be static or hardwired to constant values. The control bits must be changed only when the FMPLL is in powerdown mode. The modulation depth in % is ModulationDepth =   1---0---0----------5---------I--N--2---1C--5--S--–--T---1-E----P----x--M-M-----D-O----F-D----P----E----R----I---O-----D-- NOTE The user must ensure that the product of INCTEP and MODPERIOD is less than (215-1). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 109 Figure 6-10. Frequency modulation 6.7.6.4 Powerdown mode To reduce consumption, the FMPLL can be switched off when not required by programming the registers ME_x_MC on the MC_ME module. 6.7.7 Recommendations To avoid any unpredictable behavior of the FMPLL clock, it is recommended to follow these guidelines: • The FMPLL VCO frequency should reside in the range 256 MHz to 512 MHz. Care is required when programming the multiplication and division factors to respect this requirement. • The user must change the multiplication, division factors only when the FMPLL output clock is not selected as system clock. Use progressive clock switching if system clock changes are required while the PLL is being used as the system clock source. MOD_PERIOD, INC_STEP, SPREAD_SEL bits should be modified before activating the FM mode. Then strobe has to be generated to enable the new settings. If STRB_BYP is set to ‘1’ then MOD_PERIOD, INC_STEP and SPREAD_SEL can be modified only when FMPLL is in powerdown mode. • Use progressive clock switching (FMPLL output clock can be changed when it is the system clock, but only when using progressive clock switching). 6.8 Clock monitor unit (CMU) 6.8.1 Introduction The Clock Monitor Unit (CMU), also referred to as Clock Quality Checker or Clock Fault Detector, serves two purposes. The main task is to permanently supervise the integrity of the various clock sources, for example a crystal oscillator or FMPLL. In case the FMPLL leaves an upper or lower frequency boundary MPC5604B/C Microcontroller Reference Manual, Rev. 8 110 Freescale Semiconductor or the crystal oscillator fails it can detect and forward these kind of events towards the MC_ME and MC_CGM. The clock management unit in turn can then switch to a SAFE mode where it uses the default safe clock source (FIRC), reset the device or generate the interrupt according to the system needs. It can also monitor the external crystal oscillator clock, which must be greater than the internal RC clock divided by a division factor given by CMU_CSR[RCDIV], and generates a system clock transition request or an interrupt when enabled. The second task of the CMU is to provide a frequency meter, which allows to measure the frequency of one clock source vs. a reference clock. This is useful to allow the calibration of the on-chip RC oscillator(s), as well as being able to correct/calculate the time deviation of a counter which is clocked by the RC oscillator. 6.8.2 Main features • FIRC, SIRC, SXOSC oscillator frequency measurement using FXOSC as reference clock • External oscillator clock monitoring with respect to FIRC_clk/n clock • FMPLL clock frequency monitoring for a high and low frequency range with FIRC as reference clock • Event generation for various failures detected inside monitoring unit 6.8.3 Block diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 111 FIRC_clk SIRC_clk SXOSC_clk FIRC_clk FXOSC_clk CKSEL1[1:0] 00 01 10 11 MUX1 CMU_MDR Frequency Meter CMU_FDR FMPLL XOSC Supervisor FXOSC < FIRC / n CMU_HFREFR FMPLL > hfref OR FMPLL < lfref OLR_evt XXOSC ON/OFF From MC_ME FHH_FLL_OR_evt_a FMPLL ON/OFF From MC_ME CMU_LFREFR FMPLL Supervisor OLR_evt : It is the event signalling XOSC failure when asserted. When this signal is asserted, RGM may generate reset, interrupt or SAFE request based on the RGM configuration. FHH_FLL_OR_evt_a : It is the event signalling FMPLL failure when asserted. Based on the CMU_HFREFR and CMU_LFREFR configuration, if the FMPLL is greater than hign frequency range or less than the low frequency range configuration, this signal is generated. When this signal is asserted, RGM may generate reset, interrupt or SAFE request based on the RGM configuration. Figure 6-11. Clock Monitor Unit diagram 6.8.4 Functional description The clock and frequency names referenced in this block are defined as follows: • FXOSC_clk: clock coming from the fast external crystal oscillator MPC5604B/C Microcontroller Reference Manual, Rev. 8 112 Freescale Semiconductor • SXOSC_clk: clock coming from the slow external crystal oscillator • SIRC_clk: clock coming from the slow (low frequency) internal RC oscillator • FIRC_clk: clock coming from the fast (high frequency) internal RC oscillator • FMPLL_clk: clock coming from the FMPLL • fFXOSC_clk: frequency of fast external crystal oscillator clock • fSXOSC_clk: frequency of slow external crystal oscillator clock • fSIRC_clk: frequency of slow (low frequency) internal RC oscillator • fFIRC_clk: frequency of fast (high frequency) internal RC oscillator • fFMPLL_clk: frequency of FMPLL clock 6.8.4.1 Crystal clock monitor If fFXOSC_clk is less than fFIRC_clk divided by 2RCDIV bits of the CMU_CSR and the FXOSC_clk is ‘ON’ as signalled by the MC_ME then: • An event pending bit OLRI in CMU_ISR is set. • A failure event OLR is signalled to the MC_RGM which in turn can automatically switch to a safe fallback clock and generate an interrupt or reset. 6.8.4.2 FMPLL clock monitor The fFMPLL_clk can be monitored by programming bit CME of the CMU_CSR register to ‘1’. The FMPLL_clk monitor starts as soon as bit CME is set. This monitor can be disabled at any time by writing bit CME to ‘0’. If fFMPLL_clk is greater than a reference value determined by bits HFREF[11:0] of the CMU_HFREFR and the FMPLL_clk is ‘ON’, as signalled by the MC_ME, then: • An event pending bit FHHI in CMU_ISR is set. • A failure event is signalled to the MC_RGM which in turn can generate an interrupt or safe mode request or functional reset depending on the programming model. If fFMPLL_clk is less than a reference value determined by bits LFREF[11:0] of the CMU_LFREFR and the FMPLL_clk is ‘ON’, as signaled by the MC_ME, then: • An event pending bit FLLI in CMU_ISR is set. • A failure event FLL is signalled to the MC_RGM which in turn can generate an interrupt or safe mode request or functional reset depending on the programming model. NOTE The internal RC oscillator is used as reliable reference clock for the clock supervision. In order to avoid false events, proper programming of the dividers is required. These have to take into account the accuracy and frequency deviation of the internal RC oscillator. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 113 NOTE If PLL frequency goes out of range, the CMU shall generate FMPLL fll/fhh event. It takes approximately 5 s to generate this event. 6.8.4.3 Frequency meter The purpose of the frequency meter is twofold: • to measure the frequency of the oscillators SIRC, FIRC or SXOSC • to calibrate an internal RC oscillator (SIRC or FIRC) using a known frequency Hint: This value can then be stored into the flash so that application software can reuse it later on. The reference clock is always the FXOSC_clk. The frequency meter returns a precise value of frequencies fSXOSC_clk, fFIRC_clk or fSIRC_clk according to CKSEL1 bit value. The measure starts when bit SFM (Start Frequency Measure) in the CMU_CSR is set to ‘1’. The measurement duration is given by the CMU_MDR in numbers of clock cycles of the selected clock source with a width of 20 bits. Bit SFM is reset to ‘0’ by hardware once the frequency measurement is done and the count is loaded in the CMU_FDR. The frequency fx1 can be derived from the value loaded in the CMU_FDR as follows: fx = (fFXOSC × MD) / n where n is the value in the CMU_FDR and MD is the value in the CMU_MDR. Eqn. 6-1 The frequency meter by default evaluates fFIRC_clk, but software can swap to fSIRC_clk or fSXOSC_clk by programming the CKSEL bits in the CMU_CSR. 6.8.5 Memory map and register description The memory map of the CMU is shown in Table 6-16. Table 6-16. CMU memory map Base address: 0xC3FE_0100 Register name Control Status Register (CMU_CSR) Frequency Display Register (CMU_FDR) High Frequency Reference Register FMPLL (CMU_HFREFR) Low Frequency Reference Register FMPLL (CMU_LFREFR) Interrupt Status Register (CMU_ISR) Reserved Measurement Duration Register (CMU_MDR) Address offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Reset value Location 0x00000006 on page 115 0x00000000 on page 116 0x00000FFF on page 116 0x00000000 on page 117 0x00000000 on page 117 0x00000000 — 0x00000000 on page 118 1. x = FIRC,SIRC or SXOSC MPC5604B/C Microcontroller Reference Manual, Rev. 8 114 Freescale Semiconductor 6.8.5.1 Control Status Register (CMU_CSR) Offset: 0x00 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0000000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFM1 CME_A 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 00000 W CKSEL1 RCDIV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Figure 6-12. Control Status Register (CMU_CSR) 1 You can read this field, and you can write a value of "1" to it. Writing a "0" has no effect. A reset will also clear this bit. Field SFM CKSEL1 RCDIV CME_A Table 6-17. CMU_CSR field descriptions Description Start frequency measure. The software can only set this bit to start a clock frequency measure. It is reset by hardware when the measure is ready in the CMU_FDR register. 0 Frequency measurement completed or not yet started. 1 Frequency measurement not completed. Clock oscillator selection bit. CKSEL1 selects the clock to be measured by the frequency meter. 00 FIRC_clk selected. 01 SIRC_clk selected. 10 SXOSC_clk selected. 11 FIRC_clk selected. RC clock division factor . These bits specify the RC clock division factor. The output clock is FIRC_clk divided by the factor 2RCDIV. This output clock is used to compare with FXOSC_clk for crystal clock monitor feature.The clock division coding is as follows. 00 Clock divided by 1 (No division) 01 Clock divided by 2 10 Clock divided by 4 11 Clock divided by 8 FMPLL_0 clock monitor enable. 0 FMPLL_0 monitor disabled. 1 FMPLL_0 monitor enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 115 6.8.5.2 Frequency Display Register (CMU_FDR) Offset: 0x04 Access: Read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 FD[19:16] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R FD[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-13. Frequency Display Register (CMU_FDR) . Table 6-18. CMU_FDR field descriptions Field FD Description Measured frequency bits. This register displays the measured frequency fx with respect to fFXOSC. The measured value is given by the following formula: fx = (fFXOSC × MD) / n, where n is the value in CMU_FDR register. Note: x = FIRC, SIRC or SXOSC. 6.8.5.3 High Frequency Reference Register FMPLL (CMU_HFREFR) Offset: 0x08 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 W HFREF Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-14. High Frequency Reference Register FMPLL (CMU_HFREFR) Table 6-19. CMU_HFREFR field descriptions Field HFREF Description High Frequency reference value. This field determines the high reference value for the FMPLL clock. The reference value is given by: (HFREF  16) × (fFIRC  4). MPC5604B/C Microcontroller Reference Manual, Rev. 8 116 Freescale Semiconductor 6.8.5.4 Low Frequency Reference Register FMPLL (CMU_LFREFR) Offset: 0x0C Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 W LFREF Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-15. Low Frequency Reference Register FMPLL (CMU_LFREFR) Table 6-20. CMU_LFREFR field descriptions Field LFREF Description Low Frequency reference value. This field determines the low reference value for the FMPLL. The reference value is given by: (LFREF  16) × (fFIRC  4). 6.8.5.5 Interrupt Status Register (CMU_ISR) Offset: 0x10 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FHHI FLLI OLRI 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 W w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-16. Interrupt status register (CMU_ISR) Table 6-21. CMU_ISR field descriptions Field FHHI Description FMPLL clock frequency higher than high reference interrupt. This bit is set by hardware when fFMPLL_clk becomes higher than HFREF value and FMPLL_clk is ‘ON’ as signalled by the MC_ME. It can be cleared by software by writing ‘1’. 0 No FHH event. 1 FHH event is pending. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 117 FLLI OLRI Table 6-21. CMU_ISR field descriptions (continued) FMPLL clock frequency lower than low reference event. This bit is set by hardware when fFMPLL_clk becomes lower than LFREF value and FMPLL_clk is ‘ON’ as signalled by the MC_ME. It can be cleared by software by writing ‘1’. 0 No FLL event. 1 FLL event is pending. Oscillator frequency lower than RC frequency event. This bit is set by hardware when fFXOSC_clk is lower than FIRC_clk/2RCDIV frequency and FXOSC_clk is ‘ON’ as signalled by the MC_ME. It can be cleared by software by writing ‘1’. 0 No OLR event. 1 OLR event is pending. 6.8.5.6 Measurement Duration Register (CMU_MDR) Offset: 0x18 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 W MD[19:16] Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MD[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-17. Measurement Duration Register (CMU_MDR) Table 6-22. CMU_MDR field descriptions Field MD Description Measurement duration bits. This field displays the measurement duration in numbers of clock cycles of the selected clock source. This value is loaded in the frequency meter downcounter. When CMU_CSR[SFM] = 1, the downcounter starts counting. MPC5604B/C Microcontroller Reference Manual, Rev. 8 118 Freescale Semiconductor Chapter 7 Clock Generation Module (MC_CGM) 7.1 Overview The clock generation module (MC_CGM) generates reference clocks for all SoC blocks. The MC_CGM selects one of the system clock sources to supply the system clock. The MC_ME controls the system clock selection (see the MC_ME chapter for more details). A set of MC_CGM registers controls the clock dividers which are utilized for divided system and peripheral clock generation. The memory spaces of system and peripheral clock sources which have addressable memory spaces, are accessed through the MC_CGM memory space. The MC_CGM also selects and generates an output clock. Figure 7-1 depicts the MC_CGM block diagram. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 119 FIRC FXOSC FMPLL MC_CGM Registers Platform Interface System Clock Multiplexer/Divider Output Clock Selector/Divider MC_ME MC_RGM peripherals PA[0] core mapped peripherals Mapped Modules Interface Figure 7-1. MC_CGM Block Diagram 7.2 Features The MC_CGM includes the following features: • generates system and peripheral clocks • selects and enables/disables the system clock supply from system clock sources according to MC_ME control MPC5604B/C Microcontroller Reference Manual, Rev. 8 120 Freescale Semiconductor • contains a set of registers to control clock dividers for divided clock generation • supports multiple clock sources and maps their address spaces to its memory map • generates an output clock • guarantees glitch-less clock transitions when changing the system clock selection • supports 8-, 16- and 32-bit wide read/write accesses 7.3 Modes of Operation This section describes the basic functional modes of the MC_CGM. 7.3.1 Normal and Reset Modes of Operation During normal and reset modes of operation, the clock selection for the system clock is controlled by the MC_ME. 7.4 External Signal Description The MC_CGM delivers an output clock to the PA[0] pin for off-chip use and/or observation. 7.5 Memory Map and Register Definition Table 7-1. MC_CGM Register Description Address Name 0xC3FE_0370 CGM_OC_EN 0xC3FE_0374 CGM_OCDS_SC 0xC3FE_0378 CGM_SC_SS 0xC3FE_037C CGM_SC_DC0 0xC3FE_037D CGM_SC_DC1 0xC3FE_037E CGM_SC_DC2 Description Access Size Supervisor Location Output Clock Enable word Output Clock Division Select byte System Clock Select Status byte System Clock Divider Configuration 0 byte System Clock Divider Configuration 1 byte System Clock Divider Configuration 2 byte read/write read/write read read/write read/write read/write on page 126 on page 126 on page 127 on page 128 on page 128 on page 128 NOTE Any access to unused registers as well as write accesses to read-only registers will: • not change register content • cause a transfer error MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 121 Address 0xC3FE _0000 … 0xC3FE _001C 0xC3FE _0020 … 0xC3FE _003C 0xC3FE _0040 … 0xC3FE _005C 0xC3FE _0060 … 0xC3FE _007C 0xC3FE _0080 … 0xC3FE _009C 0xC3FE _00A0 … 0xC3FE _00BC 0xC3FE _00C0 … 0xC3FE _00DC 0xC3FE _00E0 … 0xC3FE _00FC 0xC3FE _0100 … 0xC3FE _011C Name Table 7-2. MC_CGM Memory Map 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FXOSC registers reserved SXOSC registers FIRC registers SIRC registers FMPLL registers reserved reserved CMU registers MPC5604B/C Microcontroller Reference Manual, Rev. 8 122 Freescale Semiconductor Address 0xC3FE _0120 … 0xC3FE _013C 0xC3FE _0140 … 0xC3FE _015C 0xC3FE _0160 … 0xC3FE _017C 0xC3FE _0180 … 0xC3FE _019C 0xC3FE _01A0 … 0xC3FE _01BC 0xC3FE _01C0 … 0xC3FE _01DC 0xC3FE _01E0 … 0xC3FE _01FC 0xC3FE _0200 … 0xC3FE _021C 0xC3FE _0220 … 0xC3FE _023C Name Table 7-2. MC_CGM Memory Map (continued) 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved reserved reserved reserved reserved reserved reserved reserved reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 123 Address 0xC3FE _0240 … 0xC3FE _025C 0xC3FE _0260 … 0xC3FD _C27C 0xC3FE _0280 … 0xC3FE _029C 0xC3FE _02A0 … 0xC3FE _02BC 0xC3FE _02C0 … 0xC3FE _02DC 0xC3FE _02E0 … 0xC3FE _02FC 0xC3FE _0300 … 0xC3FE _031C 0xC3FE _0320 … 0xC3FE _033C 0xC3FE _0340 … 0xC3FE _035C Name Table 7-2. MC_CGM Memory Map (continued) 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved reserved reserved reserved reserved reserved reserved reserved reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 124 Freescale Semiconductor Table 7-2. MC_CGM Memory Map (continued) Address 0xC3FE _0360 … 0xC3FE _036C Name 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved 0xC3FE CGM_OC_EN R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _0370 W R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN W 0xC3FE CGM_OCDS_ R 0 _0374 SC W 0 SELDIV SELCTL 00000000 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE CGM_SC_SS R 0 0 0 0 _0378 W SELSTAT 00000000 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W DE2 DE0 DE1 0xC3FE CGM_SC_DC R _037C 0…2 W 000 DIV0 000 DIV1 R 000 W DIV2 00000000 0xC3FE _0400 … 0xC3FE _3FFC reserved 7.5.1 Register Descriptions All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address 0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 125 7.5.1.1 Output Clock Enable Register (CGM_OC_EN) Address 0xC3FE_0370 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7-2. Output Clock Enable Register (CGM_OC_EN) This register is used to enable and disable the output clock. Table 7-3. Output Clock Enable Register (CGM_OC_EN) Field Descriptions Field EN Output Clock Enable control 0 Output Clock is disabled 1 Output Clock is enabled Description 7.5.1.2 Output Clock Division Select Register (CGM_OCDS_SC) Address 0xC3FE_0374 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 SELDIV W SELCTL 00000000 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7-3. Output Clock Division Select Register (CGM_OCDS_SC) This register is used to select the current output clock source and by which factor it is divided before being delivered at the output clock. MPC5604B/C Microcontroller Reference Manual, Rev. 8 126 Freescale Semiconductor Table 7-4. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions Field Description SELDIV Output Clock Division Select 00 output selected Output Clock without division 01 output selected Output Clock divided by 2 10 output selected Output Clock divided by 4 11 output selected Output Clock divided by 8 SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock. 0000 4-16 MHz ext. xtal osc. 0001 16 MHz int. RC osc. 0010 freq. mod. PLL 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 7.5.1.3 System Clock Select Status Register (CGM_SC_SS) Address 0xC3FE_0378 Access: Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 SELSTAT 00000000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7-4. System Clock Select Status Register (CGM_SC_SS) This register provides the current clock source selection for the following clocks: • undivided: system clock • divided by system clock divider 0: peripheral set 1 clock • divided by system clock divider 1: peripheral set 2 clock • divided by system clock divider 2: peripheral set 3 clock See Figure 7-6 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 127 Table 7-5. System Clock Select Status Register (CGM_SC_SS) Field Descriptions Field Description SELSTAT System Clock Source Selection Status — This value indicates the current source for the system clock. 0000 16 MHz int. RC osc. 0001 div. 16 MHz int. RC osc. 0010 4-16 MHz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. PLL 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled 7.5.1.4 System Clock Divider Configuration Registers (CGM_SC_DC0…2) Address 0xC3FE_037C Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000 DE0 W DIV0 000 DE1 DIV1 Reset 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000 DE2 W DIV2 00000000 Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7-5. System Clock Divider Configuration Registers (CGM_SC_DC0…2) These registers control the system clock dividers. Table 7-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2) Field Descriptions Field Description DE0 DIV0 DE1 Divider 0 Enable 0 Disable system clock divider 0 1 Enable system clock divider 0 Divider 0 Division Value — The resultant peripheral set 1 clock will have a period DIV0 + 1 times that of the system clock. If the DE0 is set to ‘0’ (Divider 0 is disabled), any write access to the DIV0 field is ignored and the peripheral set 1 clock remains disabled. Divider 1 Enable 0 Disable system clock divider 1 1 Enable system clock divider 1 MPC5604B/C Microcontroller Reference Manual, Rev. 8 128 Freescale Semiconductor Table 7-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2) Field Descriptions (continued) Field Description DIV1 DE2 DIV2 Divider 1 Division Value — The resultant peripheral set 2 clock will have a period DIV1 + 1 times that of the system clock. If the DE1 is set to ‘0’ (Divider 1 is disabled), any write access to the DIV1 field is ignored and the peripheral set 2 clock remains disabled. Divider 2 Enable 0 Disable system clock divider 2 1 Enable system clock divider 2 Divider 2 Division Value — The resultant peripheral set 3 clock will have a period DIV2 + 1 times that of the system clock. If the DE2 is set to ‘0’ (Divider 2 is disabled), any write access to the DIV2 field is ignored and the peripheral set 3 clock remains disabled. 7.6 Functional Description 7.6.1 System Clock Generation Figure 7-6 shows the block diagram of the system clock generation logic. The MC_ME provides the system clock select and switch mask (see MC_ME chapter for more details), and the MC_RGM provides the safe clock request (see MC_RGM chapter for more details). The safe clock request forces the selector to select the 16 MHz int. RC osc. as the system clock and to ignore the system clock select. 7.6.1.1 System Clock Source Selection During normal operation, the system clock selection is controlled • on a SAFE mode or reset event, by the MC_RGM • otherwise, by the MC_ME 7.6.1.2 System Clock Disable During normal operation, the system clock can be disabled by the MC_ME. 7.6.1.3 System Clock Dividers The MC_CGM generates three derived clocks from the system clock. 7.6.1.4 Dividers Functional Description Dividers are utilized for the generation of divided system and peripheral clocks. The MC_CGM has the following control registers for built-in dividers: • Section 7.5.1.4, “System Clock Divider Configuration Registers (CGM_SC_DC0…2) The reset value of all counters is ‘1’. If a divider has its DE bit in the respective configuration register set to ‘0’ (the divider is disabled), any value in its DIVn field is ignored. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 129 16 MHz int. RC osc. div. 16 MHz int. RC osc. 4-16 MHz ext. xtal osc. div. ext. xtal osc. freq. mod. PLL system clock is disabled if 0 ME__MC.SYSCLK = “1111” 1 2 3 4 ’0’ 1 system clock 0 CGM_SC_DC0 Register MC_RGM safe clock request MC_ME clock select CGM_SC_SS Register clock divider peripheral set 1 clock CGM_SC_DC1 Register clock divider peripheral set 2 clock CGM_SC_DC2 Register clock divider peripheral set 3 clock Figure 7-6. MC_CGM System Clock Generation Overview 7.6.2 Output Clock Multiplexing The MC_CGM contains a multiplexing function for a number of clock sources which can then be utilized as output clock sources. The selection is done via the CGM_OCDS_SC register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 130 Freescale Semiconductor 4-16 MHz ext. xtal osc. 0 16 MHz int. RC osc. 1 freq. mod. PLL 2 CGM_OC_EN Register 3 2 ’0’ 1 0 PA[0] CGM_OCDS_SC.SELCTL Register CGM_OCDS_SC.SELDIV Register Figure 7-7. MC_CGM Output Clock Multiplexer and PA[0] Generation 7.6.3 Output Clock Division Selection The MC_CGM provides the following output signals for the output clock generation: • PA[0] (see Figure 7-7). This signal is generated by utilizing one of the 3-stage ripple counter outputs or the selected signal without division. The non-divided signal is not guaranteed to be 50% duty cycle by the MC_CGM. • the MC_CGM also has an output clock enable register (see Section 7.5.1.1, “Output Clock Enable Register (CGM_OC_EN)) which contains the output clock enable/disable control bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 131 MPC5604B/C Microcontroller Reference Manual, Rev. 8 132 Freescale Semiconductor Chapter 8 Mode Entry Module (MC_ME) 8.1 Introduction 8.1.1 Overview The MC_ME controls the SoC mode and mode transition sequences in all functional states. It also contains configuration, control and status registers accessible for the application. Figure 8-1 depicts the MC_ME block diagram. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 133 VREG Flashes FIRC FXOSC FMPLL MC_ME Registers Platform Interface MC_PCU MC_RGM MC_CGM Device Mode State Machine core peripherals WKPU Figure 8-1. MC_MEBlock Diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 134 Freescale Semiconductor 8.1.2 Features The MC_ME includes the following features: • control of the available modes by the ME_ME register • definition of various device mode configurations by the ME__MC registers • control of the actual device mode by the ME_MCTL register • capture of the current mode and various resource status within the contents of the ME_GS register • optional generation of various mode transition interrupts • status bits for each cause of invalid mode transitions • peripheral clock gating control based on the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers • capture of current peripheral clock gated/enabled status 8.1.3 Modes of Operation The MC_ME is based on several device modes corresponding to different usage models of the device. Each mode is configurable and can define a policy for energy and processing power management to fit particular system requirements. An application can easily switch from one mode to another depending on the current needs of the system. The operating modes controlled by the MC_ME are divided into system and user modes. The system modes are modes such as RESET, DRUN, SAFE, and TEST. These modes aim to ease the configuration and monitoring of the system. The user modes are modes such as RUN0…3, HALT, STOP, and STANDBY which can be configured to meet the application requirements in terms of energy management and available processing power. The modes DRUN, SAFE, TEST, and RUN0…3 are the device software running modes. Table 8-1 describes the MC_ME modes. Table 8-1. MC_ME Mode Descriptions Name RESET DRUN Description Entry Exit This is a chip-wide virtual mode during which the application is not active. The system remains in this mode until all resources are available for the embedded software to take control of the device. It manages hardware initialization of chip configuration, voltage regulators, oscillators, PLLs, and flash modules. system reset assertion from MC_RGM system reset deassertion from MC_RGM This is the entry mode for the embedded software. It provides full accessibility to the system and enables the configuration of the system at startup. It provides the unique gate to enter USER modes. BAM when present is executed in DRUN mode. system reset deassertion from MC_RGM, software request from SAFE, TEST and RUN0…3, wakeup request from STANDBY system reset assertion, RUN0…3, TEST, STANDBY via software, SAFE via software or hardware failure. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 135 Table 8-1. MC_ME Mode Descriptions (continued) Name Description Entry Exit SAFE TEST RUN0…3 HALT STOP STANDBY This is a chip-wide service mode which may be entered on the detection of a recoverable error. It forces the system into a pre-defined safe configuration from which the system may try to recover. hardware failure, software request from DRUN, TEST, and RUN0…3 system reset assertion, DRUN via software This is a chip-wide service mode which is intended to provide a control environment for device self-test. It may enable the application to run its own self-test like flash checksum, memory BIST etc. software request from DRUN system reset assertion, DRUN via software These are software running modes where most processing activity is done. These various run modes allow to enable different clock & power configurations of the system with respect to each other. software request from DRUN, interrupt event from HALT, interrupt or wakeup event from STOP system reset assertion, SAFE via software or hardware failure, other RUN0…3 modes, HALT, STOP, STANDBY via software This is a reduced-activity low-power mode during which the clock to the core is disabled. It can be configured to switch off analog peripherals like PLL, flash, main regulator etc. for efficient power management at the cost of higher wakeup latency. software request from RUN0…3 system reset assertion, SAFE on hardware failure, RUN0…3 on interrupt event This is an advanced low-power mode during which the clock to the core is disabled. It may be configured to switch off most of the peripherals including oscillator for efficient power management at the cost of higher wakeup latency. software request from RUN0…3 system reset assertion, SAFE on hardware failure, RUN0…3 on interrupt event or wakeup event This is a reduced-leakage low-power mode during which power supply is cut off from most of the device. Wakeup from this mode takes a relatively long time, and content is lost or must be restored from backup. software request from RUN0…3, DRUN modes system reset assertion, DRUN on wakeup event 8.2 External Signal Description The MC_ME has no connections to any external pins. 8.3 Memory Map and Register Definition The MC_ME contains registers for: • mode selection and status reporting • mode configuration • mode transition interrupts status and mask control • scalable number of peripheral sub-mode selection and status reporting MPC5604B/C Microcontroller Reference Manual, Rev. 8 136 Freescale Semiconductor Table 8-2. MC_ME Register Description Address Name Description Access Size Location Supervisor 0xC3FD_C000 ME_GS 0xC3FD_C004 ME_MCTL 0xC3FD_C008 ME_ME 0xC3FD_C00C ME_IS 0xC3FD_C010 ME_IM 0xC3FD_C014 ME_IMTS 0xC3FD_C018 ME_DMTS 0xC3FD_C020 ME_RESET_MC 0xC3FD_C024 ME_TEST_MC 0xC3FD_C028 ME_SAFE_MC 0xC3FD_C02C ME_DRUN_MC 0xC3FD_C030 ME_RUN0_MC 0xC3FD_C034 ME_RUN1_MC 0xC3FD_C038 ME_RUN2_MC 0xC3FD_C03C ME_RUN3_MC 0xC3FD_C040 ME_HALT_MC 0xC3FD_C048 ME_STOP_MC 0xC3FD_C054 ME_STANDBY_MC 0xC3FD_C060 ME_PS0 0xC3FD_C064 ME_PS1 0xC3FD_C068 ME_PS2 0xC3FD_C06C ME_PS3 0xC3FD_C080 ME_RUN_PC0 0xC3FD_C084 ME_RUN_PC1 Global Status Mode Control Mode Enable Interrupt Status Interrupt Mask Invalid Mode Transition Status Debug Mode Transtion Status RESET Mode Configuration TEST Mode Configuration SAFE Mode Configuration DRUN Mode Configuration RUN0 Mode Configuration RUN1 Mode Configuration RUN2 Mode Configuration RUN3 Mode Configuration HALT Mode Configuration STOP Mode Configuration STANDBY Mode Configuration Peripheral Status 0 Peripheral Status 1 Peripheral Status 2 Peripheral Status 3 Run Peripheral Configuration 0 Run Peripheral Configuration 1 … word read word read/write word read/write word read/write word read/write word read/write word read word read word read/write word read/write word read/write word read/write word read/write word read/write word read/write word read/write word read/write word read/write word read word read word read word read word read/write word read/write on page 144 on page 146 on page 147 on page 149 on page 150 on page 151 on page 152 on page 154 on page 155 on page 155 on page 156 on page 157 on page 157 on page 157 on page 157 on page 157 on page 158 on page 158 on page 160 on page 161 on page 161 on page 162 on page 162 on page 162 0xC3FD_C09C ME_RUN_PC7 0xC3FD_C0A0 ME_LP_PC0 0xC3FD_C0A4 ME_LP_PC1 Run Peripheral Configuration 7 word Low-Power Peripheral Configuration word 0 Low-Power Peripheral Configuration word 1 … read/write read/write read/write on page 162 on page 163 on page 163 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 137 Table 8-2. MC_ME Register Description (continued) Address Name Description Access Size Location Supervisor 0xC3FD_C0BC ME_LP_PC7 0xC3FD_C0C4 ME_PCTL4 0xC3FD_C0C5 ME_PCTL5 0xC3FD_C0C6 ME_PCTL6 0xC3FD_C0D0 ME_PCTL16 0xC3FD_C0D1 ME_PCTL17 0xC3FD_C0D2 ME_PCTL18 0xC3FD_C0D3 ME_PCTL19 0xC3FD_C0D4 ME_PCTL20 0xC3FD_C0D5 ME_PCTL21 0xC3FD_C0E0 ME_PCTL32 0xC3FD_C0EC ME_PCTL44 0xC3FD_C0F0 ME_PCTL48 0xC3FD_C0F1 ME_PCTL49 0xC3FD_C0F2 ME_PCTL50 0xC3FD_C0F3 ME_PCTL51 0xC3FD_C0F9 ME_PCTL57 0xC3FD_C0FC ME_PCTL60 0xC3FD_C104 ME_PCTL68 0xC3FD_C105 ME_PCTL69 0xC3FD_C108 ME_PCTL72 0xC3FD_C109 ME_PCTL73 0xC3FD_C11B ME_PCTL91 0xC3FD_C11C ME_PCTL92 0xC3FD_C128 ME_PCTL104 Low-Power Peripheral Configuration word read/write 7 DSPI0 Control byte read/write DSPI1 Control byte read/write DSPI2 Control byte read/write FlexCAN0 Control byte read/write FlexCAN1 Control byte read/write FlexCAN2 Control byte read/write FlexCAN3 Control byte read/write FlexCAN4 Control byte read/write FlexCAN5 Control byte read/write ADC0 Control byte read/write I2C0 Control byte read/write LINFlex0 Control byte read/write LINFlex1 Control byte read/write LINFlex2 Control byte read/write LINFlex3 Control byte read/write CTU Control byte read/write CANSampler Control byte read/write SIUL Control byte read/write WKPU Control byte read/write eMIOS0 Control byte read/write eMIOS1 Control byte read/write RTC_API Control byte read/write PIT_RTI Control byte read/write CMU Control byte read/write on page 163 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 on page 164 NOTE Any access to unused registers as well as write accesses to read-only registers will: • not change register content • cause a transfer error MPC5604B/C Microcontroller Reference Manual, Rev. 8 138 Freescale Semiconductor Table 8-3. MC_ME Memory Map Address Name 0xC3FD ME_GS _C000 0 1 2 3 27 5 6 7 8 9 10 11 16 17 18 19 20 21 22 23 24 25 26 27 R S_CURRENT_MODE 00 00 12 13 14 15 28 29 30 31 S_DFLA S_CFLA S_PDO S_MVR S_MTRANS S_DC W S_FMPLL S_FXOSC S_FIRC R S_SYSCLK 0xC3FD ME_MCTL _C004 0xC3FD ME_ME _C008 W R 0000000 0 0 0 0 0 TARGET_MODE W R1 0 1 0 0101000 0 1 1 1 1 W KEY R0 0 0 0 0000000 0 0 0 0 0 W STANDBY R0 0 00 0 0xC3FD ME_IS _C00C W R0 0 0 0 0000000 0 0 0 0 0 W STOP HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET I_ICONF I_IMODE I_SAFE I_MTC R0 0 0 0 0000000 0 0xC3FD ME_IM _C010 0xC3FD ME_IMTS _C014 W w1c w1c w1c w1c R0 0 0 0 0000000 0 0 0 0 0 W R0 0 0 0 0000000 0 M_ICONF M_IMODE M_SAFE M_MTC W R0 0 0 0 0000000 0 0 0 0 0 W S_MTI S_MRI S_DMA S_NMA S_SEA R0 0 0 0 0000000 W w1c w1c w1c w1c w1c MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 139 Table 8-3. MC_ME Memory Map (continued) Address Name 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xC3FD ME_DMTS _C018 R0 0 0 0 0000 00 00 PMC_PROG CORE_DBG SMR MPH_BUSY W CDP_PRPH_96_127 CDP_PRPH_64_95 CDP_PRPH_32_63 CDP_PRPH_0_31 SYSCLK_SW DFLASH_SC CFLASH_SC CDP_PRPH_0_143 FMPLL_SC FXOSC_SC FIRC_SC R0 00 W 0xC3FD _C01C reserved 0xC3FD ME_RESET_ _C020 MC R0 0 0 0 0000 W 00 R W 0xC3FD ME_TEST_M _C024 C R0 0 0 0 0000 00 W R0 0 0 0 00000 W 0xC3FD ME_SAFE_M _C028 C R0 0 0 0 0000 00 PDO W R W FMPLLON FXOSCON FIRCON FMPLLON FXOSCON PDO MVRON FMPLLON FXOSCON FIRCON PDO MVRON MVRON FIRCON DFLAON CFLAON SYSCLK DFLAON CFLAON SYSCLK DFLAON CFLAON SYSCLK MPC5604B/C Microcontroller Reference Manual, Rev. 8 140 Freescale Semiconductor Table 8-3. MC_ME Memory Map (continued) Address Name 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xC3FD ME_DRUN_M _C02C C R0 0 0 0 0000 00 DFLAON CFLAON PDO MVRON W FIRCON FMPLLON FXOSCON R0 0 0 0 00000 W 0xC3FD ME_RUN0…3 _C030 _MC R0 0 0 0 0000 … 0xC3FD _C03C W PDO 00 R0 0 0 0 00000 W 0xC3FD ME_HALT_M R 0 0 0 0 0 0 0 0 _C040 C W 00 R0 0 0 0 00000 W 0xC3FD _C044 reserved 0xC3FD ME_STOP_M R 0 0 0 0 0 0 0 0 _C048 C W PDO 00 FMPLLON FXOSCON PDO FMPLLON FXOSCON FIRCON MVRON FIRCON MVRON SYSCLK DFLAON CFLAON SYSCLK DFLAON CFLAON SYSCLK DFLAON CFLAON FIRCON MVRON FMPLLON FXOSCON 0xC3FD _C04C … 0xC3FD _C050 R0 0 0 0 00000 W reserved SYSCLK MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 141 Table 8-3. MC_ME Memory Map (continued) Address Name 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xC3FD ME_STANDB _C054 Y_MC R0 0 0 0 0000 00 DFLAON CFLAON PDO MVRON W FMPLLON FXOSCON FIRCON R SYSCLK W 0xC3FD _C058 … 0xC3FD _C05C 0xC3FD ME_PS0 _C060 R reserved S_FlexCAN5 S_FlexCAN4 S_FlexCAN3 S_FlexCAN2 S_FlexCAN1 S_FlexCAN0 S_DSPI2 S_DSPI1 S_DSPI0 W R W 0xC3FD ME_PS1 _C064 R S_LINFlex3 S_LINFlex2 S_LINFlex1 S_LINFlex0 S_CTU S_CANSampler S_ADC0 S_I2C0 W R W MPC5604B/C Microcontroller Reference Manual, Rev. 8 142 Freescale Semiconductor Table 8-3. MC_ME Memory Map (continued) Address Name 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xC3FD ME_PS2 _C068 R S_PIT_RTI S_RTC_API S_eMIOS1 S_eMIOS0 S_WKPU S_SIUL W R W 0xC3FD ME_PS3 R _C06C W S_CMU R W 0xC3FD _C070 reserved 0xC3FD _C074 … 0xC3FD _C07C reserved 0xC3FD ME_RUN_PC R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _C080 0…7 … W 0xC3FD _C09C R0 0 0 0 0000 W 0xC3FD ME_LP_PC0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _C0A0 …7 … W 0xC3FD _C0BC R0 0 00 0 000 0 0 0 0 0 STOP HALT W RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET STANDBY MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 143 Table 8-3. MC_ME Memory Map (continued) DBG_F DBG_F DBG_F DBG_F Address Name 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xC3FD ME_PCTL0… R 0 _C0C0 143 … W 0xC3FD _C14C R0 W LP_CFG 0 RUN_CFG LP_CFG 0 RUN_CFG LP_CFG RUN_CFG LP_CFG RUN_CFG 0xC3FD _C150 … 0xC3FD _FFFC reserved 8.3.1 Register Description Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the ME_RUN_PC0 register may be accessed as a word at address 0xC3FD_C080, as a half-word at address 0xC3FD_C082, or as a byte at address 0xC3FD_C083. 8.3.1.1 Global Status Register (ME_GS) Address 0xC3FD_C000 Access: Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R S_CURRENT_MODE 00 00 S_DFLA S_CFLA S_PDO S_MVR S_MTRANS S_DC W Reset 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 S_FMPLL S_FXOSC S_FIRC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R S_SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 8-2. Global Status Register (ME_GS) This register contains global mode status. MPC5604B/C Microcontroller Reference Manual, Rev. 8 144 Freescale Semiconductor Table 8-4. Global Status Register (ME_GS) Field Descriptions Field Description S_CURREN T_MODE Current device mode status 0000 RESET 0001 TEST 0010 SAFE 0011 DRUN 0100 RUN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT 1001 reserved 1010 STOP 1011 reserved 1100 reserved 1101 STANDBY 1110 reserved 1111 reserved S_MTRANS Mode transition status 0 Mode transition process is not active 1 Mode transition is ongoing S_DC Device current consumption status 0 Device consumption is low enough to allow powering down of main voltage regulator 1 Device consumption requires main voltage regulator to remain powered regardless of mode configuration S_PDO Output power-down status — This bit specifies output power-down status of I/Os. This bit is asserted whenever outputs of pads are forced to high impedance state or the pads power sequence driver is switched off. 0 No automatic safe gating of I/Os used and pads power sequence driver is enabled 1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and pads power sequence driver is disabled. The inputs are level unchanged. In STOP mode, only pad power sequence driver is disabled but the state of the output is kept. In STANDBY mode, the power sequence driver and all pads except those mapped on wakeup lines are not powered and therefore high impedance. Wakeup lines configuration remains unchanged S_MVR Main voltage regulator status 0 Main voltage regulator is not ready 1 Main voltage regulator is ready for use S_DFLA Data flash availability status 00 Data flash is not available 01 Data flash is in power-down mode 10 Data flash is in low-power mode 11 Data flash is in normal mode and available for use S_CFLA Code flash availability status 00 Code flash is not available 01 Code flash is in power-down mode 10 Code flash is in low-power mode 11 Code flash is in normal mode and available for use S_FMPLL frequency modulated phase locked loop status 0 frequency modulated phase locked loop is not stable 1 frequency modulated phase locked loop is providing a stable clock MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 145 Table 8-4. Global Status Register (ME_GS) Field Descriptions (continued) Field Description S_FXOSC S_FIRC fast external crystal oscillator (4-16 MHz) status 0 fast external crystal oscillator (4-16 MHz) is not stable 1 fast external crystal oscillator (4-16 MHz) is providing a stable clock fast internal RC oscillator (16 MHz) status 0 fast internal RC oscillator (16 MHz) is not stable 1 fast internal RC oscillator (16 MHz) is providing a stable clock S_SYSCLK System clock switch status — These bits specify the system clock currently used by the system. 0000 16 MHz int. RC osc. 0001 div. 16 MHz int. RC osc. 0010 4-16 MHz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. PLL 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled 8.3.1.2 Mode Control Register (ME_MCTL) Address 0xC3FD_C004 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TARGET_MODE W 000000000000 Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 W KEY Reset 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 Figure 8-3. Mode Control Register (ME_MCTL) This register is used to trigger software-controlled mode changes. Depending on the modes as enabled by ME_ME register bits, configurations corresponding to unavailable modes are reserved and access to ME__MC registers must respect this for successful mode requests. MPC5604B/C Microcontroller Reference Manual, Rev. 8 146 Freescale Semiconductor NOTE Byte and half-word write accesses are not allowed for this register as a predefined key is required to change its value. Table 8-5. Mode Control Register (ME_MCTL) Field Descriptions Field Description TARGET_M ODE KEY Target device mode — These bits provide the target device mode to be entered by software programming. The mechanism to enter into any mode by software requires the write operation twice: first time with key, and second time with inverted key. These bits are automatically updated by hardware while entering SAFE on hardware request. Also, while exiting from the HALT and STOP modes on hardware exit events, these are updated with the appropriate RUN0…3 mode value. 0000 RESET 0001 TEST 0010 SAFE 0011 DRUN 0100 RUN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT 1001 reserved 1010 STOP 1011 reserved 1100 reserved 1101 STANDBY 1110 reserved 1111 reserved Control key — These bits enable write access to this register. Any write access to the register with a value different from the keys is ignored. Read access will always return inverted key. KEY: 0101101011110000 (0x5AF0) INVERTED KEY: 1010010100001111 (0xA50F) 8.3.1.3 Mode Enable Register (ME_ME) Address 0xC3FD_C008 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STANDBY STOP HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 00 00 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 Figure 8-4. Mode Enable Register (ME_ME) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 147 This register allows a way to disable the device modes which are not required for a given device. RESET, SAFE, DRUN, and RUN0 modes are always enabled. Table 8-6. Mode Enable Register (ME_ME) Field Descriptions Field STANDBY STOP HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET STANDBY mode enable 0 STANDBY mode is disabled 1 STANDBY mode is enabled STOP mode enable 0 STOP mode is disabled 1 STOP mode is enabled HALT mode enable 0 HALT mode is disabled 1 HALT mode is enabled RUN3 mode enable 0 RUN3 mode is disabled 1 RUN3 mode is enabled RUN2 mode enable 0 RUN2 mode is disabled 1 RUN2 mode is enabled RUN1 mode enable 0 RUN1 mode is disabled 1 RUN1 mode is enabled RUN0 mode enable 0 RUN0 mode is disabled 1 RUN0 mode is enabled DRUN mode enable 0 DRUN mode is disabled 1 DRUN mode is enabled SAFE mode enable 0 SAFE mode is disabled 1 SAFE mode is enabled TEST mode enable 0 TEST mode is disabled 1 TEST mode is enabled RESET mode enable 0 RESET mode is disabled 1 RESET mode is enabled Description MPC5604B/C Microcontroller Reference Manual, Rev. 8 148 Freescale Semiconductor 8.3.1.4 Interrupt Status Register (ME_IS) Address 0xC3FD_C00C Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I_ICONF I_IMODE I_SAFE I_MTC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000000000000 W w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-5. Interrupt Status Register (ME_IS) This register provides the current interrupt status. Table 8-7. Interrupt Status Register (ME_IS) Field Descriptions Field I_ICONF I_IMODE I_SAFE I_MTC Description Invalid mode configuration interrupt — This bit is set whenever a write operation to ME__MC registers with invalid mode configuration is attempted. It is cleared by writing a ‘1’ to this bit. 0 No invalid mode configuration interrupt occurred 1 Invalid mode configuration interrupt is pending Invalid mode interrupt — This bit is set whenever an invalid mode transition is requested. It is cleared by writing a ‘1’ to this bit. 0 No invalid mode interrupt occurred 1 Invalid mode interrupt is pending SAFE mode interrupt — This bit is set whenever the device enters SAFE mode on hardware requests generated in the system. It is cleared by writing a ‘1’ to this bit. 0 No SAFE mode interrupt occurred 1 SAFE mode interrupt is pending Mode transition complete interrupt — This bit is set whenever the mode transition process completes (S_MTRANS transits from 1 to 0). It is cleared by writing a ‘1’ to this bit. This mode transition interrupt bit will not be set while entering low-power modes HALT, STOP, or STANDBY. 0 No mode transition complete interrupt occurred 1 Mode transition complete interrupt is pending MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 149 8.3.1.5 Interrupt Mask Register (ME_IM) Address 0xC3FD_C010 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M_ICONF M_IMODE M_SAFE M_MTC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-6. Interrupt Mask Register (ME_IM) This register controls whether an event generates an interrupt or not. Table 8-8. Interrupt Mask Register (ME_IM) Field Descriptions Field M_ICONF M_IMODE M_SAFE M_MTC Description Invalid mode configuration interrupt mask 0 Invalid mode interrupt is masked 1 Invalid mode interrupt is enabled Invalid mode interrupt mask 0 Invalid mode interrupt is masked 1 Invalid mode interrupt is enabled SAFE mode interrupt mask 0 SAFE mode interrupt is masked 1 SAFE mode interrupt is enabled Mode transition complete interrupt mask 0 Mode transition complete interrupt is masked 1 Mode transition complete interrupt is enabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 150 Freescale Semiconductor 8.3.1.6 Invalid Mode Transition Status Register (ME_IMTS) Address 0xC3FD_C014 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S_MTI S_MRI S_DMA S_NMA S_SEA 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 00000000000 W Reset 0 w1c w1c w1c w1c w1c 000000000000000 Figure 8-7. Invalid Mode Transition Status Register (ME_IMTS) This register provides the status bits for each cause of invalid mode interrupt. Table 8-9. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions Field S_MTI S_MRI S_DMA S_NMA S_SEA Description Mode Transition Illegal status — This bit is set whenever a new mode is requested while some other mode transition process is active (S_MTRANS is ‘1’). Please refer to Section 8.4.5, “Mode Transition Interrupts for the exceptions to this behavior. It is cleared by writing a ‘1’ to this bit. 0 Mode transition requested is not illegal 1 Mode transition requested is illegal Mode Request Illegal status — This bit is set whenever the target mode requested is not a valid mode with respect to current mode. It is cleared by writing a ‘1’ to this bit. 0 Target mode requested is not illegal with respect to current mode 1 Target mode requested is illegal with respect to current mode Disabled Mode Access status — This bit is set whenever the target mode requested is one of those disabled modes determined by ME_ME register. It is cleared by writing a ‘1’ to this bit. 0 Target mode requested is not a disabled mode 1 Target mode requested is a disabled mode Non-existing Mode Access status — This bit is set whenever the target mode requested is one of those non existing modes determined by ME_ME register. It is cleared by writing a ‘1’ to this bit. 0 Target mode requested is an existing mode 1 Target mode requested is a non-existing mode SAFE Event Active status — This bit is set whenever the device is in SAFE mode, SAFE event bit is pending and a new mode requested other than RESET/SAFE modes. It is cleared by writing a ‘1’ to this bit. 0 No new mode requested other than RESET/SAFE while SAFE event is pending 1 New mode requested other than RESET/SAFE while SAFE event is pending MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 151 8.3.1.7 Debug Mode Transition Status Register (ME_DMTS) Address 0xC3FD_C018 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 00000000 00 00 PMC_PROG CORE_DBG SMR MPH_BUSY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 000 CDP_PRPH_96_127 CDP_PRPH_64_95 CDP_PRPH_32_63 CDP_PRPH_0_31 FMPLL_SC FXOSC_SC FIRC_SC SYSCLK_SW DFLASH_SC CFLASH_SC CDP_PRPH_0_143 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-8. Debug Mode Transition Status Register (ME_DMTS) This register provides the status of different factors which influence mode transitions. It is used to give an indication of why a mode transition indicated by ME_GS.S_MTRANS may be taking longer than expected. NOTE The ME_DMTS register does not indicate whether a mode transition is ongoing. Therefore, some ME_DMTS bits may still be asserted after the mode transition has completed. Table 8-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions Field Description MPH_BUSY MC_ME/MC_PCU Handshake Busy indicator — This bit is set if the MC_ME has requested a mode change from the MC_PCU and the MC_PCU has not yet responded. It is cleared when the MC_PCU has responded. 0 Handshake is not busy 1 Handshake is busy PMC_PROG MC_PCU Mode Change in Progress indicator — This bit is set if the MC_PCU is in the process of powering up or down power domains. It is cleared when all power-up/down processes have completed. 0 Power-up/down transition is not in progress 1 Power-up/down transition is in progress MPC5604B/C Microcontroller Reference Manual, Rev. 8 152 Freescale Semiconductor Table 8-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued) Field Description CORE_DBG Processor is in Debug mode indicator — This bit is set while the processor is in debug mode. 0 The processor is not in debug mode 1 The processor is in debug mode SMR SAFE mode request from MC_RGM is active indicator — This bit is set if a hardware SAFE mode request has been triggered. It is cleared when the hardware SAFE mode request has been cleared. 0 A SAFE mode request is not active 1 A SAFE mode request is active FMPLL_SC FMPLL State Change during mode transition indicator — This bit is set when the frequency modulated phase locked loop is requested to change its power up/down state. It is cleared when the frequency modulated phase locked loop has completed its state change. 0 No state change is taking place 1 A state change is taking place FXOSC_SC FXOSC State Change during mode transition indicator — This bit is set when the fast external crystal oscillator (4-16 MHz) is requested to change its power up/down state. It is cleared when the fast external crystal oscillator (4-16 MHz) has completed its state change. 0 No state change is taking place 1 A state change is taking place FIRC_SC FIRC State Change during mode transition indicator — This bit is set when the fast internal RC oscillator (16 MHz) is requested to change its power up/down state. It is cleared when the fast internal RC oscillator (16 MHz) has completed its state change. 0 No state change is taking place 1 A state change is taking place SYSCLK_S System Clock Switching pending status — W 0 No system clock source switching is pending 1 A system clock source switching is pending DFLASH_SC DFLASH State Change during mode transition indicator — This bit is set when the DFLASH is requested to change its power up/down state. It is cleared when the DFLASH has completed its state change. 0 No state change is taking place 1 A state change is taking place CFLASH_SC CFLASH State Change during mode transition indicator — This bit is set when the CFLASH is requested to change its power up/down state. It is cleared when the DFLASH has completed its state change. 0 No state change is taking place 1 A state change is taking place CDP_PRPH _0_143 Clock Disable Process Pending status for Peripherals 0…143 — This bit is set when any peripheral has been requested to have its clock disabled. It is cleared when all the peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral CDP_PRPH _96_127 Clock Disable Process Pending status for Peripherals 96…127 — This bit is set when any peripheral appearing in ME_PS3 has been requested to have its clock disabled. It is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 153 Table 8-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued) Field Description CDP_PRPH _64_95 Clock Disable Process Pending status for Peripherals 64…95 — This bit is set when any peripheral appearing in ME_PS2 has been requested to have its clock disabled. It is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral CDP_PRPH _32_63 Clock Disable Process Pending status for Peripherals 32…63 — This bit is set when any peripheral appearing in ME_PS1 has been requested to have its clock disabled. It is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral CDP_PRPH _0_31 Clock Disable Process Pending status for Peripherals 0…31 — This bit is set when any peripheral appearing in ME_PS0 has been requested to have its clock disabled. It is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral 8.3.1.8 RESET Mode Configuration Register (ME_RESET_MC) Address 0xC3FD_C020 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 PDO 0 0 DFLAON CFLAON MVRON W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 FMPLLON FXOSCON FIRCON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000000000 SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 8-9. Invalid Mode Transition Status Register (ME_IMTS) This register configures system behavior during RESET mode. Please refer to Table 8-11 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 154 Freescale Semiconductor 8.3.1.9 TEST Mode Configuration Register (ME_TEST_MC) Address 0xC3FD_C024 Access: Supervisor read/write MVRON 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 00000000 00 PDO DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 FMPLLON FXOSCON FIRCON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 W SYSCLK Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 8-10. TEST Mode Configuration Register (ME_TEST_MC) This register configures system behavior during TEST mode. Please refer to Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. 8.3.1.10 SAFE Mode Configuration Register (ME_SAFE_MC) Address 0xC3FD_C028 Access: Supervisor read/write MVRON 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 00000000 00 PDO DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 FMPLLON FXOSCON FIRCON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000000000 SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 8-11. SAFE Mode Configuration Register (ME_SAFE_MC) This register configures system behavior during SAFE mode. Please refer to Table 8-11 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 155 NOTE Byte and half-word write accesses are not allowed to this register. 8.3.1.11 DRUN Mode Configuration Register (ME_DRUN_MC) Address 0xC3FD_C02C Access: Supervisor read/write MVRON 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 PDO 0 0 DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 FMPLLON FXOSCON FIRCON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000000000 SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 8-12. DRUN Mode Configuration Register (ME_DRUN_MC) This register configures system behavior during DRUN mode. Please refer to Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. NOTE The values of FXOSCON, CFLAON and DFLAON are retained through STANDBY mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 156 Freescale Semiconductor 8.3.1.12 RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) Address 0xC3FD_C030 - 0xC3FD_C03C Access: Supervisor read/write MVRON 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 PDO 0 0 DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 FMPLLON FXOSCON FIRCON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000000000 SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 8-13. RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) This register configures system behavior during RUN0…3 modes. Please refer to Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. 8.3.1.13 HALT Mode Configuration Register (ME_HALT_MC) Address 0xC3FD_C040 Access: Supervisor read/write MVRON 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 PDO 0 0 W DFLAON CFLAON Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 FMPLLON FXOSCON FIRCON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 W SYSCLK Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 8-14. HALT Mode Configuration Register (ME_HALT_MC) This register configures system behavior during HALT mode. Please refer to Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 157 8.3.1.14 STOP Mode Configuration Register (ME_STOP_MC) Address 0xC3FD_C048 Access: Supervisor read/write MVRON 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 00 PDO W DFLAON CFLAON Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 FMPLLON FXOSCON FIRCON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000000000 SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 8-15. STOP Mode Configuration Register (ME_STOP_MC) This register configures system behavior during STOP mode. Please refer to Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. 8.3.1.15 STANDBY Mode Configuration Register (ME_STANDBY_MC) Address 0xC3FD_C054 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 PDO 0 0 DFLAON CFLAON MVRON W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 FMPLLON FXOSCON FIRCON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000000000 SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Figure 8-16. STANDBY Mode Configuration Register (ME_STANDBY_MC) This register configures system behavior during STANDBY mode. Please refer to Table 8-11 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 158 Freescale Semiconductor NOTE Byte and half-word write accesses are not allowed to this register. Table 8-11. Mode Configuration Registers (ME__MC) Field Descriptions Field Description PDO MVRON DFLAON CFLAON FMPLLON I/O output power-down control — This bit controls the output power-down of I/Os. 0 No automatic safe gating of I/Os used and pads power sequence driver is enabled 1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and pads power sequence driver is disabled. The inputs are level unchanged. In STOP mode, only pad power sequence driver is disabled but the state of the output is kept. In STANDBY mode, power sequence driver and all pads except those mapped on wakeup lines are not powered and therefore high impedance. Wakeup line configuration remains unchanged. Main voltage regulator control — This bit specifies whether main voltage regulator is switched off or not while entering this mode. 0 Main voltage regulator is switched off 1 Main voltage regulator is switched on Data flash power-down control — This bit specifies the operating mode of the data flash after entering this mode. 00 reserved 01 Data flash is in power-down mode 10 Data flash is in low-power mode 11 Data flash is in normal mode Note: If the flash memory is to be powered down in any mode, then your software must ensure that reset sources are configured as long resets in the RGM_FESS register (see Section 9.3.1.7, Functional Event Short Sequence Register (RGM_FESS)). Code flash power-down control — This bit specifies the operating mode of the program flash after entering this mode. 00 reserved 01Code flash is in power-down mode 10Code flash is in low-power mode 11Code flash is in normal mode frequency modulated phase locked loop control 0 frequency modulated phase locked loop is switched off 1 frequency modulated phase locked loop is switched on FXOSCON fast external crystal oscillator (4-16 MHz) control 0 fast external crystal oscillator (4-16 MHz) is switched off 1 fast external crystal oscillator (4-16 MHz) is switched on MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 159 Table 8-11. Mode Configuration Registers (ME__MC) Field Descriptions (continued) Field FIRCON SYSCLK Description fast internal RC oscillator (16 MHz) control 0 fast internal RC oscillator (16 MHz) is switched off 1 fast internal RC oscillator (16 MHz) is switched on System clock switch control — These bits specify the system clock to be used by the system. 0000 16 MHz int. RC osc. 0001 div. 16 MHz int. RC osc. 0010 4-16 MHz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. PLL 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled 8.3.1.16 Peripheral Status Register 0 (ME_PS0) Address 0xC3FD_C060 Access: Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0000000000 S_FlexCAN5 S_FlexCAN4 S_FlexCAN3 S_FlexCAN2 S_FlexCAN1 S_FlexCAN0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S_DSPI2 S_DSPI1 S_DSPI0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000000000 0000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-17. Peripheral Status Register 0 (ME_PS0) This register provides the status of the peripherals. Please refer to Table 8-12 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 160 Freescale Semiconductor 8.3.1.17 Peripheral Status Register 1 (ME_PS1) Address 0xC3FD_C064 Access: Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000 00 00000 S_LINFlex3 S_LINFlex2 S_LINFlex1 S_LINFlex0 S_CTU S_CANSampler W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S_ADC0 S_I2C0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000 00000000000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-18. Peripheral Status Register 1 (ME_PS1) This register provides the status of the peripherals. Please refer to Table 8-12 for details. 8.3.1.18 Peripheral Status Register 2 (ME_PS2) Address 0xC3FD_C068 Access: Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000 00000000000 S_PIT_RTI S_RTC_API W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S_WKPU S_SIUL S_eMIOS1 S_eMIOS0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 000000 00 0000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-19. Peripheral Status Register 2 (ME_PS2) This register provides the status of the peripherals. Please refer to Table 8-12 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 161 8.3.1.19 Peripheral Status Register 3 (ME_PS3) Address 0xC3FD_C06C Access: Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S_CMU 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0000000 00000000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-20. Peripheral Status Register 3 (ME_PS3) This register provides the status of the peripherals. Please refer to Table 8-12 for details. Table 8-12. Peripheral Status Registers 0…4 (ME_PS0…4) Field Descriptions Field Description S_ Peripheral status — These bits specify the current status of the peripherals in the system. If no peripheral is mapped on a particular position, the corresponding bit is always read as ‘0’. 0 Peripheral is frozen 1 Peripheral is active 8.3.1.20 Run Peripheral Configuration Registers (ME_RUN_PC0…7) Address 0xC3FD_C080 - 0xC3FD_C09C Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 00000000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-21. Run Peripheral Configuration Registers (ME_RUN_PC0…7) These registers configure eight different types of peripheral behavior during run modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 162 Freescale Semiconductor Table 8-13. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions Field RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET Peripheral control during RUN3 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during RUN2 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during RUN1 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during RUN0 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during DRUN 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during SAFE 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during TEST 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during RESET 0 Peripheral is frozen with clock gated 1 Peripheral is active Description 8.3.1.21 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Address 0xC3FD_C0A0 - 0xC3FD_C0BC Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STANDBY STOP HALT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 00 0 00000000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-22. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) These registers configure eight different types of peripheral behavior during non-run modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 163 Table 8-14. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions Field STANDBY STOP HALT Peripheral control during STANDBY 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during STOP 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during HALT 0 Peripheral is frozen with clock gated 1 Peripheral is active Description 8.3.1.22 Peripheral Control Registers (ME_PCTL0…143) Address 0xC3FD_C0C0 - 0xC3FD_C14F Access: Supervisor read/write 0 R 0 W 1 DBG_F 2 3 4 LP_CFG 5 6 7 RUN_CFG Reset 0 0 0 0 0 0 0 0 Figure 8-23. Peripheral Control Registers (ME_PCTL0…143) These registers select the configurations during run and non-run modes for each peripheral. Table 8-15. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions Field DBG_F Description Peripheral control in debug mode — This bit controls the state of the peripheral in debug mode. 0 Peripheral state depends on RUN_CFG/LP_CFG bits and the device mode. 1 Peripheral is frozen if not already frozen in device modes. Note: This feature is useful to freeze the peripheral state while entering debug. For example, this may be used to prevent a reference timer from running while making a debug accesses. MPC5604B/C Microcontroller Reference Manual, Rev. 8 164 Freescale Semiconductor Table 8-15. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions (continued) Field Description LP_CFG RUN_CFG Peripheral configuration select for non-run modes — These bits associate a configuration as defined in the ME_LP_PC0…7 registers to the peripheral. 000 Selects ME_LP_PC0 configuration 001 Selects ME_LP_PC1 configuration 010 Selects ME_LP_PC2 configuration 011 Selects ME_LP_PC3 configuration 100 Selects ME_LP_PC4 configuration 101 Selects ME_LP_PC5 configuration 110 Selects ME_LP_PC6 configuration 111 Selects ME_LP_PC7 configuration Peripheral configuration select for run modes — These bits associate a configuration as defined in the ME_RUN_PC0…7 registers to the peripheral. 000 Selects ME_RUN_PC0 configuration 001 Selects ME_RUN_PC1 configuration 010 Selects ME_RUN_PC2 configuration 011 Selects ME_RUN_PC3 configuration 100 Selects ME_RUN_PC4 configuration 101 Selects ME_RUN_PC5 configuration 110 Selects ME_RUN_PC6 configuration 111 Selects ME_RUN_PC7 configuration Table 8-16. Peripheral control registers by peripheral Peripheral ADC_0 CAN sampler CMU CTU DMA_MUX DSPI_0 DSPI_1 DSPI_2 DSPI_3 eMIOS_0 eMIOS_1 FlexCAN_0 FlexCAN_1 FlexCAN_2 FlexCAN_3 FlexCAN_4 FlexCAN_5 ME_PCTLn 32 60 104 57 23 4 5 6 7 72 73 16 17 18 10 20 21 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 165 8.4 Table 8-16. Peripheral control registers by peripheral (continued) Peripheral I2C LINFlex_0 LINFlex_1 LINFlex_2 LINFlex_3 PIT RTC/API SIUL WKPU ME_PCTLn 44 48 49 50 51 92 91 68 69 Functional Description 8.4.1 Mode Transition Request The transition from one mode to another mode is normally handled by software by accessing the mode control ME_MCTL register. But in case of special events, mode transition can be automatically managed by hardware. In order to switch from one mode to another, the application should access ME_MCTL register twice by writing • the first time with the value of the key (0x5AF0) into the KEY bit field and the required target mode into the TARGET_MODE bit field, • and the second time with the inverted value of the key (0xA50F) into the KEY bit field and the required target mode into the TARGET_MODE bit field. Once a valid mode transition request is detected, the target mode configuration information is loaded from the corresponding ME__MC register. The mode transition request may require a number of cycles depending on the programmed configuration, and software should check the S_CURRENT_MODE bit field and the S_MTRANS bit of the global status register ME_GS to verify when the mode has been correctly entered and the transition process has completed. For a description of valid mode requests, please refer to Section 8.4.5, “Mode Transition Interrupts“. Any modification of the mode configuration register of the currently selected mode will not be taken into account immediately but on the next request to enter this mode. This means that transition requests such as RUN0…3  RUN0…3, DRUN  DRUN, SAFE  SAFE, and TEST  TEST are considered valid mode transition requests. As soon as the mode request is accepted as valid, the S_MTRANS bit is set till the status in the ME_GS register matches the configuration programmed in the respective ME__MC register. NOTE It is recommended that software poll the S_MTRANS bit in the ME_GS register after requesting a transition to HALT, STOP, or STANDBY modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 166 Freescale Semiconductor SYSTEM MODES recoverable hardware failure software request SAFE RESET DRUN non-recoverable failure TEST USER MODES RUN0 RUN1 RUN2 RUN3 HALT STOP STANDBY Figure 8-24. MC_ME Mode Diagram 8.4.2 Modes Details 8.4.2.1 RESET Mode The device enters this mode on the following events: • from SAFE, DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0000” • from any mode due to a system reset by the MC_RGM because of some non-recoverable hardware failure in the system (see the MC_RGM chapter for details) Transition to this mode is instantaneous, and the system remains in this mode until the reset sequence is finished. The mode configuration information for this mode is provided by the ME_RESET_MC register. This mode has a pre-defined configuration, and the 16 MHz int. RC osc. is selected as the system clock. All power domains are made active in this mode. 8.4.2.2 DRUN Mode The device enters this mode on the following events. • automatically from RESET mode after completion of the reset sequence MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 167 • from RUN0…3, SAFE, or TEST mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0011” • from the STANDBY mode after an external wakeup event or internal wakeup alarm (e.g. RTC/API event) As soon as any of the above events has occurred, a DRUN mode transition request is generated. The mode configuration information for this mode is provided by the ME_DRUN_MC register. In this mode, the flashes, all clock sources, and the system clock configuration can be controlled by software as required. After system reset, the software execution starts with the default configuration selecting the 16 MHz int. RC osc. as the system clock. This mode is intended to be used by software • to initialize all registers as per the system needs • to execute small routines in a ‘ping-pong’ with the STANDBY mode When this mode is entered from STANDBY after a wakeup event, the ME_DRUN_MC register content is restored to its pre-STANDBY values, and the mode starts in that configuration. All power domains are active when this mode is entered due to a system reset sequence initiated by a destructive reset event. In other cases of entry, such as the exit from STANDBY after a wakeup event, a functional reset event like an external reset or a software request from RUN0…3, SAFE, or TEST mode, active power domains are determined by the power configuration register PCU_PCONF2 of the MC_PCU. All power domains except power domains #0 and #1 are configurable in this mode (see the MC_PCU chapter for details). NOTE As flashes can be configured in low-power or power-down state in this mode, software must ensure that the code executes from SRAM before changing to this mode. 8.4.2.3 SAFE Mode The device enters this mode on the following events: • from DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0010” • from any mode except RESET due to a SAFE mode request generated by the MC_RGM because of some potentially recoverable hardware failure in the system (see the MC_RGM chapter for details) As soon as any of the above events has occurred, a SAFE mode transition request is generated. The mode configuration information for this mode is provided by the ME_SAFE_MC register. This mode has a pre-defined configuration, and the 16 MHz int. RC osc. is selected as the system clock. All power domains are made active in this mode. If the SAFE mode is requested by software while some other mode transition process is ongoing, the new target mode becomes the SAFE mode regardless of other pending requests. In this case, the new mode request is not interpreted as an invalid request. MPC5604B/C Microcontroller Reference Manual, Rev. 8 168 Freescale Semiconductor NOTE If software requests to change to the SAFE mode and then requests to change back to the parent mode before the mode transition is completed, the device’s final mode after mode transition will be the parent mode. However, this is not recommended software behavior. It is recommended for software to wait until the S_MTRANS bit is cleared after requesting a change to SAFE before requesting another mode change. As long as a SAFE event is active, the system remains in the SAFE mode and no write access is allowed to the ME_MCTL register. This mode is intended to be used by software • to assess the severity of the cause of failure and then to either — re-initialize the device via the DRUN mode, or — completely reset the device via the RESET mode. If the outputs of the system I/Os need to be forced to a high impedance state upon entering this mode, the PDO bit of the ME_SAFE_MC register should be set. In this case, the pads’ power sequence driver cell is also disabled. The input levels remain unchanged. 8.4.2.4 TEST Mode The device enters this mode on the following events: • from the DRUN mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0001” As soon as any of the above events has occurred, a TEST mode transition request is generated. The mode configuration information for this mode is provided by the ME_TEST_MC register. Except for the main voltage regulator, all resources of the system are configurable in this mode. The system clock to the whole system can be stopped by programming the SYSCLK bit field to “1111”, and in this case, the only way to exit this mode is via a device reset. This mode is intended to be used by software • to execute on-chip test routines All power domains except power domains #0 and #1 are configurable in this mode. Active power domains are determined by the power configuration register PCU_PCONF2 of the MC_PCU. NOTE As flash modules can be configured to a low-power or power-down state in these modes, software must ensure that the code will execute from SRAM before it changes to this mode. 8.4.2.5 RUN0…3 Modes The device enters one of these modes on the following events: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 169 • from the DRUN another RUN0…3 mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0100…0111” • from the HALT mode by an interrupt event • from the STOP mode by an interrupt or wakeup event As soon as any of the above events occur, a RUN0…3 mode transition request is generated. The mode configuration information for these modes is provided by ME_RUN0…3_MC registers. In these modes, the flashes, all clock sources, and the system clock configuration can be controlled by software as required. These modes are intended to be used by software • to execute application routines All power domains except power domains #0 and #1 are configurable in these modes in order to reduce leakage consumption. Active power domains are determined by the power configuration register PCU_PCONF2 of the MC_PCU. NOTE As flash modules can be configured to a low-power or power-down state in these modes, software must ensure that the code will execute from SRAM before it changes to this mode. 8.4.2.6 HALT Mode The device enters this mode on the following events: • from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with “1000”. As soon as any of the above events occur, a HALT mode transition request is generated. The mode configuration information for this mode is provided by ME_HALT_MC register. This mode is quite configurable, and the ME_HALT_MC register should be programmed according to the system needs. The main voltage regulator and the flashes can be put in power-down mode as needed. If there is a HALT mode request while an interrupt request is active, the device mode does not change, and an invalid mode interrupt is not generated. This mode is intended as a first level low-power mode with • the core clock frozen • only a few peripherals running and to be used by software • to wait until it is required to do something and then to react quickly (i.e. within a few system clock cycles of an interrupt event) All power domains except power domains #0 and #1 are configurable in this mode in order to reduce leakage consumption. Active power domains are determined by the power configuration register PCU_PCONF2 of the MC_PCU. MPC5604B/C Microcontroller Reference Manual, Rev. 8 170 Freescale Semiconductor 8.4.2.7 STOP Mode The device enters this mode on the following events: • from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with “1010”. As soon as any of the above events occur, a STOP mode transition request is generated. The mode configuration information for this mode is provided by the ME_STOP_MC register. This mode is fully configurable, and the ME_STOP_MC register should be programmed according to the system needs. The FMPLL is switched off in this mode. The main voltage regulator and the flashes can be put in power-down mode as needed. If there is a STOP mode request while any interrupt or wakeup event is active, the device mode does not change, and an invalid mode interrupt is not generated. This can be used as an advanced low-power mode with the core clock frozen and almost all peripherals stopped. This mode is intended as an advanced low-power mode with • the core clock frozen • almost all peripherals stopped and to be used by software • to wait until it is required to do something with no need to react quickly (e.g. allow for system clock source to be re-started) If the pads’ power sequence driver cell needs to be disabled while entering this mode, the PDO bit of the ME_STOP_MC register should be set. The state of the outputs is kept. This mode can be used to stop all clock sources, thus preserving the device status. When exiting the STOP mode, the fast internal RC oscillator (16 MHz) clock is selected as the system clock until the target clock is available. All power domains except power domains #0 and #1 are configurable in this mode in order to reduce leakage consumption. Active power domains are determined by the power configuration register PCU_PCONF2 of the MC_PCU. 8.4.2.8 STANDBY Mode The device enters this mode on the following events: • from the DRUN or one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with “1101”. As soon as any of the above events occur, a STANDBY mode transition request is generated. The mode configuration information for this mode is provided by the ME_STANDBY_MC register. In this mode, the power supply is turned off for most of the device. The only parts of the device that are still powered during this mode are pads mapped on wakeup lines and power domain #0 which contains the MC_RGM, MC_PCU, WKPU, 8K RAM, RTC_API, CANSampler, SIRC, FIRC, SXOSC, and device and user option bits. The FIRC can be optionally switched off. This is the lowest power consumption mode possible on the device. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 171 This mode is intended as an extreme low-power mode with • the core, the flashes, and almost all peripherals and memories powered down and to be used by software • to wait until it is required to do something with no need to react quickly (i.e. allow for system power-up and system clock source to be re-started) The exit sequence of this mode is similar to the reset sequence. However, in addition to booting from the default location, the device can also be configured to boot from the backup SRAM (see the RGM_STDBY register description in the MC_RGM chapter for details). In the case of booting from backup SRAM, it is also possible to keep the flashes disabled by writing “01” to the CFLAON and DFLAON fileds in the ME_DRUN_MC register prior to STANDBY entry. If there is a STANDBY mode request while any wakeup event is active, the device mode does not change. All power domains except power domain #0 are configurable in this mode in order to reduce leakage consumption. Active power domains are determined by the power configuration register PCU_PCONF2 of the MC_PCU. 8.4.3 Mode Transition Process The process of mode transition follows the following steps in a pre-defined manner depending on the current device mode and the requested target mode. In many cases of mode transition, not all steps need to be executed based on the mode control information, and some steps may not be valid according to the mode definition itself. 8.4.3.1 Target Mode Request The target mode is requested by accessing the ME_MCTL register with the required keys. This mode transition request by software must be a valid request satisfying a set of pre-defined rules to initiate the process. If the request fails to satisfy these rules, it is ignored, and the TARGET_MODE bit field is not updated. An optional interrupt can be generated for invalid mode requests. Refer to Section 8.4.5, “Mode Transition Interrupts for details. In the case of mode transitions occurring because of hardware events such as a reset, a SAFE mode request, or interrupt requests and wakeup events to exit from low-power modes, the TARGET_MODE bit field of the ME_MCTL register is automatically updated with the appropriate target mode. The mode change process start is indicated by the setting of the mode transition status bit S_MTRANS of the ME_GS register. A RESET mode requested via the ME_MCTL register is passed to the MC_RGM, which generates a global system reset and initiates the reset sequence. The RESET mode request has the highest priority, and the MC_ME is kept in the RESET mode during the entire reset sequence. The SAFE mode request has the next highest priority after reset which can be generated by software via the ME_MCTL register from all software running modes including DRUN, RUN0…3, and TEST or by the MC_RGM after the detection of system hardware failures, which may occur in any mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 172 Freescale Semiconductor 8.4.3.2 Target Mode Configuration Loading On completion of the Target Mode Request, the target mode configuration from the ME__MC register is loaded to start the resources (voltage sources, clock sources, flashes, pads, etc.) control process. An overview of resource control possibilities for each mode is shown in Table 8-17. A ‘’ indicates that a given resource is configurable for a given mode. Table 8-17. MC_ME Resource Control Overview Resource RESET FIRC FXOSC FMPLL CFLASH on off off normal DFLASH normal MVREG on PDO off TEST  on  off  off  normal  normal on  off SAFE on off off normal normal on  on Mode DRUN on  off  off  normal RUN0…3 HALT on  off  off  normal  on  off  off  low-power  normal  normal  low-power  on on on off off off STOP  on  off off  powerdown  powerdown  on  off STANDBY  on off off powerdown powerdown off on 8.4.3.3 Peripheral Clocks Disable On completion of the Target Mode Request, the MC_ME requests each peripheral to enter its stop mode when: • the peripheral is configured to be disabled via the target mode, the peripheral configuration registers ME_RUN_PC0…7 and ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 173 CAUTION The MC_ME does not automatically request peripherals to enter their stop modes if the power domains in which they are residing are to be turned off due to a mode change. Therefore, it is software’s responsibility to ensure that those peripherals that are to be powered down are configured in the MC_ME to be frozen. Each peripheral acknowledges its stop mode request after closing its internal activity. The MC_ME then disables the corresponding clock(s) to this peripheral. In the case of a SAFE mode transition request, the MC_ME does not wait for the peripherals to acknowledge the stop requests. The SAFE mode clock gating configuration is applied immediately regardless of the status of the peripherals’ stop acknowledges. Please refer to Section 8.4.6, “Peripheral Clock Gating“ for more details. Each peripheral that may block or disrupt a communication bus to which it is connected ensures that these outputs are forced to a safe or recessive state when the device enters the SAFE mode. 8.4.3.4 Processor Low-Power Mode Entry If, on completion of the Peripheral Clocks Disable, the mode transition is to the HALT mode, the MC_ME requests the processor to enter its halted state. The processor acknowledges its halt state request after completing all outstanding bus transactions. If, on completion of the Peripheral Clocks Disable, the mode transition is to the STOP or STANDBY mode, the MC_ME requests the processor to enter its stopped state. The processor acknowledges its stop state request after completing all outstanding bus transactions. 8.4.3.5 Processor and System Memory Clock Disable If, on completion of the Processor Low-Power Mode Entry, the mode transition is to the HALT, STOP, or STANDBY mode and the processor is in its appropriate halted or stopped state, the MC_ME disables the processor and system memory clocks to achieve further power saving. The clocks to the processor and system memories are unaffected for all transitions between software running modes including DRUN, RUN0…3, and SAFE. CAUTION Clocks to the whole device including the processor and system memories can be disabled in TEST mode. 8.4.3.6 Clock Sources Switch-On On completion of the Processor Low-Power Mode Entry, the MC_ME controls all clock sources that affect the system clock based on the ON bits of the ME__MC and ME__MC registers. The following system clock sources are controlled at this step: • the fast internal RC oscillator (16 MHz) MPC5604B/C Microcontroller Reference Manual, Rev. 8 174 Freescale Semiconductor • the fast external crystal oscillator (4-16 MHz) NOTE The frequency modulated phase locked loop, which needs the main voltage regulator to be stable, is not controlled by this step. The clock sources that are required by the target mode are switched on. The duration required for the output clocks to be stable depends on the type of source, and all further steps of mode transition depending on one or more of these clocks waits for the stable status of the respective clocks. The availability status of these system clocks is updated in the S_ bits of ME_GS register. The clock sources which need to be switched off are unaffected during this process in order to not disturb the system clock which might require one of these clocks before switching to a different target clock. 8.4.3.7 Main Voltage Regulator Switch-On On completion of the Target Mode Request, if the main voltage regulator needs to be switched on from its off state based on the MVRON bit of the ME__MC and ME__MC registers, the MC_ME requests the MC_PCU to power-up the regulator and waits for the output voltage stable status in order to update the S_MVR bit of the ME_GS register. This step is required only during the exit of the low-power modes HALT and STOP. In this step, the fast internal RC oscillator (16 MHz) is switched on regardless of the target mode configuration, as the main voltage regulator requires the 16 MHz int. RC osc. during power-up in order to generate the voltage status. During the STANDBY exit sequence, the MC_PCU alone manages the power-up of the main voltage regulator, and the MC_ME is kept in RESET or shut off (depending on the power domain #1 status). 8.4.3.8 Flash Modules Switch-On On completion of the Main Voltage Regulator Switch-On, if a flash module needs to be switched to normal mode from its low-power or power-down mode based on the CFLAON and DFLAON bit fields of the ME__MC and ME__MC registers, the MC_ME requests the flash to exit from its low-power/power-down mode. When the flash modules are available for access, the S_CFLA and S_DFLA bit fields of the ME_GS register are updated to “11” by hardware. If the main regulator is also off in device low-power modes, then during the exit sequence, the flash is kept in its low-power state and is switched on only when the Main Voltage Regulator Switch-On process has completed. CAUTION It is illegal to switch the flashes from low-power mode to power-down mode and from power-down mode to low-power mode. The MC_ME, however, does not prevent this nor does it flag it. 8.4.3.9 FMPLL Switch-On On completion of the Clock Sources Switch-On and Main Voltage Regulator Switch-On, if the FMPLL is to be switched on from the off state based on the FMPLLON bit of the ME__MC and MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 175 ME__MC registers, the MC_ME requests the FMPLL digital interface to start the phase locking process and waits for the FMPLL to enter into the locked state. When the FMPLL enters the locked state and starts providing a stable output clock, the S_FMPLL bit of ME_GS register is set. 8.4.3.10 Power Domain #2 Switch-On On completion of the Main Voltage Regulator Switch-On, the MC_ME indicates a mode change to the MC_PCU. The MC_PCU then determines whether a power-up sequence is required for power domain #2. Only after the MC_PCU has executed all required power-ups does the MC_ME complete the mode transition. 8.4.3.11 Pad Outputs-On On completion of the Main Voltage Regulator Switch-On, if the PDO bit of the ME__MC register is cleared, then • all pad outputs are enabled to return to their previous state • the I/O pads power sequence driver is switched on 8.4.3.12 Peripheral Clocks Enable Based on the current and target device modes, the peripheral configuration registers ME_RUN_PC0…7, ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143, the MC_ME enables the clocks for selected modules as required. This step is executed only after the Main Voltage Regulator Switch-On process is completed. Also if a mode change translates to a power up of one or more power domains, the MC_PCU indicates the MC_ME after completing the power-up sequence upon which the MC_ME may assert the peripheral clock enables of the peripherals residing in those power domains. 8.4.3.13 Processor and Memory Clock Enable If the mode transition is from any of the low-power modes HALT or STOP to RUN0…3, the clocks to the processor and system memories are enabled. The process of enabling these clocks is executed only after the Flash Modules Switch-On process is completed. 8.4.3.14 Processor Low-Power Mode Exit If the mode transition is from any of the low-power modes HALT, STOP, or STANDBY to RUN0…3, the MC_ME requests the processor to exit from its halted or stopped state. This step is executed only after the Processor and Memory Clock Enable process is completed. 8.4.3.15 System Clock Switching Based on the SYSCLK bit field of the ME__MC and ME__MC registers, if the target and current system clock configurations differ, the following method is implemented for clock switching. MPC5604B/C Microcontroller Reference Manual, Rev. 8 176 Freescale Semiconductor • The target clock configuration for the 16 MHz int. RC osc. is effective only when the S_FIRC bit of the ME_GS register is set by hardware (i.e. the fast internal RC oscillator (16 MHz) has stabilized). • The target clock configuration for the div. 16 MHz int. RC osc. is effective only when the S_FIRC bit of the ME_GS register is set by hardware (i.e. the fast internal RC oscillator (16 MHz) has stabilized). • The target clock configuration for the 4-16 MHz ext. xtal osc. is effective only when the S_FXOSC bit of the ME_GS register is set by hardware (i.e the fast external crystal oscillator (4-16 MHz) has stabilized). • The target clock configuration for the div. ext. xtal osc. is effective only when the S_FXOSC bit of the ME_GS register is set by hardware (i.e the fast external crystal oscillator (4-16 MHz) has stabilized). • The target clock configuration for the freq. mod. PLL is effective only when the S_FMPLL bit of the ME_GS register is set by hardware (i.e. the frequency modulated phase locked loop has stabilized). • If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111”. This is possible only in the STOP and TEST modes. In the STANDBY mode, the clock configuration is fixed, and the system clock is automatically forced to ‘0’. The current system clock configuration can be observed by reading the S_SYSCLK bit field of the ME_GS register, which is updated after every system clock switching. Until the target clock is available, the system uses the previous clock configuration. System clock switching starts only after • the Clock Sources Switch-On process has completed if the target system clock source needs to be switched on • the FMPLL Switch-On process has completed if the target system clock is the freq. mod. PLL • the Peripheral Clocks Disable process is completed in order not to change the system clock frequency before peripherals close their internal activities An overview of system clock source selection possibilities for each mode is shown in Table 8-18. A ‘’ indicates that a given clock source is selectable for a given mode. Table 8-18. MC_ME System Clock Selection Overview System Clock Source RESET TEST SAFE Mode DRUN RUN0…3 HALT STOP STANDBY 16 MHz int. RC osc. div. 16 MHz int. RC osc.  (default)  (default)   (default)  (default)   (default)   (default)   (default)  MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 177 Table 8-18. MC_ME System Clock Selection Overview (continued) System Clock Source RESET TEST SAFE Mode DRUN RUN0…3 HALT STOP 4-16 MHz  ext. xtal osc. div. ext.  xtal osc.         freq. mod.  PLL    system   clock is disabled 1 disabling the system clock during TEST mode will require a reset in order to exit TEST mode STANDBY  (default) 8.4.3.16 Power Domain #2 Switch-Off Based on the device mode and the MC_PCU’s power configuration register PCU_PCONF2, the power domain #2 is controlled by the MC_PCU. If a mode change translates to a power-down of the power domain, then the MC_PCU starts the power-down sequence. The MC_PCU acknowledges the completion of the power-down sequence with respect to the new mode, and the MC_ME uses this information to update the mode transition status. This step is executed only after the Peripheral Clocks Disable process has completed. 8.4.3.17 Pad Switch-Off If the PDO bit of the ME__MC register is ‘1’ then • the outputs of the pads are forced to the high impedance state if the target mode is SAFE or TEST • I/O pads power sequence driver is switched off if the target mode is one of SAFE, TEST, or STOP modes In STANDBY mode, the power sequence driver and all pads except the external reset and those mapped on wakeup lines are not powered and therefore high impedance. The wakeup line configuration remains unchanged. This step is executed only after the Peripheral Clocks Disable process is completed. 8.4.3.18 FMPLL Switch-Off Based on the FMPLLON bit of the ME__MC and ME__MC registers, if FMPLL is to be switched off, the MC_ME requests the FMPLL to power down and updates its availability status bit S_FMPLL of the ME_GS register to ‘0’. This step is executed only after the System Clock Switching process is completed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 178 Freescale Semiconductor 8.4.3.19 Clock Sources Switch-Off Based on the device mode and the ON bits of the ME__MC registers, if a given clock source is to be switched off, the MC_ME requests the clock source to power down and updates its availability status bit S_ of the ME_GS register to ‘0’. This step is executed only after • System Clock Switching process is completed in order not to lose the current system clock during mode transition. • FMPLL Switch-Off as the input reference clock of the FMPLL can be among these clock sources. This is needed to prevent an unwanted lock transition when the FMPLL is switched on. 8.4.3.20 Flash Switch-Off Based on the CFLAON and DFLAON bit fields of the ME__MC and ME__MC registers, if any of the flash modules is to be put in a low-power state, the MC_ME requests the flash to enter the corresponding low-power state and waits for the deassertion of flash ready status signal. The exact low-power mode status of the flash modules is updated in the S_CFLA and S_DFLA bit fields of the ME_GS register. This step is executed only when Processor and System Memory Clock Disable process is completed. 8.4.3.21 Main Voltage Regulator Switch-Off Based on the MVRON bit of the ME__MC and ME__MC registers, if the main voltage regulator is to be switched off, the MC_ME requests it to power down and clears the availability status bit S_MVR of the ME_GS register. This step is required only during the entry of low-power modes like HALT and STOP. This step is executed only after completing the following processes: • FMPLL Switch-Off • Flash Switch-Off • Power Domain #2 Switch-Off • Power Domain #2 Switch-On • the device consumption is less than the pre-defined threshold value (i.e. the S_DC bit of the ME_GS register is ‘0’). If the target mode is STANDBY, the main voltage regulator is not switched off by the MC_ME and the STANDBY request is asserted after the above processes have completed upon which the MC_PCU takes control of the main regulator. As the MC_PCU needs the 16 MHz int. RC osc., the fast internal RC oscillator (16 MHz) remains active until all the STANDBY steps are executed by the MC_PCU after which it may be switched off depending on the FIRCON bit of the ME_STANDBY_MC register. 8.4.3.22 Current Mode Update The current mode status bit field S_CURRENT_MODE of the ME_GS register is updated with the target mode bit field TARGET_MODE of the ME_MCTL register when: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 179 • all the updated status bits in the ME_GS register match the configuration specified in the ME__MC register • power sequences are done • clock disable/enable process is finished • processor low-power mode (halt/stop) entry and exit processes are finished Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register. The mode transition latency can differ from one mode to another depending on the resources’ availability before the new mode request and the target mode’s requirements. MPC5604B/C Microcontroller Reference Manual, Rev. 8 180 Freescale Semiconductor Start Target Mode Request Clock sources Switch-On Write ME_MCTL register SAFE mode request interrupt/wakeup event Main VREG Switch-On ANALOG ON S_MTRANS = ‘1’ DIGITAL CONTROL Peripheral Clocks Disable Processor Low-Power Entry Processor & Memory Clock Disable PLL FLASH Power Domain Switch-On Switch-On Switch-On Pad Outputs -On System Clock Switching Processor & Memory Clock Enable Processor Low-Power Exit Peripheral Clocks Enable FLASH Power Domain Switch-Off Switch-Off PAD Outputs -Off PLL Switch-Off ANALOG OFF Main VREG N Switch-Off Target STANDBY Y STANDBY Request Clock sources Switch-Off Current Mode Update S_MTRANS = ‘0’ End Figure 8-25. MC_ME Transition Diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 181 8.4.4 Protection of Mode Configuration Registers While programming the mode configuration registers ME__MC, the following rules must be respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be generated. • FIRC must be on if the system clock is one of the following: — 16 MHz int. RC osc. — div. 16 MHz int. RC osc. • FXOSC must be on if the system clock is one of the following: — 4-16 MHz ext. xtal osc. — div. ext. xtal osc. NOTE Software must ensure to switch on the clock source that provides the input reference clock to the FMPLL. There is no automatic protection mechanism to check this in the MC_ME. • FMPLL must be on if the system clock is the freq. mod. PLL. • Configuration “00” for the CFLAON and DFLAON bit fields are reserved. • MVREG must be on if any of the following is active: — FMPLL — CFLASH — DFLASH • System clock configurations marked as ‘reserved’ may not be selected. • Configuration “1111” for the SYSCLK bit field is allowed only for the STOP and TEST modes, and only in this case may all system clock sources be turned off. CAUTION If the system clock is stopped during TEST mode, the device can exit only via a system reset. 8.4.5 Mode Transition Interrupts The following are the three interrupts related to mode transition implemented in the MC_ME. 8.4.5.1 Invalid Mode Configuration Interrupt Whenever a write operation is attempted to the ME__MC registers violating the protection rules mentioned in the Section 8.4.4, “Protection of Mode Configuration Registers, the interrupt pending bit I_ICONF of the ME_IS register is set and an interrupt request is generated if the mask bit M_ICONF of ME_IM register is ‘1’. MPC5604B/C Microcontroller Reference Manual, Rev. 8 182 Freescale Semiconductor 8.4.5.2 Invalid Mode Transition Interrupt The mode transition request is considered invalid under the following conditions: • If the system is in the SAFE mode and the SAFE mode request from MC_RGM is active, and if the target mode requested is other than RESET or SAFE, then this new mode request is considered to be invalid, and the S_SEA bit of the ME_IMTS register is set. • If the TARGET_MODE bit field of the ME_MCTL register is written with a value different from the specified mode values (i.e. a non existing mode), an invalid mode transition event is generated. When such a non existing mode is requested, the S_NMA bit of the ME_IMTS register is set. This condition is detected regardless of whether the proper key mechanism is followed while writing the ME_MCTL register. • If some of the device modes are disabled as programmed in the ME_ME register, their respective configurations are considered reserved, and any access to the ME_MCTL register with those values results in an invalid mode transition request. When such a disabled mode is requested, the S_DMA bit of the ME_IMTS register is set. This condition is detected regardless of whether the proper key mechanism is followed while writing the ME_MCTL register. • If the target mode is not a valid mode with respect to current mode, the mode request illegal status bit S_MRI of the ME_IMTS register is set. This condition is detected only when the proper key mechanism is followed while writing the ME_MCTL register. Otherwise, the write operation is ignored. • If further new mode requests occur while a mode transition is in progress (the S_MTRANS bit of the ME_GS register is ‘1’), the mode transition illegal status bit S_MTI of the ME_IMTS register is set. This condition is detected only when the proper key mechanism is followed while writing the ME_MCTL register. Otherwise, the write operation is ignored. NOTE As the causes of invalid mode transitions may overlap at the same time, the priority implemented for invalid mode transition status bits of the ME_IMTS register in the order from highest to lowest is S_SEA, S_NMA, S_DMA, S_MRI, and S_MTI. As an exception, the mode transition request is not considered as invalid under the following conditions: • A new request is allowed to enter the RESET or SAFE mode irrespective of the mode transition status. • As the exit of HALT and STOP modes depends on the interrupts of the system which can occur at any instant, these requests to return to RUN0…3 modes are always valid. • In order to avoid any unwanted lockup of the device modes, software can abort a mode transition by requesting the parent mode if, for example, the mode transition has not completed after a software determined ‘reasonable’ amount of time for whatever reason. The parent mode is the device mode before a valid mode request was made. • Self-transition requests (e.g. RUN0  RUN0) are not considered as invalid even when the mode transition process is active (i.e. S_MTRANS is ‘1’). During the low-power mode exit process, if the system is not able to enter the respective RUN0…3 mode properly (i.e. all status bits of the ME_GS register match with configuration bits in the ME__MC register), then software MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 183 can only request the SAFE or RESET mode. It is not possible to request any other mode or to go back to the low-power mode again. Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register is set, and an interrupt request is generated if the mask bit M_IMODE is ME_IM register is ‘1’. 8.4.5.3 SAFE Mode Transition Interrupt Whenever the system enters the SAFE mode as a result of a SAFE mode request from the MC_RGM due to a hardware failure, the interrupt pending bit I_SAFE of the ME_IS register is set, and an interrupt is generated if the mask bit M_SAFE of ME_IM register is ‘1’. The SAFE mode interrupt pending bit can be cleared only when the SAFE mode request is deasserted by the MC_RGM (see the MC_RGM chapter for details on how to clear a SAFE mode request). If the system is already in SAFE mode, any new SAFE mode request by the MC_RGM also sets the interrupt pending bit I_SAFE. However, the SAFE mode interrupt pending bit is not set when the SAFE mode is entered by a software request (i.e. programming of ME_MCTL register). 8.4.5.4 Mode Transition Complete interrupt Whenever the system completes a mode transition fully (i.e. the S_MTRANS bit of ME_GS register transits from ‘1’ to ‘0’), the interrupt pending bit I_MTC of the ME_IS register is set, and interrupt request is generated if the mask bit M_MTC of the ME_IM register is ‘1’. The interrupt bit I_MTC is not set when entering low-power modes HALT and STOP in order to avoid the same event requesting the exit of these low-power modes. 8.4.6 Peripheral Clock Gating During all device modes, each peripheral can be associated with a particular clock gating policy determined by two groups of peripheral configuration registers. The run peripheral configuration registers ME_RUN_PC0…7 are chosen only during the software running modes DRUN, TEST, SAFE, and RUN0…3. All configurations are programmable by software according to the needs of application. Each configuration register contains a mode bit which determines whether or not a peripheral clock is to be gated. Run configuration selection for each peripheral is done by the RUN_CFG bit field of the ME_PCTL0…143 registers. The low-power peripheral configuration registers ME_LP_PC0…7 are chosen only during the low-power modes HALT, STOP, and STANDBY. All configurations are programmable by software according to the needs of the application. Each configuration register contains a mode bit which determines whether or not a peripheral clock is to be gated. Low-power configuration selection for each peripheral is done by the LP_CFG bit field of the ME_PCTL0…143 registers. Any modifications to the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers do not affect the clock gating behavior until a new mode transition request is generated. Whenever the processor enters a debug session during any mode, the following occurs for each peripheral: MPC5604B/C Microcontroller Reference Manual, Rev. 8 184 Freescale Semiconductor • The clock is gated if the DBG_F bit of the associated ME_PCTL0…143 register is set. Otherwise, the peripheral clock gating status depends on the RUN_CFG and LP_CFG bits. Any further modifications of the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers during a debug session will take affect immediately without requiring any new mode request. 8.4.7 Application Example Figure 8-26 shows an example application flow for requesting a mode change and then waiting until the mode transition has completed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 185 START of mode change config N for target mode okay? Y write ME__MC, ME_RUN_PC0…7, ME_LP_PC0…7, and write ME_MCTL with target mode and key write ME_MCTL with target mode and inverted key start timer S_MTRANS N cleared? Y stop timer mode change DONE N timer expired? Y write ME_MCTL with current or SAFE mode and key write ME_MCTL with current or SAFE mode and inverted key Figure 8-26. MC_ME Application Example Flow Diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 186 Freescale Semiconductor Chapter 9 Reset Generation Module (MC_RGM) 9.1 Introduction 9.1.1 Overview The reset generation module (MC_RGM) centralizes the different reset sources and manages the reset sequence of the device. It provides a register interface and the reset sequencer. The different registers are available to monitor and control the device reset sequence. The reset sequencer is a state machine which controls the different phases (PHASE0, PHASE1, PHASE2, PHASE3, and IDLE) of the reset sequence and control the reset signals generated in the system. Figure 9-1 depicts the MC_RGM block diagram. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 187 power-on 1.2 V low-voltage detected (power domain #0) 1.2 V low-voltage detected (power domain #1) software watchdog timer 2.7 V low-voltage detected MC_RGM Registers Platform Interface MC_ME MC_CGM peripherals Destructive Reset Filter RESET JTAG initiated reset debug control core reset software reset checkstop reset FMPLL fail FXOSC frequency lower than reference CMU clock frequency higher/lower than reference 4.5 V low-voltage detected code or data flash fatal error Functional Reset Filter Reset State Machine core PA[8] and PA[9] Boot Mode Capture SSCM Figure 9-1. MC_RGM block diagram 9.1.2 Features The MC_RGM contains the functionality for the following features: • ‘destructive’ resets management • ‘functional’ resets management • signalling of reset events after each reset sequence (reset status flags) • conversion of reset events to SAFE mode or interrupt request events (for further mode details, please see the MC_ME chapter) MPC5604B/C Microcontroller Reference Manual, Rev. 8 188 Freescale Semiconductor • short reset sequence configuration • bidirectional reset behavior configuration • selection of alternate boot via the backup SRAM on STANDBY mode exit (for further mode details, please see the MC_ME chapter) • boot mode capture on RESET deassertion 9.1.3 Modes of operation The different reset sources are organized into two families: ‘destructive’ and ‘functional’. • A ‘destructive’ reset source is associated with an event related to a critical - usually hardware error or dysfunction. When a ‘destructive’ reset event occurs, the full reset sequence is applied to the device starting from PHASE0. This resets the full device ensuring a safe start-up state for both digital and analog modules. ‘Destructive’ resets are – power-on reset – 1.2 V low-voltage detected (power domain #0) – 1.2 V low-voltage detected (power domain #1) – software watchdog timer – 2.7 V low-voltage detected • A ‘functional’ reset source is associated with an event related to a less-critical - usually non-hardware - error or dysfunction. When a ‘functional’ reset event occurs, a partial reset sequence is applied to the device starting from PHASE1. In this case, most digital modules are reset normally, while analog modules or specific digital modules’ (e.g. debug modules, flash modules) state is preserved. ‘Functional’ resets are – external reset – JTAG initiated reset – debug control core reset – software reset – checkstop reset – FMPLL fail – FXOSC frequency lower than reference – CMU clock frequency higher/lower than reference – 4.5 V low-voltage detected – code or data flash fatal error When a reset is triggered, the MC_RGM state machine is activated and proceeds through the different phases (i.e. PHASEn states). Each phase is associated with a particular device reset being provided to the system. A phase is completed when all corresponding phase completion gates from either the system or internal to the MC_RGM are acknowledged. The device reset associated with the phase is then released, and the state machine proceeds to the next phase up to entering the IDLE phase. During this entire process, the MC_ME state machine is held in RESET mode. Only at the end of the reset sequence, when the IDLE phase is reached, does the MC_ME enter the DRUN mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 189 Alternatively, it is possible for software to configure some reset source events to be converted from a reset to either a SAFE mode request issued to the MC_ME or to an interrupt issued to the core (see Section 9.3.1.4, “Destructive Event Reset Disable Register (RGM_DERD) and Section 9.3.1.6, “Destructive Event Alternate Request Register (RGM_DEAR) for ‘destructive’ resets and Section 9.3.1.3, “Functional Event Reset Disable Register (RGM_FERD) and Section 9.3.1.5, “Functional Event Alternate Request Register (RGM_FEAR) for ‘functional’ resets). 9.2 External signal description The MC_RGM interfaces to the bidirectional reset pin RESET and the boot mode pins PA[8] and PA[9]. 9.3 Memory map and register definition Table 9-1. MC_RGM register description Address Name Description 0xC3FE_4000 RGM_FES Functional Event Status 0xC3FE_4002 RGM_DES Destructive Event Status 0xC3FE_4004 RGM_FERD Functional Event Reset Disable 0xC3FE_4006 RGM_DERD Destructive Event Reset Disable 0xC3FE_4010 RGM_FEAR Functional Event Alternate Request 0xC3FE_4012 RGM_DEAR Destructive Event Alternate Request 0xC3FE_4018 RGM_FESS Functional Event Short Sequence 0xC3FE_401A RGM_STDBY STANDBY Reset Sequence 0xC3FE_401C RGM_FBRE Functional Bidirectional Reset Enable 1 individual bits cleared on writing ‘1’ 2 write once: ‘0’ = disable, ‘1’ = enable. Access Size Location Supervisor half-word half-word half-word read/write1 read/write1 read/write2 on page 193 on page 194 on page 195 half-word read on page 197 half-word read/write on page 198 half-word read on page 199 half-word read/write on page 200 half-word read/write on page 202 half-word read/write on page 202 NOTE Any access to unused registers as well as write accesses to read-only registers will: • not change register content • cause a transfer error MPC5604B/C Microcontroller Reference Manual, Rev. 8 190 Freescale Semiconductor Table 9-2. MC_RGM Memory Map Address Name 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xC3FE RGM_ _4000 FES / RGM_ R DES F_EXR 000000 F_FLASH F_LVD45 F_CMU_FHL F_CMU_OLR F_FMPLL F_CHKSTOP F_SOFT F_CORE F_JTAG W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c F_LVD27 F_SWT F_LVD12_PD1 F_LVD12_PD0 F_POR R 00000000000 D_EXR W w1c 0xC3FE RGM_ _4004 FERD / RGM_ R DERD 000000 W D_FLASH D_LVD45 D_CMU_FHL D_CMU_OLR D_FMPLL D_CHKSTOP D_SOFT D_CORE D_JTAG w1c w1c w1c w1c D_LVD27 D_SWT D_LVD12_PD1 D_LVD12_PD0 R0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE _4008 … 0xC3FE _400C 0xC3FE RGM_ _4010 FEAR / RGM_ R DEAR W AR_EXR reserved 000000 AR_FLASH AR_LVD45 AR_CMU_FHL AR_CMU_OLR AR_FMPLL AR_CHKSTOP AR_SOFT AR_CORE AR_JTAG AR_LVD27 AR_SWT AR_LVD12_PD1 AR_LVD12_PD0 R0 0 0 0 0 0 0 0 0 0 0 0 W MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 191 Table 9-2. MC_RGM Memory Map (continued) Address Name 0xC3FE _4014 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved 0xC3FE RGM_ _4018 FESS / RGM_ R STDB Y SS_EXR 000000 SS_FLASH SS_LVD45 SS_CMU_FHL SS_CMU_OLR SS_FMPLL SS_CHKSTOP SS_SOFT SS_CORE SS_JTAG W BOOT_FROM_BKP_RAM R0 0 0 0 0 0 0 0 0000000 BE_FLASH BE_LVD45 BE_CMU_FHL BE_CMU_OLR BE_FMPLL BE_CHKSTOP BE_SOFT BE_CORE BE_JTAG W 0xC3FE RGM_ _401C FBRE R 000000 BE_EXR W 0xC3FE _4020 … 0xC3FE _7FFC reserved 9.3.1 Register descriptions Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the RGM_STDBY register may be accessed as a word at address 0xC3FE_4018, as a half-word at address 0xC3FE_401A, or as a byte at address 0xC3FE_401B. MPC5604B/C Microcontroller Reference Manual, Rev. 8 192 Freescale Semiconductor 9.3.1.1 Functional Event Status Register (RGM_FES) Address 0xC3FE_4000 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000000 F_EXR F_FLASH F_LVD45 F_CMU_FHL F_CMU_OLR F_FMPLL F_CHKSTOP F_SOFT F_CORE F_JTAG W w1c POR 0 0 w1c w1c w1c w1c w1c w1c w1c w1c w1c 00000000000000 Figure 9-2. Functional Event Status Register (RGM_FES) This register contains the status of the last asserted functional reset sources. It can be accessed in read/write on either supervisor mode or test mode. Register bits are cleared on write ‘1’. Table 9-3. Functional Event Status Register (RGM_FES) Field Descriptions Field Description F_EXR Flag for External Reset 0 No external reset event has occurred since either the last clear or the last destructive reset assertion 1 An external reset event has occurred F_FLASH Flag for code or data flash fatal error 0 No code or data flash fatal error event has occurred since either the last clear or the last destructive reset assertion 1 A code or data flash fatal error event has occurred F_LVD45 Flag for 4.5 V low-voltage detected 0 No 4.5 V low-voltage detected event has occurred since either the last clear or the last destructive reset assertion 1 A 4.5 V low-voltage detected event has occurred F_CMU_FHL Flag for CMU clock frequency higher/lower than reference 0 No CMU clock frequency higher/lower than reference event has occurred since either the last clear or the last destructive reset assertion 1 A CMU clock frequency higher/lower than reference event has occurred F_CMU_OL R Flag for FXOSC frequency lower than reference 0 No FXOSC frequency lower than reference event has occurred since either the last clear or the last destructive reset assertion 1 A FXOSC frequency lower than reference event has occurred F_FMPLL Flag for FMPLL fail 0 No FMPLL fail event has occurred since either the last clear or the last destructive reset assertion 1 A FMPLL fail event has occurred F_CHKSTOP Flag for checkstop reset 0 No checkstop reset event has occurred since either the last clear or the last destructive reset assertion 1 A checkstop reset event has occurred MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 193 Table 9-3. Functional Event Status Register (RGM_FES) Field Descriptions (continued) Field Description F_SOFT F_CORE F_JTAG Flag for software reset 0 No software reset event has occurred since either the last clear or the last destructive reset assertion 1 A software reset event has occurred Flag for debug control core reset 0 No debug control core reset event has occurred since either the last clear or the last destructive reset assertion 1 A debug control core reset event has occurred; this event can only be asserted when the DBCR0[RST] field is set by an external debugger. See the "Debug Support" chapter of the core reference manual for more details. Flag for JTAG initiated reset 0 No JTAG initiated reset event has occurred since either the last clear or the last destructive reset assertion 1 A JTAG initiated reset event has occurred 9.3.1.2 Destructive Event Status Register (RGM_DES) Address 0xC3FE_4002 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 00000000000 F_POR F_LVD27 F_SWT F_LVD12_PD1 F_LVD12_PD0 W w1c POR 1 0 w1c w1c w1c w1c 00000000000000 Figure 9-3. Destructive Event Status Register (RGM_DES) This register contains the status of the last asserted destructive reset sources. It can be accessed in read/write on either supervisor mode or test mode. Register bits are cleared on write ‘1’. Table 9-4. Destructive Event Status Register (RGM_DES) Field Descriptions Field Description F_POR F_LVD27 Flag for Power-On reset 0 No power-on event has occurred since the last clear (due to either a software clear or a low-voltage detection) 1 A power-on event has occurred Flag for 2.7 V low-voltage detected 0 No 2.7 V low-voltage detected event has occurred since either the last clear or the last power-on reset assertion 1 A 2.7 V low-voltage detected event has occurred MPC5604B/C Microcontroller Reference Manual, Rev. 8 194 Freescale Semiconductor Table 9-4. Destructive Event Status Register (RGM_DES) Field Descriptions (continued) Field Description F_SWT Flag for software watchdog timer 0 No software watchdog timer event has occurred since either the last clear or the last power-on reset assertion 1 A software watchdog timer event has occurred F_LVD12_P D1 Flag for 1.2 V low-voltage detected (power domain #1) 0 No 1.2 V low-voltage detected (power domain #1) event has occurred since either the last clear or the last power-on reset assertion 1 A 1.2 V low-voltage detected (power domain #1) event has occurred F_LVD12_P D0 Flag for 1.2 V low-voltage detected (power domain #0) 0 No 1.2 V low-voltage detected (power domain #0) event has occurred since either the last clear or the last power-on reset assertion 1 A 1.2 V low-voltage detected (power domain #0) event has occurred NOTE The F_POR flag is automatically cleared on a 1.2 V low-voltage detected (power domain #0 or #1) or a 2.7 V low-voltage detected. This means that if the power-up sequence is not monotonic (i.e the voltage rises and then drops enough to trigger a low-voltage detection), the F_POR flag may not be set but instead the F_LVD12_PD0, F_LVD12_PD1, or F_LVD27 flag is set on exiting the reset sequence. Therefore, if the F_POR, F_LVD12_PD0, F_LVD12_PD1, or F_LVD27 flags are set on reset exit, software should interpret the reset cause as power-on. NOTE In contrast to all other reset sources, the 1.2 V low-voltage detected (power domain #0) event is captured on its deassertion. Therefore, the status bit F_LVD12_PD0 is also asserted on the reset’s deassertion. In case an alternate event is selected, the SAFE mode or interrupt request are similarly asserted on the reset’s deassertion. 9.3.1.3 Functional Event Reset Disable Register (RGM_FERD) Address 0xC3FE_4004 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000000 D_EXR D_FLASH D_LVD45 D_CMU_FHL D_CMU_OLR D_FMPLL D_CHKSTOP D_SOFT D_CORE D_JTAG W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9-4. Functional Event Reset Disable Register (RGM_FERD) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 195 This register provides dedicated bits to disable functional reset sources.When a functional reset source is disabled, the associated functional event will trigger either a SAFE mode request or an interrupt request (see Section 9.3.1.5, “Functional Event Alternate Request Register (RGM_FEAR)). It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read only in user mode. Each byte can be written only once after power-on reset. Table 9-5. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions Field Description D_EXR Disable External Reset 0 An external reset event triggers a reset sequence 1 An external reset event generates a SAFE mode request D_FLASH Disable code or data flash fatal error 0 A code or data flash fatal error event triggers a reset sequence 1 A code or data flash fatal error event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_FLASH D_LVD45 Disable 4.5 V low-voltage detected 0 A 4.5 V low-voltage detected event triggers a reset sequence 1 A 4.5 V low-voltage detected event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_LVD45 D_CMU_FH L Disable CMU clock frequency higher/lower than reference 0 A CMU clock frequency higher/lower than reference event triggers a reset sequence 1 A CMU clock frequency higher/lower than reference event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_CMU_FHL D_CMU_OL R Disable FXOSC frequency lower than reference 0 A FXOSC frequency lower than reference event triggers a reset sequence 1 A FXOSC frequency lower than reference event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_CMU_OLR D_FMPLL Disable FMPLL fail 0 A FMPLL fail event triggers a reset sequence 1 A FMPLL fail event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_FMPLL D_CHKSTO P Disable checkstop reset 0 A checkstop reset event triggers a reset sequence 1 A checkstop reset event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_CHKSTOP D_SOFT Disable software reset 0 A software reset event triggers a reset sequence 1 A software reset event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_SOFT D_CORE Disable debug control core reset 0 A debug control core reset event triggers a reset sequence 1 A debug control core reset event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_CORE D_JTAG Disable JTAG initiated reset 0 A JTAG initiated reset event triggers a reset sequence 1 A JTAG initiated reset event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_JTAG MPC5604B/C Microcontroller Reference Manual, Rev. 8 196 Freescale Semiconductor 9.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) Address 0xC3FE_4006 Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000000000000 D_LVD27 D_SWT D_LVD12_PD1 D_LVD12_PD0 W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9-5. Destructive Event Reset Disable Register (RGM_DERD) This register provides dedicated bits to disable particular destructive reset sources. When a destructive reset source is disabled, the associated destructive event will trigger either a safe mode request or an interrupt request (see Section 9.3.1.6, “Destructive Event Alternate Request Register (RGM_DEAR)). Table 9-6. Destructive Event Reset Disable Register (RGM_DERD) Field Descriptions Field Description D_LVD27 Disable 2.7 V low-voltage detected 0 A 2.7 V low-voltage detected event triggers a reset sequence 1 A 2.7 V low-voltage detected event generates either a SAFE mode or an interrupt request depending on the value of RGM_DEAR.AR_LVD27 D_SWT Disable software watchdog timer 0 A software watchdog timer event triggers a reset sequence 1 A software watchdog timer event generates either a SAFE mode or an interrupt request depending on the value of RGM_DEAR. D_LVD12_P D1 Disable 1.2 V low-voltage detected (power domain #1) 0 A 1.2 V low-voltage detected (power domain #1) event triggers a reset sequence 1 A 1.2 V low-voltage detected (power domain #1) event generates either a SAFE mode or an interrupt request depending on the value of RGM_DEAR.AR_LVD12_PD1 D_LVD12_P D0 Disable 1.2 V low-voltage detected (power domain #0) 0 A 1.2 V low-voltage detected (power domain #0) event triggers a reset sequence 1 A 1.2 V low-voltage detected (power domain #0) event generates either a SAFE mode or an interrupt request depending on the value of RGM_DEAR.AR_LVD12_PD0 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 197 9.3.1.5 Functional Event Alternate Request Register (RGM_FEAR) Address 0xC3FE_4010 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000000 AR_EXR AR_FLASH AR_LVD45 AR_CMU_FHL AR_CMU_OLR AR_FMPLL AR_CHKSTOP AR_SOFT AR_CORE AR_JTAG W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9-6. Functional Event Alternate Request Register (RGM_FEAR) This register defines an alternate request to be generated when a reset on a functional event has been disabled. The alternate request can be either a SAFE mode request to MC_ME or an interrupt request to the system. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read only in user mode. Table 9-7. Functional Event Alternate Request Register (RGM_FEAR) Field Descriptions Field AR_EXR AR_FLASH AR_LVD45 AR_CMU_FHL AR_CMU_OLR AR_FMPLL Description Alternate Request for External Reset 0 Generate a SAFE mode request on an external reset event if the reset is disabled 1 Generate an interrupt request on an external reset event if the reset is disabled Alternate Request for code or data flash fatal error 0 Generate a SAFE mode request on a code or data flash fatal error event if the reset is disabled 1 Generate an interrupt request on a code or data flash fatal error event if the reset is disabled Alternate Request for 4.5 V low-voltage detected 0 Generate a SAFE mode request on a 4.5 V low-voltage detected event if the reset is disabled 1 Generate an interrupt request on a 4.5 V low-voltage detected event if the reset is disabled Alternate Request for CMU clock frequency higher/lower than reference 0 Generate a SAFE mode request on a CMU clock frequency higher/lower than reference event if the reset is disabled 1 Generate an interrupt request on a CMU clock frequency higher/lower than reference event if the reset is disabled Alternate Request for FXOSC frequency lower than reference 0 Generate a SAFE mode request on a FXOSC frequency lower than reference event if the reset is disabled 1 Generate an interrupt request on a FXOSC frequency lower than reference event if the reset is disabled For the case when RGM_FERD[D_CMU_OLR] = 1 & RGM_FEAR[AR_CMU_OLR] = 1, an RGM interrupt will not be generated for an FXOSC failure when the system clock = FXOSC as there will be no system clock to execute the interrupt service routine. However, the interrupt service routine will be executed if the FXOSC recovers at some point. The recommended use case for this feature is when the system clock = FIRC or FMPLL. Alternate Request for FMPLL fail 0 Generate a SAFE mode request on a FMPLL fail event if the reset is disabled 1 Generate an interrupt request on a FMPLL fail event if the reset is disabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 198 Freescale Semiconductor Table 9-7. Functional Event Alternate Request Register (RGM_FEAR) Field Descriptions (continued) Field AR_CHKSTOP AR_SOFT AR_CORE AR_JTAG Description Alternate Request for checkstop reset 0 Generate a SAFE mode request on a checkstop reset event if the reset is disabled 1 Generate an interrupt request on a checkstop reset event if the reset is disabled Alternate Request for software reset 0 Generate a SAFE mode request on a software reset event if the reset is disabled 1 Generate an interrupt request on a software reset event if the reset is disabled Alternate Request for debug control core reset 0 Generate a SAFE mode request on a debug control core reset event if the reset is disabled 1 Generate an interrupt request on a debug control core reset event if the reset is disabled Alternate Request for JTAG initiated reset 0 Generate a SAFE mode request on a JTAG initiated reset event if the reset is disabled 1 Generate an interrupt request on a JTAG initiated reset event if the reset is disabled 9.3.1.6 Destructive Event Alternate Request Register (RGM_DEAR) Address 0xC3FE_4012 Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000000000000 AR_LVD27 AR_SWT AR_LVD12_PD1 AR_LVD12_PD0 W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9-7. Destructive Event Alternate Request Register (RGM_DEAR) This register defines an alternate request to be generated when a reset on a destructive event has been disabled. The alternate request can be either a SAFE mode request to MC_ME or an interrupt request to the system. Table 9-8. Destructive Event Alternate Request Register (RGM_DEAR) Field Descriptions Field Description AR_LVD27 Alternate Request for 2.7 V low-voltage detected 0 Generate a SAFE mode request on a 2.7 V low-voltage detected event if the reset is disabled 1 Generate an interrupt request on a 2.7 V low-voltage detected event if the reset is disabled AR_SWT Alternate Request for software watchdog timer 0 Generate a SAFE mode request on a software watchdog timer event if the reset is disabled 1 Generate an interrupt request on a software watchdog timer event if the reset is disabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 199 Table 9-8. Destructive Event Alternate Request Register (RGM_DEAR) Field Descriptions (continued) Field Description AR_LVD12_ PD1 Alternate Request for 1.2 V low-voltage detected (power domain #1) 0 Generate a SAFE mode request on a 1.2 V low-voltage detected (power domain #1) event if the reset is disabled 1 Generate an interrupt request on a 1.2 V low-voltage detected (power domain #1) event if the reset is disabled AR_LVD12_ PD0 Alternate Request for 1.2 V low-voltage detected (power domain #0) 0 Generate a SAFE mode request on a 1.2 V low-voltage detected (power domain #0) event if the reset is disabled 1 Generate an interrupt request on a 1.2 V low-voltage detected (power domain #0) event if the reset is disabled 9.3.1.7 Functional Event Short Sequence Register (RGM_FESS) Address 0xC3FE_4018 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000000 SS_EXR SS_FLASH SS_LVD45 SS_CMU_FHL SS_CMU_OLR SS_FMPLL SS_CHKSTOP SS_SOFT SS_CORE SS_JTAG W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9-8. Functional Event Short Sequence Register (RGM_FESS) This register defines which reset sequence will be done when a functional reset sequence is triggered.The functional reset sequence can either start from PHASE1 or from PHASE3, skipping PHASE1 and PHASE2. NOTE This could be useful for fast reset sequence, for example to skip flash reset. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user mode. Table 9-9. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions Field Description SS_EXR Short Sequence for External Reset 0 The reset sequence triggered by an external reset event will start from PHASE1 1 The reset sequence triggered by an external reset event will start from PHASE3, skipping PHASE1 and PHASE2 SS_FLASH Short Sequence for code or data flash fatal error 0 The reset sequence triggered by a code or data flash fatal error event will start from PHASE1 1 The reset sequence triggered by a code or data flash fatal error event will start from PHASE3, skipping PHASE1 and PHASE2 MPC5604B/C Microcontroller Reference Manual, Rev. 8 200 Freescale Semiconductor Table 9-9. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions (continued) Field Description SS_LVD45 Short Sequence for 4.5 V low-voltage detected 0 The reset sequence triggered by a 4.5 V low-voltage detected event will start from PHASE1 1 The reset sequence triggered by a 4.5 V low-voltage detected event will start from PHASE3, skipping PHASE1 and PHASE2 SS_CMU_F HL Short Sequence for CMU clock frequency higher/lower than reference 0 The reset sequence triggered by a CMU clock frequency higher/lower than reference event will start from PHASE1 1 The reset sequence triggered by a CMU clock frequency higher/lower than reference event will start from PHASE3, skipping PHASE1 and PHASE2 SS_CMU_O LR Short Sequence for FXOSC frequency lower than reference 0 The reset sequence triggered by a FXOSC frequency lower than reference event will start from PHASE1 1 The reset sequence triggered by a FXOSC frequency lower than reference event will start from PHASE3, skipping PHASE1 and PHASE2 SS_FMPLL Short Sequence for FMPLL fail 0 The reset sequence triggered by a FMPLL fail event will start from PHASE1 1 The reset sequence triggered by a FMPLL fail event will start from PHASE3, skipping PHASE1 and PHASE2 SS_CHKST OP Short Sequence for checkstop reset 0 The reset sequence triggered by a checkstop reset event will start from PHASE1 1 The reset sequence triggered by a checkstop reset event will start from PHASE3, skipping PHASE1 and PHASE2 SS_SOFT Short Sequence for software reset 0 The reset sequence triggered by a software reset event will start from PHASE1 1 The reset sequence triggered by a software reset event will start from PHASE3, skipping PHASE1 and PHASE2 SS_CORE Short Sequence for debug control core reset 0 The reset sequence triggered by a debug control core reset event will start from PHASE1 1 The reset sequence triggered by a debug control core reset event will start from PHASE3, skipping PHASE1 and PHASE2 SS_JTAG Short Sequence for JTAG initiated reset 0 The reset sequence triggered by a JTAG initiated reset event will start from PHASE1 1 The reset sequence triggered by a JTAG initiated reset event will start from PHASE3, skipping PHASE1 and PHASE2 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 201 BOOT_FROM_BKP_RAM 9.3.1.8 STANDBY Reset Sequence Register (RGM_STDBY) Address 0xC3FE_401A Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 00000000 0000000 W reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9-9. STANDBY Reset Sequence Register (RGM_STDBY) This register defines the reset sequence to be applied on STANDBY mode exit. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read only in user mode. Table 9-10. STANDBY Reset Sequence Register (RGM_STDBY) Field Descriptions Field Description BOOT_ FROM_ BKP_RAM Boot from Backup SRAM indicator — This bit indicates whether the system will boot from backup SRAM or flash out of STANDBY exit. 0 Boot from default boot location on STANDBY exit 1 Boot from backup SRAM on STANDBY exit NOTE This register is reset on any enabled ‘destructive’ or ‘functional’ reset event. 9.3.1.9 Functional Bidirectional Reset Enable Register (RGM_FBRE) Address 0xC3FE_401C Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 000000 BE_EXR BE_FLASH BE_LVD45 BE_CMU_FHL BE_CMU_OLR BE_FMPLL BE_CHKSTOP BE_SOFT BE_CORE BE_JTAG W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9-10. Functional Bidirectional Reset Enable Register (RGM_FBRE) This register enables the generation of an external reset on functional reset. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 202 Freescale Semiconductor Table 9-11. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions Field Description BE_EXR Bidirectional Reset Enable for External Reset 0 RESET is asserted on an external reset event if the reset is enabled 1 RESET is not asserted on an external reset event BE_FLASH Bidirectional Reset Enable for code or data flash fatal error 0 RESET is asserted on a code or data flash fatal error event if the reset is enabled 1 RESET is not asserted on a code or data flash fatal error event BE_LVD45 Bidirectional Reset Enable for 4.5 V low-voltage detected 0 RESET is asserted on a 4.5 V low-voltage detected event if the reset is enabled 1 RESET is not asserted on a 4.5 V low-voltage detected event BE_CMU_F HL Bidirectional Reset Enable for CMU clock frequency higher/lower than reference 0 RESET is asserted on a CMU clock frequency higher/lower than reference event if the reset is enabled 1 RESET is not asserted on a CMU clock frequency higher/lower than reference event BE_CMU_O Bidirectional Reset Enable for FXOSC frequency lower than reference LR 0 RESET is asserted on a FXOSC frequency lower than reference event if the reset is enabled 1 RESET is not asserted on a FXOSC frequency lower than reference event BE_FMPLL Bidirectional Reset Enable for FMPLL fail 0 RESET is asserted on a FMPLL fail event if the reset is enabled 1 RESET is not asserted on a FMPLL fail event BE_CHKST Bidirectional Reset Enable for checkstop reset OP 0 RESET is asserted on a checkstop reset event if the reset is enabled 1 RESET is not asserted on a checkstop reset event BE_SOFT Bidirectional Reset Enable for software reset 0 RESET is asserted on a software reset event if the reset is enabled 1 RESET is not asserted on a software reset event BE_CORE Bidirectional Reset Enable for debug control core reset 0 RESET is asserted on a debug control core reset event if the reset is enabled 1 RESET is not asserted on a debug control core reset event BE_JTAG Bidirectional Reset Enable for JTAG initiated reset 0 RESET is asserted on a JTAG initiated reset event if the reset is enabled 1 RESET is not asserted on a JTAG initiated reset event 9.4 Functional Description 9.4.1 Reset State Machine The main role of MC_RGM is the generation of the reset sequence which ensures that the correct parts of the device are reset based on the reset source event. This is summarized in Table 9-12. Table 9-12. MC_RGM Reset Implications Source power-on reset all What Gets Reset External Reset Boot Mode Assertion Capture yes yes MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 203 Table 9-12. MC_RGM Reset Implications (continued) ‘destructive’ resets all except some clock/reset management external reset all except some clock/reset management and debug ‘functional’ resets all except some clock/reset management and debug shortened ‘functional’ resets3 flip-flops except some clock/reset management 1 the assertion of the external reset is controlled via the RGM_FBRE register 2 the boot mode is captured if the external reset is asserted 3 the short sequence is enabled via the RGM_FESS register yes yes yes yes programmable1 programmable2 programmable1 programmable2 NOTE JTAG logic has its own independent reset control and is not controlled by the MC_RGM in any way. The reset sequence is comprised of five phases managed by a state machine, which ensures that all phases are correctly processed through waiting for a minimum duration and until all processes that need to occur during that phase have been completed before proceeding to the next phase. The state machine used to produce the reset sequence is shown in Figure 9-11. MPC5604B/C Microcontroller Reference Manual, Rev. 8 204 Freescale Semiconductor x power-on or enabled ‘destructive’ reset PHASE0 power-up has completed fast internal RC oscillator (16 MHz) clock is running duration  3 fast internal RC oscillator (16 MHz) clock cycles FIRC stable, VREG voltage okay done enabled non-shortened external or ‘functional’ reset1 PHASE1 duration  350 fast internal RC oscillator (16 MHz) clock cycles PHASE2 durationfast internal RC oscillator (16 MHz) clock cycles code and data flash initialization done enabled shortened external or ‘functional’ reset PHASE3 duration 40fast internal RC oscillator (16 MHz) clock cycles code and data flash initialization done RESET released IDLE Figure 9-11. MC_RGM State Machine 9.4.1.1 PHASE0 Phase This phase is entered immediately from any phase on a power-on or enabled ‘destructive’ reset event. The reset state machine exits PHASE0 and enters PHASE1 on verification of the following: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 205 • power-up has completed • fast internal RC oscillator (16 MHz) clock is running • all enabled ‘destructive’ resets have been processed • all processes that need to be done in PHASE0 are completed — FIRC stable, VREG voltage okay • a minimum of 3 fast internal RC oscillator (16 MHz) clock cycles have elapsed since power-up completion and the last enabled ‘destructive’ reset event 9.4.1.2 PHASE1 Phase This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3, or IDLE on a non-masked external or ‘functional’ reset event if it has not been configured to trigger a ‘short’ sequence. The reset state machine exits PHASE1 and enters PHASE2 on verification of the following: • all enabled, non-shortened ‘functional’ resets have been processed • a minimum of 350 fast internal RC oscillator (16 MHz) clock cycles have elapsed since the last enabled external or non-shortened ‘functional’ reset event 9.4.1.3 PHASE2 Phase This phase is entered on exit from PHASE1. The reset state machine exits PHASE2 and enters PHASE3 on verification of the following: • all processes that need to be done in PHASE2 are completed — code and data flash initialization • a minimum of 8 fast internal RC oscillator (16 MHz) clock cycles have elapsed since entering PHASE2 9.4.1.4 PHASE3 Phase This phase is a entered either on exit from PHASE2 or immediately from IDLE on an enabled, shortened ‘functional’ reset event. The reset state machine exits PHASE3 and enters IDLE on verification of the following: • all processes that need to be done in PHASE3 are completed — code and data flash initialization • a minimum of 40 fast internal RC oscillator (16 MHz) clock cycles have elapsed since the last enabled, shortened ‘functional’ reset event 9.4.1.5 IDLE Phase This is the final phase and is entered on exit from PHASE3. When this phase is reached, the MC_RGM releases control of the system to the platform and waits for new reset events that can trigger a reset sequence. MPC5604B/C Microcontroller Reference Manual, Rev. 8 206 Freescale Semiconductor 9.4.2 Destructive Resets A ‘destructive’ reset indicates that an event has occurred after which critical register or memory content can no longer be guaranteed. The status flag associated with a given ‘destructive’ reset event (RGM_DES.F_ bit) is set when the ‘destructive’ reset is asserted and the power-on reset is not asserted. It is possible for multiple status bits to be set simultaneously, and it is software’s responsibility to determine which reset source is the most critical for the application. The ‘destructive’ reset can be optionally disabled by writing bit RGM_DERD.D_. NOTE The RGM_DERD register can be written only once between two power-on reset events. The device’s low-voltage detector threshold ensures that, when 1.2 V low-voltage detected (power domain #0) is enabled, the supply is sufficient to have the destructive event correctly propagated through the digital logic. Therefore, if a given ‘destructive’ reset is enabled, the MC_RGM ensures that the associated reset event will be correctly triggered to the full system. However, if the given ‘destructive’ reset is disabled and the voltage goes below the digital functional threshold, functionality can no longer be ensured, and the reset may or may not be asserted. An enabled destructive reset will trigger a reset sequence starting from the beginning of PHASE0. 9.4.3 External Reset The MC_RGM manages the external reset coming from RESET. The detection of a falling edge on RESET will start the reset sequence from the beginning of PHASE1. The status flag associated with the external reset falling edge event (RGM_FES.F_EXR bit) is set when the external reset is asserted and the power-on reset is not asserted. The external reset can optionally be disabled by writing bit RGM_FERD.D_EXR. NOTE The RGM_FERD register can be written only once between two power-on reset events. An enabled external reset will normally trigger a reset sequence starting from the beginning of PHASE1. Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence triggered by the external reset. When RGM_FESS.SS_EXR is set, the external reset will trigger a reset sequence starting directly from the beginning of PHASE3, skipping PHASE1 and PHASE2. This can be useful especially when an external reset should not reset the flash. The MC_RGM may also assert the external reset if the reset sequence was triggered by one of the following: • a power-on reset • a ‘destructive’ reset event MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 207 • an external reset event • a ‘functional’ reset event configured via the RGM_FBRE register to assert the external reset In this case, the external reset is asserted until the end of PHASE3. 9.4.4 Functional Resets A ‘functional’ reset indicates that an event has occurred after which it can be guaranteed that critical register and memory content is still intact. The status flag associated with a given ‘functional’ reset event (RGM_FES.F_ bit) is set when the ‘functional’ reset is asserted and the power-on reset is not asserted. It is possible for multiple status bits to be set simultaneously, and it is software’s responsibility to determine which reset source is the most critical for the application. The ‘functional’ reset can be optionally disabled by software writing bit RGM_FERD.D_. NOTE The RGM_FERD register can be written only once between two power-on reset events. An enabled functional reset will normally trigger a reset sequence starting from the beginning of PHASE1. Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence triggered by a functional reset. When RGM_FESS.SS_ is set, the associated ‘functional’ reset will trigger a reset sequence starting directly from the beginning of PHASE3, skipping PHASE1 and PHASE2. This can be useful especially in case a functional reset should not reset the flash module. 9.4.5 STANDBY Entry Sequence STANDBY mode can be entered only when the MC_RGM is in IDLE. On STANDBY entry, the MC_RGM moves to PHASE1. The minimum duration counter in PHASE1 does not start until STANDBY mode is exited. On entry to PHASE1 due to STANDBY mode entry, the resets for all power domains except power domain #0 are asserted. During this time, RESET is not asserted as the external reset can act as a wakeup for the device. There is an option to keep the flash inaccessible and in low-power mode on STANDBY exit by configuring the DRUN mode before STANDBY entry so that the flash is in power-down or low-power mode. If the flash is to be inaccessible, the PHASE2 and PHASE3 states do not wait for the flash to complete initialization before exiting, and the reset to the flash remains asserted. See the MC_ME chapter for details on the STANDBY and DRUN modes. 9.4.6 Alternate Event Generation The MC_RGM provides alternative events to be generated on reset source assertion. When a reset source is asserted, the MC_RGM normally enters the reset sequence. Alternatively, it is possible for each reset MPC5604B/C Microcontroller Reference Manual, Rev. 8 208 Freescale Semiconductor source event (except the power-on reset event) to be converted from a reset to either a SAFE mode request issued to the MC_ME or to an interrupt request issued to the core. Alternate event selection for a given reset source is made via the RGM_F/DERD and RGM_F/DEAR registers as shown in Table 9-13. Table 9-13. MC_RGM Alternate Event Selection RGM_F/DERD Bit Value 0 1 1 RGM_F/DEAR Bit Value X 0 1 Generated Event reset SAFE mode request interrupt request The alternate event is cleared by deasserting the source of the request (i.e. at the reset source that caused the alternate request) and also clearing the appropriate RGM_F/DES status bit. NOTE Alternate requests (SAFE mode as well as interrupt requests) are generated asynchronously. NOTE If a masked ‘destructive’ reset event which is configured to generate a SAFE mode/interrupt request occurs during PHASE0, it is ignored, and the MC_RGM will not send any safe mode/interrupt request to the MC_ME. The same is true for masked ‘functional’ reset events during PHASE1. 9.4.7 Boot Mode Capturing The MC_RGM provides sampling of the boot mode PA[8] and PA[9] for use by the system to determine the boot mode. This sampling is done five fast internal RC oscillator (16 MHz) clock cycles before the rising edge of RESET. The result of the sampling is then provided to the system. For each bit, a value of ‘1’ is produced only if each of the oldest three of the five samples have the value ‘1’, otherwise a value of ‘0’ is produced. NOTE In order to ensure that the boot mode is correctly captured, the application needs to apply the valid boot mode value to the device at least five fast internal RC oscillator (16 MHz) clock periods before the external reset deassertion crosses the VIH threshold. NOTE RESET can be low as a consequence of the internal reset generation. This will force re-sampling of the boot mode pins. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 209 MPC5604B/C Microcontroller Reference Manual, Rev. 8 210 Freescale Semiconductor Chapter 10 Power Control Unit (MC_PCU) 10.1 Introduction 10.1.1 Overview The power control unit (MC_PCU) is used to reduce the overall SoC power consumption. Power can be saved by disconnecting parts of the SoC from the power supply via a power switching device. The SoC is grouped into multiple parts having this capability which are called “power domains”. When a power domain is disconnected from the supply, the power consumption is reduced to zero in that domain. Any status information of such a power domain is lost. When re-connecting a power domain to the supply voltage, the domain draws an increased current until the power domain reaches its operational voltage. Power domains are controlled on a device mode basis. For each mode, software can configure whether a power domain is connected to the supply voltage (power-up state) or disconnected (power-down state). Maximum power saving is reached by entering the STANDBY mode. On each mode change request, the MC_PCU evaluates the power domain settings in the power domain configuration registers and initiates a power-down or a power-up sequence for each individual power domain. The power-up/down sequences are handled by finite state machines to ensure a smooth and safe transition from one power state to the other. Exiting the STANDBY mode can only be done via a system wakeup event as all power domains other than power domain #0 are in the power-down state. In addition, the MC_PCU acts as a bridge for mapping the VREG peripheral to the MC_PCU address space. Figure 10-1 depicts the MC_PCU block diagram. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 211 FIRC VREG power domains MC_PCU Registers Platform Interface Power Domain State Machines MC_ME core WKPU mapped peripheral Mapped Module Interface Figure 10-1. MC_PCU Block Diagram 10.1.2 Features The MC_PCU includes the following features: • support for 3 power domains • support for device modes RESET, DRUN, SAFE, TEST, RUN0…3, HALT, STOP, and STANDBY (for further mode details, please see the MC_ME chapter) • power states updating on each mode change and on system wakeup • a handshake mechanism for power state changes thus guaranteeing operable voltage • maps the VREG registers to the MC_PCU address space 10.1.3 Modes of Operation The MC_PCU is available in all device modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 212 Freescale Semiconductor 10.2 External Signal Description The MC_PCU has no connections to any external pins. 10.3 Memory Map and Register Definition Table 10-1. MC_PCU Register Description Address Name Description 0xC3FE_8000 PCU_PCONF0 0xC3FE_8004 PCU_PCONF1 0xC3FE_8008 PCU_PCONF2 0xC3FE_8040 PCU_PSTAT Power Domain #0 Configuration Power Domain #1 Configuration Power Domain #2 Configuration Power Domain Status Register Size Access Supervisor word word word word read read read/write read Location on page 215 on page 216 on page 217 on page 217 NOTE Any access to unused registers as well as write accesses to read-only registers will: • not change register content • cause a transfer error Table 10-2. MC_PCU Memory Map Address Name 0xC3FE PCU_PCONF0 _8000 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W STBY0 STOP HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RST R0 0 00 0 0xC3FE PCU_PCONF1 _8004 W R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W STBY0 STOP HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RST R0 0 00 0 0xC3FE PCU_PCONF2 _8008 W R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R0 0 00 0 W STBY0 STOP HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RST MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 213 Table 10-2. MC_PCU Memory Map (continued) Address Name 0xC3FE _800C … 0xC3FE _803C 0xC3FE PCU_PSTAT _8040 0x044 … 0x07C 0xC3FE _8080 … 0xC3FE _80FC 0xC3FE _8100 … 0xC3FE _BFFC 0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R0 0 0 0 0 0 0 0 0 0 0 0 0 W reserved VREG registers reserved PD2 PD1 PD0 10.3.1 Register Descriptions All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the PD0 field of the PCU_PSTAT register may be accessed as a word at address 0xC3FE_8040, as a half-word at address 0xC3FE_8042, or as a byte at address 0xC3FE_8043. MPC5604B/C Microcontroller Reference Manual, Rev. 8 214 Freescale Semiconductor 10.3.1.1 Power Domain #0 Configuration Register (PCU_PCONF0) Address 0xC3FE_8000 Access: Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY0 STOP HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RST 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 00 00 0 W Reset 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Figure 10-2. Power Domain #0 Configuration Register (PCU_PCONF0) This register defines for power domain #0 whether it is on or off in each device mode. As power domain #0 is the always-on power domain (and includes the MC_PCU), none of its bits are programmable. This register is available for completeness reasons. Table 10-3. Power Domain Configuration Register Field Descriptions Field Description RST Power domain control during RESET mode 0 Power domain off 1 Power domain on TEST Power domain control during TEST mode 0 Power domain off 1 Power domain on SAFE Power domain control during SAFE mode 0 Power domain off 1 Power domain on DRUN Power domain control during DRUN mode 0 Power domain off 1 Power domain on RUN0 Power domain control during RUN0 mode 0 Power domain off 1 Power domain on RUN1 Power domain control during RUN1 mode 0 Power domain off 1 Power domain on RUN2 Power domain control during RUN2 mode 0 Power domain off 1 Power domain on RUN3 Power domain control during RUN3 mode 0 Power domain off 1 Power domain on MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 215 Table 10-3. Power Domain Configuration Register Field Descriptions (continued) Field Description HALT Power domain control during HALT mode 0 Power domain off 1 Power domain on STOP Power domain control during STOP mode 0 Power domain off 1 Power domain on STBY0 Power domain control during STANDBY mode 0 Power domain off 1 Power domain on 10.3.1.2 Power Domain #1 Configuration Register (PCU_PCONF1) Address 0xC3FE_8004 Access: Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY0 STOP HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RST 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 00 00 0 W Reset 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 Figure 10-3. Power Domain #1 Configuration Register (PCU_PCONF1) This register defines for power domain #1 whether it is on or off in each device mode. The bit field description is the same as in Table 10-3. As the platform, clock generation, and mode control reside in power domain #1, this power domain is only powered down during the STANDBY mode. Therefore, none of the bits is programmable. This register is available for completeness reasons. The difference between PCU_PCONF0 and PCU_PCONF1 is the reset value of the STBY0 bit: During the STANDBY mode, power domain #1 is disconnected from the power supply, and therefore PCU_PCONF1.STBY0 is always ‘0’. Power domain #0 is always on, and therefore PCU_PCONF0.STBY0 is ‘1’. For further details about STANDBY mode, please see Section 10.4.4.2, “STANDBY Mode Transition. MPC5604B/C Microcontroller Reference Manual, Rev. 8 216 Freescale Semiconductor 10.3.1.3 Power Domain #2 Configuration Register (PCU_PCONF2) Address 0xC3FE_8008 Access: Supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 00 0 TEST SAFE DRUN RUN0 RUN1 RUN2 RUN3 HALT STOP STBY0 W Reset 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 Figure 10-4. Power Domain #2 Configuration Register (PCU_PCONF2) This register defines for power domain #2 whether it is on or off in each device mode. The bit field description is the same as in Table 10-3. 10.3.1.4 Power Domain Status Register (PCU_PSTAT) Address 0xC3FE_8040 Access: Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PD1 PD2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Figure 10-5. Power Domain Status Register (PCU_PSTAT) This register reflects the power status of all available power domains. Table 10-4. Power Domain Status Register (PCU_PSTAT) Field Descriptions Field PDn Power status for power domain #n 0 Power domain is inoperable 1 Power domain is operable Description MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 217 10.4 Functional Description 10.4.1 General The MC_PCU controls all available power domains on a device mode basis. The PCU_PCONFn registers specify during which system/user modes a power domain is powered up. The power state for each individual power domain is reflected by the bits in the PCU_PSTAT register. On a mode change, the MC_PCU evaluates which power domain(s) must change power state. The power state is controlled by a state machine (FSM) for each individual power domain which ensures a clean and safe state transition. 10.4.2 Reset / Power-On Reset After any reset, the SoC will transition to the RESET mode during which all power domains are powered up (see the MC_ME chapter). Once the reset sequence has been completed, the DRUN mode is entered and software can begin the MC_PCU configuration. 10.4.3 MC_PCU Configuration Per default, all power domains are powered in all modes other than STANDBY. Software can change the configuration for each power domain on a mode basis by programming the PCU_PCONFn registers. Each power domain which is powered down is held in a reset state. Read/write accesses to peripherals in those power domains will result in a transfer error. 10.4.4 Mode Transitions On a mode change requested by the MC_ME, the MC_PCU evaluates the power configurations for all power domains. It compares the settings in the PCU_PCONFn registers for the new mode with the settings for the current mode. If the configuration for a power domain differs between the modes, a power state change request is generated. These requests are handled by a finite state machine to ensure a smooth and safe transition from one power state to another. 10.4.4.1 DRUN, SAFE, TEST, RUN0…3, HALT, and STOP Mode Transition The DRUN, SAFE, TEST, RUN0…3, HALT, and STOP modes allow an increased power saving. The level of power saving is software-controllable via the settings in the PCU_PCONFn registers for power domain #2 onwards. The settings for power domains #0 and #1 can not be changed. Therefore, power domains #0 and #1 remain connected to the power supply for all modes beside STANDBY. Figure 10-6 shows an example for a mode transition from RUN0 to HALT and back, which will result in power domain #2 being powered down during the HALT mode. In this case, PCU_PCONF2.HALT is programmed to be ‘0’. MPC5604B/C Microcontroller Reference Manual, Rev. 8 218 Freescale Semiconductor When the MC_PCU receives the mode change request to HALT mode, it starts its power-down phase. During the power-down phase, clocks are disabled and the reset is asserted resulting in a loss of all information for this power domain. Then the power domain is disconnected from the power supply (power-down state). new mode requested by ME RUN0 HALT RUN0 PSTAT.PD2 voltage in power domain #2 current mode RUN0 HALT RUN0 Notes: power-up state power-down phase power-down state Not drawn to scale; PCONF2.RUN0 = 1; PCONF2.HALT = 0 power-up phase power-up state Figure 10-6. MC_PCU Events During Power Sequences (non-STANDBY mode) When the MC_PCU receives a mode change request to RUN0, it starts its power-up phase if PCU_PCONF2.RUN0 is ‘1’. The power domain is re-connected to the power supply, and the voltage in power domain #2 will increase slowly. Once the voltage of power domain #2 is within an operable range, its clocks are enabled, and its resets are deasserted (power-up state). NOTE It is possible that, due to a mode change, power-up is requested before a power domain completed its power-down sequence. In this case, the information in that power domain is lost. 10.4.4.2 STANDBY Mode Transition STANDBY offers the maximum power saving. The level of power saving is software-controllable via the settings in the PCU_PCONFn registers for power domain #2 onwards. Power domain #0 stays connected to the power supply while power domain #1 is disconnected from the power supply. Amongst others power domain #1 contains the platform and the MC_ME. Therefore this mode differs from all other user/system modes. Once STANDBY is entered it can only be left via a system wakeup. On exiting the STANDBY mode, all power domains are powered up according to the settings in the PCU_PCONFn registers, and the DRUN mode is entered. In DRUN mode, at least power domains #0 and #1 are powered. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 219 Figure 10-7 shows an example for a mode transition from RUN0 to STANDBY to DRUN. All power domains which have PCU_PCONFn.STBY0 cleared will enter power-down phase. In this example only power domain #1 will be disabled during STANDBY mode. When the MC_PCU receives the mode change request to STANDBY mode it starts the power down phase for power domain #1. During the power down phase, clocks are disabled and reset is asserted resulting in a loss of all information for this power domain. Then the power domain is disconnected from the power supply (power-down state). new mode requested by ME RUN0 STANDBY Mode set due to reset being asserted to power domain #1 PSTAT.PD1 voltage in power domain #1 wakeup request current mode RUN0 STANDBY DRUN power-up state power-down phase power-down state Notes: Not drawn to scale; PCONF1.RUN0 = 1; PCONF1.STBY0 = 0 power-up phase power-up state Figure 10-7. MC_PCU Events During Power Sequences (STANDBY mode) When the MC_PCU receives a system wakeup request, it starts the power-up phase. The power domain is re-connected to the power supply and the voltage in power domain #1 will increase slowly. Once the voltage is in an operable range, clocks are enabled and the reset is be deasserted (power-up state). NOTE It is possible that due to a wakeup request, power-up is requested before a power domain completed its power-down sequence. In this case, the information in that power domain is lost. 10.4.4.3 Power Saving for Memories During STANDBY Mode All memories which are not powered down during STANDBY mode automatically enter a power saving state. No software configuration is required to enable this power saving state. While a memory is residing in this state an increased power saving is achieved. Data in the memories is retained. MPC5604B/C Microcontroller Reference Manual, Rev. 8 220 Freescale Semiconductor 10.5 Initialization Information To initialize the MC_PCU, the registers PCU_PCONF2… should be programmed. After programming is done, those registers should no longer be changed. 10.6 Application Information 10.6.1 STANDBY Mode Considerations STANDBY offers maximum power saving possibility. But power is only saved during the time a power domain is disconnected from the supply. Increased power is required when a power domain is re-connected to the power supply. Additional power is required during restoring the information (e.g. in the platform). Care should be taken that the time during which the SoC is operating in STANDBY mode is significantly longer than the required time for restoring the information. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 221 MPC5604B/C Microcontroller Reference Manual, Rev. 8 222 Freescale Semiconductor Chapter 11 Voltage Regulators and Power Supplies 11.1 Voltage regulators The power blocks provide a 1.2 V digital supply to the internal logic of the device. The main supply is (3.3 V–5 V ± 10%) and digital/regulated output supply is (1.2 V ± 10%). The voltage regulator used in MPC5604B comprises three regulators. • High power regulator (HPREG) • Low power regulator (LPREG) • Ultra low power regulator (ULPREG) The HPREG and LPREG regulators are switched off during STANDBY mode to save consumption from the regulator itself. In STANDBY mode, the supply is provided by the ULPREG regulator. In STOP mode, the user can configure the HPREG regulator to switch-off (Refer to MC_ME chapter). In this case, when current is low enough to be handled by LPREG alone, the HPREG regulator is switch-off and the supply is provided by the LPREG regulator. The internal voltage regulator requires an external capacitance (CREG) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. The regulator has two digital domains, one for the high power regulator (HPREG) and the low power regulator (LPREG) called “High Power domain” and another one for the ultra low power regulator (ULPREG) called “Standby domain.” For each domain there is a low voltage detector for the 1.2 V output voltage. Additionally there are two low voltage detectors for the main/input supply with different thresholds, one at the 3.3 V level and the other one at the 5 V level. 11.1.1 High power regulator (HPREG) The HPREG converts the 3.3 V–5 V input supply to a 1.2 V digital supply. For more information, see the voltage regulator electrical characteristics section of the data sheet. The regulator can be switched off by software. Refer to the main voltage regulator control bit (MVRON) of the mode configuration registers in the mode entry module chapter of the reference manuals. 11.1.2 Low power regulator (LPREG) The LPREG generates power for the device in the STOP mode, providing the output supply of 1.2 V. It always sees the minimum external capacitance. The control part of the regulator can be used to disable the low power regulator. It is managed by MC_ME. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 223 11.1.3 Ultra low power regulator (ULPREG) The ULPREG generates power for the standby domain as well as a part of the main domain and might or might not see the external capacitance. The control circuit of ULPREG can be used to disable the ultra low power regulator by software: This action is managed by MC_ME. 11.1.4 LVDs and POR There are three kinds of LVD available: 1. LVD_MAIN for the 3.3 V–5 V input supply with thresholds at approximately 3 V level1 2. LVD_MAIN5 for the 3.3 V–5 V input supply with threshold at approximately 4.5 V level1 3. LVD_DIG for the 1.2 V output voltage The LVD_MAIN and LVD_MAIN5 sense the 3.3 V–5 V power supply for CORE, shared with IO ring supply and indicate when the 3.3 V–5 V supply is stabilized. Two LVD_DIGs are provided in the design. One LVD_DIG is placed in the high power domain and senses the HPREG/LPREG output notifying that the 1.2 V output is stable. The other LVD_DIG is placed in the standby domain and senses the standby 1.2 V supply level notifying that the 1.2 V output is stable. The reference voltage used for all LVDs is generated by the low power reference generator and is trimmed for LVD_DIG, using the bits LP[4:7]. Therefore, during the pre-trimming period, LVD_DIG exhibits higher thresholds, whereas during post trimming, the thresholds come in the desired range. Power-down pins are provided for LVDs. When LVDs are power-down, their outputs are pulled high. POR is required to initialize the device during supply rise. POR works only on the rising edge of the main supply. To ensure its functioning during the following rising edge of the supply, it is reset by the output of the LVD_MAIN block when main supply reaches below the lower voltage threshold of the LVD_MAIN. POR is asserted on power-up when Vdd supply is above VPORUP min (refer to data sheet for details). It will be released only after Vdd supply is above VPORH (refer to data sheet for details). Vdd above VPORH ensures power management module including internal LVDs modules are fully functional. 11.1.5 VREG digital interface The voltage regulator digital interface provides the temporization delay at initial power-up and at exit from low-power modes. A signal, indicating that Ultra Low Power domain is powered, is used at power-up to release reset to temporization counter. At exit from low-power modes, the power-down for high power regulator request signal is monitored by the digital interface and used to release reset to the temporization counter. In both cases, on completion of the delay counter, a end-of-count signal is released, it is gated with an other signal indicating main domain voltage fine in order to release the VREGOK signal. This is used by MC_RGM to release the reset to the device. It manages other specific requirements, like the transition between high power/low power mode to ultra low power mode avoiding a voltage drop below the permissible threshold limit of 1.08 V. The VREG digital interface also holds control register to mask 5 V LVD status coming from the voltage regulator at the power-up. 1. See section “Voltage monitor electrical characteristics” of the data sheet for detailed information about this voltage value. MPC5604B/C Microcontroller Reference Manual, Rev. 8 224 Freescale Semiconductor 11.1.6 Register description The VREG_CTL register is mapped to the MC_PCU address space as described in Chapter 10, Power Control Unit (MC_PCU). Address: 0xC3FE_8080 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 5V_LVD_MASK Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 11-1. Voltage Regulator Control Register (VREG_CTL) Table 11-1. VREG_CTL field descriptions Field Description 5V_LVD_MASK Mask bit for 5 V LVD from regulator This is a read/write bit and must be unmasked by writing a ‘1’ by software to generate LVD functional reset request to MC_RGM for 5 V trip. 1: 5 V LVD is masked 0: 5 V LVD is not masked. 11.2 Power supply strategy From a power-routing perspective, the device is organized as follows. The device provides four dedicated supply domains at package level: 1. HV (high voltage external power supply for I/Os and most analog module) — This must be provided externally through VDD_HV/VSS_HV power pins. Voltage values should be aligned with VDD/VSS. Refer to data sheet for details. 2. ADC (high voltage external power supply for ADC module) — This must be provided externally through VDD_HV_ADC/VSS_HV_ADC power pins. Voltage values should be aligned with VDD_HV_ADC/VSS_HV_ADC. Refer to data sheet for details. 3. BV (high voltage external power supply for voltage regulator module) — This must be provided externally through VDD_BV_/VSS_BV power pins. Voltage values should be aligned with VDD/VSS. Refer to data sheet for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 225 4. LV (low voltage internal power supply for core, FMPLL and Flash digital logic) — This is generated internally by embedded voltage regulator and provided to the core, FMPLL and Flash. Three VDD_LV/VSS_LV pins pairs are provided to connect the three decoupling capacitances. This is generated internally by internal voltage regulator but provided outside to connect stability capacitor. Refer to data sheet for details. The four dedicated supply domains are further divided within the package in order to reduce as much as possible EMC and noise issues. • HV_IO: High voltage pad supply • HV_FLAn: High voltage Flash supply • HV_OSC0REG1: High voltage external oscillator and regulator supply • HV_ADR: High voltage reference for ADC module. Supplies are further star routed to reduce impact of ADC resistive reference on ADC capacitive reference accuracy. • HV_ADV: High voltage supply for ADC module • BV: High voltage supply for voltage regulator ballast. These two ballast pads are used to supply core and Flash. Each pad contains two ballasts to supply 80 mA and 20 mA respectively. Core is hence supplied through two ballasts of 80 mA capability and CFlash and DFlash through two 20 mA ballasts. The HV supply for both ballasts is shorted through double bonding. • LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. • LV_FLAn: Low voltage supply for Flash module n. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. • LV_PLL2: Low voltage supply for FMPLL 11.3 Power domain organization Based on stringent requirements for current consumption in different operational modes, the device is partitioned into different power domains. Organization into these power domains primarily means separate power supplies which are separated from each other by use of power switches (switch SW1 for power domain No. 1 and switch SW2 for power domain No. 2 as shown in Figure 11-2). These different separated power supplies are hence enabling to switch off power to certain regions of the device to avoid even leakage current consumption in logic supplied by the corresponding power supply. This device employs three primary power domains, namely PD0, PD1 and PD2. As PCU supports dynamic power down of domains based on different device mode, such a possible domain is depicted below in dotted periphery. Power domain organization and connections to the internal regulator are depicted in Figure 11-2. 1. Regulator ground is separated from oscillator ground and shorted to the LV ground through star routing 2. During production test, it is also possible to provide the VDD_LV externally through pins by configuring regulator in bypass mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 226 Freescale Semiconductor PD0 PCU RGM ipe_pd ipe_iso0 nbypass POR2HV POR1HV VDD5B Vdd HPPD LPPD VREG ULPVDD HPVDD LPVDD VGATE Vss HV Vss VDD_LV_BKP WKPU RC Dig SIRC API FIRC 8 KB SRAM Option bits CAN sampler SW2 24 KB SRAM SW1 PD2 e200z0h JTAG platform CGM PAx PBx PCx PEx PFx PGx Reset CGL Wakeup Pads Vdd5_cfla CFlash ME 330nF 16 KB SRAM Peripheral Set Peripheral Set DFlash PA0 PA1 330nF Vdd5_dlf SIUL PA2 VDD_LV_COR VDD_LV_FLA0 PD1 VDD_LV_BKP VDD_LV_FLA1 VDD_LV_BKP domain PH15 FMPLL ADC VDD12 330nF AVSSref AVSSsupply AVDDsupply AVDDref MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 227 Figure 11-2. Power domain organization MPC5604B/C Microcontroller Reference Manual, Rev. 8 228 Freescale Semiconductor Chapter 12 Wakeup Unit (WKPU) 12.1 Overview The Wakeup Unit supports 2 internal sources (WKPU[0:1]) and up to 181 external sources (WKPU[2:19]) that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests. Figure 12-1 is the block diagram of the Wakeup Unit and its interfaces to other system components. The wakeup vector mapping is shown in Table 12-1. All unused WKPU pins must use a pull resistor — either pullup (internal or external) or pulldown (external) — to ensure no leakage from floating inputs. Table 12-1. Wakeup vector mapping Wakeup number Port SIU PCR# Port input function1 (can be used in conjunction with WKPU function) WKPU IRQ to INTC WKPU0 API n/a3 WKPU1 RTC n/a3 — WakeUp_IRQ_0 46 — WKPU2 PA1 PCR1 NMI WKPU3 PA2 PCR2 — WKPU4 PB1 PCR17 CAN0-RX WKPU5 PC11 PCR43 CAN1-RX, CAN4-RX WKPU6 PE0 PCR64 CAN5-RX WKPU7 PE9 PCR73 CAN2-RX, CAN3-RX WKPU8 PB10 PCR26 — WakeUp_IRQ_1 47 WKPU9 PA4 PCR4 — WKPU10 PA15 PCR15 — WKPU11 PB3 PCR19 LIN0-RX WKPU12 PC7 PCR39 LIN1-RX WKPU13 PC9 PCR41 LIN2-RX WKPU14 PE11 PCR75 LIN3-RX WKPU15 PF11 PCR91 — IRQ# 64-pin QFP 100-pin QFP 144-pin QFP 208-pin BGA WISR EIF0 EIF1 EIF2 EIF3 EIF4 EIF5 EIF6 EIF7 EIF8 EIF9 EIF10 EIF11 EIF12 EIF13 EIF14 EIF15 Register 2 bit position Package 31 3 3 3 3 30 3 3 3 3 29   28   27   26 x4    25 x4    24 x4    23   22   21   20   19   18   17 x4    16 x4 x4   1. Up to 18 external sources in 144-pin LQFP and 208BGA; up to 14 external sources in 100-pin LQFP MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 229 Table 12-1. Wakeup vector mapping (continued) IRQ# 64-pin QFP 100-pin QFP 144-pin QFP 208-pin BGA Wakeup number Port SIU PCR# Port input function1 (can be used in conjunction with WKPU function) WKPU IRQ to INTC WISR Register 2 bit position Package WKPU16 PF13 PCR93 — WakeUp_IRQ_2 48 EIF16 15 x4 x4   WKPU17 PG3 PCR99 — EIF17 14 x4 x4   WKPU18 PG5 PCR101 — EIF18 13 x4 x4   WKPU19 PA0 PCR0 — EIF19 12   1 This column does not contain an exhaustive list of functions on that pin. Rather, it includes peripheral communication functions (such as CAN and LINFlex Rx) that could be used to wake up the microcontroller. DSPI pins are not included because DSPI would typically be used in master mode. 2 WISR, IRER, WRER, WIFEER, WIFEEF, WIFER, WIPUER 3 Port not required to use timer functions. 4 Unavailable WKPU pins must use internal pullup enabled using WIPUER. Peripheral Bridge Wakeup Unit NMI / Wakeup - Configuration NMI enable filter bypass wakeup IPS BUS IRQ / Wakeup - Configuration filter bypass system wakeup IRQs Platform filter 0-19 filter Pads IOMux Mode / Power Control 0-2 Interrupt Controller 0-19 RTC, etc. Figure 12-1. WKPU block diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 230 Freescale Semiconductor 12.2 Features The Wakeup Unit supports these distinctive features: • Non-maskable interrupt support with — 1 NMI source with bypassable glitch filter — Independent interrupt destination: non-maskable interrupt, critical interrupt, or machine check request — Edge detection • External wakeup/interrupt support with — 3 system interrupt vectors for up to 18 interrupt sources — Analog glitch filter per each wakeup line — Independent interrupt mask — Edge detection — Configurable system wakeup triggering from all interrupt sources — Configurable pullup • On-chip wakeup support — 2 wakeup sources — Wakeup status mapped to same register as external wakeup/interrupt status 12.3 External signal description The Wakeup Unit has 18 signal inputs that can be used as external interrupt sources in normal RUN mode or as system wakeup sources in all power down modes. The 18 external signal inputs include one signal input that can be used as a non-maskable interrupt source in normal RUN, HALT or STOP modes or a system wakeup source in STOP or STANDBY modes. NOTE The user should be aware that the Wake-up pins are enabled in ALL modes, therefore, the Wake-up pins should be correctly terminated to ensure minimal current consumption. Any unused Wake-up signal input should be terminated by using an external pull-up or pull-down, or by internal pull-up enabled at WKPU_WIPUER. Also, care has to be taken on packages where the Wake-up signal inputs are not bonded. For these packages the user must ensure the internal pull-up are enabled for those signals not bonded. 12.4 Memory map and register description This section provides a detailed description of all registers accessible in the WKPU module. 12.4.1 Memory map Table 12-2 gives an overview on the WKPU registers implemented. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 231 Table 12-2. WKPU memory map Base address: 0xC3F9_4000 Address offset 0x00 0x04 – 0x07 0x08 0x0C – 0x13 0x14 0x18 0x1C 0x20 – 0x27 0x28 0x2C 0x30 0x34 Register name NMI Status Flag Register (NSR) Reserved NMI Configuration Register (NCR) Reserved Wakeup/Interrupt Status Flag Register (WISR) Interrupt Request Enable Register (IRER) Wakeup Request Enable Register (WRER) Reserved Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) Wakeup/Interrupt Filter Enable Register (WIFER) Wakeup/Interrupt Pullup Enable Register (WIPUER) Location on page 232 on page 233 on page 234 on page 235 on page 235 on page 236 on page 236 on page 237 on page 237 NOTE Reserved registers will read as 0, writes will have no effect. If SSCM_ERROR[RAE] is enabled, a transfer error will be issued when trying to access completely reserved register space. 12.4.2 NMI Status Flag Register (NSR) This register holds the non-maskable interrupt status flags. Offset: 0x00 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R NIF0 00000000000000 NOVF0 W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-2. NMI Status Flag Register (NSR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 232 Freescale Semiconductor Table 12-3. NSR field descriptions Field NIF0 NOVF0 Description NMI Status Flag If enabled (NREE0 or NFEE0 set), NIF0 causes an interrupt request. 1 An event as defined by NREE0 and NFEE0 has occurred 0 No event has occurred on the pad NMI Overrun Status Flag It will be a copy of the current NIF0 value whenever an NMI event occurs, thereby indicating to the software that an NMI occurred while the last one was not yet serviced. If enabled (NREE0 or NFEE0 set), NOVF0 causes an interrupt request. 1 An overrun has occurred on NMI input 0 No overrun has occurred on NMI input 12.4.3 NMI Configuration Register (NCR) This register holds the configuration bits for the non-maskable interrupt settings. Offset: 0x08 Access: User read/write NLOCK0 NWRE0 NREE0 NFEE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 NDSS0 W 00000000 NFE0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-3. NMI Configuration Register (NCR) Table 12-4. NCR field descriptions Field Description NLOCK0 NDSS0 NMI Configuration Lock Register Writing a 1 to this bit locks the configuration for the NMI until it is unlocked by a system reset. Writing a 0 has no effect. NMI Destination Source Select 00 Non-maskable interrupt 01 Critical interrupt 10 Machine check request 11 Reserved—no NMI, critical interrupt, or machine check request generated MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 233 Table 12-4. NCR field descriptions (continued) Field NWRE0 NREE0 NFEE0 NFE0 Description NMI Wakeup Request Enable 1 A set NIF0 bit or set NOVF0 bit causes a system wakeup request 0 System wakeup requests from the corresponding NIF0 bit are disabled Note: Software should only enable the NMI after the IVPR/IVOR registers have been configured. This should be noted when booting from RESET or STANDBY mode as all registers will have been cleared to their reset state. NMI Rising-edge Events Enable 1 Rising-edge event is enabled 0 Rising-edge event is disabled NMI Falling-edge Events Enable 1 Falling-edge event is enabled 0 Falling-edge event is disabled NMI Filter Enable Enable analog glitch filter on the NMI pad input. 1 Filter is enabled 0 Filter is disabled NOTE Writing a ‘0’ to both NREE0 and NFEE0 disables the NMI functionality completely (that is, no system wakeup or interrupt will be generated on any pad activity)! 12.4.4 Wakeup/Interrupt Status Flag Register (WISR) This register holds the wakeup/interrupt flags. Offset: 0x14 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 EIF[19:0]1 W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-4. Wakeup/Interrupt Status Flag Register (WISR) 1 EIF[18:15] are not available in all 100-pin packages. Field EIF[x] Table 12-5. WISR field descriptions Description External Wakeup/Interrupt WKPU[x] Status Flag This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRER[x]), EIF[x] causes an interrupt request. 1 An event as defined by WIREER and WIFEER has occurred 0 No event has occurred on the pad MPC5604B/C Microcontroller Reference Manual, Rev. 8 234 Freescale Semiconductor NOTE Status bits associated with on-chip wakeup sources are located to the left of the external wakeup/interrupt status bits and are read only. The wakeup for these sources must be configured and cleared at the on-chip wakeup source. Also, the configuration registers for the external interrupts/wakeups do not have corresponding bits. 12.4.5 Interrupt Request Enable Register (IRER) This register is used to enable the interrupt messaging from the wakeup/interrupt pads to the interrupt controller. Offset: 0x18 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 EIRE[19:0]1 W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-5. Interrupt Request Enable Register (IRER) 1 EIRE[18:15] are not available in all 100-pin packages. Table 12-6. IRER field descriptions Field EIRE[x] Description External Interrupt Request Enable x 1 A set EIF[x] bit causes an interrupt request 0 Interrupt requests from the corresponding EIF[x] bit are disabled 12.4.6 Wakeup Request Enable Register (WRER) This register is used to enable the system wakeup messaging from the wakeup/interrupt pads to the mode entry and power control modules. Offset: 0x1C Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 W WRE[19:0]1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-6. Wakeup Request Enable Register (WRER) 1 WRE[18:15] are not available in all 100-pin packages. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 235 Table 12-7. WRER field descriptions Field WRE[x] Description External Wakeup Request Enable x 1 A set EIF[x] bit causes a system wakeup request 0 System wakeup requests from the corresponding EIF[x] bit are disabled 12.4.7 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) This register is used to enable rising-edge triggered events on the corresponding wakeup/interrupt pads. NOTE The RTC_API can only be configured on the rising edge. . Offset: 0x28 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 W IREE[19:0]1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-7. Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) 1 IREE[18:15] are not available in all 100-pin packages. Table 12-8. WIREER field descriptions Field IREE[x] Description External Interrupt Rising-edge Events Enable x 1 Rising-edge event is enabled 0 Rising-edge event is disabled 12.4.8 Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) This register is used to enable falling-edge triggered events on the corresponding wakeup/interrupt pads. Offset: 0x2C Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 W IFEE[19:0]1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-8. Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) 1 IFEE[18:15] are not available in all 100-pin packages. MPC5604B/C Microcontroller Reference Manual, Rev. 8 236 Freescale Semiconductor Field IFEEx Table 12-9. WIFEER field descriptions Description External Interrupt Falling-edge Events Enable x 1 Falling-edge event is enabled 0 Falling-edge event is disabled 12.4.9 Wakeup/Interrupt Filter Enable Register (WIFER) This register is used to enable an analog filter on the corresponding interrupt pads to filter out glitches on the inputs. NOTE There is no analog filter for the RTC_API. Offset: 0x30 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 W IFE[19:0]1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-9. Wakeup/Interrupt Filter Enable Register (WIFER) 1 IFE[18:15] are not available in all 100-pin packages. Field IFE[x] Table 12-10. WIFER field descriptions Description External Interrupt Filter Enable x Enable analog glitch filter on the external interrupt pad input. 1 Filter is enabled 0 Filter is disabled 12.4.10 Wakeup/Interrupt Pullup Enable Register (WIPUER) This register is used to enable a pullup on the corresponding interrupt pads to pull an unconnected wakeup/interrupt input to a value of ‘1’. Offset: 0x34 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 W IPUE[19:0]1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-10. Wakeup/Interrupt Pullup Enable Register (WIPUER) 1 IPUE[18:15] are not available in all 100-pin packages. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 237 Table 12-11. WIPUER field descriptions Field IPUE[x] External Interrupt Pullup Enable x 1 Pullup is enabled 0 Pullup is disabled Description 12.5 Functional description 12.5.1 General This section provides a complete functional description of the Wakeup Unit. 12.5.2 Non-maskable interrupts The Wakeup Unit supports one non-maskable interrupt which is allocated to the following pins: • 100-pin LQFP: Pin 7 • 144-pin LQFP: Pin 11 • 208-pin BGA: Pin F3 The Wakeup Unit supports the generation of three types of interrupts from the NMI. The Wakeup Unit supports the capturing of a second event per NMI input before the interrupt is cleared, thus reducing the chance of losing an NMI event. Each NMI passes through a bypassable analog glitch filter. NOTE Glitch filter control and pad configuration should be done while the NMI is disabled in order to avoid erroneous triggering by glitches caused by the configuration process itself. MPC5604B/C Microcontroller Reference Manual, Rev. 8 238 Freescale Semiconductor NMI critical IRQ machine check CPU Destination Mode/ Pwr Ctl Wakeup Enable Flag Overrun Edge Detect Glitch Filter NDSS0 NWRE0 NREE0 NFEE0 NFE0 NMI Configuration Register (NCR) Figure 12-11. NMI pad diagram 12.5.2.1 NMI management The NMI can be enabled or disabled using the single NCR register laid out to contain all configuration bits for an NMI in a single byte (see Figure 12-3). The pad defined as an NMI can be configured by the user to recognize interrupts with an active rising edge, an active falling edge or both edges being active. A setting of having both edge events disabled results in no interrupt being detected and should not be configured. The active NMI edge is controlled by the user through the configuration of the NREE0 and NFEE0 bits. NOTE After reset, NREE0 and NFEE0 are set to ‘0’, therefore the NMI functionality is disabled after reset and must be enabled explicitly by software. Once the pad’s NMI functionality has been enabled, the pad cannot be reconfigured in the IOMUX to override or disable the NMI. The NMI destination interrupt is controlled by the user through the configuration of the NDSS0 field. See Table 12-4 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 239 An NMI supports a status flag and an overrun flag which are located in the NSR register (see Figure 12-2). The NIF0 and NOVF0 fields in this register are cleared by writing a ‘1’ to them; this prevents inadvertent overwriting of other flags in the register. The status flag is set whenever an NMI event is detected. The overrun flag is set whenever an NMI event is detected and the status flag is set (that is, has not yet been cleared). NOTE The overrun flag is cleared by writing a ‘1’ to the appropriate overrun bit in the NSR register. If the status bit is cleared and the overrun bit is still set, the pending interrupt will not be cleared. 12.5.3 External wakeups/interrupts The Wakeup Unit supports up to 18 external wakeup/interrupts which can be allocated to any pad necessary at the SoC level. This allocation is fixed per SoC. The Wakeup Unit supports up to three interrupt vectors to the interrupt controller of the SoC. Each interrupt vector can support up to the number of external interrupt sources from the device pads with the total across all vectors being equal to the number of external interrupt sources. Each external interrupt source is assigned to exactly one interrupt vector. The interrupt vector assignment is sequential so that one interrupt vector is for external interrupt sources 0 through N-1, the next is for N through N+M-1, and so forth. See Figure 12-12 for an overview of the external interrupt implementation for the example of three interrupt vectors with up to eight external interrupt sources each. Interrupt Vectors Interrupt Controller Mode / Pwr Ctl IRER[19:0] IRQ_19_16 IRQ_15_08 IRQ_07_00 OR OR Interrupt enable Wakeup enable WRER[19:0] OR Glitch Filter enable WIFER[19:0] Flag[19:16] Flag[15:8] Flag[7:0] Edge Detection Analog Glitch Filter Pads RTC API Figure 12-12. External interrupt pad diagram WISR[19:0] Rising WIREER[19:0] Falling WIFEER[19:0] Interrupt Edge Enable MPC5604B/C Microcontroller Reference Manual, Rev. 8 240 Freescale Semiconductor All of the external interrupt pads within a single group have equal priority. It is the responsibility of the user software to search through the group of sources in the most appropriate way for their application. NOTE Glitch filter control and pad configuration should be done while the external interrupt line is disabled in order to avoid erroneous triggering by glitches caused by the configuration process itself. 12.5.3.1 External interrupt management Each external interrupt can be enabled or disabled independently. This can be performed using a single rolled up register (Figure 12-5). A pad defined as an external interrupt can be configured by the user to recognize external interrupts with an active rising edge, an active falling edge or both edges being active. NOTE Writing a ‘0’ to both IREE[x] and IFEE[x] disables the external interrupt functionality for that pad completely (that is, no system wakeup or interrupt will be generated on any activity on that pad)! The active IRQ edge is controlled by the users through the configuration of the registers WIREER and WIFEER. Each external interrupt supports an individual flag which is held in the flag register (WISR). The bits in the WISR[EIF] field are cleared by writing a ‘1’ to them; this prevents inadvertent overwriting of other flags in the register. 12.5.4 On-chip wakeups The Wakeup Unit supports two on-chip wakeup sources. It combines the on-chip wakeups with the external ones to generate a single wakeup to the system. 12.5.4.1 On-chip wakeup management In order to allow software to determine the wakeup source at one location, on-chip wakeups are reported along with external wakeups in the WISR register (see Figure 12-4 for details). Enabling and clearing of these wakeups are done via the on-chip wakeup source’s own registers. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 241 MPC5604B/C Microcontroller Reference Manual, Rev. 8 242 Freescale Semiconductor Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API) 13.1 Overview The RTC/API is a free running counter used for time keeping applications. The RTC may be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low power mode). If in a low power mode when the RTC interval is reached, the RTC first generates a wakeup and then assert the interrupt request. The RTC also supports an autonomous periodic interrupt (API) function used to generate a periodic wakeup request to exit a low power mode or an interrupt request. 13.2 Features Features of the RTC/API include: • 3 selectable counter clock sources — SIRC (128 kHz) — SXOSC (32 KHz) — FIRC (16 MHz) • Optional 512 prescaler and optional 32 prescaler • 32-bit counter — Supports times up to 1.5 months with 1 ms resolution — Runs in all modes of operation — Reset when disabled by software and by POR • 12-bit compare value to support interrupt intervals of 1 s up to greater than 1 hr with 1 s resolution • RTC compare value changeable while counter is running • RTC status and control register are reset only by POR • Autonomous periodic interrupt (API) — 10-bit compare value to support wakeup intervals of 1.0 ms to 1 s — Compare value changeable while counter is running • Configurable interrupt for RTC match, API match, and RTC rollover • Configurable wakeup event for RTC match, API match, and RTC rollover MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 243 Reserved FIRC SIRC SXOSC CLKSEL[0:1] 0 123 div512en div32en CNTEN div512 div32 RTCCNT sync 22:31 APIVAL + APIEN reset 22:31 offset reg load == sync 32-bit counter reset 10:21 == RTCVAL APIF APIIE sync sync RTCF RTCIE ROVRF RTCIE ROVREN Figure 13-1. RTC/API block diagram API wakeup API interrupt RTC wakeup RTC interrupt MPC5604B/C Microcontroller Reference Manual, Rev. 8 244 Freescale Semiconductor (cnten & clksel== 2’b11) Reserved en C.G. CELL (cnten & clksel== 2’b10) FIRC en C.G. CELL (cnten & clksel== 2’b01) SIRC en C.G. CELL (cnten & clksel== 2’b00) SXOSC en C.G. CELL 0 1 2 3 0 C.G. div 512 1 CELL en 0 C.G. div 32 1 CELL en div512en div32en CNTEN 32-bit counter CLKSEL[0:1] Figure 13-2. Clock gating for RTC clocks 13.3 Device-specific information For MPC5604B, the device specific information is the following: • SXOSC, FIRC and SIRC clocks are provided as counter clocks for the RTC. Default clock on reset is SIRC divided by 4. • The RTC will be reset on destructive reset, with the exception of software watchdog reset. • The RTC provides a configurable divider by 512 to be optionally used when FIRC source is selected. 13.4 Modes of operation 13.4.1 Functional mode There are two functional modes of operation for the RTC: normal operation and low power mode. In normal operation, all RTC registers can read or written and the input isolation is disabled. The RTC/API MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 245 and associated interrupts are optionally enabled. In low power mode, the bus interface is disabled and the input isolation is enabled. The RTC/API is enabled if enabled prior to entry into low power mode. 13.4.2 Debug mode On entering into the debug mode the RTC counter freezes on the last valid count if the RTCC[FRZEN] is set. On exit from debug mode counter continues from the frozen value. 13.5 Register descriptions Table 13-1 lists the RTC/API registers. Table 13-1. RTC/API register map Base address: 0xC3FE_C000 Address offset Register 0x0 RTC Supervisor Control Register (RTCSUPV) 0x4 RTC Control Register (RTCC) 0x8 RTC Status Register (RTCS) 0xC RTC Counter Register (RTCCNT) Location on page 246 on page 247 on page 249 on page 250 13.5.1 RTC Supervisor Control Register (RTCSUPV) The RTCSUPV register contains the SUPV bit which determines whether other registers are accessible in supervisor mode or user mode. NOTE RTCSUPV register is accessible only in supervisor mode. Offset: 0x0 Access: Read/write SUPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13-3. RTC Supervisor Control Register (RTCSUPV) Table 13-2. RTCSUPV field descriptions Field SUPV Description RTC Supervisor Bit 0 All registers are accessible in both user as well as supervisor mode. 1 All other registers are accessible in supervisor mode only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 246 Freescale Semiconductor 13.5.2 RTC Control Register (RTCC) The RTCC register contains: • RTC counter enable • RTC interrupt enable • RTC clock source select • RTC compare value • API enable • API interrupt enable • API compare value Offset: 0x4 0 1 2 3 4 5 6 7 R W CNTEN RTCIE FRZEN ROVREN Reset 0 0 0 0 0 0 0 0 Access: User read/write 8 9 10 11 12 13 14 15 RTCVAL 00000000 APIEN APIIE DIV512EN DIV32EN 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W CLKSEL APIVAL Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13-4. RTC Control Register (RTCC) Table 13-3. RTCC field descriptions Field CNTEN RTCIE FRZEN Description Counter Enable The CNTEN field enables the RTC counter. Making CNTEN bit 1’b0 has the effect of asynchronously resetting (synchronous reset negation) all the RTC and API logic. This allows for the RTC configuration and clock source selection to be updated without causing synchronization issues. 1 Counter enabled 0 Counter disabled RTC Interrupt Enable The RTCIE field enables interrupts requests to the system if RTCF is asserted. 1 RTC interrupts enabled 0 RTC interrupts disabled Freeze Enable The counter freezes on entering the debug mode on the last valid count value if the FRZEN bit is set. After coming out of the debug mode, the counter starts from the frozen value. 0 Counter does not freeze in debug mode. 1 Counter freezes in debug mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 247 Table 13-3. RTCC field descriptions (continued) Field Description ROVREN RTCVAL APIEN APIIE CLKSEL DIV512EN DIV32EN APIVAL Counter Roll Over Wakeup/Interrupt Enable The ROVREN bit enables wakeup and interrupt requests when the RTC has rolled over from 0xFFFF_FFFF to 0x0000_0000. The RTCIE bit must also be set in order to generate an interrupt from a counter rollover. 1 RTC rollover wakeup/interrupt enabled 0 RTC rollover wakeup/interrupt disabled RTC Compare Value The RTCVAL bits are compared to bits 10:21 of the RTC counter and if match sets RTCF. RTCVAL can be updated when the counter is running. Note: RTCVAL = 0 does not generate an interrupt. Autonomous Periodic Interrupt Enable The APIEN bit enables the autonomous periodic interrupt function. 1 API enabled 0 API disabled API Interrupt Enable The APIIE bit enables interrupts requests to the system if APIF is asserted. 1 API interrupts enabled 0 API interrupts disabled Clock Select This field selects the clock source for the RTC. CLKSEL may only be updated when CNTEN is 0. The user should ensure that oscillator is enabled before selecting it as a clock source for RTC. 00 SXOSC 01 SIRC 10 FIRC 11 Reserved Divide by 512 enable The DIV512EN bit enables the 512 clock divider. DIV512EN may only be updated when CNTEN is 0. 0 Divide by 512 is disabled. 1 Divide by 512 is enabled. Divide by 32 enable The DIV32EN bit enables the 32 clock divider. DIV32EN may only be updated when CNTEN is 0. 0 Divide by 32 is disabled. 1 Divide by 32 is enabled. API Compare Value The APIVAL field is compared with bits 22:31 of the RTC counter and if match asserts an interrupt/wakeup request. APIVAL may only be updated when APIEN is 0 or API function is undefined. Note: API functionality starts only when APIVAL is non zero. The first API interrupt takes two more cycles because of synchronization of APIVAL to the RTC clock. After that interrupts are periodic in nature. The minimum supported value of APIVAL is 4. MPC5604B/C Microcontroller Reference Manual, Rev. 8 248 Freescale Semiconductor 13.5.3 RTC Status Register (RTCS) The RTCS register contains: • RTC interrupt flag • API interrupt flag • ROLLOVR Flag Offset: 0x8 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0000000000000 RTCF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 00 0000000000 ROVRF APIF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13-5. RTC Status Register (RTCS) Table 13-4. RTCS field descriptions Field RTCF APIF ROVRF Description RTC Interrupt Flag The RTCF bit indicates that the RTC counter has reached the counter value matching RTCVAL. RTCF is cleared by writing a 1 to RTCF. Writing a 0 to RTCF has no effect. 1 RTC counter matches RTCVAL 0 RTC counter is not equal to RTCVAL API Interrupt Flag The APIF bit indicates that the RTC counter has reached the counter value matching API offset value. APIF is cleared by writing a 1 to APIF. Writing a 0 to APIF has no effect. 1 API interrupt 0 No API interrupt Note: The periodic interrupt comes after APIVAL[0:9] + 1’b1 RTC counts Counter Roll Over Interrupt Flag The ROVRF bit indicates that the RTC has rolled over from 0xffff_ffff to 0x0000_0000. ROVRF is cleared by writing a 1 to ROVRF. 1 RTC has rolled over 0 RTC has not rolled over MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 249 13.5.4 RTC Counter Register (RTCCNT) The RTCCNT register contains the current value of the RTC counter. Offset: 0xC Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RTCCNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13-6. RTC Counter Register (RTCCNT) Table 13-5. RTCCNTfield descriptions Field RTCCNT Description RTC Counter Value Due to the clock synchronization, the RTCCNT value may actually represent a previous counter value. 13.6 RTC functional description The RTC consists of a 32-bit free running counter enabled with the RTCC[CNTEN] bit (CNTEN when negated asynchronously resets the counter and synchronously enables the counter when enabled). The value of the counter may be read via the RTCCNT register. Note that due to the clock synchronization, the RTCCNT value may actually represent a previous counter value. The difference between the counter and the read value depends on ratio of counter clock and system clock. Maximum possible difference between the two is 6 count values. The clock source to the counter is selected with the RTCC[CLKSEL] field, which gives the options for clocking the RTC/API. The output of the clock mux can be optionally divided by combination of 512 and 32 to give a 1 ms RTC/API count period for different clock sources. Note that the RTCC[CNTEN] bit must be disabled when the RTC/API clock source is switched. When the counter value for counter bits 10:21 match the 12-bit value in the RTCC[RTCVAL] field, then the RTCS[RTCF] interrupt flag bit is set (after proper clock synchronization). If the RTCC[RTCIE] interrupt enable bit is set, then the RTC interrupt request is generated. The RTC supports interrupt requests in the range of 1 s to 4096 s (> 1 hr) with a 1 s resolution. If there is a match while in low power mode then the RTC will first generate a wakeup request to force a wakeup to run mode, then the RTCF flag will be set. A rollover wakeup and/or interrupt can be generated when the RTC transitions from a count of 0xFFFF_FFFF to 0x0000_0000. The rollover flag is enabled by setting the RTCC[ROVREN] bit. An RTC counter rollover with this bit will cause a wakeup from low power mode. An interrupt request is generated for an RTC counter rollover when both the RTCC[ROVREN] and RTCC[RTCIE] bits are set. All the flags and counter values are synchronized with the system clock. It is assumed that the system clock frequency is always more than or equal to the rtc_clk used to run the counter. MPC5604B/C Microcontroller Reference Manual, Rev. 8 250 Freescale Semiconductor 13.7 API functional description Setting the RTCC[APIEN] bit enables the autonomous interrupt function. The 10-bit RTCC[APIVAL] field selects the time interval for triggering an interrupt and/or wakeup event. Since the RTC is a free running counter, the APIVAL is added to the current count to calculate an offset. When the counter reaches the offset count, a interrupt and/or wakeup request is generated. Then the offset value is recalculated and again re-triggers a new request when the new value is reached. APIVAL may only be updated when APIEN is disabled. When a compare is reached, the RTCS[APIF] interrupt flag bit is set (after proper clock synchronization). If the RTCC[APIIE] interrupt enable bit is set, then the API interrupt request is generated. If there is a match while in low power mode, then the API will first generate a wakeup request to force a wakeup into normal operation, then the APIF flag will be set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 251 MPC5604B/C Microcontroller Reference Manual, Rev. 8 252 Freescale Semiconductor Chapter 14 CAN Sampler 14.1 Introduction The CAN sampler peripheral has been designed to store the first identifier of CAN message “detected” on the CAN bus while no precise clock (crystal) is running at that time on the device, typically in low power modes (STOP, HALT or STANDBY) or in RUN mode with crystal switched off. Depending on both CAN baud rate and low power mode used, it is possible to catch either the first or the second CAN frame by sampling one CAN Rx port among six and storing all samples in internal registers. After selection of the mode (first or second frame), the CAN sampler stores samples of the 48 bits or skips the first frame and stores samples of the 48 bits of second frame using the 16 MHz fast internal RC oscillator and the 5-bit clock prescaler. After completion, software has to process the sampled data in order to rebuild the 48 minimal bits. Base Identifier (11-bit) Extended Identifier (18-bit) IDE-bit RTR-bit r1 Data Length Code SPR SOF r0 Figure 14-1. Extended CAN data frame 14.2 Main features • Store 384 samples, equivalent to 48 CAN bit @ 8 samples/bit • Sample frequency from 500 kHz up to 16 MHz, equivalent at 8 samples/bit to CAN baud rates of 62.5 Kbps to 2 Mbps • User selectable CAN Rx sample port [CAN0RX-CAN5RX] • 16 MHz fast internal RC oscillator clock • 5-bit clock prescaler • Configurable trigger mode (immediate, next frame) • Flexible samples processing by software • Very low power consumption MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 253 14.3 Register description The CAN sampler registers are listed in Table 14-1. Table 14-1. CAN sampler memory map Base address: 0xFFE7_0000 Address offset 0x00 0x04–0x30 Register Control Register (CR) Sample registers 0–11 Location on page 254 on page 255 14.3.1 Control Register (CR) Offset: 0x00 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RX_COMPLETE BUSY ACTIVE_CK MODE CAN_SMPLR_EN R 000 CAN_RX_SEL BRP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14-2. Control Register (CR) Table 14-2. CR field descriptions Field Description RX_COMPLETE 1: CAN frame is stored in the sample registers 0: CAN frame has not been stored in the sample registers BUSY This bit indicates the sampling status 1: Sampling is ongoing 0: Sampling is complete or has not started ACTIVE_CK This bit indicates which is current clock for sample registers, that is, xmem_ck. 1: RC_CLK is currently xmem_ck 0: ipg_clk_s is currently xmem_ck MODE 0: Skip the first frame and sample and store the second frame (SF_MODE) 1: Sample and store the first frame (FF_MODE) MPC5604B/C Microcontroller Reference Manual, Rev. 8 254 Freescale Semiconductor Table 14-2. CR field descriptions (continued) Field Description CAN_RX_SEL This field determines which RX port is sampled. One Rx port can be selected per sampling routine. 000: CAN0RX PB[1] is selected 001: CAN1RX PC[11] is selected 010: CAN2RX PE[9] is selected 011: CAN3RX PE[9] is selected 100: CAN4RX PC[11] is selected 101: CAN5RX PE[0] is selected 110: Reserved 111: Reserved BRP Baud Rate Prescaler This field is used to set the baud rate before going into STANDBY mode. 00000: Prescaler has 1 11111: Prescaler has 32 CAN_SMPLR_EN CAN Sampler Enable This bit enables the CAN sampler before going into STANDBY or STOP mode. 0: CAN sampler is disabled 1: CAN sampler is enabled 14.3.2 Sample register n (n = 0..11) Offsets: 0x04–0x30 (12 registers) Access: Read/write 0 R W Reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SR[31:16] The reset values are unknown. They will be filled only after the first CAN sampling. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SR[15:0] W Reset The reset values are unknown. They will be filled only after the first CAN sampling. Figure 14-3. Sample register n MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 255 14.4 Functional description As the CAN sampler is driven by the 16 MHz fast internal RC oscillator (or “FIRC”) to properly sample the CAN identifier, two modes are possible depending on both the CAN baud rate and low power mode used: • Immediate sampling on falling edge detection (first CAN frame): This mode is used when the FIRC is available in LP mode (for example, STOP or HALT). • Sampling on next frame (second CAN frame): This mode is used when the FIRC is switched off in LP mode (for example, STANDBY). Due to the start-up times of both the voltage regulator and the FIRC (~10 µs), the CAN sampler would miss the first bits of a CAN identifier sent at 500 kbps. Therefore, the first identifier is ignored and the sampling is performed on the first falling edge of after interframe space. The CAN sampler is in power domain 0 and maintains register settings throughout low power modes. The CAN sampler performs sampling on a user-selected CAN Rx port among six Rx ports available, normally when the device is in STANDBY or STOP mode, storing the samples in internal registers. The user is required to configure the baud rate to achieve eight samples per CAN nominal bit. It does not perform any sort of filtering on input samples. Thereafter the software must enable the sampler by setting the CAN_SMPLR_EN bit in the CR register. It then becomes the master controller for accessing the internal registers implemented for storing samples. The CAN sampler, when enabled, waits for a low pulse on the selected Rx line, taking it as a valid bit of the first CAN frame and generates the RC wakeup request which can be used to start the FIRC. Depending upon the mode, it stores the first 8 samples of the 48 bits on selected Rx line or skips the first frame and stores 8 bits for first 48 bits of second frame. In FF_MODE, it samples the CAN Rx line on the FIRC clock and stores the 8 samples of first 48 bits (384 samples). In SF_MODE, it samples the Rx and waits for 11 consecutive dominant bits ( 11 * 8 samples), taking it as the end of first frame. It then waits for first low pulse on the Rx, taking it as a valid Start of Frame (SOF) of the second frame. The sampler takes 384 samples (48 bytes * 8) using the FIRC clock (configuring 8 samples per nominal bit) of the second frame, including the SOF bit. These samples are stored in consecutive addresses of the (12 x 32) internal registers. The RX_COMPLETE bit is set to ‘1’, indicating that sampling is complete. Software should now process the sampled data by first becoming master for accessing samples internal registers by resetting the CAN_SMPLR_EN bit. The sampler will need to be enabled again to start waiting for a new sampling routine. 14.4.1 Enabling/Disabling the CAN sampler The CAN sampler is disabled on reset and the CPU is able to access the 12 registers used for storing samples. The CAN sampler must be enabled before going into STANDBY or STOP mode by setting the CAN_SMPLR_EN bit in the Control Register (CR) by writing ‘1’ to this bit. In case of any activity on the selected Rx line, the sampler enables the 16 MHz fast internal RC oscillator. When bit CAN_SMPLR_EN is reset to 0, the sampler should receive at last three FIRC clock pulses to reset itself, after which the FIRC can be switched off. MPC5604B/C Microcontroller Reference Manual, Rev. 8 256 Freescale Semiconductor When the software attempts to access the sample registers’ contents it must first reset the CAN_SMPLR_EN bit by writing a ‘0’. Before accessing the register contents it must monitor Active_CK bit for ‘0’. When this bit is reset it can safely access the (12 x 32) sample registers. While shifting from normal to sample mode and from sample to normal mode, the sample register signals must be static and inactive to ensure the data is not corrupt. 14.4.2 Baud rate generation Sampling is performed at a baud rate that is set by the software as a multiple of RC oscillator frequency of 62.5 ns (assuming RC is configured for high frequency mode, that is, 16 MHz). The user must set the baud rate prescaler (BRP) such that eight samples per bit are achieved. The baud rate setting must be made by software before going into STANDBY or STOP mode. This is done by setting bits BRP[4:0] in the Control register. The reset value of BRP is 00000 and can be set to max. 11111 which gives a prescale value of BRP + 1, thus providing a BRP range of 1 to 32. • Maximum bitrate supported for sampling is 2 Mbps using BRP as 1 • Minimum bitrate supported for sampling is 62.5 kbps using BRP as 32 For example, suppose the system is transmitting at 125 kbps. In this case, nominal bit period: T=1/(125*103)s =8*10-3*10-3s = 8µs Eqn. 14-1 To achieve 8 samples per bit Sample period= 8/8 µs = 1 µs BRP = 1 µs/62.5 ns = 16. Thus in this case BRP = 01111 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 257 MPC5604B/C Microcontroller Reference Manual, Rev. 8 258 Freescale Semiconductor ——— Core platform modules ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 259 MPC5604B/C Microcontroller Reference Manual, Rev. 8 260 Freescale Semiconductor Chapter 15 e200z0h Core 15.1 Overview The e200 processor family is a set of CPU cores that implement cost-efficient versions of the Power Architecture®. e200 processors are designed for deeply embedded control applications which require low cost solutions rather than maximum performance. The e200z0h processors integrate an integer execution unit, branch control unit, instruction fetch and load/store units, and a multi-ported register file capable of sustaining three read and two write operations per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching is performed by the branch unit to allow single-cycle branches in some cases. The e200z0h core is a single-issue, 32-bit Power Architecture technology VLE-only design with 32-bit general purpose registers (GPRs). All arithmetic instructions that execute in the core operate on data in the general purpose registers (GPRs). Instead of the base Power Architecture technology support, the e200z0h core only implements the VLE (variable-length encoding) APU, providing improved code density. 15.2 Microarchitecture summary The e200z0h processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), an 8x32 Hardware Multiplier array, result feed-forward hardware, and a hardware divider. Arithmetic and logical operations are executed in a single cycle with the exception of the divide and multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching from the BTB is performed to accelerate certain taken branches in the e200z0h. Prefetched instructions are placed into an instruction buffer with 4entries in e200z0h, each capable of holding a single 32-bit instruction or a pair of 16-bit instructions. Conditional branches which are not taken execute in a single clock. Branches with successful target prefetching have an effective execution time of one clock on e200z0h. All other taken branches have an execution time of two clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 261 instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases. The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture platform. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. MPC5604B/C Microcontroller Reference Manual, Rev. 8 262 Freescale Semiconductor 15.3 Block diagram OnCE/NEXUS CONTROL LOGIC CPU CONTROL LOGIC INSTRUCTION BUS INTERFACE UNIT DATA ADDRESS 32 LR SPR CR CTR XER GPR INSTRUCTION UNIT INSTRUCTION BUFFER PC BRANCH UNIT UNIT LOAD/ STORE UNIT INTEGER EXECUTION UNIT MULTIPLY UNIT CONTROL EXTERNAL SPR INTERFACE (MTSPR/MFSPR) DATA 32 CONTROL N DATA BUS INTERFACE UNIT 32 32 N ADDRESS DATA CONTROL Figure 15-1. e200z0h block diagram 15.4 Features The following is a list of some of the key features of the e200z0h core: • 32-bit Power Architecture VLE-only programmer’s model • Single issue, 32-bit CPU • Implements the VLE APU for reduced code footprint MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 263 • In-order execution and retirement • Precise exception handling • Branch processing unit — Dedicated branch address calculation adder — Branch acceleration using Branch Target Buffer • Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory via independent Instruction and Data bus interface units (BIUs) (e200z0h only). • Load/store unit — 1 cycle load latency — Fully pipelined — Big-endian support only — Misaligned access support — Zero load-to-use pipeline bubbles for aligned transfers • Power management — Low power design — Power saving modes: nap, sleep, and wait — Dynamic power management of execution units • Testability — Synthesizeable, full MuxD scan design — ABIST/MBIST for optional memory arrays 15.4.1 Instruction unit features The features of the e200 Instruction unit are: • 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or up to two 16-bit VLE instructions per clock • Instruction buffer with 4 entries in e200z0h, each holding a single 32-bit instruction, or a pair of 16-bit instructions • Dedicated PC incrementer supporting instruction prefetches • Branch unit with dedicated branch address adder supporting single cycle of execution of certain branches, two cycles for all others 15.4.2 Integer unit features The e200 integer unit supports single cycle execution of most integer instructions: • 32-bit AU for arithmetic and comparison operations • 32-bit LU for logical operations • 32-bit priority encoder for count leading zero’s function MPC5604B/C Microcontroller Reference Manual, Rev. 8 264 Freescale Semiconductor • 32-bit single cycle barrel shifter for shifts and rotates • 32-bit mask unit for data masking and insertion • Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing • 8x32 hardware multiplier array supports 1 to 4 cycle 32x32->32 multiply (early out) 15.4.3 Load/Store unit features The e200 load/store unit supports load, store, and the load multiple / store multiple instructions: • 32-bit effective address adder for data memory address calculations • Pipelined operation supports throughput of one load or store operation per cycle • 32-bit interface to memory (dedicated memory interface on e200z0h) 15.4.4 e200z0h system bus features The features of the e200z0h system bus interface are as follows: • Independent instruction and data buses • AMBA1 AHB2 Lite Rev 2.0 specification with support for ARM v6 AMBA extensions — Exclusive access monitor — Byte lane strobes — Cache allocate support • 32-bit address bus plus attributes and control on each bus • 32-bit read data bus for instruction interface • Separate uni-directional 32-bit read data bus and 32-bit write data bus for data interface • Overlapped, in-order accesses 15.4.5 Nexus 2+ features The Nexus 2+ module is compliant with Class 2 of the IEEE-ISTO 5001-2003 standard, with additional Class 3 and Class 4 features available. The following features are implemented: • Program Trace via Branch Trace Messaging (BTM)—Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced. • Ownership Trace via Ownership Trace Messaging (OTM)—OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An Ownership Trace Message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. • Run-time access to the processor memory map via the JTAG port. This allows for enhanced download/upload capabilities. • Watchpoint Messaging via the auxiliary interface 1. Advanced Microcontroller Bus Architecture 2. Advanced High Performance Bus MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 265 • Watchpoint Trigger enable of Program Trace Messaging • Auxiliary interface for higher data input/output — Configurable (min/max) Message Data Out pins (nex_mdo[n:0]) — One (1) or two (2) Message Start/End Out pins (nex_mseo_b[1:0]) — One (1) Read/Write Ready pin (nex_rdy_b) pin — One (1) Watchpoint Event pin (nex_evto_b) — One (1) Event In pin (nex_evti_b) — One (1) MCKO (Message Clock Out) pin • Registers for Program Trace, Ownership Trace and Watchpoint Trigger control • All features controllable and configurable via the JTAG port 15.5 Core registers and programmer’s model This section describes the registers implemented in the e200z0h cores. It includes an overview of registers defined by the Power Architecture platform, highlighting differences in how these registers are implemented in the e200 core, and provides a detailed description of e200-specific registers. Full descriptions of the architecture-defined register set are provided in the Power Architecture specification. The Power Architecture defines register-to-register operations for all computational instructions. Source data for these instructions are accessed from the on-chip registers or are provided as immediate values embedded in the opcode. The three-register instruction format allows specification of a target register distinct from the two source registers, thus preserving the original data for use by other instructions. Data is transferred between memory and registers with explicit load and store instructions only. Figure 15-2, and Figure 15-1 show the e200 register set including the registers which are accessible while in supervisor mode, and the registers which are accessible in user mode. The number to the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1). NOTE e200z0h is a 32-bit implementation of the Power Architecture specification. In this document, register bits are sometimes numbered from bit 0 (Most Significant Bit) to 31 (Least Significant Bit), rather than the Book E numbering scheme of 32:63, thus register bit numbers for some registers in Book E are 32 higher. Where appropriate, the Book E defined bit numbers are shown in parentheses. MPC5604B/C Microcontroller Reference Manual, Rev. 8 266 Freescale Semiconductor SUPERVISOR Mode Program Model SPRs General Registers Condition Register CR Count Register CTR SPR 9 General-Purpose Registers GPR0 GPR1 Link Register LR SPR 8 GPR31 XER XER SPR 1 Processor Control Registers Machine State MSR Processor Version PVR SPR 287 Processor ID PIR SPR 286 Hardware Implementation Dependent1 HID0 SPR 1008 HID1 SPR 1009 System Version1 SVR SPR 1023 Debug Registers2 Debug Control DBCR0 SPR 308 DBCR1 SPR 309 DBCR2 SPR 310 DBCR31 SPR 561 Instruction Address Compare IAC1 SPR 312 IAC2 SPR 313 IAC3 SPR 314 IAC4 SPR 315 Debug Status DBSR SPR 304 Data Address Compare DAC1 SPR 316 DAC2 SPR 317 DVC1 SPR 318 DVC2 SPR 319 SPR General SPRG0 SPRG1 Exception Handling/Control Registers Save and Restore Interrupt Vector Prefix SPR 272 SRR0 SPR 26 IVPR SPR 63 SPR 273 SRR1 SPR 27 CSRR0 SPR 58 CSRR1 DSRR01 DSRR11 SPR 59 SPR 574 SPR 575 Exception Syndrome ESR SPR 62 Machine Check Syndrome Register MCSR SPR 572 Data Exception Address DEAR SPR 61 BTB Register BTB Control1 BUCSR SPR 1013 Memory Management Registers Process ID PID0 SPR 48 Configuration (read only) MMUCFG SPR 1015 Cache Registers Cache Configuration (Read-only) L1CFG0 SPR 515 1 - These e200-specific registers may not be supported by other Power Architecture processors. 2 - Optional registers defined by the Power Architecture technology 3 - Read-only registers Figure 15-2. e200z0 SUPERVISOR Mode Program Model SPRs MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 267 MPC5604B/C Microcontroller Reference Manual, Rev. 8 268 Freescale Semiconductor Chapter 16 Interrupt Controller (INTC) 16.1 Introduction The INTC provides priority-based preemptive scheduling of interrupt service requests (ISRs). This scheduling scheme is suitable for statically scheduled hard real-time systems. The INTC supports 142 interrupt requests. It is targeted to work with a Power Architecture technology processor and automotive powertrain applications where the ISRs nest to multiple levels, but it also can be used with other processors and applications. For high priority interrupt requests in these target applications, the time from the assertion of the peripheral’s interrupt request from the peripheral to when the processor is performing useful work to service the interrupt request needs to be minimized. The INTC supports this goal by providing a unique vector for each interrupt request source. It also provides 16 priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. Since each individual application will have different priorities for each source of interrupt request, the priority of each interrupt request is configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other. Multiple processors can assert interrupt requests to each other through software configurable interrupt requests. These same software configurable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR can assert a software configurable interrupt request to finish the servicing in a lower priority ISR. Therefore these software configurable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS. 16.2 Features • Supports 134 peripheral and 8 software-configurable interrupt request sources • Unique 9-bit vector per interrupt source • Each interrupt source can be programmed to one of 16 priorities • Preemption — Preemptive prioritized interrupt requests to processor — ISR at a higher priority preempts ISRs or tasks at lower priorities — Automatic pushing or popping of preempted priority to or from a LIFO — Ability to modify the ISR or task priority; modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. • Low latency – 3 clocks from receipt of interrupt request from peripheral to interrupt request to processor MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 269 Table 16-1. Interrupt sources available Interrupt sources (142) Software ECSM Software Watchdog (SWT) STM Flash/SRAM ECC (SEC-DED) Real Time Counter (RTC/API) System Integration Unit Lite (SIUL) WKPU MC_ME MC_RGM FXOSC PIT ADC_0 FlexCAN_0 FlexCAN_1 FlexCAN_2 FlexCAN_3 FlexCAN_4 FlexCAN_5 LINFlex_0 LINFlex_1 LINFlex_2 LINFlex_3 DSPI_0 DSPI_1 DSPI_2 I2C_0 Enhanced Modular I/O Subsystem 0 (eMIOS_0) eMIOS_1 Number available 8 1 1 4 2 2 2 3 4 1 1 6 3 8 8 8 8 8 8 3 3 3 3 5 5 5 1 14 14 16.3 Block diagram Figure 16-1 provides a block diagram of the INTC. MPC5604B/C Microcontroller Reference Manual, Rev. 8 270 Freescale Semiconductor Software Set/Clear Interrupt Registers Priority Select Registers Module Configuration Register Peripheral Interrupt Requests Flag Bits 8 n1 Processor 0 Priority LIFO Pushed Priority 4 Popped Priority 4 n1 x 4-bits Priority Arbitrator Highest Priority Interrupt Requests n1 Request Selector 4 Processor 0 Current Priority Register Highest Priority New Priority 4 Current Priority 4 Priority Comparator Lowest Vector Interrupt Request n1 End of Interrupt Register Vector Encoder Vector Table Entry Size 1 Interrupt Vector 9 Processor 0 Interrupt Acknowledge Register Update Interrupt Vector 1 Hardware Vector Enable 1 Interrupt Vector 9 Interrupt Request to Processor 1 Interrupt Acknowledge Push/Update/Acknowledge Pop Memory Mapped Registers Non-Memory Mapped Logic Figure 16-1. INTC block diagram 1 1 Slave Interface 1 for Reads & Writes Peripheral Bus 16.4 Modes of operation 16.4.1 Normal mode In normal mode, the INTC has two handshaking modes with the processor: software vector mode and hardware vector mode. 16.4.1.1 Software vector mode In software vector mode, software, that is the interrupt exception handler, must read a register in the INTC to obtain the vector associated with the interrupt request to the processor. The INTC will use software vector mode for a given processor when its associated HVEN bit in INTC_MCR is negated. The hardware vector enable signal to processor 0 or processor 1 is driven as negated when its associated HVEN bit is negated. The vector is read from INC_IACKR. Reading the INTC_IACKR negates the interrupt request to the associated processor. Even if a higher priority interrupt request arrived while waiting for this interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. The reading also pushes the PRI value in INTC_CPR onto the associated LIFO and updates PRI in the associated INTC_CPR with the new priority. Furthermore, the interrupt vector to the processor is driven as all 0s. The interrupt acknowledge signal from the associated processor is ignored. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 271 16.4.1.2 Hardware vector mode In hardware vector mode, the hardware is the interrupt vector signal from the INTC in conjunction with a processor with the capability use that vector. In hardware vector mode, this hardware causes the first instruction to be executed in handling the interrupt request to the processor to be specific to that vector. Therefore the interrupt exception handler is specific to a peripheral or software configurable interrupt request rather than being common to all of them. The INTC uses hardware vector mode for a given processor when the associated HVEN bit in the INTC_MCR is asserted. The hardware vector enable signal to the associated processor is driven as asserted. When the interrupt request to the associated processor asserts, the interrupt vector signal is updated. The value of that interrupt vector is the unique vector associated with the preempting peripheral or software configurable interrupt request. The vector value matches the value of the INTVEC field in the INTC_IACKR field in the INTC_IACKR, depending on which processor was assigned to handle a given interrupt source. The processor negates the interrupt request to the processor driven by the INTC by asserting the interrupt acknowledge signal for one clock. Even if a higher priority interrupt request arrived while waiting for the interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. The assertion of the interrupt acknowledge signal for a given processor pushes the associated PRI value in the associated INTC_CPR register onto the associated LIFO and updates the associated PRI in the associated INTC_CPR register with the new priority. This pushing of the PRI value onto the associated LIFO and updating PRI in the associated INTC_CPR does not occur when the associated interrupt acknowledge signal asserts and INTC_SSCIR0_3–INTC_SSCIR4_7 is written at a time such that the PRI value in the associated INTC_CPR register would need to be pushed and the previously last pushed PRI value would need to be popped simultaneously. In this case, PRI in the associated INTC_CPR is updated with the new priority, and the associated LIFO is neither pushed or popped. 16.4.1.3 Debug mode The INTC operation in debug mode is identical to its operation in normal mode. 16.4.1.4 Stop mode The INTC supports STOP mode. The INTC can have its clock input disabled at any time by the clock driver on the device. While its clocks are disabled, the INTC registers are not accessible. The INTC requires clocking in order for a peripheral interrupt request to generate an interrupt request to the processor. Since the INTC is not clocked in STOP mode, peripheral interrupt requests can not be used as a wakeup source, unless the device supports that interrupt request as a wakeup source. 16.5 Memory map and register description 16.5.1 Module memory map Table 16-2 shows the INTC memory map. MPC5604B/C Microcontroller Reference Manual, Rev. 8 272 Freescale Semiconductor Table 16-2. INTC memory map Base address: 0xFFF4_8000 Address offset Register Location 0x0000 INTC Module Configuration Register (INTC_MCR) on page 273 0x0004 Reserved 0x0008 INTC Current Priority Register for Processor (INTC_CPR) on page 274 0x000C Reserved 0x0010 INTC Interrupt Acknowledge Register (INTC_IACKR) on page 276 0x0014 Reserved 0x0018 INTC End-of-Interrupt Register (INTC_EOIR) on page 277 0x001C Reserved 0x0020–0x0027 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3–INTC_SSCIR4_7) on page 277 0x0028–0x003C Reserved 0x0040–0x00D0 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR208_210)1 on page 279 1 The PRI fields are “reserved” for peripheral interrupt requests whose vectors are labeled ‘Reserved’ in Figure 16-3. 16.5.2 Register description With exception of the INTC_SSCIn and INTC_PSRn, all registers are 32 bits in width. Any combination of accessing the four bytes of a register with a single access is supported, provided that the access does not cross a register boundary. These supported accesses include types and sizes of eight bits, aligned 16 bits, misaligned 16 bits to the middle two bytes, and aligned 32 bits. Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. In software vector mode, the side effects of a read of INTC_IACKR are the same regardless of the size of the read. In either software or hardware vector mode, the size of a write to either INTC_SSCIR0_3–INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of the write. 16.5.2.1 INTC Module Configuration Register (INTC_MCR) The module configuration register is used to configure options of the INTC. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 273 Offset: 0x0000 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTES HVEN 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-2. INTC Module Configuration Register (INTC_MCR) Table 16-3. INTC_MCR field descriptions Field VTES HVEN Description Vector table entry size. Controls the number of ‘0’s to the right of INTVEC in Section 16.5.2.3, “INTC Interrupt Acknowledge Register (INTC_IACKR). If the contents of INTC_IACKR are used as an address of an entry in a vectortable as in software vector mode, then the number of rightmost ‘0’s will determine the size of each vector table entry. VTES impacts software vector mode operation but also affects INTC_IACKR[INTVEC] position in both hardware vector mode and software vector mode. 0 4 bytes 1 8 bytes Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector mode. Refer to Section 16.4, “Modes of operation, for the details of the handshaking with the processor in each mode. 0 Software vector mode 1 Hardware vector mode 16.5.2.2 INTC Current Priority Register for Processor (INTC_CPR) Offset: 0x0008 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Figure 16-3. INTC Current Priority Register (INTC_CPR) Table 16-4. INTC_CPR field descriptions Field PRI Description Priority PRI is the priority of the currently executing ISR according to the field values defined in Table 16-5. MPC5604B/C Microcontroller Reference Manual, Rev. 8 274 Freescale Semiconductor The INTC_CPR masks any peripheral or software configurable interrupt request set at the same or lower priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the INTC_CPR’s PRI field. The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to Section 16.7.5, “Priority ceiling protocol. NOTE A store to modify the PRI field which closely precedes or follows an access to a shared resource can result in a non-coherent access to that resource. Refer to Section 16.7.5.2, “Ensuring coherency for example code to ensure coherency. Table 16-5. PRI values PRI 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Meaning Priority 15—highest priority Priority 14 Priority 13 Priority 12 Priority 11 Priority 10 Priority 9 Priority 8 Priority 7 Priority 6 Priority 5 Priority 4 Priority 3 Priority 2 Priority 1 Priority 0—lowest priority MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 275 16.5.2.3 INTC Interrupt Acknowledge Register (INTC_IACKR) Offset: 0x0010 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VTBA[20:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R VTBA[4:0] W INTVEC 00 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-4. INTC Interrupt Acknowledge Register (INTC_IACKR) when INTC_MCR[VTES] = 0 Offset: 0x0010 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VTBA[19:4] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R VTBA[3:0] W INTVEC 000 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-5. INTC Interrupt Acknowledge Register (INTC_IACKR) when INTC_MCR[VTES] = 1 Table 16-6. INTC_IACKR field descriptions Field VTBA INTVEC Description Vector Table Base Address Can be the base address of a vector table of addresses of ISRs. Interrupt Vector It is the vector of the peripheral or software configurable interrupt request that caused the interrupt request to the processor. When the interrupt request to the processor asserts, the INTVEC is updated, whether the INTC is in software or hardware vector mode. The interrupt acknowledge register provides a value which can be used to load the address of an ISR from a vector table. The vector table can be composed of addresses of the ISRs specific to their respective interrupt vectors. MPC5604B/C Microcontroller Reference Manual, Rev. 8 276 Freescale Semiconductor In software vector mode, the INTC_IACKR has side effects from reads. Therefore, it must not be speculatively read while in this mode. The side effects are the same regardless of the size of the read. Reading the INTC_IACKR does not have side effects in hardware vector mode. 16.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) Offset: 0x0018 Access: Write only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W See text Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-6. INTC End-of-Interrupt Register (INTC_EOIR) Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When the INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR. An exception to this behavior is described in Section 16.4.1.2, “Hardware vector mode. The values and size of data written to the INTC_EOIR are ignored. The values and sizes written to this register neither update the INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0s to the INTC_EOIR. Reading the INTC_EOIR has no effect on the LIFO. 16.5.2.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3–INTC_SSCIR4_7) Offset: 0x0020 Access: User read/write CLR1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0000000 CLR0 W SET0 SET1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR3 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0000000 CLR2 W SET2 SET3 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-7. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3]) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 277 Offset: 0x0024 Access: User read/write CLR5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0000000 CLR4 W SET4 SET5 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0000000 CLR6 W SET6 SET7 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-8. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7]) Table 16-7. INTC_SSCIR[0:7] field descriptions Field SETx CLRx Description Set Flag Bits Writing a 1 sets the corresponding CLRx bit. Writing a 0 has no effect. Each SETx always will be read as a 0. Clear Flag Bits CLRx is the flag bit. Writing a 1 to CLRx clears it provided that a 1 is not written simultaneously to its corresponding SETx bit. Writing a 0 to CLRx has no effect. 0 Interrupt request not pending within INTC 1 Interrupt request pending within INTC The software set/clear interrupt registers support the setting or clearing of software configurable interrupt request. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. Excepting being set by software, this flag bit behaves the same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC like a peripheral interrupt request. Writing a 1 to SETx will leave SETx unchanged at 0 but sets CLRx. Writing a 0 to SETx has no effect. CLRx is the flag bit. Writing a 1 to CLRx clears it. Writing a 0 to CLRx has no effect. If a 1 is written simultaneously to a pair of SETx and CLRx bits, CLRx will be asserted, regardless of whether CLRx was asserted before the write. MPC5604B/C Microcontroller Reference Manual, Rev. 8 278 Freescale Semiconductor 16.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR208_210) Offset: 0x0040 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 PRI0 0 0 0 0 PRI1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 PRI2 0 0 0 0 PRI3 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-9. INTC Priority Select Register 0–3 (INTC_PSR[0:3]) Offset: 0x0110 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 W PRI208 0000 PRI209 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 W PRI210 00000000 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-10. INTC Priority Select Register 208-210 (INTC_PSR[208:210]) Table 16-8. INTC_PSR0_3–INTC_PSR208_210 field descriptions Field PRI Description Priority Select PRIx selects the priority for interrupt requests. See Section 16.6, “Functional description. Table 16-9. INTC Priority Select Register address offsets INTC_PSRx_x INTC_PSR0_3 INTC_PSR4_7 INTC_PSR8_11 INTC_PSR12_15 Offset address 0x0040 0x0044 0x0048 0x004C INTC_PSRx_x INTC_PSR108_111 INTC_PSR112_115 INTC_PSR116_119 INTC_PSR120_123 Offset address 0x00AC 0x00B0 0x00B4 0x00B8 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 279 Table 16-9. INTC Priority Select Register address offsets (continued) INTC_PSRx_x INTC_PSR16_19 INTC_PSR20_23 INTC_PSR24_27 INTC_PSR28_31 INTC_PSR32_35 INTC_PSR36_39 INTC_PSR40_43 INTC_PSR44_47 INTC_PSR48_51 INTC_PSR52_55 INTC_PSR56_59 INTC_PSR60_63 INTC_PSR64_67 INTC_PSR68_71 INTC_PSR72_75 INTC_PSR76_79 INTC_PSR80_83 INTC_PSR84_87 INTC_PSR88_91 INTC_PSR92_95 INTC_PSR96_99 INTC_PSR100_103 INTC_PSR104_107 Offset address 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 INTC_PSRx_x INTC_PSR124_127 INTC_PSR128_131 INTC_PSR132_135 INTC_PSR136_139 INTC_PSR140_143 INTC_PSR144_147 INTC_PSR148_151 INTC_PSR152_155 INTC_PSR156_159 INTC_PSR160_163 INTC_PSR164_167 INTC_PSR168_171 INTC_PSR172_175 INTC_PSR176_179 INTC_PSR180_183 INTC_PSR184_187 INTC_PSR188_191 INTC_PSR192_195 INTC_PSR196_199 INTC_PSR200_203 INTC_PSR204_207 INTC_PSR208_210 — Offset address 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC 0x00E0 0x00E4 0x00E8 0x00EC 0x00F0 0x00F4 0x00F8 0x00FC 0x0100 0x0104 0x0108 0x010C 0x0110 — 16.6 Functional description The functional description involves the areas of interrupt request sources, priority management, and handshaking with the processor. MPC5604B/C Microcontroller Reference Manual, Rev. 8 280 Freescale Semiconductor NOTE The INTC has no spurious vector support. Therefore, if an asserted peripheral or software settable interrupt request, whose PRIn value in INTC_PSR0–INTC_PSR210 is higher than the PRI value in INTC_CPR, negates before the interrupt request to the processor for that peripheral or software settable interrupt request is acknowledged, the interrupt request to the processor still can assert or will remain asserted for that peripheral or software settable interrupt request. In this case, the interrupt vector will correspond to that peripheral or software settable interrupt request. Also, the PRI value in the INTC_CPR will be updated with the corresponding PRIn value in INTC_PSRn. Furthermore, clearing the peripheral interrupt request’s enable bit in the peripheral or, alternatively, setting its mask bit has the same consequences as clearing its flag bit. Setting its enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC as an interrupt event setting the flag bit. Table 16-10. Interrupt vector table IRQ # Offset Size (bytes) Interrupt Section A (Core Section) — 0x0000 16 Critical Input (INTC software vector mode) / NMI Core — 0x0010 16 Machine check / NMI Core — 0x0020 16 Data Storage Core — 0x0030 16 Instruction Storage Core — 0x0040 16 External Input (INTC software vector mode) Core — 0x0050 16 Alignment Core — 0x0060 16 Program Core — 0x0070 16 Reserved Core — 0x0080 16 System call Core — 0x0090 96 Unused Core — 0x00F0 16 Debug Core — 0x0100 1792 Unused Core Section B (On-Platform Peripherals) 0 0x0800 4 Software configurable flag 0 Software 1 0x0804 4 Software configurable flag 1 Software 2 0x0808 4 Software configurable flag 2 Software 3 0x080C 4 Software configurable flag 3 Software 4 0x0810 4 Software configurable flag 4 Software Module MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 281 Table 16-10. Interrupt vector table (continued) IRQ # Offset Size (bytes) Interrupt 5 0x0814 4 Software configurable flag 5 6 0x0818 4 Software configurable flag 6 7 0x081C 4 Software configurable flag 7 8 0x0820 4 9 0x0824 4 Platform Flash Bank 0 Abort | Platform Flash Bank 0 Stall | Platform Flash Bank 1 Abort | Platform Flash Bank 1 Stall | 10 0x0828 4 11 0x082C 4 12 0x0830 4 13 0x0834 4 14 0x0838 4 15 0x083C 4 16 0x0840 4 17 0x0844 4 18 0x0848 4 19 0x084C 4 20 0x0850 4 21 0x0854 4 22 0x0858 4 23 0x085C 4 24 0x0860 4 25 0x0864 4 26 0x0868 4 27 0x086C 4 28 0x0870 4 Timeout 29 0x0874 4 30 0x0878 4 Match on channel 0 31 0x087C 4 Match on channel 1 32 0x0880 4 Match on channel 2 33 0x0884 4 Match on channel 3 34 0x0888 4 Software Software Software Reserved ECSM Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SWT Reserved STM STM STM STM Reserved Module MPC5604B/C Microcontroller Reference Manual, Rev. 8 282 Freescale Semiconductor Table 16-10. Interrupt vector table (continued) IRQ # Offset Size (bytes) Interrupt Module 35 0x088C 4 ECC_DBD_PlatformFlash | ECC_DBD_PlatformRAM Platform ECC Double Bit Detection 36 0x0890 4 ECC_SBC_PlatformFlash | ECC_SBC_PlatformRAM Platform ECC Single Bit Correction 37 0x0894 4 Reserved Section C 38 0x0898 4 RTC RTC/API 39 0x089C 4 API RTC/API 40 0x08A0 4 Reserved 41 0x08A4 4 SIU External IRQ_0 SIUL 42 0x08A8 4 SIU External IRQ_1 SIUL 43 0x08AC 4 Reserved 44 0x08B0 4 Reserved 45 0x08B4 4 Reserved 46 0x08B8 4 WakeUp_IRQ_0 WKPU 47 0x08BC 4 WakeUp_IRQ_1 WKPU 48 0x08C0 4 WakeUp_IRQ_2 WKPU 49 0x08C4 4 Reserved 50 0x08C8 4 Reserved 51 0x08CC 4 Safe Mode Interrupt MC_ME 52 0x08D0 4 Mode Transition Interrupt MC_ME 53 0x08D4 4 Invalid Mode Interrupt MC_ME 54 0x08D8 4 Invalid Mode Config MC_ME 55 0x08DC 4 Reserved 56 0x08E0 4 Functional and destructive reset alternate MC_RGM event interrupt (ipi_int) 57 0x08E4 4 FXOSC counter expired (ipi_int_osc) FXOSC 58 0x08E8 4 Reserved 59 0x08EC 4 PITimer Channel 0 PIT 60 0x08F0 4 PITimer Channel 1 PIT 61 0x08F4 4 PITimer Channel 2 PIT 62 0x08F8 4 ADC_EOC ADC_0 63 0x08FC 4 ADC_ER ADC_0 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 283 Table 16-10. Interrupt vector table (continued) IRQ # Offset Size (bytes) Interrupt 64 0x0900 4 ADC_WD 65 0x0904 4 FlexCAN_ESR[ERR_INT] 66 0x0908 4 FlexCAN_ESR_BOFF | FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 67 0x090C 4 68 0x0910 4 FlexCAN_BUF_00_03 69 0x0914 4 FlexCAN_BUF_04_07 70 0x0918 4 FlexCAN_BUF_08_11 71 0x091C 4 FlexCAN_BUF_12_15 72 0x0920 4 FlexCAN_BUF_16_31 73 0x0924 4 FlexCAN_BUF_32_63 74 0x0928 4 DSPI_SR[TFUF] DSPI_SR[RFOF] 75 0x092C 4 DSPI_SR[EOQF] 76 0x0930 4 DSPI_SR[TFFF] 77 0x0934 4 DSPI_SR[TCF] 78 0x0938 4 DSPI_SR[RFDF] 79 0x093C 4 LINFlex_RXI 80 0x0940 4 LINFlex_TXI 81 0x0944 4 LINFlex_ERR 82 0x0948 4 83 0x094C 4 84 0x0950 4 85 0x0954 4 FlexCAN_ESR[ERR_INT] 86 0x0958 4 FlexCAN_ESR_BOFF | FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 87 0x095C 4 88 0x0960 4 FlexCAN_BUF_00_03 89 0x0964 4 FlexCAN_BUF_04_07 90 0x0968 4 FlexCAN_BUF_08_11 91 0x096C 4 FlexCAN_BUF_12_15 92 0x0970 4 FlexCAN_BUF_16_31 ADC_0 FlexCAN_0 FlexCAN_0 Module Reserved FlexCAN_0 FlexCAN_0 FlexCAN_0 FlexCAN_0 FlexCAN_0 FlexCAN_0 DSPI_0 DSPI_0 DSPI_0 DSPI_0 DSPI_0 LINFlex_0 LINFlex_0 LINFlex_0 Reserved Reserved Reserved FlexCAN_1 FlexCAN_1 Reserved FlexCAN_1 FlexCAN_1 FlexCAN_1 FlexCAN_1 FlexCAN_1 MPC5604B/C Microcontroller Reference Manual, Rev. 8 284 Freescale Semiconductor Table 16-10. Interrupt vector table (continued) IRQ # Offset Size (bytes) Interrupt 93 0x0974 4 FlexCAN_BUF_32_63 94 0x0978 4 DSPI_SR[TFUF] DSPI_SR[RFOF] 95 0x097C 4 DSPI_SR[EOQF] 96 0x0980 4 DSPI_SR[TFFF] 97 0x0984 4 DSPI_SR[TCF] 98 0x0988 4 DSPI_SR[RFDF] 99 0x098C 4 LINFlex_RXI 100 0x0990 4 LINFlex_TXI 101 0x0994 4 LINFlex_ERR 102 0x0998 4 103 0x099C 4 104 0x09A0 4 105 0x09A4 4 FlexCAN_[ERR_INT] 106 0x09A8 4 FlexCAN_ESR_BOFF | FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 107 0x09AC 4 108 0x09B0 4 FlexCAN_BUF_00_03 109 0x09B4 4 FlexCAN_BUF_04_07 110 0x09B8 4 FlexCAN_BUF_08_11 111 0x09BC 4 FlexCAN_BUF_12_15 112 0x09C0 4 FlexCAN_BUF_16_31 113 0x09C4 4 FlexCAN_BUF_32_63 114 0x09C8 4 DSPI_SR[TFUF] DSPI_SR[RFOF] 115 0x09CC 4 DSPI_SR[EOQF] 116 0x09D0 4 DSPI_SR[TFFF] 117 0x09D4 4 DSPI_SR[TCF] 118 0x09D8 4 DSPI_SR[RFDF] 119 0x09DC 4 LINFlex_RXI 120 0x09E0 4 LINFlex_TXI 121 0x09E4 4 LINFlex_ERR 122 0x09E8 4 LINFlex_RXI FlexCAN_1 DSPI_1 DSPI_1 DSPI_1 DSPI_1 DSPI_1 LINFlex_1 LINFlex_1 LINFlex_1 Reserved Reserved Reserved FlexCAN_2 FlexCAN_2 Module Reserved FlexCAN_2 FlexCAN_2 FlexCAN_2 FlexCAN_2 FlexCAN_2 FlexCAN_2 DSPI_2 DSPI_2 DSPI_2 DSPI_2 DSPI_2 LINFlex_2 LINFlex_2 LINFlex_2 LINFlex_3 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 285 Table 16-10. Interrupt vector table (continued) IRQ # Offset Size (bytes) Interrupt 123 0x09EC 4 LINFlex_TXI 124 0x09F0 4 LINFlex_ERR 125 0x09F4 4 I2C_SR[IBAL] I2C_SR[TCF] I2C_SR[IAAS] 126 0x09F8 4 127 0x09FC 4 PITimer Channel 3 128 0x0A00 4 PITimer Channel 4 129 0x0A04 4 PITimer Channel 5 130 0x0A08 4 131 0x0A0C 4 132 0x0A10 4 133 0x0A14 4 134 0x0A18 4 135 0x0A1C 4 136 0x0A20 4 137 0x0A24 4 138 0x0A28 4 139 0x0A2C 4 140 0x0A30 4 141 0x0A34 4 EMIOS_GFR[F0,F1] 142 0x0A38 4 EMIOS_GFR[F2,F3] 143 0x0A3C 4 EMIOS_GFR[F4,F5] 144 0x0A40 4 EMIOS_GFR[F6,F7] 145 0x0A44 4 EMIOS_GFR[F8,F9] 146 0x0A48 4 EMIOS_GFR[F10,F11] 147 0x0A4C 4 EMIOS_GFR[F12,F13] 148 0x0A50 4 EMIOS_GFR[F14,F15] 149 0x0A54 4 EMIOS_GFR[F16,F17] 150 0x0A58 4 EMIOS_GFR[F18,F19] 151 0x0A5C 4 EMIOS_GFR[F20,F21] 152 0x0A60 4 EMIOS_GFR[F22,F23] 153 0x0A64 4 EMIOS_GFR[F24,F25] LINFlex_3 LINFlex_3 I2C_0 Module Reserved PIT PIT PIT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 eMIOS_0 MPC5604B/C Microcontroller Reference Manual, Rev. 8 286 Freescale Semiconductor Table 16-10. Interrupt vector table (continued) IRQ # Offset Size (bytes) Interrupt 154 0x0A68 4 EMIOS_GFR[F26,F27] eMIOS_0 155 0x0A6C 4 Reserved 156 0x0A70 4 Reserved Section D (Device specific vectors) 157 0x0A74 4 EMIOS_GFR[F0,F1] eMIOS_1 158 0x0A78 4 EMIOS_GFR[F2,F3] eMIOS_1 159 0x0A7C 4 EMIOS_GFR[F4,F5] eMIOS_1 160 0x0A80 4 EMIOS_GFR[F6,F7] eMIOS_1 161 0x0A84 4 EMIOS_GFR[F8,F9] eMIOS_1 162 0x0A88 4 EMIOS_GFR[F10,F11] eMIOS_1 163 0x0A8C 4 EMIOS_GFR[F12,F13] eMIOS_1 164 0x0A90 4 EMIOS_GFR[F14,F15] eMIOS_1 165 0x0A94 4 EMIOS_GFR[F16,F17] eMIOS_1 166 0x0A98 4 EMIOS_GFR[F18,F19] eMIOS_1 167 0x0A9C 4 EMIOS_GFR[F20,F21] eMIOS_1 168 0x0AA0 4 EMIOS_GFR[F22,F23] eMIOS_1 169 0x0AA4 4 EMIOS_GFR[F24,F25] eMIOS_1 170 0x0AA8 4 EMIOS_GFR[F26,F27] eMIOS_1 171 0x0AAC 4 Reserved 172 0x0AB0 4 Reserved 173 0x0AB4 4 FlexCAN_ESR FlexCAN_3 174 0x0AB8 4 FlexCAN_ESR_BOFF | FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning FlexCAN_3 175 0x0ABC 4 Reserved 176 0x0AC0 4 FlexCAN_BUF_0_3 FlexCAN_3 177 0x0AC4 4 FlexCAN_BUF_4_7 FlexCAN_3 178 0x0AC8 4 FlexCAN_BUF_8_11 FlexCAN_3 179 0x0ACC 4 FlexCAN_BUF_12_15 FlexCAN_3 180 0x0AD0 4 FlexCAN_BUF_16_31 FlexCAN_3 181 0x0AD4 4 FlexCAN_BUF_32_63 FlexCAN_3 182 0x0AD8 4 Reserved 183 0x0ADC 4 Reserved Module MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 287 Table 16-10. Interrupt vector table (continued) IRQ # Offset Size (bytes) Interrupt 184 0x0AE0 4 185 0x0AE4 4 186 0x0AE8 4 187 0x0AEC 4 188 0x0AF0 4 189 0x0AF4 4 190 0x0AF8 4 FlexCAN_ESR 191 0x0AFC 4 FlexCAN_ESR_BOFF | FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 192 0x0B00 4 193 0x0B04 4 FlexCAN_BUF_0_3 194 0x0B08 4 FlexCAN_BUF_4_7 195 0x0B0C 4 FlexCAN_BUF_8_11 196 0x0B10 4 FlexCAN_BUF_12_15 197 0x0B14 4 FlexCAN_BUF_16_31 198 0x0B18 4 FlexCAN_BUF_32_63 199 0x0B1C 4 200 0x0B20 4 201 0x0B24 4 202 0x0B28 4 FlexCAN_ESR 203 0x0B2C 4 FlexCAN_ESR_BOFF | FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 204 0x0B30 4 205 0x0B34 4 FlexCAN_BUF_0_3 206 0x0B38 4 FlexCAN_BUF_4_7 207 0x0B3C 4 FlexCAN_BUF_8_11 208 0x0B40 4 FlexCAN_BUF_12_15 209 0x0B44 4 FlexCAN_BUF_16_31 210 0x0B48 4 FlexCAN_BUF_32_63 211 0x0B4C 4 212 0x0B50 4 213 0x0B54 4 Reserved Reserved Reserved Reserved Reserved Reserved FlexCAN_4 FlexCAN_4 Module Reserved FlexCAN_4 FlexCAN_4 FlexCAN_4 FlexCAN_4 FlexCAN_4 FlexCAN_4 Reserved Reserved Reserved FlexCAN_5 FlexCAN_5 Reserved FlexCAN_5 FlexCAN_5 FlexCAN_5 FlexCAN_5 FlexCAN_5 FlexCAN_5 Reserved Reserved Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 288 Freescale Semiconductor IRQ # Offset Size (bytes) 214 0x0B58 4 215 0x0B5C 4 216 0x0B60 4 Table 16-10. Interrupt vector table (continued) Interrupt Reserved Reserved Reserved Module 16.6.1 Interrupt request sources The INTC has two types of interrupt requests, peripheral and software configurable. These interrupt requests can assert on any clock cycle. 16.6.1.1 Peripheral interrupt requests An interrupt event in a peripheral’s hardware sets a flag bit that resides in the peripheral. The interrupt request from the peripheral is driven by that flag bit. The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time that the INTC starts to drive the interrupt request to the processor is three clocks. External interrupts are handled by the SIU (see Section 19.6.3, “External interrupts). 16.6.1.2 Software configurable interrupt requests An interrupt request is triggered by software by writing a 1 to a SETx bit in INTC_SSCIR0_3–INTC_SSCIR4_7. This write sets the corresponding flag bit, CLRx, resulting in the interrupt request. The interrupt request is cleared by writing a 1 to the CLRx bit. The time from the write to the SETx bit to the time that the INTC starts to drive the interrupt request to the processor is four clocks. 16.6.1.3 Unique vector for each interrupt request source Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector. Software configurable interrupts 0–7 are assigned vectors 0–7 respectively. The peripheral interrupt requests are assigned vectors 8 to as high as needed to include all the peripheral interrupt requests. The peripheral interrupt request input ports at the boundary of the INTC block are assigned specific hardwired vectors within the INTC (see Table 16-1). 16.6.2 Priority management The asserted interrupt requests are compared to each other based on their PRIx values set in the INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR208_210). The result is compared to PRI in the associated INTC_CPR. The results of those comparisons manage the priority of the ISR executed by the associated processor. The associated LIFO also assists in managing that priority. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 289 16.6.2.1 Current priority and preemption The priority arbitrator, selector, encoder, and comparator subblocks shown in Figure 16-1 compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted peripheral or software configurable interrupt request is higher than the current priority for a given processor, then the interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral or software configurable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and if in hardware vector mode, for the interrupt vector provided to the processor. 16.6.2.1.1 Priority arbitrator subblock The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt requests assigned to that processor, both peripheral and software configurable. The output of the priority arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt requests which have this highest priority are output as asserted interrupt requests to the associated request selector subblock. 16.6.2.1.2 Request selector subblock If only one interrupt request from the associated priority arbitrator subblock is asserted, then it is passed as asserted to the associated vector encoder subblock. If multiple interrupt requests from the associated priority arbitrator subblock are asserted, the only the one with the lowest vector is passed as asserted to the associated vector encoder subblock. The lower vector is chosen regardless of the time order of the assertions of the peripheral or software configurable interrupt requests. 16.6.2.1.3 Vector encoder subblock The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the request selector subblock for the associated processor. 16.6.2.1.4 Priority Comparator subblock The priority comparator subblock compares the highest priority output from the priority arbitrator subblock with PRI in INTC_CPR. If the priority comparator subblock detects that this highest priority is higher than the current priority, then it asserts the interrupt request to the associated processor. This interrupt request to the processor asserts whether this highest priority is raised above the value of PRI in INTC_CPR or the PRI value in INTC_CPR is lowered below this highest priority. This highest priority then becomes the new priority which will be written to PRI in INTC_CPR when the interrupt request to the processor is acknowledged. Interrupt requests whose PRIn in INTC_PSRn are zero will not cause a preemption because their PRIn will not be higher than PRI in INTC_CPR. 16.6.2.2 Last-In First-Out (LIFO) The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are stacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not need to be loaded from the context stack and stored into the INTC_CPR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 290 Freescale Semiconductor The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in softwarevector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode. The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written. Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 will not be preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only 14 entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities first pushed are overwritten. A priority of 0 would be an overwritten priority. However, the LIFO will pop ‘0’s if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty LIFO. The LIFO is not memory mapped. 16.6.3 Handshaking with processor 16.6.3.1 Software vector mode handshaking This section describes handshaking in software vector mode. 16.6.3.1.1 Acknowledging interrupt request to processor A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in Figure 16-11. The INTC examines the peripheral and software configurable interrupt requests. When it finds an asserted peripheral or software configurable interrupt request with a higher priority than PRI in the associated INTC_CPR, it asserts the interrupt request to the processor. The INTVEC field in the associated INTC_IACKR is updated with the preempting interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the interrupt request to the processor is asserted. The rest of the handshaking is described in Section 16.4.1.1, “Software vector mode. 16.6.3.1.2 End of interrupt exception handler Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be written.When written, the associated LIFO is popped so the preempted priority is restored into PRI of the INTC_CPR. Before it is written, the peripheral or software configurable flag bit must be cleared so that the peripheral or software configurable interrupt request is negated. NOTE To ensure proper operation across all Power Architecture® MCUs, execute an MBAR or MSYNC instruction between the access to clear the flag bit and the write to the INTC_EOIR. When returning from the preemption, the INTC does not search for the peripheral or software settable interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt request may no longer even be asserted. When PRI in INTC_CPR is lowered to the priority of the preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software settable interrupt request at or below that priority will not cause a preemption. Instead, after the restoration MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 291 of the preempted context, the processor will return to the instruction address that it was to next execute before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog. Clock Interrupt request to processor Hardware vector enable Interrupt vector 0 Interrupt acknowledge Read INTC_IACKR Write INTC_EOIR INTVEC in INTC_IACKR 0 108 PRI in INTC_CPR 0 1 0 Peripheral interrupt request 100 Figure 16-11. Software vector mode handshaking timing diagram 16.6.3.2 Hardware vector mode handshaking A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in Figure 16-12. As in software vector mode, the INTC examines the peripheral and software settable interrupt requests, and when it finds an asserted one with a higher priority than PRI in INTC_CPR, it asserts the interrupt request to the processor. The INTVEC field in the INTC_IACKR is updated with the preempting peripheral or software settable interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the interrupt request to the processor is asserted. In addition, the value of the interrupt vector to the processor matches the value of the INTVEC field in the INTC_IACKR. The rest of the handshaking is described in Section 16.7.2.2, “Hardware vector mode. The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. Refer to Section 16.6.3.1.2, “End of interrupt exception handler. MPC5604B/C Microcontroller Reference Manual, Rev. 8 292 Freescale Semiconductor Clock Interrupt request to processor Hardware vector enable Interrupt vector 0 108 Interrupt acknowledge Read INTC_IACKR Write INTC_EOIR INTVEC in INTC_IACKR 0 108 PRI in INTC_CPR 0 Peripheral interrupt request 100 1 0 Figure 16-12. Hardware vector mode handshaking timing diagram 16.7 Initialization/application information 16.7.1 Initialization flow After exiting reset, all of the PRIn fields in INTC priority select registers (INTC_PSR0–INTC_PSR210) will be zero, and PRI in INTC current priority register (INTC_CPR) will be 15. These reset values will prevent the INTC from asserting the interrupt request to the processor. The enable or mask bits in the peripherals are reset such that the peripheral interrupt requests are negated. An initialization sequence for allowing the peripheral and software settable interrupt requests to cause an interrupt request to the processor is:interrupt_request_initialization: interrupt_request_initialization: configure VTES and HVEN in INTC_MCR configure VTBA in INTC_IACKR raise the PRIn fields in INTC_PSRn set the enable bits or clear the mask bits for the peripheral interrupt requests lower PRI in INTC_CPR to zero enable processor recognition of interrupts 16.7.2 Interrupt exception handler These example interrupt exception handlers use Power Architecture™ assembly code. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 293 16.7.2.1 Software vector mode interrupt_exception_handler: code to create stack frame, save working register, and save SRR0 and SRR1 lis r3,INTC_IACKR@ha # form adjusted upper half of INTC_IACKR address lwz r3,INTC_IACKR@l(r3) # load INTC_IACKR, which clears request to processor lwz r3,0x0(r3) # load address of ISR from vector table wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 EABI mtlr r3 blrl # move INTC_IACKR contents into link register # branch to ISR; link register updated with epilog # address epilog: code to restore most of context required by e500 EABI # Popping the LIFO after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address li r4,0x0 # form 0 to write to INTC_EOIR wrteei 0 # disable processor recognition of interrupts stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority code to restore SRR0 and SRR1, restore working registers, and delete stack frame rfi vector_table_base_address: address of ISR for interrupt with vector 0 address of ISR for interrupt with vector 1 . . . address of ISR for interrupt with vector 510 address of ISR for interrupt with vector 511 ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC blr # return to epilog 16.7.2.2 Hardware vector mode This interrupt exception handler is useful with processor and system bus implementations which support a hardware vector. This example assumes that each interrupt_exception_handlerx only has space for four instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed. interrupt_exception_handlerx: b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue MPC5604B/C Microcontroller Reference Manual, Rev. 8 294 Freescale Semiconductor interrupt_exception_handler_continuedx: code to create stack frame, save working register, and save SRR0 and SRR1 wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 EABI bl ISRx # branch to ISR for interrupt with vector x epilog: code to restore most of context required by e500 EABI # Popping the LIFO after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address li r4,0x0 # form 0 to write to INTC_EOIR wrteei 0 # disable processor recognition of interrupts stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority code to restore SRR0 and SRR1, restore working registers, and delete stack frame rfi ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC blr # branch to epilog 16.7.3 ISR, RTOS, and task hierarchy The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register (INTC_CPR) having a value of 0. The RTOS will execute the tasks according to whatever priority scheme that it may have, but that priority scheme is independent and has a lower priority of execution than the priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outside the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0. If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed. An ISR whose PRIn in INTC priority select registers (INTC_PSR0–INTC_PSR210) has a value of 0 will not cause an interrupt request to the processor, even if its peripheral or software settable interrupt request is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bit will cause it to remain negated, which consequently also will not cause an interrupt request to the processor. Since the ISRs are outside the control of the RTOS, this ISR will not run unless called by another ISR or the interrupt exception handler, perhaps after executing another ISR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 295 16.7.4 Order of execution An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors associated with each of their peripheral or software configurable interrupt requests. However, if multiple peripheral or software configurable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the INTC selects the one with the lowest unique vector regardless of the order in time that they asserted. However, the ability to meet deadlines with this scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software configurable interrupt requests asserted. The example in Table 16-11 shows the order of execution of both ISRs with different priorities and the same priority. Table 16-11. Order of ISR execution example Step No. Step description Code Executing at End of Step PRI in RTOS ISR1081 ISR208 ISR308 ISR408 Interrupt exception handler INTC_CPR at End of Step 1 RTOS at priority 0 is executing. X 0 2 Peripheral interrupt request 100 at X 1 priority 1 asserts. Interrupt taken. 3 Peripheral interrupt request 400 at priority 4 is asserts. Interrupt taken. X 4 4 Peripheral interrupt request 300 at priority 3 is asserts. X 4 5 Peripheral interrupt request 200 at priority 3 is asserts. X 4 6 ISR408 completes. Interrupt exception handler writes to INTC_EOIR. X 1 7 Interrupt taken. ISR208 starts to X 3 execute, even though peripheral interrupt request 300 asserted first. 8 ISR208 completes. Interrupt exception handler writes to INTC_EOIR. X 1 9 Interrupt taken. ISR308 starts to execute. X 3 10 ISR308 completes. Interrupt exception handler writes to INTC_EOIR. X 1 11 ISR108 completes. Interrupt exception handler writes to INTC_EOIR. X 0 12 RTOS continues execution. X 0 MPC5604B/C Microcontroller Reference Manual, Rev. 8 296 Freescale Semiconductor 1 ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software configurable interrupt requests. 16.7.5 Priority ceiling protocol 16.7.5.1 Elevating priority The PRI field in INTC_CPR is elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs that share a resource. This protocol allows coherent accesses of the ISRs to that shared resource. For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They share the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in INTC_CPR to 3, the ceiling of all of the ISR priorities. After they release the resource, the PRI value in INTC_CPR can be lowered. If they do not raise their priority, ISR2 can preempt ISR1, and ISR3 can preempt ISR1 or ISR2, possibly corrupting the shared resource. Another possible failure mechanism is deadlock if the higher priority ISR needs the lower priority ISR to release the resource before it can continue, but the lower priority ISR cannot release the resource until the higher priority ISR completes and execution returns to the lower priority ISR. Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked. For example, while ISR3 cannot preempt ISR1 while it is accessing the shared resource, all of the ISRs with a priority higher than 3 can preempt ISR1. 16.7.5.2 Ensuring coherency A scenario can cause non-coherent accesses to the shared resource. For example, ISR1 and ISR2 are both running on the same core and both share a resource. ISR1 has a lower priority than ISR2. ISR1 is executing and writes to the INTC_CPR. The instruction following this store is a store to a value in a shared coherent data block. Either immediately before or at the same time as the first store, the INTC asserts the interrupt request to the processor because the peripheral interrupt request for ISR2 has asserted. As the processor is responding to the interrupt request from the INTC, and as it is aborting transactions and flushing its pipeline, it is possible that both stores will be executed. ISR2 thereby thinks that it can access the data block coherently, but the data block has been corrupted. OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource. To prevent corruption of a coherent data block, modifications to PRI in INTC_CPR can be made by those system services with the code sequence: disable processor recognition of interrupts PRI modification enable processor recognition of interrupts 16.7.6 Selecting priorities according to request rates and deadlines The selection of the priorities for the ISRs can be made using rate monotonic scheduling (RMS) or a superset of it, deadline monotonic scheduling (DMS). In RMS, the ISRs which have higher request rates have higher priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 297 assigned a priority according to the time from the request for the ISR to the deadline, not from the time of the request for the ISR to the next request for it. For example, ISR1 executes every 100 µs, ISR2 executes every 200 µs, and ISR3 executes every 300 µs. ISR1 has a higher priority than ISR2 which has a higher priority than ISR3; however, if ISR3 has a deadline of 150 µs, then it has a higher priority than ISR2. The INTC has 16 priorities, which may be less than the number of ISRs. In this case, the ISRs should be grouped with other ISRs that have similar deadlines. For example, a priority could be allocated for every time the request rate doubles. ISRs with request rates around 1 ms would share a priority, ISRs with request rates around 500 µs would share a priority, ISRs with request rates around 250 µs would share a priority, etc. With this approach, a range of ISR request rates of 216 could be included, regardless of the number of ISRs. Reducing the number of priorities reduces the processor’s ability to meet its deadlines. However, reducing the number of priorities can reduce the size and latency through the interrupt controller. It also allows easier management of ISRs with similar deadlines that share a resource. They do not need to use the PCP to access the shared resource. 16.7.7 Software configurable interrupt requests The software configurable interrupt requests can be used in two ways. They can be used to schedule a lower priority portion of an ISR and they may also be used by processors to interrupt other processors in a multiple processor system. 16.7.7.1 Scheduling a lower priority portion of an ISR A portion of an ISR needs to be executed at the PRIx value in the INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR208_210), which becomes the PRI value in INTC_CPR with the interrupt acknowledge. The ISR, however, can have a portion that does not need to be executed at this higher priority. Therefore, executing the later portion that does not need to be executed at this higher priority can prevent the execution of ISRs which do not have a higher priority than the earlier portion of the ISR but do have a higher priority than what the later portion of the ISR needs. This preemptive scheduling inefficiency reduces the processor’s ability to meet its deadlines. One option is for the ISR to complete the earlier higher priority portion, but then schedule through the RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher priority portion, to set a SETx bit in INTC_SSCIR0_3–INTC_SSCIR4_7. Writing a 1 to SETx causes a software configurable interrupt request. This software configurable interrupt request will usually have a lower PRIx value in the INTC_PSRx_x and will not cause preemptive scheduling inefficiencies. After generating a software settable interrupt request, the higher priority ISR completes. The lower priority ISR is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the completion of the lower priority ISR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 298 Freescale Semiconductor 16.7.7.2 Scheduling an ISR on another processor Because the SETx bits in the INTC_SSCIRx_x are memory mapped, processors in multiple-processor systems can schedule ISRs on the other processors. One application is that one processor wants to command another processor to perform a piece of work and the initiating processor does not need to use the results of that work. If the initiating processor is concerned that the processor executing the software configurable ISR has not completed the work before asking it to again execute the ISR, it can check if the corresponding CLRx bit in INTC_SSCIRx_x is asserted before again writing a 1 to the SETx bit. Another application is the sharing of a block of data. For example, a first processor has completed accessing a block of data and wants a second processor to then access it. Furthermore, after the second processor has completed accessing the block of data, the first processor again wants to access it. The accesses to the block of data must be done coherently. To do this, the first processor writes a 1 to a SETx bit on the second processor. After accessing the block of data, the second processor clears the corresponding CLRx bit and then writes 1 to a SETx bit on the first processor, informing it that it can now access the block of data. 16.7.8 Lowering priority within an ISR A common method for avoiding preemptive scheduling inefficiencies with an ISR whose work spans multiple priorities (see Section 16.7.7.1, “Scheduling a lower priority portion of an ISR) is to lower the current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities. NOTE Lowering the PRI value in INTC_CPR within an ISR to below the ISR’s corresponding PRI value in the INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR208_210) allows more preemptions than the LIFO depth can support. Therefore, the INTC does not support lowering the current priority within an ISR as a way to avoid preemptive scheduling inefficiencies. 16.7.9 Negating an interrupt request outside of its ISR 16.7.9.1 Negating an interrupt request as a side effect of an ISR Some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt request. For example, reading a specific register can clear the flag bits and their corresponding interrupt requests. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request whose ISR presently is executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect. 16.7.9.2 Negating multiple interrupt requests in one ISR An ISR can clear other flag bits besides its own. One reason that an ISR clears multiple flag bits is because it serviced those flag bits, and therefore the ISRs for these flag bits do not need to be executed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 299 16.7.9.3 Proper setting of interrupt request priority Whether an interrupt request negates outside its own ISR due to the side effect of an ISR execution or the intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for these other flag bits must be selected properly. Their PRIx values in the INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR208_210) must be selected to be at or lower than the priority of the ISR that cleared their flag bits. Otherwise, those flag bits can cause the interrupt request to the processor to assert. Furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to INTC_SSCIR0_3–INTC_SSCIR4_7 as the clearing of the flag bit that caused the present ISR to be executed (see Section 16.6.3.1.2, “End of interrupt exception handler). A flag bit whose enable bit or mask bit negates its peripheral interrupt request can be cleared at any time, regardless of the peripheral interrupt request’s PRIx value in INTC_PSRx_x. 16.7.10 Examining LIFO contents In normal mode, the user does not need to know the contents of the LIFO. He may not even know how deeply the LIFO is nested. However, if he wants to read the contents, such as in debug mode, they are not memory mapped. The contents can be read by popping the LIFO and reading the PRI field in either INTC_CPR. The code sequence is: pop_lifo: store to INTC_EOIR load INTC_CPR, examine PRI, and store onto stack if PRI is not zero or value when interrupts were enabled, branch to pop_lifo When the examination is complete, the LIFO can be restored using this code sequence: push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo MPC5604B/C Microcontroller Reference Manual, Rev. 8 300 Freescale Semiconductor Chapter 17 Crossbar Switch (XBAR) 17.1 Introduction This chapter describes the multi-port crossbar switch (XBAR), which supports simultaneous connections between two master ports and three slave ports. XBAR supports a 32-bit address bus width and a 32-bit data bus width at all master and slave ports. The crossbar of MPC5604B is the same as the one of all other PPC55xx and PPC56xx products except that it cannot be configured by software and that it has a hard-wired configuration. 17.2 Block diagram Figure 17-1 shows a block diagram of the crossbar switch. CPU instructions CPU data / Nexus Crossbar Switch Master modules Slave modules Flash memory Internal SRAM Peripheral bridges Figure 17-1. XBAR block diagram Table 17-1 gives the crossbar switch port for each master and slave, and the assigned and fixed ID number for each master. The table shows the master ID numbers as they relate to the master port numbers. Table 17-1. XBAR switch ports for MPC5604B Module e200z0 core–CPU instructions e200z0 core–CPU data / Nexus Flash memory Internal SRAM Peripheral bridges Type Master Master Slave Slave Slave Port Logical number 0 0 0 2 7 Physical master ID 0 1 — — — MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 301 17.3 Overview The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are granted access based on a fixed priority. 17.4 Features • 2 master ports: — Core: e200z0 core instructions — Core: e200z0 core data / Nexus • 3 slave ports — Flash (refer to the flash memory chapter for information on accessing flash memory) — Internal SRAM — Peripheral bridges • 32-bit address, 32-bit data paths • Fully concurrent transfers between independent master and slave ports • Fixed priority scheme and fixed parking strategy 17.5 Modes of operation 17.5.1 Normal mode In normal mode, the XBAR provides the logic that controls crossbar switch configuration. 17.5.2 Debug mode The XBAR operation in debug mode is identical to operation in normal mode. 17.6 Functional description This section describes the functionality of the XBAR in more detail. 17.6.1 Overview The main goal of the XBAR is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep arbitration delays to a minimum. MPC5604B/C Microcontroller Reference Manual, Rev. 8 302 Freescale Semiconductor This section examines data throughput from the point of view of masters and slaves, detailing when the XBAR stalls masters, or inserts bubbles on the slave side. 17.6.2 General operation When a master makes an access to the XBAR from an idle master state, the access is taken immediately by the XBAR. If the targeted slave port of the access is available (that is, the requesting master is currently granted ownership of the slave port), the access is immediately presented on the slave port. It is possible to make single clock (zero wait state) accesses through the XBAR by a granted master. If the targeted slave port of the access is busy or parked on a different master port, the requesting master receives wait states until the targeted slave port can service the master request. The latency in servicing the request depends on each master’s priority level and the responding slave’s access time. Because the XBAR appears to be simply another slave to the master device, the master device has no indication that it owns the slave port it is targeting. While the master does not have control of the slave port it is targeting, it is wait-stated. A master is given control of a targeted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from occurring when a master has the following conditions: • Outstanding request to slave port A that has a long response time • Pending access to a different slave port B • Lower priority master also makes a request to the different slave port B. In this case, the lower priority master is granted bus ownership of slave port B after a cycle of arbitration, assuming the higher priority master slave port A access is not terminated. After a master has control of the slave port it is targeting, the master remains in control of that slave port until it gives up the slave port by running an IDLE cycle, leaves that slave port for its next access, or loses control of the slave port to a higher priority master with a request to the same slave port. However, because all masters run a fixed-length burst transfer to a slave port, it retains control of the slave port until that transfer sequence is completed. When a slave bus is idled by the XBAR, it is parked on the master which did the last transfer. 17.6.3 Master ports A master access is taken if the slave port to which the access decodes is either currently servicing the master or is parked on the master. In this case, the XBAR is completely transparent and the master access is immediately transmitted on the slave bus and no arbitration delays are incurred. A master access stall if the access decodes to a slave port that is busy serving another master, parked on another master. If the slave port is currently parked on another master, and no other master is requesting access to the slave port, then only one clock of arbitration is incurred. If the slave port is currently serving another master of a lower priority and the master has a higher priority than all other requesting masters, then the master gains control over the slave port as soon as the data phase of the current access is completed. If the slave port is currently servicing another master of a higher priority, then the master gains control of the slave port after MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 303 the other master releases control of the slave port if no other higher priority master is also waiting for the slave port. A master access is responded to with an error if the access decodes to a location not occupied by a slave port. This is the only time the XBAR directly responds with an error response. All other error responses received by the master are the result of error responses on the slave ports being passed through the XBAR. 17.6.4 Slave ports The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when masters are actively making requests. To do this the XBAR must not insert any bubbles onto the slave bus unless absolutely necessary. There is only one instance when the XBAR forces a bubble onto the slave bus when a master is actively making a request. This occurs when a handoff of bus ownership occurs and there are no wait states from the slave port. A requesting master which does not own the slave port is granted access after a one clock delay. 17.6.5 Priority assignment Each master port is assigned a fixed 3-bit priority level (hard-wired priority). The following table shows the priority levels assigned to each master (the lowest has highest priority). Table 17-2. Hardwired bus master priorities Module e200z0 core–CPU instructions e200z0 core–CPU data / Nexus Port Type Number Master 0 Master 0 Priority level 7 6 17.6.6 Arbitration XBAR supports only a fixed-priority comparison algorithm. 17.6.6.1 Fixed priority operation When operating in fixed-priority arbitration mode, each master is assigned a unique priority level in the XBAR_MPR. If two masters both request access to a slave port, the master with the highest priority in the selected priority register gains control over the slave port. Any time a master makes a request to a slave port, the slave port checks to see if the new requesting master’s priority level is higher than that of the master that currently has control over the slave port (if any). The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. If the new requesting master’s priority level is higher than that of the master that currently has control of the slave port, the higher priority master is granted control at the termination of any currently pending access, assuming the pending transfer is not part of a burst transfer. MPC5604B/C Microcontroller Reference Manual, Rev. 8 304 Freescale Semiconductor A new requesting master must wait until the end of the fixed-length burst transfer, before it is granted control of the slave port. But if the new requesting master’s priority level is lower than that of the master that currently has control of the slave port, the new requesting master is forced to wait until the master that currently has control of the slave port is finished accessing the current slave port. 17.6.6.1.1 Parking If no master is currently requesting the slave port, the slave port is parked. The slave port parks always to the last master (park-on-last). When parked on the last master, the slave port is passing that master’s signals through to the slave bus. When the master accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave port made by another master port. All other masters pay a one clock penalty. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 305 MPC5604B/C Microcontroller Reference Manual, Rev. 8 306 Freescale Semiconductor Chapter 18 Memory Protection Unit (MPU) 18.1 Introduction The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in the device. Using preprogrammed region descriptors which define memory spaces and their associated access rights, the MPU concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references that have sufficient access control rights are allowed to complete, while references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. The MPU module provides the following capabilities: • Support for 8 program-visible 128-bit (4-word) region descriptors — Each region descriptor defines a modulo-32 byte space, aligned anywhere in memory – Region sizes can vary from a minimum of 32 bytes to a maximum of 4 Gbytes — Two types of access control permissions defined in single descriptor word – Processors have separate {read, write, execute} attributes for supervisor and user accesses – Non-processor masters have {read, write} attributes — Hardware-assisted maintenance of the descriptor valid bit minimizes coherency issues — Alternate programming model view of the access control permissions word • Memory-mapped platform device — Interface to 3 slave XBAR ports: flash controller, system SRAM controller and peripherals bus – Connections to the address phase address and attributes – Typical location is immediately “downstream” of the platform’s crossbar switch A simplified block diagram of the MPU module is shown in Figure 18-1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 307 Platform Core (z0hn2p) s0 m0 s2 m1 XBAR MPU s7 PFlash PRAM PBRIDGE0 Figure 18-1. MPU block diagram 18.2 Features The Memory Protection Unit implements a two-dimensional hardware array of memory region descriptors and the crossbar slave XBAR ports to continuously monitor the legality of every memory reference generated by each bus master in the system. The feature set includes: • Support for 8 memory region descriptors, each 128 bits in size — Specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 GB — Access control definitions: 2 bus masters (processor cores) support the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses — Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor — Alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter only the access rights of a descriptor — For overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more flexibility to system software. See Section 18.6.2, “Putting it all together and AHB error terminations,” for details and Section 18.8, “Application information,” for an example. • Support for 3 XBAR slave port connections: flash controller, system SRAM controller and peripherals bus MPC5604B/C Microcontroller Reference Manual, Rev. 8 308 Freescale Semiconductor — MPU hardware continuously monitors every XBAR slave port access using the preprogrammed memory region descriptors — An access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device. — 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes and “detail” information • Global MPU enable/disable control bit provides a mechanism to easily load region descriptors during system startup or allow complete access rights during debug with the module disabled 18.3 Modes of operation The MPU module does not support any special modes of operation. As a memory-mapped device located on the platform’s high-speed system bus, it responds based strictly on the memory addresses of the connected system buses. The peripheral bus is used to access the MPU’s programming model and the memory protection functions are evaluated on a reference-by-reference basis using the addresses from the XBAR system bus port(s). Power dissipation is minimized when the MPU’s global enable/disable bit is cleared (MPU_CESR[VLD] = 0). 18.4 External signal description The MPU module does not include any external interface. The MPU’s internal interfaces include a peripheral bus connection for accessing the programming model and multiple connections to the address phase signals of the platform crossbar’s slave AHB ports. From a platform topology viewpoint, the MPU module appears to be directly connected “downstream” from the crossbar switch with interfaces to the XBAR slave ports. 18.5 Memory map and register description The MPU module provides an IPS programming model mapped to an SPP-standard on-platform 16 KB space. The programming model is partitioned into three groups: control/status registers, the data structure containing the region descriptors and the alternate view of the region descriptor access control values. The programming model can only be referenced using 32-bit (word) accesses. Attempted references using different access sizes, to undefined (reserved) addresses, or with a non-supported access type (for example, a write to a read-only register or a read of a write-only register) generate an IPS error termination. Finally, the programming model allocates space for an MPU definition with 8 region descriptors and up to 3 XBAR slave ports, like flash controller, system SRAM controller and peripheral bus. 18.5.1 Memory map The MPU programming model map is shown in Table 18-1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 309 Table 18-1. MPU memory map Base address: 0xFFF1_1000 Address offset Register 0x000 0x004–0x00F 0x010 0x014 0x018 0x01C 0x020 0x024 0x028–0x3FF 0x400 0x410 0x420 0x430 0x440 0x450 0x460 0x470 0x480–0x7FF 0x800 0x804 0x808 0x80C 0x810 0x814 0x818 0x81C MPU Control/Error Status Register (MPU_CESR) Reserved MPU Error Address Register, Slave Port 0 (MPU_EAR0) MPU Error Detail Register, Slave Port 0 (MPU_EDR0) MPU Error Address Register, Slave Port 1 (MPU_EAR1) MPU Error Detail Register, Slave Port 1 (MPU_EDR1) MPU Error Address Register, Slave Port 2 (MPU_EAR2) MPU Error Detail Register, Slave Port 2 (MPU_EDR2) Reserved MPU Region Descriptor 0 (MPU_RGD0) MPU Region Descriptor 1 (MPU_RGD1) MPU Region Descriptor 2 (MPU_RGD2) MPU Region Descriptor 3 (MPU_RGD3) MPU Region Descriptor 4 (MPU_RGD4) MPU Region Descriptor 5 (MPU_RGD5) MPU Region Descriptor 6 (MPU_RGD6) MPU Region Descriptor 7 (MPU_RGD7) Reserved MPU RGD Alternate Access Control 0 (MPU_RGDAAC0) MPU RGD Alternate Access Control 1 (MPU_RGDAAC1) MPU RGD Alternate Access Control 2 (MPU_RGDAAC2) MPU RGD Alternate Access Control 3 (MPU_RGDAAC3) MPU RGD Alternate Access Control 4 (MPU_RGDAAC4) MPU RGD Alternate Access Control 5 (MPU_RGDAAC5) MPU RGD Alternate Access Control 6 (MPU_RGDAAC6) MPU RGD Alternate Access Control 7 (MPU_RGDAAC7) Location on page 310 on page 311 on page 312 on page 311 on page 312 on page 311 on page 312 on page 314 on page 314 on page 314 on page 314 on page 314 on page 314 on page 314 on page 314 on page 319 on page 319 on page 319 on page 319 on page 319 on page 319 on page 319 on page 319 18.5.2 Register description 18.5.2.1 MPU Control/Error Status Register (MPU_CESR) The MPU_CESR provides one byte of error status plus three bytes of configuration information. A global MPU enable/disable bit is also included in this register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 310 Freescale Semiconductor Offset: 0x000 Access: Read/Partial Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SPERR[7:0] 1000 HRL W w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 1 0 0 0 * * * * 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R NSP W NRGD 0000000 VLD Reset * * * * * * * * 0 0 0 0 0 0 0 0 Figure 18-2. MPU Control/Error Status Register (MPU_CESR) Table 18-2. MPU_CESR field descriptions Field Description SPERRn Slave Port n Error, where the slave port number matches the bit number. Each bit in this field represents a flag maintained by the MPU for signaling the presence of a captured error contained in the MPU_EARn and MPU_EDRn registers. The individual bit is set when the hardware detects an error and records the faulting address and attributes. It is cleared when the corresponding bit is written as a logical one. If another error is captured at the exact same cycle as a write of a logical one, this flag remains set. A “find first one” instruction (or equivalent) can be used to detect the presence of a captured error. 0 The corresponding MPU_EARn/MPU_EDRn registers do not contain a captured error. 1 The corresponding MPU_EARn/MPU_EDRn registers do contain a captured error. HRL Hardware Revision Level This field specifies the MPU’s hardware and definition revision level. It can be read by software to determine the functional definition of the module. NSP Number of Slave Ports This field specifies the number of slave ports [1–8] connected to the MPU. NRGD Number of Region Descriptors This field specifies the number of region descriptors implemented in the MPU. The defined encodings include: 0b0000 8 region descriptors 0b0001 12 region descriptors 0b0010 16 region descriptors VLD Valid This bit provides a global enable/disable for the MPU. 0 The MPU is disabled. 1 The MPU is enabled. While the MPU is disabled, all accesses from all bus masters are allowed. 18.5.2.2 MPU Error Address Register, Slave Port n (MPU_EARn) When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this read-only register and the corresponding bit in the MPU_CESR[SPERR] field set. Additional information MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 311 about the faulting access is captured in the corresponding MPU_EDRn register at the same time. Note this register and the corresponding MPU_EDRn register contain the most recent access error; there are no hardware interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the occurrence of each protection violation. Offsets: 0x010–0x020 (3 registers) Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R EADDR [31:16] W Reset – – – – – – – – – – – – – – – – 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EADDR [15:0] W Reset – – – – – – – – – – – – – – – – Figure 18-3. MPU Error Address Register, Slave Port n (MPU_EARn) Table 18-3. MPU_EARn field descriptions Field EADDR Description Error Address This field is the reference address from slave port n that generated the access error. 18.5.2.3 MPU Error Detail Register, Slave Port n (MPU_EDRn) When the MPU detects an access error on slave port n, 32 bits of error detail are captured in this read-only register and the corresponding bit in the MPU_CESR[SPERR] field set. Information on the faulting address is captured in the corresponding MPU_EARn register at the same time. Note that this register and the corresponding MPU_EARn register contain the most recent access error; there are no hardware interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the occurrence of each protection violation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 312 Freescale Semiconductor Offsets: 0x014–0x024 (3 registers) Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R EACD W Reset – – – – – – – – – – – – – – – – 16 R W Reset – 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EPID EMN EATTR ERW ––––––––––––––– Figure 18-4. MPU Error Detail Register, Slave Port n (MPU_EDRn) Table 18-4. MPU_EDRn field descriptions Field EACD Description Error Access Control Detail This field implements one bit per region descriptor and is an indication of the region descriptor hit logically ANDed with the access error indication. The MPU performs a reference-by-reference evaluation to determine the presence/absence of an access error. When an error is detected, the hit-qualified access control vector is captured in this field. EPID EMN EATTR ERW If the MPU_EDRn register contains a captured error and the EACD field is all zeroes, this signals an access that did not hit in any region descriptor. All non-zero EACD values signal references that hit in a region descriptor(s), but failed due to a protection error as defined by the specific set bits. If only a single EACD bit is set, then the protection error was caused by a single non-overlapping region descriptor. If two or more EACD bits are set, then the protection error was caused in an overlapping set of region descriptors. Error Process Identification This field records the process identifier of the faulting reference. The process identifier is typically driven only by processor cores; for other bus masters, this field is cleared. Error Master Number This field records the logical master number of the faulting reference. This field is used to determine the bus master that generated the access error. Error Attributes This field records attribute information about the faulting reference. The supported encodings are defined as: 0b000 User mode, instruction access 0b001 User mode, data access 0b010Supervisor mode, instruction access 0b011Supervisor mode, data access All other encodings are reserved. For non-core bus masters, the access attribute information is typically wired to supervisor, data (0b011). Error Read/Write This field signals the access type (read, write) of the faulting reference. 0 Read 1 Write MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 313 18.5.2.4 MPU Region Descriptor n (MPU_RGDn) Each 128-bit (16 byte) region descriptor specifies a given memory space and the access attributes associated with that space. The descriptor definition is the very essence of the operation of the Memory Protection Unit. The region descriptors are organized sequentially in the MPU’s programming model and each of the four 32-bit words are detailed in the subsequent sections. 18.5.2.4.1 MPU Region Descriptor n, Word 0 (MPU_RGDn.Word0) The first word of the MPU region descriptor defines the 0-modulo-32 byte start address of the memory region. Writes to this word clear the region descriptor’s valid bit (see Section 18.5.2.4.4, “MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3) for more information). Offset: 0x400 + (16*n) + 0x0 (MPU_RGDn.Word0) 0 1 2 3 4 5 6 7 8 9 R SRTADDR[26:11] W Reset – – – – – – – – – – Access: Read/write 10 11 12 13 14 15 –––––– 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SRTADDR[10:0] 00000 W Reset – – – – – – – – – – – 0 0 0 0 0 Figure 18-5. MPU Region Descriptor, Word 0 Register (MPU_RGDn.Word0) Table 18-5. MPU_RGDn.Word0 field descriptions Field SRTADDR Description Start Address This field defines the most significant bits of the 0-modulo-32 byte start address of the memory region. 18.5.2.4.2 MPU Region Descriptor n, Word 1 (MPU_RGDn.Word1) The second word of the MPU region descriptor defines the 31-modulo-32 byte end address of the memory region. Writes to this word clear the region descriptor’s valid bit (see Section 18.5.2.4.4, “MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3) for more information). MPC5604B/C Microcontroller Reference Manual, Rev. 8 314 Freescale Semiconductor Offset: 0x400 + (16*n) + 0x4 (MPU_RGDn.Word1) 0 1 2 3 4 5 6 7 8 9 R ENDADDR[26:11] W Reset – – – – – – – – – – Access: Read/write 10 11 12 13 14 15 –––––– 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ENDADDR[10:0] W 11111 Reset – – – – – – – – – – – 1 1 1 1 1 Figure 18-6. MPU Region Descriptor, Word 1 Register (MPU_RGDn.Word1) Table 18-6. MPU_RGDn.Word1 field descriptions Field ENDADDR Description End Address This field defines the most significant bits of the 31-modulo-32 byte end address of the memory region. There are no hardware checks to verify that ENDADDR >= SRTADDR; it is software’s responsibility to properly load these region descriptor fields. 18.5.2.4.3 MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2) The third word of the MPU region descriptor defines the access control rights of the memory region. The access control privileges are dependent on two broad classifications of bus masters. Bus masters 0–3 are typically reserved for processor cores and the corresponding access control is a 6-bit field defining separate privilege rights for user and supervisor mode accesses as well as the optional inclusion of a process identification field within the definition. Bus masters 4–7 are typically reserved for data movement engines and their capabilities are limited to separate read and write permissions. For these fields, the bus master number refers to the logical master number defined as the XBAR hmaster[3:0] signal. For the processor privilege rights, there are three flags associated with this function: {read, write, execute}. In this context, these flags follow the traditional definition: • Read (r) permission refers to the ability to access the referenced memory address using an operand (data) fetch. • Write (w) permission refers to the ability to update the referenced memory address using a store (data) instruction. • Execute (x) permission refers to the ability to read the referenced memory address using an instruction fetch. The evaluation logic defines the processor access type based on multiple AHB signals, as hwrite and hprot[1:0]. For non-processor data movement engines (bus masters 4–7), the evaluation logic simply uses hwrite to determine if the access is a read or write. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 315 Writes to this word clear the region descriptor’s valid bit (see Section 18.5.2.4.4, “MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3) for more information). Since it is also expected that system software may adjust only the access controls within a region descriptor (MPU_RGDn.Word2) as different tasks execute, an alternate programming view of this 32-bit entity is provided. If only the access controls are being updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s valid bit. Offset: 0x400 + (16*n) + 0x8 (MPU_RGDn.Word2) Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R M3SM M3UM W M2PE M2SM[1] M7RE M7WE M6RE M6WE M5RE M5WE M4RE M4WE M3PE Reset – – – – – – – – – – – – – – – – M2SM[0] M1PE M0PE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R M2UM W M1SM M1UM M0SM M0UM Reset – – – – – – – – – – – – – – – – Figure 18-7. MPU Region Descriptor, Word 2 Register (MPU_RGDn.Word2) Table 18-7. MPU_RGDn.Word2 field descriptions Field M7RE M7WE M6RE M6WE M5RE M5WE M4RE Description Bus master 7 read enable If set, this flag allows bus master 7 to perform read operations. If cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. Bus master 7 write enable If set, this flag allows bus master 7 to perform write operations. If cleared, any attempted write by bus master 7 terminates with an access error and the write is not performed. Bus master 6 read enable If set, this flag allows bus master 6 to perform read operations. If cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed. Bus master 6 write enable If set, this flag allows bus master 6 to perform write operations. If cleared, any attempted write by bus master 6 terminates with an access error and the write is not performed. Bus master 5 read enable If set, this flag allows bus master 5 to perform read operations. If cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. Bus master 5 write enable If set, this flag allows bus master 5 to perform write operations. If cleared, any attempted write by bus master 5 terminates with an access error and the write is not performed. Bus master 4 read enable If set, this flag allows bus master 4 to perform read operations. If cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 316 Freescale Semiconductor Table 18-7. MPU_RGDn.Word2 field descriptions (continued) Field M4WE M3PE M3SM M3UM M2PE M2SM M2UM M1PE M1SM Description Bus master 4 write enable If set, this flag allows bus master 4 to perform write operations. If cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. Bus master 3 process identifier enable If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. Bus master 3 supervisor mode access control This field defines the access controls for bus master 3 when operating in supervisor mode. The M3SM field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, –, x = read and execute allowed, but no write 0b10 r, w, – = read and write allowed, but no execute 0b11 Same access controls as that defined by M3UM for user mode Bus master 3 user mode access control This field defines the access controls for bus master 3 when operating in user mode. The M3UM field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. Bus master 2 process identifier enable If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. Bus master 2 supervisor mode access control This field defines the access controls for bus master 2 when operating in supervisor mode. The M2SM field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, –, x = read and execute allowed, but no write 0b10 r, w, – = read and write allowed, but no execute 0b11 Same access controls as that defined by M2UM for user mode Bus master 2 user mode access control This field defines the access controls for bus master 2 when operating in user mode. The M2UM field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. Bus master 1 process identifier enable If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. Bus master 1 supervisor mode access control This field defines the access controls for bus master 1 when operating in supervisor mode. The M1SM field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, –, x = read and execute allowed, but no write 0b10 r, w, – = read and write allowed, but no execute 0b11 Same access controls as that defined by M1UM for user mode MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 317 Table 18-7. MPU_RGDn.Word2 field descriptions (continued) Field M1UM M0PE M0SM M0UM Description Bus master 1 user mode access control This field defines the access controls for bus master 1 when operating in user mode. The M1UM field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. Bus master 0 process identifier enable If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. Bus master 0 supervisor mode access control This field defines the access controls for bus master 0 when operating in supervisor mode. The M0SM field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, –, x = read and execute allowed, but no write 0b10 r, w, – = read and write allowed, but no execute 0b11 Same access controls as that defined by M0UM for user mode Bus master 0 user mode access control This field defines the access controls for bus master 0 when operating in user mode. The M0UM field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. 18.5.2.4.4 MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3) The fourth word of the MPU region descriptor contains the optional process identifier and mask, plus the region descriptor’s valid bit. Since the region descriptor is a 128-bit entity, there are potential coherency issues as this structure is being updated since multiple writes are required to update the entire descriptor. Accordingly, the MPU hardware assists in the operation of the descriptor valid bit to prevent incoherent region descriptors from generating spurious access errors. In particular, it is expected that a complete update of a region descriptor is typically done with sequential writes to MPU_RGDn.Word0, then MPU_RGDn.Word1,... and finally MPU_RGDn.Word3. The MPU hardware automatically clears the valid bit on any writes to words {0,1,2} of the descriptor. Writes to this word set/clear the valid bit in a normal manner. Since it is also expected that system software may adjust only the access controls within a region descriptor (MPU_RGDn.Word2) as different tasks execute, an alternate programming view of this 32-bit entity is provided. If only the access controls are being updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s valid bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 318 Freescale Semiconductor Offset: 0x400 + (16*n) + 0xC (MPU_RGDn.Word3) Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PID W PIDMASK Reset – – – – – – – – – – – – – – – – 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18-8. MPU Region Descriptor, Word 3 Register (MPU_RGDn.Word3) Table 18-8. MPU_RGDn.Word3 field descriptions Field Description PID Process Identifier This field specifies that the optional process identifier is to be included in the determination of whether the current access hits in the region descriptor. This field is combined with the PIDMASK and included in the region hit determination if MPU_RGDn.Word2[MxPE] is set. PIDMASK Process Identifier Mask This field provides a masking capability so that multiple process identifiers can be included as part of the region hit determination. If a bit in the PIDMASK is set, then the corresponding bit of the PID is ignored in the comparison. This field is combined with the PID and included in the region hit determination if MPU_RGDn.Word2[MxPE] is set. For more information on the handling of the PID and PIDMASK, see Section 18.6.1.1, “Access evaluation – Hit determination. VLD Valid This bit signals the region descriptor is valid. Any write to MPU_RGDn.Word{0,1,2} clears this bit, while a write to MPU_RGDn.Word3 sets or clears this bit depending on bit 31 of the write operand. 0 Region descriptor is invalid 1 Region descriptor is valid 18.5.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn) As noted in Section 18.5.2.4.3, “MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2), it is expected that since system software may adjust only the access controls within a region descriptor (MPU_RGDn.Word2) as different tasks execute, an alternate programming view of this 32-bit entity is desired. If only the access controls are being updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s valid bit. The memory address therefore provides an alternate location for updating MPU_RGDn.Word2. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 319 Offset: 0x800 + (4*n) (MPU_RGDAACn) Access: Read/write M2PE M2SM[1] M7RE M7WE M6RE M6WE M5RE M5WE M4RE M4WE M3PE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R M3SM M3UM W Reset – – – – – – – – – – – – – – – – M2SM[0] M1PE M0PE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R M2UM W M1SM M1UM M0SM M0UM Reset – – – – – – – – – – – – – – – – Figure 18-9. MPU RGD Alternate Access Control n (MPU_RGDAACn) Since the MPU_RGDAACn register is simply another memory mapping for MPU_RGDn.Word2, the field definitions shown in Table 18-9 are identical to those presented in Table 18-7. Table 18-9. MPU_RGDAACn field descriptions Field M7RE M7WE M6RE M6WE M5RE M5WE M4RE M4WE Description Bus master 7 read enable. If set, this flag allows bus master 7 to perform read operations. If cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. Bus master 7 write enable If set, this flag allows bus master 7 to perform write operations. If cleared, any attempted write by bus master 7 terminates with an access error and the write is not performed. Bus master 6 read enable If set, this flag allows bus master 6 to perform read operations. If cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed. Bus master 6 write enable If set, this flag allows bus master 6 to perform write operations. If cleared, any attempted write by bus master 6 terminates with an access error and the write is not performed. Bus master 5 read enable If set, this flag allows bus master 5 to perform read operations. If cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. Bus master 5 write enable If set, this flag allows bus master 5 to perform write operations. If cleared, any attempted write by bus master 5 terminates with an access error and the write is not performed. Bus master 4 read enable If set, this flag allows bus master 4 to perform read operations. If cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. Bus master 4 write enable If set, this flag allows bus master 4 to perform write operations. If cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 320 Freescale Semiconductor Table 18-9. MPU_RGDAACn field descriptions (continued) Field M3PE M3SM M3UM M2PE M2SM M2UM M1PE M1SM M1UM Description Bus master 3 process identifier enable If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. Bus master 3 supervisor mode access control This field defines the access controls for bus master 3 when operating in supervisor mode. The M3SM field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, –, x = read and execute allowed, but no write 0b10 r, w, – = read and write allowed, but no execute 0b11 Same access controls as that defined by M3UM for user mode Bus master 3 user mode access control This field defines the access controls for bus master 3 when operating in user mode. The M3UM field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. Bus master 2 process identifier enable If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. Bus master 2 supervisor mode access control This field defines the access controls for bus master 2 when operating in supervisor mode. The M2SM field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, –, x = read and execute allowed, but no write 0b10 r, w, – = read and write allowed, but no execute 0b11 Same access controls as that defined by M2UM for user mode Bus master 2 user mode access control This field defines the access controls for bus master 2 when operating in user mode. The M2UM field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. Bus master 1 process identifier enable If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. Bus master 1 supervisor mode access control This 2-bit field defines the access controls for bus master 1 when operating in supervisor mode. The M1SM field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, –, x = read and execute allowed, but no write 0b10 r, w, – = read and write allowed, but no execute 0b11 Same access controls as that defined by M1UM for user mode Bus master 1 user mode access control This 3-bit field defines the access controls for bus master 1 when operating in user mode. The M1UM field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 321 Table 18-9. MPU_RGDAACn field descriptions (continued) Field M0PE M0SM M0UM Description Bus master 0 process identifier enable If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. Bus master 0 supervisor mode access control This field defines the access controls for bus master 0 when operating in supervisor mode. The M0SM field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, –, x = read and execute allowed, but no write 0b10 r, w, – = read and write allowed, but no execute 0b11 Same access controls as that defined by M0UM for user mode Bus master 0 user mode access control This field defines the access controls for bus master 0 when operating in user mode. The M0UM field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. 18.6 Functional description In this section, the functional operation of the MPU is detailed. In particular, subsequent sections discuss the operation of the access evaluation macro as well as the handling of error-terminated bus cycles. 18.6.1 Access evaluation macro As previously discussed, the basic operation of the MPU is performed in the access evaluation macro, a hardware structure replicated in the two-dimensional connection matrix. As shown in Figure 18-10, the access evaluation macro inputs the system bus address phase signals and the contents of a region descriptor (RGDn) and performs two major functions: region hit determination (hit_b) and detection of an access protection violation (error). System bus address phase start >= end <= RGDn r,w,x hit_b >> error hit & error hit_b | error Figure 18-10. MPU access evaluation macro MPC5604B/C Microcontroller Reference Manual, Rev. 8 322 Freescale Semiconductor Figure 18-10 is not intended to be a schematic of the actual access evaluation macro, but rather a generalized block diagram showing the major functions included in this logic block. 18.6.1.1 Access evaluation – Hit determination To evaluate the region hit determination, the MPU uses two magnitude comparators in conjunction with the contents of a region descriptor: the current access must be included between the region's “start” and “end” addresses and simultaneously the region's valid bit must be active. Recall there are no hardware checks to verify that region's “end” address is greater then region's “start” address, and it is software’s responsibility to properly load appropriate values into these fields of the region descriptor. In addition to this, the optional process identifier is examined against the region descriptor’s PID and PIDMASK fields. In order to generate the pid_hit indication: the current PID with its PIDMASK must be equal to the region's PID with its PIDMASK. Also the process identifier enable is take into account in this comparison so that the MPU forces the pid_hit term to be asserted in the case of AHB bus master doesn't provide its process identifier. 18.6.1.2 Access evaluation – Privilege violation determination While the access evaluation macro is making the region hit determination, the logic is also evaluating if the current access is allowed by the permissions defined in the region descriptor. The protection violation logic then evaluates the access against the effective permissions using the specification shown in Table 18-10. Table 18-10. Protection violation definition Description inst fetch read inst fetch read data read data read data write data write eff_rgd[r] — — 0 1 — — Inputs eff_rgd[w] — — — — 0 1 eff_rgd[x] 0 1 — — — — Output Protection violation? yes, no x permission no, access is allowed yes, no r permission no, access is allowed yes, no w permission no, access is allowed As shown in Figure 18-10, the output of the protection violation logic is the error signal. The access evaluation macro then uses the hit_b and error signals to form two outputs. The combined (hit_b | error) signal is used to signal the current access is not allowed and (~hit_b & error) is used as the input to MPU_EDRn (error detail register) in the event of an error. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 323 18.6.2 Putting it all together and AHB error terminations For each XBAR slave port being monitored, the MPU performs a reduction-AND of all the individual (hit_b | error) terms from each access evaluation macro. This expression then terminates the bus cycle with an error and reports a protection error for three conditions: 1. If the access does not hit in any region descriptor, a protection error is reported. 2. If the access hits in a single region descriptor and that region signals a protection violation, then a protection error is reported. 3. If the access hits in multiple (overlapping) regions and all regions signal protection violations, then a protection error is reported. The third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to system software in region descriptor assignments. For an example of the use of overlapping region descriptors, see Section 18.8, “Application information. In event of a protection error, the MPU requires two distinct actions: 1. Intercepting the error during the address phase (first cycle out of two) and cancelling the transaction before it is seen by the slave device 2. Performing the required logic functions to force the standard 2-cycle AHB error response to properly terminate the bus transaction and then providing the right values to the crossbar switch to commit the transaction to other portions of the platform. If, instead, the access is allowed, then the MPU simply passes all “original” signals to the slave device. In this case, from a functionality point of view, the MPU is fully transparent. 18.7 Initialization information The reset state of MPU_CESR[VLD] disables the entire module. Recall that, while the MPU is disabled, all accesses from all bus masters are allowed. This state also minimizes the power dissipation of the MPU. The power dissipation of each access evaluation macro is minimized when the associated region descriptor is marked as invalid or when MPU_CESR[VLD] = 0. Typically the appropriate number of region descriptors (MPU_RGDn) is loaded at system startup, including the setting of the MPU_RGDn.Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling the module. This approach allows all the loaded region descriptors to be enabled simultaneously. Recall if a memory reference does not hit in any region descriptor, the attempted access is terminated with an error. 18.8 Application information In an operational system, interfacing with the MPU can generally be classified into the following activities: 1. Creation of a new memory region requires loading the appropriate region descriptor into an available register location. When a new descriptor is loaded into a RGDn, it would typically be performed using four 32-bit word writes. As discussed in Section 18.5.2.4.4, “MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3), the hardware assists in the maintenance of the valid MPC5604B/C Microcontroller Reference Manual, Rev. 8 324 Freescale Semiconductor bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle descriptor writes. Deletion/removal of an existing memory region is performed simply by clearing MPU_RGDn.Word3[VLD]. 2. If only the access rights for an existing region descriptor need to change, a 32-bit write to the alternate version of the access control word (MPU_RGDAACn) would typically be performed. Recall writes to the region descriptor using this alternate access control location do not affect the valid bit, so there are, by definition, no coherency issues involved with the update. The access rights associated with the memory region switch instantaneously to the new value as the IPS write completes. 3. If the region’s start and end addresses are to be changed, this would typically be performed by writing a minimum of three words of the region descriptor: MPU_RGDn.Word{0,1,3}, where the writes to Word0 and Word1 redefine the start and end addresses respectively and the write to Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region descriptor would be rewritten. 4. Typically, references to the MPU’s programming model would be restricted to supervisor mode accesses from a specific processor(s), so a region descriptor would be specifically allocated for this purpose with attempted accesses from other masters or while in user mode terminated with an error. When the MPU detects an access error, the current bus cycle is terminated with an error response and information on the faulting reference captured in the MPU_EARn and MPU_EDRn registers. The error-terminated bus cycle typically initiates some type of error response in the originating bus master. For example, the CPU errors will generate a core exception, whereas the DMA errors will generate a MPU (external) interrupt. It is important to highlight that in case of DMA access violations the core will continue to run, but if a core violation occurs the system will stop. In any event, the processor can retrieve the captured error address and detail information simply be reading the MPU_E{A,D}Rn registers. Information on which error registers contain captured fault data is signaled by MPU_CESR[SPERR]. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 325 MPC5604B/C Microcontroller Reference Manual, Rev. 8 326 Freescale Semiconductor Chapter 19 System Integration Unit Lite (SIUL) 19.1 Introduction This chapter describes the System Integration Unit Lite (SIUL), which is used for the management of the pads and their configuration. It controls the multiplexing of the alternate functions used on all pads as well as being responsible for the management of the external interrupts to the device. 19.2 Overview The System Integration Unit Lite (SIUL) controls the MCU pad configuration, ports, general-purpose input and output (GPIO) signals and external interrupts with trigger event configuration. Figure 19-1 provides a block diagram of the SIUL and its interfaces to other system components. The module provides the capability to configure, read, and write to the device’s general-purpose I/O pads that can be configured as either inputs or outputs. • When a pad is configured as an input, the state of the pad (logic high or low) is obtained by reading an associated data input register. • When a pad is configured as an output, the value driven onto the pad is determined by writing to an associated data output register. Enabling the input buffers when a pad is configured as an output allows the actual state of the pad to be read. • To enable monitoring of an output pad value, the pad can be configured as both output and input so the actual pad value can be read back and compared with the expected value. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 327 SIUL Module Pad Configuration (IOMUXC) Pad Config (PCRs) 123(1) IPS Master GPIO Functionality Data Pad Input 123(1) 123(1) IO MUX Pads 123(1) IPS BUS Interrupt Functionality Interrupt - Configuration - Glitch Filter 16(2) 2 Interrupt Controller Notes: 1 Up to 123 I/O pins in 144-pin and 208-pin packages; up to 79 I/O pins in 100-pin packages 2 Up to 16 I/O pins in 144-pin and 208-pin packages; up to 12 I/O pins in 100-pin packages Figure 19-1. System Integration Unit Lite block diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 328 Freescale Semiconductor 19.3 Features The System Integration Unit Lite supports these distinctive features: • GPIO — GPIO function on up to 123 I/O pins — Dedicated input and output registers for most GPIO pins1 • External interrupts — 2 system interrupt vectors for up to 16 interrupt sources — 16 programmable digital glitch filters — Independent interrupt mask — Edge detection • System configuration — Pad configuration control 19.4 External signal description Most device pads support multiple device functions. Pad configuration registers are provided to enable selection between GPIO and other signals. These other signals, also referred to as alternate functions, are typically peripheral functions. GPIO pads are grouped in “ports”, with each port containing up to 16 pads. With appropriate configuration, all pins in a port can be read or written to in parallel with a single R/W access. NOTE In order to use GPIO port functionality, all pads in the port must be configured as GPIO rather than as alternate functions. Table 19-1 lists the external pins configurable via the SIUL. ( Table 19-1. SIUL signal properties GPIO[0:122]1 category Name I/O direction Function System configuration GPIO [0:19] [26:47] [60:122] Input/Output General-purpose input/output GPIO [20:25] [48:59] Input Analog precise channels, low power oscillator pins External interrupt EIRQ[0:15]2 Input Pins with External Interrupt Request functionality. Please see the signal description chapter of this reference manual for details. 1 GPIO[0:122] in 144-pin LQFP and 208 MAPBGA; GPIO[0:78] in 100-pin LQFP 2 EIRQ[12:15] available only in 144-pin LQFP 1.Some device pins, e.g., analog pins, do not have both input and output functionality. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 329 19.4.1 Detailed signal descriptions 19.4.1.1 General-purpose I/O pins (GPIO[0:122]) The GPIO pins provide general-purpose input and output function. The GPIO pins are generally multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an input (GPDIn_n) or output (GPDOn_n) register. 19.4.1.2 External interrupt request input pins (EIRQ[0:15])1 The EIRQ[0:15] pins are connected to the SIUL inputs. Rising- or falling-edge events are enabled by setting the corresponding bits in the SIUL_IREER or the SIUL_IFEER register. 1. EIRQ[0:15] in 144-pin LQFP and 208 MAPBGA packages; EIRQ[0:11] in the 100-pin LQFP MPC5604B/C Microcontroller Reference Manual, Rev. 8 330 Freescale Semiconductor 19.5 Memory map and register description This section provides a detailed description of all registers accessible in the SIUL module. 19.5.1 SIUL memory map Table 19-2 gives an overview of the SIUL registers implemented. Table 19-2. SIUL memory map Base address: 0xC3F9_0000 Address offset 0x0000 0x0004 0x0008 0x000C–0x0013 0x0014 0x0018 0x001C–0x0027 0x0028 0x002C 0x0030 0x0034–0x003F 0x0040–0x0134 0x0136–0x04FF 0x0500–0x051C 0x0520–0x05FF 0x0600–0x0678 0x067C–0x07FF 0x0800–0x0878 0x087C–0x0BFF 0x0C00–0x0C0C 0x0C10–0x0C3F 0x0C40–0x0C4C 0x0C50–0x0C7F 0x0C80–0x0C9C Register Reserved MCU ID Register #1 (MIDR1) MCU ID Register #2 (MIDR2) Reserved Interrupt Status Flag Register (ISR) Interrupt Request Enable Register (IRER) Reserved Interrupt Rising-Edge Event Enable Register (IREER) Interrupt Falling-Edge Event Enable Register (IFEER) Interrupt Filter Enable Register (IFER) Reserved Pad Configuration Registers (PCR0–PCR122)1 Reserved Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI28_31) Reserved GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123)2,3 Reserved GPIO Pad Data Input Registers (GPDI0_3–GPDI120_123)2,4 Reserved Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3) Reserved Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI3) Reserved Masked Parallel GPIO Pad Data Out Register (MPGPDO0–MPGPDO7) Location on page 333 on page 334 on page 335 on page 336 on page 336 on page 337 on page 338 on page 339 on page 341 on page 344 on page 345 on page 345 on page 346 on page 347 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 331 Table 19-2. SIUL memory map (continued) Base address: 0xC3F9_0000 Address offset Register Location 0x0CA0–0x0FFF 0x1000–0x103C Reserved Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15)5 on page 349 0x1040–0x107C Reserved 0x1080 Interrupt Filter Clock Prescaler Register (IFCPR) on page 349 0x1084–0x3FFF Reserved 1 PCR[0:122] is valid in the 144-pin LQFP and the 208 MAPBGA packages, while in the 100-pin LQFP packages is PCR[0:78], so all the remaining registers are reserved. 2 Not all registers are used. The registers, although byte-accessible are allocated on 32-bit boundaries. There are some unused registers at the end of the space. The number of unused registers is further reduced in packages with reduced GPIO pin count. 3 GPDO[0:123] is valid in the 144-pin LQFP and the 208 MAPBGA packages, while in the 100-pin LQFP packages is GPDO[0:76], so all the remaining registers are reserved. 4 GPDI[0:123] is valid in the 144-pin LQFP and the 208 MAPBGA packages, while in the 100-pin LQFP packages is GPDI[0:76], so all the remaining registers are reserved. 5 IFMC[0:15] is valid in the 144-pin LQFP and the 208 MAPBGA packages, while in the 100-pin LQFP packages is IFMC[0:11], so all the remaining registers are reserved. NOTE A transfer error will be issued when trying to access completely reserved register space. 19.5.2 Register protection Individual registers in System Integration Unit Lite can be protected from accidental writes using the Register Protection module. The following registers can be protected: • Interrupt Request Enable Register (IRER) • Interrupt Rising-Edge Event Enable Register (IREER) • Interrupt Falling-Edge Event Enable Register (IFEER) • Interrupt Filter Enable Register (IFER), • Pad Configuration Registers (PCR0–PCR122). Note that only the following registers can be protected: — PCR[0:15] (Port A) — PCR[16:19] (Port B[0:3]) — PCR[34:47] (Port C[2:15]) • Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI28_31) • Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15). Note that only IFMC[0:15] can be protected. • Interrupt Filter Clock Prescaler Register (IFCPR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 332 Freescale Semiconductor See the “Register Under Protection” appendix for more details. 19.5.3 Register descriptions 19.5.3.1 MCU ID Register #1 (MIDR1) This register holds identification information about the device. Offset: 0x0004 Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PARTNUM[15:0] W Reset 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 16 17 R CSP W Reset 0 0 18 19 20 21 22 23 24 25 26 27 PKG 00 MAJOR_MASK 1101000000 Figure 19-2. MCU ID Register #1 (MIDR1) 28 29 30 31 MINOR_MASK 0000 Table 19-3. MIDR1 field descriptions Field PARTNUM[15:0] CSP PKG Description MCU Part Number, lower 16 bits Device part number of the MCU. 0101_0110_0000_0001:128 KB 0101_0110_0000_0010: 256 KB 0101_0110_0000_0011: 320/384 KB 0101_0110_0000_0100: 512 KB For the full part number this field needs to be combined with MIDR2[PARTNUM[23:16]]. Always reads back 0 Package Settings Can be read by software to determine the package type that is used for the particular device as described below. Any values not explicitly specified are reserved. 0b00001: 64-pin LQFP 0b01001: 100-pin LQFP 0b01101: 144-pin LQFP MAJOR_MASK MINOR_MASK Major Mask Revision Counter starting at 0x0. Incremented each time there is a resynthesis. Minor Mask Revision Counter starting at 0x0. Incremented each time a mask change is done. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 333 19.5.3.2 MCU ID Register #2 (MIDR2) Offset: 0x0008 Access: Read 0 R SF 1 2 3 4 FLASH_SIZE_1 5 6 7 8 FLASH_SIZE_2 9 10 11 12 13 14 15 0000000 W Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PARTNUM[23:16] 0 0 0 EE 0 0 0 0 W Reset 0 1 0 0 0 0 1 0/1 0 0 0 1 01 01 01 0 1 Static bit fixed in hardware Figure 19-3. MCU ID Register #2 (MIDR2) Table 19-4. MIDR2 field descriptions Field Description SF Manufacturer 0 Freescale 1 Reserved FLASH_SIZE_1 Coarse granularity for Flash memory size Total flash memory size = FLASH_SIZE_1 + FLASH_SIZE_2 0011 128 KB 0100 256 KB 0101 512 KB FLASH_SIZE_2 Fine granularity for Flash memory size Total flash memory size = FLASH_SIZE_1 + FLASH_SIZE_2 0000 0 x (FLASH_SIZE_1 / 8) 0010 2 x (FLASH_SIZE_1 / 8) 0100 4 x (FLASH_SIZE_1 / 8) PARTNUM [23:16] MCU Part Number, upper 8 bits containing the ASCII character within the MCU part number 0x42h: Character ‘B’ (Body controller) 0x43h: Character ‘C’ (Gateway) For the full part number this field needs to be combined with MIDR1[PARTNUM[15:0]]. EE Data Flash present 0 No Data Flash is present 1 Data Flash is present 19.5.3.3 Interrupt Status Flag Register (ISR) This register holds the interrupt flags. MPC5604B/C Microcontroller Reference Manual, Rev. 8 334 Freescale Semiconductor Offset: 0x0014 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EIF[15:0]1 W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-4. Interrupt Status Flag Register (ISR) 1 EIF[15:0] in 144-pin LQFP and the 208 MAPBGA packages; EIF[11:0] in 100-pin LQFP package. Field EIF[x] Table 19-5. ISR field descriptions Description External Interrupt Status Flag x This flag can be cleared only by writing a ‘1’. Writing a ‘0’ has no effect. If enabled (IRER[x]), EIF[x] causes an interrupt request. 0 No interrupt event has occurred on the pad 1 An interrupt event as defined by IREER[x] and IFEER[x] has occurred MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 335 19.5.3.4 Interrupt Request Enable Register (IRER) This register is used to enable the interrupt messaging to the interrupt controller. Offset: 0x0018 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IRE[15:0]1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-5. Interrupt Request Enable Register (IRER) 1 IRE[15:0] in 144-pin LQFP and the 208 MAPBGA packages; IRE[11:0] in 100-pin LQFP package. Field IRE[x] Table 19-6. IRER field descriptions Description External Interrupt Request Enable x 0 Interrupt requests from the corresponding ISR[EIF[x]] bit are disabled. 1 Interrupt requests from the corresponding ISR[EIF[x]] bit are enabled. 19.5.3.5 Interrupt Rising-Edge Event Enable Register (IREER) This register is used to enable rising-edge triggered events on the corresponding interrupt pads. Offset:0x0028 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IREE[15:0]1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-6. Interrupt Rising-Edge Event Enable Register (IREER) 1 IREE[15:0] in 144-pin LQFP and 208 MAPBGA packages; IREE[11:0] in 100-pin LQFP package. MPC5604B/C Microcontroller Reference Manual, Rev. 8 336 Freescale Semiconductor Field IREE[x] Table 19-7. IREER field descriptions Description Enable rising-edge events to cause the ISR[EIF[x]] bit to be set. 0 Rising-edge event is disabled 1 Rising-edge event is enabled 19.5.3.6 Interrupt Falling-Edge Event Enable Register (IFEER) This register is used to enable falling-edge triggered events on the corresponding interrupt pads. Offset:0x002C Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IFEE[15:0]1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-7. Interrupt Falling-Edge Event Enable Register (IFEER) 1 IFEE[15:0] in 144-pin LQFP and 208 MAPBGA packages; IFEE[11:0] in 100-pin LQFP package. Table 19-8. IFEER field descriptions Field IFEE[x] Description Enable falling-edge events to cause the ISR[EIF[x]] bit to be set. 0 Falling-edge event is disabled 1 Falling-edge event is enabled NOTE If both the IREER[IREE] and IFEER[IFEE] bits are cleared for the same interrupt source, the interrupt status flag for the corresponding external interrupt will never be set. If IREER[IREE] and IFEER[IFEE] bits are set for the same source the interrupts are triggered by both rising edge events and falling edge events. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 337 19.5.3.7 Interrupt Filter Enable Register (IFER) This register is used to enable a digital filter counter on the corresponding interrupt pads to filter out glitches on the inputs. Offset:0x0030 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IFE[15:0]1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-8. Interrupt Filter Enable Register (IFER) 1 IFE[15:0] in 144-pin LQFP and 208 MAPBGA packages; IFE[11:0] in 100-pin LQFP package. Field IFE[x] Table 19-9. IFER field descriptions Description Enable digital glitch filter on the interrupt pad input 0 Filter is disabled 1 Filter is enabled See the IFMC field descriptions in Table 19-20 for details on how the filter works. 19.5.3.8 Pad Configuration Registers (PCR0–PCR122) The Pad Configuration Registers allow configuration of the static electrical and functional characteristics associated with I/O pads. Each PCR controls the characteristics of a single pad. Please note that input and output peripheral muxing are separate. • For output pads: — Select the appropriate alternate function in Pad Config Register (PCR) — OBE is not required for functions other than GPIO • For INPUT pads: — Select the feature location from PSMI register — Set the IBE bit in the appropriate PCR • For normal GPIO (not alternate function): — Configure PCR — Read from GPDI or write to GPDO MPC5604B/C Microcontroller Reference Manual, Rev. 8 338 Freescale Semiconductor Offsets: Base + 0x0040 (PCR0)(123 registers) Base + 0x0042 (PCR1) ... Base + 0x0130 (PCR122) 0 1 2 3 R0 SMC APC W Reset 0 01 0 0 4 5 6 7 8 0 PA[1:0] OBE IBE 01 0 02 03 0 9 10 11 0 0 ODE 000 Figure 19-9. Pad Configuration Registers (PCRx) 1 SMC and PA[1] are ‘1’ for JTAG pads 2 OBE is ‘1’ for TDO 3 IBE and WPE are ‘1’ for TCK, TMS, TDI, FAB and ABS 4 WPS is ‘0’ for input only pad with analog feature and FAB Access: User read/write 12 13 14 15 0 SRC WPE WPS 0 0 03 14 NOTE 16/32-bit access is supported. In addition to the bit map above, the following Table 19-11 describes the PCR depending on the pad type (pad types are defined in the “Pad types” section of this reference manual). The bits in shaded fields are not implemented for the particular I/O type. The PA field selecting the number of alternate functions may or may not be present depending on the number of alternate functions actually mapped on the pad. Table 19-10. PCR bit implementation by pad type Pad type 0123 S, M, F (Pad with GPIO and digital alternate function) J (Pad with GPIO and analog functionality ) I (Pad dedicated to ADC) SM APC C SM APC C SM APC C PCR bit No. 45678 PA[1:0] OBE IBE 9 10 11 12 13 14 15 OD SRC WP WP E ES PA[1:0] OBE IBE OD SRC WP WP E ES PA[1:0] OBE IBE OD SRC WP WP E ES MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 339 Field SMC APC PA[1:0] OBE IBE ODE SRC WPE WPS Table 19-11. PCRx field descriptions Description Safe Mode Control. This bit supports the overriding of the automatic deactivation of the output buffer of the associated pad upon entering SAFE mode of the device. 0 In SAFE mode, the output buffer of the pad is disabled. 1 In SAFE mode, the output buffer remains functional. Analog Pad Control. This bit enables the usage of the pad as analog input. 0 Analog input path from the pad is gated and cannot be used 1 Analog input path switch can be enabled by the ADC Pad Output Assignment This field is used to select the function that is allowed to drive the output of a multiplexed pad. 00 Alternative Mode 0 — GPIO 01 Alternative Mode 1 — See the signal description chapter 10 Alternative Mode 2 — See the signal description chapter 11 Alternative Mode 3 — See the signal description chapter Note: Number of bits depends on the actual number of actual alternate functions. Please see data sheet. Output Buffer Enable This bit enables the output buffer of the pad in case the pad is in GPIO mode. 0 Output buffer of the pad is disabled when PA[1:0] = 00 1 Output buffer of the pad is enabled when PA[1:0] = 00 Input Buffer Enable This bit enables the input buffer of the pad. 0 Input buffer of the pad is disabled 1 Input buffer of the pad is enabled Open Drain Output Enable This bit controls output driver configuration for the pads connected to this signal. Either open drain or push/pull driver configurations can be selected. This feature applies to output pads only. 0 Pad configured for push/pull output 1 Pad configured for open drain Slew Rate Control This field controls the slew rate of the associated pad when it is slew rate selectable. Its usage is the following: 0 Pad configured as slow (default) 1 Pad is configured as medium or fast (depending on the pad) Note: PC[1] (TDO pad) is medium only. By default SRC = 0, and writing ‘1’ has no effect. Weak Pull Up/Down Enable This bit controls whether the weak pull up/down devices are enabled/disabled for the pad connected to this signal. 0 Weak pull device disabled for the pad 1 Weak pull device enabled for the pad Weak Pull Up/Down Select This bit controls whether weak pull up or weak pull down devices are used for the pads connected to this signal when weak pull up/down devices are enabled. 0 Weak pull-down selected 1 Weak pull-up selected MPC5604B/C Microcontroller Reference Manual, Rev. 8 340 Freescale Semiconductor 19.5.3.9 Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI28_31) In some cases, a peripheral input signal can be selected from more than one pin. For example, the CAN1_RXD signal can be selected on three different pins: PC[3], PC[11] and PF[15]. Only one can be active at a time. To select the pad to be used as input to the peripheral: • Select the signal via the pad’s PCR register using the PA field. • Specify the pad to be used via the appropriate PSMI field. Offsets:0x0500–0x051C (8 registers) Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 W PADSEL0 0000 PADSEL1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 R0 W Reset 0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 000 PADSEL2 0000 PADSEL3 000000000000000 Figure 19-10. Pad Selection for Multiplexed Inputs Register (PSMI0_3) Table 19-12. PSMI0_3 field descriptions Field Description PADSEL0–3, PADSEL4–7, ... PADSEL28–31 Pad Selection Bits Each PADSEL field selects the pad currently used for a certain input function. See Table 19-13. In order to multiplex different pads to the same peripheral input, the SIUL provides a register that controls the selection between the different sources. Table 19-13. Peripheral input pin selection PSMI registers PADSEL fields SIUL address offset Function / Peripheral Mapping1 PSMI0_3 PADSEL0 0x500 PADSEL1 PADSEL23 0x501 0x502 PADSEL34 0x503 CAN1RX / FlexCAN_1 00: PCR[35] 01: PCR[43] 10: PCR[95]2 CAN2RX / FlexCAN_2 00: PCR[73] 01: PCR[89]2 CAN3RX / FlexCAN_3 00: PCR[36] 01: PCR[73] 10: PCR[89]2 CAN4RX / FlexCAN_4 00: PCR[35] 01: PCR[43] 10: PCR[95]2 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 341 Table 19-13. Peripheral input pin selection (continued) PSMI registers PADSEL fields SIUL address offset Function / Peripheral Mapping1 PSMI4_7 PADSEL44 0x504 CAN5RX / FlexCAN_5 00: PCR[64] 01: PCR[97]2 PADSEL5 0x505 SCK_0 / DSPI_0 00: PCR[14] 01: PCR[15] PADSEL6 0x506 CS0_0 / DSPI_0 00: PCR[14] 01: PCR[15] 10: PCR[27] PADSEL7 0x507 SCK_1 / DSPI_1 00: PCR[34] 01: PCR[68] 10: PCR[114]2 PSMI8_11 PADSEL8 0x508 SIN_1 / DSPI_1 00: PCR[36] 01: PCR[66] 10: PCR[112]2 PADSEL9 0x509 CS0_1 / DSPI_1 00: PCR[435] 01: PCR[61] 10: PCR[69] 11: PCR[115]2 PADSEL10 0x50A SCK_2 / DSPI_2 00: PCR[46] 01: PCR[78]2 10: PCR[105]2 PADSEL11 0x50B SIN_2 / DSPI_2 00: PCR[44] 01: PCR[76] PSMI12_15 PADSEL12 0x50C CS0_2 / DSPI_2 00: PCR[47] 01: PCR[79]2 10: PCR[82]2 11: PCR[104]2 PADSEL13 0x50D E1UC[3] / eMIOS_0 00: PCR[3] 01: PCR[27] PADSEL14 0x50E E0UC[4] / eMIOS_0 00: PCR[4] 01: PCR[28] PADSEL15 0x50F E0UC[5] / eMIOS_0 00: PCR[5] 01: PCR[29] PSMI16_19 PADSEL16 0x510 E0UC[6] / eMIOS_0 00: PCR[6] 01: PCR[30] PADSEL17 0x511 E0UC[7] / eMIOS_0 00: PCR[7] 01: PCR[31] PADSEL18 0x512 E0UC[10] / eMIOS_0 00: PCR[10] 01: PCR[80]2 PADSEL19 0x513 E0UC[11] / eMIOS_0 00: PCR[11] 01: PCR[81]2 MPC5604B/C Microcontroller Reference Manual, Rev. 8 342 Freescale Semiconductor Table 19-13. Peripheral input pin selection (continued) PSMI registers PADSEL fields SIUL address offset Function / Peripheral Mapping1 PSMI20_23 PADSEL20 0x514 E0UC[12] / eMIOS_0 00: PCR[44] 01: PCR[82]2 PADSEL21 0x515 E0UC[13] / eMIOS_0 00: PCR[45] 01: PCR[83]2 PADSEL22 0x516 E0UC[14] / eMIOS_0 00: PCR[46] 01: PCR[84]2 PADSEL23 0x517 E0UC[22] / eMIOS_0 00: PCR[70] 01: PCR[72] 10: PCR[85]2 PSMI24_27 PADSEL24 0x518 PSMI28_31 PADSEL255 0x519 PADSEL265 0x51A PADSEL275 0x51B PADSEL285 0x51C E0UC[23] / eMIOS_0 E0UC[24] / eMIOS_0 E0UC[25] / eMIOS_0 E0UC[26] / eMIOS_0 E0UC[27] / eMIOS_0 00: PCR[71] 01: PCR[73] 10: PCR[86]2 00: PCR[60] 01: PCR[106]2 00: PCR[61] 01: PCR[107]2 00: PCR[62] 01: PCR[108]2 00: PCR[63] 01: PCR[109]2 PADSEL29 0x51D SCL / f_0 00: PCR[11] 01: PCR[19] PADSEL30 0x51E SDA / I2C__0 00: PCR[10] 01: PCR[18] PADSEL31 0x51F LIN3RX / LINFlex_3 00: PCR[8] 01: PCR[75] 1 See the signal description chapter of this reference manual for correspondence between PCR and pinout 2 Not available in 100-pin LQFP 3 Not available on MPC5603B devices 4 Available only on MPC5604B 208 MAPBGA devices 5 Not available on MPC5602B and MPC5603B 100-pin devices 19.5.3.10 GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123) These registers are used to set or clear GPIO pads. Each pad data out bit can be controlled separately with a byte access. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 343 Offsets: 0x0600–0x0678 (31 registers) Access: User read/write PDO[1] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0000000 PDO[0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO[3] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0000000 PDO[2] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-11. Port GPIO Pad Data Output Register 0–3 (GPDO0_3) Table 19-14. GPDO0_3 field descriptions Field PDO[x] Description Pad Data Out This bit stores the data to be driven out on the external GPIO pad controlled by this register. 0 Logic low value is driven on the corresponding GPIO pad when the pad is configured as an output 1 Logic high value is driven on the corresponding GPIO pad when the pad is configured as an output CAUTION Toggling several IOs at the same time can significantly increase the current in a pad group. Caution must be taken to avoid exceeding maximum current thresholds. Please see data sheet. 19.5.3.11 GPIO Pad Data Input Registers (GPDI0_3–GPDI120_123) These registers are used to read the GPIO pad data with a byte access. MPC5604B/C Microcontroller Reference Manual, Rev. 8 344 Freescale Semiconductor Offsets: 0x0800–0x0878 (31 registers) Access: User read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0000000 PDI[1] PDI[0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDI[3] PDI[2] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0000000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-12. Port GPIO Pad Data Input Register 0–3 (GPDI0_3) Table 19-15. GPDI0_3 field descriptions Field PDI[x] Description Pad Data In This bit stores the value of the external GPIO pad associated with this register. 0 Value of the data in signal for the corresponding GPIO pad is logic low 1 Value of the data in signal for the corresponding GPIO pad is logic high 19.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3) MPC5604B devices ports are constructed such that they contain 16 GPIO pins, for example PortA[0..15]. Parallel port registers for input (PGPDI) and output (PGPDO) are provided to allow a complete port to be written or read in one operation, dependent on the individual pad configuration. Writing a parallel PGPDO register directly sets the associated GPDO register bits. There is also a masked parallel port output register allowing the user to determine which pins within a port are written. While very convenient and fast, this approach does have implications regarding current consumption for the device power segment containing the port GPIO pads. Toggling several GPIO pins simultaneously can significantly increase current consumption. CAUTION Caution must be taken to avoid exceeding maximum current thresholds when toggling multiple GPIO pins simultaneously. Please see data sheet. Table 19-16 shows the locations and structure of the PGPDOx registers. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 345 Offset1 Register Table 19-16. PGPDO0 – PGPDO3 register map Field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0C00 PGPDO0 Port A Port B 0x0C04 PGPDO1 Port C Port D 0x0C08 PGPDO2 Port E Port F 0x0C0C PGPDO3 Port G Port H 1 SIU base address is 0xC3F9_0000. To calculate register address add offset to base address It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of the parallel port register corresponds to the least significant pin in the port. For example in Table 19-16, the PGPDO0 register contains fields for Port A and Port B. • Bit 0 is mapped to Port A[0], bit 1 is mapped to Port A[1] and so on, through bit 15, which is mapped to Port A[15] • Bit 16 is mapped to Port B[0], bit 17 is mapped to Port B[1] and so on, through bit 31, which is mapped to Port B[15]. 19.5.3.13 Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI3) The SIU_PGPDI registers are similar in operation to the PGPDIO registers, described in the previous section (Section 19.5.3.12, “Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3)) but they are used to read port pins simultaneously. NOTE The port pins to be read need to be configured as inputs but even if a single pin within a port has IBE set, then you can still read that pin using the parallel port register. However, this does mean you need to be very careful. Reads of PGPDI registers are equivalent to reading the corresponding GPDI registers but significantly faster since as many as two ports can be read simultaneously with a single 32-bit read operation. Table 19-17 shows the locations and structure of the PGPDIx registers. Each 32-bit PGPDIx register contains two 16-bit fields, each field containing the values for a separate port. Table 19-17. PGPDI0 – PGPDI3 register map Offset1 Register Field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0C40 PGPDI0 0x0C44 PGPDI1 0x0C48 PGPDI2 0x0C4C PGPDI3 Port A Port C Port E Port G Port B Port D Port F Port H MPC5604B/C Microcontroller Reference Manual, Rev. 8 346 Freescale Semiconductor 1 SIU base address is 0xC3F9_0000. To calculate register address add offset to base address It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of the parallel port register corresponds to the least significant pin in the port. For example in Table 19-17, the PGPDI0 register contains fields for Port A and Port B. • Bit 0 is mapped to Port A[0], bit 1 is mapped to Port A[1] and so on, through bit 15, which is mapped to Port A[15] • Bit 16 is mapped to Port B[0], bit 17 is mapped to Port B[1] and so on, through bit 31, which is mapped to Port B[15]. 19.5.3.14 Masked Parallel GPIO Pad Data Out Register (MPGPDO0–MPGPDO7) The MPGPDOx registers are similar in operation to the PGPDOx ports described in Section 19.5.3.12, “Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3), but with two significant differences: • The MPGPDOx registers support masked port-wide changes to the data out on the pads of the respective port. Masking effectively allows selective bitwise writes to the full 16-bit port. • Each 32-bit MPGPDOx register is associated to only one port. NOTE The MPGPDOx registers may only be accessed with 32-bit writes. 8-bit or 16-bit writes will not modify any bits in the register and will cause a transfer error response by the module. Read accesses return ‘0’. Table 19-18 shows the locations and structure of the MPGPDOx registers. Each 32-bit MPGPDOx register contains two 16-bit fields (MASKx and MPPDOx). The MASK field is a bitwise mask for its associated port. The MPPDO0 field contains the data to be written to the port. Table 19-18. MPGPDO0 – MPGPDO7 register map Offset1 Register Field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0C80 MPGPDO0 MASK0 (Port A) MPPDO0 (Port A) 0x0C84 MPGPDO1 MASK1 (Port B) MPPDO1 (Port B) 0x0C88 MPGPDO2 MASK2 (Port C) MPPDO2 (Port C) 0x0C8C MPGPDO3 MASK3 (Port D) MPPDO3 (Port D) 0x0C90 MPGPDO4 MASK4 (Port E) MPPDO4 (Port E) 0x0C94 MPGPDO5 MASK5 (Port F) MPPDO5 (Port F) 0x0C98 MPGPDO6 MASK6 (Port G) MPPDO6 (Port G) 0x0C9C MPGPDO7 MASK7 (Port H) MPPDO7 (Port H) 1 SIU base address is 0xC3F9_0000. To calculate register address add offset to base address It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of the parallel port register corresponds to the least significant pin in the port. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 347 For example in Table 19-18, the MPGPDO0 register contains field MASK0, which is the bitwise mask for Port A and field MPPDO0, which contains data to be written to Port A. • MPGPDO0[0] is the mask bit for Port A[0], MPGPDO0[1] is the mask bit for Port A[1] and so on, through MPGPDO0[15], which is the mask bit for Port A[15] • MPGPDO0[16] is the data bit mapped to Port A[0], MPGPDO0[17] is mapped to Port A[1] and so on, through MPGPDO0[31], which is mapped to Port A[15]. Table 19-19. MPGPDO0..MPGPDO7 field descriptions Field MASKx [15:0] MPPDOx [15:0] Description Mask Field Each bit corresponds to one data bit in the MPPDOx register at the same bit location. 0 Associated bit value in the MPPDOxfield is ignored 1 Associated bit value in the MPPDOx field is written Masked Parallel Pad Data Out Write the data register that stores the value to be driven on the pad in output mode. Accesses to this register location are coherent with accesses to the bitwise GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123). The x and bit index define which MPPDO register bit is equivalent to which PDO register bit according to the following equation: MPPDO[x][y] = PDO[(x*16)+y] CAUTION Toggling several IOs at the same time can significantly increase the current in a pad group. Caution must be taken to avoid exceeding maximum current thresholds. Please see data sheet. 19.5.3.15 Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15) These registers are used to configure the filter counter associated with each digital glitch filter. NOTE For the pad transition to trigger an interrupt it must be steady for at least the filter period. MPC5604B/C Microcontroller Reference Manual, Rev. 8 348 Freescale Semiconductor Offset: 0x1000–0x103C) (16 registers) Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 W MAXCNTx Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-13. Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15) Table 19-20. IFMC field descriptions Field MAXCNTx Description Maximum Interrupt Filter Counter setting Filter Period = T(CK)*MAXCNTx + n*T(CK) Where (n can be 1 to 3) MAXCNTx can be 0 to 15 T(CK): Prescaled Filter Clock Period, which is FIRC clock prescaled to IFCP value T(FIRC): Basic Filter Clock Period: 62.5 ns (fFIRC = 16 MHz) 19.5.3.16 Interrupt Filter Clock Prescaler Register (IFCPR) This register is used to configure a clock prescaler which is used to select the clock for all digital filter counters in the SIUL. Offsets:0x1080 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 W IFCP Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-14. Interrupt Filter Clock Prescaler Register (IFCPR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 349 Field IFCP Table 19-21. IFCPR field descriptions Description Interrupt Filter Clock Prescaler setting Prescaled Filter Clock Period = T(FIRC) x (IFCP + 1) T(FIRC) is the fast internal RC oscillator period. IFCP can be 0 to 15. 19.6 Functional description 19.6.1 Pad control The SIUL controls the configuration and electrical characteristic of the device pads. It provides a consistent interface for all pads, both on a by-port and a by-bit basis. The pad configuration registers (PCRn, see Section 19.5.3.8, “Pad Configuration Registers (PCR0–PCR122)) allow software control of the static electrical characteristics of external pins with a single write. These are used to configure the following pad features: • Open drain output enable • Slew rate control • Pull control • Pad assignment • Control of analog path switches • Safe mode behavior configuration 19.6.2 General purpose input and output pads (GPIO) The SIUL manages up to 123 GPIO pads organized as ports that can be accessed for data reads and writes as 32, 16 or 8-bit1. NOTE Ports are organized as groups of 16 GPIO pads, with the exception of Port J, which has 5. A 32-bit R/W operation accesses two ports simultaneously. A 16-bit operation accesses a full port and an 8-bit access either the upper or lower byte of a port. As shown in Figure 19-15, all port accesses are identical with each read or write being performed only at a different location to access a different port width. 1.There are exceptions. Some pads, e.g., precision analog pads, are input only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 350 Freescale Semiconductor 31 SIUL Base+ 0x0C00 23 15 7 0 32-bit Access (2 ports) 15 7 0 SIUL Base+ 0x0C02 16-bit Access (full port) 15 7 0 SIUL Base+ 0x0C00 16-bit Access (full port) 7 0 7 0 SIUL Base+ 0x0C03 8-bit Access (half port) SIUL Base+ 0x0C02 8-bit Access (half port) 7 0 SIUL Base+ 0x0C01 8-bit Access (half port) 7 0 SIUL Base+ 0x0C00 8-bit Access (half port) Figure 19-15. Data Port example arrangement showing configuration for different port width accesses The SIUL has separate data input (GPDIn_n, see Section 19.5.3.11, “GPIO Pad Data Input Registers (GPDI0_3–GPDI120_123)) and data output (GPDOn_n, see Section 19.5.3.10, “GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123)) registers for all pads, allowing the possibility of reading back an input or output value of a pad directly. This supports the ability to validate what is present on the pad rather than simply confirming the value that was written to the data register by accessing the data input registers. Data output registers allow an output pad to be driven high or low (with the option of push-pull or open drain drive). Input registers are read-only and reflect the respective pad value. When the pad is configured to use one of its alternate functions, the data input value reflects the respective value of the pad. If a write operation is performed to the data output register for a pad configured as an alternate function (non-GPIO), this write will not be reflected by the pad value until reconfigured to GPIO. The allocation of what input function is connected to the pin is defined by the PSMI registers (PCRn, see Section 19.5.3.9, “Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI28_31)).” 19.6.3 External interrupts The SIUL supports 16 external interrupts, EIRQ0–EIRQ15. In the signal description chapter of this reference manual, mapping is shown for external interrupts to pads. The SIUL supports twointerrupt vectors to the interrupt controller. Each vector interrupt has eight external interrupts combined together with the presence of flag generating an interrupt for that vector if enabled. All of the external interrupt pads within a single group have equal priority. See Figure 19-16 for an overview of the external interrupt implementation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 351 Interrupt Controller Interrupt Vectors IRQ_15_081 IRQ_07_00 OR OR Interrupt enable IRE[15:0]1 Glitch filter Prescaler IFCP[3:0] Glitch filter Counter_n MAXCOUNT[x] IRQ Glitch Filter enable IFE[15:0]1 EIF[15:8]1 EIF[7:0] Edge Detection Glitch Filter Interrupt Edge Enable Rising IREE[15:0]1 Falling IFEE[15:0]1 Pads Figure 19-16. External interrupt pad diagram 1 This value is valid in the 144-pin LQFP and the 208-pin packages, while there are 12 interrupts in the 100-pin LQFP packages Each interrupt can be enabled or disabled independently. This can be performed using the IRER. A pad defined as an external interrupt can be configured to recognize interrupts with an active rising edge, an active falling edge or both edges being active. A setting of having both edge events disabled is reserved and should not be configured. The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER. Each external interrupt supports an individual flag which is held in the Interrupt Status Flag Register (ISR). The bits in the ISR[EIF] field are cleared by writing a ‘1’ to them; this prevents inadvertent overwriting of other flags in the register. 19.7 Pin muxing For pin muxing, please see the signal description chapter of this reference manual. MPC5604B/C Microcontroller Reference Manual, Rev. 8 352 Freescale Semiconductor ——— Communication modules ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 353 MPC5604B/C Microcontroller Reference Manual, Rev. 8 354 Freescale Semiconductor Chapter 20 Inter-Integrated Circuit Bus Controller Module (I2C) 20.1 Introduction 20.1.1 Overview The Inter-Integrated Circuit (I2C™ or IIC) bus is a two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices. It minimizes the number of external connections to devices and does not require an external address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for further expansion and system development. The interface is designed to operate up to 100 kbps in Standard Mode and 400 Kbps in Fast Mode. The device is capable of operating at higher baud rates, up to a maximum of module clock/20 with reduced bus loading. Actual baud rate can be less than the programmed baud rate and is dependent on the SCL rise time. SCL rise time is dependent on the external pullup resistor value and bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. 20.1.2 Features The I2C module has the following key features: • Compatible with I2C Bus standard • Multi-master operation • Software programmable for one of 256 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection Features currently not supported: • No support for general call address • Not compliant to ten-bit addressing MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 355 20.1.3 Block diagram The block diagram of the I2C module is shown in Figure 20-1. I2C Registers Start Stop Arbitration Control Interrupt bus_clock Clock Control In/Out Data Shift Register SCL SDA Address Compare Figure 20-1. I2C block diagram 20.2 External signal description The Inter-Integrated Circuit (I2C) module has two external pins, SCL and SDA. 20.2.1 SCL This is the bidirectional Serial Clock Line (SCL) of the module, compatible with the I2C-Bus specification. 20.2.2 SDA This is the bidirectional Serial Data line (SDA) of the module, compatible with the I2C-Bus specification. 20.3 Memory map and register description 20.3.1 Module memory map The memory map for the I2C module is given below in Table 20-1. The total address for each register is the sum of the base address for the I2C module and the address offset for each register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 356 Freescale Semiconductor Address offset 0x0 0x1 0x2 0x3 0x4 0x5 Table 20-1. I2C memory map Base address: 0xFFE3_0000 Register I2C Bus Address Register (IBAD) I2C Bus Frequency Divider Register (IBFD) I2C Bus Control Register (IBCR) I2C Bus Status Register (IBSR) I2C Bus Data I/O Register (IBDR) I2C Bus Interrupt Config Register (IBIC) Location on page 357 on page 358 on page 364 on page 365 on page 366 on page 367 All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the IBDF register for the frequency divider is accessible by a 16-bit read/write to address Base + 0x000, but performing a 16-bit access to Base + 0x001 is illegal. 20.3.2 I2C Bus Address Register (IBAD) This register contains the address the I2C bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. Offset 0x0 7 R W Reset 0 Access: Read/write any time 6 5 4 3 2 1 0 0 ADR 0 0 0 0 0 0 0 Figure 20-2. I2C Bus Address Register (IBAD) Table 20-2. IBAD field descriptions Field ADR Description Slave Address. Specific slave address to be used by the I2C Bus module. Note: The default mode of I2C Bus is slave mode for an address match on the bus. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 357 20.3.3 I2C Bus Frequency Divider Register (IBFD) Offset 0x1 Access: Read/write any time 7 6 5 4 3 2 1 0 R IBC W Reset 0 0 0 0 0 0 0 0 Figure 20-3. I2C Bus Frequency Divider Register (IBFD) Table 20-3. IBFD field descriptions Field IBC Description I-Bus Clock Rate. This field is used to prescale the clock for bit rate selection. The bit clock generator is implemented as a prescale divider. The IBC bits are decoded to give the Tap and Prescale values as follows: 7–6 select the prescaled shift register (see Table 20-4) 5–3 select the prescaler divider (see Table 20-5) 2–0 select the shift register tap point (see Table 20-6) IBC7–6 00 01 10 11 Table 20-4. I-Bus multiplier factor MUL 01 02 04 RESERVED IBC5–3 000 001 010 011 100 101 110 111 Table 20-5. I-Bus prescaler divider values scl2start (clocks) 2 2 2 6 14 30 62 126 scl2stop (clocks) 7 7 9 9 17 33 65 129 scl2tap (clocks) 4 4 6 6 14 30 62 126 tap2tap (clocks) 1 2 4 8 16 32 64 128 MPC5604B/C Microcontroller Reference Manual, Rev. 8 358 Freescale Semiconductor Table 20-6. I-Bus tap and prescale values IBC2-0 000 001 010 011 100 101 110 111 SCL Tap (clocks) 5 6 7 8 9 10 12 15 SDA Tap (clocks) 1 1 2 2 3 3 4 4 The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Table 20-5. All subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Table 20-5. The SCL Tap is used to generate the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to the change of state of SDA i.e. the SDA hold time. SCL Divider SCL SDA SDA Hold Figure 20-4. SDA hold time MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 359 SDA SCL SCL Hold(start) SCL Hold(stop) START condition STOP condition Figure 20-5. SCL divider and SDA hold The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} Eqn. 20-1 The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 20-7. The equation used to generate the SDA Hold value from the IBFD bits is: SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3} Eqn. 20-2 The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap] Eqn. 20-3 SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap] Eqn. 20-4 MPC5604B/C Microcontroller Reference Manual, Rev. 8 360 Freescale Semiconductor IBC7–0 (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Table 20-7. I2C divider and hold values SCL divider (clocks) 20 22 24 26 28 30 34 40 28 32 36 40 44 48 56 68 48 56 64 72 80 88 104 128 80 96 112 128 144 160 192 240 160 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 SDA hold (clocks) 7 7 8 8 9 9 10 10 7 7 9 9 11 11 13 13 9 9 13 13 17 17 21 21 9 9 17 17 25 25 33 33 17 17 33 33 49 49 65 65 33 33 65 65 97 97 129 129 65 65 129 129 193 193 257 257 129 129 257 257 385 385 513 513 SCL hold (start) 6 7 8 9 10 11 13 16 10 12 14 16 18 20 24 30 18 22 26 30 34 38 46 58 38 46 54 62 70 78 94 118 78 94 110 126 142 158 190 238 158 190 222 254 286 318 382 478 318 382 446 510 574 638 766 958 638 766 894 1022 1150 1278 1534 1918 MUL = 1 Freescale Semiconductor MPC5604B/C Microcontroller Reference Manual, Rev. 8 SCL hold (stop) 11 12 13 14 15 16 18 21 15 17 19 21 23 25 29 35 25 29 33 37 41 45 53 65 41 49 57 65 73 81 97 121 81 97 113 129 145 161 193 241 161 193 225 257 289 321 385 481 321 385 449 513 577 641 769 961 641 769 897 1025 1153 1281 1537 1921 361 362 MUL = 2 IBC7–0 (hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Table 20-7. I2C divider and hold values (continued) SCL divider (clocks) 40 44 48 52 56 60 68 80 56 64 72 80 88 96 112 136 96 112 128 144 160 176 208 256 160 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 3584 4096 4608 5120 6144 7680 SDA hold (clocks) 14 14 16 16 18 18 20 20 14 14 18 18 22 22 26 26 18 18 26 26 34 34 42 42 18 18 34 34 50 50 66 66 28 28 32 32 36 36 40 40 28 28 36 36 44 44 52 52 36 36 52 52 68 68 84 84 36 36 68 68 100 100 132 132 SCL hold (start) 12 14 16 18 20 22 26 32 20 24 28 32 36 40 48 60 36 44 52 60 68 76 92 116 76 92 108 124 140 156 188 236 156 188 220 252 284 316 380 476 316 380 444 508 572 636 764 956 636 764 892 1020 1148 1276 1532 1916 1276 1532 1788 2044 2300 2556 3068 3836 SCL hold (stop) 22 24 26 28 30 32 36 42 30 34 38 42 46 50 58 70 50 58 66 74 82 90 106 130 82 98 114 130 146 162 194 242 162 194 226 258 290 322 386 482 322 386 450 514 578 642 770 962 642 770 898 1026 1154 1282 1538 1922 1282 1538 1794 2050 2306 2562 3074 3842 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor IBC7–0 (hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF 30 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Table 20-7. I2C divider and hold values (continued) SCL divider (clocks) 80 88 96 104 112 120 136 160 112 128 144 160 176 192 224 272 192 224 256 288 320 352 416 512 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 3584 4096 4608 5120 6144 7680 5120 6144 7168 8192 9216 10240 12288 15360 SDA hold (clocks) 28 28 32 32 36 36 40 40 28 28 36 36 44 44 52 52 36 36 52 52 68 68 84 84 36 36 68 68 100 100 132 132 68 68 132 132 196 196 260 260 132 132 260 260 388 388 516 516 260 260 516 516 772 772 1028 1028 516 516 1028 1028 1540 1540 2052 2052 SCL hold (start) 24 28 32 36 40 44 52 64 40 48 56 64 72 80 96 120 72 88 104 120 136 152 184 232 152 184 216 248 280 312 376 472 312 376 440 504 568 632 760 952 632 760 888 1016 1144 1272 1528 1912 1272 1528 1784 2040 2296 2552 3064 3832 2552 3064 3576 4088 4600 5112 6136 7672 MUL = 4 Freescale Semiconductor MPC5604B/C Microcontroller Reference Manual, Rev. 8 SCL hold (stop) 44 48 52 56 60 64 72 84 60 68 76 84 92 100 116 140 100 116 132 148 164 180 212 260 164 196 228 260 292 324 388 484 324 388 452 516 580 644 772 964 644 772 900 1028 1156 1284 1540 1924 1284 1540 1796 2052 2308 2564 3076 3844 2564 3076 3588 4100 4612 5124 6148 7684 363 20.3.4 I2C Bus Control Register (IBCR) Offset 0x2 Access: Read/write any time 7 6 5 4 3 2 1 0 R 0 0 MDIS IBIE MSSL TXRX NOACK DMAEN W RSTA Reset 1 0 0 0 0 0 0 0 Figure 20-6. I2C Bus Control Register (IBCR) Table 20-8. IBCR field descriptions Field Description MDIS Module disable. This bit controls the software reset of the entire I2C Bus module. 1 The module is reset and disabled. This is the power-on reset situation. When high, the interface is held in reset, but registers can still be accessed. Status register bits (IBSR) are not valid when module is disabled. 0 The I2C Bus module is enabled. This bit must be cleared before any other IBCR bits have any effect Note: If the I2C Bus module is enabled in the middle of a byte transfer, the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. This would ultimately result in either the current bus master or the I2C Bus module losing arbitration, after which, bus operation would return to normal. IBIE I-Bus Interrupt Enable. 1 Interrupts from the I2C Bus module are enabled. An I2C Bus interrupt occurs provided the IBIF bit in the status register is also set. 0 Interrupts from the I2C Bus module are disabled. Note that this does not clear any currently pending interrupt condition MSSL Master/Slave mode select. Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operation mode changes from master to slave. A STOP signal should be generated only if the IBIF flag is set. MSSL is cleared without generating a STOP signal when the master loses arbitration. 1 Master Mode 0 Slave Mode TXRX Transmit/Receive mode select. This bit selects the direction of master and slave transfers. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high. 1 Transmit 0 Receive NOACK Data Acknowledge disable. This bit specifies the value driven onto SDA during data acknowledge cycles for both master and slave receivers. The I2C module will always acknowledge address matches, provided it is enabled, regardless of the value of NOACK. Note that values written to this bit are only used when the I2C Bus is a receiver, not a transmitter. 1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) 0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data MPC5604B/C Microcontroller Reference Manual, Rev. 8 364 Freescale Semiconductor Table 20-8. IBCR field descriptions (continued) Field Description RSTA DMAEN Repeat Start. Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 Generate repeat start cycle 0 No effect DMA Enable. When this bit is set, the DMA TX and RX lines will be asserted when the I2C module requires data to be read or written to the data register. No Transfer Done interrupts will be generated when this bit is set, however an interrupt will be generated if the loss of arbitration or addressed as slave conditions occur. The DMA mode is only valid when the I2C module is configured as a Master and the DMA transfer still requires CPU intervention at the start and the end of each frame of data. See the DMA Application Information section for more details. 1 Enable the DMA TX/RX request signals 0 Disable the DMA TX/RX request signals 20.3.5 I2C Bus Status Register (IBSR) Offset 0x3 Access: Read-write 7 R TCF W Reset 1 6 5 4 3 2 IAAS IBB IBAL 0 SRW w1c 0 0 0 0 0 Figure 20-7. I2C Bus Status Register (IBSR) 1 0 IBIF RXAK w1c 0 0 Table 20-9. IBSR Field Descriptions Field TCF IAAS IBB Description Transfer complete. While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the I2C module or from the I2C module. 1 Transfer complete 0 Transfer in progress Addressed as a slave. When its own specific address (I-Bus Address Register) is matched with the calling address, this bit is set. The CPU is interrupted provided the IBIE is set. Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly. Writing to the I-Bus Control Register clears this bit. 1 Addressed as a slave 0 Not addressed Bus busy. This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is detected, IBB is cleared and the bus enters idle state. 1 Bus is busy 0 Bus is Idle MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 365 Table 20-9. IBSR Field Descriptions (continued) Field IBAL SRW IBIF RXAK Description Arbitration Lost. The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration is lost in the following circumstances: • SDA is sampled low when the master drives a high during an address or data transmit cycle. • SDA is sampled low when the master drives a high during the acknowledge bit of a data receive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. Slave Read/Write. When IAAS is set, this bit indicates the value of the R/W command bit of the calling address sent from the master. This bit is only valid when the I-Bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. By programming this bit, the CPU can select slave transmit/receive mode according to the command of the master. 1 Slave transmit, master reading from slave 0 Slave receive, master writing to slave I-Bus Interrupt Flag. The IBIF bit is set when one of the following conditions occurs: • Arbitration lost (IBAL bit set) • Byte transfer complete (TCF bit set - Check w/ design if this is the case (only TCF)) • Addressed as slave (IAAS bit set) • NoAck from Slave (MS & Tx bits set) • I2C Bus going idle (IBB high-low transition and enabled by BIIE) A processor interrupt request will be caused if the IBIE bit is set. Received Acknowledge. This is the value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock. This bit is valid only after transfer is complete. 1 No acknowledge received 0 Acknowledge received 20.3.6 I2C Bus Data I/O Register (IBDR) Offset 0x4 Access: Read/write any time 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 Figure 20-8. I2C Bus Data I/O Register (IBDR) In master transmit mode, when data is written to IBDR, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave mode, the same functions are available after an address match has occurred. Note that the IBCR[TXRX] field must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the I2C is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. MPC5604B/C Microcontroller Reference Manual, Rev. 8 366 Freescale Semiconductor Reading the IBDR will return the last byte received while the I2C is configured in either master receive or slave receive modes. The IBDR does not reflect every byte that is transmitted on the I2C bus, nor can software verify that a byte has been written to the IBDR correctly by reading it back. In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should comprise the calling address (in position D7–D1) concatenated with the required R/W bit (in position D0). 20.3.7 I2C Bus Interrupt Config Register (IBIC) Offset 0x5 Access: Read/write any time 7 6 5 4 3 2 1 0 R BIIE1 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 20-9. I2C Bus Interrupt Config Register (IBIC) 1 This bit cannot be set in reset state, when I2C is in slave mode. It can be set to 1 only when I2C is in Master mode. This information is missing from the spec. Table 20-10. IBIC field descriptions Field BIIE Description Bus Idle Interrupt Enable bit. This config bit can be used to enable the generation of an interrupt once the I2C bus becomes idle. Once this bit is set, an IBB high-low transition will set the IBIF bit. This feature can be used to signal to the CPU the completion of a STOP on the I2C bus. 1 Bus Idle Interrupts enabled 0 Bus Idle Interrupts disabled 20.4 Functional description 20.4.1 I-Bus protocol The I2C Bus system uses a Serial Data line (SDA) and a Serial Clock Line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logical AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 20-10. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 367 MSB LSB SCL 1 2 34 5 6 78 9 MSB LSB 1 2 34 5 6 78 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 Start Signal Calling Address Read/ Ack Write Bit MSB LSB SCL 1 2 34 5 67 89 Data Byte No Stop Ack Signal Bit MSB LSB 1 234 5 678 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal Calling Address Read/ Ack Write Bit Repeated Start Signal New Calling Address Read/ No Stop Write Ack Signal Bit Figure 20-10. I2C bus transmission signals 20.4.1.1 START signal When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 20-10, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. SDA SCL START condition STOP condition Figure 20-11. Start and stop conditions MPC5604B/C Microcontroller Reference Manual, Rev. 8 368 Freescale Semiconductor 20.4.1.2 Slave address transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer - the slave transmits data to the master 0 = Write transfer - the master transmits data to the slave Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 20-10). No two slaves in the system may have the same address. If the I2C Bus is master, it must not transmit an address that is equal to its own slave address. The I2C Bus cannot be master and slave at the same time. However, if arbitration is lost during an address cycle the I2C Bus will revert to slave mode and operate correctly, even if it is being addressed by another master. 20.4.1.3 Data transfer Once successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 20-10. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte must be followed by an acknowledge bit, which is signalled from the receiving device by pulling the SDA low at the ninth clock. Therefore, one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDA line for the master to generate a STOP or START signal. 20.4.1.4 STOP signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL is at logical “1” (see Figure 20-10). The master can generate a STOP even if the slave has generated an acknowledge, at which point the slave must release the bus. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 369 20.4.1.5 Repeated START signal As shown in Figure 20-10, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 20.4.1.6 Arbitration procedure The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure. A bus master loses arbitration if it transmits logic “1” while another master transmits logic “0”. The losing masters immediately switch over to slave receive mode and stop driving the SDA output. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 20.4.1.7 Clock synchronization Since wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus. The devices start counting their low period and once a device's clock has gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 20-12). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. SCL1 WAIT Start Counting High Period SCL2 SCL Internal Counter Reset Figure 20-12. I2C bus clock synchronization MPC5604B/C Microcontroller Reference Manual, Rev. 8 370 Freescale Semiconductor 20.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such cases, it halts the bus clock and forces the master clock into wait state until the slave releases the SCL line. 20.4.1.9 Clock stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 20.4.2 Interrupts 20.4.2.1 General The I2C uses only one interrupt vector. Table 20-11. Interrupt summary Interrupt Offset Vector Priority Source Description I2C — — — IBAL, TCF, When any of IBAL, TCF or IAAS bits is set an interrupt may Interrupt IAAS, IBB bits in be caused based on Arbitration lost, Transfer Complete or IBSR register Address Detect conditions. If enabled by BIIE, the deassertion of IBB can also cause an interrupt, indicating that the bus is idle. 20.4.2.2 Interrupt description There are five types of internal interrupts in the I2C. The interrupt service routine can determine the interrupt type by reading the Status Register. I2C Interrupt can be generated on • Arbitration Lost condition (IBAL bit set) • Byte Transfer condition (TCF bit set and DMAEN bit not set) • Address Detect condition (IAAS bit set) • No Acknowledge from slave received when expected • Bus Going Idle (IBB bit not set) The I2C interrupt is enabled by the IBIE bit in the I2C Control Register. It must be cleared by writing ‘1’ to the IBIF bit in the interrupt service routine. The Bus Going Idle interrupt needs to be additionally enabled by the BIIE bit in the IBIC register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 371 20.5 Initialization/application information 20.5.1 I2C programming examples 20.5.1.1 Initialization sequence Reset will put the I2C Bus Control Register to its default state. Before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: 1. Update the Frequency Divider Register (IBFD) and select the required division ratio to obtain SCL frequency from system clock. 2. Update the I2C Bus Address Register (IBAD) to define its slave address. 3. Clear the IBCR[MDIS] field to enable the I2C interface system. 4. Modify the bits of the I2C Bus Control Register (IBCR) to select Master/Slave mode, Transmit/Receive mode and interrupt enable or not. Optionally also modify the bits of the I2C Bus Interrupt Config Register (IBIC) to further refine the interrupt behavior. 20.5.1.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the I2C Bus Busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data written to the data register comprises the slave calling address and the LSB, which is set to indicate the direction of transfer required from the slave. The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the SCL period, it may be necessary to wait until the I2C is busy after writing the calling address to the IBDR before proceeding with the following instructions. This is illustrated in the following example. An example of the sequence of events which generates the START signal and transmits the first byte of data (slave address) is shown below: while (bit 5, IBSR ==1)// wait in loop for IBB flag to clear bit4 and bit 5, IBCR = 1// set transmit and master mode, i.e. generate start condition IBDR = calling_address// send the calling address to the data register while (bit 5, IBSR ==0)// wait in loop for IBB flag to be set 20.5.1.3 Post-transfer software response Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The I2C Bus interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the IBIE bit. The IBIF (interrupt flag) can be cleared by writing 1 (in the interrupt service routine, if interrupts are used). The TCF bit will be cleared to indicate data transfer in progress whenever data register is written to in transmit mode, or during reading out from data register in receive mode. The TCF bit should not be used MPC5604B/C Microcontroller Reference Manual, Rev. 8 372 Freescale Semiconductor as a data transfer complete flag as the flag timing is dependent on a number of factors including the I2C bus frequency. This bit may not conclusively provide an indication of a transfer complete situation. It is recommended that transfer complete situations are detected using the IBIF flag Software may service the I2C I/O in the main program by monitoring the IBIF bit if the interrupt function is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit since their operation is different when arbitration is lost. Note that when a “Transfer Complete” interrupt occurs at the end of the address cycle, the master will always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit sent with slave calling address, then the Tx/Rx bit at Master side should be toggled at this stage. If Master does not receive an ACK from Slave, then transmission must be re-initiated or terminated. In slave mode, IAAS bit will get set in IBSR if Slave address (IBAD) matches the Master calling address. This is an indication that Master-Slave data communication can now start. During address cycles (IAAS=1), the SRW bit in the status register is read to determine the direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly. For slave mode data cycles (IAAS=0), the SRW bit is not valid. The Tx/Rx bit in the control register should be read to determine the direction of the current transfer. 20.5.1.4 Transmit/receive sequence Follow this sequence in case of Master Transmit(Address/Data): 1. Clear IBSR[IBIF]. 2. Write data in Data Register (IBDR). 3. IBSR[TCF] bit will get cleared when transfer is in progress. 4. IBSR[TCF] bit will get set when transfer is complete. 5. Wait for IBSR[IBIF] to get set, then read IBSR register to determine its source: — TCF = 1 i.e. transfer is complete. — No Acknowledge condition (RXAK = 1) is found. — IBB = 0 i.e. Bus has transitioned from Busy to Idle state. — If IBB = 1, ignore check of Arbitration Loss (IBAL = 1). — Ignore Address Detect (IAAS = 1) for Master mode (valid only for Slave mode). 6. f) Check RXAK in IBSR for an acknowledge from slave. Follow this sequence in case of Slave Receive(Address/Data): 1. Clear IBSR[IBIF]. 2. IBSR[TCF] will get cleared when transfer is in progress for address transfer. 3. IBSR[TCF] will get set when transfer is complete. 4. Wait for IBSR[IBIF] to get set. Then read IBSR register to determine its source: — Address Detect has occurred (IAAS = 1) - determination of Slave mode. 5. Clear IBIF. 6. Wait until IBSR[TCF] bit gets cleared (that is, "Transfer under Progress" condition is reached for data transfer). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 373 7. Wait until IBSR[TCF] bit gets cleared(proof that Transfer Completes from "Transfer under Progress" state). 8. Wait until IBSR[IBIF] bit gets set. To find its source, check if: — TCF = 1 i.e. reception is complete — IBSR[IBB] = 0, that is, bus has transitioned from Busy to Idle state — Ignore Arbitration Loss (IBAL = 1) for IBB = 1 — Ignore No Acknowledge condition (RXAK = 1) for receiver 9. Read the Data Register (IBDR) to determine data received from Master. Sequence followed in case of Slave Transmit (Steps 1–4 of Slave Receive for Address Detect, followed by 1–6 of Master Transmit for Data Transmit). Sequence followed in case of Master Receive (Steps 1–6 of Master Transmit for Address dispatch, followed by 5–8 of Slave Receive for Data Receive). 20.5.1.5 Generation of STOP A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter. if (tx_count == 0) or// check to see if all data bytes have been transmitted (bit 0, IBSR == 1) {// or if no ACK generated clear bit 5, IBCR// generate stop condition } else { IBDR = data_to_transmit// write byte of data to DATA register tx_count --// decrement counter }// return from interrupt If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must first be generated. The following is an example showing how a STOP signal is generated by a master receiver. rx_count --// decrease the rx counter if (rx_count ==1)// 2nd last byte to be read ? bit 3, IBCR = 1// disable ACK if (rx_count == 0)// last byte to be read ? bit 5, IBCR = 0// generate stop signal else data_received = IBDR// read RX data and store 20.5.1.6 Generation of repeated START At the end of data transfer, if the master still wants to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is as shown. bit 2, IBCR = 1// generate another start ( restart) IBDR == calling_address// transmit the calling address MPC5604B/C Microcontroller Reference Manual, Rev. 8 374 Freescale Semiconductor 20.5.1.7 Slave mode In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR clears IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred. Interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR for slave transmits or dummy reading from IBDR in slave receive mode. The slave will drive SCL low in-between byte transfers SCL is released when the IBDR is accessed in the required mode. In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal. 20.5.1.8 Arbitration lost If several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. The devices that lost arbitration are immediately switched to slave receive mode by the hardware. Their data output to the SDA line is stopped, but SCL is still generated until the end of the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission, while the bus is being engaged by another master, the hardware will inhibit the transmission, switch the MS/SL bit from 1 to 0 without generating a STOP condition, generate an interrupt to CPU and set the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 375 Clear IBIF Y Master N Mode ? TX Tx/Rx RX ? Last Byte Transmitted Y ? N Clear IBAL Y Arbitration Lost ? N RXAK=0 ? N Y End Of Y Addr Cycle (Master Rx) ? N Last Byte To Be Read Y ? N Y 2nd Last Byte To Be Read ? N Write Next Byte To IBDR Set TXAK =1 Generate Stop Signal N Y (Read) IAAS=1 Y ? Y Address Transfer IAAS=1 ? N Data Transfer SRW=1 ? N (Write) TX/RX RX ? TX Set TX Mode Write Data To IBDR Y ACK From Receiver ? N Tx Next Byte Read Data From IBDR And Store Switch To Rx Mode Set RX Mode Switch To Rx Mode Dummy Read From IBDR Generate Stop Signal Read Data From IBDR And Store Dummy Read From IBDR Dummy Read From IBDR RTI Figure 20-13. Flow-Chart of Typical I2C Interrupt Routine MPC5604B/C Microcontroller Reference Manual, Rev. 8 376 Freescale Semiconductor Chapter 21 LIN Controller (LINFlex) 21.1 Introduction The LINFlex (Local Interconnect Network Flexible) controller interfaces the LIN network and supports the LIN protocol versions 1.3; 2.0 and 2.1; and J2602 in both Master and Slave modes. LINFlex includes a LIN mode that provides additional features (compared to standard UART) to ease LIN implementation, improve system robustness, minimize CPU load and allow slave node resynchronization. 21.2 Main features 21.2.1 LIN mode features • Supports LIN protocol versions 1.3, 2.0, 2.1 and J2602 • Master mode with autonomous message handling • Classic and enhanced checksum calculation and check • Single 8-byte buffer for transmission/reception • Extended frame mode for In-Application Programming (IAP) purposes • Wake-up event on dominant bit detection • True LIN field state machine • Advanced LIN error detection • Header, response and frame timeout • Slave mode1 — Autonomous header handling — Autonomous transmit/receive data handling • LIN automatic resynchronization, allowing operation with 16 MHz fast internal RC oscillator as clock source • 16 identifier filters for autonomous message handling in Slave mode1 21.2.2 UART mode features • Full duplex communication • 8- or 9-bit with parity • 4-byte buffer for reception, 4-byte buffer for transmission • 8-bit counter for timeout management 21.2.3 Features common to LIN and UART • Fractional baud rate generator 1. Only LINFlex0 supports slave mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 377 • 3 operating modes for power saving and configuration registers lock: — Initialization — Normal — Sleep • 2 test modes: — Loop Back — Self Test • Maskable interrupts 21.3 General description The increasing number of communication peripherals embedded on microcontrollers, for example CAN, LIN and SPI, requires more and more CPU resources for communication management. Even a 32-bit microcontroller is overloaded if its peripherals do not provide high-level features to autonomously handle the communication. Even though the LIN protocol with a maximum baud rate of 20 Kbit/s is relatively slow, it still generates a non-negligible load on the CPU if the LIN is implemented on a standard UART, as usually the case. To minimize the CPU load in Master mode, LINFlex handles the LIN messages autonomously. In Master mode, once the software has triggered the header transmission, LINFlex does not request any software intervention until the next header transmission request in transmission mode or until the checksum reception in reception mode. To minimize the CPU load in Slave mode, LINFlex requires software intervention only to: • Trigger transmission or reception or data discard depending on the identifier • Write data into the buffer (transmission mode) or read data from the buffer (reception mode) after checksum reception If filter mode is activated for Slave mode, LINFlex requires software intervention only to write data into the buffer (transmission mode) or read data from the buffer (reception mode) The software uses the control, status and configuration registers to: • Configure LIN parameters (for example, baud rate or mode) • Request transmissions • Handle receptions • Manage interrupts • Configure LIN error and timeout detection • Process diagnostic information The message buffer stores transmitted or received LIN frames. MPC5604B/C Microcontroller Reference Manual, Rev. 8 378 Freescale Semiconductor LIN master node LIN slave node 1 LIN slave node n MCU Application LINFlex Controller LIN LIN Rx Tx LIN Transceiver LIN LIN Bus Figure 21-1. LIN topology network REGISTER MODEL / APPLICATION INTERFACE CONFIGURATION CONTROL STATUS Message Buffer Interface LIN control LIN status Baud rate Filter configuration MASTER MESSAGE HANDLER SLAVE MESSAGE HANDLER Identifier Filters(1) LIN PROTOCOL HANDLER 1. Filter activation optional Figure 21-2. LINFlex block diagram 21.4 Fractional baud rate generation The baud rates for the receiver and transmitter are both set to the same value as programmed in the Mantissa (LINIBRR) and Fraction (LINFBRR) registers. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 379 Tx/ Rx baud = fperiph_set_1_clk (16 × LFDIV) Eqn. 21-1 LFDIV is an unsigned fixed point number. The 12-bit mantissa is coded in the LINIBRR and the fraction is coded in the LINFBRR. The following examples show how to derive LFDIV from LINIBRR and LINFBRR register values: Example 21-1. Deriving LFDIV from LINIBRR and LINFBRR register values If LINIBRR = 27d and LINFBRR = 12d, then Mantissa (LFDIV) = 27d Fraction (LFDIV) = 12/16 = 0.75d Therefore LFDIV = 27.75d Example 21-2. Programming LFDIV from LINIBRR and LINFBRR register values To program LFDIV = 25.62d, LINFBRR = 16 × 0.62 = 9.92, nearest real number 10d = 0xA LINIBRR = mantissa (25.620d) = 25d = 0x19 NOTE The baud counters are updated with the new value of the baud registers after a write to LINIBRR. Hence the baud register value must not be changed during a transaction. The LINFBRR (containing the Fraction bits) must be programmed before the LINIBRR. NOTE LFDIV must be greater than or equal to 1.5d, i.e. LINIBRR = 1 and LINFBRR = 8. Therefore, the maximum possible baudrate is fperiph_set_1_clk / 24. Table 21-1. Error calculation for programmed baud rates = fperiph_set_1_clk 64 MHz = fperiph_set_1_clk 16 MHz Baud rate Actual Value programmed % Error = in (Calculated – the baud rate Desired) register baud rate / Desired LINIBRR LINFBRR baud rate Actual Value programmed in the baud rate register LINIBRR LINFBRR % Error = (Calculated – Desired) baud rate / Desired baud rate 2400 2399.97 1666 11 –0.001 2399.88 416 11 –0.005 9600 9599.52 416 11 –0.005 9598.08 104 3 –0.02 10417 10416.7 384 0 –0.003 10416.7 96 0 –0.003 MPC5604B/C Microcontroller Reference Manual, Rev. 8 380 Freescale Semiconductor Table 21-1. Error calculation for programmed baud rates (continued) = fperiph_set_1_clk 64 MHz = fperiph_set_1_clk 16 MHz Baud rate Actual Value programmed % Error = in (Calculated – the baud rate Desired) register baud rate / Desired LINIBRR LINFBRR baud rate Actual Value programmed in the baud rate register LINIBRR LINFBRR % Error = (Calculated – Desired) baud rate / Desired baud rate 19200 19201.9 208 5 57600 57605.8 69 7 115200 115108 34 12 230400 230216 17 6 460800 460432 8 11 921600 927536 4 5 0.01 19207.7 52 0.01 57554 17 –0.08 115108 8 –0.08 231884 4 –0.08 457143 2 0.644 941176 1 1 0.04 6 –0.08 11 –0.08 5 0.644 3 –0.794 1 2.124 21.5 Operating modes LINFlex has three main operating modes: Initialization, Normal and Sleep. After a hardware reset, LINFlex is in Sleep mode to reduce power consumption. The software instructs LINFlex to enter Initialization mode or Sleep mode by setting the INIT bit or SLEEP bit in the LINCR1. RESET LINRX DOMINANT SLEEP SLEEP NORMAL SLEEP * SLEEP INIT SLEEP * SLEEP INIT * INIT INITIALIZATION Figure 21-3. LINFlex operating modes MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 381 21.5.1 Initialization mode The software can be initialized while the hardware is in Initialization mode. To enter this mode the software sets the INIT bit in the LINCR1. To exit Initialization mode, the software clears the INIT bit. While in Initialization mode, all message transfers to and from the LIN bus are stopped and the status of the LIN bus output LINTX is recessive (high). Entering Initialization mode does not change any of the configuration registers. To initialize the LINFlex controller, the software selects the mode (LIN Master, LIN Slave or UART), sets up the baud rate register and, if LIN Slave mode with filter activation is selected, initializes the identifier list. 21.5.2 Normal mode Once initilization is complete, software clears the INIT bit in the LINCR1 to put the hardware into Normal mode. 21.5.3 Low power mode (Sleep) To reduce power consumption, LINFlex has a low power mode called Sleep mode. To enter Sleep mode, software sets the SLEEP bit in the LINCR1. In this mode, the LINFlex clock is stopped. Consequently, the LINFlex will not update the status bits but software can still access the LINFlex registers. LINFlex can be awakened (exit Sleep mode) either by software clearing the SLEEP bit or on detection of LIN bus activity if automatic wake-up mode is enabled (AWUM bit is set). On LIN bus activity detection, hardware automatically performs the wake-up sequence by clearing the SLEEP bit if the AWUM bit in the LINCR1 is set. To exit from Sleep mode if the AWUM bit is cleared, software clears the SLEEP bit when a wake-up event occurs. 21.6 Test modes Two test modes are available to the user: Loop Back mode and Self Test mode. They can be selected by the LBKM and SFTM bits in the LINCR1. These bits must be configured while LINFlex is in Initialization mode. Once one of the two test modes has been selected, LINFlex must be started in Normal mode. 21.6.1 Loop Back mode LINFlex can be put in Loop Back mode by setting the LBKM bit in the LINCR. In Loop Back mode, the LINFlex treats its own transmitted messages as received messages. MPC5604B/C Microcontroller Reference Manual, Rev. 8 382 Freescale Semiconductor LINFlex Tx Rx LINTX LINRX Figure 21-4. LINFlex in loop back mode This mode is provided for self test functions. To be independent of external events, the LIN core ignores the LINRX signal. In this mode, the LINFlex performs an internal feedback from its Tx output to its Rx input. The actual value of the LINRX input pin is disregarded by the LINFlex. The transmitted messages can be monitored on the LINTX pin. 21.6.2 Self Test mode LINFlex can be put in Self Test mode by setting the LBKM and SFTM bits in the LINCR. This mode can be used for a “Hot Self Test”, meaning the LINFlex can be tested as in Loop Back mode but without affecting a running LIN system connected to the LINTX and LINRX pins. In this mode, the LINRX pin is disconnected from the LINFlex and the LINTX pin is held recessive. LINFlex Tx Rx =1 LINTX LINRX Figure 21-5. LINFlex in self test mode 21.7 Memory map and registers description 21.7.1 Memory map See the “Memory map” chapter of this reference manual for the base addresses for the LINFlex modules. Table 21-2 shows the LINFlex memory map. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 383 Table 21-2. LINFlex memory map Address offset Register 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 LIN control register 1 (LINCR1) LIN interrupt enable register (LINIER) LIN status register (LINSR) LIN error status register (LINESR) UART mode control register (UARTCR) UART mode status register (UARTSR) LIN timeout control status register (LINTCSR) LIN output compare register (LINOCR) LIN timeout control register (LINTOCR) LIN fractional baud rate register (LINFBRR) LIN integer baud rate register (LINIBRR) LIN checksum field register (LINCFR) LIN control register 2 (LINCR2) Buffer identifier register (BIDR) Buffer data register LSB (BDRL)1 Buffer data register MSB (BDRM)2 Identifier filter enable register (IFER) Identifier filter match index (IFMI) Identifier filter mode register (IFMR) Identifier filter control register 0 (IFCR0) Identifier filter control register 1 (IFCR1) Identifier filter control register 2 (IFCR2) Identifier filter control register 3 (IFCR3) Identifier filter control register 4 (IFCR4) Identifier filter control register 5 (IFCR5) Identifier filter control register 6 (IFCR6) Identifier filter control register 7 (IFCR7) Identifier filter control register 8 (IFCR8) Identifier filter control register 9 (IFCR9) Identifier filter control register 10 (IFCR10) Identifier filter control register 11 (IFCR11) Identifier filter control register 12 (IFCR12) Identifier filter control register 13 (IFCR13) Location on page 385 on page 388 on page 389 on page 392 on page 393 on page 394 on page 396 on page 397 on page 398 on page 398 on page 399 on page 400 on page 400 on page 401 on page 402 on page 403 on page 404 on page 405 on page 406 on page 407 on page 408 on page 408 on page 408 on page 408 on page 408 on page 408 on page 408 on page 408 on page 408 on page 408 on page 408 on page 408 on page 408 MPC5604B/C Microcontroller Reference Manual, Rev. 8 384 Freescale Semiconductor Table 21-2. LINFlex memory map (continued) Address offset Register 0x0084 Identifier filter control register 14 (IFCR14) 0x0088 Identifier filter control register 15 (IFCR15) 0x008C–0x000F Reserved 1 LSB: Least significant byte 2 MSB: Most significant byte Location on page 408 on page 408 21.7.1.1 LIN control register 1 (LINCR1) Offset: 0x0000 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 R CCD CFD LASE AWUM W 21 22 MBL 23 24 25 26 27 28 29 30 31 BF SFTM LBKM MME SBDT RBLM SLEEP INIT Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 Figure 21-6. LIN control register 1 (LINCR1) Table 21-3. LINCR1 field descriptions Field CCD CFD LASE Description Checksum calculation disable This bit disables the checksum calculation (see Table 21-4). 0 Checksum calculation is done by hardware. When this bit is 0, the LINCFR is read-only. 1 Checksum calculation is disabled. When this bit is set the LINCFR is read/write. User can program this register to send a software-calculated CRC (provided CFD is 0). Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. Checksum field disable This bit disables the checksum field transmission (see Table 21-4). 0 Checksum field is sent after the required number of data bytes is sent. 1 No checksum field is sent. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. LIN Slave Automatic Resynchronization Enable 0 Automatic resynchronization disable. 1 Automatic resynchronization enable. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 385 Field AWUM MBL BF SFTM LBKM MME SBDT RBLM SLEEP INIT Table 21-3. LINCR1 field descriptions (continued) Description Automatic Wake-Up Mode This bit controls the behavior of the LINFlex hardware during Sleep mode. 0 The Sleep mode is exited on software request by clearing the SLEEP bit of the LINCR. 1 The Sleep mode is exited automatically by hardware on LINRX dominant state detection. The SLEEP bit of the LINCR is cleared by hardware whenever WUF bit in the LINSR is set. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. LIN Master Break Length This field indicates the Break length in Master mode (see Table 21-5). Note: This field can be written in Initialization mode only. It is read-only in Normal or Sleep mode. Bypass filter 0 No interrupt if identifier does not match any filter. 1 An RX interrupt is generated on identifier not matching any filter. Note: • If no filter is activated, this bit is reserved and always reads 1. • This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. Self Test Mode This bit controls the Self Test mode. For more details, see Section 21.6.2, Self Test mode. 0 Self Test mode disable. 1 Self Test mode enable. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. Loop Back Mode This bit controls the Loop Back mode. For more details see Section 21.6.1, Loop Back mode. 0 Loop Back mode disable. 1 Loop Back mode enable. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode Master Mode Enable 0 Slave mode enable. 1 Master mode enable. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. Slave Mode Break Detection Threshold 0 11-bit break. 1 10-bit break. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. Receive Buffer Locked Mode 0 Receive Buffer not locked on overrun. Once the Slave Receive Buffer is full the next incoming message overwrites the previous one. 1 Receive Buffer locked against overrun. Once the Receive Buffer is full the next incoming message is discarded. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. Sleep Mode Request This bit is set by software to request LINFlex to enter Sleep mode. This bit is cleared by software to exit Sleep mode or by hardware if the AWUM bit in LINCR1 and the WUF bit in LINSR are set (see Table 21-6). Initialization Request The software sets this bit to switch hardware into Initialization mode. If the SLEEP bit is reset, LINFlex enters Normal mode when clearing the INIT bit (see Table 21-6). MPC5604B/C Microcontroller Reference Manual, Rev. 8 386 Freescale Semiconductor CFD 1 1 0 0 CCD 1 0 1 0 Table 21-4. Checksum bits configuration LINCFR Read/Write Read-only Read/Write Read-only Checksum sent None None Programmed in LINCFR by bits CF[0:7] Hardware calculated Table 21-5. LIN master break length selection MBL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Length 10-bit 11-bit 12-bit 13-bit 14-bit 15-bit 16-bit 17-bit 18-bit 19-bit 20-bit 21-bit 22-bit 23-bit 36-bit 50-bit SLEEP 1 x 0 Table 21-6. Operating mode selection INIT 0 Sleep (reset value) 1 Initialization 0 Normal Operating mode MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 387 21.7.1.2 LIN interrupt enable register (LINIER) Offset: 0x0004 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 R 0 SZIE OCIE BEIE CEIE HEIE W 22 23 24 25 26 27 28 29 30 31 0 FEIE BOIE LSIE WUIE DBFIE DBEIE DRIE DTIE HRIE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-7. LIN interrupt enable register (LINIER) Table 21-7. LINIER field descriptions Field SZIE OCIE BEIE CEIE HEIE FEIE BOIE LSIE Description Stuck at Zero Interrupt Enable 0 No interrupt when SZF bit in LINESR or UARTSR is set. 1 Interrupt generated when SZF bit in LINESR or UARTSR is set. Output Compare Interrupt Enable 0 No interrupt when OCF bit in LINESR or UARTSR is set. 1 Interrupt generated when OCF bit in LINESR or UARTSR is set. Bit Error Interrupt Enable 0 No interrupt when BEF bit in LINESR is set. 1 Interrupt generated when BEF bit in LINESR is set. Checksum Error Interrupt Enable 0 No interrupt on Checksum error. 1 Interrupt generated when checksum error flag (CEF) in LINESR is set. Header Error Interrupt Enable 0 No interrupt on Break Delimiter error, Synch Field error, Identifier field error. 1 Interrupt generated on Break Delimiter error, Synch Field error, Identifier field error. Framing Error Interrupt Enable 0 No interrupt on Framing error. 1 Interrupt generated on Framing error. Buffer Overrun Interrupt Enable 0 No interrupt on Buffer overrun. 1 Interrupt generated on Buffer overrun. LIN State Interrupt Enable 0 No interrupt on LIN state change. 1 Interrupt generated on LIN state change. This interrupt can be used for debugging purposes. It has no status flag but is reset when writing ‘1111’ into LINS[0:3] in the LINSR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 388 Freescale Semiconductor Field WUIE DBFIE DBEIE DRIE DTIE HRIE Table 21-7. LINIER field descriptions (continued) Description Wake-up Interrupt Enable 0 No interrupt when WUF bit in LINSR or UARTSR is set. 1 Interrupt generated when WUF bit in LINSR or UARTSR is set. Data Buffer Full Interrupt Enable 0 No interrupt when buffer data register is full. 1 Interrupt generated when data buffer register is full. Data Buffer Empty Interrupt Enable 0 No interrupt when buffer data register is empty. 1 Interrupt generated when data buffer register is empty. Data Reception Complete Interrupt Enable 0 No interrupt when data reception is completed. 1 Interrupt generated when data received flag (DRF) in LINSR or UARTSR is set. Data Transmitted Interrupt Enable 0 No interrupt when data transmission is completed. 1 Interrupt generated when data transmitted flag (DTF) is set in LINSR or UARTSR. Header Received Interrupt Enable 0 No interrupt when a valid LIN header has been received. 1 Interrupt generated when a valid LIN header has been received, that is, HRF bit in LINSR is set. 21.7.1.3 LIN status register (LINSR) Offset: 0x0008 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 R W Reset 0 17 18 LINS w1c 00 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 RMB 0 RBSY RPS WUF DBFF DBEF DRF DTF HRF w1c w1c w1c w1c w1c w1c w1c w1c 0000001000000 Figure 21-8. LIN status register (LINSR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 389 t Table 21-8. LINSR field descriptions Field LINS LIN modes / normal mode states Description 0000: Sleep mode LINFlex is in Sleep mode to save power consumption. 0001: Initialization mode LINFlex is in Initialization mode. RMB RBSY Normal mode states 0010: Idle This state is entered on several events: • SLEEP bit and INIT bit in LINCR1 have been cleared by software, • A falling edge has been received on RX pin and AWUM bit is set, • The previous frame reception or transmission has been completed or aborted. 0011: Break In Slave mode, a falling edge followed by a dominant state has been detected. Receiving Break. Note: In Slave mode, in case of error new LIN state can be either Idle or Break depending on last bit state. If last bit is dominant new LIN state is Break, otherwise Idle. In Master mode, Break transmission ongoing. 0100: Break Delimiter In Slave mode, a valid Break has been detected. See Section 21.7.1.1, LIN control register 1 (LINCR1) for break length configuration (10-bit or 11-bit). Waiting for a rising edge. In Master mode, Break transmission has been completed. Break Delimiter transmission is ongoing. 0101: Synch Field In Slave mode, a valid Break Delimiter has been detected (recessive state for at least one bit time). Receiving Synch Field. In Master mode, Synch Field transmission is ongoing. 0110: Identifier Field In Slave mode, a valid Synch Field has been received. Receiving Identifier Field. In Master mode, identifier transmission is ongoing. 0111: Header reception/transmission completed In Slave mode, a valid header has been received and identifier field is available in the BIDR. In Master mode, header transmission is completed. 1000: Data reception/transmission Response reception/transmission is ongoing. 1001: Checksum Data reception/transmission completed. Checksum reception/transmission ongoing. In UART mode, only the following states are flagged by the LIN state bits: • Init • Sleep • Idle • Data transmission/reception Release Message Buffer 0 Buffer is free. 1 Buffer ready to be read by software. This bit must be cleared by software after reading data received in the buffer. This bit is cleared by hardware in Initialization mode. Receiver Busy Flag 0 Receiver is idle 1 Reception ongoing Note: In Slave mode, after header reception, if BIDR[DIR] = 0 and reception starts then this bit is set. In this case, user cannot program LINCR2[DTRQ] = 1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 390 Freescale Semiconductor Field RPS WUF DBFF DBEF DRF DTF HRF Table 21-8. LINSR field descriptions (continued) Description LIN receive pin state This bit reflects the current status of LINRX pin for diagnostic purposes. Wake-up Flag This bit is set by hardware and indicates to the software that LINFlex has detected a falling edge on the LINRX pin when: • Slave is in Sleep mode • Master is in Sleep mode or idle state This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt is generated if WUIE bit in LINIER is set. Data Buffer Full Flag This bit is set by hardware and indicates the buffer is full. It is set only when receiving extended frames (DFL > 7). This bit must be cleared by software. It is reset by hardware in Initialization mode. Data Buffer Empty Flag This bit is set by hardware and indicates the buffer is empty. It is set only when transmitting extended frames (DFL > 7). This bit must be cleared by software, once buffer has been filled again, in order to start transmission. This bit is reset by hardware in Initialization mode. Data Reception Completed Flag This bit is set by hardware and indicates the data reception is completed. This bit must be cleared by software. It is reset by hardware in Initialization mode. Note: This flag is not set in case of bit error or framing error. Data Transmission Completed Flag This bit is set by hardware and indicates the data transmission is completed. This bit must be cleared by software. It is reset by hardware in Initialization mode. Note: This flag is not set in case of bit error if IOBE bit is reset. Header Reception Flag This bit is set by hardware and indicates a valid header reception is completed. This bit must be cleared by software. This bit is reset by hardware in Initialization mode and at end of completed or aborted frame. Note: If filters are enabled, this bit is set only when identifier software filtering is required, that is to say: • All filters are inactive and BF bit in LINCR1 is set • No match in any filter and BF bit in LINCR1 is set • TX filter match MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 391 21.7.1.4 LIN error status register (LINESR) Offset: 0x000C Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SZF OCF BEF CEF SFEF BDEF IDPEF FEF BOF 0 0 0 0 0 0 NF W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-9. LIN error status register (LINESR) Table 21-9. LINESR field descriptions Field SZF OCF BEF CEF SFEF BDEF IDPEF Description Stuck at Zero Flag This bit is set by hardware when the bus is dominant for more than a 100-bit time. If the dominant state continues, SZF flag is set again after 87-bit time. It is cleared by software. Output Compare Flag 0 No output compare event occurred 1 The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR. If this bit is set and IOT bit in LINTCSR is set, LINFlex moves to Idle state. If LTOM bit in LINTCSR is set, then OCF is cleared by hardware in Initialization mode. If LTOM bit is cleared, then OCF maintains its status whatever the mode is. Bit Error Flag This bit is set by hardware and indicates to the software that LINFlex has detected a bit error. This error can occur during response field transmission (Slave and Master modes) or during header transmission (in Master mode). This bit is cleared by software. Checksum Error Flag This bit is set by hardware and indicates that the received checksum does not match the hardware calculated checksum. This bit is cleared by software. Note: This bit is never set if CCD or CFD bit in LINCR1 is set. Synch Field Error Flag This bit is set by hardware and indicates that a Synch Field error occurred (inconsistent Synch Field). Break Delimiter Error Flag This bit is set by hardware and indicates that the received Break Delimiter is too short (less than one bit time). Identifier Parity Error Flag This bit is set by hardware and indicates that a Identifier Parity error occurred. Note: Header interrupt is triggered when SFEF or BDEF or IDPEF bit is set and HEIE bit in LINIER is set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 392 Freescale Semiconductor Field FEF BOF NF Table 21-9. LINESR field descriptions (continued) Description Framing Error Flag This bit is set by hardware and indicates to the software that LINFlex has detected a framing error (invalid stop bit). This error can occur during reception of any data in the response field (Master or Slave mode) or during reception of Synch Field or Identifier Field in Slave mode. Buffer Overrun Flag This bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. If RBLM in LINCR1 is set then the new byte received is discarded. If RBLM is reset then the new byte overwrites the buffer. It can be cleared by software. Noise Flag This bit is set by hardware when noise is detected on a received character. This bit is cleared by software. 21.7.1.5 UART mode control register (UARTCR) Offset: 0x0010 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 R0 W Reset 0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0000 TDFL RDFL RXEN TXEN OP PCE WL UART 000000000000000 Figure 21-10. UART mode control register (UARTCR) Table 21-10. UARTCR field descriptions Field TDFL RDFL Description Transmitter Data Field length This field sets the number of bytes to be transmitted in UART mode. It can be programmed only when the UART bit is set. TDFL[0:1] = Transmit buffer size – 1. 00 Transmit buffer size = 1. 01 Transmit buffer size = 2. 10 Transmit buffer size = 3. 11 Transmit buffer size = 4. Receiver Data Field length This field sets the number of bytes to be received in UART mode. It can be programmed only when the UART bit is set. RDFL[0:1] = Receive buffer size – 1. 00 Receive buffer size = 1. 01 Receive buffer size = 2. 10 Receive buffer size = 3. 11 Receive buffer size = 4. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 393 Field RXEN TXEN OP PCE WL UART Table 21-10. UARTCR field descriptions (continued) Description Receiver Enable 0 Receiver disable. 1 Receiver enable. This bit can be programmed only when the UART bit is set. Transmitter Enable 0 Transmitter disable. 1 Transmitter enable. This bit can be programmed only when the UART bit is set. Note: Transmission starts when this bit is set and when writing DATA0 in the BDRL register. Odd Parity 0 Sent parity is even. 1 Sent parity is odd. This bit can be programmed in Initialization mode only when the UART bit is set. Parity Control Enable 0 Parity transmit/check disable. 1 Parity transmit/check enable. This bit can be programmed in Initialization mode only when the UART bit is set. Word Length in UART mode 0 7-bit data + parity bit. 1 8-bit data (or 9-bit if PCE is set). This bit can be programmed in Initialization mode only when the UART bit is set. UART mode enable 0 LIN mode. 1 UART mode. This bit can be programmed in Initialization mode only. 21.7.1.6 UART mode status register (UARTSR) Offset: 0x0014 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0000000000000000 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 R SZF OCF PE3 PE2 PE1 PE0 RMB FEF BOF RPS WUF 0 28 29 30 31 0 DRF DTF NF W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-11. UART mode status register (UARTSR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 394 Freescale Semiconductor Field SZF OCF PE3 PE2 PE1 PE0 RMB FEF BOF RPS WUF Table 21-11. UARTSR field descriptions Description Stuck at Zero Flag This bit is set by hardware when the bus is dominant for more than a 100-bit time. It is cleared by software. OCF Output Compare Flag 0 No output compare event occurred. 1 The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR. An interrupt is generated if the OCIE bit in LINIER register is set. Parity Error Flag Rx3 This bit indicates if there is a parity error in the corresponding received byte (Rx3). See Section 21.8.1.1, Buffer in UART mode. No interrupt is generated if this error occurs. 0 No parity error. 1 Parity error. Parity Error Flag Rx2 This bit indicates if there is a parity error in the corresponding received byte (Rx2). See Section 21.8.1.1, Buffer in UART mode. No interrupt is generated if this error occurs. 0 No parity error. 1 Parity error. Parity Error Flag Rx1 This bit indicates if there is a parity error in the corresponding received byte (Rx1). See Section 21.8.1.1, Buffer in UART mode. No interrupt is generated if this error occurs. 0 No parity error. 1 Parity error. Parity Error Flag Rx0 This bit indicates if there is a parity error in the corresponding received byte (Rx0). See Section 21.8.1.1, Buffer in UART mode. No interrupt is generated if this error occurs. 0 No parity error. 1 Parity error. Release Message Buffer 0 Buffer is free. 1 Buffer ready to be read by software. This bit must be cleared by software after reading data received in the buffer. This bit is cleared by hardware in Initialization mode. Framing Error Flag This bit is set by hardware and indicates to the software that LINFlex has detected a framing error (invalid stop bit). Buffer Overrun Flag This bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. If RBLM in LINCR1 is set then the new byte received is discarded. If RBLM is reset then the new byte overwrites buffer. it can be cleared by software. LIN Receive Pin State This bit reflects the current status of LINRX pin for diagnostic purposes. Wake-up Flag This bit is set by hardware and indicates to the software that LINFlex has detected a falling edge on the LINRX pin in Sleep mode. This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt i generated if WUIE bit in LINIER is set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 395 Field DRF DTF NF Table 21-11. UARTSR field descriptions (continued) Description Data Reception Completed Flag This bit is set by hardware and indicates the data reception is completed, that is, the number of bytes programmed in RDFL[0:1] in UARTCR have been received. This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt is generated if DRIE bit in LINIER is set. Note: In UART mode, this flag is set in case of framing error, parity error or overrun. Data Transmission Completed Flag This bit is set by hardware and indicates the data transmission is completed, that is, the number of bytes programmed in TDFL[0:1] have been transmitted. This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt is generated if DTIE bit in LINIER is set. Noise Flag This bit is set by hardware when noise is detected on a received character. This bit is cleared by software. 21.7.1.7 LIN timeout control status register (LINTCSR) Offset: 0x0018 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 00000000 W Reset 0 0 0 0 0 0 0 0 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 LTOM IOT TOCE W CNT Reset 0 0 0 0 0 0 1 0 00000000 Figure 21-12. LIN timeout control status register (LINTCSR) Table 21-12. LINTCSR field descriptions Field LTOM IOT Description LIN timeout mode 0 LIN timeout mode (header, response and frame timeout detection). 1 Output compare mode. This bit can be set/cleared in Initialization mode only. Idle on Timeout 0 LIN state machine not reset to Idle on timeout event. 1 LIN state machine reset to Idle on timeout event. This bit can be set/cleared in Initialization mode only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 396 Freescale Semiconductor Field TOCE CNT Table 21-12. LINTCSR field descriptions (continued) Description Timeout counter enable 0 Timeout counter disable. OCF bit in LINESR or UARTSR is not set on an output compare event. 1 Timeout counter enable. OCF bit is set if an output compare event occurs. TOCE bit is configurable by software in Initialization mode. If LIN state is not Init and if timer is in LIN timeout mode, then hardware takes control of TOCE bit. Counter Value This field indicates the LIN timeout counter value. 21.7.1.8 LIN output compare register (LINOCR) Offset: 0x001C Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OC21 W OC11 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 If LINTCSR[LTOM] = 1, this field is read-only. Figure 21-13. LIN output compare register (LINOCR) Table 21-13. LINOCR field descriptions Field OC2 OC1 Description Output compare 2 value These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR. Output compare 1 value These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 397 21.7.1.9 LIN timeout control register (LINTOCR) Offset: 0x0020 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 R0 W Reset 0 Field RTO HTO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 000 0 RTO HTO 00011100 0 101100 Figure 21-14. LIN timeout control register (LINTOCR) Table 21-14. LINTOCR field descriptions Description Response timeout value This field contains the response timeout duration (in bit time) for 1 byte. The reset value is 0xE = 14, corresponding to TResponse_Maximum = 1.4 × TResponse_Nominal Header timeout value This field contains the header timeout duration (in bit time). This value does not include the Break and the Break Delimiter. The reset value is the 0x2C = 44, corresponding to THeader_Maximum. Programming LINSR[MME] = 1 changes the HTO value to 0x1C = 28. This field can be written only in Slave mode. 21.7.1.10 LIN fractional baud rate register (LINFBRR) Offset: 0x0024 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 W DIV_F Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-15. LIN fractional baud rate register (LINFBRR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 398 Freescale Semiconductor Field DIV_F Table 21-15. LINFBRR field descriptions Description Fraction bits of LFDIV The 4 fraction bits define the value of the fraction of the LINFlex divider (LFDIV). Fraction (LFDIV) = Decimal value of DIV_F / 16. This field can be written in Initialization mode only. 21.7.1.11 LIN integer baud rate register (LINIBRR) Offset: 0x0028 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 W DIV_M Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-16. LIN integer baud rate register (LINIBRR) Table 21-16. LINIBRR field descriptions Field DIV_M Description LFDIV mantissa This field defines the LINFlex divider (LFDIV) mantissa value (see Table 21-17). This field can be written in Initialization mode only. Table 21-17. Integer baud rate selection DIV_M[0:12] 0x0000 0x0001 ... 0x1FFE ox1FFF Mantissa LIN clock disabled 1 ... 8190 8191 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 399 21.7.1.12 LIN checksum field register (LINCFR) Offset: 0x002C Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 R0 W Reset 0 Field CF 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0000000 CF 00000000 0 000000 Figure 21-17. LIN checksum field register (LINCFR) Table 21-18. LINCFR field descriptions Description Checksum bits When LINCR1[CCD] = 0, this field is read-only. When LINCR1[CCD] = 1, this field is read/write. See Table 21-4. 21.7.1.13 LIN control register 2 (LINCR2) Offset: 0x0030 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0000000000000 IOBE IOPE W WURQ DDRQ DTRQ ABRQ HTRQ Reset 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-18. LIN control register 2 (LINCR2) Table 21-19. LINCR2 field descriptions Field IOBE Description Idle on Bit Error 0 Bit error does not reset LIN state machine. 1 Bit error reset LIN state machine. This bit can be set/cleared in Initialization mode only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 400 Freescale Semiconductor Field IOPE WURQ DDRQ DTRQ ABRQ HTRQ Table 21-19. LINCR2 field descriptions (continued) Description Idle on Identifier Parity Error 0 Identifier Parity error does not reset LIN state machine. 1 Identifier Parity error reset LIN state machine. This bit can be set/cleared in Initialization mode only. Wake-up Generation Request Setting this bit generates a wake-up pulse. It is reset by hardware when the wake-up character has been transmitted. The character sent is copied from DATA0 in BDRL buffer. Note that this bit cannot be set in Sleep mode. Software has to exit Sleep mode before requesting a wake-up. Bit error is not checked when transmitting the wake-up request. Data Discard Request Set by software to stop data reception if the frame does not concern the node. This bit is reset by hardware once LINFlex has moved to idle state. In Slave mode, this bit can be set only when HRF bit in LINSR is set and identifier did not match any filter. Data Transmission Request Set by software in Slave mode to request the transmission of the LIN Data field stored in the Buffer data register. This bit can be set only when HRF bit in LINSR is set. Cleared by hardware when the request has been completed or aborted or on an error condition. In Master mode, this bit is set by hardware when BIDR[DIR] = 1 and header transmission is completed. Abort Request Set by software to abort the current transmission. Cleared by hardware when the transmission has been aborted. LINFlex aborts the transmission at the end of the current bit. This bit can also abort a wake-up request. It can also be used in UART mode. Header Transmission Request Set by software to request the transmission of the LIN header. Cleared by hardware when the request has been completed or aborted. This bit has no effect in UART mode. 21.7.1.14 Buffer identifier register (BIDR) Offset: 0x0034 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 00 DFL DIR CCS ID W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-19. Buffer identifier register (BIDR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 401 Field DFL DIR CCS ID Table 21-20. BIDR field descriptions Description Data Field Length This field defines the number of data bytes in the response part of the frame. DFL = Number of data bytes – 1. Normally, LIN uses only DFL[2:0] to manage frames with a maximum of 8 bytes of data. Identifier filters are compatible with DFL[2:0] only. DFL[5:3] are provided to manage extended frames. Direction This bit controls the direction of the data field. 0 LINFlex receives the data and copies them in the BDR registers. 1 LINFlex transmits the data from the BDR registers. Classic Checksum This bit controls the type of checksum applied on the current message. 0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification 2.0 and higher. 1 Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and earlier. In LIN slave mode (MME bit cleared in LINCR1), this bit must be configured before the header reception. If the slave has to manage frames with 2 types of checksum, filters must be configured. Identifier Identifier part of the identifier field without the identifier parity. 21.7.1.15 Buffer data register LSB (BDRL) Offset: 0x0038 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DATA3 W DATA2 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DATA1 W DATA0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-20. Buffer data register LSB (BDRL) Table 21-21. BDRL field descriptions Field DATA3 DATA2 Data Byte 3 Data byte 3 of the data field. Data Byte 2 Data byte 2 of the data field. Description MPC5604B/C Microcontroller Reference Manual, Rev. 8 402 Freescale Semiconductor Field DATA1 DATA0 Table 21-21. BDRL field descriptions (continued) Data Byte 1 Data byte 1 of the data field. Data Byte 0 Data byte 0 of the data field. Description 21.7.1.16 Buffer data register MSB (BDRM) Offset: 0x003C Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DATA7 W DATA6 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DATA5 W DATA4 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-21. Buffer data register MSB (BDRM) Table 21-22. BDRM field descriptions Field DATA7 DATA6 DATA5 DATA4 Data Byte 7 Data byte 7 of the data field. Data Byte 6 Data byte 6 of the data field. Data Byte 5 Data byte 5 of the data field. Data Byte 4 Data byte 4 of the data field. Description MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 403 21.7.1.17 Identifier filter enable register (IFER) Offset: 0x0040 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 W FACT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-22. Identifier filter enable register (IFER) Table 21-23. IFER field descriptions Field FACT Description Filter activation (see Table 21-24) 0 Filters 2n and 2n + 1 are deactivated. 1 Filters 2n and 2n + 1 are activated. This field can be set/cleared in Initialization mode only. Bit FACT[0] FACT[1] FACT[2] FACT[3] FACT[4] FACT[5] FACT[6] Table 21-24. IFER[FACT] configuration Value Result 0 Filters 0 and 1 are deactivated. 1 Filters 0 and 1 are activated. 0 Filters 2 and 3 are deactivated. 1 Filters 2 and 3 are activated. 0 Filters 4 and 5 are deactivated. 1 Filters 4 and 5 are activated. 0 Filters 6 and 7 are deactivated. 1 Filters 6 and 7 are activated. 0 Filters 8 and 9 are deactivated. 1 Filters 8 and 9 are activated. 0 Filters 10 and 11 are deactivated. 1 Filters 10 and 11 are activated. 0 Filters 12 and 13 are deactivated. 1 Filters 12 and 13 are activated. MPC5604B/C Microcontroller Reference Manual, Rev. 8 404 Freescale Semiconductor Bit FACT[7] Table 21-24. IFER[FACT] configuration (continued) Value 0 1 Result Filters 14 and 15 are deactivated. Filters 14 and 15 are activated. 21.7.1.18 Identifier filter match index (IFMI) Address: Base + 0x0044 Access: User read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 IFMI[0:4] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-23. Identifier filter match index (IFMI) Table 21-25. IFMI field descriptions Field 0:26 IFMI[0:4] 27:31 Description Reserved Filter match index This register contains the index corresponding to the received identifier. It can be used to directly write or read the data in SRAM (see Section 21.8.2.2, Slave mode for more details). When no filter matches, IFMI[0:4] = 0. When Filter n is matching, IFMI[0:4] = n + 1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 405 21.7.1.19 Identifier filter mode register (IFMR) Offset: 0x0048 Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 IFM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-24. Identifier filter mode register (IFMR) Table 21-26. IFMR field descriptions Field IFM Description Filter mode (see Table 21-27). 0 Filters 2n and 2n + 1 are in identifier list mode. 1 Filters 2n and 2n + 1 are in mask mode (filter 2n + 1 is the mask for the filter 2n). Table 21-27. IFMR[IFM] configuration Bit Value Result IFM[0] 0 Filters 0 and 1 are in identifier list mode. 1 Filters 0 and 1 are in mask mode (filter 1 is the mask for the filter 0). IFM[1] 0 Filters 2 and 3 are in identifier list mode. 1 Filters 2 and 3 are in mask mode (filter 3 is the mask for the filter 2). IFM[2] 0 Filters 4 and 5 are in identifier list mode. 1 Filters 4 and 5 are in mask mode (filter 5 is the mask for the filter 4). IFM[3] 0 Filters 6 and 7 are in identifier list mode. 1 Filters 6 and 7 are in mask mode (filter 7 is the mask for the filter 6). IFM[4] 0 Filters 8 and 9 are in identifier list mode. 1 Filters 8 and 9 are in mask mode (filter 9 is the mask for the filter 8). IFM[5] 0 Filters 10 and 11 are in identifier list mode. 1 Filters 10 and 11 are in mask mode (filter 11 is the mask for the filter 10). IFM[6] 0 Filters 12 and 13 are in identifier list mode. 1 Filters 12 and 13 are in mask mode (filter 13 is the mask for the filter 12). MPC5604B/C Microcontroller Reference Manual, Rev. 8 406 Freescale Semiconductor Table 21-27. IFMR[IFM] configuration (continued) Bit Value Result IFM[7] 0 Filters 14 and 15 are in identifier list mode. 1 Filters 14 and 15 are in mask mode (filter 15 is the mask for the filter 14). 21.7.1.20 Identifier filter control register (IFCR2n) Offsets : 0x004C–0x0084 (8 registers) Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 00 ID DFL DIR CCS W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-25. Identifier filter control register (IFCR2n) NOTE This register can be written in Initialization mode only. Table 21-28. IFCR2n field descriptions Field DFL DIR CCS ID Description Data Field Length This field defines the number of data bytes in the response part of the frame. Direction This bit controls the direction of the data field. 0 LINFlex receives the data and copies them in the BDRL and BDRM registers. 1 LINFlex transmits the data from the BDRL and BDRM registers. Classic Checksum This bit controls the type of checksum applied on the current message. 0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification 2.0 and higher. 1 Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and earlier. Identifier Identifier part of the identifier field without the identifier parity. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 407 21.7.1.21 Identifier filter control register (IFCR2n + 1) Offsets: 0x0050–0x0088 (8 registers) Access: User read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 00 ID DFL DIR CCS W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-26. Identifier filter control register (IFCR2n + 1) NOTE This register can be written in Initialization mode only. Table 21-29. IFCR2n + 1 field descriptions Field DFL DIR CCS ID Description Data Field Length This field defines the number of data bytes in the response part of the frame. DFL = Number of data bytes – 1. Direction This bit controls the direction of the data field. 0 LINFlex receives the data and copies them in the BDRL and BDRM registers. 1 LINFlex transmits the data from the BDRL and BDRM registers. Classic Checksum This bit controls the type of checksum applied on the current message. 0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification 2.0 and higher. 1 Classic Checksum covering Data field only. This is compatible with LIN specification 1.3 and earlier. Identifier Identifier part of the identifier field without the identifier parity MPC5604B/C Microcontroller Reference Manual, Rev. 8 408 Freescale Semiconductor 21.8 Functional description 21.8.1 UART mode The main features in the UART mode are • Full duplex communication • 8- or 9-bit data with parity • 4-byte buffer for reception, 4-byte buffer for transmission • 8-bit counter for timeout management 8-bit data frames: The 8th bit can be a data or a parity bit. Even/Odd Parity can be selected by the Odd Parity bit in the UARTCR. An even parity is set if the modulo-2 sum of the 7 data bits is 1. An odd parity is cleared in this case. Byte Field Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit — Data bit — Parity bit Figure 21-27. UART mode 8-bit data frame 9-bit frames: The 9th bit is a parity bit. Even/Odd Parity can be selected by the Odd Parity bit in the UARTCR. An even parity is set if the modulo-2 sum of the 8 data bits is 1. An odd parity is cleared in this case. Byte Field Start bit D0 D1 D2 D3 D4 D5 D6 D7 D8 Stop bit — Parity bit Figure 21-28. UART mode 9-bit data frame 21.8.1.1 Buffer in UART mode The 8-byte buffer is divided into two parts: one for receiver and one for transmitter as shown in Table 21-30. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 409 Buffer data register BDRL[0:31] BDRM[0:31] Table 21-30. Message buffer LIN mode Transmit/Receive buffer DATA0[0:7] DATA1[0:7] DATA2[0:7] DATA3[0:7] DATA4[0:7] DATA5[0:7] DATA6[0:7] DATA7[0:7] UART mode Transmit buffer Tx0 Tx1 Tx2 Tx3 Receive buffer Rx0 Rx1 Rx2 Rx3 21.8.1.2 UART transmitter In order to start transmission in UART mode, you must program the UART bit and the transmitter enable (TXEN) bit in the UARTCR to 1. Transmission starts when DATA0 (least significant data byte) is programmed. The number of bytes transmitted is equal to the value configured by UARTCR[TDFL] (see Table 21-10). The Transmit buffer is 4 bytes, hence a 4-byte maximum transmission can be triggered. Once the programmed number of bytes has been transmitted, the UARTSR[DTF] bit is set. If UARTCR[TXEN] is reset during a transmission then the current transmission is completed and no further transmission can be invoked. 21.8.1.3 UART receiver The UART receiver is active as soon as the user exits Initialization mode and programs UARTCR[RXEN] = 1. There is a dedicated 4-byte data buffer for received data bytes. Once the programmed number (RDFL bits) of bytes has been received, the UARTSR[DRF] bit is set. If the RXEN bit is reset during a reception then the current reception is completed and no further reception can be invoked until RXEN is set. If a parity error occurs during reception of any byte, then the corresponding PEx bit in the UARTSR is set. No interrupt is generated in this case. If a framing error occurs in any byte (UARTSR[FE] = 1) then an interrupt is generated if the LINIER[FEIE] bit is set. If the last received frame has not been read from the buffer (that is, RMB bit is not reset by the user) then upon reception of the next byte an overrun error occurs (UARTSR[BOF] = 1) and one message will be lost. Which message is lost depends on the configuration of LINCR1[RBLM]. • If the buffer lock function is disabled (LINCR1[RBLM] = 0) the last message stored in the buffer is overwritten by the new incoming message. In this case the latest message is always available to the application. • If the buffer lock function is enabled (LINCR1[RBLM] = 1) the most recent message is discarded and the previous message is available in the buffer. MPC5604B/C Microcontroller Reference Manual, Rev. 8 410 Freescale Semiconductor An interrupt is generated if the LINIER[BOIE] bit is set. 21.8.1.4 Clock gating The LINFlex clock can be gated from the Mode Entry module (MC_ME). In UART mode, the LINFlex controller acknowledges a clock gating request once the data transmission and data reception are completed, that is, once the Transmit buffer is empty and the Receive buffer is full. 21.8.2 LIN mode LIN mode comprises four submodes: • Master mode • Slave mode1 • Slave mode with identifier filtering1 • Slave mode with automatic resynchronization1 These submodes are described in the following pages. 21.8.2.1 Master mode In Master mode the application uses the message buffer to handle the LIN messages. Master mode is selected when the LINCR1[MME] bit is set. 21.8.2.1.1 LIN header transmission According to the LIN protocol any communication on the LIN bus is triggered by the Master sending a header. The header is transmitted by the Master task while the data is transmitted by the Slave task of a node. To transmit a header with LINFlex the application must set up the identifier, the data field length and configure the message (direction and checksum type) in the BIDR before requesting the header transmission by setting LINCR2[HTRQ]. 21.8.2.1.2 Data transmission (transceiver as publisher) When the master node is publisher of the data corresponding to the identifier sent in the header, then the slave task of the master has to send the data in the Response part of the LIN frame. Therefore, the application must provide the data to LINFlex before requesting the header transmission. The application stores the data in the message buffer BDR. According to the data field length, LINFlex transmits the data and the checksum. The application uses the BDR[CCS] bit to configure the checksum type (classic or enhanced) for each message. If the response has been sent successfully, the LINSR[DTF] bit is set. In case of error, the DTF flag is not set and the corresponding error flag is set in the LINESR (see Section 21.8.2.1.6, Error handling). 1. Only LINFlex0 supports slave mode MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 411 It is possible to handle frames with a Response size larger than 8 bytes of data (extended frames). If the data field length in the BIDR is configured with a value higher than 8 data bytes, the LINSR[DBEF] bit is set after the first 8 bytes have been transmitted. The application has to update the buffer BDR before resetting the DBEF bit. The transmission of the next bytes starts when the DBEF bit is reset. After the last data byte (or the checksum byte) has been sent, the DTF flag is set. The direction of the message buffer is controlled by the BIDR[DIR] bit. When the application sets this bit the response is sent by LINFlex (publisher). Resetting this bit configures the message buffer as subscriber. 21.8.2.1.3 Data reception (transceiver as subscriber) To receive data from a slave node, the master sends a header with the corresponding identifier. LINFlex stores the data received from the slave in the message buffer and stores the message status in the LINSR. If the response has been received successfully, the LINSR[DRF] is set. In case of error, the DRF flag is not set and the corresponding error flag is set in the LINESR (see Section 21.8.2.1.6, Error handling). It is possible to handle frames with a Response size larger than 8 bytes of data (extended frames). If the data field length in the BIDR is configured with a value higher than 8 data bytes, the LINSR[DBFF] bit is set once the first 8 bytes have been received. The application has to read the buffer BDR before resetting the DBFF bit. Once the last data byte (or the checksum byte) has been received, the DRF flag is set. 21.8.2.1.4 Data discard To discard data from a slave, the BIDR[DIR] bit must be reset and the LINCR2[DDRQ] bit must be set before starting the header transmission. 21.8.2.1.5 Error detection LINFlex is able to detect and handle LIN communication errors. A code stored in the LIN error status register (LINESR) signals the errors to the software. In Master mode, the following errors are detected: • Bit error: During transmission, the value read back from the bus differs from the transmitted value. • Framing error: A dominant state has been sampled on the stop bit of the currently received character (synch field, identifier field or data field). • Checksum error: The computed checksum does not match the received one. • Response and Frame timeout: See Section 21.8.3, 8-bit timeout counter, for more details. 21.8.2.1.6 Error handling In case of Bit Error detection during transmission, LINFlex stops the transmission of the frame after the corrupted bit. LINFlex returns to idle state and an interrupt is generated if LINIER[BEIE] = 1. During reception, a Framing Error leads LINFlex to discard the current frame. LINFlex returns immediately to idle state. An interrupt is generated if LINIER[FEIE] = 1. During reception, a Checksum Error leads LINFlex to discard the received frame. LINFlex returns to idle state. An interrupt is generated if LINIER[CEIE] = 1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 412 Freescale Semiconductor 21.8.2.2 Slave mode In Slave mode the application uses the message buffer to handle the LIN messages. Slave mode is selected when LINCR1[MME] = 0. 21.8.2.2.1 Data transmission (transceiver as publisher) When LINFlex receives the identifier, the LINSR[HRF] is set and, if LINIER[HRIE] = 1, an RX interrupt is generated. The software must read the received identifier in the BIDR, fill the BDR registers, specify the data field length using the BIDR[DFL] and trigger the data transmission by setting the LINCR2[DTRQ] bit. One or several identifier filters can be configured for transmission by setting the IFCRx[DIR] bit and activated by setting one or several bits in the IFER. When at least one identifier filter is configured in transmission and activated, and if the received identifier matches the filter, a specific TX interrupt (instead of an RX interrupt) is generated. Typically, the application has to copy the data from SRAM locations to the BDAR. To copy the data to the right location, the application has to identify the data by means of the identifier. To avoid this and to ease the access to the SRAM locations, the LINFlex controller provides a Filter Match Index. This index value is the number of the filter that matched the received identifier. The software can use the index in the IFMI register to directly access the pointer that points to the right data array in the SRAM area and copy this data to the BDAR (see Figure 21-30). Using a filter avoids the software having to configure the direction, the data field length and the checksum type in the BIDR. The software fills the BDAR and triggers the data transmission by programming LINCR2[DTRQ] = 1. If LINFlex cannot provide enough TX identifier filters to handle all identifiers the software has to transmit data for, then a filter can be configured in mask mode (see Section 21.8.2.3, Slave mode with identifier filtering) in order to manage several identifiers with one filter only. 21.8.2.2.2 Data reception (transceiver as subscriber) When LINFlex receives the identifier, the LINSR[HRF] bit is set and, if LINIER[HRIE] = 1, an RX interrupt is generated. The software must read the received identifier in the BIDR and specify the data field length using the BIDR[DFL] field before receiving the stop bit of the first byte of data field. When the checksum reception is completed, an RX interrupt is generated to allow the software to read the received data in the BDR registers. One or several identifier filters can be configured for reception by programming IFCRx[DIR] = 0 and activated by setting one or several bits in the IFER. When at least one identifier filter is configured in reception and activated, and if the received identifier matches the filter, an RX interrupt is generated after the checksum reception only. Typically, the application has to copy the data from the BDAR to SRAM locations. To copy the data to the right location, the application has to identify the data by means of the identifier. To avoid this and to ease MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 413 the access to the SRAM locations, the LINFlex controller provides a Filter Match Index. This index value is the number of the filter that matched the received identifier. The software can use the index in the IFMI register to directly access the pointer that points to the right data array in the SRAM area and copy this data from the BDAR to the SRAM (see Figure 21-30). Using a filter avoids the software reading the ID value in the BIDR, and configuring the direction, the data field length and the checksum type in the BIDR. If LINFlex cannot provide enough RX identifier filters to handle all identifiers the software has to receive the data for, then a filter can be configured in mask mode (see Section 21.8.2.3, Slave mode with identifier filtering) in order to manage several identifiers with one filter only. 21.8.2.2.3 Data discard When LINFlex receives the identifier, the LINSR[HRF] bit is set and, if LINIER[HRIE] = 1, an RX interrupt is generated. If the received identifier does not concern the node, you must program LINCR2[DDRQ] = 1. LINFlex returns to idle state after bit DDRQ is set. 21.8.2.2.4 Error detection In Slave mode, the following errors are detected: • Header error: An error occurred during header reception (Break Delimiter error, Inconsistent Synch Field, Header Timeout). • Bit error: During transmission, the value read back from the bus differs from the transmitted value. • Framing error: A dominant state has been sampled on the stop bit of the currently received character (synch field, identifier field or data field). • Checksum error: The computed checksum does not match the received one. 21.8.2.2.5 Error handling In case of Bit Error detection during transmission, LINFlex stops the transmission of the frame after the corrupted bit. LINFlex returns to idle state and an interrupt is generated if the BEIE bit in the LINIER is set. During reception, a Framing Error leads LINFlex to discard the current frame. LINFlex returns immediately to idle state. An interrupt is generated if LINIER[FEIE] = 1. During reception, a Checksum Error leads LINFlex to discard the received frame. LINFlex returns to idle state. An interrupt is generated if LINIER[CEIE] = 1. During header reception, a Break Delimiter error, an Inconsistent Synch Field or a Timeout error leads LINFlex to discard the header. An interrupt is generated if LINIER[HEIE] = 1. LINFlex returns to idle state. 21.8.2.2.6 Valid header A received header is considered as valid when it has been received correctly according to the LIN protocol. If a valid Break Field and Break Delimiter come before the end of the current header or at any time during a data field, the current header or data is discarded and the state machine synchronizes on this new break. MPC5604B/C Microcontroller Reference Manual, Rev. 8 414 Freescale Semiconductor 21.8.2.2.7 Valid message A received or transmitted message is considered as valid when the data has been received or transmitted without error according to the LIN protocol. 21.8.2.2.8 Overrun Once the message buffer is full, the next valid message reception leads to an overrun and a message is lost. The hardware sets the BOF bit in the LINSR to signal the overrun condition. Which message is lost depends on the configuration of the RX message buffer: • If the buffer lock function is disabled (LINCR1[RBLM] = 0) the last message stored in the buffer is overwritten by the new incoming message. In this case the latest message is always available to the application. • If the buffer lock function is enabled (LINCR1[RBLM] = 0) the most recent message is discarded and the previous message is available in the buffer. 21.8.2.3 Slave mode with identifier filtering In the LIN protocol the identifier of a message is not associated with the address of a node but related to the content of the message. Consequently a transmitter broadcasts its message to all receivers. On header reception a slave node decides—depending on the identifier value—whether the software needs to receive or send a response. If the message does not target the node, it must be discarded without software intervention. To fulfill this requirement, the LINFlex controller provides configurable filters in order to request software intervention only if needed. This hardware filtering saves CPU resources that would otherwise be needed by software for filtering. 21.8.2.3.1 Filter mode Usually each of the eight IFCR registers filters one dedicated identifier, but this limits the number of identifiers LINFlex can handle to the number of IFCR registers implemented in the device. Therefore, in order to be able to handle more identifiers, the filters can be configured in mask mode. In identifier list mode (the default mode), both filter registers are used as identifier registers. All bits of the incoming identifier must match the bits specified in the filter register. In mask mode, the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match” or as “don’t care”. For the bit mapping and registers organization, please see Figure 21-29. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 415 Identifier Filter Register Organization 15 Identifier Bit Mapping IFCRn DFL DIR CCS 0 ID Identifier Identifier Identifier Filter Configuration Identifier List Mode IFCR2n IFCR2n + 1 Identifier Filter Mode IFM = 0 Identifier Mask Mask Mode IFCR2n IFCR2n + 1 IFM = 1 Figure 21-29. Filter configuration—register organization 21.8.2.3.2 Identifier filter mode configuration The identifier filters are configured in the IFCRx registers. To configure an identifier filter the filter must first be deactivated by programming IFER[FACT] = 0.. The identifier list or identifier mask mode for the corresponding IFCRx registers is configured by the IFMR[IFM] bit. For each filter, the IFCRx register configures the ID (or the mask), the direction (TX or RX), the data field length, and the checksum type. If no filter is active, an RX interrupt is generated on any received identifier event. If at least one active filter is configured as TX, all received identifiers matching this filter generate a TX interrupt. If at least one active filter is configured as RX, all received identifiers matching this filter generate an RX interrupt. If no active filter is configured as RX, all received identifiers not matching TX filter(s) generate an RX interrupt. Table 21-31. Filter to interrupt vector correlation Number of Number of active filters Number of active filters active filters configured as TX configured as RX Interrupt vector 0 0 0 RX interrupt on all identifiers MPC5604B/C Microcontroller Reference Manual, Rev. 8 416 Freescale Semiconductor Table 21-31. Filter to interrupt vector correlation Number of Number of active filters Number of active filters active filters configured as TX configured as RX Interrupt vector a (a > 0) n (n = a + b) a a (a > 0) b 0 (b > 0) 0 b (b > 0) b — TX interrupt on identifiers matching the filters, — RX interrupt on all other identifiers if BF bit is set, no RX interrupt if BF bit is reset — TX interrupt on identifiers matching the TX filters, — RX interrupt on identifiers matching the RX filters, — all other identifiers discarded (no interrupt) — RX interrupt on identifiers matching the filters, — TX interrupt on all other identifiers if BF bit is set, no TX interrupt if BF bit is reset @ MESSAGE0 + IFMI MESSAGE1 DATA pointers table MESSAGE2 SRAM Figure 21-30. Identifier match index 21.8.2.4 Slave mode with automatic resynchronization Automatic resynchronization must be enabled in Slave mode if fperiph_set_1_clk tolerance is greater than 1.5%. This feature compensates a fperiph_set_1_clk deviation up to 14%, as specified in LIN standard. This mode is similar to Slave mode as described in Section 21.8.2.2, Slave mode, with the addition of automatic resynchronization enabled by the LASE bit. In this mode LINFlex adjusts the fractional baud rate generator after each Synch Field reception. Automatic resynchronization method When automatic resynchronization is enabled, after each LIN Break, the time duration between five falling edges on RDI is sampled on fperiph_set_1_clk and the result of this measurement is stored in an internal 19-bit register called SM (not user accessible) (see Figure 21-31). Then the LFDIV value (and its associated registers LINIBRR and LINFBRR) are automatically updated at the end of the fifth falling edge. During MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 417 LIN Synch Field measurement, the LINFlex state machine is stopped and no data is transferred to the data register. Tperiph_set_1_clk = Clock period TBR = baud rate period TBR = 16.LFDIV.Tperiph_set_1_clk SM = Synch Measurement Register (19 bits) TBR LIN Break Break delim. Start Bit Bit0 LIN Synch Field Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Next Bit7 Stop Bit Start Bit Measurement = 8.TBR = SM.Tperiph_set_1_clk LFDIV(n) LFDIV = TBR / (16.Tperiph_set_1_clk) = Rounding (SM / 128) Figure 21-31. LIN synch field measurement LFDIV(n+1) LFDIV is an unsigned fixed point number. The mantissa is coded on 12 bits in the LINIBRR and the fraction is coded on 4 bits in the LINFBRR. If LASE bit = 1 then LFDIV is automatically updated at the end of each LIN Synch Field. Three internal registers (not user-accessible) manage the auto-update of the LINFlex divider (LFDIV): • LFDIV_NOM (nominal value written by software at LINIBRR and LINFBRR addresses) • LFDIV_MEAS (results of the Field Synch measurement) • LFDIV (used to generate the local baud rate) On transition to idle, break or break delimiter state due to any error or on reception of a complete frame, hardware reloads LFDIV with LFDIV_NOM. 21.8.2.4.1 Deviation error on the Synch Field The deviation error is checked by comparing the current baud rate (relative to the slave oscillator) with the received LIN Synch Field (relative to the master oscillator). Two checks are performed in parallel. The first check is based on a measurement between the first falling edge and the last falling edge of the Synch Field: • If D1 > 14.84%, LHE is set. • If D1 < 14.06%, LHE is not set. • If 14.06% < D1 < 14.84%, LHE can be either set or reset depending on the dephasing between the signal on LINFlex_RX pin the fperiph_set_1_clk clock. The second check is based on a measurement of time between each falling edge of the Synch Field: • If D2 > 18.75%, LHE is set. • If D2 < 15.62%, LHE is not set. • If 15.62% < D2 < 18.75%, LHE can be either set or reset depending on the dephasing between the signal on LINFlex_RX pin the fperiph_set_1_clk clock. MPC5604B/C Microcontroller Reference Manual, Rev. 8 418 Freescale Semiconductor Note that the LINFlex does not need to check if the next edge occurs slower than expected. This is covered by the check for deviation error on the full synch byte. 21.8.2.5 Clock gating The LINFlex clock can be gated from the Mode Entry module (MC_ME). In LIN mode, the LINFlex controller acknowledges a clock gating request once the frame transmission or reception is completed. 21.8.3 8-bit timeout counter 21.8.3.1 LIN timeout mode Setting the LTOM bit in the LINTCSR enables the LIN timeout mode. The LINOCR becomes read-only, and OC1 and OC2 output compare values in the LINOCR are automatically updated by hardware. This configuration detects header timeout, response timeout, and frame timeout. Depending on the LIN mode (selected by the LINCR1[MME] bit), the 8-bit timeout counter will behave differently. LIN timeout mode must not be enabled during LIN extended frames transmission or reception (that is, if the data field length in the BIDR is configured with a value higher than 8 data bytes). 21.8.3.1.1 LIN Master mode The LINTOCR[RTO] field can be used to tune response timeout and frame timeout values. Header timeout value is fixed to HTO = 28-bit time. Field OC1 checks THeader and TResponse and field OC2 checks TFrame (see Figure 21-32). When LINFlex moves from Break delimiter state to Synch Field state (see Section 21.7.1.3, LIN status register (LINSR)): • OC1 is updated with the value of OCHeader (OCHeader = CNT + 28), • OC2 is updated with the value of OCFrame (OCFrame = CNT + 28 + RTO × 9 (frame timeout value for an 8-byte frame), • the TOCE bit is set. On the start bit of the first response data byte (and if no error occurred during the header reception), OC1 is updated with the value of OCResponse (OCResponse = CNT + RTO × 9 (response timeout value for an 8-byte frame)). On the first response byte is received, OC1 and OC2 are automatically updated to check TResponse and TFrame according to RTO (tolerance) and DFL. On the checksum reception or in case of error in the header or response, the TOCE bit is reset. If there is no response, frame timeout value does not take into account the DFL value, and an 8-byte response (DFL = 7) is always assumed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 419 21.8.3.1.2 LIN Slave mode The LINTOCR[RTO] field can be used to tune response timeout and frame timeout values. Header timeout value is fixed to HTO. OC1 checks THeader and TResponse and OC2 checks TFrame (see Figure 21-32). When LINFlex moves from Break state to Break Delimiter state (see Section 21.7.1.3, LIN status register (LINSR)): • OC1 is updated with the value of OCHeader (OCHeader = CNT + HTO), • OC2 is updated with the value of OCFrame (OCFrame = CNT + HTO + RTO × 9 (frame timeout value for an 8-byte frame)), • The TOCE bit is set. On the start bit of the first response data byte (and if no error occurred during the header reception), OC1 is updated with the value of OCResponse (OCResponse = CNT + RTO × 9 (response timeout value for an 8-byte frame)). Once the first response byte is received, OC1 and OC2 are automatically updated to check TResponse and TFrame according to RTO (tolerance) and DFL. On the checksum reception or in case of error in the header or data field, the TOCE bit is reset. OC1 Frame Header OCHeader Response space Response OCResponse OC2 Break OCFrame Figure 21-32. Header and response timeout 21.8.3.2 Output compare mode Programming LINTCSR[LTOM] = 0 enables the output compare mode. This mode allows the user to fully customize the use of the counter. OC1 and OC2 output compare values can be updated in the LINTOCR by software. MPC5604B/C Microcontroller Reference Manual, Rev. 8 420 Freescale Semiconductor 21.8.4 Interrupts Table 21-32. LINFlex interrupt control Interrupt event Event flag bit Enable control bit Interrupt vector Header Received interrupt HRF HRIE RXI 1 Data Transmitted interrupt DTF DTIE TXI Data Received interrupt DRF DRIE RXI Data Buffer Empty interrupt DBEF DBEIE TXI Data Buffer Full interrupt DBFF DBFIE RXI Wake-up interrupt LIN State interrupt 2 WUPF LSF WUPIE RXI LSIE RXI Buffer Overrun interrupt BOF BOIE ERR Framing Error interrupt FEF FEIE ERR Header Error interrupt HEF HEIE ERR Checksum Error interrupt CEF CEIE ERR Bit Error interrupt BEF BEIE ERR Output Compare interrupt OCF OCIE ERR Stuck at Zero interrupt SZF SZIE ERR 1 In Slave mode, if at least one filter is configured as TX and enabled, header received interrupt vector is RXI or TXI depending on the value of identifier received. 2 For debug and validation purposes MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 421 MPC5604B/C Microcontroller Reference Manual, Rev. 8 422 Freescale Semiconductor Chapter 22 FlexCAN 22.1 Introduction The FlexCAN module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification. A general block diagram is shown in Figure 22-1, which describes the main sub-blocks implemented in the FlexCAN module, including two embedded memories, one for storing Message Buffers (MB) and another one for storing Rx Individual Mask Registers. Support for up to 64 Message Buffers is provided. The functions of the submodules are described in subsequent sections. MB63 RXIMR63 RXIMR62 MB62 ID Mask Storage 64/128/256byte SRAM Message Buffer Storage 288/544/1056byte SRAM Message Buffer Management max MB # (0–63) CAN Protocol Interface CAN Tx CAN Rx RXIMR1 RXIMR0 MB1 MB0 Bus Interface Unit IP Bus Interface Clocks, Address & Data buses, Interrupt and Test Signals Figure 22-1. FlexCAN block diagram 22.1.1 Overview The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, version 2.0 B, which supports both standard and extended message frames. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 423 A flexible number of Message Buffers (16, 32 or 64) is also supported. The Message Buffers are stored in an embedded SRAM dedicated to the FlexCAN module. The CAN Protocol Interface (CPI) submodule manages the serial communication on the CAN bus, requesting SRAM access for receiving and transmitting message frames, validating received messages and performing error handling. The Message Buffer Management (MBM) submodule handles Message Buffer selection for reception and transmission, taking care of arbitration and ID matching algorithms. The Bus Interface Unit (BIU) submodule controls the access to and from the internal interface bus, in order to establish connection to the CPU and to other blocks. Clocks, address and data buses, interrupt outputs and test signals are accessed through the Bus Interface Unit. 22.1.2 FlexCAN module features The FlexCAN module includes these distinctive features: • Full implementation of the CAN protocol specification, version 2.0B — Standard data and remote frames — Extended data and remote frames — 0–8 bytes data length — Programmable bit rate up to 1 Mbit/s — Content-related addressing • Flexible Message Buffers (up to 64) of zero to eight bytes data length • Each MB configurable as Rx or Tx, all supporting standard and extended messages • Individual Rx Mask Registers per Message Buffer • Includes either 1056 bytes (64 MBs) of SRAM used for MB storage • Includes either 256 bytes (64 MBs) of SRAM used for individual Rx Mask Registers • Full featured Rx FIFO with storage capacity for 6 frames and internal pointer handling • Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 8 extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability • Selectable backwards compatibility with previous FlexCAN version • Programmable clock source to the CAN Protocol Interface, either bus clock or crystal oscillator • Unused MB and Rx Mask Register space can be used as general purpose SRAM space • Listen-only mode capability • Programmable loop-back mode supporting self-test operation • Programmable transmission priority scheme: lowest ID, lowest buffer number or highest priority • Time Stamp based on 16-bit free-running timer • Global network time, synchronized by a specific message • Maskable interrupts • Independent of the transmission medium (an external transceiver is assumed) • Short latency time due to an arbitration scheme for high-priority messages • Low power mode MPC5604B/C Microcontroller Reference Manual, Rev. 8 424 Freescale Semiconductor • Hardware cancellation on Tx message buffers 22.1.3 Modes of operation The FlexCAN module has four functional modes: Normal Mode (User and Supervisor), Freeze Mode, Listen-Only Mode and Loop-Back Mode. There is also a low power mode: Disable Mode. • Normal Mode (User or Supervisor) In Normal Mode, the module operates receiving and/or transmitting message frames, errors are handled normally and all the CAN Protocol functions are enabled. User and Supervisor Modes differ in the access to some restricted control registers. • Freeze Mode It is enabled when the FRZ bit in the MCR is asserted. If enabled, Freeze Mode is entered when the HALT bit in MCR is set or when Debug Mode is requested at MCU level. In this mode, no transmission or reception of frames is done and synchronicity to the CAN bus is lost. See Section 22.4.10.1, “Freeze Mode for more information. • Listen-Only Mode The module enters this mode when the LOM bit in the Control Register is asserted. In this mode, transmission is disabled, all error counters are frozen and the module operates in a CAN Error Passive mode. Only messages acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the message. • Loop-Back Mode The module enters this mode when the LPB bit in the Control Register is asserted. In this mode, FlexCAN performs an internal loop back that can be used for self test operation. The bit stream output of the transmitter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive state (logic ‘1’). FlexCAN behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. • Module Disable Mode This low power mode is entered when the MDIS bit in the MCR is asserted. When disabled, the module shuts down the clocks to the CAN Protocol Interface and Message Buffer Management submodules. Exit from this mode is done by negating the MDIS bit in the MCR. See Section 22.4.10.2, “Module Disable Mode for more information. 22.2 External signal description 22.2.1 Overview The FlexCAN module has two I/O signals connected to the external MCU pins. These signals are summarized in Table 22-1 and described in more detail in the next subsections. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 425 Table 22-1. FlexCAN signals Signal name1 Direction CAN Rx Input CAN Tx Output 1 The actual MCU pins may have different names. Description CAN receive pin CAN transmit pin 22.2.2 Signal descriptions 22.2.2.1 CAN Rx This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level ‘0’. Recessive state is represented by logic level ‘1’. 22.2.2.2 CAN Tx This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by logic level ‘0’. Recessive state is represented by logic level ‘1’. 22.3 Memory map and register description This section describes the registers and data structures in the FlexCAN module. The base address of the module depends on the particular memory map of the MCU. The addresses presented here are relative to the base address. The address space occupied by FlexCAN has 96 bytes for registers starting at the module base address, followed by MB storage space in embedded SRAM starting at address 0x0060, and an extra ID Mask storage space in a separate embedded SRAM starting at address 0x0880. 22.3.1 FlexCAN memory mapping The complete memory map for a FlexCAN module with 64 MBs capability is shown in Table 22-2. Each individual register is identified by its complete name and the corresponding mnemonic. The access type can be Supervisor (S) or Unrestricted (U). Most of the registers can be configured to have either Supervisor or Unrestricted access by programming the SUPV bit in the MCR. These registers are identified as S/U in the Access column of Table 22-2. The IFLAG2 and IMASK2 registers are considered reserved space when FlexCAN is configured with 16 or 32 MBs. The Rx Global Mask (RXGMASK), Rx Buffer 14 Mask (RX14MASK) and the Rx Buffer 15 Mask (RX15MASK) registers are provided for backwards compatibility, and are not used when the BCC bit in MCR is asserted. The address ranges 0x0060–0x047F and 0x0880–0x097F are occupied by two separate embedded memories. These two ranges are completely occupied by SRAM (1056 and 256 bytes, respectively) only when FlexCAN is configured with 64 MBs. When it is configured with 16 MBs, the memory sizes are 288 and 64 bytes, so the address ranges 0x0180–0x047F and 0x08C0–0x097F are considered reserved space. MPC5604B/C Microcontroller Reference Manual, Rev. 8 426 Freescale Semiconductor When it is configured with 32 MBs, the memory sizes are 544 and 128 bytes, so the address ranges 0x0280–0x047F and 0x0900–0x097F are considered reserved space. Furthermore, if the BCC bit in MCR is negated, then the whole Rx Individual Mask Registers address range (0x0880–0x097F) is considered reserved space. Table 22-2. FlexCAN memory map Address offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034–0x005F 0x0060–0x007F 0x0080–0x017F 0x0180–0x027F 0x0280–0x047F 0x0480–0x087F 0x0880–0x08BF 0x08C0–0x08FF 0x0900–0x097F Base addresses: 0xFFFC_0000 (FlexCAN_0) 0xFFFC_4000 (FlexCAN_1) 0xFFFC_8000 (FlexCAN_2) 0xFFFC_C000 (FlexCAN_3) 0xFFFD_0000 (FlexCAN_4) 0xFFFD_4000 (FlexCAN_5) Register Module Configuration (MCR) Control Register (CTRL) Free Running Timer (TIMER) Reserved Rx Global Mask (RXGMASK) Rx Buffer 14 Mask (RX14MASK) Rx Buffer 15 Mask (RX15MASK) Error Counter Register (ECR) Error and Status Register (ESR) Interrupt Masks 2 (IMASK2) Interrupt Masks 1 (IMASK1) Interrupt Flags 2 (IFLAG2) Interrupt Flags 1 (IFLAG1) Reserved Reserved Message Buffers MB0–MB15 Message Buffers MB16–MB31 Message Buffers MB32–MB63 Reserved Rx Individual Mask Registers RXIMR0–RXIMR15 Rx Individual Mask Registers RXIMR16–RXIMR31 Rx Individual Mask Registers RXIMR32–RXIMR63 Location on page 433 on page 437 on page 440 on page 441 on page 442 on page 443 on page 443 on page 444 on page 447 on page 448 on page 448 on page 449 on page 450 on page 450 on page 450 The FlexCAN module stores CAN messages for transmission and reception using a Message Buffer structure. Each individual MB is formed by 16 bytes mapped on memory as described in Table 22-3. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 427 Table 22-3 shows a Standard/Extended Message Buffer (MB0) memory map, using 16 bytes total (0x80–0x8F space). Table 22-3. Message buffer MB0 memory mapping Address offset 0x80 0x84 0x88–0x8F MB field Control and Status (C/S) Identifier Field Data Field 0 – Data Field 7 (1 byte each) 22.3.2 Message buffer structure The Message Buffer structure used by the FlexCAN module is represented in Table 22-2. Both Extended and Standard Frames (29-bit Identifier and 11-bit Identifier, respectively) used in the CAN specification (Version 2.0 Part B) are represented. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SRR IDE RTR 0x0 CODE LENGTH 0x4 PRIO ID (Standard/Extended) 0x8 Data Byte 0 Data Byte 1 0x Data Byte 4 C Data Byte 5 TIME STAMP ID (Extended) Data Byte 2 Data Byte 6 Data Byte 3 Data Byte 7 = Unimplemented or Reserved Figure 22-2. Message Buffer Structure Table 22-4. Message Buffer Structure field description Field CODE SRR IDE Description Message Buffer Code This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. The encoding is shown in Table 22-5 and Table 22-6. See Section 22.4, “Functional description for additional information. Substitute Remote Request Fixed recessive bit, used only in extended format. It must be set to ‘1’ by the user for transmission (Tx Buffers) and will be stored with the value received on the CAN bus for Rx receiving buffers. It can be received as either recessive or dominant. If FlexCAN receives this bit as dominant, then it is interpreted as arbitration loss. 1 = Recessive value is compulsory for transmission in Extended Format frames 0 = Dominant is not a valid value for transmission in Extended Format frames ID Extended Bit This bit identifies whether the frame format is standard or extended. 1 = Frame format is extended 0 = Frame format is standard MPC5604B/C Microcontroller Reference Manual, Rev. 8 428 Freescale Semiconductor Table 22-4. Message Buffer Structure field description (continued) Field Description RTR Remote Transmission Request This bit is used for requesting transmissions of a data frame. If FlexCAN transmits this bit as ‘1’ (recessive) and receives it as ‘0’ (dominant), it is interpreted as arbitration loss. If this bit is transmitted as ‘0’ (dominant), then if it is received as ‘1’ (recessive), the FlexCAN module treats it as bit error. If the value received matches the value transmitted, it is considered as a successful bit transmission. 1 = Indicates the current MB has a Remote Frame to be transmitted 0 = Indicates the current MB has a Data Frame to be transmitted LENGTH Length of Data in Bytes This 4-bit field is the length (in bytes) of the Rx or Tx data, which is located in offset 0x8 through 0xF of the MB space (see Table 22-2). In reception, this field is written by the FlexCAN module, copied from the DLC (Data Length Code) field of the received frame. In transmission, this field is written by the CPU and corresponds to the DLC field value of the frame to be transmitted. When RTR=1, the Frame to be transmitted is a Remote Frame and does not include the data field, regardless of the Length field. TIME STAMP Free-Running Counter Time Stamp This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. PRIO Local priority This 3-bit field is only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. See Section 22.4.4, “Arbitration process. ID Frame Identifier In Standard Frame format, only the 11 most significant bits (3 to 13) are used for frame identification in both receive and transmit cases. The 18 least significant bits are ignored. In Extended Frame format, all bits are used for frame identification in both receive and transmit cases. DATA Data Field Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from the CAN bus. For Tx frames, the CPU prepares the data field to be transmitted within the frame. Table 22-5. Message buffer code for Rx buffers Rx code BEFORE Rx new frame Description 0000 INACTIVE: MB is not active. 0100 EMPTY: MB is active and empty. Rx code AFTER Rx new frame Comment — 0010 MB does not participate in the matching process. MB participates in the matching process. When a frame is received successfully, the code is automatically updated to FULL. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 429 Table 22-5. Message buffer code for Rx buffers (continued) Rx code BEFORE Rx new frame Description Rx code AFTER Rx new frame Comment 0010 FULL: MB is full. 0010 The act of reading the C/S word followed by unlocking the MB does not make the code return to EMPTY. It remains FULL. If a new frame is written to the MB after the C/S word was read and the MB was unlocked, the code still remains FULL. 0110 If the MB is FULL and a new frame is overwritten to this MB before the CPU had time to read it, the code is automatically updated to OVERRUN. Refer to Section 22.4.6, “Matching process for details about overrun behavior. 0110 OVERRUN: a frame was overwritten into a full buffer. 0010 If the code indicates OVERRUN but the CPU reads the C/S word and then unlocks the MB, when a new frame is written to the MB the code returns to FULL. 0110 If the code already indicates OVERRUN, and yet another new frame must be written, the MB will be overwritten again, and the code will remain OVERRUN. Refer to Section 22.4.6, “Matching process for details about overrun behavior. 0XY11 BUSY: FlexCAN is updating the contents of the MB. The CPU must not access the MB. 0010 0110 An EMPTY buffer was written with a new frame (XY was 01). A FULL/OVERRUN buffer was overwritten (XY was 11). 1 Note that for Tx MBs (see Table 22-6), the BUSY bit should be ignored upon read, except when AEN bit is set in the MCR. RTR X X 0 1 Initial Tx code 1000 1001 1100 1100 Table 22-6. Message buffer code for Tx buffers Code after successful transmission — — 1000 0100 Description INACTIVE: MB does not participate in the arbitration process. ABORT: MB was configured as Tx and CPU aborted the transmission. This code is only valid when AEN bit in MCR is asserted. MB does not participate in the arbitration process. Transmit data frame unconditionally once. After transmission, the MB automatically returns to the INACTIVE state. Transmit remote frame unconditionally once. After transmission, the MB automatically becomes an Rx MB with the same ID. MPC5604B/C Microcontroller Reference Manual, Rev. 8 430 Freescale Semiconductor RTR 0 0 Table 22-6. Message buffer code for Tx buffers (continued) Initial Tx code 1010 1110 Code after successful transmission 1010 1010 Description Transmit a data frame whenever a remote request frame with the same ID is received. This MB participates simultaneously in both the matching and arbitration processes. The matching process compares the ID of the incoming remote request frame with the ID of the MB. If a match occurs this MB is allowed to participate in the current arbitration process and the Code field is automatically updated to ‘1110’ to allow the MB to participate in future arbitration runs. When the frame is eventually transmitted successfully, the Code automatically returns to ‘1010’ to restart the process again. This is an intermediate code that is automatically written to the MB by the MBM as a result of match to a remote request frame. The data frame will be transmitted unconditionally once and then the code will automatically return to ‘1010’. The CPU can also write this code with the same effect. 22.3.3 Rx FIFO structure When the FEN bit is set in the MCR, the memory area from 0x80 to 0xFC (which is normally occupied by MBs 0 to 7) is used by the reception FIFO engine. Table 22-3 shows the Rx FIFO data structure. The region 0x80–0x8C contains an MB structure which is the port through which the CPU reads data from the FIFO (the oldest frame received and not read yet). The region 0x90–0xDC is reserved for internal use of the FIFO engine. The region 0xE0–0xFC contains an 8-entry ID table that specifies filtering criteria for accepting frames into the FIFO. Table 22-4 shows the three different formats that the elements of the ID table can assume, depending on the IDAM field of the MCR. Note that all elements of the table must have the same format. See Section 22.4.8, “Rx FIFO for more information. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 431 SRR IDE RTR REM EXT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x80 0x84 0x88 0x8C 0x90 to 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC LENGTH ID (Standard/Extended) Data Byte 0 Data Byte 1 Data Byte 4 Data Byte 5 Reserved TIME STAMP ID (Extended) Data Byte 2 Data Byte 3 Data Byte 6 Data Byte 7 ID Table 0 ID Table 1 ID Table 2 ID Table 3 ID Table 4 ID Table 5 ID Table 6 ID Table 7 = Unimplemented or Reserved Figure 22-3. Rx FIFO Structure 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 REM EXT A RXIDA (Standard = 2-12, Extended = 2-30) REM EXT B RXIDB_0 (Standard =2-12, Extended = 2-15) RXIDB_1 (Standard = 18-28, Extended = 18-31) C RXIDC_0 (Std/Ext = 0-7) RXIDC_1 (Std/Ext = 8-15) RXIDC_2 (Std/Ext = 16-23) = Unimplemented or Reserved Figure 22-4. ID Table 0 – 7 RXIDC_3 (Std/Ext = 24-31) MPC5604B/C Microcontroller Reference Manual, Rev. 8 432 Freescale Semiconductor Table 22-7. Rx FIFO Structure field description Field REM EXT RXIDA RXIDB_0, RXIDB_1 RXIDC_0, RXIDC_1, RXIDC_2, RXIDC_3 Description Remote Frame This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID. 1 = Remote Frames can be accepted and data frames are rejected 0 = Remote Frames are rejected and data frames can be accepted Extended Frame Specifies whether extended or standard frames are accepted into the FIFO if they match the target ID. 1 = Extended frames can be accepted and standard frames are rejected 0 = Extended frames are rejected and standard frames can be accepted Rx Frame Identifier (Format A) Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format, only the 11 most significant bits (3 to 13)are used for frame identification. In the extended frame format, all bits are used. Rx Frame Identifier (Format B) Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format, the 11 most significant bits (a full standard ID) (3 to 13)are used for frame identification. In the extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received ID. Rx Frame Identifier (Format C) Specifies an ID to be used as acceptance criteria for the FIFO. In both standard and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received ID. 22.3.4 Register description The FlexCAN registers are described in this section in ascending address order. 22.3.4.1 Module Configuration Register (MCR) This register defines global system configurations, such as the module operation mode (e.g., low power) and maximum message buffer configuration. This register can be accessed at any time, however some fields must be changed only during Freeze Mode. Find more information in the fields descriptions ahead. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 433 Offset: 0x0000 Access: Read/write MDIS HALT NOT_RDY SOFT_RST FRZ_ACK SUPV WRN_EN LPM_ACK SRX_DIS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 FRZ FEN 0 00 BCC W Reset Note 1 1 0 1 1 0 0 Note 2 1 0 0 Note 3 0 0 0 0 LPRIO_EN 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 00 00 W AEN IDAM MAXMB Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Figure 22-5. Module Configuration Register (MCR) 1 Reset value of this bit is different on various platforms. Consult the specific MCU documentation to determine its value. 2 Different on various platforms, but it is always the opposite of the MDIS reset value. 3 Different on various platforms, but it is always the same as the MDIS reset value. Field MDIS FRZ FEN Table 22-8. MCR field descriptions Description Module Disable This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the clocks to the CAN Protocol Interface and Message Buffer Management submodules. This is the only bit in MCR not affected by soft reset. See Section 22.4.10.2, “Module Disable Mode for more information. 1 = Disable the FlexCAN module 0 = Enable the FlexCAN module Freeze Enable The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR is set or when Debug Mode is requested at MCU level. When FRZ is asserted, FlexCAN is enabled to enter Freeze Mode. Negation of this bit field causes FlexCAN to exit from Freeze Mode. 1 = Enabled to enter Freeze Mode 0 = Not enabled to enter Freeze Mode FIFO Enable This bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region (0x80–0xFF) is used by the FIFO engine. See Section 22.3.3, “Rx FIFO structure and Section 22.4.8, “Rx FIFO for more information. This bit must be written in Freeze mode only. 1 = FIFO enabled 0 = FIFO not enabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 434 Freescale Semiconductor Table 22-8. MCR field descriptions (continued) Field Description HALT Halt FlexCAN Assertion of this bit puts the FlexCAN module into Freeze Mode. The CPU should clear it after initializing the Message Buffers and Control Register. No reception or transmission is performed by FlexCAN before this bit is cleared. While in Freeze Mode, the CPU has write access to the Error Counter Register, that is otherwise read-only. Freeze Mode cannot be entered while FlexCAN is in the low power mode. See Section 22.4.10.1, “Freeze Mode for more information. 1 = Enters Freeze Mode if the FRZ bit is asserted. 0 = No Freeze Mode request. NOT_RDY FlexCAN Not Ready This read-only bit indicates that FlexCAN is either in Disable Mode or Freeze Mode. It is negated once FlexCAN has exited these modes. 1 = FlexCAN module is either in Disable Mode or Freeze Mode 0 = FlexCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode SOFT_RST Soft Reset When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers. The following registers are reset: MCR (except the MDIS bit), TIMER, ECR, ESR, IMASK1, IMASK2, IFLAG1, IFLAG2. Configuration registers that control the interface to the CAN bus are not affected by soft reset. The following registers are unaffected: • CTRL • RXIMR0–RXIMR63 • RXGMASK, RX14MASK, RX15MASK • all Message Buffers The SOFT_RST bit can be asserted directly by the CPU when it writes to the MCR, but it is also asserted when global soft reset is requested at MCU level. Since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. The SOFT_RST bit remains asserted while reset is pending, and is automatically negated when reset completes. Therefore, software can poll this bit to know when the soft reset has completed. Soft reset cannot be applied while clocks are shut down in the low power mode. The module should be first removed from low power mode, and then soft reset can be applied. 1 = Resets the registers marked as “affected by soft reset” in Table 22-2 0 = No reset request FRZ_ACK Freeze Mode Acknowledge This read-only bit indicates that FlexCAN is in Freeze Mode and its prescaler is stopped. The Freeze Mode request cannot be granted until current transmission or reception processes have finished. Therefore the software can poll the FRZ_ACK bit to know when FlexCAN has actually entered Freeze Mode. If Freeze Mode request is negated, then this bit is negated once the FlexCAN prescaler is running again. If Freeze Mode is requested while FlexCAN is in the low power mode, then the FRZ_ACK bit will only be set when the low power mode is exited. See Section 22.4.10.1, “Freeze Mode for more information. 1 = FlexCAN in Freeze Mode, prescaler stopped 0 = FlexCAN not in Freeze Mode, prescaler running SUPV Supervisor Mode This bit configures some of the FlexCAN registers to be either in Supervisor or Unrestricted memory space. The registers affected by this bit are marked as S/U in the Access Type column of Table 22-2. Reset value of this bit is ‘1’, so the affected registers start with Supervisor access restrictions.This bit should be written in Freeze mode only. 1 = Affected registers are in Supervisor memory space. Any access without supervisor permission behaves as though the access was done to an unimplemented register location 0 = Affected registers are in Unrestricted memory space MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 435 Table 22-8. MCR field descriptions (continued) Field Description WRN_EN LPM_ACK SRX_DIS BCC LPRIO_EN 19 AEN Warning Interrupt Enable When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated. This bit must be written in Freeze mode only. 1 = TWRN_INT and RWRN_INT bits are set when the respective error counter transition from < 96 to  96. 0 = TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. Low Power Mode Acknowledge This read-only bit indicates that FlexCAN is in Disable Mode. This low power mode cannot be entered until all current transmission or reception processes have finished, so the CPU can poll the LPM_ACK bit to know when FlexCAN has actually entered low power mode. See Section 22.4.10.2, “Module Disable Mode for more information. 1 = FlexCAN is in Disable Mode. 0 = FlexCAN is not in Disable Mode Self Reception Disable This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this bit is asserted, frames transmitted by the module will not be stored in any MB, regardless if the MB is programmed with an ID that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due to the frame reception. This bit must be written in Freeze mode only. 1 = Self reception disabled 0 = Self reception enabled Backwards Compatibility Configuration This bit is provided to support Backwards Compatibility with previous FlexCAN versions. When this bit is negated, the following configuration is applied: • For MCUs supporting individual Rx ID masking, this feature is disabled. Instead of individual ID masking per MB, FlexCAN uses its previous masking scheme with RXGMASK, RX14MASK and RX15MASK. • The reception queue feature is disabled. Upon receiving a message, if the first MB with a matching ID that is found is still occupied by a previous unread message, FlexCAN will not look for another matching MB. It will override this MB with the new message and set the CODE field to ‘0110’ (overrun). Upon reset this bit is negated, allowing legacy software to work without modification. This bit must be written in Freeze mode only. 1 = Individual Rx masking and queue feature are enabled. 0 = Individual Rx masking and queue feature are disabled. Local Priority Enable This bit is provided for backwards compatibility reasons. It controls whether the local priority feature is enabled or not. It is used to extend the ID used during the arbitration process. With this extended ID concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted ID still has 11-bit for standard frames and 29-bit for extended frames. This bit must be written in Freeze mode only. 1 = Local Priority enabled 0 = Local Priority disabled Abort Enable This bit is supplied for backwards compatibility reasons. When asserted, it enables the Tx abort feature. This feature guarantees a safe procedure for aborting a pending transmission, so that no frame is sent in the CAN bus without notification. This bit must be written in Freeze mode only. 1 = Abort enabled 0 = Abort disabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 436 Freescale Semiconductor Field IDAM MAXMB Table 22-8. MCR field descriptions (continued) Description ID Acceptance Mode This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown in Table 22-9. Note that all elements of the table are configured at the same time by this field (they are all the same format). See Section 22.3.3, “Rx FIFO structure. This bit must be written in Freeze mode only. Maximum Number of Message Buffers This 6-bit field defines the maximum number of message buffers that will take part in the matching and arbitration processes. The reset value (0x0F) is equivalent to 16 MB configuration. This field must be changed only while the module is in Freeze Mode. Maximum MBs in use = MAXMB + 1 Note: MAXMB must be programmed with a value smaller or equal to the number of available Message Buffers, otherwise FlexCAN can transmit and receive wrong messages. IDAM 00 01 10 11 Format A B C D Table 22-9. IDAM coding Explanation One full ID (standard or extended) per filter element Two full standard IDs or two partial 14-bit extended IDs per filter element Four partial 8-bit IDs (standard or extended) per filter element All frames rejected 22.3.4.2 Control Register (CTRL) This register is defined for specific FlexCAN control features related to the CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop-Back Mode, Listen-Only Mode, Bus Off recovery behavior and interrupt enabling (Bus-Off, Error, Warning). It also determines the Division Factor for the clock prescaler. This register can be accessed at any time, however some fields must be changed only during either Disable Mode or Freeze Mode. Find more information in the fields descriptions ahead. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 437 Offset: 0x0004 0 1 2 3 4 5 R PRESDIV W Reset 0 0 0 0 0 0 Access: Read/write 6 7 8 9 10 11 12 13 14 15 RJW PSEG1 PSEG2 0000000000 BOFF_MSK ERR_ MSK CLK_SRC TWRN_MSK RWRN_MSK BOFF_REC TSYN LBUF 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 00 W LPB SMP LOM PROPSEG Reset 0 0 0 0 0 0 0000000000 Figure 22-6. Control Register (CTRL) Table 22-10. CTRL field descriptions Field Description PRESDIV Prescaler Division Factor This field defines the ratio between the CPI clock frequency and the Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value, the Sclock frequency is equal to the CPI clock frequency. The Maximum value of this register is 0xFF, that gives a minimum Sclock frequency equal to the CPI clock frequency divided by 256. For more information refer to Section 22.4.9.4, “Protocol timing. This bit must be written in Freeze mode only. Sclock frequency = CPI clock frequency / (PRESDIV + 1) RJW Resync Jump Width This field defines the maximum number of time quanta1 that a bit time can be changed by one resynchronization. The valid programmable values are 0–3. This bit must be written in Freeze mode only. Resync Jump Width = RJW + 1. PSEG1 PSEG1 — Phase Segment 1 This field defines the length of Phase Buffer Segment 1 in the bit time. The valid programmable values are 0–7. This bit must be written in Freeze mode only. Phase Buffer Segment 1 = (PSEG1 + 1) x Time-Quanta. PSEG2 PSEG2 — Phase Segment 2 This field defines the length of Phase Buffer Segment 2 in the bit time. The valid programmable values are 1–7. This bit must be written in Freeze mode only. Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta. BOFF_MSK Bus Off Mask This bit provides a mask for the Bus Off Interrupt. 1= Bus Off interrupt enabled 0 = Bus Off interrupt disabled ERR_MSK Error Mask This bit provides a mask for the Error Interrupt. 1 = Error interrupt enabled 0 = Error interrupt disabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 438 Freescale Semiconductor Table 22-10. CTRL field descriptions (continued) Field CLK_SRC Description CAN Engine Clock Source This bit selects the clock source to the CAN Protocol Interface (CPI) to be either the peripheral clock (driven by the FMPLL) or the crystal oscillator clock. The selected clock is the one fed to the prescaler to generate the Serial Clock (Sclock). In order to guarantee reliable operation, this bit should only be changed while the module is in Disable Mode. See Section 22.4.9.4, “Protocol timing for more information. 1 = The CAN engine clock source is the bus clock 0 = The CAN engine clock source is the oscillator clock Note: This clock selection feature may not be available in all MCUs. A particular MCU may not have a FMPLL, in which case it would have only the oscillator clock, or it may use only the FMPLL clock feeding the FlexCAN module. In these cases, this bit has no effect on the module operation. LPB Loop Back This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an internal loop back that can be used for self test operation. The bit stream output of the transmitter is fed back internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive state (logic ‘1’). FlexCAN behaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. Both transmit and receive interrupts are generated. This bit must be written in Freeze mode only. 1 = Loop Back enabled 0 = Loop Back disabled TWRN_MSK Tx Warning Interrupt Mask This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register. This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is negated. 1 = Tx Warning Interrupt enabled 0 = Tx Warning Interrupt disabled RWRN_MSK Rx Warning Interrupt Mask This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register. This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is negated. 1 = Rx Warning Interrupt enabled 0 = Rx Warning Interrupt disabled SMP Sampling Mode This bit defines the sampling mode of CAN bits at the Rx input. This bit must be written in Freeze mode only. 1 = Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples, a majority rule is used 0 = Just one sample is used to determine the bit value MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 439 Table 22-10. CTRL field descriptions (continued) Field Description BOFF_REC Bus Off Recovery Mode This bit defines how FlexCAN recovers from Bus Off state. If this bit is negated, automatic recovering from Bus Off state occurs according to the CAN Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is disabled and the module remains in Bus Off state until the bit is negated by the user. If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus, then Bus Off recovery happens as if the BOFF_REC bit had never been asserted. If the negation occurs after 128 sequences of 11 recessive bits occurred, then FlexCAN will resynchronize to the bus by waiting for 11 recessive bits before joining the bus. After negation, the BOFF_REC bit can be re-asserted again during Bus Off, but it will only be effective the next time the module enters Bus Off. If BOFF_REC was negated when the module entered Bus Off, asserting it during Bus Off will not be effective for the current Bus Off recovery. 1 = Automatic recovering from Bus Off state disabled 0 = Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B TSYN Timer Sync Mode This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0. This feature provides means to synchronize multiple FlexCAN stations with a special “SYNC” message (that is, global network time). If the FEN bit in MCR is set (FIFO enabled), MB8 is used for timer synchronization instead of MB0. This bit must be written in Freeze mode only. 1 = Timer Sync feature enabled 0 = Timer Sync feature disabled LBUF Lowest Buffer Transmitted First This bit defines the ordering mechanism for Message Buffer transmission. When asserted, the LPRIO_EN bit does not affect the priority arbitration. This bit must be written in Freeze mode only. 1 = Lowest number buffer is transmitted first 0 = Buffer with highest priority is transmitted first LOM Listen-Only Mode This bit configures FlexCAN to operate in Listen-Only Mode. In this mode, transmission is disabled, all error counters are frozen and the module operates in a CAN Error Passive mode. Only messages acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the message. This bit must be written in Freeze mode only. 1 = FlexCAN module operates in Listen-Only Mode 0 = Listen-Only Mode is deactivated PROPSEG Propagation Segment This field defines the length of the Propagation Segment in the bit time. The valid programmable values are 0–7. This bit must be written in Freeze mode only. Propagation Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period. 1 One time quantum is equal to the Sclock period. 22.3.4.3 Free Running Timer (TIMER) This register represents a 16-bit free running counter that can be read and written by the CPU. The timer starts from 0x0000 after Reset, counts linearly to 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on the CAN bus). During a message transmission/reception, it increments by one for each bit that is received or transmitted. When MPC5604B/C Microcontroller Reference Manual, Rev. 8 440 Freescale Semiconductor there is no message on the bus, it counts using the previously programmed baud rate. During Freeze Mode, the timer is not incremented. The timer value is captured at the beginning of the identifier field of any frame on the CAN bus. This captured value is written into the Time Stamp entry in a message buffer after a successful reception or transmission of a message. Writing to the timer is an indirect operation. The data is first written to an auxiliary register and then an internal request/acknowledge procedure across clock domains is executed. All this is transparent to the user, except for the fact that the data will take some time to be actually written to the register. If desired, software can poll the register to discover when the data was actually written. Offset: 0x0008 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TIMER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-7. Free Running Timer (TIMER) 22.3.4.4 Rx Global Mask (RXGMASK) This register is provided for legacy support and for low cost MCUs that do not have the individual masking per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR causes the RXGMASK Register to have no effect on the module operation. For MCUs not supporting individual masks per MB, this register is always effective. RXGMASK is used as acceptance mask for all Rx MBs, excluding MBs 14–15, which have individual mask registers. When the FEN bit in MCR is set (FIFO enabled), the RXGMASK also applies to all elements of the ID filter table, except elements 6–7, which have individual masks. Refer to Section 22.4.8, “Rx FIFO for important details on usage of RXGMASK on filtering process for Rx FIFO. The contents of this register must be programmed while the module is in Freeze Mode, and must not be modified when the module is transmitting or receiving frames. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 441 Offset: 0x0010 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0 W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 22-8. Rx Global Mask Register (RXGMASK) Table 22-11. RXGMASK field description Field MI31–MI0 Description Mask Bits For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the mask bits affect all bits programmed in the filter table (ID, IDE, RTR). 1 = The corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is “don’t care” 22.3.4.5 Rx 14 Mask (RX14MASK) This register is provided for legacy support and for low cost MCUs that do not have the individual masking per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR causes the RX14MASK Register to have no effect on the module operation. RX14MASK is used as acceptance mask for the Identifier in Message Buffer 14. When the FEN bit in MCR is set (FIFO enabled), the RXG14MASK also applies to element 6 of the ID filter table. This register has the same structure as the Rx Global Mask Register. Refer to Section 22.4.8, “Rx FIFO for important details on usage of RX14MASK on filtering process for Rx FIFO. It must be programmed while the module is in Freeze Mode, and must not be modified when the module is transmitting or receiving frames. • Address Offset: 0x14 • Reset Value: 0xFFFF_FFFF MPC5604B/C Microcontroller Reference Manual, Rev. 8 442 Freescale Semiconductor 22.3.4.6 Rx 15 Mask (RX15MASK) This register is provided for legacy support and for low cost MCUs that do not have the individual masking per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR causes the RX15MASK Register to have no effect on the module operation. When the BCC bit is negated, RX15MASK is used as acceptance mask for the Identifier in Message Buffer 15. When the FEN bit in MCR is set (FIFO enabled), the RXG14MASK also applies to element 7 of the ID filter table. This register has the same structure as the Rx Global Mask Register. See Section 22.4.8, “Rx FIFO for important details on usage of RXG15MASK on filtering process for Rx FIFO. It must be programmed while the module is in Freeze Mode, and must not be modified when the module is transmitting or receiving frames. • Address Offset: 0x18 • Reset Value: 0xFFFF_FFFF 22.3.4.7 Error Counter Register (ECR) This register has two 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error Counter (TX_ERR_COUNTER field) and Receive Error Counter (RX_ERR_COUNTER field). The rules for increasing and decreasing these counters are described in the CAN protocol and are completely implemented in the FlexCAN module. Both counters are read only except in Freeze Mode, where they can be written by the CPU. Writing to the Error Counter Register while in Freeze Mode is an indirect operation. The data is first written to an auxiliary register and then an internal request/acknowledge procedure across clock domains is executed. All this is transparent to the user, except for the fact that the data will take some time to be actually written to the register. If desired, software can poll the register to discover when the data was actually written. FlexCAN responds to any bus state as described in the protocol, e.g. transmit ‘Error Active’ or ‘Error Passive’ flag, delay its transmission start time (‘Error Passive’) and avoid any influence on the bus when in ‘Bus Off’ state. The following are the basic rules for FlexCAN bus state transitions. • If the value of TX_ERR_COUNTER or RX_ERR_COUNTER increases to be greater than or equal to 128, the FLT_CONF field in the Error and Status Register is updated to reflect ‘Error Passive’ state. • If the FlexCAN state is ‘Error Passive’, and either TX_ERR_COUNTER or RX_ERR_COUNTER decrements to a value less than or equal to 127 while the other already satisfies this condition, the FLT_CONF field in the Error and Status Register is updated to reflect ‘Error Active’ state. • If the value of TX_ERR_COUNTER increases to be greater than 255, the FLT_CONF field in the Error and Status Register is updated to reflect ‘Bus Off’ state, and an interrupt may be issued. The value of TX_ERR_COUNTER is then reset to zero. • If FlexCAN is in ‘Bus Off’ state, then TX_ERR_COUNTER is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, TX_ERR_COUNTER is reset to zero and counts in a manner where the internal counter counts 11 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 443 such bits and then wraps around while incrementing the TX_ERR_COUNTER. When TX_ERR_COUNTER reaches the value of 128, the FLT_CONF field in the Error and Status Register is updated to be ‘Error Active’ and both error counters are reset to zero. At any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without affecting the TX_ERR_COUNTER value. • If during system start-up, only one node is operating, then its TX_ERR_COUNTER increases in each message it is trying to transmit, as a result of acknowledge errors (indicated by the ACK_ERR bit in the Error and Status Register). After the transition to ‘Error Passive’ state, the TX_ERR_COUNTER does not increment anymore by acknowledge errors. Therefore the device never goes to the ‘Bus Off’ state. • If the RX_ERR_COUNTER increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. At the next successful message reception, the counter is set to a value between 119 and 127 to resume to ‘Error Active’ state. Offset: 0x001C Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RX_ERR_COUNTER W TX_ERR_COUNTER Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-9. Error Counter Register (ECR) 22.3.4.8 Error and Status Register (ESR) This register reflects various error conditions, some general status of the device and it is the source of four interrupts to the CPU. The reported error conditions (bits 16–21) are those that occurred since the last time the CPU read this register. The CPU read action clears bits 16–23. Bits 22–28 are status bits. Most bits in this register are read only, except TWRN_INT, RWRN_INT, BOFF_INT, WAK_INT and ERR_INT, that are interrupt flags that can be cleared by writing ‘1’ to them (writing ‘0’ has no effect). See Section 22.4.11, “Interrupts for more details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 444 Freescale Semiconductor Offset: 0x0020 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 W TWRN_INT RWRN_INT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOFF_INT ERR_ INT BIT1_ ERR BIT0_ ERR ACK_ ERR CRC_ERR FRM_ERR STF_ERR TX_WRN RX_WRN TXRX 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IDLE FLT_CONF 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 22-10. Error and Status Register (ESR) Table 22-12. ESR field descriptions Field Description TWRN_INT Tx Warning Interrupt Flag If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from ‘0’ to ‘1’, meaning that the Tx error counter reached 96. If the corresponding mask bit in the Control Register (TWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’. Writing ‘0’ has no effect. 1 = The Tx error counter transition from < 96 to  96 0 = No such occurrence RWRN_INT Rx Warning Interrupt Flag If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from ‘0’ to ‘1’, meaning that the Rx error counters reached 96. If the corresponding mask bit in the Control Register (RWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’. Writing ‘0’ has no effect. 1 = The Rx error counter transition from < 96 to  96 0 = No such occurrence BIT1_ERR Bit1 Error This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = At least one bit sent as recessive is received as dominant 0 = No such occurrence Note: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node sending a passive error flag that detects dominant bits. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 445 Table 22-12. ESR field descriptions (continued) Field Description BIT0_ERR ACK_ERR CRC_ERR FRM_ERR STF_ERR TX_WRN RX_WRN IDLE TXRX FLT_CONF Bit0 Error This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = At least one bit sent as dominant is received as recessive 0 = No such occurrence Acknowledge Error This bit indicates that an Acknowledge Error has been detected by the transmitter node, i.e., a dominant bit has not been detected during the ACK SLOT. 1 = An ACK error occurred since last read of this register 0 = No such occurrence Cyclic Redundancy Check Error This bit indicates that a CRC Error has been detected by the receiver node, i.e., the calculated CRC is different from the received. 1 = A CRC error occurred since last read of this register. 0 = No such occurrence Form Error This bit indicates that a Form Error has been detected by the receiver node, i.e., a fixed-form bit field contains at least one illegal bit. 1 = A Form Error occurred since last read of this register 0 = No such occurrence Stuffing Error This bit indicates that a Stuffing Error has been detected. 1 = A Stuffing Error occurred since last read of this register. 0 = No such occurrence. TX Error Warning This bit indicates when repetitive errors are occurring during message transmission. 1 = TX_Err_Counter  96 0 = No such occurrence Rx Error Warning This bit indicates when repetitive errors are occurring during message reception. 1 = Rx_Err_Counter 96 0 = No such occurrence CAN bus IDLE state This bit indicates when CAN bus is in IDLE state. 1 = CAN bus is now IDLE 0 = No such occurrence Current FlexCAN status (transmitting/receiving) This bit indicates if FlexCAN is transmitting or receiving a message when the CAN bus is not in IDLE state. This bit has no meaning when IDLE is asserted. 1 = FlexCAN is transmitting a message (IDLE = 0) 0 = FlexCAN is receiving a message (IDLE = 0) Fault Confinement State This field indicates the Confinement State of the FlexCAN module, as shown in Table 22-13. If the LOM bit in the Control Register is asserted, the FLT_CONF field will indicate “Error Passive”. Since the Control Register is not affected by soft reset, the FLT_CONF field will not be affected by soft reset if the LOM bit is asserted. MPC5604B/C Microcontroller Reference Manual, Rev. 8 446 Freescale Semiconductor Table 22-12. ESR field descriptions (continued) Field Description BOFF_INT ERR_INT Bus Off’ Interrupt This bit is set when FlexCAN enters ‘Bus Off’ state. If the corresponding mask bit in the Control Register (BOFF_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’. Writing ‘0’ has no effect. 1 = FlexCAN module entered ‘Bus Off’ state 0 = No such occurrence Error Interrupt This bit indicates that at least one of the Error Bits (bits 16–21) is set. If the corresponding mask bit in the Control Register (ERR_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’.Writing ‘0’ has no effect. 1 = Indicates setting of any Error Bit in the Error and Status Register 0 = No such occurrence Value 00 01 1X Table 22-13. Fault confinement state Meaning Error Active Error Passive Bus Off 22.3.4.9 Interrupt Masks 2 Register (IMASK2) This register allows any number of a range of 32 Message Buffer Interrupts to be enabled or disabled. It contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an interrupt after a successful transmission or reception (i.e. when the corresponding IFLAG2 bit is set). Offset: 0x0024 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF W 63M 62M 61M 60M 59M 58M 57M 56M 55M 54M 53M 52M 51M 50M 49M 48M Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF W 47M 46M 45M 44M 43M 42M 41M 40M 39M 38M 37M 36M 35M 34M 33M 32M Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-11. Interrupt Masks 2 Register (IMASK2) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 447 Table 22-14. IMASK2 field descriptions Field Description BUF63M – BUF32M Buffer MBi Mask Each bit enables or disables the respective FlexCAN Message Buffer (MB32 to MB63) Interrupt. 1 = The corresponding buffer Interrupt is enabled 0 = The corresponding buffer Interrupt is disabled Note: Setting or clearing a bit in the IMASK2 Register can assert or negate an interrupt request, if the corresponding IFLAG2 bit is set. 22.3.4.10 Interrupt Masks 1 Register (IMASK1) This register allows to enable or disable any number of a range of 32 Message Buffer Interrupts. It contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an interrupt after a successful transmission or reception (i.e., when the corresponding IFLAG1 bit is set). Offset: 0x0028 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF W 31M 30M 29M 28M 27M 26M 25M 24M 23M 22M 21M 20M 19M 18M 17M 16M Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF W 15M 14M 13M 12M 11M 10M 9M 8M 7M 6M 5M 4M 3M 2M 1M 0M Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-12. Interrupt Masks 1 Register (IMASK1) Table 22-15. IMASK1 field descriptions Field Description BUF31M – BUF0M BUF31M–BUF0M — Buffer MBi Mask Each bit enables or disables the respective FlexCAN Message Buffer (MB0 to MB31) Interrupt. 1 = The corresponding buffer Interrupt is enabled 0 = The corresponding buffer Interrupt is disabled Note: Setting or clearing a bit in the IMASK1 Register can assert or negate an interrupt request, if the corresponding IFLAG1 bit is set. 22.3.4.11 Interrupt Flags 2 Register (IFLAG2) This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG2 bit. If the corresponding MPC5604B/C Microcontroller Reference Manual, Rev. 8 448 Freescale Semiconductor IMASK2 bit is set, an interrupt will be generated. The interrupt flag must be cleared by writing it to ‘1’. Writing ‘0’ has no effect. When the AEN bit in the MCR is set (Abort enabled), while the IFLAG2 bit is set for a MB configured as Tx, the writing access done by CPU into the corresponding MB will be blocked. Offset: 0x002C Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF W 63I 62I 61I 60I 59I 58I 57I 56I 55I 54I 53I 52I 51I 50I 49I 48I Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF W 47I 46I 45I 44I 43I 42I 41I 40I 39I 38I 37I 36I 35I 34I 33I 32I Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-13. Interrupt Flags 2 Register (IFLAG2) Table 22-16. IFLAG2 field descriptions Field BUF32I – BUF63I Description Buffer MBi Interrupt Each bit flags the respective FlexCAN Message Buffer (MB32 to MB63) interrupt. 1 = The corresponding buffer has successfully completed transmission or reception 0 = No such occurrence 22.3.4.12 Interrupt Flags 1 Register (IFLAG1) This register defines the flags for 32 Message Buffer interrupts and FIFO interrupts. It contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt will be generated. The Interrupt flag must be cleared by writing it to ‘1’. Writing ‘0’ has no effect. When the AEN bit in the MCR is set (Abort enabled), while the IFLAG1 bit is set for a MB configured as Tx, the writing access done by CPU into the corresponding MB will be blocked. When the FEN bit in the MCR is set (FIFO enabled), the function of the 8 least significant interrupt flags (BUF7I – BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I and BUF5I indicate operating conditions of the FIFO, while BUF4I to BUF0I are not used. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 449 Offset: 0x0030 Access: Read/write BUF 31I BUF 30I BUF 29I BUF 28I BUF 27I BUF 26I BUF 25I BUF 24I BUF 23I BUF 22I BUF 21I BUF 20I BUF 19I BUF 18I BUF 17I BUF 16I 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF 15I BUF 14I BUF 13I BUF 12I BUF 11I BUF 10I BUF 9I BUF 8I BUF 7I BUF 6I BUF 5I BUF 4I BUF 3I BUF 2I BUF 1I BUF 0I 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-14. Interrupt Flags 1 Register (IFLAG1) Table 22-17. IFLAG1 field descriptions Field Description BUF31I – BUF8I Buffer MBi Interrupt Each bit flags the respective FlexCAN Message Buffer (MB8 to MB31) interrupt. 1 = The corresponding MB has successfully completed transmission or reception 0 = No such occurrence BUF7I Buffer MB7 Interrupt or “FIFO Overflow” If the FIFO is not enabled, this bit flags the interrupt for MB7. If the FIFO is enabled, this flag indicates an overflow condition in the FIFO (frame lost because FIFO is full). 1 = MB7 completed transmission/reception or FIFO overflow 0 = No such occurrence BUF6I Buffer MB6 Interrupt or “FIFO Warning” If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag indicates that 5 out of 6 buffers of the FIFO are already occupied (FIFO almost full). 1 = MB6 completed transmission/reception or FIFO almost full 0 = No such occurrence BUF5I Buffer MB5 Interrupt or “Frames available in FIFO” If the FIFO is not enabled, this bit flags the interrupt for MB5. If the FIFO is enabled, this flag indicates that at least one frame is available to be read from the FIFO. 1 = MB5 completed transmission/reception or frames available in the FIFO 0 = No such occurrence BUF4I – BUF0I Buffer MBi Interrupt or “reserved” If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled, these flags are not used and must be considered as reserved locations. 1 = Corresponding MB completed transmission/reception 0 = No such occurrence 22.3.4.13 Rx Individual Mask Registers (RXIMR0–RXIMR63) These registers are used as acceptance masks for ID filtering in Rx MBs and the FIFO. If the FIFO is not enabled, one mask register is provided for each available Message Buffer, providing ID masking capability on a per Message Buffer basis. When the FIFO is enabled (FEN bit in MCR is set), the first 8 Mask MPC5604B/C Microcontroller Reference Manual, Rev. 8 450 Freescale Semiconductor Registers apply to the 8 elements of the FIFO filter table (on a one-to-one correspondence), while the rest of the registers apply to the regular MBs, starting from MB8. The Individual Rx Mask Registers are implemented in SRAM, so they are not affected by reset and must be explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the module is in Freeze Mode. Out of Freeze Mode, write accesses are blocked and read accesses will return “all zeros”. Furthermore, if the BCC bit in the MCR is negated, any read or write operation to these registers results in access error. Base + 0x0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0 Figure 22-15. Rx Individual Mask Registers (RXIMR0 – RXIMR63) Table 22-18. RXIMR0 – RXIMR63 field description Field MI31–MI0 Description Mask Bits For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the mask bits affect all bits programmed in the filter table (ID, IDE, RTR). 1 = The corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is “don’t care” 22.4 Functional description 22.4.1 Overview The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and receiving CAN frames. The mailbox system is composed by a set of up to 64 Message Buffers (MB) that store configuration and control data, time stamp, message ID and data (see Section 22.3.2, “Message buffer structure). The memory corresponding to the first 8 MBs can be configured to support a FIFO reception scheme with a powerful ID filtering mechanism, capable of checking incoming frames against a table of IDs (up to 8 extended IDs or 16 standard IDs or 32 8-bit ID slices), each one with its own individual mask register. Simultaneous reception through FIFO and mailbox is supported. For mailbox reception, a matching algorithm makes it possible to store received frames only into MBs that have the same ID programmed on its ID field. A masking scheme makes it possible to match the ID programmed on the MB with a range of IDs on received CAN frames. For transmission, an arbitration algorithm decides MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 451 the prioritization of MBs to be transmitted based on the message ID (optionally augmented by 3 local priority bits) or the MB ordering. Before proceeding with the functional description, an important concept must be explained. A Message Buffer is said to be “active” at a given time if it can participate in the matching and arbitration algorithms that are happening at that time. An Rx MB with a ‘0000’ code is inactive (refer to Table 22-5). Similarly, a Tx MB with a ‘1000’ or ‘1001’ code is also inactive (refer to Table 22-6). An MB not programmed with ‘0000’, ‘1000’ or ‘1001’ will be temporarily deactivated (will not participate in the current arbitration or matching run) when the CPU writes to the C/S field of that MB (see Section 22.4.7.2, “Message buffer deactivation). 22.4.2 Local priority transmission The term local priority refers to the priority of transmit messages of the host node. This allows increased control over the priority mechanism for transmitting messages. Table 22-2 shows the placement of PRIO in the ID part of the message buffer. An additional 3-bit field (PRIO) in the long-word ID part of the message buffer structure has been added for local priority determination. They are prefixed to the regular ID to define the transmission priority. These bits are not transmitted and are intended only for Tx buffers. Perform the following to use the local priority feature: 1. Set the LPRIO_EN bit in the CANx_MCR. 2. Write the additional PRIO bits in the ID long-word of Tx message buffers when configuring the Tx buffers. With this extended ID concept, the arbitration process is based on the full 32-bit word. However, the actual transmitted ID continues to have 11 bits for standard frames and 29 bits for extended frames. 22.4.3 Transmit process In order to transmit a CAN frame, the CPU must prepare a Message Buffer for transmission by executing the following procedure: • If the MB is active (transmission pending), write an ABORT code (‘1001’) to the Code field of the Control and Status word to request an abortion of the transmission, then read back the Code field and the IFLAG register to check if the transmission was aborted (see Section 22.4.7.1, “Transmission abort mechanism). If backwards compatibility is desired (AEN in MCR negated), just write ‘1000’ to the Code field to inactivate the MB but then the pending frame may be transmitted without notification (see Section 22.4.7.2, “Message buffer deactivation). • Write the ID word. • Write the data bytes. • Write the Length, Control and Code fields of the Control and Status word to activate the MB. Once the MB is activated in the fourth step, it will participate into the arbitration process and eventually be transmitted according to its priority. At the end of the successful transmission, the value of the Free Running Timer is written into the Time Stamp field, the Code field in the Control and Status word is MPC5604B/C Microcontroller Reference Manual, Rev. 8 452 Freescale Semiconductor updated, a status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the corresponding Interrupt Mask Register bit. The new Code field after transmission depends on the code that was used to activate the MB in step four (see Table 22-5 and Table 22-6 in Section 22.3.2, “Message buffer structure). When the Abort feature is enabled (AEN in MCR is asserted), after the Interrupt Flag is asserted for a MB configured as transmit buffer, the MB is blocked, therefore the CPU is not able to update it until the Interrupt Flag be negated by CPU. It means that the CPU must clear the corresponding IFLAG before starting to prepare this MB for a new transmission or reception. 22.4.4 Arbitration process The arbitration process is an algorithm executed by the MBM that scans the whole MB memory looking for the highest priority message to be transmitted. All MBs programmed as transmit buffers will be scanned to find the lowest ID1 or the lowest MB number or the highest priority, depending on the LBUF and LPRIO_EN bits on the Control Register. The arbitration process is triggered in the following events: • During the CRC field of the CAN frame • During the error delimiter field of the CAN frame • During Intermission, if the winner MB defined in a previous arbitration was deactivated, or if there was no MB to transmit, but the CPU wrote to the C/S word of any MB after the previous arbitration finished • When MBM is in Idle or Bus Off state and the CPU writes to the C/S word of any MB • Upon leaving Freeze Mode When LBUF is asserted, the LPRIO_EN bit has no effect and the lowest number buffer is transmitted first. When LBUF and LPRIO_EN are both negated, the MB with the lowest ID is transmitted first but. If LBUF is negated and LPRIO_EN is asserted, the PRIO bits augment the ID used during the arbitration process. With this extended ID concept, arbitration is done based on the full 32-bit ID and the PRIO bits define which MB should be transmitted first, therefore MBs with PRIO = 000 have higher priority. If two or more MBs have the same priority, the regular ID will determine the priority of transmission. If two or more MBs have the same priority (3 extra bits) and the same regular ID, the lowest MB will be transmitted first. Once the highest priority MB is selected, it is transferred to a temporary storage space called Serial Message Buffer (SMB), which has the same structure as a normal MB but is not user accessible. This operation is called “move-out” and after it is done, write access to the corresponding MB is blocked (if the AEN bit in MCR is asserted). The write access is released in the following events: • After the MB is transmitted • FlexCAN enters in HALT or BUS OFF • FlexCAN loses the bus arbitration or there is an error during the transmission At the first opportunity window on the CAN bus, the message on the SMB is transmitted according to the CAN protocol rules. FlexCAN transmits up to eight data bytes, even if the DLC (Data Length Code) value is bigger. 1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same positions they are transmitted in the CAN frame. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 453 22.4.5 Receive process To be able to receive CAN frames into the mailbox MBs, the CPU must prepare one or more Message Buffers for reception by executing the following steps: • If the MB has a pending transmission, write an ABORT code (‘1001’) to the Code field of the Control and Status word to request an abortion of the transmission, then read back the Code field and the IFLAG register to check if the transmission was aborted (see Section 22.4.7.1, “Transmission abort mechanism). If backwards compatibility is desired (AEN in MCR negated), just write ‘1000’ to the Code field to inactivate the MB, but then the pending frame may be transmitted without notification (see Section 22.4.7.2, “Message buffer deactivation). If the MB already programmed as a receiver, just write ‘0000’ to the Code field of the Control and Status word to keep the MB inactive. • Write the ID word • Write ‘0100’ to the Code field of the Control and Status word to activate the MB Once the MB is activated in the third step, it will be able to receive frames that match the programmed ID. At the end of a successful reception, the MB is updated by the MBM as follows: • The value of the Free Running Timer is written into the Time Stamp field • The received ID, Data (8 bytes at most) and Length fields are stored • The Code field in the Control and Status word is updated (see Table 22-5 and Table 22-6 in Section 22.3.2, “Message buffer structure) • A status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the corresponding Interrupt Mask Register bit Upon receiving the MB interrupt, the CPU should service the received frame using the following procedure: • Read the Control and Status word (mandatory – activates an internal lock for this buffer) • Read the ID field (optional – needed only if a mask was used) • Read the Data field • Read the Free Running Timer (optional – releases the internal lock) Upon reading the Control and Status word, if the BUSY bit is set in the Code field, then the CPU should defer the access to the MB until this bit is negated. Reading the Free Running Timer is not mandatory. If not executed the MB remains locked, unless the CPU reads the C/S word of another MB. Note that only a single MB is locked at a time. The only mandatory CPU read operation is the one on the Control and Status word to assure data coherency (see Section 22.4.7, “Data coherence). The CPU should synchronize to frame reception by the status flag bit for the specific MB in one of the IFLAG Registers and not by the Code field of that MB. Polling the Code field does not work because once a frame was received and the CPU services the MB (by reading the C/S word followed by unlocking the MB), the Code field will not return to EMPTY. It will remain FULL, as explained in Table 22-5. If the CPU tries to workaround this behavior by writing to the C/S word to force an EMPTY code after reading the MB, the MB is actually deactivated from any currently ongoing matching process. As a result, a newly received frame matching the ID of that MB may be lost. In summary: never do polling by reading directly the C/S word of the MBs. Instead, read the IFLAG registers. MPC5604B/C Microcontroller Reference Manual, Rev. 8 454 Freescale Semiconductor Note that the received ID field is always stored in the matching MB, thus the contents of the ID field in an MB may change if the match was due to masking. Note also that FlexCAN does receive frames transmitted by itself if there exists an Rx matching MB, provided the SRX_DIS bit in the MCR is not asserted. If SRX_DIS is asserted, FlexCAN will not store frames transmitted by itself in any MB, even if it contains a matching MB, and no interrupt flag or interrupt signal will be generated due to the frame reception. To be able to receive CAN frames through the FIFO, the CPU must enable and configure the FIFO during Freeze Mode (see Section 22.4.8, “Rx FIFO). Upon receiving the frames available interrupt from FIFO, the CPU should service the received frame using the following procedure: • Read the Control and Status word (optional – needed only if a mask was used for IDE and RTR bits) • Read the ID field (optional – needed only if a mask was used) • Read the Data field • Clear the frames available interrupt (mandatory – release the buffer and allow the CPU to read the next FIFO entry) 22.4.6 Matching process The matching process is an algorithm executed by the MBM that scans the MB memory looking for Rx MBs programmed with the same ID as the one received from the CAN bus. If the FIFO is enabled, the 8-entry ID table from FIFO is scanned first and then, if a match is not found within the FIFO table, the other MBs are scanned. In the event that the FIFO is full, the matching algorithm will always look for a matching MB outside the FIFO region. When the frame is received, it is temporarily stored in a hidden auxiliary MB called Serial Message Buffer (SMB). The matching process takes place during the CRC field of the received frame. If a matching ID is found in the FIFO table or in one of the regular MBs, the contents of the SMB will be transferred to the FIFO or to the matched MB during the 6th bit of the End-Of-Frame field of the CAN protocol. This operation is called “move-in”. If any protocol error (CRC, ACK, etc.) is detected, than the move-in operation does not happen. For the regular mailbox MBs, an MB is said to be “free to receive” a new frame if the following conditions are satisfied: • The MB is not locked (see Section 22.4.7.3, “Message buffer lock mechanism) • The Code field is either EMPTY or else it is FULL or OVERRUN but the CPU has already serviced the MB (read the C/S word and then unlocked the MB) If the first MB with a matching ID is not “free to receive” the new frame, then the matching algorithm keeps looking for another free MB until it finds one. If it cannot find one that is free, then it will overwrite the last matching MB (unless it is locked) and set the Code field to OVERRUN (refer to Table 22-5 and Table 22-6). If the last matching MB is locked, then the new message remains in the SMB, waiting for the MB to be unlocked (see Section 22.4.7.3, “Message buffer lock mechanism). Suppose, for example, that the FIFO is disabled and there are two MBs with the same ID, and FlexCAN starts receiving messages with that ID. Let us say that these MBs are the second and the fifth in the array. When the first message arrives, the matching algorithm will find the first match in MB number 2. The code MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 455 of this MB is EMPTY, so the message is stored there. When the second message arrives, the matching algorithm will find MB number 2 again, but it is not “free to receive”, so it will keep looking and find MB number 5 and store the message there. If yet another message with the same ID arrives, the matching algorithm finds out that there are no matching MBs that are “free to receive”, so it decides to overwrite the last matched MB, which is number 5. In doing so, it sets the Code field of the MB to indicate OVERRUN. The ability to match the same ID in more than one MB can be exploited to implement a reception queue (in addition to the full featured FIFO) to allow more time for the CPU to service the MBs. By programming more than one MB with the same ID, received messages will be queued into the MBs. The CPU can examine the Time Stamp field of the MBs to determine the order in which the messages arrived. The matching algorithm described above can be changed to be the same one used in previous versions of the FlexCAN module. When the BCC bit in MCR is negated, the matching algorithm stops at the first MB with a matching ID that it founds, whether this MB is free or not. As a result, the message queueing feature does not work if the BCC bit is negated. Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports individual masking per MB. Please refer to Section 22.3.4.13, “Rx Individual Mask Registers (RXIMR0–RXIMR63). During the matching algorithm, if a mask bit is asserted, then the corresponding ID bit is compared. If the mask bit is negated, the corresponding ID bit is “don’t care”. Please note that the Individual Mask Registers are implemented in SRAM, so they are not initialized out of reset. Also, they can only be programmed if the BCC bit is asserted and while the module is in Freeze Mode. FlexCAN also supports an alternate masking scheme with only three mask registers (RGXMASK, RX14MASK and RX15MASK) for backwards compatibility. This alternate masking scheme is enabled when the BCC bit in the MCR is negated. 22.4.7 Data coherence In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described in Transmit process and Section 22.4.5, “Receive process. Any form of CPU accessing an MB structure within FlexCAN other than those specified may cause FlexCAN to behave in an unpredictable way. 22.4.7.1 Transmission abort mechanism The abort mechanism provides a safe way to request the abortion of a pending transmission. A feedback mechanism is provided to inform the CPU if the transmission was aborted or if the frame could not be aborted and was transmitted instead. In order to maintain backwards compatibility, the abort mechanism must be explicitly enabled by asserting the AEN bit in the MCR. In order to abort a transmission, the CPU must write a specific abort code (1001) to the Code field of the Control and Status word. When the abort mechanism is enabled, the active MBs configured as trasmission must be aborted first and then they may be updated. If the abort code is written to an MB that is currently being transmitted, or to an MB that was already loaded into the SMB for transmission, the write operation is blocked and the MB is not deactivated, but the abort request is captured and kept pending until one of the following conditions are satisfied: • The module loses the bus arbitration MPC5604B/C Microcontroller Reference Manual, Rev. 8 456 Freescale Semiconductor • There is an error during the transmission • The module is put into Freeze Mode If none of conditions above are reached, the MB is transmitted correctly, the interrupt flag is set in the IFLAG register and an interrupt to the CPU is generated (if enabled). The abort request is automatically cleared when the interrupt flag is set. In the other hand, if one of the above conditions is reached, the frame is not transmitted, therefore the abort code is written into the Code field, the interrupt flag is set in the IFLAG and an interrupt is (optionally) generated to the CPU. If the CPU writes the abort code before the transmission begins internally, then the write operation is not blocked, therefore the MB is updated and no interrupt flag is set. In this way the CPU just needs to read the abort code to make sure the active MB was deactivated. Although the AEN bit is asserted and the CPU wrote the abort code, in this case the MB is deactivated and not aborted, because the transmission did not start yet. One MB is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied. The abort procedure can be summarized as follows: • CPU writes 1001 into the code field of the C/S word • CPU reads the CODE field and compares it to the value that was written • If the CODE field that was read is different from the value that was written, the CPU must read the corresponding IFLAG to check if the frame was transmitted or it is being currently transmitted. If the corresponding IFLAG is set, the frame was transmitted. If the corresponding IFLAG is reset, the CPU must wait for it to be set, and then the CPU must read the CODE field to check if the MB was aborted (CODE=1001) or it was transmitted (CODE=1000). 22.4.7.2 Message buffer deactivation Deactivation is mechanism provided to maintain data coherence when the CPU writes to the Control and Status word of active MBs out of Freeze Mode. Any CPU write access to the Control and Status word of an MB causes that MB to be excluded from the transmit or receive processes during the current matching or arbitration round. The deactivation is temporary, affecting only for the current match/arbitration round. The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to decide which MB to transmit or receive. If the CPU updates the MB in the middle of a match or arbitration process, the data of that MB may no longer be coherent, therefore deactivation of that MB is done. Even with the coherence mechanism described above, writing to the Control and Status word of active MBs when not in Freeze Mode may produce undesirable results. Examples are: • Matching and arbitration are one-pass processes. If MBs are deactivated after they are scanned, no re-evaluation is done to determine a new match/winner. If an Rx MB with a matching ID is deactivated during the matching process after it was scanned, then this MB is marked as invalid to receive the frame, and FlexCAN will keep looking for another matching MB within the ones it has not scanned yet. If it cannot find one, then the message will be lost. Suppose, for example, that two MBs have a matching ID to a received frame, and the user deactivated the first matching MB after FlexCAN has scanned the second. The received frame will be lost even if the second matching MB was “free to receive”. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 457 • If a Tx MB containing the lowest ID is deactivated after FlexCAN has scanned it, then FlexCAN will look for another winner within the MBs that it has not scanned yet. Therefore, it may transmit an MB with ID that may not be the lowest at the time because a lower ID might be present in one of the MBs that it had already scanned before the deactivation. • There is a point in time until which the deactivation of a Tx MB causes it not to be transmitted (end of move-out). After this point, it is transmitted but no interrupt is issued and the Code field is not updated. In order to avoid this situation, the abort procedures described in Section 22.4.7.1, “Transmission abort mechanism should be used. 22.4.7.3 Message buffer lock mechanism Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive process. When the CPU reads the Control and Status word of an “active not empty” Rx MB, FlexCAN assumes that the CPU wants to read the whole MB in an atomic operation, and thus it sets an internal lock flag for that MB. The lock is released when the CPU reads the Free Running Timer (global unlock operation), or when it reads the Control and Status word of another MB. The MB locking is done to prevent a new frame to be written into the MB while the CPU is reading it. NOTE The locking mechanism only applies to Rx MBs which have a code different than INACTIVE (‘0000’) or EMPTY1 (‘0100’). Also, Tx MBs cannot be locked. Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the array are programmed with the same ID, and FlexCAN has already received and stored messages into these two MBs. Suppose now that the CPU decides to read MB number 5 and at the same time another message with the same ID is arriving. When the CPU reads the Control and Status word of MB number 5, this MB is locked. The new message arrives and the matching algorithm finds out that there are no “free to receive” MBs, so it decides to override MB number 5. However, this MB is locked, so the new message cannot be written there. It will remain in the SMB waiting for the MB to be unlocked, and only then will be written to the MB. If the MB is not unlocked in time and yet another new message with the same ID arrives, then the new message overwrites the one on the SMB and there will be no indication of lost messages either in the Code field of the MB or in the Error and Status Register. NOTE The FlexCAN module has 2 SMBs thus if a message with another ID arrives it is not lost. So overall the probability to lose message is very low unless a series of messages with the same ID arrives, which is not common in FlexCAN. While the message is being moved-in from the SMB to the MB, the BUSY bit on the Code field is asserted. If the CPU reads the Control and Status word and finds out that the BUSY bit is set, it should defer accessing the MB until the BUSY bit is negated. 1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honored when the BCC bit is negated. MPC5604B/C Microcontroller Reference Manual, Rev. 8 458 Freescale Semiconductor NOTE If the BUSY bit is asserted or if the MB is empty, then reading the Control and Status word does not lock the MB. Deactivation takes precedence over locking. If the CPU deactivates a locked Rx MB, then its lock status is negated and the MB is marked as invalid for the current matching round. Any pending message on the SMB will not be transferred anymore to the MB. 22.4.8 Rx FIFO The receive-only FIFO is enabled by asserting the FEN bit in the MCR. The reset value of this bit is zero to maintain software backwards compatibility with previous versions of the module that did not have the FIFO feature. When the FIFO is enabled, the memory region normally occupied by the first 8 MBs (0x80–0xFF) is now reserved for use of the FIFO engine (see Section 22.3.3, “Rx FIFO structure). Management of read and write pointers is done internally by the FIFO engine. The CPU can read the received frames sequentially, in the order they were received, by repeatedly accessing a Message Buffer structure at the beginning of the memory. The FIFO can store up to 6 frames pending service by the CPU. An interrupt is sent to the CPU when new frames are available in the FIFO. Upon receiving the interrupt, the CPU must read the frame (accessing an MB in the 0x80 address) and then clear the interrupt. The act of clearing the interrupt triggers the FIFO engine to replace the MB in 0x80 with the next frame in the queue, and then issue another interrupt to the CPU. If the FIFO is full and more frames continue to be received, an OVERFLOW interrupt is issued to the CPU and subsequent frames are not accepted until the CPU creates space in the FIFO by reading one or more frames. A warning interrupt is also generated when 5 frames are accumulated in the FIFO. A powerful filtering scheme is provided to accept only frames intended for the target application, thus reducing the interrupt servicing work load. The filtering criteria is specified by programming a table of 8 32-bit registers that can be configured to one of the following formats (see also Section 22.3.3, “Rx FIFO structure): • Format A: 8 extended or standard IDs (including IDE and RTR) • Format B: 16 standard IDs or 16 extended 14-bit ID slices (including IDE and RTR) • Format C: 32 standard or extended 8-bit ID slices NOTE A chosen format is applied to all 8 registers of the filter table. It is not possible to mix formats within the table. The eight elements of the filter table are individually affected by the first eight Individual Mask Registers (RXIMR0 – RXIMR7), allowing very powerful filtering criteria to be defined. The rest of the RXIMR, starting from RXIM8, continue to affect the regular MBs, starting from MB8. If the BCC bit is negated (or if the RXIMR are not available for the particular MCU), then the FIFO filter table is affected by the legacy mask registers as follows: element 6 is affected by RX14MASK, element 7 is affected by RX15MASK and the other elements (0 to 5) are affected by RXGMASK. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 459 22.4.9 CAN protocol related features 22.4.9.1 Remote frames Remote frame is a special kind of frame. The user can program a MB to be a Request Remote Frame by writing the MB as Transmit with the RTR bit set to ‘1’. After the Remote Request frame is transmitted successfully, the MB becomes a Receive Message Buffer, with the same ID as before. When a Remote Request frame is received by FlexCAN, its ID is compared to the IDs of the transmit message buffers with the Code field ‘1010’. If there is a matching ID, then this MB frame will be transmitted. Note that if the matching MB has the RTR bit set, then FlexCAN will transmit a Remote Frame as a response. A received Remote Request Frame is not stored in a receive buffer. It is only used to trigger a transmission of a frame in response. The mask registers are not used in remote frame matching, and all ID bits (except RTR) of the incoming received frame should match. In the case that a Remote Request Frame was received and matched an MB, this message buffer immediately enters the internal arbitration process, but is considered as normal Tx MB, with no higher priority. The data length of this frame is independent of the DLC field in the remote frame that initiated its transmission. If the Rx FIFO is enabled (bit FEN set in MCR), FlexCAN will not generate an automatic response for Remote Request Frames that match the FIFO filtering criteria. If the remote frame matches one of the target IDs, it will be stored in the FIFO and presented to the CPU. Note that for filtering formats A and B, it is possible to select whether remote frames are accepted or not. For format C, remote frames are always accepted (if they match the ID). 22.4.9.2 Overload frames FlexCAN does transmit overload frames due to detection of following conditions on CAN bus: • Detection of a dominant bit in the first/second bit of Intermission • Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames) • Detection of a dominant bit at the 8th bit (last) of Error Frame Delimiter or Overload Frame Delimiter 22.4.9.3 Time stamp The value of the Free Running Timer is sampled at the beginning of the Identifier field on the CAN bus, and is stored at the end of “move-in” in the TIME STAMP field, providing network behavior with respect to time. Note that the Free Running Timer can be reset upon a specific frame reception, enabling network time synchronization. Refer to TSYN description in Section 22.3.4.2, “Control Register (CTRL). MPC5604B/C Microcontroller Reference Manual, Rev. 8 460 Freescale Semiconductor 22.4.9.4 Protocol timing Figure 22-16 shows the structure of the clock generation circuitry that feeds the CAN Protocol Interface (CPI) submodule. The clock source bit (CLK_SRC) in the CTRL Register defines whether the internal clock is connected to the output of a crystal oscillator (Oscillator Clock) or to the Peripheral Clock (generally from a FMPLL). In order to guarantee reliable operation, the clock source should be selected while the module is in Disable Mode (bit MDIS set in the Module Configuration Register). Peripheral Clock (FMPLL) CPI Clock Prescaler (1 .. 256) Sclock Oscillator Clock (Xtal) CLK_SRC Figure 22-16. CAN engine clocking scheme The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the CAN bus timing. The crystal oscillator clock has better jitter performance than FMPLL generated clocks. NOTE This clock selection feature may not be available in all MCUs. A particular MCU may not have a FMPLL, in which case it would have only the oscillator clock, or it may use only the FMPLL clock feeding the FlexCAN module. In these cases, the CLK_SRC bit in the CTRL Register has no effect on the module operation. The FlexCAN module supports a variety of means to setup bit timing parameters that are required by the CAN protocol. The Control Register has various fields used to control bit timing parameters: PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW. See Section 22.3.4.2, “Control Register (CTRL). The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose period defines the ‘time quantum’ used to compose the CAN waveform. A time quantum is the atomic unit of time handled by the CAN engine. fTq= -----------------f--C---A----N----C----L---K-----------------Prescaler Þ Value A bit time is subdivided into three segments1 (reference Figure 22-17 and Table 22-19): • SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section • Time Segment 1: This segment includes the Propagation Segment and the Phase Segment 1 of the CAN standard. It can be programmed by setting the PROPSEG and the PSEG1 fields of the CTRL Register so that their sum (plus 2) is in the range of 4 to 16 time quanta 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 461 • Time Segment 2: This segment represents the Phase Segment 2 of the CAN standard. It can be programmed by setting the PSEG2 field of the CTRL Register (plus 1) to be 2 to 8 time quanta long Bit Þ Rate= -----------------------------------------f--T----q----------------------------------------number Þ of Þ Time Þ Quanta NRZ Signal SYNC_SEG Time Segment 1 (PROP_SEG + PSEG1 + 2) Time Segment 2 (PSEG2 + 1) 1 4 ... 16 8 ... 25 Time Quanta = 1 Bit Time 2 ... 8 Transmit Point Sample Point (single or triple sampling) Figure 22-17. Segments within the bit time Table 22-19. Time segment syntax Syntax SYNC_SEG Transmit Point Sample Point Description System expects transitions to occur on the bus during this period. A node in transmit mode transfers a new value to the CAN bus at this point. A node samples the bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample. Table 22-20 is an example of the CAN compliant segment settings and the related parameter values. It refers to the official CAN specification. Table 22-20. CAN standard compliant bit time segment settings Time segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 Time segment 2 2 3 4 5 Resynchronization jump width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 MPC5604B/C Microcontroller Reference Manual, Rev. 8 462 Freescale Semiconductor Table 22-20. CAN standard compliant bit time segment settings (continued) Time segment 1 7 .. 14 8 .. 15 9 .. 16 Time segment 2 6 7 8 Resynchronization jump width 1 .. 4 1 .. 4 1 .. 4 NOTE It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit time calculations, use an IPT (Information Processing Time) of 2, which is the value implemented in the FlexCAN module. 22.4.9.5 Arbitration and matching timing During normal transmission or reception of frames, the arbitration, matching, move-in and move-out processes are executed during certain time windows inside the CAN frame, as shown in Figure 22-18. CRC (15) Matching/Arbitration Window (24 bits) Start Move (bit 6) EOF (7) Interm Move Window Figure 22-18. Arbitration, match and move time windows When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer memory during the available time slot. In order to have sufficient time to do that, the following requirements must be observed: • A valid CAN bit timing must be programmed, as indicated in Table 22-20 • The peripheral clock frequency cannot be smaller than the oscillator clock frequency, i.e. the FMPLL cannot be programmed to divide down the oscillator clock • There must be a minimum ratio between the peripheral clock frequency and the CAN bit rate, as specified in Table 22-21 Table 22-21. Minimum ratio between peripheral clock frequency and CAN bit rate Number of message buffers 16 32 64 Minimum ratio 8 8 16 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 463 A direct consequence of the first requirement is that the minimum number of time quanta per CAN bit must be 8, so the oscillator clock frequency should be at least 8 times the CAN bit rate. The minimum frequency ratio specified in Table 22-21 can be achieved by choosing a high enough peripheral clock frequency when compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters (PRESDIV, PROPSEG, PSEG1, PSEG2). As an example, taking the case of 64 MBs, if the oscillator and peripheral clock frequencies are equal and the CAN bit timing is programmed to have 8 time quanta per bit, then the prescaler factor (PRESDIV + 1) should be at least 2. For prescaler factor equal to one and CAN bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock frequencies should be at least 2. 22.4.10 Modes of operation details 22.4.10.1 Freeze Mode This mode is entered by asserting the HALT bit in the MCR or when the MCU is put into Debug Mode. In both cases it is also necessary that the FRZ bit is asserted in the MCR and the module is not in low power mode (Disable Mode). When Freeze Mode is requested during transmission or reception, FlexCAN does the following: • Waits to be in either Intermission, Passive Error, Bus Off or Idle state • Waits for all internal activities like arbitration, matching, move-in and move-out to finish • Ignores the Rx input pin and drives the Tx pin as recessive • Stops the prescaler, thus halting all CAN protocol activities • Grants write access to the Error Counters Register, which is read-only in other modes • Sets the NOT_RDY and FRZ_ACK bits in MCR After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in MCR before executing any other action, otherwise FlexCAN may operate in an unpredictable way. In Freeze mode, all memory mapped registers are accessible. Exiting Freeze Mode is done in one of the following ways: • CPU negates the FRZ bit in the MCR • The MCU is removed from Debug Mode and/or the HALT bit is negated Once out of Freeze Mode, FlexCAN tries to resynchronize to the CAN bus by waiting for 11 consecutive recessive bits. 22.4.10.2 Module Disable Mode This low power mode is entered when the MDIS bit in the MCR is asserted. If the module is disabled during Freeze Mode, it shuts down the clocks to the CPI and MBM submodules, sets the LPM_ACK bit and negates the FRZ_ACK bit. If the module is disabled during transmission or reception, FlexCAN does the following: • Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and then checks it to be recessive MPC5604B/C Microcontroller Reference Manual, Rev. 8 464 Freescale Semiconductor • Waits for all internal activities like arbitration, matching, move-in and move-out to finish • Ignores its Rx input pin and drives its Tx pin as recessive • Shuts down the clocks to the CPI and MBM submodules • Sets the NOT_RDY and LPM_ACK bits in MCR The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped registers, except the Free Running Timer, the Error Counter Register and the Message Buffers, which cannot be accessed when the module is in Disable Mode. Exiting from this mode is done by negating the MDIS bit, which will resume the clocks and negate the LPM_ACK bit. 22.4.11 Interrupts The module can generate up to 69 interrupt sources (64 interrupts due to message buffers and 5 interrupts due to Ored interrupts from MBs, Bus Off, Error, Tx Warning and Rx Warning). The number of actual sources depends on the configured number of Message Buffers. Each one of the message buffers can be an interrupt source, if its corresponding IMASK bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or reception. Each of the buffers has assigned a flag bit in the IFLAG Registers. The bit is set when the corresponding buffer completes a successful transmission/reception and is cleared when the CPU writes it to ‘1’ (unless another interrupt is generated at the same time). NOTE It must be guaranteed that the CPU only clears the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine. If the Rx FIFO is enabled (bit FEN on MCR set), the interrupts corresponding to MBs 0 to 7 have a different behavior. Bit 7 of the IFLAG1 becomes the “FIFO Overflow” flag; bit 6 becomes the FIFO Warning flag, bit 5 becomes the “Frames Available in FIFO flag” and bits 4–0 are unused. See Section 22.3.4.12, “Interrupt Flags 1 Register (IFLAG1) for more information. A combined interrupt for all MBs is also generated by an Or of all the interrupt sources from MBs. This interrupt gets generated when any of the MBs generates an interrupt. In this case the CPU must read the IFLAG Registers to determine which MB caused the interrupt. The other 4 interrupt sources (Bus Off, Error, Tx Warning and Rx Warning) generate interrupts like the MB ones, and can be read from the Error and Status Register. The Bus Off, Error, Tx Warning and Rx Warning interrupt mask bits are located in the Control Register, and the Wake-Up interrupt mask bit is located in the MCR. 22.4.12 Bus interface The CPU access to FlexCAN registers are subject to the following rules: • Read and write access to supervisor registers in User Mode results in access error. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 465 • Read and write access to unimplemented or reserved address space also results in access error. Any access to unimplemented MB or Rx Individual Mask Register locations results in access error. Any access to the Rx Individual Mask Register space when the BCC bit in MCR is negated results in access error. • If MAXMB is programmed with a value smaller than the available number of MBs, then the unused memory space can be used as general purpose SRAM space. Note that the Rx Individual Mask Registers can only be accessed in Freeze Mode, and this is still true for unused space within this memory. Note also that reserved words within SRAM cannot be used. As an example, suppose FlexCAN is configured with 64 MBs and MAXMB is programmed with zero. The maximum number of MBs in this case becomes one. The MB memory starts at 0x0060, but the space from 0x0060 to 0x007F is reserved (for SMB usage), and the space from 0x0080 to 0x008F is used by the one MB. This leaves us with the available space from 0x0090 to 0x047F. The available memory in the Mask Registers space would be from 0x0884 to 0x097F. NOTE Unused MB space must not be used as general purpose SRAM while FlexCAN is transmitting and receiving CAN frames. 22.5 Initialization/Application information This section provide instructions for initializing the FlexCAN module. 22.5.1 FlexCAN initialization sequence The FlexCAN module may be reset in three ways: • MCU level hard reset, which resets all memory mapped registers asynchronously • MCU level soft reset, which resets some of the memory mapped registers synchronously (refer to Table 22-2 to see what registers are affected by soft reset) • SOFT_RST bit in MCR, which has the same effect as the MCU level soft reset Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. Therefore, it may take some time to fully propagate its effects. The SOFT_RST bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. Also, soft reset cannot be applied while clocks are shut down in the low power mode. The low power mode should be exited and the clocks resumed before applying soft reset. The clock source (CLK_SRC bit) should be selected while the module is in Disable Mode. After the clock source is selected and the module is enabled (MDIS bit negated), FlexCAN automatically goes to Freeze Mode. In Freeze Mode, FlexCAN is unsynchronized to the CAN bus, the HALT and FRZ bits in MCR are set, the internal state machines are disabled and the FRZ_ACK and NOT_RDY bits in the MCR are set. The Tx pin is in recessive state and FlexCAN does not initiate any transmission or reception of CAN frames. Note that the Message Buffers and the Rx Individual Mask Registers are not affected by reset, so they are not automatically initialized. MPC5604B/C Microcontroller Reference Manual, Rev. 8 466 Freescale Semiconductor For any configuration change/initialization it is required that FlexCAN is put into Freeze Mode (see Section 22.4.10.1, “Freeze Mode). The following is a generic initialization sequence applicable to the FlexCAN module: • Initialize the Module Configuration Register — Enable the individual filtering per MB and reception queue features by setting the BCC bit — Enable the warning interrupts by setting the WRN_EN bit — If required, disable frame self reception by setting the SRX_DIS bit — Enable the FIFO by setting the FEN bit — Enable the abort mechanism by setting the AEN bit — Enable the local priority feature by setting the LPRIO_EN bit • Initialize the Control Register — Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW — Determine the bit rate by programming the PRESDIV field — Determine the internal arbitration mode (LBUF bit) • Initialize the Message Buffers — The Control and Status word of all Message Buffers must be initialized — If FIFO was enabled, the 8-entry ID table must be initialized — Other entries in each Message Buffer should be initialized as required • Initialize the Rx Individual Mask Registers • Set required interrupt mask bits in the IMASK Registers (for all MB interrupts) and in CTRL Register (for Bus Off and Error interrupts) • Negate the HALT bit in MCR Starting with the last event, FlexCAN attempts to synchronize to the CAN bus. 22.5.2 FlexCAN addressing and SRAM size configurations There are three SRAM configurations that can be implemented within the FlexCAN module. The possible configurations are: • For 16 MBs: 288 bytes for MB memory and 64 bytes for Individual Mask Registers • For 32 MBs: 544 bytes for MB memory and 128 bytes for Individual Mask Registers • For 64 MBs: 1056 bytes for MB memory and 256 bytes for Individual Mask Registers In each configuration the user can program the maximum number of MBs that will take part in the matching and arbitration processes using the MAXMB field in the MCR. For 16 MB configuration, MAXMB can be any number between 0–15. For 32 MB configuration, MAXMB can be any number between 0–31. For 64 MB configuration, MAXMB can be any number between 0–63. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 467 MPC5604B/C Microcontroller Reference Manual, Rev. 8 468 Freescale Semiconductor Chapter 23 Deserial Serial Peripheral Interface (DSPI) 23.1 Introduction This chapter describes the Deserial Serial Peripheral Interface (DSPI), which provides a synchronous serial bus for communication between the MCU and an external peripheral device. The MPC5604B has three identical DSPI modules (DSPI_0, DSPI_1 and DSPI_2). The “x” appended to signal names signifies the module to which the signal applies. Thus CS0_x specifies that the CS0 signal applies to DSPI module 0, 1, etc. A block diagram of the DSPI is shown in Figure 23-1. INTC SPI Interrupt control TX FIFO RX FIFO CMD TX data RX data 16 16 Shift register SPI baud rate, delay and transfer 4 control SOUT_x SIN_x SCK_x CS0_x CS1:4_x CS5_x Figure 23-1. DSPI block diagram The register content is transmitted using an SPI protocol. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 469 For queued operations the SPI queues reside in internal SRAM which is external to the DSPI. Data transfers between the queues and the DSPI FIFOs are accomplished through host software. Figure 23-2 shows a DSPI with external queues in internal SRAM. Internal SRAM RX queue TX queue Address/control RX data TX data Host CPU Address/control TX data RX data DSPI TX FIFO RX FIFO Shift register Figure 23-2. DSPI with queues 23.2 Features The DSPI supports these SPI features: • Full-duplex, three-wire synchronous transfers • Master and slave mode • Buffered transmit and receive operation using the TX and RX FIFOs, with depths of four entries • Visibility into TX and RX FIFOs for ease of debugging • FIFO bypass mode for low-latency updates to SPI queues • Programmable transfer attributes on a per-frame basis — 6 clock and transfer attribute registers — Serial clock with programmable polarity and phase — Programmable delays – CS to SCK delay – SCK to CS delay – Delay between frames — Programmable serial frame size of 4 to 16 bits, expandable with software control — Continuously held chip select capability • Up to 6 peripheral chip selects, expandable to 64 with external demultiplexer • Deglitching support for up to 32 peripheral chip selects with external demultiplexer • 6 interrupt conditions: MPC5604B/C Microcontroller Reference Manual, Rev. 8 470 Freescale Semiconductor – End of queue reached (EOQF) – TX FIFO is not full (TFFF) – Transfer of current frame complete (TCF) – RX FIFO is not empty (RFDF) – FIFO overrun (attempt to transmit with an empty TX FIFO or serial frame received while RX FIFO is full) (RFOF) or (TFUF) • Modified SPI transfer formats for communication with slower peripheral devices • Supports all functional modes from QSPI subblock of QSMCM (MPC500 family) • Continuous serial communications clock (SCK) 23.3 Modes of operation The DSPI has four modes of operation. These modes can be divided into two categories: • Module-specific: Master, Slave, and Module Disable modes • MCU-specific: Debug mode The module-specific modes are entered by host software writing to a register. The MCU-specific mode is controlled by signals external to the DSPI. An MCU-specific mode is a mode that the entire device may enter, in parallel to the DSPI being in one of its module-specific modes. 23.3.1 Master mode Master mode allows the DSPI to initiate and control serial communication. In this mode the SCK, CSn and SOUT signals are controlled by the DSPI and configured as outputs. For more information, see Section 23.6.1.1, Master mode. 23.3.2 Slave mode Slave mode allows the DSPI to communicate with SPI bus masters. In this mode the DSPI responds to externally controlled serial transfers. The DSPI cannot initiate serial transfers in slave mode. In slave mode, the SCK signal and the CS0_x signal are configured as inputs and provided by a bus master. CS0_x must be configured as input and pulled high. If the internal pullup is being used then the appropriate bits in the relevant SIU_PCR must be set (SIU_PCR [WPE = 1], [WPS = 1]). For more information, see Section 23.6.1.2, Slave mode. 23.3.3 Module Disable mode The module disable mode is used for MCU power management. The clock to the non-memory mapped logic in the DSPI is stopped while in module disable mode. The DSPI enters the module disable mode when the MDIS bit in DSPIx_MCR is set. For more information, see Section 23.6.1.3, Module Disable mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 471 23.3.4 Debug mode Debug mode is used for system development and debugging. If the device enters debug mode while the FRZ bit in the DSPIx_MCR is set, the DSPI halts operation on the next frame boundary. If the device enters debug mode while the FRZ bit is cleared, the DSPI behavior is unaffected and remains dictated by the module-specific mode and configuration of the DSPI. For more information, see Section 23.6.1.4, Debug mode. 23.4 External signal description 23.4.1 Signal overview Table 23-1 lists off-chip DSPI signals. Table 23-1. Signal properties Name I/O type Master mode Function Slave mode CS0_x Output / input CS1:3_x Output Peripheral chip select 0 Peripheral chip select 1–3 Slave select Unused1 CS4_x CS5_x Output Output Peripheral chip select 4 Peripheral chip select 5 / Peripheral chip select strobe Master trigger Unused1 SIN_x Input Serial data in Serial data in SOUT_x Output Serial data out Serial data out SCK_x Output / input Serial clock (output) Serial clock (input) 1 The SIUL allows you to select alternate pin functions for the device. 23.4.2 Signal names and descriptions 23.4.2.1 Peripheral Chip Select / Slave Select (CS0_x) In master mode, the CS0_x signal is a peripheral chip select output that selects the slave device to which the current transmission is intended. In slave mode, the CS0_x signal is a slave select input signal that allows an SPI master to select the DSPI as the target for transmission. CS0_x must be configured as input and pulled high. If the internal pullup is being used then the appropriate bits in the relevant SIU_PCR must be set (SIU_PCR [WPE = 1], [WPS = 1]). Set the IBE and OBE bits in the SIU_PCR for all CS0_x pins when the DSPI chip select or slave select primary function is selected for that pin. When the pin is used for DSPI master mode as a chip select output, set the OBE bit. When the pin is used in DSPI slave mode as a slave select input, set the IBE bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 472 Freescale Semiconductor 23.4.2.2 Peripheral Chip Selects 1–3 (CS1:3_x) CS1:3_x are peripheral chip select output signals in master mode. In slave mode these signals are not used. 23.4.2.3 Peripheral Chip Select 4 (CS4_x) CS4_x is a peripheral chip select output signal in master mode. 23.4.2.4 Peripheral Chip Select 5 / Peripheral Chip Select Strobe (CS5_x) CS5_x is a peripheral chip select output signal. When the DSPI is in master mode and PCSSE bit in the DSPIx_MCR is cleared, the CS5_x signal is used to select the slave device that receives the current transfer. CS5_x is a strobe signal used by external logic for deglitching of the CS signals. When the DSPI is in master mode and the PCSSE bit in the DSPIx_MCR is set, the CS5_x signal indicates the timing to decode CS0:4_x signals, which prevents glitches from occurring. CS5_x is not used in slave mode. 23.4.2.5 Serial Input (SIN_x) SIN_x is a serial data input signal. 23.4.2.6 Serial Output (SOUT_x) SOUT_x is a serial data output signal. 23.4.2.7 Serial Clock (SCK_x) SCK_x is a serial communication clock signal. In master mode, the DSPI generates the SCK. In slave mode, SCK_x is an input from an external bus master. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 473 23.5 Memory map and register description 23.5.1 Memory map Table 23-2 shows the DSPI memory map. Table 23-2. DSPI memory map Base addresses: 0xFFF9_0000 (DSPI_0) 0xFFF9_4000 (DSPI_1) 0xFFF9_8000 (DSPI_2) Address offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24–0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C–0x78 0x7C 0x80 0x84 0x88 Register DSPI Module Configuration Register (DSPIx_MCR) Reserved DSPI Transfer Count Register (DSPIx_TCR) DSPI Clock and Transfer Attributes Register 0 (DSPIx_CTAR0) DSPI Clock and Transfer Attributes Register 1 (DSPIx_CTAR1) DSPI Clock and Transfer Attributes Register 2 (DSPIx_CTAR2) DSPI Clock and Transfer Attributes Register 3 (DSPIx_CTAR3) DSPI Clock and Transfer Attributes Register 4 (DSPIx_CTAR4) DSPI Clock and Transfer Attributes Register 5 (DSPIx_CTAR5) Reserved DSPI Status Register (DSPIx_SR) DSPI Interrupt Request Enable Register (DSPIx_RSER) DSPI Push TX FIFO Register (DSPIx_PUSHR) DSPI Pop RX FIFO Register (DSPIx_POPR) DSPI Transmit FIFO Register 0 (DSPIx_TXFR0) DSPI Transmit FIFO Register 1 (DSPIx_TXFR1) DSPI Transmit FIFO Register 2 (DSPIx_TXFR2) DSPI Transmit FIFO Register 3 (DSPIx_TXFR3) Reserved DSPI Receive FIFO Register 0 (DSPIx_RXFR0) DSPI Receive FIFO Register 1 (DSPIx_RXFR1) DSPI Receive FIFO Register 2 (DSPIx_RXFR2) DSPI Receive FIFO Register 3 (DSPIx_RXFR3) Location on page 475 on page 478 on page 478 on page 478 on page 478 on page 478 on page 478 on page 478 on page 486 on page 488 on page 490 on page 492 on page 493 on page 493 on page 493 on page 493 on page 493 on page 493 on page 493 on page 493 MPC5604B/C Microcontroller Reference Manual, Rev. 8 474 Freescale Semiconductor 23.5.2 DSPI Module Configuration Register (DSPIx_MCR) The DSPIx_MCR contains bits which configure attributes of the DSPI operation. The values of the HALT and MDIS bits can be changed at any time, but their effect begins on the next frame boundary. The HALT and MDIS bits in the DSPIx_MCR are the only bit values software can change while the DSPI is running. Offset: 0x00 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 00 W DCONF FRZ PCSIS5 PCSIS4 PCSIS3 PCSIS2 PCSIS1 PCSIS0 MSTR CONT_SCKE MTFE PCSSE ROOE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_TXF DIS_RXF CLR_TXF CLR_RXF 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 W MDIS 0000000 SMPL_PT HALT Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 23-3. DSPI Module Configuration Register (DSPIx_MCR) Table 23-3. DSPIx_MCR field descriptions Field MSTR Description Master/slave mode select Configures the DSPI for master mode or slave mode. CONT_SCKE 0 DSPI is in slave mode 1 DSPI is in master mode Continuous SCK enable Enables the serial communication clock (SCK) to run continuously. See Section 23.6.6, Continuous serial communications clock, for details. 0 Continuous SCK disabled 1 Continuous SCK enabled Note: If the FIFO is enabled with continuous SCK mode, the TX-FIFO should be cleared before setting the CONT_SCKE bit, and only the CTAR0 register should be used to transfer attributes; otherwise, a change in SCK frequency occurs. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 475 Field DCONF Table 23-3. DSPIx_MCR field descriptions (continued) Description DSPI configuration The following table lists the DCONF values for the various configurations. FRZ MTFE PCSSE ROOE PCSISn DCONF 00 01 10 11 Configuration SPI Invalid value Invalid value Invalid value Freeze Enables the DSPI transfers to be stopped on the next frame boundary when the device enters debug mode. 0 Do not halt serial transfers 1 Halt serial transfers Modified timing format enable Enables a modified transfer format to be used. See Section 23.6.5.4, Modified SPI transfer format (MTFE = 1, CPHA = 1), for more information. 0 Modified SPI transfer format disabled 1 Modified SPI transfer format enabled Peripheral chip select strobe enable Enables the CS5_x to operate as a CS strobe output signal. See Section 23.6.4.5, Peripheral chip select strobe enable (CS5_x), for more information. 0 CS5_x is used as the Peripheral chip select 5 signal 1 CS5_x as an active-low CS strobe signal Receive FIFO overflow overwrite enable Enables an RX FIFO overflow condition to ignore the incoming serial data or to overwrite existing data. If the RX FIFO is full and new data is received, the data from the transfer that generated the overflow is ignored or put in the shift register. If the ROOE bit is set, the incoming data is put in the shift register. If the ROOE bit is cleared, the incoming data is ignored. See Section 23.6.7.6, Receive FIFO Overflow Interrupt Request (RFOF), for more information. 0 Incoming data is ignored 1 Incoming data is put in the shift register Peripheral chip select inactive state Determines the inactive state of the CS0_x signal. CS0_x must be configured as inactive high for slave mode operation. 0 The inactive state of CS0_x is low 1 The inactive state of CS0_x is high MPC5604B/C Microcontroller Reference Manual, Rev. 8 476 Freescale Semiconductor Field MDIS DIS_TXF DIS_RXF CLR_TXF CLR_RXF SMPL_PT HALT Table 23-3. DSPIx_MCR field descriptions (continued) Description Module disable Allows the clock to stop to the non-memory mapped logic in the DSPI, effectively putting the DSPI in a software controlled power-saving state. See Section 23.6.8, Power saving features for more information. 0 Enable DSPI clocks 1 Allow external logic to disable DSPI clocks Disable transmit FIFO Enables and disables the TX FIFO. When the TX FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI. See Section 23.6.3.3, FIFO disable operation for details. 0 TX FIFO is enabled 1 TX FIFO is disabled Disable receive FIFO Enables and disables the RX FIFO. When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI. See Section 23.6.3.3, FIFO disable operation for details. 0 RX FIFO is enabled 1 RX FIFO is disabled Clear TX FIFO. CLR_TXF is used to flush the TX FIFO. Writing a ‘1’ to CLR_TXF clears the TX FIFO Counter. The CLR_TXF bit is always read as zero. 0 Do not clear the TX FIFO Counter 1 Clear the TX FIFO Counter Clear RX FIFO. CLR_RXF is used to flush the RX FIFO. Writing a ‘1’ to CLR_RXF clears the RX Counter. The CLR_RXF bit is always read as zero. 0 Do not clear the RX FIFO Counter 1 Clear the RX FIFO Counter Sample point Allows the host software to select when the DSPI master samples SIN in modified transfer format. Figure 23-18 shows where the master can sample the SIN pin. The following table lists the delayed sample points. SMPL_PT Number of system clock cycles between odd-numbered edge of SCK_x and sampling of SIN_x 00 0 01 1 10 2 11 Reserved Halt Provides a mechanism for software to start and stop DSPI transfers. See Section 23.6.2, Start and stop of DSPI transfers, for details on the operation of this bit. 0 Start transfers 1 Stop transfers MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 477 23.5.3 DSPI Transfer Count Register (DSPIx_TCR) The DSPIx_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter is intended to assist in queue management. The user must not write to the DSPIx_TCR while the DSPI is running. Offset: 0x08 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SPI_TCNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-4. DSPI Transfer Count Register (DSPIx_TCR) Table 23-4. DSPIx_TCR field descriptions Field Description SPI_TCNT SPI transfer counter Counts the number of SPI transfers the DSPI makes. The SPI_TCNT field is incremented every time the last bit of an SPI frame is transmitted. A value written to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT field is set in the executing SPI command. The transfer counter ‘wraps around,’ incrementing the counter past 65535 resets the counter to zero. 23.5.4 DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) The DSPI modules each contain six clock and transfer attribute registers (DSPIx_CTARn) which are used to define different transfer attribute configurations. Each DSPIx_CTAR controls: • Frame size • Baud rate and transfer delay values • Clock phase • Clock polarity • MSB or LSB first DSPIx_CTARs support compatibility with the QSPI module in the MPC5604B family of MCUs. At the initiation of an SPI transfer, control logic selects the DSPIx_CTAR that contains the transfer’s attributes. Do not write to the DSPIx_CTARs while the DSPI is running. In master mode, the DSPIx_CTARn registers define combinations of transfer attributes such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. In slave mode, a subset of the bit MPC5604B/C Microcontroller Reference Manual, Rev. 8 478 Freescale Semiconductor fields in the DSPIx_CTAR0 and DSPIx_CTAR1 registers are used to set the slave transfer attributes. See the individual bit descriptions for details on which bits are used in slave modes. When the DSPI is configured as an SPI master, the CTAS field in the command portion of the TX FIFO entry selects which of the DSPIx_CTAR registers is used on a per-frame basis. When the DSPI is configured as an SPI bus slave, the DSPIx_CTAR0 register is used. . Offsets: 0x0C–0x20 (6 registers) Access: Read/write CPOL CPHA LSBFE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DBR W FMSZ PCSSCK PASC PDT PBR Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CSSCK ASC DT BR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-5. DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) Table 23-5. DSPIx_CTARn field descriptions Field Descriptions DBR FMSZ CPOL Double Baud Rate The DBR bit doubles the effective baud rate of the Serial Communications Clock (SCK). This field is only used in Master Mode. It effectively halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the Serial Communications Clock (SCK) depends on the value in the Baud Rate Prescaler and the Clock Phase bit as listed in Table 23-12. See the BR[0:3] field description for details on how to compute the baud rate. If the overall baud rate is divide by two or divide by three of the system clock then neither the Continuous SCK Enable or the Modified Timing Format Enable bits should be set. 0 The baud rate is computed normally with a 50/50 duty cycle 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler Frame Size The FMSZ field selects the number of bits transferred per frame. The FMSZ field is used in Master Mode and Slave Mode. Table 23-13 lists the frame size encodings. Clock Polarity The CPOL bit selects the inactive state of the Serial Communications Clock (SCK). This bit is used in both Master and Slave Mode. For successful communication between serial devices, the devices must have identical clock polarities. When the Continuous Selection Format is selected, switching between clock polarities without stopping the DSPI can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 The inactive state value of SCK is low 1 The inactive state value of SCK is high MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 479 Table 23-5. DSPIx_CTARn field descriptions (continued) Field Descriptions CPHA Clock Phase The CPHA bit selects which edge of SCK causes data to change and which edge causes data to be captured. This bit is used in both Master and Slave Mode. For successful communication between serial devices, the devices must have identical clock phase settings. Continuous SCK is only supported for CPHA = 1. 0 Data is captured on the leading edge of SCK and changed on the following edge 1 Data is changed on the leading edge of SCK and captured on the following edge LSBFE LSB First The LSBFE bit selects if the LSB or MSB of the frame is transferred first. This bit is only used in Master Mode. 0 Data is transferred MSB first 1 Data is transferred LSB first PCSSCK PCS to SCK Delay Prescaler The PCSSCK field selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK. This field is only used in Master Mode. The table below lists the prescaler values. See the CSSCK field description for details on how to compute the PCS to SCK delay. PCSSCK 00 01 10 11 PCS to SCK delay prescaler value 1 3 5 7 PASC After SCK Delay Prescaler The PASC field selects the prescaler value for the delay between the last edge of SCK and the negation of PCS. This field is only used in Master Mode. The table below lists the prescaler values. See the ASC[0:3] field description for details on how to compute the After SCK delay. PASC 00 01 10 11 After SCK delay prescaler value 1 3 5 7 MPC5604B/C Microcontroller Reference Manual, Rev. 8 480 Freescale Semiconductor Table 23-5. DSPIx_CTARn field descriptions (continued) Field PDT Descriptions Delay after Transfer Prescaler The PDT field selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame. The PDT field is only used in Master Mode. The table below lists the prescaler values. See the DT[0:3] field description for details on how to compute the delay after transfer. PDT 00 01 10 11 Delay after transfer prescaler value 1 3 5 7 PBR Baud Rate Prescaler The PBR field selects the prescaler value for the baud rate. This field is only used in Master Mode. The Baud Rate is the frequency of the Serial Communications Clock (SCK). The system clock is divided by the prescaler value before the baud rate selection takes place. The Baud Rate Prescaler values are listed in the table below. See the BR[0:3] field description for details on how to compute the baud rate. PBR 00 01 10 11 Baud rate prescaler value 2 3 5 7 CSSCK PCS to SCK Delay Scaler The CSSCK field selects the scaler value for the PCS to SCK delay. This field is only used in Master Mode. The PCS to SCK Delay is the delay between the assertion of PCS and the first edge of the SCK. Table 23-14 list the scaler values.The PCS to SCK Delay is a multiple of the system clock period and it is computed according to the following equation: tCSC = -----1-----  PCSSCK  CSSCK fSYS See Section 23.6.4.2, CS to SCK delay (tCSC),” for more details. Eqn. 23-1 ASC After SCK Delay Scaler The ASC field selects the scaler value for the After SCK Delay. This field is only used in Master Mode. The After SCK Delay is the delay between the last edge of SCK and the negation of PCS. Table 23-15 lists the scaler values.The After SCK Delay is a multiple of the system clock period, and it is computed according to the following equation: tASC = -----1-----  PASC  ASC fSYS See Section 23.6.4.3, After SCK delay (tASC),” for more details. Eqn. 23-2 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 481 Table 23-5. DSPIx_CTARn field descriptions (continued) Field DT BR Descriptions Delay after Transfer Scaler The DT field selects the Delay after Transfer Scaler. This field is only used in Master Mode. The Delay after Transfer is the time between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame. Table 23-16 lists the scaler values. In the Continuous Serial Communications Clock operation the DT value is fixed to one TSCK. The Delay after Transfer is a multiple of the system clock period and it is computed according to the following equation: tDT = -----1-----  PDT  DT fSYS See Section 23.6.4.4, Delay after transfer (tDT),” for more details. Eqn. 23-3 Baud Rate Scaler The BR field selects the scaler value for the baud rate. This field is only used in Master Mode. The prescaled system clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. Table 23-17 lists the Baud Rate Scaler values.The baud rate is computed according to the following equation: SCK baud rate = -f--S---Y----S-  1-----+-----D-----B----R-PBR BR See Section 23.6.4.2, CS to SCK delay (tCSC),” for more details. Eqn. 23-4 DBR 0 1 1 1 1 1 1 1 1 Table 23-6. DSPI SCK duty cycle CPHA any 0 0 0 0 1 1 1 1 PBR any 00 01 10 11 00 01 10 11 SCK duty cycle 50/50 50/50 33/66 40/60 43/57 50/50 66/33 60/40 57/43 FMSZ 0000 0001 0010 0011 0100 0101 Table 23-7. DSPI transfer frame size Frame size Reserved Reserved Reserved 4 5 6 FMSZ 1000 1001 1010 1011 1100 1101 Frame size 9 10 11 12 13 14 MPC5604B/C Microcontroller Reference Manual, Rev. 8 482 Freescale Semiconductor FMSZ 0110 0111 Table 23-7. DSPI transfer frame size (continued) Frame size 7 8 FMSZ 1110 1111 Frame size 15 16 CSSCK 0000 0001 0010 0011 0100 0101 0110 0111 Table 23-8. DSPI PCS to SCK delay scaler PCS to SCK delay scaler value 2 4 8 16 32 64 128 256 CSSCK 1000 1001 1010 1011 1100 1101 1110 1111 PCS to SCK delay scaler value 512 1024 2048 4096 8192 16384 32768 65536 ASC 0000 0001 0010 0011 0100 0101 0110 0111 Table 23-9. DSPI After SCK delay scaler After SCK delay scaler value ASC After SCK delay scaler value 2 1000 512 4 1001 1024 8 1010 2048 16 1011 4096 32 1100 8192 64 1101 16384 128 1110 32768 256 1111 65536 DT 0000 0001 0010 0011 0100 0101 Table 23-10. DSPI delay after transfer scaler Delay after transfer scaler value 2 4 8 16 32 64 DT 1000 1001 1010 1011 1100 1101 Delay after transfer scaler value 512 1024 2048 4096 8192 16384 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 483 DT 0110 0111 Table 23-10. DSPI delay after transfer scaler (continued) Delay after transfer scaler value 128 256 DT 1110 1111 Delay after transfer scaler value 32768 65536 BR 0000 0001 0010 0011 0100 0101 0110 0111 DBR 0 1 1 1 1 1 1 1 1 FMSZ 0000 0001 0010 0011 Table 23-11. DSPI baud rate scaler Baud rate scaler value 2 4 6 8 16 32 64 128 BR 1000 1001 1010 1011 1100 1101 1110 1111 Baud rate scaler value 256 512 1024 2048 4096 8192 16384 32768 Table 23-12. DSPI SCK duty cycle CPHA any 0 0 0 0 1 1 1 1 PBR any 00 01 10 11 00 01 10 11 SCK duty cycle 50/50 50/50 33/66 40/60 43/57 50/50 66/33 60/40 57/43 Table 23-13. DSPI transfer frame size Frame size Reserved Reserved Reserved 4 FMSZ 1000 1001 1010 1011 Frame size 9 10 11 12 MPC5604B/C Microcontroller Reference Manual, Rev. 8 484 Freescale Semiconductor FMSZ 0100 0101 0110 0111 Table 23-13. DSPI transfer frame size (continued) Frame size 5 6 7 8 FMSZ 1100 1101 1110 1111 Frame size 13 14 15 16 CSSCK 0000 0001 0010 0011 0100 0101 0110 0111 Table 23-14. DSPI PCS to SCK delay scaler PCS to SCK delay scaler value 2 4 8 16 32 64 128 256 CSSCK 1000 1001 1010 1011 1100 1101 1110 1111 PCS to SCK delay scaler value 512 1024 2048 4096 8192 16384 32768 65536 ASC 0000 0001 0010 0011 0100 0101 0110 0111 Table 23-15. DSPI After SCK delay scaler After SCK delay scaler value ASC After SCK delay scaler value 2 1000 512 4 1001 1024 8 1010 2048 16 1011 4096 32 1100 8192 64 1101 16384 128 1110 32768 256 1111 65536 DT 0000 0001 0010 0011 Table 23-16. DSPI delay after transfer scaler Delay after transfer scaler value 2 4 8 16 DT 1000 1001 1010 1011 Delay after transfer scaler value 512 1024 2048 4096 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 485 Table 23-16. DSPI delay after transfer scaler (continued) (continued) DT 0100 0101 0110 0111 Delay after transfer scaler value 32 64 128 256 DT 1100 1101 1110 1111 Delay after transfer scaler value 8192 16384 32768 65536 BR 0000 0001 0010 0011 0100 0101 0110 0111 Table 23-17. DSPI baud rate scaler Baud rate scaler value 2 4 6 8 16 32 64 128 BR 1000 1001 1010 1011 1100 1101 1110 1111 Baud rate scaler value 256 512 1024 2048 4096 8192 16384 32768 23.5.5 DSPI Status Register (DSPIx_SR) The DSPIx_SR contains status and flag bits. The bits are set by the hardware and reflect the status of the DSPI and indicate the occurrence of events that can generate interrupt requests. Software can clear flag bits in the DSPIx_SR by writing a ‘1’ to clear it (w1c). Writing a ‘0’ to a flag bit has no effect. This register may not be writable in Module Disable mode due to the use of power saving mechanisms. Offset: 0x2C Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TCF 0 TFUF 0 TFFF 0 0 0 0 0 0 0 TXRXS EOQF RFOF RFDF W w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 16 R W Reset 0 17 18 TXCTR 00 19 20 21 22 23 24 25 26 27 TXNXTPTR RXCTR 000000000 Figure 23-6. DSPI Status Register (DSPIx_SR) 28 29 30 31 POPNXTPTR 0000 MPC5604B/C Microcontroller Reference Manual, Rev. 8 486 Freescale Semiconductor Field TCF TXRXS EOQF TFUF TFFF RFOF Table 23-18. DSPIx_SR field descriptions Description Transfer complete flag Indicates that all bits in a frame have been shifted out. The TCF bit is set after the last incoming databit is sampled, but before the tASC delay starts. See Section 23.6.5.1, Classic SPI transfer format (CPHA = 0) for details. 0 Transfer not complete 1 Transfer complete TX and RX status Reflects the status of the DSPI. See Section 23.6.2, Start and stop of DSPI transfers for information on what clears and sets this bit. 0 TX and RX operations are disabled (DSPI is in STOPPED state) 1 TX and RX operations are enabled (DSPI is in RUNNING state) End of queue flag Indicates that transmission in progress is the last entry in a queue. The EOQF bit is set when TX FIFO entry has the EOQ bit set in the command halfword and the end of the transfer is reached. See Section 23.6.5.1, Classic SPI transfer format (CPHA = 0) for details. When the EOQF bit is set, the TXRXS bit is automatically cleared. 0 EOQ is not set in the executing command 1 EOQ bit is set in the executing SPI command Note: EOQF does not function in slave mode. Transmit FIFO underflow flag Indicates that an underflow condition in the TX FIFO has occurred. The transmit underflow condition is detected only for DSPI modules operating in slave mode and SPI configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in SPI slave mode is empty, and a transfer is initiated by an external SPI master. 0 TX FIFO underflow has not occurred 1 TX FIFO underflow has occurred Transmit FIFO fill flag Indicates that the TX FIFO can be filled. Provides a method for the DSPI to request more entries to be added to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be cleared by writing ‘1’ to it, or an by acknowledgement from the Edam controller when the TX FIFO is full. 0 TX FIFO is full 1 TX FIFO is not full Receive FIFO overflow flag Indicates that an overflow condition in the RX FIFO has occurred. The bit is set when the RX FIFO and shift register are full and a transfer is initiated. 0 RX FIFO overflow has not occurred 1 RX FIFO overflow has occurred MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 487 Table 23-18. DSPIx_SR field descriptions (continued) Field RFDF Description Receive FIFO drain flag Indicates that the RX FIFO can be drained. Provides a method for the DSPI to request that entries be removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be cleared by writing ‘1’ to it, or by acknowledgement from the Edam controller when the RX FIFO is empty. 0 RX FIFO is empty 1 RX FIFO is not empty Note: In the interrupt service routine, RFDF must be cleared only after the DSPIx_POPR register is read. TXCTR TX FIFO counter Indicates the number of valid entries in the TX FIFO. The TXCTR is incremented every time the DSPI _PUSHR is written. The TXCTR is decremented every time an SPI command is executed and the SPI data is transferred to the shift register. TXNXTPTR Transmit next pointer Indicates which TX FIFO entry is transmitted during the next transfer. The TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to the shift register. See Section 23.6.3.4, Transmit First In First Out (TX FIFO) buffering mechanism for more details. RXCTR RX FIFO counter Indicates the number of entries in the RX FIFO. The RXCTR is decremented every time the DSPI _POPR is read. The RXCTR is incremented after the last incoming databit is sampled, but before the tASC delay starts. See Section 23.6.5.1, Classic SPI transfer format (CPHA = 0) for details. POPNXTPT R Pop next pointer Contains a pointer to the RX FIFO entry that is returned when the DSPIx_POPR is read. The POPNXTPTR is updated when the DSPIx_POPR is read. See Section 23.6.3.5, Receive First In First Out (RX FIFO) buffering mechanism for more details. 23.5.6 DSPI Interrupt Request Enable Register (DSPIx_RSER) The DSPIx_RSER enables flag bits in the DSPIx_SR to generate interrupt requests. Do not write to the DSPIx_RSER while the DSPI is running. MPC5604B/C Microcontroller Reference Manual, Rev. 8 488 Freescale Semiconductor Offset:0x30 Access: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 00 0 0000 0 W TCF_RE EOQF_RE TFUF_RE TFFF_RE TFFF_DIRS RFOF_RE RFDF_RE RFDF_DIRS Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-7. DSPI Interrupt Request Enable Register (DSPIx_RSER) Table 23-19. DSPIx_RSER field descriptions Field Description TCF_RE Transmission complete request enable Enables TCF flag in the DSPIx_SR to generate an interrupt request. 0 TCF interrupt requests are disabled 1 TCF interrupt requests are enabled EOQF_RE DSPI finished request enable Enables the EOQF flag in the DSPIx_SR to generate an interrupt request. 0 EOQF interrupt requests are disabled 1 EOQF interrupt requests are enabled TFUF_RE Transmit FIFO underflow request enable The TFUF_RE bit enables the TFUF flag in the DSPIx_SR to generate an interrupt request. 0 TFUF interrupt requests are disabled 1 TFUF interrupt requests are enabled TFFF_RE Transmit FIFO fill request enable Enables the TFFF flag in the DSPIx_SR to generate a request. The TFFF_DIRS bit selects an interrupt request. 0 TFFF interrupt requests are disabled 1 TFFF interrupt requests are enabled TFFF_DIRS Transmit FIFO fill interrupt request select Selects an interrupt request. When the TFFF flag bit in the DSPIx_SR is set, and the TFFF_RE bit in the DSPIx_RSER is set, this bit selects an interrupt request. 0 Interrupt request is selected 1 Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 489 Table 23-19. DSPIx_RSER field descriptions (continued) Field Description RFOF_RE Receive FIFO overflow request enable Enables the RFOF flag in the DSPIx_SR to generate an interrupt requests. 0 RFOF interrupt requests are disabled 1 RFOF interrupt requests are enabled RFDF_RE Receive FIFO drain request enable Enables the RFDF flag in the DSPIx_SR to generate a request. The RFDF_DIRS bit selects an interrupt request. 0 RFDF interrupt requests are disabled 1 RFDF interrupt requests are enabled RFDF_DIRS Receive FIFO drain interrupt request select Selects an interrupt request. When the RFDF flag bit in the DSPIx_SR is set, and the RFDF_RE bit in the DSPIx_RSER is set, the RFDF_DIRS bit selects an interrupt request. 0 Interrupt request is selected 1 Reserved 23.5.7 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) The DSPIx_PUSHR provides a means to write to the TX FIFO. Data written to this register is transferred to the TX FIFO. See Section 23.6.3.4, Transmit First In First Out (TX FIFO) buffering mechanism, for more information. Write accesses of 8 or 16 bits to the DSPIx_PUSHR transfers 32 bits to the TX FIFO. NOTE TXDATA is used in master and slave modes. Offset:0x34 Access: Read/write CONT CTCNT PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 00 CTAS EOQ 00 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-8. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 490 Freescale Semiconductor Table 23-20. DSPIx_PUSHR field descriptions Field Description CONT Continuous peripheral chip select enable Selects a continuous selection format. The bit is used in SPI master mode. The bit enables the selected CS signals to remain asserted between transfers. See Section 23.6.5.5, Continuous selection format, for more information. CTAS 0 Return peripheral chip select signals to their inactive state between transfers 1 Keep peripheral chip select signals asserted between transfers Clock and transfer attributes select Selects which of the DSPIx_CTARs is used to set the transfer attributes for the SPI frame. In SPI slave mode, DSPIx_CTAR0 is used. The following table shows how the CTAS values map to the DSPIx_CTARs. There are eight DSPIx_CTARs in the device DSPI implementation. Note: Use in SPI master mode only. CTAS 000 001 010 011 100 101 110 111 Use clock and transfer attributes from DSPIx_CTAR0 DSPIx_CTAR1 DSPIx_CTAR2 DSPIx_CTAR3 DSPIx_CTAR4 DSPIx_CTAR5 Reserved Reserved EOQ End of queue Provides a means for host software to signal to the DSPI that the current SPI transfer is the last in a queue. At the end of the transfer the EOQF bit in the DSPIx_SR is set. 0 The SPI data is not the last data to transfer 1 The SPI data is the last data to transfer Note: Use in SPI master mode only. CTCNT Clear SPI_TCNT Provides a means for host software to clear the SPI transfer counter. The CTCNT bit clears the SPI_TCNT field in the DSPIx_TCR. The SPI_TCNT field is cleared before transmission of the current SPI frame begins. 0 Do not clear SPI_TCNT field in the DSPIx_TCR 1 Clear SPI_TCNT field in the DSPIx_TCR Note: Use in SPI master mode only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 491 Table 23-20. DSPIx_PUSHR field descriptions (continued) Field PCSx Description Peripheral chip select x Selects which CSx signals are asserted for the transfer. 0 Negate the CSx signal 1 Assert the CSx signal Note: Use in SPI master mode only. TXDATA Transmit data Holds SPI data for transfer according to the associated SPI command. Note: Use TXDATA in master and slave modes. 23.5.8 DSPI POP RX FIFO Register (DSPIx_POPR) The DSPIx_POPR allows you to read the RX FIFO. See Section 23.6.3.5, Receive First In First Out (RX FIFO) buffering mechanism for a description of the RX FIFO operations. Eight or 16-bit read accesses to the DSPIx_POPR fetch the RX FIFO data, and update the counter and pointer. NOTE Reading the RX FIFO field fetches data from the RX FIFO. Once the RX FIFO is read, the read data pointer is moved to the next entry in the RX FIFO. Therefore, read DSPIx_POPR only when you need the data. For compatibility, configure the TLB entry for DSPIx_POPR as guarded. Offset:0x38 Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-9. DSPI POP RX FIFO Register (DSPIx_POPR) Table 23-21. DSPIx_POPR field descriptions Field Description RXDATA Received data The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next data pointer (POPNXTPTR). MPC5604B/C Microcontroller Reference Manual, Rev. 8 492 Freescale Semiconductor 23.5.9 DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) The DSPIx_TXFRn registers provide visibility into the TX FIFO for debugging purposes. Each register is an entry in the TX FIFO. The registers are read-only and cannot be modified. Reading the DSPIx_TXFRn registers does not alter the state of the TX FIFO. The MCU uses four registers to implement the TX FIFO, that is DSPIx_TXFR0–DSPIx_TXFR3 are used. Offsets: 0x3C–0x48 (4 registers) Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TXCMD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-10. DSPI Transmit FIFO Register 0–3 (DSPIx_TXFRn) Table 23-22. DSPIx_TXFRn field descriptions Field Description TXCMD Transmit command Contains the command that sets the transfer attributes for the SPI data. See Section 23.5.7, DSPI PUSH TX FIFO Register (DSPIx_PUSHR), for details on the command field. TXDATA Transmit data Contains the SPI data to be shifted out. 23.5.9.1 DSPI Receive FIFO Registers 0–3 (DSPIx_RXFRn) The DSPIx_RXFRn registers provide visibility into the RX FIFO for debugging purposes. Each register is an entry in the RX FIFO. The DSPIx_RXFR registers are read-only. Reading the DSPIx_RXFRn registers does not alter the state of the RX FIFO. The device uses four registers to implement the RX FIFO, that is DSPIx_RXFR0–DSPIx_RXFR3 are used. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 493 Offsets: 0x7C–0x88 (4 registers) Access: Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-11. DSPI Receive FIFO Registers 0–3 (DSPIx_RXFRn) Table 23-23. DSPIx_RXFRn field description Field RXDATA Receive data Contains the received SPI data. Description 23.6 Functional description The DSPI supports full-duplex, synchronous serial communications between the MCU and peripheral devices. All communications are through an SPI-like protocol. The DSPI has one configuration, namely serial peripheral interface (SPI), in which the DSPI operates as a basic SPI or a queued SPI. The DCONF field in the DSPIx_MCR register determines the DSPI configuration. See Table 23-3 for the DSPI configuration values. The DSPIx_CTAR0–DSPIx_CTAR5 registers hold clock and transfer attributes.The SPI configuration can select which CTAR to use on a frame by frame basis by setting the CTAS field in the DSPIx_PUSHR. The 16-bit shift register in the master and the 16-bit shift register in the slave are linked by the SOUT_x and SIN_x signals to form a distributed 32-bit register. When a data transfer operation is performed, data is serially shifted a pre-determined number of bit positions. Because the registers are linked, data is exchanged between the master and the slave; the data that was in the master’s shift register is now in the shift register of the slave, and vice versa. At the end of a transfer, the TCF bit in the DSPIx_SR is set to indicate a completed transfer. Figure 23-12 illustrates how master and slave data is exchanged. MPC5604B/C Microcontroller Reference Manual, Rev. 8 494 Freescale Semiconductor DSPI Master Shift register Baud rate generator SIN_x SOUT_x SOUT_x SIN_x SCK_x SCK_x CS_x CS0_x DSPI Slave Shift register Figure 23-12. SPI serial protocol overview The DSPI has six peripheral chip select (CSx) signals that are be used to select which of the slaves to communicate with. Transfer protocols and timing properties are shared by the three DSPI configurations; these properties are described independently of the configuration in Section 23.6.5, Transfer formats. The transfer rate and delay settings are described in Section 23.6.4, DSPI baud rate and clock delay generation. See Section 23.6.8, Power saving features, for information on the power-saving features of the DSPI. 23.6.1 Modes of operation The DSPI modules have the following available distinct modes: • Master mode • Slave mode • Module Disable mode • Debug mode Master, slave, and module disable modes are module-specific modes whereas debug mode is device-specific. The module-specific modes are determined by bits in the DSPIx_MCR. Debug mode is a mode that the entire device can enter in parallel with the DSPI being configured in one of its module-specific modes. 23.6.1.1 Master mode In master mode the DSPI can initiate communications with peripheral devices. The DSPI operates as bus master when the MSTR bit in the DSPIx_MCR is set. The serial communications clock (SCK) is controlled by the master DSPI. All three DSPI configurations are valid in master mode. In SPI configuration, master mode transfer attributes are controlled by the SPI command in the current TX FIFO entry. The CTAS field in the SPI command selects which of the eight DSPIx_CTARs are used to set the transfer attributes. Transfer attribute control is on a frame by frame basis. See Section 23.6.3, Serial peripheral interface (SPI) configuration for more details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 495 23.6.1.2 Slave mode In slave mode the DSPI responds to transfers initiated by an SPI master. The DSPI operates as bus slave when the MSTR bit in the DSPIx_MCR is negated. The DSPI slave is selected by a bus master by having the slave’s CS0_x asserted. In slave mode the SCK is provided by the bus master. All transfer attributes are controlled by the bus master, except the clock polarity, clock phase and the number of bits to transfer which must be configured in the DSPI slave to communicate correctly. 23.6.1.3 Module Disable mode The module disable mode is used for MCU power management. The clock to the non-memory mapped logic in the DSPI is stopped while in module disable mode. The DSPI enters the module disable mode when the MDIS bit in DSPIx_MCR is set. See Section 23.6.8, Power saving features, for more details on the module disable mode. 23.6.1.4 Debug mode The debug mode is used for system development and debugging. If the MCU enters debug mode while the FRZ bit in the DSPIx_MCR is set, the DSPI stops all serial transfers and enters a stopped state. If the MCU enters debug mode while the FRZ bit is cleared, the DSPI behavior is unaffected and remains dictated by the module-specific mode and configuration of the DSPI. The DSPI enters debug mode when a debug request is asserted by an external controller. See Figure 23-13 for a state diagram. 23.6.2 Start and stop of DSPI transfers The DSPI has two operating states: STOPPED and RUNNING. The states are independent of DSPI configuration. The default state of the DSPI is STOPPED. In the STOPPED state no serial transfers are initiated in master mode and no transfers are responded to in slave mode. The STOPPED state is also a safe state for writing the various configuration registers of the DSPI without causing undetermined results. The TXRXS bit in the DSPIx_SR is cleared in this state. In the RUNNING state, serial transfers take place. The TXRXS bit in the DSPIx_SR is set in the RUNNING state. Figure 23-13 shows a state diagram of the start and stop mechanism. MPC5604B/C Microcontroller Reference Manual, Rev. 8 496 Freescale Semiconductor RESET Power-on-Reset 0 1 STOPPED TXRXS = 0 RUNNING TXRXS = 1 2 Figure 23-13. DSPI start and stop state diagram The transitions are described in Table 23-24. Table 23-24. State transitions for start and stop of DSPI transfers Transition No. Current state Next state Description 0 RESET STOPPED Generic power-on-reset transition 1 STOPPED RUNNING The DSPI starts (transitions from STOPPED to RUNNING) when all of the following conditions are true: • EOQF bit is clear • Debug mode is unselected or the FRZ bit is clear • HALT bit is clear 2 RUNNING STOPPED The DSPI stops (transitions from RUNNING to STOPPED) after the current frame for any one of the following conditions: • EOQF bit is set • Debug mode is selected and the FRZ bit is set • HALT bit is set State transitions from RUNNING to STOPPED occur on the next frame boundary if a transfer is in progress, or on the next system clock cycle if no transfers are in progress. 23.6.3 Serial peripheral interface (SPI) configuration The SPI configuration transfers data serially using a shift register and a selection of programmable transfer attributes. The DSPI is in SPI configuration when the DCONF field in the DSPIx_MCR is 0b00. The SPI frames can be from 4 to 16 bits long. The data to be transmitted can come from queues stored in SRAM external to the DSPI. Host software can transfer the SPI data from the queues to a first-in first-out (FIFO) buffer. The received data is stored in entries in the receive FIFO (RX FIFO) buffer. Host software transfers the received data from the RX FIFO to memory external to the DSPI. The FIFO buffer operations are described in Section 23.6.3.4, Transmit First In First Out (TX FIFO) buffering mechanism, and Section 23.6.3.5, Receive First In First Out (RX FIFO) buffering mechanism. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 497 The interrupt request conditions are described in Section 23.6.7, Interrupt requests. The SPI configuration supports two module-specific modes; master mode and slave mode. The FIFO operations are similar for the master mode and slave mode. The main difference is that in master mode the DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO entry. In slave mode the DSPI only responds to transfers initiated by a bus master external to the DSPI and the SPI command field of the TX FIFO entry is ignored. 23.6.3.1 SPI Master mode In SPI master mode the DSPI initiates the serial transfers by controlling the serial communications clock (SCK_x) and the peripheral chip select (CSx) signals. The SPI command field in the executing TX FIFO entry determines which CTARs are used to set the transfer attributes and which CSx signal to assert. The command field also contains various bits that help with queue management and transfer protocol. The data field in the executing TX FIFO entry is loaded into the shift register and shifted out on the serial out (SOUT_x) pin. In SPI master mode, each SPI frame to be transmitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. See Section 23.5.7, DSPI PUSH TX FIFO Register (DSPIx_PUSHR), for details on the SPI command fields. 23.6.3.2 SPI Slave mode In SPI slave mode the DSPI responds to transfers initiated by an SPI bus master. The DSPI does not initiate transfers. Certain transfer attributes such as clock polarity, clock phase and frame size must be set for successful communication with an SPI master. The SPI slave mode transfer attributes are set in the DSPIx_CTAR0. 23.6.3.3 FIFO disable operation The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO. The DSPI operates as a double-buffered simplified SPI when the FIFOs are disabled. The TX and RX FIFOs are disabled separately. The TX FIFO is disabled by writing a ‘1’ to the DIS_TXF bit in the DSPIx_MCR. The RX FIFO is disabled by writing a ‘1’ to the DIS_RXF bit in the DSPIx_MCR. The FIFO disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the DSPIx_PUSHR and received data is read from the DSPIx_POPR. When the TX FIFO is disabled, the TFFF, TFUF, and TXCTR fields in DSPIx_SR behave as if there is a one-entry FIFO but the contents of the DSPIx_TXFRs and TXNXTPTR are undefined. When the RX FIFO is disabled, the RFDF, RFOF, and RXCTR fields in the DSPIx_SR behave as if there is a one-entry FIFO but the contents of the DSPIx_RXFRs and POPNXTPTR are undefined. Disable the TX and RX FIFOs only if the FIFO must be disabled as a requirement of the application's operating mode. A FIFO must be disabled before it is accessed. Failure to disable a FIFO prior to a first FIFO access is not supported, and can result in incorrect results. MPC5604B/C Microcontroller Reference Manual, Rev. 8 498 Freescale Semiconductor 23.6.3.4 Transmit First In First Out (TX FIFO) buffering mechanism The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX FIFO holds four entries, each consisting of a command field and a data field. SPI commands and data are added to the TX FIFO by writing to the DSPI push TX FIFO register (DSPIx_PUSHR). TX FIFO entries can only be removed from the TX FIFO by being shifted out or by flushing the TX FIFO. For more information on DSPIx_PUSHR, see Section 23.5.7, DSPI PUSH TX FIFO Register (DSPIx_PUSHR). The TX FIFO counter field (TXCTR) in the DSPI status register (DSPIx_SR) indicates the number of valid entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data is transferred into the shift register from the TX FIFO. See Section 23.5.5, DSPI Status Register (DSPIx_SR) for more information on DSPIx_SR. The TXNXTPTR field indicates which TX FIFO entry is transmitted during the next transfer. The TXNXTPTR contains the positive offset from DSPIx_TXFR0 in number of 32-bit registers. For example, TXNXTPTR equal to two means that the DSPIx_TXFR2 contains the SPI data and command for the next transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the shift register. 23.6.3.4.1 Filling the TX FIFO Host software can add (push) entries to the TX FIFO by writing to the DSPIx_PUSHR. When the TX FIFO is not full, the TX FIFO fill flag (TFFF) in the DSPIx_SR is set. The TFFF bit is cleared when the TX FIFO is full or alternatively by host software writing a ‘1’ to the TFFF in the DSPIx_SR. The TFFF then generates an interrupt request. See Section 23.6.7.2, Transmit FIFO Fill Interrupt Request (TFFF), for details. The DSPI ignores attempts to push data to a full TX FIFO; that is, the state of the TX FIFO is unchanged. No error condition is indicated. 23.6.3.4.2 Draining the TX FIFO The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO counter is decremented by one. At the end of a transfer, the TCF bit in the DSPIx_SR is set to indicate the completion of a transfer. The TX FIFO is flushed by writing a ‘1’ to the CLR_TXF bit in DSPIx_MCR. If an external SPI bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is empty, the transmit FIFO underflow flag (TFUF) in the slave’s DSPIx_SR is set. See Section 23.6.7.4, Transmit FIFO Underflow Interrupt Request (TFUF), for details. 23.6.3.5 Receive First In First Out (RX FIFO) buffering mechanism The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds four received SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the received data in the shift register is transferred into the RX FIFO. SPI data is removed (popped) from the RX FIFO by MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 499 reading the DSPIx_POPR register. RX FIFO entries can only be removed from the RX FIFO by reading the DSPIx_POPR or by flushing the RX FIFO. See Section 23.5.8, DSPI POP RX FIFO Register (DSPIx_POPR) for more information on the DSPIx_POPR. The RX FIFO counter field (RXCTR) in the DSPI status register (DSPIx_SR) indicates the number of valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is copied from the shift register to the RX FIFO. The POPNXTPTR field in the DSPIx_SR points to the RX FIFO entry that is returned when the DSPIx_POPR is read. The POPNXTPTR contains the positive, 32-bit word offset from DSPIx_RXFR0. For example, POPNXTPTR equal to two means that the DSPIx_RXFR2 contains the received SPI data that is returned when DSPIx_POPR is read. The POPNXTPTR field is incremented every time the DSPIx_POPR is read. POPNXTPTR rolls over every four frames on the MCU. 23.6.3.5.1 Filling the RX FIFO The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full, SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred to the RX FIFO the RX FIFO counter is incremented by one. If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPIx_SR is set indicating an overflow condition. Depending on the state of the ROOE bit in the DSPIx_MCR, the data from the transfer that generated the overflow is ignored or put in the shift register. If the ROOE bit is set, the incoming data is put in the shift register. If the ROOE bit is cleared, the incoming data is ignored. 23.6.3.5.2 Draining the RX FIFO Host software can remove (pop) entries from the RX FIFO by reading the DSPIx_POPR. A read of the DSPIx_POPR decrements the RX FIFO counter by one. Attempts to pop data from an empty RX FIFO are ignored, the RX FIFO counter remains unchanged. The data returned from reading an empty RX FIFO is undetermined. See Section 23.5.8, DSPI POP RX FIFO Register (DSPIx_POPR) for more information on DSPIx_POPR. When the RX FIFO is not empty, the RX FIFO drain flag (RFDF) in the DSPIx_SR is set. The RFDF bit is cleared when the RX_FIFO is empty; alternatively the RFDF bit can be cleared by the host writing a ‘1’ to it. 23.6.4 DSPI baud rate and clock delay generation The SCK_x frequency and the delay values for serial transfer are generated by dividing the system clock frequency by a prescaler and a scaler with the option of doubling the baud rate. MPC5604B/C Microcontroller Reference Manual, Rev. 8 500 Freescale Semiconductor Figure 23-14 shows conceptually how the SCK signal is generated. System Clock 1 Prescaler 1 + DBR Scaler SCK_x Figure 23-14. Communications clock prescalers and scalers 23.6.4.1 Baud rate generator The baud rate is the frequency of the serial communication clock (SCK_x). The system clock is divided by a baud rate prescaler (defined by DSPIx_CTAR[PBR]) and baud rate scaler (defined by DSPIx_CTAR[BR]) to produce SCK_x with the possibility of doubling the baud rate. The DBR, PBR, and BR fields in the DSPIx_CTARs select the frequency of SCK_x using the following formula: SCK baud rate = -----------------------f-S-----Y----S------------------------- ¥ -----------1-----+-----D-----B----R-------------PBRPrescalerValue BRScalerValue Table 23-25 shows an example of a computed baud rate. Table 23-25. Baud rate computation example fSYS 64 MHz 20 MHz PBR 0b00 0b00 Prescaler value 2 2 BR 0b0000 0b0000 Scaler value 2 2 DBR value 0 1 Baud rate 16 Mbit/s 10 Mbit/s 23.6.4.2 CS to SCK delay (tCSC) The CS_x to SCK_x delay is the length of time from assertion of the CS_x signal to the first SCK_x edge. See Figure 23-16 for an illustration of the CS_x to SCK_x delay. The PCSSCK and CSSCK fields in the DSPIx_CTARn registers select the CS_x to SCK_x delay, and the relationship is expressed by the following formula: tCSC = 1  PCSSCK fSYS  CSSCK Table 23-26 shows an example of the computed CS to SCK_x delay. Table 23-26. CS to SCK delay computation example PCSSCK 0b01 Prescaler value 3 CSSCK 0b0100 Scaler value 32 fSYS 64 MHz CS to SCK delay 1.5 µs MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 501 23.6.4.3 After SCK delay (tASC) The after SCK_x delay is the length of time between the last edge of SCK_x and the negation of CS_x. See Figure 23-16 and Figure 23-17 for illustrations of the after SCK_x delay. The PASC and ASC fields in the DSPIx_CTARn registers select the after SCK delay. The relationship between these variables is given in the following formula: tASC = 1  PASC fSYS  ASC Table 23-27 shows an example of the computed after SCK delay. Table 23-27. After SCK delay computation example PASC 0b01 Prescaler value 3 ASC 0b0100 Scaler value 32 fSYS 64 MHz After SCK delay 1.5 µs 23.6.4.4 Delay after transfer (tDT) The delay after transfer is the length of time between negation of the CSx signal for a frame and the assertion of the CSx signal for the next frame. The PDT and DT fields in the DSPIx_CTARn registers select the delay after transfer. See Figure 23-16 for an illustration of the delay after transfer. The following formula expresses the PDT/DT/delay after transfer relationship: tDT = 1 fSYS  PDT  DT Table 23-28 shows an example of the computed delay after transfer. Table 23-28. Delay after transfer computation example PDT 0b01 Prescaler value 3 DT 0b1110 Scaler value 32768 fSYS 64 MHz Delay after transfer 1.54 ms 23.6.4.5 Peripheral chip select strobe enable (CS5_x) The CS5_x signal provides a delay to allow the CSx signals to settle after transitioning thereby avoiding glitches. When the DSPI is in master mode and PCSSE bit is set in the DSPIx_MCR, CS5_x provides a signal for an external demultiplexer to decode the CS4_x signals into as many as 32 glitch-free CSx signals. MPC5604B/C Microcontroller Reference Manual, Rev. 8 502 Freescale Semiconductor Figure 23-15 shows the timing of the CS5_x signal relative to CS signals. CSx CS5_x tPCSSCK tPASC Figure 23-15. Peripheral chip select strobe timing The delay between the assertion of the CSx signals and the assertion of CS5_x is selected by the PCSSCK field in the DSPIx_CTAR based on the following formula: tPCSSCK = 1  PCSSCK fSYS At the end of the transfer the delay between CS5_x negation and CSx negation is selected by the PASC field in the DSPIx_CTAR based on the following formula: tPASC = 1 fSYS  PASC Table 23-29 shows an example of the computed tPCSSCK delay. Table 23-29. Peripheral chip select strobe assert computation example PCSSCK 0b11 Prescaler 7 fSYS 64 MHz Delay before transfer 109.4 ns Table 23-30 shows an example of the computed the tPASC delay. Table 23-30. Peripheral chip select strobe negate computation example PASC 0b11 Prescaler 7 fSYS 64 MHz Delay after transfer 109.4 ns 23.6.5 Transfer formats The SPI serial communication is controlled by the serial communications clock (SCK_x) signal and the CSx signals. The SCK_x signal provided by the master device synchronizes shifting and sampling of the data by the SIN_x and SOUT_x pins. The CSx signals serve as enable signals for the slave devices. When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI clock and transfer attributes registers (DSPIx_CTARn) select the polarity and phase of the serial clock, SCK_x. The polarity bit selects MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 503 the idle state of the SCK_x. The clock phase bit selects if the data on SOUT_x is valid before or on the first SCK_x edge. When the DSPI is the bus slave, CPOL and CPHA bits in the DSPIx_CTAR0 (SPI slave mode) select the polarity and phase of the serial clock. Even though the bus slave does not control the SCK signal, clock polarity, clock phase and number of bits to transfer must be identical for the master device and the slave device to ensure proper transmission. The DSPI supports four different transfer formats: • Classic SPI with CPHA = 0 • Classic SPI with CPHA = 1 • Modified transfer format with CPHA = 0 • Modified transfer format with CPHA = 1 A modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle to give the peripheral more setup time. The MTFE bit in the DSPIx_MCR selects between classic SPI format and modified transfer format. The classic SPI formats are described in Section 23.6.5.1, Classic SPI transfer format (CPHA = 0) and Section 23.6.5.2, Classic SPI transfer format (CPHA = 1). The modified transfer formats are described in Section 23.6.5.3, Modified SPI transfer format (MTFE = 1, CPHA = 0) and Section 23.6.5.4, Modified SPI transfer format (MTFE = 1, CPHA = 1). In the SPI configuration, the DSPI provides the option of keeping the CS signals asserted between frames. See Section 23.6.5.5, Continuous selection format for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 504 Freescale Semiconductor 23.6.5.1 Classic SPI transfer format (CPHA = 0) The transfer format shown in Figure 23-16 is used to communicate with peripheral SPI slave devices where the first data bit is available on the first clock edge. In this format, the master and slave sample their SIN_x pins on the odd-numbered SCK_x edges and change the data on their SOUT_x pins on the even-numbered SCK_x edges. SCK (CPOL = 0) SCK (CPOL = 1) Master and slave sample Master SOUT / Slave SIN Master SIN / Slave SOUT Master (CPHA = 0): TCF and EOQF are set and RXCTR counter is updated at next to last SCK edge of frame (edge 15) Slave (CPHA = 0): TCF is set and RXCTR counter is updated at last SCK edge of frame (edge 16) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PCSx / SS tCSC MSB first (LSBFE = 0): MSB Bit 6 Bit 5 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 tCSC = CSCS to SCK delay. tASC = After SCK delay. tDT = Delay after transfer (minimum CS idle time). Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 tASC tDT LSB tCSC MSB Figure 23-16. DSPI transfer timing diagram (MTFE = 0, CPHA = 0, FMSZ = 8) The master initiates the transfer by placing its first data bit on the SOUT_x pin and asserting the appropriate peripheral chip select signals to the slave device. The slave responds by placing its first data bit on its SOUT_x pin. After the tCSC delay has elapsed, the master outputs the first edge of SCK_x. This is the edge used by the master and slave devices to sample the first input data bit on their serial data input signals. At the second edge of the SCK_x the master and slave devices place their second data bit on their serial data output signals. For the rest of the frame the master and the slave sample their SIN_x pins on the odd-numbered clock edges and changes the data on their SOUT_x pins on the even-numbered clock edges. After the last clock edge occurs a delay of tASC is inserted before the master negates the CS signals. A delay of tDT is inserted before a new frame transfer can be initiated by the master. For the CPHA = 0 condition of the master, TCF and EOQF are set and the RXCTR counter is updated at the next to last serial clock edge of the frame (edge 15) of Figure 23-16. For the CPHA = 0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial clock edge of the frame (edge 16) of Figure 23-16. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 505 23.6.5.2 Classic SPI transfer format (CPHA = 1) This transfer format shown in Figure 23-17 is used to communicate with peripheral SPI slave devices that require the first SCK_x edge before the first data bit becomes available on the slave SOUT_x pin. In this format the master and slave devices change the data on their SOUT_x pins on the odd-numbered SCK_x edges and sample the data on their SIN_x pins on the even-numbered SCK_x edges. SCK (CPOL = 0) SCK (CPOL = 1) Master and slave sample Master SOUT/ Slave SIN Master SIN/ Slave SOUT Master (CPHA = 1): TCF and EOQF are set and RXCTR counter is updated at last SCK edge of frame (edge 16) Slave (CPHA = 1): TCF is set and RXCTR counter is updated at last SCK edge of frame (edge 16) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PCSx / SS tCSC MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 tCSC = CS to SCK delay. tASC = After SCK delay. tDT = Delay after transfer (minimum CS negation time). Bit 3 Bit 4 Bit 2 Bit 5 tASC tDT Bit 1 LSB Bit 6 MSB Figure 23-17. DSPI transfer timing diagram (MTFE = 0, CPHA = 1, FMSZ = 8) The master initiates the transfer by asserting the CSx signal to the slave. After the tCSC delay has elapsed, the master generates the first SCK_x edge and at the same time places valid data on the master SOUT_x pin. The slave responds to the first SCK_x edge by placing its first data bit on its slave SOUT_x pin. At the second edge of the SCK_x the master and slave sample their SIN_x pins. For the rest of the frame the master and the slave change the data on their SOUT_x pins on the odd-numbered clock edges and sample their SIN_x pins on the even-numbered clock edges. After the last clock edge occurs a delay of tASC is inserted before the master negates the CSx signal. A delay of tDT is inserted before a new frame transfer can be initiated by the master. For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of Figure 23-17. For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge. MPC5604B/C Microcontroller Reference Manual, Rev. 8 506 Freescale Semiconductor 23.6.5.3 Modified SPI transfer format (MTFE = 1, CPHA = 0) In this modified transfer format both the master and the slave sample later in the SCK period than in classic SPI mode to allow for delays in device pads and board traces. These delays become a more significant fraction of the SCK period as the SCK period decreases with increasing baud rates. NOTE For the modified transfer format to operate correctly, you must thoroughly analyze the SPI link timing budget. The master and the slave place data on the SOUT_x pins at the assertion of the CSx signal. After the CSx to SCK_x delay has elapsed the first SCK_x edge is generated. The slave samples the master SOUT_x signal on every odd numbered SCK_x edge. The slave also places new data on the slave SOUT_x on every odd numbered clock edge. The master places its second data bit on the SOUT_x line one system clock after odd numbered SCK_x edge. The point where the master samples the slave SOUT_x is selected by writing to the SMPL_PT field in the DSPIx_MCR. Table 23-31 lists the number of system clock cycles between the active edge of SCK_x and the master sample point for different values of the SMPL_PT bit field. The master sample point can be delayed by one or two system clock cycles. Table 23-31. Delayed master sample point SMPL_PT Number of system clock cycles between odd-numbered edge of SCK and sampling of SIN 00 0 01 1 10 2 11 Invalid value MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 507 Figure 23-18 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is illustrated. The delayed master sample points are indicated with a lighter shaded arrow. System clock 123456 SCK Slave sample Master sample Slave SOUT Master SOUT CSx tCSC System clock System clock tASC tCSC = CS to SCK delay. tASC = After SCK delay. Figure 23-18. DSPI modified transfer format (MTFE = 1, CPHA = 0, fSCK = fSYS / 4) 23.6.5.4 Modified SPI transfer format (MTFE = 1, CPHA = 1) At the start of a transfer the DSPI asserts the CS signal to the slave device. After the CS to SCK delay has elapsed the master and the slave put data on their SOUT pins at the first edge of SCK. The slave samples the master SOUT signal on the even numbered edges of SCK. The master samples the slave SOUT signal on the odd numbered SCK edges starting with the third SCK edge. The slave samples the last bit on the last edge of the SCK. The master samples the last slave SOUT bit one half SCK cycle after the last edge of SCK. No clock edge is visible on the master SCK pin during the sampling of the last bit. The SCK to CS delay must be greater or equal to half of the SCK period. NOTE For the modified transfer format to operate correctly, you must thoroughly analyze the SPI link timing budget. MPC5604B/C Microcontroller Reference Manual, Rev. 8 508 Freescale Semiconductor Figure 23-19 shows the modified transfer format for CPHA = 1. Only the condition where CPOL = 0 is described. System clock 123456 SCK Slave sample Master sample Master SOUT Slave SOUT CS tCSC tCSC = CS to SCK delay. tASC = After SCK delay. tASC Figure 23-19. DSPI modified transfer format (MTFE = 1, CPHA = 1, fSCK = fSYS / 4) 23.6.5.5 Continuous selection format Some peripherals must be deselected between every transfer. Other peripherals must remain selected between several sequential serial transfers. The continuous selection format provides the flexibility to handle both cases. The continuous selection format is enabled for the SPI configuration by setting the CONT bit in the SPI command. When the CONT bit = 0, the DSPI drives the asserted chip select signals to their idle states in between frames. The idle states of the chip select signals are selected by the PCSIS field in the DSPIx_MCR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 509 Figure 23-20 shows the timing diagram for two four-bit transfers with CPHA = 1 and CONT = 0. SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN CSx tCSC tASC tDT tCSC = CS to SCK delay. tCSC tASC = After SCK delay. tDT = Delay after transfer (minimum CS negation time). Figure 23-20. Example of non-continuous format (CPHA = 1, CONT = 0) When the CONT = 1 and the CS signal for the next transfer is the same as for the current transfer, the CS signal remains asserted for the duration of the two transfers. The delay between transfers (tDT) is not inserted between the transfers. Figure 23-21 shows the timing diagram for two 4-bit transfers with CPHA = 1 and CONT = 1. SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN CS tCSC tCSC = CS to SCK delay. tASC = After SCK delay. tASC tCSC Figure 23-21. Example of continuous transfer (CPHA = 1, CONT = 1) In Figure 23-21, the period length at the start of the next transfer is the sum of tASC and tCSC; that is, it does not include a half-clock period. The default settings for these provide a total of four system clocks. In many situations, tASC and tCSC must be increased if a full half-clock period is required. Switching CTARs between frames while using continuous selection can cause errors in the transfer. The CS signal must be negated before CTAR is switched. MPC5604B/C Microcontroller Reference Manual, Rev. 8 510 Freescale Semiconductor When the CONT bit = 1 and the CS signals for the next transfer are different from the present transfer, the CS signals behave as if the CONT bit was not set. NOTE You must fill the TXFIFO with the number of entries that will be concatenated together under one PCS assertion for both master and slave before the TXFIFO becomes empty. For example; while transmitting in master mode, ensure that the last entry in the TXFIFO, after which TXFIFO becomes empty, has CONT = 0 in the command frame. When operating in slave mode, ensure that when the last-entry in the TXFIFO is completely transmitted (i.e. the corresponding TCF flag is asserted and TXFIFO is empty) the slave is deselected for any further serial communication; otherwise, an underflow error occurs. 23.6.5.6 Clock polarity switching between DSPI transfers If it is desired to switch polarity between non-continuous DSPI frames, the edge generated by the change in the idle state of the clock occurs one system clock before the assertion of the chip select for the next frame. See Section 23.5.4, DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn). In Figure 23-22, time ‘A’ shows the one clock interval. Time ‘B’ is user programmable from a minimum of two system clocks. System clock CS SCK Frame 0 CPOL = 0 Frame 1 AB CPOL = 1 Figure 23-22. Polarity switching between frames 23.6.6 Continuous serial communications clock The DSPI provides the option of generating a continuous SCK signal for slave peripherals that require a continuous clock. Continuous SCK is enabled by setting the CONT_SCKE bit in the DSPIx_MCR. Continuous SCK is valid in all configurations. Continuous SCK is only supported for CPHA = 1. Setting CPHA = 0 is ignored if the CONT_SCKE bit is set. Continuous SCK is supported for modified transfer format. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 511 Clock and transfer attributes for the continuous SCK mode are set according to the following rules: • The TX FIFO must be cleared before initiating any SPI configuration transfer. • When the DSPI is in SPI configuration, CTAR0 is used initially. At the start of each SPI frame transfer, the CTAR specified by the CTAS for the frame should be CTAR0. • In all configurations, the currently selected CTAR remains in use until the start of a frame with a different CTAR specified, or the continuous SCK mode is terminated. The device is designed to use the same baud rate for all transfers made while using the continuous SCK. Switching clock polarity between frames while using continuous SCK can cause errors in the transfer. Continuous SCK operation is not guaranteed if the DSPI is put into module disable mode. Enabling continuous SCK disables the CS to SCK delay and the After SCK delay. The delay after transfer is fixed at one SCK cycle. Figure 23-23 shows timing diagram for continuous SCK format with continuous selection disabled. NOTE When in Continuous SCK mode, always use CTAR0 for the SPI transfer, and clear the TXFIFO using the MCR[CLR_TXF] field before initiating transfer. SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN CS tDT tDT = 1 SCK Figure 23-23. Continuous SCK timing diagram (CONT= 0) If the CONT bit in the TX FIFO entry is set, CS remains asserted between the transfers when the CS signal for the next transfer is the same as for the current transfer. Figure 23-24 shows timing diagram for continuous SCK format with continuous selection enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 512 Freescale Semiconductor SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN CS Transfer 1 Transfer 2 Figure 23-24. Continuous SCK timing diagram (CONT=1) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 513 23.6.7 Interrupt requests The DSPI has five conditions that can generate interrupt requests. Table 23-32 lists the five conditions. Table 23-32. Interrupt request conditions Condition Flag End of transfer queue has been reached (EOQ) EOQF Current frame transfer is complete TCF TX FIFO underflow has occurred TFUF RX FIFO overflow occurred RFOF A FIFO overrun occurred1 TFUF ORed with RFOF 1 The FIFO overrun condition is created by ORing the TFUF and RFOF flags together. Each condition has a flag bit and a request enable bit. The flag bits are described in the Section 23.5.5, DSPI Status Register (DSPIx_SR) and the request enable bits are described in the Section 23.5.6, DSPI Interrupt Request Enable Register (DSPIx_RSER). The TX FIFO fill flag (TFFF) and RX FIFO drain flag (RFDF) generate interrupt requests depending on the TFFF_DIRS and RFDF_DIRS bits in the DSPIx_RSER. 23.6.7.1 End of Queue Interrupt Request (EOQF) The end of queue request indicates that the end of a transmit queue is reached. The end of queue request is generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in the DSPIx_RSER is set. See the EOQ bit description in Section 23.5.5, DSPI Status Register (DSPIx_SR). See Figure 23-16 and Figure 23-17 that illustrate when EOQF is set. 23.6.7.2 Transmit FIFO Fill Interrupt Request (TFFF) The transmit FIFO fill request indicates that the TX FIFO is not full. The transmit FIFO fill request is generated when the number of entries in the TX FIFO is less than the maximum number of possible entries, and the TFFF_RE bit in the DSPIx_RSER is set. The TFFF_DIRS bit in the DSPIx_RSER is used to generate an interrupt request. 23.6.7.3 Transfer Complete Interrupt Request (TCF) The transfer complete request indicates the end of the transfer of a serial frame. The transfer complete request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPIx_RSER. See the TCF bit description in Section 23.5.5, DSPI Status Register (DSPIx_SR). See Figure 23-16 and Figure 23-17 that illustrate when TCF is set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 514 Freescale Semiconductor 23.6.7.4 Transmit FIFO Underflow Interrupt Request (TFUF) The transmit FIFO underflow request indicates that an underflow condition in the TX FIFO has occurred. The transmit underflow condition is detected only for DSPI modules operating in slave mode and SPI configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in slave mode and SPI configuration is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while the TFUF_RE bit in the DSPIx_RSER is set, an interrupt request is generated. 23.6.7.5 Receive FIFO Drain Interrupt Request (RFDF) The receive FIFO drain request indicates that the RX FIFO is not empty. The receive FIFO drain request is generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in the DSPIx_RSER is set. The RFDF_DIRS bit in the DSPIx_RSER is used to generate an interrupt request. 23.6.7.6 Receive FIFO Overflow Interrupt Request (RFOF) The receive FIFO overflow request indicates that an overflow condition in the RX FIFO has occurred. A receive FIFO overflow request is generated when RX FIFO and shift register are full and a transfer is initiated. The RFOF_RE bit in the DSPIx_RSER must be set for the interrupt request to be generated. Depending on the state of the ROOE bit in the DSPIx_MCR, the data from the transfer that generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is shifted in to the shift register. If the ROOE bit is negated, the incoming data is ignored. 23.6.7.7 FIFO Overrun Request (TFUF) or (RFOF) The FIFO overrun request indicates that at least one of the FIFOs in the DSPI has exceeded its capacity. The FIFO overrun request is generated by logically OR’ing together the RX FIFO overflow and TX FIFO underflow signals. 23.6.8 Power saving features The DSPI supports the following power-saving strategies: • Module disable mode—clock gating of non-memory mapped logic • Clock gating of slave interface signals and clock to memory-mapped logic 23.6.8.1 Module Disable mode Module disable mode is a module-specific mode that the DSPI can enter to save power. Host software can initiate the module disable mode by writing a ‘1’ to the MDIS bit in the DSPIx_MCR. In module disable mode, the DSPI is in a dormant state, but the memory mapped registers are still accessible. Certain read or write operations have a different affect when the DSPI is in the module disable mode. Reading the RX FIFO pop register does not change the state of the RX FIFO. Likewise, writing to the TX FIFO push register does not change the state of the TX FIFO. Clearing either of the FIFOs does not have any effect in the module disable mode. Changes to the DIS_TXF and DIS_RXF fields of the DSPIx_MCR does not have any affect in the module disable mode. In the module disable mode, all status bits and register flags in the DSPI return the correct values when read, but writing to them has no affect. Writing to the MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 515 DSPIx_TCR during module disable mode does not have an effect. Interrupt request signals cannot be cleared while in the module disable mode. 23.6.8.2 Slave interface signal gating The DSPI module enable signal is used to gate slave interface signals such as address, byte enable, read/write and data. This prevents toggling slave interface signals from consuming power unless the DSPI is accessed. 23.7 Initialization and application information 23.7.1 How to change queues DSPI queues are not part of the DSPI module, but the DSPI includes features in support of queue management. Queues are primarily supported in SPI configuration. This section presents an example of how to change queues for the DSPI. 1. The last command word from a queue is executed. The EOQ bit in the command word is set to indicate to the DSPI that this is the last entry in the queue. 2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ flag (EOQF) in the DSPIx_SR is set. 3. The setting of the EOQF flag disables both serial transmission, and serial reception of data, putting the DSPI in the STOPPED state. The TXRXS bit is negated to indicate the STOPPED state. 4. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the RXCNT in DSPIx_SR or by checking RFDF in the DSPIx_SR after each read operation of the DSPIx_POPR. 5. Flush TX FIFO by writing a ‘1’ to the CLR_TXF bit in the DSPIx_MCR register and flush the RX FIFO by writing a ‘1’ to the CLR_RXF bit in the DSPIx_MCR register. 6. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new queue or via CPU writing directly to SPI_TCNT field in the DSPIx_TCR. 7. Enable serial transmission and serial reception of data by clearing the EOQF bit. 23.7.2 Baud rate settings Table 23-33 shows the baud rate that is generated based on the combination of the baud rate prescaler PBR and the baud rate scaler BR in the DSPIx_CTARs. The values are calculated at a 64 MHz system frequency. MPC5604B/C Microcontroller Reference Manual, Rev. 8 516 Freescale Semiconductor Baud rate scaler values (DSPI_CTAR[BR]) 2 4 6 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 Table 23-33. Baud rate values Baud rate divider prescaler values (DSPI_CTAR[PBR]) 2 16.0 MHz 3 10.7 MHz 5 6.4 MHz 8 MHz 5.33 MHz 3.2 MHz 5.33 MHz 3.56 MHz 2.13 MHz 4 MHz 2.67 MHz 1.60 MHz 2 MHz 1.33 MHz 800 kHz 1 MHz 670 kHz 400 kHz 500 kHz 333 kHz 200 kHz 250 kHz 166 kHz 100 kHz 125 kHz 83.2 kHz 50 kHz 62.5 kHz 41.6 kHz 25 kHz 31.2 kHz 20.8 kHz 12.5 kHz 15.6 kHz 10.4 kHz 6.25 kHz 7.81 kHz 5.21 kHz 3.12 kHz 3.90 kHz 2.60 kHz 1.56 kHz 1.95 kHz 1.31 kHz 781 Hz 979 Hz 653 Hz 390 Hz 7 4.57 MHz 2.28 MHz 1.52 MHz 1.15 MHz 571 kHz 285 kHz 142 kHz 71.7 kHz 35.71 kHz 17.86 kHz 8.96 kHz 4.47 kHz 2.23 kHz 1.11 kHz 558 Hz 279 Hz MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 517 23.7.3 Delay settings Table 23-34 shows the values for the delay after transfer (tDT) that can be generated based on the prescaler values and the scaler values set in the DSPIx_CTARs. The values calculated assume a 64 MHz system frequency. Table 23-34. Delay values Delay prescaler values (DSPI_CTAR[PDT]) Delay scaler values (DSPI_CTAR[DT]) 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536 1 31.25 ns 62.5 ns 125 ns 250 ns 0.5 µs 1 µs 2 µs 4 µs 8 µs 16 µs 32 µs 64 µs 128 µs 256 µs 512 µs 1.02 ms 3 93.75 ns 187.5 ns 375 ns 750 ns 1.5 µs 3 µs 6 µs 12 µs 24 µs 48 µs 96 µs 192 µs 384 µs 768 µs 1.54 ms 3.07 ms 5 156.25 ns 312.5 ns 625 ns 1.25 µs 2.5 µs 5 µs 10 µs 20 µs 40 µs 80 µs 160 µs 320 µs 640 µs 1.28 ms 2.56 ms 5.12 ms 7 218.75 ns 437.5 ns 875 ns 1.75 µs 3.5 µs 7 µs 14 µs 28 µs 56 µs 112 µs 224 µs 448 µs 896 µs 1.79 ms 3.58 ms 7.17 ms 23.7.4 Calculation of FIFO pointer addresses The user has complete visibility of the TX and RX FIFO contents through the FIFO registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each FIFO. The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is the transmit next pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the pop next pointer (POPNXTPTR). MPC5604B/C Microcontroller Reference Manual, Rev. 8 518 Freescale Semiconductor See Section 23.6.3.4, Transmit First In First Out (TX FIFO) buffering mechanism, and Section 23.6.3.5, Receive First In First Out (RX FIFO) buffering mechanism, for details on the FIFO operation. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO. Figure 23-25 illustrates the concept of first-in and last-in FIFO entries along with the FIFO counter. Push TX FIFO register TX FIFO base – – Entry A (first in) Entry B Entry C Entry D (last in) – – Transmit next data pointer (TXNXTPTR) Shift register SOUT +1 TX FIFO counter –1 Figure 23-25. TX FIFO pointers and counter 23.7.4.1 Address calculation for the first-in entry and last-in entry in the TX FIFO The memory address of the first-in entry in the TX FIFO is computed by the following equation: First-in entry address = TXFIFO base + 4 (TXNXTPTR) The memory address of the last-in entry in the TX FIFO is computed by the following equation: Last-in entry address = TXFIFO base + 4 x [(TXCTR + TXNXTPTR - 1) modulo TXFIFO depth] where: TXFIFO base = base address of transmit FIFO TXCTR = transmit FIFO counter TXNXTPTR = transmit next pointer TX FIFO depth = transmit FIFO depth, implementation specific 23.7.4.2 Address calculation for the first-in entry and last-in entry in the RX FIFO The memory address of the first-in entry in the RX FIFO is computed by the following equation: First-in entry address = RXFIFO base + 4 x (POPNXTPTR) The memory address of the last-in entry in the RX FIFO is computed by the following equation: Last-in entry address = RXFIFO base + 4 x [(RXCTR + POPNXTPTR - 1) modulo RXFIFO depth] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 519 where: RXFIFO base = base address of receive FIFO RXCTR = receive FIFO counter POPNXTPTR = pop next pointer RX FIFO depth = receive FIFO depth, implementation specific MPC5604B/C Microcontroller Reference Manual, Rev. 8 520 Freescale Semiconductor ——— Timers ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 521 MPC5604B/C Microcontroller Reference Manual, Rev. 8 522 Freescale Semiconductor Chapter 24 Timers 24.1 Introduction This chapter describes the timer modules implemented on the microcontroller: • System Timer Module (STM) • Enhanced Modular IO Subsystem (eMIOS) • Periodic Interrupt Timer (PIT) The microcontroller also has a Real Time Clock / Autonomous Periodic Interrupt (RTC/API) module. The main purpose of this is to provide a periodic device wakeup source. 24.2 Technical overview This section gives a technical overview of each of the timers as well as detailing the pins that can be used to access the timer peripherals if applicable. Figure 24-1 details the interaction between the timers and the eDMA, INTC, CTU, and ADC. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 523 eMIOS 0 CH[0..27] eMIOS 1 CH[0..27] CTU 24 eMIOS0 CH[0..22, 24] Trigger [0..22, 24] 24 eMIOS1 CH[0..22, 24] Trigger [32..54, 56] 1 PIT_CH[3] Trigger [23] PIT PIT[0..5] STM CH[0..3] CTU triggers for all ADC channels Single ADC conversion per CTU channel 14 eMIOS0 INTC CH[0..27]* IRQ[141..154] 14 eMIOS1 CH[0..27]* IRQ[157..170] 6 PIT[0..2, 3..5] IRQ[59..61, 127..129] 4 STM_CH[0..3] IRQ[30..33] 1 PIT Trigger for INJECTED ADC Conversions ADC 0 (10-bit) PIT_CH[2] Note* There are 14 interrupt requests from the eMIOS to the INTC. eMIOS channels are routed to the interrupt controller in pairs for example CH[0,1] CH[2,3] Figure 24-1. Interaction between timers and relevant peripherals MPC5604B/C Microcontroller Reference Manual, Rev. 8 524 Freescale Semiconductor 24.2.1 Overview of the STM The STM is a 32-bit free running up-counter clocked by the system clock with a configurable 8-bit clock pre-scaler (divide by 1 to 256). The counter is disabled out of reset and must therefore be enabled by software prior to use. The counter value can be read at any time. The STM has four 32-bit compare channels. Each channel can generate a unique interrupt on an exact match event with the free running counter. The STM is often used to analyse code execution times. By starting the STM and reading the timer before and after a task or function, you can make an accurate measurement of the time taken in clock cycles to perform the task. The STM can be configured to stop (freeze) or continue to run in debug mode and is available for use in all operating mode where the system clock is present (not STANDBY or certain STOP mode configurations) There are no external pins associated with the STM. 24.2.2 Overview of the eMIOS Each eMIOS offers a combination of PWM, Output Capture and Input Compare functions. There are different types of channel implemented and not every channel supports every eMIOS function. The channel functionality also differs between each eMIOS module. See Section 24.4, Enhanced Modular IO Subsystem (eMIOS), for more details. Each channel has its own independent 16-bit counter. To allow synchronization between channels, there are a number of shared counter busses that can be used as a common timing reference. These counter buses can be used in combination with the individual channel counters to provide advanced features such as centre aligned PWM with dead time insertion. Once configured, the eMIOS needs very little CPU intervention. Interrupts, eDMA requests and CTU trigger requests can be raised based on eMIOS flag and timeout events. The eMIOS is clocked from the system clock via peripheral clock group 3 (with a maximum permitted clock frequency of 64 MHz). The eMIOS can be used in all modes where the system clock is available (which excludes STANDBY mode and STOP mode when the system clock is turned off). The eMIOS has an option to allow the eMIOS counters to freeze or to continue running in debug mode. The CTU allows an eMIOS event to trigger a single ADC conversion via the CTU without any CPU intervention. Without the CTU, the eMIOS would have to trigger an interrupt request. The respective ISR would then perform a software triggered ADC conversion. This not only uses CPU resource, but also increases the latency between the eMIOS event and the ADC trigger. The eMIOS "Output Pulse Width Modulation with Trigger" mode (see Section 24.4.4.1.1.12, Output Pulse Width Modulation with Trigger (OPWMT) mode) allows a customisable trigger point to be defined at any point in the waveform period. This is extremely useful for LED lighting applications where the trigger can be set to a point where the PWM output is high but after the initial inrush current to the LED has occurred. The PWM trigger can then cause the CTU to perform a single ADC conversion which in turn measures the operating conditions of the LED to ensure it is working within specification. A watchdog feature on MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 525 the ADC allows channels to be monitored and if the results fall outwith a specific range an interrupt is triggered. This means that all of the measurement is without CPU intervention if the results are within range. To make it easier to plan which pins to use for the eMIOS, Table 24-1 and Table 24-2 show the eMIOS channel numbers that are available on each pin. The color shading matches the channel configuration diagram in the eMIOS section. Table 24-1. eMIOS_0 channel to pin mapping Channel UC[0] UC[1] UC[2] UC[3] UC[4] UC[5] UC[6] UC[7] UC[8] UC[9] UC[10] UC[11] UC[12] UC[13] UC[14] UC[15] Pin function ALT1 ALT2 PA[0] PA[1] PA[2] PA[3], PB[11] PA[4], PB[12] PA[5], PB[13] PA[6], PB[14] PA[7], PB[15] PA[8] PA[9] PA[10], PF[0] PA[11], PF[1] PC[12], PF[2] PC[13], PF[3] PC[14], PF[4] PC[15] ALT3 Channel UC[16] UC[17] UC[18] UC[19] UC[20] UC[21] UC[22] UC[23] UC[24] UC[25] UC[26] UC[27] Pin function ALT1 ALT2 PE[0] PE[1] PE[2] PE[3] PE[4] PE[5] PE[6], PF[5] PE[7], PF[6] PG[10] PG[11] PG[12] PG[13] PE[8] PE[9] PD[12] PD[13] PD[14] PD[15] ALT3 Table 24-2. eMIOS_1 channel to pin mapping Channel UC[0] UC[1] UC[2] UC[3] UC[4] UC[5] UC[6] UC[7] UC[8] UC[9] UC[10] UC[11] Pin function ALT1 PG[14] PG[15] PH[0] PH[1] PH[2] PH[3] PH[4] PH[5] PH[6] PH[7] PH[8] PG[2] ALT2 ALT3 PH[11] Channel UC[16] UC[17] UC[18] UC[19] UC[20] UC[21] UC[22] UC[23] UC[24] UC[25] UC[26] UC[27] Pin function ALT1 PG[7] PG[8] PG[9] PF[12] PF[13] ALT2 PE[12] PE[13] PE[14] PE[15] PG[0] PG[1] PF[14] ALT3 MPC5604B/C Microcontroller Reference Manual, Rev. 8 526 Freescale Semiconductor Channel UC[12] UC[13] UC[14] UC[15] Table 24-2. eMIOS_1 channel to pin mapping (continued) Pin function ALT1 ALT2 PG[3] PG[4] PG[5] PG[6] ALT3 Channel Pin function ALT1 ALT2 ALT3 24.2.3 Overview of the PIT The PIT module consists of 6 Periodic Interrupt Timers (PITs) clocked from the system clock. Out of reset, the PITis disabled. There is a global disable control bit for all of the PIT timers. Before using the timers, software must clear the appropriate disabled bit. Each of the PIT timers are effectively standalone entities and each have their own timer and control registers. The PIT timers are 32-bit count down timers. To use them, you must first program an initial value into the LDVAL register. The timer will then start to count down and can be read at any time. Once the timer reaches 0x0000_0000, a flag is set and the previous value is automatically re-loaded into the LDVAL register and the countdown starts again. The flag event can be routed to a dedicated INTC interrupt if desired. The PIT is also used to trigger other events: • 1 PIT channels can be used to trigger a CTU ADC conversion (single) • 1 PIT channel can be used to directly trigger injected conversions on the ADC The timers can be configured to stop (freeze) or to continue to run in debug mode. The PITis available in all modes where a system clock is generated. There are no external pins associated with the PIT. 24.3 System Timer Module (STM) 24.3.1 Introduction 24.3.1.1 Overview The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). 24.3.1.2 Features The STM has the following features: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 527 • One 32-bit up counter with 8-bit prescaler • Four 32-bit compare channels • Independent interrupt source for each channel • Counter can be stopped in debug mode 24.3.1.3 Modes of operation The STM supports two device modes of operation: normal and debug. When the STM is enabled in normal mode, its counter runs continuously. In debug mode, operation of the counter is controlled by the FRZ bit in the STM_CR register. If the FRZ bit is set, the counter is stopped in debug mode, otherwise it continues to run. 24.3.2 External signal description The STM does not have any external interface signals. 24.3.3 Memory map and register definition The STM programming model has fourteen 32-bit registers. The STM registers can only be accessed using 32-bit (word) accesses. Attempted references using a different size or to a reserved address generates a bus error termination. 24.3.3.1 Memory map The STM memory map is shown in Table 24-3. Table 24-3. STM memory map Base address: 0xFFF3_C000 Address offset Register 0x0000 0x0004 0x0008–0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 STM Control Register (STM_CR) STM Counter Value (STM_CNT) Reserved STM Channel 0 Control Register (STM_CCR0) STM Channel 0 Interrupt Register (STM_CIR0) STM Channel 0 Compare Register (STM_CMP0) Reserved STM Channel 1 Control Register (STM_CCR1) STM Channel 1 Interrupt Register (STM_CIR1) STM Channel 1 Compare Register (STM_CMP1) Reserved STM Channel 2 Control Register (STM_CCR2) Location on page 529 on page 530 on page 530 on page 531 on page 531 on page 530 on page 531 on page 531 on page 530 MPC5604B/C Microcontroller Reference Manual, Rev. 8 528 Freescale Semiconductor Address offset 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C–0x3FFF Table 24-3. STM memory map (continued) Base address: 0xFFF3_C000 Register STM Channel 2 Interrupt Register (STM_CIR2) STM Channel 2 Compare Register (STM_CMP2) Reserved STM Channel 3 Control Register (STM_CCR3) STM Channel 3 Interrupt Register (STM_CIR3) STM Channel 3 Compare Register (STM_CMP3) Reserved Location on page 531 on page 531 on page 530 on page 531 on page 531 24.3.3.2 Register descriptions The following sections detail the individual registers within the STM programming model. 24.3.3.2.1 STM Control Register (STM_CR) The STM Control Register (STM_CR) includes the prescale value, freeze control and timer enable bits. Offset: 0x000 Access: Read/Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CPS W 000000 FRZ TEN Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-2. STM Control Register (STM_CR) Table 24-4. STM_CR field descriptions Field Description CPS Counter Prescaler. Selects the clock divide value for the prescaler (1 - 256). 0x00 = Divide system clock by 1 0x01 = Divide system clock by 2 ... 0xFF = Divide system clock by 256 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 529 Table 24-4. STM_CR field descriptions Field Description FRZ TEN Freeze. Allows the timer counter to be stopped when the device enters debug mode. 0 = STM counter continues to run in debug mode. 1 = STM counter is stopped in debug mode. Timer Counter Enabled. 0 = Counter is disabled. 1 = Counter is enabled. 24.3.3.2.2 STM Count Register (STM_CNT) The STM Count Register (STM_CNT) holds the timer count value. Offset: 0x004 Access: Read/Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-3. STM Count Register (STM_CNT) Table 24-5. STM_CNT field descriptions Field Description CNT Timer count value used as the time base for all channels. When enabled, the counter increments at the rate of the system clock divided by the prescale value. 24.3.3.2.3 STM Channel Control Register (STM_CCRn) The STM Channel Control Register (STM_CCRn) has the enable bit for channel n of the timer. Offset: 0x10+0x10*n Access: Read/Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-4. STM Channel Control Register (STM_CCRn) MPC5604B/C Microcontroller Reference Manual, Rev. 8 530 Freescale Semiconductor Table 24-6. STM_CCRn field descriptions Field CEN Channel Enable. 0 = The channel is disabled. 1 = The channel is enabled. Description 24.3.3.2.4 STM Channel Interrupt Register (STM_CIRn) The STM Channel Interrupt Register (STM_CIRn) has the interrupt flag for channel n of the timer. Offset: 0x14+0x10*n Access: Read/Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIF W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-5. STM Channel Interrupt Register (STM_CIRn) Table 24-7. STM_CIRn field descriptions Field Description CIF Channel Interrupt Flag 0 = No interrupt request. 1 = Interrupt request due to a match on the channel. 24.3.3.2.5 STM Channel Compare Register (STM_CMPn) The STM channel compare register (STM_CMPn) holds the compare value for channel n. Offset: 0x18+0x10*n Access: Read/Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CMP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-6. STM Channel Compare Register (STM_CMPn) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 531 Table 24-8. STM_CMPn field descriptions Field Description CMP Compare value for channel n. If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the STM_CNT register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is set. 24.3.4 Functional description The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The STM has one 32-bit up counter (STM_CNT) that is used as the time base for all channels. When enabled, the counter increments at the system clock frequency divided by a prescale value. The STM_CR[CPS] field sets the divider to any value in the range from 1 to 256. The counter is enabled with the STM_CR[TEN] bit. When enabled in normal mode the counter continuously increments. When enabled in debug mode the counter operation is controlled by the STM_CR[FRZ] bit. When the STM_CR[FRZ] bit is set, the counter is stopped in debug mode, otherwise it continues to run in debug mode. The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary. The STM has four identical compare channels. Each channel includes a channel control register (STM_CCRn), a channel interrupt register (STM_CIRn) and a channel compare register (STM_CMPn). The channel is enabled by setting the STM_CCRn[CEN] bit. When enabled, the channel will set the STM_CIR[CIF] bit and generate an interrupt request when the channel compare register matches the timer counter. The interrupt request is cleared by writing a 1 to the STM_CIRn[CIF] bit. A write of 0 to the STM_CIRn[CIF] bit has no effect. NOTE STM counter does not advance when the system clock is stopped. 24.4 Enhanced Modular IO Subsystem (eMIOS) 24.4.1 Introduction 24.4.1.1 Overview of the eMIOS module The eMIOS provides functionality to generate or measure time events. The eMIOS uses timer channels that are reduced versions of the unified channel (UC) module used on MPC555x devices. Each channel provides a subset of the functionality available in the unified channel, at a resolution of 16 bits, and provides a user interface that is consistent with previous eMIOS implementations. 24.4.1.2 Features of the eMIOS module • 2 eMIOS blocks with 28 channels each — 50 channels with OPWMT, which can be connected to the CTU — 6 channels with single action IC/OC MPC5604B/C Microcontroller Reference Manual, Rev. 8 532 Freescale Semiconductor — Both eMIOS blocks can be synchronized • One global prescaler • 16-bit data registers • 10 x 16-bit wide counter buses — Counter buses B, C, D, and E can be driven by Unified Channel 0, 8, 16, and 24, respectively — Counter bus A is driven by the Unified Channel #23 — Several channels have their own time base, alternative to the counter buses — Shared timebases through the counter buses — Synchronization among timebases • Control and Status bits grouped in a single register • Shadow FLAG register • State of the UC can be frozen for debug purposes • Motor control capability 24.4.1.3 Modes of operation The Unified Channels can be configured to operate in the following modes: • General purpose input/output • Single Action Input Capture • Single Action Output Compare • Input Pulse Width Measurement • Input Period Measurement • Double Action Output Compare • Modulus Counter • Modulus Counter Buffered • Output Pulse Width and Frequency Modulation Buffered • Output Pulse Width Modulation Buffered • Output Pulse Width Modulation with Trigger • Center Aligned Output Pulse Width Modulation Buffered These modes are described in Section 24.4.4.1.1, UC modes of operation. Each channel can have a specific set of modes implemented, according to device requirements. If an unimplemented mode (reserved) is selected, the results are unpredictable such as writing a reserved value to MODE[0:6] in Section 24.4.3.2.8, eMIOS UC Control Register (EMIOSC[n]). 24.4.1.4 Channel implementation Figure 24-7 shows the channel configuration of the eMIOS blocks. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 533 Bus Clk Global Prescaler 8-bit Counter eMIOS_0 Key DAOC GPIO IPM IPWM MC MCB OPWMB OPWMT OPWFMB OPWMCB SAIC SAOC Counter Bus_A Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8 Ch9 Ch10 Ch11 Ch12 Ch13 Ch14 Ch15 Ch16 Ch17 Ch18 Ch19 Ch20 Ch21 Ch22 Ch23 Ch24 Ch25 Ch26 Ch27 Counter Bus_E Counter Bus_D Counter Bus_C Counter Bus_B Bus Clk Global Prescaler 8-bit Counter eMIOS_1 Counter Bus_A Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8 Ch9 Ch10 Ch11 Ch12 Ch13 Ch14 Ch15 Ch16 Ch17 Ch18 Ch19 Ch20 Ch21 Ch22 Ch23 Ch24 Ch25 Ch26 Ch27 Dual Action Output Compare General Purpose Input Output Input Period Measurement Input Pulse Width Measurement Modulus Counter Buffered Modulus Counter Buffered Output Pulse Width Modulation Buffered Output Pulse Width Modulation with Trigger Buffered Output Pulse Width and Frequency Modulation Center Aligned Output PWM Buffered with Dead-Time Single Action Input Capture Single Action Output Compare Figure 24-7. Channel configuration Counter Bus_E Counter Bus_D Counter Bus_C Counter Bus_B Channel Functionality TYPE G • MCB • OPWMT • OPWMB • OPWFMB • OPWMCB • IPWM, IPM • DAOC • SAIC, SAOC • GPIO TYPE X • MC, MCB • OPWMT • OPWMB • OPWFMB • SAIC, SAOC • GPIO TYPE H • OPWMT • OPWMB • IPWM, IPM • DAOC • SAIC, SAOC • GPIO TYPE Y • OPWMT • OPWMB • SAIC, SAOC • GPIO TYPEF • SAIC, SAOC • GPIO MPC5604B/C Microcontroller Reference Manual, Rev. 8 534 Freescale Semiconductor 24.4.1.4.1 Channel mode selection Channel modes are selected using the mode selection bits MODE[0:6] in the eMIOS UC Control Register (EMIOSC[n]). Table 24-21 provides the specific mode selection settings for the eMIOS implementation on this device. 24.4.2 External signal description For information on eMIOS external signals on this device, please refer to the signal description chapter of the reference manual. 24.4.3 Memory map and register description 24.4.3.1 Memory maps The overall address map organization is shown in Table 24-9. 24.4.3.1.1 Unified Channel memory map Table 24-9. eMIOS memory map Base addresses: 0xC3FA_0000 (eMIOS_0) 0xC3FA_4000 (eMIOS_1) Address offset 0x000–0x003 0x004–0x007 0x008–0x00B 0x00C–0x00F 0x010–0x01F 0x020–0x11F 0x120–0x21F 0x220–0x31F 0x320–0x39F 0x3A0–0xFFF Description Location eMIOS Module Configuration Register (EMIOSMCR) on page 536 eMIOS Global FLAG (EMIOSGFLAG) Register on page 537 eMIOS Output Update Disable (EMIOSOUDIS) Register on page 538 eMIOS Disable Channel (EMIOSUCDIS) Register on page 539 Reserved — Channel [0] — to Channel [7] Channel [8] — to Channel [15] Channel [16] — to Channel [23] Channel [24] — to Channel [27] Reserved — MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 535 Addresses of Unified Channel registers are specified as offsets from the channel’s base address; otherwise the eMIOS base address is used as reference. Table 24-10 describes the Unified Channel memory map. Table 24-10. Unified Channel memory map UC[n] base address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18–0x1F Description eMIOS UC A Register (EMIOSA[n]) eMIOS UC B Register (EMIOSB[n]) eMIOS UC Counter Register (EMIOSCNT[n]) eMIOS UC Control Register (EMIOSC[n]) eMIOS UC Status Register (EMIOSS[n]) eMIOS UC Alternate A Register (EMIOSALTA[n]) Reserved Location on page 539 on page 540 on page 541 on page 541 on page 545 on page 546 — 24.4.3.2 Register description All control registers are 32 bits wide. Data registers and counter registers are 16 bits wide. 24.4.3.2.1 eMIOS Module Configuration Register (EMIOSMCR) The EMIOSMCR contains global control bits for the eMIOS block. Address: eMIOS base address +0x00 GTBE GPREN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 MDIS FRZ W 0000000000 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 R W Reset 0 Field MDIS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GPRE 00000000 000000000000000 Figure 24-8. eMIOS Module Configuration Register (EMIOSMCR) Table 24-11. EMIOSMCR field descriptions Description Module Disable Puts the eMIOS in low power mode. The MDIS bit is used to stop the clock of the block, except the access to registers EMIOSMCR, EMIOSOUDIS and EMIOSUCDIS. 1 = Enter low power mode 0 = Clock is running MPC5604B/C Microcontroller Reference Manual, Rev. 8 536 Freescale Semiconductor Field FRZ GTBE GPREN GPRE Table 24-11. EMIOSMCR field descriptions (continued) Description Freeze Enables the eMIOS to freeze the registers of the Unified Channels when Debug Mode is requested at MCU level. Each Unified Channel should have FREN bit set in order to enter freeze state. While in Freeze state, the eMIOS continues to operate to allow the MCU access to the Unified Channels registers. The Unified Channel will remain frozen until the FRZ bit is written to ‘0’ or the MCU exits Debug mode or the Unified Channel FREN bit is cleared. 1 = Stops Unified Channels operation when in Debug mode and the FREN bit is set in the EMIOSC[n] register 0 = Exit freeze state Global Time Base Enable The GTBE bit is used to export a Global Time Base Enable from the module and provide a method to start time bases of several blocks simultaneously. 1 = Global Time Base Enable Out signal asserted 0 = Global Time Base Enable Out signal negated Note: The Global Time Base Enable input pin controls the internal counters. When asserted, Internal counters are enabled. When negated, Internal counters disabled. Global Prescaler Enable The GPREN bit enables the prescaler counter. 1 = Prescaler enabled 0 = Prescaler disabled (no clock) and prescaler counter is cleared Global Prescaler The GPRE bits select the clock divider value for the global prescaler, as shown in Table 24-12. Table 24-12. Global prescaler clock divider GPRE 00000000 00000001 00000010 00000011 . . . . 11111110 11111111 Divide ratio 1 2 3 4 . . . . 255 256 24.4.3.2.2 eMIOS Global FLAG (EMIOSGFLAG) Register The EMIOSGFLAG is a read-only register that groups the flag bits (F[27:0]) from all channels. This organization improves interrupt handling on simpler devices. Each bit relates to one channel. For Unified Channels these bits are mirrors of the FLAG bits in the EMIOSS[n] register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 537 Address: eMIOS base address +0x04 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-9. eMIOS Global FLAG (EMIOSGFLAG) Register Table 24-13. EMIOSGFLAG field descriptions Field Fn Channel [n] Flag bit Description 24.4.3.2.3 eMIOS Output Update Disable (EMIOSOUDIS) Register OU27 OU26 OU25 OU24 OU23 OU22 OU21 OU20 OU19 OU18 OU17 OU16 Address: eMIOS base address +0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 R W Reset 0 Field OUn OU15 OU14 OU13 OU12 OU11 OU10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OU9 OU8 OU7 OU6 OU5 OU4 OU3 OU2 OU1 OU0 000000000000000 Figure 24-10. eMIOS Output Update Disable (EMIOSOUDIS) Register Table 24-14. EMIOSOUDIS field descriptions Description Channel [n] Output Update Disable bit When running MC, MCB or an output mode, values are written to registers A2 and B2. OU[n] bits are used to disable transfers from registers A2 to A1 and B2 to B1. Each bit controls one channel. 1 = Transfers disabled 0 = Transfer enabled. Depending on the operation mode, transfer may occur immediately or in the next period. Unless stated otherwise, transfer occurs immediately. MPC5604B/C Microcontroller Reference Manual, Rev. 8 538 Freescale Semiconductor 24.4.3.2.4 eMIOS Disable Channel (EMIOSUCDIS) Register Address: eMIOS base address +0x0C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 W CHDIS27 CHDIS26 CHDIS25 CHDIS24 CHDIS23 CHDIS22 CHDIS21 CHDIS20 CHDIS19 CHDIS18 CHDIS17 CHDIS16 Reset 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 CHDIS15 CHDIS14 CHDIS13 CHDIS12 CHDIS11 CHDIS10 CHDIS9 CHDIS8 CHDIS7 CHDIS6 CHDIS5 CHDIS4 CHDIS3 CHDIS2 CHDIS1 CHDIS0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reset 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Figure 24-11. eMIOS Enable Channel (EMIOSUCDIS) Register Table 24-15. EMIOSUCDIS field descriptions Field CHDISn Description Enable Channel [n] bit The CHDIS[n] bit is used to disable each of the channels by stopping its respective clock. 1 = Channel [n] disabled 0 = Channel [n] enabled 24.4.3.2.5 eMIOS UC A Register (EMIOSA[n]) Address: UC[n] base address + 0x00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R A W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-12. eMIOS UC A Register (EMIOSA[n]) Depending on the mode of operation, internal registers A1 or A2, used for matches and captures, can be assigned to address EMIOSA[n]. Both A1 and A2 are cleared by reset. Figure 24-16 summarizes the EMIOSA[n] writing and reading accesses for all operation modes. For more information see Section 24.4.4.1.1, UC modes of operation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 539 24.4.3.2.6 eMIOS UC B Register (EMIOSB[n]) Address: UC[n] base address + 0x04 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R B W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-13. eMIOS UC B Register (EMIOSB[n]) Depending on the mode of operation, internal registers B1 or B2 can be assigned to address EMIOSB[n]. Both B1 and B2 are cleared by reset. Table 24-16 summarizes the EMIOSB[n] writing and reading accesses for all operation modes. For more information see Section 24.4.4.1.1, UC modes of operation. Depending on the channel configuration, it may have EMIOSB register or not. This means that, if at least one mode that requires the register is implemented, then the register is present; otherwise it is absent. Table 24-16. EMIOSA[n], EMIOSB[n] and EMIOSALTA[n] values assignment Operation mode write read Register access write read alt write GPIO SAIC1 SAOC1 A1, A2 A1 B1,B2 B1 A2 — A2 B2 B2 — A2 A1 B2 B2 — IPWM — A2 — B1 — IPM — A2 — B1 — DAOC MC1 A2 A1 B2 B1 — A2 A1 B2 B2 — OPWMT MCB1 A1 A1 B2 B1 A2 A2 A1 B2 B2 — OPWFMB A2 A1 B2 B1 — OPWMCB A2 A1 B2 B1 — OPWMB A2 A1 B2 B1 — 1 In these modes, the register EMIOSB[n] is not used, but B2 can be accessed. alt read A2 — — — — — — A2 — — — — MPC5604B/C Microcontroller Reference Manual, Rev. 8 540 Freescale Semiconductor 24.4.3.2.7 eMIOS UC Counter Register (EMIOSCNT[n]) Address: UC[n] base address + 0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R C W1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-14. eMIOS UC Counter Register (EMIOSCNT[n]) 1 In GPIO mode or Freeze action, this register is writable. The EMIOSCNT[n] register contains the value of the internal counter. When GPIO mode is selected or the channel is frozen, the EMIOSCNT[n] register is read/write. For all others modes, the EMIOSCNT[n] is a read-only register. When entering some operation modes, this register is automatically cleared (refer to Section 24.4.4.1.1, UC modes of operation for details). Depending on the channel configuration it may have an internal counter or not. It means that if at least one mode that requires the counter is implemented, then the counter is present; otherwise it is absent. Channels of type X and G have the internal counter enabled, so their timebase can be selected by channel's BSL[1:0]=11:eMIOS_A - channels 0 to 8, 16, 23 and 24, eMIOS_B = channels 0, 8, 16, 23 and 24. Other channels from the above list don't have internal counters. 24.4.3.2.8 eMIOS UC Control Register (EMIOSC[n]) The Control register gathers bits reflecting the status of the UC input/output signals and the overflow condition of the internal counter, as well as several read/write control bits. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 541 Address: UC[n] base address + 0x0C 0 1 2 3 4 5 R 000 W UCPRE 6 7 8 0 DMA 9 10 11 12 13 14 15 0 IF FCK FEN UCPREN FREN Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 0 0 0 0 W BSL MODE EDSEL EDPOL FORCMA FORCMB Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-15. eMIOS UC Control Register (EMIOSC[n]) Table 24-17. EMIOSC[n] field descriptions Field FREN UCPRE UCPREN DMA IF FCK Description Freeze Enable bit The FREN bit, if set and validated by FRZ bit in EMIOSMCR register allows the channel to enter freeze state, freezing all registers values when in debug mode and allowing the MCU to perform debug functions. 1 = Freeze UC registers values 0 = Normal operation Prescaler bits The UCPRE bits select the clock divider value for the internal prescaler of Unified Channel, as shown in Table 24-18. Prescaler Enable bit The UCPREN bit enables the prescaler counter. 1 = Prescaler enabled 0 = Prescaler disabled (no clock) Direct Memory Access bit The DMA bit selects if the FLAG generation will be used as an interrupt or as a CTU trigger. 1 = Flag/overrun assigned to CTU trigger 0 = Flag/overrun assigned to interrupt request Input Filter The IF field controls the programmable input filter, selecting the minimum input pulse width that can pass through the filter, as shown in Table 24-19. For output modes, these bits have no meaning. Filter Clock select bit The FCK bit selects the clock source for the programmable input filter. 1 = Main clock 0 = Prescaled clock MPC5604B/C Microcontroller Reference Manual, Rev. 8 542 Freescale Semiconductor Table 24-17. EMIOSC[n] field descriptions (continued) Field FEN FORCMA FORCMB BSL EDSEL Description FLAG Enable bit The FEN bit allows the Unified Channel FLAG bit to generate an interrupt signal or a CTU trigger signal (The type of signal to be generated is defined by the DMA bit). 1 = Enable (FLAG will generate an interrupt request or a CTU trigger) 0 = Disable (FLAG does not generate an interrupt request or a CTU trigger) Force Match A bit For output modes, the FORCMA bit is equivalent to a successful comparison on comparator A (except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit is valid for every output operation mode which uses comparator A, otherwise it has no effect. 1 = Force a match at comparator A 0 = Has no effect Note: For input modes, the FORCMA bit is not used and writing to it has no effect. Force Match B bit For output modes, the FORCMB bit is equivalent to a successful comparison on comparator B (except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit is valid for every output operation mode which uses comparator B, otherwise it has no effect. 1 = Force a match at comparator B 0 = Has not effect Note: For input modes, the FORCMB bit is not used and writing to it has no effect. Bus Select The BSL field is used to select either one of the counter buses or the internal counter to be used by the Unified Channel. Refer to Table 24-20 for details. Edge Selection bit For input modes, the EDSEL bit selects whether the internal counter is triggered by both edges of a pulse or just by a single edge as defined by the EDPOL bit. When not shown in the mode of operation description, this bit has no effect. 1 = Both edges triggering 0 = Single edge triggering defined by the EDPOL bit For GPIO in mode, the EDSEL bit selects if a FLAG can be generated. 1 = No FLAG is generated 0 = A FLAG is generated as defined by the EDPOL bit EDPOL For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match. 1 = The output flip-flop is toggled 0 = The EDPOL value is transferred to the output flip-flop Edge Polarity bit For input modes, the EDPOL bit asserts which edge triggers either the internal counter or an input capture or a FLAG. When not shown in the mode of operation description, this bit has no effect. 1 = Trigger on a rising edge 0 = Trigger on a falling edge MODE For output modes, the EDPOL bit is used to select the logic level on the output pin. 1 = A match on comparator A sets the output flip-flop, while a match on comparator B clears it 0 = A match on comparator A clears the output flip-flop, while a match on comparator B sets it Mode selection The MODE field selects the mode of operation of the Unified Channel, as shown in Table 24-21. Note: If a reserved value is written to mode the results are unpredictable. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 543 UCPRE 00 01 10 11 Table 24-18. UC internalprescaler clock divider Divide ratio 1 2 3 4 Table 24-19. UC input filter bits IF1 Minimum input pulse width [FLT_CLK periods] 0000 Bypassed2 0001 02 0010 04 0100 08 1000 16 all others Reserved 1 Filter latency is 3 clock edges. 2 The input signal is synchronized before arriving to the digital filter. BSL 00 01 10 11 Table 24-20. UC BSL bits Selected bus All channels: counter bus[A] Channels 0 to 7: counter bus[B] Channels 8 to 15: counter bus[C] Channels 16 to 23: counter bus[D] Channels 24 to 27: counter bus[E] Reserved All channels: internal counter MODE1 0000000 0000001 0000010 0000011 0000100 0000101 0000110 Table 24-21. Channel mode selection Mode of operation General purpose Input/Output mode (input) General purpose Input/Output mode (output) Single Action Input Capture Single Action Output Compare Input Pulse Width Measurement Input Period Measurement Double Action Output Compare (with FLAG set on B match) MPC5604B/C Microcontroller Reference Manual, Rev. 8 544 Freescale Semiconductor Table 24-21. Channel mode selection (continued) MODE1 Mode of operation 0000111 Double Action Output Compare (with FLAG set on both match) 0001000 – 0001111 Reserved 001000b Modulus Counter (Up counter with clear on match start) 001001b Modulus Counter (Up counter with clear on match end) 00101bb Modulus Counter (Up/Down counter) 0011000 – 0100101 Reserved 0100110 Output Pulse Width Modulation with Trigger 0100111 – 1001111 Reserved 101000b Modulus Counter Buffered (Up counter) 101001b Reserved 10101bb Modulus Counter Buffered (Up/Down counter) 10110b0 Output Pulse Width and Frequency Modulation Buffered 10110b1 Reserved 10111b0 Center Aligned Output Pulse Width Modulation Buffered (with trail edge dead-time) 10111b1 Center Aligned Output Pulse Width Modulation Buffered (with lead edge dead-time) 11000b0 Output Pulse Width Modulation Buffered 1100001 – 1111111 Reserved 1 b = adjust parameters for the mode of operation. Refer to Section 24.4.4.1.1, UC modes of operation for details. 24.4.3.2.9 eMIOS UC Status Register (EMIOSS[n]) Address: UC[n] base address + 0x10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R OVR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVFL UCOUT FLAG 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 UCIN W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-16. eMIOS UC Status Register (EMIOSS[n]) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 545 Field OVR OVFL UCIN UCOUT FLAG Table 24-22. EMIOSS[n] field descriptions Description Overrun bit The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set. 1 = Overrun has occurred 0 = Overrun has not occurred Overflow bit The OVFL bit indicates that an overflow has occurred in the internal counter. OVFL must be cleared by software writing a 1 to the OVFLC bit. 1 = An overflow had occurred 0 = No overflow Unified Channel Input pin bit The UCIN bit reflects the input pin state after being filtered and synchronized. UCOUT — Unified Channel Output pin bit The UCOUT bit reflects the output pin state. FLAG bit The FLAG bit is set when an input capture or a match event in the comparators occurred. 1 = FLAG set event has occurred 0 = FLAG cleared Note: When DMA bit is set, the FLAG bit can be cleared by the CTU. 24.4.3.2.10 eMIOS UC Alternate A Register (EMIOSALTA[n]) Address: UC[n] base address + 0x14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ALTA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-17. eMIOS UC Alternate A register (EMIOSALTA[n]) The EMIOSALTA[n] register provides an alternate address to access A2 channel registers in restricted modes (GPIO, OPWMT) only. If EMIOSA[n] register is used along with EMIOSALTA[n], both A1 and A2 registers can be accessed in these modes. Figure 24-16 summarizes the EMIOSALTA[n] writing and reading accesses for all operation modes. Please, see Section 24.4.4.1.1.1, General purpose Input/Output (GPIO) mode, Section 24.4.4.1.1.12, Output Pulse Width Modulation with Trigger (OPWMT) mode for a more detailed description of the use of EMIOSALTA[n] register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 546 Freescale Semiconductor 24.4.4 Functional description The five types of channels of the eMIOS can operate in the modes as listed in Figure 24-7. The eMIOS provides independently operating unified channels (UC) that can be configured and accessed by a host MCU. Up to four time bases can be shared by the channels through four counter buses and each unified channel can generate its own time base. The eMIOS block is reset at positive edge of the clock (synchronous reset). All registers are cleared on reset. 24.4.4.1 Unified Channel (UC) Each Unified Channel consists of: • Counter bus selector, which selects the time base to be used by the channel for all timing functions • A programmable clock prescaler • Two double buffered data registers A and B that allow up to two input capture and/or output compare events to occur before software intervention is needed. • Two comparators (equal only) A and B, which compares the selected counter bus with the value in the data registers • Internal counter, which can be used as a local time base or to count input events • Programmable input filter, which ensures that only valid pin transitions are received by channel • Programmable input edge detector, which detects the rising, falling or either edges • An output flip-flop, which holds the logic level to be applied to the output pin • eMIOS Status and Control register 24.4.4.1.1 UC modes of operation The mode of operation of the Unified Channel is determined by the mode select bits MODE[0:6] in the eMIOS UC Control Register (EMIOSC[n]) (see Figure 24-15 for details). As the internal counter EMIOSCNT[n] continues to run in all modes (except for GPIO mode), it is possible to use this as a time base if the resource is not used in the current mode. In order to provide smooth waveform generation even if A and B registers are changed on the fly, it is available the MCB, OPWFMB, OPWMB and OPWMCB modes. In these modes A and B registers are double buffered. 24.4.4.1.1.1 General purpose Input/Output (GPIO) mode In GPIO mode, all input capture and output compare functions of the UC are disabled, the internal counter (EMIOSCNT[n] register) is cleared and disabled. All control bits remain accessible. In order to prepare the UC for a new operation mode, writing to registers EMIOSA[n] or EMIOSB[n] stores the same value in registers A1/A2 or B1/B2, respectively. Writing to register EMIOSALTA[n] stores a value only in register A2. MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 547 It is required that when changing MODE[0:6], the application software goes to GPIO mode first in order to reset the UC’s internal functions properly. Failure to do this could lead to invalid and unexpected output compare or input capture results or the FLAGs being set incorrectly. In GPIO input mode (MODE[0:6] = 0000000), the FLAG generation is determined according to EDPOL and EDSEL bits and the input pin status can be determined by reading the UCIN bit. In GPIO output mode (MODE[0:6] = 0000001), the Unified Channel is used as a single output port pin and the value of the EDPOL bit is permanently transferred to the output flip-flop. 24.4.4.1.1.2 Single Action Input Capture (SAIC) mode In SAIC mode (MODE[0:6] = 0000010), when a triggering event occurs on the input pin, the value on the selected time base is captured into register A2. The FLAG bit is set along with the capture event to indicate that an input capture has occurred. Register EMIOSA[n] returns the value of register A2. As soon as the SAIC mode is entered coming out from GPIO mode the channel is ready to capture events. The events are captured as soon as they occur thus reading register A always returns the value of the latest captured event. Subsequent captures are enabled with no need of further reads from EMIOSA[n] register. The FLAG is set at any time a new event is captured. The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL and EDSEL bits in EMIOSC[n] register. Figure 24-18 and Figure 24-19 show how the Unified Channel can be used for input capture. EDSEL = 0 EDPOL = 1 input signal1 selected counter bus FLAG pin/register 0x000500 Edge detect 0x001000 0x001100 Edge detect 0x001250 Edge detect 0x001525 0x0016A0 A2 (captured) value2 0xxxxxxx 0x001000 0x001250 0x0016A0 Notes: 1. After input filter 2. EMIOSA[n] <= A2 Figure 24-18. Single action input capture with rising edge triggering example MPC5604B/C Microcontroller Reference Manual, Rev. 8 548 Freescale Semiconductor EDSEL = 1 EDPOL = x Edge detect Edge detect Edge detect input signal1 selected counter bus 0x001000 0x001001 0x001102 0x001103 0x001104 0x001105 0x001106 0x001107 0x001108 FLAG set event FLAG pin/register FLAG clear A2 (captured) value2 0xxxxxxx 0x001000 0x001103 0x001108 Notes: 1. After input filter 2. EMIOSA[n] <= A2 Figure 24-19. Single action input capture with both edges triggering example 24.4.4.1.1.3 Single Action Output Compare (SAOC) mode In SAOC mode (MODE[0:6] = 0000011) a match value is loaded in register A2 and then immediately transferred to register A1 to be compared with the selected time base. When a match occurs, the EDSEL bit selects whether the output flip-flop is toggled or the value in EDPOL is transferred to it. Along with the match the FLAG bit is set to indicate that the output compare match has occurred. Writing to register EMIOSA[n] stores the value in register A2 and reading to register EMIOSA[n] returns the value of register A1. An output compare match can be simulated in software by setting the FORCMA bit in EMIOSC[n] register. In this case, the FLAG bit is not set. When SAOC mode is entered coming out from GPIO mode the output flip-flop is set to the complement of the EDPOL bit in the EMIOSC[n] register. Counter bus can be either internal or external and is selected through bits BSL[0:1]. Figure 24-20 and Figure 24-21 show how the Unified Channel can be used to perform a single output compare with EDPOL value being transferred to the output flip-flop and toggling the output flip-flop at each match, respectively. Note that once in SAOC mode the matches are enabled thus the desired match value on register A1 must be written before the mode is entered. A1 register can be updated at any time thus modifying the match value which will reflect in the output signal generated by the channel. Subsequent matches are enabled with no need of further writes to EMIOSA[n] register. The FLAG is set at the same time a match occurs (see Figure 24-22). NOTE The channel internal counter in SAOC mode is free-running. It starts counting as soon as the SAOC mode is entered. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 549 EDSEL = 0 EDPOL = 1 Update to A1 A1 match A1 match A1 match output flip-flop selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 FLAG pin/register A1 value1 0xxxxxxx 0x001000 0x001000 0x001000 0x001000 Notes: 1. EMIOSA[n] = A2 A2 = A1 according to OU[n] bit Figure 24-20. SAOC example with EDPOL value being transferred to the output flip-flop EDSEL = 1 EDPOL = x Update to A1 A1 match A1 match output flip-flop selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 FLAG pin/register A1 value1 0xxxxxxx 0x001000 0x001000 0x001000 Notes: 1. EMIOSA[n] = A2 A2 = A1 according to OU[n] bit Figure 24-21. SAOC example toggling the output flip-flop A1 match 0x001000 0x001000 EDSEL = 1 EDPOL = x output flip-flop selected counter bus 0x0 0x1 0x2 0x0 0x1 0x2 0x0 0x1 0x2 System Clock A1 match FLAG set event FLAG pin/register FLAG clear A2 value1 0x1 Note: 1. EMIOSA[n] <= A2 Figure 24-22. SAOC example with flag behavior 24.4.4.1.1.4 Input Pulse Width Measurement (IPWM) Mode The IPWM mode (MODE[0:6] = 0000100) allows the measurement of the width of a positive or negative pulse by capturing the leading edge on register B1 and the trailing edge on register A2. Successive captures are done on consecutive edges of opposite polarity. The leading edge sensitivity (that is, pulse polarity) is selected by EDPOL bit in the EMIOSC[n] register. Registers EMIOSA[n] and EMIOSB[n] return the values in register A2 and B1, respectively. The capture function of register A2 remains disabled until the first leading edge triggers the first input capture on register B2. When this leading edge is detected, the count value of the selected time base is latched into register B2; the FLAG bit is not set. When the trailing edge is detected, the count value of the MPC5604B/C Microcontroller Reference Manual, Rev. 8 550 Freescale Semiconductor selected time base is latched into register A2 and, at the same time, the FLAG bit is set and the content of register B2 is transferred to register B1 and to register A1. If subsequent input capture events occur while the corresponding FLAG bit is set, registers A2, B1 and A1 will be updated with the latest captured values and the FLAG will remain set. Registers EMIOSA[n] and EMIOSB[n] return the value in registers A2 and B1, respectively. In order to guarantee coherent access, reading EMIOSA[n] forces B1 be updated with the content of register A1. At the same time transfers between B2 and B1 are disabled until the next read of EMIOSB[n] register. Reading EMIOSB[n] register forces B1 be updated with A1 register content and re-enables transfers from B2 to B1, to take effect at the next trailing edge capture. Transfers from B2 to A1 are not blocked at any time. The input pulse width is calculated by subtracting the value in B1 from A2. Figure 24-23 shows how the Unified Channel can be used for input pulse width measurement. EDPOL = 1 B A B A B Input signal1 selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016A0 FLAG pin/register A2(captured) value2 B2(captured) value A1 value3 B1 value3 Notes: 1. After input filter 2. EMIOSA[n] = A2 3. EMIOSB[n] = B1 0xxxxxxx 0xxxxxxx 0xxxxxxx 0xxxxxxx 0x001000 0x001100 0x001000 0x001000 0x001250 0x001525 0x001250 0x001250 0x0016A0 Figure 24-23. Input pulse width measurement example Figure 24-24 shows the A1 and B1 updates when EMIOSA[n] and EMIOSB[n] register reads occur. Note that A1 register has always coherent data related to A2 register. Note also that when EMIOSA[n] read is performed B1 register is loaded with A1 register content. This guarantee that the data in register B1 has always the coherent data related to the last EMIOSA[n] read. The B1 register updates remains locked until EMIOSB[n] read occurs. If EMIOSA[n] read is performed B1 is updated with A1 register content even if B1 update is locked by a previous EMIOSA[n] read operation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 551 EDPOL = 1 Read EMIOSA[n] Read EMIOSB[n] B A B A B Input signal1 selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016A0 FLAG pin/register A2(captured) value2 B2(captured) value A1 value3 B1 value3 0xxxxxxx 0xxxxxxx 0xxxxxxx 0xxxxxxx 0x001000 0x001100 0x001000 0x001000 0x001525 0x001250 0x001250 0x001000 0x0016A0 0x001250 Notes: 1. After input filter 2. EMIOSA[n] = A2 3. EMIOSB[n] = B1 Figure 24-24. B1 and A1 updates at EMIOSA[n] and EMIOSB[n] reads Reading EMIOSA[n] followed by EMIOSB[n] always provides coherent data. If not coherent data is required for any reason, the sequence of reads should be inverted, therefore EMIOSB[n] should be read prior to EMIOSA[n] register. Note that even in this case B1 register updates will be blocked after EMIOSA[n] read, thus a second EMIOSB[n] is required in order to release B1 register updates. 24.4.4.1.1.5 Input Period Measurement (IPM) mode The IPM mode (MODE[0:6] = 0000101) allows the measurement of the period of an input signal by capturing two consecutive rising edges or two consecutive falling edges. Successive input captures are done on consecutive edges of the same polarity. The edge polarity is defined by the EDPOL bit in the EMIOSC[n] register. When the first edge of selected polarity is detected, the selected time base is latched into the registers A2 and B2, and the data previously held in register B2 is transferred to register B1. On this first capture the FLAG line is not set, and the values in registers B1 is meaningless. On the second and subsequent captures, the FLAG line is set and data in register B2 is transferred to register B1. When the second edge of the same polarity is detected, the counter bus value is latched into registers A2 and B2, the data previously held in register B2 is transferred to data register B1 and to register A1. The FLAG bit is set to indicate the start and end points of a complete period have been captured. This sequence of events is repeated for each subsequent capture. Registers EMIOSA[n] and EMIOSB[n] return the values in register A2 and B1, respectively. In order to allow coherent data, reading EMIOSA[n] forces A1 content be transferred to B1 register and disables transfers between B2 and B1. These transfers are disabled until the next read of the EMIOSB[n] register. Reading EMIOSB[n] register forces A1 content to be transferred to B1 and re-enables transfers from B2 to B1, to take effect at the next edge capture. The input pulse period is calculated by subtracting the value in B1 from A2. Figure 24-25 shows how the Unified Channel can be used for input period measurement. MPC5604B/C Microcontroller Reference Manual, Rev. 8 552 Freescale Semiconductor EDPOL = 1 Input signal1 selected counter bus 0x000500 A 0x001000 0x001100 A 0x001250 0x001525 A 0x0016A0 FLAG pin register A2(captured) value2 0xxxxxxx 0x001000 0x001250 B2 (captured) value 0xxxxxxx 0x001000 0x001250 A1 value 0xxxxxxx 0x001000 B1 value3 0xxxxxxx 0x001000 Notes: 1. After input filter 2. EMIOSA[n] = A2 3. EMIOSB[n] = B1 Figure 24-25. Input period measurement example 0x0016A0 0x0016A0 0x001250 0x001250 Figure 24-26 describes the A1 and B1 register updates when EMIOSA[n] and EMIOSB[n] read operations are performed. When EMIOSA[n] read occurs the content of A1 is transferred to B1 thus providing coherent data in A2 and B1 registers. Transfers from B2 to B1 are then blocked until EMIOSB[n] is read. After EMIOSB[n] is read, register A1 content is transferred to register B1 and the transfers from B2 to B1 are re-enabled to occur at the transfer edges, which is the leading edge in the Figure 24-26 example. EDPOL = 1 Read EMIOSA[n] Read EMIOSB[n] A A A Input signal1 selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016A0 FLAG pin/register A2(captured) value2 B2(captured) value A1 value B1 value3 0xxxxxxx 0xxxxxxx 0xxxxxxx 0xxxxxxx 0x001000 0x001000 0x001250 0x001250 0x001000 0x001000 0x001000 0x0016A0 0x0016A0 0x001250 0x001250 Notes: 1. After input filter 2. EMIOSA[n] = A2 3. EMIOSB[n] = B1 Figure 24-26. A1 and B1 updates at EMIOSA[n] and EMIOSB[n] reads 24.4.4.1.1.6 Double Action Output Compare (DAOC) mode In the DAOC mode the leading and trailing edges of the variable pulse width output are generated by matches occurring on comparators A and B. There is no restriction concerning the order in which A and B matches occur. When the DAOC mode is entered, coming out from GPIO mode both comparators are disabled and the output flip-flop is set to the complement of the EDPOL bit in the EMIOSC[n] register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor 553 Data written to A2 and B2 are transferred to A1 and B1, respectively, on the next system clock cycle if bit OU[n] of the EMIOSOUDIS register is cleared (see Figure 24-29). The transfer is blocked if bit OU[n] is set. Comparator A is enabled only after the transfer to A1 register occurs and is disabled on the next A match. Comparator B is enabled only after the transfer to B1 register occurs and is disabled on the next B match. Comparators A and B are enabled and disabled independently. The output flip-flop is set to the value of EDPOL when a match occurs on comparator A and to the complement of EDPOL when a match occurs on comparator B. MODE[6] controls if the FLAG is set on both matches (MODE[0:6] = 0000111) or just on the B match (MODE[0:6] = 0000110). FLAG bit assertion depends on comparator enabling. If subsequent enabled output compares occur on registers A1 and B1, pulses will continue to be generated, regardless of the state of the FLAG bit. At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level corresponding to a comparison event in comparator A or B, respectively. Note that the FLAG bit is not affected by these forced operations. NOTE If both registers (A1 and B1) are loaded with the same value, the B match prevails concerning the output pin state (output flip-flop is set to the complement of EDPOL), the FLAG bit is set and both comparators are disabled. Figure 24-27 and Figure 24-28 show how the Unified Channel can be used to generate a single output pulse with FLAG bit being set on the second match or on both matches, respectively. MODE[6] = 0 Update to A1 and B1 A1 match B1 match A1 match B1 match output flip-flop selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 FLAG pin/register A1 value1 0xxxxxxx 0x001000 B1 value2 0xxxxxxx 0x001100 0x001000 0x001100 0x001000 0x001100 Notes: 1. EMIOSA[n] = A1 (when reading) 2. EMIOSB[n] = B1 (when reading) A2 = A1according to OU[n] bit B2 = B1according to OU[n] bit Figure 24-27. Double action output compare with FLAG set on the second match MPC5604B/C Microcontroller Reference Manual, Rev. 8 554 Freescale Semiconductor MODE[6] = 1 Update to A1 and B1 A1 match B1 match A1 match B1 match output flip-flop selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 FLAG pin/register A1 value1 0xxxxxxx 0x001000 B1 value2 0xxxxxxx 0x001100 0x001000 0x001100 0x001000 0x001100 Notes: 1. EMIOSA[n] = A1 (when reading) 2. EMIOSB[n] = B1 (when reading) A2 = A1according to OU[n] bit B2 = B1according to OU[n] bit Figure 24-28. Double action output compare with FLAG set on both matches write to A2 write to B2 write to A2 write to B2 write to A2 write to B2 MODE[0]=1 EDSEL = 1 EDPOL = x output flip-flop selected counter bus 0x0 0x1 0x2 0x0 0x1 0x2 0x0 0x1 0x2 System Clock enabled A1 match enabled B1 match FLAG set event FLAG pin/register FLAG clear OU1 A1 value2 0xx 0x1 A2 value3 0xx 0x1 0x1 0x1 0x1 0x1 B1 value4 0xx 0x2 0x2 0x2 B2 value5 0xx 0x2 0x2 0x2 Note: 1. OU[n] bit of EMIOSOUDIS register 2. EMIOSA[n] = A1 (when reading) 3. EMIOSA[n] = A2 (when writing) 4. EMIOSB[n] = B1 (when reading) 5. EMIOSB[n] = B2 (when writing) Figure 24-29. DAOC with transfer disabling example 24.4.4.1.1.7 Modulus Counter (MC) mode The MC mode can be used to provide a time base for a counter bus or as a general purpose timer. Bit MODE[6] selects internal or external clock source when cleared or set, respectively. When external clock is selected, the input signal pin is used