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    LF155 LF156 LF157 Series Monolithic JFET Input Operational Amplifiers December 1994 LF155 LF156 LF157 Series Monolithic JFET Input Operational Amplifiers General Description These are the first monolithic JFET input operational amplifiers to incorporate well matched high voltage JFETs on the same chip with standard bipolar transistors (BI-FETTM Technology) These amplifiers feature low input bias and offset currents low offset voltage and offset voltage drift coupled with offset adjust which does not degrade drift or commonmode rejection The devices are also designed for high slew rate wide bandwidth extremely fast settling time low voltage and current noise and a low 1 f noise corner Advantages Y Replace expensive hybrid and module FET op amps Y Rugged JFETs allow blow-out free handling compared with MOSFET input devices Y Excellent for low noise applications using either high or low source impedance very low 1 f corner Y Offset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers Y New output stage allows use of large capacitive loads (5 000 pF) without stability problems Y Internal compensation and large differential input volt- age capability Applications Y Precision high speed integrators Y Fast D A and A D converters Y High impedance buffers Y Wideband low noise low drift amplifiers Y Logarithmic amplifiers Y Photocell amplifiers Y Sample and Hold circuits Common Features (LF155A LF156A LF157A) Y Low input bias current Y Low Input Offset Current Y High input impedance Y Low input offset voltage Y Low input offset voltage temp drift Y Low input noise current Y High common-mode rejection ratio Y Large dc voltage gain 30 pA 3 pA 1012X 1 mV 3 mV C 0 01 pA 0Hz 100 dB 106 dB Uncommon Features Y Extremely fast settling time to 0 01% LF155A LF156A LF157A (AVe5) Units 4 15 15 ms Y Fast slew rate 5 12 50 V ms Y Wide gain 25 5 20 MHz bandwidth Y Low input noise voltage 20 12 12 nV 0Hz Simplified Schematic 3 pF in LF157 series BI-FETTM BI-FET IITM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL H 5646 TL H 5646 – 1 RRD-B30M115 Printed in U S A Absolute Maximum Ratings If Military Aerospace specified devices are required contact the National Semiconductor Sales Office Distributors for availability and specifications (Note 8) LF155A 6A 7A LF155 6 7 LF355B 6B 7B LF255 6 7 LF355 6 7 LF355A 6A 7A Supply Voltage g22V g22V g22V g18V Differential Input Voltage g40V g40V g40V g30V Input Voltage Range (Note 2) g20V g20V g20V g16V Output Short Circuit Duration Continuous Continuous Continuous Continuous TjMAX H-Package N-Package M-Package 150 C 150 C 115 C 100 C 100 C 115 C 100 C 100 C Power Dissipation at TA e 25 C (Notes 1 and 9) H-Package (Still Air) 560 mW H-Package (400 LF Min Air Flow) 1200 mW N-Package M-Package 560 mW 1200 mW 400 mW 1000 mW 670 mW 380 mW 400 mW 1000 mW 670 mW 380 mW Thermal Resistance (Typical) iJA H-Package (Still Air) H-Package (400 LF Min Air Flow) N-Package M-Package 160 C W 65 C W 160 C W 65 C W 160 C W 65 C W 130 C W 195 C W 160 C W 65 C W 130 C W 195 C W (Typical) iJC H-Package 23 C W 23 C W 23 C W 23 C W Storage Temperature Range b65 C to a150 C b65 C to a150 C b65 C to a150 C b65 C to a150 C Soldering Information (Lead Temp ) Metal Can Package Soldering (10 sec ) 300 C 300 C 300 C 300 C Dual-In-Line Package Soldering (10 sec ) 260 C 260 C 260 C Small Outline Package Vapor Phase (60 sec ) 215 C 215 C Infrared (15 sec ) 220 C 220 C See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices ESD tolerance (100 pF discharged through 1 5 kX) 1000V 1000V 1000V 1000V DC Electrical Characteristics (Note 3) TA e Tj e 25 C Symbol Parameter Conditions LF155A 6A 7A Min Typ Max VOS Input Offset Voltage RSe50X TAe25 C Over Temperature 1 2 25 DVOS DT Average TC of Input Offset Voltage RSe50X 3 5 DTC DVOS IOS Change in Average TC with VOS Adjust Input Offset Current RSe50X (Note 4) Tje25 C (Notes 3 5) TjsTHIGH 05 3 10 10 IB Input Bias Current Tje25 C (Notes 3 5) TjsTHIGH RIN Input Resistance Tje25 C 30 50 25 1012 AVOL Large Signal Voltage VSe g15V TAe25 C 50 200 Gain VOe g10V RLe2k Over Temperature 25 VO Output Voltage Swing VSe g15V RLe10k g12 g13 VSe g15V RLe2k g10 g12 LF355A 6A 7A Min Typ Max 1 2 23 3 5 05 3 10 1 30 50 5 1012 50 200 25 g12 g10 g13 g12 Units mV mV mV C mV C per mV pA nA pA nA X V mV V mV V V 2 DC Electrical Characteristics (Note 3) TA e Tj e 25 C (Continued) Symbol Parameter Conditions LF155A 6A 7A Min Typ Max VCM Input Common-Mode Voltage Range VSe g15V g11 a15 1 b12 CMRR Common-Mode Rejection Ratio 85 100 PSRR Supply Voltage Rejection Ratio (Note 6) 85 100 LF355A 6A 7A Min Typ Max g11 a15 1 b12 85 100 85 100 Units V V dB dB AC Electrical Characteristics TA e Tj e 25 C VSeg15V Symbol Parameter Conditions LF155A 355A LF156A 356A Min Typ Max Min Typ Max SR GBW Slew Rate Gain Bandwidth Product LF155A 6A AVe1 3 5 LF157A AVe5 25 10 12 4 45 ts Settling Time to 0 01% (Note 7) en Equivalent Input Noise RSe100X Voltage fe100 Hz fe1000 Hz 4 15 25 15 20 12 in Equivalent Input fe100 Hz Noise Current fe1000 Hz 0 01 0 01 0 01 0 01 CIN Input Capacitance 3 3 LF157A 357A Min Typ Max 40 50 15 20 15 15 12 0 01 0 01 3 Units V ms V ms MHz ms nV 0Hz nV 0Hz pA 0Hz pA 0Hz pF DC Electrical Characteristics (Note 3) Symbol Parameter Conditions LF155 6 7 Min Typ Max LF255 6 7 LF355B 6B 7B Min Typ Max LF355 6 7 Min Typ Max Units VOS Input Offset Voltage RSe50X TAe25 C Over Temperature 3 5 7 3 5 65 3 10 mV 13 mV DVOS DT Average TC of Input Offset Voltage RSe50X 5 5 5 mV C DTC DVOS Change in Average TC RSe50X (Note 4) with VOS Adjust IOS Input Offset Current Tje25 C (Notes 3 5) TjsTHIGH 05 3 20 20 05 3 20 1 05 mV C per mV 3 50 pA 2 nA IB Input Bias Current Tje25 C (Notes 3 5) 30 100 30 100 30 200 pA TjsTHIGH 50 5 8 nA RIN Input Resistance Tje25 C 1012 1012 1012 X AVOL Large Signal Voltage VSe g15V TAe25 C 50 200 Gain VOe g10V RLe2k Over Temperature 25 50 200 25 25 200 15 V mV V mV VO Output Voltage Swing VSe g15V RLe10k g12 g13 g12 g13 g12 g13 V VSe g15V RLe2k g10 g12 g10 g12 g10 g12 V VCM Input Common-Mode Voltage Range VSe g15V g11 a15 1 b12 g11 g15 1 b12 a10 a15 1 b12 V V CMRR Common-Mode Rejection Ratio 85 100 85 100 80 100 dB PSRR Supply Voltage Rejec- (Note 6) tion Ratio 85 100 85 100 80 100 dB 3 DC Electrical Characteristics TA e Tj e 25 C VS e g15V Parameter LF155A 155 LF255 LF355A 355B LF355 LF156A 156 LF256 356B LF356A 356 Typ Max Typ Max Typ Max Typ Max Supply Current 2 4 24 5 7 5 10 LF157A 157 LF257 357B Typ Max 5 7 LF357A 357 Units Typ Max 5 10 mA AC Electrical Characteristics TA e Tj e 25 C VS e g15V Symbol Parameter Conditions LF155 255 LF156 256 LF156 256 355 355B LF356B 356 356B Typ Min Typ SR Slew Rate LF155 6 AVe1 5 LF157 AVe5 75 12 GBW Gain Bandwidth Product 25 5 ts Settling Time to 0 01% (Note 7) 4 15 en Equivalent Input Noise RSe100X Voltage fe100 Hz 25 15 fe1000 Hz 20 12 in Equivalent Input fe100 Hz 0 01 0 01 Current Noise fe1000 Hz 0 01 0 01 CIN Input Capacitance 3 3 LF157 257 LF157 257 LF357B 357 357B Min Typ 30 50 20 15 15 12 0 01 0 01 3 Units V ms V ms MHz ms nV 0Hz nV 0Hz pA 0Hz pA 0Hz pF Notes for Electrical Characteristics Note 1 The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TjMAX ijA and the ambient temperature TA The maximum available power dissipation at any temperature is Pde(TjMAXbTA) ijA or the 25 C PdMAX whichever is less Note 2 Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage Note 3 Unless otherwise stated these test conditions apply LF155A 6A 7A LF155 6 7 LF255 6 7 LF355A 6A 7A LF355B 6B 7B LF355 6 7 Supply Voltage VS TA THIGH g 15VsVSs g 20V b55 CsTAsa125 C a125 C g 15VsVSs g 20V b25 CsTAsa85 C a85 C g 15VsVSs g 18V 0 CsTAsa70 C a70 C g15VsVSg20V 0 CsTAsa70 C a70 C VSe g15V 0 CsTAsa70 C a70 C and VOS IB and IOS are measured at VCMe0 Note 4 The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0 5mV C typically) for each mV of adjustment from its original unadjusted value Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment Note 5 The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature TJ Due to limited production test time the input bias currents measured are correlated to junction temperature In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation Pd TjeTAaijA Pd where ijA is the thermal resistance from junction to ambient Use of a heat sink is recommended if input bias current is to be kept to a minimum Note 6 Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice Note 7 Settling time is defined here for a unity gain inverter connection using 2 kX resistors for the LF155 6 It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0 01% of its final value from the time a 10V step input is applied to the inverter For the LF157 AVeb5 the feedback resistor from output to input is 2 kX and the output step is 10V (See Settling Time Test Circuit) Note 8 Refer to RETS155AX for LF155A RETS155X for LF155 RETS156AX for LF156A RETS156X for LF156 RETS157A for LF157A and RETS157X for LF157 military specifications Note 9 Max Power Dissipation is defined by the package characteristics Operating the part near the Max Power Dissipation may cause the part to operate outside guaranteed limits 4 Typical DC Performance Characteristics Curves are for LF155 LF156 and LF157 unless otherwise specified Input Bias Current Input Bias Current Input Bias Current Voltage Swing Supply Current Supply Current Negative Current Limit Positive Current Limit Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit Open Loop Voltage Gain TL H 5646 – 2 Output Voltage Swing TL H 5646 – 3 5 Typical AC Performance Characteristics Gain Bandwidth Gain Bandwidth Normalized Slew Rate Output Impedance Output Impedance TL H 5646 – 4 Output Impedance LF155 Small Signal Pulse Response AVe a1 LF156 Small Signal Pulse Response AVe a1 Small Signal Pulse Response AVe a5 TL H 5646 – 12 TL H 5646–5 LF155 Large Signal Pulse Response AVe a1 TL H 5646 – 6 LF156 Large Signal Pulse Response AVe a1 TL H 5646 – 7 LF157 Large Signal Pulse Response AVe a5 TL H 5646–8 TL H 5646 – 9 6 TL H 5646 – 10 Typical AC Performance Characteristics (Continued) Inverter Settling Time Inverter Settling Time Open Loop Frequency Response Bode Plot Bode Plot Bode Plot Common-Mode Rejection Ratio Power Supply Rejection Ratio Power Supply Rejection Ratio Undistorted Output Voltage Swing Equivalent Input Noise Voltage Equivalent Input Noise Voltage (Expanded Scale) TL H 5646 – 11 7 Detailed Schematic C e 3 pF in LF157 series Connection Diagrams (Top Views) Metal Can Package (H) TL H 5646 – 13 Dual-In-Line Package (M and N) TL H 5646–14 Order Number LF156AH LF155H LF156H LF255H LF256H LF257H LF355AH LF356AH LF357AH LF356BH LF355H LF356H LF357H LM155AH 883 LM155H 883 LM156AH 883 LM156H 883 LM157AH 883 or LM157H 883 See NS Package Number H08C TL H 5646 – 29 Order Number LF355M LF356M LF357M LF355BM LF356BM LF355BN LF356BN LF357BN LF355N LF356N or LF357N See NS Package Number M08A or N08E Available per JM38510 11401 or JM38510 11402 8 Application Hints The LF155 6 7 series are op amps with JFET input devices These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs Therefore large differential input voltages can easily be accomodated without a large increase in input current The maximum differential input voltage is independent of the supply voltages However neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit Exceeding the negative common-mode limit on either input will force the output to a high state potentially causing a reversal of phase to the output Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode Exceeding the positive common-mode limit on a single input will not change the phase of the output however if both inputs exceed the limit the output of the amplifier will be forced to a high state These amplifiers will operate with the common-mode input voltage equal to the positive supply In fact the commonmode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range The positive supply can therefore be used as a reference on an input as for example in a supply current monitor and or limiter Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit All of the bias currents in these amplifiers are set by FET current sources The drain currents for the amplifiers are therefore essentially independent of supply voltage As with most amplifiers care should be taken with lead dress component placement and supply decoupling in order to ensure stability For example resistors from the output to an input should be placed with the body close to the input to minimize ‘‘pickup’’ and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground A feedback pole is created when the feedback around any amplifier is resistive The parallel resistance and capacitance from the input of the device (usually the inverting input) to ac ground set the frequency of the pole In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin However if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant Typical Circuit Connections VOS Adjustment Driving Capacitive Loads LF157 A Large Power BW Amplifier  VOS is adjusted with a 25k potentiometer  The potentiometer wiper is connected to Va  For potentiometers with temperature coefficient of 100 ppm C or less the additional drift with adjust is 0 5 mV C mV of adjustment  Typical overall drift 5 mV C g(0 5 mV C mV of adj ) LF155 6 Re5k LF157 Re1 25k Due to a unique output stage design these amplifiers have the ability to drive large capacitive loads and still maintain stability CL(MAX) j 0 01 mF Overshoot s 20% Settling time (ts) j 5 ms TL H 5646 – 15 For distortion s 1% and a 20 Vp-p VOUT swing power bandwidth is 500 kHz 9 Typical Applications Settling Time Test Circuit  Settling time is tested with the LF155 6 connected as unity gain inverter and LF157 connected for AV e b5  FET used to isolate the probe capacitance  Output e 10V step  AV e b5 for LF157 TL H 5646 – 16 LF355 Large Signal inverter Output VOUT (from Settling Time Circuit) LF356 LF357 TL H 5646–17 TL H 5646 – 18 TL H 5646 – 19 Low Drift Adjustable Voltage Reference  D VOUT DTe g0 002% C  All resistors and potentiometers should be wire-wound  P1 drift adjust  P2 VOUT adjust  Use LF155 for X Low IB X Low drift X Low supply current TL H 5646–20 10 Typical Applications (Continued) Fast Logarithmic Converter  Dynamic range 100 mA s Ii s 1 mA (5 dec- ades) lVOle1V decade  Transient response 3 ms for DIie 1 decade  C1 C2 R2 R3 added dynamic compensation  VOS adjust the LF156 to minimize quiescent error  RT Tel Labs type Q81 a 0 3% C TL H 5646 – 21 l l ( ( VOUT e R2 1a RT kT q ln Vi Rr VREF Ri 1 e log Vi RiIr R2 e 15 7k RT e 1k 0 3% C (for temperature compensation) Precision Current Monitor  VOe5 R1 R2 (V mA of IS)  R1 R2 R3 0 1% resistors  Use LF155 for X Common-mode range to supply range X Low IB X Low VOS X Low Supply Current TL H 5646 – 31 8-Bit D A Converter with Symmetrical Offset Binary Operation TL H 5646 – 32  R1 R2 should be matched within g0 05%  Full-scale response time 3ms EO B1 B2 B3 B4 B5 B6 B7 B8 Comments a9 920 1 1 1 1 1 1 1 1 Positive Full-Scale a0 040 1 0 0 0 0 0 0 0 (a) Zero-Scale b0 040 0 1 1 1 1 1 1 1 (b) Zero-Scale b9 920 0 0 0 0 0 0 0 0 Negative Full-Scale 11 Typical Applications (Continued) Wide BW Low Noise Low Drift Amplifier Isolating Large Capacitive Loads  Power BW fMAX e Sr j 191 kHz 2qVP  Parasitic input capacitance C1 j (3 pF for LF155 LF156 and LF157 plus any additional layout capacitance) interacts with feedback elements and creates undesirable high frequency pole To compensate add C2 such that R2 C2 j R1 C1 Boosting the LF156 with a Current Amplifier  Overshoot 6% TL H 5646 – 22  ts 10 ms  When driving large CL the VOUT slew rate determined by CL and IOUT(MAX) DVOUT e IOUT j 0 02 V DT CL 0 5 ms e 0 04 V ms (with CL shown) Low Drift Peak Detector  IOUT(MAX)j150 mA (will drive RL t 100X)  DVOUT DT e 0 15 10b2 V ms (with CL shown)  No additional phase shift added by the current amplifier 3 Decades VCO TL H 5646  By adding D1 and Rf VD1e0 during hold mode Leakage of D2 provided by feedback path through Rf  Leakage of circuit is essentially Ib (LF155 LF156) plus capacitor leakage of Cp  Diode D3 clamps VOUT (A1) to VINbVD3 to improve speed and to limit reverse bias of D2  Maximum input frequency should be kk qRfCD2 where CD2 is the shunt capacitance of D2 Non-Inverting Unity Gain Operation for LF157 1 R1C t (2q) (5 MHz) R1 e R2 a RS 4 AV(DC) e 1 fb3 dB 5 MHz f e VC (R8aR7) (8 VPU R8 R1) C 0sVCs30V 10 Hzsfs10 kHz R1 R4 matched Linearity 0 1% over 2 decades TL H 5646–24 12 Inverting Unity Gain for LF157 1 R1C t (2q) (5 MHz) R2 R1 e 4 AV(DC) e b1 fb3 dB 5 MHz TL H 5646 – 25 Typical Applications (Continued) High Impedance Low Drift Instrumentation Amplifier ( R3 2R2  VOUT e R a1 R1 DV Vb a 2V s VIN common-mode s Va  System VOS adjusted via A2 VOS adjust  Trim R3 to boost up CMRR to 120 dB Instrumentation amplifier resistor array recommended for best accuracy and lowest drift TL H 5646 – 26 13 Typical Applications (Continued) Fast Sample and Hold  Both amplifiers (A1 A2) have feedback loops individually closed with stable responses (overshoot negligible)  Acquisition time TA estimated by ( TA j 2RON VIN Ch Sr provided that VIN k 2qSr RON Ch and TA l VIN Ch IOUT(MAX) RON is of SW1 If inequality not satisfied TA j VIN Ch 20 mA  LF156 develops full Sr output capability for VINt1V  Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop  Overall accuracy of system determined by the accuracy of both amplifiers A1 and A2 TL H 5646 – 33 High Accuracy Sample and Hold  By closing the loop through A2 the VOUT accuracy will be determined uniquely by A1 No VOS adjust required for A2  TA can be estimated by same considerations as previously but because of the added propagation delay in the feedback loop (A2) the overshoot is not negligible  Overall system slower than fast sample and hold  R1 CC additional compensation  Use LF156 for X Fast settling time X Low VOS TL H 5646 – 27 14 Typical Applications (Continued) High Q Band Pass Filter  By adding positive feedback (R2) Q increases to 40  fBPe100 kHz VOUT VIN e 100Q  Clean layout recommended  Response to a 1 Vp-p tone burst 300 ms TL H 5646 – 28 High Q Notch Filter  2R1 e R e 10 MX 2C e C1 e 300 pF  Capacitors should be matched to obtain high Q  fNOTCH e 120 Hz notch e b55 dB Q l 100  Use LF155 for X Low IB X Low supply current TL H 5646 – 34 15 16 Physical Dimensions inches (millimeters) Metal Can Package (H) Order Number LF156AH LF155H LF156H LF255H LF256H LF257H LF355AH LF356AH LF357AH LF356BH LF355H LF356H or LF357H NS Package Number H08C Small Outline Package (M) Order Number LF355M LF356M LF357M LF355BM or LF356BM NS Package Number M08A 17 LF155 LF156 LF157 Series Monolithic JFET Input Operational Amplifiers Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number LF355N LF356N LF357N LF355BN LF356BN LF357BN NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

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