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TPS25940数据手册

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    TPS25940 eFuse 电源开关是一款紧凑且特性丰富的

    此器件具有一整套的保护功能, 其中包括一个低功率 DevSleep™ 模式, 此模式支持与 SATA™ 器件睡眠标准的兼容性。 宽工作范围可实现对很多常用直流总线电压的控制。 集成背靠背场效应晶体管 (FET) 提供双向电流控制, 从而使得器件非常适合于那些具有负载侧保持能量, 而这些能量又一定不能回流至故障电源总线的系统。

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    Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 TPS25940x 2.7V - 18V 电子熔丝 (eFuse),具有真正反向阻断和针对固态 硬盘 (SSD) 的 DevSleep 支持 1 特性 •1 2.7V - 18V 工作电压,最大绝对值 20V • 42mΩ RON(典型值) • 0.6A 至 5.3A 可调电流限值 (±8%) • IMON 电流指示器输出 (±8%) • 200μA 工作 IQ(典型值) • 95μA DevSleep 模式 IQ(典型值) • 被禁用时,15µA IQ(典型值) • ±2% 过压、欠压阈值 • 反向电流阻断 • 1µs 反向电压关闭 • 可编程 dVo/dt 控制 • 电源正常和故障输出 • -40°C 至 125°C 的结温范围 • UL2367 认证正在处理中 • UL60950 - 单点故障测试期间安全 2 应用范围 • PCIe/SATA/SAS 硬盘 (HDD) 和 SSD 硬盘 • 企业级和微型服务器 • 智能负载开关 • 机顶盒 (STB),数字电视 (DTV) 和游戏控制台 • RAID 卡 - 保持电源管理 • 电信交换机和路由器 • 适配器供电器件 3 说明 TPS25940 eFuse 电源开关是一款紧凑且特性丰富的 电源管理器件,此器件具有一整套的保护功能,其中包 括一个低功率 DevSleep™ 模式,此模式支持与 SATA™ 器件睡眠标准的兼容性。 宽工作范围可实现 对很多常用直流总线电压的控制。 集成背靠背场效应 晶体管 (FET) 提供双向电流控制,从而使得器件非常 适合于那些具有负载侧保持能量,而这些能量又一定不 能回流至故障电源总线的系统。 负载、电源和器件保护由很多可编程特性提供,其中包 括过流,dVo/dt 斜率和过压、欠压阈值。 为了实现系 统状态监视和下游负载控制,此器件提供 PGOOD,FLT 和精密电流监视输出。 精密可编程欠 压、过压阈值和低 IQ DevSleep 模式简化了 SSD 电源 管理设计。 TPS25940 监视 V(IN) 和 V(OUT),以便在 V(IN) < (V(OUT) - 10mV) 时提供真正反向阻断。 这个功能在后备电压 大于总线电压的系统中支持快速切换至一个升压储能元 件。 产品型号(2) TPS25940A TPS25940L 器件信息(1) 封装 超薄四方扁平无引线 (WQFN) (20) 封装尺寸(标称值) 3.00mm x 4.00mm (1) 如需了解所有可用封装,请见数据表末尾的可订购产品附录。 (2) TPS25940L = 已锁存,TPS25940A = 自动重试 4 简化电路原理图 2.7 to 18 V V(IN) IN RTOTAL = EN/UVLO 42 m: OUT FLT OVP PGOOD DEVSLP PGTH dVdT IMON GND ILIM TPS25940x To Load 电源故障检测和阻断 1 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. English Data Sheet: SLVSCF3 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn 目录 1 特性.......................................................................... 1 2 应用范围................................................................... 1 3 说明.......................................................................... 1 4 简化电路原理图........................................................ 1 5 修订历史记录 ........................................................... 2 6 Pin Configuration and Functions ......................... 3 7 Specifications......................................................... 4 7.1 Absolute Maximum Ratings ...................................... 4 7.2 Handling Ratings....................................................... 4 7.3 Recommended Operating Conditions....................... 4 7.4 Thermal Characteristics ............................................ 5 7.5 Electrical Characteristics........................................... 6 7.6 Timing Requirements ................................................ 8 7.7 Typical Characteristics .............................................. 9 8 Parametric Measurement Information ............... 16 9 Detailed Description ............................................ 17 9.1 Overview ................................................................. 17 9.2 Functional Block Diagram ....................................... 18 9.3 Feature Description................................................. 19 9.4 Device Functional Modes........................................ 23 10 Application and Implementation........................ 25 10.1 Application Information.......................................... 25 10.2 Typical Application ................................................ 25 10.3 System Examples ................................................. 33 11 Power Supply Recommendations ..................... 36 11.1 Transient Protection .............................................. 36 11.2 Output Short-Circuit Measurements ..................... 37 12 Layout................................................................... 38 12.1 Layout Guidelines ................................................. 38 12.2 Layout Example .................................................... 39 13 器件和文档支持 ..................................................... 40 13.1 相关链接................................................................ 40 13.2 Trademarks ........................................................... 40 13.3 Electrostatic Discharge Caution ............................ 40 13.4 Glossary ................................................................ 40 14 机械封装和可订购信息 .......................................... 40 5 修订历史记录 日期 2014 年 6 月 修订版本 * 注释 最初发布。 2 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn 6 Pin Configuration and Functions TPS25940 RVC PACKAGE (TOP VIEW) TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 ILIM 17 dVdT 18 IMON 19 FLT 20 DEVSLP 1 PGOOD 2 PGTH 3 OUT 4 OUT 5 OUT 6 Thermal Pad 16 GND 15 OVP 14 EN 13 IN 12 IN 11 IN 10 IN 9 IN 8 OUT 7 OUT NAME DEVSLP PGOOD PGTH OUT IN EN/UVLO NO. 1 2 3 4-8 9 - 13 14 OVP 15 GND 16 ILIM 17 dVdT 18 IMON 19 FLT 20 PowerPADTM Pin Functions I/O DESCRIPTION I Active High. DevSleep Mode control. A high at this pin will activate the DevSleep mode(Low Power Mode). O Active High. A high indicates PGTH has crossed the threshold value. It is an open drain output. I Positive input of PGOOD comparator. O Power Output of the device. I Power Input and supply voltage of the device. I Input for setting programmable undervoltage lockout threshold. An undervoltage event will open internal FET and assert FLT to indicate power-failure. When pulled to GND, resets the fault latch in TPS25940L. I Input for setting programmable overvoltage protection threshold. An overvoltage event will open the internal FET and assert FLT to indicate overvoltage. — Ground. I/O A resistor from this pin to GND sets the overload and short-circuit current limit. I/O A capacitor from this pin to GND sets the ramp rate of output voltage. O This pin sources a scaled down ratio of current through the internal FET. A resistor from this pin to GND converts current to proportional voltage, used as analog current monitor. O Fault event indicator, goes low to indicate fault condition due to Undervoltage, Overvoltage, Reverse voltage and Thermal shutdown event. It is an open drain output. The GND terminal must be connected to the exposed PowerPAD. This PowerPAD must be connected to a PCB ground plane using multiple vias for good thermal performance. Copyright © 2014, Texas Instruments Incorporated 3 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn 7 Specifications 7.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted) (1) IN, OUT, PGTH, PGOOD, EN/UVLO, OVP, DEVSLP, FLT Input voltage range IN (10 ms Transient) dVdT, ILIM IMON Sink current PGOOD, FLT, dVdT Source current dVdT, ILIM, IMON Maximum junction, TJ Continuous power dissipation VALUE UNIT MIN MAX –0.3 20 22 V –0.3 3.6 –0.3 7 10 mA Internally Limited –40 150 °C See the Thermal Characteristics(2) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.2 Handling Ratings Tstg VESD Storage temperature range Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) MIN –65 -2 -500 MAX 150 2 500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. UNIT °C kV V 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) IN EN/UVLO, OVP, DEVSLP, OUT, PGTH, PGOOD, FLT Input voltage range dVdT, ILIM IMON Resistance ILIM IMON OUT External capacitance dVdT Operating junction temperature range, TJ MIN NOM MAX UNIT 2.7 18 0 18 V 0 3 0 6 16.9 150 kΩ 1 0.1 µF 470 nF –40 25 125 °C 4 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 7.4 Thermal Characteristics(1) THERMAL METRIC TPS25940 RVC (20) PINS UNIT RθJA RθJCtop RθJB ψJT ψJB RθJCbot Junction-to-ambient thermal resistance Junction-to-case (top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance 38.1 40.5 13.6 °C/W 0.6 13.7 3.4 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2014, Texas Instruments Incorporated 5 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn 7.5 Electrical Characteristics Conditions are –40°C ≤ TJ=TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted) PARAMETER TEST CONDITIONS SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT V(IN) Operating Input Voltage V(UVR) Internal UVLO threshold, rising V(UVRhys) Internal UVLO hysteresis V(EN/UVLO) = 2 V, V(IN) = 3 V IQ(ON) Supply current, Enabled V(EN/UVLO) = 2 V, V(IN) = 12 V V(EN/UVLO) = 2 V, V(IN) = 18 V V(EN/UVLO) = 0 V, V(IN) = 3 V IQ(OFF) Supply current, Disabled V(EN/UVLO) = 0 V, V(IN) = 12 V V(EN/UVLO) = 0 V, V(IN) = 18 V IQ(DEVSLP) Supply current, DevSleep Mode V(DEVSLP) = 0 V, V(IN) = 2.7V to 18V ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT V(ENR) V(ENF) V(SHUTF) EN/UVLO threshold voltage, rising EN/UVLO threshold voltage, falling EN threshold voltage for Low IQ shutdown, falling V(SHUTFhys) EN hysteresis for low IQ shutdown, hysteresis (1) IEN EN Input leakage current OVER VOLTAGE PROTECTION (OVP) INPUT 0 V ≤ V(EN/UVLO) ≤ 18 V V(OVPR) Overvoltage Threshold Voltage, Rising, V(OVPF) Overvoltage Threshold Voltage, Falling I(OVP) OVP Input Leakage Current DEVSLP MODE INPUT (DEVSLP): ACTIVE HIGH 0 V ≤ V(OVP) ≤ 5 V V(DEVSLPR) DEVSLP threshold voltage, rising V(DEVSLPF) DEVSLP threshold voltage, falling I(DEVSLP) DEVSLP input leakage current OUTPUT RAMP CONTROL (dVdT) 0.2 V ≤ V(DEVSLP) ≤ 18 V I(dVdT) dVdT charging current R(dVdT) dVdT discharging resistance V(dVdTmax) dVdT maximum capacitor voltage GAIN(dVdT) dVdT to OUT gain CURRENT LIMIT PROGRAMMING (ILIM) V(dVdT) = 0 V EN/UVLO = 0 V, I(dVdT) = 10 mA sinking ΔV(OUT)/ΔV(dVdT) V(ILIM) ILIM bias voltage I(LIM) Current limit(2) R(ILIM) = 150 kΩ, (V(IN) - V(OUT)) = 1 V R(ILIM) = 88.7 kΩ, (V(IN) - V(OUT)) = 1 V R(ILIM) = 42.2 kΩ, (V(IN) - V(OUT)) = 1 V R(ILIM) = 24.9 kΩ, (V(IN) - V(OUT)) = 1 V R(ILIM) = 16.9 kΩ, (V(IN) - V(OUT)) = 1 V R(ILIM) = OPEN, Open resistor current limit (Single Point Failure Test: UL60950) R(ILIM) = SHORT, Shorted resistor current limit (Single Point Failure Test: UL60950) I(DEVSLP(LIM)) DevSleep Mode Current Limit MIN 2.7 2.2 105 140 140 140 4 6 8 70 0.97 0.9 0.3 –100 0.97 0.9 -100 1.6 0.8 0.6 0.85 2.6 11.65 0.53 0.9 1.92 3.25 4.78 0.35 0.55 0.55 TYP MAX UNIT 18 V 2.3 2.4 V 116 125 mV 210 300 199 260 µA 202 270 8.6 15 15 20 µA 18.5 25 95 130 µA 0.99 1.01 V 0.92 0.94 V 0.47 0.63 V 66 mV 0 100 nA 0.99 1.01 V 0.92 0.94 V 0 100 nA 1.85 2 V 0.96 1.1 V 1 1.25 µA 1 1.15 µA 16 24 Ω 2.88 3.1 V 11.9 12.05 V/V 0.87 V 0.58 0.63 0.99 1.07 2.08 2.25 3.53 3.81 5.2 5.62 A 0.45 0.55 0.67 0.8 0.67 0.8 A (1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty. (2) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately. 6 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Electrical Characteristics (continued) Conditions are –40°C ≤ TJ=TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOS I(FASTRIP) R(ILIM) = 42.2 kΩ, V(VIN) = 12 V, (V(IN) -V(OUT)) = 5 V 1.91 2.07 2.24 Short-circuit current limit (2) R(ILIM) = 24.9 kΩ, V(VIN) = 12 V, (V(IN) -V(OUT)) = 5 V R(ILIM) = 16.9 kΩ, V(VIN) = 12 V, (V(IN) -V(OUT))= 5 V, -40°C ≤ TJ ≤ 85°C 3.21 4.7 3.49 3.77 A 5.11 5.52 Fast-Trip comparator threshold(1)(2) 1.5 x I(LIM) + 0.375 A CURRENT MONITOR OUTPUT (IMON) GAIN(IMON) Gain Factor I(IMON):I(OUT) MOSFET – POWER SWITCH 1 A ≤ I(OUT) ≤ 5 A 47.78 52.3 57.23 µA/A RON IN to OUT - ON Resistance PASS FET OUTPUT (OUT) 1 A ≤ I(OUT) ≤ 5 A, TJ = 25°C 1 A ≤ I(OUT) ≤ 5 A, -40°C ≤ TJ ≤ 85°C 1 A ≤ I(OUT) ≤ 5 A, -40°C ≤ TJ ≤ 125°C 34 42 49 26 42 58 mΩ 26 42 64 Ilkg(OUT) V(REVTH) OUT leakage current in off state V(IN) = 18 V, V(EN/UVLO) = 0 V, V(OUT) = 0 V (Sourcing) –2 V(IN) = 2.7 V, V(EN/UVLO) = 0 V, V(OUT) = 18 V (Sinking) 6 V(IN) -V(OUT) threshold for reverse protection comparator, falling –15 0 2 µA 13 20 -9.3 –3 mV V(FWDTH) V(IN) -V(OUT) threshold for reverse protection comparator, rising 86 100 114 mV FAULT FLAG (FLT): ACTIVE LOW R(FLT) FLT internal pull-down resistance V(OVP) = 2 V, I(FLT) = 5 mA sinking I(FLT) FLT input leakage current 0 V ≤ V(FLT) ≤ 18 V POSITIVE INPUT for POWER-GOOD COMPARATOR (PGTH) 10 18 30 Ω –1 0 1 µA V(PGTHR) PGTH threshold voltage, rising V(PGTHF) PGTH threshold voltage, falling I(PGTH) PGTH input leakage current 0 V ≤ V(PGTH) ≤ 18 V POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH 0.97 0.9 –100 0.99 1.01 V 0.92 0.94 V 0 100 nA R(PGOOD) PGOOD internal pull-down resistance V(PGTH) = 0V, I(PGOOD) = 5 mA sinking 10 20 35 Ω I(PGOOD) PGOOD input leakage current THERMAL SHUT DOWN (TSD) T(TSD) T(TSDhys) TSD Threshold(3) TSD Hysteresis(3) Thermal Fault: (Latched or AutoRetry) 0 V ≤ V(PGOOD) ≤ 18 V TPS25940L TPS25940A –1 0 160 12 LATCHED AUTORETRY 1 µA °C °C (3) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty. Copyright © 2014, Texas Instruments Incorporated 7 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn 7.6 Timing Requirements Conditions are –40°C ≤ TJ=TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted). Refer to Figure 42 for the timing diagrams. PARAMETER TEST CONDITIONS ENABLE and UVLO INPUT tON(dly) EN turn on delay tOFF(dly) EN turn off delay OVERVOLTAGE PROTECTION INPUT (OVP) EN/UVLO ↑ (100mV above V(ENR)) to V(OUT) = 100 mV, C(dVdT) < 0.8 nF EN/UVLO ↑ (100mV above V(ENR)) to V(OUT) = 100 mV, C(dVdT) ≥ 0.8 nF, [C(dVdT) in nF] EN/UVLO ↓ (100mV below V(ENF)) to FLT↓ tOVP(dly) OVP disable delay OUTPUT RAMP CONTROL (dV/dT ) OVP↑ (100mV above V(OVPR)) to FLT↓ tdVdT Output ramp time CURRENT LIMIT EN/UVLO ↑ to V(OUT) = 4.5 V, with C(dVdT) = open EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = open EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = 1 nF tFASTRIP(dly) Fast-Trip comparator delay REVERSE PROTECTION COMPARATOR I(OUT) > I(FASTRIP) tREV(dly) tFWD(dly) Reverse protection comparator delay (V(IN) - V(OUT))↓ (1 mV overdrive below V(REVTH)) to FLT↓ (V(IN) - V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT↓ (V(IN) - V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT↑ POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH tPGOODR tPGOODF PGOOD delay (de-glitch) time THERMAL SHUT DOWN (TSD) Rising edge Falling edge Retry delay in TSD TPS25940A Only MIN TYP MAX UNIT 220 µs 100 + 150 x C(dVdT) µs 2 µs 2 µs 0.12 0.25 0.37 0.5 ms 0.97 200 ns 10 1 µs 3.1 0.42 0.54 0.66 ms 0.42 0.54 0.66 ms 128 ms 8 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 7.7 Typical Characteristics Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise) Internal UVLO Threshold Voltage (V) 2.35 2.30 2.25 2.20 2.15 2.10 ±50 ±20 10 40 70 Temperature (oC) VU(UVVLRO) R VU(UVVLFO) F 100 130 C014 Supply Current, IQ(ON) (µA) 300 250 200 150 100 50 0 0 TTAA = -40o0CC TTAA = 25o0CC TTAA = 85o0CC TTAA = 125o0CC 5 10 15 20 Input Voltage (V) C014 Supply Current, IQ(OFF) (µA) Figure 1. UVLO Threshold Voltage vs Temperature 25 20 15 10 5 0 0 TTAA = -40o0CC TTAA = 25o0CC TTAA = 85o0CC TTAA = 125o0CC 5 10 15 20 Input Voltage (V) C014 Supply Current, IQ(DEVSLP) (µA) Figure 2. Input Supply Current vs Supply Voltage During Normal Operation 150 125 100 75 50 25 0 0 TTAA = -40o0CC TTAA = 25o0CC TTAA = 85o0CC TTAA = 125o0CC 5 10 15 20 Input Voltage (V) C014 EN/UVLO Threshold Voltage (V) Figure 3. Input Supply Current vs Supply Voltage at Shutdown 1.00 0.98 0.96 0.94 V(EENNR)Ris V(EENNF)Fall 0.92 0.90 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 OVP Threshold Voltage (V) Figure 4. Input Supply Current vs Supply Voltage in DevSleep Mode 1.00 0.98 0.96 0.94 OVV(OPVPRRi)sing OVV(OPVPFFa) lling 0.92 0.90 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 Figure 5. EN Threshold Voltage vs Temperature Figure 6. OVP Threshold Voltage vs Temperature Copyright © 2014, Texas Instruments Incorporated 9 EN Threshold Voltage for Low IQ Mode (V) TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn Typical Characteristics (continued) Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise) 1.00 0.60 EVN(SRHUisTiRn)g 0.98 0.55 EVN(SFHaUlTlFin) g 0.96 0.94 VP(GPGTTHHR)Rising VP(GPGTHHTFF) alling 0.50 0.45 0.92 PGTH Threshold Voltage (V) 0.90 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 0.40 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 Enalbe Turn ON delay tON(dly) (µs) Figure 7. PGTH Threshold Voltage vs Temperature 300 250 200 150 100 50 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 Enalbe Turn OFF Delay tOFF(dly) (µs) Figure 8. EN Threshold Voltage for Low IQ mode vs Temperature 3.0 2.6 2.2 1.8 1.4 1.0 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 OVP Disable Delay, tOVP(dly) (2s) Figure 9. Enable Turn ON Delay vs Temperature 3.0 2.6 2.2 1.8 1.4 1.0 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 DEVSLP Threshold Voltage (V) Figure 10. Enable Turn OFF Delay vs Temperature 2.1 1.9 1.7 1.5 VD(DEEVVSSLPLRP) R VD(DEEVVSLLPSFL) P F 1.3 1.1 0.9 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 Figure 11. OVP Disable Delay vs Temperature Figure 12. DEVSLP Threshold Voltage vs Temperature 10 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Typical Characteristics (continued) Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise) 1.2 11.90 Gain(dVdT) DEVSLP Pull down Current, I(DEVSLP) (µA) 11.89 11.88 1.1 11.87 11.86 11.85 1.0 11.84 11.83 0.9 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 11.82 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 Figure 13. DEVSLP Pull Down Current vs Temperature 1000 Figure 14. GAIN(dVdT) vs Temperature 10 Current Limit, I(LIM) (A) Output Ramp Time, t(dVdT) (ms) 100 10 1 1 Accuracy (%) (Process, Voltage, Temperature) 0 1 10 100 C(dVdT) (nF) 1000 C014 Figure 15. Output Ramp Time vs C(dVdT) 9.5 9.0 8.5 8.0 7.5 0 1 2 3 4 5 6 Current Limit(A) C014 Figure 17. Current Limit Accuracy vs Current Limit Current Limit, I(LIM) (A) 0 10 100 R(ILIM) Resistor (k:) C014 Figure 16. Current Limit vs Current Limit Resistor 6 16.9 k: 5 4 3 2 1 0 ±50 24.9 k: 42.4 k: 88.6 k: 150 k: 0 50 100 150 Temperature (oC) C014 Figure 18. Current Limit vs Temperature Across R(ILIM) Copyright © 2014, Texas Instruments Incorporated 11 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn Typical Characteristics (continued) Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise) 2.0% 1.5% 1.0% 0.5% 150 k 88.6 k 42.4 k 24.9 k 16.9 k 0.5% 0.0% -0.5% -1.0% II((LOIMV) =) =1.10.0AA II((LOIMV) =) =2.21.1AA II((LOIMV) =) =3.36.6AA II((LOIMV) =) =5.53.3AA I(LIM) Normalized (%) I(LIM) (% Normalized) 0.0% -0.5% -1.5% -1.0% -2.0% -1.5% -2.5% -2.0% -50 0 50 100 Temperature (oC) -3.0% 150 0 2 4 6 8 C014 V(IN) - V(OUT) (V) Thermal shutdown occurs when I(LIM) = 5.3 A and [V(IN) - V(OUT)] > 8 V 10 12 C014 Figure 19. Current Limit (% Normalized) vs R(LIMIT) Resistor 0.70 Figure 20. Current Limit Normalized (%) vs V(IN) - V(OUT) 0.70 Current Limit in DevSleep Mode, I(DEVSLP(LIM)) (A) Current Limit, I(LIM) (A) 0.65 0.60 0.55 0.50 0.45 RR(I(LILIIMM) )==SShhoortrt RR(I(LILIIMM) )==OOppeenn 0.69 0.68 0.67 0.66 0.40 ±50 0 50 100 150 Temperature (oC) C014 0.65 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 Fast Trip Current, I(FASTTRIP) (A) Figure 21. Current Limit for R(ILIM) = Open and Short vs Temperature 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 Current Limit I(LIM) (A) C014 GAIN(IMON) Normalized (%) Figure 22. Current Limit in DevSleep Mode vs Temperature 118 116 114 112 110 108 106 104 102 100 98 0.1 TA -=40-4C0oC TA 2=52C5oC TA 8=58C5oC TA 1=2152C5oC 1.0 Output Current (A) 10.0 C014 Figure 23. Fast Trip Threshold vs Current Limit Figure 24. GAIN(IMON)% Normalized vs Output Current 12 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Typical Characteristics (continued) Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise) 54.0 500 Current Monitor Output I(MON) (µA) 53.5 GAIN, I(MON) (µA/A) 53.0 52.5 50 52.0 51.5 51.0 ±50 ±20 10 40 70 Temperature (oC) 100 130 C014 5 0.1 1.0 Output Current , IOUT (A) TATA= -=4-04o0C0C TATA= 2=52o5C0C TATA= 8=58o5C0C TATA= 1=2152o5C0C 10.0 C014 RON (m:  Figure 25. GAIN(IMON) vs Temperature 60 55 50 45 40 35 30 25 ±50 0 50 100 Temperature (oC) 1A 2A 3A 4A 5A 150 C014 OUT Pin Leakage Current, Ilkg(out) (µA) Figure 26. Current Monitor Output vs Output Current 16 14 12 10 V(OvUoTu) t==00VV 8 V(O1U8TV) = 18 V 6 4 2 0 ±2 ±50 0 50 100 150 Temperature (oC) C014 V(REVTH) (mV) Figure 27. RON vs Temperature Across Load Current ±9.0 ±9.1 ±9.2 ±9.3 ±9.4 ±9.5 ±9.6 ±9.7 ±9.8 ±9.9 ±10.0 ±50 0 50 100 150 Temperature (oC) C014 V(FWDTH) (mV) Figure 28. OUT Leakage Current in Off State vs Temperature 102.0 101.5 101.0 100.5 100.0 99.5 99.0 98.5 98.0 ±50 0 50 100 150 Temperature (oC) C014 Figure 29. V(REVTH) vs Temperature Figure 30. V(FWDTH) vs Temperature Copyright © 2014, Texas Instruments Incorporated 13 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn Typical Characteristics (continued) Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise) 100000 TA -=40-4C0oC 10000 TA 2=52C5oC TA 8=58C5oC 1000 TA 1=2152C5oC Thermal Shutdown Time (ms) 100 10 1 0.1 1 10 100 Power Dissipation (W) C014 Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm2 (Top) and 20 cm2 (bottom) Figure 31. Thermal Shutdown Time vs Power Dissipation V(IN) = 4.5 V Figure 32. Turn ON with Enable V(IN) = 11 V Figure 33. Turn ON and OFF with Enable R(FLT)=100 kΩ Figure 34. EN Turn ON Delay : EN ↑ to Output Ramp ↑ R(FLT)=100 kΩ Figure 35. EN Turn OFF Delay : EN ↓ to Fault ↓ V(IN) = 12 V RL = 12 Ω R(FLT)=100 kΩ Figure 36. OVP Turn OFF delay: OVP ↑ to Fault ↓ 14 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Typical Characteristics (continued) Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise) V(IN) = 12 V RL = 12 Ω R(FLT)=100 kΩ Figure 37. OVP Turn ON delay: OVP ↓ to Output Ramp ↑ V(IN) = 12 V RL = 12 Ω R(FLT)= 100 kΩ R(PGOOD)= 100 kΩ Figure 38. Power Good Delay (Rising) V(IN) = 12 V RL = 12 Ω R(FLT)= 100 kΩ R(PGOOD)= 100 kΩ Figure 39. Power Good Delay (Falling) R(FLT) =100 kΩ R(IMON)= 16.9 kΩ Figure 40. Hot-Short: Fast Trip Response and Current Regulation R(FLT)=100 kΩ R(IMON)= 16.9 kΩ Figure 41. Hot-Short: Fast Trip Response (Zoomed) Copyright © 2014, Texas Instruments Incorporated 15 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 8 Parametric Measurement Information V(OUT) VEN 0 0.1V V(ENR)+0.1V tON(dly) time www.ti.com.cn VEN FLT 0 V(ENF)-0.1V 10% tOFF(dly) time V(IN)-V(OUT) FLT 0 -20mV tREV(dly) 10% time V(IN)-V(OUT) FLT 0 110mV 90% tFWD(dly) time I(FASTRIP) I(OUT) 0 tFASTRIP(dly) I(LIM) V(OVP) FLT time 0 Figure 42. Timing Diagrams V(OVPR) + 0.1V 10% tOVP(dly) time 16 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn 9 Detailed Description TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 9.1 Overview TPS25940 is a smart eFuse with integrated back-to-back FETs and enhanced built-in protection circuitry. It provides robust protection for all systems and applications powered from 2.7 V to 18 V. For hot-plug-in boards, the device provides hot-swap power management with in-rush current control and programmable output ramp-rate. The device integrates overcurrent and short circuit protection. The precision overcurrent limit helps to minimize over design of the input power supply, while the fast response short circuit protection immediately isolates the load from input when a short circuit is detected. The device allows the user to program the overcurrent limit threshold between 0.6 A and 5.3 A via an external resistor. The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault for downstream system. Its overall threshold accuracy of 2% ensures tight supervision of bus, eliminating the need for a separate supply voltage supervisor chip. The device is designed to protect systems such as enterprise SSD drives against sudden power loss events. The device monitors V(IN) and V(OUT) to provide true reverse blocking from output when reverse condition or input power fail condition is detected. Also, the device signals the downstream controller to initiate transfer of power to the hold-up capacitor for data hardening. The additional features include: • Precise current monitor output for health monitoring of the system • Additional power good comparator with precision internal reference for output or any other rail voltage monitoring • Over temperature protection to safely shutdown in the event of an overcurrent event • De-glitched fault reporting for brown-out and overvoltage faults • A choice of latched or automatic restart mode Copyright © 2014, Texas Instruments Incorporated 17 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 9.2 Functional Block Diagram www.ti.com.cn IN 9-13 OUT 4-8 + 2.30V 2.18V EN/UVLO 14 + 0.99V 0.92V OVP 15 + 0.99V DEVSLP 0.92V 1 + 1.85V 0.96V 1PA UVLO EN -10mV +100mV + Charge Pump CP REVERSE 42m: x52P Current Sense x OVP Thermal TSD Shutdown SWEN Gate Control Logic Current Limit Amp Low Current Mode Fast-Trip Comp EN/UVLO Shutdown 0.87V IMON 19 ILIM 17 Short Detect Ramp Control FLT 20 dVdT 18 GND 16 1uA 16: 12x SWEN UVLO S SET Q SWEN R CLR Q Fault Latch Shaded Blocks will be Turned-Off in DevSleep Mode 0.99V Gate Enhanced + TPS25940A/L 3 PGTH 0.92V Figure 43. TPS25940A/L Block Diagram 0.5ms 0.5ms 16: 16: PGOOD 2 18 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 9.3 Feature Description 9.3.1 Enable and Adjusting Undervoltage Lockout The EN/UVLO pin controls the ON/OFF state of the internal FET. A voltage V(EN/UVLO) < V(ENF) on this pin will turn off the internal FET, thus disconnecting IN from OUT, while voltage below V(SHUTF) will take the device into shutdown mode, with IQ less than 15 µA to ensure minimal power loss. Cycling EN/UVLO low and then back high resets the TPS25940L that has latched off due to a fault condition. The internal de-glitch delay on EN/UVLO falling edge is kept low for quick detection of power failure. For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO terminal to GND. The undervoltage lock out can be programmed by using an external resistor divider from supply IN terminal to EN/UVLO terminal to GND as shown in Figure 44. When an undervoltage or input power fail event is detected, the internal FET is quickly turned off, and FLT is asserted. If the Under-Voltage Lock-Out function is not needed, the EN/UVLO terminal should be connected to the IN terminal. EN/UVLO terminal should not be left floating. The device also implements internal undervoltage-lockout (UVLO) circuitry on the IN terminal. The device disables when the IN terminal voltage falls below internal UVLO Threshold V(UVF). The internal UVLO threshold has a hysteresis of 115mV. V(IN) IN TPS25940x R1 EN/UVLO + EN 0.99V R2 0.92V OVP + OVP R3 0.99V 0.92V GND Figure 44. UVLO and OVP Thresholds Set By R1, R2 and R3 9.3.2 Overvoltage Protection (OVP) The device incorporates circuit to protect system during overvoltage conditions. A resistor divider connected from the supply to OVP terminal to GND (as shown in Figure 44) programs the overvoltage threshold. A voltage more than V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. This pin should be tied to GND when not used. 9.3.3 Hot Plug-in and In-Rush Current Control The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of the system power. A slew rate controlled startup (dVdT) also helps to eliminate conductive and radiative interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output voltage at power-on (as shown in Figure 45). Equation governing slew rate at start-up is shown in Equation 1 : Copyright © 2014, Texas Instruments Incorporated 19 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Feature Description (continued) TPS25940x www.ti.com.cn dVdT C(dVdT) GND 1uA 16: SWEN Figure 45. Output Ramp Up Time tdVdT is Set by C(dVdT) I(dVdT) = æ ççè C(dVdT) GAIN(dVdT) ö ÷÷ø x æ ççè dV(OUT) dt ö ÷÷ø (1) Where: • I(dVdT) = 1 µA (typical) space dV(OUT) • dt = Desired output slew rate • GAIN(dVdT) = dVdT to OUT gain = 12 The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2: tdVdT = 8.3 x 104 x V(IN) x C(dVdT) (2) The inrush current, I(INRUSH) can be calculated as I(INRUSH) = C(OUT) x V(IN) / tdVdT. (3) The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When terminal is left floating, the device sets an internal ramp rate of 12V/ms for output (V(OUT)) ramp. Figure 58 and Figure 59 illustrate the inrush current control behavior of the device. For systems where load is present during start-up, the current never exceeds the overcurrent limit set by R(ILIM) resistor for the application. For defining appropriate charging time/rate under different load conditions, refer to the Setting Output Voltage Ramp time (tdVdT) section. 9.3.4 Overload and Short Circuit Protection : At all times load current is monitored by sensing voltage across an internal sense resistor. During overload events, current is limited to the current limit (I(LIM)) programmed by R(ILIM) resistor I(LIM) = 89 R(ILIM) (4) • I(LIM) is overload current limit in Ampere • R(ILIM) is the current limit resistor in kΩ The device incorporates two distinct levels: a current limit (I(LIM)) and a fast-trip threshold (I(FASTRIP)). Fast trip and current limit operation are shown in Figure 46. Bias current on ILIM pin directly controls current-limiting behavior of the device, and PCB routing of this node must be kept away from any noisy (switching) signals. 20 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Feature Description (continued) 9.3.4.1 Overload Protection For overload conditions, the internal current-limit amplifier regulates the output current to I(LIM). The output voltage droops during the current regulation, resulting in increased power dissipation in the device. If the device junction temperature reaches the thermal shutdown threshold (T(TSD)), the internal FET is turned off. Once in thermal shutdown, The TPS25940L version stays latched off, whereas TPS25940A commences an auto-retry cycle 128 ms after TJ < [T(TSD) - 12°C]. During thermal shutdown, the fault pin FLT pulls low to signal a fault condition. Figure 62 and Figure 63 illustrate overload behavior. 9.3.4.2 Short Circuit Protection During a transient short circuit event, the current through the device increases very rapidly. As current-limit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip comparator, with a threshold I(FASTRIP). This comparator shuts down the pass device within 1µs, when the current through internal FET exceeds I(FASTRIP) (I(OUT) > I(FASTRIP)), and terminates the rapid short-circuit peak current. The trip threshold is set to more than 50% of the programmed overload current limit ( I(FASTRIP) = 1.5 x I(LIM)+ 0.375 ). The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device turns back on slowly, allowing the current-limit loop to regulate the output current to I(LIM). Then, device behaves similar to overload condition. Figure 64 through Figure 66 illustrate the behavior of the system when the current exceeds the fast-trip threshold. 9.3.4.3 Start-Up with Short on Output During start-up into a short circuit current is limited to I(LIM). Figure 67 and Figure 68 illustrate start-up with a short on the output. This feature helps in quick fault isolation and hence ensures stability of the DC bus. 9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults When power dissipation in the internal FET [PD = (V(IN) - V(OUT)) × I(OUT)] > 10 W, there is a ~0 to 5 % thermal fold back in the current limit value so that I(LIM) drops to IOS. Eventually, the device shuts down due to over temperature. I(FASTRIP) Current Limit I(FASTRIP) = 1.5 x I(LIM) + 0.375 Thermal Foldback 0-5% I(LIM) IOS Figure 46. Fast-Trip Current 9.3.5 FAULT Response The FLT open-drain output is asserted (active low) during undervoltage, overvoltage, reverse voltage/current and thermal shutdown conditions. The FLT signal remains asserted until the fault condition is removed and the device resumes normal operation. The device is designed to eliminate false fault reporting by using an internal "deglitch" circuit for undervoltage and overvoltage (2.2-µs typical) conditions without the need for external circuitry. This ensures that fault is not accidentally asserted during transients on input bus. Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when not used. V(IN) falling below V(UVF) = 2.1 V resets FLT. Copyright © 2014, Texas Instruments Incorporated 21 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn Feature Description (continued) 9.3.6 Current Monitoring: The current source at IMON terminal is configured to be proportional to the current flowing from IN to OUT. This current can be converted to a voltage using a resistor R(IMON) from IMON terminal to GND terminal. This voltage, computed using Equation 6, can be used as a means of monitoring current flow through the system. The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(IN)- 2.2 V], 6.0 V) to ensure linear output. This puts limitation on maximum value of R(IMON) resistor and is determined by Equation 5. R(IMONmax) = minimum (V(IN) - 2.2, 6) 1.6 x I(LIM) x GAIN(IMON) (5) The output voltage at IMON terminal is calculated from Equation 6 V(IMON) = I(OUT) x GAIN(IMON) x R(IMON) (6) Where • GAIN(IMON) = Gain factor I(IMON):I(OUT) = 52 µA/A • I(OUT) = Load current This pin should not have a bypass capacitor to avoid delay in the current monitoring information. The voltage at IMON pin can be digitized using an ADC (such as ADS1100, SBAS239) to read the current monitor information over an I2C bus. 9.3.7 Power Good Comparator The device incorporates a Power Good comparator for co-ordination of status to downstream DC-DC converters or system monitoring circuits. The comparator has an internal reference of V(PGTHR) = 0.99 V at negative terminal and positive terminal PGTH can be utilized for monitoring of either input or output of the device. The comparator output PGOOD is an open-drain active high signal, which can be used to indicate the status to downstream units. PGOOD is asserted high when internal FET is fully enhanced and PGTH pin voltage is higher than internal reference V(PGTHR). The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy load is applied by downstream converters. Rising de-glitch delay is determined by Equation 7. tPGOOD(degl) = Maximum{(3.5 x 106 x C(dVdT)), tPGOODR} (7) Connect the PGOOD pin with a pull up resistor to Input or Output voltage rail. PGOOD may be left open or tied to ground when not used. 9.3.8 IN, OUT and GND Pins The device has multiple pins for input (IN) and output (OUT). All IN pins should be connected together and to the power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is 2.7 V – 18 V. Similarly all OUT pins should be connected together and to the load. V(OUT) in the ON condition, is calculated using the Equation 8 V(OUT) = V(IN) - (RON × I(OUT)) (8) where, RON is the total ON resistance of the internal FET. GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference unless otherwise specified. 9.3.9 Thermal Shutdown: Internal over temperature shutdown disables turns off the FET when TJ > 160°C (typical). The TPS25940L version latches off the internal FET, whereas TPS25940A commences an auto-retry cycle128 ms after TJ drops below [T(TSD) - 12°C]. During the thermal shutdown, the fault pin FLT pulls low to signal a fault condition. 22 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 9.4 Device Functional Modes 9.4.1 DevSleep Mode for SATA® Interface Devices DevSleep is a new state introduced in the SATA® specification, which requires SATA-based storage solutions to reach a level of low power operation. This is appended to meet the aggressive power/battery life requirements of SATA-based mobile devices. DevSleep enables hosts and devices to completely hibernate the SATA interface. This saves more power versus the existing Partial and Slumber interface power states, which require that the PHY be left powered. In this mode, power consumption is limited to 5 mW or less for SSDs. Detailed information on DevSleep is available in document 'SATA-DevSleep' and on www.sata-io.org TPS25940 provides a dedicated DevSleep interface terminal (DEVSLP) to drive the device in low power mode. The DEVSLP terminal is compatible with standard hardware signals asserted from the host controller. When pulled high, it puts the device in low power DevSleep mode. In this mode, the quiescent current consumption of the device is limited to less than 130 µA (95 µA typical). During this mode, the output voltage remains active, the overload current limit is set to I(DEVSLP(LIM)) and functionality of reverse comparator and current monitoring is disabled. All other protections are kept active ensuring the safety of the system even in DevSleep mode. User must ensure that load currents on the bus are limited to less than I(DEVSLP(LIM)), when the device is driven to DevSleep mode. Also, while coming out of DevSleep, it is important to sequence the TPS25940 earlier than the load. Otherwise, the load can exceed I(DEVSLP(LIM)) and cause TPS25940 to enter the overload mode. Figure 47 through Figure 50 illustrate the behavior of the system in DevSleep mode. V(IN) = 12 V C(OUT) = 1 µF l(LIM) = 5.3A RL = 22Ω Figure 47. IN and OUT of DevSleep Mode with 550mA Load V(IN) = 12 V C(OUT) = 1 µF l(LIM) = 5.3A RL = 15Ω Figure 48. IN and OUT of DevSleep Mode with 800mA Load. In DevSleep, load current gets limited to I(DEVSLP(LIM)) Copyright © 2014, Texas Instruments Incorporated 23 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Device Functional Modes (continued) www.ti.com.cn RL = 22Ω l(LIM) = 5.3A C(OUT) = 1 µF l(LIM–) = 5.3A C(OUT) = 1 µF Figure 49. IMON Disabled in DevSleep Mode Figure 50. Hot Short and Retry in DevSleep Mode 9.4.2 Shutdown Control The internal FET and hence the load current can be remotely switched off by taking the UVLO pin below its 0.6 V threshold with an open collector or open drain device as shown in Figure 51. The device quiescent current is reduced to less than 20 µA in this state. Upon releasing the UVLO pin the device turns on with soft-start cycle. V(IN) IN TPS25940x from µC R1 EN/UVLO + EN 0.99V R2 0.92V GND Figure 51. Shutdown Control 24 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 10 Application and Implementation 10.1 Application Information The TPS25940 is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It operates from 2.7 V to 18 V with programmable current limit, overvoltage and undervoltage protection. The device aids in controlling the in-rush current and provides fast turn-off during reverse voltage conditions for systems such as Enterprise SSDs, HDDs, Servers, Power Back-up Storage units and RAID cards. The device also provides robust protection for multiple faults on the sub-system rail. The following design procedure can be used to select component values for the device. Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. Additionally, a spreadsheet design tool TPS25940 Design Calculator is available on web folder. This section presents a simplified discussion of the design process. 10.2 Typical Application 10.2.1 eFuse for Enterprise SSDs IN 2.7 to 18 V R1 475kO CIN 0.1µF (See Note A) R2 16.7kO from µC R3 CdVdT 31.2kO 1.5nF IN OUT 42mO R6 EN/UVLO OVP FLT PGOOD DEVSLP PGTH dVdT GND IMON ILIM RILIM TPS25940x 17.8kO OUT R4 475kO R7 COUT 100µF Health Monitor Load Monitor R5 47kO RIMON 19.1kO A. CIN: Optional and only for noise suppression. Figure 52. Typical Application Schematics: eFuse for Enterprise SSDs 10.2.1.1 Design Requirements Table 1. Design Parameters DESIGN PARAMETER Input voltage range, V(IN) Undervoltage lockout set point, V(UV) Overvoltage protection set point , V(LIM) Load at Start-Up , RL(SU) Current limit, I(LIM) Load capacitance , C(OUT) Maximum ambient temperatures , TA EXAMPLE VALUE 12 V 10.8 V 16.5 V 4.8 Ω 5A 100 µF 85°C Copyright © 2014, Texas Instruments Incorporated 25 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn 10.2.1.2 Detailed Design Procedure The following design procedure can be used to select component values for the TPS25940A and TPS25940L. 10.2.1.2.1 Step by Step Design Procedure To begin the design process a few parameters must be decided upon. The designer needs to know the following: • Normal input operation voltage • Maximum output capacitance • Maximum current Limit • Load during start-up • Maximum ambient temperature of operation This design procedure below seeks to control the junction temperature of device under both static and transient conditions by proper selection of output ramp-up time and associated support components. The designer can adjust this procedure to fit the application and design criteria. 10.2.1.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4. R(ILIM) = 89 5 = 17.8kW (9) Choose closest standard value: 17.8k, 1% standard value resistor. 10.2.1.2.3 Undervoltage Lockout and Overvoltage Set Point The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider network of R1, R2 and R3 as connected between IN, EN, OVP and GND pins of the device. The values required for setting the undervoltage and overvoltage are calculated solving Equation 10 and Equation 11. V(OVPR) = R1 + R3 R2 + R3 x V(OV) (10) V(ENR) = R2 + R3 R1 + R2 + R3 x V(UV) (11) For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1 + R2 + R3)}, it is recommended to use higher values of resistance for R1, R2 and R3. However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage current expected. From the device electrical specifications, V(OVPR) = 0.99 V and V(ENR) = 0.99 V. For design requirements, V(OV) is 16.5 V and V(UV) is 10.8 V. To solve the equation, first choose the value of R3 = 31.2 kΩ and use Equation 10 to solve for (R1 + R2) = 488.8 kΩ. Use Equation 11 and value of (R1 + R2) to solve for R2 = 16.47 kΩ and finally R1= 472.33 kΩ. Using the closest standard 1% resistor values gives R1 = 475 kΩ, R2 = 16.7 kΩ, and R3 = 31.2 kΩ. The power failure threshold is detected on the falling edge of supply. This threshold voltage is 7% lower than the rising threshold, V(UV). This is calculated using Equation 12. V(PFAIL) = 0.93 x V(UV) (12) 10.2.1.2.4 Programming Current Monitoring Resistor - RIMON Voltage at IMON pin V(IMON) represents the voltage proportional to load current. This can be connected to an ADC of the downstream system for health monitoring of the system. The R(IMON) need to be configured based on the maximum input voltage range of the ADC used. R(IMON) is set using Equation 13. R(IMON) = V(IMONmax) I(LIM) x 52 x 10-6 kW (13) For I(LIM) = 5 A, and considering the operating range of ADC from 0 V to 5 V, V(IMONmax) is 5 V and R(IMON) is determined by: 26 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 R(IMON) = 5 x 5 52 x 10-6 = 19.23 kW (14) Selecting R(IMON) value less than determined by Equation 14 ensures that ADC limits are not exceeded for maximum value of load current. If the IMON pin voltage is not being digitized with an ADC, R(IMON) can be selected to produce a 1V/1A voltage at the IMON pin, using Equation 13. Choose closest 1 % standard value: 19.1 kΩ. If current monitoring up to I(FASTRIP) is desired, R(IMON) can be reduced by a factor of 1.6, as in Equation 5. 10.2.1.2.5 Setting Output Voltage Ramp time (tdVdT) For a successful design, the junction temperature of device should be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load. The ramp-up capacitor C(dVdT) needed is calculated considering the two possible cases: 10.2.1.2.5.1 Case1: Start-up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-up During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and the power dissipated decreases as well. Typical ramp-up of output voltage V(OUT) with inrush current limit of 1.2A and power dissipated in the device during start-up is shown in Figure 53. The average power dissipated in the device during start-up is equal to area of triangular plot (red curve in Figure 54) averaged over tdVdT. V(IN) = 12 V C(dVdT) = 1 nF C(OUT)=100 µF Figure 53. Start-up Without Load Input Current (A), Power Dissipation (W) Output Voltage (V) 16 Input Current (A) 16 14 Power Dissioation (W) 14 Output Voltage (V) 12 12 10 10 8 8 6 6 4 4 2 2 0 0 V(IN) = 12 V 0 20 40 60 80 100 Start-Up Time, tdVdt (%) C(dVdT) = 1 nF C013 C(OUT)=100 µF Figure 54. PD(INRUSH) Due to Inrush Current For TPS25940 device, the inrush current is determined as, I=C x dV dT => I(INRUSH) = C(OUT) x V(IN) tdVdT (15) Power dissipation during start-up is: PD(INRUSH) = 0.5 x V(IN) x I(INRUSH) (16) Equation 16 assumes that load does not draw any current until the output voltage has reached its final value. 10.2.1.2.5.2 Case 2: Start-up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-up When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a resistive load RL(SU) during start-up, load current ramps up proportionally with increase in output voltage during tdVdT time. Typical ramp-up of output voltage, Load current and power dissipation in the device is shown in Figure 55 and power dissipation with respect to time is plotted in Figure 56. The additional power dissipation during start-up phase is calculated as follows. Copyright © 2014, Texas Instruments Incorporated 27 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn (VI - VO )(t) = V(IN) x çæçççè1- t tdVdT öø÷÷÷÷ IL (t) = æçççççèRVL((ISNU) ) ÷÷÷÷÷öø x t tdVdT (17) (18) Where RL(SU) is the load resistance present during start-up. Average energy loss in the internal FET during charging time due to resistive load is given by: ò Wt = tdVdT 0 V(IN) x èççççæ1 - t tdVdT ÷ø÷÷÷ö x çèççççæRVL((ISNU) ) x t tdVdT ø÷÷÷÷÷ödt (19) V(IN) = 12 V C(dVdT) = 1 nF RL(SU) = 4.8 Ω Figure 55. Start-up With Load Load Current (A), Power Dissipation (W) Output Voltage (V) 14 14 Output Voltage (V) 12 Power Dissipoation (W) 12 Load Current (A) 10 10 8 8 6 6 4 4 2 2 0 0 V(IN) = 12 V 0 20 40 60 80 100 Start-Up Time, tdVdT (%) C013 C(dVdT) = 1 nF RL(SU) = 4.8 Ω Figure 56. PD(LOAD) in Load During Start-up On solving Equation 19 the average power loss in the internal FET due to load is: PD(LOAD) = æçççè 61 ö÷ø÷÷ x V 2 (IN) RL(SU) (20) Total power dissipated in the device during startup is: PD(STARTUP) = PD(INRUSH) + PD(LOAD) (21) Total current during startup is given by: I(STARTUP) = I(INRUSH) + IL(t) (22) If I(STARTUP) > I(LIM), the device limits the current to I(LIM) and the current limited charging time is determined by: tdVdT(current limited) = C(OUT) x V(IN) I(LIM) (23) The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as shown in Figure 57. 28 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Thermal Shutdown Time (ms) 100000 10000 1000 100 TA -=40-4C0oC TA 2=52C5oC TA 8=58C5oC TA 1=2152C5oC 10 1 0.1 1 10 100 Power Dissipation (W) C014 Figure 57. Thermal Shutdown Limit Plot For the design example under discussion, Select ramp-up capacitor C(dVdT) = 1nF, using Equation 2. tdvdt = 8.3 x 104 x 12 x 1 x 10-9 = 0.996ms = : 1ms (24) The inrush current drawn by the load capacitance (C(OUT)) during ramp-up using Equation 3. ( ) I(INRUSH) = 100 x 10-6 x æçççèç1 12 x 10-3 ÷÷÷÷öø = 1.2 A (25) The inrush Power dissipation is calculated, using Equation 16. PD(INRUSH) = 0.5 x 12 x 1.2 = 7.2 W (26) For 7.2 W of power loss, the thermal shut down time of the device should not be less than the ramp-up time tdVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 57 at TA = 85°C, for 7.2 W of power the shutdown time is ~60 ms. So it is safe to use 1 ms as start-up time without any load on output. Considering the start-up with load 4.8 Ω, the additional power dissipation, when load is present during start up is calculated, using Equation 20. PD(LOAD) = æçççè 61 ö÷ø÷÷ x 12 x 12 4.8 =5W (27) The total device power dissipation during start up is: PD(STARTUP) = (7.2 + 5) = 12.2 W (28) From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 12.2 W is close to 7.5 ms. It is safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 4.8 Ω. If there is a need to decrease the power loss during start-up, it can be done with increase of C(dVdT) capacitor. To illustrate, choose C(dVdT) = 1.5 nF as an option and recalculate: tdvdt = 1.5ms (29) ( ) I(INRUSH) = 100 x 10-6 x çæçççè1.5 12 x 10-3 ÷÷÷÷öø = 0.8 A (30) PD(INRUSH) = 0.5 x 12x 0.8 = 4.8 W (31) PD(LOAD) = æçççè61÷÷÷öø x æèççç124x.812÷÷÷öø = 5 W (32) PD(STARTUP) = 4.8 + 5 = 9.8 W (33) Copyright © 2014, Texas Instruments Incorporated 29 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn From thermal shutdown limit graph at TA = 85°C, the shutdown time for 10 W power dissipation is ~17 ms, which increases the margins further for shutdown time and ensures successful operation during start up and steady state conditions. The spreadsheet tool available on the web can be used for iterative calculations. 10.2.1.2.6 Programing the Power Good Set Point As shown in Figure 52, R4 and R5 sets the required limit for PGOOD signal as needed for the downstream converters. Considering a power good threshold of 11 V for this design, the values of R4 and R5 are calculated using Equation 34. V(PGTH) = 0.99 x çæçççè1 + R4 R5 ÷÷÷÷öø (34) It is recommended to have high values for these resistors to limit the current drawn from the output node. Choosing a value of R4 = 475 kΩ, R5 = 47 kΩ provides V(PGTH) = 11 V. 10.2.1.2.7 Support Component Selections - R6, R7 and CIN Reference to application schematics, R6 and R7 are required only if PGOOD and FLT are used; these resistors serve as pull-ups for the open-drain output drivers. The current sunk by each of these pins should not exceed 10 mA (refer to the Absolute Maximum Ratings table). CIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for C(IN). 10.2.1.3 Application Curves Figure 58. Hot-Plug Start-Up: Output Ramp Without Load on output Figure 59. Hot-Plug Start-Up: Output Ramp With Start-up load of 4.8Ω 30 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Figure 60. Overvoltage Shutdown IMON Figure 61. Overvoltage Recovery IMON Figure 62. Over Load: Step Change in Load from 12Ω to 2Ω and Back Figure 63. Overload Condition: Auto Retry and Recovery TPS25940A Figure 64. Hot Short: Fast Trip and Current Regulation Figure 65. Hot Short: Latched - TPS25940L Copyright © 2014, Texas Instruments Incorporated 31 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 www.ti.com.cn Figure 66. Hot Short: Auto-Retry and Recovery from Short Circuit - TPS25940A Figure 67. Hot Plug-in with Short on Output: Latched TPS25940L Figure 68. Hot Plug-in with Short on Output: Auto-Retry TPS25940A Figure 69. Power Good Response During Turn-ON Figure 70. Power Good Response During Turn-OFF 32 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 10.3 System Examples 10.3.1 Power Failure Protection and Data Retention in SSDs For enterprise and Industrial SSDs, it is necessary to have hold-up circuit and capacitor bank to ensure that critical user data is never lost during power-failure to the drive. The power-failure event could be due to momentary loss of power regulation (transient brown-out condition) or due to loss of power when drive is hotplugged out. The TPS25940 continuously monitors the supply voltage at EN/UVLO pin and swiftly disconnects the input bus from output when the voltage drops below a predefined threshold (power fail detection). The TPS25940 also monitors the reverse voltage from IN to OUT and when it exceeds -10 mV, it stops the flow of reverse current. In addition, it provides an instant warning signal (FLT) to the SSD controller to initiate the data hardening process. Its swift true reverse blocking feature reacts in 1 µs (typical) ensuring that the capacitor bank charge is retained. This helps the drive to have power for longer time to harden data and reduces the capacitance required in the hold-up bank, saving system cost. The typical application diagram and application schematic of TPS25940 usage for enterprise SSD are shown in Figure 71 and Figure 72 3V3 or 5V or 12V Inrush Current Control / Soft start TPS25940 Power FET Isolation during Power Failure EN Power Failure Detection (Voltage monitor & Reset Circuit) FLT (PFAIL) To SSD PGOOD Controller Hold Up Capacitor Bank Voltage Regulators SSD Controllers NAND Flash Figure 71. Power Circuit Block Diagram of Enterprise and Industrial SSDs 2.7 to 18 V IN R1 CIN (See Note A) R2 R3 CdVdT IN OUT 42mO EN/UVLO OVP DEVSLP dVdT GND FLT PGOOD PGTH IMON ILIM TPS25940x R6 RILIM OUT COUT R4 R7 Power Good Load Monitor R5 RIMON System Load Hold Up Capacitor Bank A. CIN: Optional and only for noise suppression. Figure 72. Enterprise SSD – Holdup Capacitor Implementation using TPS25940 The oscilloscope plots demonstrating the true reverse blocking, fast turn-off and FLT signal delay are shown in Figure 73 through Figure 75. Copyright © 2014, Texas Instruments Incorporated 33 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 System Examples (continued) www.ti.com.cn V(IN) = 12V C(OUT) = 1500 µF RL = 5.6 Ω Figure 73. Hot-Plug Out Condition V(IN) = 12V C(OUT) = 1500 µF RL = 5.6 Ω Figure 74. Hot-Plug Out Condition: FLT Delay V(IN) = 12V C(OUT) = 1500 µF RL = 5.6 Ω Figure 75. Standard Power Shutdown or Brownout Conditions 10.3.2 Boost Power Rail Configuration for Data Retention in Enterprise SSDs In certain enterprise SSD architectures, the hold-up capacitor voltage is boosted to value higher than the input bus voltage to optimize the storage capacitor bank. A typical boosted hold-up voltage ranges from 12 V to 18 V. A typical power circuit block diagram is shown in Figure 76. For these applications, TPS25940 provides quick and smooth changeover of the power from main input bus to boosted backup voltage. 34 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn System Examples (continued) TPS25940 3V3 or 5V or 12V Inrush Current Control Power FET Isolation / Soft start during Power Failure switchover signal FLT OVP EN Power Failure FLT (PFAIL) Detection PGOOD To SSD Controller EN Boost (Voltage monitor and Reset Circuit) Converter TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Voltage Regulators SSD Controllers NAND Flash Power FET Isolation VBOOST / 18V Hold Up Capacitor Bank TPS25940 Figure 76. Power Circuit Block Diagram with Boosted Backup Power for Enterprise SSD A typical application schematic for implementation of boosted backup power configuration is shown in Figure 77. During startup TPS25940 provides the inrush current control to charge up the C(BUS) as well as C(HOLDUP) close to V(IN). Once V(BUS) reaches the programmed PGOOD threshold, the boost converter is enabled to charge C(HOLDUP) to V(BOOST). When V(IN) fails, TPS25940 detects power failure and asserts the fault signal (FLT), which in turn disables the boost converter and shorts V(BOOST) to V(BUS), through M1. The FLT signal can be interfaced to SSD controller to initiate the data hardening process. If current limit protection is desired during data hardening process (when holdup capacitor is supplying system bus), M1 can be replaced by another TPS25940. The oscilloscope plot demonstrating change over from Main (12 V) to Boosted backup power (14.5 V) is shown in Figure 78. 2.7 to 18 V IN R1 CIN (See Note A) R2 R3 CdVdT IN OUT OUT VBUS 42mO EN/UVLO OVP DEVSLP dVdT GND FLT PGOOD PGTH IMON ILIM TPS25940x R6 RILIM CBUS R4 R7 Load Monitor R5 RIMON Boost Converter EN M1 R8 DC/DC : System Load VBOOST R9 CHOLDUP VBOOST ^ 18V A. CIN: Optional and only for noise suppression. Figure 77. Enterprise SSDs: Boosted Backup Power Multiplexing Circuit Implementation Copyright © 2014, Texas Instruments Incorporated 35 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 System Examples (continued) www.ti.com.cn V(IN) = 12 V V(BOOST) = 14.5 V C(BUS) = 150 µF P(LOAD) = 12.5 W V(IN-UVLO-low) = 10.2 V C(dVdT) = 1 nF Figure 78. Brownout (Power Fail) Condition: Switch over to Boosted Backup Power 11 Power Supply Recommendations The TPS25940 device is designed for supply voltage range of 2.7 V ≤ VIN ≤ 18 V. If the input supply is located more than a few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power supply should be rated higher than the current limit set to avoid voltage droops during over current and short-circuit conditions. 11.1 Transient Protection In case of short circuit and over load current limit, when the device interrupts current flow, input inductance generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients include • Minimizing lead length and inductance into and out of the device • Using large PCB GND plane • Schottky diode across the output to absorb negative spikes • A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with Equation 35. VSPIKE(Absolute) = V(IN) x I(LOAD) x L(IN) C(IN) (35) Where: • V(IN) is the nominal supply voltage • I(LOAD) is the load current, • L(IN) equals the effective inductance seen looking into the source • C(IN) is the capacitance present at the input 36 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Transient Protection (continued) Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from exceeding the Absolute Maximum Ratings of the device. The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is shown in Figure 79. IN 2.7 to 18 V R1 CIN (See Note A) (See Note A) R2 R3 CdVdT IN OUT OUT 42mO EN/UVLO OVP DEVSLP dVdT GND FLT PGOOD PGTH IMON ILIM TPS25940x R6 RILIM R4 R7 R5 RIMON COUT (See Note A) A. Optional components needed for suppression of transients Figure 79. Circuit Implementation With Optional Protection Components 11.2 Output Short-Circuit Measurements It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short, and instrumentation all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do not expect to see waveforms exactly like those in the data sheet; every setup differs. Copyright © 2014, Texas Instruments Incorporated 37 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 12 Layout www.ti.com.cn 12.1 Layout Guidelines • For all applications, a 0.1-uF or greater ceramic decoupling capacitor is recommended between IN terminal and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be eliminated/minimized. • The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC. See Figure 80 for a PCB layout example. • High current carrying power path connections should be as short as possible and should be sized to carry at least twice the full-load current. • Low current signal ground (SGND), which is the reference ground for the device should be a copper plane or island. • Locate all TPS25940 support components: R(ILIM), CdVdT, R(IMON), and resistors for UVLO and OVP, close to their connection pin. Connect the other end of the component to the SGND with shortest trace length. • The trace routing for the RILIM and R(IMON) components to the device should be as short as possible to reduce parasitic effects on the current limit and current monitoring accuracy. These traces should not have any coupling to switching signals on the board. • The SGND plane must be connected to high current ground (main power ground) at a single point, that is at the negative terminal of input capacitor • Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the device they are intended to protect, and routed with short traces to reduce inductance. For example, a protection Schottky diode is recommended to address negative transients due to switching of inductive loads, and it should be physically close to the OUT pins. • Thermal Considerations: When properly mounted the PowerPAD™ package provides significantly greater cooling ability than an ordinary package. To operate at rated power, the PowerPAD must be soldered directly to the board GND plane directly under the device. The PowerPAD is at GND potential and can be connected using multiple vias to inner layer GND. Other planes, such as the bottom side of the circuit board can be used to increase heat sinking in higher current applications. Refer to Technical Briefs: PowerPad™ Thermally Enhanced Package (TI literature Number SLMA002) and PowerPAD™ Made Easy (TI Literature Number SLMA004) or more information on using this PowerPAD™ package • The thermal via land pattern specific to TPS25940 can be downloaded from device webpage • Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been shown to produce good results and is intended as a guideline. 38 Copyright © 2014, Texas Instruments Incorporated www.ti.com.cn 12.2 Layout Example Top layer Top layer signal ground plane Bottom layer signal ground plane Via to signal ground plane TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 Power Ground Input VI High Frequency Bypass Capacitor IN 11 IN 12 IN 13 EN 14 OVP 15 GND 16 OUT 7 OUT 8 IN 9 IN 10 (See Note A) 6 OUT 5 OUT 4 OUT 3 PGTH 2 PGOOD 1 DEVSLP Output VO 20 FLT 19 IMON 18 dVdT 17 ILIM Signal Ground Top Layer A. Optional: Needed only to suppress the transients caused by inductive load switching Figure 80. Board Layout Signal Ground Bottom layer Copyright © 2014, Texas Instruments Incorporated 39 TPS25940A, TPS25940L ZHCSCK2 – JUNE 2014 13 器件和文档支持 www.ti.com.cn 13.1 相关链接 以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件,并且可以快速访问样片或购买 链接。 部件 TPS25940A TPS25940L 产品文件夹 请单击此处 请单击此处 Table 2. 相关链接 样片与购买 请单击此处 请单击此处 技术文档 请单击此处 请单击此处 工具与软件 请单击此处 请单击此处 支持与社区 请单击此处 请单击此处 13.2 Trademarks DevSleep, SATA are trademarks of The Serial ATA International Organization (SATA-IO). All other trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. 14 机械封装和可订购信息 以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对 本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。 40 Copyright © 2014, Texas Instruments Incorporated RVC0020A PACKAGE OUTLINE WQFN - 0.8 mm max height WQFN 1 6 0,20 Nominal 2,50 0,50 1,50 16 11 Exposed Thermal Pad 4219150/A 07/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com RVC0020A EXAMPLE BOARD LAYOUT WQFN - 0.8 mm max height WQFN 16 11 NOTES: (continued) 4219150/A 07/2014 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271) . www.ti.com RVC0020A 16 EXAMPLE STENCIL DESIGN WQFN - 0.8 mm max height WQFN 11 NOTES: (continued) 4219150/A 07/2014 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 19-Feb-2015 PACKAGING INFORMATION Orderable Device TPS25940ARVCR TPS25940ARVCT TPS25940EVM-637 TPS25940EVM-638 TPS25940LRVCR TPS25940LRVCT TPS25940XEVM-635 Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) ACTIVE WQFN RVC 20 3000 Green (RoHS & no Sb/Br) ACTIVE WQFN RVC 20 250 Green (RoHS & no Sb/Br) PREVIEW 0 1 TBD PREVIEW 0 1 TBD ACTIVE WQFN RVC 20 3000 Green (RoHS & no Sb/Br) ACTIVE WQFN RVC 20 250 Green (RoHS & no Sb/Br) PREVIEW 0 1 TBD Lead/Ball Finish (6) CU NIPDAU CU NIPDAU Call TI Call TI CU NIPDAU CU NIPDAU Call TI MSL Peak Temp Op Temp (°C) (3) Level-2-260C-1 YEAR -40 to 85 Level-2-260C-1 YEAR -40 to 85 Call TI Call TI Level-2-260C-1 YEAR -40 to 85 Level-2-260C-1 YEAR -40 to 85 Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Device Marking (4/5) 25940A 25940A 25940L 25940L (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Feb-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 重要声明 德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改, 并有权根据 JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售 都遵循在订单确认时所提供的TI 销售条款与条件。 TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内,且 TI 认为 有必要时才会使 用测试或其它质量控制技术。除非适用法律做出了硬性规定,否则没有必要对每种组件的所有参数进行测试。 TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险, 客户应提供充分的设计与操作安全措施。 TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权 限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息,不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用 此类信息可能需要获得第三方的专利权或其它知识产权方面的许可,或是 TI 的专利权或其它 知识产权方面的许可。 对于 TI 的产品手册或数据表中 TI 信息的重要部分,仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行 复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。 在转售 TI 组件或服务时,如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分,则会失去相关 TI 组件 或服务的所有明 示或暗示授权,且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。 客户认可并同意,尽管任何应用相关信息或支持仍可能由 TI 提供,但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法 律、法规和安全相关要求。客户声明并同意,他们具备制定与实施安全措施所需的全部专业技术和知识,可预见 故障的危险后果、监测故障 及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而 对 TI 及其代理造成的任何损失。 在某些场合中,为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用 的功能安全性标准和要求的终端产品解决方案。尽管如此,此类组件仍然服从这些条款。 TI 组件未获得用于 FDA Class III(或类似的生命攸关医疗设备)的授权许可,除非各方授权官员已经达成了专门管控此类使 用的特别协议。 只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意,对并非指定面 向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用,其风险由客户单独承担,并且由客户独 力负责满足与此类使用相关的所有 法律和法规要求。 TI 已明确指定符合 ISO/TS16949 要求的产品,这些产品主要用于汽车。在任何情况下,因使用非指定产品而无法达到 ISO/TS16949 要 求,TI不承担任何责任。 数字音频 放大器和线性器件 数据转换器 DLP® 产品 DSP - 数字信号处理器 时钟和计时器 接口 逻辑 电源管理 微控制器 (MCU) RFID 系统 OMAP应用处理器 无线连通性 产品 www.ti.com.cn/audio www.ti.com.cn/amplifiers www.ti.com.cn/dataconverters www.dlp.com www.ti.com.cn/dsp www.ti.com.cn/clockandtimers www.ti.com.cn/interface www.ti.com.cn/logic www.ti.com.cn/power www.ti.com.cn/microcontrollers www.ti.com.cn/rfidsys www.ti.com/omap www.ti.com.cn/wirelessconnectivity 通信与电信 计算机及周边 消费电子 能源 工业应用 医疗电子 安防应用 汽车电子 视频和影像 应用 www.ti.com.cn/telecom www.ti.com.cn/computer www.ti.com/consumer-apps www.ti.com/energy www.ti.com.cn/industrial www.ti.com.cn/medical www.ti.com.cn/security www.ti.com.cn/automotive www.ti.com.cn/video 德州仪器在线技术支持社区 www.deyisupport.com IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated

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