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MT6572 HSPA Smartphone Application Processor Technical Brief Version: 1.0 Release date: 2013-01-02 © 2011 - 2013 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Specifications are subject to change without notice. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA Smartphone Application Processor Technical Brief V1.0 Confidential A Document Revision History Revision 1.0 Date 2013-01-02 Author SY Jan First release Description MediaTek Confidential © 2013 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 2 of 64 loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA Smartphone Application Processor Technical Brief V1.0 Confidential A Table of Contents Document Revision History .................................................................................... 2 Table of Contents ..................................................................................................... 3 Preface ...................................................................................................................... 5 1 System Overview ................................................................................................ 6 1.1 Platform Features ................................................................................................................... 7 1.2 MODEM Features ................................................................................................................... 9 1.3 Connectivity Features ........................................................................................................... 10 1.4 Multimedia Features ............................................................................................................. 11 1.5 General Description .............................................................................................................. 13 2 Product Description.......................................................................................... 15 2.1 Pin Description...................................................................................................................... 15 2.2 Electrical Characteristic ........................................................................................................ 34 2.3 EMI Timing Diagram ............................................................................................................. 36 2.4 System Configuration ........................................................................................................... 40 2.5 Power-on Sequence ............................................................................................................. 41 2.6 Analog Baseband ................................................................................................................. 43 2.7 Package Information............................................................................................................. 62 2.8 Ordering Information............................................................................................................. 64 Lists of Tables and Figures Table 1. Pin coordinate (use LPDDR1) ................................................................................................. 16 Table 2. Acronym for pin type ............................................................................................................... 24 Table 3. Detailed pin description (use LPDDR1) .................................................................................. 24 Table 4. Absolute maximum ratings for power supply........................................................................... 34 Table 5. Recommended operating conditions for power supply ........................................................... 34 Table 6. EMI clock timing parameters ................................................................................................... 36 Table 7. EMI LPDDR1 timing parameters ............................................................................................. 37 Table 8. EMI LPDDR2 timing parameters ............................................................................................. 38 Table 9 Mode selection ......................................................................................................................... 40 Table 10 Constant tied pins................................................................................................................... 40 Table 11. Baseband downlink specifications ......................................................................................... 44 Table 12. Baseband uplink transmitter specifications ........................................................................... 46 Table 13. APC-DAC specifications ........................................................................................................ 47 Table 14. VBIAS-DAC specifications .................................................................................................... 48 Table 15. Definitions of AUXADC channels .......................................................................................... 49 MediaTek Confidential © 2013 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 3 of 64 loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA Smartphone Application Processor Technical Brief V1.0 Confidential A Table 16. AUXADC specifications ......................................................................................................... 50 Table 17. Clock squarer 1 & 2 specifications ........................................................................................ 51 Table 18. MT6572 PLL list..................................................................................................................... 52 Table 19. ARMPLL specifications .......................................................................................................... 52 Table 20. MAINPLL specifications......................................................................................................... 53 Table 21. UNIVPLL specifications ......................................................................................................... 53 Table 22. MDPLL specifications ............................................................................................................ 53 Table 23. WPLL specifications .............................................................................................................. 54 Table 24. WHPLL specifications............................................................................................................ 54 Table 25. MCUPLL1 specifications ....................................................................................................... 55 Table 26. BTPLL specifications ............................................................................................................. 55 Table 27. WFPLL specifications ............................................................................................................ 56 Table 28. Temperature sensor specifications ........................................................................................ 57 Table 29. Wi -Fi/BT receiver specifications ........................................................................................... 58 Table 30. Wi-Fi/BT transmitter specifications ........................................................................................ 59 Table 31 . GPS receiver specifications ................................................................................................. 60 Table 32 Thermal operating specifications............................................................................................ 62 Figure 1. Block diagram of MT6572 ...................................................................................................... 14 Figure 2. Ball map view for LPDDR1 .................................................................................................... 15 Figure 3. Ball map view for LPDDR2 .................................................................................................... 16 Figure 4. EMI clock EDCLKx and EDCLKx_B ...................................................................................... 36 Figure 5. Differential signals of EMI clock ............................................................................................. 36 Figure 6. EMI LPDDR1 write timing ...................................................................................................... 37 Figure 7 . EMI LPDDR1 Read timing .................................................................................................... 37 Figure 8. EMI LPDDR2 write timing ...................................................................................................... 38 Figure 9. EMI LPDDR2 read timing ...................................................................................................... 38 Figure 10. Power on/off sequence with XTAL ....................................................................................... 41 Figure 11. Power on/off sequence without XTAL .................................................................................. 42 Figure 12. Block diagram of BBRX-ADC .............................................................................................. 44 Figure 13. Block diagram of APC-DAC ................................................................................................. 47 Figure 14. Block diagram of VBIAS-DAC.............................................................................................. 48 Figure 15. Block diagram of AUXADC .................................................................................................. 49 Figure 16. Wi-Fi/BT receiver analog based-band ................................................................................. 58 Figure 17. Wi -Fi/BT transmitter analog based-band ............................................................................ 59 Figure 18. GPS receiver analog based-band........................................................................................ 60 Figure 19 Outlines and dimensions of TFBGA 10.6mm*10.6mm, 428-ball, 0.4mm pitch package...... 62 Figure 20. Top mark of MT6572 ............................................................................................................ 64 MediaTek Confidential © 2013 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 4 of 64 loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA Smartphone Application Processor Technical Brief V1.0 Confidential A Preface Acronyms for register types R/W RO RC WO W1S W1C For both read and write access Read only Read only. After the register bank is read, every bit that is HIGH(1) will be cleared to LOW(0) automatically. Write only Write only. When data bits are written to the register bank, every bit that is HIGH(1) will cause the corresponding bit to be set to 1. Data bits that are LOW(0) have no effects on the corresponding bit. Write only. When data bits are written to the register bank, every bit that is HIGH(1) will cause the corresponding bit to be cleared to 0. Data bits that are LOW(0) have no effects on the corresponding bit. MediaTek Confidential © 2013 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 5 of 64 loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 1 System Overview MT6572 is a highly integrated baseband platform incorporating both modem and application processing subsystems to enable 3G smart phone applications, with integrated Bluetooth, WiLAN and GPS modules. The chip integrates a Dual-core ARM® Cortex-A7 MPCoreTM operating up to 1.2GHz, an ARM® Cortex-R4 MCU and a powerful multi-standard video accelerator. MT6572 supports various interfaces, including parallel/serial NAND flash memory and 32-bit LPDDR2 for optimal performance, and supports booting from SLC NAND or eMMC to minimize the overall BOM cost. In addition, an extensive set of interfaces and connectivity peripherals are included to interface to cameras, touch-screen displays, MMC/SD cards. The application processor, a Dual-core ARM® Cortex-A7 MPCoreTM which includes a NEON multimedia processing engine, offers processing power necessary to support the latest OpenOS along with its demanding applications such as web browsing, email, GPS navigation and games. All are viewed on a high resolution touch screen display with graphics enhanced by the 2D and 3D graphics acceleration. The multi-standard video accelerator and an advanced audio subsystem are also included to provide advanced multimedia applications and services such as streaming audio and video, a multitude of decoders and encoders such as H.264 and MPEG-4. Audio supported includes FR, HR, EFR, AMR FR, AMR HR and Wide-Band AMR vocoders, polyphonic ringtones and advanced audio functions such as echo cancellation, hands-free speakerphone operation and noise cancellation. An ARM® Cortex-R4, DSP, and 2G and 3G coprocessors provide a powerful modem subsystem capable of supporting WCDMA Category 14 (21 Mbps) HSDPA downlink and Category 6 (5.76 Mbps) HSUPA uplink data rates or TD-SCDMA Category 14 (2.8 Mbps) HSDPA downlink, Category 6 (2.2 Mbps) HSUPA , as well as Class 12 GPRS and EDGE. MT6572 also embodies wireless communication device, including WLAN, Bluetooth and GPS. With four advanced radio technologies integrated into one single chip, MT6572 provides the best and most convenient connectivity solution among the industry. MT6572 implements advanced and sophisticated radio coexistence algorithms and hardware mechanisms. It also supports single antenna sharing among 2.4 GHz antenna for Bluetooth, WLAN and 1.575 GHz for GPS. MediaTek Confidential © 2013 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 6 of 64 loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 1.1 Platform Features  General  Smartphone,3 MCU subsystems architecture  SLC NAND flash and eMMC bootloader  Supports LPDDR-1/LPDDR-2/LPDDR-3/P D-DDR3  AP MCU subsystem  Dual-core ARM® Cortex-A7 MPCoreTM operating at 1.2GHz  NEON multimedia processing engine with SIMDv2/VFPv4 ISA support  32KB L1 I-cache and 32KB L1 D-cache  256KB unified L2 cache  DVFS technology with adaptive operating voltage from 1.05V to 1.26V  MD external interfaces  Supports dual SIM/USIM interface  Interface pins with RF and radio-related peripherals (antenna tuner, PA, …)  UART for modem logging/debugging purpose  External memory interface  Supports LPDDR1/2/3, PC-DDR3 up to 2GB  32-bit data bus width  Memory clock up to 333MHz  Supports self-refresh/partial self-refresh mode  Low-power operation  Programmable slew rate for memory controller’s IO pads  Supports dual rank memory device  Advanced bandwidth arbitration control  MD MCU subsystem  ARM® Cortex-R4 processor with maximum 480MHz operation frequency  32KB I-cache, 16KB D-cache  256KB TCM (tightly-coupled memory)  DSP for running modem/voice tasks, with maximum 245.76MHz operation frequency  High-performance AXI and AHB bus  General DMA engine and dedicated DMA channels for peripheral data transfer  Watchdog timer for system error recovery  Power management for clock gating control  Peripherals  USB2.0 high-speed OTG supporting 8 Tx and 8 Rx endpoints  USB2.0 full-speed host  NAND flash controller supporting NAND bootable, iNAND2® and MoviNAND®  2 UART for debugging and applications  SPI for external device  2 I2C to control peripheral devices, e.g. CMOS image sensor, LCM or FM receiver module  Maximum 5 PWM channels (depending on system configuration/IO usage)  I2S for connection with optional MediaTek Confidential © 2013 MediaTek Inc. Page 7 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A external hi-end audio codec  GPIOs  2 sets of memory card controllers supporting SD/SDHC/MS/MSPRO/MMC and SDIO2.0/3.0 protocols  GPU voltage: 1.15V  I/O voltage: 1.8V/2.8V/3.3V  Memory: 1.2V/1.8V/1.35V/1.5V  NAND: 1.8V  LCM interface: 1.8V  Clock source: 26MHz, 32.768kHz  Operating conditions  Core voltage: 1.15V  Processor DVFS voltage: 1.15V ~ 1.26V (Typ. 1.15V; sleep mode 1.05V)  Processor SRAM voltage: 1.15V ~ 1.26V (Typ. 1.15V; sleep mode 1.05V)  Package  Type: TFBGA  10.6mm x 10.6mm  Height: 1.1mm maximum  Ball count: 428 balls  Ball pitch: 0.4mm MediaTek Confidential © 2013 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 8 of 64 loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 1.2 MODEM Features  3G UMTS FDD supported features (with MT6166)  CPC (DTX in CELL_DCH, UL DRX DL DRX), HS-SCCH-less, HS-DSCH  MAC-ehs  Uplink Cat.6, throughput up to 5.7Mbps  Downlink Cat. 14, throughput up to 21Mbps  Fast dormancy  ETWS  Network selection enhancements  3G TDD supported features  TD-SCDMA/HSDPA/HSUPA baseband  Supports TD-SCDMA Bands 34, 39 & 40 and Quad band GSM/EDGE  Circuit-switched voice and data, and packet-switched data  384/384Kbps class in UL/DL for TD-SCDMA  TD-HSDPA: 2.8Mbps DL (Cat.14)  TD-HSUPA: 2.2Mbps UL (Cat.6)  F8/F9 ciphering/integrity protection  Radio interface and baseband front-end  High dynamic range delta-sigma ADC converts the downlink analog I and Q signals to digital baseband  10-bit D/A converter for Automatic Power Control (APC)  Programmable radio Rx filter with adaptive gain control  Dedicated Rx filter for FB acquisition  Baseband Parallel Interface (BPI) with programmable driving strength (shared by 2G & 3G modem)  Supports multi-band  GSM modem and voice CODEC  Dial tone generation  Noise reduction  Echo suppression  Advanced sidetone oscillation reduction  Digital sidetone generator with programmable gain  Two programmable acoustic compensation filters  GSM quad vocoders for adaptive multi-rate (AMR), enhanced full rate (EFR), full rate (FR) and half rate (HR)  GSM channel coding, equalization and A5/1, A5/2 and A5/3 ciphering  GPRS GEA1, GEA2 and GEA3 ciphering  Programmable GSM/GPRS/EDGE modem  Packet switched data with CS1/CS2/CS3/CS4 coding schemes  GSM circuit switch data  GPRS/EDGE Class 12  Supports SAIC (single antenna interference cancellation) technology  Supports VAMOS (Voice services over Adaptive Multi-user channels on One Slot) technology in R9 spec MediaTek Confidential © 2013 MediaTek Inc. Page 9 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 1.3 Connectivity Features  Supports integrated WIFI/BlueTooth/GPS  Supports single antenna for Bluetooth and WLAN, GPS  Self calibration  Supports TCXO & TSX  Best-in-class current consumption performance  Intelligent BT/WLAN coexistence scheme that goes beyond PTA signaling (for example, transmit window and duration that take into account protocol exchange sequence, frequency, etc.)  Wi-Fi  Single-band (2.4GHz) single stream 802.11 b/g/n MAC/BB/RF  802.11 d/h/k compliant  Security: WFA WPA/WPA2 personal, WPS2.0, WAPI (Hardware)  QoS: WFA WMM, WMM PS  Supports 802.11n optional features: STBC, A-MPDU, Blk-Ack, RIFS, MCS feedback, 20/40MHz coexistence (PCO), unscheduled PSMP  Supports 802.11w protected managed frames  Supports Wi-Fi Direct (WFA P-2-P standard) Supports HotSpot 2.0 Passpoint  Per packet TX power control  BlueTooth  Bluetooth specification v2.1+EDR  Bluetooth specification 3.0+HS compliance  Bluetooth v4.0 Low Energy (LE)  Rx sensitivity: GFSK -95dBm, DQPSK -94dBm, 8-DPSK -88dBm  Best-in-class BT/Wi-Fi coexistence performance  Up to 4 piconets simultaneously with background inquiry/page scan  Supports Scatternet  Packet Loss Concealment (PLC) function for better voice quality  Low-power scan function to reduce power consumption in scan modes  GPS  Supports GPS/QZSS/SBAS (WAAS/MSAS/EGNOS/GAGAN)  Best-in-class sensitivity performance  Full A-GPS capability (E911/SUPL/EPO/HotStill)  Active interference cancellation for up to 8 in-band tones  Low-power operational modes  5Hz update rate MediaTek Confidential © 2013 MediaTek Inc. Page 10 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 1.4 Multimedia Features  Display  Supports landscape or portrait panel resolution up to qHD (960x540)  Supports 8/9/16/18-bit host interface (MIPI DBI)  Supports 8/9/16/18/24/32-bit serial interfaces  Supports landscape or portrait panel resolution up to qHD (960x540)  Supports 8/9/16/18-bit host interface (MIPI DBI)  Supports 8/9/16/18/24/32-bit serial interfaces  Supports 16/18/24-bit RGB interfaces (MIPI DPI)  MIPI DSI interface (3 data lanes)  Embedded LCD gamma correction  Supports true colors  4 overlay layers with per-pixel alpha channel and gamma table  Supports spatial and temporal dithering  Supports side-by-side format output to stereo 3D panel in both portrait and landscape modes  Supports color enhancement  Supports adaptive contrast enhancement  Supports image/video/graphic sharpness enhancement  Supports dynamic backlight scaling  Graphics  OpenGL ES 1.1/2.0 3D graphic accelerator  OpenVG1.1 vector graphics accelerator  Image  Supports 5 MP Capture up to 15fps  Supports MIPI CSI-2 high-speed camera serial interface with 2 data lane (for main) + 2 data lane (for sub)  Supports face detection and visual tracking  Supports zero shutter delay image capture  Supports capturing image when recording video  Supports JPEG decoder for baseline decoding up to 29.4M pixel/sec; supports progressive format decoding  Supports JPEG encoder for baseline encoding up to 17.5M pixel/sec  Video  H.264 decoder: Baseline 720p @ 30fps  H.264 decoder: Main/high profile 720p@30fps  MPEG-4 SP/ASP decoder: 720p @ 30fps  DIVX3/DIVX4/DIVX5/DIVX6/DIV X HD/XVID decoder: 720p @ 30fps  VP8 decoder: 720p @ 30fps  VC-1 decoder: 720p @ 30fps  MPEG-4 encoder: Simple profile 720p @ 30fps  H.263 encoder: 720p @ 30fps  H.264 encoder: Baseline profile VGA @ 24fps  Audio  Sampling rates supported: 8kHz to 48kHz MediaTek Confidential © 2013 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 11 of 64 loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A  Sample formats supported: 8-bit/16-bit, Mono/Stereo  Interfaces supported: I2S, proprietary audio interface for MT6323  Customizable multiband loudspeaker and headphone compensation IIR filter  MediaTek proprietaty audio post-processing, BesSound Series: BesAudEnh (earphone enhancer), BesLoudness (volume maximizer), BesSurround (virtual 3D surround), BesEQ (multiband equalizer), BesBass (bass booster), BesLive (virtual auditory space), BesRecord (mono/stereo record, up-to 48KHz sampling rate, with Stereo-widening)  Android built-in post processing  Audio encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM  Audio decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM  Speech  Speech codec (FR, HR, EFR, AMR FR, AMR HR and Wide-Band AMR)  CTM  Noise reduction  Noise suppression  Noise cancellation  Dual-MIC noise cancellation  Echo cancellation  Echo suppression  Dual-MIC input  Digital MIC input MediaTek Confidential © 2013 MediaTek Inc. Page 12 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 1.5 General Description MediaTek MT6572 is a highly integrated 3G System-on-chip (SoC) which incorporates advanced features, e.g. HSPA modem, Dual-core ARM® Cortex-A7 MPCoreTM operating at 1.2 GHz, 3D graphics (OpenGL|ES 2.0), 5M camera, LPDDR2 up to 667MHz and high-definition 720p video decoder. MT6572 helps phone manufacturers build high-performance 3G smart phones with PC-like browser, 3D gaming and cinema class home entertainment experiences. World-leading technology Based on MediaTek’s world-leading mobile chip SoC architecture with advanced 28nm process, MT6572 is the brand-new generation smart phone SoC integrating MediaTek HSPA modem, 1.2GHz Dual-core ARM® Cortex-A7 MPCoreTM, 3D graphics and high-definition 720pp video decoder. Rich in features, high-valued product To enrich the camera features, MT6572 equips a 5M camera with advanced features, e.g. auto focus, anti-handshake, auto sensor defect pixel correction, continuous video AF, face detection, burst shot, optical zoom and panorama view. Incredible browser experience The 1.2GHz Dual-core ARM® Cortex-A7 MPCoreTM with NEON multimedia processing engine brings PC-like browser experiences and helps accelerate OpenGL|ES 2.0 3D Adobe Flash 10 rendering performance to an unbeatable level. MediaTek Confidential © 2013 MediaTek Inc. Page 13 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A NAND Flash USB2.0 OTG SW JTAG MMC/SD/SDIO LPDDR1 /LPDDR2 /LPDDR3 /PCDDR3 EDGE RF WCDMA RF TDSCDMA RF MT6166 W-CDMA/ TD-SCDMA/ GSM RF I2C Multimedia External Memory Interface HSPA MT6572 Modem Analog RX ADC TX ADC APC AFC Modem GSM/GPRS/ EDGE TDSCDMA WiFi/BTGPS ABB PLL DAC ADC Combo WIFI BT GPS Cellular Modem ABB PLL DAC ADC Power Management GP Timer Internal Memory Modem MCU ARM® Cortex-R4 DMA JTAG AP MCU ARM® Cortex-A7 MPCoreTM ARM® Cortex-A7 MPCoreTM NEON L2 Cache Multimedia Video Codec LCD Control Camera Image Post-process ARM® MALI-400 Graphics accelerator GPIO 5MP Camera LCD UART Touch Panel MT6627 WIFI/BT/GPS/FM MT6R62F8 Qwerty Keypad SIM SIM MT6323 PMIC Speaker Battery Headset MIC1 MIC2 Figure 1. Block diagram of MT6572 MediaTek Confidential © 2013 MediaTek Inc. Page 14 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX 2 Product Description 2.1 Pin Description 2.1.1 Ball Map View MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Figure 2. Ball map view for LPDDR1 MediaTek Confidential © 2013 MediaTek Inc. Page 15 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Figure 3. Ball map view for LPDDR2 2.1.2 Pin Coordinate Table 1. Pin coordinate (use LPDDR1) Ball Loc. A1 Ball name AVSS18_MD Ball Loc. K5 Ball name AUD_CLK_MOSI Ball Loc. U21 A2 UL_I_P K6 VCCK U22 Ball name RDP0_A RDN0_A MediaTek Confidential © 2013 MediaTek Inc. Page 16 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. A4 A5 A7 A8 A10 A11 A13 A14 A16 A18 A19 A21 A22 A24 A25 A26 B1 B2 B3 Ball name AVSS18_MD AUX_IN5_YM VM1 VM0 BPI_BUS7 BPI_BUS3 BPI_BUS6 GND_WBG GPS_RXIP WB_TXQP WB_TXIN WB_RXIN WB_RXIP KROW1 KCOL2 DUMMY DL_Q_P UL_I_N UL_Q_N Ball Loc. K7 Ball name VCCK Ball Loc. U25 Ball name DVSS18_MIPIRX K8 VCCK V1 ND15 K9 VCCK V2 LPD0 K11 VCCK V5 ND13 K12 VCCK V13 VSS K14 VCCK V23 RDP1_A K15 VCCK V24 RDN1_A K16 VCCK V25 RCN_A K17 VCCK W1 ND2 K20 DVDD18_CAM W2 ND8 K21 VSS W3 ND3 K22 MC1_DAT0 W4 ND6 K23 MC1_CMD W5 NCEB K24 DVDD3_MC1 W9 VCCIO_EMI K25 CMRST2 W11 VSS L2 PMIC_SPI_MOSI W12 VCCIO_EMI L3 DVDD18_VIO_1 W14 VCCIO_EMI L4 PMIC_SPI_SCK W16 VCCIO_EMI L5 PMIC_SPI_MISO W19 VCCIO_EMI MediaTek Confidential © 2013 MediaTek Inc. Page 17 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. B4 B5 B6 B7 B8 B9 B10 B11 B12 B14 B15 B16 B18 B19 B20 B21 B22 B23 B24 Ball name UL_Q_P AUX_IN3_YP AUX_IN1 AUX_IN0 BPI_BUS13 BPI_BUS12 BPI_BUS8 BPI_BUS1 BPI_BUS0 GPS_RXQN GPS_RXQP GPS_RXIN WB_TXQN WB_TXIP WB_RXQN WB_RXQP GND_WBG SDA_1 SCL_1 Ball Loc. L6 L7 L8 L9 L11 L12 L14 L15 L16 L17 L21 L25 L26 M1 M2 M3 M5 M6 M7 Ball name VCCK VCCK VCCK VCCK VSS VSS VSS VSS VSS VCCK MC1_CK CMPDN2 MC1_DAT3 SIM2_SIO SYSRSTB SIM1_SIO VSS VCCK VCCK Ball Loc. W23 W24 W25 W26 Y2 Y3 Y4 Y5 Y8 Y9 Y13 Y14 Y18 Y19 Y21 Y22 Y23 Y25 Y26 Ball name VSS DVDD3_LCD RCP_A VSS ND1 ND9 ND12 NWRB EDQS2 EDQS3_B EDQS1 EDQS0_B EDCLK0_B EDCLK1 VSS CMMCLK CMPCLK CMDAT2 CMDAT3 MediaTek Confidential © 2013 MediaTek Inc. Page 18 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. B25 B26 C1 C2 C3 C4 C5 C7 C10 C11 C12 C14 C15 C16 C17 C18 C19 C20 C21 Ball name KROW0 KROW2 DL_Q_N DL_I_N AVSS18_MD AUX_IN4_XM AUX_IN2_XP BSI_DATA1 DVDD28_BPI BPI_BUS5 BPI_BUS2 CONN_RSTB GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG Ball Loc. M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M22 M25 N1 N2 N3 N4 N5 N8 N9 Ball name VCCK VCCK VCCK VSS VSS VSS VSS VSS VSS VCCK MC1_DAT1 MC1_DAT2 LPD17 LPD16 LPD15 LPD13 LPD11 VSS VSS Ball Loc. AA1 Ball name DVDD18_MC0 AA2 ND0 AA8 EDQS2_B AA9 EDQS3 AA13 EDQS1_B AA14 EDQS0 AA18 EDCLK0 AA19 EDCLK1_B AA22 LPRDB AA25 CMDAT1 AB1 ND4 AB2 NREB AB3 NWPB AB5 VSS AB6 ED16 AB9 ED24 AB11 VSS AB13 EDQM0 AB14 VSS MediaTek Confidential © 2013 MediaTek Inc. Page 19 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. Ball name Ball Loc. C22 CONN_WB_CTRL4 N10 C23 CONN_WB_CTRL5 N11 C24 KCOL0 N12 C25 SCL_0 N13 C26 SDA_0 N14 D2 DL_I_P N15 D3 AVDD18_MD N16 D5 TXBPI N19 D6 BSI_DATA2 N20 D7 BPI_BUS15 N22 D10 BPI_BUS9 N25 D11 BPI_BUS4 N26 D12 PWM_A P2 D16 GND_WBG P5 D17 GND_WBG P6 D18 GND_WBG P7 D19 GND_WBG P8 D20 GND_WBG P9 D22 CONN_WB_CTRL2 P10 Ball name VSS VSS VSS VSS VSS VSS VSS TCP TCN VSS TDN1 TDP1 LPD14 LPD9 VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VSS Ball Loc. AB16 Ball name ED0 AB17 VREF1 AB18 EA18 AB19 EA14 AB20 ECAS_B AB23 LPA0 AB24 DVDD18_LCD AB25 CMDAT0 AB26 LPTE AC1 ND11 AC2 ND10 AC3 NCLE AC5 ED20 AC7 ED25 AC8 VSS AC9 ED26 AC11 VREF0 AC13 ED8 AC15 ED1 MediaTek Confidential © 2013 MediaTek Inc. Page 20 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. D24 Ball name KCOL1 Ball Loc. P11 Ball name VSS Ball Loc. AC18 D25 URXD1 P12 VSS AC21 E1 CLK26M P13 VSS AC22 E2 AVSS18_MD P14 VSS AC23 E5 AVDD18_AP P15 VSS AC24 E7 BPI_BUS14 P16 VSS AC25 E8 BPI_BUS11 P19 TDN0 AC26 E9 BPI_BUS10 P20 TDP0 AD2 E12 PWM_B P23 TDN2 AD3 E13 CONN_F2W_DAT P24 TDP2 AD5 E14 CONN_SDATA P25 DVSS18_MIPITX AD8 E15 CONN_SEN P26 VRT AD11 E20 CONN_WB_CTRL0 R1 LPD10 AD12 E22 CONN_WB_CTRL3 R2 LPD12 AD15 E23 SPI_CS R5 LPD7 AD18 E25 UTXD1 R6 VCCK_CPU AD21 E26 UTXD2 R7 VCCK_CPU AD22 F1 AVDD28_DAC R8 VCCK_CPU AD24 F2 APC R9 VCCK_CPU AD25 Ball name EA3 VSS ERESET EA12 FSOURCE LPWRB LRSTB ND5 NALE ED21 EDQM2 VSS EDQM1 ED14 EA10 ERAS_B EA11 ECKE LPCE0B MediaTek Confidential © 2013 MediaTek Inc. Page 21 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. F3 Ball name VBIAS Ball Loc. R10 Ball name VSS Ball Loc. AE1 F6 REFP R11 VSS AE2 F9 BSI_DATA0 R12 VSS AE3 F11 BSI_EN R13 VSS AE4 F12 CONN_F2W_CLK R14 VSS AE5 F14 CONN_XO_IN R15 VSS AE6 F18 AVDD18_WBG R16 VSS AE7 F20 CONN_WB_CTRL1 R17 VCCK AE8 F23 SPI_SCK R21 RDP1 AE9 F24 SPI_MISO R22 RDN1 AE10 F25 SPI_MOSI R23 RDP0 AE11 F26 URXD2 R24 RDN0 AE12 G2 WATCHDOG R25 DVDD18_MIPITX AE13 G3 VSS R26 RCN AE14 G4 TESTMODE T1 LPD8 AE15 G6 REFN T2 LPD6 AE16 G11 BSI_CLK T3 LPD3 AE17 G12 CONN_SCLK T4 LPD1 AE18 G23 AVSS33_USB T5 LPD5 AE19 G24 AVDD33_USB T6 VCCK_CPU AE20 G25 USB_DP T7 VCCK_CPU AE21 G26 USB_DM T8 VCCK_CPU AE22 Ball name ND7 ND14 NRNB ED19 ED22 ED30 ED28 ED27 ED12 ED13 ED15 EDQM3 ED6 ED4 ED5 ED7 EA16 EA17 EA2 EA1 EA15 EA13 MediaTek Confidential © 2013 MediaTek Inc. Page 22 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. H2 Ball name CLK32K_IN Ball Loc. T9 Ball name VCCK_CPU Ball Loc. AE23 Ball name EA8 H4 SRCLKENA T10 VSS AE24 EA6 H5 SIM1_SCLK T11 VSS AE25 EA9 H13 DVDD18_VIO_3 T12 VSS AE26 EA4 H22 CMPDN T13 VSS AF1 VSS H23 AVDD18_USB T14 VSS AF2 ED17 H25 USB_VRT T15 VSS AF3 ED18 J1 AUD_DAT_MISO T16 VCCK AF5 ED23 J2 EINTX T17 VCCK AF6 ED31 J5 SIM2_SCLK T25 DVDD18_MIPIRX AF8 ED29 J8 VCCK T26 RCP AF9 ED9 J9 VCCK U2 LPD4 AF11 ED10 J10 VCCK U5 LPD2 AF12 ED11 J11 VCCK U6 VCCK_CPU AF13 VSS J14 VCCK U7 VCCK_CPU AF15 ED3 J15 VCCK U9 DVDD18_PLLGP AF16 ED2 J16 VCCK U10 VSS AF18 EA0 J17 VCCK U11 VSS AF19 ECS1_B J19 DVDD18_VIO_2 U12 VCCK AF21 EWR_B J22 CMRST U13 VCCK AF22 ECS0_B J25 CHD_DM U14 VCCK AF24 EA5 J26 CHD_DP U15 VCCK AF25 EA7 MediaTek Confidential © 2013 MediaTek Inc. Page 23 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. K1 K2 Ball name AUD_DAT_MOSI PMIC_SPI_CSN Ball Loc. U16 U17 Ball name VCCK VCCK Ball Loc. AF26 2.1.3 Detailed Pin Description Table 2. Acronym for pin type Abbreviation AI AO AIO DI DO DIO P G Description Analog input Analog output Analog bi-direction Digital input Digital output Digital bi-direction Power Ground Ball name VSS Table 3. Detailed pin description (use LPDDR1) Pin name SYSTEM SYSRSTB WATCHDOG TESTMODE RTC32K_IN SRCLKENA PMIC PMIC_SPI_MOSI PMIC_SPI_MISO PMIC_SPI_CSN PMIC_SPI_SCK EINTX AUD_CLK_MOSI AUD_DAT_MOSI ADC_DAT_MISO SIM SIM1_SIO SIM1_SCLK SIM2_SIO SIM2_SCLK LCD Type DIO DO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description System reset input Watchdog reset output Test mode 32K clock intput 26MHz co-clock enable output PMIC SPI control interface PMIC SPI control interface PMIC SPI control interface PMIC SPI control interface PMIC SPI control interface PMIC audio input interface PMIC audio input interface PMIC audio input interface SIM1 data, PMIC interface SIM1 clock, PMIC interface SIM2 data, PMIC interface SIM2 clock, PMIC interface Power domain DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 MediaTek Confidential © 2013 MediaTek Inc. Page 24 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name LPCE0B LPTE LRSTB LPWRB LPRDB LPA0 LPD17 LPD16 LPD15 LPD14 LPD13 LPD12 LPD11 LPD10 LPD9 LPD8 LPD7 LPD6 LPD5 LPD4 LPD3 LPD2 LPD1 LPD0 PWM Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description Parallel display interface chip select 0 output Parallel display interface tearing effect Parallel display interface Reset Signal Parallel display interface Write Signal Parallel display interface Read Signal Parallel display interface Address Signal Data pin 17 for DBI parallel LCD interface Data pin 16 for DBI parallel LCD interface Data pin 15 for DBI parallel LCD interface Data pin 14 for DBI parallel LCD interface Data pin 13 for DBI parallel LCD interface Data pin 12 for DBI parallel LCD interface Data pin 11 for DBI parallel LCD interface Data pin 10 for DBI parallel LCD interface Data pin 9 for DBI parallel LCD interface Data pin 8 for DBI parallel LCD interface Data pin 7 for DBI parallel LCD interface Data pin 6 for DBI parallel LCD interface Data pin 5 for DBI parallel LCD interface Data pin 4 for DBI parallel LCD interface Data pin 3 for DBI parallel LCD interface Data pin 2 for DBI parallel LCD interface Data pin 1 for DBI parallel LCD interface Data pin 0 for DBI parallel LCD interface Power domain DVDD3_LCD/DVDD18_LCD DVDD3_LCD/DVDD18_LCD DVDD3_LCD/DVDD18_LCD DVDD3_LCD/DVDD18_LCD DVDD3_LCD/DVDD18_LCD DVDD3_LCD/DVDD18_LCD DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 MediaTek Confidential © 2013 MediaTek Inc. Page 25 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name PWM_A PWM_B UART1 UTXD1 URXD1 UART2 UTXD2 URXD2 SPI SPI_CS SPI_MISO SPI_MOSI SPI_SCK BPI BPI_BUS0 BPI_BUS1 BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 BPI_BUS10 BPI_BUS11 BPI_BUS12 BPI_BUS13 BPI_BUS14 BPI_BUS15 VM VM1 VM0 BSI BSI_EN BSI_CLK BSI_DATA0 BSI_DATA1 BSI_DATA2 TXBPI MSDC1 MC1_CLK MC1_CMD MC1_DAT0 Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description PWM_A PWM_B UART1 TX UART1 RX UART2 TX UART2 RX SPI chip select SPI data in SPI data out SPI clock BPI BUS0 BPI BUS1 BPI BUS2 BPI BUS3 BPI BUS4 BPI BUS5 BPI BUS6 BPI BUS7 BPI BUS8 BPI BUS9 BPI BUS10 BPI BUS11 BPI BUS12 BPI BUS13 BPI BUS14 BPI BUS15 PA mode selection PA mode selection BSI CS BSI CLK BSI DATA0 BSI DATA1 BSI DATA2 RF MT6166 TXBPI MSDC1 clock output MSDC1 command pin MSDC1 data0 pin Power domain DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD28_BPI/DVDD18_VIO_3 DVDD28_BPI/DVDD18_VIO_3 DVDD28_BPI/DVDD18_VIO_3 DVDD28_BPI/DVDD18_VIO_3 DVDD28_BPI/DVDD18_VIO_3 DVDD28_BPI/DVDD18_VIO_3 DVDD28_BPI/DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD3_MC1/DVDD18_CAM DVDD3_MC1/DVDD18_CAM DVDD3_MC1/DVDD18_CAM MediaTek Confidential © 2013 MediaTek Inc. Page 26 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name MC1_DAT1 MC1_DAT2 MC1_DAT3 MSDC0 ND11/MC0_CLK NRNB/MC0_CMD ND10/MC0_DAT0 ND14/MC0_DAT1 NALE/MC0_DAT2 NREB/MC0_DAT3 NWPB/MC0_DAT4 ND5/MC0_DAT5 ND7/MC0_DAT6 NCLE/MC0_DAT7 ND4/MC0_RSTB NFI NCEB NWRB NLD0 NLD1 NLD2 NLD3 NLD6 NLD8 NLD9 NLD12 NLD13 NLD15 EFUSE FSOURCE EMI Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description MSDC1 data1 pin MSDC1 data2 pin MSDC1 data3 pin Nand-Flash Data 11 / MSDC0 clock output Parallel NAND interface chip ready input/MSDC0 command pin Nand-Flash Data 10/MSDC0 data0 pin Nand-Flash Data 14/MSDC0 data1 pin Parallel NAND interface address latch enable output/MSDC0 data2 pin Parallel NAND interface read strobe output/MSDC0 data3 pin Parallel NAND interface write protect output/MSDC0 data4 pin Nand-Flash Data 5/MSDC0 data5 pin Nand-Flash Data 7/MSDC0 data6 pin Parallel NAND interface command latch enable output7/MSDC0 data7 pin Nand-Flash Data 4/MSDC0 reset output Parallel NAND interface chip select output Parallel NAND interface write strobe output Nand-Flash Data 0 Nand-Flash Data 1 Nand-Flash Data 2 Nand-Flash Data 3 Nand-Flash Data 6 Nand-Flash Data 8 Nand-Flash Data 9 Nand-Flash Data 12 Nand-Flash Data 13 Nand-Flash Data 15 E-FUSE blowing power control Power domain DVDD3_MC1/DVDD18_CAM DVDD3_MC1/DVDD18_CAM DVDD3_MC1/DVDD18_CAM DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_VIO_1 DVDD18_MC0 DVDD18_MC0 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_VIO_1 DVDD18_MC0 DVDD18_MC0 DVDD18_VIO_1 DVDD18_VIO_1 FSOURCE MediaTek Confidential © 2013 MediaTek Inc. Page 27 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name ERESET EDCLK0 EDCLK0_B EDCLK1 EDCLK1_B ECKE ECS0_B ECS1_B ECAS_B ERAS_B ERW_B EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description DDR3 reset output # DRAM clock 0 output DRAM clock 0 output # DRAM clock 1 output DRAM clock 1 output # DRAM command output CKE DRAM chip select 0 # DRAM chip select 1 # DRAM command output CAS# DRAM command output RAS# DRAM command output WR# DRAM address output 0 DRAM address output 1 DRAM address output 2 DRAM address output 3 DRAM address output 4 DRAM address output 5 DRAM address output 6 DRAM address output 7 DRAM address output 8 DRAM address output 9 DRAM address output 10 DRAM address output 11 DRAM address output 12 DRAM address output 13 Power domain VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI MediaTek Confidential © 2013 MediaTek Inc. Page 28 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name EA14 EA15 EA16 EA17 EDQM0 EDQM1 EDQM2 EDQM3 EDQS0 EDQS0_B EDQS1 EDQS1_B EDQS2 EDQS2_B EDQS3 EDQS3_B ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 ED24 ED25 Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description DRAM address output 14 DRAM address output 15 DRAM address output 16 DRAM address output 17 DRAM DQM 0 DRAM DQM 1 DRAM DQM 2 DRAM DQM 3 DRAM DQS 0 DRAM DQS 0 # DRAM DQS 1 DRAM DQS 1 # DRAM DQS 2 DRAM DQS 2 # DRAM DQS 3 DRAM DQS 3 # DRAM data pin 0 DRAM data pin 1 DRAM data pin 2 DRAM data pin 3 DRAM data pin 4 DRAM data pin 5 DRAM data pin 6 DRAM data pin 7 DRAM data pin 8 DRAM data pin 9 DRAM data pin 10 DRAM data pin 11 DRAM data pin 12 DRAM data pin 13 DRAM data pin 14 DRAM data pin 15 DRAM data pin 16 DRAM data pin 17 DRAM data pin 18 DRAM data pin 19 DRAM data pin 20 DRAM data pin 21 DRAM data pin 22 DRAM data pin 23 DRAM data pin 24 DRAM data pin 25 Power domain VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI MediaTek Confidential © 2013 MediaTek Inc. Page 29 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name ED26 ED27 ED28 ED29 ED30 ED31 VREF0 VREF1 CAM CMPCLK CMMCLK CMDAT0 CMDAT1 CMDAT2 CMDAT3 CMRST CMPDN CMRST2 CMPDN2 I2C0 SCL_0 SDA_0 I2C1 SCL_1 SDA_1 CONN CONN_WB_CTRL5 CONN_WB_CTRL4 CONN_WB_CTRL3 CONN_WB_CTRL2 CONN_WB_CTRL1 CONN_WB_CTRL0 CONN_RSTB CONN_SEN CONN_SCLK CONN_SDATA CONN_F2W_CLK CONN_F2W_DAT ABB UL_Q_N UL_Q_P UL_I_P UL_I_N VBIAS Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO AIO AIO AIO AIO AIO Description DRAM data pin 26 DRAM data pin 27 DRAM data pin 28 DRAM data pin 29 DRAM data pin 30 DRAM data pin 31 VREF for DRAM IO Pixel clock from sensor Master clock to sensor Pixel data[0] from sensor Pixel data[1] from sensor Pixel data[2] from sensor Pixel data[3] from sensor Reset control to 1st sensor Power down to 1st sensor Reset control to 2nd sensor Power down to 2nd sensor I2C0 clock I2C0 data I2C1 clock I2C1 data WB control for CONN_RF WB control for CONN_RF WB control for CONN_RF WB control for CONN_RF WB control for CONN_RF WB control for CONN_RF Reset for CONN_RF SPI for CONN_RF SPI for CONN_RF SPI for CONN_RF AUD_IN from CONN_RF AUD_IN from CONN_RF UMTS uplink for UMTSTX_QN UMTS uplink for UMTSTX_QP UMTS uplink for UMTSTX_IP UMTS uplink for UMTSTX_IN 3G PA analog control Power domain VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI DVDD18_LCD DVDD18_LCD DVDD18_LCD DVDD18_LCD DVDD18_LCD DVDD18_LCD DVDD18_CAM DVDD18_CAM DVDD18_CAM DVDD18_CAM DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_2 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 DVDD18_VIO_3 AVDD18_MD AVDD18_MD AVDD18_MD AVDD18_MD AVDD28_DAC MediaTek Confidential © 2013 MediaTek Inc. Page 30 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name APC CLK26M DL_Q_P DL_Q_N DL_I_N DL_I_P REFN REFP AUX_IN0 AUX_IN1 AUX_IN2_XP AUX_IN3_YP AUX_IN4_XM AUX_IN5_YM MIPI TDN2 TDP2 TDN1 TDP1 TDN0 TDP0 TCN TCP VRT RDN1 RDP1 RDN0 RDP0 RCN RCP RDN1_A Type AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AO AIO AIO AIO AIO AIO AIO AIO Description Automatic power control for modem 26MHz clock input for AP & modem UMTS downlink for UMTSRX_QP UMTS downlink for UMTSRX_QN UMTS downlink for UMTSRX_IN UMTS downlink for UMTSRX_IP Negative reference port for internal circuit Positive reference port for internal circuit AuxADC external input channel 0 AuxADC external input channel 1 AuxADC channel for touch screen TP_X+ AuxADC channel for touch screen TP_Y+ AuxADC channel for touch screen TP_XAuxADC channel for touch screen TP_Y- DSI0 lane2 N DSI0 lane2 P DSI0 lane1 N DSI0 lane1 P DSI0 lane0 N DSI0 lane0 P DSI0 CK lane N DSI0 CK lane P External resistor for DSI bias Connect 1.5K ohm 1% resistor to ground. CSI0 lane1 N CSI0 lane1 P CSI0 lane0 N CSI0 lane0 P CSI0 CK lane N CSI0 CK lane P CSI1 lane1 N/Pixel data [7] from sensor Power domain AVDD28_DAC AVDD18_MD AVDD18_MD AVDD18_MD AVDD18_MD AVDD18_MD AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX MediaTek Confidential © 2013 MediaTek Inc. Page 31 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name RDP1_A RDN0_A RDP0_A RCN_A RCP_A USB USB_DP USB_DM CHD_DP CHD_DM USB_VRT WBG WB_RX_QN WB_RX_QP WB_RX_IP WB_RX_IN WB_TX_QP WB_TX_QN WB_TX_IN WB_TX_IP GPS_RXQN GPS_RXQP GPS_RXIP GPS_RXIN CONN_XO_IN Analog power DVDD18_PLLGP AVDD18_AP AVDD18_MD AVDD28_DAC DVDD18_MIPITX DVDD18_MIPIRX AVDD33_USB AVDD18_USB Type AIO AIO AIO AIO AIO AIO AIO AIO AIO AO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO P P P P P P P P Description CSI1 lane1 P/Pixel data [6] from sensor CSI1 lane0 N/Pixel data [5] from sensor CSI1 lane0 P/Pixel data [4] from sensor CSI1 CK lane P/HREF from sensor CSI1 CK lane P/VREF from sensor USB D+ differential data line USB D- differential data line BC1.1 Charger DP BC1.1 Charger DM USB output for bias current; connect with 5.11K 1% Ohm to GND RX_QN for WIFI/BT Rx RX_QP for WIFI/BT Rx RX_IN for WIFI/BT Rx RX_IP for WIFI/BT Rx TX_QP for WIFI/BT Tx TX_QN for WIFI/BT Tx TX_IN for WIFI/BT Tx TX_IP for WIFI/BT Tx RX_QN for GPS Rx RX_QP for GPS Rx RX_IN for GPS Rx RX_IP for GPS Rx 26MHz clock input for WBG Analog power input 1.8V for PLL Analog power input 1.8V for AuxADC, TSENSE Analog power input 1.8V for BBTX, BBRX Analog power input 2.8V for APC Analog power for MIPI DSI Analog power for MIPI CSI0 & CSI1 Analog power 3.3V for USB Analog power 1.8V for USB Power domain DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX AVDD33_USB AVDD33_USB AVDD33_USB AVDD33_USB AVDD18_USB AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG AVDD18_WBG MediaTek Confidential © 2013 MediaTek Inc. Page 32 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX Pin name AVDD18_WBG Digital power DVDD18_VIO_1 DVDD18_VIO_2 DVDD18_VIO_3 DVDD28_BPI VCCIO_EMI DVDD18_MC0 DVDD33_MC1 DVDD33_LCD DVDD18_LCD DVDD18_CAM VCCK VCCK_CPU Analog ground AVSS18_MD DVSS18_MIPITX DVSS18_MIPIRX AVSS33_USB GND_WBG Digital ground VSS MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Type P P P P P P P P P P P P P G G G G G G Description Analog power 1.8V for WBTX, WBRX, GPSRX Digital power input Digital power input Digital power input Digital power input for 2.8V BPI IO Digital power input for EMI Digital power input for MSDC0 Digital power input for MSDC1 transmitter Digital power input for LCD control pins’ transmitter Digital power input for LCD control pins’ receiver Digital power input for CAM control pins Digital power input for core Digital power input for processor Power domain - - MediaTek Confidential © 2013 MediaTek Inc. Page 33 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.2 Electrical Characteristic 2.2.1 Absolute Maximum Ratings Table 4. Absolute maximum ratings for power supply Symbol or pin name Description Min. Max. Unit DVDD18_PLLGP Analog power input 1.8V for PLL 1.7 1.9 V AVDD18_AP Analog power input 1.8V for AuxADC, TSENSE 1.7 1.9 V AVDD18_MD Analog power input 1.8V for BBTX, BBRX 1.7 1.9 V AVDD28_DAC Analog power input 2.8V for APC 2.66 2.94 V DVDD18_MIPITX Analog power for MIPI DSI 1.7 1.9 V DVDD18_MIPIRX Analog power for MIPI CSI0 & CSI1 1.7 1.9 V AVDD33_USB Analog power 3.3V for USB 3.135 3.465 V AVDD18_USB Analog power 1.8V for USB 1.7 1.9 V DVDD18_VIO_1 DVDD18_VIO_2 DVDD18_VIO_3 Digital power input for 1.8V IO 1.62 1.98 V DVDD28_BPI Digital power input for BPI 1.7 3.6 V DVDD18_MC0 Digital power input for MSDC0 1.62 1.98 V DVDD3_MC1 Digital power input for MSDC1 1.7 3.6 V DVDD3_LCD Digital power input for LCD control pins’ transmitter 1.7 3.6 V DVDD18_LCD Digital power input for LCD control pins’ receiver 1.62 1.98 V DVDD18_CAM Digital power input for CAM control pins 1.62 1.98 V VCCIO_EMI Digital power input for EMI 1.08 1.98 V VCCK Digital power input for core 0.95 1.15 V VCCK_CPU Digital power input for processor 0.77 1.26 V Warning: Stressing the device beyond the absolute maximum ratings may cause permanent damage. These are stress ratings only. 2.2.2 Recommended Operating Conditions Table 5. Recommended operating conditions for power supply Symbol or pin name DVDD18_PLLGP AVDD18_AP AVDD18_MD Description Analog power input 1.8V for PLL Analog power input 1.8V for AuxADC, TSENSE Analog power input 1.8V for BBTX, BBRX Min. Typ. Max. Unit 1.7 1.8 1.89 V 1.71 1.8 1.89 V 1.71 1.8 1.89 V MediaTek Confidential © 2013 MediaTek Inc. Page 34 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol or pin name AVDD28_DAC DVDD18_MIPITX DVDD18_MIPIRX AVDD33_USB AVDD18_USB DVDD28_BPI DVDD18_VIO1 DVDD18_VIO2 DVDD18_VIO3 DVDD18_MC0 DVDD3_MC1 Description Analog power input 2.8V for APC Analog power for MIPI DSI Analog power for MIPI CSI0 & CSI1 Analog power 3.3V for USB Analog power 1.8V for USB Digital power input for BPI Digital power input for 1.8V IO Digital power input for MSDC0 Digital power input for MSDC1 DVDD3_LCD DVDD18_LCD DVDD18_CAM VCCIO_EMI VCCK VCCK_CPU Digital power input for LCD control pins Digital power input for LCD control pins Digital power input for CAM control pins Digital power input for EMI (LPDDR1) Digital power input for EMI (LPDDR2/3) Digital power input for EMI (LVDDR3) Digital power input for EMI (DDR3) Digital power input for core Digital power input for processor Min. Typ. Max. Unit 2.66 2.8 2.94 V 1.71 1.8 1.89 V 1.71 1.8 1.89 V 3.135 3.3 3.465 V 1.71 1.8 1.89 V 1.7 1.8 1.95 V 2.7 3.3 3.6 1.62 1.8 1.98 V 1.62 1.8 1.98 V 1.7 1.8 1.95 V 2.7 3.3 3.6 1.7 1.8 1.95 V 2.7 3.3 3.6 1.62 1.8 1.98 V 1.62 1.8 1.98 V 1.7 1.8 1.9 1.08 1.2 1.32 V 1.215 1.35 1.485 1.35 1.5 1.65 0.85 1.15 1.20 V 0.85 1.15 1.20 V 2.2.3 Storage Condition 1. Shelf life in sealed bag: 12 months at < 40°C and < 90% relative humidity (RH). 2. After bag opened, devices subjected to infrared reflow, vapor-phase reflow or equivalent processing must be:  Mounted within 168 hours at factory conditions of 30°C/60% RH, or  Stored at 20% RH. 3. Devices require baking before mounting, if:  192 hours at 40°C +5°C/-0°C and < 5% RH for low temperature device containers, or  24 hours at 125°C +5°C/-0°C for high temperature device containers. MediaTek Confidential © 2013 MediaTek Inc. Page 35 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.3 EMI Timing Diagram 2.3.1 Introduction The measurement point for all signals follows definition in JEDEC DRAM standard. Timing symbols in this section are matched with the JEDEC DRAM standard. This section describes the timing characteristics when LPDDR/LPDDR2/LPDDR2/PCDDR3 SDRAM are used. 2.3.2 EMI Clock Figure 4. EMI clock EDCLKx and EDCLKx_B Figure 5. Differential signals of EMI clock Table 6. EMI clock timing parameters Symbol tCK tCH tCL VIX Parameter Clock cycle time Clock high-level width Clock low-level width Differential clock crosspoint voltage Min. TBD 0.45 0.45 TBD Max. Unit TBD ns 0.55 tCK 0.55 tCK TBD V 2.3.3 2.3.3.1 EMI Read and Write Timing Read and Write Timing of LPDDR1 MediaTek Confidential © 2013 MediaTek Inc. Page 36 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Figure 6. EMI LPDDR1 write timing Figure 7 . EMI LPDDR1 Read timing Table 7. EMI LPDDR1 timing parameters Symbol Parameter Min. Max. Unit tIS Address and control setup input setup time TBD TBD ns tIH Address and control input hold time TBD TBD ns tIPW Address and control input pulse width TBD TBD ns Timing of read cycle tRPRE Write preamble TBD TBD tCK tRPST Write postamble TBD TBD tCK tDQSQ DQS-DQ skew TBD TBD ns tDV DQ/DQS valid window TBD TBD ns Timing of write cycle tDQSS Write command to the 1st DQS latching transition TBD TBD tCK tWPST Write postamble TBD TBD tCK tDS DQ and DQM setup time TBD TBD ns tDH DQ and DQM hold time TBD TBD ns tDIPW DQ and DQM pulse width TBD TBD ns tDQSH DQS high-level width TBD TBD tCK tDQSL DQS low-level width TBD TBD tCK tDQSCK DQS access time from CK/CK_B TBD TBD ns MediaTek Confidential © 2013 MediaTek Inc. Page 37 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.3.3.2 Read and Write Timing of LPDDR2 Figure 8. EMI LPDDR2 write timing Figure 9. EMI LPDDR2 read timing Table 8. EMI LPDDR2 timing parameters Symbol Parameter Min. Max. Unit tIS Address and control setup input setup time TBD TBD ns tIH Address and control input hold time TBD TBD ns tIPW Address and control input pulse width TBD TBD ns Timing of read cycle tRPRE Write preamble TBD TBD tCK tRPST Write postamble TBD TBD tCK tDQSQ DQS-DQ skew TBD TBD ns tDV DQ/DQS valid window TBD TBD ns Timing of write cycle tDQSS Write command to the 1st DQS latching transition TBD TBD tCK tWPST Write postamble TBD TBD tCK tDS DQ and DQM setup time TBD TBD ns tDH DQ and DQM hold time TBD TBD ns tDIPW DQ and DQM pulse width TBD TBD ns MediaTek Confidential © 2013 MediaTek Inc. Page 38 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX Symbol tDQSH tDQSL tDQSCK Parameter DQS high-level width DQS low-level width DQS access time from CK/CK_B MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Min. Max. Unit TBD TBD tCK TBD TBD tCK TBD TBD ns 2.3.3.3 TBD 2.3.3.4 TBD Read and Write Timing of LPDDR3 Read and Write Timing of PCDDR3 MediaTek Confidential © 2013 MediaTek Inc. Page 39 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.4 2.4.1 System Configuration Mode Selection Table 9 Mode selection Pin name [0] PMIC_SPI_CSN [1] AUD_DAT_MOSI KCOL0 BPI_BUS4 [0] SIM1_SCK [1] SIM2_SCK Description 00: Use pin map for LPDDR1 01: Use pin map for LPDDR2 1x: Use pin map for PCDDR3 0: Force USB download mode in bootrom 1: NA (default) 0: Boot from eMMC/NAND (default) 1: Boot from SD/SPI-NAND 00: No dedicate JTAG 01: Use KP pin for S-JTAG 10: Use MC1 pins for legacy JTAG 11: Use CM pins for legacy JTAG 2.4.2 Constant Tie Pins Table 10 Constant tied pins Pin name TESTMODE FSOURCE Description Test mode (tied to GND) EFUSE burning (tied to GND) MediaTek Confidential © 2013 MediaTek Inc. Page 40 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.5 Power-on Sequence The power-on/off sequence with XTAL is shown in the following figure: VBAT DDLO UVLO PWRKEY BBWAKEUP VCORE VSYS VIO18/VEMC_3V3 VA28/VIO28 VM VUSB_3V3 VMC/VMCH VTCXO RESETB De-bounce time = 50ms 4ms 2ms 2ms 2ms 2ms 2ms 2ms 2ms 20ms Figure 10. Power on/off sequence with XTAL 2ms 2ms 2ms Note that the above figure only shows one power-on/off condition with XTAL. The external PMIC for application processor handles the power ON and OFF of the handset. The following three different methods switch on the handset (when VBAT ≥ 3.2V): 1. Pulling PWRKEY low (The user presses PWRKEY.) 2. Pulling BBWAKEUP high 3. Valid charger plug-in Pulling PWRKEY low is a normal way to turn on the handset, which turns on regulators as long as the PWRKEY is kept low. PMIC outputs reset signal RESETB to application processor SYSRSTB input. After SYSRSTB is de-asserted, the microprocessor starts and pulls BBWAKEUP high. After that PWRKEY can be released. Pulling BBWAKEUP high will also turn on the handset. This is the case when the alarm in the RTC expires. Besides, applying a valid external supply on CHRIN will also turn on the handset. However, if the battery is in the UV state (VBAT < 3.2V), the handset cannot be turned on in any way. MediaTek Confidential © 2013 MediaTek Inc. Page 41 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A The UVLO function in PMIC prevents system startup when the initial voltage of the main battery is below the 3.2V threshold. When the battery voltage is bigger than 3.2V, the UVLO comparator switches and threshold are reduced to 2.9V, which allows the handset to start smoothly unless the battery decays to 2.9V and below. Once PMIC enters the UVLO state, it draws very low quiescent current. The VRTC LDO will still be active until the DDLO disables it. VBAT DDLO UVLO PWRKEY BBWAKEUP VCORE VSYS VIO18/VEMC_3V3 VA28/VIO28 VM VUSB_3V3 VMC/VMCH VTCXO RESETB De-bounce time = 50ms 4ms 2ms 2ms 2ms 2ms 2ms 2ms 2ms 2ms 20ms 2ms Figure 11. Power on/off sequence without XTAL The figure above shows the power-on/off sequence without XTAL. VTCXO is always turned on when VBAT is above the DDLO threshold. MediaTek Confidential © 2013 MediaTek Inc. Page 42 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.6 Analog Baseband To communicate with analog blocks, a common control interface for all analog blocks is implemented. In addition, there are some dedicated interfaces for data transfer. The common control interface translates the APB bus write and read cycle for specific addresses related to analog front-end control. During the writing or reading of any of these control registers, there is a latency associated with the transfer of data to or from the analog front-end. Dedicated data interface of each analog block is implemented in the corresponding digital block. An analog block includes the following analog functions for the complete GSM/GPRS/WCDMA base-band signal processing:  Base-band Rx: For I/Q channels base-band A/D conversion  Base-band Tx: For I/Q channels base-band D/A conversion and smoothing filtering.  RF control: Two DACs for automatic power control (APC) are included. Their outputs are provided to the external RF power amplifier respectively, according to the system dual-talk configuration. One more DAC for voltage bias control (VBIAS) is included for the WCDMA system, and the output is provided to the external RF power amplifier.  Auxiliary ADC: Provides an ADC for the battery and other auxiliary analog functions monitoring.  Clock generation: Includes two clock-squarers for shaping the dual-talk system clock and 14 PLLs providing clock signals to base-band TRx, DSP, MCUUSB, MSDC, LVDS and HDMI units. The analog blocks include the following analog functions for complete GSM/GPRS/WCDMA base-band signal processing:  BBRX  BBTX  APC-DAC  VBIAS-DAC  AUXADC  Phase locked loop 2.6.1 BBRX 2.6.1.1 Block Descriptions The receiver (Rx) performs baseband I/Q channels downlink analog-to-digital conversion: 1. Analog input multiplexer: For each channel, a 2-input multiplexer is included. 2. A/D converter: 2 high performance sigma-delta ADCs perform I/Q digitization for further digital signal processing. MediaTek Confidential © 2013 MediaTek Inc. Page 43 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A DL_I_P1 DL_I_N1 VCM1 VCM1 DL_Q_P1 DL_Q_N1 VCM1 VCM1 MUX MUX Thermometer (fS) 2's complement (fS) Main path ΔΣ Modulator Encoder DOUT_I1[3:0] ΔΣ Modulator Encoder CKOUT_208M_IQ1 INT_SEL_VIN_IQ1 DOUT_Q1[3:0] Figure 12. Block diagram of BBRX-ADC 2.6.1.2 Function Specifications See the table below for the function specifications of the base-band downlink receiver. Table 11. Baseband downlink specifications Symbol VIN ICM VCM FC RIN FS Parameter Differential analog input voltage (peak-to-peak) Common mode input current magnitude Common mode input voltage Input clock frequency Clock rate (SC mode & GSM mode) Input clock duty cycle Input clock period jitter, SC mode & GSM mode Differential input resistance SC mode & GSM mode Output sampling rate Min. Typ. Max. Unit 2.4 V 1 uA 0.65 0.7 0.75 V 208 MHz 49.5 50 50.5 % 0.61 % (rms) 11.2 16 20.8 kΩ 208 MSPS MediaTek Confidential © 2013 MediaTek Inc. Page 44 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Parameter Min. Typ. Max. Unit VOS Differential input referred offset 10 mV Signal to in-band noise SC mode, 2.4Vpp (2.7MHz) sinewave, 1kHz ~ 2.1MHz band 72 75 dB SIN GSM mode: 2.4Vpp(570kHz) sinewave, 70kHz ~ 270kHz band 84 87 dB DVDD18 AVDD18 T Digital power supply Analog power supply Operating temperature Current consumption (per channel)  Power-up  Power-down 1.7 1.8 1.7 1.8 −20 1.9 V 1.9 V 80 °C 3 mA 1 uA 2.6.2 BBTX 2.6.2.1 Block Descriptions BBTX includes two channel DACs with the 1st order low pass filter. The DACs are PMOS current-steering topology with NMOS constant sinking current, and the active RC filter performs current to voltage buffer. The bitwidth of DACs is 10-bit which is encoded into 7 bits of thermometer code and 7 binary code by mixedsys hardware. The encoded bits are timing synchronized by D-type flip-flop which is toggled by the analog local clock. The MD-PLL delivers 832MHz differential clock to BBTX. A clock divider translates the 832MHz to 416MHz for DACs and AFIFO inside mixedsys. The IO power, DVDD18_MD is regulated to a voltage around 1.55V to supply analog component. The required bias currents are generated by BBRX. MediaTek Confidential © 2013 MediaTek Inc. Page 45 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.6.2.2 Function Specifications Table 12. Baseband uplink transmitter specifications Symbol Parameter Min. Typ. Max. Unit Vocm IK Vfs N Fs Imis Gmis Vos_T Vos F3dB SLPF NOOB CN IM3 DC output common mode voltage HF leakage current @ supply, Irms @416*2 = 832MHz DAC output swing DAC resolution Sampling clock 1-sgma DAC unit cell mismatch 3-sigma I/Q gain mismatch 3-sigma output differential DC offset over temp. 3-sigma output differential DC offset 3dB corner freq. LPF selectivity @832MHz Output noise level @45MHz Signal to noise ratio@45MHz In-band two-tone test swing V1=V2=290/sqrt(2) mV 0.615 -0.2 20 28 0.65 2100 10.0 416 25 15.1 -146 -60 0.685 V 3.5 uA 1 0.2 4 10 30 30.1. -140 mV bit MHz % dB mV mV MHz dB nVrms/sqrt(Hz) dBc/Hz -56 dBc T Operating temperature -20 80 °C MediaTek Confidential © 2013 MediaTek Inc. Page 46 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Parameter Current consumption  Power-up  Power-down Min. Typ. Max. Unit 4.1 mA 10 uA 2.6.3 APC-DAC 2.6.3.1 Block Descriptions See the figure below. APC-DAC is designed to produce a single-ended output signal at the APC pin. RG_APCBUF_TRIM[3:0] APC_EN APC_BUS[9:0] APC_RSTB APC_TG RG_APC_TGSEL VBG (from bandgap) Reference buffer & bias gen. PAD_APC 10- bit DFF R-string DAC core Output Buffer PA APC-DAC Figure 13. Block diagram of APC-DAC 2.6.3.2 Function Specifications See the table below for the function specifications of APC-DAC. Table 13. APC-DAC specifications Symbol N FS SNDR TS VO,max CL DNL INL DVDD AVDD T Parameter Resolution Clock rate Signal-to-noise-and-distortion ratio (10kHz sine wave with 1.0V swing) Settling time (99% full-swing settling) Maximum output Output loading capacitance Differential nonlinearity (code 30 ~ 970) Integral nonlinearity (code 30 ~ 970) Digital power supply Analog power supply Operating temperature Min. Typ. 10 1.0833 50 1,000 1.0 2.0 0.9 1.0 2.6 2.8 20 Max. 2.1666 5 AVDD  0.2 2,200 1.1 3.0 85 Unit Bit MS/s dB us V pF LSB LSB V V C MediaTek Confidential © 2013 MediaTek Inc. Page 47 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol ION IOFF Parameter Current consumption (power-on state) Current consumption (power-down state) Min. Typ. Max. Unit 300 uA 1 uA 2.6.4 VBIAS-DAC 2.6.4.1 Block Descriptions RG_VBIASBUF_TRIM[3:0] VBIAS_EN VBIAS_BUS[9:0] VBIAS_RSTB VBIAS_TG RG_VBIAS_TGSEL VBG (from bandgap) Reference buffer & bias gen. 10- bit DFF R-string DAC core VBIAS-DAC Output Buffer Figure 14. Block diagram of VBIAS-DAC PAD_VBIAS PA 2.6.4.2 Function Specifications The functional specifications of the VBIAS-DAC are listed in the following table. Table 14. VBIAS-DAC specifications Symbol Parameter N Resolution FS SNDR Clock rate Signal-to-noise-and-distortion ratio (10KHz sine wave with 1.0V swing) TS VO,max Settling time (99% full-swing settling) Maximum output CL Output loading capacitance DNL Differential nonlinearity (code 20 ~ 970) INL Integral nonlinearity (code 20 ~ 970) DVDD Digital power supply AVDD T Analog power supply Operating temperature ION Current consumption (power-on state) IOFF Current consumption (power-down state) Min. 1.0833 Typ. 10 50 1000 1.0 2.0 0.9 1.0 2.6 2.8 20 300 Max. 2.1666 5 AVDD  0.2 1.1 3.0 85 1 Unit Bit MS/s dB us V pF LSB LSB V V C uA uA MediaTek Confidential © 2013 MediaTek Inc. Page 48 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.6.5 AUXADC 2.6.5.1 Block Descriptions The auxiliary ADC measures ADC and is the resistive touch panel controller. The auxiliary ADC includes the following functional blocks: 1. Analog multiplexer: Selects signal from one of the auxiliary input channels. There are 16 input channels of AUXADC. Some are for internal voltage measuring and some for external voltage measuring. Environmental messages to be monitored, e.g. temperature, should be transferred to the voltage domain. 2. 12-bit A/D converter: Converts the multiplexed input signal to 12-bit digital data. The touch screen controller drives the external touch panel via Pads XP, XM, YP and YM, and AUXADC as a voltage meter, obtains the X/Y-position of the touched point on the external touch screen. The touch screen interface contains 3 main blocks, which are touch screen pads control logic, ADC interface logic and interrupt generation logic. The touch screen interface supports 2 conversion modes, separate X/Y position conversion mode and auto (sequential) X/Y position conversion mode. See for brief descriptions of AUXADC input channels. AVDD AVDD PAD_XP PAD_YP PAD_XM PAD_YM S/H PAD_AUXIN<4:0> 5 Pen Interrupt VRB VRT ADC DO<11:0> Digital Controller MUX Figure 15. Block diagram of AUXADC Table 15. Definitions of AUXADC channels AUXADC channel ID Channel 0 Channel 1 Channel 2 MediaTek Confidential Description External use (AUX_IN0) External use (AUX_IN1) NA © 2013 MediaTek Inc. Page 49 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A AUXADC channel ID Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Description NA Optional external use (AUX_IN4) NA NA NA NA NA NA NA XM (touch panel) XP (touch panel) YP (touch panel) YM (touch panel) 2.6.5.2 Function Specifications See the table below for the function specifications of auxiliary ADC. Table 16. AUXADC specifications Symbol Parameter Min. Typ. Max. Unit N Resolution FC Clock rate FS Sampling rate @ N-Bit Input swing 0 Input capacitance CIN Unselected channel Selected channel Input resistance RIN Unselected channel 400 Clock latency DNL Differential nonlinearity INL Integral nonlinearity OE Offset error FSE Full swing error Signal to noise and distortion ratio (10kHz full SINAD 62 swing input & 1.0833MHz clock rate) DVDD Digital power supply 1.0 MediaTek Confidential © 2013 MediaTek Inc. 12 4 4/(N+4) AVDD Bit MHz MSPS V 50 fF 4 pF N+4 +1.0/-1.0 +1.0/-1.0 +/- 5 +/- 5 68 1.1 MΩ 1/FC LSB LSB mV mV dB 1.2 V Page 50 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Parameter AVDD T Analog power supply Operating temperature Current consumption  Power-up  Power-down Ztp Supports touch panel impedance Min. 1.75 -20 200 Typ. 1.8 250 1 Max. 1.85 80 2K Unit V °C uA uA Ω 2.6.6 Clock Squarer 2.6.6.1 Block Descriptions For most VCXO, the output clock waveform is sinusoidal with too small amplitude (about several hundred mV) to make MT6589 digital circuits function well. Clock squarer is designed to convert such a small signal to a rail-to-rail clock signal with excellent duty-cycle. 2.6.6.2 Function Specifications See the table below for the function specifications of clock squarer. Table 17. Clock squarer 1 & 2 specifications Symbol Parameter Fin Fout Input clock frequency Output clock frequency Vin Input signal amplitude DcycIN DcycOUT Input signal duty cycle Output signal duty cycle TR Rise time on pin CLKSQOUT TF Fall time on pin CLKSQOUT DVDD Digital power supply AVDD T Analog power supply Operating temperature Current consumption Min. 13 13 350 DcycIN-5 1.0 1.7 -20 Typ. 26 26 500 50 1.1 1.8 500 Max. 1,000 DcycIN+5 5 5 1.2 1.9 80 Unit MHz MHz mVpp % % ns/pF ns/pF V V ℃ uA 2.6.7 Phase Locked Loop 2.6.7.1 Block Descriptions There are total 10 PLLs in PLL macro, providing several clocks for CPU, BUS, modem, analog modem, GPU, Wi-Fi, BlueTooth and GPS. The usage of each PLL is listed below: MediaTek Confidential © 2013 MediaTek Inc. Page 51 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Table 18. MT6572 PLL list 2.6.7.2 Function Specifications See the table below for the function specifications of PLL. Table 19. ARMPLL specifications Symbol Fin Fout DVDD AVDD T Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Min. 754 47 0.95 1.7 -20 Typ. 26 20 50 30 1.05 1.8 Max. 1,508 53 1.15 1.9 80 Unit MHz MHz us % ps V V °C MediaTek Confidential © 2013 MediaTek Inc. Page 52 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Parameter Current consumption Power-down current consumption Min. Typ. Max. Unit 1.2 mA 1 uA Table 20. MAINPLL specifications Symbol Fin Fout DVDD AVDD T Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. 500 47 0.95 1.7 -20 Typ. 26 806 20 50 60 1.05 1.8 0.8 Max. 884 53 1.15 1.9 80 1 Unit MHz MHz us % ps V V °C mA uA Table 21. UNIVPLL specifications Symbol Fin Fout DVDD AVDD T Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. N/A 45 0.95 1.7 -20 Typ. 26 624 20 50 60 1.05 1.8 0.8 Max. N/A 55 1.15 1.9 80 1 Unit MHz MHz us % ps V V °C mA uA Table 22. MDPLL specifications Symbol Fin Fout Parameter Input clock frequency Output clock frequency Settling time Min. N/A Typ. 26 416 20 w/o Calib Max. N/A Unit MHz MHz us MediaTek Confidential © 2013 MediaTek Inc. Page 53 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Parameter DVDD AVDD T Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. Typ. Max. Unit 100 w/I Calib 47 50 53 % 30 ps 0.95 1.05 1.15 V 1.7 1.8 1.9 V -20 80 °C 2.5 mA 1 uA Table 23. WPLL specifications Symbol Fin Fout DVDD AVDD T Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. N/A 47 0.95 1.7 -20 Typ. 26 245.76 20 50 60 1.05 1.8 0.8 Max. N/A 53 1.15 1.9 80 1 Unit MHz MHz us % ps V V °C mA uA Table 24. WHPLL specifications Symbol Fin Fout DVDD AVDD T Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. N/A 47 0.95 1.7 -20 Typ. 26 250.25 20 50 60 1.05 1.8 0.8 Max. N/A 53 1.15 1.9 80 1 Unit MHz MHz us % ps V V °C mA uA MediaTek Confidential © 2013 MediaTek Inc. Page 54 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Table 25. MCUPLL1 specifications Symbol Fin Fout DVDD AVDD T Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. 47 0.95 1.7 -20 Typ. 26 481 20 50 60 1.05 1.8 2 Max. 53 1.15 1.9 80 1 Unit MHz MHz us % ps V V °C mA uA Below table shows the function specifications of the CONN_PLL. Table 26. BTPLL specifications Symbol Fin Fout Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle PN Spur 416MHz spur DVDD AVDD T Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. N/A 47 0.95 1.7 -20 Typ. 26 832 20 w/o Calib 150 w/I Calib 50 -80@10kHz. -87@100kHz -87@400kHz -87@1MHz -107@10MHz -46@2M -40@26M -40@52M -40@78M <-46@others 1.15 1.8 1 Max. N/A 53 Unit MHz MHz us % dBc/(Hz)^0.5 dBc 1.25 V 1.9 V 80 °C mA 1 uA MediaTek Confidential © 2013 MediaTek Inc. Page 55 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Table 27. WFPLL specifications Symbol Fin Fout Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle PN Spur 960MHz spur DVDD AVDD T Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. N/A 47 0.95 1.7 -20 Typ. 32 960 20 w/o Calib 150 w/I Calib 50 -80@10kHz. -87@100kHz -87@400kHz -87@1MHz -107@10MHz -46@2M -40@26M -40@32M -46@64M -46@96M <-52@others 1.15 1.8 2 Max. N/A 53 Unit MHz MHz us % dBc/(Hz)^0.5 dBc 1.25 V 1.9 V 80 °C mA 1 uA MediaTek Confidential © 2013 MediaTek Inc. Page 56 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.6.8 Temperature Sensor 2.6.8.1 Block Descriptions In order to monitor the temperature of CPUs, several temperature sensors are provided. The temperature sensor is made of substrate BJT in the CMOS process. The voltage output of temperature sensor is measured by AUXADC. 2.6.8.2 Function Specifications See the table below for the function specifications of temperature sensor. Table 28. Temperature sensor specifications Symbol Parameter Resolution Temperature range Accuracy Active current Quiescent current Min. Typ. Max. Unit 0.15 °C 0 85 °C -5 5 °C 300 uA 3 uA 2.6.9 Connectivity ABB The analog blocks include the following analog functions for complete connectivity analog base-band signal processing:  WBRX, Wi-Fi and BT receiver analog based-band  WBTX, Wi-Fi and BT transmitter analog based-band  GPSRX, GPS receiver analog based-band For the Wi-Fi and BT in ISM-band, there is only one ISM can be used at the same time. Use TDD (Time-Division-Duplex) to dynamically switch between Wi-Fi and BT mode. 2.6.9.1 Wi-Fi/BT RX The Wi-Fi/BT receiver (Rx) performs connectivity baseband I/Q channels analog-to-digital conversion:  Analog input buffer: Deliver driving capability.  A/D converter: I/Q channels of ADCs perform I/Q digitization for further digital signal processing. MediaTek Confidential © 2013 MediaTek Inc. Page 57 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A At the same time, there is only one standard that is operating for Wi-Fi/BT (ISM-band). WB_RXIP WB_RXIN WB_RXQP WB_RXQN I_AD Q_AD Figure 16. Wi-Fi/BT receiver analog based-band 2.6.9.2 WB RX Function Specifications See the table below for the function specifications of the Wi-Fi/BT base-band receiver. Table 29. Wi -Fi/BT receiver specifications Symbol VIN VCM FS RIN VOS DR AVDD18 T Parameter Differential analog input voltage (peak-to-peak) Common mode input voltage Input clock frequency Clock rate (WiFi-mode) Clock rate (BT-mode) Differential input resistance WiFi-mode BT-mode Differential input referred offset Dynamic range WF:Sig=20M@-10dBF BW=+-20M@fs=80M BT:Sig=1M@-10dBF BW=+1M@fs=32M GPS:Sig=4M@-10dBF BW=+-8M@fs=16M Analog power supply Operating temperature Current consumption (per channel)  WF mode  BT mode  Power down Min. Typ. Max. Unit 950 mV 0.5 0.55 0.6 V 80 MHz 32 MHz 3.5 5 6.5 kΩ 14 20 26 kΩ 10 mV WF:53 dB BT:69 1.7 1.8 1.9 V −20 80 °C 2.2 mA 5.8 0.001 MediaTek Confidential © 2013 MediaTek Inc. Page 58 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.6.9.3 Wi -Fi/BT TX WB_TXIP WB_TXIN WB_TXQP WB_TXQN I_DA Q_DA Figure 17. Wi -Fi/BT transmitter analog based-band 2.6.9.4 WB TX Function Specifications See the table below for the function specifications of the Wi -Fi/BT base-band transmitter. Table 30. Wi-Fi/BT transmitter specifications Symbol VIN VCM FS BW VOS IM3 A-die loading AVDD18 T Parameter Differential analog input voltage (peak-to-peak) Common mode input voltage Input clock frequency Clock rate (WiFi-mode) Clock rate (BT-mode) LPF bandwidth WiFi-mode BT-mode Differential input referred offset IM3 WiFi-mode 38M@-11dBm+40M@-11dBm BT-mode 0.5M@4dBm+0.6M@4dBm Analog power supply Operating temperature Current consumption (per channel) WF mode BT mode Power down Min. Typ. 2 0.6 0.65 480 64 55 12 WF:60 BT:34 10p//1.3k 1.7 1.8 −20 8.7 3.4 0.001 Max. 0.7 30 1.9 80 Unit V V MHz MHz MHz mV dB F//ohm V °C mA MediaTek Confidential © 2013 MediaTek Inc. Page 59 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.6.9.5 GPS RX The GPS receiver (Rx) performs connectivity baseband I/Q channels analog-to-digital conversion:  Analog input buffer: Deliver driving capability.  A/D converter: I/Q channels of ADCs perform I/Q digitization for further digital signal processing. GPS_RXIP GPS_RXIN GPS_RXQP GPS_RXQN I_AD Q_AD Figure 18. GPS receiver analog based-band 2.6.9.6 GPS Function Specifications See the table below for the function specifications of the GPS base-band receiver. There are two modes for GPS; one is 16MHz, and the other is 64MHz sampling clock. Table 31 . GPS receiver specifications Symbol VIN VCM Parameter Differential analog input voltage (peak-to-peak) Common mode input voltage FS Input clock frequency RIN VOS DR AVDD18 T Differential input resistance Differential input referred offset Dynamic range GPS:Sig=4M@-10dBF BW=+-8M@fs=16M Analog power supply Operating temperature Current consumption (per channel) Min. Typ. 950 0.5 0.55 16 64 14 20 52 1.7 1.8 −20 Max. 0.6 26 10 1.9 80 Unit mV V MHz kΩ mV dB V °C MediaTek Confidential © 2013 MediaTek Inc. Page 60 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX Symbol Parameter  Power on-16MHz mode  Power down MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Min. Typ. Max. Unit 1.8 mA 0.001 MediaTek Confidential © 2013 MediaTek Inc. Page 61 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX 2.7 Package Information 2.7.1 Package Outlines MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A Figure 19 Outlines and dimensions of TFBGA 10.6mm*10.6mm, 428-ball, 0.4mm pitch package 2.7.2 Symbol Thermal Operating Specifications Table 32 Thermal operating specifications Description Value Unit Maximum operating junction 125 °C temperature Package thermal resistances in nature convection °C/Watt Note MediaTek Confidential © 2013 MediaTek Inc. Page 62 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.7.3 Lead-free Packaging The chip is provided in a lead-free package and meets RoHS requirements. MediaTek Confidential © 2013 MediaTek Inc. Page 63 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX 2.8 Ordering Information 2.8.1 Top Marking Definition MT6572 HSPA+ Smartphone Application Processor Technical Brief Confidential A MT6572 %A DDDD - #### LLLLL MTXXXXXX %: DDDD: ####: LLLLL: S: Part No. W : WCDMA T : TD-SCDMA E : Edge Date Code Subcontractor Code Die Lot No. Special Code Figure 20. Top mark of MT6572 MediaTek Confidential © 2013 MediaTek Inc. Page 64 of 64 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. loginid=longjiang.zeng@nbbsw.com,time=2013-01-07 12:43:58,ip=218.75.87.37,doctitle=MT6572 HSPA Smartphone Application Processor Technical Brief v1.0.pdf,company=Bird_WCX

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