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W25Q64FV 3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI Publication Release Date: December 19, 2011 -1- Revision D W25Q64FV Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................... 5 2. FEATURES ....................................................................................................................................... 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS........................................................................... 6 3.1 Pin Configuration SOIC 208-mil ........................................................................................... 6 3.2 Pad Configuration WSON 6x5-mm / 8X6-mm ..................................................................... 6 3.3 Pin Configuration PDIP 300-mil ............................................................................................ 7 3.4 Pin Description SOIC 208-mil, WSON 6x5/8x6-mm and PDIP 300-mil ............................... 7 3.5 Pin Configuration SOIC 300-mil ........................................................................................... 8 3.6 Pin Description SOIC 300-mil............................................................................................... 8 3.7 Ball Configuration TFBGA 8x6-mm ...................................................................................... 9 3.8 Ball Description TFBGA 8x6-mm ......................................................................................... 9 4. PIN DESCRIPTIONS ...................................................................................................................... 10 4.1 Chip Select (/CS) ................................................................................................................ 10 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)................................... 10 4.3 Write Protect (/WP) ............................................................................................................ 10 4.4 HOLD (/HOLD) ................................................................................................................... 10 4.5 Serial Clock (CLK) .............................................................................................................. 10 5. BLOCK DIAGRAM .......................................................................................................................... 11 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 12 6.1 SPI/QPI OPERATIONS ...................................................................................................... 12 6.1.1 Standard SPI Instructions.....................................................................................................12 6.1.2 Dual SPI Instructions ............................................................................................................12 6.1.3 Quad SPI Instructions...........................................................................................................13 6.1.4 QPI Instructions ....................................................................................................................13 6.1.5 Hold Function .......................................................................................................................13 6.2 WRITE PROTECTION ....................................................................................................... 14 6.2.1 Write Protect Features .........................................................................................................14 7. STATUS REGISTERS AND INSTRUCTIONS ............................................................................... 15 7.1 STATUS REGISTERS........................................................................................................ 15 7.1.1 BUSY....................................................................................................................................15 7.1.2 Write Enable Latch (WEL)....................................................................................................15 7.1.3 Block Protect Bits (BP2, BP1, BP0)......................................................................................15 7.1.4 Top/Bottom Block Protect (TB) .............................................................................................15 7.1.5 Sector/Block Protect (SEC) ..................................................................................................15 7.1.6 Complement Protect (CMP)..................................................................................................16 7.1.7 Status Register Protect (SRP1, SRP0).................................................................................16 7.1.8 Erase/Program Suspend Status (SUS) ................................................................................16 -2- W25Q64FV 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) ........................................................................16 7.1.10 Quad Enable (QE) ..............................................................................................................17 7.1.11 W25Q64FV Status Register Memory Protection (CMP = 0)...............................................18 7.1.12 W25Q64FV Status Register Memory Protection (CMP = 1)...............................................19 7.2 INSTRUCTIONS................................................................................................................. 20 7.2.1 Manufacturer and Device Identification ................................................................................20 7.2.2 Instruction Set Table 1 (Standard SPI Instructions) .............................................................21 7.2.3 Instruction Set Table 2 (Dual SPI Instructions).....................................................................22 7.2.4 Instruction Set Table 3 (Quad SPI Instructions) ...................................................................22 7.2.5 Instruction Set Table 4 (QPI Instructions).............................................................................23 7.2.6 Write Enable (06h) ...............................................................................................................25 7.2.7 Write Enable for Volatile Status Register (50h)....................................................................25 7.2.8 Write Disable (04h)...............................................................................................................26 7.2.9 Read Status Register-1 (05h) and Read Status Register-2 (35h) ........................................26 7.2.10 Write Status Register (01h) ................................................................................................27 7.2.11 Read Data (03h) .................................................................................................................29 7.2.12 Fast Read (0Bh) .................................................................................................................30 7.2.13 Fast Read Dual Output (3Bh) .............................................................................................32 7.2.14 Fast Read Quad Output (6Bh)............................................................................................33 7.2.15 Fast Read Dual I/O (BBh)...................................................................................................34 7.2.16 Fast Read Quad I/O (EBh) .................................................................................................36 7.2.17 Word Read Quad I/O (E7h) ................................................................................................39 7.2.18 Octal Word Read Quad I/O (E3h).......................................................................................41 7.2.19 Set Burst with Wrap (77h) ..................................................................................................43 7.2.20 Page Program (02h) ...........................................................................................................44 7.2.21 Quad Input Page Program (32h) ........................................................................................46 7.2.22 7.2.23 7.2.24 7.2.25 7.2.26 Sector Erase (20h) .............................................................................................................47 32KB Block Erase (52h) .....................................................................................................48 64KB Block Erase (D8h).....................................................................................................49 Chip Erase (C7h / 60h).......................................................................................................50 Erase / Program Suspend (75h).........................................................................................51 7.2.27 Erase / Program Resume (7Ah) .........................................................................................53 7.2.28 Power-down (B9h) ..............................................................................................................54 7.2.29 Release Power-down / Device ID (ABh) .............................................................................55 7.2.30 Read Manufacturer / Device ID (90h) .................................................................................57 7.2.31 Read Manufacturer / Device ID Dual I/O (92h) ...................................................................58 7.2.32 Read Manufacturer / Device ID Quad I/O (94h) .................................................................59 7.2.33 Read Unique ID Number (4Bh)...........................................................................................60 7.2.34 Read JEDEC ID (9Fh) ........................................................................................................61 7.2.35 Read SFDP Register (5Ah) ................................................................................................62 7.2.36 Erase Security Registers (44h)...........................................................................................65 Publication Release Date: December 19, 2011 -3- Revision D W25Q64FV 7.2.37 Program Security Registers (42h) ......................................................................................66 7.2.38 Read Security Registers (48h) ...........................................................................................67 7.2.39 Set Read Parameters (C0h) ...............................................................................................68 7.2.40 Burst Read with Wrap (0Ch)...............................................................................................69 7.2.41 Enable QPI (38h)................................................................................................................70 7.2.42 Disable QPI (FFh)...............................................................................................................71 7.2.43 Enable Reset (66h) and Reset (99h)..................................................................................72 8. ELECTRICAL CHARACTERISTICS............................................................................................... 73 8.1 Absolute Maximum Ratings................................................................................................ 73 8.2 Operating Ranges............................................................................................................... 73 8.3 Power-up Timing and Write Inhibit Threshold .................................................................... 74 8.4 DC Electrical Characteristics .............................................................................................. 75 8.5 AC Measurement Conditions.............................................................................................. 76 8.6 AC Electrical Characteristics .............................................................................................. 77 8.7 AC Electrical Characteristics (cont’d) ................................................................................. 78 8.8 Serial Output Timing........................................................................................................... 79 8.9 Serial Input Timing.............................................................................................................. 79 8.10 HOLD Timing...................................................................................................................... 79 8.11 WP Timing.......................................................................................................................... 79 9. PACKAGE SPECIFICATION .......................................................................................................... 80 9.1 8-Pin SOIC 208-mil (Package Code SS)............................................................................ 80 9.2 8-Pin PDIP 300-mil (Package Code DA) ............................................................................ 81 9.3 8-Pad WSON 6x5-mm (Package Code ZP)....................................................................... 82 9.4 8-Pad WSON 8x6-mm (Package Code ZE)....................................................................... 83 9.5 16-Pin SOIC 300-mil (Package Code SF) .......................................................................... 84 9.6 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array)............................................. 85 10. ORDERING INFORMATION .......................................................................................................... 86 10.1 Valid Part Numbers and Top Side Marking ........................................................................ 87 11. REVISION HISTORY...................................................................................................................... 88 -4- W25Q64FV 1. GENERAL DESCRIPTION The W25Q64FV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-saving packages. The W25Q64FV array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q64FV has 2,048 erasable sectors and 128 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q64FV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification, a 64-bit Unique Serial Number and four 256-bytes Security Registers. 2. FEATURES • Family of SpiFlash Memories – W25Q64FV: 64M-bit / 8M-byte (8,388,608) – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – QPI: CLK, /CS, IO0, IO1, IO2, IO3 • Highest Performance Serial Flash – 104MHz Standard/Dual/Quad SPI clocks – 208/416MHz equivalent Dual/Quad SPI – 50MB/S continuous data transfer rate – More than 100,000 erase/program cycles – More than 20-year data retention • Efficient “Continuous Read” and QPI Mode – Continuous Read with 8/16/32/64-Byte Wrap – As few as 8 clocks to address memory – Quad Peripheral Interface (QPI) reduces instruction overhead – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash • Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down (typ.) – -40°C to +85°C operating range • Flexible Architecture with 4KB sectors – Uniform Sector Erase (4K-bytes) – Uniform Block Erase (32K and 64K-bytes) – Program 1 to 256 byte per programmable page – Erase/Program Suspend & Resume • Advanced Security Features – Software and Hardware Write-Protect – Top/Bottom, 4KB complement array protection – Power Supply Lock-Down and OTP protection – 64-Bit Unique ID for each device – Discoverable Parameters (SFDP) Register – 3X256-Bytes Security Registers with OTP locks – Volatile & Non-volatile Status Register Bits • Space Efficient Packaging – 8-pin SOIC 208-mil – 8-pad WSON 6x5-mm/8x6-mm – 16-pin SOIC 300-mil – 8-pin PDIP 300-mil – 24-ball TFBGA 8x6-mm – Contact Winbond for KGD and other options Publication Release Date: December 19, 2011 -5- Revision D W25Q64FV 3. PACKAGE TYPES AND PIN CONFIGURATIONS W25Q64FV is offered in an 8-pin SOIC 208-mil (package code SS), an 8-pad WSON 6x5-mm or 8x6-mm (package code ZP & ZE), an 8-pin PDIP 300-mil (package code DA), a 16-pin SOIC 300-mil (package code SF) and a 24-ball 8x6-mm TFBGA (package code TC) as shown in Figure 1a-e respectively. Package diagrams and dimensions are illustrated at the end of this datasheet. 3.1 Pin Configuration SOIC 208-mil Top View /CS 1 8 DO (IO1) /WP (IO2) GND 2 7 3 6 4 5 VCC /HOLD (IO3) CLK DI (IO0) Figure 1a. W25Q64FV Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 3.2 Pad Configuration WSON 6x5-mm / 8X6-mm Top View /CS 18 VCC DO (IO1) /WP (IO2) GND 27 36 45 /HOLD (IO3) CLK DI (IO0) Figure 1b. W25Q64FV Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code ZP & ZE) -6- W25Q64FV 3.3 Pin Configuration PDIP 300-mil Top View /CS 1 8 DO (IO1) 2 7 /WP (IO2) 3 6 GND 4 5 VCC /HOLD (IO3) CLK DI (IO0) Figure 1c. W25Q64FV Pin Assignments, 8-pin PDIP 300-mil (Package Code DA) 3.4 Pin Description SOIC 208-mil, WSON 6x5/8x6-mm and PDIP 300-mil PIN NO. 1 2 3 4 5 6 7 8 PIN NAME /CS DO (IO1) /WP (IO2) GND DI (IO0) CLK /HOLD (IO3) VCC I/O FUNCTION I Chip Select Input I/O Data Output (Data Input Output 1)*1 I/O Write Protect Input ( Data Input Output 2)*2 Ground I/O Data Input (Data Input Output 0)*1 I Serial Clock Input I/O Hold Input (Data Input Output 3)*2 Power Supply *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions Publication Release Date: December 19, 2011 -7- Revision D W25Q64FV 3.5 Pin Configuration SOIC 300-mil /HOLD (IO3) VCC NC NC NC NC /CS DO (IO1) Top View 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 CLK DI (IO0) NC NC NC NC GND /WP (IO2) Figure 1d. W25Q64FV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 3.6 Pin Description SOIC 300-mil PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME /HOLD (IO3) VCC N/C N/C N/C N/C /CS DO (IO1) /WP (IO2) GND N/C N/C N/C N/C DI (IO0) CLK I/O FUNCTION I/O Hold Input (Data Input Output 3)*2 Power Supply No Connect No Connect No Connect No Connect I Chip Select Input I/O Data Output (Data Input Output 1)*1 I/O Write Protect Input (Data Input Output 2)*2 Ground No Connect No Connect No Connect No Connect I/O Data Input (Data Input Output 0)*1 I Serial Clock Input *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions -8- W25Q64FV 3.7 Ball Configuration TFBGA 8x6-mm Top View A1 A2 A3 A4 NC NC NC NC B1 B2 B3 B4 NC CLK GND VCC C1 C2 C3 C4 NC /CS NC /WP (IO2) D1 D2 D3 D4 NC DO(IO1) DI(IO0) /HOLD(IO3) E1 E2 E3 E4 NC NC NC NC F1 F2 F3 F4 NC NC NC NC Figure 1e. W25Q64FV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TC) 3.8 Ball Description TFBGA 8x6-mm BALL NO. B2 B3 B4 C2 C4 D2 D3 D4 Multiple PIN NAME CLK GND VCC /CS /WP (IO2) DO (IO1) DI (IO0) /HOLD (IO3) NC I/O FUNCTION I Serial Clock Input Ground Power Supply I Chip Select Input I/O Write Protect Input (Data Input Output 2)*2 I/O Data Output (Data Input Output 1)*1 I/O Data Input (Data Input Output 0)*1 I/O Hold Input (Data Input Output 3)*2 No Connect *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions Publication Release Date: December 19, 2011 -9- Revision D W25Q64FV 4. PIN DESCRIPTIONS 4.1 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high, the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low, the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up (see “Write Protection” and figure 43). If needed a pullup resister on /CS can be used to accomplish this. 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) The W25Q64FV supports standard SPI, Dual SPI, Quad SPI and QPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual/Quad SPI and QPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3. 4.3 Write Protect (/WP) The Write Protect (/WP) pin can be used to prevent the Status Registers from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. However, when the QE bit of Status Register-2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2. See figure 1a, 1b and 1c for the pin configuration of Quad I/O operation. 4.4 HOLD (/HOLD) The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See figure 1a, 1b and 1c for the pin configuration of Quad I/O operation. 4.5 Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations") - 10 - W25Q64FV Write Protect Logic and Row Decode W25Q64FV 5. BLOCK DIAGRAM SFDP Register 000000h 0000FFh Block Segmentation xxFF00h • xxF000h Sector 15 (4KB) xxFFFFh • xxF0FFh xxEF00h • xxE000h Sector 14 (4KB) xxEFFFh • xxE0FFh xxDF00h • xxD000h Sector 13 (4KB) xxDFFFh • xxD0FFh • • • xx2F00h • xx2000h xx1F00h • xx1000h xx0F00h • xx0000h Sector 2 (4KB) Sector 1 (4KB) Sector 0 (4KB) xx2FFFh • xx20FFh xx1FFFh • xx10FFh xx0FFFh • xx00FFh /WP (IO2) Write Control Logic Status Register /HOLD (IO3) CLK /CS DI (IO0) DO (IO1) SPI Command & Control Logic High Voltage Generators Page Address Latch / Counter Data Byte Address Latch / Counter Security Register 1 - 3 003000h 002000h 001000h 0030FFh 0020FFh 0010FFh 7FFF00h 7FFFFFh • Block 127 (64KB) • 7F0000h 7F00FFh • • • 40FF00h • Block 64 (64KB) 400000h 3FFF00h • Block 63 (64KB) 3F0000h • • • 20FF00h • Block 32 (64KB) 200000h 1FFF00h • Block 31 (64KB) 1F0000h • • • 00FF00h • 000000h Block 0 (64KB) 40FFFFh • 4000FFh 3FFFFFh • 3F00FFh 20FFFFh • 2000FFh 1FFFFFh • 1F00FFh 00FFFFh • 0000FFh Beginning Page Address Ending Page Address Column Decode And 256-Byte Page Buffer Figure 2. W25Q64FV Serial Flash Memory Block Diagram - 11 - Publication Release Date: December 19, 2011 Revision D 6. FUNCTIONAL DESCRIPTIONS 6.1 SPI/QPI OPERATIONS W25Q64FV Power On Reset (66h + 99h) Device Initialization Reset (66h + 99h) Standard SPI Dual SPI Quad SPI operations Enable QPI (38h) Disable QPI (FFh) QPI operations Figure 3. W25Q64FV Serial Flash Memory Operation Diagram 6.1.1 Standard SPI Instructions The W25Q64FV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS. 6.1.2 Dual SPI Instructions The W25Q64FV supports Dual SPI operation when using instructions such as “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speedcritical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1. - 12 - W25Q64FV 6.1.3 Quad SPI Instructions The W25Q64FV supports Quad SPI operation when using instructions such as “Fast Read Quad Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. 6.1.4 QPI Instructions The W25Q64FV supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable QPI (38h)” instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required. This can significantly reduce the SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time. “Enable QPI (38h)” and “Disable QPI (FFh)” instructions are used to switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction, the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. See Figure 3 for the device operation modes. 6.1.5 Hold Function For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q64FV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI or QPI. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device. - 13 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 6.2 WRITE PROTECTION Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W25Q64FV provides several means to protect the data from inadvertent writes. 6.2.1 Write Protect Features • Device resets when VCC is below threshold • Time delay write disable after Power-up • Write enable/disable instructions and automatic write disable after erase or program • Software and Hardware (/WP pin) write protection using Status Register • Write Protection using Power-down instruction • Lock Down write protection for Status Register until the next power-up • One Time Program (OTP) write protection for array and Security Registers using Status Register* * Note: This feature is available upon special order. Please contact Winbond for details. Upon power-up or at power-down, the W25Q64FV will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits. These settings allow a portion as small as a 4KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction. - 14 - W25Q64FV 7. STATUS REGISTERS AND INSTRUCTIONS The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting and Security Register OTP lock. Write access to the Status Register is controlled by the state of the nonvolatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin. 7.1 STATUS REGISTERS 7.1.1 BUSY BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions. 7.1.2 Write Enable Latch (WEL) Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register. 7.1.3 Block Protect Bits (BP2, BP1, BP0) The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected. 7.1.4 Top/Bottom Block Protect (TB) The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits. 7.1.5 Sector/Block Protect (SEC) The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. - 15 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.1.6 Complement Protect (CMP) The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0. 7.1.7 Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software /WP pin has no control. The Status register can be written to Protection after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware When /WP pin is high the Status register is unlocked and can Unprotected be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Status Register is protected and can not be written to again Lock-Down until the next power-down, power-up cycle.(1) 1 1 X One Time Status Register is permanently protected and can not be Program(2) written to. Note: 1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available upon special order. Please contact Winbond for details. 7.1.8 Erase/Program Suspend Status (SUS) The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle. 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The default state of LB3-0 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently. - 16 - W25Q64FV 7.1.10 Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI and QPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled. QE bit is required to be set to a 1 before issuing an “Enable QPI (38h)” to switch the device from Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode, QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a “1” to a “0”. WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the QE bit should never be set to a 1. S7 S6 S5 S4 S3 S2 S1 S0 STATUS REGISTER PROTECT 0 (non-volatile) SECTOR PROTECT (non-volatile) TOP/BOTTOM PROTECT (non-volatile) BLOCK PROTECT BITS (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS SRP0 SEC TB BP2 BP1 BP0 WEL BUSY Figure 4a. Status Register-1 S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRP1 SUSPEND STATUS COMPLEMENT PROTECT (non-volatile) SECURITY REGISTER LOCK BITS (non-volatile OTP) RESERVED QUAD ENABLE (non-volatile) STATUS REGISTER PROTECT 1 (non-volatile) Figure 4b. Status Register-2 - 17 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.1.11 W25Q64FV Status Register Memory Protection (CMP = 0) STATUS REGISTER(1) W25Q64FV (64M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED PROTECTED DENSITY PORTION(2) X X0 0 0 NONE NONE NONE NONE 0 00 0 1 126 and 127 7E0000h – 7FFFFFh 128KB Upper 1/64 0 00 1 0 124 thru 127 7C0000h – 7FFFFFh 256KB Upper 1/32 0 00 1 1 120 thru 127 780000h – 7FFFFFh 512KB Upper 1/16 0 01 0 0 112 thru 127 700000h – 7FFFFFh 1MB Upper 1/8 0 01 0 1 96 thru 127 600000h – 7FFFFFh 2MB Upper 1/4 0 01 1 0 64 thru 127 400000h – 7FFFFFh 4MB Upper 1/2 0 10 0 1 0 10 1 0 0 10 1 1 0 11 0 0 0 11 0 1 0 11 1 0 0 and 1 0 thru 3 0 thru 7 0 thru 15 0 thru 31 0 thru 63 000000h – 01FFFFh 000000h – 03FFFFh 000000h – 07FFFFh 000000h – 0FFFFFh 000000h – 1FFFFFh 000000h – 3FFFFFh 128KB 256KB 512KB 1MB 2MB 4MB Lower 1/64 Lower 1/32 Lower 1/16 Lower 1/8 Lower 1/4 Lower 1/2 X X1 1 1 0 thru 127 000000h – 7FFFFFh 8MB ALL 1 00 0 1 127 7FF000h – 7FFFFFh 4KB U – 1/2048 1 00 1 0 127 7FE000h – 7FFFFFh 8KB U – 1/1024 1 00 1 1 127 7FC000h – 7FFFFFh 16KB U – 1/512 1 01 0 X 127 7F8000h – 7FFFFFh 32KB U – 1/256 1 10 0 1 0 000000h – 000FFFh 4KB L – 1/2048 1 10 1 0 0 000000h – 001FFFh 8KB L – 1/1024 1 10 1 1 0 000000h – 003FFFh 16KB L – 1/512 1 11 0 X 0 000000h – 007FFFh 32KB L – 1/256 Note: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. - 18 - W25Q64FV 7.1.12 W25Q64FV Status Register Memory Protection (CMP = 1) STATUS REGISTER(1) W25Q64FV (64M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED PROTECTED DENSITY PORTION(2) X X0 0 0 0 thru 127 000000h – 7FFFFFh 8MB ALL 0 00 0 1 0 thru 125 000000h – 7DFFFFh 8,064KB Lower 63/64 0 00 1 0 0 thru 123 000000h – 7BFFFFh 7,936KB Lower 31/32 0 00 1 1 0 thru 119 000000h – 77FFFFh 7,680KB Lower 15/16 0 01 0 0 0 thru 111 000000h – 6FFFFFh 7MB Lower 7/8 0 01 0 1 0 thru 95 000000h – 5FFFFFh 5MB Lower 3/4 0 01 1 0 0 thru 63 000000h – 3FFFFFh 4MB Lower 1/2 0 10 0 1 2 thru 127 020000h – 7FFFFFh 8,064KB Upper 63/64 0 10 1 0 4 thru 127 040000h – 7FFFFFh 7,936KB Upper 31/32 0 10 1 1 8 thru 127 080000h – 7FFFFFh 7,680KB Upper 15/16 0 11 0 0 16 thru 127 100000h – 7FFFFFh 7MB Upper 7/8 0 11 0 1 32 thru 127 200000h – 7FFFFFh 5MB Upper 3/4 0 11 1 0 64 thru 127 400000h – 7FFFFFh 4MB Upper 1/2 X X1 1 1 NONE NONE NONE NONE 1 00 0 1 0 thru 127 000000h – 7FEFFFh 8,188KB L – 2047/2048 1 00 1 0 0 thru 127 000000h – 7FDFFFh 8,184KB L – 1023/1024 1 00 1 1 0 thru 127 000000h – 7FBFFFh 8,176KB L – 511/512 1 01 0 X 0 thru 127 000000h – 7F7FFFh 8,160KB L – 255/256 1 10 0 1 0 thru 127 001000h – 7FFFFFh 8,188KB L – 2047/2048 1 10 1 0 0 thru 127 002000h – 7FFFFFh 8,184KB L – 1023/1024 1 10 1 1 0 thru 127 004000h – 7FFFFFh 8,176KB L – 511/512 1 11 0 X 0 thru 127 008000h – 7FFFFFh 8,160KB L – 255/256 Note: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. - 19 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2 INSTRUCTIONS The Standard/Dual/Quad SPI instruction set of the W25Q64FV consists of thirty six basic instructions that are fully controlled through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. The QPI instruction set of the W25Q64FV consists of twenty four basic instructions that are fully controlled through the SPI bus (see Instruction Set table 4). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all four IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions, addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with every two serial clocks (CLK). Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in figures 5 through 42. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed. 7.2.1 Manufacturer and Device Identification MANUFACTURER ID (MF7 - MF0) Winbond Serial Flash EFh Device ID Instruction W25Q64FV (SPI) W25Q64FV (QPI) (ID7 - ID0) ABh, 90h, 92h, 94h 16h 16h (ID15 - ID0) 9Fh 4017h 6017h - 20 - W25Q64FV 7.2.2 Instruction Set Table 1 (Standard SPI Instructions)(1) INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 CLOCK NUMBER (0 – 7) (8 – 15) (16 – 23) (24 – 31) Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Read Status Register-1 05h Read Status Register-2 35h Write Status Register 01h Page Program 02h Sector Erase (4KB) 20h Block Erase (32KB) 52h Block Erase (64KB) D8h Chip Erase C7h/60h Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Read Data 03h Fast Read Release Powerdown / ID(4) Manufacturer/Device ID(4) 0Bh ABh 90h (S7-S0)(2) (S15-S8)(2) (S7-S0) A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 dummy dummy (S15-S8) A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 dummy dummy A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 dummy 00h JEDEC ID(4) Read Unique ID Read SFDP Register Erase Security Registers(5) Program Security Registers(5) Read Security Registers(5) Enable QPI Enable Reset Reset (MF7-MF0) (ID15-ID8) 9Fh Manufacturer Memory Type 4Bh dummy dummy 5Ah 00h 00h 44h A23-A16 A15-A8 42h A23-A16 A15-A8 48h A23-A16 38h 66h 99h A15-A8 (ID7-ID0) Capacity dummy A7–A0 A7-A0 A7-A0 A7-A0 BYTE 5 (32 – 39) BYTE 6 (40 – 47) D7-D0 D7-D0(3) (D7-D0) dummy (ID7-ID0)(2) (MF7-MF0) (D7-D0) (ID7-ID0) dummy dummy (UID63-UID0) (D7-0) D7-D0 dummy D7-D0(3) (D7-D0) - 21 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.3 Instruction Set Table 2 (Dual SPI Instructions) INSTRUCTION NAME BYTE 1 CLOCK NUMBER (0 – 7) BYTE 2 (8 – 15) BYTE 3 (16 – 23) BYTE 4 (24 – 31) Fast Read Dual Output Fast Read Dual I/O Manufacturer/Device ID by Dual I/O(4) 3Bh BBh 92h A23-A16 A23-A8(6) A23-A8(6) A15-A8 A7-A0, M7-M0 (6) A7-A0 (D7-D0, …)(7) A7-A0, M7-M0 (6) (MF7-MF0, ID7-ID0) BYTE 5 (32 – 39) dummy BYTE 6 (40 – 47) (D7-D0, …)(7) 7.2.4 Instruction Set Table 3 (Quad SPI Instructions) INSTRUCTION NAME BYTE 1 CLOCK NUMBER (0 – 7) BYTE 2 (8 – 15) BYTE 3 (16 – 23) BYTE 4 (24 – 31) Quad Page Program Fast Read Quad Output Fast Read Quad I/O 32h 6Bh EBh Word Read Quad I/O(12) E7h Octal Word Read Quad I/O(13) E3h Set Burst with Wrap 77h Manufacture/Device ID by Quad I/O(4) 94h A23-A16 A23-A16 A23-A0, M7-M0(8) A23-A0, M7-M0(8) A23-A0, M7-M0(8) xxxxxx, W6-W4(8) A23-A0, M7-M0(8) A15-A8 A15-A8 A7-A0 A7-A0 (xxxx, D7-D0)(10) (D7-D0, …)(9) (xx, D7-D0)(11) (D7-D0, …)(9) (D7-D0, …)(9) xxxx, (MF7-MF0, (MF7-MF0, ID7-ID0) ID7-ID0, …) BYTE 5 (32 – 39) D7-D0, …(9) dummy BYTE 6 (40 – 47) D7-D0, …(3) (D7-D0, …)(9) - 22 - W25Q64FV 7.2.5 Instruction Set Table 4 (QPI Instructions)(14) INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 CLOCK NUMBER (0 , 1) (2 , 3) (4 , 5) Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Read Status Register-1 05h Read Status Register-2 35h Write Status Register 01h Page Program 02h Sector Erase (4KB) 20h Block Erase (32KB) 52h Block Erase (64KB) D8h Chip Erase C7h/60h Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Set Read Parameters C0h Fast Read 0Bh Burst Read with Wrap(16) 0Ch Fast Read Quad I/O Release Powerdown / ID(4) Manufacturer/Device ID(4) EBh ABh 90h (S7-S0)(2) (S15-S8)(2) (S7-S0) A23-A16 A23-A16 A23-A16 A23-A16 P7-P0 A23-A16 A23-A16 A23-A16 dummy dummy (S15-S8) A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 dummy dummy JEDEC ID(4) Disable QPI Enable Reset Reset (MF7-MF0) (ID15-ID8) 9Fh Manufacturer Memory Type FFh 66h 99h BYTE 4 (6 , 7) A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 dummy 00h (ID7-ID0) Capacity BYTE 5 (8 , 9) D7-D0(9) dummy(15) dummy(15) M7-M0(15) (ID7-ID0)(2) (MF7-MF0) BYTE 6 (10 , 11) D7-D0(3) (D7-D0) (D7-D0) (D7-D0) (ID7-ID0) - 23 - Publication Release Date: December 19, 2011 Revision D W25Q64FV Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data output from the device on either 1, 2 or 4 IO pins. 2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction. 3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 4. See Manufacturer and Device Identification table for device ID information. 5. Security Register Address: Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address 6. Dual SPI address input format: IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 7. Dual SPI data output format: IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 8. Quad SPI address input format: IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 Set Burst with Wrap input format: IO0 = x, x, x, x, x, x, W4, x IO1 = x, x, x, x, x, x, W5, x IO2 = x, x, x, x, x, x, W6, x IO3 = x, x, x, x, x, x, x, x 9. Quad SPI data input/output format: IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3, …..) 10. Fast Read Quad I/O data output format: IO0 = (x, x, x, x, D4, D0, D4, D0) IO1 = (x, x, x, x, D5, D1, D5, D1) IO2 = (x, x, x, x, D6, D2, D6, D2) IO3 = (x, x, x, x, D7, D3, D7, D3) 11. Word Read Quad I/O data output format: IO0 = (x, x, D4, D0, D4, D0, D4, D0) IO1 = (x, x, D5, D1, D5, D1, D5, D1) IO2 = (x, x, D6, D2, D6, D2, D6, D2) IO3 = (x, x, D7, D3, D7, D3, D7, D3) 12. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0) 13. For Octal Word Read Quad I/O, the lowest four address bits must be 0. (A3, A2, A1, A0 = 0) 14. QPI Command, Address, Data input/output format: CLK # 0 1 2 3 4 5 67 IO0 = C4, C0, A20, A16, A12, A8, A4, A0, IO1 = C5, C1, A21, A17, A13, A9, A5, A1, IO2 = C6, C2, A22, A18, A14, A10, A6, A2, IO3 = C7, C3, A23, A19, A15, A11, A7, A3, 89 D4, D0, D5, D1, D6, D2, D7, D3, 10 11 D4, D0 D5, D1 D6, D2 D7, D3 15. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is controlled by read parameter P7 – P4. 16. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0. - 24 - W25Q64FV 7.2.6 Write Enable (06h) The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. /CS CLK Mode 3 Mode 0 DI (IO0) DO (IO1) 012345 Instruction (06h) 67 Mode 3 Mode 0 High Impedance /CS CLK IO0 Mode 3 Mode 0 01 Instruction 06h Mode 3 Mode 0 IO1 IO2 IO3 Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right) 7.2.7 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register nonvolatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bit values. /CS CLK Mode 3 Mode 0 DI (IO0) DO (IO1) 012345 Instruction (50h) 67 Mode 3 Mode 0 High Impedance /CS CLK IO0 Mode 3 Mode 0 01 Instruction 50h Mode 3 Mode 0 IO1 IO2 IO3 Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right) - 25 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.8 Write Disable (04h) The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase and Reset instructions. /CS CLK Mode 3 Mode 0 DI (IO0) DO (IO1) 012345 Instruction (04h) 67 Mode 3 Mode 0 High Impedance /CS CLK IO0 Mode 3 Mode 0 01 Instruction 04h Mode 3 Mode 0 IO1 IO2 IO3 Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right) 7.2.9 Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 or “35h” for Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8. The Status Register bits are shown in Figure 4a and 4b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0, SRP1, QE, LB3-0, CMP and SUS bits (see Status Register section earlier in this datasheet). The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 8. The instruction is completed by driving /CS high. /CS CLK DI (IO0) DO (IO1) Mode 3 0 Mode 0 * = MSB 123456 Instruction (05h or 35h) High Impedance 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Status Register 1 or 2 out Status Register 1 or 2 out 76543210765432107 * * Figure 8a. Read Status Register Instruction (SPI Mode) - 26 - W25Q64FV /CS CLK IO0 Mode 3 Mode 0 012345 Instruction 05h or 35h 40404 IO1 51515 IO2 62626 IO3 73737 SR1 or SR2 SR1 or SR2 out out Figure 8b. Read Status Register Instruction (QPI Mode) 7.2.10 Write Status Register (01h) The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2, LB1, QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. LB3-0 are nonvolatile OTP bits, once it is set to 1, it can not be cleared to 0. The Status Register bits are shown in Figure 4a and 4b, and described in 7.1. To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as illustrated in figure 9. To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRP1 and LB3, LB2, LB1 can not be changed from “1” to “0” because of the OTP protection for these bits. Upon power off or the execution of a “Reset (99h)” instruction, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored. To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP, QE and SRP1 bits will be cleared to 0. During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle - 27 - Publication Release Date: December 19, 2011 Revision D W25Q64FV and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period. The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to enter and operate in the QPI mode. Please refer to 7.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits are 0. /CS CLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 3 Mode 0 DI (IO0) DO (IO1) * = MSB Instruction (01h) Status Register 1 in Status Register 2 in 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 * * High Impedance Figure 9a. Write Status Register Instruction (SPI Mode) /CS CLK IO0 Mode 3 Mode 0 012345 Instruction 01h SR1 in 40 SR2 in 12 8 Mode 3 Mode 0 IO1 5 1 13 9 IO2 6 2 14 10 IO3 7 3 15 11 Figure 9b. Write Status Register Instruction (QPI Mode) - 28 - W25Q64FV 7.2.11 Read Data (03h) The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in figure 10. If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR (see AC Electrical Characteristics). The Read Data (03h) instruction is only supported in Standard SPI mode. /CS CLK DI (IO0) DO (IO1) Mode 3 0 Mode 0 * = MSB 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Instruction (03h) 24-Bit Address 23 22 21 * High Impedance 3210 Data Out 1 765432107 * Figure 10. Read Data Instruction (SPI Mode only) - 29 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.12 Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in figure 11. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”. /CS CLK DI (IO0) DO (IO1) /CS CLK DI (IO0) DO (IO1) Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction (0Bh) 24-Bit Address 23 22 21 * High Impedance 3210 * = MSB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Dummy Clocks 0 High Impedance Data Out 1 Data Out 2 76543210765432107 * * Figure 11a. Fast Read Instruction (SPI Mode) - 30 - W25Q64FV Fast Read (0Bh) in QPI Mode The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2. /CS CLK IO0 Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Instruction 0Bh A23-16 20 16 A15-8 12 8 A7-0 Dummy* 40404 IOs switch from Input to Output 0404 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 * "Set Read Parameters" instruction (C0h) can set the number of dummy clocks. Figure 11b. Fast Read Instruction (QPI Mode) - 31 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.13 Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data to be transferred from the W25Q64FV at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution. Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 12. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock. /CS CLK DI (IO0) DO (IO1) /CS CLK DI (IO0) DO (IO1) Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction (3Bh) 24-Bit Address 23 22 21 * High Impedance 3210 * = MSB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Dummy Clocks IO0 switches from Input to Output 0 64206420642064206 High Impedance 75317531753175317 * Data Out 1 * Data Out 2 * Data Out 3 * Data Out 4 Figure 12. Fast Read Dual Output Instruction (SPI Mode only) - 32 - W25Q64FV 7.2.14 Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q64FV at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 13. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. /CS CLK IO0 IO1 IO2 IO3 /CS CLK IO0 IO1 IO2 IO3 Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction (6Bh) 24-Bit Address 23 22 21 * High Impedance 3210 High Impedance High Impedance * = MSB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Dummy Clocks 0 High Impedance High Impedance High Impedance IO0 switches from Input to Output 404040404 515151515 626262626 737373737 Byte 1 Byte 2 Byte 3 Byte 4 Figure 13. Fast Read Quad Output Instruction (SPI Mode only) - 33 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.15 Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with “Continuous Read Mode” The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14a. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instruction code, as shown in Figure 14b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFFFh on IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal operation. /CS CLK Mode 3 Mode 0 DI (IO0) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Instruction (BBh) A23-16 A15-8 A7-0 M7-0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 DO (IO1) /CS CLK DI (IO0) * = MSB 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 * * 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 IOs switch from Input to Output 064206420642064206 DO (IO1) 175317531753175317 * Byte 1 * Byte 2 * Byte 3 * Byte 4 Figure 14a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only) - 34 - W25Q64FV /CS CLK Mode 3 Mode 0 DI (IO0) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A23-16 A15-8 A7-0 M7-0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 DO (IO1) /CS CLK DI (IO0) 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 * * * = MSB 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IOs switch from Input to Output 064206420642064206 DO (IO1) 175317531753175317 * Byte 1 * Byte 2 * Byte 3 * Byte 4 Figure 14b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only) - 35 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.16 Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. Fast Read Quad I/O with “Continuous Read Mode” The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 15a. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in Figure 15b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. /CS CLK Mode 3 Mode 0 IO0 IO1 IO2 IO3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Instruction (EBh) A23-16 A15-8 20 16 12 8 A7-0 40 M7-0 40 Dummy Dummy 4 IOs switch from Input to Output 0404 21 17 13 9 5 1 5 1 51515 22 18 14 10 6 2 6 2 62626 23 19 15 11 7 3 7 3 73 Byte 1 73 Byte 2 7 Byte 3 Figure 15a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, SPI Mode) - 36 - W25Q64FV /CS CLK Mode 3 Mode 0 IO0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A23-16 A15-8 20 16 12 8 A7-0 40 M7-0 Dummy Dummy 40 4 IOs switch from Input to Output 0404 IO1 21 17 13 9 5 1 5 1 51515 IO2 22 18 14 10 6 2 6 2 62626 IO3 23 19 15 11 7 3 7 3 73 Byte 1 73 Byte 2 7 Byte 3 Figure 15b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode) Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See 7.2.19 for detail descriptions. - 37 - Publication Release Date: December 19, 2011 Revision D W25Q64FV Fast Read Quad I/O (EBh) in QPI Mode The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 15c. When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default setting, the data output will follow the Continuous Read Mode bits immediately. “Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please refer to the description on previous pages. “Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch) instruction must be used. Please refer to 7.2.39 for details. /CS CLK IO0 Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Instruction EBh A23-16 A15-8 A7-0 M7-0* IOs switch from Input to Output 20 16 12 8 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 * "Set Read Parameters" instruction (C0h) can set the number of dummy clocks. Figure 15c. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, QPI Mode) - 38 - W25Q64FV 7.2.17 Word Read Quad I/O (E7h) The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word Read Quad I/O Instruction. Word Read Quad I/O with “Continuous Read Mode” The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 16a. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E7h instruction code, as shown in Figure 16b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. /CS CLK Mode 3 Mode 0 IO0 IO1 IO2 IO3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Instruction (E7h) A23-16 A15-8 20 16 12 8 A7-0 40 M7-0 40 Dummy 4 IOs switch from Input to Output 0404 21 17 13 9 5 1 5 1 51515 22 18 14 10 6 2 6 2 62626 23 19 15 11 7 3 7 3 73 Byte 1 73 Byte 2 7 Byte 3 Figure 16a. Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only) - 39 - Publication Release Date: December 19, 2011 Revision D W25Q64FV /CS CLK Mode 3 Mode 0 IO0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 A23-16 A15-8 20 16 12 8 A7-0 40 M7-0 Dummy 40 4 IOs switch from Input to Output 0404 IO1 21 17 13 9 5 1 5 1 51515 IO2 22 18 14 10 6 2 6 2 62626 IO3 23 19 15 11 7 3 7 3 73737 Byte 1 Byte 2 Byte 3 Figure 16b. Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only) Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See 7.2.19 for detail descriptions. - 40 - W25Q64FV 7.2.18 Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read Quad I/O Instruction. Octal Word Read Quad I/O with “Continuous Read Mode” The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 17a. The upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E3h instruction code, as shown in Figure 17b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. /CS CLK Mode 3 Mode 0 IO0 IO1 IO2 IO3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Instruction (E3h) A23-16 A15-8 A7-0 M7-0 IOs switch from Input to Output 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Byte 4 Figure 17a. Octal Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only) - 41 - Publication Release Date: December 19, 2011 Revision D W25Q64FV /CS CLK Mode 3 Mode 0 IO0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 A23-16 A15-8 A7-0 M7-0 IOs switch from Input to Output 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Byte 4 Figure 17b. Octal Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only) - 42 - W25Q64FV 7.2.19 Set Burst with Wrap (77h) In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance. Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction sequence is shown in Figure 18. Wrap bit W7 and the lower nibble W3-0 are not used. W6, W5 00 01 10 11 W4 = 0 Wrap Around Wrap Length Yes 8-byte Yes 16-byte Yes 32-byte Yes 64-byte W4 =1 (DEFAULT) Wrap Around Wrap Length No N/A No N/A No N/A No N/A Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case of a system Reset while W4 = 0, it is recommended that the controller issues a Set Burst with Wrap instruction to reset W4 = 1 prior to any normal Read instructions since W25Q64FV does not have a hardware Reset Pin. In QPI mode, the “Burst Read with Wrap (0Ch)” instruction should be used to perform the Read operation with “Wrap Around” feature. The Wrap Length set by W5-4 in Standard SPI mode is still valid in QPI mode and can also be re-configured by “Set Read Parameters (C0h)” instruction. Refer to 7.2.38 and 7.2.39 for details. /CS CLK Mode 3 Mode 0 IO0 IO1 IO2 IO3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3 Instruction (77h) don't care don't care don't care Wrap Bit Mode 0 X X X X X X w4 X X X X X X X w5 X X X X X X X w6 X XXXXXXXX Figure 18. Set Burst with Wrap Instruction (SPI Mode only) - 43 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.20 Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 19. If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits. /CS CLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 DI (IO0) * = MSB Instruction (02h) 24-Bit Address Data Byte 1 23 22 21 * 321076543210 * /CS 2072 2073 2074 2075 2076 2077 2078 2079 CLK DI (IO0) 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Data Byte 2 Data Byte 3 07654321076543210 * * Data Byte 256 76543210 * Mode 3 Mode 0 Figure 19a. Page Program Instruction (SPI Mode) - 44 - W25Q64FV /CS CLK IO0 Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Instruction 02h A23-16 20 16 A15-8 12 8 A7-0 40 Byte1 40 Byte 2 40 Byte 3 40 IO1 21 17 13 9 5 1 5 1 5 1 5 1 IO2 22 18 14 10 6 2 6 2 6 2 6 2 IO3 23 19 15 11 7 3 7 3 7 3 7 3 516 517 518 519 Byte 255 Byte 256 4040 Mode 3 Mode 0 5151 6262 7373 Figure 19b. Page Program Instruction (QPI Mode) - 45 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.21 Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data. To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. All other functions of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in Figure 20. /CS CLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction (32h) 24-Bit Address IO0 23 22 21 3210 * IO1 IO2 IO3 * = MSB /CS 536 537 538 539 540 541 542 543 CLK IO0 IO1 IO2 IO3 31 32 33 34 35 36 37 Byte 1 Byte 2 Byte 3 0404040 Byte 253 40 Byte 254 40 Byte 255 40 Byte 256 40 515151 51515151 626262 62626262 737373 *** 73737373 **** Figure 20. Quad Input Page Program Instruction (SPI Mode only) Mode 3 Mode 0 - 46 - W25Q64FV 7.2.22 Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2). The Sector Erase instruction sequence is shown in Figure 21a & 21b. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). /CS CLK DI (IO0) DO (IO1) Mode 3 0 Mode 0 * = MSB 123456789 29 30 31 Instruction (20h) 24-Bit Address 23 22 * High Impedance 210 Mode 3 Mode 0 Figure 21a. Sector Erase Instruction (SPI Mode) /CS CLK IO0 Mode 3 Mode 0 01234567 Instruction 20h A23-16 20 16 A15-8 12 8 A7-0 40 Mode 3 Mode 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 Figure 21b. Sector Erase Instruction (QPI Mode) - 47 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.23 32KB Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0). The Block Erase instruction sequence is shown in Figure 22a & 22b. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). /CS CLK DI (IO0) DO (IO1) Mode 3 0 Mode 0 * = MSB 123456789 29 30 31 Instruction (52h) 24-Bit Address 23 22 * High Impedance 210 Mode 3 Mode 0 Figure 22a. 32KB Block Erase Instruction (SPI Mode) /CS CLK IO0 Mode 3 Mode 0 01234567 Instruction 52h A23-16 20 16 A15-8 12 8 A7-0 40 Mode 3 Mode 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 Figure 22b. 32KB Block Erase Instruction (QPI Mode) - 48 - W25Q64FV 7.2.24 64KB Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0). The Block Erase instruction sequence is shown in Figure 23a & 23b. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). /CS CLK DI (IO0) DO (IO1) Mode 3 0 Mode 0 * = MSB 123456789 29 30 31 Instruction (D8h) 24-Bit Address 23 22 * High Impedance 210 Mode 3 Mode 0 Figure 23a. 64KB Block Erase Instruction (SPI Mode) /CS CLK IO0 Mode 3 Mode 0 01234567 Instruction D8h A23-16 20 16 A15-8 12 8 A7-0 40 Mode 3 Mode 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 Figure 23b. 64KB Block Erase Instruction (QPI Mode) - 49 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.25 Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 24. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). /CS CLK Mode 3 Mode 0 DI (IO0) DO (IO1) 01234567 Instruction (C7h/60h) Mode 3 Mode 0 High Impedance /CS CLK IO0 Mode 3 Mode 0 01 Instruction C7h/60h Mode 3 Mode 0 IO1 IO2 IO3 Figure 24. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right) - 50 - W25Q64FV 7.2.26 Erase / Program Suspend (75h) The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in Figure 25a & 25b. The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation. The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of “tSUS” (See AC Characteristics) is required to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within “tSUS” and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction “75h” is not issued earlier than a minimum of time of “tSUS” following the preceding Resume instruction “7Ah”. Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted. It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. /CS CLK Mode 3 Mode 0 DI (IO0) DO (IO1) 01234567 Instruction (75h) High Impedance tSUS Mode 3 Mode 0 Accept instructions Figure 25a. Erase/Program Suspend Instruction (SPI Mode) - 51 - Publication Release Date: December 19, 2011 Revision D W25Q64FV /CS CLK IO0 Mode 3 Mode 0 01 Instruction 75h IO1 IO2 IO3 tSUS Mode 3 Mode 0 Accept instructions Figure 25b. Erase/Program Suspend Instruction (QPI Mode) - 52 - W25Q64FV 7.2.27 Erase / Program Resume (7Ah) The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah” will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 26a & 26b. Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “tSUS” following a previous Resume instruction. /CS CLK Mode 3 Mode 0 DI (IO0) 01234567 Instruction (7Ah) Mode 3 Mode 0 Resume previously suspended Program or Erase Figure 26a. Erase/Program Resume Instruction (SPI Mode) /CS CLK IO0 Mode 3 Mode 0 01 Instruction 7Ah Mode 3 Mode 0 IO1 IO2 IO3 Resume previously suspended Program or Erase Figure 26b. Erase/Program Resume Instruction (QPI Mode) - 53 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.28 Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 27a & 27b. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP (See AC Characteristics). While in the power-down state only the Release from Powerdown / Device ID instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. /CS CLK Mode 3 Mode 0 DI (IO0) 01234567 Instruction (B9h) tDP Mode 3 Mode 0 Stand-by current Power-down current Figure 27a. Deep Power-down Instruction (SPI Mode) /CS CLK IO0 Mode 3 Mode 0 01 Instruction B9h IO1 IO2 IO3 tDP Mode 3 Mode 0 Stand-by current Power-down current Figure 27b. Deep Power-down Instruction (QPI Mode) - 54 - W25Q64FV 7.2.29 Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in Figure 28a & 28b. Release from power-down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 28. The Device ID values for the W25Q64FV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 28c & 28d, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle. /CS CLK Mode 3 Mode 0 DI (IO0) 01234567 Instruction (ABh) tRES1 Mode 3 Mode 0 Power-down current Stand-by current Figure 28a. Release Power-down Instruction (SPI Mode) - 55 - Publication Release Date: December 19, 2011 Revision D W25Q64FV /CS CLK IO0 Mode 3 Mode 0 01 Instruction ABh IO1 IO2 IO3 tRES1 Mode 3 Mode 0 Power-down current Stand-by current Figure 28b. Release Power-down Instruction (QPI Mode) /CS CLK DI (IO0) DO (IO1) Mode 3 0 Mode 0 * = MSB 123456789 29 30 31 32 33 34 35 36 37 38 Instruction (ABh) 3 Dummy Bytes Mode 3 Mode 0 tRES2 23 22 * High Impedance 210 Device ID 76543210 * Power-down current Stand-by current Figure 28c. Release Power-down / Device ID Instruction (SPI Mode) /CS CLK IO0 Mode 3 Mode 0 012345678 tRES2 Instruction ABh 3 Dummy Bytes IOs switch from Input to Output XXXXXX4 0 Mode 3 Mode 0 IO1 XXXXXX5 1 IO2 XXXXXX6 2 IO3 XXXXXX7 3 Device ID Power-down current Stand-by current Figure 28d. Release Power-down / Device ID Instruction (QPI Mode) - 56 - W25Q64FV 7.2.30 Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 29. The Device ID values for the W25Q64FV is listed in Manufacturer and Device Identification table. The instruction is completed by driving /CS high. /CS CLK DI (IO0) DO (IO1) /CS CLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction (90h) Address (000000h) 23 22 21 * High Impedance 3210 * = MSB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Mode 3 Mode 0 DI (IO0) 0 DO (IO1) Manufacturer ID (EFh) 76543210 * Device ID Figure 29. Read Manufacturer / Device ID Instruction (SPI Mode) - 57 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.31 Read Manufacturer / Device ID Dual I/O (92h) The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x speed. The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown in Figure 30. The Device ID values for the W25Q64FV is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. /CS CLK Mode 3 Mode 0 DI (IO0) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Instruction (92h) A23-16 A15-8 A7-0 (00h) M7-0 6420642064206420 DO (IO1) * = MSB High Impedance 7531753175317531 * * * * /CS CLK DI (IO0) DO (IO1) 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 IOs switch from Input to Output 06420642064206420 17531753175317531 * MFR ID * Device ID * MFR ID (repeat) * Device ID (repeat) Mode 3 Mode 0 Note: Figure 30. Read Manufacturer / Device ID Dual I/O Instruction (SPI Mode only) The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction. - 58 - W25Q64FV 7.2.32 Read Manufacturer / Device ID Quad I/O (94h) The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x speed. The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed by a four clock dummy cycles and then a 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 31. The Device ID values for the W25Q64FV is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. /CS CLK Mode 3 Mode 0 IO0 IO1 IO2 IO3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Instruction (94h) High Impedance High Impedance High Impedance A23-16 40 A15-8 40 A7-0 (00h) 40 M7-0 40 Dummy Dummy 4 IOs switch from Input to Output 040 51515151 5151 62626262 6262 73737373 7373 MFR ID Device ID /CS CLK 23 24 25 26 27 28 29 30 Mode 3 Mode 0 IO0 040404040 IO1 151515151 IO2 262626262 IO3 373737373 MFR ID Device ID MFR ID Device ID (repeat) (repeat) (repeat) (repeat) Note: Figure 31. Read Manufacturer / Device ID Quad I/O Instruction (SPI Mode only) The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction. - 59 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.33 Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q64FV device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After which, the 64bit ID is shifted out on the falling edge of CLK as shown in Figure 32. /CS CLK Mode 3 Mode 0 DI (IO0) DO (IO1) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Instruction (4Bh) Dummy Byte 1 Dummy Byte 2 High Impedance /CS CLK DI (IO0) DO (IO1) 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Dummy Byte 3 Dummy Byte 4 * = MSB High Impedance 63 62 61 210 * 64-bit Unique Serial Number 100 101 102 Mode 3 Mode 0 Figure 32. Read Unique ID Number Instruction (SPI Mode only) - 60 - W25Q64FV 7.2.34 Read JEDEC ID (9Fh) For compatibility reasons, the W25Q64FV provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 33a & 33b. For memory type and capacity values refer to Manufacturer and Device Identification table. /CS CLK DI (IO0) DO (IO1) /CS CLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction (9Fh) * = MSB High Impedance Manufacturer ID (EFh) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 3 Mode 0 DI (IO0) DO (IO1) Memory Type ID15-8 Capacity ID7-0 7654321076543210 * * Figure 33a. Read JEDEC ID Instruction (SPI Mode) /CS CLK IO0 Mode 3 Mode 0 012 Instruction 9Fh 3456 IOs switch from Input to Output 12 8 4 0 IO1 13 9 5 1 IO2 14 10 6 2 IO3 15 11 7 3 EFh ID15-8 ID7-0 Mode 3 Mode 0 Figure 33b. Read JEDEC ID Instruction (QPI Mode) - 61 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.35 Read SFDP Register (5Ah) The W25Q64FV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about device configurations, available instructions and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified, but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications, as well as the JEDEC standard JESD216 that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet. The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah” followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight “dummy” clocks are also required before the SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first as shown in Figure 34. For SFDP register values and descriptions, refer to the following SFDP Definition table. Note: 1. A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register. /CS CLK Mode 3 Mode 0 DI (IO0) DO (IO1) 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction (5Ah) 24-Bit Address 23 22 21 * High Impedance 3210 /CS CLK DI (IO0) DO (IO1) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Dummy Byte 076543210 High Impedance * = MSB Data Out 1 Data Out 2 76543210765432107 * * Figure 34. Read SFDP Register Instruction Sequence Diagram (SPI Mode only) - 62 - W25Q64FV Serial Flash Discoverable Parameter (JEDEC JESD216) Definition Table BYTE ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h ...(1) 7Fh 80h 81h 82h 83h 84h 85h 86h 87h DATA DESCRIPTION 53h SFDP Signature 46h SFDP Signature 44h SFDP Signature 50h SFDP Signature 00h SFDP Minor Revision Number 01h SFDP Major Revision Number 00h Number of Parameter Headers (NPH) FFh Reserved 00h PID(3)(0): ID Number 00h PID(0): Parameter Table Minor Revision Number 01h PID(0): Parameter Table Major Revision Number 09h PID(0): Parameter Table Length 80h PID(0): Parameter Table Pointer (PTP) (A7-A0) 00h PID(0): Parameter Table Pointer (PTP) (A15-A8) 00h PID(0): Parameter Table Pointer (PTP) (A23-A16) FFh Reserved FFh Reserved FFh Reserved FFh Reserved Bit[7:5]=111 E5h Bit[4:3]=00 Bit[2] =1 Bit[1:0]=01 Reserved Non-volatile Status Register Page Programmable Supports 4KB Erase 20h 4K-Byte Erase Opcode Bit[7] =1 Bit[6] =1 Bit[5] =1 F1h Bit[4] =1 Bit[3] =0 Bit[2:1]=00 Bit[0] =1 Reserved Supports (1-1-4) Fast Read Supports (1-4-4) Fast Read Supports (1-2-2) Fast Read Not support Dual Transfer Rate 3-Byte/24-Bit Only Addressing Supports (1-1-2) Fast Read FFh Reserved FFh Flash Size in Bits FFh Flash Size in Bits FFh Flash Size in Bits 03h Flash Size in Bits COMMENT SFDP Signature = 50444653h JEDEC JESD216 1 Parameter Header 00h = JEDEC specified JEDEC JESD216 9 Dwords(2) PID(0) Pointer = 000080h 64 Mega Bits = 03FFFFFFh - 63 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 88h 44h Bit[7:5]=010 Bit[4:0]=00100 8 Mode Bits are needed 16 Dummy Bits are needed 89h EBh Quad Input Quad Output Fast Read Opcode 8Ah 08h Bit[7:5]=000 No Mode Bits are needed Bit[4:0]=01000 8 Dummy Bits are needed 8Bh 6Bh Single Input Quad Output Fast Read Opcode 8Ch 08h Bit[7:5]=000 Bit[4:0]=01000 No Mode Bits are needed 8 Dummy Bits are needed 8Dh 3Bh Single Input Dual Output Fast Read Opcode 8Eh 80h Bit[7:5]=100 8 Mode bits are needed Bit[4:0]=00000 No Dummy bits are needed 8Fh BBh Dual Input Dual Output Fast Read Opcode Bit[7:5]=111 Reserved 90h FEh Bit[4] =1 Bit[3:1]=111 Not support (4-4-4) Fast Read Reserved Bit[0] =0 Not support (2-2-2) Fast Read 91h FFh Reserved Fast Read Quad I/O Setting Fast Read Quad Output Setting Fast Read Dual Output Setting Fast Read Dual I/O Setting 92h FFh Reserved 93h FFh Reserved 94h FFh Reserved 95h FFh Reserved 96h 00h No Mode Bits or Dummy Bits for (2-2-2) Fast Read 97h 00h Not support (2-2-2) Fast Read 98h FFh Reserved 99h FFh Reserved 9Ah 44h Bit[7:5]=010 Bit[4:0]=00100 8 Mode Bits are needed 16 Dummy Bits are needed 9Bh EBh Support (4-4-4) Fast Read 9Ch 0Ch Sector Type 1 Size (4KB) 9Dh 20h Sector Type 1 Opcode 9Eh 0Fh Sector Type 2 Size (32KB) Sector Erase Type & Opcode 9Fh 52h Sector Type 2 Opcode A0h 10h Sector Type 3 Size (64KB) A1h D8h Sector Type 3 Opcode A2h 00h Sector Type 4 Size (256KB) – Not supported Sector Erase Type & Opcode A3h ...(1) 00h Sector Type 4 Opcode – Not supported FFh Reserved FFh FFh Reserved Notes: 1. 2. 3. Data stored in Byte Address 10h to 7Fh & A4h to FFh are Reserved, the value is FFh. 1 Dword = 4 Bytes PID(x) = Parameter Identification Table (x) - 64 - W25Q64FV 7.2.36 Erase Security Registers (44h) The W25Q64FV offers four 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the four security registers. ADDRESS Security Register #1 Security Register #2 Security Register #3 A23-16 00h 00h 00h A15-12 0001 0010 0011 A11-8 0000 0000 0000 A7-0 Don’t Care Don’t Care Don’t Care The Erase Security Register instruction sequence is shown in Figure 35. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed. After /CS is driven high, the self-timed Erase Security Register operation will commence for a time duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Erase Security Register instruction to that register will be ignored (See 11.1.9 for detail descriptions). /CS CLK DI (IO0) DO (IO1) Mode 3 0 Mode 0 * = MSB 123456789 29 30 31 Instruction (44h) 24-Bit Address 23 22 * High Impedance 210 Mode 3 Mode 0 Figure 35. Erase Security Registers Instruction (SPI Mode only) - 65 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.37 Program Security Registers (42h) The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. ADDRESS Security Register #1 Security Register #2 Security Register #3 A23-16 00h 00h 00h A15-12 0001 0010 0011 A11-8 0000 0000 0000 A7-0 Byte Address Byte Address Byte Address The Program Security Register instruction sequence is shown in Figure 36. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Program Security Register instruction to that register will be ignored (See 11.1.9, 11.2.21 for detail descriptions). /CS CLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 DI (IO0) /CS * = MSB Instruction (42h) 24-Bit Address Data Byte 1 23 22 21 * 321076543210 * 2072 2073 2074 2075 2076 2077 2078 2079 CLK DI (IO0) 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Data Byte 2 Data Byte 3 07654321076543210 * * Data Byte 256 76543210 * Mode 3 Mode 0 Figure 36. Program Security Registers Instruction (SPI Mode only) - 66 - W25Q64FV 7.2.38 Read Security Registers (48h) The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches the last byte of the register (byte FFh), it will reset to 00h, the first byte of the register, and continue to increment. The instruction is completed by driving /CS high. The Read Security Register instruction sequence is shown in Figure 37. If a Read Security Register instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a maximum of FR (see AC Electrical Characteristics). ADDRESS Security Register #1 Security Register #2 Security Register #3 A23-16 00h 00h 00h A15-12 0001 0010 0011 A11-8 0000 0000 0000 A7-0 Byte Address Byte Address Byte Address /CS CLK DI (IO0) DO (IO1) /CS CLK DI (IO0) DO (IO1) Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction (48h) 24-Bit Address 23 22 21 * High Impedance 3210 * = MSB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Dummy Byte 076543210 High Impedance Data Out 1 Data Out 2 76543210765432107 * * Figure 37. Read Security Registers Instruction (SPI Mode only) - 67 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.39 Set Read Parameters (C0h) In QPI mode, to accommodate a wide range of applications with different needs for either maximum read frequency or minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to configure the number of dummy clocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0Ch)” instruction. In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer to the Instruction Table 7.2.2-7.2.4 for details. The “Wrap Length” is set by W5-4 bit in the “Set Burst with Wrap (77h)” instruction. This setting will remain unchanged when the device is switched from Standard SPI mode to QPI mode. The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of dummy clocks is 2. The number of dummy clocks is only programmable for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions in the QPI mode. Whenever the device is switched from SPI mode to QPI mode, the number of dummy clocks should be set again, prior to any 0Bh, EBh or 0Ch instructions. P5 – P4 00 01 10 11 DUMMY CLOCKS 2 4 6 8 VOLTAGE 2.7V ~ 3.0V 3.0V ~ 3.6V 2.7V ~ 3.0V 3.0V ~ 3.6V 2.7V ~ 3.0V 3.0V ~ 3.6V 2.7V ~ 3.0V 3.0V ~ 3.6V MAXIMUM READ FREQ. (0Bh, EBh) 40MHz 50MHz 60MHz 80MHz 80MHz 104MHz 104MHz 104MHz MAXIMUM READ FREQ. (0Ch) 50MHz 60MHz 80MHz 104MHz 104MHz 104MHz 104MHz 104MHz P1 – P0 00 01 10 11 WRAP LENGTH 8-byte 16-byte 32-byte 64-byte /CS CLK IO0 Mode 3 Mode 0 0123 Instruction Read C0h Parameters P4 P0 Mode 3 Mode 0 IO1 P5 P1 IO2 P6 P2 IO3 P7 P3 Figure 38. Set Read Parameters Instruction (QPI Mode only) - 68 - W25Q64FV 7.2.40 Burst Read with Wrap (0Ch) The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read operation with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)” instruction in QPI mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap Length” once the ending boundary is reached. The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters (C0h)” instruction. /CS CLK IO0 Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Instruction 0Ch A23-16 20 16 A15-8 12 8 A7-0 Dummy* 40 4 IOs switch from Input to Output 0404 IO1 21 17 13 9 5 1 51515 IO2 22 18 14 10 6 2 62626 IO3 23 19 15 11 7 3 * "Set Read Parameters" instruction (C0h) can set the number of dummy clocks. 73 Byte 1 73 Byte 2 7 Byte 3 Figure 39. Burst Read with Wrap Instruction (QPI Mode only) - 69 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.41 Enable QPI (38h) The W25Q64FV support both Standard/Dual/Quad Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI). However, SPI mode and QPI mode can not be used at the same time. “Enable QPI (38h)” instruction is the only way to switch the device from SPI mode to QPI mode. Upon power-up, the default state of the device upon is Standard/Dual/Quad SPI mode. This provides full backward compatibility with earlier generations of Winbond serial flash memories. See Intruction Set Table 1-3 for all supported SPI commands. In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register 2 must be set to 1 first, and an “Enable QPI (38h)” instruction must be issued. If the Quad Enable (QE) bit is 0, the “Enable QPI (38h)” instruction will be ignored and the device will remain in SPI mode. See Instruction Set Table 4 for all the commands supported in QPI mode. When the device is switched from SPI mode to QPI mode, the exsiting Write Enable and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. /CS CLK Mode 3 Mode 0 DI (IO0) DO (IO1) 01234567 Mode 3 Mode 0 Instruction (38h) High Impedance Figure 40. Enable QPI Instruction (SPI Mode only) - 70 - W25Q64FV 7.2.42 Disable QPI (FFh) In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, a “Disable QPI (FFh)” instruction must be issued. When the device is switched from QPI mode to SPI mode, the exsiting Write Enable Latch (WEL) and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. /CS CLK IO0 Mode 3 Mode 0 01 Instruction FFh Mode 3 Mode 0 IO1 IO2 IO3 Figure 41. Disable QPI Instruction (QPI Mode only) - 71 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 7.2.43 Enable Reset (66h) and Reset (99h) Because of the small package and the limitation on the number of pins, the W25Q64FV provide a software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4). “Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To avoid accidental reset, both instructions must be issued in sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset command is accepted by the device, the device will take approximately tRST=30us to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. /CS CLK Mode 3 Mode 0 DI (IO0) DO (IO1) 01234567 Instruction (66h) Mode 3 Mode 0 012345 Instruction (99h) 67 Mode 3 Mode 0 High Impedance Figure 42a. Enable Reset and Reset Instruction Sequence (SPI Mode) /CS CLK IO0 Mode 3 Mode 0 01 Instruction 66h Mode 3 Mode 0 01 Instruction 99h Mode 3 Mode 0 IO1 IO2 IO3 Figure 42b. Enable Reset and Reset Instruction Sequence (QPI Mode) - 72 - W25Q64FV 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings (1) PARAMETERS SYMBOL Supply Voltage VCC Voltage Applied to Any Pin VIO Transient Voltage on any Pin VIOT Storage Temperature Lead Temperature Electrostatic Discharge Voltage TSTG TLEAD VESD CONDITIONS Relative to Ground <20nS Transient Relative to Ground Human Body Model(3) RANGE –0.6 to VCC+0.4 –0.6 to VCC+0.4 –2.0V to VCC+2.0V –65 to +150 See Note (2) –2000 to +2000 UNIT V V V °C °C V Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms). 8.2 Operating Ranges PARAMETER SYMBOL CONDITIONS Supply Voltage(1) Ambient Temperature, Operating VCC TA FR = 104MHz, fR = 50MHz FR = 80MHz, fR = 33MHz Industrial SPEC MIN MAX 3.0 3.6 2.7 3.0 –40 +85 UNIT V °C Note: 1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write) voltage. - 73 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 8.3 Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage SYMBOL tVSL(1) tPUW(1) VWI(1) SPEC MIN 10 1 1.0 MAX 10 2.0 Note: 1. These parameters are characterized only. UNIT µs ms V VCC VCC (max) Program, Erase and Write Instructions are ignored /CS must track VCC VCC (min) VWI Reset State tVSL Read Instructions Allowed tPUW Device is fully Accessible Figure 43. Power-up Timing and Voltage Levels Time - 74 - W25Q64FV 8.4 DC Electrical Characteristics PARAMETER Input Capacitance Output Capacitance SYMBOL CONDITIONS CIN(1) Cout(1) VIN = 0V(1) VOUT = 0V(1) SPEC MIN TYP MAX 6 8 Input Leakage ILI ±2 I/O Leakage ILO ±2 Standby Current ICC1 /CS = VCC, VIN = GND or VCC 10 50 Power-down Current ICC2 /CS = VCC, VIN = GND or VCC 1 25 Current Read Data / Dual /Quad 1MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 15 Current Read Data / Dual /Quad 50MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 20 Current Read Data / Dual /Quad 80MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 30 Current Read Data / Dual Output Read/Quad Output Read 104MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 40 Current Write Status Register ICC4 /CS = VCC 8 12 Current Page Program ICC5 /CS = VCC 20 25 Current Sector/Block Erase ICC6 /CS = VCC 20 25 Current Chip Erase ICC7 /CS = VCC 20 25 Input Low Voltage VIL –0.5 VCC x 0.3 Input High Voltage VIH VCC x 0.7 VCC + 0.4 Output Low Voltage VOL IOL = 100 µA 0.2 Output High Voltage VOH IOH = –100 µA VCC – 0.2 Notes: 1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 1.8V. 2. Checker Board Pattern. UNIT pF pF µA µA µA µA mA mA mA mA mA mA mA mA V V V V - 75 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 8.5 AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages SYMBOL CL TR, TF VIN IN OUT Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SPEC MIN MAX 30 5 0.1 VCC to 0.9 VCC 0.3 VCC to 0.7 VCC 0.5 VCC to 0.5 VCC Input Levels Input and Output Timing Reference Levels 0.9 VCC 0.1 VCC 0.5 VCC Figure 39. AC Measurement I/O Waveform UNIT pF ns V V V - 76 - W25Q64FV 8.6 AC Electrical Characteristics DESCRIPTION Clock frequency for SPI Read data instructions (03h) 2.7-3.0V / 3.0-3.6V Clock frequency for QPI Read instructions (0Bh, EBh) with 2/4/6/8 dummy clocks Clock frequency for QPI Read instructions (0Ch) with 2/4/6/8 dummy clocks Clock frequency for all other SPI/QPI instructions 2.7-3.0V / 3.0-3.6V Clock High, Low Time for all instructions except for Read Data (03h) Clock High, Low Time for Read Data (03h) instruction Clock Rise Time peak to peak Clock Fall Time peak to peak /CS Active Setup Time relative to CLK /CS Not Active Hold Time relative to CLK Data In Setup Time Data In Hold Time /CS Active Hold Time relative to CLK /CS Not Active Setup Time relative to CLK /CS Deselect Time (for Array Read Æ Array Read) /CS Deselect Time (for Erase or Program Æ Read Status Registers) Volatile Status Register Write Time Output Disable Time Clock Low to Output Valid 2.7V-3.0V / 3.0V-3.6V Clock Low to Output Valid (Non-array Read) 2.7V-3.0V / 3.0V-3.6V Output Hold Time /HOLD Active Setup Time relative to CLK SYMBOL fR SPEC ALT MIN TYP MAX D.C. 33/50 UNIT MHz FR fC1 D.C. 40/60/80/104 MHz FR fC1 D.C. 50/80/104/104 MHz FR fC1 D.C. tCLH, tCLL(1) 4 tCRLH, tCRLL(1) tCLCH(2) tCHCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL1 tSHSL2 8 0.1 0.1 tCSS 5 5 tDSU 2 tDH 3 5 5 tCSH 10 tCSH 50 tSHQZ(2) 50 tDIS tCLQV1 tV1 80/104 MHz ns ns V/ns V/ns ns ns ns ns ns ns ns ns 7 ns 7/6 ns tCLQV2 tCLQX tHLCH tV2 tHO 0 5 8.5 / 7.5 ns ns ns Continued – next page - 77 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 8.7 AC Electrical Characteristics (cont’d) DESCRIPTION SYMBOL ALT MIN SPEC TYP MAX UNIT /HOLD Active Hold Time relative to CLK tCHHH 5 ns /HOLD Not Active Setup Time relative to CLK tHHCH 5 ns /HOLD Not Active Hold Time relative to CLK tCHHL 5 /HOLD to Output Low-Z tHHQX(2) tLZ /HOLD to Output High-Z tHLQZ(2) tHZ Write Protect Setup Time Before /CS Low tWHSL(3) 20 Write Protect Hold Time After /CS High tSHWL(3) 100 /CS High to Power-down Mode tDP(2) /CS High to Standby Mode without Electronic Signature Read tRES1(2) /CS High to Standby Mode with Electronic Signature Read tRES2(2) /CS High to next Instruction after Suspend tSUS(2) /CS High to next Instruction after Reset tRST(2) ns 7 ns 12 ns ns ns 3 µs 30 µs 30 µs 20 µs 30 µs Write Status Register Time tW Byte Program Time (First Byte) (4) tBP1 Additional Byte Program Time (After First Byte) (4) tBP2 Page Program Time tPP Sector Erase Time (4KB) tSE 15 20 ms 20 50 µs 2.5 10 µs 0.7 3 ms 30 200/400(5) ms Block Erase Time (32KB) Block Erase Time (64KB) Chip Erase Time tBE1 120 1,600 ms tBE2 150 2,000 ms tCE 30 120 s Notes: 1. 2. 3. 4. 5. Clock high + Clock low must be less than or equal to 1/fC. Value guaranteed by design and/or characterization, not 100% tested in production. Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1). For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed. Max Value tSE with <50K cycles is 200ms and >50K & <100K cycles is 400ms. - 78 - W25Q64FV 8.8 Serial Output Timing /CS CLK tCLQX IO output tCLQV tCLQX MSB OUT 8.9 Serial Input Timing tCLQV /CS tCHSL CLK IO input tSLCH tDVCH MSB IN 8.10 /HOLD Timing tCHDX /CS CLK tCHHL /HOLD IO output IO input 8.11 /WP Timing /CS tWHSL /WP tCLH tCLL LSB OUT tSHQZ tCHSH tSHSL tSHCH tCLCH LSB IN tCHCL tHLCH tCHHH tHLQZ tHHCH tHHQX tSHWL CLK IO input Write Status Register is allowed Write Status Register is not allowed - 79 - Publication Release Date: December 19, 2011 Revision D 9. PACKAGE SPECIFICATION 9.1 8-Pin SOIC 208-mil (Package Code SS) W25Q64FV θ Symbol A A1 A2 b C D D1 E E1 e H L y θ Min 1.75 0.05 1.70 0.35 0.19 5.18 5.13 5.18 5.13 7.70 0.50 --0° Millimeters Nom 1.95 0.15 1.80 0.42 0.20 5.28 5.23 5.28 5.23 1.27 BSC 7.90 0.65 ----- Max 2.16 0.25 1.91 0.48 0.25 5.38 5.33 5.38 5.33 8.10 0.80 0.10 8° Min 0.069 0.002 0.067 0.014 0.007 0.204 0.202 0.204 0.202 0.303 0.020 --0° Inches Nom 0.077 0.006 0.071 0.017 0.008 0.208 0.206 0.208 0.206 0.050 BSC 0.311 0.026 ----- Max 0.085 0.010 0.075 0.019 0.010 0.212 0.210 0.212 0.210 0.319 0.031 0.004 8° - 80 - 9.2 8-Pin PDIP 300-mil (Package Code DA) W25Q64FV Symbol A A1 A2 D E E1 L eB θ° Min --0.38 3.18 9.02 6.22 2.92 8.51 0° Millimeters Nom ----3.30 9.27 7.62 BSC 6.35 3.30 9.02 7° Max 5.33 --3.43 10.16 6.48 3.81 9.53 15° Min --0.015 0.125 0.355 0.245 0.115 0.335 0° Inches Nom ----0.130 0.365 0.300 BSC 0.250 0.130 0.355 7° Max 0.210 --- 0.135 0.400 0.255 0.150 0.375 15° - 81 - Publication Release Date: December 19, 2011 Revision D 9.3 8-Pad WSON 6x5-mm (Package Code ZP) W25Q64FV Symbol A A1 b C D D2 E E2 e L y Min 0.70 0.00 0.35 --5.90 3.35 4.90 4.25 0.55 0.00 Millimeters Nom Max 0.75 0.80 0.02 0.05 0.40 0.48 0.20 REF --- 6.00 6.10 3.40 3.45 5.00 5.10 4.30 4.35 1.27 BSC 0.60 0.65 --- 0.075 Min 0.028 0.000 0.014 --0.232 0.132 0.193 0.167 0.022 0.000 Inches Nom 0.030 0.001 0.016 0.008 REF 0.236 0.134 0.197 0.169 0.050 BSC 0.024 --- Max 0.031 0.002 0.019 --0.240 0.136 0.201 0.171 0.026 0.003 - 82 - 9.4 8-Pad WSON 8x6-mm (Package Code ZE) W25Q64FV Symbol A A1 b C D D2 E E2 e L y Min 0.70 0.00 0.35 0.19 7.90 4.60 5.90 5.15 0.45 0.00 Millimeters Nom 0.75 0.02 0.40 0.20 8.00 4.65 6.00 5.20 1.27 BSC 0.50 --- Max 0.80 0.05 0.48 0.25 8.10 4.70 6.10 5.25 0.55 0.050 Min 0.028 0.000 0.014 0.007 0.311 0.181 0.232 0.203 0.018 0.000 Inches Nom 0.030 0.001 0.016 0.008 0.315 0.183 0.236 0.205 0.050 BSC 0.020 --- Max 0.031 0.002 0.019 0.010 0.319 0.185 0.240 0.207 0.022 0.002 - 83 - Publication Release Date: December 19, 2011 Revision D 9.5 16-Pin SOIC 300-mil (Package Code SF) W25Q64FV Symbol A A1 A2 b C D E E1 e L y θ Min 2.36 0.10 --0.33 0.18 10.08 10.01 7.39 0.38 --0° Millimeters Nom 2.49 --2.31 0.41 0.23 10.31 10.31 7.49 1.27 BSC 0.81 ----- Max 2.64 0.30 --0.51 0.28 10.49 10.64 7.59 1.27 0.076 8° Min 0.093 0.004 --0.013 0.007 0.397 0.394 0.291 0.015 --0° Inches Nom 0.098 --- 0.091 0.016 0.009 0.406 0.406 0.295 0.050 BSC 0.032 ----- Max 0.104 0.012 --0.020 0.011 0.413 0.419 0.299 0.050 0.003 8° - 84 - W25Q64FV 9.6 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array) Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm Symbol A A1 b D D1 E E1 e Min --0.25 0.35 7.95 5.95 Millimeters Nom --0.30 0.40 8.00 5.00 BSC 6.00 3.00 BSC 1.00 BSC Max 1.20 0.35 0.45 8.05 6.05 Min --0.010 0.014 0.313 0.234 Inches Nom --0.012 0.016 0.315 0.197 BSC 0.236 0.118 BSC 0.039 BSC Max 0.047 0.014 0.018 0.317 0.238 - 85 - Publication Release Date: December 19, 2011 Revision D 10. ORDERING INFORMATION W25Q64FV W = Winbond W(1) 25Q 64F V xx(2) 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 64F = 64M-bit V = 2.7V to 3.6V SS = 8-pin SOIC 208-mil SF = 16-pin SOIC 300-mil ZP = 8-pad WSON 6x5mm ZE = 8-pad WSON 8x6mm DA = 8-pin PDIP 300-mil TC = 24-ball TFBGA 8x6mm I = Industrial (-40°C to +85°C) (3,4) G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) P = Green Package with Status Register Power-Down & OTP enabled Notes: 1. The “W” prefix is not included on the part marking. 2. Only the 2nd letter is used for the part marking; WSON package type ZP and ZE are not used for the part marking. 3. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 4. For shipments with OTP feature enabled, please specify when placing orders. - 86 - W25Q64FV 10.1 Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the W25Q64FV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number. PACKAGE TYPE SS SOIC-8 208mil SF SOIC-16 300mil DA PDIP-8 300mil ZP(1) WSON-8 6x5mm ZE(1) WSON-8 8x6mm TC TFBGA-24 8x6mm DENSITY 64M-bit 64M-bit 64M-bit 64M-bit 64M-bit 64M-bit PRODUCT NUMBER W25Q64FVSSIG W25Q64FVSSIP W25Q64FVSFIG W25Q64FVSFIP W25Q64FVDAIG W25Q64FVDAIP W25Q64FVZPIG W25Q64FVZPIP W25Q64FVZEIG W25Q64FVZEIP W25Q64FVTCIG W25Q64FVTCIP TOP SIDE MARKING 25Q64FVSIG 25Q64FVSIP 25Q64FVFIG 25Q64FVFIP 25Q64FVAIG 25Q64FVAIP 25Q64FVIG 25Q64FVIP 25Q64FVIG 25Q64FVIP 25Q64FVCIG 25Q64FVCIP Notes: 1. For WSON packages, the package type ZP and ZE is not used in the top side marking. - 87 - Publication Release Date: December 19, 2011 Revision D W25Q64FV 11. REVISION HISTORY VERSION DATE A 03/29/2011 B 08/10/2011 C 11/02/2011 D 12/19/2011 PAGE 60-62 5-9, 81, 85-87 All 78 DESCRIPTION New Create Preliminary Updated SFDP to JESD216 Added PDIP, TFBGA package types Removed preliminary designator Updated tBE, tCE Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice. - 88 -

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