首页资源分类其它科学普及 > STM32L15 SPEC

STM32L15 SPEC

已有 460221个资源

下载专区


TI最新应用解决方案

工业电子 汽车电子 个人消费电子

上传者其他资源

文档信息举报收藏

标    签: STM32L15

分    享:

文档简介

STM32L15 SPEC

文档预览

STM32L151xD STM32L152xD Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 384KB Flash, 48KB SRAM, 12KB EEPROM, LCD, USB, ADC, DAC, memory I/F Datasheet  production data Features ■ Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40°C to 85°C/105°C Temperature range – 0.35 µA Standby mode (3 wakeup pins) – 1.3 µA Standby mode + RTC – 0.65 µA Stop mode (16 wakeup lines) – 1.7 µA Stop mode + RTC – 11 µA Low-power Run mode – 238 µA/MHz Run mode – 10 nA ultra-low I/O leakage – 8 µs wakeup time ■ Core: ARM 32-bit Cortex™-M3 CPU – From 32 kHz up to 32 MHz max – 33.3 DMIPS peak (Dhrystone 2.1) – Memory protection unit ■ Up to 34 capacitive sensing channels ■ CRC calculation unit, 96-bit unique ID ■ Reset and supply management – Low power, ultrasafe BOR (brownout reset) with 5 selectable thresholds – Ultralow power POR/PDR – Programmable voltage detector (PVD) ■ Clock sources – 1 to 24 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – High Speed Internal 16 MHz factorytrimmed RC (+/- 1%) – Internal low power 37 kHz RC – Internal multispeed low power 65 kHz to 4.2 MHz – PLL for CPU clock and USB (48 MHz) ■ Pre-programmed bootloader – USB and USART supported ■ Serial wire debug, JTAG and trace LQFP144 (20 × 20 mm) LQFP100 (14 × 14 mm) LQFP64 (10 × 10 mm) UFBGA132 (7 × 7 mm) WLCSP64 (0.400 mm pitch) ■ Up to 116 fast I/Os (102 I/Os 5V tolerant), all mappable on 16 external interrupt vectors ■ Memories – 384 KB Flash with ECC (with 2 bank of 192 KB enabling Rww capability) – 48 KB RAM – 12 KB of true EEPROM with ECC – 128 Byte Backup Register – Memory interface controller supporting SRAM, PSRAM and NOR Flash ■ LCD driver for up to 8x40 segments (contrast adjustment, blinking mode, step-up converter) ■ Rich analog peripherals (down to 1.8V) – 3x Operational Amplifier – 12-bit ADC 1 Msps up to 40 channels – 12-bit DAC 2 ch with output buffers – 2x ultra-low-power-comparators (window mode and wake up capability) ■ DMA controller 12x channels ■ 12x peripherals communication interface – 1x USB 2.0 (internal 48 MHz PLL) – 5x USART – 3x SPI 16 Mbits/s (2x SPI with I2S) – 2x I2C (SMBus/PMBus) – 1x SDIO interface ■ 11x timers: 1x 32-bit, 6x 16-bit with up to 4 IC/OC/PWM channels, 2x 16-bit basic timer, 2x watchdog timers (independent and window) Table 1. Device summary Reference Part number STM32L151xx STM32L152xx STM32L151QD STM32L151RD STM32L151VD STM32L151ZD STM32L152QD STM32L152RD STM32L152VD STM32L152ZD October 2012 This is information on a product in full production. Doc ID 022027 Rev 5 1/141 www.st.com 1 Contents Contents STM32L151xD STM32L152xD 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 ARM® Cortex™-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23 3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.12 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 28 3.15 System configuration controller and routing interface . . . . . . . . . . . . . . . 28 2/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Contents 3.16 3.17 3.18 3.19 3.20 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.17.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.17.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.17.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 30 3.18.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.18.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.18.5 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.18.6 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 31 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 57 6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Doc ID 022027 Rev 5 3/141 Contents STM32L151xD STM32L152xD 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12 6.3.13 6.3.14 6.3.15 6.3.16 6.3.17 6.3.18 6.3.19 6.3.20 6.3.21 6.3.22 6.3.23 6.3.24 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 96 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 LCD controller (STM32L152xD only) . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ultra-low-power STM32L15xxD device features and peripheral counts . . . . . . . . . . . . . . . 11 Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 16 CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16 Functionalities depending on the working mode (from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STM32L15xxD pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 58 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Current consumption in Run mode, code with data processing running from Flash. . . . . . 61 Current consumption in Run mode, code with data processing running from RAM . . . . . . 62 Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 67 Typical and maximum timings in Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 HSE 1-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 83 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 85 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 86 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 93 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Doc ID 022027 Rev 5 5/141 List of tables STM32L151xD STM32L152xD Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 127 LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 129 LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 130 UFBGA132 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 WLCSP64, 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . . 134 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 STM32L15xxD ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Ultra-low-power STM32L15xxD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32L15xZD LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STM32L15xQD BGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STM32L15xVD LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32L15xRD LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32L15xRD WLCSP64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 84 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 85 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 86 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 87 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 93 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SDIO timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum dynamic current consumption on VREF+ supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 117 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 117 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 126 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 128 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 130 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package outline . . . . 132 Doc ID 022027 Rev 5 7/141 List of figures STM32L151xD STM32L152xD Figure 48. WLCSP64, 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . . 133 Figure 49. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L151xD and STM32L152xD ultra-low-power ARM Cortex™-based microcontrollers product line. STM32L15xD devices are microcontrollers with a Flash memory density of 384 Kbytes. The ultra-low-power STM32L15xxD family includes devices in 5 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the ultra-low-power STM32L15xxD microcontroller family suitable for a wide range of applications: ● Medical and handheld equipment ● Application control and user interface ● PC peripherals, gaming, GPS and sport equipment ● Alarm systems, wired and wireless sensors, Video intercom ● Utility metering This STM32L151xD and STM32L152xD datasheet should be read in conjunction with the STM32L1xxxx reference manual (RM0038). The document "Getting started with STM32L1xxx hardware development" AN3216 gives a hardware implementation overview. Both documents are available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g. Figure 1 shows the general block diagram of the device family. Doc ID 022027 Rev 5 9/141 Description 2 Description STM32L151xD STM32L152xD The ultra-low-power STM32L15xxD incorporates the connectivity power of the universal serial bus (USB) with the high-performance ARM Cortex™-M3 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 384 Kbytes and RAM up to 48 Kbytes), a flexible static memory controller (FSMC) interface (for devices with packages of 100 pins and more) and an extensive range of enhanced I/Os and peripherals connected to two APB buses. The STM32L15xxD devices offer three operational amplifiers, one 12-bit ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six general-purpose 16bit timers and two basic timers, which can be used as time bases. Moreover, the STM32L15xxD devices contain standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2S, one SDIO, three USARTs, two UARTs and a USB. The STM32L15xxD devices offer up to 34 capacitive sensing channels to simply add touch sensing functionality to any application. They also include a real-time clock and a set of backup registers that remain powered in Standby mode. Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to drive up to 8 multiplexed LCDs with contrast independent of the supply voltage. The ultra-low-power STM32L15xxD operates from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. It is available in the -40 to +85 °C temperature range, extended to 105°C in low power dissipation state. A comprehensive set of power-saving modes allows the design of lowpower applications. 10/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 2.1 Device overview Description Table 2. Ultra-low-power STM32L15xxD device features and peripheral counts Peripheral STM32L15xRD STM32L15xVD STM32L15xQD STM32L15xZD Flash (Kbytes) 384 Data EEPROM (Kbytes) 12 RAM (Kbytes) 48 FSMC No multiplexed only Yes 32 bit 1 Timers General-purpose 6 Basic 2 Communication interfaces SPI/(I2S) I2C USART USB 3/(2) 2 5 1 SDIO 1 GPIOs 51 83 109 115 Operation amplifiers 3 12-bit synchronized ADC Number of channels 1 1 1 1 21 25 40 40 12-bit DAC Number of channels LCD (1) COM x SEG 1 4x32 or 8x28 2 2 1 4x44 or 8x40 Comparators 2 Capacitive sensing channels 23 33 34 Max. CPU frequency Operating voltage Operating temperatures Packages 1. STM32L152xx devices only. 32 MHz 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option 1.65 V to 3.6 V without BOR option LQFP64, WLCSP64 Ambient temperature: –40 to +85 °C Junction temperature: –40 to +105 °C LQFP100 BGA132 LQFP144 Doc ID 022027 Rev 5 11/141 Description STM32L151xD STM32L152xD 2.2 Note: 2.2.1 2.2.2 2.2.3 2.2.4 Ultra-low-power device continuum The ultra-low-power STM32L15xxD, STM32L162xD, STM32L15xxC and STM32L162xC are fully pin-to-pin and software compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture and features. They are all based on STMicroelectronics ultralow leakage process. The ultra-low-power STM32L and general-purpose STM32Fxxxx families are pin-to-pin compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx devices. Please refer to the STM32F and STM8L documentation for more information on these devices. Performance All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs. Shared peripherals STM8L15xxx and STM32L15xxx share identical peripherals which ensure a very easy migration from one family to another: ● Analog peripherals: ADC, DAC and comparators ● Digital peripherals: RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance, the STM8L15xxx and STM32L15xxx families use a common architecture: ● Same power supply range from 1.65 V to 3.6 V ● Architecture optimized to reach ultralow consumption both in low power modes and Run mode ● Fast startup strategy from low power modes ● Flexible system clock ● Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector Features ST ultra-low-power continuum also lies in feature compatibility: ● More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm ● Memory density ranging from 4 to 384 Kbytes 12/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 3 Functional overview Functional overview Figure 1. Ultra-low-power STM32L15xxD block diagram 42!#%#+ 42!#%$ 42!#%$ 42!#%$ 42!#%$ .*4234 *4$) *4#+37#,+ *4-337$!4 *4$/ AS!& ! $ #,+ /%. 7%. 7! )4. %"!2  ,"! 2 ",. 6$$! 633! #/-0X?).X 0!;= 0";= 0#;= 0$;= 0%;= 0(;= 0&;= 0';=  !& -/3) -)3/ 3#+ .33AS!& 28 48 #43 243 3MART#ARDAS!& !& 6$$2%&?!$# 6332%&?!$# $ #-$ #+ #HANN ELS #HANNEL #HANNEL * 4! ' 37 PBUS -#05 )BUS F MAX-(Z -05 .6)# $BU S 3YSTEM '0$-!CHANNELS '0$-!CHANNELS &3-# 3UPPLY MONITORING "/2"GAP 06$ #APSENS '0#OMP 050$ '0)/0/24! '0)/0/24" '0)/0/24# '0)/0/24$ '0)/0/24% '0)/0/24( '0)/0/24& '0)/0/24' %84)4 7+50 30) "/2 )NT 6$$! 53!24 6$$! BIT!$# )& 4EMPSENSOR 3$)/ 'ENERALPURPOSE TIMERS 4)-%2 4)-%2 4)-%2 !"0F-!8-(Z !"0F-!8-(Z "US-ATRIX-3 %%£ OBL )NTERFACE 4RACE#ONTROLLER %4- 6$$#/2% 6$$ 0/7%2 %%02/- BIT +" 02/'2!+" $!4! +" "//4 $5!,"!.+ 277 32!-+ 0$2 6/,42%' 6REF 3UPPLYMONITORING 0$2 6$$ !( " 0#, + ! 0" 0#, + (#,+ &#,+ 6$$! 0,, #LOCK -GMT 84!,/3#   -(Z 7$'+ 2#(3) 2#-3) 26#$,$3!) 3TANDBY INTERFACE 84!,K(Z 24#6 !7 5 "ACK UP REG "ACKUPINTERFACE 6$$ ,#$"OOSTER !(" &MAX-(Z 6,#$ !("  !0" ! ("  !0" 53"32!-" 7IN7!4#($/' 4)-%2 4)-%2 /0!-0 /0!-0 /0!-0 4)-%2 4)-%2 4)-%2 4)-%2BITS 53! 24 53! 24 53! 24 53! 24 XX3BIT0))3 XX3BIT0))3 )# )# 53"&3DEVICE #APSENSING ,#$X 6$$! BIT$!#  ))&& BIT$!#  6$$6TO6 633 .234 /3#?). /3#?/54 /3#?). /3#?/54 24#?/54 4!-0%2 6,#$6TO6 #HANNELS #HANNELS #HANNELS #HANNELS 28 48 #43 243 3MART#ARDAS!& 28 48 #43 243 3MART#ARDAS!& 28 48AS ! & 28 48AS!& -/3) -)3/ 3#+ .33 73 #+ -#+ 3$AS!& -/3) -)3/ 3#+ .33 73 #+ -#+ 3$AS!& 3#, 3$! AS!& 3#, 3$! 3-" US 0-" US AS!& 53"? $0 53"? $0X 3%'X #/-X $!#?/54AS!& $!#?/54AS!& 7*/1 7*/1 7*/. 7*/. 7065 7065 7*/1 7*/. 7065 -36 Doc ID 022027 Rev 5 13/141 Functional overview STM32L151xD STM32L152xD 1. Legend: AF: alternate function ADC: analog-to-digital converter BOR: brown out reset DMA: direct memory access DAC: digital-to-analog converter I²C: inter-integrated circuit multimaster interface 3.1 Low power modes The ultra-low-power STM32L15xxD supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply. There are three power consumption ranges: ● Range 1 (VDD range limited to 2.0V-3.6V), with the CPU running at up to 32 MHz ● Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz ● Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated only with the multispeed internal RC oscillator clock source) Seven low power modes are provided to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at 16 MHz is about 1 mA with all peripherals off. ● Low power run mode This mode is achieved with the multispeed internal (MSI) RC oscillator set to the minimum clock (131 kHz), execution from SRAM or Flash memory, and internal regulator in low power mode to minimize the regulator's operating current. In Low power run mode, the clock frequency and the number of enabled peripherals are both limited. ● Low power sleep mode This mode is achieved by entering Sleep mode with the internal voltage regulator in Low power mode to minimize the regulator’s operating current. In Low power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz. When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. ● Stop mode with RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the VCORE domain are stopped, the PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event or the RTC wakeup. 14/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview Note: ● Stop mode without RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and HSE crystal oscillators are disabled. The voltage regulator is in the low power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB wakeup. ● Standby mode with RTC Standby mode is used to achieve the lowest power consumption and real time clock. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event occurs. ● Standby mode without RTC Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs. The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by entering Stop or Standby mode. Doc ID 022027 Rev 5 15/141 Functional overview STM32L151xD STM32L152xD Table 3. Functionalities depending on the operating power supply range Functionalities depending on the operating power supply range Operating power supply range DAC and ADC operation USB Dynamic voltage scaling range I/O operation VDD = 1.65 to 1.8 V Not functional Not functional Range 2 or range 3 Degraded speed performance VDD = 1.8 to 2.0 V Conversion time up to 500 Ksps Not functional Range 2 or range 3 Degraded speed performance VDD = 2.0 to 2.4 V Conversion time up to 500 Ksps Functional(1) Range 1, range 2 or range 3 Full speed operation VDD = 2.4 to 3.6 V Conversion time up to 1 Msps Functional(1) Range 1, range 2 or range 3 Full speed operation 1. To be USB compliant from the IO voltage standpoint, the minimum VDD is 3.0 V. Table 4. CPU frequency range depending on dynamic voltage scaling CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz (1ws) 32 kHz to 16 MHz (0ws) 8 MHz to 16 MHz (1ws) 32 kHz to 8 MHz (0ws) 2.1MHz to 4.2 MHz (1ws) 32 kHz to 2.1 MHz (0ws) Range 1 Range 2 Range 3 16/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview Table 5. Functionalities depending on the working mode (from Run/active down to standby) Low- Low- Stop Standby Ips Run/Active Sleep power Run power Sleep Wakeup capability Wakeup capability CPU Y -- Y -- -- -- Flash Y Y Y N -- -- RAM Y Y Y Y Y -- Backup Registers Y Y Y Y Y Y EEPROM Y -- Y Y Y -- Brown-out rest (BOR) Y DMA Y Y Y Y Y Y Y Y Y Y -- -- Programable Voltage Detector Y (PVD) Power On Reset (POR) Y Power Down Rest (PDR) Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y High Speed Internal (HSI) Y Y -- -- -- -- High Speed External (HSE) Y Y -- -- -- -- Low Speed Internal (LSI) Y Y Y Y Y -- Low Speed External (LSE) Y Y Y Y Y -- Multi-Speed Internal (MSI) Y Y Y Y -- -- Inter-Connect Controler Y RTC Y Y Y Y -- -- Y Y Y Y Y Y RTC Tamper Y Auto WakeUp (AWU) Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y LCD USB USART SPI I2C Y Y Y Y Y -- Y Y -- -- -- Y -- Y Y Y Y Y (1) -- Y Y Y Y -- Y Y Y Y (1) -- Doc ID 022027 Rev 5 17/141 Functional overview STM32L151xD STM32L152xD Table 5. Functionalities depending on the working mode (from Run/active down to standby) (continued) Low- Low- Stop Standby Ips Run/Active Sleep power power Wakeup Wakeup Run Sleep capability capability ADC Y Y -- -- -- -- DAC Y Y Y Y Y -- Tempsensor Y Y Y Y Y -- OP amp Y Y -- -- -- Comparators Y Y Y Y Y Y -- 16-bit and 32-bit Timers Y Y Y Y -- -- Touch sensing Y Y -- -- -- -- Systic Timer Y Y Y Y -- GPIOs Y Y Y Y Y Y 3Pins Wakeup time to Run mode 0 µs 0.36 µs 3 µs 32 µs < 8 µs 50 µs 0.65 µA (No 0.35 µA (No RTC) VDD=1.8V RTC) VDD=1.8V Consumption VDD=1.8V to 3.6V (Typ) Down to 238 µA/MHz (from Flash) Down to 55 µA/MHz (from Flash) Down to 11 µA Down to 4.4 µA 1.5 µA (with RTC) VDD=1.8V 0.65µA (No RTC) VDD=3.0V 1 µA (with RTC) VDD=1.8V 0.35 µA (No RTC) VDD=3.0V 1.7 µA (with 1.3 µA (with RTC) VDD=3.0V RTC) VDD=3.0V 1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before entering run mode. 3.2 ARM® Cortex™-M3 core with MPU The ARM Cortex™-M3 processor is the industry leading processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region. Owing to its embedded ARM core, the STM32L15xxD is compatible with all ARM tools and software. 18/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview Nested vectored interrupt controller (NVIC) The ultra-low-power STM32L15xxD embeds a nested vectored interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. ● Closely coupled NVIC gives low-latency interrupt processing ● Interrupt entry vector table address passed directly to the core ● Closely coupled NVIC core interface ● Allows early processing of interrupts ● Processing of late arriving, higher-priority interrupts ● Support for tail-chaining ● Processor state automatically saved ● Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.3 3.3.1 3.3.2 Reset and supply management Power supply schemes ● VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. ● VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR) that can be coupled with a brownout reset (BOR) circuitry. The device exists in two versions: ● The version with BOR activated at power-on operates between 1.8 V and 3.6 V. ● The other version without BOR operates between 1.65 V and 3.6 V. After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes 1.65 V (whatever the version, BOR active or not, at power-on). When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits the POR area. Doc ID 022027 Rev 5 19/141 Functional overview STM32L151xD STM32L152xD Note: 3.3.3 3.3.4 Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● MR is used in Run mode (nominal regulation) ● LPR is used in the Low power run, Low power sleep and Stop modes ● Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR). Boot modes At startup, boot pins are used to select one of three boot options: ● Boot from Flash memory ● Boot from System memory ● Boot from embedded RAM The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot mechanism is available through user option byte, to allow booting from bank 2 when bank 2 contains valid code. This dual boot capability can be used to easily implement a secure field software update mechanism. The boot loader is located in System memory. It is used to reprogram the Flash memory by using USART1, USART2 or USB. See STM32™ microcontroller system memory boot mode AN2606 for details. 20/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview 3.4 Clock management The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. It features: ● Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. ● Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. ● Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ● System clock source: three different clock sources can be used to drive the master clock SYSCLK: – 1-24 MHz high-speed external crystal (HSE), that can supply a PLL – 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a ±0.5% accuracy. ● Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the LCD controller and the real-time clock: – 32.768 kHz low-speed external crystal (LSE) – 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision. ● RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock. ● USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface. ● Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ● Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled. ● Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application. Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree. Doc ID 022027 Rev 5 21/141 Functional overview STM32L151xD STM32L152xD Figure 2. Clock tree 3TANDBYSUPPLIEDVOLTAGEDOMAIN ENABLE 7ATCHDOG ,3)2# ,3)TEMPO 7ATCHDOG ,3 ,3%/3# ,3%TEMPO 24#ENABLE 24# ,3 ,3 ,3 ,3 6$$#/2% -(Z 6 -3)2# LEVELSHIFTERS 6$$#/2% 6 (3)2#     CK?LSI CK?LSE LEVELSHIFTERS 6$$#/2% 6 (3% /3# LEVELSHIFTERS 6$$#/2% ,3 6 -(ZCLOCK DETECTOR ,3 #+?53" CK?MSI CK?HSI CK?HSE 6 CK?PLL CK?PLLIN 0,, 8            LEVELSHIFTERS (3%PRESENTORNOT 6$$#/2% USBENANDNOTDEEPSLEEP CK?USB6CO6COMUSTBEAT-(Z ,#$ENABLE !$#ENABLE #+?,#$ #+?!$# -#/      NOTDEEPSLEEP NOTDEEPSLEEP 3YSTEM CLOCK !(" PRESCALER    NOTSLEEPOR DEEPSLEEP NOTSLEEPOR DEEPSLEEP  #+?072 #+?&#,+ #+?#05 #+?4)-393 !0" !0" PRESCALER PRESCALER           #LOCK SOURCE CONTROL #+?4)-4'/ #+?!0" #+?!0" TIMERENANDNOTDEEPSLEEP APBPERIPHENANDNOTDEEPSLEEP APBPERIPHENANDNOTDEEPSLEEP IF!0"PRESC X ELSE X -36 1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 24 MHz or 32 MHz. 22/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview 3.5 Low power real-time clock and backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides two programmable alarms and programmable periodic interrupts with wakeup from Stop and Standby modes. The programmable wakeup time ranges from 120 µs to 36 hours. The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. The RTC can also be automatically corrected with a 50/60Hz stable powerline. The RTC calendar can be updated on the fly down to sub second precision, which enables network system synchronisation. A time stamp can record an external event occurrence, and generates an interrupt. There are thirty-two 32-bit backup registers provided to store 128 bytes of user application data. They are cleared in case of tamper detection. Three pins can be used to detect tamper events. A change on one of these pins can reset backup register and generate an interrupt. To prevent false tamper event, like ESD event, these three tamper inputs can be digitally filtered. 3.6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high current capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB, comparator events or capacitive sensing acquisition. Doc ID 022027 Rev 5 23/141 Functional overview STM32L151xD STM32L152xD 3.7 Memories The STM32L15xxD devices have the following features: ● 48 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses). ● The non-volatile memory is divided into three arrays: – 384 Kbytes of embedded Flash program memory – 12 Kbytes of data EEPROM – Options bytes Flash program and data EEPROM are divided into two banks, this enables writing in one bank while running code or reading data in the other bank. The options bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: – Level 0: no readout protection – Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected – Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse) The whole non-volatile memory embeds the error correction code (ECC) feature. 3.8 FSMC (flexible static memory controller) The FSMC supports the following modes: SRAM, PSRAM, NOR Flash. Functionality overview: ● Up to 26 bit address bus ● Up to 16-bit data bus ● Write FIFO ● Burst mode ● Code execution from external memory ● Four chip select signals ● Up to 32 MHz external access 3.9 DMA (direct memory access) The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, SDIO, general-purpose timers, DAC and ADC. 24/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview 3.10 LCD (liquid crystal display) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. ● Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD ● Supports static, 1/2, 1/3, 1/4 and 1/8 duty ● Supports static, 1/2, 1/3 and 1/4 bias ● Phase inversion to reduce power consumption and EMI ● Up to 8 pixels can be programmed to blink ● Unneeded segments and common pins can be used as general I/O pins ● LCD RAM can be updated at any time owing to a double-buffer ● The LCD controller can operate in Stop mode 3.11 3.11.1 ADC (analog-to-digital converter) A 12-bit analog-to-digital converters is embedded into STM32L15xxD devices with up to 40 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs with up to 29 external channel in a group. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers. An injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task. The ADC includes a specific low power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC’s runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode. Temperature sensor The temperature sensor (TSENSE) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. Doc ID 022027 Rev 5 25/141 Functional overview STM32L151xD STM32L152xD To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 6. Temperature sensor calibration values Calibration value name Description TSENSE_CAL1 TSENSE_CAL2 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3 V TS ADC raw data acquired at temperature of 110 °C VDDA= 3 V Memory address 0x1FF8 00FA - 0x1FF8 00FB 0x1FF8 00FE - 0x1FF8 00FF 3.11.2 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It enables accurate monitoring of the VDD value (when no external voltage, VREF+, is available for ADC). The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in readonly mode. Table 7. Internal voltage reference measured values Calibration value name Description Memory address VREFINT_CAL Raw data acquired at temperature of 30 °C VDDA= 3 V 0x1FF8 00F8 - 0x1FF8 00F9 3.12 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This dual digital Interface supports the following features: ● Two DAC converters: one for each output channel ● Up to 10-bit output ● Left or right data alignment in 12-bit mode ● Synchronized update capability ● Noise-wave generation ● Triangular-wave generation ● Dual DAC channels, independent or simultaneous conversions ● DMA capability for each channel (including the underrun interrupt) ● External triggers for conversion ● Input reference voltage VREF+ 26/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview Eight DAC trigger inputs are used in the STM32L15xxD. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.13 Operational amplifier The STM32L15xxD embeds three operational amplifiers with external or internal follower routing capability (or even amplifier and filter capability with external components). When one operational amplifier is selected, one external ADC channel is used to enable output measurement. The operational amplifiers feature: ● Low input bias current ● Low offset voltage ● Low power mode ● Rail-to-rail input 3.14 Ultra-low-power comparators and reference voltage The STM32L15xxD embeds two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O). ● One comparator with fixed threshold ● One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following: – DAC output – External I/O – Internal reference voltage (VREFINT) or a submultiple (1/4, 1/2, 3/4) Both comparators can wake up from Stop mode, and be combined into a window comparator. The internal reference voltage is available externally via a low power / low current output buffer (driving current capability of 1 µA typical). 3.15 3.16 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. The highly flexible routing interface allows the application firmware to control the routing of different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage VREFINT. Touch sensing The STM32L15xxD devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 34 capacitive sensing channels distributed over 11 analog I/O groups. Both software and timer capacitive sensing acquisition modes are supported. Doc ID 022027 Rev 5 27/141 Functional overview STM32L151xD STM32L152xD Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. The capacitive sensing acquisition only requires few external components to operate. Reliable touch sensing functionality can be quickly and easily implemented using the free STM32L1xx STMTouch touch sensing firmware library. 3.17 Timers and watchdogs The ultra-low-power STM32L15xxD devices include seven general-purpose timers, two basic timers, and two watchdog timers. Table 8 compares the features of the general-purpose and basic timers. Table 8. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM2, TIM3, TIM4 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM5 32-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM9 16-bit Up, down, up/down Any integer between 1 and 65536 No 2 No TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.17.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) There are seven synchronizable general-purpose timers embedded in the STM32L15xxD devices (see Table 8 for differences). TIM2, TIM3, TIM4, TIM5 TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures/output compares/PWMs on the largest packages. TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. 28/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview 3.17.2 3.17.3 3.17.4 3.17.5 TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. TIM10, TIM11 and TIM9 TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock. Basic timers (TIM6 and TIM7) These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases. SysTick timer This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0. Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.18 3.18.1 Communication interfaces I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. Doc ID 022027 Rev 5 29/141 Functional overview STM32L151xD STM32L152xD 3.18.2 3.18.3 3.18.4 3.18.5 3.18.6 Universal synchronous/asynchronous receiver transmitter (USART) The three USART and two UART interfaces are able to communicate at speeds of up to 4 Mbit/s. They support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The three USARTs provide hardware management of the CTS and RTS signals. All USART/UART interfaces can be served by the DMA controller. Serial peripheral interface (SPI) Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPIs can be served by the DMA controller. Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. The I2Ss can be served by the DMA controller. SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 24 MHz in 8-bit mode, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. Universal serial bus (USB) The STM32L15xxD embeds a USB device peripheral compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated 30/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 3.19 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.20 Development support Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP. The JTAG port can be permanently disabled with a JTAG fuse. Embedded Trace Macrocell™ The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L15xxD through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. Doc ID 022027 Rev 5 31/141 Pin descriptions 4 Pin descriptions Figure 3. STM32L15xZD LQFP144 pinout STM32L151xD STM32L152xD  6$$?  633?  0%  0%  0"  0"  "//4  0"  0"  0"  0"  0"  0'  6$$?  633?  0'  0'  0'  0'  0'  0'  0$  0$  6$$?  633?  0$  0$  0$  0$  0$  0$  0#  0#  0#  0!   0!  0%  0%  0%  0%  0% 7+50  6,#$  0# 7+50  0# /3#?).  0# /3#?/54  0&  0&  0&  0&  0&  0&  633?  6$$?  0&  0&  0&  0&  0&  /3#?).  /3#?/54  .234  0#  0#  0#  0#  633!  62%&  62%&  6$$!  0!  7+50  0!   0!   0!   633?  6$$?  0!   0!   0!   0!   0#  0#  0"  0"  0"  0&  0&  633?  6$$?  0&  0&  0&  ,1&0 0'  0'  0%  0%  0%  633?  6$$?  0%  0%  0%  0%  0%  0%  0"  0"  633? 6$$?    6$$?  633?  0(  0!   0!   0!   0!   0!   0!   0#  0#  0#  0#   6$$? 633?  0'  0'  0'  0'  0'  0'  0'  0$  0$  6$$?  633?  0$  0$  0$  0$  0$  0$  0"  0"  0"  0" -36 32/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Figure 4. STM32L15xQD BGA132 ballout Pin descriptions             ! 0% 0% 0" "//4 0$ 0$ 0" 0" 0! 0! 0! 0! " 0% 0% 0" 0" 0" 0$ 0$ 0$ 0$ 0# 0# 0! # 0# 0% 0% 6$$? 0" 0' 0' 0$ 0$ 0# 0( 0! 7+50 $ 0# 0% /3# 7+50 633? 0& 0& 0& 0' 0' 0' 0! 0! 0# ?). % 0# /3# 6,#$ 633? 0& ?/54 0' 0# 0# 0# & 0( /3#?). 633? 0& 0& 633? 633? 0' 0' 633? 633? ' 0( /3#? 6$$? 0& 0& /54 ( 0# .234 6$$? 0& 6$$? 6$$? 0' 0' 6$$? 6$$? 0' 0$ 0$ 0$ * 633! 0# 0# 0! 0! 0& 0& 0& 0& 0$ 0$ 0$ + /0!-0 ?6).- 0# 0! 0! 0# 0& 0& 0$ 0$ 0" 0" 0" , 62%& 0! 0! 0! 0# 0" 0% 0% 0% 0" 0" 0" 7+50 - 6$$! 0! /0!-0 /0!-0 ?6).- ?6).- 0" 0" 0% 0% 0% 0% 0% 0% 1. This figure shows the package top view. -36 Doc ID 022027 Rev 5 33/141 Pin descriptions Figure 5. STM32L15xVD LQFP100 pinout STM32L151xD STM32L152xD 100 VDD_3 99 VSS_3 98 PE1 97 PE0 96 PB9 95 PB8 94 BOOT0 93 PB7 92 PB6 91 PB5 90 PB4 89 PB3 88 PD7 87 PD6 86 PD5 85 PD4 84 PD3 83 PD2 82 PD1 81 PD0 80 PC12 79 PC11 78 PC10 77 PA15 76 PA14 PE2 1 PE3 2 PE4 3 PE5 4 PE6-WKUP3 5 VLCD 6 PC13-WKUP2 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 VSS_5 10 VDD_5 11 PH0-OSC_IN 12 PH1-OSC_OUT 13 NRST 14 PC0 15 PC1 16 PC2 17 PC3 18 VSSA 19 VREF- 20 VREF+ 21 VDDA 22 PA0-WKUP1 23 PA1 24 PA2 25 LQFP100 75 VDD_2 74 VSS_2 73 PH2 72 PA 13 71 PA 12 70 PA 11 69 PA 10 68 PA 9 67 PA 8 66 PC9 65 PC8 64 PC7 63 PC6 62 PD15 61 PD14 60 PD13 59 PD12 58 PD11 57 PD10 56 PD9 55 PD8 54 PB15 53 PB14 52 PB13 51 PB12 ai15692c PA3 26 VSS_4 27 VDD_4 28 PA4 29 PA5 30 PA6 31 PA7 32 PC4 33 PC5 34 PB0 35 PB1 36 PB2 37 PE7 38 PE8 39 PE9 40 PE10 41 PE11 42 PE12 43 PE13 44 PE14 45 PE15 46 PB10 47 PB11 48 VSS_1 49 VDD_1 50 34/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Figure 6. STM32L15xRD LQFP64 pinout Pin descriptions VDD_ 3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VLCD PC13-WKUP2 PC14-OSC32_IN PC15-OSC32_OUT PH0 -OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP1 PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 LQFP64 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VPAS1S3_2 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai15693c Doc ID 022027 Rev 5 35/141 Pin descriptions Figure 7. STM32L15xRD WLCSP64 ballout STM32L151xD STM32L152xD         ! 6$$? 0# 0$ 0" 0" "//4 633? 6$$? 0# " 633? 0! 0# 0" 0" 0" 0# /3#?). /3#?/54 # 0! 0! 0! 0# 0" 6,#$ .234 0# 7+50 $ 0# 0! 0! 0! 0" 0# 0( 0( /3#?/54 /3#?). % 0# 0# 0# 0! 0! 0! 633! 0# & 0" 0" 0" 0" 633? 0! 7+50 0# 0# ' 0" 0" 0" 0! 0! 6$$? 0! 6$$! ( 6$$? 633? 0" 0" 0# 0# 0! 0! 1. This figure shows the package top view. -36 36/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Pin descriptions LQFP144 UFBGA132 LQFP100 LQFP64 WLCSP64 Type(1) I / O Level(2) Table 9. STM32L15xxD pin definitions Pins Pin name Main function(3) (after reset) Alternate functions 1 B2 1 - - PE2 I/O FT 2 A1 2 - - PE3 I/O FT 3 B1 3 - - PE4 I/O FT 4 C2 4 - - PE5 I/O FT 5 D2 5 - - PE6WKUP3 I/O FT 6 E2 6 1 C6 VLCD(4) S 7 C1 7 2 C8 PC13-WKUP2 I/O FT 8 D1 8 3 B8 PC14OSC32_IN(5) I/O 9 E1 9 4 B7 PC15OSC32_OUT I/O 10 D6 - - - PF0 I/O FT 11 D5 - - - PF1 I/O FT 12 D4 - - - PF2 I/O FT 13 E4 - - - PF3 I/O FT 14 F3 - - - PF4 I/O FT 15 F4 - - - PF5 I/O FT 16 F2 10 - 17 G2 11 - 18 G3 - - - VSS_5 VDD_5 PF6 S S I/O FT 19 G4 - - - PF7 I/O FT 20 H4 - - - PF8 I/O FT 21 J6 - - - PF9 I/O FT 22 - - - - PF10 I/O FT 23 F1 12 5 D8 PH0-OSC_IN(6) I 24 G1 13 6 D7 PH1OSC_OUT(6) O 25 H2 14 7 C7 NRST I/O 26 H1 15 8 E8 PC0 I/O FT 27 J2 16 9 F8 PC1 I/O FT PE2 PE3 PE4 PE5 PE6 VLCD PC13 PC14 PC15 PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 28 17 10 D6 PC2 I/O FT PC2 J3 - PC2 I/O FT PC2 K1 - OPAMP3_VINM I OPAMP3 _VINM TIM3_ETR/LCD_SEG38/FSMC_A23/TRACECLK TIM3_CH1/LCD_SEG39/FSMC_A19/TRACED0 TIM3_CH2/FSMC_A20/TRACED1 TIM9_CH1/FSMC_A21/TRACED2 WKUP3/RTC_TAMP3/TIM9_CH2/TRACED3 WKUP2/RTC_TAMP1/RTC_TS/RTC_OUT OSC32_IN OSC32_OUT FSMC_A0 FSMC_A1 FSMC_A2 FSMC_A3 FSMC_A4 FSMC_A5 TIM5_CH1/TIM5_ETR/ADC_IN27 TIM5_CH2/ADC_IN28/COMP1_INP TIM5_CH3/ADC_IN29/COMP1_INP TIM5_CH4/ADC_IN30/COMP1_INP ADC_IN30/COMP1_INP OSC_IN OSC_OUT LCD_SEG18/ADC_IN10/COMP1_INP LCD_SEG19/ADC_IN11/COMP1_INP /OPAMP3_VINP LCD_SEG20/ADC_IN12/COMP1_INP /OPAMP3_VINM LCD_SEG20/ADC_IN12/COMP1_INP Doc ID 022027 Rev 5 37/141 Pin descriptions STM32L151xD STM32L152xD LQFP144 UFBGA132 LQFP100 LQFP64 WLCSP64 Type(1) I / O Level(2) Table 9. STM32L15xxD pin definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions 29 K2 18 11 F7 PC3 I/O PC3 LCD_SEG21/ADC_IN13/COMP1_INP /OPAMP3_VOUT 30 J1 19 12 E7 VSSA S 31 - 20 - - VREF- S 32 L1 21 - - VREF+ S 33 M1 22 13 G8 VDDA S 34 L2 23 14 F6 PA0-WKUP1 I/O FT VSSA VREFVREF+ VDDA PA0 WKUP1/RTC_TAMP2/TIM2_CH1_ETR/TIM5_CH1/ USART2_CTS/ADC_IN0/COMP1_INP 35 M2 24 15 E6 PA1 I/O FT PA1 TIM2_CH2/TIM5_CH2/ USART2_RTS/LCD_SEG0/ ADC_IN1/COMP1_INP/OPAMP1_VINP 36 25 16 H8 PA2 I/O FT PA2 TIM2_CH3/TIM5_CH3/TIM9_CH1/USART2_TX/ LCD_SEG1/ADC_IN2/ COMP1_INP/OPAMP1_VINM K3 - PA2 I/O FT PA2 TIM2_CH3/TIM5_CH3/TIM9_CH1/USART2_TX/ LCD_SEG1/ADC_IN2/COMP1_INP M3 - OPAMP1_VINM I OPAMP1_ VINM 37 L3 26 17 G7 PA3 I/O PA3 TIM2_CH4/TIM5_CH4/TIM9_CH2/USART2_RX/ LCD_SEG2/ ADC_IN3/COMP1_INP/OPAMP1_VOUT 38 - 27 18 F5 VSS_4 S 39 - 28 19 G6 VDD_4 S 40 J4 29 20 H7 PA4 I/O VSS_4 VDD_4 PA4 SPI1_NSS/SPI3_NSS/I2S3_WS/USART2_CK/ ADC_IN4/DAC_OUT1/COMP1_INP 41 K4 30 21 E5 PA5 I/O PA5 TIM2_CH1_ETR/SPI1_SCK/ADC_IN5/DAC_OUT2/ COMP1_INP 42 L4 31 22 G5 PA6 I/O FT PA6 TIM3_CH1/TIM10_CH1/SPI1_MISO/LCD_SEG3/ ADC_IN6/COMP1_INP/OPAMP2_VINP 43 32 23 G4 PA7 I/O FT PA7 TIM3_CH2/TIM11_CH1/ SPI1_MOSI/LCD_SEG4/ ADC_IN7/COMP1_INP/OPAMP2_VINM J5 - PA7 I/O FT PA7 TIM3_CH2/TIM11_CH1/ SPI1_MOSI/LCD_SEG4/ ADC_IN7/COMP1_INP M4 - OPAMP2_VINM I OPAMP2_VI NM 44 K5 33 24 H6 PC4 I/O FT PC4 LCD_SEG22/ADC_IN14/COMP1_INP 45 L5 34 25 H5 PC5 I/O FT PC5 LCD_SEG23/ADC_IN15/COMP1_INP 46 M5 35 26 H4 PB0 I/O PB0 TIM3_CH3/LCD_SEG5/ADC_IN8/COMP1_INP/ VREF_OUT/ OPAMP2_VOUT 47 M6 36 27 F4 PB1 I/O FT PB1 TIM3_CH4/LCD_SEG6/ADC_IN9/COMP1_INP/ VREF_OUT - - 37 28 H3 PB2 I/O FT PB2/BOOT1 COMP1_INP 48 L6 - - PB2 I/O FT PB2/BOOT1 ADC_IN0b/COMP1_INP 38/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Pin descriptions LQFP144 UFBGA132 LQFP100 LQFP64 WLCSP64 Type(1) I / O Level(2) Table 9. STM32L15xxD pin definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions 49 K6 - - 50 J7 - - 51 E3 - - 52 H3 - - 53 K7 - - 54 J8 - - 55 J9 - - 56 H9 - - 57 G9 - - 58 M7 38 - 59 L7 39 - 60 M8 - - 61 - - - 62 - - - 63 L8 41 - 64 M9 42 - 65 L9 43 - 66 M10 44 - 67 M11 45 - 68 M12 46 - 69 L10 47 29 G3 70 L11 48 30 F3 71 F12 49 31 H2 72 G12 50 32 H1 73 L12 51 33 G2 74 K12 52 34 G1 75 K11 53 35 F2 76 K10 54 36 F1 77 K9 55 - 78 K8 56 - 79 J12 57 - 80 J11 58 - 81 J10 59 - - PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PD8 PD9 PD10 PD11 PD12 I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O I/O I/O S S I/O I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PD8 PD9 PD10 PD11 PD12 ADC_IN1b/COMP1_INP ADC_IN2b/COMP1_INP/FSMC_A6 ADC_IN3b/COMP1_INP/FSMC_A7 ADC_IN6b/COMP1_INP/FSMC_A8 ADC_IN7b/COMP1_INP/FSMC_A9 ADC_IN8b/COMP1_INP/FSMC_A10 ADC_IN9b/COMP1_INP/FSMC_A11 FSMC_D4/ADC_IN22/COMP1_INP FSMC_D5/ADC_IN23/COMP1_INP TIM2_CH1_ETR/FSMC_D6/ ADC_IN24/COMP1_INP TIM2_CH2/ FSMC_D7/ADC_IN25/COMP1_INP TIM2_CH3/FSMC_D8 TIM2_CH4/SPI1_NSS/FSMC_D9 SPI1_SCK/FSMC_D10 SPI1_MISO/FSMC_D11 SPI1_MOSI/FSMC_D12 TIM2_CH3/I2C2_SCL/USART3_TX/LCD_SEG10 TIM2_CH4/I2C2_SDA/ USART3_RX/LCD_SEG11 TIM10_CH1/I2C2_SMBA/SPI2_NSS/I2S2_WS/ USART3_CK/ LCD_SEG12/ADC_IN18/COMP1_INP TIM9_CH1/SPI2_SCK/ I2S2_CK/ USART3_CTS/ LCD_SEG13/ADC_IN19/COMP1_INP TIM9_CH2/SPI2_MISO/ USART3_RTS/LCD_SEG14/ ADC_IN20/COMP1_INP TIM11_CH1/SPI2_MOSI/I2S2_SD/LCD_SEG15/ ADC_IN21/COMP1_INP/RTC_REFIN USART3_TX/LCD_SEG28/FSMC_D13 USART3_RX/LCD_SEG29/FSMC_D14 USART3_CK/LCD_SEG30/FSMC_D15 USART3_CTS/LCD_SEG31/FSMC_A16 TIM4_CH1 / USART3_RTS/LCD_SEG32/FSMC_A17 Doc ID 022027 Rev 5 39/141 Pin descriptions STM32L151xD STM32L152xD LQFP144 UFBGA132 LQFP100 LQFP64 WLCSP64 Type(1) I / O Level(2) Table 9. STM32L15xxD pin definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions 82 H12 60 - 83 - - - 84 - - - 85 H11 61 - 86 H10 62 - 87 G10 - - 88 F9 - - 89 F10 - - 90 E9 - - 91 - - - 92 - - - 93 - - - 94 F6 - - 95 G6 - - 96 E12 63 37 E1 97 E11 64 38 E2 98 E10 65 39 E3 99 D12 66 40 D1 100 D11 67 41 E4 101 D10 68 42 D2 102 C12 69 43 D3 103 B12 70 44 C1 104 A12 71 45 C2 105 A11 72 46 D4 106 C11 73 - 107 F11 74 47 B1 108 G11 75 48 A1 109 A10 76 49 B2 110 A9 77 50 C3 111 B11 78 51 A2 112 C10 79 52 B3 113 B10 80 53 C4 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 VDD_9 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 PA13 PH2 VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 VDD_9 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 JTMSSWDAT PH2 VSS_2 VDD_2 JTCKSWCLK I/O FT JTDI I/O FT PC10 I/O FT PC11 I/O FT PC12 TIM4_CH2/LCD_SEG33/FSMC_A18 TIM4_CH3/LCD_SEG34/FSMC_D0 TIM4_CH4/LCD_SEG35/FSMC_D1 FSMC_A12/ADC_IN10b/COMP1_INP FSMC_A13/ADC_IN11b/COMP1_INP FSMC_A14/ADC_IN12b/COMP1_INP FSMC_A15 TIM3_CH1/I2S2_MCK/LCD_SEG24/SDIO_D6 TIM3_CH2/I2S3_MCK/LCD_SEG25/SDIO_D7 TIM3_CH3/LCD_SEG26/SDIO_D0 TIM3_CH4/LCD_SEG27/SDIO_D1 USART1_CK/MCO/LCD_COM0 USART1_TX / LCD_COM1 USART1_RX / LCD_COM2 USART1_CTS/ USB_DM/SPI1_MISO USART1_RTS/USB_DP/SPI1_MOSI FSMC_A22 TIM2_CH1_ETR/ SPI1_NSS/SPI3_NSS/ I2S3_WS/LCD_SEG17 SPI3_SCK/I2S3_CK/USART3_TX/ UART4_TX/ LCD_SEG28/LCD_SEG40/LCD_COM4/SDIO_D2 SPI3_MISO/USART3_RX/UART4_RX/ LCD_SEG29/LCD_SEG41/LCD_COM5/SDIO_D3 SPI3_MOSI/I2S3_SD/USART3_CK/ UART5_TX/ LCD_SEG30/ LCD_SEG42/LCD_COM6/SDIO_CK 40/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Pin descriptions LQFP144 UFBGA132 LQFP100 LQFP64 WLCSP64 Type(1) I / O Level(2) Table 9. STM32L15xxD pin definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions 114 C9 81 - 115 B9 82 - - 116 C8 83 54 A3 117 B8 84 - 118 B7 85 - 119 A6 86 - 120 F7 - - 121 G7 - - 122 B6 87 - 123 A5 88 - 124 D9 - - 125 D8 - - 126 - - - 127 D7 - - 128 C7 - - 129 C6 - - 130 - - - 131 - - - 132 - - - - 133 A8 89 55 A4 134 A7 90 56 B4 135 C5 91 57 A5 136 B5 92 58 B5 137 B4 93 59 C5 138 A4 94 60 A6 139 A3 95 61 D5 140 B3 96 62 B6 141 C3 97 - 142 A2 98 - 143 D3 99 63 A7 144 C4 100 64 A8 PD0 PD1 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT PD0 PD1 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 JTDO I/O FT NJTRST I/O FT PB5 I/O FT PB6 I/O FT PB7 I BOOT0 I/O FT PB8 I/O FT I/O FT I/O FT S S PB9 PE0 PE1 VSS_3 VDD_3 TIM9_CH1/SPI2_NSS/I2S2_WS/ FSMC_D2 SPI2_SCK/I2S2_CK/FSMC_D3 TIM3_ETR/UART5_RX/LCD_SEG31/LCD_SEG43/ LCD_COM7/SDIO_CMD SPI2_MISO/USART2_CTS/FSMC_CLK SPI2_MOSI/I2S2_SD/USART2_RTS/FSMC_NOE USART2_TX/FSMC_NWE USART2_RX/FSMC_NWAIT TIM9_CH2/USART2_CK/FSMC_NE1 FSMC_NE2 FSMC_NE3 FSMC_NE4 FSMC_A24 FSMC_A25 TIM2_CH2/SPI1_SCK/SPI3_SCK/ I2S3_CK/ LCD_SEG7/COMP2_INM TIM3_CH1/ SPI1_MISO/SPI3_MISO/LCD_SEG8/ COMP2_INP TIM3_CH2 /I2C1_SMBA/SPI1_MOSI/SPI3_MOSI/ I2S3_SD/LCD_SEG9/COMP2_INP TIM4_CH1/I2C1_SCL/USART1_TX/COMP2_INP TIM4_CH2/I2C1_SDA/USART1_RX/PVD_IN/ FSMC_NADV/ COMP2_INP TIM4_CH3/TIM10_CH1/I2C1_SCL/LCD_SEG16/ SDIO_D4 TIM4_CH4/ TIM11_CH1/I2C1_SDA/LCD_COM3/ SDIO_D5 TIM4_ETR/TIM10_CH1/LCD_SEG36 /FSMC_NBL0 TIM11_CH1/LCD_SEG37/FSMC_NBL1 Doc ID 022027 Rev 5 41/141 Pin descriptions STM32L151xD STM32L152xD 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. Applicable to STM32L152xD devices only. In STM32L151xD devices, this pin should be connected to VDD. 5. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038). 6. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO function. 42/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 10. Alternate function input/output Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 Alternate function AFIO15 Doc ID 022027 Rev 5 SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 BOOT0 BOOT0 NRST NRST PA0- WKUP1/ WKUP1 TAMPER2 TIM2_CH1_ ETR TIM5_CH1 USART2_CTS PA1 TIM2_CH2 TIM5_CH2 USART2_RTS PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX PA3 PA4 PA5 PA6 PA7 PA8 MCO PA9 PA10 TIM2_CH4 TIM5_CH4 TIM9_CH2 TIM2_CH1_ETR TIM3_CH1 TIM10_ CH1 TIM3_CH2 TIM11_ CH1 USART2_RX SPI1_NSS SPI3_NSS I2S3_WS USART2_CK SPI1_SCK SPI1_MISO SPI1_MOSI USART1_CK USART1_TX USART1_RX USB LCD FSMC/ SDIO CPRI SYSTEM EVENT OUT SEG0 SEG1 SEG2 SEG3 SEG4 COM0 COM1 COM2 COMP1_INP/ TIMx_IC1_0/ G1IO1 COMP1_INP/ TIMx_IC2_0 G1IO2 COMP1_INP/ TIMx_IC3_0/ G1IO3 COMP1_INP/ TIMx_IC4_0/ G1IO4 COMP1_INP/ TIMx_IC1_1 COMP1_INP/ TIMx_IC2_1 COMP1_INP/ TIMx_IC3_1 G2IO1 COMP1_INP/ TIMx_IC4_1/ G2IO2 TIMx_IC1_2/ G4IO1 TIMx_IC2_2/ G4IO2 TIMx_IC3_2/ G4IO3 EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT Pin descriptions 43/141 Pin descriptions 44/ Table 10. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 Alternate function AFIO15 Doc ID 022027 Rev 5 PA11 PA12 PA13 PA14 PA15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO CPRI SYSTEM SPI1_MISO USART1_CTS SPI1_MOSI USART1_RTS JTMS-SWDIO JTCK-SWCLK JTDI TIM2_CH1_ETR TIM3_CH3 SPI1_NSS SPI3_NSS I2S3_WS TIM3_CH4 BOOT1 JTDO JTRST TIM2_CH2 TIM3_CH1 TIM3_CH2 TIM4_CH1 SPI1_SCK SPI3_SCK I2S3_CK SPI1_MISO SPI3_MISO I2C1_ SMBA SPI1_MOSI SPI3_MOSI I2S3_SD I2C1_SCL USART1_TX TIM4_CH2 I2C1_SDA TIM4_CH3 TIM10_ CH1 TIM4_CH4 TIM11_ CH1 I2C1_SCL I2C1_SDA USART1_RX USBDM USBDP SEG17 SEG5 SEG6 SEG7 SEG8 SEG9 SEG16 COM3 NADV SDIO_D4 SDIO_D5 TIMx_IC4_2/ G4IO4 TIMx_IC1_3/ TIMx_IC2_3/ G5IO1 TIMx_IC3_3/ G5IO2 TIMx_IC4_3/ G5IO3 COMP1_INP/ G3IO1 COMP1_INP/ G3IO2 COMP1_INP/ G3IO3 G6IO1 G6IO2 G6IO3 G6IO4 EVENT OUT EVENT OUT EVENT OUT EVEN TOUT EVEN TOUT EVEN TOUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT STM32L151xD STM32L152xD STM32L151xD STM32L152xD Table 10. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 Alternate function AFIO15 Doc ID 022027 Rev 5 SYSTEM TIM2 PB10 TIM2_CH3 PB11 TIM2_CH4 PB12 PB13 PB14 PB15 RTC_REFIN PC0 PC1 PC2 PC3 PC4 PC5 PC6 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 I2C2_SCL USART3_TX I2C2_SDA TIM10_ CH1 TIM9_ CH1 TIM9_ CH2 TIM11_ CH1 I2C2_SMBA SPI2_NSS I2S2_WS SPI2_SCK I2S2_CK SPI2_MISO SPI2_MOSI I2S2_SD USART3_RX USART3_CK USART3_CTS USART3_RTS TIM3_CH1 I2S2_MCK USB LCD FSMC/ SDIO CPRI SYSTEM SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SDIO_D6 COMP1_INP/ G7IO1 COMP1_INP/ G7IO2 COMP1_INP/ G7IO3 COMP1_INP/ G7IO4 COMP1_INP/ TIMx_IC1_4/ G8IO1 COMP1_INP/ TIMx_IC2_4/ G8IO2 COMP1_INP/ TIMx_IC3_4/ G8IO3 COMP1_INP/ TIMx_IC4_4/ G8IO4 COMP1_INP/ TIMx_IC1_5/ G9IO1 COMP1_INP/ TIMx_IC2_5/ G9IO2 TIMx_IC3_5/ G10IO1 EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT Pin descriptions 45/141 Pin descriptions 46/ Table 10. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 Alternate function AFIO15 Doc ID 022027 Rev 5 SYSTEM PC7 PC8 PC9 PC10 PC11 PC12 PC13WKUP2 WKUP2/ TAMPER1/ TIMESTAMP/ ALARM_OUT/ 512Hz PC14 OSC32_ OSC32_IN IN PC15 OSC32_ OSC32_OUT OUT PD0 PD1 PD2 TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 TIM3_CH2 I2S3_MCK TIM3_CH3 TIM3_CH4 SPI3_SCK I2S3_CK USART3_TX UART4_TX SPI3_MISO USART3_RX UART4_RX SPI3_MOSI I2S3_SD USART3_CK UART5_TX TIM9_CH1 TIM3_ETR SPI2_NSS I2S2_WS SPI2 SCK I2S2_CK UART5_RX USB LCD FSMC/ SDIO CPRI SEG25 SEG26 SEG27 COM4/ SEG28/ SEG40 COM5/ SEG29 /SEG41 COM6/ SEG30/ SEG42 SDIO_D7 SDIO_D0 SDIO_D1 SDIO_D2 SDIO_D3 SDIO_CK TIMx_IC4_5/ G10IO2 TIMx_IC1_6/ G10IO3 TIMx_IC2_6/ G10IO4 TIMx_IC3_6/ G5IO4 TIMx_IC4_6 TIMx_IC1_7 SYSTEM EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT TIMx_IC2_7 EVENT OUT TIMx_IC3_7 EVENT OUT D2 /DA2 D3 /DA3 COM7/ SEG31/ SEG43 SDIO_ CMD TIMx_IC4_7 TIMx_IC1_8 TIMx_IC2_8 TIMx_IC3_8 EVENT OUT EVENT OUT EVENT OUT EVENT OUT STM32L151xD STM32L152xD STM32L151xD STM32L152xD Table 10. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 Alternate function AFIO15 Doc ID 022027 Rev 5 SYSTEM PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PE0 PE1 TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 SPI2_MISO SPI2_MOSI I2S2_SD USART2_CTS USART2_RTS USART2_TX USART2_RX TIM9_CH2 USART2_CK USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1 USART3_RTS TIM4_CH2 TIM4_CH3 TIM4_CH4 TIM4_ETR TIM10_ CH1 TIM11_ CH1 USB LCD FSMC/ SDIO CPRI CLK TIMx_IC4_8 NOE TIMx_IC1_9 NWE TIMx_IC2_9 NWAIT TIMx_IC3_9 NE1 TIMx_IC4_9 SEG28 D13/DA13 TIMx_IC1_10 SEG29 D14/DA14 TIMx_IC2_10 SEG30 D15/DA15 TIMx_IC3_10 SEG31 A16 TIMx_IC4_10 SEG32 A17 TIMx_IC1_11 SEG33 A18 TIMx_IC2_11 SEG34 D0/DA0 TIMx_IC3_11 SEG35 D1/DA1 TIMx_IC4_11 SEG36 NBL0 TIMx_IC1_12 SEG37 NBL1 TIMx_IC2_12 SYSTEM EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT Pin descriptions 47/141 Pin descriptions 48/ Table 10. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 Alternate function AFIO15 Doc ID 022027 Rev 5 SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 PE2 TRACECK TIM3_ETR PE3 TRACED0 TIM3_CH1 PE4 TRACED1 TIM3_CH2 PE5 TRACED2 PE6WKUP3 WKUP3/ TAMPER3 / TRACED3 PE7 TIM9_CH1 TIM9_CH2 PE8 PE9 TIM2_CH1_ETR PE10 TIM2_CH2 PE11 TIM2_CH3 PE12 TIM2_CH4 SPI1_NSS PE13 SPI1_SCK PE14 SPI1_MISO PE15 SPI1_MOSI PF0 USB LCD FSMC/ SDIO CPRI SYSTEM SEG 38 A23 SEG 39 A19 A20 A21 TIMx_IC3_12 TIMx_IC4_12 TIMx_IC1_13 TIMx_IC2_13 EVENT OUT EVENT OUT EVENT OUT EVENT OUT TIMx_IC3_13 EVENT OUT D4/DA4 D5/DA5 D6/DA6 D7/DA7 D8/DA8 COMP1_INP/ TIMx_IC4_13 COMP1_INP/ TIMx_IC1_14 COMP1_INP/ TIMx_IC2_14 COMP1_INP/ TIMx_IC3_14 TIMx_IC4_14 D9/DA9 TIMx_IC1_15 D10/DA10 TIMx_IC2_15 D11/DA11 TIMx_IC3_15 D12/DA12 TIMx_IC4_15 A0 EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT STM32L151xD STM32L152xD STM32L151xD STM32L152xD Table 10. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 Alternate function AFIO15 Doc ID 022027 Rev 5 SYSTEM PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 TIM5_ETR TIM5_CH2 TIM5_CH3 TIM5_CH4 USB LCD FSMC/ SDIO CPRI A1 A2 A3 A4 A5 COMP1_INP G11IO1 COMP1_INP G11IO2 COMP1_INP G11IO3 COMP1_INP G11IO4 COMP1_INP G11IO5 COMP1_INP G3IO4 A6 G3IO5 A7 G9IO3 A8 G9IO4 A9 G2IO3 SYSTEM EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT Pin descriptions 49/141 Pin descriptions 50/ Table 10. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 Alternate function AFIO15 Doc ID 022027 Rev 5 SYSTEM PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO CPRI A10 G2IO4 A11 G2IO5 A12 G7IO5 A13 G7IO6 A14 G7IO7 A15 NE2 NE3 NE4 A24 A25 SYSTEM EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT EVENT OUT STM32L151xD STM32L152xD STM32L151xD STM32L152xD Table 10. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 Alternate function AFIO15 SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO CPRI SYSTEM PG15 PH0OSC _IN OSC_IN PH1OSC _OUT OSC_OUT PH2 EVENT OUT A22 Doc ID 022027 Rev 5 Pin descriptions 51/141 Memory mapping 5 Memory mapping STM32L151xD STM32L152xD Figure 8. Memory map X &&&&& &&&  X%  #ORTEX -)NTERNAL X%   0ERIPHERALS  X#    X!   &3-#REGISTERS  X     X    &3-# EXTERNALMEMORY X     X    0ERIPHERALS  X   32!-  X    .ON VOLATILE MEMORY 2ESERVE D X && & X &&   X &&  & X &&   X && &&& X && &&& X &&   /PTION "YTES "ANK RESE RVED /PT"IOANNK"YTES RESE RVED 3YSTEREMSEMREVMEDORY "ANK 3YSTEMMEMORY "ANK RESERVED X  &&& X  && $ATA %%02/"ANK X    $ATA %%02/" ANK RESE RVED X  &&&& X  &&&& &LASHMEMORY "ANK &LASHMEMORY "ANK X    !LIASEDTO&LASHORSYSTEM MEMORYDEPENDINGON X "//4PINS X  && X   X    X   X  # X    X    X    X    X# X X X X# X X X    X  # X    X    X    X  # X    X    X    X    X  # X    X    X    X    X  # X X    X    X    X    X  # X    X    X    X  # X    X    X    X  # X    X    X    X  # X    X X# X X X  # X    X    X    $-! $-! RESERVED &LASH)NTERF ACE 2## RESERVED #2# RESERVED 0ORT' 0ORT& 0ORT( 0ORT% 0ORT$ 0ORT# 0ORT" 0ORT! RESERVED 53!24  RESERVED 30) 3$)/ RESERVED !$# RESE RVE D 4)- 4)- 4)- %84) 393#&' RESERVED #/-0 2) RESERVED $!# 072 RESERVED BYTE 53" 53"2EG ISTERS )# )# 5!24 5!24 53!24  53!24  RESERVED 30) 30) RESERVED )7$' 77$' 24# ,#$ RESERVED 4)- 4)- 4)- 4)- 4)- 4)- -36 52/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6 Electrical characteristics Electrical characteristics 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3). Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the 1.65 V  VDD  3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2). Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage #P& 34-,XXXPIN 34-,XXXPIN 6). AI Doc ID 022027 Rev 5 AI 53/141 Electrical characteristics 6.1.6 Power supply scheme Figure 11. Power supply scheme STM32L151xD STM32L152xD Standby-power circuitry (OSC32K,RTC, Wake-up logic RTC backup registers) Level shifter GP I/Os VDD N × 100 nF + 1 × 4.7 µF VDD1/2/.../N VSS1/2/.../N VDD VDDA 10 nF + 1 µF VREF 10 nF + 1 µF VREF+ VREF- VSSA O UT IO Logic IN Regulator Kernel logic (CPU, Digital & Memories) ADC Analog: RCs, PLL, ... MS18291V2 6.1.7 Current consumption measurement Figure 12. Current consumption measurement scheme IDD VDD VDDA ai14126b 54/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 11. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS VIN(2) External main supply voltage (including VDDA and VDD)(1) Input voltage on five-volt tolerant pin Input voltage on any other pin |VDDx| |VSSX VSS| VESD(HBM) Variations between different VDD power pins Variations between all different ground pins Electrostatic discharge voltage (human body model) –0.3 VSS  0.3 VSS 0.3 4.0 VDD+4.0 V 4.0 50 mV 50 see Section 6.3.11 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 12 for maximum allowed injected current values. Table 12. Current characteristics Symbol Ratings Max. Unit IVDD Total current into VDD/VDDA power lines (source)(1) 80 IVSS Total current out of VSS ground lines (sink)(1) 80 Output current sunk by any I/O and control pin IIO Output current sourced by any I/O and control pin 25 - 25 mA IINJ(PIN) (2) Injected current on five-volt tolerant I/O(3) Injected current on any other pin (4) +0 /-5 ±5 IINJ(PIN) Total injected current (sum of all I/O and control pins)(5) ± 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.19. 3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 11: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Doc ID 022027 Rev 5 55/141 Electrical characteristics Table 13. Thermal characteristics Symbol Ratings TSTG TJ Storage temperature range Maximum junction temperature STM32L151xD STM32L152xD Value Unit –65 to +150 °C 150 °C 6.3 6.3.1 6.3.2 Operating conditions General operating conditions Table 14. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK fPCLK1 fPCLK2 Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency BOR detector disabled 0 32 0 32 0 32 1.65 3.6 MHz VDD Standard operating voltage BOR detector enabled, at power on 1.8 3.6 V BOR detector disabled, after power on 1.65 3.6 VDDA(1) Analog operating voltage (ADC and DAC not used) Analog operating voltage (ADC or DAC used) 1.65 3.6 Must be the same voltage as VDD(2) 1.8 3.6 V PD Power dissipation at TA = 85 °C(3) TA Temperature range UFBGA132 package 333 mW Maximum power dissipation –40 85 Low power dissipation(4) °C –40 105 TJ Junction temperature range -40 °C  TA  105 °C –40 105 °C 1. When the ADC is used, refer to Table 64: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see ). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see ). Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in Table 14. 56/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 15. Embedded reset and power control block characteristics Symbol Parameter Conditions tVDD(1) VDD rise time rate VDD fall time rate TRSTTEMPO(1) Reset temporization VPOR/PDR Power on/power down reset threshold VBOR0 Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 VPVD0 Brown-out reset threshold 4 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 BOR detector enabled BOR detector disabled BOR detector enabled BOR detector disabled VDD rising, BOR enabled VDD rising, BOR disabled(2) Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Min Typ Max Unit 0  0 1000 µs/V 20  0 1000 2 3.3 ms 0.4 0.7 1.6 1 1.5 1.65 1.3 1.5 1.65 1.67 1.7 1.74 1.69 1.76 1.8 1.87 1.93 1.97 1.96 2.03 2.07 2.22 2.30 2.35 2.31 2.41 2.44 2.45 2.55 2.60 2.54 2.66 2.7 2.68 2.8 2.85 2.78 2.9 2.95 1.8 1.85 1.88 V 1.88 1.94 1.99 1.98 2.04 2.09 2.08 2.14 2.18 2.20 2.24 2.28 2.28 2.34 2.38 2.39 2.44 2.48 2.47 2.54 2.58 2.57 2.64 2.69 2.68 2.74 2.79 2.77 2.83 2.88 2.87 2.94 2.99 2.97 3.05 3.09 3.08 3.15 3.20 Doc ID 022027 Rev 5 57/141 Electrical characteristics STM32L151xD STM32L152xD Table 15. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Vhyst Hysteresis voltage BOR0 threshold - 40 - All BOR and PVD thresholds excepting BOR0 - 100 - mV 1. Guaranteed by characterisation, not tested in production. 2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details. 58/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.3 Embedded internal reference voltage The parameters given in Table 16 are based on characterization results, unless otherwise specified. Table 16. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT (1) out IREFINT Internal reference voltage Internal reference current consumption – 40 °C < TJ < +105 °C 1.202 1.224 1.242 V - 1.4 2.3 µA TVREFINT Internal reference startup time - 2 3 ms VVREF_MEAS VDDA and VREF+ voltage during VREFINT factory measure 2.99 3 3.01 V AVREF_MEAS Accuracy of factory-measured VREF value(2) Including uncertainties due to ADC and VDDA/VREF+ values - - ±5 mV TCoeff(3) ACoeff(3) VDDCoeff(3) Temperature coefficient Long-term stability Voltage coefficient –40 °C < TJ < +105 °C - 0 °C < TJ < +50 °C - 1000 hours, T= 25 °C - 3.0 V < VDDA < 3.6 V - 20 50 ppm/°C - 20 - 1000 ppm - 2000 ppm/V TS_vrefint(3)(4) ADC sampling time when reading the internal reference voltage - 5 10 µs TADC_BUF(3) Startup time of reference voltage buffer for ADC - - 10 µs IBUF_ADC(3) Consumption of reference voltage buffer for ADC - 13.5 IVREF_OUT(3) CVREF_OUT(3) VREF_OUT output current(5) VREF_OUT output load - - - - ILPBUF(3) Consumption of reference voltage buffer for VREF_OUT and COMP - 730 VREFINT_DIV1(3) VREFINT_DIV2(3) VREFINT_DIV3(3) 1/4 reference voltage 1/2 reference voltage 3/4 reference voltage 24 25 49 50 74 75 1. Tested in production. 2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes. 3. Guaranteed by design, not tested in production. 4. Shortest sampling time can be determined in the application by multiple iterations. 5. To guarantee less than 1% VREF_OUT deviation. 25 1 50 1200 26 51 76 µA µA pF nA % VREFINT Doc ID 022027 Rev 5 59/141 Electrical characteristics STM32L151xD STM32L152xD 6.3.4 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 12: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: ● VDD = 3.6 V ● All I/O pins are in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled except when explicitly mentioned ● The Flash memory access time is adjusted depending on fHCLK frequency and voltage range ● Prefetch and 64-bit access are enabled in configurations with 1 wait state The parameters given in Table 17, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 17. Current consumption in Run mode, code with data processing running from Flash Symbol Parameter Conditions fHCLK Max(1) Typ Unit 55 °C 85 °C 105 °C IDD (Run from Flash) Supply current in Run mode, code executed from Flash fHSE = fHCLK up to 16 MHz, included fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) HSI clock source (16 MHz) Range 3, VCORE=1.2 V VOS[1:0] = 11 Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 MSI clock, 65 kHz MSI clock, 524 kHz MSI clock, 4.2 MHz Range 3, VCORE=1.2 V VOS[1:0] = 11 1 MHz 360 500 500 2 MHz 620 750 750 4 MHz 1070 1200 1200 4 MHz 1.30 1.6 1.6 8 MHz 2.4 2.9 2.9 16 MHz 4.6 5.2 5.2 8 MHz 2.9 3.5 3.5 16 MHz 5.7 6.5 6.5 32 MHz 10.4 12 12 500 750 µA 1200 1.6 2.9 5.2 3.5 6.5 12 16 MHz 4.5 5.2 5.2 5.2 mA 32 MHz 10.9 12.3 12.3 12.3 65 kHz 0.05 0.079 0.092 0.13 524 kHz 0.17 0.2 0.21 0.25 4.2 MHz 1.0 1.1 1.1 1.2 1. Based on characterization, not tested in production, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). 60/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 18. Symbol Current consumption in Run mode, code with data processing running from RAM Parameter Conditions fHCLK Max(1) Typ Unit 55 °C 85 °C 105 °C IDD (Run from RAM) Supply current in Run mode, code executed from RAM, Flash switched off fHSE = fHCLK up to 16 MHz, included fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) HSI clock source (16 MHz) Range 3, VCORE=1.2 V VOS[1:0] = 11 Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 MSI clock, 65 kHz Range 3, MSI clock, 524 kHz VCORE=1.2 V MSI clock, 4.2 MHz VOS[1:0] = 11 1 MHz 310 470 470 470 2 MHz 590 780 780 780 µA 4 MHz 1030 1200 1200 1200(3) 4 MHz 1.2 1.5 1.5 1.5 8 MHz 2.3 3 3 3 16 MHz 4.3 5 5 5 8 MHz 2.7 3.5 3.5 3.5 16 MHz 5.0 5.55 5.55 5.55 32 MHz 9.8 10.9 10.9 10.9 mA 16 MHz 4.3 4.8 4.8 4.8 32 MHz 10.1 11.7 11.7 11.7 65 kHz 40 48.5 63 100 524 kHz 148 175 183 215 µA 4.2 MHz 990 1032 1034 1100 1. Based on characterization, not tested in production, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). 3. Tested in production. Doc ID 022027 Rev 5 61/141 Electrical characteristics Table 19. Current consumption in Sleep mode Symbol Parameter Conditions Supply current in Sleep mode, code executed from RAM, Flash switched OFF fHSE = fHCLK up to 16 MHz, included fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) HSI clock source (16 MHz) Range 3, VCORE=1.2 V VOS[1:0] = 11 Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 IDD (Sleep) MSI clock, 65 kHz MSI clock, 524 kHz MSI clock, 4.2 MHz Range 3, VCORE=1.2 V VOS[1:0] = 11 Range 3, VCORE=1.2 V VOS[1:0] = 11 Supply current in Sleep mode, code executed from Flash HSE = 16 MHz(2) (PLL ON for fHCLK above 16 MHz) HSI clock source (16 MHz) Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 IDD (Sleep) Supply current in Sleep mode, code executed from Flash MSI clock, 65 kHz MSI clock, 524 kHz MSI clock, 4.2 MHz Range 3, VCORE=1.2V VOS[1:0] = 11 STM32L151xD STM32L152xD fHCLK Max(1) Typ Unit 55 °C 85 °C 105 °C 1 MHz 180 220 220 220 2 MHz 225 300 300 300 4 MHz 300 380 380 380(3) 4 MHz 360 500 500 500 8 MHz 570 700 700 700 16 MHz 990 1100 1100 1100 8 MHz 675 800 800 800 16 MHz 1150 1250 1250 1250 32 MHz 2300 2700 2700 2700 µA 16 MHz 1025 1100 1100 1100 32 MHz 2460 2700 2700 2700 65 kHz 30 36 46 72 524 kHz 50 58 67 92 4.2 MHz 210 245 251 273 1 MHz 190 250 250 250 2 MHz 235 300 300 300 4 MHz 315 380 380 380 4 MHz 390 500 500 500 8 MHz 600 700 700 700 16 MHz 1000 1120 1120 1120 8 MHz 690 800 800 800 µA 16 MHz 1160 1300 1300 1300 32 MHz 2310 2700 2700 2700 16 MHz 1040 1160 1160 1160 32 MHz 2500 2800 2800 2800 65 kHz 42 50 60 90 524 kHz 63 72 82 110 µA 4.2 MHz 230 263 265 290 62/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 1. Based on characterization, not tested in production, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register) 3. Tested in production. Table 20. Current consumption in Low power run mode Symbol Parameter Conditions IDD (LP Run) Supply current in Low power run mode All peripherals OFF, code executed from RAM, Flash switched OFF, VDD from 1.65 V to 3.6 V MSI clock, 65 kHz fHCLK = 32 kHz MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz All peripherals OFF, code executed from Flash, VDD from 1.65 V to 3.6 V MSI clock, 65 kHz fHCLK = 32 kHz MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz IDD max (LP Run) Max allowed current in Low power run mode VDD from 1.65 V to 3.6 V TA = -40 °C to 25 °C TA = 85 °C TA = 105 °C TA =-40 °C to 25 °C TA = 85 °C TA = 105 °C TA = -40 °C to 25 °C TA = 55 °C TA = 85 °C TA = 105 °C TA = -40 °C to 25 °C TA = 85 °C TA = 105 °C TA = -40 °C to 25 °C TA = 85 °C TA = 105 °C TA = -40 °C to 25 °C TA = 55 °C TA = 85 °C TA = 105 °C 1. Based on characterization, not tested in production, unless otherwise specified. Typ Max (1) Unit 11 14 26 32 53 72 18 21 33 40 60 78 36 41 39 44 50 58 78 95 36 40.5 53 60 µA 81 100 44 49 61 67 89 107 64 71 68 73 80 88 101 110 - 200 Doc ID 022027 Rev 5 63/141 Electrical characteristics STM32L151xD STM32L152xD Table 21. Current consumption in Low power sleep mode Symbol Parameter Conditions Typ Max (1) Unit MSI clock, 65 kHz fHCLK = 32 kHz Flash OFF TA = -40 °C to 25 °C 4.4 - MSI clock, 65 kHz TA = -40 °C to 25 °C 18 21 fHCLK = 32 kHz TA = 85 °C 24 27 All Flash ON TA = 105 °C 35 43 peripherals OFF, VDD MSI clock, 65 kHz TA = -40 °C to 25 °C 18.6 21 from 1.65 V fHCLK = 65 kHz, TA = 85 °C 24.5 28 to 3.6 V Flash ON TA = 105 °C 35 42 TA = -40 °C to 25 °C 22 25 Supply IDD (LP Sleep) current in Low power sleep MSI clock, 131 kHz fHCLK = 131 kHz, Flash ON TA = 55 °C TA = 85 °C TA = 105 °C 23.5 26 28.5 31 39 45 mode TA = -40 °C to 25 °C 18 20.5 MSI clock, 65 kHz fHCLK = 32 kHz TA = 85 °C µA 24 27 TIM9 and TA = 105 °C 35 43 USART1 TA = -40 °C to 25 °C 18.6 21 enabled, Flash ON, MSI clock, 65 kHz fHCLK = 65 kHz TA = 85 °C 24.5 28 VDD from TA = 105 °C 35 42 1.65 V to 3.6 V TA = -40 °C to 25 °C 22 25 MSI clock, 131 kHz TA = 55 °C 23.5 26 fHCLK = 131 kHz TA = 85 °C 28.5 31 TA = 105 °C 39 45 IDD max (LP Sleep) Max allowed current in Low power Sleep mode VDD from 1.65 V to 3.6 V - 200 1. Based on characterization, not tested in production, unless otherwise specified. 64/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 22. Typical and maximum current consumptions in Stop mode Symbol Parameter Conditions Typ Max(1) Unit TA = -40°C to 25°C VDD = 1.8 V 1.5 TA = -40°C to 25°C 1.7 4 LCD OFF TA = 55°C 2.4 6 TA= 85°C 5.4 10 RTC clocked by LSI or TA = 105°C 11.0 23 LSE external clock (32.768kHz), regulator TA = -40°C to 25°C 3.8 6 in LP mode,HSI and HSE OFF (no independent watchdog) LCD ON (static duty)(2) TA = 55°C TA= 85°C 4.4 7 7.4 12 TA = 105°C 14.4 27 TA = -40°C to 25°C 7.8 10 LCD ON TA = 55°C (1/8 duty)(3) TA= 85°C 8.3 11 11.4 16 TA = 105°C 20.5 44 IDD (Stop Supply current in Stop with RTC) mode with RTC enabled TA = -40°C to 25°C 2.1 - LCD OFF TA = 55°C TA= 85°C 2.8 - µA 3.8 - TA = 105°C 11.1 - TA = -40°C to 25°C 4.2 - RTC clocked by LSE external quartz (32.768kHz), regulator LCD ON (static TA = 55°C duty)(2) TA= 85°C TA = 105°C 4.8 7.9 15.0 - in LP mode, HSI and TA = -40°C to 25°C 8.2 - HSE OFF (no independent watchdog(4) LCD ON (1/8 TA = 55°C duty)(3) TA= 85°C 8.7 11.9 - TA = 105°C 21.4 - TA = -40°C to 25°C VDD = 1.8V 1.6 - LCD OFF TA = VDD -40°C to = 3.0V 25°C 1.9 - TA = -40°C to 25°C VDD = 3.6V 2.1 - Doc ID 022027 Rev 5 65/141 Electrical characteristics STM32L151xD STM32L152xD Table 22. Typical and maximum current consumptions in Stop mode (continued) Symbol Parameter Conditions Typ Max(1) Unit Regulator in LP mode, HSI and HSE OFF, independent watchdog TA = -40°C to 25°C 1.6 2.2 and LSI enabled IDD (Stop) Supply current in Stop mode (RTC disabled) TA = -40°C to 25°C 0.65 1 µA Regulator in LP mode, LSI, HSI TA = 55°C and HSE OFF (no independent 1.3 3 watchdog) TA= 85°C 4.4 9 TA = 105°C 10.0 22(5) IDD Supply current during (WU from wakeup from Stop mode Stop) MSI = 4.2 MHz MSI = 1.05 MHz MSI = 65 kHz(6) 2 - TA = -40°C to 25°C 1.45 - mA 1.45 - 1. Based on characterization, not tested in production, unless otherwise specified. 2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected. 3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 5. Tested in production. 6. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part of the wakeup period, the current corresponds the Run mode current. Table 23. Typical and maximum current consumptions in Standby mode Symbol Parameter Conditions IDD (Standby with RTC) Supply current in Standby mode with RTC enabled TA = -40 °C to 25 °C RTC clocked by LSI (no independent watchdog) TA = 55 °C TA= 85 °C TA = 105 °C RTC clocked by LSE external quartz(no independent watchdog)(3) TA = -40 °C to 25 °C TA = 55 °C TA= 85 °C TA = 105 °C Independent watchdog and LSI enabled TA = -40 °C to 25 °C IDD Supply current in Standby (Standby) mode (RTC disabled) TA = -40 °C to 25 °C Independent watchdog and TA = 55 °C LSI OFF TA = 85 °C TA = 105 °C IDD Supply current during wakeup (WU from time from Standby mode Standby) TA = -40 °C to 25 °C 1. Based on characterization, not tested in production, unless otherwise specified Typ Max(1) Unit 1.3 1.9 1.44 2.2 1.90 4 3.05 8.3(2) 1.7 - 1.84 - 2.33 - 3.59 µA 1 1.7 0.35 0.6 0.47 0.9 1.2 2.75 2.9 7(2) 1 - 66/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 2. Tested in production. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors. Doc ID 022027 Rev 5 67/141 Electrical characteristics STM32L151xD STM32L152xD Wakeup time from low-power mode The wakeup times given in the following table are measured with the MSI RC oscillator. The clock source used to wake up the device depends on the current operating mode: ● Sleep mode: the clock source is the clock that was set before entering Sleep mode ● Stop mode: the clock source is the MSI oscillator in the range configured before entering Stop mode ● Standby mode: the clock source is the MSI oscillator running at 2.1 MHz All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 24. Typical and maximum timings in Low power modes Symbol Parameter Conditions Typ Max(1) Unit tWUSLEEP tWUSLEEP_LP tWUSTOP tWUSTDBY Wakeup from Sleep mode Wakeup from Low power sleep mode fHCLK = 262 kHz fHCLK = 32 MHz fHCLK = 262 kHz Flash enabled fHCLK = 262 kHz Flash switched OFF 0.4 - 46 - 46 - Wakeup from Stop mode, regulator in Run mode fHCLK = fMSI = 4.2 MHz 8.2 - fHCLK = fMSI = 4.2 MHz Voltage range 1 and 2 7.7 8.9 fHCLK = fMSI = 4.2 MHz Voltage range 3 8.2 13.1 µs Wakeup from Stop mode, fHCLK = fMSI = 2.1 MHz regulator in low power mode fHCLK = fMSI = 1.05 MHz fHCLK = fMSI = 524 kHz fHCLK = fMSI = 262 kHz fHCLK = fMSI = 131 kHz fHCLK = MSI = 65 kHz Wakeup FWU bit from =1 Standby mode fHCLK = MSI = 2.1 MHz 10.2 16 31 57 112 221 58 13.4 20 37 66 123 236 104 Wakeup FWU bit from =0 Standby mode fHCLK = MSI = 2.1 MHz 2.6 3.25 ms 1. Based on characterization, not tested in production, unless otherwise specified 68/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions: ● all I/O pins are in input mode with a static value at VDD or VSS (no load) ● all peripherals are disabled unless otherwise mentioned ● the given value is calculated by measuring the current consumption – with all peripherals clocked off – with only one peripheral clocked on Table 25. Peripheral current consumption(1) Typical consumption, VDD = 3.0 V, TA = 25 °C Peripheral Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low power sleep and run TIM2 TIM3 13 11 9 11 12 10 9 11 TIM4 TIM5 TIM6 TIM7 LCD 12 10 9 11 16 13 11 14 4 4 4 4 4 4 4 4 4 3 3 4 WWDG 3 SPI2 8 SPI3 7 APB1 USART2 8 2.5 2.5 3 7 9 7.5 6 7 6 7 7 7 USART3 8 7 7 7 USART4 8 7 7 7 USART5 8 7 7 7 I2C1 8 7 6 7 I2C2 7 6 5 6 USB PWR DAC COMP 15 7 7 7 3 3 3 3 6 5 4.5 5 4 3.5 3.5 4 Unit µA/MHz (fHCLK) Doc ID 022027 Rev 5 69/141 Electrical characteristics STM32L151xD STM32L152xD Table 25. Peripheral current consumption(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 °C Peripheral Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low power sleep and run SYSCFG & RI 3 2 2 3 TIM9 8 7 6 7 TIM10 6 5 5 5 APB2 TIM11 6 5 5 5 ADC(2) 10 8 7 8 SDIO 20 6 5 6 SPI1 4 4 4 4 USART1 8 7 6 7 GPIOA 7 6 5 6 GPIOB 7 6 5 6 GPIOC 7 6 5 6 GPIOD 7 6 5 6 GPIOE 7 6 5 6 GPIOF 7 6 5 6 AHB GPIOG 7 6 5 6 GPIOH 2 2 1 2 CRC FLASH 0.5 0.5 0.5 1 26 26 29 -(3) DMA1 18 15 13 18 DMA2 16 14 12 16 FSMC 15 12 10 12 All enabled 279 221 219 215 Unit µA/MHz (fHCLK) 70/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 25. Peripheral current consumption(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 °C Peripheral Range 1, Range 2, Range 3, VCORE= 1.8 V VCORE= 1.5 V VCORE= 1.2 V Low power sleep and Unit VOS[1:0] = VOS[1:0] = VOS[1:0] = run 01 10 11 IDD (RTC) 0.4 IDD (LCD) IDD (4) (ADC) IDD (5) (DAC) 3.1 1450 340 IDD (COMP1) 0.16 µA Slow mode 2 IDD (COMP2) Fast mode 5 IDD (PVD / (6) BOR) 2.6 IDD (IWDG) 0.25 1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz (range 3), fHCLK = 64kHz (Low power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production. 2. HSI oscillator is OFF for this measure. 3. In low power sleep and run mode, the Flash memory must always be in power-down mode. 4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI consumption not included). 5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD/2. DAC is in buffered mode, output is left floating. 6. Including supply current of internal reference voltage. 6.3.5 External clock source characteristics High-speed external user clock generated from an external source Table 26. High-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE) User external clock source frequency OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time OSC_IN rise or fall time OSC_IN input capacitance 1 8 32 MHz 0.7VDD - VDD V VSS - 0.3VDD 12 - - ns - - 20 - 2.6 - pF Doc ID 022027 Rev 5 71/141 Electrical characteristics STM32L151xD STM32L152xD Table 26. High-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit DuCy(HSE) Duty cycle 45 - 55 % IL OSC_IN Input leakage current VSS  VIN  VDD - - ±1 µA 1. Guaranteed by design, not tested in production. 72/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 27. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fLSE_ext User external clock source frequency 1 32.768 1000 kHz VLSEH VLSEL OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage 0.7VDD - VDD V VSS - 0.3VDD tw(LSE) tw(LSE) OSC32_IN high or low time 465 - tr(LSE) tf(LSE) OSC32_IN rise or fall time - - CIN(LSE) OSC32_IN input capacitance - 0.6 DuCy(LSE) Duty cycle 45 - IL OSC32_IN Input leakage current VSS  VIN  VDD - - 1. Guaranteed by design, not tested in production ns 10 - pF 55 % ±1 µA Figure 13. Low-speed external clock source AC timing diagram 6,3%( 6,3%,   TR,3% TF,3% 4,3% T7,3% T7,3% T %84%2 .!, #,/#+ 3/52# % F,3%?EXT /3#?). ), 34-,XX AI Doc ID 022027 Rev 5 73/141 Electrical characteristics STM32L151xD STM32L152xD Figure 14. High-speed external clock source AC timing diagram 6(3%( 6(3%,   TR(3% TF(3% 4(3% T7(3% T7(3% T %84%2 .!, F(3%?EXT #,/#+ 3/52# % /3# ?). ), 34-,XX AI High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 28. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 74/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 28. HSE 1-24 MHz oscillator characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit fOSC_IN Oscillator frequency 1 RF Feedback resistor - 200 Recommended load C capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 - 20 IHSE HSE driving current VDD= 3.3 V, VIN = VSS with 30 pF load - - IDD(HSE) HSE oscillator power consumption C = 20 pF fOSC = 16 MHz C = 10 pF fOSC = 16 MHz --- gm Oscillator transconductance Startup 3.5 - tSU(HSE) (4) Startup time VDD is stabilized -1 24 MHz - k - pF 3 mA 2.5 (startup) 0.7 (stabilized) mA 2.5 (startup) 0.46 (stabilized) - mA /V - ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 15). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Doc ID 022027 Rev 5 75/141 Electrical characteristics STM32L151xD STM32L152xD Figure 15. HSE oscillator circuit diagram 2M ,M #/ #M 2ESONATOR #, /3#?). 2ESONATOR F(3%TOCORE 2& GM #ONSUMPTION CONTROL /3#?/54 #, 34- AI 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 29. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol Parameter Conditions Min Typ Max Unit fLSE Low speed external oscillator frequency - 32.768 - kHz RF Feedback resistor - Recommended load capacitance C(2) versus equivalent serial RS = 30 k - resistance of the crystal (RS)(3) ILSE LSE driving current VDD = 3.3 V, VIN = VSS - IDD (LSE) LSE oscillator current consumption VDD = 1.8 V - VDD = 3.0 V - VDD = 3.6V - gm Oscillator transconductance tSU(LSE)(4) Startup time 3 VDD is stabilized - 1.2 - M 8 - pF - 1.1 µA 450 - 600 - nA 750 - - µA/V 1 - s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details. 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. 76/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Note: Caution: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 16. Typical application with a 32.768 kHz crystal 2ESONATORWITH INTEGRATEDCAPACITORS #, K( Z RESONATOR #, /3#?). 2& /3#?/5 4 "IAS CONTROLLED GAIN F,3% 34-,XXX AI Doc ID 022027 Rev 5 77/141 Electrical characteristics STM32L151xD STM32L152xD 6.3.6 Internal clock source characteristics The parameters given in Table 30 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 30. HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency (1)(2) HSI user-trimmed TRIM resolution Accuracy of the ACCHSI(2) factory-calibrated HSI oscillator tSU(HSI)(2) HSI oscillator startup time VDD = 3.0 V Trimming code is not a multiple of 16 Trimming code is a multiple of 16 VDDA = 3.0 V, TA = 25 °C VDDA = 3.0 V, TA = 0 to 55 °C VDDA = 3.0 V, TA = -10 to 70 °C VDDA = 3.0 V, TA = -10 to 85 °C VDDA = 3.0 V, TA = -10 to 105 °C VDDA = 1.65 V to 3.6 V TA = -40 to 105 °C - 16 - MHz - 0.4 0.7 % - - 1.5 % -1(3) - 1(3) % -1.5 - 1.5 % -2 - 2% -2.5 - 2% -4 - 2% -4 - 3% - 3.7 6 µs IDD(HSI)(2) HSI oscillator power consumption - 100 140 µA 1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). 2. Based on characterization, not tested in production. 3. Tested in production. Low-speed internal (LSI) RC oscillator Table 31. LSI oscillator characteristics Symbol Parameter Min Typ Max fLSI(1) LSI frequency 26 38 56 DLSI(2) tsu(LSI)(3) IDD(LSI)(3) LSI oscillator frequency drift 0°C  TA  85°C LSI oscillator startup time LSI oscillator power consumption -10 - 4 - - 200 - 400 510 1. Tested in production. 2. This is a deviation for an individual part, once the initial frequency has been measured. 3. Guaranteed by design, not tested in production. Unit kHz % µs nA 78/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Multi-speed internal (MSI) RC oscillator Table 32. MSI oscillator characteristics Symbol Parameter fMSI Frequency after factory calibration, done at VDD= 3.3 V and TA = 25 °C ACCMSI Frequency error after factory calibration DTEMP(MSI)(1) MSI oscillator frequency drift 0 °C  TA  85 °C DVOLT(MSI)(1) MSI oscillator frequency drift 1.65 V  VDD  3.6 V, TA = 25 °C IDD(MSI)(2) MSI oscillator power consumption Electrical characteristics Condition MSI range 0 MSI range 1 MSI range 2 MSI range 3 MSI range 4 MSI range 5 MSI range 6 Typ Max Unit 65.5 131 - kHz 262 524 1.05 2.1 - MHz 4.2 0.5 - % 3 - % - 2.5 %/V MSI range 0 0.75 MSI range 1 1 MSI range 2 1.5 MSI range 3 2.5 - µA MSI range 4 4.5 MSI range 5 8 MSI range 6 15 - Doc ID 022027 Rev 5 79/141 Electrical characteristics STM32L151xD STM32L152xD Table 32. MSI oscillator characteristics (continued) Symbol Parameter Condition Typ Max Unit tSU(MSI) MSI oscillator startup time tSTAB(MSI)(2) MSI oscillator stabilization time fOVER(MSI) MSI oscillator frequency overshoot MSI range 0 30 - MSI range 1 20 - MSI range 2 15 - MSI range 3 10 - MSI range 4 6- MSI range 5 5- MSI range 6, Voltage range 1 3.5 and 2 MSI range 6, Voltage range 3 5 - µs MSI range 0 - 40 MSI range 1 - 20 MSI range 2 - 10 MSI range 3 - 4 MSI range 4 - 2.5 MSI range 5 - 2 MSI range 6, Voltage range 1 - 2 and 2 MSI range 3, Voltage range 3 - 3 Any range to range 5 Any range to range 6 - 4 MHz - 6 1. This is a deviation for an individual part, once the initial frequency has been measured. 2. Based on characterization, not tested in production. 80/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.7 6.3.8 PLL characteristics The parameters given in Table 33 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 33. PLL characteristics Symbol Parameter Value Min Typ Max(1) Unit fPLL_IN PLL input clock(2) PLL input clock duty cycle 2 - 45 - 24 MHz 55 % fPLL_OUT tLOCK PLL output clock Worst case PLL lock time PLL input = 2 MHz PLL VCO = 96 MHz 2 - - 100 32 MHz 130 µs Jitter Cycle-to-cycle jitter -  600 ps IDDA(PLL) IDD(PLL) Current consumption on VDDA Current consumption on VDD - 220 450 µA - 120 150 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. Memory characteristics The characteristics are given at TA = -40 to 105 °C unless otherwise specified. RAM memory Table 34. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode(1) STOP mode (or RESET) 1.65 - - V 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). Doc ID 022027 Rev 5 81/141 Electrical characteristics STM32L151xD STM32L152xD Flash memory and data EEPROM Table 35. Flash memory and data EEPROM characteristics Symbol Parameter Conditions Min Operating voltage VDD Read / Write / Erase 1.65 tprog Programming time for word or half-page Erasing Programming - Average current during the whole programming / - erase operation IDD Maximum current (peak) TA25 °C, VDD = 3.6 V during the whole programming / erase - operation 1. Guaranteed by design, not tested in production. Typ Max(1) Unit - 3.6 V 3.28 3.94 ms 3.28 3.94 600 900 µA 1.5 2.5 mA Table 36. Flash memory and data EEPROM endurance and retention Symbol Parameter Conditions Value Min(1) Typ Max Unit NCYC(2) Cycling (erase / write) Program memory Cycling (erase / write) EEPROM data memory TA-40°C to 105 °C tRET(2) Data retention (program memory) after 10 kcycles at TA = 85 °C Data retention (EEPROM data memory) after 300 kcycles at TA = 85 °C TRET = +85 °C Data retention (program memory) after 10 kcycles at TA = 105 °C Data retention (EEPROM data memory) after 300 kcycles at TA = 105 °C TRET = +105 °C 1. Based on characterization not tested in production. 2. Characterization is done according to JEDEC JESD22-A117. 10 300 - kcycles - 30 - - 30 - years 10 - - 10 - - 82/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.9 FSMC characteristics Asynchronous waveforms and timings Figure 17 through Figure 20 represent asynchronous waveforms and Table 37 through Table 40 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● AddressSetupTime = 0 (AddressSetupTime = 1, for asynchronous multiplexed modes) ● AddressHoldTime = 1 ● DataSetupTime = 1 Figure 17. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms &3-#?.% &3-#?./% T V./%?.% TW.% T W./% T H.%?./% &3-#?.7% &3-#?!;= &3-#?.",;= TV!?.% TV",?.% !DDRESS T H!?./% T H",?./% &3-#?$;= &3-#?.!$6  T V.!$6?.% TW.!$6 TSU$ATA?./% TSU$ATA?.% $ATA 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. T H$ATA?.% TH$ATA?./% -36 Doc ID 022027 Rev 5 83/141 Electrical characteristics STM32L151xD STM32L152xD Table 37. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time THCLK -2 tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0 tw(NOE) FSMC_NOE low time THCLK th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 tv(A_NE) FSMC_NEx low to FSMC_A valid - th(A_NOE) Address hold time after FSMC_NOE high THCLK + 1.5 tv(BL_NE) FSMC_NEx low to FSMC_BL valid - th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 2*THCLK - 0.5 tsu(Data_NE) Data to FSMC_NEx high setup time THCLK tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK th(Data_NOE) Data hold time after FSMC_NOE high 0 th(Data_NE) Data hold time after FSMC_NEx high 0 tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - tw(NADV) FSMC_NADV low time - 1. CL = 30 pF. THCLK ns 2 ns THCLK - 1 ns - ns 4 ns - ns 0.5 ns - ns - ns - ns - ns - ns 2 ns THCLK ns Figure 18. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx tw(NE) FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV(1) tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) t v(NADV_NE) tw(NADV) th(A_NWE) Address th(BL_NWE) NBL th(Data_NWE) Data 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. t h(NE_NWE) ai14990 84/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 38. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tw(NWE) FSMC_NWE low time th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) FSMC_NEx low to Data valid th(Data_NWE) Data hold time after FSMC_NWE high 1. CL = 30 pF. 2*THCLK -3 0.5 THCLK - 2 THCLK - 2.5 THCLK - 2.5 THCLK - 4 THCLK - 2.5 2*THCLK +2 ns 1 ns THCLK + 3 ns - ns 0 ns - ns 0 ns - ns THCLK ns - ns Figure 19. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE tv(NOE_NE) tw(NE) t h(NE_NOE) FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_AD[15:0] FSMC_NADV t w(NOE) tv(A_NE) tv(BL_NE) Address NBL th(A_NOE) th(BL_NOE) t v(A_NE) Address t v(NADV_NE) tw(NADV) tsu(Data_NE) tsu(Data_NOE) Data th(AD_NADV) th(Data_NE) th(Data_NOE) ai14892b Doc ID 022027 Rev 5 85/141 Electrical characteristics STM32L151xD STM32L152xD Table 39. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3*THCLK - 1.5 3*THCLK + 1 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 2*THCLK - 1 2*THCLK ns tw(NOE) FSMC_NOE low time THCLK - 0.5 THCLK + 0.5 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 5 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1.5 2 ns tw(NADV) FSMC_NADV low time THCLK - 0.5 THCLK ns th(AD_NADV) FSMC_AD(address) valid hold time after FSMC_NADV high THCLK - 6 - ns th(A_NOE) Address hold time after FSMC_NOE high 2*THCLK - 1 - ns th(BL_NOE) FSMC_BL time after FSMC_NOE high 1.5 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 30 pF. Figure 20. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx tw(NE) FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_AD[15:0] FSMC_NADV tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) t v(A_NE) Address t v(NADV_NE) tw(NADV) th(A_NWE) Address th(BL_NWE) NBL t v(Data_NADV) Data th(AD_NADV) t h(NE_NWE) th(Data_NWE) ai14891B 86/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 40. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Parameter Min Max Unit tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD (address) valid hold time after FSMC_NADV high 4*THCLK - 3 4*THCLK + 2 ns THCLK THCLK + 1 ns 2*THCLK - 2 2*THCLK + 4 ns THCLK - 2.5 - ns - 6 ns 1.5 2 ns THCLK - 4 THCLK + 4 ns THCLK - 5 - ns th(A_NWE) Address hold time after FSMC_NWE high th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high 1. CL = 30 pF. THCLK - 2.5 - ns THCLK - 3 - ns - 0.5 ns - THCLK + 6 ns THCLK - 2.5 - ns Doc ID 022027 Rev 5 87/141 Electrical characteristics STM32L151xD STM32L152xD Synchronous waveforms and timings Figure 21 through Figure 24 represent synchronous waveforms and Table 42 through Table 44 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ● CLKDivision = 1; ● DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Figure 21. Synchronous multiplexed NOR/PSRAM read timings TW#,+ TW#,+ "53452. &3-#?#,+ &3-#?.%X TD#,+, .!$6, &3-#?.!$6 &3-#?!;= $ATALATENCY TD#,+, .%X, TD#,+, .!$6( TD#,+, !6 T D#,+, .%X( TD#,+, !)6 TD#,+, ./%, TD#,+, ./%( &3-#?./% TD#,+, !$6 &3-#?!$;= TD#,+, !$)6 TSU!$6 #,+( !$;= TSU.7!)46 #,+( TH#,+( !$6 TSU!$6 #,+( $ $ TH#,+( !$6 TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B 7!)40/, B &3-#?.7!)4 7!)4#&'B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 TSU.7!)46 #,+( TH#,+( .7!)46 AIG 88/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 41. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Parameter Min Max Unit tw(CLK) td(CLKL-NExL) td(CLKL-NExH) FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x = 0...2) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2*THCLK 0.5 - ns - 0 ns THCLK + 1.5 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 1. CL = 30 pF. 3.5 0 2.5 0 6 4 TBD TBD 3 ns - ns 0 ns - ns THCLK - 1 ns - ns 4 ns - ns - ns - ns - ns - ns Doc ID 022027 Rev 5 89/141 Electrical characteristics STM32L151xD STM32L152xD Figure 22. Synchronous multiplexed PSRAM write timings TW#,+ &3-#?#,+ TW#,+ &3-#?.%X TD#,+, .!$6, &3-#?.!$6 &3-#?!;= &3-#?.7% TD#,+, !$6 &3-#?!$;= $ATALATENCY TD#,+, .%X, TD#,+, .!$6( TD#,+, !6 TD#,+, .7%, TD#,+, !$)6 TD#,+, $ATA !$;= TD#,+, $ATA $ "53452. TD#,+, .%X( TD#,+, !)6 TD#,+, .7%( $ &3-#?.7!)4 7!)4#&'B 7!)40/, B &3-#?.", TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( AIF 90/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 42. Synchronous multiplexed PSRAM write timings(1) Symbol Parameter Min Max Unit tw(CLK) td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-ADIV) td(CLKL-DATA) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKL-NBLH) 1. CL = 30 pF. FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x = 0...2) FSMC_CLK low to FSMC_NEx high (x = 0...2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 16...25) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) FSMC_CLK low to FSMC_NWE low FSMC_CLK low to FSMC_NWE high FSMC_CLK low to FSMC_AD[15:0] invalid FSMC_A/D[15:0] valid after FSMC_CLK low FSMC_NWAIT valid before FSMC_CLK high FSMC_NWAIT valid after FSMC_CLK high FSMC_CLK low to FSMC_NBL high 2*THCLK - - ns 0 ns 0 - ns - 0 ns 0 - ns - 0 ns THCLK + 4 - ns - 0 ns 1 - ns 5 - ns - 6 ns TBD - ns TBD - ns 1 - ns Doc ID 022027 Rev 5 91/141 Electrical characteristics STM32L151xD STM32L152xD Figure 23. Synchronous non-multiplexed NOR/PSRAM read timings TW#,+ TW#,+ "53452. &3-#?#,+ TD#,+, .%X, &3-#?.%X $ATALATENCY TD#,+, .%X( TD#,+, .!$6, &3-#?.!$6 TD#,+, .!$6( &3-#?!;= TD#,+, !6 TD#,+, !)6 &3-#?./% &3-#?$;= TD#,+, ./%, TD#,+, ./%( TSU$6 #,+( TH#,+( $6 TSU$6 #,+( $ $ TH#,+( $6 TSU.7!)46 #,+( TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B 7!)40/, B &3-#?.7!)4 7!)4#&'B 7!)40/, B TSU.7!)46 #,+( T H#,+( .7!)46 TSU.7!)46 #,+( TH#,+( .7!)46 AIF Table 43. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2*THCLK 0.5 td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 0 3.5 0 2.5 4 4 TBD TBD 1. CL = 30 pF. - ns 0 ns - ns 3 ns - ns 0 ns - ns THCLK + 1 ns - ns - ns - ns - ns - ns 92/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Figure 24. Synchronous non-multiplexed PSRAM write timings TW#,+ &3-#?#,+ TW#,+ "53452. TD#,+, .%X, &3-#?.%X $ATALATENCY TD#,+, .%X( TD#,+, .!$6, &3-#?.!$6 TD#,+, .!$6( &3-#?!;= &3-#?.7% TD#,+, !6 TD#,+, .7%, TD#,+, !)6 TD#,+, .7%( &3-#?$;= TD#,+, $ATA TD#,+, $ATA $ $ &3-#?.7!)4 7!)4#&'B 7!)40/, B &3-#?.", TSU.7!)46 #,+( TD#,+, .",( TH#,+( .7!)46 AIG Table 44. Synchronous non-multiplexed PSRAM write timings(1) Symbol Parameter Min Max Unit tw(CLK) td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-DATA) td(CLKL-NBLH) tsu(NWAITV-CLKH) th(CLKH-NWAITV) 1. CL = 30 pF. FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x = 0...2) FSMC_CLK low to FSMC_NEx high (x = 0...2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 16...25) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) FSMC_CLK low to FSMC_NWE low FSMC_CLK low to FSMC_NWE high FSMC_D[15:0] valid data after FSMC_CLK low FSMC_CLK low to FSMC_NBL high FSMC_NWAIT valid before FSMC_CLK high FSMC_NWAIT valid after FSMC_CLK high 2*THCLK -3 - ns - 0 ns 1 - ns - 5 ns 7 - ns - 0 ns THCLK + 4 - ns - 2 ns 5 - ns - 7 ns 3 - ns TBD - ns TBD - ns Doc ID 022027 Rev 5 93/141 Electrical characteristics STM32L151xD STM32L152xD 6.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: ● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. ● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 45. They are based on the EMS levels and classes defined in application note AN1709. Table 45. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD 3.3 V, LQFP100, TA +25 °C, fHCLK 32 MHz conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.3 V, LQFP100, TA +25 °C, fHCLK 32 MHz 4A conforms to IEC 61000-4-4 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: ● Corrupted program counter ● Unexpected reset ● Critical data corruption (control registers...) 94/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 46. EMI characteristics Max vs. frequency range Symbol Parameter Conditions Monitored frequency band 4 MHz 16 MHz 32 MHz voltage voltage voltage Unit range 3 range 2 range 1 VDD 3.3 V, 0.1 to 30 MHz 3 -6 -5 TA 25 °C, 30 to 130 MHz 18 4 -7 dBµV SEMI Peak level LQFP100 package compliant with IEC 130 MHz to 1GHz 15 5 -7 61967-2 SAE EMI Level 2.5 2 1 - 6.3.11 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 47. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage (human body model) TA +25 °C, conforming to JESD22-A114 2 VESD(CDM) Electrostatic discharge voltage (charge device model) TA +25 °C, conforming to JESD22-C101 II 2000 V 500 1. Based on characterization results, not tested in production. Doc ID 022027 Rev 5 95/141 Electrical characteristics STM32L151xD STM32L152xD Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 48. Electrical sensitivities Symbol Parameter Conditions LU Static latch-up class TA +105 °C conforming to JESD78A Class II level A 6.3.12 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, LCD levels, etc.). The test results are given in the following table. Table 49. I/O current injection susceptibility Symbol Description Functional susceptibility Negative Positive Unit injection injection Injected current on true open-drain pins -5 +0 IINJ Injected current on all 5 V tolerant (FT) pins -5 Injected current on any other pin -5 +0 mA +5 96/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.13 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 50. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage Standard I/O input high level voltage VIH FT(2) I/O input high level voltage TTL ports 2.7 V  VDD 3.6 V VSS - 0.3 2(1) - 0.8 - VDD+0.3 - 5.5V VIL Input low level voltage CMOS ports 1.65 V  VDD 3.6 V –0.3 - 0.3VDD(3) Standard I/O Input high level voltage CMOS ports 1.65 V  VDD 3.6 V - VDD+0.3 V VIH FT(5) I/O input high level voltage CMOS ports 1.65 V  VDD 2.0 V 0.7 VDD(3)(4) - CMOS ports 2.0 V VDD 3.6 V - 5.25 5.5 Vhys Standard I/O Schmitt trigger voltage hysteresis(6) 10% VDD(7) - - VSS  VIN  VDD I/Os with LCD - - ±50 VSS  VIN  VDD I/Os with analog - switches - ±50 Ilkg Input leakage current (8)(3) VSS  VIN  VDD I/Os with analog - switches and LCD VSS  VIN  VDD I/Os with USB - - ±50 nA - TBD VSS  VIN  VDD Standard I/Os - - ±50 RPU Weak pull-up equivalent resistor(9)(3) RPD Weak pull-down equivalent resistor(9)(3) VIN VSS VIN VDD 30 45 60 k 30 45 60 k CIO I/O pin capacitance - 5 - pF 1. Guaranteed by design. 2. FT = 5V tolerant. To sustain a voltage higher than VDD +0.5 the internal pull-up/pull-down resistors must be disabled. 3. Tested in production 4. 0.7VDD for 5V-tolerant receiver 5. FT = Five-volt tolerant. 6. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 7. With a minimum of 200 mV. Based on characterization, not tested in production. Doc ID 022027 Rev 5 97/141 Electrical characteristics STM32L151xD STM32L152xD 8. The max. value may be exceeded if negative current is injected on adjacent pins. 9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA with the non-standard VOL/VOH specifications given in Table 51. in the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: ● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). ● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 51. Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL(1)(2) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +8 mA - 0.4 VOH(3)(2) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.7 V < VDD < 3.6 V 2.4 - VOL (1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time IIO =+ 4 mA - 0.45 1.65 V < VDD < V 2.7 V VDD-0.45 - VOL(1)(4) Output low level voltage for an I/O pin when 4 pins are sunk at same time IIO = +20 mA - 1.3 VOH(3)(4) Output high level voltage for an I/O pin when 4 pins are sourced at same time 2.7 V < VDD < 3.6 V VDD-1.3 - 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. Tested in production. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. 98/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 25 and Table 52, respectively. Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 52. I/O AC characteristics(1) OSPEEDRx [1:0] bit value(1) Symbol Parameter Conditions Min Max(2) Unit fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 1.65 V to 2.7 V - 400 kHz - 400 00 tf(IO)out tr(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V Output rise and fall time CL = 50 pF, VDD = 1.65 V to 2.7 V - 625 ns - 625 fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 2 MHz CL = 50 pF, VDD = 1.65 V to 2.7 V - 1 01 tf(IO)out tr(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V Output rise and fall time CL = 50 pF, VDD = 1.65 V to 2.7 V - 125 ns - 250 Fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 10 MHz CL = 50 pF, VDD = 1.65 V to 2.7 V - 2 10 tf(IO)out tr(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V Output rise and fall time CL = 50 pF, VDD = 1.65 V to 2.7 V - 25 ns - 125 Fmax(IO)out Maximum frequency(3) CL = 30 pF, VDD = 2.7 V to 3.6 V - 50 MHz CL = 50 pF, VDD = 1.65 V to 2.7 V - 8 11 tf(IO)out tr(IO)out CL = 30 pF, VDD = 2.7 V to 3.6 V Output rise and fall time CL = 50 pF, VDD = 1.65 V to 2.7 V - 5 - 30 Pulse width of external ns - tEXTIpw signals detected by the EXTI controller 8 - 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. Not tested in production. 3. The maximum frequency is defined in Figure 25. Doc ID 022027 Rev 5 99/141 Electrical characteristics STM32L151xD STM32L152xD 6.3.14 Figure 25. I/O AC characteristics definition External Output on 50pF 90% 50% 10% tr(I O)out 10% 50% 90% tr(I O)out T Maximum frequency is achieved if (tr + tf)  2/3)T and if the duty cycle is (45-55%) when loaded by 50 pF ai14131 NRST pin characteristics The NRST pin input driver uses CMOS technology. Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 53. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST)(1) NRST input low level voltage VIH(NRST)(1) NRST input high level voltage VSS - 0.8 1.4 - VDD VOL(NRST)(1) NRST output low level voltage IOL = 2 mA 2.7 V < VDD < 3.6 V - IOL = 1.5 mA 1.65 V < VDD < 2.7 V - - V 0.4 - Vhys(NRST)(1) NRST Schmitt trigger voltage hysteresis 10%VDD(2) - - mV RPU Weak pull-up equivalent resistor(3) VIN VSS 30 45 60 k VF(NRST)(1) NRST input filtered pulse VNF(NRST)(1) NRST input not filtered pulse - - 50 ns 350 - - ns 1. Guaranteed by design, not tested in production. 2. 200 mV minimum value 3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%. 100/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.15 Figure 26. Recommended NRST pin protection %XTERNAL RESETCIRCUIT 6$$ .234 205 —& )NTERNALRESET &ILTER 34-,XXX AI 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 53. Otherwise the reset will not be taken into account by the device. TIM timer characteristics The parameters given in the following table are guaranteed by design. Refer to Section 6.3.12: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 54. TIMx(1) characteristics Symbol Parameter Conditions Min Max Unit tres(TIM) fEXT ResTIM Timer resolution time fTIMxCLK = 32 MHz Timer external clock frequency on CH1 to CH4 fTIMxCLK = 32 MHz Timer resolution 1 31.25 0 0 fTIMxCLK/2 16 16 tCOUNTER 16-bit counter clock period when internal clock is selected (timer’s prescaler disabled) fTIMxCLK = 32 MHz 1 0.0312 65536 2048 - tMAX_COUNT Maximum possible count fTIMxCLK = 32 MHz - 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. 65536 × 65536 134.2 tTIMxCLK ns MHz MHz bit tTIMxCLK µs tTIMxCLK s Doc ID 022027 Rev 5 101/141 Electrical characteristics STM32L151xD STM32L152xD 6.3.16 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 14. The STM32L151xD and STM32L152xD product line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 55. Refer also to Section 6.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 55. I2C characteristics Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Min Max Min Max Unit tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time 4.7 - 4.0 - 250 - 0 - 1.3 - µs 0.6 - 100 - 0 900(3) - 1000 20 + 0.1Cb 300 ns - 300 - 300 4.0 - 0.6 - µs 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - s Cb Capacitive load for each bus line - 400 - 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal. 102/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Figure 27. I2C bus AC waveforms and measurement circuit 6$$ 6$$ )#BUS   K   K 34-,XXX  3$!  3#, 3$ ! TF3$! 3 4!24 3 4!242%0%!4%$ TSU34! 3 4!24 TR3$! TSU3$! TH34! TW3#+, TH3$! 3 4/0 TSU34!34/ 3#, TW3#+( TR3#+ TF3#+ TSU34/ AI 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 56. SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V)(1)(2) fSCL (kHz) I2C_CCR value RP = 4.7 k 400 0x801B 300 0x8024 200 0x8035 100 0x00A0 50 0x0140 20 0x0320 1. RP = External pull-up resistance, fSCL = I2C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external components used to design the application. Doc ID 022027 Rev 5 103/141 Electrical characteristics STM32L151xD STM32L152xD SPI characteristics Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14. Refer to Section 6.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 57. SPI characteristics(1) Symbol Parameter Conditions Min Max(2) Unit fSCK 1/tc(SCK) SPI clock frequency Master mode Slave mode Slave transmitter - 16 - 16 MHz - 12(3) tr(SCK)(2) tf(SCK)(2) DuCy(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF SPI slave input clock duty cycle Slave mode - 6 ns 30 70 % tsu(NSS) th(NSS) tw(SCKH)(2) tw(SCKL)(2) tsu(MI)(2) tsu(SI)(2) th(MI)(2) th(SI)(2) ta(SO)(4) tv(SO) (2) tv(MO)(2) th(SO)(2) th(MO)(2) NSS setup time NSS hold time SCK high and low time Data input setup time Data input hold time Data output access time Data output valid time Data output valid time Data output hold time Slave mode Slave mode Master mode Master mode Slave mode Master mode Slave mode Slave mode Slave mode Master mode Slave mode Master mode 4tHCLK - 2tHCLK - tSCK/25 tSCK/2+3 5 - 6 - 5 - ns 5 - 0 3tHCLK - 33 - 6.5 17 - 0.5 - 1. The characteristics above are given for voltage range 1. 2. Based on characterization, not tested in production. 3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK)) ranging between 40 to 60%. 4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 104/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Figure 28. SPI timing diagram - slave mode and CPHA = 0 SCK Input NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tSU(NSS) tc(SCK) tw(SCKH) tw(SCKL) ta(SO) MISO OUT P UT MOSI I NPUT tsu(SI) tv(SO) MS B O UT M SB IN th(SI) th(SO) BI T6 OUT B I T1 IN Figure 29. SPI timing diagram - slave mode and CPHA = 1(1) Electrical characteristics th(NSS) tr(SCK) tf(SCK) tdis(SO) LSB OUT LSB IN ai14134c SCK Input NSS input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) MISO OUT P UT MOSI I NPUT ta(SO) tsu(SI) tc(SCK) tv(SO) MS B O UT th(SI) M SB IN th(SO) BI T6 OUT B I T1 IN 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. th(NSS) tr(SCK) tf(SCK) tdis(SO) LSB OUT LSB IN ai14135 Doc ID 022027 Rev 5 105/141 Electrical characteristics Figure 30. SPI timing diagram - master mode(1) High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tc(SCK) STM32L151xD STM32L152xD SCK Input SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO INP UT tsu(MI) MOSI OUTPU T tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) BI T6 IN B I T1 OUT th(MO) 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. tr(SCK) tf(SCK) LSB IN LSB OUT ai14136 106/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.17 Note: I2S characteristics Table 58. I2S characteristics Symbol Parameter Conditions Min Max Unit fMCK I2S Main Clock Output fCK I2S clock frequency Master data: 32 bits Slave data: 32 bits 256 x 8K 256xFs (1) MHz - 64xFs MHz - 64xFs DCK I2S clock frequency duty cycle Slave receiver, 48KHz 30 tr(CK) tf(CK) I2S clock rise time I2S clock fall time Capacitive load CL=30pF - tv(WS) WS valid time Master mode 4 th(WS) WS hold time Master mode 0 tsu(WS) WS setup time Slave mode 15 th(WS) WS hold time Slave mode 0 tsu(SD_MR) Data input setup time Master receiver 8 tsu(SD_SR) Data input setup time Slave receiver 9 th(SD_MR) Master receiver 5 Data input hold time th(SD_SR) Slave receiver 4 tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 70 % 8 8 24 - - - - - - ns - 64 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 22 - tv(SD_MT) Data output valid time Master transmitter (after enable edge) - 12 th(SD_MT) Data output hold time Master transmitter (after enable edge) 8 - 1. The maximum for 256xFs is 8 MHz Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral behavior, source clock precision might slightly change them. DCK depends mainly on the ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of (I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition. Doc ID 022027 Rev 5 107/141 Electrical characteristics STM32L151xD STM32L152xD Figure 31. I2S slave timing diagram (Philips protocol)(1) tc(CK) CPOL = 0 CK Input CPOL = 1 WS input SDtransmit SDreceive tw(CKH) tw(CKL) th(WS) tsu(WS) LSB transmit(2) tsu(SD_SR) LSB receive(2) MSB transmit MSB receive tv(SD_ST) Bitn transmit th(SD_SR) Bitn receive th(SD_ST) LSB transmit LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 32. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output CPOL = 0 CPOL = 1 WS output SDtransmit SDreceive tc(CK) tw(CKH) tv(WS) tw(CKL) th(WS) tv(SD_MT) LSB transmit(2) MSB transmit Bitn transmit tsu(SD_MR) LSB receive(2) MSB receive th(SD_MR) Bitn receive th(SD_MT) LSB transmit LSB receive ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 108/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.18 SDIO characteristics Table 59. SDIO characteristics(1) Symbol Parameter Conditions Min Max fPP Clock frequency in data transfer mode CL 30 pF 0 24 tW(CKL) Clock low time, fPP = 24 MHz CL 30 pF 20(2) - tW(CKH) Clock high time, fPP = 24 MHz CL 30 pF 18(2) - tr Clock rise time, fPP = 24 MHz CL 30 pF - 5 tf Clock fall time, fPP = 24 MHz CL 30 pF - 5 CMD, D inputs (referenced to CK) in SD default mode From 2.8 to 3.6 V tISU Input setup time, fPP = 24 MHz tIH Input hold time, fPP = 24 MHz CL 30 pF 2 - CL 30 pF 1.6 - CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time, fPP = 24 MHz CL 30 pF 0 14 tOHD Output hold default time, fPP = 24 MHz CL 30 pF 0 - 1. Based on characterization, not tested in production. 2. Values measured with a threshold level equal to VDD/2. Figure 33. SDIO timings tf tr Unit MHz ns ns ns tW(CKH) CK D, CMD(output) D, CMD(input) tC tW(CKL) tOVD tOHD tISU tIH -36 Doc ID 022027 Rev 5 109/141 Electrical characteristics STM32L151xD STM32L152xD USB characteristics The USB interface is USB-IF certified (full speed). Table 60. USB startup time Symbol Parameter tSTARTUP(1) USB transceiver startup time 1. Guaranteed by design, not tested in production. Max Unit 1 µs Table 61. USB DC electrical characteristics Symbol Parameter Conditions Input levels VDD VDI(2) VCM(2) VSE(2) USB operating voltage Differential input sensitivity I(USB_DP, USB_DM) Differential common mode range Includes VDI range Single ended receiver threshold Output levels VOL(3) VOH(3) Static output level low Static output level high RL of 1.5 k to 3.6 V(4) RL of 15 k to VSS(4) 1. All the voltages are measured from the local ground potential. 2. Guaranteed by characterization, not tested in production. 3. Tested in production. 4. RL is the load connected on the USB drivers. Min.(1) Max.(1) Unit 3.0 3.6 V 0.2 - 0.8 2.5 V 1.3 2.0 - 0.3 V 2.8 3.6 Figure 34. USB timings: definition of data signal rise and fall time Differen tial Data L ines VCR S Crossover points VS S tf tr ai14137 Table 62. USB: full speed electrical characteristics Driver characteristics(1) Symbol Parameter Conditions Min tr Rise time(2) tf Fall Time(2) CL = 50 pF 4 CL = 50 pF 4 trfm Rise/ fall time matching tr/tf 90 VCRS Output signal crossover voltage 1.3 Max 20 20 110 2.0 Unit ns ns % V 110/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 6.3.19 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 64 are guaranteed by design. Table 63. ADC clock frequency Symbol Parameter Conditions Min fADC ADC clock frequency VREF+ = VDDA Voltage range 1 & 2 2.4 V  VDDA  3.6 V VREF+ VDDA VREF+ > 2.4 V VREF+ VDDA VREF+  2.4 V 0.480 1.8 V  VDDA  2.4 V VREF+ = VDDA VREF+ VDDA Voltage range 3 Max 16 8 4 8 4 4 Unit MHz Table 64. ADC characteristics Symbol Parameter Conditions Min Typ VDDA VREF+ VREFIVDDA Power supply Positive reference voltage Negative reference voltage Current on the VDDA input pin 1.8 - 2.4 V  VDDA  3.6 V VREF+ must be below or equal to VDDA 1.8(1) - VSSA - 1000 IVREF(2) Current on the VREF input pin Peak Average 400 - VAIN Conversion voltage range(3) 0(4) - 12-bit sampling rate Direct channels 0.03 - Multiplexed channels 0.03 - 10-bit sampling rate fS 8-bit sampling rate Direct channels 0.03 - Multiplexed channels 0.03 - Direct channels 0.03 - Multiplexed channels 0.03 - 6-bit sampling rate Direct channels 0.03 - Multiplexed channels 0.03 - Max 3.6 VDDA - 1450 700 450 VREF+ 1 0.76 1.07 0.8 1.23 0.89 1.54 1 Unit V µA V Msps Msps Msps Msps Doc ID 022027 Rev 5 111/141 Electrical characteristics STM32L151xD STM32L152xD Table 64. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit tS Sampling time tCONV Total conversion time (including sampling time) Direct channels 2.4 V  VDDA  3.6 V 0.25(5) - - Multiplexed channels 2.4 V  VDDA  3.6 V 0.56(5) - - Direct channels 1.8 V  VDDA  2.4 V 0.56(5) - - Multiplexed channels 1.8 V  VDDA  2.4 V 1(5) - - 4 - 384 fADC = 16 MHz 1 - 24.75 4 to 384 (sampling phase) +12 (successive approximation) µs 1/fADC µs 1/fADC CADC Internal sample and hold capacitor Direct channels - Multiplexed channels - 16 - pF fTRIG External trigger frequency Regular sequencer 12-bit conversions 6/8/10-bit conversions - fTRIG External trigger frequency Injected sequencer 12-bit conversions 6/8/10-bit conversions - RAIN(6) External input impedance - - Tconv+1 1/fADC - Tconv 1/fADC - Tconv+2 1/fADC - Tconv+1 1/fADC - 50 k - 0.5 tlat Injection trigger conversion latency fADC = 16 MHz 219 - 3.5 - 281 ns 4.5 1/fADC tlatr Regular trigger conversion latency fADC = 16 MHz 156 - 2.5 - 219 ns 3.5 1/fADC tSTAB Power-up time - - 3.5 µs 1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage reference). 2. The current consumption through VREF is composed of two parameters: - one constant (max 300 µA) - one variable (max 400 µA), only during sampling time + 2 first conversion pulses So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at 1Msps 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pin descriptions for further details. 4. VSSA or VREF- must be tied to ground. 5. Minimum sampling and conversion time is reached for maximum Rext = 0.5 k 6. For 1 Msps, maximum Rext is 0.5 k. 112/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Table 65. Symbol ADC accuracy(1)(2) Parameter Test conditions Min(3) Typ Max(3) Unit ET Total unadjusted error - 2 4 EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 2.4 V  VDDA  3.6 V 2.4 V  VREF+  3.6 V fADC = 8 MHz, RAIN = 50  TA = -40 to 105 C - 1 2 - 1.5 3.5 LSB - 1 2 - 1.7 3 ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion ET Total unadjusted error 2.4 V  VDDA  3.6 V VDDA = VREF+ fADC = 16 MHz, RAIN = 50  TA = -40 to 105 C 1 kHz  Finput  100 kHz 9.2 10 - bits 57.5 62 - 57.5 62 - dB -74 -75 - - 4 6.5 EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ET Total unadjusted error 2.4 V  VDDA  3.6 V 1.8 V  VREF+  2.4 V fADC = 4 MHz, RAIN = 50  TA = -40 to 105 C - 2 4 - 4 6 LSB - 1 2 - 1.5 3 - 2 3 EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1.8 V  VDDA  2.4 V 1.8 V  VREF+  2.4 V fADC = 4 MHz, RAIN = 50  TA = -40 to 105 C - 1 1.5 - 1.5 2 LSB - 1 2 - 1 1.5 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.12 does not affect the ADC accuracy. 3. Based on characterization, not tested in production. Doc ID 022027 Rev 5 113/141 Electrical characteristics STM32L151xD STM32L152xD Figure 35. ADC accuracy characteristics 4095 4094 4093 7 6 5 4 3 2 1 [1LSBIDEAL =VREF+ 4096 (or VDDA depending 4096 on package)] EG (2) ET (3) (1) EO EL ED 1 LSBIDEAL (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 0 1234567 VSSA 4093 4094 4095 4096 VDDA ai14395b Figure 36. Typical connection diagram using the ADC 2!). !).X 6!). #PARASITIC 6$$ 64 6 64 6 34-,XXX 3AMPLEANDHOLD!$# CONVERTER 2!$# ),›N!  BIT CONVERTER #!$# AIB 1. Refer to Table 64 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 114/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Figure 37. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion Sampling (n cycles) ADC clock Iref+ 700µA 300µA Conversion (12 cycles) Table 66. Ts (cycles) RAIN max for fADC = 16 MHz(1) RAIN max (k) Ts (µs) Multiplexed channels Direct channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 0.7 Not allowed 9 0.5625 0.8 Not allowed 2.0 1.0 16 1 2.0 0.8 4.0 3.0 24 1.5 3.0 1.8 6.0 4.5 48 3 6.8 4.0 15.0 10.0 96 6 15.0 10.0 30.0 20.0 192 12 32.0 25.0 50.0 40.0 384 24 50.0 50.0 50.0 50.0 1. Guaranteed by design, not tested in production. Doc ID 022027 Rev 5 115/141 Electrical characteristics STM32L151xD STM32L152xD General PCB design guidelines Power supply decoupling should be performed as shown in Figure 38 or Figure 39, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 38. Power supply and reference decoupling (VREF+ not connected to VDDA) 34-,XXX 62%& SEENOTE —&N& —&N& 6$$! 633! 62%&n SEENOTE AIB 1. VREF+ and VREF– inputs are available only on 100-pin packages. Figure 39. Power supply and reference decoupling (VREF+ connected to VDDA) 34-,XXX 62%& 6$$! 3EENOTE —&N& 62%&n633! 3EENOTE AIA 1. VREF+ and VREF– inputs are available only on 100-pin packages. 116/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.20 DAC electrical specifications Data guaranteed by design, not tested in production, unless otherwise specified. Table 67. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage 1.8 - 3.6 VREF+ Reference supply voltage VREF+ must always be below VDDA 1.8 - 3.6 V VREF- Lower reference voltage VSSA Current consumption on No load, middle code (0x800) - 130 IDDVREF+(1) VREF+ supply VREF+ = 3.3 V No load, worst code (0x000) - 220 Current consumption on No load, middle code (0x800) - 210 IDDA(1) VDDA supply VDDA = 3.3 V No load, worst code (0xF1C) - 320 RL(2) CL(2) Resistive load Capacitive load DAC output buffer ON 5 - - - 220 350 µA 320 520 - k 50 pF RO Output impedance DAC output buffer OFF 6 8 10 k VDAC_OUT Voltage on DAC_OUT output DAC output buffer ON DAC output buffer OFF 0.2 - VDDA – 0.2 V 0.5 - VREF+ – 1LSB mV DNL(1) INL(1) Offset(1) Offset1(1) CL  50 pF, RL  5 k DAC output buffer ON Differential non linearity(3) No RLOAD, CL  50 pF DAC output buffer OFF Integral non linearity(4) CL  50 pF, RL  5 k DAC output buffer ON No RLOAD, CL  50 pF DAC output buffer OFF Offset error at code 0x800 (5) CL  50 pF, RL  5 k DAC output buffer ON No RLOAD, CL  50 pF DAC output buffer OFF Offset error at code 0x001(6) No RLOAD, CL  50 pF DAC output buffer OFF - 1.5 - 1.5 - 2 - 2 - ±10 - ±5 - ±1.5 3 3 4 4 LSB ±25 ±8 ±5 Doc ID 022027 Rev 5 117/141 Electrical characteristics STM32L151xD STM32L152xD Table 67. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit dOffset/dT(1) Offset error temperature coefficient (code 0x800) VDDA 3.3V VREF+ 3.0V TA = 0 to 50 C DAC output buffer OFF VDDA 3.3V VREF+ 3.0V TA = 0 to 50 C DAC output buffer ON Gain(1) Gain error(7) CL  50 pF, RL  5 k DAC output buffer ON No RLOAD, CL  50 pF DAC output buffer OFF dGain/dT(1) Gain error temperature coefficient VDDA 3.3V VREF+ 3.0V TA = 0 to 50 C DAC output buffer OFF VDDA 3.3V VREF+ 3.0V TA = 0 to 50 C DAC output buffer ON TUE(1) Total unadjusted error CL  50 pF, RL  5 k DAC output buffer ON No RLOAD, CL  50 pF DAC output buffer OFF tSETTLING Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes till CL  50 pF, RL  5 k DAC_OUT reaches final value ±1LSB -20 -10 0 20 0 µV/°C 50 - +0.1 / -0.2% +0.2 / -0.5% % - +0 / -0.2% +0 / -0.4% -10 -2 -40 -8 0 µV/°C 0 - 12 - 8 30 LSB 12 - 7 12 µs Update rate Max frequency for a correct DAC_OUT change (95% of final value) with 1 CL  50 pF, RL  5 k LSB variation in the input code tWAKEUP Wakeup time from off state (setting the ENx bit in the DAC Control register)(8) CL  50 pF, RL  5 k - 1 Msps - 9 15 µs PSRR+ VDDA supply rejection ratio (static DC measurement) CL  50 pF, RL  5 k - -60 -35 dB 1. Data based on characterization results. 2. Connected between DAC_OUT and VSSA. 3. Difference between two consecutive codes - 1 LSB. 4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2. 118/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6. Difference between the value measured at Code (0x001) and the ideal value. 7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON. 8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). Figure 40. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) 12-bit digital to analog converter DAC_OUTx R LOAD C LOAD ai17157V2 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.21 Operational amplifier characteristics Table 68. Operational amplifier characteristics Symbol Parameter Condition(1) CMIR Common mode input range VIOFFSET Maximum calibration range Input offset voltage After offset calibration VIOFFSET Input offset voltage drift Normal mode Low power mode Dedicated input IIB Input current bias General purpose input ILOAD Drive current Normal mode Low power mode Normal mode IDD Consumption Low power mode 75 °C No load, quiescent mode CMRR PSRR Common mode rejection ration Power supply rejection ratio Normal mode Low power mode Normal mode DC Low power mode Min(2) 0 - - - - - Typ Max(2) Unit - VDD - 15 mV - 1.5 - 40 µV/°C - 80 - 1 nA - 10 - 500 µA - 100 100 220 µA 30 60 -85 - dB -90 - -85 - dB -90 - Doc ID 022027 Rev 5 119/141 Electrical characteristics STM32L151xD STM32L152xD Table 68. Operational amplifier characteristics (continued) Symbol Parameter Condition(1) Min(2) Typ Max(2) Unit GBW Bandwidth Normal mode Low power mode Normal mode Low power mode VDD>2.4 V VDD<2.4 V 400 1000 3000 150 300 800 kHZ 200 500 2200 70 150 800 SR Slew rate Normal mode Low power mode Normal mode Low power mode VDD>2.4 V (between 0.1 V and VDD-0.1 V) VDD>2.4 V VDD<2.4 V - 700 - - 100 - V/ms - 300 - - 50 - Normal mode AO Open loop gain Low power mode 55 100 - dB 65 110 - RLOAD Resistive load Normal mode Low power mode VDD<2.4 V 4 - 20 - k - CLOAD VOHSAT Capacitive load High saturation voltage VOLSAT Low saturation voltage Normal mode Low power mode Normal mode low power mode ILOAD = max or RLOAD = min - - VDD100 - VDD-50 - - - - - 50 pF - - mV 100 50 m Phase margin - 60 - ° GM Gain margin - -12 - dB tOFFTRIM Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy - 1 - ms tWAKEUP Wakeup time Normal mode Low power mode CLOAD  50 pf, RLOAD  4 k CLOAD  50 pf, RLOAD  20 k - 10 - µs - 30 - 1. Operating conditions are limited to junction temperature (0 °C to 105 °C) when VDD is below 2 V. Otherwise, the operating temperature range is 105 °C to -40 °C. 2. Data based on characterization results, not tested in production. 120/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.22 6.3.23 Temperature sensor characteristics Table 69. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit TL(1) Avg_Slope(1) V110 IDDA(TEMP)(3) tSTART(3) TS_temp(4)(3) VSENSE linearity with temperature Average slope Voltage at 110°C ±5°C(2) Current consumption Startup time ADC sampling time when reading the temperature 1.48 612 - 10 1 1.61 626.8 3.4 - - 2 1.75 641.5 6 10 - °C mV/°C mV µA µs 1. Guaranteed by characterization, not tested in production. 2. Measured at VDD = 3 V ±10 mV. V110 ADC conversion result is stored in the TSENSE_CAL2 byte. 3. Guaranteed by design, not tested in production. 4. Shortest sampling time can be determined in the application by multiple iterations. Comparator Table 70. Comparator 1 characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit VDDA R400K R10K VIN Analog supply voltage R400K value R10K value Comparator 1 input voltage range 1.65 3.6 V - 400 - k - 10 - 0.6 - VDDA V tSTART td Comparator startup time Propagation delay(2) - 7 10 µs - 3 10 Voffset Comparator offset - 3 10 mV dVoffset/dt Comparator offset variation in worst voltage stress conditions VDDA 3.6 V VIN+ 0 V VIN- VREFINT TA = 25 C 0 1.5 ICOMP1 Current consumption(3) - 160 10 mV/1000 h 260 nA 1. Based on characterization, not tested in production. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. Doc ID 022027 Rev 5 121/141 Electrical characteristics STM32L151xD STM32L152xD Table 71. Comparator 2 characteristics Symbol Parameter Conditions Min Typ Max(1) Unit VDDA VIN tSTART Analog supply voltage Comparator 2 input voltage range Comparator startup time Fast mode Slow mode 1.65 0- 15 - 20 td slow Propagation delay(2) in slow mode 1.65 V  VDDA  2.7 V - 1.8 2.7 V  VDDA  3.6 V - 2.5 td fast Propagation delay(2) in fast mode 1.65 V  VDDA  2.7 V - 0.8 2.7 V  VDDA  3.6 V - 1.2 Voffset Comparator offset error - 4 VDDA 3.3V dThreshold/ Threshold voltage temperature dt coefficient TA = 0 to 50 C V- = VREF+, 3/4 VREF+, - 15 1/2 VREF+, 1/4 VREF+. ICOMP2 Current consumption(3) Fast mode Slow mode - 3.5 - 0.5 3.6 V VDDA V 20 25 3.5 µs 6 2 4 20 mV 30 ppm /°C 5 µA 2 1. Based on characterization, not tested in production. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included. 122/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6.3.24 LCD controller (STM32L152xD only) The STM32L152xD embeds a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 72. LCD controller characteristics Symbol Parameter Min Typ Max Unit VLCD LCD external voltage - - 3.6 VLCD0 LCD internal reference voltage 0 - 2.6 - VLCD1 LCD internal reference voltage 1 - 2.73 - VLCD2 LCD internal reference voltage 2 - 2.86 - VLCD3 LCD internal reference voltage 3 - 2.98 - V VLCD4 LCD internal reference voltage 4 - 3.12 - VLCD5 LCD internal reference voltage 5 - 3.26 - VLCD6 LCD internal reference voltage 6 - 3.4 - VLCD7 LCD internal reference voltage 7 - 3.55 - Cext VLCD external capacitance 0.1 2 µF ILCD(1) RHtot(2) RL(2) Supply current at VDD = 2.2 V Supply current at VDD = 3.0 V Low drive resistive network overall value High drive resistive network total value - 3.3 - 3.1 5.28 6.6 192 240 µA - 7.92 M 288 k V44 Segment/Common highest level voltage - - VLCD V V34 Segment/Common 3/4 level voltage - 3/4 VLCD - V23 Segment/Common 2/3 level voltage - 2/3 VLCD - V12 Segment/Common 1/2 level voltage V13 Segment/Common 1/3 level voltage - 1/2 VLCD - V - 1/3 VLCD - V14 Segment/Common 1/4 level voltage - 1/4 VLCD - V0 Segment/Common lowest level voltage 0 - - Vxx(3) Segment/Common level voltage error TA = -40 to 85 C - - 50 mV 1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected. 2. Guaranteed by design, not tested in production. 3. Based on characterization, not tested in production. Doc ID 022027 Rev 5 123/141 Package characteristics 7 Package characteristics STM32L151xD STM32L152xD 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 124/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Package characteristics Figure 41. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline Seating plane C A A2 A1 b ccc C D D1 D3 108 109 c 73 72 0.25 mm gage plane k A1 L L1 144 Pin 1 1 identification 1. Drawing is not to scale. E1 E E3 37 36 e ME_1A Doc ID 022027 Rev 5 125/141 Package characteristics STM32L151xD STM32L152xD Table 73. Symbol LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data millimeters inches(1) Min Typ Max Min Typ Max A 1.60 0.063 A1 0.05 0.15 0.002 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 D 21.80 22.00 22.20 0.8583 0.8661 0.874 D1 19.80 20.00 20.20 0.7795 0.7874 0.7953 D3 17.50 0.689 E 21.80 22.00 22.20 0.8583 0.8661 0.874 E1 19.80 20.00 20.20 0.7795 0.7874 0.7953 E3 17.50 0.689 e 0.50 0.0197 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 k 0° 3.5° 7° ccc 0.08 0° 3.5° 7° 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 42. Recommended footprint 108 109 0.35 73 1.35 72 0.5 17.85 19.9 22.6 144 1 1. Dimensions are in millimeters. 19.9 22.6 37 36 ai14905c 126/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Package characteristics Figure 43. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline 75 76 D D1 D3 51 50 0.25 mm 0.10 inch GAGE PLANE k L L1 C b E3 E1 E 100 Pin 1 1 identification 1. Drawing is not to scale. 26 25 e SEATING PLANE C ccc C A1 A2 A 1L_ME Doc ID 022027 Rev 5 127/141 Package characteristics STM32L151xD STM32L152xD Table 74. Symbol LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data millimeters inches(1) Min Typ Max Min Typ Max A 1.6 0.063 A1 0.05 0.15 0.002 0.0059 A2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.2 0.0035 0.0079 D 15.8 16 16.2 0.622 0.6299 0.6378 D1 13.8 14 14.2 0.5433 0.5512 0.5591 D3 12 0.4724 E 15.8 16 16.2 0.622 0.6299 0.6378 E1 13.8 14 14.2 0.5433 0.5512 0.5591 E3 12 0.4724 e 0.5 0.0197 L 0.45 0.6 0.75 0.0177 0.0236 0.0295 L1 1 0.0394 k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc 0.08 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44. Recommended footprint 75 76 51 50 0.5 0.3 16.7 14.3 100 1 1. Dimensions are in millimeters. 26 1.2 25 12.3 16.7 ai14906 128/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Package characteristics Figure 45. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline A A2 A1 E E1 b e D1 c D L1 1. Drawing is not to scale. L ai14398b Table 75. Symbol LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data millimeters inches(1) Min Typ Max Min Typ Max A 1.60 A1 0.05 0.15 0.0020 A2 1.35 1.40 1.45 0.0531 b 0.17 0.22 0.27 0.0067 c 0.09 0.20 0.0035 D 12.00 D1 10.00 E 12.00 E1 10.00 e 0.50  0° 3.5° 7° 0° L 0.45 0.60 0.75 0.0177 L1 1.00 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 0.0551 0.0087 0.4724 0.3937 0.4724 0.3937 0.0197 3.5° 0.0236 0.0394 0.0630 0.0059 0.0571 0.0106 0.0079 7° 0.0295 Doc ID 022027 Rev 5 129/141 Package characteristics Figure 46. Recommended footprint 48 49 12.7 10.3 64 1 1. Dimensions are in millimeters. STM32L151xD STM32L152xD 33 0.3 0.5 32 10.3 16 7.8 12.7 17 1.2 ai14909 130/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Package characteristics Figure 47. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package outline A1 Ball Pad Corner Detail A 2 Side view Top view A1 Ball Pad Corner 1 Detail A rotated 90° Seating plane Bottom view 1. Primary datum C and seating plane are defined by the spherical crowns of the solder balls. 2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C. Table 76. UFBGA132 package mechanical data millimeters Symbol Min Typ Max Min A 0.46 0.53 0.60 0.0181 A1 0.05 0.08 0.11 0.0020 A2 0.40 0.45 0.50 0.0157 b 0.17 0.28 0.33 0.0067 1. Values in inches are converted from mm and rounded to 4 decimal digits. inches(1) Typ 0.0209 0.0032 0.0177 0.0110 A0G8_ME Max 0.0236 0.0043 0.0197 0.0130 Doc ID 022027 Rev 5 131/141 Package characteristics STM32L151xD STM32L152xD Figure 48. WLCSP64, 0.400 mm pitch wafer level chip size package outline $ !CORNER $ETAIL! % 7AFERBACKSIDE ! ! 3IDEVIEW "UMP EEE B $ETAIL! ROTATED ! 3EATINGPLANE E & '   ! E ( E "UMPSIDE E ' & 1. Drawing is not to scale. !*6?-% 132/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Package characteristics Table 77. Symbol WLCSP64, 0.400 mm pitch wafer level chip size package mechanical data millimeters inches(1) Min Typ Max Min Typ Max A 0.520 0.570 0.620 0.0205 0.0224 0.0244 A1 0.170 0.190 0.210 0.0067 0.0075 0.0083 A2 0.350 0.380 0.410 0.0138 0.0150 0.0161 b 0.240 0.270 0.300 0.0094 0.0106 0.0118 D 4.519 4.539 4.559 0.1779 0.1787 0.1795 E 4.891 4.911 4.931 0.1926 0.1933 0.1941 e 0.400 0.0157 e1 2.800 0.1102 F 0.870 0.0343 G 1.056 0.0416 eee 0.050 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 022027 Rev 5 133/141 Package characteristics STM32L151xD STM32L152xD 7.2 Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × JA) Where: ● TA max is the maximum ambient temperature in C, ● JA is the package junction-to-ambient thermal resistance, in C/W, ● PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), ● PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 78. Thermal characteristics Symbol Parameter Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch Thermal resistance junction-ambient BGA132 - 7 x 7 mm JA Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch Thermal resistance junction-ambient WLCSP64 - 0.400 mm pitch Value 40 60 43 46 46 Unit °C/W 134/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Figure 49. Thermal resistance 3000.00 Package characteristics 2500.00 2000.00 PD (mW) 1500.00 'PSCJEEFOBSFB 5+5+NBY 1000.00 ,1&0XMM 7,#30 5&"'!XMM ,1&0XXMM 500.00 7.2.1 0.00 100 75 50 25 0 Te mperature(°C) -36 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Doc ID 022027 Rev 5 135/141 Ordering information scheme 8 Ordering information scheme STM32L151xD STM32L152xD Table 79. STM32L15xxD ordering information scheme Example: STM32 L 151 R C Device family STM32 = ARM-based 32-bit microcontroller Product type L = Low power Device subfamily 151: Devices without LCD 152: Devices with LCD Pin count R = 64 pins V = 100 pins Z = 144 pins Q = 132 pins Flash memory size D = 384 Kbytes of Flash memory Package H = BGA T = LQFP Y = WLCSP64 Temperature range 6 = Industrial temperature range, –40 to 85 °C Options No character = VDD range: 1.8 to 3.6 V and BOR enabled D = VDD range: 1.65 to 3.6 V and BOR disabled Packing TR = tape and reel No character = tray or tube T 6 D xxx For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 136/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 9 Revision history Revision history Table 80. Document revision history Date Revision Changes 03-Oct-2011 1 Initial release. 03-Feb-2012 Status of the document changed (datasheet instead of preliminary data). Updated low power features on page 1. Removed references to devices with 256 KB of Flash memory. GPIOF replaced with GIOPH. Added SDIO in Table 2: Ultra-low-power STM32L15xxD device features and peripheral counts on page 11 and in Table 10: Alternate function input/output on page 43 (FSMC/SDIO instead of FSMC). Table 2: Ultra-low-power STM32L15xxD device features and peripheral counts: replaced STM32L15xWx with STM32L15xQx. Figure 1: Ultra-low-power STM32L15xxD block diagram: updated legend. Modified Section 3.4: Clock management on page 21. Table 4: STM32L15xQD BGA132 ballout: replaced STM32L15xWC/D with STM32L15xQD. Figure 5, Figure 5, Figure 6: updated titles. Table 9: STM32L15xxD pin definitions: updated title, updated pins PF0, PF1, PH2, PF12, PF13, PF14, PF15, PG0, PG1, PG12, PG15, 2 PD0, and PD1. Table 10: Alternate function input/output: Modified alternate function for PA13 and PA14; removed EVENT OUT for PH2. Figure 8: Memory map: removed the text “APB memory space”. Modified Figure 11: Power supply scheme on page 54. Modified Table 3: Functionalities depending on the operating power supply range on page 16. Table 18: Current consumption in Run mode, code with data processing running from RAM: added footnote 3. Table 19: Current consumption in Sleep mode: updated condition for fHSE; added footnote 3. Table 23: Typical and maximum current consumptions in Standby mode: modified max values. Table 61: USB DC electrical characteristics: removed two footnotes. Modified Table 35: Flash memory and data EEPROM characteristics on page 82. Table 78: Thermal characteristics: updated “TBDs” with values. Modified tables in Section 6.3.4: Supply current characteristics on page 60. Doc ID 022027 Rev 5 137/141 Revision history STM32L151xD STM32L152xD Table 80. Document revision history (continued) Date Revision Changes 18-Apr-2012 15-Jun-2012 Added WLCSP64 package. Section 3.1: Low power modes: changed ‘128 kHz’ to ‘131 kHz’ in section “Low power run mode”. Section 3.17.1: General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11): changed ‘six’ to ‘seven’ synchronizable general-purpose timers. 3 Table 9: STM32L15xxD pin definitions on page 37: updated name of reference manual in footnote 5. I2C updated: footnote 3. from Table 55 Note about I2C clock updated: footnote 2. from Table 55 modified. Note [non-robust] updated: footnote 2. from Table 65 modified. GPIOs high current capability updated: Section 3.6: GPIOs (generalpurpose inputs/outputs) ‘except for analog inputs’ was removed. Changed maximum number of touch sensing channels to 34, and updated Table 2: Ultra-low-power STM32L15xxD device features and peripheral counts. Updated Section 3.11: ADC (analog-to-digital converter) to add Section 3.11.1: Temperature sensor and Section 3.11.2: Internal voltage reference (VREFINT). Removed caution note below Figure 11: Power supply scheme. Added note below Table 4: STM32L15xQD BGA132 ballout. Modified Table 7: STM32L15xRD WLCSP64 ballout to match top view. Changed FSMC_LBAR into FSMC_NADV, and I2C1_SMBAI into I2C1_SMBA in Table 9: STM32L15xxD pin definitions. 4 Modified PB10/11/12 for AFIO4 alternate function, and replaced LBAR by NADV for AFIO12 in Table 10: Alternate function input/output. Updated Table 22: Typical and maximum current consumptions in Stop mode and added Note 6. Updated Table 23: Typical and maximum current consumptions in Standby mode. Updated tWUSTOP in Table 24: Typical and maximum timings in Low power modes. Updated Table 25: Peripheral current consumption. Updated Table 57: SPI characteristics, added Note 1 and Note 3, and applied Note 2 to tr(SCK), tf(SCK), tw(SCKH), tw(SCKL), tsu(MI), tsu(SI), th(MI), and th(SI). Updated IDD maximum value in Table 35: Flash memory and data EEPROM characteristics. 138/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Revision history Table 80. Document revision history (continued) Date Revision Changes 25-Oct-2012 Updated Features Updated Figure 1: Ultra-low-power STM32L15xxD block diagram Added Table 5: Functionalities depending on the working mode (from Run/active down to standby), and Table 9: CPU frequency range depending on dynamic voltage scaling Updated Figure 5: STM32L15xVD LQFP100 pinout Updated Table 9: STM32L15xxD pin definitions Added Note 2 in Table 15: Embedded reset and power control block characteristics 5 Replaced TBD values in Table 27: Low-speed external user clock characteristics, Table 35: Flash memory and data EEPROM characteristics and Table 52: I/O AC characteristics Added Table 58: I2S characteristics, Figure 31: I2S slave timing diagram (Philips protocol)(1) and Figure 32: I2S master timing diagram (Philips protocol)(1) Added Table 59: SDIO characteristics Added Figure 33: SDIO timings Updated Section 6.3.9: FSMC characteristics Updated Table 69: Temperature sensor characteristics Added Figure 49: Thermal resistance Doc ID 022027 Rev 5 139/141 STM32L151xD STM32L152xD Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 022027 Rev 5 141/141

Top_arrow
回到顶部
EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。