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MT6589 MT6589 HSPA+ Smartphone Application Processor Technical Brief

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    MT6589

    MT6589 HSPA+ Smartphone Application Processor Technical Brief

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    MT6589 HSPA+ Smartphone Application Processor Technical Brief http://www.DataSheet4U.net/ Version: Release date: 0.2 2012-09-26 © 2011 - 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Specifications are subject to change without notice. datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Document Revision History Revision 0.1 0.2 Date 2012-09-14 2012-09-26 Author YC Lai YC Lai Description First created by YC Lai Document revised. http://www.DataSheet4U.net/ MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 2 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Table of Contents Document Revision History .................................................................................................................. 2 Table of Contents ................................................................................................................................... 3 1 System Overview.......................................................................................................................... 6 1.1 Platform Features ................................................................................................................. 7 1.2 MODEM Features................................................................................................................. 8 1.3 Multimedia Features ............................................................................................................. 9 1.4 General Descriptions .......................................................................................................... 10 2 Product Description ................................................................................................................... 12 2.1 Pin Description.................................................................................................................... 12 2.1.1 Ball Map View..................................................................................................... 12 2.1.2 Pin Coordinate.................................................................................................... 13 2.1.3 Detailed Pin Description ..................................................................................... 17 2.2 Electrical Characteristic ...................................................................................................... 29 2.2.1 Absolute Maximum Ratings ............................................................................... 29 2.2.2 Recommended Operating Conditions ................................................................ 30 2.2.3 Storage Condition............................................................................................... 31 2.2.4 AC Electrical Characteristics and Timing Diagram ............................................ 31 http://www.DataSheet4U.net/ 2.3 System Configuration ......................................................................................................... 34 2.3.1 Mode Selection................................................................................................... 34 2.3.1 Constant Tie Pins ............................................................................................... 34 2.4 Power-on Sequence ........................................................................................................... 35 2.5 Analog Baseband ............................................................................................................... 36 2.5.1 BBRX.................................................................................................................. 37 2.5.2 BBTX .................................................................................................................. 39 2.5.3 2GBBTX ............................................................................................................. 41 2.5.4 APC-DAC ........................................................................................................... 42 2.5.5 VBIAS-DAC ........................................................................................................ 43 2.5.6 AUXADC ............................................................................................................ 44 2.5.7 Clock Squarer..................................................................................................... 46 2.5.8 Phase Locked Loop............................................................................................ 46 2.5.9 Temperature Sensor .......................................................................................... 51 2.6 Package Information........................................................................................................... 52 2.6.1 Package Outlines ............................................................................................... 52 2.6.2 Thermal Operating Specifications ...................................................................... 52 2.6.3 Lead-free Packaging .......................................................................................... 52 2.7 Ordering Information........................................................................................................... 53 2.7.1 Top Marking Definition ....................................................................................... 53 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 3 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A List of Figures Figure 1-1: Block diagram of MT6589................................................................................................... 11 Figure 2-1 : Ball map view of MT6589 .................................................................................................. 12 Figure 2-2: Basic timing parameter for LPDDR2 commands................................................................ 32 Figure 2-3: Basic timing parameter for LPDDR2 write.......................................................................... 32 Figure 2-4: Basic timing parameter for LPDDR2 read .......................................................................... 33 Figure 2-8: Power on/off sequence with XTAL...................................................................................... 35 Figure 2-9: Power on/off sequence without XTAL................................................................................. 36 Figure 2-10: Block diagram of BBRX-ADC ........................................................................................... 38 Figure 2-11: Block diagram of 2GBBTX ................................................................................................ 41 Figure 2-12: Block diagram of APC-DAC .............................................................................................. 42 Figure 2-13: Block diagram of VBIAS-DAC .......................................................................................... 43 Figure 2-14: Block diagram of AUXADC ............................................................................................... 44 Figure 2-15: Block diagram of PLL ....................................................................................................... 47 Figure 2-16: Outlines and dimensions of FCCSP 11.8mm*11.8mm, 515-ball, 0.4mm pitch package.. 52 Figure 2-17: Top mark of MT6589......................................................................................................... 53 List of Tables Table 2-1: Pin coordinate ...................................................................................................................... 13 Table 2-2: Acronym for pin type ............................................................................................................ 17 Table 2-3: Detailed pin description ........................................................................................................ 17 Table 2-4: Absolute maximum ratings for power supply ....................................................................... 29 Table 2-5: Recommended operating conditions for power http://www.DataSheet4U.net/ supply ........................................................ 30 Table 2-6: LPDDR2 AC timing parameter table of external memory interfaces.................................... 33 Table 2-8: Mode selection of chip (PMU 6320 pin) ............................................................................... 34 Table 2-9: Constant tied pins of MT6589 .............................................................................................. 34 Table 2-10: Baseband downlink specifications ..................................................................................... 38 Table 2-11: Baseband uplink transmitter specifications ........................................................................ 40 Table 2-12: Baseband uplink transmitter specifications ........................................................................ 41 Table 2-13: APC-DAC specifications..................................................................................................... 42 Table 2-14: VBIAS-DAC specifications ................................................................................................. 43 Table 2-15: Definitions of AUXADC channels ....................................................................................... 44 Table 2-16: AUXADC specifications ...................................................................................................... 45 Table 2-17: Clock squarer 1 & 2 specifications ..................................................................................... 46 Table 2-18: ARMPLL specifications....................................................................................................... 47 Table 2-19: MAINPLL specifications ..................................................................................................... 48 Table 2-20: MMPLL specifications ........................................................................................................ 48 Table 2-21: ISPPLL specifications......................................................................................................... 48 Table 2-22: UNIVPLL specifications ...................................................................................................... 49 Table 2-23: MSDCPLL specifications .................................................................................................... 49 Table 2-24: TVDPLL specifications ....................................................................................................... 49 Table 2-25: LVDSPLL specifications ..................................................................................................... 50 Table 2-26: MDPLL1 & MDPLL2 specifications .................................................................................... 50 Table 2-27: WPLL specifications ........................................................................................................... 50 Table 2-28: WHPLL specifications ........................................................................................................ 50 Table 2-29: MCUPLL1 & MCUPLL2 specifications ............................................................................... 51 Table 2-30: Temperature sensor specifications..................................................................................... 51 Table 2-31: Thermal operating specifications ....................................................................................... 52 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 4 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A http://www.DataSheet4U.net/ MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 5 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 1 System Overview MT6589 is a highly integrated baseband platform incorporating both modem and application processing subsystems to enable 3G smart phone applications. The chip integrates a Quad-core ARM® Cortex-A7 MPCoreTM operating up to 1.2GHz, an ARM® Cortex-R4 MCU and a powerful multistandard video accelerator. The MT6589 interfaces to NAND flash memory, 32-bit LPDDR2 for optimal performance and also supports booting from SLC NAND or eMMC to minimize the overall BOM cost. In addition, an extensive set of interfaces and connectivity peripherals are included to interface to cameras, touch-screen displays, MMC/SD cards and external Bluetooth, WiLAN and GPS modules. The application processor, a Quad-core ARM® Cortex-A7 MPCoreTM which includes a NEON multimedia processing engine, offers processing power necessary to support the latest OpenOS along with its demanding applications such as web browsing, email, GPS navigation and games. All are viewed on a high resolution touch screen display with graphics enhanced by the 2D and 3D graphics acceleration. The multi-standard video accelerator and an advanced audio subsystem are also included to provide advanced multimedia applications and services such as streaming audio and video, a multitude of decoders and encoders such as H.264 and MPEG-4. Audio supports include FR, HR, EFR, AMR FR, AMR HR and Wide-Band AMR vocoders, polyphonic ringtones and advanced audio functions such as echo cancellation, hands-free speakerphone operation and noise cancellation. http://www.DataSheet4U.net/ An ARM® Cortex-R4, DSP, and 2G and 3G coprocessors provide a powerful modem subsystem capable of supporting Category 24 (42.2 Mbps) HSDPA downlink and Category 7 (11.5 Mbps) HSUPA uplink data rates, as well as Class 12 GPRS and EDGE. MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 6 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 1.1 Platform Features  General  Smartphone two MCU subsystems architecture  SLC NAND flash and eMMC bootloader  AP MCU subsystem  Quad-core ARM® Cortex-A7 MPCoreTM operating at 1.2GHz  NEON multimedia processing engine with SIMDv2/VFPv4 ISA support  32KB L1 I-cache and 32KB L1 D-cache  1MB unified L2 cache  DVFS technology with adaptive operating voltage from 0.95V to 1.26V  MD MCU subsystem  ARM® Cortex-R4 processor with maximum 480MHz operation frequency  64KB I-cache, 32KB D-cache  256KB TCM (tightly-coupled memory)  DSP for running modem/voice tasks, with maximum 240MHz operation frequency  High-performance AXI and AHB bus  General DMA engine and dedicated DMA channels for peripheral data transfer  Watchdog timer for system error recovery  Power management for clock gating control  MD external interfaces  Supports dual SIM/USIM interface  Interface pins with RF and radio-related peripherals (antenna tuner, PA, …)  UART for modem logging/debugging purpose  External memory interface  Supports LPDDR2 up to 2GB  32-bit data bus width  Memory clock up to 533MHz  Supports self-refresh/partial self-refresh mode  Low-power operation  Programmable slew rate for memory controller’s IO pads  Supports dual rank memory device  Advanced bandwidth arbitration control  Security  ARM® TrustZone® Security  Connectivity  USB2.0 high-speed OTG supporting 15 Tx and 15 Rx endpoints  USB2.0 full-speed host  NAND flash controller supporting NAND http://www.DataSheet4U.net/ bootable, iNAND2® and MoviNAND®  4 UART for GPS, BT, FM-RDS, modem and debugging interfaces  IrDA FIR/MIR/SIR  SPI for external device  7 I2C to control peripheral devices, e.g. CMOS image sensor, LCM or FM receiver module  I2S for connection with optional external hi-end audio codec  GPIOs  4 sets of memory card controllers supporting SD/SDHC/MS/MSPRO/MMC and SDIO2.0/3.0 protocols  Operating conditions  Core voltage: 1.05V  Processor DVFS voltage: 0.95V ~ 1.26V (Typ. 1.05V; sleep mode 0.85V)  Processor SRAM voltage: 1.05V ~ 1.26V (Typ. 1.05V; sleep mode 0.85V) MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 7 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A  GPU voltage: 1.05V  I/O voltage: 1.8V/2.8V/3.3V  Memory: 1.2V/1.8V/1.35V/1.5V/1.25V  NAND: 1.8V/2.8V  LCM interface: 1.8V  Clock source: 26MHz, 32.768kHz  Type: FCCSP  11.8mm x 11.8mm  Height: 1.0mm maximum  Ball count: 515 ballsc  Ball pitch: 0.4mm  Package 1.2 MODEM Features  3G UMTS FDD supported features (with  High dynamic range delta-sigma ADC MT6167) converts the downlink analog I and Q  3G modem supports most main features signals to digital baseband in 3GPP Release 7 and Release 8  10-bit D/A converter for Automatic  CPC (DTX in CELL_DCH, UL DRX DL Power Control (APC) DRX), HS-SCCH-less, HS-DSCH  Programmable radio Rx filter with  Dual cell operation adaptive gain control  MAC-ehs  Dedicated Rx filter for FB acquisition  Two DRX (receiver diversity) schemes  Baseband Parallel Interface (BPI) with in URA_PCH and CELL_PCH programmable driving strength (shared  Uplink Cat. 7 (16QAM), throughput up to 11.5Mbps http://www.DataSheet4U.net/ by 2G & 3G modem)  Supports multi-band  Downlink Cat. 24 (64QAM, dual-cell HSDPA), throughput up to 42.2Mbps  GSM modem and voice CODEC  Fast dormancy  Dial tone generation  ETWS  Noise reduction  Network selection enhancements  Echo suppression  Advanced sidetone oscillation reduction  3G TDD supported features (with  Digital sidetone generator with MT6168) programmable gain  TD-SCDMA/HSDPA/HSUPA baseband  Two programmable acoustic  Supports TD-SCDMA Bands 34, 39 & compensation filters 40 and Quad band GSM/EDGE  GSM quad vocoders for adaptive  Circuit-switched voice and data, and multirate (AMR), enhanced full rate packet-switched data (EFR), full rate (FR) and half rate (HR)  384/384Kbps class in UL/DL for TD-  GSM channel coding, equalization and SCDMA A5/1, A5/2 and A5/3 ciphering  TD-HSDPA: 2.8Mbps DL (Cat.14)  GPRS GEA1, GEA2 and GEA3  TD-HSUPA: 2.2Mbps UL (Cat.6) ciphering  F8/F9 ciphering/integrity protection  Programmable GSM/GPRS/EDGE modem  Packet switched data with  Radio interface and baseband front-end CS1/CS2/CS3/CS4 coding schemes MediaTek Confidential © 2012 MediaTek Inc. Page 8 of 53 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A  GSM circuit switch data  GPRS/EDGE Class 12  Supports SAIC (single antenna interference cancellation) technology  Supports VAMOS (Voice services over Adaptive Multi-user channels on One Slot) technology in R9 spec 1.3 Multimedia Features  Display  Supports landscape or portrait panel  Image resolution up to WXGA (1280x800)  Integrated image signal processor  Supports 8/9/16/18/24-bit host interface supports 13 MP up to 15fps (MIPI DBI)  Supports electronic image stabilization  Supports 8/9/16/24/32-bit serial  Supports video stabilization interfaces  Supports local contrast enhancement  Supports 16/18/24-bit RGB interfaces  Supports preference color adjustment (MIPI DPI)  Supports noise reduction  MIPI DSI interface (4 data lanes)  Supports multiple frame noise reduction  Embedded LCD gamma correction for video recording  Supports true colors  4 overlay layers with per-pixel alpha  Supports lens shading correction http://www.DataSheet4U.net/  Supports auto sensor defect pixel channel and gamma table correction  Supports spatial and temporal dithering  Supports AE/AWB/AF  Supports side-by-side format output to  Supports edge enhancement stereo 3D panel in both portrait and (sharpness) landscape modes  Supports face detection and visual  Supports external HDMI/MHL Tx bridge tracking with 720p video output  Supports multiple frame blending for  Supports color enhancement multi-motion special effect  Supports adaptive contrast  Supports zero shutter delay image enhancement capture  Supports image/video/graphic  Supports capturing full size image when sharpness enhancement recording video (up to 8M sensor)  Supports dynamic backlight scaling  Supports capturing stereo image without bridge IC  Graphics  Supports stereo video recording without  OpenGL ES 1.1/2.0 3D graphic bridge IC accelerator capable of processing 50M  Supports MIPI CSI-2 high-speed tri/sec and 572M pixel/sec @ 286MHz camera serial interface with 4 data lane (effective pixel rate: 1,430M pixel/sec.) (for main) + 2 data lane (for stereo) + 2  OpenVG1.1 vector graphics accelerator data lane (for sub)  2D graphics hardware accelerator  Supports Xenon flash MediaTek Confidential © 2012 MediaTek Inc. Page 9 of 53 This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A  Hardware JPEG decoder: Baseline  Sample formats supported: 8-bit/16-bit, decoding with 42M pixel/sec, Mono/Stereo progressive format decoding support  Interfaces supported: DAI, I2S, PCM  Hardware JPEG encoder: Baseline  4-band IIR compensation filter to encoding with 90M pixel/sec enhance loudspeaker responses  Supports YUV422/YUV420 color format  Proprietary audio post-processing and EXIF/JFIF format technologies: BesLoudness, Android  Hardware WebP decoder built-in post processing  Audio encode: AMR-NB, AMR-WB, AAC,  Video OGG  H.264 decoder: Baseline 1080p @  Audio decode: WAV, MP3, MP2, 30fps/40Mbps AAC, AMR-NB, AMR-WB, MIDI, Vorbis,  H.264 decoder: Main/high profile APE, AAC-plus v1, AAC-plus v2, FLAC, 1080p@30fps/40Mbps WMA  Sorenson H.263/H.263 decoder: 1080p @ 30fps/40Mbps  Speech  MPEG-4 SP/ASP decoder: 1080p @  Speech codec (FR, HR, EFR, AMR FR, 30fps/40Mbps AMR HR and Wide-Band AMR)  DIVX3/DIVX4/DIVX5/DIVX6/DIVX  CTM HD/XVID decoder: 1080p @  Noise reduction 30fps/40Mbps  Noise suppression  VP8 decoder: 1080p @ 30fps/40Mbps http://www.DataSheet4U.net/  Noise cancellation  VC-1 decoder: 1080p @ 30fps/40Mbps  Dual-MIC noise cancellation  MPEG-4 encoder: Simple profile 1080p  Echo cancellation @ 30fps  Echo suppression  H.263 encoder: 1080p @ 30fps  Dual-MIC input  H.264 encoder: High profile 720p @ 30fps  Digital MIC input  VP8 encoder: 720p@ 30fps  Audio  Sampling rates supported: 6kHz to 96kHz 1.4 General Descriptions MediaTek MT6589 is a highly integrated 3G System-on-chip (SoC) which incorporates advanced features e.g. HSPA R8 modem, Quad-core ARM® Cortex-A7 MPCoreTM operating at 1.2 GHz, 3D graphics (OpenGL|ES 2.0), 13M camera ISP, LPDDR2 533MHz and high-definition 1080p video decoder. MT6589 helps phone manufacturers build high-performance 3G smart phones with PC-like browser, 3D gaming and cinema class home entertainment experiences. World-leading technology MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 10 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Based on MediaTek’s world-leading mobile chip SoC architecture with advanced 28nm process, MT6589 is the brand-new generation smart phone SoC integrating MediaTek HSPA R8 modem, 1.2GHz Quad-core ARM® Cortex-A7 MPCoreTM, 3D graphics and high-definition 1080p video decoder. Rich in features, high-valued product To enrich the camera features, MT6589 equips a 13M camera ISP with advanced features e.g. auto focus, anti-handshake, auto sensor defect pixel correction, continuous video AF, face detection, burst shot, optical zoom and panorama view. Incredible browser experience The 1.2GHz Quad-core ARM® Cortex-A7 MPCoreTM with NEON multimedia processing engine brings PC-like browser experiences and helps accelerate OpenGL|ES 2.0 3D Adobe Flash 10 rendering performance to an unbeatable level. NAND Flash USB2.0 HOST USB2.0 OTG JTAG MMC/SD/SDIO LPDDR2 EDGE RF WCDMA RF MT6167 For WCDMA I2C EDGE RF TDSCDMA RF MT6168 For TDSCDMA External Memory Interface HSPA+ MT6589 Modem Analog RX ADC TX ADC APC AFC Modem GSM/GPRS/ EDGE http://www.DataSheet4U.net/ DSP GP Timer Modem MCU Cache TCM Internal Memory ARM® Cortex-R4 JTAG DMA Video Codec Multimedia JPEG Codec Image Post-process Camera ISP LCD Control AP MCU ARM® Cortex-A7 MPCoreTM ARM® Cortex-A7 MPCoreTM ARM® Cortex-A7 MPCoreTM ARM® Cortex-A7 MPCoreTM NEON L2 Cache PowerVR™ SGX544 Graphics accelerator Analog PLL ARM® TrustZone® DAC Power Management ADC GPIO 13MP Camera LCD UART Touch Panel Figure 1-1: Block diagram of MT6589 MT6628 BT/FM WIFI/GPS Qwerty Keypad SIM SIM MT6320 Speaker Battery Headset MIC1 MIC2 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 11 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2 Product Description 2.1 2.1.1 Pin Description Ball Map View http://www.DataSheet4U.net/ Figure 2-1 : Ball map view of MT6589 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 12 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.1.2 Ball Loc. A1 A2 A4 A5 A8 A9 A12 A13 A15 A17 A20 A21 A24 A25 A27 A28 A29 B1 B2 B3 B4 B5 B7 B8 B9 B11 B12 B13 B14 B15 B17 B18 B20 B21 B22 B24 B25 B26 B27 B28 B29 Pin Coordinate Ball name NC SCL2 MSDC3_DAT0 RDQ9 RDQM0 RDQ5 RDQ15 RA6 RA4 RDQ30 RDQ21 RDQM2 RDQ26 MSDC0_DAT4 MSDC0_DAT5 MSDC0_CMD NC SDA2 MRG_I2S_PCM_CLK URXD3 MSDC3_DAT1 RDQ8 RDQ0 RDQ3 RDQ4 RDQ12 RDQ14 RA12 RBA0 RCAS_ RDQ31 RDQ28 RDQ20 RDQ18 RDQ16 RDQ25 MSDC0_DAT2 MSDC0_DAT0 MSDC0_DAT6 NLD4 NRNB Table 2-1: Pin coordinate Ball Loc. K12 K13 K15 K16 K17 K18 K20 K25 K26 K28 L1 L2 L3 L4 L7 L24 L25 L26 L27 L28 L29 M1 M2 M3 M4 M6 M15 M16 M24 M25 M26 M27 M28 M29 N2 N3 N4 N10 N11 N12 N13 Ball name GND DVDD18_EMI DVDD18_EMI GND GND GND DVDD18_EMI ADC_CLK ADC_WS ADC_DAT_IN RDP0 RDN1_A RDP0_A RCP_A DVDD18_MIPIRX GND TESTMODE DAC_WS DAC_DAT_OUT http://www.DataSheet4U.net/ PWRAP_EVENT PWRAP_SPI0_CSN RDN0 RDP2 RDN1 RCP DVSS18_MIPIRX AVSS18_MEMPLL AVDD18_MEMPLL SIM2_SCLK SIM1_SIO PWRAP_SPI0_MI DAC_CLK PWRAP_SPI0_MO PWRAP_SPI0_CLK RDN2 RDP1 RCN DVDD DVDD DVDD DVDD Ball Loc. W19 W20 W24 W25 W26 W27 W28 Y1 Y2 Y3 Y4 Y5 Y24 Y25 Y26 Y27 Y28 Y29 AA1 AA2 AA5 AA6 AA25 AA26 AA28 AA29 AB2 AB4 AB5 AB11 AB25 AB26 AB27 AB28 AC1 AC2 AC3 AC4 AC5 AC26 AC27 Ball name GND DVDD GND URXD4 URXD2 PWM1 URTS2 DVDD33_MC2 MSDC1_INSI MSDC2_INSI MSDC2_DAT1 DPIB4 DVDD28_NML2 URTS1 URXD1 UTXD1 UTXD4 UCTS1 DPIB7 DPIG7 DPIG5 GND CHD_DM_P0 PWM3 PWM4 PWM2 DPIR2 DPIB3 DPIG1 VPROC_FB CHD_DP_P0 AVSS33_USB_P0 USB_DM_P0 AVDD33_USB_P0 DPIG0 DPIHSYNC DPIB0 DPIR6 DPIB1 AVDD18_USB_P1 USB_DP_P0 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 13 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C26 C27 C28 C29 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D17 D18 D19 D20 Ball name SDA1 MRG_I2S_PCM_RX MRG_I2S_PCM_SYNC MSDC3_CLK GND RDQ11 RDQ10 GND RDQM1 RDQ6 RDQ13 RBA1 RRAS_ RODT RA3 RA5 RDQM3 RDQ22 RDQ23 GND RDQ24 RDQ27 GND MSDC0_DAT1 MSDC0_CLK NLD0 NLD7 SCL1 MSDC3_DAT3 MSDC3_DAT2 MSDC3_CMD RDQ1 GND RDQ2 GND RDQ7 GND RA14 RA1 RA10 RA13 GND RDQ29 GND Ball Loc. N14 N15 N16 N17 N18 N19 N24 N25 N28 P1 P2 P3 P4 P6 P7 P8 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P25 P26 P28 P29 R1 R2 R3 R4 R6 R7 R10 R11 R12 R13 R14 R15 R16 Ball name DVDD DVDD DVDD DVDD TN_MEMPLL TP_MEMPLL SIM2_SIO SIM1_SCLK SIM2_SRST RDN3 RDP3 TDN0 TDP1 TDN3 TDP3 TCP DVDD GND GND GND GND GND http://www.DataSheet4U.net/ GND DVDD DVDD DVDD DVDD RTC32K_CK SRCLKENA SIM1_SRST SRCVOLTEN TDP2 TDN2 TDP0 TDN1 VRT TCN GND GND DVDD_DVFS GND GND DVDD_DVFS GND Ball Loc. AD1 AD2 AD3 AD4 AD5 AD6 AD8 AD10 AD11 AD12 AD16 AD20 AD24 AD27 AD28 AD29 AE2 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE17 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AF1 AF2 AF4 AF5 AF6 AF8 AF9 Ball name DPIVSYNC DPIR5 DPIG3 DPIB6 DPIR3 DPIG4 I2S_DATA_OUT EINT10_AUXIN2 GND_VPROC_FB AVSS18_AP AVSS18_MD GND GND AVDD18_USB_P0 USB_VRT USB_DM_P1 DPIB5 DPIR0 LSA0 DISP_PWM EINT5 SDA0 EINT11_AUXIN3 AUX_XM AUX_YP AVSS18_AP AVSS18_MD BSI1A_CS0 BSI1A_DATA1 BSI1B_DATA BSI1B_CS0 BPI1_BUS18 DVDD28_BPI BPI1_BUS16 USB_VBUS AVSS33_USB_P1 USB_DP_P1 DVDD18_NML3 DPIR4 DPIDE SPI1_MO LPCE1B EINT9 SCL0 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 14 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. D21 D22 D23 D24 D25 D26 D27 D28 E1 E2 E5 E6 E9 E11 E12 E13 E14 E15 E16 E17 E18 E20 E23 E25 E26 E28 E29 F1 F2 F4 F6 F9 F12 F16 F17 F18 F20 F23 F25 F28 F29 G2 G3 G4 Ball name RDQ19 GND RDQ17 FSOURCE_P MSDC0_DAT3 MSDC0_DAT7 NCLE NLD14 DAI_RSTB MRG_I2S_PCM_TX SRCLKENAI RDQS0 RDQS1_ RA8 RA11 RCKE RCS_ REXTDN RWE_ DDR3RSTB RA0 RDQS3 RDQS2_ MSDC0_RSTB NLD11 NLD8 NCEB0 DVDD18_NML4 CMPDN UTXD3 RDQS0_ RDQS1 RCS1_ RA2 RA7 RA9 RDQS3_ RDQS2 NLD12 NLD13 NWEB CMFLASH CMMCLK CMPCLK Ball Loc. R17 R18 R19 R20 R24 R25 R26 R27 R28 R29 T2 T3 T4 T5 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T25 T26 T27 T28 U1 U2 U5 U6 U8 U9 U10 U11 U12 U13 U14 U15 U16 Ball name DVDD GND DVDD GND DVDD18_MC0 EINT4 IDDIG EINT3 WATCHDOG SYSRSTB DVSS18_MIPITX DVDD18_MIPITX MSDC1_DAT1 MSDC1_DAT3 GND GND DVDD_GPU GND DVDD_DVFS GND GND DVDD_DVFS http://www.DataSheet4U.net/ GND DVDD GND DVDD GND JTRST_B EINT2 EINT1 EINT0 DVDD33_MC1 MSDC1_CLK MSDC1_CMD MSDC1_SDWPI GND DVDD_GPU DVDD_GPU GND DVDD_DVFS DVDD_DVFS DVDD_DVFS DVDD_DVFS GND Ball Loc. AF10 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF26 AF27 AF28 AF29 AG1 AG2 AG3 AG4 AG5 AG8 AG9 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG22 AG23 AG26 AG27 AG28 AH1 AH2 AH3 AH4 AH5 Ball name EINT16_AUXIN4 AUX_XP UL_Q_N2 UL_Q_P2 DL_Q_P2 DL_Q_N2 UL_I_N1 UL_I_P1 UL_Q_P1 UL_Q_N1 BSI1C_CLK SRCLKENA2 BSI1B_CLK BPI1_BUS11 BPI1_BUS6 BPI1_BUS4 VM0 AVDD33_USB_P1 DPIB2 DPIR7 DPIR1 LSCK SPI1_CLK EINT7 I2S_CLK AUX_YM UL_I_P2 UL_I_N2 DL_I_P2 DL_I_N2 DVDD18_MD VBIAS APC2 APC1 BSI1A_DATA2 DVDD28_BSI BPI1_BUS1 BPI1_BUS8 BPI1_BUS5 DPIG2 DPIG6 LSDA LPCE0B SPI1_MI MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 15 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX Ball Loc. G25 G26 G27 G28 H1 H2 H3 H4 H10 H12 H13 H14 H15 H16 H18 H19 H20 H25 H26 H27 H28 H29 J1 J2 J3 J4 J6 J10 J11 J14 J17 J18 J19 J20 J25 J28 J29 K2 K3 K4 K6 K10 K11 Ball name NLD15 NLD1 NLD3 NLD6 DVDD18_MIPIIO CMRST RDN0_B RCN_B DVDD18_EMI RCLK1 RCLK1_ VREF RCLK0_ RCLK0 VREF DVDD18_EMI DVDD18_EMI NLD10 NALE NLD2 NLD5 NCEB1 RDN1_B RDP1_B RDP0_B RCP_B GND DVDD18_EMI DVDD18_EMI GND DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI NREB NLD9 DVDD18_NML1 RDP1_A RDN0_A RCN_A DVSS18_MIPIIO GND GND MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Ball Loc. U17 U18 U19 U20 U24 U25 U28 U29 V1 V2 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V24 V25 V26 V28 V29 W2 W3 W4 W5 W8 W11 W12 W13 W14 W15 W16 Ball name DVDD GND DVDD DVDD JTCK JRTCK JTDO JTDI MSDC1_DAT0 MSDC1_DAT2 MSDC2_DAT0 MSDC2_SDWPI GND GND GND DVDD_GPU DVDD_GPU GND DVDD_DVFS DVDD_DVFS DVDD_DVFS DVDD_DVFS http://www.DataSheet4U.net/ GND DVDD GND GND DVDD UTXD2 UCTS2 JTMS SDA3 SCL3 MSDC2_DAT2 MSDC2_CLK MSDC2_CMD MSDC2_DAT3 DVDD18_MC12 GND DVDD_DVFS DVDD_SRAM DVDD_SRAM DVDD_DVFS GND Ball Loc. AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AJ1 AJ2 AJ3 AJ5 AJ6 AJ8 AJ9 AJ11 AJ12 AJ14 AJ16 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AJ28 AJ29 Ball name LRSTB LPTE EINT6 I2S_WS AUXIN1 AUXIN0 REFP REFN AVDD18_MD DL_I_N1 DL_Q_N1 DL_Q_P1 AVDD28_DAC TXBPI1 BSI1A_DATA0 BSI1A_CLK BSI1C_DATA BPI1_BUS10 BPI1_BUS13 BPI1_BUS9 BPI1_BUS17 BPI1_BUS3 VM1 NC DPICK LSCE0B LSCE1B SPI1_CSN EINT8 I2S_DATA_IN DVDD18_PLLGP AVDD18_AP CLK26M2 DL_I_P1 CLK26M1 EXT_CLK_EN DVDD18_BSI BPI1_BUS0 BPI1_BUS7 BPI1_BUS2 BPI1_BUS12 NC MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 16 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.1.3 Detailed Pin Description Table 2-2: Acronym for pin type Abbreviation AI Description Analog input AO Analog output AIO Analog bi-direction DI Digital input DO Digital output DIO Digital bi-direction P Power G Ground Pin name SYSTEM SYSRSTB WATCHDOG SRCVOLTEN TESTMODE RTC32K_CK SRCLKENAI SRCLKENA PMIC PWRAP_SPI0_MO PWRAP_SPI0_MI PWRAP_SPI0_CSN PWRAP_SPI0_CLK PWRAP_EVENT ADC_CLK ADC_WS ADC_DAT_IN DAC_CLK DAC_WS DAC_DAT_OUT SIM SIM1_SIO SIM1_SRST SIM1_SCLK SIM2_SIO SIM2_SRST SIM2_SCLK JTAG JTCK Table 2-3: Detailed pin description Type Description DIO DO DIO DIO DIO DIO DIO System reset input Watchdog reset output Wakeup signal to external PMIC Test mode 32K clock intput http://www.DataSheet4U.net/ 26MHz co-clock enable input 26MHz co-clock enable output DIO PMIC SPI control interface DIO PMIC SPI control interface DIO PMIC SPI control interface DIO PMIC SPI control interface DIO PMIC SPI control interface DIO PMIC audio input interface DIO PMIC audio input interface DIO PMIC audio input interface DIO PMIC audio output interface DIO PMIC audio output interface DIO PMIC audio output interface DIO SIM1 data, PMIC interface DIO SIM1 reset, PMIC interface DIO SIM1 clock, PMIC interface DIO SIM2 data, PMIC interface DIO SIM2 reset, PMIC interface DIO SIM2 clock, PMIC interface DIO JTCK Power domain DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML4 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 17 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name JTDO JTRST_B JTDI JRTCK JTMS LCD DISP_PWM LPCE1B LPCE0B LPTE LRSTB DPI DPIDE DPICK DPIVSYNC DPIHSYNC DPIR7 DPIR6 DPIR5 DPIR4 DPIR3 DPIR2 DPIR1 DPIR0 DPIG7 DPIG6 Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description JTDO JTRST_B JTDI JRTCK JTMS Display PWM output Parallel display interface chip select 1 output Parallel display interface chip select 0 output Parallel display interface tearing effect Parallel display interface Reset Signal Data enable signal of DPI Clock pin of DPI Vertical synchronization signal of DPI Horizontal synchronization signal of DPI Data pin 7 of DPI Rchannel/Data 23 for DBI parallel http://www.DataSheet4U.net/ LCD interface Data pin 6 of DPI Rchannel/Data 22 for DBI parallel LCD interface Data pin 5 of DPI Rchannel/Data 21 for DBI parallel LCD interface Data pin 4 of DPI Rchannel/Data 20 for DBI parallel LCD interface Data pin 3 of DPI Rchannel/Data 19 for DBI parallel LCD interface Data pin 2 of DPI Rchannel/Data 18 for DBI parallel LCD interface Data pin 1 of DPI Rchannel/Data 17 for DBI parallel LCD interface Data pin 0 of DPI Rchannel/Data 16 for DBI parallel LCD interface Data pin 7 of DPI Gchannel/Data 15 for DBI parallel LCD interface Data pin 6 of DPI Gchannel/Data 14 for DBI parallel Power domain DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 18 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name DPIG5 DPIG4 DPIG3 DPIG2 DPIG1 DPIG0 DPIB7 DPIB6 DPIB5 DPIB4 DPIB3 DPIB2 DPIB1 DPIB0 SLCD LSCE0B LSCK LSCE1B LSDA LSA0 Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description LCD interface Data pin 5 of DPI Gchannel/Data 13 for DBI parallel LCD interface Data pin 4 of DPI Gchannel/Data 12 for DBI parallel LCD interface Data pin 3 of DPI Gchannel/Data 11 for DBI parallel LCD interface Data pin 2 of DPI Gchannel/Data 10 for DBI parallel LCD interface Data pin 1 of DPI Gchannel/Data 9 for DBI parallel LCD interface Data pin 0 of DPI Gchannel/Data 8 for DBI parallel LCD interface Data pin 7 of DPI Bchannel/Data 7 for DBI parallel LCD interface Data pin 6 of DPI Bchannel/Data 6 for DBI parallel LCD interface Data pin 5 of DPI Bhttp://www.DataSheet4U.net/ channel/Data 5 for DBI parallel LCD interface Data pin 4 of DPI Bchannel/Data 4 for DBI parallel LCD interface Data pin 3 of DPI Bchannel/Data 3 for DBI parallel LCD interface Data pin 2 of DPI Bchannel/Data 2 for DBI parallel LCD interface Data pin 1 of DPI Bchannel/Data 1 for DBI parallel LCD interface Data pin 0 of DPI Bchannel/Data 0 for DBI parallel LCD interface Serial display interface chip select 0 output Serial display interface clock output Serial display interface chip select 1 output Serial display interface data Serial display interface address Power domain DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 19 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name Type I2S I2S_DATA_IN DIO I2S_DATA_OUT DIO I2S_WS DIO I2S_CK DIO PCM/I2S merge interface MRG_I2S_PCM_TX DIO MRG_I2S_PCM_CLK DIO MRG_I2S_PCM_RX MRG_I2S_PCM_SYN C DAI_RSTB EINT EINT0 EINT1 EINT2 EINT3 EINT4 EINT5 EINT6 EINT7 EINT8 EINT9 EINT10_AUX_IN2 DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO/AIO EINT11_AUX_IN3 DIO/AIO EINT16_AUX_IN4 PWM PWM1 PWM2 PWM3 PWM4 UART1 URXD1 URTS1 UCTS1 UTXD1 UART2 UTXD2 URXD2 DIO/AIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description output I2S data input pin I2S data output pin I2S word select I2S clock PCM/I2S/merge audio interface to MT6628 PCM/I2S/merge audio interface to MT6628 PCM/I2S/merge audio interface to MT6628 PCM/I2S/merge audio interface to MT6628 PCM/I2S/merge audio interface to MT6628 External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 http://www.DataSheet4U.net/ External interrupt 6 External interrupt 7 External interrupt 8 External interrupt 9 External interrupt 10/Aux ADC external channel 2 External interrupt 11/Aux ADC external channel 3 External interrupt 16/Aux ADC external channel 4 PWM1 PWM2 PWM3 PWM4 UART1 RX UART1 RTS UART1 CTS UART1 TX UART2 TX UART2 RX Power domain DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD28_NML2 DVDD28_NML2 DVDD28_NML2 DVDD28_NML2 DVDD28_NML2 DVDD28_NML2 DVDD28_NML2 DVDD28_NML2 DVDD18_NML1 DVDD18_NML1 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 20 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name UCTS2 URTS2 UART3 UTXD3 URXD3 UART4 UTXD4 URXD4 SPI SPI1_CSN SPI1_MI SPI1_MO SPI1_CLK BPI BPI_BUS0 BPI_BUS1 BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 BPI_BUS10 BPI_BUS11 BPI_BUS12 BPI_BUS13 BPI_BUS16 BPI_BUS17 BPI_BUS18 VM VM1 VM0 BSI BSI1A_CS0 BSI1A_CLK BSI1A_DATA0 BSI1A_DATA1 BSI1A_DATA2 BSI1B_CS0 BSI1B_CLK BSI1B_DATA BSI1C_CLK BSI1C_DATA Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description UART2 CTS UART2 RTS UART3 TX UART3 RX UART4 TX UART4 RX SPI1 chip select SPI1 data in SPI1 data out SPI1 clock BPI BUS0 BPI BUS1 BPI BUS2 BPI BUS3 BPI BUS4 BPI BUS5 BPI BUS6 BPI BUS7 BPI BUS8 http://www.DataSheet4U.net/ BPI BUS9 BPI BUS10 BPI BUS11 BPI BUS12 BPI BUS13 BPI BUS16 BPI BUS17 BPI BUS18 PA mode selection PA mode selection BSI1A CS0 BSI1A CLK BSI1A DATA0 BSI1A DATA1 BSI1A DATA2 BSI1B CS0 BSI1B CLK BSI1B DATA BSI1C CLK BSI1C DATA Power domain DVDD18_NML1 DVDD18_NML1 DVDD18_NML4 DVDD18_NML4 DVDD28_NML2 DVDD28_NML2 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD18_NML3 DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD28_BPI DVDD18_BSI DVDD18_BSI DVDD18_BSI DVDD18_BSI DVDD18_BSI DVDD28_BSI DVDD28_BSI DVDD28_BSI DVDD18_BSI DVDD18_BSI MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 21 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name TXBPI1 EXT_CLK_EN SRCLKENA2 MSDC0 MSDC0_DAT6 MSDC0_DAT7 MSDC0_DAT5 MSDC0_RSTB MSDC0_DAT4 MSDC0_DAT2 MSDC0_DAT3 MSDC0_CMD MSDC0_CLK MSDC0_DAT1 MSDC0_DAT0 MSDC1 MSDC1_CLK MSDC1_CMD MSDC1_DAT0 MSDC1_DAT1 MSDC1_DAT2 MSDC1_DAT3 MSDC1_SDWPI MSDC1_INSI MSDC2 MSDC2_CLK MSDC2_CMD MSDC2_DAT0 MSDC2_DAT1 MSDC2_DAT2 MSDC2_DAT3 MSDC2_SDWPI MSDC2_INSI MSDC3 MSDC3_CLK MSDC3_CMD MSDC3_DAT0 MSDC3_DAT1 MSDC3_DAT2 MSDC3_DAT3 NFI NCEB0 NCEB1 Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description RF MT6167 TXBPI1 Co-clock control pin Co-clock control pin MSDC0 data6 pin MSDC0 data7 pin MSDC0 data5 pin MSDC0 reset output MSDC0 data4 pin MSDC0 data2 pin MSDC0 data3 pin MSDC0 command pin MSDC0 clock output MSDC0 data1 pin MSDC0 data0 pin MSDC1 clock output MSDC1 command pin MSDC1 data0 pin MSDC1 data1 pin MSDC1 data2 pin MSDC1 data3 pin http://www.DataSheet4U.net/ MSDC1 WP pin MSDC1 card insertion MSDC2 clock output MSDC2 command pin MSDC2 data0 pin MSDC2 data1 pin MSDC2 data2 pin MSDC2 data3 pin MSDC2 WP pin MSDC2 card insertion MSDC3 clock output MSDC3 command pin MSDC3 data0 pin MSDC3 data1 pin MSDC3 data2 pin MSDC3 data3 pin Parallel NAND interface chip select 0 output Parallel NAND interface chip select 1 output Power domain DVDD18_BSI DVDD18_BSI DVDD18_BSI DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD18_MC0 DVDD33_MC1/DVDD18_MC12 DVDD33_MC1/DVDD18_MC12 DVDD33_MC1/DVDD18_MC12 DVDD33_MC1/DVDD18_MC12 DVDD33_MC1/DVDD18_MC12 DVDD33_MC1/DVDD18_MC12 DVDD33_MC1/DVDD18_MC12 DVDD18_NML3 DVDD33_MC2/DVDD18_MC12 DVDD33_MC2/DVDD18_MC12 DVDD33_MC2/DVDD18_MC12 DVDD33_MC2/DVDD18_MC12 DVDD33_MC2/DVDD18_MC12 DVDD33_MC2/DVDD18_MC12 DVDD33_MC2/DVDD18_MC12 DVDD33_MC2/DVDD18_MC12 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML1 DVDD18_NML1 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 22 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name NRNB NCLE NALE NREB NWEB NLD0 NLD1 NLD2 NLD3 NLD4 NLD5 NLD6 NLD7 NLD8 NLD9 NLD10 NLD11 NLD12 NLD13 NLD14 NLD15 EFUSE FSOURCE_P EMI DDR3RSTB RCLK0 RCLK0_ RCLK1 RCLK1_ RCKE RCS_ RCS1_ RCAS_ RRAS_ RWE_ RBA0 RBA1 RA0 RA1 RA2 RA3 Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description Parallel NAND interface chip ready input Parallel NAND interface command latch enable output Parallel NAND interface address latch enable output Parallel NAND interface read strobe output Parallel NAND interface write strobe output Nand-Flash Data 0 Nand-Flash Data 1 Nand-Flash Data 2 Nand-Flash Data 3 Nand-Flash Data 4 Nand-Flash Data 5 Nand-Flash Data 6 Nand-Flash Data 7 Nand-Flash Data 8 Nand-Flash Data 9 Nand-Flash Data 10 Nand-Flash Data 11 Nand-Flash Data 12 http://www.DataSheet4U.net/ Nand-Flash Data 13 Nand-Flash Data 14 Nand-Flash Data 15 E-FUSE blowing power control DDR3 reset output # DRAM clock 0 output DRAM clock 0 output # DRAM clock 1 output DRAM clock 1 output # DRAM command output CKE DRAM chip select 0 # DRAM chip select 1 # DRAM command output CAS# DRAM command output RAS# DRAM command output WR# DRAM bank address output 0 DRAM bank address output 1 DRAM address output 0 DRAM address output 1 DRAM address output 2 DRAM address output 3 Power domain DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 DVDD18_NML1 FSOURCE_P DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 23 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13 RA14 RDQM0 RDQM1 RDQM2 RDQM3 RDQS0 RDQS0_ RDQS1 RDQS1_ RDQS2 RDQS2_ RDQS3 RDQS3_ RDQ0 RDQ1 RDQ2 RDQ3 RDQ4 RDQ5 RDQ6 RDQ7 RDQ8 RDQ9 RDQ10 RDQ11 RDQ12 RDQ13 RDQ14 RDQ15 RDQ16 RDQ17 RDQ18 RDQ19 RDQ20 RDQ21 Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Description DRAM address output 4 DRAM address output 5 DRAM address output 6 DRAM address output 7 DRAM address output 8 DRAM address output 9 DRAM address output 10 DRAM address output 11 DRAM address output 12 DRAM address output 13 DRAM address output 14 DRAM DQM 0 DRAM DQM 1 DRAM DQM 2 DRAM DQM 3 DRAM DQS 0 DRAM DQS 0 # DRAM DQS 1 DRAM DQS 1 # DRAM DQS 2 DRAM DQS 2 # DRAM DQS 3 http://www.DataSheet4U.net/ DRAM DQS 3 # DRAM data pin 0 DRAM data pin 1 DRAM data pin 2 DRAM data pin 3 DRAM data pin 4 DRAM data pin 5 DRAM data pin 6 DRAM data pin 7 DRAM data pin 8 DRAM data pin 9 DRAM data pin 10 DRAM data pin 11 DRAM data pin 12 DRAM data pin 13 DRAM data pin 14 DRAM data pin 15 DRAM data pin 16 DRAM data pin 17 DRAM data pin 18 DRAM data pin 19 DRAM data pin 20 DRAM data pin 21 Power domain DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 24 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name RDQ22 RDQ23 RDQ24 RDQ25 RDQ26 RDQ27 RDQ28 RDQ29 RDQ30 RDQ31 RODT(/RBA2) REXTDN CAM CMPCLK CMMCLK CMRST CMPDN CMFLASH I2C0 SCL0 SDA0 I2C1 SCL1 SDA1 I2C2 SCL2 SDA2 I2C3 SCL3 SDA3 ABB UL_Q_N1 UL_Q_P1 UL_I_P1 UL_I_N1 VBIAS APC1 APC2 CLK26M1 DL_Q_P1 DL_Q_N1 DL_I_N1 Type DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO Description DRAM data pin 22 DRAM data pin 23 DRAM data pin 24 DRAM data pin 25 DRAM data pin 26 DRAM data pin 27 DRAM data pin 28 DRAM data pin 29 DRAM data pin 30 DRAM data pin 31 DRAM ODT pin(/DRAM bank address output 2) DRAM REXTDN pin Pixel clock from sensor Master clock to sensor Reset control to sensor Power down to sensor Camera flash control signal I2C0 clock I2C0 data I2C1 clock I2C1 data http://www.DataSheet4U.net/ I2C2 clock I2C2 data I2C3 clock I2C3 data UMTS uplink for UMTSTX_QN UMTS uplink for UMTSTX_QP UMTS uplink for UMTSTX_IP UMTS uplink for UMTSTX_IN 3G PA analog control Automatic power control for 1st modem Automatic power control for 2nd modem 26MHz clock input for AP & 1st modem UMTS uplink for UMTSRX_QP UMTS uplink for UMTSRX_QN UMTS uplink for UMTSRX_IN Power domain DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_EMI DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML3 DVDD18_NML3 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML4 DVDD18_NML1 DVDD18_NML1 DVDD18_MD DVDD18_MD DVDD18_MD DVDD18_MD AVDD28_DAC AVDD28_DAC AVDD28_DAC AVDD18_MD DVDD18_MD DVDD18_MD DVDD18_MD MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 25 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name DL_I_P1 DL_Q_P2 DL_Q_N2 DL_I_N2 DL_I_P2 CLK26M2 UL_Q_N2 UL_Q_P2 UL_I_P2 UL_I_N2 REFN REFP AUX_IN0 AUX_IN1 AUX_XP AUX_YP AUX_XM AUX_YM MIPI TDN3 TDP3 TDN2 TDP2 TCN TCP TDN1 TDP1 TDN0 TDP0 Type AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO Description UMTS uplink for UMTSRX_IP UMTS uplink for 2nd UMTSRX_QP or WCDMA diversity path UMTS uplink for 2nd UMTSRX_QN or WCDMA diversity path UMTS uplink for 2nd UMTSRX_IN or WCDMA diversity path UMTS uplink for 2nd UMTSRX_IP or WCDMA diversity path 26MHz clock input for AP & 2nd modem UMTS uplink for 2nd UMTSTX_QN UMTS uplink for 2nd UMTSTX_QP UMTS uplink for 2nd UMTSTX_IP UMTS uplink for 2nd UMTSTX_IN Negative reference port for internal circuit Positive reference port for http://www.DataSheet4U.net/ internal circuit AuxADC external input channel 0 AuxADC external input channel 1 AuxADC channel for touch screen TP_X+ AuxADC channel for touch screen TP_Y+ AuxADC channel for touch screen TP_X- AuxADC channel for touch screen TP_Y- DSI0 lane3 N DSI0 lane3 P DSI0 lane2 N DSI0 lane2 P DSI0 CK lane N DSI0 CK lane P DSI0 lane1 N DSI0 lane1 P DSI0 lane0 N DSI0 lane0 P Power domain DVDD18_MD DVDD18_MD DVDD18_MD DVDD18_MD DVDD18_MD AVDD18_MD AVDD18_MD AVDD18_MD AVDD18_MD AVDD18_MD AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP AVDD18_AP DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX DVDD18_MIPITX MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 26 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name VRT RDN3 RDP3 RDN2 RDP2 RCN RCP RDN1 RDP1 RDN0 RDP0 RDN1_A RDP1_A RCN_A RCP_A RDN0_A RDP0_A RDN1_B RDP1_B RCN_B RCP_B RDN0_B RDP0_B USB USB_DP_P0 USB_DM_P0 CHD_DP_P0 CHD_DM_P0 USB_VRT USB_VBUS Type AO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AIO AO AI Description External resistor for DSI bias Connect 1.5K ohm 1% resistor to ground. CSI0 lane3 N CSI0 lane3 P CSI0 lane2 N CSI0 lane2 P CSI0 CK lane N CSI0 CK lane P CSI0 lane1 N CSI0 lane1 P CSI0 lane0 N CSI0 lane0 P CSI1 lane1 N/Pixel data [6] from sensor CSI1 lane1 P/Pixel data [7] from sensor CSI1 CK lane N/Pixel data [8] from sensor CSI1 CK lane P/Pixel data [9] from sensor CSI1 lane0 N/VREF from sensor CSI1 lane0 P/HREF from http://www.DataSheet4U.net/ sensor CSI1 sub-cam lane1 N/Pixel data [2] from sensor CSI1 sub-cam lane1 P/Pixel data [3] from sensor CSI1 sub-cam CK lane N/Pixel data [4] from sensor CSI1 sub-cam CK lane P/Pixel data [5] from sensor CSI1 sub-cam lane0 N/Pixel data [0] from sensor CSI1 sub-cam lane0 P/Pixel data [1] from sensor USB port0 D+ differential data line USB port0 D- differential data line BC1.1 Charger DP BC1.1 Charger DM USB output for bias current; connect with 5.11K 1% Ohm to GND Power for connected device +3.3V Power domain DVDD18_MIPITX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIRX DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO DVDD18_MIPIIO AVDD33_USB_P0 AVDD33_USB_P0 AVDD33_USB_P0 AVDD33_USB_P0 AVDD18_USB_P0 AVDD18_USB_P0 MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 27 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name USB_DP_P1 USB_DM_P1 IDDIG MEMPLL TP_MEMPLL TN_MEMPLL Analog power DVDD18_PLLGP AVDD18_AP AVDD18_MD DVDD18_MD AVDD28_DAC DVDD18_MIPITX DVDD18_MIPIRX DVDD18_MIPIIO AVDD33_USB_P0 AVDD33_USB_P1 AVDD18_USB_P0 AVDD18_USB_P1 AVDD18_MEMPLL Digital power DVDD18_NML1 DVDD28_NML2 DVDD18_NML3 DVDD18_NML4 DVDD28_BPI DVDD28_BSI DVDD18_BSI DVDD18_EMI DVDD18_MC0 DVDD33_MC1 Type AIO AIO DIO AIO AIO P P P P P P P P P P P P P P P P P P P P P P P Description USB port1 D+ differential data line USB port1 D- differential data line USB OTG ID pin MEMPLL differential output P for debug MEMPLL differential output N for debug Analog power input 1.8V for PLL Analog power input 1.8V for AuxADC, TSENSE Analog power input 1.8V for BBTX, BBRX, 2GBBTX Alternative analog power input 1.8V for BBTX, BBRX, 2GBBTX Analog power input 2.8V for APC Analog power for MIPI DSI Analog power for MIPI CSI0 Analog power for MIPI CSI1 & GPI http://www.DataSheet4U.net/ Analog power 3.3V for USB port 0 Analog power 3.3V for USB port 1 Analog power 1.8V for USB port 0 Analog power 1.8V for USB port 1 Analog power for MEMPLL Digital power input for NML1 Digital power input for NML2 Digital power input for NML3 Digital power input for NML4 Digital power input for 2.8V BPI IO Digital power input for 2.8V BSI IO Digital power input for 1.8V BSI IO Digital power input for EMI Digital power input for MSDC0 Digital power input for MSDC1 transmitter Power domain AVDD33_USB_P1 AVDD33_USB_P1 DVDD18_NML1 AVDD18_MEMPLL AVDD18_MEMPLL - MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 28 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name DVDD33_MC2 DVDD18_MC12 DVDD_GPU DVDD DVDD_DVFS DVDD_SRAM Analog ground AVSS18_AP AVSS18_MD DVSS18_MIPITX DVSS18_MIPIRX DVSS18_MIPIIO AVSS33_USB_P0 AVSS33_USB_P1 AVSS18_MEMPLL Digital ground GND Type P P P P P P G G G G G G G G G Description Digital power input for MSDC2 transmitter Digital power input for MSDC1/MSDC2 receiver Digital power input for graphic processor Digital power input for core Digital power input for processor Digital power input for processor memory 2.2 http://www.DataSheet4U.net/ Electrical Characteristic Power domain - - 2.2.1 Absolute Maximum Ratings Table 2-4: Absolute maximum ratings for power supply Symbol or pin name Description Min. Max. Unit DVDD18_PLLGP Analog power input 1.8V for PLL 1.7 1.9 V AVDD18_AP Analog power input 1.8V for AuxADC, TSENSE 1.7 1.9 V AVDD18_MD Analog power input 1.8V for BBTX, BBRX, 2GBBTX 1.7 1.9 V DVDD18_MD Alternative analog power input 1.8V for BBTX, BBRX, 2GBBTX 1.7 1.9 V AVDD28_DAC Analog power input 2.8V for APC 2.66 2.94 V DVDD18_MIPITX Analog power for MIPI DSI 1.7 1.9 V DVDD18_MIPIRX Analog power for MIPI CSI0 1.7 1.9 V DVDD18_MIPIIO Analog power for MIPI CSI1 & GPI 1.7 1.9 V AVDD33_USB_P0 Analog power 3.3V for USB port 0 3.135 3.465 V AVDD33_USB_P1 Analog power 3.3V for USB port 1 3.135 3.465 V AVDD18_USB_P0 Analog power 1.8V for USB port 0 1.7 1.9 V AVDD18_USB_P1 Analog power 1.8V for USB port 1 1.7 1.9 V AVDD18_MEMPLL Analog power for MEMPLL 1.7 1.9 V DVDD18_NML1 Digital power input for NML1 1.62 1.98 V MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 29 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol or pin name DVDD28_NML2 DVDD18_NML3 DVDD18_NML4 DVDD28_BPI DVDD28_BSI DVDD18_BSI DVDD18_MC0 DVDD18_MC12 DVDD33_MC1 DVDD33_MC2 DVDD18_EMI DVDD DVDD_GPU DVDD_DVFS DVDD_SRAM Description Digital power input for NML2 Digital power input for NML3 Digital power input for NML4 Digital power input for BPI Digital power input for BSI Digital power input for BSI Digital power input for MSDC0 Digital power input for MSDC1/MSDC2 Digital power input for MSDC1 Digital power input for MSDC2 Digital power input for EMI Digital power input for core Digital power input for GPU Digital power input for processor Digital power input for processor memory Min. Max. Unit 1.7 3.6 V 1.62 1.98 V 1.62 1.98 V 1.7 3.6 V 1.7 3.6 V 1.62 1.98 V 1.62 1.98 V 1.62 1.98 V 1.7 3.6 V 1.7 3.6 V 1.08 1.98 V 0.95 1.15 V 0.95 1.26 V 0.77 1.26 V 0.95 1.26 V Warning: Stressing the device beyond the absolute maximum ratings may cause permanent damage. These are stress ratings only. 2.2.2 Recommended Operating Conditions http://www.DataSheet4U.net/ Table 2-5: Recommended operating conditions for power supply Symbol or pin name Description Min. Typ. Max. Unit DVDD18_PLLGP Analog power input 1.8V for PLL 1.7 1.8 1.89 V AVDD18_AP Analog power input 1.8V for AuxADC, TSENSE 1.71 1.8 1.89 V AVDD18_MD Analog power input 1.8V for BBTX, BBRX, 2GBBTX 1.71 1.8 1.89 V DVDD18_MD Alternative analog power input 1.8V for BBTX, BBRX, 2GBBTX 1.71 1.8 1.89 V AVDD28_DAC Analog power input 2.8V for APC 2.66 2.8 2.94 V DVDD18_MIPITX Analog power for MIPI DSI 1.71 1.8 1.89 V DVDD18_MIPIRX Analog power for MIPI CSI0 1.71 1.8 1.89 V DVDD18_MIPIIO Analog power for MIPI CSI1 & GPI 1.71 1.8 1.89 V AVDD33_USB_P0 Analog power 3.3V for USB port 0 3.135 3.3 3.465 V AVDD33_USB_P1 Analog power 3.3V for USB port 1 3.135 3.3 3.465 V AVDD18_USB_P0 Analog power 1.8V for USB port 0 1.71 1.8 1.89 V AVDD18_USB_P1 Analog power 1.8V for USB port 1 1.71 1.8 1.89 V AVDD18_MEMPLL Analog power for MEMPLL 1.71 1.8 1.89 V DVDD18_NML1 Digital power input for NML1 1.62 1.8 1.98 V DVDD28_NML2 Digital power input for NML2 1.7 1.8 1.95 V 2.7 3.3 3.6 DVDD18_NML3 Digital power input for NML3 1.62 1.8 1.98 V MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 30 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol or pin name DVDD18_NML4 DVDD28_BPI DVDD28_BSI DVDD18_BSI DVDD18_MC0 DVDD18_MC12 DVDD33_MC1 DVDD33_MC2 DVDD18_EMI DVDD DVDD_GPU DVDD_DVFS DVDD_SRAM Description Digital power input for NML4 Digital power input for BPI Digital power input for BSI Digital power input for BSI Digital power input for MSDC0 Digital power input for MSDC1/MSDC2 Digital power input for MSDC1 Digital power input for MSDC2 Digital power input for EMI (LPDDR2) Digital power input for EMI (UVDDR3) Digital power input for EMI (LVDDR3) Digital power input for EMI (DDR3) Digital power input for core Digital power input for GPU Digital power input for processor Digital power input for processor memory Min. Typ. Max. Unit 1.62 1.8 1.98 V 1.7 1.8 1.95 V 2.7 3.3 3.6 1.7 1.8 1.95 V 2.7 3.3 3.6 1.62 1.8 1.98 V 1.62 1.8 1.98 V 1.62 1.8 1.98 V 1.7 1.8 1.95 V 2.7 3.3 3.6 1.7 1.8 1.95 V 2.7 3.3 3.6 1.08 1.2 1.32 1.125 1.25 1.375 V 1.215 1.35 1.485 1.35 1.5 1.65 1.00 1.05 1.10 V 1.00 1.05 1.20 V 0.81 1.15 1.20 V 1.00 1.15 1.20 V 2.2.3 Storage Condition http://www.DataSheet4U.net/ 1. Shelf life in sealed bag: 12 months at < 40°C and < 90% relative humidity (RH). 2. After bag opened, devices subjected to infrared reflow, vapor-phase reflow, or equivalent processing must be:  Mounted within 168 hours at factory conditions of 30°C/60% RH, or  Stored at 20% RH. 3. Devices require baking before mounting, if:  192 hours at 40°C +5°C/-0°C and < 5% RH for low temperature device containers, or  24 hours at 125°C +5°C/-0°C for high temperature device containers. 2.2.4 AC Electrical Characteristics and Timing Diagram 2.2.4.1 External Memory Interface for LPDDR2 The external memory interface, shown in Figure 2-4, Figure 2-5 and Figure 2-6, is used to connect LPDDR2 device for MT6589. It includes pins ED_CLK, ED_CLK_B, ECKE, ECS#, EBA[2:0], EDQS[3:0], EDQS#[3:0], EA[9:0] and ED[31:0]. Table 2-5 summarizes the symbol definition and the related timing specifications. MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 31 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX ED_CLK_B ED_CLK ECS_B MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A ECA0-9 [CMD] Figure 2-2: Basic timing parameter for LPDDR2 commands ED_CLK_B ED_CLK ECA0-9 [CMD] EDQS /EDQS_B EDQs http://www.DataSheet4U.net/ EDQS /EDQS_B EDQs Figure 2-3: Basic timing parameter for LPDDR2 write MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 32 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Figure 2-4: Basic timing parameter for LPDDR2 read http://www.DataSheet4U.net/ Table 2-6: LPDDR2 AC timing parameter table of external memory interfaces Symbol tCK tDQSCK tCH tCL tHP tDS tDH tDQSS tDSS tDSH Description Clock cycle time DQS output access time from CK/CK’ Clock high level width Clock low level width Clock half period DQ & DM input setup time DQ & DM input hold time Write command to 1st DQS latching transition DQS falling edge to CK setup time DQS falling edge hold time from CK Min. 3.75 2.5 0.45 0.45 0.45 0.43 0.43 0.75 0.2 0.2 Typ. Max. Unit 8 ns 5.5 ns 0.55 tCK 0.55 tCK 0.55 tCK ns ns 1.25 tCK tCK tCK tIS Address & control input setup time 0.46 ns tIH Address & control input hold time 0.46 ns tLZ(DQS) DQS low-impedance time from CK/CK’ tDQSCK (Min.) – 300 ns tHZ(DQS) DQS high-impedance time from CK/CK’ tDQSCK (Max.) – 100 ns tLZ(DQ) DQ low-impedance time from CK/CK’ tDQSCK (Min.) – (1.4×tQHS (Max.)) ns tHZ(DQ) DQ high-impedance time from CK/CK’ tDQSCK (Max.) + ns MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 33 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol tDQSQ tQHP tQHS tQH tDQSH tDQSL tQSH tQSL tMRW tMRR tRPRE tRPST tRAS tRC tRFC tRCD tRP tRRD tWR tWTR tXSR tXP tCKE Description DQS-DQ skew Data half period Data hold skew factor DQ/DQS output hold time from DQS DQS input high-level width DQS input low-level width DQS output high pulse width DQS output low pulse width MODE register Write command period MODE register Read command period Read preamble Read postamble ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period AUTO REFRESH to ACTIVE/AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period ACTIVE bank A to ACTIVE bank B delay WRITE recovery time Internal write to READ command time http://www.DataSheet4U.net/ SELF REFRESH exit to the next valid command EXIT power-down to the next valid command delay CKE min. pulse width (high & low pulse width) Min. (1.4×tDQSQ (Max.)) 0.34 Min. (tQSH, tQSL) 0.4 tQHP – tQHS 0.4 0.4 tCH – 0.05 tCL – 0.05 5 2 0.9 tCL – 0.05 3 6 Typ. 56 3 3 2 3 2 40 2 2 Max. 1.1 Unit ns tCK ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK 2.3 2.3.1 System Configuration Mode Selection Table 2-7: Mode selection of chip (PMU 6320 pin) Pin name KP_COL0 KP_ROW0 Description 0: Trigger USB download without battery 1: NA 0: Trigger USB download without battery 1: NA 2.3.1 Constant Tie Pins Table 2-8: Constant tied pins of MT6589 Pin name Description MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 34 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Pin name TESTMODE FSOURCE_P Description Test mode (tie to GND) EFUSE burning (tie to GND) 2.4 Power-on Sequence The power-on/off sequence with XTAL is shown in the following figure: VBAT DDLO UVLO PWRKEY BBWAKEUP VCORE VIO18 VA/VA28/VIO28 VAST VPROC VSRAM VM VUSB/VEMC3V3/VEMC1V8 VMC/VMCH VTCXO RESETB De-bounce time = 50ms 2ms 2ms 2ms 2ms 2ms 2ms 2ms 2ms http://www.DataSheet4U.net/ 2ms 2ms 20ms 8ms 2ms 2ms Figure 2-5: Power on/off sequence with XTAL Note that the above figure only shows one power-on/off condition with XTAL. The external PMIC MT6320 for application processor MT6589 handles the power ON and OFF of the handset. The following three different methods switch on the handset (when VBAT ≥ 3.2V): 1. Pulling PWRKEY low (The user presses PWRKEY.) 2. Pulling BBWAKEUP high 3. Valid charger plug-in Pulling PWRKEY low is a normal way to turn on the handset, which turns on regulators as long as the PWRKEY is kept low. MT6320 outputs reset signal RESETB to MT6589 SYSRSTB input. After SYSRSTB is de-asserted, the microprocessor starts and pulls BBWAKEUP high. After that PWRKEY can be released, pulling BBWAKEUP high will also turn on the handset. This is the case when the alarm in the RTC expires. MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 35 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Besides, applying a valid external supply on CHRIN will also turn on the handset. However, if the battery is in the UV state (VBAT < 3.2V), the handset cannot be turned on in any way. The UVLO function in MT6320 prevents system startup when initial voltage of the main battery is below the 3.2V threshold. When the battery voltage is bigger than 3.2V, the UVLO comparator switches and threshold are reduced to 2.9V, which allows the handset to start smoothly unless the battery decays to 2.9V and below. Once MT6320 enters the UVLO state, it draws very low quiescent current. The VRTC LDO will still be active until the DDLO disables it. VBAT DDLO UVLO PWRKEY BBWAKEUP VCORE VIO18 VA/VA28/VIO28 VAST VPROC VSRAM VM VUSB/VEMC3V3/VEMC1V8 VMC/VMCH VTCXO RESETB De-bounce time = 50ms 2ms 2ms 2ms 2ms 2ms http://www.DataSheet4U.net/ 2ms 2ms 2ms 2ms 22ms 8ms 2ms 2ms Figure 2-6: Power on/off sequence without XTAL The figure above shows the power-on/off sequence without XTAL. VTCXO is always turned on when VBAT is above the DDLO threshold. 2.5 Analog Baseband To communicate with analog blocks, a common control interface for all analog blocks is implemented. In addition, there are some dedicated interfaces for data transfer. The common control interface translates the APB bus write and read cycle for specific addresses related to analog front-end control. During the writing or reading of any of these control registers, there is a latency associated with the transfer of data to or from the analog front-end. Dedicated data interface of each analog block is implemented in the corresponding digital block. An analog block includes the following analog functions for the complete GSM/GPRS/WCDMA base-band signal processing: MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 36 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A  Base-band Rx: For I/Q channels base-band A/D conversion  Base-band Tx: For I/Q channels base-band D/A conversion and smoothing filtering.  2G base-band Tx: For the 2nd I/Q channels base-band D/A conversion and smoothing filtering.  RF control: Two DACs for automatic power control (APC) are included. Their outputs are provided to the external RF power amplifier respectively, according to the system dual-talk configuration. One more DAC for voltage bias control (VBIAS) is included for WCDMA system, and the output is provided to the external RF power amplifier.  Auxiliary ADC: Provides an ADC for the battery and other auxiliary analog functions monitoring.  Clock generation: Includes two clock-squarers for shaping the dual-talk system clock and 14 PLLs providing clock signals to base-band TRx, DSP, MCUUSB, MSDC, LVDS and HDMI units. The analog blocks include the following analog functions for complete GSM/GPRS/WCDMA baseband signal processing:  BBRX  BBTX  2GBBTX  APC-DAC  VBIAS-DAC  AUXADC  Phase locked loop http://www.DataSheet4U.net/ 2.5.1 BBRX 2.5.1.1 Block Descriptions The receiver (Rx) performs baseband I/Q channels downlink analog-to-digital conversion: 1. Analog input multiplexer: For each channel, a 2-input multiplexer is included. 2. A/D converter: 4 high performance sigma-delta ADCs perform I/Q digitization for further digital signal processing. MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 37 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A DL_I_P1 DL_I_N1 VCM1 VCM1 DL_Q_P1 DL_Q_N1 VCM1 VCM1 DL_I_P2 DL_I_N2 VCM2 VCM2 DL_Q_P2 DL_Q_N2 VCM2 VCM2 MUX MUX MUX MUX Thermometer (fS) 2's complement (fS) Main path ΔΣ 8 Modulator Encoder DOUT_I1[3:0] ΔΣ 8 Modulator Encoder CKOUT_416M_IQ1 INT_SEL_VIN_IQ1 DOUT_Q1[3:0] Diversity path (or 2nd modem) ΔΣ 8 Modulator Encoder DOUT_I2[3:0] ΔΣ 8 Modulator Encoder CKOUT_416M_IQ2 INT_SEL_VIN_IQ2 DOUT_Q2[3:0] Figure 2-7: Block diagram of BBRX-ADC http://www.DataSheet4U.net/ 2.5.1.2 Function Specifications See the table below for the function specifications of the base-band downlink receiver. Symbol VIN ICM VCM FC RIN FS VOS SIN Table 2-9: Baseband downlink specifications Parameter Min. Typ. Differential analog input voltage (peak-to-peak) Common mode input current magnitude Common mode input voltage Input clock frequency  Clock rate (DC mode)  Clock rate (SC mode & GSM mode) Input clock duty cycle 0.65 0.7 416 208 49.5 50 Input clock period jitter, DC mode Input clock period jitter, SC mode & GSM mode Differential input resistance  DC mode  SC mode & GSM mode 5.6 8 11.2 16 Output sampling rate 416/208 Differential input referred offset Signal to in-band noise  DC mode, 2.4Vpp (5.2MHz) sinewave, 400kHz ~ 72 75 4.6MHz band Max. 2.4 1 0.75 50.5 0.14 0.61 10.4 20.8 10 Unit V uA V MHz MHz % % (rms) % (rms) kΩ kΩ MSPS mV dB MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 38 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Parameter Min. Typ. Max. Unit  SC mode, 2.4Vpp (2.7MHz) sinewave, 1kHz ~ 72 75 dB 2.1MHz band  GSM mode: 2.4Vpp(570kHz) sinewave, 70kHz ~ 84 87 dB 270kHz band DVDD18 Digital power supply 1.7 1.8 1.9 V AVDD18 Analog power supply 1.7 1.8 1.9 V T Operating temperature −20 80 °C Current consumption (per channel)  Power-up  Power-down 3 mA 1 uA 2.5.2 BBTX 2.5.2.1 Block Descriptions BBTX includes two channel DACs with the 1st order low pass filter. The DACs are PMOS currentsteering topology with NMOS constant sinking current and the active RC filter performs current to voltage buffer. The bitwidth of DACs is 10-bit which is encoded into 7 bits of thermometer code and 7 binary code by mixedsys hardware. The encoded bits are timing synchronized by D-type flip-flop which is toggled by the analog local clock. The MD-PLL delivers 832MHz differential http://www.DataSheet4U.net/ clock to BBTX. A clock divider translates the 832MHz to 416MHz for DACs and AFIFO inside mixedsys. The IO power, DVDD18_MD is regulated to a voltage around 1.55V to supply analog component. The required bias currents are generated by BBRX. MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 39 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.5.2.2 Function Specifications Symbol Vocm IK Vfs N Fs Imis Gmis Vos_T Vos F3dB SLPF NOOB CN IM3 T Table 2-10: Baseband uplink transmitter http://www.DataSheet4U.net/ specifications Parameter DC output common mode voltage HF leakage current @ supply, Irms @416*2 = 832MHz DAC output swing DAC resolution Sampling clock 1-sgma DAC unit cell mismatch 3-sigma I/Q gain mismatch 3-sigma output differential DC offset over temp. 3-sigma output differential DC offset 3dB corner freq. LPF selectivity @832MHz Output noise level @45MHz Signal to noise ratio@45MHz In-band two-tone test swing V1=V2=290/sqrt(2) mV Min. 0.615 -0.2 20 28 Typ. 0.65 2100 10.0 416 25 15.1 -146 -60 Max. 0.685 3.5 1 0.2 4 10 30 30.1. -140 -56 Operating temperature Current consumption  Power-up  Power-down -20 80 4.1 10 Unit V uA mV bit MHz % dB mV mV MHz dB nVrms/sqrt(Hz) dBc/Hz dBc °C mA uA MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 40 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.5.3 2GBBTX 2.5.3.1 Block Descriptions The 2G transmitter (2GTx) performs 2G baseband I/Q channels up-link digital-to-analog conversion for dual-talk application. Each channel includes: 1. 11-bit D/A converter: Converts digital modulated signals to analog domain. The input to the DAC is sampled at 26 MHz rate with the 11-bit resolution. 2. Smoothing filter: The low-pass filter performs smoothing function for DAC output signals with a 1.8MHz 2nd-order Butterworth frequency response. UL_I_Data[10:0] DAC LPF RG_UL_Analog_PwdB RG_UL_LPF_Vcm[1:0] RG_UL_LPF_BiasAdj[1:0] RG_UL_LPF_FcAdj[7:0] UL_Q_Data[10:0] UL_Analog_CK DAC http://www.DataSheet4U.net/ Bias Gen LPF Figure 2-8: Block diagram of 2GBBTX ULIP ULIN LPF BW CAL ULQP ULQN 2.5.3.2 Function Specifications See the table below for the function specifications of the 2G base-band uplink transmitter. Symbol N FS SINAD THD VOCM DNL INL Table 2-11: Baseband uplink transmitter specifications Parameter Min. Typ. Max. Resolution 11 Sampling rate 26 Signal to noise and distortion ratio (in-band) 80 Total harmonic distortion -60 Output swing (full Swing) 0.9 1.0 1.1 Output CM voltage 1.05 1.1 1.15 Output capacitance (single-ended) 20 Output resistance (differential) 1.5 Differential nonlinearity -0.5 +0.5 Integral nonlinearity -1.0 +1.0 Unit Bit MSPS dB dB Vppd V PF KΩ LSB LSB MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 41 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol OE FCUT DVDD AVDD T Parameter Offset error (after calibration) Filter -3dB cutoff frequency (calibrated) I/Q gain mismatch Digital power supply Analog power supply Operating temperature Current consumption  Power-up  Power-down Min. 0.95 1.7 -20 Typ. +/- 1 1.8 +/- 0.2 1.05 1.8 3.6 10 Max. 1.15 1.9 80 Unit LSB MHz dB V V °C mA uA 2.5.4 APC-DAC 2.5.4.1 Block Descriptions See the figure below. APC-DAC is designed to produce a single-ended output signal at APC pin. RG_APCBUF_TRIM[3:0] APC_EN APC_BUS[9:0] APC_RSTB APC_TG RG_APC_TGSEL VBG (from bandgap) Reference buffer & bias gen. PAD_APC 10- bit DFF R-string DAC core http://www.DataSheet4U.net/ Output Buffer PA APC-DAC Figure 2-9: Block diagram of APC-DAC 2.5.4.2 Function Specifications See the table below for the function specifications of the APC-DAC. Symbol N FS SNDR TS VO,max CL DNL INL DVDD AVDD Table 2-12: APC-DAC specifications Parameter Min. Typ. Resolution Clock rate Signal-to-noise-and-distortion ratio (10kHz sine wave with 1.0V swing) Settling time (99% full-swing settling) Maximum output Output loading capacitance 10 1.0833 50 1,000 Differential nonlinearity (code 30 ~ 970) Integral nonlinearity (code 30 ~ 970) Digital power supply Analog power supply 1.0 2.0 0.9 1.0 2.6 2.8 Max. 2.1666 5 AVDD  0.2 2,200 1.1 3.0 Unit Bit MS/s dB us V pF LSB LSB V V MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 42 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol T ION IOFF Parameter Operating temperature Current consumption (power-on state) Current consumption (power-down state) Min. Typ. Max. Unit 20 85 C 300 uA 1 uA 2.5.5 VBIAS-DAC 2.5.5.1 Block Descriptions RG_VBIASBUF_TRIM[3:0] VBIAS_EN VBIAS_BUS[9:0] VBIAS_RSTB VBIAS_TG RG_VBIAS_TGSEL VBG (from bandgap) Reference buffer & bias gen. 10- bit DFF R-string DAC core Output Buffer VBIAS-DAC Figure 2-10: Block diagram of VBIAS-DAC PAD_VBIAS PA 2.5.5.2 Function Specifications http://www.DataSheet4U.net/ The functional specifications of the VBIAS-DAC are listed in the following table. Symbol N FS SNDR TS VO,max CL DNL INL DVDD AVDD T ION IOFF Table 2-13: VBIAS-DAC specifications Parameter Min. Typ. Resolution Clock rate Signal-to-noise-and-distortion ratio (10KHz sine wave with 1.0V swing) Settling time (99% full-swing settling) 10 1.0833 50 Maximum output Output loading capacitance 1000 Differential nonlinearity (code 20 ~ 970) 1.0 Integral nonlinearity (code 20 ~ 970) Digital power supply Analog power supply 2.0 0.9 1.0 2.6 2.8 Operating temperature Current consumption (power-on state) Current consumption (power-down state) 20 300 Max. 2.1666 5 AVDD  0.2 1.1 3.0 85 1 Unit Bit MS/s dB us V pF LSB LSB V V C uA uA MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 43 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.5.6 AUXADC 2.5.6.1 Block Descriptions Auxiliary ADC measures ADC and is the resistive touch panel controller. The auxiliary ADC includes the following functional blocks: 1. Analog multiplexer: Selects signal from one of the auxiliary input channels. There are 16 input channels of AUXADC. Some are for internal voltage measuring and some for external voltage measuring. Environmental messages to be monitored, e.g. temperature, should be transferred to the voltage domain. 2. 12-bit A/D converter: Converts the multiplexed input signal to 12-bit digital data. The touch screen controller drives the external touch panel via Pads XP, XM, YP and YM, and AUXADC as a voltage meter, obtains the X/Y-position of the touched point on the external touch screen. The touch screen interface contains 3 main blocks, which are touch screen pads control logic, ADC interface logic and interrupt generation logic. The touch screen interface supports 2 conversion modes, separate X/Y position conversion mode and auto (sequential) X/Y position conversion mode. See Table 2-14: Definitions of AUXADC channels for brief descriptions of AUXADC input channels. AVDD AVDD http://www.DataSheet4U.net/ Pen Interrupt PAD_XP PAD_YP PAD_XM PAD_YM S/H PAD_AUXIN<4:0> 5 VRB VRT ADC DO<11:0> Digital Controller MUX Figure 2-11: Block diagram of AUXADC Table 2-14: Definitions of AUXADC channels AUXADC channel ID Description Channel 0 Channel 1 External use (AUX_IN0) External use (AUX_IN1) Channel 2 Optional external use (AUX_IN2) MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 44 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A AUXADC channel ID Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Description Optional external use (AUX_IN3) Optional external use (AUX_IN4) NA NA NA NA NA NA NA XM (touch panel) XP (touch panel) YP (touch panel) YM (touch panel) 2.5.6.2 Function Specifications See the table below for the function specifications of auxiliary ADC. Symbol N FC FS CIN RIN DNL INL OE FSE SINAD DVDD AVDD T Ztp Table 2-15: AUXADC specifications Parameter Resolution http://www.DataSheet4U.net/ Clock rate Sampling rate @ N-Bit Input swing Input capacitance Unselected channel Selected channel Input resistance Unselected channel Clock latency Differential nonlinearity Integral nonlinearity Offset error Full swing error Signal to noise and distortion ratio (10kHz full swing input & 1.0833MHz clock rate) Digital power supply Analog power supply Operating temperature Current consumption  Power-up  Power-down Supports touch panel impedance Min. 0 400 62 1.0 1.75 -20 200 Typ. 12 4 4/(N+4) 50 4 N+4 +1.0/-1.0 +1.0/-1.0 +/- 5 +/- 5 68 1.1 1.8 250 1 Max. AVDD 1.2 1.85 80 2K Unit Bit MHz MSPS V fF pF MΩ 1/FC LSB LSB mV mV dB V V °C uA uA Ω MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 45 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.5.7 Clock Squarer 2.5.7.1 Block Descriptions For most VCXO, the output clock waveform is sinusoidal with too small amplitude (about several hundred mV) to make MT6589 digital circuits function well. Clock squarer is designed to convert such a small signal to a rail-to-rail clock signal with excellent duty-cycle. 2.5.7.2 Function Specifications See the table below for the function specifications of clock squarer. Symbol Fin Fout Vin DcycIN DcycOUT TR TF DVDD AVDD T Table 2-16: Clock squarer 1 & 2 specifications Parameter Input clock frequency Output clock frequency Input signal amplitude Input signal duty cycle Output signal duty cycle Rise time on pin CLKSQOUT Fall time on pin CLKSQOUT Digital power supply Analog power supply Operating temperature Min. 13 13 350 DcycIN-5 Typ. 26 26 500 50 http://www.DataSheet4U.net/ 1.0 1.7 -20 1.1 1.8 Current consumption 500 Max. 1,000 DcycIN+5 5 5 1.2 1.9 80 Unit MHz MHz mVpp % % ns/pF ns/pF V V ℃ uA 2.5.8 Phase Locked Loop 2.5.8.1 Block Descriptions There are total 14 PLLs in PLL macro, providing several clocks for CPU, BUS, modem, analog modem, MSDC, LVDS, HDMI and image-sensor. ARMPLL provides around 1.2GHz clock for ARM Cortex-A15. MAINPLL provides around 806MHz clock for bus and most of the function modules. MMPLL provides around 286MHz clock for VENC and MFG. ISPPLL is the clock source of image sense processing, which ranges from 104 to 208MHz for supporting various image sensors. UNIVPLL provides 48MHz for USBPHY. MSDCPLL provides around 208MHz as the clock source of MSDC module. TVDPLL provides 27/54/148.5MHz clock for the TV encoder and HDMI bridge. LVDSPLL provides 20 ~ 75MHz clock for LVDS bridge and DPI interface. MDPLL1 and MDPLL2 are the main clock source of dual-talk modem, providing a fixed 416MHz from different clock squarers for further clock division. WPLL is a fractional PLL which multiplies clock 26MHz to 245.76MHz for HSPA. WHPLL provides a fixed 250.25MHz for 3G HSPA. MCUPLL1 and MCUPLL2 provide around 481MHz for ARM Cortex-R4, FD216 and bus. MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 46 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A MT6589 MDPLL1 CLKSQ1 PAD_CLK26M_1 CLKSQ 26MHz /M External of PLL RG_CLKSQ1_EN Bias / LDO MDPLL1 MD_PLL (832MHz) /M Internal of PLL /M Analog Special Divider AD_SYS_26M_CK AD_MDSYS1_26M_CK AD_MEM_26M_CK AD_MIPI_26M_CK PAD_CLK26M_2 RG_CLKSQ2_EN MT6589 MDPLL2 CLKSQ2 CLKSQ 26MHz Bias / LDO MDPLL2 /2 AD_MDPLL1_416M_CK MD_PLL (832MHz) AD_MDSYS2_26M_CK /2 AD_MDPLL2_416M_CK MT6589 PLLGP Bias / LDO To BBTRX NS_MD832M_CKP NS_MD832M_CKN QS_MD832M_VSS WPLL MODEM SDM_PLL /4 /2 (1966.08MHz) Test CKT WHPLL /4 LC_INT_PLL /4 (1001MHz) + MCUPLL1 SDM_PLL /4 (Hop 1924MHz) AD_WPLL_245P76M_CK AD_WHPLL_250P25M_CK AD_MCU1_H481M_CK DA_CPU_CK_MON UNIVPLL /2 /3 LC_INT_PLL /5 (1248MHz) /7 /26 MAINPLL /2 SDM_PLL /1 (Hop 1612MHz) /3 /5 /7 ARMPLL SDM_PLL /1 (Hop 1300MHz) MMPLL /2 LC_INT_PLL /3 (1430MHz) /5 /7 MSDCPLL SDM_PLL /4 /2 (Hop 1664MHz) TVDPLL /2 SDM_PLL /4 (Hop 2376MHz) /4 /8 /16 LVDSPLL SDM_PLL /4 /2 (Hop 1440MHz) AD_UNIV_624M_CK AD_UNIV_416M_CK AD_UNIV_249P6M_CK AD_UNIV_178P3M_CK AD_UNIV_48M_CK AD_USB_48M_CK AD_MAIN_H806M_CK AD_MAIN_H537P3M_CK AD_MAIN_H322P4M_CK AD_MAIN_H230P3M_CK AD_ARM_H1300M_CK AD_MM_DIV2_CK AD_MM_DIV3_CK AD_MM_DIV5_CK AD_MM_DIV7_CK AD_MSDC_H208M_CK http://www.DataSheet4U.net/ AD_TVD_H148P5M_CK AD_LVDS_H180M_CK To BBTRX NS_MD832M_CKP NS_MD832M_CKN QS_MD832M_VSS MCUPLL2 MODEM SDM_PLL /4 /2 (Hop 1924MHz) AD_MCU2_H481M_CK ISPPLL LC_INT_PLL /4 (1664MHz) 125MHz ~ 312.5MHz /2 AD_ISP_208M_CK Back-up for special sensor Figure 2-12: Block diagram of PLL 2.5.8.2 Function Specifications See the table below for the function specifications of PLL. Symbol Fin Fout DVDD Table 2-17: ARMPLL specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Min. Typ. 26 754 20 47 50 30 0.95 1.05 Max. 1,508 53 1.15 Unit MHz MHz us % ps V MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 47 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Parameter AVDD Analog power supply T Operating temperature Current consumption Power-down current consumption Min. Typ. 1.7 1.8 -20 1.2 Symbol Fin Fout DVDD AVDD T Table 2-18: MAINPLL specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. 500 47 0.95 1.7 -20 Typ. 26 806 20 50 60 1.05 1.8 0.8 Symbol Fin Fout DVDD AVDD T Table 2-19: MMPLL specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption http://www.DataSheet4U.net/ Min. 47 0.95 1.7 -20 Typ. 26 286 20 50 60 1.05 1.8 0.8 Max. 1.9 80 1 Max. 884 53 1.15 1.9 80 1 Max. 338 53 1.15 1.9 80 1 Unit V °C mA uA Unit MHz MHz us % ps V V °C mA uA Unit MHz MHz us % ps V V °C mA uA Symbol Fin Fout DVDD AVDD T Table 2-20: ISPPLL specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Min. Typ. 26 104 20 47 50 60 0.95 1.05 1.7 1.8 -20 Max. 208 53 1.15 1.9 80 Unit MHz MHz us % ps V V °C MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 48 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Parameter Current consumption Power-down current consumption Min. Typ. 0.8 Symbol Fin Fout DVDD AVDD T Table 2-21: UNIVPLL specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. Typ. 26 N/A 624 20 45 50 60 0.95 1.05 1.7 1.8 -20 0.8 Max. 1 Max. N/A 55 1.15 1.9 80 1 Unit mA uA Unit MHz MHz us % ps V V °C mA uA Symbol Fin Fout DVDD AVDD T Table 2-22: MSDCPLL specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. http://www.DataSheet4U.net/ 45 0.95 1.7 -20 Typ. 26 208 20 50 60 1.05 1.8 0.8 Max. 55 1.15 1.9 80 1 Unit MHz MHz us % ps V V °C mA uA Symbol Fin Fout DVDD AVDD T Table 2-23: TVDPLL specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. 45 0.95 1.7 -20 Typ. 26 148.5 20 50 60 1.05 1.8 0.8 Max. 55 1.15 1.9 80 1 Unit MHz MHz us % ps V V °C mA uA MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 49 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Fin Fout DVDD AVDD T Table 2-24: LVDSPLL specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. Typ. 26 75 20 45 50 60 0.95 1.05 1.7 1.8 -20 0.8 Max. 55 1.15 1.9 80 1 Unit MHz MHz us % ps V V °C mA uA Symbol Fin Fout DVDD AVDD T Table 2-25: MDPLL1 & MDPLL2 specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. N/A 47 http://www.DataSheet4U.net/ 0.95 1.7 -20 Typ. 26 416 100 50 30 1.05 1.8 2.5 Symbol Fin Fout DVDD AVDD T Table 2-26: WPLL specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. N/A 47 0.95 1.7 -20 Typ. 26 245.76 20 50 60 1.05 1.8 0.8 Max. N/A 53 1.15 1.9 80 1 Max. N/A 53 1.15 1.9 80 1 Unit MHz MHz us % ps V V °C mA uA Unit MHz MHz us % ps V V °C mA uA Table 2-27: WHPLL specifications Symbol Parameter Fin Input clock frequency Min. Typ. 26 Max. Unit MHz MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 50 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A Symbol Fout DVDD AVDD T Parameter Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. N/A 47 0.95 1.7 -20 Typ. 250.25 20 50 60 1.05 1.8 0.8 Max. N/A 53 1.15 1.9 80 1 Symbol Fin Fout DVDD AVDD T Table 2-28: MCUPLL1 & MCUPLL2 specifications Parameter Input clock frequency Output clock frequency Settling time Output clock duty cycle Output clock jitter (period jitter) Digital power supply Analog power supply Operating temperature Current consumption Power-down current consumption Min. 47 0.95 1.7 -20 http://www.DataSheet4U.net/ Typ. 26 481 20 50 60 1.05 1.8 2 Max. 53 1.15 1.9 80 1 Unit MHz us % ps V V °C mA uA Unit MHz MHz us % ps V V °C mA uA 2.5.9 Temperature Sensor 2.5.9.1 Block Descriptions In order to monitor the temperature of CPUs, several temperature sensors are provided. The temperature sensor is made of substrate BJT in the CMOS process. The voltage output of temperature sensor is measured by AUXADC. 2.5.9.2 Function Specifications See the table below for the function specifications of temperature sensor. Table 2-29: Temperature sensor specifications Symbol Parameter Resolution Temperature range Accuracy Active current Quiescent current Min. Typ. Max. Unit 0.15 °C 0 85 °C -5 5 °C 300 uA 3 uA MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 51 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.6 2.6.1 Package Information Package Outlines http://www.DataSheet4U.net/ Figure 2-13: Outlines and dimensions of FCCSP 11.8mm*11.8mm, 515-ball, 0.4mm pitch package 2.6.2 Thermal Operating Specifications Symbol Table 2-30: Thermal operating specifications Description Maximum operating junction temperature Package thermal resistances in nature convection Value 125 29.55 Unit °C °C/Watt Notes 2.6.3 Lead-free Packaging MT6589 is provided in a lead-free package and meets RoHS requirements. MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 52 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX MT6589 HSPA+ Smartphone Application Processor Technical Brief Confidential A 2.7 2.7.1 Ordering Information Top Marking Definition MT6589 %K DDDD - #### LLLLL MTXXXXXX %: DDDD: ####: LLLLL: S: Part No. W : WCDMA T : TD-SCDMA E : Edge Date Code Subcontractor Code Die Lot No. Special Code Figure 2-14: Top mark of MT6589 http://www.DataSheet4U.net/ MediaTek Confidential © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. Page 53 of 53 datasheet pdf - http://www.DataSheet4U.net/ loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX

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