首页资源分类嵌入式处理器MSP430 > msp430f449

msp430f449

已有 445042个资源

下载专区

上传者其他资源

文档信息举报收藏

标    签:430mspTI

分    享:

文档简介

英文原版的文档,十分实用,。

文档预览

MSP430x4xx Family User’s Guide April 2013 SLAU056L Related Documentation From Texas Instruments Preface Read This First About This Manual This manual discusses modules and peripherals of the MSP430x4xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family. Pin functions, internal signal connections and operational parameters differ from device to device. The user should consult the device-specific data sheet for these details. Related Documentation From Texas Instruments For related documentation see the web site http://www.ti.com/msp430. FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Notational Conventions Program examples, are shown in a special typeface. iii Glossary Glossary ACLK Auxiliary Clock See Basic Clock Module ADC Analog-to-Digital Converter BOR Brown-Out Reset See System Resets, Interrupts, and Operating Modes BSL Bootstrap Loader See www.ti.com/msp430 for application reports CPU Central Processing Unit See RISC 16-Bit CPU DAC Digital-to-Analog Converter DCO Digitally Controlled Oscillator See FLL+ Module dst Destination See RISC 16-Bit CPU FLL Frequency Locked Loop See FLL+ Module GIE General Interrupt Enable See System Resets Interrupts and Operating Modes INT(N/2) Integer portion of N/2 I/O Input/Output See Digital I/O ISR Interrupt Service Routine LSB Least-Significant Bit LSD Least-Significant Digit LPM Low-Power Mode See System Resets Interrupts and Operating Modes MAB Memory Address Bus MCLK Master Clock See FLL+ Module MDB Memory Data Bus MSB Most-Significant Bit MSD Most-Significant Digit NMI (Non)-Maskable Interrupt See System Resets Interrupts and Operating Modes PC Program Counter See RISC 16-Bit CPU POR Power-On Reset See System Resets Interrupts and Operating Modes PUC Power-Up Clear See System Resets Interrupts and Operating Modes RAM Random Access Memory SCG System Clock Generator See System Resets Interrupts and Operating Modes SFR Special Function Register SMCLK Sub-System Master Clock See FLL+ Module SP Stack Pointer See RISC 16-Bit CPU SR Status Register See RISC 16-Bit CPU src Source See RISC 16-Bit CPU TOS Top-of-Stack See RISC 16-Bit CPU WDT Watchdog Timer See Watchdog Timer iv Register Bit Conventions Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition Key Bit Accessibility rw Read/write r Read only r0 Read as 0 r1 Read as 1 w Write only w0 Write as 0 w1 Write as 1 (w) No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0. h0 Cleared by hardware h1 Set by hardware −0,−1 Condition after PUC −(0),−(1) Condition after POR v vi Contents &RQWHQWV 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Flexible Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 Embedded Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4.1 Flash/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.3 Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.4 Special Function Registers (SFRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.5 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 2 System Resets, Interrupts, and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 System Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 Brownout Reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.2 Device Initial Conditions After System Reset . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.1 (Non)-Maskable Interrupts (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.2 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.3 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.4 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.5 Special Function Registers (SFRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.1 Entering and Exiting Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.4 Principles for Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5 Connection of Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 vii Contents 3 RISC 16-Bit CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 CPU Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.1 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.2 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.3 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.4 Constant Generator Registers CG1 and CG2 . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.5 General-Purpose Registers R4 to R15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.3.1 Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.3.2 Indexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.3.3 Symbolic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.3.4 Absolute Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.3.5 Indirect Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.3.6 Indirect Autoincrement Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.3.7 Immediate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.4.1 Double-Operand (Format I) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.4.2 Single-Operand (Format II) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.4.3 Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.4.4 Instruction Cycles and Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72 3.4.5 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 4 16-Bit MSP430X CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 CPU Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.1 The Program Counter PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.3 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.3.4 The Constant Generator Registers CG1 and CG2 . . . . . . . . . . . . . . . . . . . 4-11 4.3.5 The General Purpose Registers R4 to R15 . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.4.1 Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.4.2 Indexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.4.3 Symbolic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4.4.4 Absolute Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 4.4.5 Indirect Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4.4.6 Indirect, Autoincrement Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 4.4.7 Immediate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 4.5 MSP430 and MSP430X Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 4.5.1 MSP430 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 4.5.2 MSP430X Extended Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 4.6 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58 4.6.1 Extended Instruction Binary Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59 4.6.2 MSP430 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 4.6.3 Extended Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-113 4.6.4 Address Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-156 viii Contents 5 FLL+ Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 FLL+ Clock Module Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 FLL+ Clock Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.2.1 FLL+ Clock features for Low-Power Applications . . . . . . . . . . . . . . . . . . . . 5-8 5.2.2 Internal Very Low-Power, Low-Frequency Oscillator . . . . . . . . . . . . . . . . . . 5-9 5.2.3 LFXT1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.2.4 XT2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.2.5 Digitally Controlled Oscillator (DCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.2.6 Frequency Locked Loop (FLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.2.7 DCO Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.2.8 Disabling the FLL Hardware and Modulator . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.2.9 FLL Operation from Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.2.10 Buffered Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.2.11 FLL+ Fail-Safe Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.3 FLL+ Clock Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 6 Flash Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 Flash Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Flash Memory Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.1 SegmentA on MSP430FG47x, MSP430F47x, MSP430F47x3/4, and MSP430F471xx Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3 Flash Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.3.1 Flash Memory Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.3.2 Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.3.3 Writing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.4 Flash Memory Access During Write or Erase . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.3.5 Stopping a Write or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.3.6 Marginal Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.3.7 Configuring and Accessing the Flash Memory Controller . . . . . . . . . . . . . . 6-18 6.3.8 Flash Memory Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.3.9 Programming Flash Memory Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.4 Flash Memory Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 7 Supply Voltage Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1 SVS Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2 SVS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1 Configuring the SVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.2 SVS Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.3 Changing the VLDx Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.4 SVS Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3 SVS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 8 16-Bit Hardware Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1 Hardware Multiplier Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1 Operand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.2 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.3 Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.2.4 Indirect Addressing of RESLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.5 Using Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.3 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 ix Contents 9 32-Bit Hardware Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1 32-Bit Hardware Multiplier Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 32-Bit Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2.1 Operand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.2.2 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.2.3 Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.2.4 Fractional Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.2.5 Putting It All Together . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.2.6 Indirect Addressing of Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.2.7 Using Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.2.8 Using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.3 32-Bit Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 10 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1 DMA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2.1 DMA Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2.2 DMA Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.2.3 Initiating DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10.2.4 Stopping DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10.2.5 DMA Channel Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10.2.6 DMA Transfer Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10.2.7 Using DMA with System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10.2.8 DMA Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10.2.9 DMAIV, DMA Interrupt Vector Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10.2.10 Using the USCI_B I2C Module with the DMA Controller . . . . . . . . . . . . . . 10-19 10.2.11 Using ADC12 with the DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10.2.12 Using DAC12 With the DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10.2.13 Using SD16 or SD16_A With the DMA Controller . . . . . . . . . . . . . . . . . . . . 10-20 10.2.14 Writing to Flash With the DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.3 DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 11 Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 Digital I/O Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 Digital I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.1 Input Register PxIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.2 Output Registers PxOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.3 Direction Registers PxDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.4 Pullup/Pulldown Resistor Enable Registers PxREN (MSP430F47x3/4 and MSP430F471xx only) . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.5 Function Select Registers PxSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.6 P1 and P2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.7 Configuring Unused Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3 Digital I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 x Contents 12 Watchdog Timer, Watchdog Timer+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1 Watchdog Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.1 Watchdog Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.2 Watchdog Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.3 Interval Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.4 Watchdog Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.2.5 WDT+ Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.2.6 Operation in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.2.7 Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.3 Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 13 Basic Timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1 Basic Timer1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 Basic Timer1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2.1 Basic Timer1 Counter One . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2.2 Basic Timer1 Counter Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2.3 16-Bit Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2.4 Basic Timer1 Operation: Signal fLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.2.5 Basic Timer1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3 Basic Timer1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 14 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1 RTC Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 Real-Time Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.2.1 Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.2.2 Calendar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.2.3 RTC and Basic Timer1 Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.2.4 Real-Time Clock Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.3 Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 15 Timer_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1 Timer_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 Timer_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.1 16-Bit Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2 Starting the Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.2.3 Timer Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.2.4 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 15.2.5 Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.2.6 Timer_A Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.3 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 xi Contents 16 Timer_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1 Timer_B Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.1.1 Similarities and Differences From Timer_A . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 Timer_B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.2.1 16-Bit Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.2.2 Starting the Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.2.3 Timer Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.2.4 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.2.5 Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.2.6 Timer_B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 16.3 Timer_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 17 USART Peripheral Interface, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1 USART Introduction: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2 USART Operation: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.1 USART Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2 Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.3 Asynchronous Communication Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.2.4 USART Receive Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.2.5 USART Transmit Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17.2.6 USART Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.2.7 USART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17 17.3 USART Registers: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 18 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1 USART Introduction: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.2 USART Operation: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.2.1 USART Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.2.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.2.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.2.4 SPI Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.2.5 Serial Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 18.2.6 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 18.3 USART Registers: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13 xii Contents 19 Universal Serial Communication Interface, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1 USCI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2 USCI Introduction: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.3 USCI Operation: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.3.1 USCI Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.3.2 Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.3.3 Asynchronous Communication Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.3.4 Automatic Baud Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.3.5 IrDA Encoding and Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 19.3.6 Automatic Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.3.7 USCI Receive Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 19.3.8 Receive Data Glitch Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 19.3.9 USCI Transmit Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 19.3.10 UART Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 19.3.11 Setting a Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 19.3.12 Transmit Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 19.3.13 Receive Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 19.3.14 Typical Baud Rates and Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21 19.3.15 Using the USCI Module in UART Mode with Low-Power Modes . . . . . . . 19-25 19.3.16 USCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.4 USCI Registers: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 20 Universal Serial Communication Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1 USCI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.2 USCI Introduction: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3 USCI Operation: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.3.1 USCI Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.3.2 Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.3.3 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.3.4 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.3.5 SPI Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 20.3.6 Serial Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 20.3.7 Using the SPI Mode with Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . 20-12 20.3.8 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 20.4 USCI Registers: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 21 Universal Serial Communication Interface, I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1 USCI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.2 USCI Introduction: I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.3 USCI Operation: I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.3.1 USCI Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 21.3.2 I2C Serial Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.3.3 I2C Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3.4 I2C Module Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.3.5 I2C Clock Generation and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 21-22 21.3.6 Using the USCI Module in I2C Mode With Low-Power Modes . . . . . . . . . 21-23 21.3.7 USCI Interrupts in I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24 21.4 USCI Registers: I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 xiii Contents 22 OA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1 OA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2 OA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.2.1 OA Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.2.2 OA Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.2.3 OA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.2.4 OA Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.3 OA Modules in MSP430FG42x0 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.3.1 OA Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 22.3.2 OA Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 22.3.3 OA Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 22.3.4 OA Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 22.3.5 Switch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14 22.3.6 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 22.4 OA Modules in MSP430FG47x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16 22.4.1 OA Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18 22.4.2 OA Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18 22.4.3 OA Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18 22.4.4 OA Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18 22.4.5 Switch Control of the FG47x devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 22.4.6 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 22.5 OA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.6 OA Registers in MSP430FG42x0 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27 22.7 OA Registers in MSP430FG47x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-31 23 Comparator_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1 Comparator_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.2 Comparator_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.2.1 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.2.2 Input Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.2.3 Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.2.4 Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.2.5 Comparator_A, Port Disable Register CAPD . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.6 Comparator_A Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.7 Comparator_A Used to Measure Resistive Elements . . . . . . . . . . . . . . . . . 23-7 23.3 Comparator_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 24 Comparator_A+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1 Comparator_A+ Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.2 Comparator_A+ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.1 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.2 Input Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.3 Input Short Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.4 Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.2.5 Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.2.6 Comparator_A+, Port Disable Register CAPD . . . . . . . . . . . . . . . . . . . . . . . 24-7 24.2.7 Comparator_A+ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 24.2.8 Comparator_A+ Used to Measure Resistive Elements . . . . . . . . . . . . . . . . 24-8 24.3 Comparator_A+ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10 xiv Contents 25 LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1 LCD Controller Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.2 LCD Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.1 LCD Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.2 Blinking the LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.3 LCD Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.4 LCD Voltage Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.2.5 LCD Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.2.6 Static Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.2.7 2-Mux Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.2.8 3-Mux Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.2.9 4-Mux Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.3 LCD Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18 26 LCD_A Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1 LCD_A Controller Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.2 LCD_A Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.2.1 LCD Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.2.2 Blinking the LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.2.3 LCD_A Voltage And Bias Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.2.4 LCD Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.2.5 LCD Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.2.6 Static Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9 26.2.7 2-Mux Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12 26.2.8 3-Mux Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15 26.2.9 4-Mux Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18 26.3 LCD Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21 27 ADC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.1 ADC10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.2 ADC10 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.2.1 10-Bit ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.2.2 ADC10 Inputs and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.2.3 Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.2.4 Auto Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.2.5 Sample and Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.2.6 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.2.7 ADC10 Data Transfer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-15 27.2.8 Using the Integrated Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 27-21 27.2.9 ADC10 Grounding and Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . 27-22 27.2.10 ADC10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-23 27.3 ADC10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-24 xv Contents 28 ADC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1 ADC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.2 ADC12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.2.1 12-Bit ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.2.2 ADC12 Inputs and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.2.3 Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.2.4 Auto Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.2.5 Sample and Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.2.6 Conversion Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10 28.2.7 ADC12 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10 28.2.8 Using the Integrated Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 28-16 28.2.9 ADC12 Grounding and Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . 28-17 28.2.10 ADC12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18 28.3 ADC12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20 29 SD16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1 SD16 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.2 SD16 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.2.1 ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.2.2 Analog Input Range and PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.2.3 Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.2.4 Auto Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.2.5 Analog Input Pair Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5 29.2.6 Analog Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.2.7 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.2.8 Conversion Memory Registers: SD16MEMx . . . . . . . . . . . . . . . . . . . . . . . . 29-10 29.2.9 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 29.2.10 Conversion Operation Using Preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14 29.2.11 Using the Integrated Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 29-16 29.2.12 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-17 29.3 SD16 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19 30 SD16_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.1 SD16_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.2 SD16_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2.1 ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2.2 Analog Input Range and PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2.3 Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2.4 Auto Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2.5 Analog Input Pair Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.6 Analog Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.2.7 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.2.8 Conversion Memory Register: SD16MEMx . . . . . . . . . . . . . . . . . . . . . . . . . 30-12 30.2.9 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-14 30.2.10 Conversion Operation Using Preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17 30.2.11 Using the Integrated Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.2.12 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20 30.3 SD16_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22 xvi Contents 31 DAC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.1 DAC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.2 DAC12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.2.1 DAC12 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.2.2 DAC12 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.2.3 Updating the DAC12 Voltage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.2.4 DAC12_xDAT Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.2.5 DAC12 Output Amplifier Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10 31.2.6 Grouping Multiple DAC12 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11 31.2.7 DAC12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 31.3 DAC12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13 32 Scan IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.1 Scan IF Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.2 Scan IF Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.2.1 Scan IF Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.2.2 Scan IF Timing State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-14 32.2.3 Scan IF Processing State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-20 32.2.4 Scan IF Debug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-26 32.2.5 Scan IF Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-27 32.2.6 Using the Scan IF with LC Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-28 32.2.7 Using the Scan IF With Resistive Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . 32-32 32.2.8 Quadrature Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-33 32.3 Scan IF Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-35 33 Embedded Emulation Module (EEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.1 EEM Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.2 EEM Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.2.1 Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.2.2 Trigger Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5 33.2.3 State Storage (Internal Trace Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5 33.2.4 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5 33.3 EEM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6 xvii xviii Chapter 1 Introduction This chapter describes the architecture of the MSP430. Topic Page 1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Flexible Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 Embedded Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Introduction 1-1 Architecture 1.1 Architecture The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von Neumann common memory address bus (MAB) and memory data bus (MDB). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x4xx family include: - Ultralow-power architecture extends battery life J 0.1-μA RAM retention J 0.8-μA real-time clock mode J 250-μA / MIPS active - High-performance analog ideal for precision measurement J 12-bit or 10-bit ADC — 200 ksps, temperature sensor, VRef J 12-bit dual DAC J Comparator-gated timers for measuring resistive elements J Supply voltage supervisor - 16-bit RISC CPU enables new applications at a fraction of the code size. J Large register file eliminates working file bottleneck J Compact core design reduces power consumption and cost J Optimized for modern high-level programming J Only 27 core instructions and seven addressing modes J Extensive vectored-interrupt capability - In-system programmable Flash permits flexible code changes, field upgrades, and data logging 1.2 Flexible Clock System The clock system is designed specifically for battery-powered applications. A low-frequency auxiliary clock (ACLK) is driven directly from a common 32-kHz watch crystal. The ACLK can be used for a background real-time clock self wake-up function. An integrated high-speed digitally controlled oscillator (DCO) can source the master clock (MCLK) used by the CPU and high-speed peripherals. By design, the DCO is active and stable in less than 6 μs. MSP430-based solutions effectively use the high-performance 16-bit RISC CPU in very short bursts. - Low-frequency auxiliary clock = Ultralow-power standby mode - High-speed master clock = High performance signal processing 1-2 Introduction Figure 1−1. MSP430 Architecture Embedded Emulation Clock System ACLK SMCLK Flash/ ROM MCLK RAM Peripheral Peripheral Peripheral JTAG/Debug RISC CPU 16-Bit MAB 16-Bit JTAG MDB 16-Bit Bus Conv. MDB 8-Bit ACLK SMCLK Watchdog Peripheral Peripheral Peripheral Peripheral 1.3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources. The benefits of embedded emulation include: - Unobtrusive development and debug with full-speed execution, breakpoints, and single steps in an application are supported. - Development is in-system and subject to the same characteristics as the final application. - Mixed-signal integrity is preserved and not subject to cabling interference. Introduction 1-3 Address Space 1.4 Address Space The MSP430 von Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1−2. See the device-specific data sheets for specific memory maps. Code access are always performed on even addresses. Data can be accessed as bytes or words. The addressable memory space is 128 KB with future expansion planned. Figure 1−2. Memory Map Access 10000h 0FFFFh 0FFE0h 0FFDFh Flash/ROM Interrupt Vector Table Flash/ROM Word/Byte Word/Byte Word/Byte 0200h 01FFh 0100h 0FFh 010h 0Fh 0h RAM 16-Bit Peripheral Modules 8-Bit Peripheral Modules Special Function Registers Word/Byte Word Byte Byte 1.4.1 Flash/ROM The start address of Flash/ROM depends on the amount of Flash/ROM present and varies by device. The end address for Flash/ROM is 0FFFFh for devices with less than 60kB of Flash/ROM; otherwise, it is device dependent. Flash can be used for both code and data. Word or byte tables can be stored and used in Flash/ROM without the need to copy the tables to RAM before using them. The interrupt vector table is mapped into the upper 16 words of Flash/ROM address space, with the highest priority interrupt vector at the highest Flash/ROM word address (0FFFEh). 1-4 Introduction 1.4.2 RAM Address Space RAM starts at 0200h. The end address of RAM depends on the amount of RAM present and varies by device. RAM can be used for both code and data. 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules should be accessed with word instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always 0. The address space from 010h to 0FFh is reserved for 8-bit peripheral modules. These modules should be accessed with byte instructions. Read access of byte modules using word instructions results in unpredictable data in the high byte. If word data is written to a byte module only the low byte is written into the peripheral register, ignoring the high byte. 1.4.4 Special Function Registers (SFRs) Some peripheral functions are configured in the SFRs. The SFRs are located in the lower 16 bytes of the address space and are organized by byte. SFRs must be accessed using byte instructions only. See the device-specific data sheets for applicable SFR bits. 1.4.5 Memory Organization Bytes are located at even or odd addresses. Words are only located at even addresses as shown in Figure 1−3. When using word instructions, only even addresses may be used. The low byte of a word is always an even address. The high byte is at the next odd address. For example, if a data word is located at address xxx4h, then the low byte of that data word is located at address xxx4h, and the high byte of that word is located at address xxx5h. Introduction 1-5 Address Space Figure 1−3. Bits, Bytes, and Words in a Byte-Organized Memory xxxAh 15 14 . . Bits . . 9 8 xxx9h 7 6 . . Bits . . 1 0 xxx8h Byte Byte xxx7h xxx6h Word (High Byte) Word (Low Byte) xxx5h xxx4h xxx3h 1-6 Introduction Chapter 2 System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x4xx system resets, interrupts, and operating modes. Topic Page 2.1 System Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.4 Principles for Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5 Connection of Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 System Resets, Interrupts, and Operating Modes 2-1 System Reset and Initialization 2.1 System Reset and Initialization The system reset circuitry shown in Figure 2−1 sources both a power-on reset (POR) and a power-up clear (PUC) signal. Different events trigger these reset signals and different initial conditions exist depending on which signal was generated. Figure 2−1. Power-On Reset and Power-Up Clear Schematic VCC Brownout Reset 0V SVS_POR RST/NMI WDTNMI† WDTTMSEL† WDTQn† WDTIFG† ~ 50us Resetwd1 EQU† KEYV (from flash module) Resetwd2 † From watchdog timer peripheral module POR S Latch R Delay S S PUC S Latch S R MCLK POR PUC A POR is a device reset. A POR is only generated by the following three events: - Powering up the device - A low signal on the RST/NMI pin when configured in the reset mode - An SVS low condition when PORON = 1. A PUC is always generated when a POR is generated, but a POR is not generated by a PUC. The following events trigger a PUC: - A POR signal - Watchdog timer expiration when in watchdog mode only - Watchdog timer security key violation - A Flash memory security key violation 2-2 System Resets, Interrupts, and Operating Modes System Reset and Initialization 2.1.1 Brownout Reset (BOR) All MSP430x4xx devices have a brownout reset circuit. The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the VCC terminal. The brownout reset circuit resets the device by triggering a POR signal when power is applied or removed. The operating levels are shown in Figure 2−2. The POR signal becomes active when VCC crosses the VCC(start) level. It remains active until VCC crosses the V(B_IT+) threshold and the delay t(BOR) elapses. The delay t(BOR) is adaptive being longer for a slow ramping VCC. The hysteresis Vhys(B_ IT−) ensures that the supply voltage must drop below V(B_IT−) to generate another POR signal from the brownout reset circuitry. Figure 2−2. Brownout Timing V(B_IT+) V(B_IT−) V hys(B_IT−) VCC(start) VCC Set Signal for POR circuitry t(BOR) As the V(B_IT−) level is significantly above the V(MIN) level of the POR circuit, the BOR provides a reset for power failures where VCC does not fall below V(MIN). See the device-specific data sheet for parameters. System Resets, Interrupts, and Operating Modes 2-3 System Reset and Initialization 2.1.2 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: - The RST/NMI pin is configured in the reset mode. - I/O pins are switched to input mode as described in the Digital I/O chapter. - Other peripheral modules and registers are initialized as described in their respective chapters in this manual. - Status register (SR) is reset. - The watchdog timer powers up active in watchdog mode. - Program counter (PC) is loaded with address contained at reset vector location (0FFFEh). CPU execution begins at that address. Software Initialization After a system reset, user software must initialize the MSP430 for the application requirements. The following must occur: - Initialize the SP, typically to the top of RAM. - Initialize the watchdog to the requirements of the application. - Configure peripheral modules to the requirements of the application. Additionally, the watchdog timer, oscillator fault, and flash memory flags can be evaluated to determine the source of the reset. 2-4 System Resets, Interrupts, and Operating Modes System Reset and Initialization 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2−3. The nearer a module is to the CPU/NMIRS, the higher the priority. Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously. There are three types of interrupts: - System reset - (Non)-maskable NMI - Maskable Figure 2−3. Interrupt Priority CPU Priority High Low GMIRS GIE NMIRS Module Module 1 2 12 12 WDT Timer Module Module m n 12 12 1 PUC PUC Circuit OSCfault Flash ACCV Reset/NMI WDT Security Key Flash Security Key MAB − 5LSBs Bus Grant System Resets, Interrupts, and Operating Modes 2-5 System Reset and Initialization 2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enable bit (GIE), but are enabled by individual interrupt enable bits (ACCVIE, NMIIE, OFIE). When a NMI interrupt is accepted, all NMI interrupt enable bits are automatically reset. Program execution begins at the address stored in the (non)-maskable interrupt vector, 0FFFCh. User software must set the required NMI interrupt enable bits for the interrupt to be re-enabled. The block diagram for NMI sources is shown in Figure 2−4. A (non)-maskable NMI interrupt can be generated by three sources: - An edge on the RST/NMI pin when configured in NMI mode - An oscillator fault occurs - An access violation to the flash memory Reset/NMI Pin At power-up, the RST/NMI pin is configured in the reset mode. The function of the RST/NMI pins is selected in the watchdog control register WDTCTL. If the RST/NMI pin is set to the reset function, the CPU is held in the reset state as long as the RST/NMI pin is held low. After the input changes to a high state, the CPU starts program execution at the word address stored in the reset vector, 0FFFEh. If the RST/NMI pin is configured by user software to the NMI function, a signal edge selected by the WDTNMIES bit generates an NMI interrupt if the NMIIE bit is set. The RST/NMI flag NMIIFG is also set. Note: Holding RST/NMI Low When configured in the NMI mode, a signal generating an NMI event should not hold the RST/NMI pin low. If a PUC occurs from a different source while the NMI signal is low, the device will be held in the reset state because a PUC changes the RST/NMI pin to the reset function. Note: Modifying WDTNMIES When NMI mode is selected and the WDTNMIES bit is changed, an NMI can be generated, depending on the actual level at the RST/NMI pin. When the NMI edge select bit is changed before selecting the NMI mode, no NMI is generated. 2-6 System Resets, Interrupts, and Operating Modes System Reset and Initialization Figure 2−4. Block Diagram of (Non)-Maskable Interrupt Sources ACCV FCTL3.2 ACCVIFG S ACCVIE IE1.5 Clear PUC RST/NMI Flash Module POR PUC KEYV SVS_POR BOR System Reset Generator PUC POR NMIIFG S IFG1.4 Clear WDTTMSEL WDTNMIES WDTNMI WDTQn NMIRS EQU PUC POR PUC NMIIE IE1.4 Clear PUC OSCFault OFIFG S IFG1.1 OFIE IE1.1 PUC Clear NMI_IRQA WDTIFG S IRQ IFG1.0 Clear Counter WDT POR IRQA WDTTMSEL WDTIE IE1.0 Clear IRQA: Interrupt Request Accepted Watchdog Timer Module PUC System Resets, Interrupts, and Operating Modes 2-7 System Reset and Initialization Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator. The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit. The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault. A PUC signal can trigger an oscillator fault, because the PUC switches the LFXT1 to LF mode, therefore switching off the HF mode. The PUC signal also switches off the XT2 oscillator. Flash Access Violation The flash ACCVIFG flag is set when a flash access violation occurs. The flash access violation can be enabled to generate an NMI interrupt by setting the ACCVIE bit. The ACCVIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by a flash access violation. 2-8 System Resets, Interrupts, and Operating Modes System Reset and Initialization Example of an NMI Interrupt Handler The NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE, and ACCVIE interrupt-enable bits. The user NMI service routine resets the interrupt flags and re-enables the interrupt-enable bits according to the application needs as shown in Figure 2−5. Figure 2−5. NMI Interrupt Handler Start of NMI Interrupt Handler Reset by HW: OFIE, NMIIE, ACCVIE OFIFG=1 no no ACCVIFG=1 yes yes Reset OFIFG Reset ACCVIFG no NMIIFG=1 yes Reset NMIIFG User’s Software, Oscillator Fault Handler Optional User’s Software, Flash Access Violation Handler User’s Software, External NMI Handler RETI End of NMI Interrupt Handler Note: Enabling NMI Interrupts with ACCVIE, NMIIE, and OFIE To prevent nested NMI interrupts, the ACCVIE, NMIIE, and OFIE enable bits should not be set inside of an NMI interrupt service routine. 2.2.2 Maskable Interrupts Maskable interrupts are caused by peripherals with interrupt capability including the watchdog timer overflow in interval-timer mode. Each maskable interrupt source can be disabled individually by an interrupt enable bit, or all maskable interrupts can be disabled by the general interrupt enable (GIE) bit in the status register (SR). Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual. System Resets, Interrupts, and Operating Modes 2-9 System Reset and Initialization 2.2.3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)-maskable interrupts to be requested. Interrupt Acceptance The interrupt latency is six cycles, starting with the acceptance of an interrupt request and lasting until the start of execution of the first instruction of the interrupt-service routine, as shown in Figure 2−6. The interrupt logic executes the following: 1) Any currently executing instruction is completed. 2) The PC, which points to the next instruction, is pushed onto the stack. 3) The SR is pushed onto the stack. 4) The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service. 5) The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set for servicing by software. 6) The SR is cleared with the exception of SCG0, which is left unchanged. This terminates any low-power mode. Because the GIE bit is cleared, further interrupts are disabled. 7) The content of the interrupt vector is loaded into the PC: the program continues with the interrupt service routine at that address. Figure 2−6. Interrupt Processing Before Interrupt After Interrupt Item1 Item1 SP Item2 TOS Item2 PC SP SR TOS 2-10 System Resets, Interrupts, and Operating Modes System Reset and Initialization Return From Interrupt The interrupt handling routine terminates with the instruction: RETI (return from an interrupt service routine) The return from the interrupt takes 5 cycles to execute the following actions and is illustrated in Figure 2−7. 1) The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are now in effect, regardless of the settings used during the interrupt service routine. 2) The PC pops from the stack and begins execution at the point where it was interrupted. Figure 2−7. Return From Interrupt Before Return From Interrupt After Item1 Item1 Item2 SP Item2 TOS PC PC SP SR TOS SR Interrupt nesting is enabled if the GIE bit is set inside an interrupt service routine. When interrupt nesting is enabled, any interrupt occurring during an interrupt service routine will interrupt the routine, regardless of the interrupt priorities. System Resets, Interrupts, and Operating Modes 2-11 System Reset and Initialization 2.2.4 Interrupt Vectors The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h as described in Table 2−1. A vector is programmed by the user with the 16-bit address of the corresponding interrupt service routine. Some devices may contain more interrupt vectors. See the device-specific data sheet for the complete interrupt vector list. Table 2−1. Interrupt Sources,Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS Power-up, external reset, watchdog, flash password WDTIFG KEYV Reset 0FFFEh NMI, oscillator fault, NMIIFG flash memory access OFIFG violation ACCVIFG (non)-maskable (non)-maskable (non)-maskable 0FFFCh Device-specific 0FFFAh Device-specific 0FFF8h Device-specific 0FFF6h Watchdog timer WDTIFG maskable 0FFF4h Device-specific 0FFF2h Device-specific 0FFF0h Device-specific 0FFEEh Device-specific 0FFECh Device-specific 0FFEAh Device-specific 0FFE8h Device-specific 0FFE6h Device-specific 0FFE4h Device-specific 0FFE2h Device-specific 0FFE0h PRIORITY 15, highest 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0, lowest 2.2.5 Special Function Registers (SFRs) Some module enable bits, interrupt enable bits, and interrupt flags are located in the SFRs. The SFRs are located in the lower address range and are implemented in byte format. SFRs must be accessed using byte instructions. See the device-specific data sheet for the SFR configuration. 2-12 System Resets, Interrupts, and Operating Modes Operating Modes 2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 2−9. The operating modes take into account three different needs: - Ultralow-power - Speed and data throughput - Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2−8. Figure 2−8. Typical Current Consumption of 41x Devices vs Operating Modes ICC/ μA @ 1 MHz 315 300 270 225 200 180 135 90 45 55 32 0 AM LPM0 VCC = 3 V VCC = 2.2 V 17 11 0.9 0.7 LPM2 LPM3 Operating Modes 0.1 0.1 LPM4 The low-power modes 0 to 4 are configured with the CPUOFF, OSCOFF, SCG0, and SCG1 bits in the status register. The advantage of including the CPUOFF, OSCOFF, SCG0, and SCG1 mode-control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine. Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine. Program flow can be returned to a different operating mode by manipulating the saved SR value on the stack inside of the interrupt service routine. The mode-control bits and the stack can be accessed with any instruction. When setting any of the mode-control bits, the selected operating mode takes effect immediately. Peripherals operating with any disabled clock are disabled until the clock becomes active. The peripherals may also be disabled with their individual control register settings. All I/O port pins and RAM/registers are unchanged. Wake up is possible through all enabled interrupts. System Resets, Interrupts, and Operating Modes 2-13 Operating Modes Figure 2−9. MSP430x4xx Operating Modes For FLL+ Clock System RST/NMI Reset Active VCC On WDT Active, Time Expired, Overflow WDTIFG = 1 WDTIFG = 1 POR WDTIFG = 0 PUC RST/NMI is Reset Pin WDT is Active WDT Active, Security Key Violation RST/NMI NMI Active CPUOFF = 1 SCG0 = 0 SCG1 = 0 Active Mode CPU Is Active Peripheral Modules Are Active LPM0 CPU Off, FLL+ On, 41x/42x MCLK On, 43x/44x MCLK off, ACLK On CPUOFF = 1 SCG0 = 1 SCG1 = 0 CPUOFF = 1 CPUOFF = 1 SCG0 = 1 LPM1 CPU Off, FLL+ Off, SCG0 = 0 SCG1 = 1 SCG1 = 1 41x/42x MCLK On, 43x/44x MCLK off ACLK On LPM2 CPU Off, FLL+ Off, MCLK Off, ACLK On CPUOFF = 1 OSCOFF = 1 SCG0 = 1 SCG1 = 1 LPM4 CPU Off, FLL+ Off, MCLK Off, ACLK Off DC Generator Off LPM3 CPU Off, FLL+ Off, MCLK Off, ACLK On DC Generator Off SCG1 0 0 SCG0 OSCOFF CPUOFF Mode 0 0 0 Active 0 0 1 LPM0 0 1 0 1 LPM1 1 0 0 1 1 0 1 1 1 1 LPM2 1 LPM3 1 LPM4 CPU and Clocks Status CPU is active, all enabled clocks are active CPU, MCLK are disabled (41x/42x peripheral MCLK remains on) SMCLK , ACLK are active CPU, MCLK, DCO oscillator are disabled (41x/42x peripheral MCLK remains on) DC generator is disabled if the DCO is not used for MCLK or SMCLK in active mode SMCLK , ACLK are active CPU, MCLK, SMCLK, DCO oscillator are disabled DC generator remains enabled ACLK is active CPU, MCLK, SMCLK, DCO oscillator are disabled DC generator disabled ACLK is active CPU and all clocks disabled 2-14 System Resets, Interrupts, and Operating Modes Operating Modes 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes. The program flow is: - Enter interrupt service routine: J The PC and SR are stored on the stack J The CPUOFF, SCG1, and OSCOFF bits are automatically reset - Options for returning from the interrupt service routine: J The original SR is popped from the stack, restoring the previous operating mode. J The SR bits stored on the stack can be modified within the interrupt service routine returning to a different operating mode when the RETI instruction is executed. ; Enter LPM0 Example BIS #GIE+CPUOFF,SR ; Enter LPM0 ; ... ; Program stops here ; ; Exit LPM0 Interrupt Service Routine BIC #CPUOFF,0(SP) ; Exit LPM0 on RETI RETI ; Enter LPM3 Example BIS #GIE+CPUOFF+SCG1+SCG0,SR ; Enter LPM3 ; ... ; Program stops here ; ; Exit LPM3 Interrupt Service Routine BIC #CPUOFF+SCG1+SCG0,0(SP) ; Exit LPM3 on RETI RETI Extended Time in Low-Power Modes The negative temperature coefficient of the DCO should be considered when the DCO is disabled for extended low-power mode periods. If the temperature changes significantly, the DCO frequency at wake-up may be significantly different from when the low-power mode was entered and may be out of the specified operating range. To avoid this, the DCO can be set to it lowest value before entering the low-power mode for extended periods of time where temperature can change. ; Enter LPM4 Example with lowest DCO Setting BIC.B #FN_8+FN_4+FN_3+FN_2,&SCFI0 ; Lowest Range MOV.B #010h,&SCFI1 ; Select Tap 2 BIS #GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR ; Enter LPM4 ; ... ; Program stops ; Interrupt Service Routine BIC #CPUOFF+OSCOFF+SCG1+SCG0,0(SP); Exit LPM4 on RETI RETI System Resets, Interrupts, and Operating Modes 2-15 Principles for Low-Power Applications 2.4 Principles for Low-Power Applications Often, the most important factor for reducing power consumption is using the MSP430’s clock system to maximize the time in LPM3. LPM3 power consumption is less than 2 μA typical with both a real-time clock function and all interrupts active. A 32-kHz watch crystal is used for the ACLK, and the CPU is clocked from the DCO (normally off) which has a 6-μs wake-up time. - Use interrupts to wake the processor and control program flow. - Peripherals should be switched on only when needed. - Use low-power integrated peripheral modules in place of software driven functions. For example Timer_A and Timer_B can automatically generate PWM and capture external timing, with no CPU resources. - Calculated branching and fast table look-ups should be used in place of flag polling and long software calculations. - Avoid frequent subroutine and function calls due to overhead. - For longer software routines, single-cycle CPU registers should be used. 2.5 Connection of Unused Pins The correct termination of all unused pins is listed in Table 2−2. Table 2−2. Connection of Unused Pins Pin Potential Comment AVCC AVSS VREF+ VeREF+ VREF−/VeREF− XIN XOUT DVCC DVSS Open DVSS DVSS DVCC Open XT2IN XT2OUT DVSS Open 43x, 44x. and 46x devices 43x, 44x, and 46x devices Px.0 to Px.7 Open Switched to port function, output direction RST/NMI R03 COM0 DVCC or VCC DVSS Open 47-kΩ pullup with 10-nF (2.2 nF†) pulldown TDO/TDI/TMS/ TCK Open Ax (dedicated) Open 42x devices Sxx Open † MSP430F41x2 only: The pulldown capacitor should not exceed 2.2 nF when using Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers. 2-16 System Resets, Interrupts, and Operating Modes Chapter 3 RISC 16-Bit CPU This chapter describes the MSP430 CPU, addressing modes, and instruction set. Topic Page 3.1 CPU Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 RISC 16-Bit CPU 3-1 CPU Introduction 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The CPU can address the complete address range without paging. The CPU features include: - RISC architecture with 27 instructions and 7 addressing modes - Orthogonal architecture with every instruction usable with every addressing mode - Full register access including program counter, status registers, and stack pointer - Single-cycle register operations - Large 16-bit register file reduces fetches to memory - 16-bit address bus allows direct access and branching throughout entire memory range - 16-bit data bus allows direct manipulation of word-wide arguments - Constant generator provides six most used immediate values and reduces code size - Direct memory-to-memory transfers without intermediate register holding - Word and byte addressing and instruction formats The block diagram of the CPU is shown in Figure 3−1. 3-2 RISC 16-Bit CPU Figure 3−1. CPU Block Diagram MDB − Memory Data Bus Memory Address Bus − MAB 15 0 R0/PC Program Counter 0 R1/SP Stack Pointer 0 R2/SR/CG1 Status R3/CG2 Constant Generator R4 General Purpose R5 General Purpose R6 General Purpose R7 General Purpose R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14 General Purpose R15 General Purpose 16 Zero, Z dst src Carry, C Overflow, V 16−bit ALU Negative, N 16 MCLK CPU Introduction RISC 16-Bit CPU 3-3 CPU Registers 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 have dedicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (two, four, or six), and the PC is incremented accordingly. Instruction accesses in the 64-KB address space are performed on word boundaries, and the PC is aligned to even addresses. Figure 3−2 shows the program counter. Figure 3−2. Program Counter 15 10 Program Counter Bits 15 to 1 0 The PC can be addressed with all instructions and addressing modes. A few examples: MOV #LABEL,PC ; Branch to address LABEL MOV LABEL,PC ; Branch to address contained in LABEL MOV @R14,PC ; Branch indirect to address in R14 3-4 RISC 16-Bit CPU CPU Registers 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes. Figure 3−3 shows the SP. The SP is initialized into RAM by the user, and is aligned to even addresses. Figure 3−4 shows stack usage. Figure 3−3. Stack Pointer 15 Stack Pointer Bits 15 to 1 10 0 MOV MOV PUSH POP 2(SP),R6 ; Item I2 −> R6 R7,0(SP) ; Overwrite TOS with R7 #0123h ; Put 0123h onto TOS R8 ; R8 = 0123h Figure 3−4. Stack Usage Address 0xxxh I1 0xxxh − 2 I2 0xxxh − 4 I3 0xxxh − 6 0xxxh − 8 PUSH #0123h POP R8 I1 I2 SP I3 0123h I1 I2 I3 SP SP 0123h The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 3−5. Figure 3−5. PUSH SP - POP SP Sequence PUSH SP POP SP SPold SP1 SP1 SP2 SP1 The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction. instruction. The POP SP instruction places SP1 into the stack pointer SP (SP2=SP1) RISC 16-Bit CPU 3-5 CPU Registers 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator. Figure 3−6 shows the SR bits. Figure 3−6. Status Register Bits 15 Reserved 98 7 0 V SCG1 SCG0 OSC CPU OFF OFF GIE N ZC rw-0 Table 3−1 describes the status register bits. Table 3−1. Description of Status Register Bits Bit Description V Overflow bit. This bit is set when the result of an arithmetic operation overflows the signed-variable range. ADD(.B),ADDC(.B) Set when: Positive + Positive = Negative Negative + Negative = Positive, otherwise reset SUB(.B),SUBC(.B),CMP(.B) Set when: Positive − Negative = Negative Negative − Positive = Positive, otherwise reset SCG1 System clock generator 1. This bit, when set, turns off the DCO dc generator, if DCOCLK is not used for MCLK or SMCLK. SCG0 System clock generator 0. This bit, when set, turns off the FLL+ loop control OSCOFF Oscillator Off. This bit, when set, turns off the LFXT1 crystal oscillator, when LFXT1CLK is not use for MCLK or SMCLK CPUOFF CPU off. This bit, when set, turns off the CPU. GIE General interrupt enable. This bit, when set, enables maskable interrupts. When reset, all maskable interrupts are disabled. N Negative bit. This bit is set when the result of a byte or word operation is negative and cleared when the result is not negative. Word operation: N is set to the value of bit 15 of the result Byte operation: N is set to the value of bit 7 of the result Z Zero bit. This bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0. C Carry bit. This bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred. 3-6 RISC 16-Bit CPU CPU Registers 3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constants are selected with the source-register addressing modes (As), as described in Table 3−2. Table 3−2. Values of Constant Generators CG1, CG2 Register R2 R2 R2 R2 R3 R3 R3 R3 As Constant 00 −−−−− 01 (0) 10 00004h 11 00008h 00 00000h 01 00001h 10 00002h 11 0FFFFh Remarks Register mode Absolute address mode +4, bit processing +8, bit processing 0, word processing +1 +2, bit processing −1, word processing The constant generator advantages are: - No special instructions required - No additional code word for the six constants - No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as source-only registers. Constant Generator − Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions. However, the constant generator allows the MSP430 assembler to support 24 additional, emulated instructions. For example, the single-operand instruction: CLR dst is emulated by the double-operand instruction with the same length: MOV R3,dst where the #0 is replaced by the assembler, and R3 is used with As = 00. INC dst is replaced by: ADD 0(R3),dst RISC 16-Bit CPU 3-7 CPU Registers 3.2.5 General-Purpose Registers R4 to R15 Twelve registers, R4 to R15, are general-purpose registers. All of these registers can be used as data registers, address pointers, or index values, and they can be accessed with byte or word instructions as shown in Figure 3−7. Figure 3−7. Register-Byte/Byte-Register Operations Register-Byte Operation High Byte Unused Low Byte Register Byte-Register Operation High Byte Low Byte Byte Memory Byte Memory 0h Register Example Register-Byte Operation R5 = 0A28Fh R6 = 0203h Mem(0203h) = 012h ADD.B R5,0(R6) 08Fh + 012h 0A1h Mem (0203h) = 0A1h C = 0, Z = 0, N = 1 (Low byte of register) + (Addressed byte) −>(Addressed byte) Example Byte-Register Operation R5 = 01202h R6 = 0223h Mem(0223h) = 05Fh ADD.B @R6,R5 05Fh + 002h 00061h R5 = 00061h C = 0, Z = 0, N = 0 (Addressed byte) + (Low byte of register) −>(Low byte of register, zero to High byte) 3-8 RISC 16-Bit CPU Addressing Modes 3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in Table 3−3 describe the contents of the As (source) and Ad (destination) mode bits. Table 3−3. Source/Destination Operand Addressing Modes As/Ad 00/0 01/1 Addressing Mode Register mode Indexed mode 01/1 Symbolic mode 01/1 Absolute mode 10/− 11/− Indirect register mode Indirect autoincrement 11/− Immediate mode Syntax Rn X(Rn) ADDR &ADDR @Rn @Rn+ #N Description Register contents are operand (Rn + X) points to the operand. X is stored in the next word. (PC + X) points to the operand. X is stored in the next word. Indexed mode X(PC) is used. The word following the instruction contains the absolute address. X is stored in the next word. Indexed mode X(SR) is used. Rn is used as a pointer to the operand. Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for .B instructions and by 2 for .W instructions. The word following the instruction contains the immediate constant N. Indirect autoincrement mode @PC+ is used. The seven addressing modes are explained in detail in the following sections. Most of the examples show the same addressing mode for the source and destination, but any valid combination of source and destination addressing modes is possible in an instruction. Note: Use of Labels EDE, TONI, TOM, and LEO Throughout MSP430 documentation, EDE, TONI, TOM, and LEO are used as generic labels. They are only labels. They have no special meaning. RISC 16-Bit CPU 3-9 Addressing Modes 3.3.1 Register Mode The register mode is described in Table 3−4. Table 3−4. Register Mode Description Assembler Code MOV R10,R11 Content of ROM MOV R10,R11 Length: One or two words Operation: Move the content of R10 to R11. R10 is not affected. Comment: Valid for source and destination Example: MOV R10,R11 Before: After: R10 0A023h R10 0A023h R11 0FA15h R11 0A023h PC PCold PC PCold + 2 Note: Data in Registers The data in the register can be accessed using word or byte instructions. If byte instructions are used, the high byte is always 0 in the result. The status bits are handled according to the result of the byte instruction. 3-10 RISC 16-Bit CPU Addressing Modes 3.3.2 Indexed Mode The indexed mode is described in Table 3−5. Table 3−5. Indexed Mode Description Assembler Code MOV 2(R5),6(R6) Content of ROM MOV X(R5),Y(R6) X=2 Y=6 Length: Two or three words Operation: Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6). The source and destination registers (R5 and R6) are not affected. In indexed mode, the program counter is incremented automatically so that program execution continues with the next instruction. Comment: Valid for source and destination Example: MOV 2(R5),6(R6); Before: Address Space Register 0FF16h 0FF14h 0FF12h 00006h 00002h 04596h R5 R6 PC 01080h 0108Ch After: Address Space 0xxxxh 0FF16h 00006h 0FF14h 00002h 0FF12h 04596h Register PC R5 01080h R6 0108Ch 01094h 01092h 01090h 0xxxxh 05555h 0xxxxh 0108Ch +0006h 01092h 01094h 01092h 01090h 0xxxxh 01234h 0xxxxh 01084h 01082h 01080h 0xxxxh 01234h 0xxxxh 01080h +0002h 01082h 01084h 01082h 01080h 0xxxxh 01234h 0xxxxh RISC 16-Bit CPU 3-11 Addressing Modes 3.3.3 Symbolic Mode The symbolic mode is described in Table 3−6. Table 3−6. Symbolic Mode Description Assembler Code MOV EDE,TONI Content of ROM MOV X(PC),Y(PC) X = EDE − PC Y = TONI − PC Length: Two or three words Operation: Move the contents of the source address EDE (contents of PC + X) to the destination address TONI (contents of PC + Y). The words after the instruction contain the differences between the PC and the source or destination addresses. The assembler computes and inserts offsets X and Y automatically. With symbolic mode, the program counter (PC) is incremented automatically so that program execution continues with the next instruction. Comment: Valid for source and destination Example: MOV EDE,TONI ;Source address EDE = 0F016h ;Dest. address TONI=01114h Before: Address Space Register 0FF16h 0FF14h 0FF12h 011FEh 0F102h 04090h PC After: 0FF16h 0FF14h 0FF12h Address Space 0xxxxh 011FEh 0F102h 04090h Register PC 0F018h 0F016h 0F014h 0xxxxh 0A123h 0xxxxh 0FF14h +0F102h 0F016h 0F018h 0F016h 0F014h 0xxxxh 0A123h 0xxxxh 01116h 01114h 01112h 0xxxxh 05555h 0xxxxh 0FF16h +011FEh 01114h 01116h 01114h 01112h 0xxxxh 0A123h 0xxxxh 3-12 RISC 16-Bit CPU Addressing Modes 3.3.4 Absolute Mode The absolute mode is described in Table 3−7. Table 3−7. Absolute Mode Description Assembler Code MOV &EDE,&TONI Length: Two or three words Content of ROM MOV X(0),Y(0) X = EDE Y = TONI Operation: Move the contents of the source address EDE to the destination address TONI. The words after the instruction contain the absolute address of the source and destination addresses. With absolute mode, the PC is incremented automatically so that program execution continues with the next instruction. Comment: Valid for source and destination Example: MOV &EDE,&TONI ;Source address EDE=0F016h, ;dest. address TONI=01114h Before: Address Space Register 0FF16h 0FF14h 0FF12h 01114h 0F016h 04292h PC After: 0FF16h Address Space 0xxxxh 01114h Register PC 0FF14h 0F016h 0FF12h 04292h 0F018h 0F016h 0F014h 0xxxxh 0A123h 0xxxxh 0F018h 0F016h 0F014h 0xxxxh 0A123h 0xxxxh 01116h 01114h 01112h 0xxxxh 01234h 0xxxxh 01116h 01114h 01112h 0xxxxh 0A123h 0xxxxh This address mode is mainly for hardware peripheral modules that are located at an absolute, fixed address. These are addressed with absolute mode to ensure software transportability (for example, position-independent code). RISC 16-Bit CPU 3-13 Addressing Modes 3.3.5 Indirect Register Mode The indirect register mode is described in Table 3−8. Table 3−8. Indirect Mode Description Assembler Code MOV @R10,0(R11) Content of ROM MOV @R10,0(R11) Length: One or two words Operation: Move the contents of the source address (contents of R10) to the destination address (contents of R11). The registers are not modified. Comment: Valid only for source operand. The substitute for destination operand is 0(Rd). Example: MOV.B @R10,0(R11) Before: Address Space 0xxxxh 0FF16h 0000h 0FF14h 04AEBh 0FF12h 0xxxxh Register R10 0FA33h PC R11 002A7h After: Address Space 0xxxxh 0FF16h 0000h 0FF14h 04AEBh 0FF12h 0xxxxh Register PC R10 0FA33h R11 002A7h 0FA34h 0FA32h 0FA30h 0xxxxh 05BC1h 0xxxxh 0FA34h 0xxxxh 0FA32h 05BC1h 0FA30h 0xxxxh 002A8h 002A7h 002A6h 0xxh 012h 0xxh 002A8h 002A7h 002A6h 0xxh 05Bh 0xxh 3-14 RISC 16-Bit CPU Addressing Modes 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 3−9. Table 3−9. Indirect Autoincrement Mode Description Assembler Code MOV @R10+,0(R11) Content of ROM MOV @R10+,0(R11) Length: One or two words Operation: Move the contents of the source address (contents of R10) to the destination address (contents of R11). Register R10 is incremented by 1 for a byte operation, or 2 for a word operation after the fetch; it points to the next address without any overhead. This is useful for table processing. Comment: Valid only for source operand. The substitute for destination operand is 0(Rd) plus second instruction INCD Rd. Example: MOV @R10+,0(R11) Before: Address Space After: Register Address Space Register 0FF18h 0FF16h 0FF14h 0FF12h 0xxxxh 00000h 04ABBh 0xxxxh R10 PC R11 0FA32h 010A8h 0FF18h 0xxxxh PC 0FF16h 00000h R10 0FA34h 0FF14h 04ABBh R11 010A8h 0FF12h 0xxxxh 0FA34h 0FA32h 0FA30h 0xxxxh 05BC1h 0xxxxh 0FA34h 0xxxxh 0FA32h 05BC1h 0FA30h 0xxxxh 010AAh 0xxxxh 010A8h 01234h 010A6h 0xxxxh 010AAh 0xxxxh 010A8h 05BC1h 010A6h 0xxxxh The autoincrementing of the register contents occurs after the operand is fetched. This is shown in Figure 3−8. Figure 3−8. Operand Fetch Operation Instruction Address Operand +1/ +2 RISC 16-Bit CPU 3-15 Addressing Modes 3.3.7 Immediate Mode The immediate mode is described in Table 3−10. Table 3−10.Immediate Mode Description Assembler Code MOV #45h,TONI Content of ROM MOV @PC+,X(PC) 45 X = TONI − PC Length: Two or three words It is one word less if a constant of CG1 or CG2 can be used. Operation: Move the immediate constant 45h, which is contained in the word following the instruction, to destination address TONI. When fetching the source, the program counter points to the word following the instruction and moves the contents to the destination. Comment: Valid only for a source operand. Example: MOV #45h,TONI Before: Address Space Register 0FF16h 0FF14h 0FF12h 01192h 00045h 040B0h PC After: 0FF18h 0FF16h 0FF14h 0FF12h Address Space 0xxxxh 01192h 00045h 040B0h Register PC 010AAh 010A8h 010A6h 0xxxxh 01234h 0xxxxh 0FF16h +01192h 010A8h 010AAh 010A8h 010A6h 0xxxxh 00045h 0xxxxh 3-16 RISC 16-Bit CPU Instruction Set 3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions. The core instructions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automatically by the assembler with an equivalent core instruction. There is no code or performance penalty for using emulated instruction. There are three core-instruction formats: - Dual operand - Single operand - Jump All single-operand and dual-operand instructions can be byte or word instructions by using .B or .W extensions. Byte instructions are used to access byte data or byte peripherals. Word instructions are used to access word data or word peripherals. If no extension is used, the instruction is a word instruction. The source and destination of an instruction are defined by the following fields: src dst As S-reg Ad D-reg B/W The source operand defined by As and S-reg The destination operand defined by Ad and D-reg The addressing bits responsible for the addressing mode used for the source (src) The working register used for the source (src) The addressing bits responsible for the addressing mode used for the destination (dst) The working register used for the destination (dst) Byte or word operation: 0: word operation 1: byte operation Note: Destination Address Destination addresses are valid anywhere in the memory map. However, when using an instruction that modifies the contents of the destination, the user must ensure the destination address is writable. For example, a masked-ROM location would be a valid destination address, but the contents are not modifiable, so the results of the instruction would be lost. RISC 16-Bit CPU 3-17 Instruction Set 3.4.1 Double-Operand (Format I) Instructions Figure 3−9 illustrates the double-operand instruction format. Figure 3−9. Double-Operand Instruction Format 15 14 13 12 11 Op-code 10 9 S-Reg 8 7 6 5 4 3210 Ad B/W As D-Reg Table 3−11 lists and describes the double operand instructions. Table 3−11. Double-Operand Instructions Mnemonic S-Reg, D-Reg Operation MOV(.B) ADD(.B) ADDC(.B) SUB(.B) SUBC(.B) src,dst src,dst src,dst src,dst src,dst src → dst src + dst → dst src + dst + C → dst dst + .not.src + 1 → dst dst + .not.src + C → dst CMP(.B) DADD(.B) BIT(.B) BIC(.B) BIS(.B) XOR(.B) AND(.B) src,dst src,dst src,dst src,dst src,dst src,dst src,dst dst − src src + dst + C → dst (decimally) src .and. dst .not.src .and. dst → dst src .or. dst → dst src .xor. dst → dst src .and. dst → dst * The status bit is affected − The status bit is not affected 0 The status bit is cleared 1 The status bit is set Status Bits VNZC −−−− **** **** **** **** **** **** 0* * * −−−− −−−− **** 0* * * Note: Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result. The same is true for the BIT and AND instructions. 3-18 RISC 16-Bit CPU Instruction Set 3.4.2 Single-Operand (Format II) Instructions Figure 3−10 illustrates the single-operand instruction format. Figure 3−10. Single-Operand Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Op-code B/W Ad D/S-Reg Table 3−12 lists and describes the single operand instructions. Table 3−12.Single-Operand Instructions Mnemonic S-Reg, D-Reg Operation RRC(.B) dst RRA(.B) dst PUSH(.B) src SWPB dst CALL dst RETI SXT dst C → MSB →.......LSB → C MSB → MSB →....LSB → C SP − 2 → SP, src → @SP Swap bytes SP − 2 → SP, PC+2 → @SP dst → PC TOS → SR, SP + 2 → SP TOS → PC,SP + 2 → SP Bit 7 → Bit 8........Bit 15 * The status bit is affected − The status bit is not affected 0 The status bit is cleared 1 The status bit is set Status Bits VNZ C **** 0* * * −−−− −−−− −−−− **** 0* * * All addressing modes are possible for the CALL instruction. If the symbolic mode (ADDRESS), the immediate mode (#N), the absolute mode (&EDE), or the indexed mode x(RN) is used, the word that follows contains the address information. RISC 16-Bit CPU 3-19 Instruction Set 3.4.3 Jumps Figure 3−11 shows the conditional-jump instruction format. Figure 3−11. Jump Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Op-code C 10-Bit PC Offset Table 3−13 lists and describes the jump instructions. Table 3−13.Jump Instructions Mnemonic JEQ/JZ JNE/JNZ JC JNC JN JGE JL JMP S-Reg, D-Reg Label Label Label Label Label Label Label Label Operation Jump to label if zero bit is set Jump to label if zero bit is reset Jump to label if carry bit is set Jump to label if carry bit is reset Jump to label if negative bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally Conditional jumps support program branching relative to the PC and do not affect the status bits. The possible jump range is from − 511 to +512 words relative to the PC value at the jump instruction. The 10-bit program-counter offset is treated as a signed 10-bit value that is doubled and added to the program counter: PCnew = PCold + 2 + PCoffset × 2 3-20 RISC 16-Bit CPU * ADC[.W] * ADC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Add carry to destination Add carry to destination ADC dst or ADC.W dst ADC.B dst dst + C −> dst ADDC #0,dst ADDC.B #0,dst The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if dst was incremented from 0FFFFh to 0000, reset otherwise Set if dst was incremented from 0FFh to 00, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. The 16-bit counter pointed to by R13 is added to a 32-bit counter pointed to by R12. ADD @R13,0(R12) ; Add LSDs ADC 2(R12) ; Add carry to MSD The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ; Add LSDs ADC.B 1(R12) ; Add carry to MSD RISC 16-Bit CPU 3-21 Instruction Set ADD[.W] ADD.B Syntax Operation Description Status Bits Mode Bits Example Example Add source to destination Add source to destination ADD src,dst or ADD.B src,dst ADD.W src,dst src + dst −> dst The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the result, cleared if not V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. R5 is increased by 10. The jump to TONI is performed on a carry. ADD JC ...... #10,R5 TONI ; Carry occurred ; No carry R5 is increased by 10. The jump to TONI is performed on a carry. ADD.B JC ...... #10,R5 TONI ; Add 10 to Lowbyte of R5 ; Carry occurred, if (R5) ≥ 246 [0Ah+0F6h] ; No carry 3-22 RISC 16-Bit CPU ADDC[.W] ADDC.B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Add source and carry to destination Add source and carry to destination ADDC ADDC.B src,dst or ADDC.W src,dst src,dst src + dst + C −> dst The source operand and the carry bit (C) are added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. The 32-bit counter pointed to by R13 is added to a 32-bit counter, eleven words (20/2 + 2/2) above the pointer in R13. ADD ADDC ... @R13+,20(R13) ; ADD LSDs with no carry in @R13+,20(R13) ; ADD MSDs with carry ; resulting from the LSDs The 24-bit counter pointed to by R13 is added to a 24-bit counter, eleven words above the pointer in R13. ADD.B ADDC.B ADDC.B ... @R13+,10(R13) @R13+,10(R13) @R13+,10(R13) ; ADD LSDs with no carry in ; ADD medium Bits with carry ; ADD MSDs with carry ; resulting from the LSDs RISC 16-Bit CPU 3-23 Instruction Set AND[.W] AND.B Syntax Operation Description Status Bits Mode Bits Example Example Source AND destination Source AND destination AND AND.B src,dst or AND.W src,dst src,dst src .AND. dst −> dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. N: Set if result MSB is set, reset if not set Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The bits set in R5 are used as a mask (#0AA55h) for the word addressed by TOM. If the result is zero, a branch is taken to label TONI. MOV AND JZ ...... ; ; ; ; ; AND JZ #0AA55h,R5 R5,TOM TONI ; Load mask into register R5 ; mask word addressed by TOM with R5 ; ; Result is not zero or #0AA55h,TOM TONI The bits of mask #0A5h are logically ANDed with the low byte TOM. If the result is zero, a branch is taken to label TONI. AND.B JZ ...... #0A5h,TOM TONI ; mask Lowbyte TOM with 0A5h ; ; Result is not zero 3-24 RISC 16-Bit CPU BIC[.W] BIC.B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Clear bits in destination Clear bits in destination BIC BIC.B src,dst or BIC.W src,dst src,dst .NOT.src .AND. dst −> dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The six MSBs of the RAM word LEO are cleared. BIC #0FC00h,LEO ; Clear 6 MSBs in MEM(LEO) The five MSBs of the RAM byte LEO are cleared. BIC.B #0F8h,LEO ; Clear 5 MSBs in Ram location LEO RISC 16-Bit CPU 3-25 Instruction Set BIS[.W] BIS.B Syntax Operation Description Status Bits Mode Bits Example Example Set bits in destination Set bits in destination BIS BIS.B src,dst or BIS.W src,dst src,dst src .OR. dst −> dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The six LSBs of the RAM word TOM are set. BIS #003Fh,TOM; set the six LSBs in RAM location TOM The three MSBs of RAM byte TOM are set. BIS.B #0E0h,TOM ; set the three MSBs in RAM location TOM 3-26 RISC 16-Bit CPU BIT[.W] BIT.B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Test bits in destination Test bits in destination BIT src,dst or BIT.W src,dst src .AND. dst The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected. N: Set if MSB of result is set, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT. zero) V: Reset OSCOFF, CPUOFF, and GIE are not affected. If bit 9 of R8 is set, a branch is taken to label TOM. BIT #0200h,R8 ; bit 9 of R8 set? JNZ TOM ; Yes, branch to TOM ... ; No, proceed If bit 3 of R8 is set, a branch is taken to label TOM. BIT.B JC #8,R8 TOM A serial communication receive bit (RCV) is tested. Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit, the carry bit is used by the subsequent instruction; the read information is shifted into register RECBUF. ; ; Serial communication with LSB is shifted first: ; xxxx xxxx xxxx xxxx BIT.B #RCV,RCCTL ; Bit info into carry RRC RECBUF ; Carry −> MSB of RECBUF ; cxxx xxxx ...... ; repeat previous two instructions ...... ; 8 times ; cccc cccc ;^ ^ ; MSB LSB ; Serial communication with MSB shifted first: BIT.B #RCV,RCCTL ; Bit info into carry RLC.B RECBUF ; Carry −> LSB of RECBUF ; xxxx xxxc ...... ; repeat previous two instructions ...... ; 8 times ; cccc cccc ;| LSB ; MSB RISC 16-Bit CPU 3-27 Instruction Set * BR, BRANCH Syntax Operation Emulation Description Status Bits Example Branch to .......... destination BR dst dst −> PC MOV dst,PC An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. BR #EXEC ;Branch to label EXEC or direct branch (e.g. #0A4h) ; Core instruction MOV @PC+,PC BR EXEC ; Branch to the address contained in EXEC ; Core instruction MOV X(PC),PC ; Indirect address BR &EXEC ; Branch to the address contained in absolute ; address EXEC ; Core instruction MOV X(0),PC ; Indirect address BR R5 ; Branch to the address contained in R5 ; Core instruction MOV R5,PC ; Indirect R5 BR @R5 ; Branch to the address contained in the word ; pointed to by R5. ; Core instruction MOV @R5,PC ; Indirect, indirect R5 BR @R5+ ; Branch to the address contained in the word pointed ; to by R5 and increment pointer in R5 afterwards. ; The next time—S/W flow uses R5 pointer—it can ; alter program execution due to access to ; next address in a table pointed to by R5 ; Core instruction MOV @R5,PC ; Indirect, indirect R5 with autoincrement BR X(R5) ; Branch to the address contained in the address ; pointed to by R5 + X (e.g. table with address ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X 3-28 RISC 16-Bit CPU CALL Syntax Operation Description Status Bits Example Instruction Set Subroutine CALL dst dst SP − 2 PC tmp −> tmp −> SP −> @SP −> PC dst is evaluated and stored PC updated to TOS dst saved to PC A subroutine call is made to an address anywhere in the 64K address space. All addressing modes can be used. The return address (the address of the following instruction) is stored on the stack. The call instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. CALL #EXEC ; Call on label EXEC or immediate address (e.g. #0A4h) ; SP−2 → SP, PC+2 → @SP, @PC+ → PC CALL EXEC ; Call on the address contained in EXEC ; SP−2 → SP, PC+2 → @SP, X(PC) → PC ; Indirect address CALL &EXEC ; Call on the address contained in absolute address ; EXEC ; SP−2 → SP, PC+2 → @SP, X(0) → PC ; Indirect address CALL R5 ; Call on the address contained in R5 ; SP−2 → SP, PC+2 → @SP, R5 → PC ; Indirect R5 CALL @R5 ; Call on the address contained in the word ; pointed to by R5 ; SP−2 → SP, PC+2 → @SP, @R5 → PC ; Indirect, indirect R5 CALL @R5+ ; Call on the address contained in the word ; pointed to by R5 and increment pointer in R5. ; The next time—S/W flow uses R5 pointer— ; it can alter the program execution due to ; access to next address in a table pointed to by R5 ; SP−2 → SP, PC+2 → @SP, @R5 → PC ; Indirect, indirect R5 with autoincrement CALL X(R5) ; Call on the address contained in the address pointed ; to by R5 + X (e.g. table with address starting at X) ; X can be an address or a label ; SP−2 → SP, PC+2 → @SP, X(R5) → PC ; Indirect, indirect R5 + X RISC 16-Bit CPU 3-29 Instruction Set * CLR[.W] * CLR.B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destination CLR CLR.B dst or CLR.W dst dst 0 −> dst MOV MOV.B #0,dst #0,dst The destination operand is cleared. Status bits are not affected. RAM word TONI is cleared. CLR TONI ; 0 −> TONI Register R5 is cleared. CLR R5 RAM byte TONI is cleared. CLR.B TONI ; 0 −> TONI 3-30 RISC 16-Bit CPU * CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Clear carry bit CLRC 0 −> C BIC #1,SR The carry bit (C) is cleared. The clear carry instruction is a word instruction. N: Not affected Z: Not affected C: Cleared V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12. CLRC DADD DADC ; C = 0: defines start @R13,0(R12) ; add 16-bit counter to low word of 32-bit counter 2(R12) ; add carry to high word of 32-bit counter RISC 16-Bit CPU 3-31 Instruction Set * CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET Clear negative bit CLRN 0→N or (.NOT.src .AND. dst −> dst) BIC #4,SR The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction. N: Reset to 0 Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The Negative bit in the status register is cleared. This avoids special treatment with negative numbers of the subroutine called. CLRN CALL ...... ...... JN ...... ...... ...... RET SUBR SUBRET ; If input is negative: do nothing and return 3-32 RISC 16-Bit CPU * CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Clear zero bit CLRZ 0→Z or (.NOT.src .AND. dst −> dst) BIC #2,SR The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. N: Not affected Z: Reset to 0 C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The zero bit in the status register is cleared. CLRZ RISC 16-Bit CPU 3-33 Instruction Set CMP[.W] CMP.B Syntax Operation Description Status Bits Mode Bits Example Example Example Compare source and destination Compare source and destination CMP CMP.B src,dst or src,dst CMP.W src,dst dst + .NOT.src + 1 or (dst − src) The source operand is subtracted from the destination operand. This is accomplished by adding the 1s complement of the source operand plus 1. The two operands are not affected and the result is not stored; only the status bits are affected. N: Set if result is negative, reset if positive (src >= dst) Z: Set if result is zero, reset otherwise (src = dst) C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. R5 and R6 are compared. If they are equal, the program continues at the label EQUAL. CMP JEQ R5,R6 EQUAL ; R5 = R6? ; YES, JUMP Two RAM blocks are compared. If they are not equal, the program branches to the label ERROR. MOV #NUM,R5 MOV #BLOCK1,R6 MOV #BLOCK2,R7 L$1 CMP @R6+,0(R7) JNZ ERROR INCD R7 DEC R5 JNZ L$1 ; number of words to be compared ; BLOCK1 start address in R6 ; BLOCK2 start address in R7 ; Are Words equal? R6 increments ; No, branch to ERROR ; Increment R7 pointer ; Are all words compared? ; No, another compare The RAM bytes addressed by EDE and TONI are compared. If they are equal, the program continues at the label EQUAL. CMP.B EDE,TONI JEQ EQUAL ; MEM(EDE) = MEM(TONI)? ; YES, JUMP 3-34 RISC 16-Bit CPU * DADC[.W] * DADC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Add carry decimally to destination Add carry decimally to destination DADC DADC.B dst or DADC.W src,dst dst dst + C −> dst (decimally) DADD DADD.B #0,dst #0,dst The carry bit (C) is added decimally to the destination. N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise C: Set if destination increments from 9999 to 0000, reset otherwise Set if destination increments from 99 to 00, reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The four-digit decimal number contained in R5 is added to an eight-digit decimal number pointed to by R8. CLRC DADD DADC R5,0(R8) 2(R8) ; Reset carry ; next instruction’s start condition is defined ; Add LSDs + C ; Add carry to MSD The two-digit decimal number contained in R5 is added to a four-digit decimal number pointed to by R8. CLRC DADD.B DADC R5,0(R8) 1(R8) ; Reset carry ; next instruction’s start condition is defined ; Add LSDs + C ; Add carry to MSDs RISC 16-Bit CPU 3-35 Instruction Set DADD[.W] DADD.B Syntax Operation Description Status Bits Mode Bits Example Example Source and carry added decimally to destination Source and carry added decimally to destination DADD DADD.B src,dst or DADD.W src,dst src,dst src + dst + C −> dst (decimally) The source operand and the destination operand are treated as four binary coded decimals (BCD) with positive signs. The source operand and the carry bit (C) are added decimally to the destination operand. The source operand is not affected. The previous contents of the destination are lost. The result is not defined for non-BCD numbers. N: Set if the MSB is 1, reset otherwise Z: Set if result is zero, reset otherwise C: Set if the result is greater than 9999 Set if the result is greater than 99 V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The eight-digit BCD number contained in R5 and R6 is added decimally to an eight-digit BCD number contained in R3 and R4 (R6 and R4 contain the MSDs). CLRC DADD DADD JC ; clear carry R5,R3 ; add LSDs R6,R4 ; add MSDs with carry OVERFLOW ; If carry occurs go to error handling routine The two-digit decimal counter in the RAM byte CNT is incremented by one. CLRC DADD.B #1,CNT ; clear carry ; increment decimal counter or SETC DADD.B #0,CNT ; ≡ DADC.B CNT 3-36 RISC 16-Bit CPU Instruction Set * DEC[.W] * DEC.B Decrement destination Decrement destination Syntax DEC DEC.B dst or DEC.W dst dst Operation dst − 1 −> dst Emulation Emulation SUB #1,dst SUB.B #1,dst Description The destination operand is decremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08000h, otherwise reset. Set if initial value of destination was 080h, otherwise reset. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example R10 is decremented by 1 DEC R10 ; Decrement R10 ; Move a block of 255 bytes from memory location starting with EDE to memory location starting with ;TONI. Tables should not overlap: start of destination address TONI must not be within the range EDE ; to EDE+0FEh ; MOV #EDE,R6 MOV #255,R10 L$1 MOV.B @R6+,TONI−EDE−1(R6) DEC R10 JNZ L$1 ; Do not transfer tables using the routine above with the overlap shown in Figure 3−12. Figure 3−12. Decrement Overlap EDE EDE+254 TONI TONI+254 RISC 16-Bit CPU 3-37 Instruction Set * DECD[.W] * DECD.B Double-decrement destination Double-decrement destination Syntax DECD DECD.B dst or DECD.W dst dst Operation dst − 2 −> dst Emulation Emulation SUB #2,dst SUB.B #2,dst Description The destination operand is decremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08001 or 08000h, otherwise reset. Set if initial value of destination was 081 or 080h, otherwise reset. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example R10 is decremented by 2. DECD R10 ; Decrement R10 by two ; Move a block of 255 words from memory location starting with EDE to memory location ; starting with TONI ; Tables should not overlap: start of destination address TONI must not be within the ; range EDE to EDE+0FEh ; MOV #EDE,R6 MOV #510,R10 L$1 MOV @R6+,TONI−EDE−2(R6) DECD R10 JNZ L$1 Example Memory at location LEO is decremented by two. DECD.B LEO ; Decrement MEM(LEO) Decrement status byte STATUS by two. DECD.B STATUS 3-38 RISC 16-Bit CPU * DINT Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Disable (general) interrupts DINT 0 → GIE or (0FFF7h .AND. SR → SR / .NOT.src .AND. dst −> dst) BIC #8,SR All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR. Status bits are not affected. GIE is reset. OSCOFF and CPUOFF are not affected. The general interrupt enable (GIE) bit in the status register is cleared to allow a nondisrupted move of a 32-bit counter. This ensures that the counter is not modified during the move by any interrupt. DINT NOP MOV MOV EINT ; All interrupt events using the GIE bit are disabled COUNTHI,R5 ; Copy counter COUNTLO,R6 ; All interrupt events using the GIE bit are enabled Note: Disable Interrupt If any code sequence needs to be protected from interruption, the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence, or should be followed by a NOP instruction. RISC 16-Bit CPU 3-39 Instruction Set * EINT Enable (general) interrupts Syntax EINT Operation 1 → GIE or (0008h .OR. SR −> SR / .src .OR. dst −> dst) Emulation BIS #8,SR Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR. Status Bits Status bits are not affected. Mode Bits GIE is set. OSCOFF and CPUOFF are not affected. Example The general interrupt enable (GIE) bit in the status register is set. ; Interrupt routine of ports P1.2 to P1.7 ; P1IN is the address of the register where all port bits are read. P1IFG is the address of ; the register where all interrupt events are latched. ; PUSH.B &P1IN BIC.B @SP,&P1IFG ; Reset only accepted flags EINT ; Preset port 1 interrupt flags stored on stack ; other interrupts are allowed BIT #Mask,@SP JEQ MaskOK ; Flags are present identically to mask: jump ...... MaskOK BIC #Mask,@SP ...... INCD SP ; Housekeeping: inverse to PUSH instruction ; at the start of interrupt subroutine. Corrects ; the stack pointer. RETI Note: Enable Interrupt The instruction following the enable interrupt instruction (EINT) is always executed, even if an interrupt service request is pending when the interrupts are enable. 3-40 RISC 16-Bit CPU * INC[.W] * INC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Increment destination Increment destination INC INC.B dst or INC.W dst dst dst + 1 −> dst ADD #1,dst The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The status byte, STATUS, of a process is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B CMP.B JEQ STATUS #11,STATUS OVFL RISC 16-Bit CPU 3-41 Instruction Set * INCD[.W] * INCD.B Syntax Operation Emulation Emulation Example Status Bits Mode Bits Example Example Double-increment destination Double-increment destination INCD INCD.B dst or INCD.W dst dst dst + 2 −> dst ADD #2,dst ADD.B #2,dst The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The item on the top of the stack (TOS) is removed without using a register. ....... PUSH R5 INCD SP RET ; R5 is the result of a calculation, which is stored ; in the system stack ; Remove TOS by double-increment from stack ; Do not use INCD.B, SP is a word-aligned ; register The byte on the top of the stack is incremented by two. INCD.B 0(SP) ; Byte on TOS is increment by two 3-42 RISC 16-Bit CPU * INV[.W] * INV.B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example Instruction Set Invert destination Invert destination INV dst INV.B dst .NOT.dst −> dst XOR #0FFFFh,dst XOR.B #0FFh,dst The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. Content of R5 is negated (twos complement). MOV #00AEh,R5 ; INV R5 ; Invert R5, INC R5 ; R5 is now negated, R5 = 000AEh R5 = 0FF51h R5 = 0FF52h Content of memory byte LEO is negated. MOV.B INV.B INC.B #0AEh,LEO ; MEM(LEO) = 0AEh LEO ; Invert LEO, MEM(LEO) = 051h LEO ; MEM(LEO) is negated,MEM(LEO) = 052h RISC 16-Bit CPU 3-43 Instruction Set JC JHS Syntax Operation Description Status Bits Example Example Jump if carry set Jump if higher or same JC label JHS label If C = 1: PC + 2 × offset −> PC If C = 0: execute following instruction The status register carry bit (C) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is reset, the next instruction following the jump is executed. JC (jump if carry/higher or same) is used for the comparison of unsigned numbers (0 to 65536). Status bits are not affected. The P1IN.1 signal is used to define or control the program flow. BIT #01h,&P1IN ; State of signal −> Carry JC PROGA ; If carry=1 then execute program routine A ...... ; Carry=0, execute program here R5 is compared to 15. If the content is higher or the same, branch to LABEL. CMP JHS ...... #15,R5 LABEL ; Jump is taken if R5 ≥ 15 ; Continue here if R5 < 15 3-44 RISC 16-Bit CPU JEQ, JZ Syntax Operation Description Status Bits Example Example Example Instruction Set Jump if equal, jump if zero JEQ label, JZ label If Z = 1: PC + 2 × offset −> PC If Z = 0: execute following instruction The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is not set, the instruction following the jump is executed. Status bits are not affected. Jump to address TONI if R7 contains zero. TST R7 JZ TONI ; Test R7 ; if zero: JUMP Jump to address LEO if R6 is equal to the table contents. CMP JEQ ...... R6,Table(R5) LEO ; Compare content of R6 with content of ; MEM (table address + content of R5) ; Jump if both data are equal ; No, data are not equal, continue here Branch to LABEL if R5 is 0. TST R5 JZ LABEL ...... RISC 16-Bit CPU 3-45 Instruction Set JGE Syntax Operation Description Status Bits Example Jump if greater or equal JGE label If (N .XOR. V) = 0 then jump to label: PC + 2 × offset −> PC If (N .XOR. V) = 1 then execute the following instruction The status register negative bit (N) and overflow bit (V) are tested. If both N and V are set or reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If only one is set, the instruction following the jump is executed. This allows comparison of signed integers. Status bits are not affected. When the content of R6 is greater or equal to the memory pointed to by R7, the program continues at label EDE. CMP JGE ...... ...... ...... @R7,R6 EDE ; R6 ≥ (R7)?, compare on signed numbers ; Yes, R6 ≥ (R7) ; No, proceed 3-46 RISC 16-Bit CPU JL Syntax Operation Description Status Bits Example Instruction Set Jump if less JL label If (N .XOR. V) = 1 then jump to label: PC + 2 × offset −> PC If (N .XOR. V) = 0 then execute following instruction The status register negative bit (N) and overflow bit (V) are tested. If only one is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If both N and V are set or reset, the instruction following the jump is executed. This allows comparison of signed integers. Status bits are not affected. When the content of R6 is less than the memory pointed to by R7, the program continues at label EDE. CMP JL ...... ...... ...... @R7,R6 EDE ; R6 < (R7)?, compare on signed numbers ; Yes, R6 < (R7) ; No, proceed RISC 16-Bit CPU 3-47 Instruction Set JMP Syntax Operation Description Status Bits Hint: Jump unconditionally JMP label PC + 2 × offset −> PC The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status bits are not affected. This one-word instruction replaces the BRANCH instruction in the range of −511 to +512 words relative to the current program counter. 3-48 RISC 16-Bit CPU JN Syntax Operation Description Status Bits Example L$1 Instruction Set Jump if negative JN label if N = 1: PC + 2 × offset −> PC if N = 0: execute following instruction The negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If N is reset, the next instruction following the jump is executed. Status bits are not affected. The result of a computation in R5 is to be subtracted from COUNT. If the result is negative, COUNT is to be cleared and the program continues execution in another path. SUB JN ...... ...... ...... ...... CLR ...... ...... ...... R5,COUNT L$1 ; COUNT − R5 −> COUNT ; If negative continue with COUNT=0 at PC=L$1 ; Continue with COUNT≥0 COUNT RISC 16-Bit CPU 3-49 Instruction Set JNC JLO Syntax Operation Description Status Bits Example ERROR CONT Example Jump if carry not set Jump if lower JNC label JLO label if C = 0: PC + 2 × offset −> PC if C = 1: execute following instruction The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is set, the next instruction following the jump is executed. JNC (jump if no carry/lower) is used for the comparison of unsigned numbers (0 to 65536). Status bits are not affected. The result in R6 is added in BUFFER. If an overflow occurs, an error handling routine at address ERROR is used. ADD JNC ...... ...... ...... ...... ...... ...... ...... R6,BUFFER CONT ; BUFFER + R6 −> BUFFER ; No carry, jump to CONT ; Error handler start ; Continue with normal program flow Branch to STL 2 if byte STATUS contains 1 or 0. CMP.B JLO ...... #2,STATUS STL 2 ; STATUS < 2 ; STATUS ≥ 2, continue here 3-50 RISC 16-Bit CPU JNE JNZ Syntax Operation Description Status Bits Example Instruction Set Jump if not equal Jump if not zero JNE label JNZ label If Z = 0: PC + 2 × offset −> PC If Z = 1: execute following instruction The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is set, the next instruction following the jump is executed. Status bits are not affected. Jump to address TONI if R7 and R8 have different contents. CMP JNE ...... R7,R8 TONI ; COMPARE R7 WITH R8 ; if different: jump ; if equal, continue RISC 16-Bit CPU 3-51 Instruction Set MOV[.W] MOV.B Syntax Operation Description Status Bits Mode Bits Example Loop Example Loop Move source to destination Move source to destination MOV MOV.B src,dst or MOV.W src,dst src,dst src −> dst The source operand is moved to the destination. The source operand is not affected. The previous contents of the destination are lost. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The contents of table EDE (word data) are copied to table TOM. The length of the tables must be 020h locations. MOV MOV MOV DEC JNZ ...... ...... ...... #EDE,R10 #020h,R9 @R10+,TOM−EDE−2(R10) R9 Loop ; Prepare pointer ; Prepare counter ; Use pointer in R10 for both tables ; Decrement counter ; Counter ≠ 0, continue copying ; Copying completed The contents of table EDE (byte data) are copied to table TOM. The length of the tables should be 020h locations MOV #EDE,R10 MOV #020h,R9 MOV.B @R10+,TOM−EDE−1(R10) DEC R9 JNZ Loop ...... ...... ...... ; Prepare pointer ; Prepare counter ; Use pointer in R10 for ; both tables ; Decrement counter ; Counter ≠ 0, continue ; copying ; Copying completed 3-52 RISC 16-Bit CPU * NOP Syntax Operation Emulation Description Status Bits Instruction Set No operation NOP None MOV #0, R3 No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status bits are not affected. The NOP instruction is mainly used for two purposes: - To fill one, two, or three memory words - To adjust software timing Note: Emulating No-Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words. Some examples are: Examples: MOV MOV MOV BIC JMP BIC #0,R3 0(R4),0(R4) @R4,0(R4) #0,EDE(R4) $+2 #0,R5 ; 1 cycle, 1 word ; 6 cycles, 3 words ; 5 cycles, 2 words ; 4 cycles, 2 words ; 2 cycles, 1 word ; 1 cycle, 1 word However, care should be taken when using these examples to prevent unintended results. For example, if MOV 0(R4), 0(R4) is used and the value in R4 is 120h, then a security violation will occur with the watchdog timer (address 120h) because the security key was not used. RISC 16-Bit CPU 3-53 Instruction Set * POP[.W] * POP.B Syntax Operation Emulation Emulation Description Status Bits Example Example Example Example Pop word from stack to destination Pop byte from stack to destination POP dst POP.B dst @SP −> temp SP + 2 −> SP temp −> dst MOV MOV.B @SP+,dst or MOV.W @SP+,dst @SP+,dst The stack location pointed to by the stack pointer (TOS) is moved to the destination. The stack pointer is incremented by two afterwards. Status bits are not affected. The contents of R7 and the status register are restored from the stack. POP POP R7 ; Restore R7 SR ; Restore status register The contents of RAM byte LEO is restored from the stack. POP.B LEO ; The low byte of the stack is moved to LEO. The contents of R7 is restored from the stack. POP.B R7 ; The low byte of the stack is moved to R7, ; the high byte of R7 is 00h The contents of the memory pointed to by R7 and the status register are restored from the stack. POP.B POP 0(R7) SR ; The low byte of the stack is moved to the ; the byte which is pointed to by R7 : Example: R7 = 203h ; Mem(R7) = low byte of system stack : Example: R7 = 20Ah ; Mem(R7) = low byte of system stack ; Last word on stack moved to the SR Note: The System Stack Pointer The system stack pointer (SP) is always incremented by two, independent of the byte suffix. 3-54 RISC 16-Bit CPU PUSH[.W] PUSH.B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Push word onto stack Push byte onto stack PUSH PUSH.B src or PUSH.W src src SP − 2 → SP src → @SP The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS). Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The contents of the status register and R8 are saved on the stack. PUSH SR PUSH R8 ; save status register ; save R8 The contents of the peripheral TCDAT is saved on the stack. PUSH.B &TCDAT ; save data from 8-bit peripheral module, ; address TCDAT, onto stack Note: The System Stack Pointer The system stack pointer (SP) is always decremented by two, independent of the byte suffix. RISC 16-Bit CPU 3-55 Instruction Set * RET Syntax Operation Emulation Description Status Bits Return from subroutine RET @SP→ PC SP + 2 → SP MOV @SP+,PC The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call. Status bits are not affected. 3-56 RISC 16-Bit CPU Instruction Set RETI Syntax Operation Description Status Bits Mode Bits Example Return from interrupt RETI TOS SP + 2 TOS SP + 2 → SR → SP → PC → SP The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two. The program counter is restored to the value at the beginning of interrupt service. This is the consecutive step after the interrupted program flow. Restoration is performed by replacing the present PC contents with the TOS memory contents. The stack pointer (SP) is incremented. N: restored from system stack Z: restored from system stack C: restored from system stack V: restored from system stack OSCOFF, CPUOFF, and GIE are restored from system stack. Figure 3−13 illustrates the main program interrupt. Figure 3−13. Main Program Interrupt PC −6 PC −4 PC −2 PC PC +2 PC +4 PC +6 PC +8 Interrupt Request Interrupt Accepted PC+2 is Stored Onto Stack PC = PCi PCi +2 PCi +4 PCi +n−4 PCi +n−2 PCi +n RETI RISC 16-Bit CPU 3-57 Instruction Set * RLA[.W] * RLA.B Syntax Operation Emulation Description Rotate left arithmetically Rotate left arithmetically RLA dst or RLA.W dst RLA.B dst C <− MSB <− MSB−1 .... LSB+1 <− LSB <− 0 ADD dst,dst ADD.B dst,dst The destination operand is shifted left one position as shown in Figure 3−14. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2. An overflow occurs if dst ≥ 04000h and dst < 0C000h before operation is performed: the result has changed sign. Figure 3−14. Destination Operand—Arithmetic Shift Left Word 15 C Byte 7 0 0 0 Status Bits Mode Bits Example Example An overflow occurs if dst ≥ 040h and dst < 0C0h before the operation is performed: the result has changed sign. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R7 is multiplied by 2. RLA R7 ; Shift left R7 (× 2) The low byte of R7 is multiplied by 4. RLA.B R7 RLA.B R7 ; Shift left low byte of R7 (× 2) ; Shift left low byte of R7 (× 4) Note: RLA Substitution The assembler does not recognize the instruction: RLA @R5+, RLA.B @R5+, or It must be substituted by: ADD @R5+,−2(R5) ADD.B @R5+,−1(R5) or RLA(.B) @R5 ADD(.B) @R5 3-58 RISC 16-Bit CPU Instruction Set * RLC[.W] * RLC.B Syntax Operation Emulation Description Rotate left through carry Rotate left through carry RLC dst or RLC.W dst RLC.B dst C <− MSB <− MSB−1 .... LSB+1 <− LSB <− C ADDC dst,dst The destination operand is shifted left one position as shown in Figure 3−15. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C). Figure 3−15. Destination Operand—Carry Left Shift Word 15 0 C Byte 7 0 Status Bits Mode Bits Example Example Example N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R5 is shifted left one position. RLC R5 ; (R5 x 2) + C −> R5 The input P1IN.1 information is shifted into the LSB of R5. BIT.B RLC #2,&P1IN R5 ; Information −> Carry ; Carry=P0in.1 −> LSB of R5 The MEM(LEO) content is shifted left one position. RLC.B LEO ; Mem(LEO) x 2 + C −> Mem(LEO) Note: RLC and RLC.B Substitution The assembler does not recognize the instruction: RLC @R5+, RLC.B @R5+, or RLC(.B) @R5 It must be substituted by: ADDC @R5+,−2(R5) ADDC.B @R5+,−1(R5) or ADDC(.B) @R5 RISC 16-Bit CPU 3-59 Instruction Set RRA[.W] RRA.B Syntax Operation Description Rotate right arithmetically Rotate right arithmetically RRA dst or RRA.B dst RRA.W dst MSB −> MSB, MSB −> MSB−1, ... LSB+1 −> LSB, LSB −> C The destination operand is shifted right one position as shown in Figure 3−16. The MSB is shifted into the MSB, the MSB is shifted into the MSB−1, and the LSB+1 is shifted into the LSB. Figure 3−16. Destination Operand—Arithmetic Right Shift Word 15 0 C Byte 15 0 Status Bits Mode Bits Example ; ; Example N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. R5 is shifted right one position. The MSB retains the old value. It operates equal to an arithmetic division by 2. RRA R5 ; R5/2 −> R5 The value in R5 is multiplied by 0.75 (0.5 + 0.25). PUSH RRA ADD RRA ...... R5 R5 @SP+,R5 R5 ; Hold R5 temporarily using stack ; R5 × 0.5 −> R5 ; R5 × 0.5 + R5 = 1.5 × R5 −> R5 ; (1.5 × R5) × 0.5 = 0.75 × R5 −> R5 The low byte of R5 is shifted right one position. The MSB retains the old value. It operates equal to an arithmetic division by 2. RRA.B PUSH.B RRA.B ADD.B ...... R5 R5 @SP @SP+,R5 ; R5/2 −> R5: operation is on low byte only ; High byte of R5 is reset ; R5 × 0.5 −> TOS ; TOS × 0.5 = 0.5 × R5 × 0.5 = 0.25 × R5 −> TOS ; R5 × 0.5 + R5 × 0.25 = 0.75 × R5 −> R5 3-60 RISC 16-Bit CPU Instruction Set RRC[.W] RRC.B Syntax Operation Description Rotate right through carry Rotate right through carry RRC dst or RRC dst RRC.W dst C −> MSB −> MSB−1 .... LSB+1 −> LSB −> C The destination operand is shifted right one position as shown in Figure 3−17. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C). Figure 3−17. Destination Operand—Carry Right Shift Word 15 0 C Byte 7 0 Status Bits Mode Bits Example Example N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. R5 is shifted right one position. The MSB is loaded with 1. SETC RRC R5 ; Prepare carry for MSB ; R5/2 + 8000h −> R5 R5 is shifted right one position. The MSB is loaded with 1. SETC RRC.B R5 ; Prepare carry for MSB ; R5/2 + 80h −> R5; low byte of R5 is used RISC 16-Bit CPU 3-61 Instruction Set * SBC[.W] * SBC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Subtract source and borrow/.NOT. carry from destination Subtract source and borrow/.NOT. carry from destination SBC dst or SBC.B dst SBC.W dst dst + 0FFFFh + C −> dst dst + 0FFh + C −> dst SUBC #0,dst SUBC.B #0,dst The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, reset otherwise. OSCOFF, CPUOFF, and GIE are not affected. The 16-bit counter pointed to by R13 is subtracted from a 32-bit counter pointed to by R12. SUB SBC @R13,0(R12) 2(R12) ; Subtract LSDs ; Subtract carry from MSD The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUB.B SBC.B @R13,0(R12) 1(R12) ; Subtract LSDs ; Subtract carry from MSD Note: Borrow Implementation. The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1 3-62 RISC 16-Bit CPU * SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB Instruction Set Set carry bit SETC 1 −> C BIS #1,SR The carry bit (C) is set. N: Not affected Z: Not affected C: Set V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Emulation of the decimal subtraction: Subtract R5 from R6 decimally Assume that R5 = 03987h and R6 = 04137h ADD #06666h,R5 INV R5 SETC DADD R5,R6 ; Move content R5 from 0−9 to 6−0Fh ; R5 = 03987h + 06666h = 09FEDh ; Invert this (result back to 0−9) ; R5 = .NOT. R5 = 06012h ; Prepare carry = 1 ; Emulate subtraction by addition of: ; (010000h − R5 − 1) ; R6 = R6 + R5 + 1 ; R6 = 0150h RISC 16-Bit CPU 3-63 Instruction Set * SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1 −> N BIS #4,SR The negative bit (N) is set. N: Set Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. 3-64 RISC 16-Bit CPU * SETZ Syntax Operation Emulation Description Status Bits Mode Bits Set zero bit SETZ 1 −> Z BIS #2,SR The zero bit (Z) is set. N: Not affected Z: Set C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Instruction Set RISC 16-Bit CPU 3-65 Instruction Set SUB[.W] SUB.B Syntax Operation Description Status Bits Mode Bits Example Example Subtract source from destination Subtract source from destination SUB src,dst SUB.B src,dst or SUB.W src,dst dst + .NOT.src + 1 −> dst or [(dst − src −> dst)] The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the constant 1. The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. See example at the SBC instruction. See example at the SBC.B instruction. Note: Borrow Is Treated as a .NOT. The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1 3-66 RISC 16-Bit CPU SUBC[.W]SBB[.W] SUBC.B,SBB.B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Subtract source and borrow/.NOT. carry from destination Subtract source and borrow/.NOT. carry from destination SUBC src,dst SBB src,dst SUBC.B src,dst or SUBC.W or SBB.W or SBB.B src,dst or src,dst src,dst dst + .NOT.src + C −> dst or (dst − src − 1 + C −> dst) The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the carry bit (C). The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive. Z: Set if result is zero, reset otherwise. C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, reset otherwise. OSCOFF, CPUOFF, and GIE are not affected. Two floating point mantissas (24 bits) are subtracted. LSBs are in R13 and R10, MSBs are in R12 and R9. SUB.W R13,R10 ; 16-bit part, LSBs SUBC.B R12,R9 ; 8-bit part, MSBs The 16-bit counter pointed to by R13 is subtracted from a 16-bit counter in R10 and R11(MSD). SUB.B @R13+,R10 SUBC.B @R13,R11 ... ; Subtract LSDs without carry ; Subtract MSDs with carry ; resulting from the LSDs Note: Borrow Implementation The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1 RISC 16-Bit CPU 3-67 Instruction Set SWPB Syntax Operation Description Status Bits Mode Bits Swap bytes SWPB dst Bits 15 to 8 <−> bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure 3−18. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Figure 3−18. Destination Operand Byte Swap 15 87 0 Example Example MOV #040BFh,R7 SWPB R7 ; 0100000010111111 −> R7 ; 1011111101000000 in R7 The value in R5 is multiplied by 256. The result is stored in R5,R4. SWPB MOV BIC BIC R5 R5,R4 #0FF00h,R5 #00FFh,R4 ; ;Copy the swapped value to R4 ;Correct the result ;Correct the result 3-68 RISC 16-Bit CPU Instruction Set SXT Syntax Operation Description Status Bits Mode Bits Extend Sign SXT dst Bit 7 −> Bit 8 ......... Bit 15 The sign of the low byte is extended into the high byte as shown in Figure 3−19. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT. Zero) V: Reset OSCOFF, CPUOFF, and GIE are not affected. Figure 3−19. Destination Operand Sign Extension 15 87 0 Example R7 is loaded with the P1IN value. The operation of the sign-extend instruction expands bit 8 to bit 15 with the value of bit 7. R7 is then added to R6. MOV.B &P1IN,R7 SXT R7 ; P1IN = 080h: ; R7 = 0FF80h: . . . . . . . . 1000 0000 1111 1111 1000 0000 RISC 16-Bit CPU 3-69 Instruction Set * TST[.W] * TST.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Test destination Test destination TST TST.B dst or TST.W dst dst dst + 0FFFFh + 1 dst + 0FFh + 1 CMP CMP.B #0,dst #0,dst The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. TST JN JZ R7POS ...... R7NEG ...... R7ZERO ...... R7 R7NEG R7ZERO ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TST.B JN JZ ...... ..... ...... R7 R7NEG R7ZERO ; Test low byte of R7 ; Low byte of R7 is negative ; Low byte of R7 is zero ; Low byte of R7 is positive but not zero ; Low byte of R7 is negative ; Low byte of R7 is zero 3-70 RISC 16-Bit CPU XOR[.W] XOR.B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Exclusive OR of source with destination Exclusive OR of source with destination XOR XOR.B src,dst or src,dst XOR.W src,dst src .XOR. dst −> dst The source and destination operands are exclusive ORed. The result is placed into the destination. The source operand is not affected. N: Set if result MSB is set, reset if not set Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if both operands are negative OSCOFF, CPUOFF, and GIE are not affected. The bits set in R6 toggle the bits in the RAM word TONI. XOR R6,TONI ; Toggle bits of word TONI on the bits set in R6 The bits set in R6 toggle the bits in the RAM byte TONI. XOR.B R6,TONI ; Toggle bits of byte TONI on the bits set in ; low byte of R6 Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE. XOR.B EDE,R7 INV.B R7 ; Set different bit to “1s” ; Invert Lowbyte, Highbyte is 0h RISC 16-Bit CPU 3-71 Instruction Set 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK. Interrupt and Reset Cycles Table 3−14 lists the CPU cycles for interrupt overhead and reset. Table 3−14.Interrupt and Reset Cycles Action Return from interrupt (RETI) Interrupt accepted WDT reset Reset (RST/NMI) No. of Cycles 5 6 4 4 Length of Instruction 1 − − − Format-II (Single Operand) Instruction Cycles and Lengths Table 3−15 lists the length and CPU cycles for all addressing modes of format-II instructions. Table 3−15.Format-II Instruction Cycles and Lengths Addressing Mode Rn No. of Cycles RRA, RRC SWPB, SXT PUSH 1 3 CALL 4 @Rn 3 4 4 @Rn+ 3 5 5 #N (See note) 4 5 X(Rn) 4 5 5 EDE 4 5 5 &EDE 4 5 5 Length of Instruction 1 1 1 2 2 2 2 Example SWPB R5 RRC @R9 SWPB @R10+ CALL #0F00h CALL 2(R7) PUSH EDE SXT &EDE Note: Instruction Format II Immediate Mode Do not use instructions RRA, RRC, SWPB, and SXT with the immediate mode in the destination field. Use of these in the immediate mode results in an unpredictable program operation. Format-III (Jump) Instruction Cycles and Lengths All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not. 3-72 RISC 16-Bit CPU Instruction Set Format-I (Double Operand) Instruction Cycles and Lengths Table 3−16 lists the length and CPU cycles for all addressing modes of format-I instructions. Table 3−16.Format I Instruction Cycles and Lengths Addressing Mode Src Dst Rn Rm PC x(Rm) EDE &EDE @Rn Rm PC x(Rm) EDE &EDE @Rn+ Rm PC x(Rm) EDE &EDE #N Rm PC x(Rm) EDE &EDE x(Rn) Rm PC TONI x(Rm) &TONI EDE Rm PC TONI x(Rm) &TONI &EDE Rm PC TONI x(Rm) &TONI No. of Cycles 1 2 4 4 4 2 2 5 5 5 2 3 5 5 5 2 3 5 5 5 3 3 6 6 6 3 3 6 6 6 3 3 6 6 6 Length of Instruction 1 MOV 1 BR 2 ADD 2 XOR 2 MOV 1 AND 1 BR 2 XOR 2 MOV 2 XOR 1 ADD 1 BR 2 XOR 2 MOV 2 MOV 2 MOV 2 BR 3 MOV 3 ADD 3 ADD 2 MOV 2 BR 3 MOV 3 ADD 3 MOV 2 AND 2 BR 3 CMP 3 MOV 3 MOV 2 MOV 2 BRA 3 MOV 3 MOV 3 MOV Example R5,R8 R9 R5,4(R6) R8,EDE R5,&EDE @R4,R5 @R8 @R5,8(R6) @R5,EDE @R5,&EDE @R5+,R6 @R9+ @R5,8(R6) @R9+,EDE @R9+,&EDE #20,R9 #2AEh #0300h,0(SP) #33,EDE #33,&EDE 2(R5),R7 2(R6) 4(R7),TONI 4(R4),6(R9) 2(R4),&TONI EDE,R6 EDE EDE,TONI EDE,0(SP) EDE,&TONI &EDE,R8 &EDE &EDE,TONI &EDE,0(SP) &EDE,&TONI RISC 16-Bit CPU 3-73 Instruction Set 3.4.5 Instruction Set Description The instruction map is shown in Figure 3−20 and the complete instruction set is summarized in Table 3−17. Figure 3−20. Core Instruction Map 000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0 0xxx 4xxx 8xxx Cxxx 1xxx RRC RRC.B SWPB RRA RRA.B SXT PUSH PUSH.B CALL RETI 14xx 18xx 1Cxx 20xx JNE/JNZ 24xx 28xx JEQ/JZ JNC 2Cxx JC 30xx JN 34xx 38xx 3Cxx JGE JL JMP 4xxx MOV, MOV.B 5xxx 6xxx ADD, ADD.B ADDC, ADDC.B 7xxx SUBC, SUBC.B 8xxx 9xxx SUB, SUB.B CMP, CMP.B Axxx DADD, DADD.B Bxxx BIT, BIT.B Cxxx Dxxx Exxx Fxxx BIC, BIC.B BIS, BIS.B XOR, XOR.B AND, AND.B 3-74 RISC 16-Bit CPU Table 3−17.MSP430 Instruction Set Mnemonic ADC(.B)† dst ADD(.B) src,dst ADDC(.B) src,dst AND(.B) src,dst BIC(.B) src,dst BIS(.B) src,dst BIT(.B) BR† src,dst dst CALL dst CLR(.B)† dst CLRC† CLRN† CLRZ† CMP(.B) src,dst DADC(.B)† dst DADD(.B) DEC(.B)† DECD(.B)† DINT† EINT† INC(.B)† INCD(.B)† INV(.B)† src,dst dst dst dst dst dst JC/JHS label JEQ/JZ label JGE label JL label JMP label JN label JNC/JLO label JNE/JNZ label MOV(.B) NOP† POP(.B)† src,dst dst PUSH(.B) src RET† RETI RLA(.B)† dst RLC(.B)† dst RRA(.B) dst RRC(.B) dst SBC(.B)† dst SETC† SETN† SETZ† SUB(.B) src,dst SUBC(.B) src,dst SWPB dst SXT dst TST(.B)† dst XOR(.B) src,dst † Emulated Instruction Description Add C to destination Add source to destination Add source and C to destination AND source and destination Clear bits in destination Set bits in destination Test bits in destination Branch to destination Call destination Clear destination Clear C Clear N Clear Z Compare source and destination Add C decimally to destination Add source and C decimally to dst. Decrement destination Double-decrement destination Disable interrupts Enable interrupts Increment destination Double-increment destination Invert destination Jump if C set/Jump if higher or same Jump if equal/Jump if Z set Jump if greater or equal Jump if less Jump Jump if N set Jump if C not set/Jump if lower Jump if not equal/Jump if Z not set Move source to destination No operation Pop item from stack to destination Push source onto stack Return from subroutine Return from interrupt Rotate left arithmetically Rotate left through C Rotate right arithmetically Rotate right through C Subtract not(C) from destination Set C Set N Set Z Subtract source from destination Subtract source and not(C) from dst. Swap bytes Extend sign Test destination Exclusive OR source and destination Instruction Set VNZC dst + C → dst **** src + dst → dst **** src + dst + C → dst **** src .and. dst → dst 0* * * .not.src .and. dst → dst −−−− src .or. dst → dst −−−− src .and. dst 0* * * dst → PC −−−− PC+2 → stack, dst → PC −−−− 0 → dst −−−− 0→C −−−0 0→N −0−− 0→Z −−0− dst − src **** dst + C → dst (decimally) **** src + dst + C → dst (decimally) * * * * dst − 1 → dst **** dst − 2 → dst **** 0 → GIE −−−− 1 → GIE −−−− dst +1 → dst **** dst+2 → dst **** .not.dst → dst **** −−−− −−−− −−−− −−−− PC + 2 x offset → PC −−−− −−−− −−−− −−−− src → dst −−−− −−−− @SP → dst, SP+2 → SP −−−− SP − 2 → SP, src → @SP −−−− @SP → PC, SP + 2 → SP −−−− **** **** **** 0* * * **** dst + 0FFFFh + C → dst **** 1→C −−−1 1→N −1−− 1→C −−1− dst + .not.src + 1 → dst **** dst + .not.src + C → dst **** −−−− 0* * * dst + 0FFFFh + 1 0* *1 src .xor. dst → dst **** RISC 16-Bit CPU 3-75 3-76 RISC 16-Bit CPU Chapter 4 16-Bit MSP430X CPU This chapter describes the extended MSP430X 16-bit RISC CPU with 1-MB memory access, its addressing modes, and instruction set. The MSP430X CPU is implemented in all MSP430 devices that exceed 64-KB of address space. Topic Page 4.1 CPU Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.5 MSP430 and MSP430X Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 4.6 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58 16-Bit MSP430X CPU 4-1 CPU Introduction 4.1 CPU Introduction The MSP430X CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The MSP430X CPU can address a 1-MB address range without paging. In addition, the MSP430X CPU has fewer interrupt overhead cycles and fewer instruction cycles in some cases than the MSP430 CPU, while maintaining the same or better code density than the MSP430 CPU. The MSP430X CPU is completely backwards compatible with the MSP430 CPU. The MSP430X CPU features include: - RISC architecture. - Orthogonal architecture. - Full register access including program counter, status register and stack pointer. - Single-cycle register operations. - Large register file reduces fetches to memory. - 20-bit address bus allows direct access and branching throughout the entire memory range without paging. - 16-bit data bus allows direct manipulation of word-wide arguments. - Constant generator provides the six most often used immediate values and reduces code size. - Direct memory-to-memory transfers without intermediate register holding. - Byte, word, and 20-bit address-word addressing The block diagram of the MSP430X CPU is shown in Figure 4−1. 4-2 16-Bit MSP430X CPU Figure 4−1. MSP430X CPU Block Diagram MDB − Memory Data Bus Memory Address Bus − MAB 19 16 15 0 R0/PC Program Counter 0 R1/SP Pointer Stack 0 R2/SR Status Register R3/CG2 Constant Generator R4 General Purpose R5 General Purpose R6 General Purpose R7 General Purpose R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14 General Purpose R15 General Purpose 16 Zero, Z Carry, C Overflow,V Negative,N dst src 16/20−bit ALU 20 MCLK CPU Introduction 16-Bit MSP430X CPU 4-3 Interrupts 4.2 Interrupts The MSP430X uses the same interrupt structure as the MSP430: - Vectored interrupts with no polling necessary - Interrupt vectors are located downward from address 0FFFEh Interrupt operation for both MSP430 and MSP430X CPUs is described in Chapter 2 System Resets, Interrupts, and Operating modes, Section 2 Interrupts. The interrupt vectors contain 16-bit addresses that point into the lower 64-KB memory. This means all interrupt handlers must start in the lower 64-KB memory − even in MSP430X devices. During an interrupt, the program counter and the status register are pushed onto the stack as shown in Figure 4−2. The MSP430X architecture efficiently stores the complete 20-bit PC value by automatically appending the PC bits 19:16 to the stored SR value on the stack. When the RETI instruction is executed, the full 20-bit PC is restored making return from interrupt to any address in the memory range possible. Figure 4−2. Program Counter Storage on the Stack for Interrupts SPold SP PC.19:16 Item n−1 PC.15:0 SR.11:0 4-4 16-Bit MSP430X CPU CPU Registers 4.3 CPU Registers The CPU incorporates sixteen registers R0 to R15. Registers R0, R1, R2, and R3 have dedicated functions. R4 to R15 are working registers for general use. 4.3.1 The Program Counter PC The 20-bit program counter (PC/R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (two, four, six or eight bytes), and the PC is incremented accordingly. Instruction accesses are performed on word boundaries, and the PC is aligned to even addresses. Figure 4−3 shows the program counter. Figure 4−3. Program Counter PC 19 16 15 Program Counter Bits 19 to 1 10 0 The PC can be addressed with all instructions and addressing modes. A few examples: MOV.W #LABEL,PC ; Branch to address LABEL (lower 64 KB) MOVA #LABEL,PC ; Branch to address LABEL (1MB memory) MOV.W LABEL,PC ; Branch to address in word LABEL ; (lower 64 KB) MOV.W @R14,PC ; Branch indirect to address in ; R14 (lower 64 KB) ADDA #4,PC ; Skip two words (1 MB memory) The BR and CALL instructions reset the upper four PC bits to 0. Only addresses in the lower 64-KB address range can be reached with the BR or CALL instruction. When branching or calling, addresses beyond the lower 64-KB range can only be reached using the BRA or CALLA instructions. Also, any instruction to directly modify the PC does so according to the used addressing mode. For example, MOV.W #value,PC will clear the upper four bits of the PC because it is a .W instruction. 16-Bit MSP430X CPU 4-5 CPU Registers The program counter is automatically stored on the stack with CALL, or CALLA instructions, and during an interrupt service routine. Figure 4−4 shows the storage of the program counter with the return address after a CALLA instruction. A CALL instruction stores only bits 15:0 of the PC. Figure 4−4. Program Counter Storage on the Stack for CALLA SPold SP Item n PC.19:16 PC.15:0 The RETA instruction restores bits 19:0 of the program counter and adds 4 to the stack pointer. The RET instruction restores bits 15:0 to the program counter and adds 2 to the stack pointer. 4-6 16-Bit MSP430X CPU CPU Registers 4.3.2 Stack Pointer (SP) The 20-bit stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes. Figure 4−5 shows the SP. The SP is initialized into RAM by the user, and is always aligned to even addresses. Figure 4−6 shows the stack usage. Figure 4−7 shows the stack usage when 20-bit address-words are pushed. Figure 4−5. Stack Pointer 19 Stack Pointer Bits 19 to 1 10 0 MOV.W 2(SP),R6 MOV.W R7,0(SP) PUSH #0123h POP R8 Figure 4−6. Stack Usage Address 0xxxh I1 0xxxh − 2 I2 0xxxh − 4 I3 0xxxh − 6 0xxxh − 8 ; Copy Item I2 to R6 ; Overwrite TOS with R7 ; Put 0123h on stack ; R8 = 0123h PUSH #0123h POP R8 I1 I1 I2 I2 SP I3 I3 SP 0123h SP Figure 4−7. PUSHX.A Format on the Stack SPold SP Item n−1 Item.19:16 Item.15:0 16-Bit MSP430X CPU 4-7 CPU Registers The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 4−8. Figure 4−8. PUSH SP - POP SP Sequence PUSH SP POP SP SPold SP1 SP1 SP2 SP1 The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction. instruction. The POP SP instruction places SP1 into the stack pointer SP (SP2=SP1) 4-8 16-Bit MSP430X CPU CPU Registers 4.3.3 Status Register (SR) The 16-bit status register (SR/R2), used as a source or destination register, can only be used in register mode addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator. Figure 4−9 shows the SR bits. Do not write 20-bit values to the SR. Unpredictable operation can result. Figure 4−9. Status Register Bits 15 Reserved 98 7 0 V SCG1 SCG0 OSC CPU OFF OFF GIE N ZC rw-0 Table 4−1 describes the status register bits. Table 4−1. Description of Status Register Bits Bit Description Reserved Reserved V Overflow bit. This bit is set when the result of an arithmetic operation overflows the signed-variable range. ADD(.B), ADDX(.B,.A), ADDC(.B), ADDCX(.B.A), ADDA Set when: positive + positive = negative negative + negative = positive otherwise reset SUB(.B), SUBX(.B,.A), SUBC(.B),SUBCX(.B,.A), SUBA, CMP(.B), CMPX(.B,.A), CMPA Set when: positive − negative = negative negative − positive = positive otherwise reset SCG1 System clock generator 1. This bit, when set, turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK. SCG0 System clock generator 0. This bit, when set, turns off the FLL+ loop control. OSCOFF Oscillator Off. This bit, when set, turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or SMCLK. CPUOFF CPU off. This bit, when set, turns off the CPU. GIE General interrupt enable. This bit, when set, enables maskable inter- rupts. When reset, all maskable interrupts are disabled. N Negative bit. This bit is set when the result of an operation is negative and cleared when the result is positive. 16-Bit MSP430X CPU 4-9 CPU Registers Bit Description Z Zero bit. This bit is set when the result of an operation is zero and cleared when the result is not zero. C Carry bit. This bit is set when the result of an operation produced a carry and cleared when no carry occurred. 4-10 16-Bit MSP430X CPU CPU Registers 4.3.4 The Constant Generator Registers CG1 and CG2 Six commonly used constants are generated with the constant generator registers R2 (CG1) and R3 (CG2), without requiring an additional 16-bit word of program code. The constants are selected with the source register addressing modes (As), as described in Table 4−2. Table 4−2. Values of Constant Generators CG1, CG2 Register R2 R2 R2 R2 R3 R3 R3 R3 As Constant 00 - 01 (0) 10 00004h 11 00008h 00 00000h 01 00001h 10 00002h 11 FFh, FFFFh, FFFFFh Remarks Register mode Absolute address mode +4, bit processing +8, bit processing 0, word processing +1 +2, bit processing -1, word processing The constant generator advantages are: - No special instructions required - No additional code word for the six constants - No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as source-only registers. Constant Generator − Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions. However, the constant generator allows the MSP430 assembler to support 24 additional, emulated instructions. For example, the single-operand instruction: CLR dst is emulated by the double-operand instruction with the same length: MOV R3,dst where the #0 is replaced by the assembler, and R3 is used with As=00. INC dst is replaced by: ADD 0(R3),dst 16-Bit MSP430X CPU 4-11 CPU Registers 4.3.5 The General Purpose Registers R4 to R15 The twelve CPU registers R4 to R15, contain 8-bit, 16-bit, or 20-bit values. Any byte-write to a CPU register clears bits 19:8. Any word-write to a register clears bits 19:16. The only exception is the SXT instruction. The SXT instruction extends the sign through the complete 20-bit register. The following figures show the handling of byte, word and address-word data. Note the reset of the leading MSBs, if a register is the destination of a byte or word instruction. Figure 4−10 shows byte handling (8-bit data, .B suffix). The handling is shown for a source register and a destination memory byte and for a source memory byte and a destination register. Figure 4−10. Register-Byte/Byte-Register Operation Register-Byte Operation High Byte Low Byte 19 16 15 87 0 Unused Unused Register Byte-Register Operation High Byte Low Byte Memory Memory 19 16 15 87 Unused Unused 0 Register Operation Operation Memory 0 0 Register 4-12 16-Bit MSP430X CPU CPU Registers Figure 4−11 and Figure 4−12 show 16-bit word handling (.W suffix). The handling is shown for a source register and a destination memory word and for a source memory word and a destination register. Figure 4−11. Register-Word Operation Register-Word Operation High Byte Low Byte 19 16 15 87 0 Unused Register Memory Operation Memory Figure 4−12. Word-Register Operation Word-Register Operation High Byte Low Byte Memory 19 16 15 87 Un- used 0 Register Operation 0 Register 16-Bit MSP430X CPU 4-13 CPU Registers Figure 4−13 and Figure 4−14 show 20-bit address-word handling (.A suffix). The handling is shown for a source register and a destination memory address-word and for a source memory address-word and a destination register. Figure 4−13. Register − Address-Word Operation Register − Address-Word Operation High Byte Low Byte 19 16 15 87 0 Register Memory +2 Unused Memory Operation Memory +2 0 Memory Figure 4−14. Address-Word − Register Operation Address-Word − Register Operation High Byte Low Byte 19 16 15 87 0 Memory +2 Unused Memory Register Operation Register 4-14 16-Bit MSP430X CPU CPU Registers 4.4 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand use 16-bit or 20-bit addresses. The MSP430 and MSP430X instructions are usable throughout the entire 1-MB memory range. Table 4−3. Source/Destination Addressing As/Ad 00/0 01/1 Addressing Mode Register mode Indexed mode 01/1 Symbolic mode 01/1 Absolute mode 10/− 11/− Indirect register mode Indirect autoincrement 11/− Immediate mode Syntax Rn X(Rn) ADDR &ADDR @Rn @Rn+ #N Description Register contents are operand (Rn + X) points to the operand. X is stored in the next word, or stored in combination of the preceding extension word and the next word. (PC + X) points to the operand. X is stored in the next word, or stored in combination of the preceding extension word and the next word. Indexed mode X(PC) is used. The word following the instruction contains the absolute address. X is stored in the next word, or stored in combination of the preceding extension word and the next word. Indexed mode X(SR) is used. Rn is used as a pointer to the operand. Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for .B instructions. by 2 for .W instructions, and by 4 for .A instructions. N is stored in the next word, or stored in combination of the preceding extension word and the next word. Indirect autoincrement mode @PC+ is used. The seven addressing modes are explained in detail in the following sections. Most of the examples show the same addressing mode for the source and destination, but any valid combination of source and destination addressing modes is possible in an instruction. Note: Use of Labels EDE, TONI, TOM, and LEO Throughout MSP430 documentation EDE, TONI, TOM, and LEO are used as generic labels. They are only labels. They have no special meaning. 16-Bit MSP430X CPU 4-15 CPU Registers 4.4.1 Register Mode Operation: The operand is the 8-, 16-, or 20-bit content of the used CPU register. Length: One, two, or three words Comment: Valid for source and destination Byte operation: Byte operation reads only the 8 LSBs of the source register Rsrc and writes the result to the 8 LSBs of the destination register Rdst. The bits Rdst.19:8 are cleared. The register Rsrc is not modified. Word operation:Word operation reads the 16 LSBs of the source register Rsrc and writes the result to the 16 LSBs of the destination register Rdst. The bits Rdst.19:16 are cleared. The register Rsrc is not modified. Address-Word operation: Address-word operation reads the 20 bits of the source register Rsrc and writes the result to the 20 bits of the destination register Rdst. The register Rsrc is not modified SXT Exception: The SXT instruction is the only exception for register operation. The sign of the low byte in bit 7 is extended to the bits Rdst.19:8. Example: BIS.W R5,R6 ; This instruction logically ORs the 16-bit data contained in R5 with the 16-bit contents of R6. R6.19:16 is cleared. Before: Address Space Register After: Address Space Register 21036h xxxxh R5 AA550h 21034h D506h PC R6 11111h 21036h 21034h xxxxh D506h PC R5 AA550h R6 0B551h A550h.or.1111h = B551h 4-16 16-Bit MSP430X CPU CPU Registers Example: BISX.A R5,R6 ; This instruction logically ORs the 20-bit data contained in R5 with the 20-bit contents of R6. The extension word contains the A/L-bit for 20-bit data. The instruction word uses byte mode with bits A/L:B/W = 01. The result of the instruction is: Before: Address Space Register After: Address Space Register 21036h 21034h 21032h xxxxh D546h 1800h R5 AA550h R6 11111h PC 21036h 21034h 21032h xxxxh D546h 1800h PC R5 AA550h R6 BB551h AA550h.or.11111h = BB551h 16-Bit MSP430X CPU 4-17 CPU Registers 4.4.2 Indexed Mode The Indexed mode calculates the address of the operand by adding the signed index to a CPU register. The Indexed mode has three addressing possibilities: - Indexed mode in lower 64-KB memory - MSP430 instruction with Indexed mode addressing memory above the lower 64-KB memory. - MSP430X instruction with Indexed mode Indexed Mode in Lower 64 KB Memory If the CPU register Rn points to an address in the lower 64 KB of the memory range, the calculated memory address bits 19:16 are cleared after the addition of the CPU register Rn and the signed 16-bit index. This means, the calculated memory address is always located in the lower 64 KB and does not overflow or underflow out of the lower 64-KB memory space. The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4−15. Figure 4−15. Indexed Mode in Lower 64 KB FFFFF Lower 64 KB. Rn.19:16 = 0 19 16 15 0 0 CPU Register Rn 10000 ÇÇÇÇÇ 0FFFF ÇÇÇÇÇ Rn.19:0 ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ 00000 Lower 64KB S 16-bit byte index 16-bit signed index 16-bit signed add 0 Memory address Length: Operation: Comment: Two or three words The signed 16-bit index is located in the next word after the instruction and is added to the CPU register Rn. The resulting bits 19:16 are cleared giving a truncated 16-bit memory address, which points to an operand address in the range 00000h to 0FFFFh. The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the register index and inserts it. 4-18 16-Bit MSP430X CPU CPU Registers Example: ADD.B 1000h(R5),0F000h(R6); The previous instruction adds the 8-bit data contained in source byte 1000h(R5) and the destination byte 0F000h(R6) and places the result into the destination byte. Source and destination bytes are both located in the lower 64 KB due to the cleared bits 19:16 of registers R5 and R6. Source: The byte pointed to by R5 + 1000h results in address 0479Ch + 1000h = 0579Ch after truncation to a 16-bit address. Destination: The byte pointed to by R6 + F000h results in address 01778h + F000h = 00778h after truncation to a 16-bit address. Before: Address Space Register After: Address Space Register 1103Ah 11038h 11036h 11034h xxxxh F000h 1000h 55D6h R5 0479Ch R6 01778h PC 1103Ah 11038h 11036h 11034h xxxxh F000h 1000h 55D6h PC R5 0479Ch R6 01778h 0077Ah 00778h xxxxh xx45h 01778h +F000h 00778h 0077Ah 00778h xxxxh xx77h 32h +45h 77h src dst Sum 0579Eh 0579Ch xxxxh xx32h 0479Ch +1000h 0579Ch 0579Eh 0579Ch xxxxh xx32h 16-Bit MSP430X CPU 4-19 CPU Registers MSP430 Instruction with Indexed Mode in Upper Memory If the CPU register Rn points to an address above the lower 64-KB memory, the Rn bits 19:16 are used for the address calculation of the operand. The operand may be located in memory in the range Rn ±32 KB, because the index, X, is a signed 16-bit value. In this case, the address of the operand can overflow or underflow into the lower 64-KB memory space. See Figure 4−16 and Figure 4−17. Figure 4−16. Indexed Mode in Upper Memory FFFFF Upper Memory Rn.19:16 > 0 Rn.19:0 Rn ±32 KB 10000 0FFFF 19 16 15 1 ... 15 0 CPU Register Rn S S 16-bit byte index 16-bit signed index (sign extended to 20 bits) 20-bit signed add Lower 64 KB 00000 Memory address Figure 4−17. Overflow and Underflow for the Indexed Mode ÇÇÇÇÇÇÇÇÇÇÇÇ FFFFF Rn.19:0 ÇÇÇÇÇÇ ÇÇÇÇÇÇ Rn.19:0 Lower 64 KB ±32KB ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇ 10000 0,FFFF ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ Rn.19:0 ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ 0000C Rn.19:0 ±32KB 4-20 16-Bit MSP430X CPU CPU Registers Length: Two or three words Operation: The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the CPU register Rn. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh. The operand is the content of the addressed memory location. Comment: Valid for source and destination. The assembler calculates the register index and inserts it. Example: ADD.W 8346h(R5),2100h(R6); This instruction adds the 16-bit data contained in the source and the destination addresses and places the 16-bit result into the destination. Source and destination operand can be located in the entire address range. Source: The word pointed to by R5 + 8346h. The negative index 8346h is sign-extended, which results in address 23456h + F8346h = 1B79Ch. Destination: The word pointed to by R6 + 2100h results in address 15678h + 2100h = 17778h. Figure 4−18. Example for the Indexed Mode Before: Address Space Register After: Address Space Register 1103Ah 11038h 11036h 11034h xxxxh 2100h 8346h 5596h R5 23456h R6 15678h PC 1103Ah 11038h 11036h 11034h xxxxh 2100h 8346h 5596h PC R5 23456h R6 15678h 1777Ah 17778h xxxxh 2345h 15678h +02100h 17778h 1777Ah 17778h xxxxh 7777h 05432h +02345h 07777h src dst Sum 1B79Eh 1B79Ch xxxxh 5432h 23456h +F8346h 1B79Ch 1B79Eh 1B79Ch xxxxh 5432h 16-Bit MSP430X CPU 4-21 CPU Registers MSP430X Instruction with Indexed Mode When using an MSP430X instruction with Indexed mode, the operand can be located anywhere in the range of Rn ± 19 bits. Length: Three or four words Operation: The operand address is the sum of the 20-bit CPU register content and the 20-bit index. The four MSBs of the index are contained in the extension word, the 16 LSBs are contained in the word following the instruction. The CPU register is not modified. Comment: Valid for source and destination. The assembler calculates the register index and inserts it. Example: ADDX.A 12346h(R5),32100h(R6) ; This instruction adds the 20-bit data contained in the source and the destination addresses and places the result into the destination. Source: Two words pointed to by R5 + 12346h which results in address 23456h + 12346h = 3579Ch. Destination: Two words pointed to by R6 + 32100h which results in address 45678h + 32100h = 77778h. 4-22 16-Bit MSP430X CPU CPU Registers The extension word contains the MSBs of the source index and of the destination index and the A/L-bit for 20-bit data. The instruction word uses byte mode due to the 20-bit data length with bits A/L:B/W = 01. Before: Address Space Register After: Address Space Register 2103Ah 21038h 21036h 21034h 21032h xxxxh 2100h 2346h 55D6h 1883h R5 R6 PC 23456h 45678h 2103Ah 21038h 21036h 21034h 21032h xxxxh 2100h 2346h 55D6h 1883h PC R5 R6 23456h 45678h 7777Ah 77778h 0001h 2345h 45678h +32100h 77778h 7777Ah 77778h 0007h 7777h 65432h +12345h 77777h src dst Sum 3579Eh 3579Ch 0006h 5432h 23456h +12346h 3579Ch 3579Eh 3579Ch 0006h 5432h 16-Bit MSP430X CPU 4-23 CPU Registers 4.4.3 Symbolic Mode The Symbolic mode calculates the address of the operand by adding the signed index to the program counter. The Symbolic mode has three addressing possibilities: - Symbolic mode in lower 64-KB memory - MSP430 instruction with symbolic mode addressing memory above the lower 64-KB memory. - MSP430X instruction with symbolic mode Symbolic Mode in Lower 64 KB If the PC points to an address in the lower 64 KB of the memory range, the calculated memory address bits 19:16 are cleared after the addition of the PC and the signed 16-bit index. This means, the calculated memory address is always located in the lower 64 KB and does not overflow or underflow out of the lower 64-KB memory space. The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4−15. Figure 4−19. Symbolic Mode Running in Lower 64 KB FFFFF Lower 64 KB. PC.19:16 = 0 19 16 15 0 0 Program counter PC 10000 0FFFF ÇÇÇÇÇÇÇÇÇÇ PC.19:0 ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ 00000 Lower 64 KB S 16-bit byte index 16-bit signed PC index 16-bit signed add 0 Memory address Operation: The signed 16-bit index in the next word after the instruction is added temporarily to the PC. The resulting bits 19:16 are cleared giving a truncated 16-bit memory address, which points to an operand address in the range 00000h, to 0FFFFh. The operand is the content of the addressed memory location. Length: Two or three words Comment: Valid for source and destination. The assembler calculates the PC index and inserts it. Example: ADD.B EDE,TONI ; 4-24 16-Bit MSP430X CPU CPU Registers The previous instruction adds the 8-bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI. Bytes EDE and TONI and the program are located in the lower 64 KB. Source: Byte EDE located at address 0,579Ch, pointed to by PC + 4766h where the PC index 4766h is the result of 0579Ch − 01036h = 04766h. Address 01036h is the location of the index for this example. Destination: Byte TONI located at address 00778h, pointed to by PC + F740h, is the truncated 16-bit result of 00778h − 1038h = FF740h. Address 01038h is the location of the index for this example. Before: Address Space After: Address Space 0103Ah 01038h 01036h 01034h xxxxh F740h 4766h 05D0h PC 0103Ah 01038h 01036h 01034h xxxxh PC F740h 4766h 50D0h 0077Ah 00778h xxxxh xx45h 01038h +0F740h 00778h 0077Ah 00778h xxxxh xx77h 32h +45h 77h src dst Sum 0579Eh 0579Ch xxxxh xx32h 01036h +04766h 0579Ch 0579Eh 0579Ch xxxxh xx32h 16-Bit MSP430X CPU 4-25 CPU Registers MSP430 Instruction with Symbolic Mode in Upper Memory If the PC points to an address above the lower 64-KB memory, the PC bits 19:16 are used for the address calculation of the operand. The operand may be located in memory in the range PC ±32 KB, because the index, X, is a signed 16-bit value. In this case, the address of the operand can overflow or underflow into the lower 64-KB memory space as shown in Figure 4−20 and Figure 4−21. Figure 4−20. Symbolic Mode Running in Upper Memory FFFFF Upper Memory PC.19:16 > 0 19 16 15 1 ... 15 0 Program counter PC PC.19:0 PC ±32 KB 10000 0FFFF S S 16-bit byte index 16-bit signed PC index (sign extended to 20 bits) 20-bit signed add Lower 64 KB 00000 Memory address Figure 4−21. Overflow and Underflow for the Symbolic Mode ÇÇÇÇÇÇÇÇÇÇÇÇ FFFFF PC.19:0 ÇÇÇÇÇÇ ÇÇÇÇÇÇ PC.19:0 Lower 64 KB ±32KB ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇ 10000 0FFFF ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ PC.19:0 ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ 0000C PC.19:0 ±32KB 4-26 16-Bit MSP430X CPU CPU Registers Length: Two or three words Operation: The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the PC. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh. The operand is the content of the addressed memory location. Comment: Valid for source and destination. The assembler calculates the PC index and inserts it Example: ADD.W EDE,&TONI ; This instruction adds the 16-bit data contained in source word EDE and destination word TONI and places the 16-bit result into the destination word TONI. For this example, the instruction is located at address 2,F034h. Source: Word EDE at address 3379Ch, pointed to by PC + 4766h which is the 16-bit result of 3379Ch − 2F036h = 04766h. Address 2F036h is the location of the index for this example. Destination: Word TONI located at address 00778h pointed to by the absolute address 00778h. Before: Address Space After: Address Space 2F03Ah 2F038h 2F036h 2F034h xxxxh 0778h 4766h 5092h PC 2F03Ah 2F038h 2F036h 2F034h xxxxh PC 0778h 4766h 5092h 3379Eh 3379Ch xxxxh 5432h 2F036h +04766h 3379Ch 3379Eh 3379Ch xxxxh 5432h 0077Ah 00778h xxxxh 2345h 0077Ah 00778h xxxxh 7777h 5432h +2345h 7777h src dst Sum 16-Bit MSP430X CPU 4-27 CPU Registers MSP430X Instruction with Symbolic Mode When using an MSP430X instruction with Symbolic mode, the operand can be located anywhere in the range of PC ± 19 bits. Length: Three or four words Operation: The operand address is the sum of the 20-bit PC and the 20-bit index. The four MSBs of the index are contained in the extension word, the 16 LSBs are contained in the word following the instruction. Comment: Valid for source and destination. The assembler calculates the register index and inserts it. Example: ADDX.B EDE,TONI ; The instruction adds the 8-bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI. Source: Byte EDE located at address 3579Ch, pointed to by PC + 14766h, is the 20-bit result of 3579Ch - 21036h = 14766h. Address 21036h is the address of the index in this example. Destination: Byte TONI located at address 77778h, pointed to by PC + 56740h, is the 20-bit result of 77778h - 21038h = 56740h. Address 21038h is the address of the index in this example.. Before: Address Space After: Address Space 2103Ah 21038h 21036h 21034h 21032h xxxxh 6740h 4766h 50D0h 18C5h PC 2103Ah 21038h 21036h 21034h 21032h xxxxh PC 6740h 4766h 50D0h 18C5h 7777Ah 77778h xxxxh xx45h 21038h +56740h 77778h 7777Ah 77778h xxxxh xx77h 32h +45h 77h src dst Sum 3579Eh 3579Ch xxxxh xx32h 21036h +14766h 3579Ch 3579Eh 3579Ch xxxxh xx32h 4-28 16-Bit MSP430X CPU CPU Registers 4.4.4 Absolute Mode The Absolute mode uses the contents of the word following the instruction as the address of the operand. The Absolute mode has two addressing possibilities: - Absolute mode in lower 64-KB memory - MSP430X instruction with Absolute mode 16-Bit MSP430X CPU 4-29 CPU Registers Absolute Mode in Lower 64 KB If an MSP430 instruction is used with Absolute addressing mode, the absolute address is a 16-bit value and therefore points to an address in the lower 64 KB of the memory range. The address is calculated as an index from 0 and is stored in the word following the instruction The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications. Length: Two or three words Operation: The operand is the content of the addressed memory location. Comment: Valid for source and destination. The assembler calculates the index from 0 and inserts it Example: ADD.W &EDE,&TONI ; This instruction adds the 16-bit data contained in the absolute source and destination addresses and places the result into the destination. Source: Word at address EDE Destination: Word at address TONI Before: Address Space After: Address Space 2103Ah 21038h 21036h 21034h xxxxh 7778h 579Ch 5292h PC 2103Ah 21038h 21036h 21034h xxxxh PC 7778h 579Ch 5292h 0777Ah 07778h xxxxh 2345h 0777Ah 07778h xxxxh 7777h 5432h +2345h 7777h src dst Sum 0579Eh 0579Ch xxxxh 5432h 0579Eh 0579Ch xxxxh 5432h 4-30 16-Bit MSP430X CPU CPU Registers MSP430X Instruction with Absolute Mode If an MSP430X instruction is used with Absolute addressing mode, the absolute address is a 20-bit value and therefore points to any address in the memory range. The address value is calculated as an index from 0. The four MSBs of the index are contained in the extension word, and the 16 LSBs are contained in the word following the instruction. Length: Three or four words Operation: The operand is the content of the addressed memory location. Comment: Valid for source and destination. The assembler calculates the index from 0 and inserts it Example: ADDX.A &EDE,&TONI ; This instruction adds the 20-bit data contained in the absolute source and destination addresses and places the result into the destination. Source: Two words beginning with address EDE Destination: Two words beginning with address TONI Before: Address Space After: Address Space 2103Ah 21038h 21036h 21034h 21032h xxxxh 7778h 579Ch 52D2h 1987h PC 2103Ah 21038h 21036h 21034h 21032h xxxxh PC 7778h 579Ch 52D2h 1987h 7777Ah 77778h 0001h 2345h 7777Ah 77778h 0007h 7777h 65432h +12345h 77777h src dst Sum 3579Eh 3579Ch 0006h 5432h 3579Eh 3579Ch 0006h 5432h 16-Bit MSP430X CPU 4-31 CPU Registers 4.4.5 Indirect Register Mode The Indirect Register mode uses the contents of the CPU register Rsrc as the source operand. The Indirect Register mode always uses a 20-bit address. Length: One, two, or three words Operation: The operand is the content the addressed memory location. The source register Rsrc is not modified. Comment: Valid only for the source operand. The substitute for the destination operand is 0(Rdst). Example: ADDX.W @R5,2100h(R6) This instruction adds the two 16-bit operands contained in the source and the destination addresses and places the result into the destination. Source: Word pointed to by R5. R5 contains address 3,579Ch for this example. Destination: Word pointed to by R6 + 2100h which results in address 45678h + 2100h = 7778h. Before: Address Space Register After: Address Space Register 21038h 21036h 21034h xxxxh 2100h 55A6h R5 R6 PC 3579Ch 45678h 21038h 21036h 21034h xxxxh 2100h 55A6h PC R5 3579Ch R6 45678h 4777Ah 47778h xxxxh 2345h 45678h +02100h 47778h 4777Ah 47778h xxxxh 7777h 5432h +2345h 7777h src dst Sum 3579Eh 3579Ch xxxxh 5432h R5 3579Eh 3579Ch xxxxh 5432h R5 4-32 16-Bit MSP430X CPU CPU Registers 4.4.6 Indirect, Autoincrement Mode The Indirect Autoincrement mode uses the contents of the CPU register Rsrc as the source operand. Rsrc is then automatically incremented by 1 for byte instructions, by 2 for word instructions, and by 4 for address-word instructions immediately after accessing the source operand. If the same register is used for source and destination, it contains the incremented address for the destination access. Indirect Autoincrement mode always uses 20-bit addresses. Length: One, two, or three words Operation: The operand is the content of the addressed memory location. Comment: Valid only for the source operand. Example: ADD.B @R5+,0(R6) This instruction adds the 8-bit data contained in the source and the destination addresses and places the result into the destination. Source: Byte pointed to by R5. R5 contains address 3,579Ch for this example. Destination: Byte pointed to by R6 + 0h which results in address 0778h for this example. Before: Address Space Register After: Address Space Register 21038h 21036h 21034h xxxxh 0000h 55F6h R5 R6 PC 3579Ch 00778h 21038h 21036h 21034h xxxxh 0000h 55F6h PC R5 3579Dh R6 00778h 0077Ah 00778h xxxxh xx45h 00778h +0000h 00778h 0077Ah 00778h xxxxh xx77h 32h +45h 77h src dst Sum 3579Dh 3579Ch xxh 32h R5 3579Dh 3579Ch xxh R5 xx32h 16-Bit MSP430X CPU 4-33 CPU Registers 4.4.7 Immediate Mode The Immediate mode allows accessing constants as operands by including the constant in the memory location following the instruction. The program counter PC is used with the Indirect Autoincrement mode. The PC points to the immediate value contained in the next word. After the fetching of the immediate operand, the PC is incremented by 2 for byte, word, or address-word instructions. The Immediate mode has two addressing possibilities: - 8- or 16-bit constants with MSP430 instructions - 20-bit constants with MSP430X instruction MSP430 Instructions with Immediate Mode If an MSP430 instruction is used with Immediate addressing mode, the constant is an 8- or 16-bit value and is stored in the word following the instruction. Length: Two or three words. One word less if a constant of the constant generator can be used for the immediate operand. Operation: The 16-bit immediate source operand is used together with the 16-bit destination operand. Comment: Valid only for the source operand. Example: ADD #3456h,&TONI This instruction adds the 16-bit immediate operand 3456h to the data in the destination address TONI. Source: 16-bit immediate value 3456h. Destination: Word at address TONI. Before: Address Space After: Address Space 2103Ah 21038h 21036h 21034h xxxxh 0778h 3456h 50B2h PC 2103Ah 21038h 21036h 21034h xxxxh PC 0778h 3456h 50B2h 0077Ah 00778h xxxxh 2345h 0077Ah 00778h xxxxh 579Bh 3456h +2345h 579Bh src dst Sum 4-34 16-Bit MSP430X CPU CPU Registers MSP430X Instructions with Immediate Mode If an MSP430X instruction is used with immediate addressing mode, the constant is a 20-bit value. The 4 MSBs of the constant are stored in the extension word and the 16 LSBs of the constant are stored in the word following the instruction. Length: Three or four words. One word less if a constant of the constant generator can be used for the immediate operand. Operation: The 20-bit immediate source operand is used together with the 20-bit destination operand. Comment: Valid only for the source operand. Example: ADDX.A #23456h,&TONI ; This instruction adds the 20-bit immediate operand 23456h to the data in the destination address TONI. Source: 20-bit immediate value 23456h. Destination: Two words beginning with address TONI. Before: Address Space After: Address Space 2103Ah 21038h 21036h 21034h 21032h xxxxh 7778h 3456h 50F2h 1907h PC 2103Ah 21038h 21036h 21034h 21032h xxxxh PC 7778h 3456h 50F2h 1907h 7777Ah 77778h 0001h 2345h 7777Ah 77778h 0003h 579Bh 23456h +12345h 3579Bh src dst Sum 16-Bit MSP430X CPU 4-35 MSP430 and MSP430X Instructions 4.5 MSP430 and MSP430X Instructions MSP430 instructions are the 27 implemented instructions of the MSP430 CPU. These instructions are used throughout the 1-MB memory range unless their 16-bit capability is exceeded. The MSP430X instructions are used when the addressing of the operands or the data length exceeds the 16-bit capability of the MSP430 instructions. There are three possibilities when choosing between an MSP430 and MSP430X instruction: - To use only the MSP430 instructions: The only exceptions are the CALLA and the RETA instruction. This can be done if a few, simple rules are met: J Placement of all constants, variables, arrays, tables, and data in the lower 64 KB. This allows the use of MSP430 instructions with 16-bit addressing for all data accesses. No pointers with 20-bit addresses are needed. J Placement of subroutine constants immediately after the subroutine code. This allows the use of the symbolic addressing mode with its 16-bit index to reach addresses within the range of PC ±32 KB. - To use only MSP430X instructions: The disadvantages of this method are the reduced speed due to the additional CPU cycles and the increased program space due to the necessary extension word for any double operand instruction. - Use the best fitting instruction where needed The following sections list and describe the MSP430 and MSP430X instructions. 4-36 16-Bit MSP430X CPU MSP430 and MSP430X Instructions 4.5.1 MSP430 Instructions The MSP430 instructions can be used, regardless if the program resides in the lower 64 KB or beyond it. The only exceptions are the instructions CALL and RET which are limited to the lower 64 KB address range. CALLA and RETA instructions have been added to the MSP430X CPU to handle subroutines in the entire address range with no code size overhead. MSP430 Double Operand (Format I) Instructions Figure 4−22 shows the format of the MSP430 double operand instructions. Source and destination words are appended for the Indexed, Symbolic, Absolute and Immediate modes. Table 4−4 lists the twelve MSP430 double operand instructions. Figure 4−22. MSP430 Double Operand Instruction Format 15 12 11 87654 0 Op-code Rsrc Ad B/W As Rdst Source or Destination 15:0 Destination 15:0 Table 4−4. MSP430 Double Operand Instructions Mnemonic S-Reg, D-Reg Operation MOV(.B) ADD(.B) ADDC(.B) SUB(.B) SUBC(.B) CMP(.B) DADD(.B) BIT(.B) BIC(.B) BIS(.B) XOR(.B) AND(.B) src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src → dst src + dst → dst src + dst + C → dst dst + .not.src + 1 → dst dst + .not.src + C → dst dst − src src + dst + C → dst (decimally) src .and. dst .not.src .and. dst → dst src .or. dst → dst src .xor. dst → dst src .and. dst → dst * The status bit is affected − The status bit is not affected 0 The status bit is cleared 1 The status bit is set Status Bits VNZ C −−−− **** **** **** **** **** **** 0* *Z −−−− −−−− ***Z 0* *Z 16-Bit MSP430X CPU 4-37 MSP430 and MSP430X Instructions Single Operand (Format II) Instructions Figure 4−23 shows the format for MSP430 single operand instructions, except RETI. The destination word is appended for the Indexed, Symbolic, Absolute and Immediate modes .Table 4−5 lists the seven single operand instructions. Figure 4−23. MSP430 Single Operand Instructions 15 Op-code 7654 0 B/W Ad Rdst Destination 15:0 Table 4−5. MSP430 Single Operand Instructions Mnemonic S-Reg, D-Reg RRC(.B) dst RRA(.B) dst PUSH(.B) src SWPB dst CALL dst RETI SXT dst Operation Status Bits VNZ C C → MSB →.......LSB → C **** MSB → MSB →....LSB → C 0* * * SP − 2 → SP, src → @SP −−−− bit 15…bit 8 ⇔ bit 7…bit 0 −−−− Call subroutine in lower 64 KB − − − − TOS → SR, SP + 2 → SP **** TOS → PC,SP + 2 → SP Register mode: bit 7 → bit 8 …bit 19 Other modes: bit 7 → bit 8 …bit 15 0* *Z * The status bit is affected − The status bit is not affected 0 The status bit is cleared 1 The status bit is set 4-38 16-Bit MSP430X CPU MSP430 and MSP430X Instructions Jumps Figure 4−24 shows the format for MSP430 and MSP430X jump instructions. The signed 10-bit word offset of the jump instruction is multiplied by two, sign-extended to a 20-bit address, and added to the 20-bit program counter. This allows jumps in a range of -511 to +512 words relative to the program counter in the full 20-bit address space Jumps do not affect the status bits. Table 4−6 lists and describes the eight jump instructions. Figure 4−24. Format of the Conditional Jump Instructions 15 13 12 10 9 8 0 Op-Code Condition S 10-Bit Signed PC Offset Table 4−6. Conditional Jump Instructions Mnemonic JEQ/JZ JNE/JNZ JC JNC JN JGE JL JMP S-Reg, D-Reg Label Label Label Label Label Label Label Label Operation Jump to label if zero bit is set Jump to label if zero bit is reset Jump to label if carry bit is set Jump to label if carry bit is reset Jump to label if negative bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally 16-Bit MSP430X CPU 4-39 MSP430 and MSP430X Instructions Emulated Instructions In addition to the MSP430 and MSP430X instructions, emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves. Instead, they are replaced automatically by the assembler with a core instruction. There is no code or performance penalty for using emulated instructions. The emulated instructions are listed in Table 4−7. Table 4−7. Emulated Instructions Instruction ADC(.B) dst BR dst CLR(.B) dst CLRC CLRN CLRZ DADC(.B) dst DEC(.B) dst DECD(.B) dst DINT EINT INC(.B) dst INCD(.B) dst INV(.B) dst NOP POP dst RET RLA(.B) dst RLC(.B) dst SBC(.B) dst SETC SETN SETZ TST(.B) dst Explanation Add Carry to dst Branch indirectly dst Clear dst Clear Carry bit Clear Negative bit Clear Zero bit Add Carry to dst decimally Decrement dst by 1 Decrement dst by 2 Disable interrupt Enable interrupt Increment dst by 1 Increment dst by 2 Invert dst No operation Pop operand from stack Return from subroutine Shift left dst arithmetically Shift left dst logically through Carry Subtract Carry from dst Set Carry bit Set Negative bit Set Zero bit Test dst (compare with 0) Emulation ADDC(.B) #0,dst MOV dst,PC MOV(.B) #0,dst BIC #1,SR BIC #4,SR BIC #2,SR DADD(.B) #0,dst SUB(.B) #1,dst SUB(.B) #2,dst BIC #8,SR BIS #8,SR ADD(.B) #1,dst ADD(.B) #2,dst XOR(.B) #-1,dst MOV R3,R3 MOV @SP+,dst MOV @SP+,PC ADD(.B) dst,dst ADDC(.B) dst,dst SUBC(.B) #0,dst BIS #1,SR BIS #4,SR BIS #2,SR CMP(.B) #0,dst VNZ C **** ---------0 - 0- - - 0**** **** **** ------**** **** **** ---------**** **** **** ---1 - 1- - - 10* * 1 4-40 16-Bit MSP430X CPU MSP430 and MSP430X Instructions MSP430 Instruction Execution The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to MCLK. Instruction Cycles and Length for Interrupt, Reset, and Subroutines Table 4−8 lists the length and the CPU cycles for reset, interrupts and subroutines. Table 4−8. Interrupt, Return and Reset Cycles and Length Action Return from interrupt RETI Return from subroutine RET Interrupt request service (cycles needed before 1st instruction) WDT reset Reset (RST/NMI) † The cycle count in MSP430 CPU is 5. ‡ The cycle count in MSP430 CPU is 6. Execution Time MCLK Cycles 3† 3 5‡ Length of Instruction (Words) 1 1 - 4 - 4 - 16-Bit MSP430X CPU 4-41 MSP430 and MSP430X Instructions Format-II (Single Operand) Instruction Cycles and Lengths Table 4−9 lists the length and the CPU cycles for all addressing modes of the MSP430 single operand instructions. Table 4−9. MSP430 Format-II Instruction Cycles and Length No. of Cycles Length of Instruction Example Addressing Mode Rn @Rn @Rn+ #N X(Rn) EDE &EDE RRA, RRC SWPB, SXT 1 3 3 n.a. 4 4 4 PUSH 3 3† 3† 3† 4‡ 4‡ 4‡ CALL 3† 4 4‡ 4‡ 4‡ 4‡ 4‡ Length of Instruction 1 1 1 2 2 2 2 Example SWPB R5 RRC @R9 SWPB @R10+ CALL #LABEL CALL 2(R7) PUSH EDE SXT &EDE † The cycle count in MSP430 CPU is 4. ‡ The cycle count in MSP430 CPU is 5. Also, the cycle count is 5 for X(Rn) addressing mode, when Rn = SP. Jump Instructions. Cycles and Lengths All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not. 4-42 16-Bit MSP430X CPU MSP430 and MSP430X Instructions Format-I (Double Operand) Instruction Cycles and Lengths Table 4−10 lists the length and CPU cycles for all addressing modes of the MSP430 format-I instructions. Table 4−10.MSP430 Format-I Instructions Cycles and Length Addressing Mode Src Dst No. of Length of Cycles Instruction Rn Rm 1 1 MOV PC 2 x(Rm) 4† EDE 4† &EDE 4† 1 BR 2 ADD 2 XOR 2 MOV @Rn Rm 2 1 AND PC 3 x(Rm) 5† EDE 5† &EDE 5† 1 BR 2 XOR 2 MOV 2 XOR @Rn+ Rm 2 1 ADD PC 3 x(Rm) 5† EDE 5† &EDE 5† 1 BR 2 XOR 2 MOV 2 MOV #N Rm 2 2 MOV PC 3 x(Rm) 5† EDE 5† &EDE 5† 2 BR 3 MOV 3 ADD 3 ADD x(Rn) Rm 3 2 MOV PC 3 TONI 6† x(Rm) 6† &TONI 6† 2 BR 3 MOV 3 ADD 3 MOV EDE Rm 3 2 AND PC 3 TONI 6† x(Rm) 6† &TONI 6† 2 BR 3 CMP 3 MOV 3 MOV &EDE Rm 3 2 MOV PC 3 TONI 6† x(Rm) 6† &TONI 6† 2 BR 3 MOV 3 MOV 3 MOV † MOV, BIT, and CMP instructions execute in 1 fewer cycle Example R5,R8 R9 R5,4(R6) R8,EDE R5,&EDE @R4,R5 @R8 @R5,8(R6) @R5,EDE @R5,&EDE @R5+,R6 @R9+ @R5,8(R6) @R9+,EDE @R9+,&EDE #20,R9 #2AEh #0300h,0(SP) #33,EDE #33,&EDE 2(R5),R7 2(R6) 4(R7),TONI 4(R4),6(R9) 2(R4),&TONI EDE,R6 EDE EDE,TONI EDE,0(SP) EDE,&TONI &EDE,R8 &EDE &EDE,TONI &EDE,0(SP) &EDE,&TONI 16-Bit MSP430X CPU 4-43 MSP430X Extended Instructions 4.5.2 MSP430X Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space. Most MSP430X instructions require an additional word of op-code called the extension word. Some extended instructions do not require an additional word and are noted in the instruction description. All addresses, indexes and immediate numbers have 20-bit values, when preceded by the extension word. There are two types of extension word: - Register/register mode for Format-I instructions and register mode for Format-II instructions. - Extension word for all other address mode combinations. 4-44 16-Bit MSP430X CPU MSP430X Extended Instructions Register Mode Extension Word The register mode extension word is shown in Figure 4−25 and described in Table 4−11. An example is shown in Figure 4−27. Figure 4−25. The Extension Word for Register Modes 15 0001 12 11 10 9 8 7 6 5 4 3 0 1 00 ZC # A/L 0 0 (n−1)/Rn Table 4−11. Description of the Extension Word Bits for Register Mode Bit 15:11 10:9 ZC # A/L 5:4 3:0 Description Extension word op-code. Op-codes 1800h to 1FFFh are extension words. Reserved Zero carry bit. 0: The executed instruction uses the status of the carry bit C. 1: The executed instruction uses the carry bit as 0. The carry bit will be defined by the result of the final operation after instruction execution. Repetition bit. 0: The number of instruction repetitions is set by extension-word bits 3:0. 1: The number of instructions repetitions is defined by the value of the four LSBs of Rn. See description for bits 3:0. Data length extension bit. Together with the B/W-bits of the following MSP430 instruction, the AL bit defines the used data length of the instruction. A/L B/W Comment 0 0 Reserved 0 1 20-bit address-word 1 0 16-bit word 1 1 8-bit byte Reserved Repetition Count. # = 0: These four bits set the repetition count n. These bits contain n - 1. # = 1: These four bits define the CPU register whose bits 3:0 set the number of repetitions. Rn.3:0 contain n - 1. 16-Bit MSP430X CPU 4-45 MSP430X Extended Instructions Non-Register Mode Extension Word The extension word for non-register modes is shown in Figure 4−26 and described in Table 4−12. An example is shown in Figure 4−28. Figure 4−26. The Extension Word for Non-Register Modes 15 00 12 11 10 765 0 1 1 Source bits 19:16 A/L 0 43 0 0 Destination bits 19:16 Table 4−12.Description of the Extension Word Bits for Non-Register Modes Bit 15:11 Description Extension word op-code. Op-codes 1800h to 1FFFh are extension words. Source Bits 19:16 The four MSBs of the 20-bit source. Depending on the source addressing mode, these four MSBs may belong to an immediate operand, an index or to an absolute address. A/L Data length extension bit. Together with the B/W-bits of the fol- lowing MSP430 instruction, the AL bit defines the used data length of the instruction. A/L B/W Comment 0 0 Reserved 0 1 20 bit address-word 1 0 16 bit word 1 1 8 bit byte 5:4 Reserved Destination Bits The four MSBs of the 20-bit destination. Depending on the des- 19:16 tination addressing mode, these four MSBs may belong to an index or to an absolute address. Note: B/W and A/L Bit Settings for SWPBX and SXTX The B/W and A/L bit settings for SWPBX and SXTX are: A/L B/W 00 01 10 11 SWPBX.A, SXTX.A n.a. SWPB.W, SXTX.W n.a. 4-46 16-Bit MSP430X CPU MSP430X Extended Instructions Figure 4−27. Example for an Extended Register/Register Instruction 15 14 13 12 11 10 9 8 7 6 5 4 00011 00 ZC # A/L Rsvd 3210 (n−1)/Rn Op-code Rsrc Ad B/W As Rdst XORX.A R9,R8 1: Repetition count in bits 3:0 0: Use Carry 01: Address word 00011 0 000 0 0 14(XOR) 9 01 0 8(R8) XORX instruction Source R9 Destination register mode Source register mode Destination R8 Figure 4−28. Example for an Extended Immediate/Indexed Instruction 15 14 13 12 11 10 9 8 7 6 5 4 00011 Source 19:16 A/L Rsvd 3210 Destination 19:16 Op-code Rsrc Ad B/W As Rdst Source 15:0 Destination 15:0 XORX.A #12345h, 45678h(R15) 18xx extension word 00011 12345h X(Rn) 01: Address word 1 0 0 14 (XOR) 0 (PC) 11 3 Immediate operand LSBs: 2345h Index destination LSBs: 5678h @PC+ 4 15 (R15) 16-Bit MSP430X CPU 4-47 MSP430X Extended Instructions Extended Double Operand (Format-I) Instructions All twelve double-operand instructions have extended versions as listed in Table 4−13. Table 4−13.Extended Double Operand Instructions Mnemonic Operands MOVX(.B,.A) src,dst ADDX(.B,.A) src,dst ADDCX(.B,.A) src,dst SUBX(.B,.A) src,dst SUBCX(.B,.A) src,dst CMPX(.B,.A) src,dst DADDX(.B,.A) src,dst BITX(.B,.A) src,dst BICX(.B,.A) src,dst BISX(.B,.A) src,dst XORX(.B,.A) src,dst ANDX(.B,.A) src,dst Operation src → dst src + dst → dst src + dst + C → dst dst + .not.src + 1 → dst dst + .not.src + C → dst dst − src src + dst + C → dst (decimal) src .and. dst .not.src .and. dst → dst src .or. dst → dst src .xor. dst → dst src .and. dst → dst * The status bit is affected − The status bit is not affected 0 The status bit is cleared 1 The status bit is set Status Bits VNZC −−−− **** **** **** **** **** **** 0* *Z −−−− −−−− * * *Z 0* *Z 4-48 16-Bit MSP430X CPU MSP430X Extended Instructions The four possible addressing combinations for the extension word for format-I instructions are shown in Figure 4−29. Figure 4−29. Extended Format-I Instruction Formats 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 1 1 0 0 ZC # A/L 0 0 n−1/Rn Op-code src 0 B/W 0 0 dst 0 0 01 1 Op-code src.19:16 A/L 0 0 0 0 0 0 src Ad B/W As dst src.15:0 0 0 0 1 1 0 0 0 0 A/L 0 0 Op-code src Ad B/W As dst.15:0 dst.19:16 dst 0 0 01 1 Op-code src.19:16 A/L 0 0 src Ad B/W As src.15:0 dst.15:0 dst.19:16 dst If the 20-bit address of a source or destination operand is located in memory, not in a CPU register, then two words are used for this operand as shown in Figure 4−30. Figure 4−30. 20-Bit Addresses in Memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address+2 0 ....................................................................................... 0 19:16 Address Operand LSBs 15:0 16-Bit MSP430X CPU 4-49 MSP430X Extended Instructions Extended Single Operand (Format-II) Instructions Extended MSP430X Format-II instructions are listed in Table 4−14. Table 4−14.Extended Single-Operand Instructions Operation Mnemonic Operands CALLA dst Call indirect to subroutine (20-bit address) POPM.A #n,Rdst Pop n 20-bit registers from stack POPM.W #n,Rdst Pop n 16-bit registers from stack PUSHM.A #n,Rsrc Push n 20-bit registers to stack PUSHM.W #n,Rsrc Push n 16-bit registers to stack PUSHX(.B,.A) src Push 8/16/20-bit source to stack RRCM(.A) #n,Rdst Rotate right Rdst n bits through carry (16-/20-bit register) RRUM(.A) #n,Rdst Rotate right Rdst n bits unsigned (16-/20-bit register) RRAM(.A) #n,Rdst Rotate right Rdst n bits arithmetically (16-/20-bit register) RLAM(.A) #n,Rdst Rotate left Rdst n bits arithmetically (16-/20-bit register) RRCX(.B,.A) dst Rotate right dst through carry (8-/16-/20-bit data) RRUX(.B,.A) dst Rotate right dst unsigned (8-/16-/20-bit ) RRAX(.B,.A) dst Rotate right dst arithmetically SWPBX(.A) dst Exchange low byte with high byte SXTX(.A) Rdst Bit7 → bit8 … bit19 SXTX(.A) dst Bit7 → bit8 … MSB Status Bits n VNZC −−−− 1 − 16 − − − − 1 − 16 − − − − 1 − 16 − − − − 1 − 16 −−−− 1−4 0 * * * 1−4 0 * * * 1−4 * * * * 1−4 * * * * 1 0*** 1 0*** 1 **** 1 −−−− 1 0*** 1 0*** 4-50 16-Bit MSP430X CPU MSP430X Extended Instructions The three possible addressing mode combinations for format-II instructions are shown in Figure 4−31. Figure 4−31. Extended Format-II Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 1 1 0 0 ZC # A/L 0 0 n−1/Rn Op-code B/W 0 0 dst 0 0 0 1 1 0 0 0 0 A/L 0 0 0 0 0 0 Op-code B/W 1 x dst 0 0 0 1 1 0 0 0 0 A/L 0 0 Op-code B/W x 1 dst.15:0 dst.19:16 dst Extended Format II Instruction Format Exceptions Exceptions for the Format II instruction formats are shown below. Figure 4−32. PUSHM/POPM Instruction Format 15 Op-code 87 43 0 n−1 Rdst − n+1 Figure 4−33. RRCM, RRAM, RRUM and RLAM Instruction Format 15 12 11 10 9 C n−1 Op-code 43 0 Rdst 16-Bit MSP430X CPU 4-51 MSP430X Extended Instructions Figure 4−34. BRA Instruction Format 15 12 11 87 43 0 C Rsrc Op-code 0(PC) C #imm/abs19:16 Op-code #imm15:0 / &abs15:0 0(PC) C Rsrc Op-code 0(PC) index15:0 Figure 4−35. CALLA Instruction Format 15 Op-code Op-code index15:0 43 0 Rdst Rdst Op-code #imm15:0 / index15:0 / &abs15:0 #imm/ix/abs19:16 4-52 16-Bit MSP430X CPU MSP430X Extended Instructions Extended Emulated Instructions The extended instructions together with the constant generator form the extended Emulated instructions. Table 4−15 lists the Emulated instructions. Table 4−15.Extended Emulated Instructions Instruction ADCX(.B,.A) dst BRA dst RETA CLRA Rdst CLRX(.B,.A) dst DADCX(.B,.A) dst DECX(.B,.A) dst DECDA Rdst DECDX(.B,.A) dst INCX(.B,.A) dst INCDA Rdst INCDX(.B,.A) dst INVX(.B,.A) dst RLAX(.B,.A) dst RLCX(.B,.A) dst SBCX(.B,.A) dst TSTA Rdst TSTX(.B,.A) dst POPX dst Explanation Add carry to dst Branch indirect dst Return from subroutine Clear Rdst Clear dst Add carry to dst decimally Decrement dst by 1 Decrement dst by 2 Decrement dst by 2 Increment dst by 1 Increment Rdst by 2 Increment dst by 2 Invert dst Shift left dst arithmetically Shift left dst logically through carry Subtract carry from dst Test Rdst (compare with 0) Test dst (compare with 0) Pop to dst Emulation ADDCX(.B,.A) #0,dst MOVA dst,PC MOVA @SP+,PC MOV #0,Rdst MOVX(.B,.A) #0,dst DADDX(.B,.A) #0,dst SUBX(.B,.A) #1,dst SUBA #2,Rdst SUBX(.B,.A) #2,dst ADDX(.B,.A) #1,dst ADDA #2,Rdst ADDX(.B,.A) #2,dst XORX(.B,.A) #-1,dst ADDX(.B,.A) dst,dst ADDCX(.B,.A) dst,dst SUBCX(.B,.A) #0,dst CMPA #0,Rdst CMPX(.B,.A) #0,dst MOVX(.B, .A) @SP+,dst 16-Bit MSP430X CPU 4-53 MSP430X Extended Instructions MSP430X Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the register mode and the Immediate mode, except for the MOVA instruction as listed in Table 4−16. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time. Address instructions should be used any time an MSP430X instruction is needed with the corresponding restricted addressing mode. Table 4−16.Address Instructions, Operate on 20-bit Registers Data Mnemonic ADDA MOVA CMPA SUBA Operands Rsrc,Rdst #imm20,Rdst Operation Add source to destination register Status Bits VNZC **** Rsrc,Rdst Move source to destination - - - - #imm20,Rdst z16(Rsrc),Rdst EDE,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,z16(Rdst) Rsrc,&abs20 Rsrc,Rdst #imm20,Rdst Compare source to destina- * * * * tion register Rsrc,Rdst #imm20,Rdst Subtract source from destination register **** 4-54 16-Bit MSP430X CPU MSP430X Extended Instructions MSP430X Instruction Execution The number of CPU clock cycles required for an MSP430X instruction depends on the instruction format and the addressing modes used — not the instruction itself. The number of clock cycles refers to MCLK. MSP430X Format-II (Single-Operand) Instruction Cycles and Lengths Table 4−17 lists the length and the CPU cycles for all addressing modes of the MSP430X extended single-operand instructions. Table 4−17.MSP430X Format II Instruction Cycles and Length Execution Cycles/Length of Instruction (Words) Instruction RRAM Rn @Rn @Rn+ #N X(Rn) EDE &EDE n/1 − − − − − − RRCM n/1 − − − − − − RRUM n/1 − − − − − − RLAM n/1 − − − − − − PUSHM 2+n/1 − − − − − − PUSHM.A 2+2n/1 − − − − − − POPM 2+n/1 − − − − − − POPM.A CALLA 2+2n/1 − − − − − − 4/1 5/1 5/1 4/2 6†/2 6/2 6/2 RRAX(.B) 1+n/2 4/2 4/2 − 5/3 5/3 5/3 RRAX.A 1+n/2 6/2 6/2 − 7/3 7/3 7/3 RRCX(.B) 1+n/2 4/2 4/2 − 5/3 5/3 5/3 RRCX.A PUSHX(.B) 1+n/2 6/2 6/2 − 7/3 7/3 7/3 4/2 4/2 4/2 4/3 5†/3 5/3 5/3 PUSHX.A 5/2 6/2 6/2 6/3 7†/3 7/3 7/3 POPX(.B) 3/2 − − − 5/3 5/3 5/3 POPX.A 4/2 − − − 7/3 7/3 7/3 † Add one cycle when Rn = SP. MSP430X Format-I (Double-Operand) Instruction Cycles and Lengths Table 4−18 lists the length and CPU cycles for all addressing modes of the MSP430X extended format-I instructions. 16-Bit MSP430X CPU 4-55 MSP430X Extended Instructions Table 4−18.MSP430X Format-I Instruction Cycles and Length Addressing Mode No. of Cycles Length of Instruction Source Destination .B/.W .A .B/.W/.A Examples Rn Rm† 2 2 2 BITX.B R5,R8 PC 3 3 2 ADDX R9,PC X(Rm) 5‡ 7§ 3 ANDX.A R5,4(R6) EDE 5‡ 7§ 3 XORX R8,EDE &EDE 5‡ 7§ 3 BITX.W R5,&EDE @Rn Rm 3 4 2 BITX @R5,R8 PC 3 4 2 ADDX @R9,PC X(Rm) 6‡ 9§ 3 ANDX.A @R5,4(R6) EDE 6‡ 9§ 3 XORX @R8,EDE &EDE 6‡ 9§ 3 BITX.B @R5,&EDE @Rn+ Rm 3 4 2 BITX @R5+,R8 PC 4 5 2 ADDX.A @R9+,PC X(Rm) 6‡ 9§ 3 ANDX @R5+,4(R6) EDE 6‡ 9§ 3 XORX.B @R8+,EDE &EDE 6‡ 9§ 3 BITX @R5+,&EDE #N Rm 3 3 3 BITX #20,R8 PC¶ 4 4 3 ADDX.A #FE000h,PC X(Rm) 6‡ 8§ 4 ANDX #1234,4(R6) EDE 6‡ 8§ 4 XORX #A5A5h,EDE &EDE 6‡ 8§ 4 BITX.B #12,&EDE X(Rn) Rm 4 5 3 BITX 2(R5),R8 PC¶ 5 6 3 SUBX.A 2(R6),PC X(Rm) 7‡ 10§ 4 ANDX 4(R7),4(R6) EDE 7‡ 10§ 4 XORX.B 2(R6),EDE &EDE 7‡ 10§ 4 BITX 8(SP),&EDE EDE Rm 4 5 3 BITX.B EDE,R8 PC¶ 5 6 3 ADDX.A EDE,PC X(Rm) 7‡ 10§ 4 ANDX EDE,4(R6) EDE 7‡ 10§ 4 ANDX EDE,TONI &TONI 7‡ 10§ 4 BITX EDE,&TONI &EDE Rm 4 5 3 BITX &EDE,R8 PC¶ 5 6 3 ADDX.A &EDE,PC X(Rm) 7‡ 10§ 4 ANDX.B &EDE,4(R6) TONI 7‡ 10§ 4 XORX &EDE,TONI &TONI 7‡ 10§ 4 BITX &EDE,&TONI † Repeat instructions require n+1 cycles where n is the number of times the instruction is executed. ‡ Reduce the cycle count by one for MOV, BIT, and CMP instructions. § Reduce the cycle count by two for MOV, BIT, and CMP instructions. ¶ Reduce the cycle count by one for MOV, ADD, and SUB instructions. 4-56 16-Bit MSP430X CPU MSP430X Extended Instructions MSP430X Address Instruction Cycles and Lengths Table 4−19 lists the length and the CPU cycles for all addressing modes of the MSP430X address instructions. Table 4−19.Address Instruction Cycles and Length Addressing Mode Source Destination Rn Rn PC x(Rm) EDE &EDE @Rn Rm PC @Rn+ Rm PC #N Rm PC x(Rn) Rm PC EDE Rm PC &EDE Rm PC Execution Time MCLK Cycles MOVA BRA CMPA ADDA SUBA 1 1 2 2 4 - 4 - 4 - 3 - 3 - 3 - 3 - 2 3 3 3 4 - 4 - 4 - 4 - 4 - 4 - Length of Instruction (Words) MOVA CMPA ADDA SUBA Example 1 1 CMPA R5,R8 1 1 SUBA R9,PC 2 - MOVA R5,4(R6) 2 - MOVA R8,EDE 2 - MOVA R5,&EDE 1 - MOVA @R5,R8 1 - MOVA @R9,PC 1 - MOVA @R5+,R8 1 - MOVA @R9+,PC 2 2 CMPA #20,R8 2 2 SUBA #FE000h,PC 2 - MOVA 2(R5),R8 2 - MOVA 2(R6),PC 2 - MOVA EDE,R8 2 - MOVA EDE,PC 2 - MOVA &EDE,R8 2 - MOVA &EDE,PC 16-Bit MSP430X CPU 4-57 Instruction Set Description 4.6 Instruction Set Description The instruction map of the MSP430X shows all available instructions: 000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0 0xxx MOVA, CMPA, ADDA, SUBA, RRCM, RRAM, RLAM, RRUM 10xx 14xx 18xx 1Cxx RRC RRC.B SWPB RRA RRA.B SXT PUSH PUSH.B CALL PUSHM.A, POPM.A, PUSHM.W, POPM.W Extension Word For Format I and Format II Instructions RETI CALLA 20xx 24xx 28xx 2Cxx 30xx 34xx 38xx 3Cxx JNE/JNZ JEQ/JZ JNC JC JN JGE JL JMP 4xxx 5xxx 6xxx 7xxx 8xxx 9xxx Axxx Bxxx Cxxx Dxxx Exxx Fxxx MOV, MOV.B ADD, ADD.B ADDC, ADDC.B SUBC, SUBC.B SUB, SUB.B CMP, CMP.B DADD, DADD.B BIT, BIT.B BIC, BIC.B BIS, BIS.B XOR, XOR.B AND, AND.B 4-58 16-Bit MSP430X CPU Instruction Set Description 4.6.1 Extended Instruction Binary Descriptions Detailed MSP430X instruction binary descriptions are shown below. Instruction MOVA CMPA ADDA SUBA MOVA CMPA ADDA SUBA Instruction src or Instruction Group data.19:16 Identifier dst 15 12 11 87 43 0 0 000 src 0000 dst MOVA @Rsrc,Rdst 0 000 src 0001 dst MOVA @Rsrc+,Rdst 0 0 0 0 &abs.19:16 0 0 1 0 dst MOVA &abs20,Rdst &abs.15:0 0 000 src 0011 dst MOVA x(Rsrc),Rdst x.15:0 ±15-bit index x 0 000 src 0 1 1 0 &abs.19:16 MOVA Rsrc,&abs20 &abs.15:0 0 000 src 0111 dst MOVA Rsrc,X(Rdst) x.15:0 ±15-bit index x 0 0 0 0 imm.19:16 1 0 0 0 dst MOVA #imm20,Rdst imm.15:0 0 0 0 0 imm.19:16 1 0 0 1 dst CMPA #imm20,Rdst imm.15:0 0 0 0 0 imm.19:16 1 0 1 0 dst ADDA #imm20,Rdst imm.15:0 0 0 0 0 imm.19:16 1 0 1 1 dst SUBA #imm20,Rdst imm.15:0 0 000 src 1100 dst MOVA Rsrc,Rdst 0 000 src 1101 dst CMPA Rsrc,Rdst 0 000 src 1110 dst ADDA Rsrc,Rdst 0 000 src 1111 dst SUBA Rsrc,Rdst Instruction RRCM.A RRAM.A RLAM.A RRUM.A RRCM.W RRAM.W RLAM.W RRUM.W Instruction Bit Inst. Instruction Group loc. ID Identifier dst 15 12 11 10 9 8 7 43 0 0 0 0 0 n−1 0 0 0 1 0 0 dst RRCM.A #n,Rdst 0 0 0 0 n−1 0 1 0 1 0 0 dst RRAM.A #n,Rdst 0 0 0 0 n−1 1 0 0 1 0 0 dst RLAM.A #n,Rdst 0 0 0 0 n−1 1 1 0 1 0 0 dst RRUM.A #n,Rdst 0 0 0 0 n−1 0 0 0 1 0 1 dst RRCM.W #n,Rdst 0 0 0 0 n−1 0 1 0 1 0 1 dst RRAM.W #n,Rdst 0 0 0 0 n−1 1 0 0 1 0 1 dst RLAM.W #n,Rdst 0 0 0 0 n−1 1 1 0 1 0 1 dst RRUM.W #n,Rdst 16-Bit MSP430X CPU 4-59 Instruction Set Description Instruction RETI CALLA Reserved Reserved PUSHM.A PUSHM.W POPM.A POPM.W Instruction Identifier dst 15 12 11 8765 43 0 0 00 1 0 01 1000 0000 0 0 00 1 0 01 1010 0 dst CALLA Rdst 0 00 1 0 01 1010 1 dst CALLA x(Rdst) x.15:0 0 00 1 0 01 1011 0 dst CALLA @Rdst 0 00 1 0 01 1011 1 dst CALLA @Rdst+ 0 0 0 1 0 0 1 1 1 0 0 0 &abs.19:16 CALLA &abs20 &abs.15:0 0 0 0 1 0 0 1 1 1 0 0 1 x.19:16 CALLA EDE x.15:0 CALLA x(PC) 0 0 0 1 0 0 1 1 1 0 1 1 imm.19:16 CALLA #imm20 imm.15:0 0 00 1 0 01 1101 0x x x x 0 00 1 0 01 111x xx x x x 000 1 0100 n−1 dst PUSHM.A #n,Rdst 000 1 0101 n−1 dst PUSHM.W #n,Rdst 000 1 0110 n−1 dst−n+1 POPM.A #n,Rdst 000 1 0111 n−1 dst−n+1 POPM.W #n,Rdst 4-60 16-Bit MSP430X CPU MSP430 Instructions 4.6.2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages. 16-Bit MSP430X CPU 4-61 MSP430 Instructions * ADC[.W] * ADC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Add carry to destination Add carry to destination ADC dst or ADC.W dst ADC.B dst dst + C −> dst ADDC #0,dst ADDC.B #0,dst The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if dst was incremented from 0FFFFh to 0000, reset otherwise Set if dst was incremented from 0FFh to 00, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. The 16-bit counter pointed to by R13 is added to a 32-bit counter pointed to by R12. ADD @R13,0(R12) ; Add LSDs ADC 2(R12) ; Add carry to MSD The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ; Add LSDs ADC.B 1(R12) ; Add carry to MSD 4-62 16-Bit MSP430X CPU ADD[.W] ADD.B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Add source word to destination word Add source byte to destination byte ADD ADD.B src,dst or ADD.W src,dst src,dst src + dst → dst The source operand is added to the destination operand. The previous content of the destination is lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise. OSCOFF, CPUOFF, and GIE are not affected. Ten is added to the 16-bit counter CNTR located in lower 64 K. ADD.W #10,&CNTR ; Add 10 to 16-bit counter A table word pointed to by R5 (20-bit address in R5) is added to R6. The jump to label TONI is performed on a carry. ADD.W JC ... @R5,R6 TONI ; Add table word to R6. R6.19:16 = 0 ; Jump if carry ; No carry A table byte pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. R6.19:8 = 0 ADD.B JNC ... @R5+,R6 TONI ; Add byte to R6. R5 + 1. R6: 000xxh ; Jump if no carry ; Carry occurred 16-Bit MSP430X CPU 4-63 MSP430 Instructions ADDC[.W] ADDC.B Syntax Operation Description Status Bits Mode Bits Example Add source word and carry to destination word Add source byte and carry to destination byte ADDC src,dst or ADDC.W src,dst ADDC.B src,dst src + dst + C → dst The source operand and the carry bit C are added to the destination operand. The previous content of the destination is lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise. OSCOFF, CPUOFF, and GIE are not affected. Constant value 15 and the carry of the previous instruction are added to the 16-bit counter CNTR located in lower 64 K. Example ADDC.W #15,&CNTR ; Add 15 + C to 16-bit CNTR A table word pointed to by R5 (20-bit address) and the carry C are added to R6. The jump to label TONI is performed on a carry. R6.19:16 = 0 Example ADDC.W JC ... @R5,R6 TONI ; Add table word + C to R6 ; Jump if carry ; No carry A table byte pointed to by R5 (20-bit address) and the carry bit C are added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. R6.19:8 = 0 ADDC.B JNC ... @R5+,R6 TONI ; Add table byte + C to R6. R5 + 1 ; Jump if no carry ; Carry occurred 4-64 16-Bit MSP430X CPU AND[.W] AND.B Syntax Operation Description Status Bits Mode Bits Example Example MSP430 Instructions Logical AND of source word with destination word Logical AND of source byte with destination byte AND AND.B src,dst or AND.W src,dst src,dst src .and. dst → dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The bits set in R5 (16-bit data) are used as a mask (AA55h) for the word TOM located in the lower 64 K. If the result is zero, a branch is taken to label TONI. R5.19:16 = 0 MOV AND JZ ... #AA55h,R5 R5,&TOM TONI ; Load 16-bit mask to R5 ; TOM .and. R5 -> TOM ; Jump if result 0 ; Result > 0 or shorter: AND #AA55h,&TOM JZ TONI ; TOM .and. AA55h -> TOM ; Jump if result 0 A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R5 is incremented by 1 after the fetching of the byte. R6.19:8 = 0 AND.B @R5+,R6 ; AND table byte with R6. R5 + 1 16-Bit MSP430X CPU 4-65 MSP430 Instructions BIC[.W] BIC.B Syntax Operation Description Status Bits Mode Bits Example Clear bits set in source word in destination word Clear bits set in source byte in destination byte BIC BIC.B src,dst or BIC.W src,dst src,dst (.not. src) .and. dst → dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The bits 15:14 of R5 (16-bit data) are cleared. R5.19:16 = 0 Example BIC #0C000h,R5 ; Clear R5.19:14 bits A table word pointed to by R5 (20-bit address) is used to clear bits in R7. R7.19:16 = 0 Example BIC.W @R5,R7 ; Clear bits in R7 set in @R5 A table byte pointed to by R5 (20-bit address) is used to clear bits in Port1. BIC.B @R5,&P1OUT ; Clear I/O port P1 bits set in @R5 4-66 16-Bit MSP430X CPU BIS[.W] BIS.B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Set bits set in source word in destination word Set bits set in source byte in destination byte BIS BIS.B src,dst or BIS.W src,dst src,dst src .or. dst → dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Bits 15 and 13 of R5 (16-bit data) are set to one. R5.19:16 = 0 BIS #A000h,R5 ; Set R5 bits A table word pointed to by R5 (20-bit address) is used to set bits in R7. R7.19:16 = 0 BIS.W @R5,R7 ; Set bits in R7 A table byte pointed to by R5 (20-bit address) is used to set bits in Port1. R5 is incremented by 1 afterwards. BIS.B @R5+,&P1OUT ; Set I/O port P1 bits. R5 + 1 16-Bit MSP430X CPU 4-67 MSP430 Instructions BIT[.W] BIT.B Syntax Operation Description Status Bits Mode Bits Example Test bits set in source word in destination word Test bits set in source byte in destination byte BIT BIT.B src,dst or BIT.W src,dst src,dst src .and. dst The source operand and the destination operand are logically ANDed. The result affects only the status bits in SR. Register Mode: the register bits Rdst.19:16 (.W) resp. Rdst. 19:8 (.B) are not cleared! N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. Test if one − or both − of bits 15 and 14 of R5 (16-bit data) is set. Jump to label TONI if this is the case. R5.19:16 are not affected. Example BIT #C000h,R5 JNZ TONI ... ; Test R5.15:14 bits ; At least one bit is set in R5 ; Both bits are reset A table word pointed to by R5 (20-bit address) is used to test bits in R7. Jump to label TONI if at least one bit is set. R7.19:16 are not affected. Example BIT.W @R5,R7 JC TONI ... ; Test bits in R7 ; At least one bit is set ; Both are reset A table byte pointed to by R5 (20-bit address) is used to test bits in output Port1. Jump to label TONI if no bit is set. The next table byte is addressed. BIT.B JNC ... @R5+,&P1OUT TONI ; Test I/O port P1 bits. R5 + 1 ; No corresponding bit is set ; At least one bit is set 4-68 16-Bit MSP430X CPU * BR, BRANCH Syntax Operation Emulation Description Status Bits Example MSP430 Instructions Branch to destination in lower 64K address space BR dst dst −> PC MOV dst,PC An unconditional branch is taken to an address anywhere in the lower 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. BR #EXEC ;Branch to label EXEC or direct branch (e.g. #0A4h) ; Core instruction MOV @PC+,PC BR EXEC ; Branch to the address contained in EXEC ; Core instruction MOV X(PC),PC ; Indirect address BR &EXEC ; Branch to the address contained in absolute ; address EXEC ; Core instruction MOV X(0),PC ; Indirect address BR R5 ; Branch to the address contained in R5 ; Core instruction MOV R5,PC ; Indirect R5 BR @R5 ; Branch to the address contained in the word ; pointed to by R5. ; Core instruction MOV @R5,PC ; Indirect, indirect R5 BR @R5+ ; Branch to the address contained in the word pointed ; to by R5 and increment pointer in R5 afterwards. ; The next time—S/W flow uses R5 pointer—it can ; alter program execution due to access to ; next address in a table pointed to by R5 ; Core instruction MOV @R5,PC ; Indirect, indirect R5 with autoincrement BR X(R5) ; Branch to the address contained in the address ; pointed to by R5 + X (e.g. table with address ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X 16-Bit MSP430X CPU 4-69 MSP430 Instructions CALL Syntax Operation Description Status Bits Mode Bits Examples Call a Subroutine in lower 64 K CALL dst dst → tmp SP − 2 → SP PC → @SP tmp → PC 16-bit dst is evaluated and stored updated PC with return address to TOS saved 16-bit dst to PC A subroutine call is made from an address in the lower 64 K to a subroutine address in the lower 64 K. All seven source addressing modes can be used. The call instruction is a word instruction. The return is made with the RET instruction. Not affected PC.19:16: Cleared (address in lower 64 K) OSCOFF, CPUOFF, and GIE are not affected. Examples for all addressing modes are given. Immediate Mode: Call a subroutine at label EXEC (lower 64 K) or call directly to address. CALL #EXEC CALL #0AA04h ; Start address EXEC ; Start address 0AA04h Symbolic Mode: Call a subroutine at the 16-bit address contained in address EXEC. EXEC is located at the address (PC + X) where X is within PC±32 K. CALL EXEC ; Start address at @EXEC. z16(PC) Absolute Mode: Call a subroutine at the 16-bit address contained in absolute address EXEC in the lower 64 K. CALL &EXEC ; Start address at @EXEC Register Mode: Call a subroutine at the 16-bit address contained in register R5.15:0. CALL R5 ; Start address at R5 Indirect Mode: Call a subroutine at the 16-bit address contained in the word pointed to by register R5 (20-bit address). CALL @R5 ; Start address at @R5 4-70 16-Bit MSP430X CPU * CLR[.W] * CLR.B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destination CLR CLR.B dst or CLR.W dst dst 0 −> dst MOV MOV.B #0,dst #0,dst The destination operand is cleared. Status bits are not affected. RAM word TONI is cleared. CLR TONI ; 0 −> TONI Register R5 is cleared. CLR R5 RAM byte TONI is cleared. CLR.B TONI ; 0 −> TONI MSP430 Instructions 16-Bit MSP430X CPU 4-71 MSP430 Instructions * CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Clear carry bit CLRC 0 −> C BIC #1,SR The carry bit (C) is cleared. The clear carry instruction is a word instruction. N: Not affected Z: Not affected C: Cleared V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12. CLRC DADD DADC ; C=0: defines start @R13,0(R12) ; add 16-bit counter to low word of 32-bit counter 2(R12) ; add carry to high word of 32-bit counter 4-72 16-Bit MSP430X CPU * CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET MSP430 Instructions Clear negative bit CLRN 0→N or (.NOT.src .AND. dst −> dst) BIC #4,SR The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction. N: Reset to 0 Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The Negative bit in the status register is cleared. This avoids special treatment with negative numbers of the subroutine called. CLRN CALL ...... ...... JN ...... ...... ...... RET SUBR SUBRET ; If input is negative: do nothing and return 16-Bit MSP430X CPU 4-73 MSP430 Instructions * CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Clear zero bit CLRZ 0→Z or (.NOT.src .AND. dst −> dst) BIC #2,SR The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. N: Not affected Z: Reset to 0 C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The zero bit in the status register is cleared. CLRZ Indirect, Auto-Increment mode: Call a subroutine at the 16-bit address contained in the word pointed to by register R5 (20-bit address) and increment the 16-bit address in R5 afterwards by 2. The next time the software uses R5 as a pointer, it can alter the program execution due to access to the next word address in the table pointed to by R5. CALL @R5+ ; Start address at @R5. R5 + 2 Indexed mode: Call a subroutine at the 16-bit address contained in the 20-bit address pointed to by register (R5 + X), e.g. a table with addresses starting at X. The address is within the lower 64 KB. X is within ±32 KB. CALL X(R5) ; Start address at @(R5+X). z16(R5) 4-74 16-Bit MSP430X CPU CMP[.W] CMP.B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Compare source word and destination word Compare source byte and destination byte CMP CMP.B src,dst or CMP.W src,dst src,dst (.not.src) + 1 + dst or dst − src The source operand is subtracted from the destination operand. This is made by adding the 1’s complement of the source + 1 to the destination. The result affects only the status bits in SR. Register Mode: the register bits Rdst.19:16 (.W) resp. Rdst. 19:8 (.B) are not cleared. N: Set if result is negative (src > dst), reset if positive (src = dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive des- tination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. Compare word EDE with a 16-bit constant 1800h. Jump to label TONI if EDE equals the constant. The address of EDE is within PC ± 32 K. CMP JEQ ... #01800h,EDE TONI ; Compare word EDE with 1800h ; EDE contains 1800h ; Not equal A table word pointed to by (R5 + 10) is compared with R7. Jump to label TONI if R7 contains a lower, signed 16-bit number. R7.19:16 is not cleared. The address of the source operand is a 20-bit address in full memory range. CMP.W 10(R5),R7 JL TONI ... ; Compare two signed numbers ; R7 < 10(R5) ; R7 >= 10(R5) A table byte pointed to by R5 (20-bit address) is compared to the value in output Port1. Jump to label TONI if values are equal. The next table byte is addressed. CMP.B @R5+,&P1OUT JEQ TONI ... ; Compare P1 bits with table. R5 + 1 ; Equal contents ; Not equal 16-Bit MSP430X CPU 4-75 MSP430 Instructions * DADC[.W] * DADC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Add carry decimally to destination Add carry decimally to destination DADC DADC.B dst or DADC.W src,dst dst dst + C −> dst (decimally) DADD DADD.B #0,dst #0,dst The carry bit (C) is added decimally to the destination. N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise C: Set if destination increments from 9999 to 0000, reset otherwise Set if destination increments from 99 to 00, reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The four-digit decimal number contained in R5 is added to an eight-digit decimal number pointed to by R8. CLRC DADD DADC R5,0(R8) 2(R8) ; Reset carry ; next instruction’s start condition is defined ; Add LSDs + C ; Add carry to MSD The two-digit decimal number contained in R5 is added to a four-digit decimal number pointed to by R8. CLRC DADD.B DADC R5,0(R8) 1(R8) ; Reset carry ; next instruction’s start condition is defined ; Add LSDs + C ; Add carry to MSDs 4-76 16-Bit MSP430X CPU DADD[.W] DADD.B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADD src,dst or DADD.W src,dst DADD.B src,dst src + dst + C → dst (decimally) The source operand and the destination operand are treated as two (.B) or four (.W) binary coded decimals (BCD) with positive signs. The source operand and the carry bit C are added decimally to the destination operand. The source operand is not affected. The previous content of the destination is lost. The result is not defined for non-BCD numbers. N: Set if MSB of result is 1 (word > 7999h, byte > 79h), reset if MSB is 0. Z: Set if result is zero, reset otherwise C: Set if the BCD result is too large (word > 9999h, byte > 99h), reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. Decimal 10 is added to the 16-bit BCD counter DECCNTR. DADD #10h,&DECCNTR ; Add 10 to 4-digit BCD counter The eight-digit BCD number contained in 16-bit RAM addresses BCD and BCD+2 is added decimally to an eight-digit BCD number contained in R4 and R5 (BCD+2 and R5 contain the MSDs). The carry C is added, and cleared. CLRC DADD.W &BCD,R4 DADD.W &BCD+2,R5 JC OVERFLOW ... ; Clear carry ; Add LSDs. R4.19:16 = 0 ; Add MSDs with carry. R5.19:16 = 0 ; Result >9999,9999: go to error routine ; Result ok The two-digit BCD number contained in word BCD (16-bit address) is added decimally to a two-digit BCD number contained in R4. The carry C is added, also. R4.19:8 = 0 CLRC DADD.B &BCD,R4 ; Clear carry ; Add BCD to R4 decimally. R4: 0,00ddh 16-Bit MSP430X CPU 4-77 MSP430 Instructions * DEC[.W] * DEC.B Decrement destination Decrement destination Syntax DEC DEC.B dst or DEC.W dst dst Operation dst − 1 −> dst Emulation Emulation SUB #1,dst SUB.B #1,dst Description The destination operand is decremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08000h, otherwise reset. Set if initial value of destination was 080h, otherwise reset. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example R10 is decremented by 1 DEC R10 ; Decrement R10 ; Move a block of 255 bytes from memory location starting with EDE to memory location starting with ;TONI. Tables should not overlap: start of destination address TONI must not be within the range EDE ; to EDE+0FEh ; MOV #EDE,R6 MOV #255,R10 L$1 MOV.B @R6+,TONI−EDE−1(R6) DEC R10 JNZ L$1 ; Do not transfer tables using the routine above with the overlap shown in Figure 4−36. Figure 4−36. Decrement Overlap EDE EDE+254 4-78 16-Bit MSP430X CPU TONI TONI+254 MSP430 Instructions * DECD[.W] * DECD.B Double-decrement destination Double-decrement destination Syntax DECD DECD.B dst or DECD.W dst dst Operation dst − 2 −> dst Emulation Emulation SUB #2,dst SUB.B #2,dst Description The destination operand is decremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08001 or 08000h, otherwise reset. Set if initial value of destination was 081 or 080h, otherwise reset. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example R10 is decremented by 2. DECD R10 ; Decrement R10 by two ; Move a block of 255 words from memory location starting with EDE to memory location ; starting with TONI ; Tables should not overlap: start of destination address TONI must not be within the ; range EDE to EDE+0FEh ; MOV #EDE,R6 MOV #510,R10 L$1 MOV @R6+,TONI−EDE−2(R6) DECD R10 JNZ L$1 Example Memory at location LEO is decremented by two. DECD.B LEO ; Decrement MEM(LEO) Decrement status byte STATUS by two. DECD.B STATUS 16-Bit MSP430X CPU 4-79 MSP430 Instructions * DINT Syntax Operation Emulation Description Status Bits Mode Bits Example Disable (general) interrupts DINT 0 → GIE or (0FFF7h .AND. SR → SR / .NOT.src .AND. dst −> dst) BIC #8,SR All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR. Status bits are not affected. GIE is reset. OSCOFF and CPUOFF are not affected. The general interrupt enable (GIE) bit in the status register is cleared to allow a nondisrupted move of a 32-bit counter. This ensures that the counter is not modified during the move by any interrupt. DINT NOP MOV MOV EINT ; All interrupt events using the GIE bit are disabled COUNTHI,R5 ; Copy counter COUNTLO,R6 ; All interrupt events using the GIE bit are enabled Note: Disable Interrupt If any code sequence needs to be protected from interruption, the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence, or should be followed by a NOP instruction. 4-80 16-Bit MSP430X CPU MSP430 Instructions * EINT Enable (general) interrupts Syntax EINT Operation 1 → GIE or (0008h .OR. SR −> SR / .src .OR. dst −> dst) Emulation BIS #8,SR Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR. Status Bits Status bits are not affected. Mode Bits GIE is set. OSCOFF and CPUOFF are not affected. Example The general interrupt enable (GIE) bit in the status register is set. ; Interrupt routine of ports P1.2 to P1.7 ; P1IN is the address of the register where all port bits are read. P1IFG is the address of ; the register where all interrupt events are latched. ; PUSH.B &P1IN BIC.B @SP,&P1IFG ; Reset only accepted flags EINT ; Preset port 1 interrupt flags stored on stack ; other interrupts are allowed BIT #Mask,@SP JEQ MaskOK ; Flags are present identically to mask: jump ...... MaskOK BIC #Mask,@SP ...... INCD SP ; Housekeeping: inverse to PUSH instruction ; at the start of interrupt subroutine. Corrects ; the stack pointer. RETI Note: Enable Interrupt The instruction following the enable interrupt instruction (EINT) is always executed, even if an interrupt service request is pending when the interrupts are enable. 16-Bit MSP430X CPU 4-81 MSP430 Instructions * INC[.W] * INC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Increment destination Increment destination INC INC.B dst or INC.W dst dst dst + 1 −> dst ADD #1,dst The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The status byte, STATUS, of a process is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B CMP.B JEQ STATUS #11,STATUS OVFL 4-82 16-Bit MSP430X CPU * INCD[.W] * INCD.B Syntax Operation Emulation Emulation Example Status Bits Mode Bits Example Example MSP430 Instructions Double-increment destination Double-increment destination INCD INCD.B dst or INCD.W dst dst dst + 2 −> dst ADD #2,dst ADD.B #2,dst The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The item on the top of the stack (TOS) is removed without using a register. ....... PUSH R5 INCD SP RET ; R5 is the result of a calculation, which is stored ; in the system stack ; Remove TOS by double-increment from stack ; Do not use INCD.B, SP is a word-aligned ; register The byte on the top of the stack is incremented by two. INCD.B 0(SP) ; Byte on TOS is increment by two 16-Bit MSP430X CPU 4-83 MSP430 Instructions * INV[.W] * INV.B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example Invert destination Invert destination INV dst INV.B dst .NOT.dst −> dst XOR #0FFFFh,dst XOR.B #0FFh,dst The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. Content of R5 is negated (twos complement). MOV #00AEh,R5 ; INV R5 ; Invert R5, INC R5 ; R5 is now negated, R5 = 000AEh R5 = 0FF51h R5 = 0FF52h Content of memory byte LEO is negated. MOV.B INV.B INC.B #0AEh,LEO ; MEM(LEO) = 0AEh LEO ; Invert LEO, MEM(LEO) = 051h LEO ; MEM(LEO) is negated,MEM(LEO) = 052h 4-84 16-Bit MSP430X CPU JC JHS Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Jump if carry Jump if Higher or Same (unsigned) JC label JHS label If C = 1: PC + (2 × Offset) → PC If C = 0: execute the following instruction The carry bit C in the status register is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC. This means a jump in the range -511 to +512 words relative to the PC in the full memory range. If C is reset, the instruction after the jump is executed. JC is used for the test of the carry bit C JHS is used for the comparison of unsigned numbers Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected The state of the port 1 pin P1IN.1 bit defines the program flow. BIT.B JC ... #2,&P1IN Label1 ; Port 1, bit 1 set? Bit -> C ; Yes, proceed at Label1 ; No, continue If R5 ≥ R6 (unsigned) the program continues at Label2 CMP JHS ... R6,R5 Label2 ; Is R5 ≥ R6? Info to C ; Yes, C = 1 ; No, R5 < R6. Continue If R5 ≥ 12345h (unsigned operands) the program continues at Label2 CMPA #12345h,R5 JHS Label2 ... ; Is R5 ≥ 12345h? Info to C ; Yes, 12344h < R5 <= F,FFFFh. C = 1 ; No, R5 < 12345h. Continue 16-Bit MSP430X CPU 4-85 MSP430 Instructions JEQ,JZ Syntax Operation Description Status Bits Mode Bits Example Jump if equal,Jump if zero JZ label JEQ label If Z = 1: If Z = 0: PC + (2 × Offset) → PC execute following instruction The Zero bit Z in the status register is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC. This means a jump in the range -511 to +512 words relative to the PC in the full memory range. If Z is reset, the instruction after the jump is executed. JZ is used for the test of the Zero bit Z JEQ is used for the comparison of operands Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected The state of the P2IN.0 bit defines the program flow Example BIT.B JZ ... #1,&P2IN Label1 ; Port 2, bit 0 reset? ; Yes, proceed at Label1 ; No, set, continue If R5 = 15000h (20-bit data) the program continues at Label2 Example CMPA #15000h,R5 JEQ Label2 ... ; Is R5 = 15000h? Info to SR ; Yes, R5 = 15000h. Z = 1 ; No, R5 ≠ 15000h. Continue R7 (20-bit counter) is incremented. If its content is zero, the program continues at Label4. ADDA #1,R7 JZ Label4 ... ; Increment R7 ; Zero reached: Go to Label4 ; R7 ≠ 0. Continue here. 4-86 16-Bit MSP430X CPU JGE Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Jump if Greater or Equal (signed) JGE label If (N .xor. V) = 0: PC + (2 × Offset) → PC If (N .xor. V) = 1: execute following instruction The negative bit N and the overflow bit V in the status register are tested. If both bits are set or both are reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC. This means a jump in the range -511 to +512 words relative to the PC in full Memory range. If only one bit is set, the instruction after the jump is executed. JGE is used for the comparison of signed operands: also for incorrect results due to overflow, the decision made by the JGE instruction is correct. Note: JGE emulates the non-implemented JP (jump if positive) instruction if used after the instructions AND, BIT, RRA, SXTX and TST. These instructions clear the V-bit. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected If byte EDE (lower 64 K) contains positive data, go to Label1. Software can run in the full memory range. TST.B JGE ... &EDE Label1 ; Is EDE positive? V <- 0 ; Yes, JGE emulates JP ; No, 80h <= EDE <= FFh If the content of R6 is greater than or equal to the memory pointed to by R7, the program continues a Label5. Signed data. Data and program in full memory range. CMP JGE ... @R7,R6 Label5 ; Is R6 ≥ @R7? ; Yes, go to Label5 ; No, continue here. If R5 ≥ 12345h (signed operands) the program continues at Label2. Program in full memory range. CMPA JGE ... #12345h,R5 Label2 ; Is R5 ≥ 12345h? ; Yes, 12344h < R5 <= 7FFFFh. ; No, 80000h <= R5 < 12345h. 16-Bit MSP430X CPU 4-87 MSP430 Instructions JL Syntax Operation Description Status Bits Mode Bits Example Jump if Less (signed) JL label If (N .xor. V) = 1: PC + (2 × Offset) → PC If (N .xor. V) = 0: execute following instruction The negative bit N and the overflow bit V in the status register are tested. If only one is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC. This means a jump in the range -511 to +512 words relative to the PC in full memory range. If both bits N and V are set or both are reset, the instruction after the jump is executed. JL is used for the comparison of signed operands: also for incorrect results due to overflow, the decision made by the JL instruction is correct. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected If byte EDE contains a smaller, signed operand than byte TONI, continue at Label1. The address EDE is within PC ± 32 K. Example CMP.B JL ... &TONI,EDE Label1 ; Is EDE < TONI ; Yes ; No, TONI <= EDE If the signed content of R6 is less than the memory pointed to by R7 (20-bit address) the program continues at Label Label5. Data and program in full memory range. Example CMP JL ... @R7,R6 Label5 ; Is R6 < @R7? ; Yes, go to Label5 ; No, continue here. If R5 < 12345h (signed operands) the program continues at Label2. Data and program in full memory range. CMPA JL ... #12345h,R5 Label2 ; Is R5 < 12345h? ; Yes, 80000h =< R5 < 12345h. ; No, 12344h < R5 =< 7FFFFh. 4-88 16-Bit MSP430X CPU JMP Syntax Operation Description Status Bits Mode Bits Example Example MSP430 Instructions Jump unconditionally JMP label PC + (2 × Offset) → PC The signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC. This means an unconditional jump in the range -511 to +512 words relative to the PC in the full memory. The JMP instruction may be used as a BR or BRA instruction within its limited range relative to the program counter. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected The byte STATUS is set to 10. Then a jump to label MAINLOOP is made. Data in lower 64 K, program in full memory range. MOV.B JMP #10,&STATUS ; Set STATUS to 10 MAINLOOP ; Go to main loop The interrupt vector TAIV of Timer_A3 is read and used for the program flow. Program in full memory range, but interrupt handlers always starts in lower 64K. ADD RETI JMP JMP RETI &TAIV,PC IHCCR1 IHCCR2 ; Add Timer_A interrupt vector to PC ; No Timer_A interrupt pending ; Timer block 1 caused interrupt ; Timer block 2 caused interrupt ; No legal interrupt, return 16-Bit MSP430X CPU 4-89 MSP430 Instructions JN Syntax Operation Description Status Bits Mode Bits Example Jump if Negative JN label If N = 1: PC + (2 × Offset) → PC If N = 0: execute following instruction The negative bit N in the status register is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC. This means a jump in the range -511 to +512 words relative to the PC in the full memory range. If N is reset, the instruction after the jump is executed. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected The byte COUNT is tested. If it is negative, program execution continues at Label0. Data in lower 64 K, program in full memory range. Example TST.B JN ... &COUNT Label0 ; Is byte COUNT negative? ; Yes, proceed at Label0 ; COUNT ≥ 0 R6 is subtracted from R5. If the result is negative, program continues at Label2. Program in full memory range. Example SUB JN ... R6,R5 Label2 ; R5 − R6 -> R5 ; R5 is negative: R6 > R5 (N = 1) ; R5 ≥ 0. Continue here. R7 (20-bit counter) is decremented. If its content is below zero, the program continues at Label4. Program in full memory range. SUBA JN ... #1,R7 Label4 ; Decrement R7 ; R7 < 0: Go to Label4 ; R7 ≥ 0. Continue here. 4-90 16-Bit MSP430X CPU JNC JLO Syntax Operation Description Status Bits Mode Bits Example Example MSP430 Instructions Jump if No carry Jump if lower (unsigned) JNC label JLO label If C = 0: PC + (2 × Offset) → PC If C = 1: execute following instruction The carry bit C in the status register is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC. This means a jump in the range -511 to +512 words relative to the PC in the full memory range. If C is set, the instruction after the jump is executed. JNC is used for the test of the carry bit C JLO is used for the comparison of unsigned numbers . Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected If byte EDE < 15 the program continues at Label2. Unsigned data. Data in lower 64 K, program in full memory range. CMP.B JLO ... #15,&EDE Label2 ; Is EDE < 15? Info to C ; Yes, EDE < 15. C = 0 ; No, EDE ≥ 15. Continue The word TONI is added to R5. If no carry occurs, continue at Label0. The address of TONI is within PC ± 32 K. ADD JNC ... TONI,R5 Label0 ; TONI + R5 -> R5. Carry -> C ; No carry ; Carry = 1: continue here 16-Bit MSP430X CPU 4-91 MSP430 Instructions JNZ JNE Syntax Operation Description Status Bits Mode Bits Example Jump if Not Zero Jump if Not Equal JNZ label JNE label If Z = 0: If Z = 1: PC + (2 × Offset) → PC execute following instruction The zero bit Z in the status register is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC. This means a jump in the range -511 to +512 words relative to the PC in the full memory range. If Z is set, the instruction after the jump is executed. JNZ is used for the test of the Zero bit Z JNE is used for the comparison of operands Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected The byte STATUS is tested. If it is not zero, the program continues at Label3. The address of STATUS is within PC ± 32 K. Example TST.B JNZ ... STATUS Label3 ; Is STATUS = 0? ; No, proceed at Label3 ; Yes, continue here If word EDE ≠ 1500 the program continues at Label2. Data in lower 64 K, program in full memory range. Example CMP JNE ... #1500,&EDE Label2 ; Is EDE = 1500? Info to SR ; No, EDE ≠ 1500. ; Yes, R5 = 1500. Continue R7 (20-bit counter) is decremented. If its content is not zero, the program continues at Label4. Program in full memory range. SUBA JNZ ... #1,R7 Label4 ; Decrement R7 ; Zero not reached: Go to Label4 ; Yes, R7 = 0. Continue here. 4-92 16-Bit MSP430X CPU MOV[.W] MOV.B Syntax Operation Description Status Bits Mode Bits Example MSP430 Instructions Move source word to destination word Move source byte to destination byte MOV MOV.B src,dst or MOV.W src,dst src,dst src → dst The source operand is copied to the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Move a 16-bit constant 1800h to absolute address-word EDE (lower 64 K). Example MOV #01800h,&EDE ; Move 1800h to EDE The contents of table EDE (word data, 16-bit addresses) are copied to table TOM. The length of the tables is 030h words. Both tables reside in the lower 64K. Example MOV Loop MOV CMP JLO ... #EDE,R10 ; Prepare pointer (16-bit address) @R10+,TOM-EDE-2(R10) ; R10 points to both tables. R10+2 #EDE+60h,R10 ; End of table reached? Loop ; Not yet ; Copy completed The contents of table EDE (byte data, 16-bit addresses) are copied to table TOM. The length of the tables is 020h bytes. Both tables may reside in full memory range, but must be within R10 ±32 K. Loop MOVA MOV MOV.B DEC JNZ ... #EDE,R10 ; Prepare pointer (20-bit) #20h,R9 ; Prepare counter @R10+,TOM-EDE-1(R10) ; R10 points to both tables. ; R10+1 R9 ; Decrement counter Loop ; Not yet done ; Copy completed 16-Bit MSP430X CPU 4-93 MSP430 Instructions * NOP Syntax Operation Emulation Description Status Bits No operation NOP None MOV #0, R3 No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status bits are not affected. 4-94 16-Bit MSP430X CPU * POP[.W] * POP.B Syntax Operation Emulation Emulation Description Status Bits Example Example Example Example MSP430 Instructions Pop word from stack to destination Pop byte from stack to destination POP dst POP.B dst @SP −> temp SP + 2 −> SP temp −> dst MOV MOV.B @SP+,dst or MOV.W @SP+,dst @SP+,dst The stack location pointed to by the stack pointer (TOS) is moved to the destination. The stack pointer is incremented by two afterwards. Status bits are not affected. The contents of R7 and the status register are restored from the stack. POP POP R7 ; Restore R7 SR ; Restore status register The contents of RAM byte LEO is restored from the stack. POP.B LEO ; The low byte of the stack is moved to LEO. The contents of R7 is restored from the stack. POP.B R7 ; The low byte of the stack is moved to R7, ; the high byte of R7 is 00h The contents of the memory pointed to by R7 and the status register are restored from the stack. POP.B POP 0(R7) SR ; The low byte of the stack is moved to the ; the byte which is pointed to by R7 : Example: R7 = 203h ; Mem(R7) = low byte of system stack : Example: R7 = 20Ah ; Mem(R7) = low byte of system stack ; Last word on stack moved to the SR Note: The System Stack Pointer The system stack pointer (SP) is always incremented by two, independent of the byte suffix. 16-Bit MSP430X CPU 4-95 MSP430 Instructions PUSH[.W] PUSH.B Syntax Operation Description Status Bits Mode Bits Example Save a word on the stack Save a byte on the stack PUSH dst or PUSH.W dst PUSH.B dst SP − 2 → SP dst → @SP The 20-bit stack pointer SP is decremented by two. The operand is then copied to the RAM word addressed by the SP. A pushed byte is stored in the low byte, the high byte is not affected. Not affected. OSCOFF, CPUOFF, and GIE are not affected. Save the two 16-bit registers R9 and R10 on the stack. Example PUSH R9 PUSH R10 ; Save R9 and R10 XXXXh ; YYYYh Save the two bytes EDE and TONI on the stack. The addresses EDE and TONI are within PC ± 32 K. PUSH.B EDE PUSH.B TONI ; Save EDE xxXXh ; Save TONI xxYYh 4-96 16-Bit MSP430X CPU RET Syntax Operation Description Status Bits Mode Bits Example MSP430 Instructions Return from subroutine RET @SP → PC.15:0 Saved PC to PC.15:0. PC.19:16 ← 0 SP + 2 → SP The 16-bit return address (lower 64 K), pushed onto the stack by a CALL instruction is restored to the PC. The program continues at the address following the subroutine call. The four MSBs of the program counter PC.19:16 are cleared. Not affected PC.19:16: Cleared OSCOFF, CPUOFF, and GIE are not affected. Call a subroutine SUBR in the lower 64 K and return to the address in the lower 64K after the CALL CALL ... SUBR PUSH ... POP RET #SUBR R14 R14 Figure 4−37. The Stack After a RET Instruction ; Call subroutine starting at SUBR ; Return by RET to here ; Save R14 (16 bit data) ; Subroutine code ; Restore R14 ; Return to lower 64 K Item n SP PCReturn SP Item n Stack before RET instruction Stack after RET instruction 16-Bit MSP430X CPU 4-97 MSP430 Instructions RETI Syntax Operation Description Status Bits Mode Bits Example Return from interrupt RETI @SP → SR.15:0 Restore saved status register SR with PC.19:16 SP + 2 → SP @SP → PC.15:0 Restore saved program counter PC.15:0 SP + 2 → SP House keeping The status register is restored to the value at the beginning of the interrupt service routine. This includes the four MSBs of the program counter PC.19:16. The stack pointer is incremented by two afterwards. The 20-bit PC is restored from PC.19:16 (from same stack location as the status bits) and PC.15:0. The 20-bit program counter is restored to the value at the beginning of the interrupt service routine. The program continues at the address following the last executed instruction when the interrupt was granted. The stack pointer is incremented by two afterwards. N: restored from stack Z: restored from stack C: restored from stack V: restored from stack OSCOFF, CPUOFF, and GIE are restored from stack Interrupt handler in the lower 64 K. A 20-bit return address is stored on the stack. INTRPT PUSHM.A ... POPM.A RETI #2,R14 #2,R14 ; Save R14 and R13 (20-bit data) ; Interrupt handler code ; Restore R13 and R14 (20-bit data) ; Return to 20-bit address in full memory range 4-98 16-Bit MSP430X CPU MSP430 Instructions * RLA[.W] * RLA.B Syntax Operation Emulation Description Rotate left arithmetically Rotate left arithmetically RLA dst or RLA.W dst RLA.B dst C <− MSB <− MSB−1 .... LSB+1 <− LSB <− 0 ADD dst,dst ADD.B dst,dst The destination operand is shifted left one position as shown in Figure 4−38. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2. An overflow occurs if dst ≥ 04000h and dst < 0C000h before operation is performed: the result has changed sign. Figure 4−38. Destination Operand—Arithmetic Shift Left Word 15 C Byte 7 0 0 0 Status Bits Mode Bits Example Example An overflow occurs if dst ≥ 040h and dst < 0C0h before the operation is performed: the result has changed sign. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R7 is multiplied by 2. RLA R7 ; Shift left R7 (× 2) The low byte of R7 is multiplied by 4. RLA.B R7 RLA.B R7 ; Shift left low byte of R7 (× 2) ; Shift left low byte of R7 (× 4) Note: RLA Substitution The assembler does not recognize the instruction: RLA @R5+, RLA.B @R5+, or It must be substituted by: ADD @R5+,−2(R5) ADD.B @R5+,−1(R5) or RLA(.B) @R5 ADD(.B) @R5 16-Bit MSP430X CPU 4-99 MSP430 Instructions * RLC[.W] * RLC.B Syntax Operation Emulation Description Rotate left through carry Rotate left through carry RLC dst or RLC.W dst RLC.B dst C <− MSB <− MSB−1 .... LSB+1 <− LSB <− C ADDC dst,dst The destination operand is shifted left one position as shown in Figure 4−39. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C). Figure 4−39. Destination Operand—Carry Left Shift Word 15 0 C Byte 7 0 Status Bits Mode Bits Example Example Example N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R5 is shifted left one position. RLC R5 ; (R5 x 2) + C −> R5 The input P1IN.1 information is shifted into the LSB of R5. BIT.B RLC #2,&P1IN R5 ; Information −> Carry ; Carry=P0in.1 −> LSB of R5 The MEM(LEO) content is shifted left one position. RLC.B LEO ; Mem(LEO) x 2 + C −> Mem(LEO) Note: RLC and RLC.B Substitution The assembler does not recognize the instruction: RLC @R5+, RLC.B @R5+, or RLC(.B) @R5 It must be substituted by: ADDC @R5+,−2(R5) ADDC.B @R5+,−1(R5) or ADDC(.B) @R5 4-100 16-Bit MSP430X CPU RRA[.W] RRA.B Syntax Operation Description Status Bits Mode Bits Example MSP430 Instructions Rotate Right Arithmetically destination word Rotate Right Arithmetically destination byte RRA.B dst or RRA.W dst MSB → MSB → MSB-1 . →... LSB+1 → LSB → C The destination operand is shifted right arithmetically by one bit position as shown in Figure 4−40. The MSB retains its value (sign). RRA operates equal to a signed division by 2. The MSB is retained and shifted into the MSB-1. The LSB+1 is shifted into the LSB. The previous LSB is shifted into the carry bit C. N: Set if result is negative (MSB = 1), reset otherwise (MSB = 0) Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 16-bit number in R5 is shifted arithmetically right one position. Example RRA R5 ; R5/2 -> R5 The signed RAM byte EDE is shifted arithmetically right one position. RRA.B EDE ; EDE/2 -> EDE Figure 4−40. Rotate Right Arithmetically RRA.B and RRA.W 19 15 7 0 C 0 0 0 0 0 0 0 0 0 0 0 0 MSB LSB 19 15 0 C 0 0 0 0 MSB LSB 16-Bit MSP430X CPU 4-101 MSP430 Instructions RRC[.W] RRC.B Syntax Operation Description Status Bits Mode Bits Example Rotate Right through carry destination word Rotate Right through carry destination byte RRC RRC.B dst or RRC.W dst dst C → MSB → MSB-1 → ... LSB+1 → LSB → C The destination operand is shifted right by one bit position as shown in Figure 4−41. The carry bit C is shifted into the MSB and the LSB is shifted into the carry bit C. N: Set if result is negative (MSB = 1), reset otherwise (MSB = 0) Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. RAM word EDE is shifted right one bit position. The MSB is loaded with 1. SETC RRC EDE ; Prepare carry for MSB ; EDE = EDE » 1 + 8000h Figure 4−41. Rotate Right through Carry RRC.B and RRC.W 19 15 7 0 C 0 0 0 0 0 0 0 0 0 0 0 0 MSB LSB 19 15 0 C 0 0 0 0 MSB LSB 4-102 16-Bit MSP430X CPU * SBC[.W] * SBC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example MSP430 Instructions Subtract source and borrow/.NOT. carry from destination Subtract source and borrow/.NOT. carry from destination SBC dst or SBC.B dst SBC.W dst dst + 0FFFFh + C −> dst dst + 0FFh + C −> dst SUBC #0,dst SUBC.B #0,dst The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, reset otherwise. OSCOFF, CPUOFF, and GIE are not affected. The 16-bit counter pointed to by R13 is subtracted from a 32-bit counter pointed to by R12. SUB SBC @R13,0(R12) 2(R12) ; Subtract LSDs ; Subtract carry from MSD The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUB.B SBC.B @R13,0(R12) 1(R12) ; Subtract LSDs ; Subtract carry from MSD Note: Borrow Implementation. The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1 16-Bit MSP430X CPU 4-103 MSP430 Instructions * SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB Set carry bit SETC 1 −> C BIS #1,SR The carry bit (C) is set. N: Not affected Z: Not affected C: Set V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Emulation of the decimal subtraction: Subtract R5 from R6 decimally Assume that R5 = 03987h and R6 = 04137h ADD #06666h,R5 INV R5 SETC DADD R5,R6 ; Move content R5 from 0−9 to 6−0Fh ; R5 = 03987h + 06666h = 09FEDh ; Invert this (result back to 0−9) ; R5 = .NOT. R5 = 06012h ; Prepare carry = 1 ; Emulate subtraction by addition of: ; (010000h − R5 − 1) ; R6 = R6 + R5 + 1 ; R6 = 0150h 4-104 16-Bit MSP430X CPU * SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1 −> N BIS #4,SR The negative bit (N) is set. N: Set Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. MSP430 Instructions 16-Bit MSP430X CPU 4-105 MSP430 Instructions * SETZ Syntax Operation Emulation Description Status Bits Mode Bits Set zero bit SETZ 1 −> Z BIS #2,SR The zero bit (Z) is set. N: Not affected Z: Set C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. 4-106 16-Bit MSP430X CPU SUB[.W] SUB.B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Subtract source word from destination word Subtract source byte from destination byte SUB SUB.B src,dst or SUB.W src,dst src,dst (.not.src) + 1 + dst → dst or dst − src → dst The source operand is subtracted from the destination operand. This is made by adding the 1’s complement of the source + 1 to the destination. The source operand is not affected, the result is written to the destination operand. N: Set if result is negative (src > dst), reset if positive (src <= dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive des- tination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. A 16-bit constant 7654h is subtracted from RAM word EDE. SUB #7654h,&EDE ; Subtract 7654h from EDE A table word pointed to by R5 (20-bit address) is subtracted from R7. Afterwards, if R7 contains zero, jump to label TONI. R5 is then auto-incremented by 2. R7.19:16 = 0. SUB JZ ... @R5+,R7 TONI ; Subtract table number from R7. R5 + 2 ; R7 = @R5 (before subtraction) ; R7 <> @R5 (before subtraction) Byte CNT is subtracted from byte R12 points to. The address of CNT is within PC ± 32 K. The address R12 points to is in full memory range. SUB.B CNT,0(R12) ; Subtract CNT from @R12 16-Bit MSP430X CPU 4-107 MSP430 Instructions SUBC[.W] SUBC.B Syntax Operation Description Status Bits Mode Bits Example Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBC src,dst or SUBC.W src,dst SUBC.B src,dst (.not.src) + C + dst → dst or dst − (src − 1) + C → dst The source operand is subtracted from the destination operand. This is done by adding the 1’s complement of the source + carry to the destination. The source operand is not affected, the result is written to the destination operand. Used for 32, 48, and 64-bit operands. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive des- tination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. A 16-bit constant 7654h is subtracted from R5 with the carry from the previous instruction. R5.19:16 = 0 Example SUBC.W #7654h,R5 ; Subtract 7654h + C from R5 A 48-bit number (3 words) pointed to by R5 (20-bit address) is subtracted from a 48-bit counter in RAM, pointed to by R7. R5 points to the next 48-bit number afterwards. The address R7 points to is in full memory range. Example SUB SUBC SUBC @R5+,0(R7) @R5+,2(R7) @R5+,4(R7) ; Subtract LSBs. R5 + 2 ; Subtract MIDs with C. R5 + 2 ; Subtract MSBs with C. R5 + 2 Byte CNT is subtracted from the byte, R12 points to. The carry of the previous instruction is used. The address of CNT is in lower 64 K. SUBC.B &CNT,0(R12) ; Subtract byte CNT from @R12 4-108 16-Bit MSP430X CPU SWPB Syntax Operation Description Status Bits Mode Bits Example MSP430 Instructions Swap bytes SWPB dst dst.15:8 ⇔ dst.7:0 The high and the low byte of the operand are exchanged. PC.19:16 bits are cleared in register mode. Not affected OSCOFF, CPUOFF, and GIE are not affected. Exchange the bytes of RAM word EDE (lower 64 K). MOV SWPB #1234h,&EDE &EDE Figure 4−42. Swap Bytes in Memory ; 1234h -> EDE ; 3412h -> EDE Before SWPB 15 87 0 High Byte Low Byte After SWPB 15 87 0 Low Byte High Byte Figure 4−43. Swap Bytes in a Register Before SWPB 19 16 15 87 0 x High Byte Low Byte After SWPB 19 16 15 87 0 0 ... 0 Low Byte High Byte 16-Bit MSP430X CPU 4-109 MSP430 Instructions SXT Syntax Operation Description Status Bits Mode Bits Example Extend sign SXT dst dst.7 → dst.15:8, dst.7 → dst.19:8 (Register Mode) Register Mode: the sign of the low byte of the operand is extended into the bits Rdst.19:8 Rdst.7 = 0: Rdst.19:8 = 000h afterwards. Rdst.7 = 1: Rdst.19:8 = FFFh afterwards. Other Modes: the sign of the low byte of the operand is extended into the high byte. dst.7 = 0: high byte = 00h afterwards. dst.7 = 1: high byte = FFh afterwards. N: Set if result is negative, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (C = .not.Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 8-bit data in EDE (lower 64 K) is sign extended and added to the 16-bit signed data in R7. Example MOV.B SXT ADD &EDE,R5 R5 R5,R7 ; EDE -> R5. 00XXh ; Sign extend low byte to R5.19:8 ; Add signed 16-bit values The signed 8-bit data in EDE (PC ±32 K) is sign extended and added to the 20-bit data in R7. MOV.B SXT ADDA EDE,R5 R5 R5,R7 ; EDE -> R5. 00XXh ; Sign extend low byte to R5.19:8 ; Add signed 20-bit values 4-110 16-Bit MSP430X CPU * TST[.W] * TST.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example MSP430 Instructions Test destination Test destination TST TST.B dst or TST.W dst dst dst + 0FFFFh + 1 dst + 0FFh + 1 CMP CMP.B #0,dst #0,dst The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. TST JN JZ R7POS ...... R7NEG ...... R7ZERO ...... R7 R7NEG R7ZERO ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TST.B JN JZ ...... ..... ...... R7 R7NEG R7ZERO ; Test low byte of R7 ; Low byte of R7 is negative ; Low byte of R7 is zero ; Low byte of R7 is positive but not zero ; Low byte of R7 is negative ; Low byte of R7 is zero 16-Bit MSP430X CPU 4-111 MSP430 Instructions XOR[.W] XOR.B Syntax Operation Description Status Bits Mode Bits Example Exclusive OR source word with destination word Exclusive OR source byte with destination byte XOR XOR.B dst or XOR.W dst dst src .xor. dst → dst The source and destination operands are exclusively ORed. The result is placed into the destination. The source operand is not affected. The previous content of the destination is lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (C = .not. Z) V: Set if both operands are negative before execution, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Toggle bits in word CNTR (16-bit data) with information (bit = 1) in address-word TONI. Both operands are located in lower 64 K. Example XOR &TONI,&CNTR ; Toggle bits in CNTR A table word pointed to by R5 (20-bit address) is used to toggle bits in R6. R6.19:16 = 0. Example XOR @R5,R6 ; Toggle bits in R6 Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE. R7.19:8 = 0. The address of EDE is within PC ± 32 K. XOR.B INV.B EDE,R7 R7 ; Set different bits to 1 in R7. ; Invert low byte of R7, high byte is 0h 4-112 16-Bit MSP430X CPU Extended Instructions 4.6.3 Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space. Some MSP430X instructions require an additional word of op-code called the extension word. All addresses, indexes, and immediate numbers have 20-bit values, when preceded by the extension word. The MSP430X extended instructions are listed and described in the following pages. For MSP430X instructions that do not require the extension word, it is noted in the instruction description. 16-Bit MSP430X CPU 4-113 Extended Instructions * ADCX.A * ADCX.[W] * ADCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Add carry to destination address-word Add carry to destination word Add carry to destination byte ADCX.A dst ADCX dst ADCX.B dst or ADCX.W dst dst + C −> dst ADDCX.A #0,dst ADDCX #0,dst ADDCX.B #0,dst The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 40-bit counter, pointed to by R12 and R13, is incremented. INCX.A ADCX.A @R12 @R13 ; Increment lower 20 bits ; Add carry to upper 20 bits 4-114 16-Bit MSP430X CPU ADDX.A ADDX[.W] ADDX.B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Add source address-word to destination address-word Add source word to destination word Add source byte to destination byte ADDX.A ADDX ADDX.B src,dst src,dst or ADDX.W src,dst src,dst src + dst → dst The source operand is added to the destination operand. The previous contents of the destination are lost. Both operands can be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Ten is added to the 20-bit pointer CNTR located in two words CNTR (LSBs) and CNTR+2 (MSBs). ADDX.A #10,CNTR ; Add 10 to 20-bit pointer A table word (16-bit) pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is performed on a carry. ADDX.W JC ... @R5,R6 TONI ; Add table word to R6 ; Jump if carry ; No carry A table byte pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. ADDX.B JNC ... @R5+,R6 TONI ; Add table byte to R6. R5 + 1. R6: 000xxh ; Jump if no carry ; Carry occurred Note: Use ADDA for the following two cases for better code density and execution. ADDX.A Rsrc,Rdst or ADDX.A #imm20,Rdst 16-Bit MSP430X CPU 4-115 Extended Instructions ADDCX.A ADDCX[.W] ADDCX.B Syntax Operation Description Status Bits Mode Bits Example Add source address-word and carry to destination address-word Add source word and carry to destination word Add source byte and carry to destination byte ADDCX.A src,dst ADDCX src,dst or ADDCX.W src,dst ADDCX.B src,dst src + dst + C → dst The source operand and the carry bit C are added to the destination operand. The previous contents of the destination are lost. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Constant 15 and the carry of the previous instruction are added to the 20-bit counter CNTR located in two words. Example ADDCX.A #15,&CNTR ; Add 15 + C to 20-bit CNTR A table word pointed to by R5 (20-bit address) and the carry C are added to R6. The jump to label TONI is performed on a carry. Example ADDCX.W JC ... @R5,R6 TONI ; Add table word + C to R6 ; Jump if carry ; No carry A table byte pointed to by R5 (20-bit address) and the carry bit C are added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. ADDCX.B JNC ... @R5+,R6 TONI ; Add table byte + C to R6. R5 + 1 ; Jump if no carry ; Carry occurred 4-116 16-Bit MSP430X CPU ANDX.A ANDX[.W] ANDX.B Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Logical AND of source address-word with destination address-word Logical AND of source word with destination word Logical AND of source byte with destination byte ANDX.A ANDX ANDX.B src,dst src,dst or ANDX.W src,dst src,dst src .and. dst → dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The bits set in R5 (20-bit data) are used as a mask (AAA55h) for the address-word TOM located in two words. If the result is zero, a branch is taken to label TONI. MOVA ANDX.A JZ ... or shorter: #AAA55h,R5 R5,TOM TONI ; Load 20-bit mask to R5 ; TOM .and. R5 -> TOM ; Jump if result 0 ; Result > 0 ANDX.A JZ #AAA55h,TOM TONI ; TOM .and. AAA55h -> TOM ; Jump if result 0 A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R6.19:8 = 0. The table pointer is auto-incremented by 1. ANDX.B @R5+,R6 ; AND table byte with R6. R5 + 1 16-Bit MSP430X CPU 4-117 Extended Instructions BICX.A BICX[.W] BICX.B Syntax Operation Description Status Bits Mode Bits Example Clear bits set in source address-word in destination address-word Clear bits set in source word in destination word Clear bits set in source byte in destination byte BICX.A BICX BICX.B src,dst src,dst or BICX.W src,dst src,dst (.not. src) .and. dst → dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Both operands may be located in the full address space. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The bits 19:15 of R5 (20-bit data) are cleared. Example BICX.A #0F8000h,R5 ; Clear R5.19:15 bits A table word pointed to by R5 (20-bit address) is used to clear bits in R7. R7.19:16 = 0 Example BICX.W @R5,R7 ; Clear bits in R7 A table byte pointed to by R5 (20-bit address) is used to clear bits in output Port1. BICX.B @R5,&P1OUT ; Clear I/O port P1 bits 4-118 16-Bit MSP430X CPU BISX.A BISX[.W] BISX.B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Set bits set in source address-word in destination address-word Set bits set in source word in destination word Set bits set in source byte in destination byte BISX.A BISX BISX.B src,dst src,dst or BISX.W src,dst src,dst src .or. dst → dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Both operands may be located in the full address space. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Bits 16 and 15 of R5 (20-bit data) are set to one. BISX.A #018000h,R5 ; Set R5.16:15 bits A table word pointed to by R5 (20-bit address) is used to set bits in R7. BISX.W @R5,R7 ; Set bits in R7 A table byte pointed to by R5 (20-bit address) is used to set bits in output Port1. BISX.B @R5,&P1OUT ; Set I/O port P1 bits 16-Bit MSP430X CPU 4-119 Extended Instructions BITX.A BITX[.W] BITX.B Syntax Operation Description Status Bits Mode Bits Example Test bits set in source address-word in destination address-word Test bits set in source word in destination word Test bits set in source byte in destination byte BITX.A BITX BITX.B src,dst src,dst or BITX.W src,dst src,dst src .and. dst The source operand and the destination operand are logically ANDed. The result affects only the status bits. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. Test if bit 16 or 15 of R5 (20-bit data) is set. Jump to label TONI if so. Example BITX.A JNZ ... #018000h,R5 TONI ; Test R5.16:15 bits ; At least one bit is set ; Both are reset A table word pointed to by R5 (20-bit address) is used to test bits in R7. Jump to label TONI if at least one bit is set. Example BITX.W JC ... @R5,R7 TONI ; Test bits in R7: C = .not.Z ; At least one is set ; Both are reset A table byte pointed to by R5 (20-bit address) is used to test bits in input Port1. Jump to label TONI if no bit is set. The next table byte is addressed. BITX.B JNC ... @R5+,&P1IN TONI ; Test input P1 bits. R5 + 1 ; No corresponding input bit is set ; At least one bit is set 4-120 16-Bit MSP430X CPU * CLRX.A * CLRX.[W] * CLRX.B Syntax Operation Emulation Description Status Bits Example Clear destination address-word Clear destination word Clear destination byte CLRX.A CLRX CLRX.B dst dst or CLRX.W dst dst 0 −> dst MOVX.A MOVX MOVX.B #0,dst #0,dst #0,dst The destination operand is cleared. Status bits are not affected. RAM address-word TONI is cleared. CLRX.A TONI ; 0 −> TONI Extended Instructions 16-Bit MSP430X CPU 4-121 Extended Instructions CMPX.A CMPX[.W] CMPX.B Syntax Operation Description Status Bits Mode Bits Example Compare source address-word and destination address-word Compare source word and destination word Compare source byte and destination byte CMPX.A CMPX CMPX.B src,dst src,dst or CMPX.W src,dst src,dst (.not. src) + 1 + dst or dst − src The source operand is subtracted from the destination operand by adding the 1’s complement of the source + 1 to the destination. The result affects only the status bits. Both operands may be located in the full address space. N: Set if result is negative (src > dst), reset if positive (src <= dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. Compare EDE with a 20-bit constant 18000h. Jump to label TONI if EDE equals the constant. Example CMPX.A JEQ ... #018000h,EDE TONI ; Compare EDE with 18000h ; EDE contains 18000h ; Not equal A table word pointed to by R5 (20-bit address) is compared with R7. Jump to label TONI if R7 contains a lower, signed, 16-bit number. Example CMPX.W JL ... @R5,R7 TONI ; Compare two signed numbers ; R7 < @R5 ; R7 >= @R5 A table byte pointed to by R5 (20-bit address) is compared to the input in I/O Port1. Jump to label TONI if the values are equal. The next table byte is addressed. CMPX.B JEQ ... @R5+,&P1IN TONI ; Compare P1 bits with table. R5 + 1 ; Equal contents ; Not equal Note: Use CMPA for the following two cases for better density and execution. CMPA Rsrc,Rdst or CMPA #imm20,Rdst 4-122 16-Bit MSP430X CPU * DADCX.A * DADCX[.W] * DADCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Add carry decimally to destination address-word Add carry decimally to destination word Add carry decimally to destination byte DADCX.A DADCX DADCX.B dst dst or DADCX.W src,dst dst dst + C −> dst (decimally) DADDX.A DADDX DADDX.B #0,dst #0,dst #0,dst The carry bit (C) is added decimally to the destination. N: Set if MSB of result is 1 (address-word > 79999h, word > 7999h, byte > 79h), reset if MSB is 0. Z: Set if result is zero, reset otherwise. C: Set if the BCD result is too large (address-word > 99999h, word > 9999h, byte > 99h), reset otherwise. V: Undefined. OSCOFF, CPUOFF, and GIE are not affected. The 40-bit counter, pointed to by R12 and R13, is incremented decimally. DADDX.A #1,0(R12) ; Increment lower 20 bits DADCX.A 0(R13) ; Add carry to upper 20 bits 16-Bit MSP430X CPU 4-123 Extended Instructions DADDX.A DADDX[.W] DADDX.B Syntax Operation Description Status Bits Mode Bits Example Add source address-word and carry decimally to destination address-word Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADDX.A src,dst DADDX src,dst or DADDX.W src,dst DADDX.B src,dst src + dst + C → dst (decimally) The source operand and the destination operand are treated as two (.B), four (.W), or five (.A) binary coded decimals (BCD) with positive signs. The source operand and the carry bit C are added decimally to the destination operand. The source operand is not affected. The previous contents of the destination are lost. The result is not defined for non-BCD numbers. Both operands may be located in the full address space. N: Set if MSB of result is 1 (address-word > 79999h, word > 7999h, byte > 79h), reset if MSB is 0. Z: Set if result is zero, reset otherwise. C: Set if the BCD result is too large (address-word > 99999h, word > 9999h, byte > 99h), reset otherwise. V: Undefined. OSCOFF, CPUOFF, and GIE are not affected. Decimal 10 is added to the 20-bit BCD counter DECCNTR located in two words. Example DADDX.A #10h,&DECCNTR ; Add 10 to 20-bit BCD counter The eight-digit BCD number contained in 20-bit addresses BCD and BCD+2 is added decimally to an eight-digit BCD number contained in R4 and R5 (BCD+2 and R5 contain the MSDs). Example CLRC DADDX.W DADDX.W JC ... ; Clear carry BCD,R4 ; Add LSDs BCD+2,R5 ; Add MSDs with carry OVERFLOW ; Result >99999999: go to error routine ; Result ok The two-digit BCD number contained in 20-bit address BCD is added decimally to a two-digit BCD number contained in R4. CLRC DADDX.B BCD,R4 ; Clear carry ; Add BCD to R4 decimally. ; R4: 000ddh 4-124 16-Bit MSP430X CPU * DECX.A * DECX[.W] * DECX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Decrement destination address-word Decrement destination word Decrement destination byte DECX dst DECX dst or DECX.W dst DECX.B dst dst − 1 −> dst SUBX.A #1,dst SUBX #1,dst SUBX.B #1,dst The destination operand is decremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. OSCOFF, CPUOFF, and GIE are not affected. RAM address-word TONI is decremented by 1 DECX.A TONI ; Decrement TONI 16-Bit MSP430X CPU 4-125 Extended Instructions * DECDX.A * DECDX[.W] * DECDX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Double-decrement destination address-word Double-decrement destination word Double-decrement destination byte DECDX.A dst DECDX dst or DECDX.W dst DECDX.B dst dst − 2 −> dst SUBX.A #2,dst SUBX #2,dst SUBX.B #2,dst The destination operand is decremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. OSCOFF, CPUOFF, and GIE are not affected. RAM address-word TONI is decremented by 2. DECDX.A TONI ; Decrement TONI by two 4-126 16-Bit MSP430X CPU * INCX.A * INCX[.W] * INCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Increment destination address-word Increment destination word Increment destination byte INCX.A INCX INCX.B dst dst or INCX.W dst dst dst + 1 −> dst ADDX.A #1,dst ADDX #1,dst ADDX.B #1,dst The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFFh, reset otherwise Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFFh, reset otherwise Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. RAM address-word TONI is incremented by 1. INCX.A TONI ; Increment TONI (20-bits) 16-Bit MSP430X CPU 4-127 Extended Instructions * INCDX.A * INCDX[.W] * INCDX.B Syntax Operation Emulation Example Status Bits Mode Bits Example Double-increment destination address-word Double-increment destination word Double-increment destination byte INCDX.A INCDX INCDX.B dst dst or INCDX.W dst dst dst + 2 −> dst ADDX.A #2,dst ADDX #2,dst ADDX.B #2,dst The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFEh, reset otherwise Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFFEh or 0FFFFFh, reset otherwise Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFFEh or 07FFFFh, reset otherwise Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. RAM byte LEO is incremented by two; PC points to upper memory INCDX.B LEO ; Increment LEO by two 4-128 16-Bit MSP430X CPU * INVX.A * INVX[.W] * INVX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Extended Instructions Invert destination Invert destination Invert destination INVX.A dst INVX dst or INVX.W dst INVX.B dst .NOT.dst −> dst XORX.A #0FFFFFh,dst XORX #0FFFFh,dst XORX.B #0FFh,dst The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFFh, reset otherwise Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. 20-bit content of R5 is negated (twos complement). INVX.A R5 ; Invert R5 INCX.A R5 ; R5 is now negated Content of memory byte LEO is negated. PC is pointing to upper memory INVX.B LEO ; Invert LEO INCX.B LEO ; MEM(LEO) is negated 16-Bit MSP430X CPU 4-129 Extended Instructions MOVX.A MOVX[.W] MOVX.B Syntax Operation Description Status Bits Mode Bits Example Move source address-word to destination address-word Move source word to destination word Move source byte to destination byte MOVX.A MOVX MOVX.B src,dst src,dst or MOVX.W src,dst src,dst src → dst The source operand is copied to the destination. The source operand is not affected. Both operands may be located in the full address space. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Move a 20-bit constant 18000h to absolute address-word EDE. Example MOVX.A #018000h,&EDE ; Move 18000h to EDE The contents of table EDE (word data, 20-bit addresses) are copied to table TOM. The length of the table is 030h words. Example Loop MOVA MOVX.W CMPA JLO ... #EDE,R10 ; Prepare pointer (20-bit address) @R10+,TOM-EDE-2(R10) ; R10 points to both tables. R10+2 #EDE+60h,R10 ; End of table reached? Loop ; Not yet ; Copy completed The contents of table EDE (byte data, 20-bit addresses) are copied to table TOM. The length of the table is 020h bytes. Loop MOVA MOV MOVX.B DEC JNZ ... #EDE,R10 ; Prepare pointer (20-bit) #20h,R9 ; Prepare counter @R10+,TOM-EDE-1(R10) ; R10 points to both tables. ; R10+1 R9 ; Decrement counter Loop ; Not yet done ; Copy completed 4-130 16-Bit MSP430X CPU Extended Instructions Ten of the 28 possible addressing combinations of the MOVX.A instruction can use the MOVA instruction. This saves two bytes and code cycles. Examples for the addressing combinations are: MOVX.A MOVX.A MOVX.A MOVX.A MOVX.A MOVX.A Rsrc,Rdst #imm20,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,&abs20 MOVA Rsrc,Rdst MOVA #imm20,Rdst MOVA &abs20,Rdst MOVA @Rsrc,Rdst MOVA @Rsrc+,Rdst MOVA Rsrc,&abs20 ; Reg/Reg ; Immediate/Reg ; Absolute/Reg ; Indirect/Reg ; Indirect,Auto/Reg ; Reg/Absolute The next four replacements are possible only if 16-bit indexes are sufficient for the addressing. MOVX.A MOVX.A MOVX.A MOVX.A z20(Rsrc),Rdst Rsrc,z20(Rdst) symb20,Rdst Rsrc,symb20 MOVA z16(Rsrc),Rdst ; Indexed/Reg MOVA Rsrc,z16(Rdst) ; Reg/Indexed MOVA symb16,Rdst ; Symbolic/Reg MOVA Rsrc,symb16 ; Reg/Symbolic 16-Bit MSP430X CPU 4-131 Extended Instructions POPM.A POPM[.W] Syntax Operation Description Status Bits Mode Bits Example Restore n CPU registers (20-bit data) from the stack Restore n CPU registers (16-bit data) from the stack POPM.A #n,Rdst POPM.W #n,Rdst 1 ≤ n ≤ 16 or POPM #n,Rdst 1 ≤ n ≤ 16 POPM.A: Restore the register values from stack to the specified CPU registers. The stack pointer SP is incremented by four for each register restored from stack. The 20-bit values from stack (2 words per register) are restored to the registers. POPM.W: Restore the 16-bit register values from stack to the specified CPU registers. The stack pointer SP is incremented by two for each register restored from stack. The 16-bit values from stack (one word per register) are restored to the CPU registers. Note : This does not use the extension word. POPM.A: The CPU registers pushed on the stack are moved to the extended CPU registers, starting with the CPU register (Rdst - n + 1). The stack pointer is incremented by (n × 4) after the operation. POPM.W: The 16-bit registers pushed on the stack are moved back to the CPU registers, starting with CPU register (Rdst - n + 1). The stack pointer is incremented by (n × 2) after the instruction. The MSBs (Rdst.19:16) of the restored CPU registers are cleared Not affected, except SR is included in the operation OSCOFF, CPUOFF, and GIE are not affected, except SR is included in the operation. Restore the 20-bit registers R9, R10, R11, R12, R13 from the stack. Example POPM.A #5,R13 ; Restore R9, R10, R11, R12, R13 Restore the 16-bit registers R9, R10, R11, R12, R13 from the stack. POPM.W #5,R13 ; Restore R9, R10, R11, R12, R13 4-132 16-Bit MSP430X CPU PUSHM.A PUSHM[.W] Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Save n CPU registers (20-bit data) on the stack Save n CPU registers (16-bit words) on the stack PUSHM.A PUSHM.W #n,Rdst 1 ≤ n ≤ 16 #n,Rdst or PUSHM #n,Rdst 1 ≤ n ≤ 16 PUSHM.A: Save the 20-bit CPU register values on the stack. The stack pointer (SP) is decremented by four for each register stored on the stack. The MSBs are stored first (higher address). PUSHM.W: Save the 16-bit CPU register values on the stack. The stack pointer is decremented by two for each register stored on the stack. PUSHM.A: The n CPU registers, starting with Rdst backwards, are stored on the stack. The stack pointer is decremented by (n × 4) after the operation. The data (Rn.19:0) of the pushed CPU registers is not affected. PUSHM.W: The n registers, starting with Rdst backwards, are stored on the stack. The stack pointer is decremented by (n × 2) after the operation. The data (Rn.19:0) of the pushed CPU registers is not affected. Note : This instruction does not use the extension word. Not affected. OSCOFF, CPUOFF, and GIE are not affected. Save the five 20-bit registers R9, R10, R11, R12, R13 on the stack. PUSHM.A #5,R13 ; Save R13, R12, R11, R10, R9 Save the five 16-bit registers R9, R10, R11, R12, R13 on the stack. PUSHM.W #5,R13 ; Save R13, R12, R11, R10, R9 16-Bit MSP430X CPU 4-133 Extended Instructions * POPX.A * POPX[.W] * POPX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Restore single address-word from the stack Restore single word from the stack Restore single byte from the stack POPX.A POPX POPX.B dst dst or POPX.W dst dst Restore the 8/16/20-bit value from the stack to the destination. 20-bit addresses are possible. The stack pointer SP is incremented by two (byte and word operands) and by four (address-word operand). MOVX(.B,.A) @SP+,dst The item on TOS is written to the destination operand. Register Mode, Indexed Mode, Symbolic Mode, and Absolute Mode are possible. The stack pointer is incremented by two or four. Note: the stack pointer is incremented by two also for byte operations. Not affected. OSCOFF, CPUOFF, and GIE are not affected. Write the 16-bit value on TOS to the 20-bit address &EDE. Example POPX.W &EDE ; Write word to address EDE Write the 20-bit value on TOS to R9. POPX.A R9 ; Write address-word to R9 4-134 16-Bit MSP430X CPU PUSHX.A PUSHX[.W] PUSHX.B Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Save a single address-word on the stack Save a single word on the stack Save a single byte on the stack PUSHX.A src PUSHX src or PUSHX.W src PUSHX.B src Save the 8/16/20-bit value of the source operand on the TOS. 20-bit addresses are possible. The stack pointer (SP) is decremented by two (byte and word operands) or by four (address-word operand) before the write operation. The stack pointer is decremented by two (byte and word operands) or by four (address-word operand). Then the source operand is written to the TOS. All seven addressing modes are possible for the source operand. Note : This instruction does not use the extension word. Not affected. OSCOFF, CPUOFF, and GIE are not affected. Save the byte at the 20-bit address &EDE on the stack. PUSHX.B &EDE ; Save byte at address EDE Save the 20-bit value in R9 on the stack. PUSHX.A R9 ; Save address-word in R9 16-Bit MSP430X CPU 4-135 Extended Instructions RLAM.A RLAM[.W] Syntax Operation Description Status Bits Mode Bits Example Rotate Left Arithmetically the 20-bit CPU register content Rotate Left Arithmetically the 16-bit CPU register content RLAM.A #n,Rdst RLAM.W #n,Rdst 1≤n≤4 or RLAM #n,Rdst 1≤n≤4 C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 The destination operand is shifted arithmetically left one, two, three, or four positions as shown in Figure 4−44. RLAM works as a multiplication (signed and unsigned) with 2, 4, 8, or 16. The word instruction RLAM.W clears the bits Rdst.19:16 Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the MSB (n = 1), MSB-1 (n = 2), MSB-2 (n = 3), MSB-3 (n = 4) V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The 20-bit operand in R5 is shifted left by three positions. It operates equal to an arithmetic multiplication by 8. RLAM.A #3,R5 ; R5 = R5 x 8 Figure 4−44. Rotate Left Arithmetically RLAM[.W] and RLAM.A 19 16 15 C 0000 MSB 0 LSB 0 19 C MSB 0 LSB 0 4-136 16-Bit MSP430X CPU Extended Instructions * RLAX.A * RLAX[.W] * RLAX.B Syntax Operation Emulation Description Rotate left arithmetically address-word Rotate left arithmetically word Rotate left arithmetically byte RLAX.B dst RLAX dst or RLAX.W dst RLAX.B dst C <− MSB <− MSB−1 .... LSB+1 <− LSB <− 0 ADDX.A dst,dst ADDX dst,dst ADDX.B dst,dst The destination operand is shifted left one position as shown in Figure 4−45. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLAX instruction acts as a signed multiplication by 2. Figure 4−45. Destination Operand—Arithmetic Shift Left MSB C 0 0 Status Bits Mode Bits Example N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs: the initial value is 040000h ≤ dst < 0C0000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R7 is multiplied by 2. RLAX.A R7 ; Shift left R7 (20-bit) 16-Bit MSP430X CPU 4-137 Extended Instructions * RLCX.A * RLCX[.W] * RLCX.B Syntax Operation Emulation Description Rotate left through carry address-word Rotate left through carry word Rotate left through carry byte RLCX.A dst RLCX dst or RLCX.B dst RLCX.W dst C <− MSB <− MSB−1 .... LSB+1 <− LSB <− C ADDCX.A dst,dst ADDCX dst,dst ADDCX.B dst,dst The destination operand is shifted left one position as shown in Figure 4−46. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C). Figure 4−46. Destination Operand—Carry Left Shift MSB 0 C Status Bits Mode Bits Example Example N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs the initial value is 040000h ≤ dst < 0C0000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is shifted left one position. RLCX.A R5 ; (R5 x 2) + C −> R5 The RAM byte LEO is shifted left one position. PC is pointing to upper memory RLCX.B LEO ; RAM(LEO) x 2 + C −> RAM(LEO) 4-138 16-Bit MSP430X CPU RRAM.A RRAM[.W] Syntax Operation Description Status Bits Mode Bits Example Extended Instructions Rotate Right Arithmetically the 20-bit CPU register content Rotate Right Arithmetically the 16-bit CPU register content RRAM.A #n,Rdst RRAM.W #n,Rdst 1≤n≤4 or RRAM #n,Rdst 1≤n≤4 MSB → MSB → MSB-1 …. LSB+1 → LSB → C The destination operand is shifted right arithmetically by one, two, three, or four bit positions as shown in Figure 4−47. The MSB retains its value (sign). RRAM operates equal to a signed division by 2/4/8/16. The MSB is retained and shifted into MSB-1. The LSB+1 is shifted into the LSB, and the LSB is shifted into the carry bit C. The word instruction RRAM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 20-bit number in R5 is shifted arithmetically right two positions. Example RRAM.A #2,R5 ; R5/4 -> R5 The signed 20-bit value in R15 is multiplied by 0.75. (0.5 + 0.25) x R15 PUSHM.A RRAM.A ADDX.A RRAM.A #1,R15 #1,R15 @SP+,R15 #1,R15 ; Save extended R15 on stack ; R15 × 0.5 -> R15 ; R15 × 0.5 + R15 = 1.5 × R15 -> R15 ; (1.5 × R15) × 0.5 = 0.75 × R15 -> R15 Figure 4−47. Rotate Right Arithmetically RRAM[.W] and RRAM.A 19 16 15 0 C 0000 MSB LSB 19 0 C MSB LSB 16-Bit MSP430X CPU 4-139 Extended Instructions RRAX.A RRAX[.W] RRAX.B Syntax Operation Description Status Bits Mode Bits Rotate Right Arithmetically the 20-bit operand Rotate Right Arithmetically the 16-bit operand Rotate Right Arithmetically the 8-bit operand RRAX.A RRAX.W RRAX RRAX.B Rdst Rdst Rdst Rdst RRAX.A dst RRAX.W dst or RRAX.B dst RRAX dst MSB → MSB → MSB-1 . ... LSB+1 → LSB → C Register Mode for the destination: the destination operand is shifted right by one bit position as shown in Figure 4−48. The MSB retains its value (sign). The word instruction RRAX.W clears the bits Rdst.19:16, the byte instruction RRAX.B clears the bits Rdst.19:8. The MSB retains its value (sign), the LSB is shifted into the carry bit. RRAX here operates equal to a signed division by 2. All other modes for the destination: the destination operand is shifted right arithmetically by one bit position as shown in Figure 4−49. The MSB retains its value (sign), the LSB is shifted into the carry bit. RRAX here operates equal to a signed division by 2. All addressing modes − with the exception of the Immediate Mode − are possible in the full memory. N: Set if result is negative .A: dst.19 = 1, reset if dst.19 = 0 .W: dst.15 = 1, reset if dst.15 = 0 .B: dst.7 = 1, reset if dst.7 = 0 Z: Set if result is zero, reset otherwise C: Loaded from LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. 4-140 16-Bit MSP430X CPU Example Extended Instructions The signed 20-bit number in R5 is shifted arithmetically right four positions. Example RPT #4 RRAX.A R5 ; R5/16 −> R5 The signed 8-bit value in EDE is multiplied by 0.5. RRAX.B &EDE ; EDE/2 -> EDE Figure 4−48. Rotate Right Arithmetically RRAX(.B,.A). Register Mode 19 8 7 0 C 0 0 MSB LSB 19 16 15 0 C 0000 MSB LSB 19 0 C MSB LSB Figure 4−49. Rotate Right Arithmetically RRAX(.B,.A). Non-Register Mode 7 0 C MSB LSB C 31 0 19 C MSB 15 MSB 0 LSB 20 0 0 LSB 16-Bit MSP430X CPU 4-141 Extended Instructions RRCM.A RRCM[.W] Syntax Operation Description Status Bits Mode Bits Example Rotate Right through carry the 20-bit CPU register content Rotate Right through carry the 16-bit CPU register content RRCM.A #n,Rdst RRCM.W #n,Rdst 1≤n≤4 or RRCM #n,Rdst 1≤n≤4 C → MSB → MSB-1 → ... LSB+1 → LSB → C The destination operand is shifted right by one, two, three, or four bit positions as shown in Figure 4−50. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. The word instruction RRCM.W clears the bits Rdst.19:16 Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3) or LSB+3 (n = 4) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The address-word in R5 is shifted right by three positions. The MSB-2 is loaded with 1. Example SETC RRCM.A #3,R5 ; Prepare carry for MSB-2 ; R5 = R5 » 3 + 20000h The word in R6 is shifted right by two positions. The MSB is loaded with the LSB. The MSB-1 is loaded with the contents of the carry flag. RRCM.W #2,R6 ; R6 = R6 » 2. R6.19:16 = 0 Figure 4−50. Rotate Right Through Carry RRCM[.W] and RRCM.A 19 16 15 0 C 0 MSB LSB 19 0 C MSB LSB 4-142 16-Bit MSP430X CPU RRCX.A RRCX[.W] RRCX.B Syntax Operation Description Status Bits Mode Bits Extended Instructions Rotate Right through carry the 20-bit operand Rotate Right through carry the 16-bit operand Rotate Right through carry the 8-bit operand RRCX.A RRCX.W RRCX RRCX.B Rdst Rdst Rdst Rdst RRCX.A dst RRCX.W dst or RRCX.B dst RRCX dst C → MSB → MSB-1 → ... LSB+1 → LSB → C Register Mode for the destination: the destination operand is shifted right by one bit position as shown in Figure 4−51. The word instruction RRCX.W clears the bits Rdst.19:16, the byte instruction RRCX.B clears the bits Rdst.19:8. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. All other modes for the destination: the destination operand is shifted right by one bit position as shown in Figure 4−52. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. All addressing modes − with the exception of the Immediate Mode − are possible in the full memory. N: Set if result is negative .A: dst.19 = 1, reset if dst.19 = 0 .W: dst.15 = 1, reset if dst.15 = 0 .B: dst.7 = 1, reset if dst.7 = 0 Z: Set if result is zero, reset otherwise C: Loaded from LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. 16-Bit MSP430X CPU 4-143 Extended Instructions Example The 20-bit operand at address EDE is shifted right by one position. The MSB is loaded with 1. Example SETC RRCX.A EDE ; Prepare carry for MSB ; EDE = EDE » 1 + 80000h The word in R6 is shifted right by twelve positions. RPT #12 RRCX.W R6 ; R6 = R6 » 12. R6.19:16 = 0 Figure 4−51. Rotate Right Through Carry RRCX(.B,.A). Register Mode 19 87 0 C 0 − − − − − − − − − − − − − − − − − − − − 0 MSB LSB 19 16 15 0 C 0000 MSB LSB 19 0 C MSB LSB Figure 4−52. Rotate Right Through Carry RRCX(.B,.A). Non-Register Mode 7 0 C MSB LSB C 31 0 19 C MSB 15 MSB 0 LSB 20 0 0 LSB 4-144 16-Bit MSP430X CPU RRUM.A RRUM[.W] Syntax Operation Description Status Bits Mode Bits Example Extended Instructions Rotate Right Unsigned the 20-bit CPU register content Rotate Right Unsigned the 16-bit CPU register content RRUM.A #n,Rdst RRUM.W #n,Rdst 1≤n≤4 or RRUM #n,Rdst 1≤n≤4 0 → MSB → MSB-1 . →... LSB+1 → LSB → C The destination operand is shifted right by one, two, three, or four bit positions as shown in Figure 4−53. Zero is shifted into the MSB, the LSB is shifted into the carry bit. RRUM works like an unsigned division by 2, 4, 8, or 16. The word instruction RRUM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3) or LSB+3 (n = 4) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The unsigned address-word in R5 is divided by 16. Example RRUM.A #4,R5 ; R5 = R5 » 4. R5/16 The word in R6 is shifted right by one bit. The MSB R6.15 is loaded with 0. RRUM.W #1,R6 ; R6 = R6/2. R6.19:15 = 0 Figure 4−53. Rotate Right Unsigned RRUM[.W] and RRUM.A 19 16 15 0 C 0000 MSB LSB 0 19 0 C 0 MSB LSB 16-Bit MSP430X CPU 4-145 Extended Instructions RRUX.A RRUX[.W] RRUX.B Syntax Operation Description Status Bits Mode Bits Example Rotate Right unsigned the 20-bit operand Rotate Right unsigned the 16-bit operand Rotate Right unsigned the 8-bit operand RRUX.A RRUX.W RRUX RRUX.B Rdst Rdst Rdst Rdst C=0 → MSB → MSB-1 → ... LSB+1 → LSB → C RRUX is valid for register Mode only: the destination operand is shifted right by one bit position as shown in Figure 4−54. The word instruction RRUX.W clears the bits Rdst.19:16. The byte instruction RRUX.B clears the bits Rdst.19:8. Zero is shifted into the MSB, the LSB is shifted into the carry bit. N: Set if result is negative .A: dst.19 = 1, reset if dst.19 = 0 .W: dst.15 = 1, reset if dst.15 = 0 .B: dst.7 = 1, reset if dst.7 = 0 Z: Set if result is zero, reset otherwise C: Loaded from LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The word in R6 is shifted right by twelve positions. RPT #12 RRUX.W R6 ; R6 = R6 » 12. R6.19:16 = 0 Figure 4−54. Rotate Right Unsigned RRUX(.B,.A). Register Mode 19 87 0 C 0 − − − − − − − − − − − − − − − − − − − − 0 MSB LSB 0 19 16 15 0 C 0000 MSB LSB 0 19 0 C 0 MSB LSB 4-146 16-Bit MSP430X CPU * SBCX.A * SBCX[.W] * SBCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Subtract source and borrow/.NOT. carry from destination address-word Subtract source and borrow/.NOT. carry from destination word Subtract source and borrow/.NOT. carry from destination byte SBCX.A dst SBCX dst or SBCX.B dst SBCX.W dst dst + 0FFFFFh + C −> dst dst + 0FFFFh + C −> dst dst + 0FFh + C −> dst SUBCX.A SUBCX SUBCX.B #0,dst #0,dst #0,dst The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, reset otherwise. OSCOFF, CPUOFF, and GIE are not affected. The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUBX.B SBCX.B @R13,0(R12) 1(R12) ; Subtract LSDs ; Subtract carry from MSD Note: Borrow Implementation. The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1 16-Bit MSP430X CPU 4-147 Extended Instructions SUBX.A SUBX[.W] SUBX.B Syntax Operation Description Status Bits Mode Bits Example Subtract source address-word from destination address-word Subtract source word from destination word Subtract source byte from destination byte SUBX.A SUBX SUBX.B src,dst src,dst or SUBX.W src,dst src,dst (.not. src) + 1 + dst → dst or dst − src → dst The source operand is subtracted from the destination operand. This is made by adding the 1’s complement of the source + 1 to the destination. The source operand is not affected. The result is written to the destination operand. Both operands may be located in the full address space. N: Set if result is negative (src > dst), reset if positive (src <= dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive des- tination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. A 20-bit constant 87654h is subtracted from EDE (LSBs) and EDE+2 (MSBs). Example SUBX.A #87654h,EDE ; Subtract 87654h from EDE+2|EDE A table word pointed to by R5 (20-bit address) is subtracted from R7. Jump to label TONI if R7 contains zero after the instruction. R5 is auto-incremented by 2. R7.19:16 = 0 Example SUBX.W JZ ... @R5+,R7 TONI ; Subtract table number from R7. R5 + 2 ; R7 = @R5 (before subtraction) ; R7 <> @R5 (before subtraction) Byte CNT is subtracted from the byte R12 points to in the full address space. Address of CNT is within PC ± 512 K. SUBX.B CNT,0(R12) ; Subtract CNT from @R12 Note: Use SUBA for the following two cases for better density and execution. SUBX.A Rsrc,Rdst or SUBX.A #imm20,Rdst 4-148 16-Bit MSP430X CPU SUBCX.A SUBCX[.W] SUBCX.B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Subtract source address-word with carry from destination address-word Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBCX.A src,dst SUBCX src,dst or SUBCX.W src,dst SUBCX.B src,dst (.not. src) + C + dst → dst or dst − (src − 1) + C → dst The source operand is subtracted from the destination operand. This is made by adding the 1’s complement of the source + carry to the destination. The source operand is not affected, the result is written to the destination operand. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive des- tination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. A 20-bit constant 87654h is subtracted from R5 with the carry from the previous instruction. SUBCX.A #87654h,R5 ; Subtract 87654h + C from R5 A 48-bit number (3 words) pointed to by R5 (20-bit address) is subtracted from a 48-bit counter in RAM, pointed to by R7. R5 auto-increments to point to the next 48-bit number. SUBX.W @R5+,0(R7) SUBCX.W @R5+,2(R7) SUBCX.W @R5+,4(R7) ; Subtract LSBs. R5 + 2 ; Subtract MIDs with C. R5 + 2 ; Subtract MSBs with C. R5 + 2 Byte CNT is subtracted from the byte, R12 points to. The carry of the previous instruction is used. 20-bit addresses. SUBCX.B &CNT,0(R12) ; Subtract byte CNT from @R12 16-Bit MSP430X CPU 4-149 Extended Instructions SWPBX.A SWPBX[.W] Syntax Operation Description Status Bits Mode Bits Example Swap bytes of lower word Swap bytes of word SWPBX.A dst SWPBX.W dst or SWPBX dst dst.15:8 à dst.7:0 Register Mode: Rn.15:8 are swapped with Rn.7:0. When the .A extension is used, Rn.19:16 are unchanged. When the .W extension is used, Rn.19:16 are cleared. Other Modes: When the .A extension is used, bits 31:20 of the destination address are cleared, bits 19:16 are left unchanged, and bits 15:8 are swapped with bits 7:0. When the .W extension is used, bits 15:8 are swapped with bits 7:0 of the addressed word. Not affected OSCOFF, CPUOFF, and GIE are not affected. Exchange the bytes of RAM address-word EDE. Example MOVX.A SWPBX.A #23456h,&EDE EDE Exchange the bytes of R5. ; 23456h −> EDE ; 25634h −> EDE MOVA SWPBX.W #23456h,R5 R5 ; 23456h −> R5 ; 05634h −> R5 Figure 4−55. Swap Bytes SWPBX.A Register Mode Before SWPBX.A 19 16 15 87 0 X High Byte Low Byte After SWPBX.A 19 16 15 87 0 X Low Byte High Byte 4-150 16-Bit MSP430X CPU Figure 4−56. Swap Bytes SWPBX.A In Memory Before SWPBX.A 31 20 19 16 15 X X After SWPBX.A 31 20 19 16 15 0 X High Byte Low Byte Extended Instructions 87 87 0 Low Byte 0 High Byte Figure 4−57. Swap Bytes SWPBX[.W] Register Mode Before SWPBX 19 16 15 87 0 X High Byte Low Byte After SWPBX 19 16 15 87 0 0 Low Byte High Byte Figure 4−58. Swap Bytes SWPBX[.W] In Memory Before SWPBX 15 87 0 High Byte Low Byte After SWPBX 15 87 0 Low Byte High Byte 16-Bit MSP430X CPU 4-151 Extended Instructions SXTX.A SXTX[.W] Syntax Operation Description Status Bits Mode Bits Example Extend sign of lower byte to address-word Extend sign of lower byte to word SXTX.A dst SXTX.W dst or SXTX dst dst.7 → dst.15:8, Rdst.7 → Rdst.19:8 (Register Mode) Register Mode: The sign of the low byte of the operand (Rdst.7) is extended into the bits Rdst.19:8. Other Modes: SXTX.A: the sign of the low byte of the operand (dst.7) is extended into dst.19:8. The bits dst.31:20 are cleared. SXTX[.W]: the sign of the low byte of the operand (dst.7) is extended into dst.15:8. N: Set if result is negative, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (C = .not.Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 8-bit data in EDE.7:0 is sign extended to 20 bits: EDE.19:8. Bits 31:20 located in EDE+2 are cleared. SXTX.A &EDE Figure 4−59. Sign Extend SXTX.A ; Sign extended EDE −> EDE+2/EDE SXTX.A Rdst SXTX.A dst 31 0 ...... 19 16 15 20 19 0 16 15 876 0 S 876 0 S 4-152 16-Bit MSP430X CPU Figure 4−60. Sign Extend SXTX[.W] SXTX[.W] Rdst 19 16 15 SXTX[.W] dst 15 Extended Instructions 876 0 S 876 0 S 16-Bit MSP430X CPU 4-153 Extended Instructions * TSTX.A * TSTX[.W] * TSTX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Test destination address-word Test destination word Test destination byte TSTX.A TSTX TST.B dst dst or TST.W dst dst dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 CMPX.A CMPX CMPX.B #0,dst #0,dst #0,dst The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. RAM byte LEO is tested; PC is pointing to upper memory. If it is negative, continue at LEONEG; if it is positive but not zero, continue at LEOPOS. LEOPOS LEONEG LEOZERO TSTX.B JN JZ ...... ...... ...... LEO LEONEG LEOZERO ; Test LEO ; LEO is negative ; LEO is zero ; LEO is positive but not zero ; LEO is negative ; LEO is zero 4-154 16-Bit MSP430X CPU XORX.A XORX[.W] XORX.B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Exclusive OR source address-word with destination address-word Exclusive OR source word with destination word Exclusive OR source byte with destination byte XORX.A XORX XORX.B src,dst src,dst or XORX.W src,dst src,dst src .xor. dst → dst The source and destination operands are exclusively ORed. The result is placed into the destination. The source operand is not affected. The previous contents of the destination are lost. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (carry = .not. Zero) V: Set if both operands are negative (before execution), reset otherwise. OSCOFF, CPUOFF, and GIE are not affected. Toggle bits in address-word CNTR (20-bit data) with information in address-word TONI (20-bit address). XORX.A TONI,&CNTR ; Toggle bits in CNTR A table word pointed to by R5 (20-bit address) is used to toggle bits in R6. XORX.W @R5,R6 ; Toggle bits in R6. R6.19:16 = 0 Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE (20-bit address). XORX.B INV.B EDE,R7 R7 ; Set different bits to 1 in R7 ; Invert low byte of R7. R7.19:8 = 0. 16-Bit MSP430X CPU 4-155 Address Instructions 4.6.4 Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode, except for the MOVA instruction. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time. The MSP430X address instructions are listed and described in the following pages. 4-156 16-Bit MSP430X CPU ADDA Syntax Operation Description Status Bits Mode Bits Example Address Instructions Add 20-bit source to a 20-bit destination register ADDA ADDA Rsrc,Rdst #imm20,Rdst src + Rdst → Rdst The 20-bit source operand is added to the 20-bit destination CPU register. The previous contents of the destination are lost. The source operand is not affected. N: Set if result is negative (Rdst.19 = 1), reset if positive (Rdst.19 = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the 20-bit result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise. OSCOFF, CPUOFF, and GIE are not affected. R5 is increased by 0A4320h. The jump to TONI is performed if a carry occurs. ADDA JC ... #0A4320h,R5 TONI ; Add A4320h to 20-bit R5 ; Jump on carry ; No carry occurred 16-Bit MSP430X CPU 4-157 Address Instructions * BRA Syntax Operation Emulation Description Status Bits Mode Bits Examples Branch to destination BRA dst dst → PC MOVA dst,PC An unconditional branch is taken to a 20-bit address anywhere in the full address space. All seven source addressing modes can be used. The branch instruction is an address-word instruction. If the destination address is contained in a memory location X, it is contained in two ascending words: X (LSBs) and (X + 2) (MSBs). N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Examples for all addressing modes are given. Immediate Mode: Branch to label EDE located anywhere in the 20-bit address space or branch directly to address. BRA BRA #EDE #01AA04h ; MOVA #imm20,PC Symbolic Mode: Branch to the 20-bit address contained in addresses EXEC (LSBs) and EXEC+2 (MSBs). EXEC is located at the address (PC + X) where X is within ±32 K. Indirect addressing. BRA EXEC ; MOVA z16(PC),PC Note: if the 16-bit index is not sufficient, a 20-bit index may be used with the following instruction. MOVX.A EXEC,PC ; 1M byte range with 20-bit index Absolute Mode: Branch to the 20-bit address contained in absolute addresses EXEC (LSBs) and EXEC+2 (MSBs). Indirect addressing. BRA &EXEC ; MOVA &abs20,PC Register Mode: Branch to the 20-bit address contained in register R5. Indirect R5. BRA R5 ; MOVA R5,PC 4-158 16-Bit MSP430X CPU Address Instructions Indirect Mode: Branch to the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. BRA @R5 ; MOVA @R5,PC Indirect, Auto-Increment Mode: Branch to the 20-bit address contained in the words pointed to by register R5 and increment the address in R5 afterwards by 4. The next time the S/W flow uses R5 as a pointer, it can alter the program execution due to access to the next address in the table pointed to by R5. Indirect, indirect R5. BRA @R5+ ; MOVA @R5+,PC. R5 + 4 Indexed Mode: Branch to the 20-bit address contained in the address pointed to by register (R5 + X) (e.g. a table with addresses starting at X). (R5 + X) points to the LSBs, (R5 + X + 2) points to the MSBs of the address. X is within R5 ± 32 K. Indirect, indirect (R5 + X). BRA X(R5) ; MOVA z16(R5),PC Note: if the 16-bit index is not sufficient, a 20-bit index X may be used with the following instruction: MOVX.A X(R5),PC ; 1M byte range with 20-bit index 16-Bit MSP430X CPU 4-159 Address Instructions CALLA Syntax Operation Description Status Bits Mode Bits Examples Call a Subroutine CALLA dst dst SP − 2 PC.19:16 SP − 2 PC.15:0 tmp → tmp 20-bit dst is evaluated and stored → SP → @SP updated PC with return address to TOS (MSBs) → SP → @SP updated PC to TOS (LSBs) → PC saved 20-bit dst to PC A subroutine call is made to a 20-bit address anywhere in the full address space. All seven source addressing modes can be used. The call instruction is an address-word instruction. If the destination address is contained in a memory location X, it is contained in two ascending words: X (LSBs) and (X + 2) (MSBs). Two words on the stack are needed for the return address. The return is made with the instruction RETA. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Examples for all addressing modes are given. Immediate Mode: Call a subroutine at label EXEC or call directly an address. CALLA CALLA #EXEC #01AA04h ; Start address EXEC ; Start address 01AA04h Symbolic Mode: Call a subroutine at the 20-bit address contained in addresses EXEC (LSBs) and EXEC+2 (MSBs). EXEC is located at the address (PC + X) where X is within ±32 K. Indirect addressing. CALLA EXEC ; Start address at @EXEC. z16(PC) Absolute Mode: Call a subroutine at the 20-bit address contained in absolute addresses EXEC (LSBs) and EXEC+2 (MSBs). Indirect addressing. CALLA &EXEC ; Start address at @EXEC Register Mode: Call a subroutine at the 20-bit address contained in register R5. Indirect R5. CALLA R5 ; Start address at @R5 4-160 16-Bit MSP430X CPU Address Instructions Indirect Mode: Call a subroutine at the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. CALLA @R5 ; Start address at @R5 Indirect, Auto-Increment Mode: Call a subroutine at the 20-bit address contained in the words pointed to by register R5 and increment the 20-bit address in R5 afterwards by 4. The next time the S/W flow uses R5 as a pointer, it can alter the program execution due to access to the next word address in the table pointed to by R5. Indirect, indirect R5. CALLA @R5+ ; Start address at @R5. R5 + 4 Indexed Mode: Call a subroutine at the 20-bit address contained in the address pointed to by register (R5 + X) e.g. a table with addresses starting at X. (R5 + X) points to the LSBs, (R5 + X + 2) points to the MSBs of the word address. X is within R5 ±32 K. Indirect, indirect (R5 + X). CALLA X(R5) ; Start address at @(R5+X). z16(R5) 16-Bit MSP430X CPU 4-161 Address Instructions * CLRA Syntax Operation Emulation Description Status Bits Example Clear 20-bit destination register CLRA Rdst 0 −> Rdst MOVA #0,Rdst The destination register is cleared. Status bits are not affected. The 20-bit value in R10 is cleared. CLRA R10 ; 0 −> R10 4-162 16-Bit MSP430X CPU CMPA Syntax Operation Description Status Bits Mode Bits Example Example Address Instructions Compare the 20-bit source with a 20-bit destination register CMPA CMPA Rsrc,Rdst #imm20,Rdst (.not. src) + 1 + Rdst or Rdst − src The 20-bit source operand is subtracted from the 20-bit destination CPU register. This is made by adding the 1’s complement of the source + 1 to the destination register. The result affects only the status bits. N: Set if result is negative (src > dst), reset if positive (src <= dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. A 20-bit immediate operand and R6 are compared. If they are equal the program continues at label EQUAL. CMPA JEQ ... #12345h,R6 EQUAL ; Compare R6 with 12345h ; R5 = 12345h ; Not equal The 20-bit values in R5 and R6 are compared. If R5 is greater than (signed) or equal to R6, the program continues at label GRE. CMPA JGE ... R6,R5 GRE ; Compare R6 with R5 (R5 − R6) ; R5 >= R6 ; R5 < R6 16-Bit MSP430X CPU 4-163 Address Instructions * DECDA Syntax Operation Emulation Description Status Bits Mode Bits Example Double-decrement 20-bit destination register DECDA Rdst Rdst − 2 −> Rdst SUBA #2,Rdst The destination register is decremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if Rdst contained 2, reset otherwise C: Reset if Rdst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is decremented by 2 DECDA R5 ; Decrement R5 by two 4-164 16-Bit MSP430X CPU * INCDA Syntax Operation Emulation Example Status Bits Mode Bits Example Address Instructions Double-increment 20-bit destination register INCDA Rdst dst + 2 −> dst ADDA #2,Rdst The destination register is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if Rdst contained 0FFFFEh, reset otherwise Set if Rdst contained 0FFFEh, reset otherwise Set if Rdst contained 0FEh, reset otherwise C: Set if Rdst contained 0FFFFEh or 0FFFFFh, reset otherwise Set if Rdst contained 0FFFEh or 0FFFFh, reset otherwise Set if Rdst contained 0FEh or 0FFh, reset otherwise V: Set if Rdst contained 07FFFEh or 07FFFFh, reset otherwise Set if Rdst contained 07FFEh or 07FFFh, reset otherwise Set if Rdst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is incremented by 2 INCDA R5 ; Increment R5 by two 16-Bit MSP430X CPU 4-165 Address Instructions MOVA Syntax Operation Description Status Bits Mode Bits Examples Move the 20-bit source to the 20-bit destination MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA Rsrc,Rdst #imm20,Rdst z16(Rsrc),Rdst EDE,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,z16(Rdst) Rsrc,&abs20 src → Rdst Rsrc → dst The 20-bit source operand is moved to the 20-bit destination. The source operand is not affected. The previous content of the destination is lost. Not affected OSCOFF, CPUOFF, and GIE are not affected. Copy 20-bit value in R9 to R8. MOVA R9,R8 ; R9 -> R8 Write 20-bit immediate value 12345h to R12. MOVA #12345h,R12 ; 12345h -> R12 Copy 20-bit value addressed by (R9 + 100h) to R8. Source operand in addresses (R9 + 100h) LSBs and (R9 + 102h) MSBs MOVA 100h(R9),R8 ; Index: ± 32 K. 2 words transferred Move 20-bit value in 20-bit absolute addresses EDE (LSBs) and EDE+2 (MSBs) to R12. MOVA &EDE,R12 ; &EDE -> R12. 2 words transferred Move 20-bit value in 20-bit addresses EDE (LSBs) and EDE+2 (MSBs) to R12. PC index ±32 K. MOVA EDE,R12 ; EDE -> R12. 2 words transferred Copy 20-bit value R9 points to (20 bit address) to R8. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9,R8 ; @R9 -> R8. 2 words transferred 4-166 16-Bit MSP430X CPU Address Instructions Copy 20-bit value R9 points to (20 bit address) to R8. R9 is incremented by four afterwards. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9+,R8 ; @R9 -> R8. R9 + 4. 2 words transferred. Copy 20-bit value in R8 to destination addressed by (R9 + 100h). Destination operand in addresses @(R9 + 100h) LSBs and @(R9 + 102h) MSBs. MOVA R8,100h(R9) ; Index: +- 32 K. 2 words transferred Move 20-bit value in R13 to 20-bit absolute addresses EDE (LSBs) and EDE+2 (MSBs). MOVA R13,&EDE ; R13 -> EDE. 2 words transferred Move 20-bit value in R13 to 20-bit addresses EDE (LSBs) and EDE+2 (MSBs). PC index ±32 K. MOVA R13,EDE ; R13 -> EDE. 2 words transferred 16-Bit MSP430X CPU 4-167 Address Instructions * RETA Syntax Operation Emulation Description Status Bits Mode Bits Example Return from subroutine RETA @SP → PC.15:0 SP + 2 → SP @SP → PC.19:16 SP + 2 → SP LSBs (15:0) of saved PC to PC.15:0 MSBs (19:16) of saved PC to PC.19:16 MOVA @SP+,PC The 20-bit return address information, pushed onto the stack by a CALLA instruction, is restored to the program counter PC. The program continues at the address following the subroutine call. The status register bits SR.11:0 are not affected. This allows the transfer of information with these bits. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Call a subroutine SUBR from anywhere in the 20-bit address space and return to the address after the CALLA. CALLA #SUBR ... SUBR PUSHM.A #2,R14 ... POPM.A #2,R14 RETA ; Call subroutine starting at SUBR ; Return by RETA to here ; Save R14 and R13 (20 bit data) ; Subroutine code ; Restore R13 and R14 (20 bit data) ; Return (to full address space) 4-168 16-Bit MSP430X CPU * TSTA Syntax Operation Emulation Description Status Bits Mode Bits Example Address Instructions Test 20-bit destination register TSTA Rdst dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 CMPA #0,Rdst The destination register is compared with zero. The status bits are set according to the result. The destination register is not affected. N: Set if destination register is negative, reset if positive Z: Set if destination register contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TSTA JN JZ ...... ...... ...... R7 R7NEG R7ZERO ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero 16-Bit MSP430X CPU 4-169 Address Instructions SUBA Syntax Operation Description Status Bits Mode Bits Example Subtract 20-bit source from 20-bit destination register SUBA SUBA Rsrc,Rdst #imm20,Rdst (.not.src) + 1 + Rdst → Rdst or Rdst − src → Rdst The 20-bit source operand is subtracted from the 20-bit destination register. This is made by adding the 1’s complement of the source + 1 to the destination. The result is written to the destination register, the source is not affected. N: Set if result is negative (src > dst), reset if positive (src <= dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB (Rdst.19), reset otherwise V: Set if the subtraction of a negative source operand from a positive des- tination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is subtracted from R6. If a carry occurs, the program continues at label TONI. SUBA JC ... R5,R6 TONI ; R6 − R5 -> R6 ; Carry occurred ; No carry 4-170 16-Bit MSP430X CPU Chapter 5 FLL+ Clock Module The FLL+ clock module provides the clocks for MSP430x4xx devices. This chapter discusses the FLL+ clock module. The FLL+ clock module is implemented in all MSP430x4xx devices. Topic Page 5.1 FLL+ Clock Module Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 FLL+ Clock Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 FLL+ Clock Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 FLL+ Clock Module 5-1 5.1 FLL+ Clock Module Introduction The frequency-locked loop (FLL+) clock module supports low system cost and ultra low-power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The FLL+ features digital frequency-locked loop (FLL) hardware. The FLL operates together with a digital modulator and stabilizes the internal digitally controlled oscillator (DCO) frequency to a programmable multiple of the LFXT1 watch crystal frequency. The FLL+ clock module can be configured to operate without any external components, with one or two external crystals, or with resonators, under full software control. The FLL+ clock module includes two or three clock sources: - LFXT1CLK: Low-frequency/high-frequency oscillator that can be used either with low-frequency 32768-Hz watch crystals or standard crystals or resonators in the 450-kHz to 8-MHz range. See the device-specific data sheet for details. - XT2CLK: Optional high-frequency oscillator that can be used with standard crystals, resonators, or external clock sources in the 450-kHz to 8-MHz range. In MSP430F47x3/4 and MSP430F471xx devices the upper limit is 16 MHz. See the device-specific data sheet for details. - DCOCLK: Internal digitally controlled oscillator (DCO) with RC-type characteristics, stabilized by the FLL. - VLOCLK: Internal very low power, low frequency oscillator with 12-kHz typical frequency. Four clock signals are available from the FLL+ module: - ACLK: Auxiliary clock. The ACLK is software selectable as LFXT1CLK or VLOCLK as clock source. ACLK is software selectable for individual peripheral modules. - ACLK/n: Buffered output of the ACLK. The ACLK/n is ACLK divided by 1,2,4, or 8 and used externally only. - MCLK: Master clock. MCLK is software selectable as LFXT1CLK, VLOCLK, XT2CLK (if available), or DCOCLK. MCLK can be divided by 1, 2, 4, or 8 within the FLL block. MCLK is used by the CPU and system. - SMCLK: Sub-main clock. SMCLK is software selectable as XT2CLK (if available) or DCOCLK. SMCLK is software selectable for individual peripheral modules. 5-2 FLL+ Clock Module The block diagrams of the FLL+ clock module are shown in Figure 5−1 to Figure 5−4. - Figure 5−1 shows the block diagram for MSP430x43x, MSP430x44x, MSP430FG47x, MSP430F47x, and MSP430x461x devices. - Figure 5−2 shows the block diagram for MSP430x42x and MSP430x41x devices. - Figure 5−3 shows the block diagram for MSP430x47x3/4 and MSP430F471xx devices. - Figure 5−4 shows the block diagram for MSP430x41x2 devices. FLL+ Clock Module 5-3 Figure 5−1. MSP430x43x, MSP430x44x, MSP430FG47x, MSP430F47x, and MSP430x461x Frequency-Locked Loop FLL_DIVx OSCOFF XTS_FLL fCrystal Divider /1/2/4/8 ACLK/n ACLK XIN XOUT 0V LF XT LFOff 0V XT1Off LFXT1 Oscillator XCAPxPF /(N+1) SCG1 FNx 4 off DC Generator FLLDx Divider /1/2/4/8 XT2IN XT20FF SCG0 PUC Enable Reset + 10−bit Frequency Integrator − 10 M SELMx CPUOFF 00 0011 0 1100 1111 1 MCLK DCO + Modulator fDCO fDCO/D fDCOCLK DCOPLUS SELS 1 SMCLKOFF 0 0 0 1 1 SMCLK XT2OUT XT2 Oscillator 5-4 FLL+ Clock Module Figure 5−2. MSP430x42x and MSP430x41x Frequency-Locked Loop FLL_DIVx OSCOFF XTS_FLL fCrystal Divider /1/2/4/8 ACLK/n ACLK XIN XOUT 0V LF XT LFOff 0V XT1Off LFXT1 Oscillator XCAPxPF /(N+1) SCG1 FNx 4 off DC Generator FLLDx Divider /1/2/4/8 SCG0 PUC Enable Reset + 10−bit Frequency Integrator − 10 M CPUOFF 0 1 MCLK to CPU DCO + Modulator fDCO fDCO/D MCLK to Peripherals DCOPLUS fDCOCLK 1 0 SMCLK FLL+ Clock Module 5-5 Figure 5−3. MSP430x47x3/4 and MSP430F471xx Frequency-Locked Loop FLL_DIVx OSCOFF XTS_FLL fCrystal Divider /1/2/4/8 ACLK/n ACLK XIN XOUT 0V LF XT LFOff 0V XT1Off LFXT1 Oscillator XCAPxPF /(N+1) SCG1 FNx 4 off DC Generator FLLDx Divider /1/2/4/8 XT2IN XT20FF XT2Sx SCG0 PUC Enable Reset + 10−bit Frequency Integrator − 10 M SELMx CPUOFF 00 0011 0 1100 1111 1 MCLK DCO + Modulator fDCO fDCO/D fDCOCLK DCOPLUS SELS 1 SMCLKOFF 0 0 0 1 1 SMCLK XT2OUT XT2 Oscillator (supporting upto 16MHz) 5-6 FLL+ Clock Module Figure 5--4. MSP430x41x2 Frequency-Locked Loop Internal VLOCLK LP/LF Oscillator 10 LFXT1CLK else OSCOFF XTS_FLL LFXT1Sx FLL_DIVx Divider /1/2/4/8 ACLK/n ACLK XIN 0V LF XT XOUT 0V XT1Off LFXT1 Oscillator XCAPxPF /(N+1) SCG0 PUC Enable Reset + 10-bit Frequency Integrator - SCG1 FNx 4 off DC Generator Divider /1/2/4/8 10 DCO + Modulator fDCO fDCO/D DCOPLUS 0 1 SELM 00 CPUOFF 01 0 10 1 MCLK 11 SMCLKOFF 0 SMCLK 1 FLL+ Clock Module 5-7 FLL+ Clock Module Operation 5.2 FLL+ Clock Module Operation After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times the ACLK frequency. When a 32 768-Hz crystal is used for ACLK, MCLK and SMCLK stabilize to 1.048576 MHz. Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure the MSP430 operating modes and enable or disable components of the FLL+ clock module. See Chapter System Resets, Interrupts and Operating Modes. The SCFQCTL, SCFI0, SCFI1, FLL_CTL0, and FLL_CTL1 registers configure the FLL+ clock module. The FLL+ can be configured or reconfigured by software at any time during program execution. Example, MCLK = 64 × ACLK = 2097152 BIC #GIE,SR MOV.B #(64−1),&SCFQCTL MOV.B #FN_2,&SCFI0 BIS #GIE,SR ; Disable interrupts ; MCLK = 64 * ACLK, DCOPLUS=0 ; Select DCO range ; Enable interrupts 5.2.1 FLL+ Clock features for Low-Power Applications Conflicting requirements typically exist in battery-powered MSP430x4xx applications: - Low clock frequency for energy conservation and time keeping - High clock frequency for fast reaction to events and fast burst processing capability - Clock stability over operating temperature and supply voltage The FLL+ clock module addresses the above conflicting requirements by allowing the user to select from the three available clock signals: ACLK, MCLK, and SMCLK. For optimal low-power performance, the ACLK can be configured to oscillate with a low-power 32 786-Hz watch-crystal, providing a stable time base for the system and low-power standby operation. The MCLK can be configured to operate from the on-chip DCO, stabilized by the FLL, and can activate when requested by interrupt events. The digital frequency-locked loop provides decreased start-time and stabilization delay over an analog phase-locked loop. A phase-locked loop takes hundreds or thousands of clock cycles to start and stabilize. The FLL starts immediately at its previous setting. 5-8 FLL+ Clock Module FLL+ Clock Module Operation 5.2.2 Internal Very Low-Power, Low-Frequency Oscillator The internal very low-power, low-frequency oscillator (VLO) provides a typical frequency of 12kHz (see device-specific data sheet for parameters) without requiring a crystal. VLOCLK source is selected by setting LFXT1Sx = 10 when XTS_FLL = 0. The OSCOFF bit disables the VLO for LPM4. The LFXT1 crystal oscillators are disabled when the VLO is selected reducing current consumption. The VLO consumes no power when not being used. 5.2.3 LFXT1 Oscillator The LFXT1 oscillator supports ultralow-current consumption using a 32,768-Hz watch crystal in LF mode (XTS_FLL = 0). A watch crystal connects to XIN and XOUT without any external components. The LFXT1 oscillator supports high-speed crystals or resonators when in HF mode (XTS_FLL = 1). The high-speed crystal or resonator connects to XIN and XOUT. LFXT1 may be used with an external clock signal on the XIN pin when XTS_FLL = 1. The input frequency range is ~1 Hz to 8 MHz. When the input frequency is below 450 kHz, the XT1OF bit may be set to prevent the CPU from being clocked from the external frequency. The software-selectable XCAPxPF bits configure the internally provided load capacitance for the LFXT1 crystal. The internal pin capacitance plus the parasitic 2-pF pin capacitance combine serially to form the load capacitance. The load capacitance can be selected as 1, 6, 8, or 10 pF. Additional external capacitors can be added if necessary. Software can disable LFXT1 by setting OSCOFF if this signal does not source MCLK (SELM ≠ 3 or CPUOFF = 1 ). Note: LFXT1 Oscillator Characteristics Low-frequency crystals often require hundreds of milliseconds to start up, depending on the crystal. Ultralow-power oscillators such as the LFXT1 in LF mode should be guarded from noise coupling from other sources. The crystal should be placed as close as possible to the MSP430 with the crystal housing grounded and the crystal traces guarded with ground traces. The default value of XCAPxPF is 0, providing a crystal load capacitance of ~1 pF. Reliable crystal operation may not be achieved unless the crystal is provided with the proper load capacitance, either by selection of XCAPxPF values or by external capacitors. FLL+ Clock Module 5-9 FLL+ Clock Module Operation 5.2.4 XT2 Oscillator Some devices have a second crystal oscillator, XT2. XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode, except XT2 does not have internal load capacitors. The required load capacitance for the high-frequency crystal or resonator must be provided externally. The XT2OFF bit disables the XT2 oscillator if XT2CLK is unused for MCLK (SELMx ≠ 2 or CPUOFF = 1) and SMCLK (SELS = 0 or SMCLKOFF = 1). XT2 may be used with external clock signals on the XT2IN pin. When used with an external signal, the external frequency must meet the data sheet parameters for XT2. If there is only one crystal in the system it should be connected to LFXT1. Using only XT2 causes the LFOF fault flag to remain set, not allowing for the OFIFG to ever be cleared. XT2 Oscillator in MSP430x47x3/4 and MSP430F471xx Devices The MSP430x47x3/4 and MSP430F471xx devices have a second crystal oscillator (XT2) that supports crystals up to 16 MHz. XT2 sources XT2CLK. The XT2Sx bits select the range of operation of XT2. The XT2OFF bit disables the XT2 oscillator, if XT2CLK is not used for MCLK or SMCLK as described above. XT2 may be used with external clock signals on the XT2IN pin when XT2Sx = 11. When used with an external signal, the external frequency must meet the data sheet parameters for XT2. When the input frequency is below the specified lower limit, the XT2OF bit may be set to prevent the CPU from being clocked with XT2CLK. If there is only one crystal with a frequency below 8 MHz in the system, it should be connected to LFXT1. Using only XT2 causes the LFOF fault flag to remain set, not allowing for the OFIFG to ever be cleared. 5-10 FLL+ Clock Module FLL+ Clock Module Operation 5.2.5 Digitally Controlled Oscillator (DCO) The DCO is an integrated ring oscillator with RC-type characteristics. The DCO frequency is stabilized by the FLL to a multiple of ACLK as defined by N, the lowest 7 bits of the SCFQCTL register. The DCOPLUS bit sets the fDCOCLK frequency to fDCO or fDCO/D. The FLLDx bits configure the divider, D, to 1, 2, 4, or 8. By default, DCOPLUS = 0 and D = 2, providing a clock frequency of fDCO/2 on fDCOCLK. The multiplier (N+1) and D set the frequency of DCOCLK. DCOPLUS = 0: fDCOCLK = (N + 1) x fACLK DCOPLUS = 1: fDCOCLK = D x (N + 1) x fACLK DCO Frequency Range The frequency range of fDCO is selected with the FNx bits as listed in Table 5−1. The range control allows the DCO to operate near the center of the available taps for a given DCOCLK frequency. The user must ensure that MCLK does not exceed the maximum operating frequency. See the device-specific data sheet for parameters. Table 5−1. DCO Range Control Bits FN_8 FN_4 FN_3 0 0 0 0 0 0 0 0 1 0 1 X 1 X X FN_2 0 1 X X X Typical fDCO Range 0.65 to 6.1 1.3 to 12.1 2 to 17.9 2.8 to 26.6 4.2 to 46 5.2.6 Frequency Locked Loop (FLL) The FLL continuously counts up or down a 10-bit frequency integrator. The output of the frequency integrator that drives the DCO can be read in SCFI1 and SCFI0. The count is adjusted +1 or −1 with each ACLK crystal period. Five of the integrator bits, SCFI1 bits 7−3, set the DCO frequency tap. Twenty-nine taps are implemented for the DCO (28, 29, 30, and 31 are equivalent), and each is approximately 10% higher than the previous. The modulator mixes two adjacent DCO frequencies to produce fractional taps. SCFI1 bits 2−0 and SCFI0 bits 1−0 are used for the modulator. The DCO starts at the lowest tap after a PUC or when SCFI0 and SCFI1 are cleared. Time must be allowed for the DCO to settle on the proper tap for normal operation. 32 ACLK cycles are required between taps requiring a worst case of 28 x 32 ACLK cycles for the DCO to settle. FLL+ Clock Module 5-11 FLL+ Clock Module Operation 5.2.7 DCO Modulator The modulator mixes two adjacent DCO frequencies to produce an intermediate effective frequency and spread the clock energy, reducing electromagnetic interference (EMI). The modulator mixes the two adjacent frequencies across 32 DCOCLK clock cycles. The error of the effective frequency is zero every 32 DCOCLK cycles and does not accumulate. The modulator settings and DCO control are automatically controlled by the FLL hardware. Figure 5−5 illustrates the modulator operation. Figure 5−5. Modulator Patterns NDCOmod 31 24 16 15 5 4 3 2 Lower DCO Tap Frequency fDCO 1 0 Upper DCO Tap Frequency fDCO+1 f(DCOCLK) Cycles, Shown for f(DCOCLK)=f(ACLK) × 32 One ACLK Cycle 5-12 FLL+ Clock Module FLL Operation from Low-Power Modes 5.2.8 Disabling the FLL Hardware and Modulator The FLL is disabled when the status register bit SCG0 = 1. When the FLL is disabled, the DCO runs at the previously selected tap and DCOCLK is not automatically stabilized. The DCO modulator is disabled when SCFQ_M = 1. When the DCO modulator is disabled, the DCOCLK is adjusted to the nearest of the available DCO taps. 5.2.9 FLL Operation from Low-Power Modes An interrupt service request clears SCG1, CPUOFF, and OSCOFF if set but does not clear SCG0. This means that FLL operation from within an interrupt service routine entered from LPM1, 3, or 4, the FLL remains disabled and the DCO operates at the previous setting as defined in SCFI0 and SCFI1. SCG0 can be cleared by user software if FLL operation is required. 5.2.10 Buffered Clock Output ACLK may be divided by 1, 2, 4, or 8 and buffered out of the device on P1.5. The division rate is selected with the FLL_DIV bits. The ACLK output is multiplexed with other pin functions. When multiplexed, the pin must be configured for the ACLK output. BIS.B #BIT5,&P1SEL BIS.B #BIT5,&P1DIR ; Select ACLK/n signal as ; output for port P1.5 ; Select port P1.5 to ACLK/n ; signal for output FLL+ Clock Module 5-13 Buffered Clock Output 5.2.11 FLL+ Fail-Safe Operation The FLL+ module incorporates an oscillator-fault fail-safe feature. This feature detects an oscillator fault for LFXT1, DCO and XT2 as shown in Figure 5−6. The available fault conditions are: - Low-frequency oscillator fault (LFOF) for LFXT1 in LF mode - High-frequency oscillator fault (XT1OF) for LFXT1 in HF mode - High-frequency oscillator fault (XT2OF) for XT2 - DCO fault flag (DCOF) for the DCO The crystal oscillator fault bits LFOF, XT1OF and XT2OF are set if the corresponding crystal oscillator is turned on and not operating properly. The fault bits remain set as long as the fault condition exists and are automatically cleared if the enabled oscillators function normally. During a LFXT1crystal failure, no ACLK signal is generated and the FLL+ continues to count down to zero in an attempt to lock ACLK and MCLK/(D×[N+1]). The DCO tap moves to the lowest position (SCFI1.7 to SCFI1.3 are cleared) and the DCOF is set. A DCOF is also generated if the N-multiplier value is set too high for the selected DCO frequency range resulting the DCO tap to move to the highest position (SCFI1.7 to SCFI1.3 are set). The DCOF is cleared automatically if the DCO tap is not in the lowest or the highest positions. The OFIFG oscillator-fault interrupt flag is set and latched at POR or when an oscillator fault (LFOF, XT1OF, XT2OF, or DCOF set) is detected. When OFIFG is set, MCLK is sourced from the DCO, and if OFIE is set, the OFIFG requests an NMI interrupt. When the interrupt is granted, the OFIE is reset automatically. The OFIFG flag must be cleared by software. The source of the fault can be identified by checking the individual fault bits. When OFIFG is set and MCLK is automatically switched to the DCO, the SELMx bit settings are not changed. This condition must be handled by user software. Note: DCO Active During Oscillator Fault DCOCLK is active even at the lowest DCO tap. The clock signal is available for the CPU to execute code and service an NMI during an oscillator fault. Figure 5−6. Oscillator Fault Logic Oscillator Fault DCO Fault LF_OscFault XTS_FLL XT1_OscFault XT2_OscFault DCOF LFOF XT1OF XT2OF Set OFIFG Flag 5-14 FLL+ Clock Module 5.3 FLL+ Clock Module Registers The FLL+ registers are listed in Table 5−2. Table 5−2. FLL+ Registers FLL+ Clock Module Registers Register Short Form Register Type Address System clock control SCFQCTL Read/write 052h System clock frequency integrator 0 SCFI0 Read/write 050h System clock frequency integrator 1 SCFI1 Read/write 051h FLL+ control register 0 FLL_CTL0 Read/write 053h FLL+ control register 1 FLL+ control register 2† FLL_CTL1 FLL_CTL2 Read/write Read/write 054h 055h SFR interrupt enable register 1 IE1 Read/write 000h SFR interrupt flag register 1 IFG1 Read/write † MSP430F41x2, MSP430F47x3/4, and MSP430F471xx devices only. 002h Initial State 01Fh with PUC 040h with PUC Reset with PUC 003h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC FLL+ Clock Module 5-15 FLL+ Clock Module Registers SCFQCTL, System Clock Control Register 7 SCFQ_M rw−0 6 rw−0 5 rw−0 4 rw−1 3 N rw−1 2 rw−1 1 rw−1 0 rw−1 SCFQ_M N Bit 7 Bits 6-0 Modulation. This enables or disables modulation. 0 Modulation enabled 1 Modulation disabled Multiplier. These bits set the multiplier value for the DCO. N must be > 0 or unpredictable operation results. When DCOPLUS = 0: fDCOCLK = (N + 1) ⋅ fcrystal When DCOPLUS = 1: fDCOCLK = D x (N + 1) ⋅ fcrystal SCFI0, System Clock Frequency Integrator Register 0 7 6 FLLDx rw−0 rw−1 5 rw−0 4 3 FN_x rw−0 rw−0 2 rw−0 1 0 MODx (LSBs) rw−0 rw−0 FLLDx FN_x MODx Bits FLL+ loop divider. These bits divide fDCOCLK in the FLL+ feedback loop. 7-6 This results in an additional multiplier for the multiplier bits. See also multiplier bits. 00 /1 01 /2 10 /4 11 /8 Bits DCO range control. These bits select the fDCO operating range. 5-2 0000 0.65 to 6.1 MHz 0001 1.3 to 12.1 MHz 001x 2 to 17.9 MHz 01xx 2.8 to 26.6 MHz 1xxx 4.2 to 46 MHz Bits Least significant modulator bits. Bit 0 is the modulator LSB. These bits 1−0 affect the modulator pattern. All MODx bits are modified automatically by the FLL+. 5-16 FLL+ Clock Module SCFI1, System Clock Frequency Integrator Register 1 FLL+ Clock Module Registers 7 rw−0 6 rw−0 5 DCOx rw−0 4 rw−0 3 rw−0 2 rw−0 1 MODx (MSBs) rw−0 0 rw−0 DCOx MODx Bits 7-3 Bit 2 These bits select the DCO tap and are modified automatically by the FLL+. Most significant modulator bits. Bit 2 is the modulator MSB. These bits affect the modulator pattern. All MODx bits are modified automatically by the FLL+. FLL+ Clock Module 5-17 FLL+ Clock Module Registers FLL_CTL0, FLL+ Control Register 0 7 6 5 4 DCOPLUS XTS_FLL XCAPxPF rw−0 rw−0 rw−0 rw−0 † Not present in MSP430x41x, MSP430x42x devices 3 XT2OF† r−0 2 XT1OF r−0 1 LFOF r−(1) 0 DCOF r−1 DCOPLUS Bit 7 XTS_FLL Bit 6 XCAPxPF Bits 5−4 XT2OF Bit 3 XT1OF Bit 2 LFOF Bit 1 DCOF Bit 0 DCO output pre-divider. This bit selects if the DCO output is pre-divided before sourcing MCLK or SMCLK. The division rate is selected with the FLL_D bits 0 DCO output is divided 1 DCO output is not divided LFTX1 mode select 0 Low frequency mode 1 High frequency mode Oscillator capacitor selection. These bits select the effective capacitance seen by the LFXT1 crystal or resonator. Should be set to 00 if the high-frequency mode is selected for LFXT1 with XTS_FLL = 1. 00 ~1 pF 01 ~6 pF 10 ~8 pF 11 ~10 pF XT2 oscillator fault. Not present in MSP430x41x, and MSP430x42x devices. 0 No fault condition present 1 Fault condition present LFXT1 high-frequency oscillator fault 0 No fault condition present 1 Fault condition present LFXT1 low-frequency oscillator fault 0 No fault condition present 1 Fault condition present DCO oscillator fault 0 No fault condition present 1 Fault condition present 5-18 FLL+ Clock Module FLL_CTL1, FLL+ Control Register 1 FLL+ Clock Module Registers 7 LFXT1DIG‡ 6 SMCLK OFF† 5 XT2OFF† 4 3 SELMx† 2 SELS† 1 0 FLL_DIVx rw−0 rw−0 rw−(1) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) † Not present in MSP430x41x, MSP430x42x devices except MSP430F41x2. ‡ Only supported by MSP430xG46x, MSP430FG47x, MSP430F47x, MSP430x47x3/4, and MSP430F471xx devices. Otherwise unused. LFXT1DIG Bit 7 SMCLKOFF Bit 6 XT2OFF Bit 5 SELMx Bits 4−3 SELS Bit 2 FLL_DIVx Bits 1−0 Select digital external clock source. This bit enables the input of an external digital clock signal on XIN in low-frequency mode (XTS_FLL = 0). Only supported in MSP430xG46x, MSP430FG47x, MSP430F47x, MSP430x47x3/4, and MSP430F471xx devices. 0 Crystal input selected 1 Digital clock input selected SMCLK off. This bit turns off SMCLK. Not present in MSP430x41x and MSPx42x devices. 0 SMCLK is on 1 SMCLK is off XT2 off. This bit turns off the XT2 oscillator. Not present in MSP430x41x and MSPx42x devices. 0 XT2 is on 1 XT2 is off if it is not used for MCLK or SMCLK Select MCLK. These bits select the MCLK source. Not present in MSP430x41x and MSP430x42x devices except MSP430F41x2. 00 DCOCLK 01 DCOCLK 10 XT2CLK 11 LFXT1CLK In the MSP430F41x2 devices: 00 DCOCLK 01 DCOCLK 10 LFXT1CLK or VLO 11 LFXT1CLK or VLO Select SMCLK. This bit selects the SMCLK source. Not present in MSP430x41x and MSP430x42x devices. 0 DCOCLK 1 XT2CLK ACLK divider 00 /1 01 /2 10 /4 11 /8 FLL+ Clock Module 5-19 FLL+ Clock Module Registers FLL_CTL2, FLL+ Control Register 2 (MSP430x47x3/4, and MSP430F471xx devices only) 7 6 5 4 3 2 1 0 XT2Sx Reserved rw−0 rw−0 r0 r0 r0 r0 r0 r0 XT2Sx Bits 7-6 Reserved Bits 5-0 XT2 range select. These bits select the frequency range for XT2. 00 0.4 to 1-MHz crystal or resonator 01 1 to 3-MHz crystal or resonator 10 3 to 16-MHz crystal or resonator 11 Digital external 0.4 to 16-MHz clock source Reserved. FLL_CTL2, FLL+ Control Register 2 (MSP430F41x2 devices only) 7 6 5 4 3 2 1 0 Reserved LFXT1Sx Reserved r0 r0 rw−0 rw−0 r0 r0 r0 r0 Reserved Bits 7-6 LFXT1Sx Bits 5−4 Reserved Bits 3-0 Reserved. Low−frequency clock select and LFXT1 range select. These bits select between LFXT1 and VLO when XTS_FLL = 0. When XTS_FLL = 0: 00 32 768-Hz crystal on LFXT1 01 Reserved 10 VLOCLK 11 Digital external clock source When XTS_FLL = 1: 00 Reserved 01 Reserved 10 Reserved 11 Reserved Reserved. 5-20 FLL+ Clock Module IE1, Interrupt Enable Register 1 FLL+ Clock Module Registers 7 6 5 4 3 2 1 0 OFIE rw−0 OFIE Bits 7-2 Bit 1 Bits 0 These bits may be used by other modules. See device-specific data sheet. Oscillator fault interrupt enable. This bit enables the OFIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled This bit may be used by other modules. See device-specific data sheet. FLL+ Clock Module 5-21 FLL+ Clock Module Registers IFG1, Interrupt Flag Register 1 7 6 5 4 3 2 1 0 OFIFG rw−0 OFIFG Bits 7-2 Bit 1 Bits 0 These bits may be used by other modules. See device-specific data sheet. Oscillator fault interrupt flag. Because other bits in IFG1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 No interrupt pending 1 Interrupt pending This bit may be used by other modules. See device-specific data sheet. 5-22 FLL+ Clock Module Chapter 6 Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller. Topic Page 6.1 Flash Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Flash Memory Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3 Flash Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.4 Flash Memory Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Flash Memory Controller 6-1 Flash Memory Introduction 6.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations. The controller has three or four registers (see the device-specific data sheet), a timing generator, and a voltage generator to supply program and erase voltages. MSP430 flash memory features include: - Internal programming voltage generation - Bit, byte, or word programmable - Ultralow-power operation - Segment erase and mass erase - Marginal 0 and marginal 1 read mode (implemented in MSP430FG47x, MSP430F47x, MSP430F47x3/4, and MSP430F471xx devices only (see the device-specific data sheet). The block diagram of the flash memory and controller is shown in Figure 6−1. Note: Minimum VCC During Flash Write or Erase The minimum VCC voltage during a flash write or erase operation is between 2.2 V and 2.7 V (see the device-specific data sheet). If VCC falls below the minimum VCC during a write or erase, the result of the write or erase is unpredictable. 6-2 Flash Memory Controller Figure 6−1. Flash Memory Module Block Diagram Flash Memory Introduction MAB FCTL1 FCTL2 FCTL3 Enable Address Latch Timing Generator Enable Data Latch Programming Voltage Generator † MSP430FG461x devices only MDB Address Latch Data Latch Flash Memory Array 1 Flash Memory Array 2† Flash Memory Controller 6-3 Flash Memory Segmentation 6.2 Flash Memory Segmentation MSP430FG461x devices have two flash memory arrays. Other MSP430x4xx devices have one flash array. All flash memory is partitioned into segments. Single bits, bytes, or words can be written to flash memory, but the segment is the smallest size of flash memory that can be erased. The flash memory is partitioned into main and information memory sections. There is no difference in the operation of the main and information memory sections. Code or data can be located in either section. The differences between the two sections are the segment size and the physical addresses. The information memory has four 64-byte segments on the MSP430FG47x, MSP430F47x, MSP430F47x3/4, and MSP430F471xx devices or two 128-byte segments on all other MSP430x4xx devices. The main memory has two or more 512-byte segments. See the device-specific data sheet for the complete memory map of a device. The segments are further divided into blocks. Figure 6−2 shows the flash segmentation using an example of 4-KB flash that has eight main segments and two information segments. Figure 6−2. Flash Memory Segments, 4-KB Example 4 KB + 256 byte FFFFh 4-kbyte Flash Main Memory F000h 10FFh 1000h 256-byte Flash Information Memory FFFFh FE00h FDFFh FC00h Segment0 Segment1 Segment2 Segment3 Segment4 xxFFh xxC0h xxBFh xx80h xx7Fh xx40h xx3Fh xx00h Block Block Block Block Segment5 Segment6 F000h 10FFh Segment7 SegmentA 1000h SegmentB 6-4 Flash Memory Controller Flash Memory Segmentation 6.2.1 SegmentA on MSP430FG47x, MSP430F47x, MSP430F47x3/4, and MSP430F471xx Devices On MSP430FG47x, MSP430F47x, MSP430F47x3/4, and MSP430F471xx devices, SegmentA of the information memory is locked separately from all other segments with the LOCKA bit. When LOCKA = 1, SegmentA cannot be written or erased and all information memory is protected from erasure during a mass erase or production programming. When LOCKA = 0, SegmentA can be erased and written as any other flash memory segment, and all information memory is erased during a mass erase or production programming. The state of the LOCKA bit is toggled when a 1 is written to it. Writing a 0 to LOCKA has no effect. This allows existing flash programming routines to be used unchanged. ; Unlock SegmentA BIT #LOCKA,&FCTL3 JZ SEGA_UNLOCKED MOV #FWKEY+LOCKA,&FCTL3 SEGA_UNLOCKED ; SegmentA is unlocked ; Test LOCKA ; Already unlocked? ; No, unlock SegmentA ; Yes, continue ; Lock SegmentA BIT #LOCKA,&FCTL3 JNZ SEGALOCKED MOV #FWKEY+LOCKA,&FCTL3 SEGA_LOCKED ; SegmentA is locked ; Test LOCKA ; Already locked? ; No, lock SegmentA ; Yes, continue Flash Memory Controller 6-5 Flash Memory Operation 6.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are off, and the memory operates identically to ROM. MSP430 flash memory is in-system programmable (ISP) without the need for additional external voltage. The CPU can program its own flash memory. The flash memory write/erase modes are selected with the BLKWRT, WRT, GMERAS, MERAS, and ERASE bits and are: - Byte/word write - Block write - Segment erase - Mass erase (all main memory segments) - All erase (all segments) Reading or writing to flash memory while it is being programmed or erased is prohibited. If CPU execution is required during the write or erase, the code to be executed must be in RAM. Any flash update can be initiated from within flash memory or RAM. 6.3.1 Flash Memory Timing Generator Write and erase operations are controlled by the flash timing generator shown in Figure 6−3. The flash timing generator operating frequency, fFTG, must be in the range from ~ 257 kHz to ~ 476 kHz (see device-specific data sheet). Figure 6−3. Flash Memory Timing Generator Block Diagram FSSELx FN5 ........... FN0 ACLK 00 MCLK 01 SMCLK 10 SMCLK 11 Divider, 1−64 f(FTG) PUC EMEX Reset Flash Timing Generator BUSY WAIT The flash timing generator can be sourced from ACLK, SMCLK, or MCLK. The selected clock source should be divided using the FNx bits to meet the frequency requirements for fFTG. If the fFTG frequency deviates from the specification during the write or erase operation, the result of the write or erase may be unpredictable, or the flash memory may be stressed above the limits of reliable operation. 6-6 Flash Memory Controller Flash Memory Operation 6.3.2 Erasing Flash Memory The erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a segment. Erase modes are selected with the GMERAS (MSP430FG461x devices), MERAS, and ERASE bits listed in Table 6−1, Table 6−2, and Table 6−3. Table 6−1. MSP430FG461x Erase Modes GMERAS MERAS X 0 0 1 0 1 1 1 1 1 ERASE Erase Mode 1 Segment erase 0 Mass erase (all main memory segments of selected memory array) 1 Erase all flash memory (main and information segments of selected memory array) 0 Global mass erase (all main memory segments of both memory arrays) 1 Erase main memory and information segments of both memory arrays Table 6−2. MSP430FG47x, MSP430F47x, MSP430F47x3/4, and F471xx Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Mass erase (all main memory segments) 1 1 LOCKA = 0: Erase main and information flash memory. LOCKA = 1: Erase only main flash memory. Table 6−3. Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Mass erase (all main memory segments) 1 1 Erase all flash memory (main and information segments) Any erase is initiated by a dummy write into the address range to be erased. The dummy write starts the flash timing generator and the erase operation. Figure 6−4 shows the erase cycle timing. The BUSY bit is set immediately after the dummy write and remains set throughout the erase cycle. BUSY, GMERAS (when present), MERAS, and ERASE are automatically cleared when the cycle completes. The erase cycle timing is not dependent on the amount of flash memory present on a device. Erase cycle times are device-specific (see the device-specific data sheet). Flash Memory Controller 6-7 Flash Memory Operation Figure 6−4. Erase Cycle Timing Generate Programming Voltage Erase Operation Active Remove Programming Voltage Erase Time, VCC Current Consumption is Increased BUSY tMass Erase, tSeg Erase, or tGlobal Mass Erase (see device-specific data sheet) A dummy write to an address not in the range to be erased does not start the erase cycle, does not affect the flash memory, and is not flagged in any way. This errant dummy write is ignored. 6-8 Flash Memory Controller Flash Memory Operation Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase operation is initiated from within flash memory, all timing is controlled by the flash controller, and the CPU is held while the erase cycle completes. After the erase cycle completes, the CPU resumes code execution with the instruction following the dummy write. When initiating an erase cycle from within flash memory, it is possible to erase the code needed for execution after the erase. If this occurs, CPU execution is unpredictable after the erase cycle. The flow to initiate an erase from flash is shown in Figure 6−5. Figure 6−5. Erase Cycle from Within Flash Memory Disable watchdog Setup flash controller and erase mode Dummy write Set LOCK=1, re-enable watchdog ; Segment Erase from flash. 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2 MOV #FWKEY,&FCTL3 ; Clear LOCK MOV #FWKEY+ERASE,&FCTL1 ; Enable segment erase CLR &0FC10h ; Dummy write, erase S1 MOV #FWKEY+LOCK,&FCTL3 ; Done, set LOCK ... ; Re-enable WDT? Flash Memory Controller 6-9 Flash Memory Operation Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not held and can continue to execute code from RAM. The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again. If a flash access occurs while BUSY = 1, it is an access violation, ACCVIFG is set, and the erase results are unpredictable. The flow to initiate an erase from RAM is shown in Figure 6−6. Figure 6−6. Erase Cycle from Within RAM Disable watchdog yes BUSY = 1 Setup flash controller and erase mode Dummy write yes BUSY = 1 Set LOCK = 1, re-enable watchdog ; Segment Erase from RAM. 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2 MOV #FWKEY,&FCTL3 ; Clear LOCK MOV #FWKEY+ERASE,&FCTL1 ; Enable erase CLR &0FC10h ; Dummy write, erase S1 L2 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L2 ; Loop while busy MOV #FWKEY+LOCK,&FCTL3 ; Done, set LOCK ... ; Re-enable WDT? 6-10 Flash Memory Controller Flash Memory Operation 6.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed in Table 6−4. Table 6−4. Write Modes BLKWRT WRT 0 1 1 1 Write Mode Byte/word write Block write Both write modes use a sequence of individual write instructions, but using the block write mode is approximately twice as fast as byte/word mode, because the voltage generator remains on for the complete block write. Any instruction that modifies a destination can be used to modify a flash location in either byte/word mode or block-write mode. A flash word (low + high byte) must not be written more than twice between erasures. Otherwise, damage can occur. The BUSY bit is set while a write operation is active and cleared when the operation completes. If the write operation is initiated from RAM, the CPU must not access flash while BUSY = 1. Otherwise, an access violation occurs, ACCVIFG is set, and the flash write is unpredictable. Byte/Word Write A byte/word write operation can be initiated from within flash memory or from RAM. When initiating from within flash memory, all timing is controlled by the flash controller, and the CPU is held while the write completes. After the write completes, the CPU resumes code execution with the instruction following the write. The byte/word write timing is shown in Figure 6−7. Figure 6−7. Byte/Word Write Timing ÎÎ ÎÎÎÎ Generate Programming Voltage Programming Operation Active Remove Programming Voltage Programming Time, VCC Current Consumption is Increased BUSY tWord (see device-specific data sheet) When a byte/word write is executed from RAM, the CPU continues to execute code from RAM. The BUSY bit must be zero before the CPU accesses flash again, otherwise an access violation occurs, ACCVIFG is set, and the write result is unpredictable. Flash Memory Controller 6-11 Flash Memory Operation In byte/word mode, the internally generated programming voltage is applied to the complete 64-byte block each time a byte or word is written for tWORD minus threefFTG cycles. With each byte or word write, the amount of time the block is subjected to the programming voltage accumulates. The cumulative programming time, tCPT, must not be exceeded for any block. If the cumulative programming time is met, the block must be erased before performing any further writes to any address within the block. See the device-specific data sheet for specifications. Initiating a Byte/Word Write from Within Flash Memory The flow to initiate a byte/word write from flash is shown in Figure 6−8. Figure 6−8. Initiating a Byte/Word Write from Flash Disable watchdog Setup flash controller and set WRT=1 Write byte or word Set WRT=0, LOCK=1, re-enable watchdog ; Byte/word write from flash. 514 kHz < SMCLK < 952 kHz ; Assumes 0FF1Eh is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2 MOV #FWKEY,&FCTL3 ; Clear LOCK MOV #FWKEY+WRT,&FCTL1 ; Enable write MOV #0123h,&0FF1Eh ; 0123h −> 0FF1Eh MOV #FWKEY,&FCTL1 ; Done. Clear WRT MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT? 6-12 Flash Memory Controller Flash Memory Operation Initiating a Byte/Word Write from RAM The flow to initiate a byte/word write from RAM is shown in Figure 6−9. Figure 6−9. Initiating a Byte/Word Write from RAM Disable watchdog yes BUSY = 1 Setup flash controller and set WRT=1 Write byte or word yes BUSY = 1 Set WRT=0, LOCK = 1 re-enable watchdog ; Byte/word write from RAM. 514 kHz < SMCLK < 952 kHz ; Assumes 0FF1Eh is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2 MOV #FWKEY,&FCTL3 ; Clear LOCK MOV #FWKEY+WRT,&FCTL1 ; Enable write MOV #0123h,&0FF1Eh ; 0123h −> 0FF1Eh L2 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L2 ; Loop while busy MOV #FWKEY,&FCTL1 ; Clear WRT MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT? Flash Memory Controller 6-13 Flash Memory Operation Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 64-byte block. The cumulative programming time tCPT must not be exceeded for any block during a block write. A block write cannot be initiated from within flash memory. The block write must be initiated from RAM only. The BUSY bit remains set throughout the duration of the block write. The WAIT bit must be checked between writing each byte or word in the block. When WAIT is set the next byte or word of the block can be written. When writing successive blocks, the BLKWRT bit must be cleared after the current block is complete. BLKWRT can be set initiating the next block write after the required flash recovery time given by tEnd. BUSY is cleared following each block write completion indicating the next block can be written. Figure 6−10 shows the block write timing; see device-specific data sheet for specifications. Figure 6−10. Block-Write Cycle Timing BLKWRT bit Write to Flash e.g., MOV #123h, &Flash Generate Programming Voltage Programming Operation Active Remove Programming Voltage BUSY Cumulative Programming Time tCPT ∼=< 10ms, VCC Current Consumption is Increased WAIT tBlock, 0 tBlock 1-63 tBlock, 1-63 tBlock,End 6-14 Flash Memory Controller Flash Memory Operation Block Write Flow and Example A block write flow is shown in Figure 6−11 and in the following example. Figure 6−11. Block Write Flow Disable watchdog yes BUSY = 1 Setup flash controller Set BLKWRT=WRT=1 Write byte or word yes WAIT=0? no Block Border? Set BLKWRT=0 yes BUSY = 1 yes Another Block? Set WRT=0, LOCK=1 re-enable WDT Flash Memory Controller 6-15 Flash Memory Operation ; Write one block starting at 0F000h. ; Must be executed from RAM, Assumes Flash is already erased. ; 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #32,R5 ; Use as write counter MOV #0F000h,R6 ; Write pointer MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2 MOV #FWKEY,&FCTL3 ; Clear LOCK MOV #FWKEY+BLKWRT+WRT,&FCTL1 ; Enable block write L2 MOV Write_Value,0(R6) ; Write location L3 BIT #WAIT,&FCTL3 ; Test WAIT JZ L3 ; Loop while WAIT=0 INCD R6 ; Point to next word DEC R5 ; Decrement write counter JNZ L2 ; End of block? MOV #FWKEY,&FCTL1 ; Clear WRT,BLKWRT L4 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L4 ; Loop while busy MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT if needed 6-16 Flash Memory Controller Flash Memory Operation 6.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY = 1, the CPU may not read or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable. Also if a write to flash is attempted with WRT = 0, the ACCVIFG interrupt flag is set, and the flash memory is unaffected. When a byte/word write or any erase operation is initiated from within flash memory, the flash controller returns op-code 03FFFh to the CPU at the next instruction fetch. Op-code 03FFFh is the JMP PC instruction. This causes the CPU to loop until the flash operation is finished. When the operation is finished and BUSY = 0, the flash controller allows the CPU to fetch the proper op-code and program execution resumes. The flash access conditions while BUSY=1 are listed in Table 6−5. Table 6−5. Flash Access While BUSY = 1 Flash Operation Flash WAIT Access Result Read 0 ACCVIFG = 0. 03FFFh is the value read Any erase or Write 0 ACCVIFG = 1. Write is ignored byte/word write Instruction 0 ACCVIFG = 0. CPU fetches 03FFFh. This fetch is the JMP PC instruction. Any 0 ACCVIFG = 1, LOCK = 1 Block write Read Write 1 ACCVIFG = 0, 03FFFh is the value read 1 ACCVIFG = 0, Flash is written Instruction 1 ACCVIFG = 1, LOCK = 1 fetch Interrupts are automatically disabled during any flash operation on F47x3/4 and F471xx devices when EEI = 0 and EEIEX = 0 and on all other devices where EEI and EEIEX are not present. After the flash operation has completed, interrupts are automatically re-enabled. Any interrupt that occurred during the operation will have its associated flag set and will generate an interrupt request when re-enabled. On F47x3/4 and F471xx devices when EEIEX = 1 and GIE = 1, an interrupt will immediately abort any flash operation and the FAIL flag will be set. When EEI = 1, GIE = 1, and EEIEX = 0, a segment erase will be interrupted by a pending interrupt every 32 fFTG cycles. After servicing the interrupt, the segment erase is continued for at least 32 fFTG cycles or until it is complete. During the servicing of the interrupt, the BUSY bit remains set, but the flash memory can be accessed by the CPU without causing an access violation. Nested interrupts are not supported, because the RETI instruction is decoded to detect the return from interrupt. The watchdog timer (in watchdog mode) should be disabled before a flash erase cycle. A reset aborts the erase and the result is unpredictable. After the erase cycle has completed, the watchdog may be re-enabled. Flash Memory Controller 6-17 Flash Memory Operation 6.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller. All flash operations cease, the flash returns to read mode, and all bits in the FCTL1 register are reset. The result of the intended operation is unpredictable. 6.3.6 Marginal Read Mode The marginal read mode can be used to verify the integrity of the flash memory contents. This feature is implemented in MSP430FG47x, MSP430F47x, MSP430F47x3/4, and MSP430F471xx devices; see the device-specific data sheet for availability. During marginal read mode, the presence of an insufficiently programmed flash memory bit location can be detected. Events that could produce this situation include improper fFTG settings, violation of minimum VCC during erase/program operations, and data retention end-of-life. One method for identifying such memory locations would be to periodically perform a checksum calculation over a section of flash memory (for example, a flash segment) and then to repeat this procedure with the marginal read mode enabled. If they do not match, it could indicate an insufficiently programmed flash memory location. It is possible to refresh the affected flash memory segment by disabling marginal read mode, copying to RAM, erasing the flash segment, and copying back from RAM to flash. The program checking the flash memory contents must be executed from RAM. Executing code from flash automatically disables the marginal read mode. The marginal read modes are controlled by the MRG0 and MRG1 bits. Setting MRG1 is used to detect insufficiently programmed flash cells containing a “1“ (erased bits). Setting MRG0 is used to detect insufficiently programmed flash cells containing a “0“ (programmed bits). Only one of these bits should be set at a time. Therefore, a full marginal read check requires two passes of checking the flash memory content’s integrity. During marginal read mode, the flash access speed must be limited to 1 MHz (see device-specific data sheet). 6.3.7 Configuring and Accessing the Flash Memory Controller The FCTLx registers are 16-bit password-protected read/write registers. Any read or write access must use word instructions and write accesses must include the write password 0A5h in the upper byte. Any write to any FCTLx register with any value other than 0A5h in the upper byte is a security key violation, sets the KEYV flag, and triggers a PUC system reset. Any read of any FCTLx registers reads 096h in the upper byte. Any write to FCTL1 during an erase or byte/word write operation is an access violation and sets ACCVIFG. Writing to FCTL1 is allowed in block write mode when WAIT = 1, but writing to FCTL1 in block write mode when WAIT = 0 is an access violation and sets ACCVIFG. Any write to FCTL2 when the BUSY = 1 is an access violation. Any FCTLx register may be read when BUSY = 1. A read does not cause an access violation. 6-18 Flash Memory Controller Flash Memory Operation 6.3.8 Flash Memory Controller Interrupts The flash controller has two interrupt sources, KEYV and ACCVIFG. ACCVIFG is set when an access violation occurs. When the ACCVIE bit is re-enabled after a flash write or erase, a set ACCVIFG flag generates an interrupt request. ACCVIFG sources the NMI interrupt vector, so it is not necessary for GIE to be set for ACCVIFG to request an interrupt. ACCVIFG may also be checked by software to determine if an access violation occurred. ACCVIFG must be reset by software. The key violation flag KEYV is set when any of the flash control registers are written with an incorrect password. When this occurs, a PUC is generated, immediately resetting the device. 6.3.9 Programming Flash Memory Devices There are three options for programming an MSP430 flash device. All options support in-system programming: - Program via JTAG - Program via the bootstrap loader - Program via a custom solution Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port. The JTAG interface requires four signals, ground, and optionally VCC and RST/NMI. The JTAG port is protected with a fuse. Blowing the fuse completely disables the JTAG port and is not reversible. Further access to the device via JTAG is not possible For more details see the application report Programming a Flash-Based MSP430 Using the JTAG Interface (SLAA149) at www.ti.com/msp430. Programming Flash Memory via the Bootstrap Loader (BSL) Every MSP430 flash device contains a bootstrap loader. The BSL enables users to read or program the flash memory or RAM using a UART serial interface. Access to the MSP430 flash memory via the BSL is protected by a 256-bit, user-defined password. For more details see the application report Features of the MSP430 Bootstrap Loader (SLAA089) at www.ti.com/msp430. Flash Memory Controller 6-19 Flash Memory Operation Programming Flash Memory via a Custom Solution The ability of the MSP430 CPU to write to its own flash memory allows for in-system and external custom programming solutions as shown in Figure 6−12. The user can choose to provide data to the MSP430 through any means available (UART, SPI, etc.). User-developed software can receive the data and program the flash memory. Because this type of solution is developed by the user, it can be completely customized to fit the application needs for programming, erasing, or updating the flash memory. Figure 6−12. User-Developed Programming Solution Host MSP430 Commands, data, etc. Flash Memory UART, Px.x, SPI, etc. CPU executes user software Read/write flash memory 6-20 Flash Memory Controller Flash Memory Registers 6.4 Flash Memory Registers The flash memory registers are listed in Table 6−6. Table 6−6. Flash Memory Registers Register Short Form Register Type Address Flash memory control register 1 FCTL1 Read/write 0128h Flash memory control register 2 FCTL2 Read/write 012Ah Flash memory control register 3 Flash memory control register 4‡ FCTL3 FCTL4 Read/write Read/write 012Ch 01BEh Interrupt enable 1 IE1 Read/write 000h † 09658h in MSP430FG47x, MSP430F47x, MSP430F47x3/4, and MSP430F471xx devices ‡ MSP430FG47x, MSP430F47x, MSP430F47x3/4, and MSP430F471xx devices only Initial State 09600h with PUC 09642h with PUC 09618h† with PUC 0000h with PUC Reset with PUC Flash Memory Controller 6-21 Flash Memory Registers FCTL1, Flash Memory Control Register 15 14 13 12 11 10 9 8 FRKEY, Read as 096h FWKEY, Must be written as 0A5h 7 BLKWRT rw−0 6 WRT rw−0 5 Reserved r0 4 EEIEX‡ r0 3 GMERAS† EEI‡ rw-0 2 MERAS rw−0 1 ERASE rw−0 0 Reserved r0 † MSP430FG461x devices only. Reserved with r0 access on all other devices. ‡ F47x3/4 and F471xx devices only. Reserved with r0 access on all other devices. FRKEY/ FWKEY BLKWRT WRT Reserved EEIEX EEI Bits 15-8 Bit 7 Bit 6 Bit 5 Bit 4 Bits 3 FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC is generated. Block write mode. WRT must also be set for block write mode. BLKWRT is automatically reset when EMEX is set. 0 Block-write mode is off 1 Block-write mode is on Write. This bit is used to select any write mode. WRT is automatically reset when EMEX is set. 0 Write mode is off 1 Write mode is on Reserved. Always read as 0. Enable emergency interrupt exit. Setting this bit enables an interrupt to cause an emergency exit from a flash operation when GIE = 1. EEIEX is automatically reset when EMEX is set. 0 Exit interrupt disabled 1 Exit on interrupt enabled Enable erase Interrupts. Setting this bit allows a segment erase to be interrupted by an interrupt request. After the interrupt is serviced, the erase cycle is resumed. 0 Interrupts during segment erase disabled 1 Interrupts during segment erase enabled 6-22 Flash Memory Controller Flash Memory Registers GMERAS MERAS ERASE Bit 3 Bit 2 Bit 1 Global mass erase, mass erase, and erase. These bits are used together to select the erase mode. GMERAS, MERAS, and ERASE are automatically reset when EMEX is set or the erase operation completes. GMERAS 0 X 0 MERAS 0 0 1 0 1 1 1 1 1 ERASE 0 1 0 1 0 1 Erase Cycle No erase Erase individual segment only Erase main memory segment of selected array Erase main memory segments and information segments of selected array Erase main memory segments of all memory arrays. Erase all main memory and information segments of all memory arrays Reserved Bit 0 Reserved. Always read as 0. Flash Memory Controller 6-23 Flash Memory Registers FCTL2, Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 FSSELx FNx rw−0 rw−1 rw-0 rw-0 rw-0 rw−0 rw-1 rw−0 FWKEYx FSSELx FNx Bits 15-8 Bits 7−6 Bits 5-0 FCTLx password. Always read as 096h. Must be written as 0A5h, or a PUC is generated. Flash controller clock source select 00 ACLK 01 MCLK 10 SMCLK 11 SMCLK Flash controller clock divider. These six bits select the divider for the flash controller clock. The divisor value is FNx + 1. For example, when FNx = 00h, 0the divisor is 1. When FNx = 03Fh the divisor is 64. 6-24 Flash Memory Controller FCTL3, Flash Memory Control Register FCTL3 15 14 13 12 11 10 FWKEYx, Read as 096h Must be written as 0A5h Flash Memory Registers 9 8 7 FAIL† 6 LOCKA† 5 EMEX 4 LOCK 3 WAIT 2 ACCVIFG r(w)−0 r(w)−1 rw-0 rw-1 r-1 rw−0 † MSP430FG47x, MSP430F47x, MSP430F47x3/4, and MSP430F471xx devices only. Reserved with r0 access on all other devices. 1 KEYV rw-(0) 0 BUSY r(w)−0 FWKEYx FAIL Bits 15-8 Bit 7 LOCKA Bit 6 EMEX Bit 5 LOCK Bit 4 WAIT Bit 3 ACCVIFG Bit 2 FCTLx password. Always read as 096h. Must be written as 0A5h, or a PUC is generated. Operation failure. This bit is set if the fFTG clock source fails or if a flash operation is aborted from an interrupt when EEIEX = 1. FAIL must be reset with software. 0 No failure 1 Failure SegmentA and Info lock. Write a 1 to this bit to change its state. Writing 0 has no effect. 0 Segment A unlocked and all information memory is erased during a mass erase. 1 Segment A locked and all information memory is protected from erasure during a mass erase. Emergency exit 0 No emergency exit 1 Emergency exit Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit can be set anytime during a byte/word write or erase operation and the operation completes normally. In the block write mode, if the LOCK bit is set while BLKWRT=WAIT=1, then BLKWRT and WAIT are reset, and the mode ends normally. 0 Unlocked 1 Locked Wait. Indicates the flash memory is being written. 0 The flash memory is not ready for the next byte/word write 1 The flash memory is ready for the next byte/word write Access violation interrupt flag 0 No interrupt pending 1 Interrupt pending Flash Memory Controller 6-25 Flash Memory Registers KEYV BUSY Bit 1 Bit 0 Flash security key violation. This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set. KEYV must be reset with software. 0 FCTLx password was written correctly 1 FCTLx password was written incorrectly Busy. This bit indicates the status of the flash timing generator. 0 Not busy 1 Busy 6-26 Flash Memory Controller FCTL4, Flash Memory Control Register FCTL4 (FG47x, F47x, F47x3/4, and F471xx devices only) 15 14 13 12 11 10 FWKEYx, Read as 096h Must be written as 0A5h Flash Memory Registers 9 8 7 6 5 4 3 2 1 0 MRG1 MRG0 r-0 r-0 rw-0 rw-0 r-0 r-0 r-0 r-0 FWKEYx Reserved MRG1 Bits 15-8 Bits 7−6 Bit 5 MRG0 Bit 4 Reserved Bits 3−0 FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC will be generated. Reserved. Always read as 0. Marginal read 1 mode. This bit enables the marginal 1 read mode. The marginal read 1 bit is cleared if the CPU starts execution from the flash memory. If both MRG1 and MRG0 are set MRG1 is active and MRG0 is ignored. 0 Marginal 1 read mode is disabled. 1 Marginal 1 read mode is enabled. Marginal read 0 mode. This bit enables the marginal 0 read mode. The marginal mode 0 is cleared if the CPU starts execution from the flash memory. If both MRG1 and MRG0 are set MRG1 is active and MRG0 is ignored. 0 Marginal 0 read mode is disabled. 1 Marginal 0 read mode is enabled. Reserved. Always read as 0. Flash Memory Controller 6-27 Flash Memory Registers IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 ACCVIE rw−0 ACCVIE Bits 7-6, 4-0 Bit 5 These bits may be used by other modules. See device-specific data sheet. Flash memory access violation interrupt enable. This bit enables the ACCVIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled 6-28 Flash Memory Controller Chapter 7 Supply Voltage Supervisor This chapter describes the operation of the SVS. The SVS is implemented in all MSP430x4xx devices. Topic Page 7.1 SVS Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2 SVS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.3 SVS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Supply Voltage Supervisor 7-1 SVS Introduction 7.1 SVS Introduction The supply voltage supervisor (SVS) is used to monitor the AVCC supply voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user-selected threshold. The SVS features include: - AVCC monitoring - Selectable generation of POR - Output of SVS comparator accessible by software - Low-voltage condition latched and accessible by software - 14 selectable threshold levels - External channel to monitor external voltage The SVS block diagram is shown in Figure 7−1. Note: MSP430x412 and MSP430x413 Voltage Level Detect The MSP430x412 and MSP430x413 devices implement only one voltage level detect setting. When VLDx = 0, the SVS is off. Any value greater than 0 for VLDx selects a voltage level detect of 1.9V. 7-2 Supply Voltage Supervisor Figure 7−1. SVS Block Diagram AVCC AVCC D GS VCC Brownout Reset SVSIN 1111 0001 0010 1011 1100 1101 ~ 50us − + 1.2V D GS SVS Introduction SVS_POR tReset ~ 50us SVSOUT Set SVSFG Reset VLD PORON SVSON SVSOP SVSFG SVSCTL Bits Supply Voltage Supervisor 7-3 SVS Operation 7.2 SVS Operation The SVS detects if the AVCC voltage drops below a selectable level. It can be configured to provide a POR or set a flag when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve current consumption. 7.2.1 Configuring the SVS The VLDx bits are used to enable/disable the SVS and select one of 14 threshold levels (V(SVS_IT−)) for comparison with AVCC. The SVS is off when VLDx = 0 and on when VLDx > 0. The SVSON bit does not turn on the SVS. Instead, it reflects the on/off state of the SVS and can be used to determine when the SVS is on. When VLDx = 1111, the external SVSIN channel is selected. The voltage on SVSIN is compared to an internal level of approximately 1.2 V. 7.2.2 SVS Comparator Operation A low-voltage condition exists when AVCC drops below the selected threshold or when the external voltage drops below its 1.2-V threshold. Any low-voltage condition sets the SVSFG bit. The PORON bit enables or disables the device-reset function of the SVS. If PORON = 1, a POR is generated when SVSFG is set. If PORON = 0, a low-voltage condition sets SVSFG, but does not generate a POR. The SVSFG bit is latched. This allows user software to determine if a low-voltage condition occurred previously. The SVSFG bit must be reset by user software. If the low-voltage condition is still present when SVSFG is reset, it is immediately set again by the SVS. 7-4 Supply Voltage Supervisor SVS Operation 7.2.3 Changing the VLDx Bits When the VLDx bits are changed from zero to any non-zero value, there is an automatic settling delay, td(SVSon), implemented that allows the SVS circuitry to settle. The td(SVSon) delay is approximately 50 μs. During this delay, the SVS does not flag a low-voltage condition or reset the device, and the SVSON bit is cleared. Software can test the SVSON bit to determine when the delay has elapsed and the SVS is monitoring the voltage properly. Writing to SVSCTL while SVSON = 0 aborts the SVS automatic settling delay, td(SVSon), and switch the SVS to active mode immediately. In doing so, the SVS circuitry might not be settled, resulting in unpredictable behavior. When the VLDx bits are changed from any non-zero value to any other non-zero value, the circuitry requires the time tsettle to settle. The settling time tsettle is a maximum of ~12 μs (see the device-specific data sheet). There is no automatic delay implemented that prevents SVSFG to be set or to prevent a reset of the device. The recommended flow to switch between levels is shown in the following code. ; Enable SVS for the first time: MOV.B #080h,&SVSCTL ; Level 2.8V, do not cause POR ; ... ; Change SVS level MOV.B #000h,&SVSCTL MOV.B #018h,&SVSCTL ; ... ; Temporarily disable SVS ; Level 1.9V, cause POR Supply Voltage Supervisor 7-5 SVS Operation 7.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AVCC is close to the threshold. The SVS operation and SVS/Brownout interoperation are shown in Figure 7−2. Figure 7−2. Operating Levels for SVS and Brownout/Reset Circuit AVCC V(SVS_IT−) V(SVSstart) V(B_IT−) VCC(start) Brownout 1 Vhys(SVS_IT−) Vhys(B_IT−) Brownout Region 0 SVSOUT 1 t d(BOR) 0 Set SVS_POR 1 0 undefined Software Sets VLD>0 BrownOut Region SVS Circuit Active td(SVSon) td(SVSR) t d(BOR) 7-6 Supply Voltage Supervisor SVS Registers 7.3 SVS Registers The SVS registers are listed in Table 7−1. Table 7−1. SVS Registers Register SVS Control Register Short Form SVSCTL Register Type Address Read/write 056h Initial State Reset with BOR SVSCTL, SVS Control Register 7 6 5 4 VLDx rw−0† rw−0† rw−0† rw−0† † Reset by a brownout reset only, not by a POR or PUC. 3 PORON rw−0† 2 SVSON r† 1 SVSOP r† 0 SVSFG rw−0† VLDx PORON SVSON SVSOP SVSFG Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Voltage level detect. These bits turn on the SVS and select the nominal SVS threshold voltage level. See the device-specific data sheet for parameters. 0000 SVS is off 0001 1.9 V 0010 2.1 V 0011 2.2 V 0100 2.3 V 0101 2.4 V 0110 2.5 V 0111 2.65 V 1000 2.8 V 1001 2.9 V 1010 3.05 1011 3.2 V 1100 3.35 V 1101 3.5 V 1110 3.7 V 1111 Compares external input voltage SVSIN to 1.2 V. POR on. This bit enables the SVSFG flag to cause a POR device reset. 0 SVSFG does not cause a POR 1 SVSFG causes a POR SVS on. This bit reflects the status of SVS operation. This bit DOES NOT turn on the SVS. The SVS is turned on by setting VLDx > 0. 0 SVS is Off 1 SVS is On SVS output. This bit reflects the output value of the SVS comparator. 0 SVS comparator output is low 1 SVS comparator output is high SVS flag. This bit indicates a low voltage condition. SVSFG remains set after a low voltage condition until reset by software. 0 No low voltage condition occurred 1 A low condition is present or has occurred Supply Voltage Supervisor 7-7 7-8 Supply Voltage Supervisor Chapter 8 16-Bit Hardware Multiplier This chapter describes the 16-bit hardware multiplier. The hardware multiplier is implemented in MSP430x44x, MSP430FE42x, MSP430FE42xA, MSP430FE42x2, and MSP430F42x, MSP430F42xA devices. Topic Page 8.1 Hardware Multiplier Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 16-Bit Hardware Multiplier 8-1 Hardware Multiplier Introduction 8.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means that its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions. The hardware multiplier supports: - Unsigned multiply - Signed multiply - Unsigned multiply accumulate - Signed multiply accumulate - 16 × 16 bits, 16 × 8 bits, 8 × 16 bits, 8 × 8 bits The hardware multiplier block diagram is shown in Figure 8−1. Figure 8−1. Hardware Multiplier Block Diagram 15 rw 0 MPY 130h MPYS 132h MAC 134h MACS 136h Accessible Register MPY = 0000 MACS MPYS MAC Multiplexer OP1 15 rw 0 OP2 138h 16 x 16 Multipiler 32−bit Adder MPY, MPYS 32−bit Multiplexer MAC, MACS SUMEXT 13Eh 15 r C 0 S RESHI 13Ch 31 rw RESLO 13Ah rw 0 8-2 16-Bit Hardware Multiplier Hardware Multiplier Operation 8.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and signed multiply accumulate operations. The type of operation is selected by the address the first operand is written to. The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers, RESLO, RESHI, and SUMEXT. RESLO stores the low word of the result, RESHI stores the high word of the result, and SUMEXT stores information about the result. The result is ready in three MCLK cycles and can be read with the next instruction after writing to OP2, except when using an indirect addressing mode to access the result. When using indirect addressing for the result, a NOP is required before the result is ready. 8.2.1 Operand Registers The operand one register OP1 has four addresses, shown in Table 8−1, used to select the multiply mode. Writing the first operand to the desired address selects the type of multiply operation but does not start any operation. Writing the second operand to the operand two register OP2 initiates the multiply operation. Writing OP2 starts the selected operation with the values stored in OP1 and OP2. The result is written into the three result registers RESLO, RESHI, and SUMEXT. Repeated multiply operations may be performed without reloading OP1 if the OP1 value is used for successive operations. It is not necessary to re-write the OP1 value to perform the operations. Table 8−1. OP1 addresses OP1 Address 0130h 0132h 0134h 0136h Register Name MPY MPYS MAC MACS Operation Unsigned multiply Signed multiply Unsigned multiply accumulate Signed multiply accumulate 16-Bit Hardware Multiplier 8-3 Hardware Multiplier Operation 8.2.2 Result Registers The result low register RESLO holds the lower 16-bits of the calculation result. The result high register RESHI contents depend on the multiply operation and are listed in Table 8−2. Table 8−2. RESHI Contents Mode MPY MPYS MAC MACS RESHI Contents Upper 16 bits of the result The MSB is the sign of the result. The remaining bits are the upper 15 bits of the result. Two’s complement notation is used for the result. Upper 16 bits of the result Upper 16 bits of the result. Two’s complement notation is used for the result. The sum extension registers SUMEXT contents depend on the multiply operation and are listed in Table 8−3. Table 8−3. SUMEXT Contents Mode MPY MPYS MAC MACS SUMEXT SUMEXT is always 0000h SUMEXT contains the extended sign of the result 00000h Result was positive or zero 0FFFFh Result was negative SUMEXT contains the carry of the result 0000h No carry for result 0001h Result has a carry SUMEXT contains the extended sign of the result 00000h Result was positive or zero 0FFFFh Result was negative MACS Underflow and Overflow The multiplier does not automatically detect underflow or overflow in the MACS mode. The accumulator range for positive numbers is 0 to 7FFF FFFFh and for negative numbers is 0FFFF FFFFh to 8000 0000h. An underflow occurs when the sum of two negative numbers yields a result that is in the range for a positive number. An overflow occurs when the sum of two positive numbers yields a result that is in the range for a negative number. In both of these cases, the SUMEXT register contains the sign of the result, 0FFFFh for overflow and 0000h for underflow. User software must detect and handle these conditions appropriately. 8-4 16-Bit Hardware Multiplier Hardware Multiplier Operation 8.2.3 Software Examples Examples for all multiplier modes follow. All 8x8 modes use the absolute address for the registers, because the assembler does not allow .B access to word registers when using the labels from the standard definitions file. ; 16x16 Unsigned Multiply MOV #01234h,&MPY ; Load first operand MOV #05678h,&OP2 ; Load second operand ; ... ; Process results ; 8x8 Unsigned Multiply. Absolute addressing. MOV.B #012h,&0130h ; Load first operand MOV.B #034h,&0138h ; Load 2nd operand ; ... ; Process results ; 16x16 Signed Multiply MOV #01234h,&MPYS ; Load first operand MOV #05678h,&OP2 ; Load 2nd operand ; ... ; Process results ; 8x8 Signed Multiply. Absolute addressing. MOV.B #012h,&0132h ; Load first operand SXT &MPYS ; Sign extend first operand MOV.B #034h,&0138h ; Load 2nd operand SXT &OP2 ; Sign extend 2nd operand ; (triggers 2nd multiplication) ; ... ; Process results ; 16x16 Unsigned Multiply Accumulate MOV #01234h,&MAC ; Load first operand MOV #05678h,&OP2 ; Load 2nd operand ; ... ; Process results ; 8x8 Unsigned Multiply Accumulate. Absolute addressing MOV.B #012h,&0134h ; Load first operand MOV.B #034h,&0138h ; Load 2nd operand ; ... ; Process results ; 16x16 Signed Multiply Accumulate MOV #01234h,&MACS ; Load first operand MOV #05678h,&OP2 ; Load 2nd operand ; ... ; Process results ; 8x8 Signed Multiply Accumulate. Absolute addressing MOV.B #012h,&0136h ; Load first operand SXT &MACS ; Sign extend first operand MOV.B #034h,R5 ; Temp. location for 2nd operand SXT R5 ; Sign extend 2nd operand MOV R5,&OP2 ; Load 2nd operand ; ... ; Process results 16-Bit Hardware Multiplier 8-5 Hardware Multiplier Operation 8.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers, At least one instruction is needed between loading the second operand and accessing one of the result registers. ; Access multiplier results with indirect addressing MOV #RESLO,R5 ; RESLO address in R5 for indirect MOV &OPER1,&MPY ; Load 1st operand MOV &OPER2,&OP2 ; Load 2nd operand NOP ; Need one cycle MOV @R5+,&xxx ; Move RESLO MOV @R5,&xxx ; Move RESHI 8.2.5 Using Interrupts If an interrupt occurs after writing OP1 but before writing OP2, and the multiplier is used in servicing that interrupt, the original multiplier mode selection is lost and the results are unpredictable. To avoid this, disable interrupts before using the hardware multiplier or do not use the multiplier in interrupt service routines. ; Disable interrupts before using the hardware multiplier DINT ; Disable interrupts NOP ; Required for DINT MOV #xxh,&MPY ; Load 1st operand MOV #xxh,&OP2 ; Load 2nd operand EINT ; Interrupts may be enable before ; Process results 8-6 16-Bit Hardware Multiplier Hardware Multiplier Registers 8.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 8−4. Table 8−4. Hardware Multiplier Registers Register Short Form Operand one - multiply MPY Operand one - signed multiply MPYS Operand one - multiply accumulate MAC Operand one - signed multiply accumulate MACS Operand two OP2 Result low word RESLO Result high word RESHI Sum Extension register SUMEXT Register Type Address Read/write 0130h Read/write 0132h Read/write 0134h Read/write 0136h Read/write 0138h Read/write 013Ah Read/write 013Ch Read 013Eh Initial State Unchanged Unchanged Unchanged Unchanged Unchanged Undefined Undefined Undefined 16-Bit Hardware Multiplier 8-7 8-8 16-Bit Hardware Multiplier Chapter 9 32-Bit Hardware Multiplier This chapter describes the 32-bit hardware multiplier (MPY32) of the MSP430x4xx family. The 32-bit hardware multiplier is implemented in MSP430F47x3/4 and MSP430F471xx devices. Topic Page 9.1 32-Bit Hardware Multiplier Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 32-Bit Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3 32-Bit Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 32-Bit Hardware Multiplier 9-1 32-Bit Hardware Multiplier Introduction 9.1 32-Bit Hardware Multiplier Introduction The 32-bit hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions. The hardware multiplier supports: - Unsigned multiply - Signed multiply - Unsigned multiply accumulate - Signed multiply accumulate - 8-bit, 16-bit, 24-bit and 32-bit operands - Saturation - Fractional numbers - 8-bit and 16-bit operation compatible with 16-bit hardware multiplier - 8-bit and 24-bit multiplications without requiring a “sign extend” instruction The 32-bit hardware multiplier block diagram is shown in Figure 9−1. 9-2 32-Bit Hardware Multiplier Figure 9−1. 32-Bit Hardware Multiplier Block Diagram 32-Bit Hardware Multiplier Introduction Accessible Register MPY MPYS MAC MACS MPY32H MPY32L MPYS32H MPYS32L MAC32H MAC32L MACS32H MACS32L 31 16 15 0 OP1 (high word) OP1 (low word) OP2 OP2H OP2L 31 16 15 0 OP2 (high word) OP2 (low word) 16−bit Multiplexer 16−bit Multiplexer OP1_32 OP2_32 MPYMx 2 MPYSAT MPYFRAC MPYC Control Logic SUMEXT RES3 16 x 16 Multiplier 32−bit Adder 32−bit De−Multiplexer RES2 RES1/RESHI RES0/RESLO 32−bit Multiplexer 32-Bit Hardware Multiplier 9-3 32-Bit Hardware Multiplier Operation 9.2 32-Bit Hardware Multiplier Operation The hardware multiplier supports 8-bit, 16-bit, 24-bit, and 32-bit operands with unsigned multiply, signed multiply, unsigned multiply-accumulate, and signed multiply-accumulate operations. The size of the operands are defined by the address the operand is written to and if it is written as word or byte. The type of operation is selected by the address the first operand is written to. The hardware multiplier has two 32-bit operand registers, operand one OP1 and operand two OP2, and a 64-bit result register accessible via registers RES0 to RES3. For compatibility with the 16x16 hardware multiplier the result of a 8-bit or 16-bit operation is accessible via RESLO, RESHI, and SUMEXT, as well. RESLO stores the low word of the 16x16-bit result, RESHI stores the high word of the result, and SUMEXT stores information about the result. The result of a 8-bit or 16-bit operation is ready in three MCLK cycles and can be read with the next instruction after writing to OP2, except when using an indirect addressing mode to access the result. When using indirect addressing for the result, a NOP is required before the result is ready. The result of a 24-bit or 32-bit operation can be read with successive instructions after writing OP2 or OP2H starting with RES0, except when using an indirect addressing mode to access the result. When using indirect addressing for the result, a NOP is required before the result is ready. Table 9−1 summarizes when each word of the 64-bit result is available for the various combinations of operand sizes. With a 32-bit wide second operand OP2L and OP2H needs to be written. Depending on when the two 16-bit parts are written the result availability may vary thus the table shows two entries, one for OP2L written and one for OP2H written. The worst case defines the actual result availability. Table 9−1. Result Availability (MPYFRAC = 0; MPYSAT = 0) Operation Result ready in MCLK cycles (OP1 x OP2) RES0 RES1 RES2 8/16 x 8/16 3 3 4 24/32 x 8/16 3 5 6 8/16 x 24/32 3 5 6 N/A 3 4 24/32 x 24/32 3 8 10 N/A 3 5 RES3 4 7 7 4 11 6 MPYC Bit 3 7 7 4 11 6 After OP2 written OP2 written OP2L written OP2H written OP2L written OP2H written 9-4 32-Bit Hardware Multiplier 32-Bit Hardware Multiplier Operation 9.2.1 Operand Registers Operand one OP1 has twelve registers, shown in Table 9−2, used to load data into the multiplier and also select the multiply mode. Writing the low-word of the first operand to a given address selects the type of multiply operation to be performed but does not start any operation. When writing a second word to a high-word register with suffix “32H“ the multiplier assumes a 32-bit wide OP1, otherwise 16-bits are assumed. The last address written prior to writing OP2 defines the width of the first operand. For example, if MPY32L is written first followed by MPY32H, all 32 bits are used and the data width of OP1 is set to 32 bits. If MPY32H is written first followed by MPY32L, the multiplication will ignore MPY32H and assume a 16−bit wide OP1 using the data written into MPY32L. Repeated multiply operations may be performed without reloading OP1 if the OP1 value is used for successive operations. It is not necessary to rewrite the OP1 value to perform the operations. Table 9−2. OP1 registers OP1 Register Name Operation MPY Unsigned Multiply − operand bits 0 up to 15 MPYS Signed Multiply − operand bits 0 up to 15 MAC Unsigned Multiply Accumulate − operand bits 0 up to 15 MACS Signed Multiply Accumulate − operand bits 0 up to 15 MPY32L Unsigned Multiply − operand bits 0 up to 15 MPY32H Unsigned Multiply − operand bits 16 up to 31 MPYS32L Signed Multiply − operand bits 0 up to 15 MPYS32H Signed Multiply − operand bits 16 up to 31 MAC32L Unsigned Multiply Accumulate − operand bits 0 up to 15 MAC32H Unsigned Multiply Accumulate − operand bits 16 up to 31 MACS32L Signed Multiply Accumulate − operand bits 0 up to 15 MACS32H Signed Multiply Accumulate − operand bits 16 up to 31 Writing the second operand to the operand two register OP2 initiates the multiply operation. Writing OP2 starts the selected operation with a 16-bit wide second operand together with the values stored in OP1. Writing OP2L starts the selected operation with a 32-bit wide second operand and the multiplier expects a the high word to be written to OP2H. Writing to OP2H without a preceding write to OP2L is ignored. 32-Bit Hardware Multiplier 9-5 32-Bit Hardware Multiplier Operation Table 9−3. OP2 registers OP2 Register Name Operation OP2 Start multiplication with 16-bit wide operand two OP2 (operand bits 0 up to 15) OP2L Start multiplication with 32-bit wide operand two OP2 (operand bits 0 up to 15) OP2H Continue multiplication with 32-bit wide operand two OP2 (operand bits 16 up to 31) For 8-bit or 24-bit operands the operand registers can be accessed with byte instructions. Accessing the multiplier with a byte instruction during a signed operation will automatically cause a sign extension of the byte within the multiplier module. For 24-bit operands only the high word should be written as byte. Whether or not the 24-bit operands are sign extended is defined by the register that is used to write the low word, because this register defines if the operation is unsigned or signed. The high word of a 32-bit operand remains unchanged when changing the size of the operand to 16 bit either by modifying the operand size bits or by writing to the respective operand register. During the execution of the 16-bit operation the content of the high word is ignored. Note: Changing of First or Second Operand During Multiplication Changing OP1 or OP2 while the selected multiply operation is being calculated will render any results invalid that are not ready at the time the new operand(s) are changed. Writing OP2 or OP2L will abort any ongoing calculation and start a new operation. Results that are not ready at that time are invalid also for following MAC or MACS operations. Refer to the tables “Result Availability” for the different modes on how many CPU cycles are needed until a certain result register is ready and valid. 9-6 32-Bit Hardware Multiplier 32-Bit Hardware Multiplier Operation 9.2.2 Result Registers The multiplication result is always 64-bits wide. It is accessible via registers RES0 to RES3. Used with a signed operation MPYS or MACS the results are appropriately sign extended. If the result registers are loaded with initial values before a MACS operation the user software must take care that the written value is properly sign extended to 64 bits. Note: Changing of Result Registers During Multiplication The result registers must not be modified by the user software after writing the second operand into OP2 or OP2L until the initiated operation is completed. In addition to RES0 to RES3, for compatibility with the 16×16 hardware multiplier the 32-bit result of a 8-bit or 16-bit operation is accessible via RESLO, RESHI, and SUMEXT. In this case the result low register RESLO holds the lower 16-bits of the calculation result and the result high register RESHI holds the upper 16 bits. RES0 and RES1 are identical to RESLO and RESHI, respectively, in usage and access of calculated results. The sum extension registers SUMEXT contents depend on the multiply operation and are listed in Table 9−4. If all operands are 16 bits wide or less the 32-bit result is used to determine sign and carry. If one of the operands is larger than 16 bits the 64-bit result is used. The MPYC bit reflects the multiplier’s carry as listed in Table 9−4 and thus can be used as 33rd or 65th bit of the result if fractional or saturation mode is not selected. With MAC or MACS operations the MPYC bit reflects the carry of the 32-bit or 64-bit accumulation and is not taken into account for successive MAC and MACS operations as the 33rd or 65th bit. Table 9−4. SUMEXT Contents and MPYC Contents Mode MPY MPYS MAC MACS SUMEXT SUMEXT is always 0000h SUMEXT contains the extended sign of the result 00000h Result was positive or zero 0FFFFh Result was negative SUMEXT contains the carry of the result 0000h No carry for result 0001h Result has a carry SUMEXT contains the extended sign of the result 00000h Result was positive or zero 0FFFFh Result was negative MPYC MPYC is always 0 MPYC contains the sign of the result 0 Result was positive or zero 1 Result was negative MPYC contains the carry of the result 0 No carry for result 1 Result has a carry MPYC contains the carry of the result 0 No carry for result, 1 Result has a carry 32-Bit Hardware Multiplier 9-7 32-Bit Hardware Multiplier Operation MACS Underflow and Overflow The multiplier does not automatically detect underflow or overflow in MACS mode. For example working with 16-bit input data and 32-bit results, i.e. using just RESLO and RESHI, the available range for positive numbers is 0 to 07FFF FFFFh and for negative numbers is 0FFFF FFFFh to 08000 0000h. An underflow occurs when the sum of two negative numbers yields a result that is in the range for a positive number. An overflow occurs when the sum of two positive numbers yields a result that is in the range for a negative number. The SUMEXT register contains the sign of the result in both cases described above, 0FFFFh for a 32-bit overflow and 0000h for a 32-bit underflow. The MPYC bit in MPY32CTL0 can be used to detect the overflow condition. If the carry is different than the sign reflected by the SUMEXT register an overflow or underflow occurred. User software must handle these conditions appropriately. 9-8 32-Bit Hardware Multiplier 32-Bit Hardware Multiplier Operation 9.2.3 Software Examples Examples for all multiplier modes follow. All 8×8 modes use the absolute address for the registers because the assembler will not allow .B access to word registers when using the labels from the standard definitions file. There is no sign extension necessary in software. Accessing the multiplier with a byte instruction during a signed operation will automatically cause a sign extension of the byte within the multiplier module. ; 32x32 Unsigned Multiply MOV #01234h,&MPY32L ; Load low word of 1st operand MOV #01234h,&MPY32H ; Load high word of 1st operand MOV #05678h,&OP2L ; Load low word of 2nd operand MOV #05678h,&OP2H ; Load high word of 2nd operand ; ... ; Process results ; 16x16 Unsigned Multiply MOV #01234h,&MPY ; Load 1st operand MOV #05678h,&OP2 ; Load 2nd operand ; ... ; Process results ; 8x8 Unsigned Multiply. Absolute addressing. MOV.B #012h,&MPY_B ; Load 1st operand MOV.B #034h,&OP2_B ; Load 2nd operand ; ... ; Process results ; 32x32 Signed Multiply MOV #01234h,&MPYS32L ; Load low word of 1st operand MOV #01234h,&MPYS32H ; Load high word of 1st operand MOV #05678h,&OP2L ; Load low word of 2nd operand MOV #05678h,&OP2H ; Load high word of 2nd operand ; ... ; Process results ; 16x16 Signed Multiply MOV #01234h,&MPYS MOV #05678h,&OP2 ; ... ; Load 1st operand ; Load 2nd operand ; Process results ; 8x8 Signed Multiply. Absolute addressing. MOV.B #012h,&MPYS_B ; Load 1st operand MOV.B #034h,&OP2_B ; Load 2nd operand ; ... ; Process results 32-Bit Hardware Multiplier 9-9 32-Bit Hardware Multiplier Operation 9.2.4 Fractional Numbers The 32-bit multiplier provides support for fixed-point signal processing. In fixed−point signal processing, fractional number are represented by using a fixed decimal point. To classify different ranges of decimal numbers, a Q-format is used. Different Q-formats represent different locations of the decimal point. Figure 9−2 shows the format of a signed Q15 number using 16 bits. Every bit after the decimal point has a resolution of 1/2, the most significant bit is used as the sign bit. The most negative number is 08000h and the maximum positive number is 07FFFh. This gives a range from −1.0 to 0.999969482 ≅ 1.0 for the signed Q15 format with 16 bits. Figure 9−2. Q15 Format Representation S 1 2 1 4 1 8 1 16 ... 15 bits Decimal point Sign bit Decimal number equivalent The range can be increased by shifting the decimal point to the right as shown in Figure 9−3. The signed Q14 format with 16 bits gives a range from −2.0 to 1.999938965 ≅ 2.0. Figure 9−3. Q14 Format Representation S x 1 2 1 4 1 8 1 16 ... 14 bits The benefit of using 16-bit signed Q15 or 32-bit signed Q31 numbers with multiplication is that the product of two number in the range from −1.0 to 1.0 is always in that same range. 9-10 32-Bit Hardware Multiplier 32-Bit Hardware Multiplier Operation Fractional Number Mode Multiplying two fractional numbers using the default multiplication mode with MPYFRAC = 0 and MPYSAT = 0 gives a result with 2 sign bits. For example if two 16-bit Q15 numbers are multiplied a 32-bit result in Q30 format is obtained. To convert the result into Q15 format manually, the first 15 trailing bits and the extended sign bit must be removed. However, when the fractional mode of the multiplier is used, the redundant sign bit is automatically removed yielding a result in Q31 format for the multiplication of two 16-bit Q15 numbers. Reading the result register RES1 gives the result as 16-bit Q15 number. The 32-bit Q31 result of a multiplication of two 32-bit Q31 numbers is accessed by reading registers RES2 and RES3. The fractional mode is enabled with MPYFRAC = 1 in register MPY32CTL0. The actual content of the result register(s) is not modified when MPYFRAC = 1. When the result is accessed using software, the value is left−shifted 1 bit resulting in the final Q formatted result. This allows user software to switch between reading both the shifted (fractional) and the un-shifted result. The fractional mode should only be enabled when required and disabled after use. In fractional mode the SUMEXT register contains the sign extended bits 32 and 33 of the shifted result for 16x16-bit operations and bits 64 and 65 for 32x32-bit operations − not only bits 32 or 64, respectively. The MPYC bit is not affected by the fractional mode. It always reads the carry of the nonfractional result. ; Example using ; Fractional 16x16 multiplication BIS #MPYFRAC,&MPY32CTL0 ; Turn on fractional mode MOV &FRACT1,&MPYS ; Load 1st operand as Q15 MOV &FRACT2,&OP2 ; Load 2nd operand as Q15 MOV &RES1,&PROD ; Save result as Q15 BIC #MPYFRAC,&MPY32CTL0 ; Back to normal mode Table 9−5. Result Availability in Fractional Mode (MPYFRAC = 1; MPYSAT = 0) Operation Result ready in MCLK cycles (OP1 x OP2) RES0 RES1 RES2 8/16 x 8/16 3 3 4 24/32 x 8/16 3 5 6 8/16 x 24/32 3 5 6 N/A 3 4 24/32 x 24/32 3 8 10 N/A 3 5 RES3 4 7 7 4 11 6 MPYC Bit 3 7 7 4 11 6 After OP2 written OP2 written OP2L written OP2H written OP2L written OP2H written 32-Bit Hardware Multiplier 9-11 32-Bit Hardware Multiplier Operation Saturation Mode The multiplier prevents overflow and underflow of signed operations in saturation mode. The saturation mode is enabled with MPYSAT = 1 in register MPY32CTL0. If an overflow occurs the result is set to the most positive value available. If an underflow occurs the result is set to the most negative value available. This is useful to reduce mathematical artifacts in control systems on overflow and underflow conditions. The saturation mode should only be enabled when required and disabled after use. The actual content of the result register(s) is not modified when MPYSAT = 1. When the result is accessed using software, the value is automatically adjusted providing the most positive or most negative result when an overflow or underflow has occurred. The adjusted result is also used for successive multiply−and−accumulate operations. This allows user software to switch between reading the saturated and the non-saturated result. With 16x16 operations the saturation mode only applies to the least significant 32 bits, i.e. the result registers RES0 and RES1. Using the saturation mode in MAC or MACS operations that mix 16x16 operations with 32x32, 16x32 or 32x16 operations will lead to unpredictable results. With 32x32, 16x32, and 32x16 operations the saturated result can only be calculated when RES3 is ready. In non-5xx devices, reading RES0 to RES2 prior to the complete result being ready will deliver the nonsaturated results, independent of the MPYSAT bit setting. Enabling the saturation mode does not affect the content of the SUMEXT register nor the content of the MPYC bit. ; Example using ; Fractional 16x16 multiply accumulate with Saturation ; Turn on fractional and saturation mode: BIS #MPYSAT+MPYFRAC,&MPY32CTL0 MOV &A1,&MPYS ; Load A1 for 1st term MOV &K1,&OP2 ; Load K1 to get A1*K1 MOV &A2,&MACS ; Load A2 for 2nd term MOV &K2,&OP2 ; Load K2 to get A2*K2 MOV &RES1,&PROD ; Save A1*K1+A2*K2 as result BIC #MPYSAT+MPYFRAC,&MPY32CTL0; turn back to normal Table 9−6. Result Availability in Saturation Mode (MPYSAT = 1) Operation Result ready in MCLK cycles (OP1 x OP2) RES0 RES1 RES2 8/16 x 8/16 3 3 N/A 24/32 x 8/16 7 7 7 8/16 x 24/32 7 7 7 4 4 4 24/32 x 24/32 11 11 11 6 6 6 RES3 N/A 7 7 4 11 6 MPYC Bit 3 7 7 4 11 6 after OP2 written OP2 written OP2L written OP2H written OP2L written OP2H written 9-12 32-Bit Hardware Multiplier 32-Bit Hardware Multiplier Operation Figure 9−4 shows the flow for 32-bit saturation used for 16×16 bit multiplications and the flow for 64-bit saturation used in all other cases. Primarily, the saturated results depends on the carry bit MPYC and the most significant bit of the result. Secondly, if the fractional mode is enabled it depends also on the two most significant bits of the unshift result; i.e., the result that is read with fractional mode disabled. Figure 9−4. Saturation Flow Chart 32−bit Saturation 64−bit Saturation MPYC=0 and unshifted RES1, bit 15=1 No MPYC=1 and unshifted RES1, bit 15=0 No MPYFRAC = 1 Overflow: Yes RES3 unchanged RES2 unchanged RES1 = 07FFFh RES0 = 0FFFFh Underflow: Yes RES3 unchanged RES2 unchanged RES1 = 08000h RES0 = 00000h No Yes unshifted RES1, bit 15=0 and bit 14=1 No unshifted RES1, bit 15=1 and bit 14=0 No Overflow: Yes RES3 unchanged RES2 unchanged RES1 = 07FFFh RES0 = 0FFFFh Underflow: Yes RES3 unchanged RES2 unchanged RES1 = 08000h RES0 = 00000h 32−bit Saturation completed MPYC=0 and unshifted RES3, bit 15=1 No MPYC=1 and unshifted RES3, bit 15=0 No MPYFRAC = 1 Overflow: Yes RES3 = 07FFFh RES2 = 0FFFFh RES1 = 0FFFFh RES0 = 0FFFFh Underflow: Yes RES3 = 08000h RES2 = 00000h RES1 = 00000h RES0 = 00000h No Yes unshifted RES3, bit 15=0 and bit 14=1 No unshifted RES3, bit 15=1 and bit 14=0 No Overflow: Yes RES3 = 07FFFh RES2 = 0FFFFh RES1 = 0FFFFh RES0 = 0FFFFh Underflow: Yes RES3 = 08000h RES2 = 00000h RES1 = 00000h RES0 = 00000h 64−bit Saturation completed Note: Saturation in Fractional Mode In case of multiplying −1.0 x −1.0 in fractional mode, the result of +1.0 is out of range, thus, the saturated result gives the most positive result. 32-Bit Hardware Multiplier 9-13 32-Bit Hardware Multiplier Operation The following example illustrates a special case showing the saturation function in fractional mode. It also uses the 8-bit functionality of the MPY32 module. ; Turn on fractional and saturation mode, ; clear all other bits in MPY32CTL0: MOV #MPYSAT+MPYFRAC,&MPY32CTL0 ;Pre−load result registers to demonstrate overflow MOV #0,&RES3 ; MOV #0,&RES2 ; MOV #07FFFh,&RES1 ; MOV #0FA60h,&RES0 ; MOV.B #050h,&MACS_B ; 8-bit signed MAC operation MOV.B #012h,&OP2_B ; Start 16x16 bit operation MOV &RES0,R6 ; R6 = 0FFFFh MOV &RES1,R7 ; R7 = 07FFFh The result is saturated because already the result not converted into a fractional number shows an overflow. The multiplication of the two positive numbers 00050h and 00012h gives 005A0h. 005A0h added to 07FFF.FA60h results in 8000.059F without MPYC being set. Since the MSB of the unmodified result RES1 is 1 and MPYC = 0 the result is saturated according to the saturation flow chart in Figure 9−4. Note: Validity of Saturated Result The saturated result is only valid if the registers RES0 to RES3, the size of operands 1 and 2 and MPYC are not modified. If the saturation mode is used with a preloaded result, user software must ensure that MPYC in the MPY32CTL0 register is loaded with the sign bit of the written result otherwise the saturation mode erroneously saturates the result. 9-14 32-Bit Hardware Multiplier 32-Bit Hardware Multiplier Operation 9.2.5 Putting It All Together Figure 9−5 shows the complete multiplication flow depending on the various selectable modes for the MPY32 module. Figure 9−5. Multiplication Flow Chart New Multiplication started No Clear Result: RES1 = 00000h RES0 = 00000h Yes Yes MAC or MACS ? Yes MPYSAT=1 ? 32−bit Saturation No 16x16 ? No Yes MAC or MACS ? Yes MPYSAT=1 ? No 64−bit Saturation No Clear Result: RES3 = 00000h RES2 = 00000h RES1 = 00000h RES0 = 00000h Perform 16x16 MPY or MPYS Operation Perform 16x16 MAC or MACS Operation Perform MAC or MACS Operation Perform MPY or MPYS Operation MPYFRAC=1 ? No Yes Shift 64−bit result. Calculate SUMEXT based on MPYC and bit 15 of unshifted RES1. Yes Shift 64−bit result. Calculate SUMEXT based on MPYC and bit 15 of unshifted RES3. MPYFRAC=1 ? No MPYSAT=1 ? No Yes 32−bit Saturation Yes 64−bit Saturation MPYSAT=1 ? No Multiplication completed 32-Bit Hardware Multiplier 9-15 32-Bit Hardware Multiplier Operation Given the separation in processing of 16-bit operations (32-bit results) and 32-bit operations (64-bit results) by the module, it is important to understand the implications when using MAC/MACS operations and mixing 16-bit operands/results with 32-bit operands/results. User software must address these points during usage when mixing these operations. The following code illustrates the issue. ; Mixing 32x24 multiplication with 16x16 MACS operation MOV #MPYSAT,&MPY32CTL0; Saturation mode MOV #052C5h,&MPY32L ; Load low word of 1st operand MOV #06153h,&MPY32H ; Load high word of 1st operand MOV #001ABh,&OP2L ; Load low word of 2nd operand MOV.B #023h,&OP2H_B ; Load high word of 2nd operand ;... 5 NOPs required MOV &RES0,R6 ; R6 = 00E97h MOV &RES1,R7 ; R7 = 0A6EAh MOV &RES2,R8 ; R8 = 04F06h MOV &RES3,R9 ; R9 = 0000Dh ; Note that MPYC = 0! MOV #0CCC3h,&MACS ; Signed MAC operation MOV #0FFB6h,&OP2 ; 16x16 bit operation MOV &RESLO,R6 ; R6 = 0FFFFh MOV &RESHI,R7 ; R7 = 07FFFh The second operation gives a saturated result because the 32-bit value used for the 16x16 bit MACS operation was already saturated when the operation was started: the carry bit MPYC was 0 from the previous operation but the most significant bit in result register RES1 is set. As one can see in the flow chart the content of the result registers are saturated for multiply-and-accumulate operations after starting a new operation based on the previous results but depending on the size of the result (32-bit or 64-bit) of the newly initiated operation. The saturation before the multiplication can cause issues if the MPYC bit is not properly set as the following code example illustrates. ;Pre−load result registers to demonstrate overflow MOV #0,&RES3 ; MOV #0,&RES2 ; MOV #0,&RES1 ; MOV #0,&RES0 ; ; Saturation mode and set MPYC: MOV #MPYSAT+MPYC,&MPY32CTL0 MOV.B #082h,&MACS_B ; 8-bit signed MAC operation MOV.B #04Fh,&OP2_B ; Start 16x16 bit operation MOV &RES0,R6 ; R6 = 00000h MOV &RES1,R7 ; R7 = 08000h 9-16 32-Bit Hardware Multiplier 32-Bit Hardware Multiplier Operation Even though the result registers were loaded with all zeros the final result is saturated. This is because the MPYC bit was set causing the result used for the multiply-and-accumulate to be saturated to 08000 0000h. Adding a negative number to it would again cause an underflow thus the final result is also saturated to 08000 0000h. 9.2.6 Indirect Addressing of Result Registers When using indirect or indirect autoincrement addressing mode to access the result registers and the multiplier requires 3 cycles until result availability according to Table 9−1, at least one instruction is needed between loading the second operand and accessing the result registers: ; Access multiplier 16x16 results with indirect addressing MOV #RES0,R5 ; RES0 address in R5 for indirect MOV &OPER1,&MPY ; Load 1st operand MOV &OPER2,&OP2 ; Load 2nd operand NOP ; Need one cycle MOV @R5+,&xxx ; Move RES0 MOV @R5,&xxx ; Move RES1 In case of a 32x16 multiplication there is also one instruction required between reading the first result register RES0 and the second result register RES1: ; Access multiplier 32x16 results with indirect addressing MOV #RES0,R5 ; RES0 address in R5 for indirect MOV &OPER1L,&MPY32L ; Load low word of 1st operand MOV &OPER1H,&MPY32H ; Load high word of 1st operand MOV &OPER2,&OP2 ; Load 2nd operand (16 bits) NOP ; Need one cycle MOV @R5+,&xxx ; Move RES0 NOP ; Need one additional cycle MOV @R5,&xxx ; Move RES1 ; No additional cycles required! MOV @R5,&xxx ; Move RES2 32-Bit Hardware Multiplier 9-17 32-Bit Hardware Multiplier Operation 9.2.7 Using Interrupts If an interrupt occurs after writing OP1, but before writing OP2, and the multiplier is used in servicing that interrupt, the original multiplier mode selection is lost and the results are unpredictable. To avoid this, disable interrupts before using the hardware multiplier, do not use the multiplier in interrupt service routines, or use the save and restore functionality of the 32-bit multiplier. ; Disable interrupts before using the hardware multiplier DINT ; Disable interrupts NOP ; Required for DINT MOV #xxh,&MPY ; Load 1st operand MOV #xxh,&OP2 ; Load 2nd operand EINT ; Interrupts may be enabled before ; processing results if result ; registers are stored and restored in ; interrupt service routines 9-18 32-Bit Hardware Multiplier 32-Bit Hardware Multiplier Operation Save and Restore If the multiplier is used in interrupt service routines its state can be saved and restored using the MPY32CTL0 register. The following code example shows how the complete multiplier status can be saved and restored to allow interruptible multiplications together with the usage of the multiplier in interrupt service routines. Since the state of the MPYSAT and MPYFRAC bits are unknown they should be cleared before the registers are saved as shown in the code example. ; Interrupt service routine using multiplier MPY_USING_ISR PUSH &MPY32CTL0 ; Save multiplier mode, etc. BIC #MPYSAT+MPYFRAC,&MPY32CTL0 ; Clear MPYSAT+MPYFRAC PUSH &RES3 ; Save result 3 PUSH &RES2 ; Save result 2 PUSH &RES1 ; Save result 1 PUSH &RES0 ; Save result 0 PUSH &MPY32H ; Save operand 1, high word PUSH &MPY32L ; Save operand 1, low word PUSH &OP2H ; Save operand 2, high word PUSH &OP2L ; Save operand 2, low word ; ... ; Main part of ISR ; Using standard MPY routines ; POP &OP2L ; Restore operand 2, low word POP &OP2H ; Restore operand 2, high word ; Starts dummy multiplication but ; result is overwritten by ; following restore operations: POP &MPY32L ; Restore operand 1, low word POP &MPY32H ; Restore operand 1, high word POP &RES0 ; Restore result 0 POP &RES1 ; Restore result 1 POP &RES2 ; Restore result 2 POP &RES3 ; Restore result 3 POP &MPY32CTL0 ; Restore multiplier mode, etc. reti ; End of interrupt service routine 32-Bit Hardware Multiplier 9-19 32-Bit Hardware Multiplier Operation 9.2.8 Using DMA In devices with a DMA controller the multiplier can trigger a transfer when the complete result is available. The DMA controller needs to start reading the result with MPY32RES0 successively up to MPY32RES3. Not all registers need to be read. The trigger timing is such that the DMA controller starts reading MPY32RES0 when its ready and that the MPY32RES3 can be read exactly in the clock cycle when it is available to allow fastest access via DMA. The signal into the DMA controller is ’Multiplier ready’. Please refer to the DMA user’s guide chapter for details. 9-20 32-Bit Hardware Multiplier 32-Bit Hardware Multiplier Registers 9.3 32-Bit Hardware Multiplier Registers The 32-bit hardware multiplier registers are listed in Table 9−7. Table 9−7. 32-bit Hardware Multiplier Registers Register 16-bit operand one − multiply 8-bit operand one − multiply 16-bit operand one − signed multiply 8-bit operand one − signed multiply 16-bit operand one − multiply accumulate 8-bit operand one − multiply accumulate 16-bit operand one − signed multiply accumulate 8-bit operand one − signed multiply accumulate 16-bit operand two 8-bit operand two 16x16-bit result low word 16x16-bit result high word 16x16-bit sum extension register 32-bit operand 1 − multiply − low word 32-bit operand 1 − multiply − high word 24-bit operand 1 − multiply − high byte 32-bit operand 1 − signed multiply − low word 32-bit operand 1 − signed multiply − high word 24-bit operand 1 − signed multiply − high byte 32-bit operand 1 − multiply accumulate − low word 32-bit operand 1 − multiply accumulate − high word 24-bit operand 1 − multiply accumulate − high byte 32-bit operand 1 − signed multiply accumulate − low word 32-bit operand 1 − signed multiply accumulate − high word 24-bit operand 1 − signed multiply accumulate − high byte 32-bit operand 2 − low word 32-bit operand 2 − high word 24-bit operand 2 − high byte 32x32-bit result 0 − least significant word 32x32-bit result 1 32x32-bit result 2 32x32-bit result 3 − most significant word MPY32 Control Register 0 Short Form Register Type MPY MPY_B Read/write Read/write MPYS Read/write MPYS_B Read/write MAC MAC_B MACS Read/write Read/write Read/write MACS_B Read/write OP2 Read/write OP2_B RESLO RESHI Read/write Read/write Read/write SUMEXT Read MPY32L Read/write MPY32H Read/write MPY32H_B MPYS32L MPYS32H Read/write Read/write Read/write MPYS32H_B Read/write MAC32L Read/write MAC32H Read/write MAC32H_B Read/write MACS32L Read/write MACS32H Read/write MACS32H_B Read/write OP2L OP2H OP2H_B RES0 RES1 RES2 RES3 MPY32CTL0 Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Address Initial State 0130h 0132h 0132h 0132h 0134h 0134h 0136h 0136h 0138h 0138h 013Ah 013Ch 013Eh 0140h 0142h 0142h 0144h 0146h 0146h 0148h 014Ah 014Ah 014Ch Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Undefined Undefined Undefined Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged 014Eh Unchanged 014Eh Unchanged 0150h 0152h 0152h 0154h 0156h 0158h 015Ah 015Ch Unchanged Unchanged Unchanged Undefined Undefined Undefined Undefined Undefined 32-Bit Hardware Multiplier 9-21 32-Bit Hardware Multiplier Registers The registers listed in Table 9−8 are treated equally. Table 9−8. Alternative Registers Register 16-bit operand one − multiply 8-bit operand one − multiply 16-bit operand one − signed multiply 8-bit operand one − signed multiply 16-bit operand one − multiply accumulate 8-bit operand one − multiply accumulate 16-bit operand one − signed multiply accumulate 8-bit operand one − signed multiply accumulate 16x16-bit result low word 16x16-bit result high word Alternative 1 MPY MPY_B MPYS MPYS_B MAC MAC_B MACS MACS_B RESLO RESHI Alternative 2 MPY32L MPYS32L_B MPYS32L MPYS32L_B MAC32L MAC32L_B MACS32L MACS32L_B RES0 RES1 9-22 32-Bit Hardware Multiplier MPY32CTL0, 32-bit Multiplier Control Register 0 15 14 13 12 11 Reserved r−0 r−0 r−0 r−0 r−0 32-Bit Hardware Multiplier Registers 10 9 8 r−0 r−0 r−0 7 MPY OP2_32 rw 6 MPY OP1_32 rw 5 4 MPYMx rw rw 3 MPYSAT rw−0 2 1 MPYFRAC Reserved rw−0 rw−0 0 MPYC rw Reserved MPY OP2_32 Bits 15−8 Bit 7 MPY OP1_32 Bit 6 MPYMx Bits 5-4 MPYSAT Bit 3 MPYFRAC Bit 2 Reserved MPYC Bit 1 Bit 0 Reserved Multiplier bit-width of operand 2 0 16 bits 1 32 bits Multiplier bit-width of operand 1. 0 16 bits 1 32 bits Multiplier mode 00 MPY − Multiply 01 MPYS − Signed multiply 10 MAC − Multiply accumulate 11 MACS − Signed multiply accumulate Saturation mode 0 Saturation mode disabled 1 Saturation mode enabled Fractional mode 0 Fractional mode disabled 1 Fractional mode enabled Reserved Carry of the multiplier. It can be considered as 33rd or 65th bit of the result if fractional or saturation mode is not selected because the MPYC bit does not change when switching to saturation or fractional mode. It is used to restore the SUMEXT content in MAC mode. 0 No carry for result 1 Result has a carry 32-Bit Hardware Multiplier 9-23 9-24 32-Bit Hardware Multiplier Chapter 10 DMA Controller The DMA controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller. One DMA channel is implemented in MSP430FG43x and three DMA channels are implemented in the MSP430FG461x and MSP430F471xx devices. Topic Page 10.1 DMA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.3 DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 DMA Controller 10-1 DMA Introduction 10.1 DMA Introduction The direct memory access (DMA) controller transfers data from one address to another, without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC12 conversion memory to RAM. Devices that contain a DMA controller may have one, two, or three DMA channels available. Therefore, depending on the number of DMA channels available, some features described in this chapter are not applicable to all devices. Using the DMA controller can increase the throughput of peripheral modules. It can also reduce system power consumption by allowing the CPU to remain in a low-power mode without having to awaken to move data to or from a peripheral. The DMA controller features include: - Up to three independent transfer channels - Configurable DMA channel priorities - Requires only two MCLK clock cycles per transfer - Byte or word and mixed byte/word transfer capability - Block sizes up to 65535 bytes or words - Configurable transfer trigger selections - Selectable edge or level-triggered transfer - Four addressing modes - Single, block, or burst-block transfer modes The DMA controller block diagram is shown in Figure 10−1. 10-2 DMA Controller Figure 10−1. DMA Controller Block Diagram DMA Introduction DMA0TSELx 4 DMAREQ 0000 Halt TACCR2_CCIFG 0001 TBCCR2_CCIFG 0010 Serial data received 0011 Serial transmit ready 0100 DAC12_0IFG 0101 ADC12IFGx 0110 TACCR0_CCIFG 0111 TBCCR0_CCIFG 1000 USART1 data received 1001 USART1 transmit ready 1010 Multiplier ready 1011 Serial data received 1100 Serial transmit ready 1101 DMA2IFG 1110 DMAE0 1111 DMA Priority And Control DMA1TSELx 4 DMAREQ TACCR2_CCIFG TBCCR2_CCIFG Serial data received Serial transmit ready DAC12_0IFG ADC12IFGx TACCR0_CCIFG TBCCR0_CCIFG USART1 data received USART1 transmit ready Multiplier ready Serial data received Serial transmit ready DMA0IFG DMAE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DMA2TSELx 4 DMAREQ TACCR2_CCIFG TBCCR2_CCIFG Serial data received Serial transmit ready DAC12_0IFG ADC12IFGx TACCR0_CCIFG TBCCR0_CCIFG USART1 data received USART1 transmit ready Multiplier ready Serial data received Serial transmit ready DMA1IFG DMAE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ROUNDROBIN JTAG Active NMI Interrupt Request ENNMI DMADSTINCRx DMADTx 2 DMADSTBYTE 3 DMA Channel 0 DMA0SA DT DMA0DA DMA0SZ 2 DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx 2 DMADSTBYTE 3 DMA Channel 1 DMA1SA DT DMA1DA DMA1SZ 2 DMASRSBYTE DMASRCINCRx DMAEN Address Space DMADSTINCRx DMADTx 2 DMADSTBYTE 3 DMA Channel 2 DMA2SA DT DMA2DA DMA2SZ 2 DMASRSBYTE DMASRCINCRx DMAEN DMAONFETCH Halt CPU DMA Controller 10-3 DMA Operation 10.2 DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 10.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable. For example, channel 0 may transfer between two fixed addresses, while channel 1 transfers between two blocks of addresses. The addressing modes are shown in Figure 10−2. The addressing modes are: - Fixed address to fixed address - Fixed address to block of addresses - Block of addresses to fixed address - Block of addresses to block of addresses The addressing modes are configured with the DMASRCINCRx and DMADSTINCRx control bits. The DMASRCINCRx bits select if the source address is incremented, decremented, or unchanged after each transfer. The DMADSTINCRx bits select if the destination address is incremented, decremented, or unchanged after each transfer. Transfers may be byte-to-byte, word-to-word, byte-to-word, or word-to-byte. When transferring word-to-byte, only the lower byte of the source-word transfers. When transferring byte-to-word, the upper byte of the destination-word is cleared when the transfer occurs. Figure 10−2. DMA Addressing Modes DMA Controller Address Space Fixed Address To Fixed Address DMA Controller Address Space Fixed Address To Block Of Addresses DMA Controller Address Space Block Of Addresses To Fixed Address 10-4 DMA Controller DMA Controller Address Space Block Of Addresses To Block Of Addresses DMA Operation 10.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 10−1. Each channel is individually configurable for its transfer mode. For example, channel 0 may be configured in single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates in repeated block mode. The transfer mode is configured independently from the addressing mode. Any addressing mode can be used with any transfer mode. Two types of data can be transferred selectable by the DMAxCTL DSTBYTE and SRCBYTE fields. The source and/or destination location can be either byte or word data. It is also possible to transfer byte to byte, word to word or any combination. Table 10−1. DMA Transfer Modes DMADTx Transfer Mode Description 000 Single transfer Each transfer requires a trigger. DMAEN is automatically cleared when DMAxSZ transfers have been made. 001 Block transfer A complete block is transferred with one trigger. DMAEN is automatically cleared at the end of the block transfer. 010, 011 Burst-block transfer CPU activity is interleaved with a block transfer. DMAEN is automatically cleared at the end of the burst-block transfer. 100 Repeated Each transfer requires a trigger. DMAEN remains single transfer enabled. 101 Repeated A complete block is transferred with one trigger. block transfer DMAEN remains enabled. 110, 111 Repeated burst-block transfer CPU activity is interleaved with a block transfer. DMAEN remains enabled. DMA Controller 10-5 DMA Operation Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state diagram is shown in Figure 10−3. The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer. The DMAxSZ register is decremented after each transfer. When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set. When DMADTx = 0, the DMAEN bit is cleared automatically when DMAxSZ decrements to zero and must be set again for another transfer to occur. In repeated single transfer mode, the DMA controller remains enabled with DMAEN = 1, and a transfer occurs every time a trigger occurs. 10-6 DMA Controller Figure 10−3. DMA Single Transfer State Diagram DMAEN = 0 Reset DMAEN = 0 DMAREQ = 0 T_Size → DMAxSZ DMAEN = 1 [ DMADTx = 0 AND DMAxSZ = 0] DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd OR DMAEN = 0 DMAABORT = 1 DMAEN = 0 Idle DMA Operation DMAABORT=0 DMAREQ = 0 Wait for Trigger DMAxSZ > 0 AND DMAEN = 1 2 x MCLK [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] [ENNMI = 1 AND NMI event] OR [DMALEVEL = 1 AND Trigger = 0] Hold CPU, Transfer one word/byte T_Size → DMAxSZ DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMADTx = 4 AND DMAxSZ = 0 AND DMAEN = 1 Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd DMA Controller 10-7 DMA Operation Block Transfers In block transfer mode, a transfer of a complete block of data occurs after one trigger. When DMADTx = 1, the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered. After a block transfer has been triggered, further trigger signals occurring during the block transfer are ignored. The block transfer state diagram is shown in Figure 10−4. The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer of the block. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block. The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block. When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set. During a block transfer, the CPU is halted until the complete block has been transferred. The block transfer takes 2 x MCLK x DMAxSZ clock cycles to complete. CPU execution resumes with its previous state after the block transfer is complete. In repeated block transfer mode, the DMAEN bit remains set after completion of the block transfer. The next trigger after the completion of a repeated block transfer triggers another block transfer. 10-8 DMA Controller Figure 10−4. DMA Block Transfer State Diagram DMAEN = 0 DMA Operation DMAEN = 0 DMAREQ = 0 T_Size → DMAxSZ Reset DMAEN = 1 DMAEN = 0 [DMADTx = 1 AND DMAxSZ = 0] OR DMAEN = 0 DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMAABORT = 1 Idle DMAABORT=0 DMAREQ = 0 T_Size → DMAxSZ DMAxSA → T_SourceAdd DMAxDA → T_DestAdd Wait for Trigger 2 x MCLK [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMADTx = 5 AND DMAxSZ = 0 AND DMAEN = 1 [ENNMI = 1 AND NMI event] OR [DMALEVEL = 1 AND Trigger = 0] Hold CPU, Transfer one word/byte Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd DMAxSZ > 0 DMA Controller 10-9 DMA Operation Burst-Block Transfers In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes 2 MCLK cycles after every four byte/word transfers of the block resulting in 20% CPU execution capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared. DMAEN must be set again before another burst-block transfer can be triggered. After a burst-block transfer has been triggered, further trigger signals occurring during the burst-block transfer are ignored. The burst-block transfer state diagram is shown in Figure 10−5. The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer of the block. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block. The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block. When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set. In repeated burst-block mode the DMAEN bit remains set after completion of the burst-block transfer and no further trigger signals are required to initiate another burst-block transfer. Another burst-block transfer begins immediately after completion of a burst-block transfer. In this case, the transfers must be stopped by clearing the DMAEN bit, or by an NMI interrupt when ENNMI is set. In repeated burst-block mode the CPU executes at 20% capacity continuously until the repeated burst-block transfer is stopped. 10-10 DMA Controller Figure 10−5. DMA Burst-Block Transfer State Diagram DMAEN = 0 DMAEN = 0 DMAREQ = 0 T_Size → DMAxSZ Reset DMAEN = 1 DMAEN = 0 [DMADTx = {2, 3} AND DMAxSZ = 0] OR DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMAEN = 0 DMAABORT = 1 Idle DMA Operation DMAABORT=0 Wait for Trigger 2 x MCLK [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] [ENNMI = 1 AND NMI event] OR [DMALEVEL = 1 AND Trigger = 0] Hold CPU, Transfer one word/byte Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd T_Size → DMAxSZ DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMAxSZ > 0 DMAxSZ > 0 AND a multiple of 4 words/bytes were transferred 2 x MCLK Burst State (release CPU for 2xMCLK) DMAxSZ > 0 [DMADTx = {6, 7} AND DMAxSZ = 0] DMA Controller 10-11 DMA Operation 10.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in Table 10−2.The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur. When selecting the trigger, the trigger must not have already occurred, or the transfer will not take place. For example, if the TACCR2 CCIFG bit is selected as a trigger, and it is already set, no transfer will occur until the next time the TACCR2 CCIFG bit is set. Edge-Sensitive Triggers When DMALEVEL = 0, edge-sensitive triggers are used and the rising edge of the trigger signal initiates the transfer. In single-transfer mode, each transfer requires its own trigger. When using block or burst-block modes, only one trigger is required to initiate the block or burst-block transfer. Level-Sensitive Triggers When DMALEVEL = 1, level-sensitive triggers are used. For proper operation, level-sensitive triggers can only be used when external trigger DMAE0 is selected as the trigger. DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set. The trigger signal must remain high for a block or burst-block transfer to complete. If the trigger signal goes low during a block or burst-block transfer, the DMA controller is held in its current state until the trigger goes back high or until the DMA registers are modified by software. If the DMA registers are not modified by software, when the trigger signal goes high again, the transfer resumes from where it was when the trigger signal went low. When DMALEVEL = 1, transfer modes selected when DMADTx = {0, 1, 2, 3} are recommended because the DMAEN bit is automatically reset after the configured transfer. Halting Executing Instructions for DMA Transfers The DMAONFETCH bit controls when the CPU is halted for a DMA transfer. When DMAONFETCH = 0, the CPU is halted immediately and the transfer begins when a trigger is received. When DMAONFETCH = 1, the CPU finishes the currently executing instruction before the DMA controller halts the CPU and the transfer begins. Note: DMAONFETCH Must Be Used When The DMA Writes To Flash If the DMA controller is used to write to flash memory, the DMAONFETCH bit must be set. Otherwise, unpredictable operation can result. 10-12 DMA Controller DMA Operation Table 10−2. DMA Trigger Operation DMAxTSELx Operation 0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer starts 0001 A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag is automatically reset when the transfer starts. If the TACCR2 CCIE bit is set, the TACCR2 CCIFG flag will not trigger a transfer. 0010 A transfer is triggered when the TBCCR2 CCIFG flag is set. The TBCCR2 CCIFG flag is automatically reset when the transfer starts. If the TBCCR2 CCIE bit is set, the TBCCR2 CCIFG flag will not trigger a transfer. 0011 Devices with USART0: A transfer is triggered when the URXIFG0 flag is set. URXIFG0 is automatically reset when the transfer starts. If URXIE0 is set, the URXIFG0 flag will not trigger a transfer. Devices with USCI_A0: A transfer is triggered when the UCA0RXIFG flag is set. UCA0RXIFG is automatically reset when the transfer starts. If UCA0RXIE is set, the UCA0RXIFG flag will not trigger a transfer. 0100 Devices with USART0: A transfer is triggered when the UTXIFG0 flag is set. UTXIFG0 is automatically reset when the transfer starts. If UTXIE0 is set, the UTXIFG0 flag will not trigger a transfer. Devices with USCI_A0: A transfer is triggered when the UCA0TXIFG flag is set. UCA0TXIFG is automatically reset when the transfer starts. If UCA0TXIE is set, the UCA0TXIFG flag will not trigger a transfer. 0101 Devices with DAC12: A transfer is triggered when the DAC12_0CTL DAC12IFG flag is set. The DAC12_0CTL DAC12IFG flag is automatically cleared when the transfer starts. If the DAC12_0CTL DAC12IE bit is set, the DAC12_0CTL DAC12IFG flag will not trigger a transfer. 0110 Devices with ADC12: A transfer is triggered by an ADC12IFGx flag. When single-channel conversions are performed, the corresponding ADC12IFGx is the trigger. When sequences are used, the ADC12IFGx for the last conversion in the sequence is the trigger. A transfer is triggered when the conversion is completed and the ADC12IFGx is set. Setting the ADC12IFGx with software will not trigger a transfer. All ADC12IFGx flags are automatically reset when the associated ADC12MEMx register is accessed by the DMA controller. Devices with SD16 or SD16_A: A transfer is triggered by the SD16IFG flag of the master channel in grouped mode or of channel 0. Setting the SD16IFG with software will not trigger a transfer. All SD16IFG flags are automatically reset when the associated SD16MEMx register is accessed by the DMA controller. If the SD16IE of the master channel is set, the SD16IFG will not trigger a transfer. 0111 A transfer is triggered when the TACCR0 CCIFG flag is set. The TACCR0 CCIFG flag is automatically reset when the transfer starts. If the TACCR0 CCIE bit is set, the TACCR0 CCIFG flag will not trigger a transfer. 1000 A transfer is triggered when the TBCCR0 CCIFG flag is set. The TBCCR0 CCIFG flag is automatically reset when the transfer starts. If the TBCCR0 CCIE bit is set, the TBCCR0 CCIFG flag will not trigger a transfer. 1001 Devices with USART1: A transfer is triggered when the URXIFG1 flag is set. URXIFG1 is automatically reset when the transfer starts. If URXIE1 is set, the URXIFG1 flag will not trigger a transfer. Devices with USCI_A1: A transfer is triggered when the UCA1RXIFG flag is set. UCA1RXIFG is automatically reset when the transfer starts. If UCA1RXIE is set, the UCA1RXIFG flag will not trigger a transfer. DMA Controller 10-13 DMA Operation Table 10−2. DMA Trigger Operation (Continued) DMAxTSELx Operation 1010 Devices with USART1: A transfer is triggered when the UTXIFG1 flag is set. UTXIFG1 is automatically reset when the transfer starts. If UTXIE1 is set, the UTXIFG1 flag will not trigger a transfer. Devices with USCI_A1: A transfer is triggered when the UCA1TXIFG flag is set. UCA1TXIFG is automatically reset when the transfer starts. If UCA1TXIE is set, the UCA1TXIFG flag will not trigger a transfer. 1011 A transfer is triggered when the hardware multiplier is ready for a new operand. 1100 A transfer is triggered when the UCB0RXIFG flag is set. UCB0RXIFG is automatically reset when the transfer starts. If UCB0RXIE is set, the UCB0RXIFG flag will not trigger a transfer. 1101 A transfer is triggered when the UCB0TXIFG flag is set. UCB0TXIFG is automatically reset when the transfer starts. If UCB0TXIE is set, the UCB0TXIFG flag will not trigger a transfer. 1110 A transfer is triggered when the DMAxIFG flag is set. DMA0IFG triggers channel 1, DMA1IFG triggers channel 2, and DMA2IFG triggers channel 0. None of the DMAxIFG flags are automatically reset when the transfer starts. 1111 A transfer is triggered by the external trigger DMAE0. 10-14 DMA Controller DMA Operation 10.2.4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress: - A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in register DMACTL1. - A burst-block transfer may be stopped by clearing the DMAEN bit. 10.2.5 DMA Channel Priorities The default DMA channel priorities are DMA0−DMA1−DMA2. If two or three triggers happen simultaneously or are pending, the channel with the highest priority completes its transfer (single, block or burst-block transfer) first, then the second priority channel, then the third priority channel. Transfers in progress are not halted if a higher priority channel is triggered. The higher priority channel waits until the transfer in progress completes before starting. The DMA channel priorities are configurable with the ROUNDROBIN bit. When the ROUNDROBIN bit is set, the channel that completes a transfer becomes the lowest priority. The order of the priority of the channels always stays the same, DMA0−DMA1−DMA2, for example: DMA Priority DMA0 − DMA1 − DMA2 DMA2 − DMA0 − DMA1 DMA0 − DMA1 − DMA2 Transfer Occurs DMA1 DMA2 DMA0 New DMA Priority DMA2 − DMA0 − DMA1 DMA0 − DMA1 − DMA2 DMA1 − DMA2 − DMA0 When the ROUNDROBIN bit is cleared the channel priority returns to the default priority. DMA channel priorities are not applicable to MSP430FG43x devices. DMA Controller 10-15 DMA Operation 10.2.6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after synchronization, and one cycle of wait time after the transfer. Because the DMA controller uses MCLK, the DMA cycle time is dependent on the MSP430 operating mode and clock system setup. If the MCLK source is active, but the CPU is off, the DMA controller will use the MCLK source for each transfer, without re-enabling the CPU. If the MCLK source is off, the DMA controller will temporarily restart MCLK, sourced with DCOCLK, for the single transfer or complete block or burst-block transfer. The CPU remains off, and after the transfer completes, MCLK is turned off. The maximum DMA cycle time for all operating modes is shown in Table 10−3. Table 10−3. Maximum Single-Transfer DMA Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time Active mode MCLK=DCOCLK 4 MCLK cycles Active mode MCLK=LFXT1CLK 4 MCLK cycles Low-power mode LPM0/1 MCLK=DCOCLK 5 MCLK cycles Low-power mode LPM3/4 MCLK=DCOCLK 5 MCLK cycles + 6 μs† Low-power mode LPM0/1 MCLK=LFXT1CLK 5 MCLK cycles Low-power mode LPM3 MCLK=LFXT1CLK 5 MCLK cycles Low-power mode LPM4 MCLK=LFXT1CLK 5 MCLK cycles + 6 μs† † The additional 6 μs are needed to start the DCOCLK. It is the t(LPMx) parameter in the data sheet. 10-16 DMA Controller DMA Operation 10.2.7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the completion of the transfer. NMI interrupts can interrupt the DMA controller if the ENNMI bit is set. System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine or other routine must execute with no interruptions, the DMA controller should be disabled prior to executing the routine. 10.2.8 DMA Controller Interrupts Each DMA channel has its own DMAIFG flag. Each DMAIFG flag is set in any mode when the corresponding DMAxSZ register counts to zero. If the corresponding DMAIE and GIE bits are set, an interrupt request is generated. All DMAIFG flags source only one DMA controller interrupt vector and the interrupt vector may be shared with the other modules. See the device-specific datasheet for specific interrupt assignments. In this case, software must check the DMAIFG and other flags to determine the source of the interrupt. The DMAIFG flags are not reset automatically and must be reset by software. 10.2.9 DMAIV, DMA Interrupt Vector Generator MSP430FG461x and MSP430F471xx devices implement the interrupt vector register DMAIV. In this case, all DMAIFG flags are prioritized and combined to source a single interrupt vector. The interrupt vector register DMAIV is used to determine which flag requested an interrupt. The highest priority enabled interrupt generates a number in the DMAIV register (see register description). This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled DMA interrupts do not affect the DMAIV value. Any access, read or write, of the DMAIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. For example, If the DMA0IFG and DMA2IFG flags are set when the interrupt service routine accesses the DMAIV register, DMA0IFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the DMA2IFG will generate another interrupt. DMA Controller 10-17 DMA Operation DMAIV Software Example The following software example shows the recommended use of DMAIV and the handling overhead. The DMAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. ;Interrupt handler for DMA0IFG, DMA1IFG, DMA2IFG Cycles DMA_HND ... ; Interrupt latency 6 ADD &DMAIV,PC ; Add offset to Jump table 3 RETI 5 ; Vector 0: No interrupt JMP DMA0_HND ; Vector 2: DMA channel 0 2 JMP DMA1_HND ; Vector 4: DMA channel 1 2 JMP DMA2_HND ; Vector 6: DMA channel 2 2 RETI ; Vector 8: Reserved 5 RETI ; Vector 10: Reserved 5 RETI ; Vector 12: Reserved 5 RETI ; Vector 14: Reserved 5 DMA2_HND ... RETI ; Vector 6: DMA channel 2 ; Task starts here ; Back to main program 5 DMA1_HND ... RETI ; Vector 4: DMA channel 1 ; Task starts here ; Back to main program 5 DMA0_HND ... RETI ; Vector 2: DMA channel 0 ; Task starts here ; Back to main program 5 10-18 DMA Controller DMA Operation 10.2.10 Using the USCI_B I2C Module with the DMA Controller The USCI_B I2C module provides two trigger sources for the DMA controller. The USCI_B I2C module can trigger a transfer when new I2C data is received and when data is needed for transmit. A transfer is triggered if UCB0RXIFG is set. The UCB0RXIFG is cleared automatically when the DMA controller acknowledges the transfer. If UCB0RXIE is set, UCB0RXIFG will not trigger a transfer. A transfer is triggered if UCB0TXIFG is set. The UCB0TXIFG is cleared automatically when the DMA controller acknowledges the transfer. If UCB0TXIE is set, UCB0TXIFG will not trigger a transfer. 10.2.11 Using ADC12 with the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from any ADC12MEMx register to another location. DMA transfers are done without CPU intervention and independently of any low-power modes. The DMA controller increases throughput of the ADC12 module, and enhances low-power applications allowing the CPU to remain off while data transfers occur. DMA transfers can be triggered from any ADC12IFGx flag. When CONSEQx = {0,2} the ADC12IFGx flag for the ADC12MEMx used for the conversion can trigger a DMA transfer. When CONSEQx = {1,3}, the ADC12IFGx flag for the last ADC12MEMx in the sequence can trigger a DMA transfer. Any ADC12IFGx flag is automatically cleared when the DMA controller accesses the corresponding ADC12MEMx. 10.2.12 Using DAC12 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the DAC12_xDAT register. DMA transfers are done without CPU intervention and independently of any low-power modes. The DMA controller increases throughput to the DAC12 module, and enhances low-power applications allowing the CPU to remain off while data transfers occur. Applications requiring periodic waveform generation can benefit from using the DMA controller with the DAC12. For example, an application that produces a sinusoidal waveform may store the sinusoid values in a table. The DMA controller can continuously and automatically transfer the values to the DAC12 at specific intervals creating the sinusoid with zero CPU execution. The DAC12_xCTL DAC12IFG flag is automatically cleared when the DMA controller accesses the DAC12_xDAT register. DMA Controller 10-19 DMA Operation 10.2.13 Using SD16 or SD16_A With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from any SD16MEMx register to another location. DMA transfers are done without CPU intervention and independently of any low-power modes. The DMA controller increases throughput of the SD16 or SD16_A module, and enhances low-power applications allowing the CPU to remain off while data transfers occur. In Grouped mode DMA transfers can be triggered by the master channel that controls the group (i.e. the channel with the lowest channel number and SD16GRP = 0). Otherwise channel 0 can trigger DMA transfers. Any SD16IFG is automatically cleared when the DMA controller accesses the corresponding SD16MEMx register. 10.2.14 Writing to Flash With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the Flash memory. DMA transfers are done without CPU intervention and independent of any low-power modes. The DMA controller performs the move of the data word/byte to the Flash. The write timing control is done by the Flash controller. Write transfers to the Flash memory succeed if the Flash controller set−up is prior to the DMA transfer and if the Flash is not busy. 10-20 DMA Controller DMA Registers 10.3 DMA Registers The DMA registers for MSP430FG43x devices are listed in Table 10−4. The DMA registers for MSP430FG461x and MSP430F471xx devices are listed in Table 10−5. Table 10−4. DMA Registers, MSP430FG43x devices Register DMA control 0 DMA control 1 DMA channel 0 control DMA channel 0 source address DMA channel 0 destination address DMA channel 0 transfer size DMA channel 1 control DMA channel 1 source address DMA channel 1 destination address DMA channel 1 transfer size DMA channel 2 control DMA channel 2 source address DMA channel 2 destination address DMA channel 2 transfer size Short Form DMACTL0 DMACTL1 DMA0CTL DMA0SA DMA0DA DMA0SZ DMA1CTL DMA1SA DMA1DA DMA1SZ DMA2CTL DMA2SA DMA2DA DMA2SZ Register Type Address Read/write 0122h Read/write 0124h Read/write 01E0h Read/write 01E2h Read/write 01E4h Read/write 01E6h Read/write 01E8h Read/write 01EAh Read/write 01ECh Read/write 01EEh Read/write 01F0h Read/write 01F2h Read/write 01F4h Read/write 01F6h Initial State Reset with POR Reset with POR Reset with POR Unchanged Unchanged Unchanged Reset with POR Unchanged Unchanged Unchanged Reset with POR Unchanged Unchanged Unchanged Table 10−5. DMA Registers, MSP430FG461x, MSP430F471xx devices Register DMA control 0 DMA control 1 DMA interrupt vector DMA channel 0 control DMA channel 0 source address DMA channel 0 destination address DMA channel 0 transfer size DMA channel 1 control DMA channel 1 source address DMA channel 1 destination address DMA channel 1 transfer size DMA channel 2 control DMA channel 2 source address DMA channel 2 destination address DMA−channel 2 transfer size Short Form DMACTL0 DMACTL1 DMAIV DMA0CTL DMA0SA DMA0DA DMA0SZ DMA1CTL DMA1SA DMA1DA DMA1SZ DMA2CTL DMA2SA DMA2DA DMA2SZ Register Type Address Read/write 0122h Read/write 0124h Read only 0126h Read/write 01D0h Read/write 01D2h Read/write 01D6h Read/write 01DAh Read/write 01DCh Read/write 01DEh Read/write 01E2h Read/write 01E6h Read/write 01E8h Read/write 01EAh Read/write 01EEh Read/write 01F2h Initial State Reset with POR Reset with POR Reset with POR Reset with POR Unchanged Unchanged Unchanged Reset with POR Unchanged Unchanged Unchanged Reset with POR Unchanged Unchanged Unchanged DMA Controller 10-21 DMA Registers DMACTL0, DMA Control Register 0 15 rw−(0) 14 13 Reserved rw−(0) rw−(0) 12 rw−(0) 11 rw−(0) 10 9 DMA2TSELx rw−(0) rw−(0) 8 rw−(0) 7 rw−(0) 6 5 DMA1TSELx rw−(0) rw−(0) 4 rw−(0) 3 rw−(0) 2 1 DMA0TSELx rw−(0) rw−(0) 0 rw−(0) Reserved DMA2 TSELx DMA1 TSELx DMA0 TSELx Bits 15−12 Bits 11−8 Bits 7−4 Bits 3–0 Reserved DMA trigger select. These bits select the DMA transfer trigger. The trigger selection is device-specific. For MSP430FG43x and MSP430FG461x devices it is given below; for other devices, see the device-specific data sheet. 0000 DMAREQ bit (software trigger) 0001 TACCR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 URXIFG0 (MSP430FG43x), UCA0RXIFG (MPS430FG461x) 0100 UTXIFG0 (MSP430FG43x), UCA0TXIFG (MSP430FG461x) 0101 DAC12_0CTL DAC12IFG bit 0110 ADC12 ADC12IFGx bit 0111 TACCR0 CCIFG bit 1000 TBCCR0 CCIFG bit 1001 URXIFG1 bit 1010 UTXIFG1 bit 1011 Multiplier ready 1100 No action (MSP430FG43x), UCB0RXIFG (MSP430FG461x) 1101 No action (MSP430FG43x), UCB0TXIFG (MSP430FG461x) 1110 DMA0IFG bit triggers DMA channel 1 DMA1IFG bit triggers DMA channel 2 DMA2IFG bit triggers DMA channel 0 1111 External trigger DMAE0 Same as DMA2TSELx Same as DMA2TSELx 10-22 DMA Controller DMACTL1, DMA Control Register 1 DMA Registers 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 0 DMA ONFETCH ROUND ROBIN ENNMI r0 r0 r0 r0 r0 rw−(0) rw−(0) rw−(0) Reserved DMA ONFETCH Bits 15−3 Bit 2 ROUND ROBIN Bit 1 ENNMI Bit 0 Reserved. Read only. Always read as 0. DMA on fetch 0 The DMA transfer occurs immediately 1 The DMA transfer occurs on next instruction fetch after the trigger Round robin. This bit enables the round-robin DMA channel priorities. 0 DMA channel priority is DMA0 − DMA1 − DMA2 1 DMA channel priority changes with each transfer Enable NMI. This bit enables the interruption of a DMA transfer by an NMI interrupt. When an NMI interrupts a DMA transfer, the current transfer is completed normally, further transfers are stopped, and DMAABORT is set. 0 NMI interrupt does not interrupt DMA transfer 1 NMI interrupt interrupts a DMA transfer DMA Controller 10-23 DMA Registers DMAxCTL, DMA Channel x Control Register 15 Reserved rw−(0) 14 rw−(0) 13 DMADTx rw−(0) 12 rw−(0) 11 10 DMADSTINCRx rw−(0) rw−(0) 9 8 DMASRCINCRx rw−(0) rw−(0) 7 DMA DSTBYTE rw−(0) 6 DMA SRCBYTE 5 DMALEVEL rw−(0) rw−(0) 4 DMAEN rw−(0) 3 DMAIFG rw−(0) 2 DMAIE rw−(0) 1 DMA ABORT rw−(0) 0 DMAREQ rw−(0) Reserved Bit 15 Reserved DMADTx Bits 14−12 DMA Transfer mode. 000 Single transfer 001 Block transfer 010 Burst-block transfer 011 Burst-block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst-block transfer 111 Repeated burst-block transfer DMA DSTINCRx Bits 11−10 DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer. When DMADSTBYTE=1, the destination address increments/decrements by one. When DMADSTBYTE=0, the destination address increments/decrements by two. The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented. DMAxDA is not incremented or decremented. 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented DMA Bits SRCINCRx 9−8 DMA source increment. This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer. When DMASRCBYTE=1, the source address increments/decrements by one. When DMASRCBYTE=0, the source address increments/decrements by two. The DMAxSA is copied into a temporary register and the temporary register is incremented or decremented. DMAxSA is not incremented or decremented. 00 Source address is unchanged 01 Source address is unchanged 10 Source address is decremented 11 Source address is incremented DMA Bit 7 DSTBYTE DMA destination byte. This bit selects the destination as a byte or word. 0 Word 1 Byte 10-24 DMA Controller DMA Registers DMA Bit 6 SRCBYTE DMA LEVEL Bit 5 DMAEN Bit 4 DMAIFG Bit 3 DMAIE Bit 2 DMA ABORT Bit 1 DMAREQ Bit 0 DMA source byte. This bit selects the source as a byte or word. 0 Word 1 Byte DMA level. This bit selects between edge-sensitive and level-sensitive triggers. 0 Edge sensitive (rising edge) 1 Level sensitive (high level) DMA enable 0 Disabled 1 Enabled DMA interrupt flag 0 No interrupt pending 1 Interrupt pending DMA interrupt enable 0 Disabled 1 Enabled DMA Abort. This bit indicates if a DMA transfer was interrupt by an NMI. 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0 No DMA start 1 Start DMA DMA Controller 10-25 DMA Registers DMAxSA, DMA Source Address Register 31 30 29 28 27 26 25 824 Reserved r0 r0 r0 r0 r0 r0 r0 r0 23 22 21 20 19 18 17 16 Reserved DMAxSAx r0 r0 r0 r0 rw rw rw rw 15 14 13 12 11 10 9 8 DMAxSAx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxSAx rw rw rw rw rw rw rw rw Reserved Bits Reserved 31−20 DMAxSAx Bits 19−0 DMA source address. The source address register points to the DMA source address for single transfers or the first source address for block transfers. The source address register remains unchanged during block and burst-block transfers. Devices that have addressable memory range 64−KB or below contain a single word for the DMAxSA. MSP430FG461x and MSP430F471xx devices implement two words for the DMAxSA register as shown. Bits 31−20 are reserved and always read as zero. Reading or writing bits 19-16 requires the use of extended instructions. When writing to DMAxSA with word instructions, bits 19-16 are cleared. 10-26 DMA Controller DMAxDA, DMA Destination Address Register DMA Registers 31 30 29 28 27 26 25 824 Reserved r0 r0 r0 r0 r0 r0 r0 r0 23 22 21 20 19 18 17 16 Reserved DMAxDAx r0 r0 r0 r0 rw rw rw rw 15 14 13 12 11 10 9 8 DMAxDAx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxDAx rw rw rw rw rw rw rw rw Reserved Bits Reserved 31−20 DMAxDAx Bits 19−0 DMA destination address. The destination address register points to the destination address for single transfers or the first address for block transfers. The DMAxDA register remains unchanged during block and burst-block transfers. Devices that have addressable memory range 64−KB or below contain a single word for the DMAxDA. MSP430FG461x and MSP430F471xx devices implement two words for the DMAxDA register as shown. Bits 31−20 are reserved and always read as zero. Reading or writing bits 19-16 requires the use of extended instructions. When writing to DMAxDA with word instructions, bits 19-16 are cleared. DMA Controller 10-27 DMA Registers DMAxSZ, DMA Size Address Register 15 14 13 12 11 10 9 8 DMAxSZx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxSZx rw rw rw rw rw rw rw rw DMAxSZx Bits 15−0 DMA size. The DMA size register defines the number of byte/word data per block transfer. DMAxSZ register decrements with each word or byte transfer. When DMAxSZ decrements to 0, it is immediately and automatically reloaded with its previously initialized value. 00000h Transfer is disabled 00001h One byte or word to be transferred 00002h Two bytes or words have to be transferred : 0FFFFh 65535 bytes or words have to be transferred 10-28 DMA Controller DMAIV, DMA Interrupt Vector Register DMA Registers 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 DMAIVx 0 r0 r0 r0 r0 r−(0) r−(0) r−(0) r0 DMAIVx Bits 15-0 DMA Interrupt Vector value DMAIV Contents 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh Interrupt Source No interrupt pending DMA channel 0 DMA channel 1 DMA channel 2 Reserved Reserved Reserved Reserved Interrupt Flag − DMA0IFG DMA1IFG DMA2IFG − − − − Interrupt Priority Highest Lowest DMA Controller 10-29 10-30 DMA Controller Chapter 11 Digital I/O This chapter describes the operation of the digital I/O ports. Topic Page 11.1 Digital I/O Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 Digital I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3 Digital I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Digital I/O 11-1 Digital I/O Introduction 11.1 Digital I/O Introduction MSP430 devices have up to ten digital I/O ports implemented, P1 to P10. Each port has eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read from or written to. Ports P1 and P2 have interrupt capability. Each interrupt for the P1 and P2 I/O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal. All P1 I/O lines source a single interrupt vector, and all P2 I/O lines source a different, single interrupt vector. The digital I/O features include: - Independently programmable individual I/Os - Any combination of input or output - Individually configurable P1 and P2 interrupts - Independent input and output data registers 11-2 Digital I/O Digital I/O Operation 11.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of the digital I/O is described in the following sections. Each port register is an 8-bit register and is accessed with byte instructions. Registers for P7/P8 and P9/P10 are arranged such that the two ports can be addressed at once as a 16-bit port. The P7/P8 combination is referred to as PA and the P9/P10 combination is referred to as PB in the standard definitions file. For example, to write to P7SEL and P8SEL simultaneously, a word write to PASEL would be used. Some examples of accessing these ports follow: BIS.B #01h,&P7OUT MOV.W #05555h,&PAOUT CLR.B &P9SEL MOV.W &PBIN,&0200h ; Set LSB of P7OUT. ; P8OUT is unchanged ; P7OUT and P8OUT written ; simultaneously ; Clear P9SEL, P10SEL is unchanged ; P9IN and P10IN read simultaneously ; as 16-bit port. 11.2.1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at the corresponding I/O pin when the pin is configured as I/O function. Bit = 0: The input is low Bit = 1: The input is high Note: Writing to Read-Only Registers PxIN Writing to these read-only registers results in increased current consumption while the write attempt is active. 11.2.2 Output Registers PxOUT Each bit in each PxOUT register is the value to be output on the corresponding I/O pin when the pin is configured as I/O function and output direction. Bit = 0: The output is low Bit = 1: The output is high 11.2.3 Direction Registers PxDIR Each bit in each PxDIR register selects the direction of the corresponding I/O pin, regardless of the selected function for the pin. PxDIR bits for I/O pins that are selected for other module functions must be set as required by the other function. Bit = 0: The port pin is switched to input direction Bit = 1: The port pin is switched to output direction Digital I/O 11-3 Digital I/O Operation 11.2.4 Pullup/Pulldown Resistor Enable Registers PxREN (MSP430F47x3/4 and MSP430F471xx only) In MSP430F47x3/4 and MSP430F471xx devices all port pins have a programmable pullup/pulldown resistor. Each bit in each PxREN register enables or disables the pullup/pulldown resistor of the corresponding I/O pin. The corresponding bit in the PxOUT register selects if the pin is pulled up or pulled down. Bit = 0: Pullup/pulldown resistor disabled Bit = 1: Pullup/pulldown resistor enabled 11.2.5 Function Select Registers PxSEL Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet to determine pin functions. Each PxSEL bit is used to select the pin function — I/O port or peripheral module function. Bit = 0: I/O function is selected for the pin Bit = 1: Peripheral module function is selected for the pin Setting PxSELx = 1 does not automatically set the pin direction. Other peripheral module functions may require the PxDIRx bits to be configured according to the direction needed for the module function. See the pin schematics in the device-specific data sheet. ;Output ACLK on P1.5 on MSP430F41x BIS.B #020h,&P1SEL ; Select ACLK function for pin BIS.B #020h,&P1DIR ; Set direction to output *Required* Note: P1 and P2 Interrupts Are Disabled When PxSEL = 1 When any P1SELx or P2SELx bit is set, the corresponding pin’s interrupt function is disabled. Therefore, signals on these pins do not generate P1 or P2 interrupts, regardless of the state of the corresponding P1IE or P2IE bit. When a port pin is selected as an input to a peripheral, the input signal to the peripheral is a latched representation of the signal at the device pin. While PxSELx = 1, the internal input signal follows the signal at the pin. However, if the PxSELx = 0, the input to the peripheral maintains the value of the input signal at the device pin before the PxSELx bit was reset. 11-4 Digital I/O Digital I/O Operation 11.2.6 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector, and all P2 pins source a different single interrupt vector. The PxIFG register can be tested to determine the source of a P1 or P2 interrupt. Interrupt Flag Registers P1IFG, P2IFG Each PxIFGx bit is the interrupt flag for its corresponding I/O pin and is set when the selected input signal edge occurs at the pin. All PxIFGx interrupt flags request an interrupt when their corresponding PxIE bit and the GIE bit are set. Each PxIFG flag must be reset with software. Software can also set each PxIFG flag, providing a way to generate a software-initiated interrupt. Bit = 0: No interrupt is pending Bit = 1: An interrupt is pending Only transitions, not static levels, cause interrupts. If any PxIFGx flag becomes set during a Px interrupt service routine or is set after the RETI instruction of a Px interrupt service routine is executed, the set PxIFGx flag generates another interrupt. This ensures that each transition is acknowledged. Note: PxIFG Flags When Changing PxOUT or PxDIR Writing to P1OUT, P1DIR, P2OUT, or P2DIR can result in setting the corresponding P1IFG or P2IFG flags. Note: Length of I/O Pin Interrupt Event Any external interrupt event should be at least 1.5 times MCLK or longer, to ensure that it is accepted and the corresponding interrupt flag is set. Digital I/O 11-5 Digital I/O Operation Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin. Bit = 0: The PxIFGx flag is set with a low-to-high transition Bit = 1: The PxIFGx flag is set with a high-to-low transition Note: Writing to PxIESx Writing to P1IES or P2IES can result in setting the corresponding interrupt flags. PxIESx 0→1 0→1 1→0 1→0 PxINx 0 1 0 1 PxIFGx May be set Unchanged Unchanged May be set Interrupt Enable P1IE, P2IE Each PxIE bit enables the associated PxIFG interrupt flag. Bit = 0: The interrupt is disabled Bit = 1: The interrupt is enabled 11.2.7 Configuring Unused Port Pins Unused I/O pins should be configured as I/O function, output direction, and left unconnected on the PC board, to reduce power consumption. The value of the PxOUT bit is don’t care, because the pin is unconnected. See chapter System Resets, Interrupts, and Operating Modes for termination of unused pins. 11-6 Digital I/O Digital I/O Registers 11.3 Digital I/O Registers The digital I/O registers are listed in Table 11−1 and Table 11−2. Table 11−1. Digital I/O Registers, P1-P6 Port P1 P2 P3 P4 P5 P6 Note: Register Short Form Address Register Type Initial State Input P1IN 020h Read only − Output P1OUT 021h Read/write Unchanged Direction P1DIR 022h Read/write Reset with PUC Interrupt Flag P1IFG 023h Read/write Reset with PUC Interrupt Edge Select P1IES 024h Read/write Unchanged Interrupt Enable P1IE 025h Read/write Reset with PUC Port Select P1SEL 026h Read/write Reset with PUC Resistor Enable P1REN 027h Read/write Reset with PUC Input P2IN 028h Read only − Output P2OUT 029h Read/write Unchanged Direction P2DIR 02Ah Read/write Reset with PUC Interrupt Flag P2IFG 02Bh Read/write Reset with PUC Interrupt Edge Select P2IES 02Ch Read/write Unchanged Interrupt Enable P2IE 02Dh Read/write Reset with PUC Port Select P2SEL 02Eh Read/write 0C0h with PUC Resistor Enable P2REN 02Fh Read/write Reset with PUC Input P3IN 018h Read only − Output P3OUT 019h Read/write Unchanged Direction P3DIR 01Ah Read/write Reset with PUC Port Select P3SEL 01Bh Read/write Reset with PUC Resistor Enable P3REN 010h Read/write Reset with PUC Input P4IN 01Ch Read only − Output P4OUT 01Dh Read/write Unchanged Direction P4DIR 01Eh Read/write Reset with PUC Port Select P4SEL 01Fh Read/write Reset with PUC Resistor Enable P4REN 011h Read/write Reset with PUC Input P5IN 030h Read only − Output P5OUT 031h Read/write Unchanged Direction P5DIR 032h Read/write Reset with PUC Port Select P5SEL 033h Read/write Reset with PUC Resistor Enable P5REN 012h Read/write Reset with PUC Input P6IN 034h Read only − Output P6OUT 035h Read/write Unchanged Direction P6DIR 036h Read/write Reset with PUC Port Select P6SEL 037h Read/write Reset with PUC Resistor Enable P6REN 013h Read/write Reset with PUC Resistor enable registers RxREN only available in MSP430F47x3/4 and MSP430F471xx devices. Digital I/O 11-7 Digital I/O Registers Table 11−2. Digital I/O Registers, P7-P10 Port Register Short Form Address Register Type Initial State P7 Input PA Output P7IN P7OUT 038h 03Ah Read only Read/write − Unchanged Direction P7DIR 03Ch Read/write Reset with PUC Port Select P7SEL 03Eh Read/write Reset with PUC Resistor Enable P7REN 014h Read/write Reset with PUC P8 Input P8IN 039h Read only − Output P8OUT 03Bh Read/write Unchanged Direction P8DIR 03Dh Read/write Reset with PUC Port Select P8SEL 03Fh Read/write Reset with PUC Resistor Enable P8REN 015h Read/write Reset with PUC P9 Input PB Output P9IN P9OUT 008h 00Ah Read only Read/write − Unchanged Direction P9DIR 00Ch Read/write Reset with PUC Port Select P9SEL 00Eh Read/write Reset with PUC Resistor Enable P9REN 016h Read/write Reset with PUC P10 Input P10IN 009h Read only − Output P10OUT 00Bh Read/write Unchanged Direction P10DIR 00Dh Read/write Reset with PUC Port Select P10SEL 00Fh Read/write Reset with PUC Resistor Enable P10REN 017h Read/write Reset with PUC Note: Resistor enable registers RxREN only available in MSP430F47x3/4 and MSP430F471xx devices. 11-8 Digital I/O Chapter 12 Watchdog Timer, Watchdog Timer+ The watchdog timer is a 16-bit timer that can be used as a watchdog or as an interval timer. This chapter describes the watchdog timer. The watchdog timer is implemented in all MSP430x4xx devices, except those with the enhanced watchdog timer, WDT+. The WDT+ is implemented in the MSP430F41x2, MSP430F42x, MSP430F42xA, MSP430FE42x, MSP430FE42xA, MSP430FG461x, MSP430F47x, MSP430FG47x, MSP430F47x3/4, and MSP430F471xx devices. Topic Page 12.1 Watchdog Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3 Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 Watchdog Timer, Watchdog Timer+ 12-1 Watchdog Timer Introduction 12.1 Watchdog Timer Introduction The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. Features of the watchdog timer module include: - Four software-selectable time intervals - Watchdog mode - Interval mode - Access to WDT control register is password protected - Control of RST/NMI pin function - Selectable clock source - Can be stopped to conserve power - Clock fail-safe feature in WDT+ The WDT block diagram is shown in Figure 12−1. Note: Watchdog Timer Powers Up Active After a PUC, the WDT module is automatically configured in the watchdog mode with an initial 32768 clock cycle reset interval using the DCOCLK. The user must setup or halt the WDT prior to the expiration of the initial reset interval. 12-2 Watchdog Timer, Watchdog Timer+ Figure 12−1. Watchdog Timer Block Diagram Watchdog Timer Introduction Int. Flag WDTQn Y Pulse Generator A B PUC MCLK† Q6 4 0 Q9 3 1 Q13 2 0 Q15 1 16−bit 1 Counter 1 0 Clear 1 (Asyn) CLK 0 Fail-Safe Logic† EQU WDTCTL MSB MDB Password Compare 16−bit EQU Write Enable Low Byte R/W SMCLK ACLK 1 1 A EN WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTIS1 WDTIS0 LSB Clock Request Logic† † MSP430x42x, MSP430FE42x, MSP430FG461x, and MSP430F47x devices only MCLK Active SMCLK Active ACLK Active Watchdog Timer, Watchdog Timer+ 12-3 Watchdog Timer Operation 12.2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer with the WDTCTL register. The WDTCTL register also contains control bits to configure the RST/NMI pin. WDTCTL is a 16-bit password-protected read/write register. Any read or write access must use word instructions and write accesses must include the write password 05Ah in the upper byte. Any write to WDTCTL with any value other than 05Ah in the upper byte is a security key violation and triggers a PUC system reset regardless of timer mode. Any read of WDTCTL reads 069h in the upper byte. The WDT+ counter clock should be slower than or equal to the system (MCLK) frequency. 12.2.1 Watchdog Timer Counter The watchdog timer counter (WDTCNT) is a 16-bit up-counter that is not directly accessible by software. The WDTCNT is controlled and time intervals selected through the watchdog timer control register WDTCTL. The WDTCNT can be sourced from ACLK or SMCLK. The clock source is selected with the WDTSSEL bit. 12.2.2 Watchdog Mode After a PUC condition, the WDT module is configured in the watchdog mode with an initial 32768 cycle reset interval using the DCOCLK. The user must setup, halt, or clear the WDT prior to the expiration of the initial reset interval, or another PUC is generated. When the WDT is configured to operate in watchdog mode, either writing to WDTCTL with an incorrect password or expiration of the selected time interval triggers a PUC. A PUC resets the WDT to its default condition and configures the RST/NMI pin to reset mode. 12.2.3 Interval Timer Mode Setting the WDTTMSEL bit to 1 selects the interval timer mode. This mode can be used to provide periodic interrupts. In interval timer mode, the WDTIFG flag is set at the expiration of the selected time interval. A PUC is not generated in interval timer mode at expiration of the selected timer interval and the WDTIFG enable bit WDTIE remains unchanged. When the WDTIE bit and the GIE bit are set, the WDTIFG flag requests an interrupt. The WDTIFG interrupt flag is automatically reset when its interrupt request is serviced, or may be reset by software. The interrupt vector address in interval timer mode is different from that in watchdog mode. 12-4 Watchdog Timer, Watchdog Timer+ Watchdog Timer Operation Note: Modifying the Watchdog Timer The WDT interval should be changed together with WDTCNTCL = 1 in a single instruction to avoid an unexpected immediate PUC or interrupt. The WDT should be halted before changing the clock source to avoid a possible incorrect interval. 12.2.4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control. - The WDT interrupt flag, WDTIFG, located in IFG1.0 - The WDT interrupt enable, WDTIE, located in IE1.0 When using the WDT in the watchdog mode, the WDTIFG flag sources a reset vector interrupt. The WDTIFG can be used by the reset interrupt service routine to determine if the watchdog caused the device to reset. If the flag is set, then the watchdog timer initiated the reset condition either by timing out or by a security key violation. If WDTIFG is cleared, the reset was caused by a different source. When using the WDT in interval timer mode, the WDTIFG flag is set after the selected time interval and requests a WDT interval timer interrupt if the WDTIE and the GIE bits are set. The interval timer interrupt vector is different from the reset vector used in watchdog mode. In interval timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced or can be reset with software. 12.2.5 WDT+ Enhancements The WDT+ module provides enhanced functionality over the WDT. The WDT+ provides a fail-safe clocking feature to ensure that the clock to the WDT+ cannot be disabled while in watchdog mode. This means the low-power modes may be affected by the choice for the WDT+ clock. For example, if ACLK is the WDT+ clock source, LPM4 is not available, because the WDT+ prevents ACLK from being disabled. Also, if ACLK or SMCLK fail while sourcing the WDT+, the WDT+ clock source is automatically switched to MCLK. In this case, if MCLK is sourced from a crystal and the crystal has failed, the FLL+ fail-safe feature activates the DCO and uses it as the source for MCLK. When the WDT+ module is used in interval timer mode, there is no fail-safe feature for the clock source. Watchdog Timer, Watchdog Timer+ 12-5 Watchdog Timer Operation 12.2.6 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signals are available in different low-power modes. The requirements of the user’s application and the type of clocking used determine how the WDT should be configured. For example, the WDT should not be configured in watchdog mode with SMCLK as its clock source if the user wants to use LPM3, because SMCLK is not active in LPM3 and the WDT would not function. If WDT+ is sourced from SMCLK, SMCLK remains enabled during LPM3, which increases the current consumption of LPM3. When the watchdog timer is not required, the WDTHOLD bit can be used to hold the WDTCNT, reducing power consumption. 12.2.7 Software Examples Any write operation to WDTCTL must be a word operation with 05Ah (WDTPW) in the upper byte: ; Periodically clear an active watchdog MOV #WDTPW+WDTCNTCL,&WDTCTL ; ; Change watchdog timer interval MOV #WDTPW+WDTCNTL+WDTSSEL,&WDTCTL ; ; Stop the watchdog MOV #WDTPW+WDTHOLD,&WDTCTL ; ; Change WDT to interval timer mode, clock/8192 interval MOV #WDTPW+WDTCNTCL+WDTTMSEL+WDTIS0,&WDTCTL 12-6 Watchdog Timer, Watchdog Timer+ Watchdog Timer Registers 12.3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 12−1. Table 12−1.Watchdog Timer Registers Register Watchdog timer control register SFR interrupt enable register 1 SFR interrupt flag register 1 † WDTIFG is reset with POR Short Form WDTCTL IE1 IFG1 Register Type Address Read/write 0120h Read/write 0000h Read/write 0002h Initial State 06900h with PUC Reset with PUC Reset with PUC† Watchdog Timer, Watchdog Timer+ 12-7 Watchdog Timer Registers WDTCTL, Watchdog Timer Control Register 15 14 13 12 11 10 9 8 WDTPW Reads as 069h Must be written as 05Ah 7 6 5 4 3 2 WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL rw−0 rw−0 rw−0 rw−0 r0(w) rw−0 1 0 WDTISx rw−0 rw−0 WDTPW WDTHOLD Bits 15-8 Bit 7 WDTNMIES Bit 6 WDTNMI Bit 5 WDTTMSEL Bit 4 WDTCNTCL Bit 3 WDTSSEL Bit 2 WDTISx Bits 1-0 Watchdog timer password. Always read as 069h. Must be written as 05Ah, or a PUC is generated. Watchdog timer hold. This bit stops the watchdog timer. Setting WDTHOLD = 1 when the WDT is not in use conserves power. 0 Watchdog timer is not stopped 1 Watchdog timer is stopped Watchdog timer NMI edge select. This bit selects the interrupt edge for the NMI interrupt when WDTNMI = 1. Modifying this bit can trigger an NMI. Modify this bit when WDTNMI = 0 to avoid triggering an accidental NMI. 0 NMI on rising edge 1 NMI on falling edge Watchdog timer NMI select. This bit selects the function for the RST/NMI pin. 0 Reset function 1 NMI function Watchdog timer mode select 0 Watchdog mode 1 Interval timer mode Watchdog timer counter clear. Setting WDTCNTCL = 1 clears the count value to 0000h. WDTCNTCL is automatically reset. 0 No action 1 WDTCNT = 0000h Watchdog timer clock source select 0 SMCLK 1 ACLK Watchdog timer interval select. These bits select the watchdog timer interval to set the WDTIFG flag and/or generate a PUC. 00 Watchdog clock source / 32768 01 Watchdog clock source / 8192 10 Watchdog clock source / 512 11 Watchdog clock source / 64 12-8 Watchdog Timer, Watchdog Timer+ IE1, Interrupt Enable Register 1 7 6 5 4 3 NMIIE rw−0 Watchdog Timer Registers 2 1 0 WDTIE rw−0 NMIIE WDTIE Bits 7-5 Bit 4 Bits 3-1 Bit 0 These bits may be used by other modules. See device-specific data sheet. NMI interrupt enable. This bit enables the NMI interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. Watchdog timer interrupt enable. This bit enables the WDTIFG interrupt for interval timer mode. It is not necessary to set this bit for watchdog mode. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled Watchdog Timer, Watchdog Timer+ 12-9 Watchdog Timer Registers IFG1, Interrupt Flag Register 1 7 6 5 4 3 2 1 0 NMIIFG WDTIFG rw−(0) rw−(0) NMIIFG WDTIFG Bits 7-5 Bit 4 Bits 3-1 Bit 0 These bits may be used by other modules. See device-specific data sheet. NMI interrupt flag. NMIIFG must be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear NMIIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. Watchdog timer interrupt flag. In watchdog mode, WDTIFG remains set until reset by software. In interval mode, WDTIFG is reset automatically by servicing the interrupt, or it can be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 No interrupt pending 1 Interrupt pending 12-10 Watchdog Timer, Watchdog Timer+ Chapter 13 Basic Timer1 The Basic Timer1 module is composed of two independent cascadable 8-bit timers. This chapter describes the Basic Timer1. Basic Timer1 is implemented in all MSP430x4xx devices. Topic Page 13.1 Basic Timer1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 Basic Timer1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3 Basic Timer1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 Basic Timer1 13-1 Basic Timer1 Introduction 13.1 Basic Timer1 Introduction The Basic Timer1 supplies LCD timing and low frequency time intervals. The Basic Timer1 is two independent 8-bit timers that can also be cascaded to form one 16-bit timer function. Some uses for the Basic Timer1 include: - Real-time clock (RTC) function - Software time increments Basic Timer1 features include: - Selectable clock source - Two independent, cascadable 8-bit timers - Interrupt capability - LCD control signal generation The Basic Timer1 block diagram is shown in Figure 13−1. Note: Basic Timer1 Initialization The Basic Timer1 module registers have no initial condition. These registers must be configured by user software before use. 13-2 Basic Timer1 Figure 13−1. Basic Timer1 Block Diagram Basic Timer1 Introduction ACLK BTDIV BTHOLD BTSSEL 00 ACLK:256 01 SMCLK 10 11 EN1 CLK1 BTCNT1 Q4 Q5 Q6 Q7 BTFRFQx 11 10 01 fLCD 00 EN2 CLK2 BTCNT2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 BTIPx 111 110 101 100 Set_BTIFG 011 010 001 000 Basic Timer1 13-3 Basic Timer1 Introduction 13.2 Basic Timer1 Operation The Basic Timer1 module can be configured as two 8-bit timers or one 16-bit timer with the BTCTL register. The BTCTL register is an 8-bit read/write register. Any read or write access must use byte instructions. The Basic Timer1 controls the LCD frame frequency with BTCNT1. 13.2.1 Basic Timer1 Counter One The Basic Timer1 counter one, BTCNT1, is an 8-bit timer/counter directly accessible by software. BTCNT1 is incremented with ACLK and provides the frame frequency for the LCD controller. BTCNT1 can be stopped by setting the BTHOLD and BTDIV bits. 13.2.2 Basic Timer1 Counter Two The Basic Timer1 counter two, BTCNT2, is an 8-bit timer/counter directly accessible by software. BTCNT2 can be sourced from ACLK or SMCLK, or from ACLK/256 when cascaded with BTCNT1. The BTCNT2 clock source is selected with the BTSSEL and BTDIV bits. BTCNT2 can be stopped to reduce power consumption by setting the HOLD bit. BTCNT2 sources the Basic Timer1 interrupt, BTIFG. The interrupt interval is selected with the BTIPx bits Note: Reading or Writing BTCNT1 and BTCNT2 When the CPU clock and counter clock are asynchronous, any read from BTCNT1 or BTCNT2 may be unpredictable. Any write to BTCNT1 or BTCNT2 takes effect immediately. 13.2.3 16-Bit Counter Mode The 16-bit timer/counter mode is selected when control the BTDIV bit is set. In this mode, BTCNT1 is cascaded with BTCNT2. The clock source of BTCNT1 is ACLK, and the clock source of BTCNT2 is ACLK/256. 13-4 Basic Timer1 Basic Timer1 Introduction 13.2.4 Basic Timer1 Operation: Signal fLCD The LCD controller (but not the LCD_A controller) uses the fLCD signal from the BTCNT1 to generate the timing for common and segment lines. ACLK sources BTCNT1 and is assumed to be 32768 Hz for generating fLCD. The fLCD frequency is selected with the BTFRFQx bits and can be ACLK/256, ACLK/128, ACLK/64, or ACLK/32. The proper fLCD frequency depends on the LCD’s frame frequency and the LCD multiplex rate and is calculated by: fLCD = 2 × mux × fFrame For example, to calculate fLCD for a 3-mux LCD, with a frame frequency of 30 Hz to 100 Hz: fFrame (from LCD data sheet) = 30 Hz to 100 Hz fLCD = 2 × 3 × fFrame fLCD(min) = 180 Hz fLCD(max) = 600 Hz select fLCD = 32768/128 = 256 Hz or 32768/64 = 512 Hz The LCD_A controller does not use the Basic Timer1 for fLCD generation. See the LCD Controller and LCD_A Controller chapters for more details on the LCD controllers. 13.2.5 Basic Timer1 Interrupts The Basic Timer1 uses two bits in the SFRs for interrupt control. - Basic Timer1 interrupt flag, BTIFG, located in IFG2.7 - Basic Timer1 interrupt enable, BTIE, located in IE2.7 The BTIFG flag is set after the selected time interval and requests a Basic Timer1 interrupt if the BTIE and the GIE bits are set. The BTIFG flag is reset automatically when the interrupt is serviced, or it can be reset with software. Basic Timer1 13-5 Basic Timer1 Introduction 13.3 Basic Timer1 Registers The Basic Timer1 module registers are listed in Table 13−1. Table 13−1.Basic Timer1 Registers Register Short Form Register Type Address Initial State Basic Timer1 Control Basic Timer1 Counter 1 Basic Timer1 Counter 2 SFR interrupt enable register 2 SFR interrupt flag register 2 BTCTL BTCNT1 BTCNT2 IE2 IFG2 Read/write Read/write Read/write Read/write Read/write 040h 046h 047h 001h 003h Unchanged Unchanged Unchanged Reset with PUC Reset with PUC Note: The Basic Timer1 registers should be configured at power-up. There is no initial state for BTCTL, BTCNT1, or BTCNT2. 13-6 Basic Timer1 BTCTL, Basic Timer1 Control Register 7 BTSSEL rw 6 BTHOLD rw 5 BTDIV rw 4 3 BTFRFQx rw rw Basic Timer1 Introduction 2 1 0 BTIPx rw rw rw BTSSEL BTHOLD BTDIV Bit 7 Bit 6 Bit 5 BTCNT2 clock select. This bit, together with the BTDIV bit, selects the clock source for BTCNT2. See the description for BTDIV. Basic Timer1 hold 0 BTCNT1 and BTCNT2 are operational 1 BTCNT1 is held if BTDIV=1 BTCNT2 is held Basic Timer1 clock divide. This bit together with the BTSSEL bit, selects the clock source for BTCNT2. BTSSEL 0 0 1 1 BTDIV 0 1 0 1 BTCNT2 Clock Source ACLK ACLK/256 SMCLK ACLK/256 BTFRFQx Bits 4−3 BTIPx Bits 2−0 fLCD frequency. These bits control the LCD update frequency. 00 fACLK/32 01 fACLK/64 10 fACLK/128 11 fACLK/256 Basic Timer1 interrupt interval 000 fCLK2/2 001 fCLK2/4 010 fCLK2/8 011 fCLK2/16 100 fCLK2/32 101 fCLK2/64 110 fCLK2/128 111 fCLK2/256 Basic Timer1 13-7 Basic Timer1 Introduction BTCNT1, Basic Timer1 Counter 1 7 6 5 4 3 2 1 0 BTCNT1x rw rw rw rw rw rw rw rw BTCNT1x Bits 7−0 BTCNT1 register. The BTCNT1 register is the count of BTCNT1. BTCNT2, Basic Timer1 Counter 2 7 6 5 4 3 2 1 0 BTCNT2x rw rw rw rw rw rw rw rw BTCNT2x Bits 7−0 BTCNT2 register. The BTCNT2 register is the count of BTCNT2. 13-8 Basic Timer1 IE2, Interrupt Enable Register 2 Basic Timer1 Introduction 7 6 5 4 3 2 1 0 BTIE rw−0 BTIE Bit 7 Bits 6-1 Basic Timer1 interrupt enable. This bit enables the BTIFG interrupt. Because other bits in IE2 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. IFG2, Interrupt Flag Register 2 7 6 5 4 3 2 1 0 BTIFG rw−0 BTIFG Bit 7 Bits 6-1 Basic Timer1 interrupt flag. Because other bits in IFG2 may be used for other modules, it is recommended to clear BTIFG automatically by servicing the interrupt, or by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. Basic Timer1 13-9 13-10 Basic Timer1 Chapter 14 Real-Time Clock The Real-Time Clock module is a 32-bit counter module with calendar function. This chapter describes the Real-Time Clock (RTC) module of the MSP430x4xx family. The RTC is implemented in MSP430F41x2, MSP430FG461x, MSP430F47x, MSP430FG47x, MSP430F47x3/4, and MSP430F471xx devices. Topic Page 14.1 Real-Time Clock Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 Real-Time Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.3 Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 Real Time Clock 14-1 RTC Introduction 14.1 RTC Introduction The Real-Time Clock (RTC) module can be used as a general-purpose 32-bit timer or as a RTC with calendar function. RTC features include: - Calender and clock mode - 32-bit counter mode with selectable clock sources - Automatic counting of seconds, minutes, hours, day of week, day of month, month and year in calender mode. - Interrupt capability - Selectable BCD format The RTC block diagram is shown in Figure 14−1. Note: Real-Time Clock Initialization Most RTC module registers have no initial condition. These registers must be configured by user software before use. 14-2 Real Time Clock Figure 14−1. Real-Time Clock ACLK 00 Basic Timer BTCNT2.Q6 01 SMCLK 10 11 RTC Introduction RTCBCD RTCMODEx RTCHOLD BCD 31 ... 24 RTCNT4/ RTCDOW 23 ... 16 RTCNT3/ RTCHOUR 15 ... 8 RTCNT2/ RTCMIN Mode 7 ... 0 RTCNT1/ RTCSEC RTCTEVx BCD RTCYEARH 8−bit overflow / minute changed 16−bit overflow / hour changed 24−bit overflow / RTCHOUR = Midnight 32−bit overflow / RTCHOUR = Noon EN Calendar 00 01 Set_RTCFG 10 RTCIE 11 1 Set_BTIFG from Basic Timer 0 Set_BTIFG RTCYEARL RTCMON RTCDAY Midnight Real Time Clock 14-3 Real-Time Clock Operation 14.2 Real-Time Clock Operation The Real-Time Clock module can be configured as a real-time clock with calendar function or as a 32-bit general-purpose counter with the RTCMODEx bits. 14.2.1 Counter Mode Counter mode is selected when RTCMODEx < 11. In this mode, a 32-bit counter is provided that is directly accessible by software. Switching from calendar to counter mode resets the count value. The clock to increment the counter can be sourced from ACLK, SMCLK, or from the BTCNT2 input clock divided by 128 from the Basic Timer1 module, selected by the RTCMODEx bits. The counter can be stopped by setting the RTCHOLD bit. Four individual 8-bit counters are cascaded to provide the 32-bit counter. This provides interrupt triggers at 8-bit, 16-bit, 24-bit, and 32-bit overflows. Each counter RTCNT1 - RTCNT4 is individually accessible and may be read or written to. Note: Accessing the RTCNTx registers When the counter clock is asynchronous to the CPU clock, any read from any RTCNTx register should occur while the counter is not operating. Otherwise, the results may be unpredictable. Alternatively, the counter may be read multiple times while operating, and a majority vote taken in software to determine the correct reading. Any write to any RTCNTx register takes effect immediately. 14-4 Real Time Clock Real-Time Clock Operation 14.2.2 Calendar Mode Calendar mode is selected when RTCMODEx = 11. In calendar mode the RTC provides seconds, minutes, hours, day of week, day of month, month, and year in selectable BCD or hexadecimal format. Switching from counter to calendar mode clears the seconds, minutes, hours, day-of-week, and year counts and sets day-of-month and month counts to 1. When RTCBCD = 1, BCD format is selected for the calendar registers. The format must be selected before the time is set. Changing the state of RTCBCD clears the seconds, minutes, hours, day-of-week, and year counts and sets day-of-month and month counts to 1. The calendar includes a leap year algorithm that considers all years evenly divisible by 4 as leap years. This algorithm is accurate from the year 1901 through 2099. Note: Accessing the Real-Time Clock registers When the counter clock is asynchronous to the CPU clock, any read from any counting register should occur while the counter is not operating. Otherwise, the results may be unpredictable. Alternatively, the counter may be read multiple times while operating, and a majority vote taken in software to determine the correct reading. Any write to any counting register takes effect immediately. However the clock is stopped during the write. This could result in losing up to one second during a write. Writing of data outside the legal ranges results in unpredictable behavior. The RTC does not provide an alarm function. It can easily be implemented in software if required. 14.2.3 RTC and Basic Timer1 Interaction In calendar mode the Basic Timer1 is automatically configured as a pre-divider for the RTC module with the two 8-bit timers cascaded and ACLK selected as the Basic Timer1 clock source. The BTSSEL, BTHOLD and BTDIV bits are ignored and RTCHOLD controls both the RTC and the Basic Timer1. RTC and Basic Timer1 interrupts interact as described in Section 14.2.4, Real-Time Clock Interrupts. Real Time Clock 14-5 Real-Time Clock Operation 14.2.4 Real-Time Clock Interrupts The Real-Time Clock uses two bits for interrupt control. - Basic Timer1 interrupt flag, BTIFG, located in IFG2.7 - Real-Time Clock interrupt enable, RTCIE, located in the module The Real-Time Clock module shares the Basic Timer1 interrupt flag and vector. When RTCIE = 0, the Basic Timer1 controls interrupt generation with the BTIPx bits. In this case, the RTCEVx bits select the interval for setting the RTCFG flag, but the RTCFG flag does not generate an interrupt. The RTCFG flag must be cleared with software when RTCIE = 0. When RTCIE = 1, the RTC controls interrupt generation and the Basic Timer1 BTIPx bits are ignored. In this case, the RTCFG and BTIFG flags are set at the interval selected with the RTCEVx bits, and an interrupt request is generated if the GIE bit is set. Both the RTCFG and BTIFG flags are reset automatically when the interrupt is serviced, or can be reset with software. The interrupt intervals are listed in Table 14−1. Table 14−1.RTC Interrupt Intervals RTC Mode Counter Mode Calendar Mode RTCTEVx 00 01 10 11 00 01 10 11 Interrupt Interval 8-bit overflow 16-bit overflow 24-bit overflow 32-bit overflow Minute changed Hour changed Every day at midnight (00:00) Every day at noon (12:00) 14-6 Real Time Clock Real-Time Clock Registers 14.3 Real-Time Clock Registers The Real-Time Clock registers are listed in Table 14−2 for byte access. They may be accessed with word instructions as listed in Table 14−3. Table 14−2.Real-Time Clock Registers Register Real-Time Clock control register Real-Timer Clock second Real-Timer Counter register 1 Real-Time Clock minute Real-Time Counter register 2 Real-Time Clock hour Real-Time Counter register 3 Real-Time Clock day-of-Week Real-Time Counter register 4 Real-Time Clock day-of-month Real-Time Clock month Real-Time Clock year (low byte) Real-Time Clock year (high byte) SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form RTCCTL RTCSEC/ RTCNT1 RTCMIN/ RTCNT2 RTCHOUR/ RTCNT3 RTCDOW/ RTCNT4 RTCDAY RTCMON RTCYEARL RTCYEARH IE2 IFG2 Register Type Address Read/write 041h Read/write 042h Initial State 040h with POR None, not reset Read/write 043h None, not reset Read/write 044h None, not reset Read/write 045h None, not reset Read/write Read/write Read/write Read/write Read/write Read/write 04Ch 04Dh 04Eh 04Fh 001h 003h None, not reset None, not reset None, not reset None, not reset Reset with PUC Reset with PUC Note: Modifying SFR bits To avoid modifying control bits of other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. Table 14−3.Real-Time Clock Registers, Word Access Word Register Real-Time control register Real-Time Clock time 0 Real-Time Counter registers 1,2 Real-Time Clock time 1 Real-Time Counter registers 3,4 Real-Time Clock date Real-Time Clock year Short Form RTCTL RTCTIM0/ RTCNT12 RTCTIM1/ RTCNT34 RTCDATE RTCYEAR High-Byte Register RTCCTL RTCMIN/ RTCNT2 RTCDOW/ RTCNT4 RTCMON RTCYEARH Low-Byte Register BTCTL RTCSEC/ RTCNT1 RTCHOUR/ RTCNT3 RTCDAY RTCYEARL Address 040h 042h 044h 04Ch 04Eh Real Time Clock 14-7 Real-Time Clock Registers RTCCTL, Real-Time Clock Control Register 7 6 RTCBCD RTCHOLD rw-(0) rw-(1) 5 4 RTCMODEx rw-(0) rw-(0) 3 2 RTCTEVx rw-(0) rw-(0) 1 RTCIE rw-0 0 RTCFG rw-0 RTCBCD Bit 7 RTCHOLD Bit 6 RTCMODEx Bits 5-4 BCD format select. This bit selects BCD format for the calendar registers when RTCMODEx = 11. 0 Hexadecimal format 1 BCD format Real-Time Clock hold 0 Real-Time Clock is operational 1 RTCMODEx < 11: The RTC module is stopped RTCMODEx = 11: The RTC and the Basic Timer1 are stopped Real-Time Clock mode and clock source select RTCMODEx Counter Mode 00 32-bit counter 01 32-bit counter 10 32-bit counter 11 Calendar mode Clock Source ACLK BTCNT2.Q6 SMCLK BTCNT2.Q6 RTCTEVx Bits 3-2 Real-Time Clock interrupt event. These bits select the event for setting RTCFG. RTC Mode Counter Mode Calendar Mode RTCTEVx 00 01 10 11 00 01 10 11 Interrupt Interval 8-bit overflow 16-bit overflow 24-bit overflow 32-bit overflow Minute changed Hour changed Every day at midnight (00:00) Every day at noon (12:00) RTCIE RTCFG Bit 1 Bit 0 Real-Time Clock interrupt enable 0 Interrupt not enabled 1 Interrupt enabled Real-Time Clock interrupt flag 0 No time event occurred 1 Time event occurred 14-8 Real Time Clock RTCNT1, RTC Counter 1, Counter Mode 7 6 5 4 3 RTCNT1x rw rw rw rw rw Real-Time Clock Registers 2 1 0 rw rw rw RTCNT1x Bits 7−0 RTCNT1 register. The RTCNT1 register is the count of RTCNT1. RTCNT2, RTC Counter 2, Counter Mode 7 6 5 4 3 2 1 0 RTCNT2x rw rw rw rw rw rw rw rw RTCNT2x Bits 7−0 RTCNT2 register. The RTCNT2 register is the count of RTCNT2. RTCNT3, RTC Counter 3, Counter Mode 7 6 5 4 3 2 1 0 RTCNT3x rw rw rw rw rw rw rw rw RTCNT3x Bits 7−0 RTCNT3 register. The RTCNT3 register is the count of RTCNT3. RTCNT4, RTC Counter 4, Counter Mode − 7 6 5 4 3 2 1 0 RTCNT4x rw rw rw rw rw rw rw rw RTCNT4x Bits 7−0 RTCNT4 register. The RTCNT4 register is the count of RTCNT4. Real Time Clock 14-9 Real-Time Clock Registers RTCSEC, RTC Seconds Register, Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 0 0 Seconds (0...59) r-0 r-0 rw rw rw rw rw rw RTCSEC, RTC Seconds Register, Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 Seconds - high digit (0...5) Seconds - low digit (0...9) r-0 rw rw rw rw rw rw rw RTCMIN, RTC Minutes Register, Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 0 0 Minutes (0...59) r-0 r-0 rw rw rw rw rw rw RTCMIN, RTC Minutes Register, Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 Minutes - high digit (0...5) Minutes - low digit (0...9) r-0 rw rw rw rw rw rw rw 14-10 Real Time Clock Real-Time Clock Registers RTCHOUR, RTC Hours Register, Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 0 0 0 Hours (0...24) r-0 r-0 r-0 rw rw rw rw rw RTCHOUR, RTC Hours Register, Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 0 Hours high digit (0...2) Hours low digit (0...9) r-0 r-0 rw rw rw rw rw rw RTCDOW, RTC Day-of-Week Register, Calendar Mode 7 6 5 4 3 2 1 0 0 0 0 0 0 Day-of-Week (0...6) r-0 r-0 r-0 r-0 r-0 rw rw rw Real Time Clock 14-11 Real-Time Clock Registers RTCDAY, RTC Day-of-Month Register, Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 0 0 0 Day-of-Month (1...28,29,30,31) r-0 r-0 r-0 rw rw rw rw rw RTCDAY, RTC Day-of-Month Register, Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 0 Day-of-Month high digit (0...3) Day-of-Month low digit (0...9) r-0 r-0 rw rw rw rw rw rw RTCMON, RTC Month Register, Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 0 0 0 0 Month (1..12) r-0 r-0 r-0 r-0 rw rw rw rw RTCMON, RTC Month Register, Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 0 0 Month high digit (0...3) Month low digit (0...9) r-0 r-0 r-0 rw rw rw rw rw 14-12 Real Time Clock Real-Time Clock Registers RTCYEARL, RTC Year Low-Byte Register, Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 Year Low Byte of 0...4095 rw rw rw rw rw rw rw rw RTCYEARL, RTC Year Low-Byte Register, Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 Decade (0...9) Year lowest digit (0...9) rw rw rw rw rw rw rw rw RTCYEARH, RTC Year High-Byte Register, Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 0 0 0 0 Year High Byte of 0...4095 r-0 r-0 r-0 r-0 rw rw rw rw RTCYEARH, RTC Year High-Byte Register, Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 Century high digit (0...4) Century low digit (0...9) r-0 rw rw rw rw rw rw rw Real Time Clock 14-13 Real-Time Clock Registers IE2, Interrupt Enable Register 2 7 6 5 4 3 2 1 0 BTIE rw-0 BTIE Bit 7 Bits 6-1 Basic Timer1 interrupt enable. This bit enables the BTIFG interrupt. Because other bits in IE2 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. IFG2, Interrupt Flag Register 2 7 6 5 4 3 2 1 0 BTIFG rw-0 BTIFG Bit 7 Bits 6-1 Basic Timer1 interrupt flag. Because other bits in IFG2 may be used for other modules, it is recommended to clear BTIFG automatically by servicing the interrupt, or by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. 14-14 Real Time Clock Chapter 15 Timer_A Timer_A is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes Timer_A. This chapter describes the operation of the Timer_A of the MSP430x4xx device family. Topic Page 15.1 Timer_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 Timer_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.3 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 Timer_A 15-1 Timer_A Introduction 15.1 Timer_A Introduction Timer_A is a 16-bit timer/counter with three or five capture/compare registers. Timer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A features include: - Asynchronous 16-bit timer/counter with four operating modes - Selectable and configurable clock source - Three or five configurable capture/compare registers - Configurable outputs with PWM capability - Asynchronous input and output latching - Interrupt vector register for fast decoding of all Timer_A interrupts The block diagram of Timer_A is shown in Figure 15−1. Note: Use of the Word Count Count is used throughout this chapter. It means the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then an associated action does not take place. Note: Second Timer_A On Select Devices MSP430x415, MSP430x417, and MSP430xW42x devices implement a second Timer_A with five capture/compare registers. On these devices, both Timer_A modules are identical in function, except for the additional capture/compare registers. 15-2 Timer_A Figure 15−1. Timer_A Block Diagram Timer_A Introduction TACLK ACLK SMCLK TASSELx 00 01 10 11 Timer Clock IDx 15 Divider 1/2/4/8 Clear TACLR 16−bit Timer TAR CCISx CCI4A 00 CCI4B 01 GND 10 VCC 11 CMx Capture Mode Timer Clock logic Sync COV SCS 0 1 MCx Timer Block 0 Count Mode EQU0 RC Set TAIFG CCR0 CCR1 CCR2 CCR3 CCR4 15 0 TACCR4 CCI SCCI Y A EN Compararator 4 EQU4 CAP 0 Set TA1CCR4 1 CCIFG EQU0 Output Unit4 OUT Timer Clock D Set Q Reset OUT4 Signal OUTMODx POR Timer_A 15-3 Timer_A Operation 15.2 Timer_A Operation The Timer_A module is configured with user software. The setup and operation of Timer_A is discussed in the following sections. 15.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TAR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TAR can be read or written with software. Additionally, the timer can generate an interrupt when it overflows. TAR may be cleared by setting the TACLR bit. Setting TACLR also clears the clock divider and count direction for up/down mode. Note: Modifying Timer_A Registers It is recommended to stop the timer before modifying its operation (with exception of the interrupt enable, interrupt flag, and TACLR) to avoid errant operating conditions. When the timer clock is asynchronous to the CPU clock, any read from TAR should occur while the timer is not operating or the results may be unpredictable. Alternatively, the timer may be read multiple times while operating, and a majority vote taken in software to determine the correct reading. Any write to TAR takes effect immediately. Clock Source Select and Divider The timer clock can be sourced from ACLK, SMCLK, or externally via TACLK or INCLK. The clock source is selected with the TASSELx bits. The selected clock source may be passed directly to the timer or divided by 2, 4, or 8 using the IDx bits. The clock divider is reset when TACLR is set. 15-4 Timer_A Timer_A Operation 15.2.2 Starting the Timer The timer may be started or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TACCR0. The timer may then be restarted by writing a nonzero value to TACCR0. In this scenario, the timer starts incrementing in the up direction from zero. 15.2.3 Timer Mode Control The timer has four modes of operation as described in Table 15−1: stop, up, continuous, and up/down. The operating mode is selected with the MCx bits. Table 15−1.Timer Modes MCx 00 01 10 11 Mode Stop Up Continuous Up/down Description The timer is halted. The timer repeatedly counts from zero to the value of TACCR0. The timer repeatedly counts from zero to 0FFFFh. The timer repeatedly counts from zero up to the value of TACCR0 and back down to zero. Timer_A 15-5 Timer_A Operation Up Mode The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly counts up to the value of compare register TACCR0, which defines the period, as shown in Figure 15−2. The number of timer counts in the period is TACCR0+1. When the timer value equals TACCR0 the timer restarts counting from zero. If up mode is selected when the timer value is greater than TACCR0, the timer immediately restarts counting from zero. Figure 15−2. Up Mode 0FFFFh TACCR0 0h The TACCR0 CCIFG interrupt flag is set when the timer counts to the TACCR0 value. The TAIFG interrupt flag is set when the timer counts from TACCR0 to zero. Figure 15−3 shows the flag set cycle. Figure 15−3. Up Mode Flag Setting Timer Clock Timer CCR0−1 CCR0 0h 1h Set TAIFG Set TACCR0 CCIFG CCR0−1 CCR0 0h Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, if the new period is greater than or equal to the old period or greater than the current count value, the timer counts up to the new period. If the new period is less than the current count value, the timer rolls to zero. However, one additional count may occur before the counter rolls to zero. 15-6 Timer_A Timer_A Operation Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in Figure 15−4. The capture/compare register TACCR0 works the same way as the other capture/compare registers. Figure 15−4. Continuous Mode 0FFFFh 0h The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero. Figure 15−5 shows the flag set cycle. Figure 15−5. Continuous Mode Flag Setting Timer Clock Timer FFFEh FFFFh 0h 1h Set TAIFG FFFEh FFFFh 0h Timer_A 15-7 Timer_A Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TACCRx register in the interrupt service routine. Figure 15−6 shows two separate time intervals t0 and t1 being added to the capture/compare registers. In this usage, the time interval is controlled by hardware, not software, without impact from interrupt latency. Up to three (Timer_A3) or five (Timer_A5) independent time intervals or output frequencies can be generated using capture/compare registers. Figure 15−6. Continuous Mode Time Intervals 0FFFFh TACCR1b TACCR0b TACCR1a TACCR0a TACCR1c TACCR0c TACCR0d TACCR1d t0 t0 t0 t1 t1 t1 Time intervals can be produced with other modes as well, where TACCR0 is used as the period register. Their handling is more complex since the sum of the old TACCRx data and the new period can be higher than the TACCR0 value. When the previous TACCRx value plus tx is greater than the TACCR0 data, the TACCR0 value must be subtracted to obtain the correct time interval. 15-8 Timer_A Timer_A Operation Up/Down Mode The up/down mode is used if the timer period must be different from 0FFFFh counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare register TACCR0 and back down to zero, as shown in Figure 15−7. The period is twice the value in TACCR0. Figure 15−7. Up/Down Mode 0FFFFh TACCR0 0h The count direction is latched. This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped. If this is not desired, the TACLR bit must be set to clear the direction. The TACLR bit also clears the TAR value and the clock divider. In up/down mode, the TACCR0 CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a period, separated by 1/2 the timer period. The TACCR0 CCIFG interrupt flag is set when the timer counts from TACCR0 − 1 to TACCR0, and TAIFG is set when the timer completes counting down from 0001h to 0000h. Figure 15−8 shows the flag set cycle. Figure 15−8. Up/Down Mode Flag Setting Timer Clock Timer Up/Down Set TAIFG Set TACCR0 CCIFG CCR0−1 CCR0 CCR0−1 CCR0−2 1h 0h Timer_A 15-9 Timer_A Operation Changing the Period Register TACCR0 When changing TACCR0 while the timer is running and counting in the down direction, the timer continues its descent until it reaches zero. The value in TACCR0 is latched into TACL0 immediately; however, the new period takes effect after the counter counts down to zero. When the timer is counting in the up direction and the new period is greater than or equal to the old period or greater than the current count value, the timer counts up to the new period before counting down. When the timer is counting in the up direction, and the new period is less than the current count value, the timer begins counting down. However, one additional count may occur before the counter begins counting down. Use of the Up/Down Mode The up/down mode supports applications that require dead times between output signals (See section Timer_A Output Unit). For example, to avoid overload conditions, two outputs driving an H-bridge must never be in a high state simultaneously. In the example shown in Figure 15−9 the tdead is: tdead = ttimer × (TACCR1 − TACCR2) With: tdead Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TACCRx Content of capture/compare register x The TACCRx registers are not buffered. They update immediately when written to. Therefore, any required dead time is not maintained automatically. Figure 15−9. Output Unit in Up/Down Mode 0FFFFh TACCR0 TACCR1 TACCR2 0h Dead Time Output Mode 6: Toggle/Set Output Mode 2: Toggle/Reset TAIFG EQU1 EQU1 EQU0 TAIFG EQU1 EQU1 EQU0 EQU2 EQU2 EQU2 EQU2 Interrupt Events 15-10 Timer_A Timer_A Operation 15.2.4 Capture/Compare Blocks Three or five identical capture/compare blocks, TACCRx, are present in Timer_A. Any of the blocks may be used to capture the timer data or to generate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits. The CMx bits select the capture edge of the input signal as rising, falling, or both. A capture occurs on the selected edge of the input signal. If a capture occurs: - The timer value is copied into the TACCRx register - The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit. MSP430x4xx family devices may have different signals connected to CCIxA and CCIxB. See the device-specific data sheet for the connections of these signals. The capture signal can be asynchronous to the timer clock and cause a race condition. Setting the SCS bit synchronizes the capture with the next timer clock. Setting the SCS bit to synchronize the capture signal with the timer clock is recommended. This is illustrated in Figure 15−10. Figure 15−10. Capture Signal (SCS=1) Timer Clock Timer CCI Capture Set TACCRx CCIFG n−2 n−1 n n+1 n+2 n+3 n+4 Overflow logic is provided in each capture/compare register to indicate if a second capture was performed before the value from the first capture was read. Bit COV is set when this occurs as shown in Figure 15−11. COV must be reset with software. Timer_A 15-11 Timer_A Operation Figure 15−11.Capture Cycle No Capture Taken Capture Clear Bit COV in Register TACCTLx Idle Capture Read Capture Taken Capture Read Taken Capture Capture Read and No Capture Capture Second Capture Idle Taken COV = 1 Capture Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then sets CCIS1 = 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND, initiating a capture each time CCIS0 changes state: Compare Mode MOV #CAP+SCS+CCIS1+CM_3,&TACCTLx ; Setup TACCTLx XOR #CCIS0,&TACCTLx ; TACCTLx = TAR The compare mode is selected when CAP = 0. The compare mode is used to generate PWM output signals or interrupts at specific time intervals. When TAR counts to the value in a TACCRx: - Interrupt flag CCIFG is set - Internal signal EQUx = 1 - EQUx affects the output according to the output mode - The input signal CCI is latched into SCCI 15-12 Timer_A Timer_A Operation 15.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. Output Modes The output modes are defined by the OUTMODx bits and are described in Table 15−2. The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0, because EQUx = EQU0. Table 15−2.Output Modes OUTMODx 000 001 010 011 100 101 110 111 Mode Output Set Toggle/Reset Set/Reset Toggle Reset Toggle/Set Reset/Set Description The output signal OUTx is defined by the OUTx bit. The OUTx signal updates immediately when OUTx is updated. The output is set when the timer counts to the TACCRx value. It remains set until a reset of the timer, or until another output mode is selected and affects the output. The output is toggled when the timer counts to the TACCRx value. It is reset when the timer counts to the TACCR0 value. The output is set when the timer counts to the TACCRx value. It is reset when the timer counts to the TACCR0 value. The output is toggled when the timer counts to the TACCRx value. The output period is double the timer period. The output is reset when the timer counts to the TACCRx value. It remains reset until another output mode is selected and affects the output. The output is toggled when the timer counts to the TACCRx value. It is set when the timer counts to the TACCR0 value. The output is reset when the timer counts to the TACCRx value. It is set when the timer counts to the TACCR0 value. Timer_A 15-13 Timer_A Operation Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode. An example is shown in Figure 15−12 using TACCR0 and TACCR1. Figure 15−12. Output Example—Timer in Up Mode 0FFFFh TACCR0 TACCR1 0h EQU0 TAIFG EQU1 EQU0 TAIFG Output Mode 1: Set Output Mode 2: Toggle/Reset Output Mode 3: Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: Toggle/Set EQU1 Output Mode 7: Reset/Set EQU0 TAIFG Interrupt Events 15-14 Timer_A Timer_A Operation Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCR0 values, depending on the output mode. An example is shown in Figure 15−13 using TACCR0 and TACCR1. Figure 15−13. Output Example—Timer in Continuous Mode 0FFFFh TACCR0 TACCR1 0h Output Mode 1: Set Output Mode 2: Toggle/Reset Output Mode 3: Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: Toggle/Set TAIFG EQU1 EQU0 TAIFG EQU1 EQU0 Output Mode 7: Reset/Set Interrupt Events Timer_A 15-15 Timer_A Operation Output Example—Timer in Up/Down Mode The OUTx signal changes when the timer equals TACCRx in either count direction and when the timer equals TACCR0, depending on the output mode. An example is shown in Figure 15−14 using TACCR0 and TACCR2. Figure 15−14. Output Example—Timer in Up/Down Mode 0FFFFh TACCR0 TACCR2 0h Output Mode 1: Set Output Mode 2: Toggle/Reset Output Mode 3: Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: Toggle/Set EQU2 EQU2 EQU2 EQU2 TAIFG EQU0 TAIFG EQU0 Output Mode 7: Reset/Set Interrupt Events Note: Switching Between Output Modes When switching between output modes, one of the OUTMODx bits should remain set during the transition, unless switching to mode 0. Otherwise, output glitching can occur because a NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: BIS #OUTMOD_7,&TACCTLx ; Set output mode=7 BIC #OUTMODx,&TACCTLx ; Clear unwanted bits 15-16 Timer_A Timer_A Operation 15.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: - TACCR0 interrupt vector for TACCR0 CCIFG - TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register. In compare mode, any CCIFG flag is set if TAR counts to the associated TACCRx value. Software may also set or clear any CCIFG flag. All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set. TACCR0 Interrupt The TACCR0 CCIFG flag has the highest Timer_A interrupt priority and has a dedicated interrupt vector as shown in Figure 15−15. The TACCR0 CCIFG flag is automatically reset when the TACCR0 interrupt request is serviced. Figure 15−15. Capture/Compare TACCR0 Interrupt Flag Capture EQU0 CAP Timer Clock Set CCIE D Q Reset POR IRQ, Interrupt Service Requested IRACC, Interrupt Request Accepted TAIV, Interrupt Vector Generator The TACCR1 CCIFG, TACCR2 CCIFG, and TAIFG flags are prioritized and combined to source a single interrupt vector. The interrupt vector register TAIV is used to determine which flag requested an interrupt. The highest priority enabled interrupt generates a number in the TAIV register (see register description). This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled Timer_A interrupts do not affect the TAIV value. Any access, read or write, of the TAIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. For example, if the TACCR1 and TACCR2 CCIFG flags are set when the interrupt service routine accesses the TAIV register, TACCR1 CCIFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the TACCR2 CCIFG flag generates another interrupt. Timer_A 15-17 Timer_A Operation TAIV Software Example The following software example shows the recommended use of TAIV and the handling overhead. The TAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. The latencies are: - Capture/compare block TACCR0 - Capture/compare blocks TACCR1, TACCR2 - Timer overflow TAIFG 11 cycles 16 cycles 14 cycles ; Interrupt handler for TACCR0 CCIFG. Cycles CCIFG_0_HND ; ... ; Start of handler Interrupt latency 6 RETI 5 ; Interrupt handler for TAIFG, TACCR1 and TACCR2 CCIFG. TA_HND ... ; Interrupt latency 6 ADD &TAIV,PC ; Add offset to Jump table 3 RETI ; Vector 0: No interrupt 5 JMP CCIFG_1_HND ; Vector 2: TACCR1 2 JMP CCIFG_2_HND ; Vector 4: TACCR2 2 RETI ; Vector 6: Reserved 5 RETI ; Vector 8: Reserved 5 TAIFG_HND ... RETI ; Vector 10: TAIFG Flag ; Task starts here 5 CCIFG_2_HND ... RETI ; Vector 4: TACCR2 ; Task starts here ; Back to main program 5 CCIFG_1_HND ... RETI ; Vector 2: TACCR1 ; Task starts here ; Back to main program 5 15-18 Timer_A Timer_A Registers 15.3 Timer_A Registers The Timer_A registers are listed in Table 15−3 and Table 15−4. Table 15−3.Timer_A3 Registers Register Timer_A control Timer0_A3 Control Timer_A counter Timer0_A3 counter Timer_A capture/compare control 0 Timer0_A3 capture/compare control 0 Timer_A capture/compare 0 Timer0_A3 capture/compare 0 Timer_A capture/compare control 1 Timer0_A3 capture/compare control 1 Timer_A capture/compare 1 Timer0_A3 capture/compare 1 Timer_A capture/compare control 2 Timer0_A3 capture/compare control 2 Timer_A capture/compare 2 Timer0_A3 capture/compare 2 Timer_A interrupt vector Timer0_A3 interrupt vector Short Form TACTL/ TA0CTL TAR/ TA0R TACCTL0/ TA0CCTL TACCR0/ TA0CCR0 TACCTL1/ TA0CCTL1 TACCR1/ TA0CCR1 TACCTL 2/ TA0CCTL2 TACCR2/ TA0CCR2 TAIV/ TA0IV Register Type Address Read/write 0160h Initial State Reset with POR Read/write 0170h Reset with POR Read/write 0162h Reset with POR Read/write 0172h Reset with POR Read/write 0164h Reset with POR Read/write 0174h Reset with POR Read/write 0166h Reset with POR Read/write 0176h Reset with POR Read only 012Eh Reset with POR Table 15−4.Timer1_A5 Registers Register Short Form Timer1_A5 control TA1CTL Timer1_A5 counter TA1R Timer1_A5 capture/compare control 0 TA1CCTL0 Timer1_A5 capture/compare 0 TA1CCR0 Timer1_A5 capture/compare control 1 TA1CCTL1 Timer1_A5 capture/compare 1 TA1CCR1 Timer1_A5 capture/compare control 2 TA1CCTL 2 Timer1_A5 capture/compare 2 TA1CCR2 Timer1_A5 capture/compare control 3 TA1CCTL3 Timer1_A5 capture/compare 3 TA1CCR3 Timer1_A5 capture/compare control 4 TA1CCTL4 Timer1_A5 capture/compare 4 TA1CCR4 Timer1_A5 interrupt Vector TA1IV Register Type Address Read/write 0180h Read/write 0190h Read/write 0182h Read/write 0192h Read/write 0184h Read/write 0194h Read/write 0186h Read/write 0196h Read/write 0188h Read/write 0198h Read/write 018Ah Read/write 019Ah Read only 011Eh Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Timer_A 15-19 Timer_A Registers TACTL, Timer_A Control Register 15 rw−(0) 14 rw−(0) 13 12 Unused rw−(0) rw−(0) 11 rw−(0) 10 rw−(0) 9 8 TASSELx rw−(0) rw−(0) 7 6 IDx rw−(0) rw−(0) 5 4 MCx rw−(0) rw−(0) 3 Unused rw−(0) 2 TACLR w−(0) 1 TAIE rw−(0) 0 TAIFG rw−(0) Unused TASSELx IDx MCx Unused TACLR TAIE TAIFG Bits 15-10 Bits 9-8 Bits 7-6 Bits 5-4 Bit 3 Bit 2 Bit 1 Bit 0 Unused Timer_A clock source select 00 TACLK 01 ACLK 10 SMCLK 11 Inverted TACLK Input divider. These bits select the divider for the input clock. 00 /1 01 /2 10 /4 11 /8 Mode control. Setting MCx = 00h when Timer_A is not in use conserves power. 00 Stop mode: the timer is halted 01 Up mode: the timer counts up to TACCR0 10 Continuous mode: the timer counts up to 0FFFFh 11 Up/down mode: the timer counts up to TACCR0 then down to 0000h Unused Timer_A clear. Setting this bit resets TAR, the clock divider, and the count direction. The TACLR bit is automatically reset and is always read as zero. Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled Timer_A interrupt flag 0 No interrupt pending 1 Interrupt pending 15-20 Timer_A TAR, Timer_A Register 15 14 13 rw−(0) rw−(0) rw−(0) 12 11 TARx rw−(0) rw−(0) 10 rw−(0) Timer_A Registers 9 8 rw−(0) rw−(0) 7 rw−(0) 6 rw−(0) 5 rw−(0) 4 3 TARx rw−(0) rw−(0) 2 rw−(0) 1 rw−(0) TARx Bits 15-0 Timer_A register. The TAR register is the count of Timer_A. 0 rw−(0) TACCRx, Timer_A Capture/Compare Register x 15 rw−(0) 14 rw−(0) 13 rw−(0) 12 11 TACCRx rw−(0) rw−(0) 10 rw−(0) 9 rw−(0) 8 rw−(0) 7 rw−(0) 6 rw−(0) 5 rw−(0) 4 3 TACCRx rw−(0) rw−(0) 2 rw−(0) 1 rw−(0) 0 rw−(0) TACCRx Bits 15-0 Timer_A capture/compare register. Compare mode: TACCRx holds the data for the comparison to the timer value in the Timer_A Register, TAR. Capture mode: The Timer_A Register, TAR, is copied into the TACCRx register when a capture is performed. Timer_A 15-21 Timer_A Registers TACCTLx, Capture/Compare Control Register 15 14 CMx rw−(0) rw−(0) 13 12 CCISx rw−(0) rw−(0) 11 SCS rw−(0) 10 SCCI r 9 Unused r0 8 CAP rw−(0) 7 6 5 4 3 2 1 0 OUTMODx CCIE CCI OUT COV CCIFG rw−(0) rw−(0) rw−(0) rw−(0) r rw−(0) rw−(0) rw−(0) CMx CCISx SCS SCCI Unused CAP OUTMODx Bit 15-14 Bit 13-12 Bit 11 Bit 10 Bit 9 Bit 8 Bits 7-5 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture/compare input select. These bits select the TACCRx input signal. See the device-specific data sheet for specific signal connections. 00 CCIxA 01 CCIxB 10 GND 11 VCC Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0 Asynchronous capture 1 Synchronous capture Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be read via this bit. Unused. Read only. Always read as 0. Capture mode 0 Compare mode 1 Capture mode Output mode. Modes 2, 3, 6, and 7 are not useful for TACCR0 because EQUx = EQU0. 000 OUT bit value 001 Set 010 Toggle/reset 011 Set/reset 100 Toggle 101 Reset 110 Toggle/set 111 Reset/set 15-22 Timer_A CCIE CCI OUT COV CCIFG Timer_A Registers Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled Capture/compare input. The selected input signal can be read by this bit. Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0 No capture overflow occurred 1 Capture overflow occurred Capture/compare interrupt flag 0 No interrupt pending 1 Interrupt pending TAIV, Timer_A Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 0 r0 TAIVx 6 5 4 3 2 1 0 0 0 0 TAIVx 0 r0 r0 r0 r−(0) r−(0) r−(0) r0 Bits 15-0 Timer_A interrupt vector value TAIV Contents 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh † Timer1_A5 only Interrupt Source No interrupt pending Capture/compare 1 Capture/compare 2 Capture/compare 3† Capture/compare 4† Timer overflow Reserved Reserved Interrupt Flag − TACCR1 CCIFG TACCR2 CCIFG TACCR3 CCIFG TACCR4 CCIFG TAIFG − − Interrupt Priority Highest Lowest Timer_A 15-23 15-24 Timer_A Chapter 16 Timer_B Timer_B is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes the operation of the Timer_B of the MSP430x4xx device family. Topic Page 16.1 Timer_B Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 Timer_B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.3 Timer_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 Timer_B 16-1 Timer_B Introduction 16.1 Timer_B Introduction Timer_B is a 16-bit timer/counter with three or seven capture/compare registers. Timer_B can support multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_B features include : - Asynchronous 16-bit timer/counter with four operating modes and four selectable lengths - Selectable and configurable clock source - Three or seven configurable capture/compare registers - Configurable outputs with PWM capability - Double-buffered compare latches with synchronized loading - Interrupt vector register for fast decoding of all Timer_B interrupts The block diagram of Timer_B is shown in Figure 16−1. Note: Use of the Word Count Count is used throughout this chapter. It means the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then an associated action does not take place. 16.1.1 Similarities and Differences From Timer_A Timer_B is identical to Timer_A with the following exceptions: - The length of Timer_B is programmable to be 8, 10, 12, or 16 bits. - Timer_B TBCCRx registers are double-buffered and can be grouped. - All Timer_B outputs can be put into a high-impedance state. - The SCCI bit function is not implemented in Timer_B. 16-2 Timer_B Figure 16−1. Timer_B Block Diagram Timer_B Introduction TBCLK ACLK SMCLK TBSSELx Timer Clock IDx 15 00 Divider 01 1/2/4/8 10 11 TBCLGRPx Clear TBCLR 0 16−bit Timer TBR RC 8 10 12 16 Group Load Logic MCx Timer Block Count Mode CNTLx EQU0 00 01 Set TBIFG 10 11 CCISx CMx CCI6A CCI6B GND VCC 00 Capture 01 Mode 10 Timer Clock 11 CLLDx CCI VCC 00 TBR=0 01 EQU0 10 UP/DOWN 11 logic COV SCS 0 Sync 1 Group Load Logic CCR5 CCR4 CCR1 CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 15 0 TBCCR6 Load Compare Latch TBCL6 Compararator 6 EQU6 CAP 0 Set TBCCR6 1 CCIFG EQU0 Output Unit6 OUT Timer Clock D Set Q Reset OUT6 Signal OUTMODx POR Timer_B 16-3 Timer_B Operation 16.2 Timer_B Operation The Timer_B module is configured with user software. The setup and operation of Timer_B is discussed in the following sections. 16.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TBR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TBR can be read or written with software. Additionally, the timer can generate an interrupt when it overflows. TBR may be cleared by setting the TBCLR bit. Setting TBCLR also clears the clock divider and count direction for up/down mode. Note: Modifying Timer_B Registers It is recommended to stop the timer before modifying its operation (with exception of the interrupt enable, interrupt flag, and TBCLR) to avoid errant operating conditions. When the timer clock is asynchronous to the CPU clock, any read from TBR should occur while the timer is not operating, or the results may be unpredictable. Alternatively, the timer may be read multiple times while operating, and a majority vote taken in software to determine the correct reading. Any write to TBR takes effect immediately. TBR Length Timer_B is configurable to operate as an 8-, 10-, 12-, or 16-bit timer with the CNTLx bits. The maximum count value, TBR(max), for the selectable lengths is 0FFh, 03FFh, 0FFFh, and 0FFFFh, respectively. Data written to the TBR register in 8-, 10-, and 12-bit modes is right-justified with leading zeros. Clock Source Select and Divider The timer clock can be sourced from ACLK, SMCLK, or externally via TBCLK or INCLK. The clock source is selected with the TBSSELx bits. The selected clock source may be passed directly to the timer or divided by 2,4, or 8 using the IDx bits. The clock divider is reset when TBCLR is set. 16-4 Timer_B Timer_B Operation 16.2.2 Starting the Timer The timer may be started or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBCL0. The timer may then be restarted by loading a nonzero value to TBCL0. In this scenario, the timer starts incrementing in the up direction from zero. 16.2.3 Timer Mode Control The timer has four modes of operation as described in Table 16−1: stop, up, continuous, and up/down. The operating mode is selected with the MCx bits. Table 16−1.Timer Modes MCx 00 01 10 11 Mode Stop Up Continuous Up/down Description The timer is halted. The timer repeatedly counts from zero to the value of compare register TBCL0. The timer repeatedly counts from zero to the value selected by the CNTLx bits. The timer repeatedly counts from zero up to the value of TBCL0 and then back down to zero. Timer_B 16-5 Timer_B Operation Up Mode The up mode is used if the timer period must be different from TBR(max) counts. The timer repeatedly counts up to the value of compare latch TBCL0, which defines the period, as shown in Figure 16−2. The number of timer counts in the period is TBCL0+1. When the timer value equals TBCL0 the timer restarts counting from zero. If up mode is selected when the timer value is greater than TBCL0, the timer immediately restarts counting from zero. Figure 16−2. Up Mode TBR(max) TBCL0 0h The TBCCR0 CCIFG interrupt flag is set when the timer counts to the TBCL0 value. The TBIFG interrupt flag is set when the timer counts from TBCL0 to zero. Figure 15−3 shows the flag set cycle. Figure 16−3. Up Mode Flag Setting Timer Clock Timer TBCL0−1 TBCL0 0h 1h Set TBIFG Set TBCCR0 CCIFG TBCL0−1 TBCL0 0h Changing the Period Register TBCL0 When changing TBCL0 while the timer is running and when the TBCL0 load event is immediate, CLLD0 = 00, if the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period. If the new period is less than the current count value, the timer rolls to zero. However, one additional count may occur before the counter rolls to zero. 16-6 Timer_B Timer_B Operation Continuous Mode In continuous mode the timer repeatedly counts up to TBR(max) and restarts from zero as shown in Figure 16−4. The compare latch TBCL0 works the same way as the other capture/compare registers. Figure 16−4. Continuous Mode TBR(max) 0h The TBIFG interrupt flag is set when the timer counts from TBR(max) to zero. Figure 16−5 shows the flag set cycle. Figure 16−5. Continuous Mode Flag Setting Timer Clock Timer TBR (max−) 1 TBR (max) 0h 1h Set TBIFG TBR (max−)1 TBR (max) 0h Timer_B 16-7 Timer_B Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TBCLx latch in the interrupt service routine. Figure 16−6 shows two separate time intervals t0 and t1 being added to the capture/compare registers. The time interval is controlled by hardware, not software, without impact from interrupt latency. Up to three (Timer_B3) or 7 (Timer_B7) independent time intervals or output frequencies can be generated using capture/compare registers. Figure 16−6. Continuous Mode Time Intervals TBR(max) TBCL1b TBCL0b TBCL1a TBCL0a 0h EQU0 Interrupt t0 TBCL1c TBCL0c t0 EQU1 Interrupt t1 t1 TBCL0d TBCL1d t0 t1 Time intervals can be produced with other modes as well, where TBCL0 is used as the period register. Their handling is more complex since the sum of the old TBCLx data and the new period can be higher than the TBCL0 value. When the sum of the previous TBCLx value plus tx is greater than the TBCL0 data, TBCL0 + 1 must be subtracted to obtain the correct time interval. 16-8 Timer_B Up/Down Mode Timer_B Operation The up/down mode is used if the timer period must be different from TBR(max) counts, and if a symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare latch TBCL0, and back down to zero, as shown in Figure 16−7. The period is twice the value in TBCL0. Note: TBCL0 > TBR(max) If TBCL0 > TBR(max), the counter operates as if it were configured for continuous mode. It does not count down from TBR(max) to zero. Figure 16−7. Up/Down Mode TBCL0 0h The count direction is latched. This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped. If this is not desired, the TBCLR bit must be used to clear the direction. The TBCLR bit also clears the TBR value and the clock divider. In up/down mode, the TBCCR0 CCIFG interrupt flag and the TBIFG interrupt flag are set only once during the period, separated by 1/2 the timer period. The TBCCR0 CCIFG interrupt flag is set when the timer counts from TBCL0−1 to TBCL0, and TBIFG is set when the timer completes counting down from 0001h to 0000h. Figure 16−8 shows the flag set cycle. Figure 16−8. Up/Down Mode Flag Setting Timer Clock Timer Up/Down Set TBIFG Set TBCCR0 CCIFG TBCL0−1 TBCL0 TBCL0−1 TBCL0−2 1h 0h 1h Timer_B 16-9 Timer_B Operation Changing the Value of Period Register TBCL0 When changing TBCL0 while the timer is running and counting in the down direction, and when the TBCL0 load event is immediate, the timer continues its descent until it reaches zero. The value in TBCCR0 is latched into TBCL0 immediately; however, the new period takes effect after the counter counts down to zero. If the timer is counting in the up direction when the new period is latched into TBCL0, and the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period before counting down. When the timer is counting in the up direction, and the new period is less than the current count value when TBCL0 is loaded, the timer begins counting down. However, one additional count may occur before the counter begins counting down. Use of the Up/Down Mode The up/down mode supports applications that require dead times between output signals (see section Timer_B Output Unit). For example, to avoid overload conditions, two outputs driving an H-bridge must never be in a high state simultaneously. In the example shown in Figure 16−9 the tdead is: tdead = ttimer × (TBCL1 − TBCL3) With: tdead Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TBCLx Content of compare latch x The ability to simultaneously load grouped compare latches assures the dead times. Figure 16−9. Output Unit in Up/Down Mode TBR(max) TBCL0 TBCL1 TBCL3 0h Dead Time Output Mode 6: Toggle/Set Output Mode 2: Toggle/Reset TBIFG EQU1 EQU1 EQU0 TBIFG EQU1 EQU1 EQU0 EQU3 EQU3 EQU3 EQU3 Interrupt Events 16-10 Timer_B Timer_B Operation 16.2.4 Capture/Compare Blocks Three or seven identical capture/compare blocks, TBCCRx, are present in Timer_B. Any of the blocks may be used to capture the timer data or to generate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits. The CMx bits select the capture edge of the input signal as rising, falling, or both. A capture occurs on the selected edge of the input signal. If a capture is performed: - The timer value is copied into the TBCCRx register - The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit. MSP430x4xx family devices may have different signals connected to CCIxA and CCIxB. Refer to the device-specific data sheet for the connections of these signals. The capture signal can be asynchronous to the timer clock and cause a race condition. Setting the SCS bit synchronizes the capture with the next timer clock. Setting the SCS bit to synchronize the capture signal with the timer clock is recommended. This is illustrated in Figure 16−10. Figure 16−10. Capture Signal (SCS = 1) Timer Clock Timer CCI Capture Set TBCCRx CCIFG n−2 n−1 n n+1 n+2 n+3 n+4 Overflow logic is provided in each capture/compare register to indicate if a second capture was performed before the value from the first capture was read. Bit COV is set when this occurs as shown in Figure 16−11. COV must be reset with software. Timer_B 16-11 Timer_B Operation Figure 16−11.Capture Cycle No Capture Taken Capture Clear Bit COV in Register TBCCTLx Idle Capture Read Capture Taken Capture Read Taken Capture Capture Read and No Capture Capture Second Capture Idle Taken COV = 1 Capture Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then sets bit CCIS1 = 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND, initiating a capture each time CCIS0 changes state: Compare Mode MOV #CAP+SCS+CCIS1+CM_3,&TBCCTLx ; Setup TBCCTLx XOR #CCIS0,&TBCCTLx ; TBCCTLx = TBR The compare mode is selected when CAP = 0. Compare mode is used to generate PWM output signals or interrupts at specific time intervals. When TBR counts to the value in a TBCLx: - Interrupt flag CCIFG is set - Internal signal EQUx = 1 - EQUx affects the output according to the output mode 16-12 Timer_B Timer_B Operation Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to the timer value in compare mode. TBCLx is buffered by TBCCRx. The buffered compare latch gives the user control over when a compare period updates. The user cannot directly access TBCLx. Compare data is written to each TBCCRx and automatically transferred to TBCLx. The timing of the transfer from TBCCRx to TBCLx is user-selectable with the CLLDx bits as described in Table 16−2. Table 16−2.TBCLx Load Events CLLDx Description 00 New data is transferred from TBCCRx to TBCLx immediately when TBCCRx is written to. 01 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 10 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 for up and continuous modes. New data is transferred to from TBCCRx to TBCLx when TBR counts to the old TBCL0 value or to 0 for up/down mode 11 New data is transferred from TBCCRx to TBCLx when TBR counts to the old TBCLx value. Grouping Compare Latches Multiple compare latches may be grouped together for simultaneous updates with the TBCLGRPx bits. When using groups, the CLLDx bits of the lowest numbered TBCCRx in the group determine the load event for each compare latch of the group, except when TBCLGRP = 3, as shown in Table 16−3. The CLLDx bits of the controlling TBCCRx must not be set to zero. When the CLLDx bits of the controlling TBCCRx are set to zero, all compare latches update immediately when their corresponding TBCCRx is written; no compare latches are grouped. Two conditions must exist for the compare latches to be loaded when grouped. First, all TBCCRx registers of the group must be updated, even when new TBCCRx data equals old TBCCRx data. Second, the load event must occur. Table 16−3.Compare Latch Operating Modes TBCLGRPx 00 01 10 11 Grouping None TBCL1+TBCL2 TBCL3+TBCL4 TBCL5+TBCL6 TBCL1+TBCL2+TBCL3 TBCL4+TBCL5+TBCL6 TBCL0+TBCL1+TBCL2+ TBCL3+TBCL4+TBCL5+TBCL6 Update Control Individual TBCCR1 TBCCR3 TBCCR5 TBCCR1 TBCCR4 TBCCR1 Timer_B 16-13 Timer_B Operation 16.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. The TBOUTH pin function can be used to put all Timer_B outputs into a high-impedance state. When the TBOUTH pin function is selected for the pin, and when the pin is pulled high, all Timer_B outputs are in a high-impedance state. Output Modes The output modes are defined by the OUTMODx bits and are described in Table 16−4. The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0, because EQUx = EQU0. Table 16−4.Output Modes OUTMODx 000 001 010 011 100 101 110 111 Mode Output Set Toggle/Reset Set/Reset Toggle Reset Toggle/Set Reset/Set Description The output signal OUTx is defined by the OUTx bit. The OUTx signal updates immediately when OUTx is updated. The output is set when the timer counts to the TBCLx value. It remains set until a reset of the timer, or until another output mode is selected and affects the output. The output is toggled when the timer counts to the TBCLx value. It is reset when the timer counts to the TBCL0 value. The output is set when the timer counts to the TBCLx value. It is reset when the timer counts to the TBCL0 value. The output is toggled when the timer counts to the TBCLx value. The output period is double the timer period. The output is reset when the timer counts to the TBCLx value. It remains reset until another output mode is selected and affects the output. The output is toggled when the timer counts to the TBCLx value. It is set when the timer counts to the TBCL0 value. The output is reset when the timer counts to the TBCLx value. It is set when the timer counts to the TBCL0 value. 16-14 Timer_B Timer_B Operation Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode. An example is shown in Figure 16−12 using TBCL0 and TBCL1. Figure 16−12. Output Example—Timer in Up Mode TBR(max) TBCL0 TBCL1 0h EQU0 TBIFG EQU1 EQU0 TBIFG Output Mode 1: Set Output Mode 2: Toggle/Reset Output Mode 3: Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: Toggle/Set EQU1 Output Mode 7: Reset/Set EQU0 TBIFG Interrupt Events Timer_B 16-15 Timer_B Operation Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, An example is shown in Figure 16−13 using TBCL0 and TBCL1. Figure 16−13. Output Example—Timer in Continuous Mode TBR(max) TBCL0 TBCL1 0h Output Mode 1: Set Output Mode 2: Toggle/Reset Output Mode 3: Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: Toggle/Set TBIFG EQU1 EQU0 TBIFG EQU1 EQU0 Output Mode 7: Reset/Set Interrupt Events 16-16 Timer_B Timer_B Operation Output Example − Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode. An example is shown in Figure 16−14 using TBCL0 and TBCL3. Figure 16−14. Output Example—Timer in Up/Down Mode TBR(max) TBCL0 TBCL3 0h Output Mode 1: Set Output Mode 2: Toggle/Reset Output Mode 3: Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: Toggle/Set EQU3 EQU3 EQU3 EQU3 TBIFG EQU0 TBIFG EQU0 Output Mode 7: Reset/Set Interrupt Events Note: Switching Between Output Modes When switching between output modes, one of the OUTMODx bits should remain set during the transition, unless switching to mode 0. Otherwise, output glitching can occur because a NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: BIS #OUTMOD_7,&TBCCTLx ; Set output mode=7 BIC #OUTMODx,&TBCCTLx ; Clear unwanted bits Timer_B 16-17 Timer_B Operation 16.2.6 Timer_B Interrupts Two interrupt vectors are associated with the 16-bit Timer_B module: - TBCCR0 interrupt vector for TBCCR0 CCIFG - TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured in the associated TBCCRx register. In compare mode, any CCIFG flag is set when TBR counts to the associated TBCLx value. Software may also set or clear any CCIFG flag. All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set. TBCCR0 Interrupt Vector The TBCCR0 CCIFG flag has the highest Timer_B interrupt priority and has a dedicated interrupt vector as shown in Figure 16−15. The TBCCR0 CCIFG flag is automatically reset when the TBCCR0 interrupt request is serviced. Figure 16−15. Capture/Compare TBCCR0 Interrupt Flag Capture EQU0 CAP Timer Clock Set CCIE D Q Reset POR IRQ, Interrupt Service Requested IRACC, Interrupt Request Accepted TBIV, Interrupt Vector Generator The TBIFG flag and TBCCRx CCIFG flags (excluding TBCCR0 CCIFG) are prioritized and combined to source a single interrupt vector. The interrupt vector register TBIV is used to determine which flag requested an interrupt. The highest priority enabled interrupt (excluding TBCCR0 CCIFG) generates a number in the TBIV register (see register description). This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled Timer_B interrupts do not affect the TBIV value. Any access, read or write, of the TBIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. For example, if the TBCCR1 and TBCCR2 CCIFG flags are set when the interrupt service routine accesses the TBIV register, TBCCR1 CCIFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the TBCCR2 CCIFG flag generates another interrupt. 16-18 Timer_B Timer_B Operation TBIV, Interrupt Handler Examples The following software example shows the recommended use of TBIV and the handling overhead. The TBIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU clock cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. The latencies are: - Capture/compare block CCR0 - Capture/compare blocks CCR1 to CCR6 - Timer overflow TBIFG 11 cycles 16 cycles 14 cycles The following software example shows the recommended use of TBIV for Timer_B3. ; Interrupt handler for TBCCR0 CCIFG. Cycles CCIFG_0_HND ... ; Start of handler Interrupt latency 6 RETI 5 ; Interrupt handler for TBIFG, TBCCR1 and TBCCR2 CCIFG. TB_HND ... ; Interrupt latency 6 ADD &TBIV,PC ; Add offset to Jump table 3 RETI ; Vector 0: No interrupt 5 JMP CCIFG_1_HND ; Vector 2: Module 1 2 JMP CCIFG_2_HND ; Vector 4: Module 2 2 RETI ; Vector 6 RETI ; Vector 8 RETI ; Vector 10 RETI ; Vector 12 TBIFG_HND ... RETI ; Vector 14: TIMOV Flag ; Task starts here 5 CCIFG_2_HND ... RETI ; Vector 4: Module 2 ; Task starts here ; Back to main program 5 ; The Module 1 handler shows a way to look if any other ; interrupt is pending: 5 cycles have to be spent, but ; 9 cycles may be saved if another interrupt is pending CCIFG_1_HND ; Vector 6: Module 3 ... ; Task starts here JMP TB_HND ; Look for pending ints 2 Timer_B 16-19 Timer_B Registers 16.3 Timer_B Registers The Timer_B registers are listed in Table 16−5. Table 16−5.Timer_B Registers Register Timer_B control Timer_B counter Timer_B capture/compare control 0 Timer_B capture/compare 0 Timer_B capture/compare control 1 Timer_B capture/compare 1 Timer_B capture/compare control 2 Timer_B capture/compare 2 Timer_B capture/compare control 3 Timer_B capture/compare 3 Timer_B capture/compare control 4 Timer_B capture/compare 4 Timer_B capture/compare control 5 Timer_B capture/compare 5 Timer_B capture/compare control 6 Timer_B capture/compare 6 Timer_B Interrupt Vector Short Form TBCTL TBR TBCCTL0 TBCCR0 TBCCTL1 TBCCR1 TBCCTL 2 TBCCR2 TBCCTL3 TBCCR3 TBCCTL4 TBCCR4 TBCCTL5 TBCCR5 TBCCTL6 TBCCR6 TBIV Register Type Address Read/write 0180h Read/write 0190h Read/write 0182h Read/write 0192h Read/write 0184h Read/write 0194h Read/write 0186h Read/write 0196h Read/write 0188h Read/write 0198h Read/write 018Ah Read/write 019Ah Read/write 018Ch Read/write 019Ch Read/write 018Eh Read/write 019Eh Read only 011Eh Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR 16-20 Timer_B Timer_B Control Register TBCTL 15 Unused rw−(0) 14 13 TBCLGRPx rw−(0) rw−(0) 12 11 CNTLx rw−(0) rw−(0) 10 Unused rw−(0) Timer_B Registers 9 8 TBSSELx rw−(0) rw−(0) 7 6 IDx rw−(0) rw−(0) 5 4 MCx rw−(0) rw−(0) 3 Unused rw−(0) 2 TBCLR w−(0) 1 TBIE rw−(0) 0 TBIFG rw−(0) Unused TBCLGRP CNTLx Unused TBSSELx IDx MCx Bit 15 Bit 14-13 Bits 12-11 Bit 10 Bits 9-8 Bits 7-6 Bits 5-4 Unused TBCLx group 00 Each TBCLx latch loads independently 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update) TBCL0 independent 10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update) TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update) TBCL0 independent 11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6 (TBCCR1 CLLDx bits control the update) Counter length 00 16-bit, TBR(max) = 0FFFFh 01 12-bit, TBR(max) = 0FFFh 10 10-bit, TBR(max) = 03FFh 11 8-bit, TBR(max) = 0FFh Unused Timer_B clock source select 00 TBCLK 01 ACLK 10 SMCLK 11 Inverted TBCLK Input divider. These bits select the divider for the input clock. 00 /1 01 /2 10 /4 11 /8 Mode control. Setting MCx = 00h when Timer_B is not in use conserves power. 00 Stop mode: the timer is halted 01 Up mode: the timer counts up to TBCL0 10 Continuous mode: the timer counts up to the value set by TBCNTLx 11 Up/down mode: the timer counts up to TBCL0 and down to 0000h Timer_B 16-21 Timer_B Registers Unused TBCLR TBIE TBIFG Bit 3 Bit 2 Bit 1 Bit 0 Unused Timer_B clear. Setting this bit resets TBR, the clock divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero. Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled Timer_B interrupt flag. 0 No interrupt pending 1 Interrupt pending TBR, Timer_B Register 15 rw−(0) 14 rw−(0) 13 rw−(0) 12 11 TBRx rw−(0) rw−(0) 10 rw−(0) 9 rw−(0) 8 rw−(0) 7 rw−(0) 6 rw−(0) 5 rw−(0) 4 3 TBRx rw−(0) rw−(0) 2 rw−(0) 1 rw−(0) TBRx Bits 15-0 Timer_B register. The TBR register is the count of Timer_B. 0 rw−(0) 16-22 Timer_B TBCCRx, Timer_B Capture/Compare Register x 15 rw−(0) 14 rw−(0) 13 rw−(0) 12 11 TBCCRx rw−(0) rw−(0) 10 rw−(0) Timer_B Registers 9 8 rw−(0) rw−(0) 7 rw−(0) 6 rw−(0) 5 rw−(0) 4 3 TBCCRx rw−(0) rw−(0) 2 rw−(0) 1 rw−(0) 0 rw−(0) TBCCRx Bits 15-0 Timer_B capture/compare register Compare mode: Compare data is written to each TBCCRx and automatically transferred to TBCLx. TBCLx holds the data for the comparison to the timer value in the Timer_B Register, TBR. Capture mode: The Timer_B Register, TBR, is copied into the TBCCRx register when a capture is performed. Timer_B 16-23 Timer_B Registers TBCCTLx, Capture/Compare Control Register 15 14 CMx rw−(0) rw−(0) 13 12 CCISx rw−(0) rw−(0) 11 SCS rw−(0) 10 9 CLLDx rw−(0) rw−(0) 8 CAP rw−(0) 7 6 5 4 3 2 1 0 OUTMODx CCIE CCI OUT COV CCIFG rw−(0) rw−(0) rw−(0) rw−(0) r rw−(0) rw−(0) rw−(0) CMx CCISx SCS CLLDx CAP OUTMODx Bit 15-14 Bit 13-12 Bit 11 Bit 10-9 Bit 8 Bits 7-5 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture/compare input select. These bits select the TBCCRx input signal. See the device-specific data sheet for specific signal connections. 00 CCIxA 01 CCIxB 10 GND 11 VCC Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0 Asynchronous capture 1 Synchronous capture Compare latch load. These bits select the compare latch load event. 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBCLx loads when TBR counts to 0 (up or continuous mode) TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode) 11 TBCLx loads when TBR counts to TBCLx Capture mode 0 Compare mode 1 Capture mode Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0, because EQUx = EQU0. 000 OUT bit value 001 Set 010 Toggle/reset 011 Set/reset 100 Toggle 101 Reset 110 Toggle/set 111 Reset/set 16-24 Timer_B CCIE CCI OUT COV CCIFG Timer_B Registers Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled Capture/compare input. The selected input signal can be read by this bit. Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0 No capture overflow occurred 1 Capture overflow occurred Capture/compare interrupt flag 0 No interrupt pending 1 Interrupt pending Timer_B 16-25 Timer_B Registers TBIV, Timer_B Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 0 r0 TBIVx 6 5 4 3 2 1 0 0 0 0 TBIVx 0 r0 r0 r0 r−(0) r−(0) r−(0) r0 Bits 15-0 Timer_B interrupt vector value TBIV Contents Interrupt Source 00h No interrupt pending 02h Capture/compare 1 04h Capture/compare 2 06h Capture/compare 3† 08h Capture/compare 4† 0Ah Capture/compare 5† 0Ch Capture/compare 6† 0Eh Timer overflow † MSP430x4xx devices only Interrupt Flag − TBCCR1 CCIFG TBCCR2 CCIFG TBCCR3 CCIFG TBCCR4 CCIFG TBCCR5 CCIFG TBCCR6 CCIFG TBIFG Interrupt Priority Highest Lowest 16-26 Timer_B Chapter 17 USART Peripheral Interface, UART Mode The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. USART0 is implemented on the MSP430x42x and MSP430x43x devices. In addition to USART0, the MSP430x44x devices implement a second identical USART module, USART1. USART1 is also implemented in MSP430FG461x devices. Topic Page 17.1 USART Introduction: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2 USART Operation: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3 USART Registers: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 USART Peripheral Interface, UART Mode 17-1 USART Introduction: UART Mode 17.1 USART Introduction: UART Mode In asynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UART mode is selected when the SYNC bit is cleared. UART mode features include: - 7- or 8-bit data with odd parity, even parity, or non-parity - Independent transmit and receive shift registers - Separate transmit and receive buffer registers - LSB-first data transmit and receive - Built-in idle-line and address-bit communication protocols for multiprocessor systems - Receiver start-edge detection for auto-wake up from LPMx modes - Programmable baud rate with modulation for fractional baud rate support - Status flags for error detection and suppression and address detection - Independent interrupt capability for receive and transmit Figure 17−1 shows the USART when configured for UART mode. 17-2 USART Peripheral Interface, UART Mode Figure 17−1. USART Block Diagram: UART Mode USART Introduction: UART Mode FE PE OE BRK SWRST URXEx* URXEIE URXWIE Receive Control URXIFGx* SYNC= 0 Receive Status Receiver Buffer UxRXBUF RXERR RXWAKE Receiver Shift Register SSEL1 SSEL0 SPB CHAR PEV PENA UCLKI 00 ACLK 01 SMCLK 10 SMCLK 11 Baud−Rate Generator Prescaler/Divider UxBRx Modulator UxMCTL UCLKS SPB CHAR PEV PENA LISTEN 0 1 MM SYNC 1 1 SOMI 0 0 1 URXD 0 STE UTXD WUT Transmit Shift Register TXWAKE Transmit Buffer UxTXBUF 1 1 0 0 SIMO UTXIFGx* Transmit Control SWRST UTXEx* TXEPT UCLKI STC SYNC CKPH CKPL Clock Phase and Polarity UCLK * Refer to the device-specific datasheet for SFR locations USART Peripheral Interface, UART Mode 17-3 USART Operation: UART Mode 17.2 USART Operation: UART Mode In UART mode, the USART transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USART. The transmit and receive functions use the same baud rate frequency. 17.2.1 USART Initialization and Reset The USART is reset by a PUC or by setting the SWRST bit. After a PUC, the SWRST bit is automatically set, keeping the USART in a reset condition. When set, the SWRST bit resets the URXIEx, UTXIEx, URXIFGx, RXWAKE, TXWAKE, RXERR, BRK, PE, OE, and FE bits and sets the UTXIFGx and TXEPT bits. The receive and transmit enable flags, URXEx and UTXEx, are not altered by SWRST. Clearing SWRST releases the USART for operation. See also chapter USART Module, I2C mode for USART0 when reconfiguring from I2C mode to UART mode. Note: Initializing or Reconfiguring the USART Module The required USART initialization/reconfiguration process is: 1) Set SWRST (BIS.B #SWRST,&UxCTL) 2) Initialize all USART registers with SWRST = 1 (including UxCTL) 3) Enable USART module via the MEx SFRs (URXEx and/or UTXEx) 4) Clear SWRST via software (BIC.B #SWRST,&UxCTL) 5) Enable interrupts (optional) via the IEx SFRs (URXIEx and/or UTXIEx) Failure to follow this process may result in unpredictable USART behavior. 17.2.2 Character Format The UART character format, shown in Figure 17−2, consists of a start bit, seven or eight data bits, an even/odd/no parity bit, an address bit (address-bit mode), and one or two stop bits. The bit period is defined by the selected clock source and setup of the baud rate registers. Figure 17−2. Character Format ST D0 [Optional Bit, Condition] D6 D7 AD PA SP SP Mark Space [2nd Stop Bit, SPB = 1] [Parity Bit, PENA = 1] [Address Bit, MM = 1] [8th Data Bit, CHAR = 1] 17-4 USART Peripheral Interface, UART Mode USART Operation: UART Mode 17.2.3 Asynchronous Communication Formats When two devices communicate asynchronously, the idle-line format is used for the protocol. When three or more devices communicate, the USART supports the idle-line and address-bit multiprocessor communication formats. Idle-Line Multiprocessor Format When MM = 0, the idle-line multiprocessor format is selected. Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 17−3. An idle receive line is detected when 10 or more continuous ones (marks) are received after the first stop bit of a character. When two stop bits are used for the idle line the second stop bit is counted as the first mark bit of the idle period. The first character received after an idle period is an address character. The RXWAKE bit is used as an address tag for each block of characters. In the idle-line multiprocessor format, this bit is set when a received character is an address and is transferred to UxRXBUF. Figure 17−3. Idle-Line Format UTXDx/URXDx Blocks of Characters UTXDx/URXDx Expanded Idle Periods of 10 Bits or More UTXDx/URXDx ST Address SP ST Data SP ST Data SP First Character Within Block Is Address. It Follows Idle Period of 10 Bits or More Character Within Block Character Within Block Idle Period Less Than 10 Bits USART Peripheral Interface, UART Mode 17-5 USART Operation: UART Mode The URXWIE bit is used to control data reception in the idle-line multiprocessor format. When the URXWIE bit is set, all non-address characters are assembled but not transferred into the UxRXBUF, and interrupts are not generated. When an address character is received, the receiver is temporarily activated to transfer the character to UxRXBUF and sets the URXIFGx interrupt flag. Any applicable error flag is also set. The user can then validate the received address. If an address is received, user software can validate the address and must reset URXWIE to continue receiving data. If URXWIE remains set, only address characters are received. The URXWIE bit is not modified by the USART hardware automatically. For address transmission in idle-line multiprocessor format, a precise idle period can be generated by the USART to generate address character identifiers on UTXDx. The wake-up temporary (WUT) flag is an internal flag double-buffered with the user-accessible TXWAKE bit. When the transmitter is loaded from UxTXBUF, WUT is also loaded from TXWAKE resetting the TXWAKE bit. The following procedure sends out an idle frame to indicate an address character follows: 1) Set TXWAKE, then write any character to UxTXBUF. UxTXBUF must be ready for new data (UTXIFGx = 1). The TXWAKE value is shifted to WUT and the contents of UxTXBUF are shifted to the transmit shift register when the shift register is ready for new data. This sets WUT, which suppresses the start, data, and parity bits of a normal transmission, then transmits an idle period of exactly 11 bits. When two stop bits are used for the idle line, the second stop bit is counted as the first mark bit of the idle period. TXWAKE is reset automatically. 2) Write desired address character to UxTXBUF. UxTXBUF must be ready for new data (UTXIFGx = 1). The new character representing the specified address is shifted out following the address-identifying idle period on UTXDx. Writing the first “don’t care” character to UxTXBUF is necessary in order to shift the TXWAKE bit to WUT and generate an idle-line condition. This data is discarded and does not appear on UTXDx. 17-6 USART Peripheral Interface, UART Mode USART Operation: UART Mode Address-Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 17−4. The first character in a block of characters carries a set address bit which indicates that the character is an address. The USART RXWAKE bit is set when a received character is a valid address character and is transferred to UxRXBUF. The URXWIE bit is used to control data reception in the address-bit multiprocessor format. If URXWIE is set, data characters (address bit = 0) are assembled by the receiver but are not transferred to UxRXBUF and no interrupts are generated. When a character containing a set address bit is received, the receiver is temporarily activated to transfer the character to UxRXBUF and set URXIFGx. All applicable error status flags are also set. If an address is received, user software must reset URXWIE to continue receiving data. If URXWIE remains set, only address characters (address bit = 1) are received. The URXWIE bit is not modified by the USART hardware automatically. Figure 17−4. Address-Bit Multiprocessor Format Blocks of Characters UTXDx/URXDx UTXDx/URXDx Expanded Idle Periods of No Significance UTXDx/URXDx ST Address 1 SP ST Data 0 SP ST Data 0 SP First Character Within Block Is an Address. AD Bit Is 1 AD Bit Is 0 for Data Within Block. Idle Time Is of No Significance For address transmission in address-bit multiprocessor mode, the address bit of a character can be controlled by writing to the TXWAKE bit. The value of the TXWAKE bit is loaded into the address bit of the character transferred from UxTXBUF to the transmit shift register, automatically clearing the TXWAKE bit. TXWAKE must not be cleared by software. It is cleared by USART hardware after it is transferred to WUT or by setting SWRST. USART Peripheral Interface, UART Mode 17-7 USART Operation: UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time tτ (approximately 300 ns) is ignored. See the device-specific data sheet for parameters. When a low period on URXDx exceeds tτ a majority vote is taken for the start bit. If the majority vote fails to detect a valid start bit the USART halts character reception and waits for the next low period on URXDx. The majority vote is also used for each bit in a character to prevent bit errors. The USART module automatically detects framing errors, parity errors, overrun errors, and break conditions when receiving characters. The bits FE, PE, OE, and BRK are set when their respective condition is detected. When any of these error flags are set, RXERR is also set. The error conditions are described in Table 17−1. Table 17−1.Receive Error Conditions Error Condition Description Framing error A framing error occurs when a low stop bit is detected. When two stop bits are used, only the first stop bit is checked for framing error. When a framing error is detected, the FE bit is set. Parity error A parity error is a mismatch between the number of 1s in a character and the value of the parity bit. When an address bit is included in the character, it is included in the parity calculation. When a parity error is detected, the PE bit is set. An overrun error occurs when a character is loaded into Receive overrun error UxRXBUF before the prior character has been read. When an overrun occurs, the OE bit is set. Break condition A break condition is a period of 10 or more low bits received on URXDx after a missing stop bit. When a break condition is detected, the BRK bit is set. A break condition can also set the interrupt flag URXIFGx when URXEIE = 0. When URXEIE = 0 and a framing error, parity error, or break condition is detected, no character is received into UxRXBUF. When URXEIE = 1, characters are received into UxRXBUF and any applicable error bit is set. When any of the FE, PE, OE, BRK, or RXERR bits are set, the bit remains set until user software resets it or UxRXBUF is read. 17-8 USART Peripheral Interface, UART Mode USART Operation: UART Mode 17.2.4 USART Receive Enable The receive enable bit, URXEx, enables or disables data reception on URXDx as shown in Figure 17−5. Disabling the USART receiver stops the receive operation following completion of any character currently being received or immediately if no receive operation is active. The receive-data buffer, UxRXBUF, contains the character moved from the RX shift register after the character is received. Figure 17−5. State Diagram of Receiver Enable URXEx = 0 No Valid Start Bit Not Completed Receive Disable URXEx = 1 URXEx = 0 Idle State (Receiver Enabled) URXEx = 1 Valid Start Bit URXEx = 1 URXEx = 0 Receiver Collects Character Handle Interrupt Conditions Character Received Note: Re-Enabling the Receiver (Setting URXEx): UART Mode When the receiver is disabled (URXEx = 0), re-enabling the receiver (URXEx = 1) is asynchronous to any data stream that may be present on URXDx at the time. Synchronization can be performed by testing for an idle line condition before receiving a valid character (see URXWIE). USART Peripheral Interface, UART Mode 17-9 USART Operation: UART Mode 17.2.5 USART Transmit Enable When UTXEx is set, the UART transmitter is enabled. Transmission is initiated by writing data to UxTXBUF. The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty, and transmission begins. This process is shown in Figure 17−6. When the UTXEx bit is reset the transmitter is stopped. Any data moved to UxTXBUF and any active transmission of data currently in the transmit shift register prior to clearing UTXEx continue until all data transmission is completed. Figure 17−6. State Diagram of Transmitter Enable UTXEx = 0 Transmit Disable UTXEx = 1 UTXEx = 0 No Data Written to Transmit Buffer Idle State (Transmitter Enabled) UTXEx = 1 Data Written to Transmit Buffer Not Completed Transmission Active Handle Interrupt Conditions UTXEx = 1 Character Transmitted UTXEx = 0 And Last Buffer Entry Is Transmitted When the transmitter is enabled (UTXEx = 1), data should not be written to UxTXBUF unless it is ready for new data indicated by UTXIFGx = 1. Violation can result in an erroneous transmission if data in UxTXBUF is modified as it is being moved into the TX shift register. It is recommended that the transmitter be disabled (UTXEx = 0) only after any active transmission is complete. This is indicated by a set transmitter empty bit (TXEPT = 1). Any data written to UxTXBUF while the transmitter is disabled are held in the buffer but are not moved to the transmit shift register or transmitted. Once UTXEx is set, the data in the transmit buffer is immediately loaded into the transmit shift register and character transmission resumes. 17-10 USART Peripheral Interface, UART Mode USART Operation: UART Mode 17.2.6 USART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non-standard source frequencies. The baud rate generator uses one prescaler/divider and a modulator as shown in Figure 17−7. This combination supports fractional divisors for baud rate generation. The maximum USART baud rate is one-third the UART source clock frequency BRCLK. Figure 17−7. MSP430 Baud Rate Generator SSEL1 SSEL0 N = 215 ... 28 27 ... 20 UCLKI ACLK SMCLK SMCLK 00 01 BRCLK 10 11 UxBR1 UxBR0 8 8 16−Bit Counter R Q15 ............ Q0 +0 or 1 Compare (0 or 1) Toggle FF R Modulation Data Shift Register R (LSB first) mX m7 8 m0 UxMCTL Bit Start BITCLK Timing for each bit is shown in Figure 17−8. For each bit received, a majority vote is taken to determine the bit value. These samples occur at the N/2−1, N/2, and N/2+1 BRCLK periods, where N is the number of BRCLKs per BITCLK. Figure 17−8. BITCLK Baud Rate Timing Bit Start BRCLK Counter BITCLK Majority Vote: (m= 0) (m= 1) N/2 N/2−1 N/2−2 1 N/2 N/2−1 N/2−2 1 0 N/2 N/2−1 1 N/2 N/2−1 1 0 N/2 INT(N/2) + m(= 0) INT(N/2) + m(= 1) m: corresponding modulation bit R: Remainder from N/2 division Bit Period NEVEN: INT(N/2) NODD : INT(N/2) + R(= 1) USART Peripheral Interface, UART Mode 17-11 USART Operation: UART Mode Baud Rate Bit Timing The first stage of the baud rate generator is the 16-bit counter and comparator. At the beginning of each bit transmitted or received, the counter is loaded with INT(N/2) where N is the value stored in the combination of UxBR0 and UxBR1. The counter reloads INT(N/2) for each bit period half-cycle, giving a total bit period of N BRCLKs. For a given BRCLK clock source, the baud rate used determines the required division factor N: N= BRCLK baud rate The division factor N is often a non-integer value of which the integer portion can be realized by the prescaler/divider. The second stage of the baud rate generator, the modulator, is used to meet the fractional part as closely as possible. The factor N is then defined as: N + UxBR ) 1 n n*1 S i+0 mi Where: N: Target division factor UxBR: 16-bit representation of registers UxBR0 and UxBR1 i: Bit position in the character n: Total number of bits in the character mi: Data of each corresponding modulation bit (1 or 0) Baud rate + BRCLK N + BRCLK UxBR ) 1 n ȍn–1 mi i+0 The BITCLK can be adjusted from bit to bit with the modulator to meet timing requirements when a non-integer divisor is needed. Timing of each bit is expanded by one BRCLK clock cycle if the modulator bit mi is set. Each time a bit is received or transmitted, the next bit in the modulation control register determines the timing for that bit. A set modulation bit increases the division factor by one while a cleared modulation bit maintains the division factor given by UxBR. The timing for the start bit is determined by UxBR plus m0, the next bit is determined by UxBR plus m1, and so on. The modulation sequence begins with the LSB. When the character is greater than 8 bits, the modulation sequence restarts with m0 and continues until all bits are processed. Determining the Modulation Value Determining the modulation value is an interactive process. Using the timing error formula provided, beginning with the start bit , the individual bit errors are calculated with the corresponding modulator bit set and cleared. The modulation bit setting with the lower error is selected and the next bit error is calculated. This process is continued until all bit errors are minimized. When a character contains more than 8 bits, the modulation bits repeat. For example, the ninth bit of a character uses modulation bit 0. 17-12 USART Peripheral Interface, UART Mode USART Operation: UART Mode Transmit Bit Timing The timing for each character is the sum of the individual bit timings. By modulating each bit, the cumulative bit error is reduced. The individual bit error can be calculated by: NJ ƪ ƫ Nj Error [%] + baud rate BRCLK j (j ) 1) UxBR ) i+S0mi * (j ) 1) 100% With: baud rate: Desired baud rate BRCLK: Input frequency − UCLKI, ACLK, or SMCLK j: Bit position - 0 for the start bit, 1 for data bit D0, and so on UxBR: Division factor in registers UxBR1 and UxBR0 For example, the transmit errors for the following conditions are calculated: Baud rate = BRCLK = UxBR = UxMCTL = 2400 32,768 Hz (ACLK) 13, since the ideal division factor is 13.65 6Bh: m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1, and m0= 1. The LSB of UxMCTL is used first. ǒ Ǔ Start bit Error [%] + baud rate BRCLK ((0 ) 1) UxBR ) 1)–1 100% + 2.54% ǒ Ǔ Data bit D0 Error [%] + baud rate BRCLK ((1 ) 1) UxBR ) 2)–2 100% + 5.08% ǒ Ǔ Data bit D1 Error [%] + baud rate BRCLK ((2 ) 1) UxBR ) 2)–3 100% + 0.29% ǒ Data bit D2 Error [%] + baud rate BRCLK ǒ Data bit D3 Error [%] + baud rate BRCLK ((3 ) 1) ((4 ) 1) Ǔ UxBR ) 3)–4 Ǔ UxBR ) 3)–5 100% + 2.83% 100% +*1.95% ǒ Ǔ Data bit D4 Error [%] + baud rate BRCLK ((5 ) 1) UxBR ) 4)–6 100% + 0.59% ǒ Ǔ Data bit D5 Error [%] + baud rate BRCLK ((6 ) 1) UxBR ) 5)–7 100% + 3.13% ǒ Ǔ Data bit D6 Error [%] + baud rate BRCLK ((7 ) 1) UxBR ) 5)–8 100% + *1.66% ǒ Ǔ Data bit D7 Error [%] + baud rate BRCLK ((8 ) 1) UxBR ) 6)–9 100% + 0.88% ǒ Ǔ Parity bit Error [%] + baud rate BRCLK ((9 ) 1) UxBR ) 7)–10 100% + 3.42% ǒ Ǔ Stop bit 1 Error [%] + baud rate BRCLK ((10 ) 1) UxBR ) 7)–11 100% + *1.37% The results show the maximum per-bit error to be 5.08% of a BITCLK period. USART Peripheral Interface, UART Mode 17-13 USART Operation: UART Mode Receive Bit Timing Receive timing is subject to two error sources. The first is the bit-to-bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USART. Figure 17−9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud-rate clock. Figure 17−9. Receive Error i tideal BRCLK 0 1 2 t0 t1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 URXDx ST D0 D1 URXDS ST D0 D1 tactual t0 t1 t2 Synchronization Error ± 0.5x BRCLK Sample URXDS Int(UxBR/2)+m0 = Int (13/2)+1 = 6+1 = 7 UxBR +m1 = 13+1 = 14 UxBR +m2 = 13+0 = 13 Majority Vote Taken Majority Vote Taken Majority Vote Taken The ideal start bit timing tideal(0) is half the baud-rate timing tbaudrate, because the bit is tested in the middle of its period. The ideal baud-rate timing tideal(i) for the remaining character bits is the baud rate timing tbaudrate. The individual bit errors can be calculated by: ȧȡȢ NJ ƪ ǒ Ǔƫ ǒ ǓNj Ǔ Error [%] + baud rate BRCLK 2 m0 ) int UxBR 2 )i j UxBR ) i+S1mi *1*j 100% Where: baud rate is the required baud rate BRCLK is the input frequency—selected for UCLK, ACLK, or SMCLK j = 0 for the start bit, 1 for data bit D0, and so on UxBR is the division factor in registers UxBR1 and UxBR0 17-14 USART Peripheral Interface, UART Mode USART Operation: UART Mode For example, the receive errors for the following conditions are calculated: Baud rate = 2400 BRCLK = 32,768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.65 UxMCTL = 6B:m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1 and m0 = 1 The LSB of UxMCTL is used first. ǒ Ǔ Start bit Error [%] + baud rate BRCLK [2x(1 ) 6) ) (0 UxBR ) 0)] * 1 * 0 100% + 2.54% ǒ Ǔ Data bit D0 Error [%] + baud rate BRCLK [2x(1 ) 6) ) (1 UxBR ) 1)] * 1 * 1 100% + 5.08% ǒ Data bit D1 Error [%] + baud rate BRCLK ǒ Data bit D2 Error [%] + baud rate BRCLK ǒ Data bit D3 Error [%] + baud rate BRCLK ǒ Data bit D4 Error [%] + baud rate BRCLK [2x(1 ) 6) ) (2 [2x(1 ) 6) ) (3 [2x(1 ) 6) ) (4 [2x(1 ) 6) ) (5 Ǔ UxBR ) 1)] * 1 * 2 Ǔ UxBR ) 2)] * 1 * 3 Ǔ UxBR ) 2)] * 1 * 4 Ǔ UxBR ) 3)] * 1 * 5 100% + 0.29% 100% + 2.83% 100% + −1.95% 100% + 0.59% ǒ Ǔ Data bit D5 Error [%] + baud rate BRCLK [2x(1 ) 6) ) (6 UxBR ) 4)] * 1 * 6 100% + 3.13% ǒ Data bit D6 Error [%] + baud rate BRCLK ǒ Data bit D7 Error [%] + baud rate BRCLK [2x(1 ) 6) ) (7 [2x(1 ) 6) ) (8 Ǔ UxBR ) 4)] * 1 * 7 Ǔ UxBR ) 5)] * 1 * 8 100% + −1.66% 100% + 0.88% ǒ Ǔ Parity bit Error [%] + baud rate BRCLK [2x(1 ) 6) ) (9 UxBR ) 6)] * 1 * 9 100% + 3.42% ǒ Ǔ Stop bit 1 Error [%] + baud rate BRCLK [2x(1 ) 6) ) (10 UxBR ) 6)] * 1 * 10 100% + −1.37% The results show the maximum per-bit error to be 5.08% of a BITCLK period. USART Peripheral Interface, UART Mode 17-15 USART Operation: UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in Table 17−2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-Hz SMCLK. The receive error is the accumulated time versus the ideal scanning time in the middle of each bit. The transmit error is the accumulated timing error versus the ideal time of the bit period. Table 17−2.Commonly Used Baud Rates, Baud Rate Data, and Errors Divide by A: BRCLK = 32,768 Hz B: BRCLK = 1,048,576 Hz Baud Rate A: B: UxBR1 1200 27.31 873.81 0 UxBR0 1B UxMCTL 03 Max. Max. Synchr. TX RX RX Error % Error % Error % UxBR1 −4/3 − 4/3 ± 2 03 UxBR0 69 UxMCTL FF Max. Max. TX RX Error % Error % 0/0.3 ± 2 2400 13.65 436.91 0 0D 6B − 6/3 − 6/3 ± 4 01 B4 FF 0/0.3 ± 2 4800 6.83 218.45 0 06 6F − 9/11 − 9/11 ± 7 0 DA 55 0/0.4 ± 2 9600 3.41 109.23 0 03 4A − 21/12 − 21/12 ± 15 0 6D 03 −0.4/1 ± 2 19,200 54.61 0 36 6B −0.2/2 ± 2 38,400 27.31 0 1B 03 − 4/3 ± 2 76,800 13.65 0 0D 6B − 6/3 ± 4 115,20 9.1 0 0 09 08 − 5/7 ± 7 17-16 USART Peripheral Interface, UART Mode USART Operation: UART Mode 17.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF. UTXIFGx is set after a PUC or when SWRST = 1. UTXIEx is reset after a PUC or when SWRST = 1. The operation is shown is Figure 17−10. Figure 17−10. Transmit Interrupt Operation UTXIEx Q PUC or SWRST VCC Character Moved From Buffer to Shift Register Clear Set DQ UTXIFGx Interrupt Service Requested Clear SWRST Data written to UxTXBUF IRQA USART Peripheral Interface, UART Mode 17-17 USART Operation: UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1. URXIFGx is automatically reset if the pending interrupt is served (when URXSE = 0) or when UxRXBUF is read. The operation is shown in Figure 17−11. Figure 17−11.Receive Interrupt Operation SYNC Valid Start Bit Receiver Collects Character From URXD URXSE τ Erroneous Character Rejection PE FE BRK URXEIE URXWIE RXWAKE Non-Address Character Rejection URXS S Clear URXIEx Interrupt Service Requested S URXIFGx Clear Character Received or Break Detected SWRST PUC UxRXBUF Read URXSE IRQA URXEIE is used to enable or disable erroneous characters from setting URXIFGx. When using multiprocessor addressing modes, URXWIE is used to auto-detect valid address characters and reject unwanted data characters. Two types of characters do not set URXIFGx: - Erroneous characters when URXEIE = 0 - Non-address characters when URXWIE = 1 When URXEIE = 1 a break condition sets the BRK bit and the URXIFGx flag. 17-18 USART Peripheral Interface, UART Mode USART Operation: UART Mode Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. The recommended usage of the receive-start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low-power mode operation. The ultra-fast turn-on of the DCO allows character reception after the start edge detection. When URXSE, URXIEx and GIE are set and a start edge occurs on URXDx, the internal signal URXS is set. When URXS is set, a receive interrupt request is generated but URXIFGx is not set. User software in the receive interrupt service routine can test URXIFGx to determine the source of the interrupt. When URXIFGx = 0 a start edge was detected, and when URXIFGx = 1 a valid character (or break) was received. When the ISR determines the interrupt request was from a start edge, user software toggles URXSE, and must enable the BRCLK source by returning from the ISR to active mode or to a low-power mode where the source is active. If the ISR returns to a low-power mode where the BRCLK source is inactive, the character is not received. Toggling URXSE clears the URXS signal and re-enables the start edge detect feature for future characters. See chapter System Resets, Interrupts, and Operating Modes for information on entering and exiting low-power modes. The now active BRCLK allows the USART to receive the balance of the character. After the full character is received and moved to UxRXBUF, URXIFGx is set and an interrupt service is again requested. Upon ISR entry, URXIFGx = 1 indicating a character was received. The URXIFGx flag is cleared when user software reads UxRXBUF. ; Interrupt handler for start condition and ; Character receive. BRCLK = DCO. U0RX_Int BIT.B #URXIFG0,&IFG1 JZ ST_COND MOV.B &UxRXBUF,dst ... RETI ; Test URXIFGx to determine ; If start or character ; Read buffer ; ; ST_COND BIC.B #URXSE,&U0TCTL ; Clear URXS signal BIS.B #URXSE,&U0TCTL ; Re-enable edge detect BIC #SCG0+SCG1,0(SP) ; Enable BRCLK = DCO RETI ; Note: Break Detect With Halted UART Clock When using the receive start-edge detect feature, a break condition cannot be detected when the BRCLK source is off. USART Peripheral Interface, UART Mode 17-19 USART Operation: UART Mode Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time tτ (approximately 300 ns) is ignored by the USART and no interrupt request is generated (see Figure 17−12). See the device-specific data sheet for parameters. Figure 17−12. Glitch Suppression, USART Receive Not Started URXDx URXS tτ When a glitch is longer than tτ or a valid start bit occurs on URXDx, the USART receive operation is started and a majority vote is taken as shown in Figure 17−13. If the majority vote fails to detect a start bit, the USART halts character reception. If character reception is halted, an active BRCLK is not necessary. A time-out period longer than the character receive duration can be used by software to indicate that a character was not received in the expected time, and the software can disable BRCLK. Figure 17−13. Glitch Suppression, USART Activated URXDx URXS Majority Vote Taken tτ 17-20 USART Peripheral Interface, UART Mode USART Registers: UART Mode 17.3 USART Registers: UART Mode Table 17−3 lists the registers for all devices implementing a USART module. Table 17−4 applies only to devices with a second USART module, USART1. Table 17−3.USART0 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0 Baud rate control register 1 Receive buffer register Transmit buffer register SFR module enable register 1 SFR interrupt enable register 1 SFR interrupt flag register 1 Short Form U0CTL U0TCTL U0RCTL U0MCTL U0BR0 U0BR1 U0RXBUF U0TXBUF ME1 IE1 IFG1 Register Type Address Read/write 070h Read/write 071h Read/write 072h Read/write 073h Read/write 074h Read/write 075h Read 076h Read/write 077h Read/write 004h Read/write 000h Read/write 002h Initial State 001h with PUC 001h with PUC 000h with PUC Unchanged Unchanged Unchanged Unchanged Unchanged 000h with PUC 000h with PUC 082h with PUC Table 17−4.USART1 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0 Baud rate control register 1 Receive buffer register Transmit buffer register SFR module enable register 2 SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form U1CTL U1TCTL U1RCTL U1MCTL U1BR0 U1BR1 U1RXBUF U1TXBUF ME2 IE2 IFG2 Register Type Address Read/write 078h Read/write 079h Read/write 07Ah Read/write 07Bh Read/write 07Ch Read/write 07Dh Read 07Eh Read/write 07Fh Read/write 005h Read/write 001h Read/write 003h Initial State 001h with PUC 001h with PUC 000h with PUC Unchanged Unchanged Unchanged Unchanged Unchanged 000h with PUC 000h with PUC 020h with PUC Note: Modifying SFR bits To avoid modifying control bits of other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. USART Peripheral Interface, UART Mode 17-21 USART Registers: UART Mode UxCTL, USART Control Register 7 PENA rw−0 6 PEV rw−0 5 SPB rw−0 4 CHAR rw−0 3 LISTEN rw−0 2 SYNC rw−0 1 MM rw−0 0 SWRST rw−1 PENA PEV SPB CHAR LISTEN SYNC MM SWRST Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Parity enable 0 Parity disabled 1 Parity enabled. Parity bit is generated (UTXDx) and expected (URXDx). In address-bit multiprocessor mode, the address bit is included in the parity calculation. Parity select. PEV is not used when parity is disabled. 0 Odd parity 1 Even parity Stop bit select. Number of stop bits transmitted. The receiver always checks for one stop bit. 0 One stop bit 1 Two stop bits Character length. Selects 7-bit or 8-bit character length. 0 7-bit data 1 8-bit data Listen enable. The LISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UTXDx is internally fed back to the receiver. Synchronous mode enable 0 UART mode 1 SPI Mode Multiprocessor mode select 0 Idle-line multiprocessor protocol 1 Address-bit multiprocessor protocol Software reset enable 0 Disabled. USART reset released for operation 1 Enabled. USART logic held in reset state 17-22 USART Peripheral Interface, UART Mode UxTCTL, USART Transmit Control Register USART Registers: UART Mode 7 Unused rw−0 6 CKPL rw−0 5 4 SSELx rw−0 rw−0 3 URXSE rw−0 2 TXWAKE rw−0 1 Unused rw−0 0 TXEPT rw−1 Unused CKPL SSELx URXSE TXWAKE Unused TXEPT Bit 7 Bit 6 Bits 5-4 Bit 3 Bit 2 Bit 1 Bit 0 Unused Clock polarity select 0 UCLKI = UCLK 1 UCLKI = inverted UCLK Source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK UART receive start-edge. The bit enables the UART receive start-edge feature. 0 Disabled 1 Enabled Transmitter wake 0 Next frame transmitted is data 1 Next frame transmitted is an address Unused Transmitter empty flag 0 UART is transmitting data and/or data is waiting in UxTXBUF 1 Transmitter shift register and UxTXBUF are empty or SWRST = 1 USART Peripheral Interface, UART Mode 17-23 USART Registers: UART Mode UxRCTL, USART Receive Control Register 7 FE rw−0 6 PE rw−0 5 OE rw−0 4 BRK rw−0 3 URXEIE rw−0 2 URXWIE rw−0 1 RXWAKE rw−0 0 RXERR rw−0 FE PE OE BRK URXEIE URXWIE RXWAKE RXERR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Framing error flag 0 No error 1 Character received with low stop bit Parity error flag. When PENA = 0, PE is read as 0. 0 No error 1 Character received with parity error Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous character was read. 0 No error 1 Overrun error occurred Break detect flag 0 No break condition 1 Break condition occurred Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and URXIFGx is not set 1 Erroneous characters received set URXIFGx Receive wake-up interrupt-enable. This bit enables URXIFGx to be set when an address character is received. When URXEIE = 0, an address character does not set URXIFGx if it is received with errors. 0 All received characters set URXIFGx 1 Only received address characters set URXIFGx Receive wake-up flag 0 Received character is data 1 Received character is an address Receive error flag. This bit indicates a character was received with error(s). When RXERR = 1, on or more error flags (FE,PE,OE, BRK) is also set. RXERR is cleared when UxRXBUF is read. 0 No receive errors detected 1 Receive error detected 17-24 USART Peripheral Interface, UART Mode UxBR0, USART Baud Rate Control Register 0 USART Registers: UART Mode 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxBR1, USART Baud Rate Control Register 1 7 215 rw UxBRx 6 5 4 3 2 1 0 214 213 212 211 210 29 28 rw rw rw rw rw rw rw The valid baud-rate control range is 3 ≤ UxBR < 0FFFFh, where UxBR = {UxBR1+UxBR0}. Unpredictable receive and transmit timing occurs if UxBR < 3. UxMCTL, USART Modulation Control Register 7 6 5 4 3 2 1 0 m7 m6 m5 m4 m3 m2 m1 m0 rw rw rw rw rw rw rw rw UxMCTLx Bits 7−0 Modulation bits. These bits select the modulation for BRCLK. USART Peripheral Interface, UART Mode 17-25 USART Registers: UART Mode UxRXBUF, USART Receive Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 r r r r r r r r UxRXBUFx Bits 7−0 The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UxRXBUF resets the receive-error bits, the RXWAKE bit, and URXIFGx. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset. UxTXBUF, USART Transmit Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxTXBUFx Bits 7−0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UTXDx. Writing to the transmit data buffer clears UTXIFGx. The MSB of UxTXBUF is not used for 7-bit data and is reset. 17-26 USART Peripheral Interface, UART Mode ME1, Module Enable Register 1 USART Registers: UART Mode 7 6 5 4 3 2 1 0 UTXE0 URXE0 rw−0 rw−0 UTXE0 URXE0 Bit 7 Bit 6 Bits 5-0 USART0 transmit enable. This bit enables the transmitter for USART0. 0 Module not enabled 1 Module enabled USART0 receive enable. This bit enables the receiver for USART0. 0 Module not enabled 1 Module enabled These bits may be used by other modules. See device-specific data sheet. ME2, Module Enable Register 2 7 6 5 4 3 2 1 0 UTXE1 URXE1 rw−0 rw−0 UTXE1 URXE1 Bits 7-6 Bit 5 Bit 4 Bits 3-0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit enable. This bit enables the transmitter for USART1. 0 Module not enabled 1 Module enabled USART1 receive enable. This bit enables the receiver for USART1. 0 Module not enabled 1 Module enabled These bits may be used by other modules. See device-specific data sheet. USART Peripheral Interface, UART Mode 17-27 USART Registers: UART Mode IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 UTXIE0 URXIE0 rw−0 rw−0 UTXIE0 URXIE0 Bit 7 Bit 6 Bits 5-0 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. IE2, Interrupt Enable Register 2 7 6 5 4 3 2 1 0 UTXIE1 URXIE1 rw−0 rw−0 UTXIE1 URXIE1 Bits 7-6 Bit 5 Bit 4 Bits 3-0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. 17-28 USART Peripheral Interface, UART Mode USART Registers: UART Mode IFG1, Interrupt Flag Register 1 7 6 5 4 3 2 1 0 UTXIFG0 URXIFG0 rw−1 rw−0 UTXIFG0 URXIFG0 Bit 7 Bit 6 Bits 5-0 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. IFG2, Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UTXIFG1 URXIFG1 rw−1 rw−0 UTXIFG1 URXIFG1 Bits 7-6 Bit 5 Bit 4 Bits 3-0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF empty. 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. USART Peripheral Interface, UART Mode 17-29 17-30 USART Peripheral Interface, UART Mode Chapter 18 USART Peripheral Interface, SPI Mode The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. USART0 is implemented on the MSP430x42x and MSP430x43x devices. In addition to USART0, the MSP430x44x devices implement a second identical USART module, USART1. USART1 is also implemented in MSP430FG461x devices. Topic Page 18.1 USART Introduction: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.2 USART Operation: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.3 USART Registers: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13 USART Peripheral Interface, SPI Mode 18-1 USART Introduction: SPI Mode 18.1 USART Introduction: SPI Mode In synchronous mode, the USART connects the MSP430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared. SPI mode features include: - 7-bit or 8-bit data length - 3-pin and 4-pin SPI operation - Master or slave modes - Independent transmit and receive shift registers - Separate transmit and receive buffer registers - Selectable UCLK polarity and phase control - Programmable UCLK frequency in master mode - Independent interrupt capability for receive and transmit Figure 18−1 shows the USART when configured for SPI mode. 18-2 USART Peripheral Interface, SPI Mode Figure 18−1. USART Block Diagram: SPI Mode USART Introduction: SPI Mode FE PE OE BRK SWRST USPIEx* URXEIE URXWIE Receive Control URXIFGx* SYNC= 1 Receive Status Receiver Buffer UxRXBUF RXERR RXWAKE Receiver Shift Register SSEL1 SSEL0 SPB CHAR PEV PENA UCLKI 00 ACLK 01 SMCLK 10 SMCLK 11 Baud−Rate Generator Prescaler/Divider UxBRx Modulator UxMCTL UCLKS SPB CHAR PEV PENA LISTEN 0 1 MM SYNC 1 1 SOMI 0 0 1 URXD 0 STE UTXD WUT Transmit Shift Register TXWAKE Transmit Buffer UxTXBUF 1 1 0 0 SIMO UTXIFGx* Transmit Control SWRST USPIEx* TXEPT UCLKI STC SYNC CKPH CKPL Clock Phase and Polarity UCLK * See the device-specific data sheet for SFR locations. USART Peripheral Interface, SPI Mode 18-3 USART Operation: SPI Mode 18.2 USART Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, STE, is provided as to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: - SIMO Slave in, master out Master mode: SIMO is the data output line. Slave mode: SIMO is the data input line. - SOMI Slave out, master in Master mode: SOMI is the data input line. Slave mode: SOMI is the data output line. - UCLK USART SPI clock Master mode: UCLK is an output. Slave mode: UCLK is an input. - STE Slave transmit enable. Used in 4-pin mode to allow multiple masters on a single bus. Not used in 3-pin mode. 4-Pin master mode: When STE is high, SIMO and UCLK operate normally. When STE is low, SIMO and UCLK are set to the input direction. 4-pin slave mode: When STE is high, RX/TX operation of the slave is disabled and SOMI is forced to the input direction. When STE is low, RX/TX operation of the slave is enabled and SOMI operates normally. 18.2.1 USART Initialization and Reset The USART is reset by a PUC or by the SWRST bit. After a PUC, the SWRST bit is automatically set, keeping the USART in a reset condition. When set, the SWRST bit resets the URXIEx, UTXIEx, URXIFGx, OE, and FE bits and sets the UTXIFGx flag. The USPIEx bit is not altered by SWRST. Clearing SWRST releases the USART for operation. See also chapter 17. Note: Initializing or Reconfiguring the USART Module The required USART initialization/reconfiguration process is: 1) Set SWRST (BIS.B #SWRST,&UxCTL) 2) Initialize all USART registers with SWRST=1 (including UxCTL) 3) Enable USART module via the MEx SFRs (USPIEx) 4) Clear SWRST via software (BIC.B #SWRST,&UxCTL) 5) Enable interrupts (optional) via the IEx SFRs (URXIEx and/or UTXIEx) Failure to follow this process may result in unpredictable USART behavior. 18-4 USART Peripheral Interface, SPI Mode 18.2.2 Master Mode Figure 18−2. USART Master and External Slave USART Operation: SPI Mode MASTER SIMO Receive Buffer UxRXBUF Transmit Buffer UxTXBUF Px.x STE Receive Shift Register SOMI Transmit Shift Register MSB LSB MSB MSP430 USART LSB UCLK SIMO SLAVE SPI Receive Buffer STE SS Port.x SOMI Data Shift Register (DSR) MSB SCLK LSB COMMON SPI Figure 18−2 shows the USART as a master in both 3-pin and 4-pin configurations. The USART initiates a data transfer when data is moved to the transmit data buffer UxTXBUF. The UxTXBUF data is moved to the TX shift register when the TX shift register is empty, initiating data transfer on SIMO starting with the most significant bit. Data on SOMI is shifted into the receive shift register on the opposite clock edge, starting with the most significant bit. When the character is received, the receive data is moved from the RX shift register to the received data buffer UxRXBUF and the receive interrupt flag, URXIFGx, is set, indicating the RX/TX operation is complete. A set transmit interrupt flag, UTXIFGx, indicates that data has moved from UxTXBUF to the TX shift register and UxTXBUF is ready for new data. It does not indicate RX/TX completion. In master mode, the completion of an active transmission is indicated by a set transmitter empty bit TXEPT = 1. To receive data into the USART in master mode, data must be written to UxTXBUF because receive and transmit operations operate concurrently. Four-Pin SPI Master Mode In 4-pin master mode, STE is used to prevent conflicts with another master. The master operates normally when STE is high. When STE is low: - SIMO and UCLK are set to inputs and no longer drive the bus - The error bit FE is set indicating a communication integrity violation to be handled by the user A low STE signal does not reset the USART module. The STE input signal is not used in 3-pin master mode. USART Peripheral Interface, SPI Mode 18-5 USART Operation: SPI Mode 18.2.3 Slave Mode Figure 18−3. USART Slave and External Master MASTER SIMO SPI Receive Buffer Px.x STE SOMI Data Shift Register DSR MSB LSB COMMON SPI SCLK SIMO SLAVE Transmit Buffer UxTXBUF Receive Buffer UxRXBUF STE SS Port.x SOMI Transmit Shift Register Receive Shift Register MSB UCLK LSB MSB LSB MSP430 USART Figure 18−3 shows the USART as a slave in both 3-pin and 4-pin configurations. UCLK is used as the input for the SPI clock and must be supplied by the external master. The data transfer rate is determined by this clock and not by the internal baud rate generator. Data written to UxTXBUF and moved to the TX shift register before the start of UCLK is transmitted on SOMI. Data on SIMO is shifted into the receive shift register on the opposite edge of UCLK and moved to UxRXBUF when the set number of bits are received. When data is moved from the RX shift register to UxRXBUF, the URXIFGx interrupt flag is set, indicating that data has been received. The overrun error bit, OE, is set when the previously received data is not read from UxRXBUF before new data is moved to UxRXBUF. Four-Pin SPI Slave Mode In 4-pin slave mode, STE is used by the slave to enable the transmit and receive operations and is provided by the SPI master. When STE is low, the slave operates normally. When STE is high: - Any receive operation in progress on SIMO is halted - SOMI is set to the input direction A high STE signal does not reset the USART module. The STE input signal is not used in 3-pin slave mode. 18-6 USART Peripheral Interface, SPI Mode USART Operation: SPI Mode 18.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USART in SPI mode. When USPIEx = 0, the USART stops operation after the current transfer completes, or immediately if no operation is active. A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated. Transmit Enable When USPIEx = 0, any further write to UxTXBUF does not transmit. Data written to UxTXBUF begin to transmit when USPIEx = 1 and the BRCLK source is active. Figure 18−4 and Figure 18−5 show the transmit enable state diagrams. Figure 18−4. Master Mode Transmit Enable USPIEx = 0 Transmit Disable USPIEx = 1 USPIEx = 0 PUC SWRST USPIEx = 0 And Last Buffer Entry Is Transmitted No Data Written to Transfer Buffer Not Completed Idle State (Transmitter Enabled) USPIEx = 1, Data Written to Transmit Buffer Transmission Active Handle Interrupt Conditions USPIEx = 1 Character Transmitted USPIEx = 0 Figure 18−5. Slave Transmit Enable State Diagram USPIEx = 0 No Clock at UCLK Not Completed Transmit Disable USPIEx = 1 USPIEx = 0 Idle State (Transmitter Enabled) USPIEx = 1 External Clock Present Transmission Active PUC SWRST USPIEx = 0 USPIEx = 1 Handle Interrupt Conditions Character Transmitted USART Peripheral Interface, SPI Mode 18-7 USART Operation: SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 18−6 and Figure 18−7. When USPIEx = 0, UCLK is disabled from shifting data into the RX shift register. Figure 18−6. SPI Master Receive-Enable State Diagram USPIEx = 0 No Data Written to UxTXBUF Not Completed Receive Disable USPIEx = 1 USPIEx = 0 PUC SWRST Idle State (Receiver Enabled) USPIEx = 1 Data Written to UxTXBUF Receiver Collects Character USPIEx = 1 USPIEx = 0 Handle Interrupt Conditions Character Received Figure 18−7. SPI Slave Receive-Enable State Diagram USPIEx = 0 No Clock at UCLK Not Completed Receive Disable USPIEx = 1 USPIEx = 0 PUC SWRST Idle State (Receive Enabled) USPIEx = 1 External Clock Present USPIEx = 1 USPIEx = 0 Receiver Collects Character Handle Interrupt Conditions Character Received 18-8 USART Peripheral Interface, SPI Mode USART Operation: SPI Mode 18.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Figure 18−8. When MM = 0, the USART clock is provided on the UCLK pin by the master and, the baud rate generator is not used and the SSELx bits are “don’t care”. The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer. Figure 18−8. SPI Baud Rate Generator SSEL1 SSEL0 N = 215 ... 28 27 ... 20 UCLKI ACLK SMCLK SMCLK 00 01 BRCLK 10 11 UxBR1 UxBR0 8 8 16−Bit Counter R Q15 ............ Q0 Compare (0 or 1) Modulation Data Shift Register R (LSB first) Toggle FF R mX m7 8 m0 UxMCTL Bit Start BITCLK The 16-bit value of UxBR0+UxBR1 is the division factor of the USART clock source, BRCLK. The maximum baud rate that can be generated in master mode is BRCLK/2. The maximum baud rate that can be generated in slave mode is BRCLK The modulator in the USART baud rate generator is not used for SPI mode and is recommended to be set to 000h. The UCLK frequency is given by: Baud rate = BRCLK UxBR with UxBR= [UxBR1, UxBR0] USART Peripheral Interface, SPI Mode 18-9 USART Operation: SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART. Timing for each case is shown in Figure 18−9. Figure 18−9. USART SPI Timing CKPH CKPL Cycle# 1 2 3 4 5 6 7 8 00 UCLK 01 UCLK 10 UCLK 11 UCLK STE 0 X SIMO/ SOMI MSB LSB 1 X SIMO/ SOMI MSB LSB Move to UxTXBUF TX Data Shifted Out RX Sample Points 18-10 USART Peripheral Interface, SPI Mode USART Operation: SPI Mode 18.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF. UTXIFGx is set after a PUC or when SWRST = 1. UTXIEx is reset after a PUC or when SWRST = 1. The operation is shown is Figure 18−10. Figure 18−10. Transmit Interrupt Operation UTXIEx Q SYNC = 1 PUC or SWRST VCC Character Moved From Buffer to Shift Register Clear Set UTXIFGx DQ Interrupt Service Requested Clear SWRST Data moved to UxTXBUF IRQA Note: Writing to UxTXBUF in SPI Mode Data written to UxTXBUF when UTXIFGx = 0 and USPIEx = 1 may result in erroneous data transmission. USART Peripheral Interface, SPI Mode 18-11 USART Operation: SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF as shown in Figure 18−11 and Figure 18−12. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1. URXIFGx is automatically reset if the pending interrupt is served or when UxRXBUF is read. Figure 18−11.Receive Interrupt Operation SYNC Valid Start Bit Receiver Collects Character From URXD URXSE τ PE FE BRK URXEIE URXWIE RXWAKE URXS SYNC = 1 Clear URXIEx Interrupt Service Requested (S) URXIFGx Clear Character Received SWRST PUC UxRXBUF Read URXSE IRQA Figure 18−12. Receive Interrupt State Diagram SWRST = 1 Wait For Next Start Receive Character USPIEx = 0 URXIFGx = 0 URXIEx = 0 PUC Receive Character Completed USPIEx = 1 SWRST = 1 USPIEx = 0 URXIFGx = 1 USPIEx = 1 and URXIEx = 1 and GIE = 1 and Priority Priority Valid Too GIE = 0 Low Interrupt Service Started, GIE = 0 URXIFGx = 0 18-12 USART Peripheral Interface, SPI Mode USART Registers: SPI Mode 18.3 USART Registers: SPI Mode Table 18−1 lists the registers for all devices implementing a USART module. Table 18−2 applies only to devices with a second USART module, USART1. Table 18−1.USART0 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0 Baud rate control register 1 Receive buffer register Transmit buffer register SFR module enable register 1 SFR interrupt enable register 1 SFR interrupt flag register 1 Short Form U0CTL U0TCTL U0RCTL U0MCTL U0BR0 U0BR1 U0RXBUF U0TXBUF ME1 IE1 IFG1 Register Type Address Read/write 070h Read/write 071h Read/write 072h Read/write 073h Read/write 074h Read/write 075h Read 076h Read/write 077h Read/write 004h Read/write 000h Read/write 002h Initial State 001h with PUC 001h with PUC 000h with PUC Unchanged Unchanged Unchanged Unchanged Unchanged 000h with PUC 000h with PUC 082h with PUC Table 18−2.USART1 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0 Baud rate control register 1 Receive buffer register Transmit buffer register SFR module enable register 2 SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form U1CTL U1TCTL U1RCTL U1MCTL U1BR0 U1BR1 U1RXBUF U1TXBUF ME2 IE2 IFG2 Register Type Address Read/write 078h Read/write 079h Read/write 07Ah Read/write 07Bh Read/write 07Ch Read/write 07Dh Read 07Eh Read/write 07Fh Read/write 005h Read/write 001h Read/write 003h Initial State 001h with PUC 001h with PUC 000h with PUC Unchanged Unchanged Unchanged Unchanged Unchanged 000h with PUC 000h with PUC 020h with PUC Note: Modifying the SFR bits To avoid modifying control bits for other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. USART Peripheral Interface, SPI Mode 18-13 USART Registers: SPI Mode UxCTL, USART Control Register 7 Unused rw−0 6 Unused rw−0 5 I2C† rw−0 4 CHAR rw−0 3 LISTEN rw−0 2 SYNC rw−0 1 MM rw−0 0 SWRST rw−1 Unused I2C† CHAR LISTEN SYNC MM SWRST Bits 7−6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unused I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1. 0 SPI mode 1 I2C mode Character length 0 7-bit data 1 8-bit data Listen enable. The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled. The transmit signal is internally fed back to the receiver Synchronous mode enable 0 UART mode 1 SPI mode Master mode 0 USART is slave 1 USART is master Software reset enable 0 Disabled. USART reset released for operation 1 Enabled. USART logic held in reset state † Not implemented in 4xx devices. 18-14 USART Peripheral Interface, SPI Mode UxTCTL, USART Transmit Control Register USART Registers: SPI Mode 7 CKPH rw−0 6 CKPL rw−0 5 4 SSELx rw−0 rw−0 3 Unused rw−0 2 Unused rw−0 1 STC rw−0 0 TXEPT rw−1 CKPH CKPL SSELx Unused Unused STC TXEPT Bit 7 Bit 6 Bits 5-4 Bit 3 Bit 2 Bit 1 Bit 0 Clock phase select. 0 Data is changed on the first UCLK edge and captured on the following edge. 1 Data is captured on the first UCLK edge and changed on the following edge. Clock polarity select 0 The inactive state is low. 1 The inactive state is high. Source select. These bits select the BRCLK source clock. 00 External UCLK (valid for slave mode only) 01 ACLK (valid for master mode only) 10 SMCLK (valid for master mode only) 11 SMCLK (valid for master mode only) Unused Unused Slave transmit control. 0 4-pin SPI mode: STE enabled. 1 3-pin SPI mode: STE disabled. Transmitter empty flag. The TXEPT flag is not used in slave mode. 0 Transmission active and/or data waiting in UxTXBUF 1 UxTXBUF and TX shift register are empty USART Peripheral Interface, SPI Mode 18-15 USART Registers: SPI Mode UxRCTL, USART Receive Control Register 7 FE rw−0 6 Unused rw−0 5 OE rw−0 4 Unused rw−0 3 Unused rw−0 2 Unused rw−0 1 Unused rw−0 0 Unused rw−0 FE Bit 7 Undefined OE Bit 6 Bit 5 Unused Unused Unused Unused Unused Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode. 0 No conflict detected 1 A negative edge occurred on STE, indicating bus conflict Unused Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous character was read. OE is automatically reset when UxRXBUF is read, when SWRST = 1, or can be reset by software. 0 No error 1 Overrun error occurred Unused Unused Unused Unused Unused 18-16 USART Peripheral Interface, SPI Mode UxBR0, USART Baud Rate Control Register 0 7 6 5 4 3 27 26 25 24 23 rw rw rw rw rw USART Registers: SPI Mode 2 1 0 22 21 20 rw rw rw UxBR1, USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 215 214 213 212 211 210 29 28 rw rw rw rw rw rw rw rw UxBRx The baud-rate generator uses the content of {UxBR1+UxBR0} to set the baud rate. Unpredictable SPI operation occurs if UxBR < 2. UxMCTL, USART Modulation Control Register 7 6 5 4 3 2 1 0 m7 m6 m5 m4 m3 m2 m1 m0 rw rw rw rw rw rw rw rw UxMCTLx Bits 7−0 The modulation control register is not used for SPI mode and should be set to 000h. USART Peripheral Interface, SPI Mode 18-17 USART Registers: SPI Mode UxRXBUF, USART Receive Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 r r r r r r r r UxRXBUFx Bits 7−0 The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UxRXBUF resets the OE bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset. UxTXBUF, USART Transmit Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxTXBUFx Bits 7−0 The transmit data buffer is user accessible and contains current data to be transmitted. When seven-bit character-length is used, the data should be MSB justified before being moved into UxTXBUF. Data is transmitted MSB first. Writing to UxTXBUF clears UTXIFGx. 18-18 USART Peripheral Interface, SPI Mode ME1, Module Enable Register 1 USART Registers: SPI Mode 7 6 5 4 3 2 1 0 USPIE0 rw−0 USPIE0 Bit 7 Bit 6 Bits 5-0 This bit may be used by other modules. See device-specific data sheet. USART0 SPI enable. This bit enables the SPI mode for USART0. 0 Module not enabled 1 Module enabled These bits may be used by other modules. See device-specific data sheet. ME2, Module Enable Register 2 7 6 5 4 3 2 1 0 USPIE1 rw−0 USPIE1 Bits 7-5 Bit 4 Bits 3-0 These bits may be used by other modules. See device-specific data sheet. USART1 SPI enable. This bit enables the SPI mode for USART1. 0 Module not enabled 1 Module enabled These bits may be used by other modules. See device-specific data sheet. USART Peripheral Interface, SPI Mode 18-19 USART Registers: SPI Mode IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 UTXIE0 URXIE0 rw−0 rw−0 UTXIE0 URXIE0 Bit 7 Bit 6 Bits 5-0 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. IE2, Interrupt Enable Register 2 7 6 5 4 3 2 1 0 UTXIE1 URXIE1 rw−0 rw−0 UTXIE1 URXIE1 Bits 7-6 Bit 5 Bit 4 Bits 3-0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. 18-20 USART Peripheral Interface, SPI Mode USART Registers: SPI Mode IFG1, Interrupt Flag Register 1 7 6 5 4 3 2 1 0 UTXIFG0 URXIFG0 rw−1 rw−0 UTXIFG0 URXIFG0 Bit 7 Bit 6 Bits 5-0 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. IFG2, Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UTXIFG1 URXIFG1 rw−1 rw−0 UTXIFG1 URXIFG1 Bits 7-6 Bit 5 Bit 4 Bits 3-0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. USART Peripheral Interface, SPI Mode 18-21 18-22 USART Peripheral Interface, SPI Mode Chapter 19 Universal Serial Communication Interface, UART Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. Topic Page 19.1 USCI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2 USCI Introduction: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.3 USCI Operation: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.4 USCI Registers: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 Universal Serial Communication Interface, UART Mode 19-1 USCI Overview 19.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers. For example, if one device has two USCI_A modules, they are named USCI_A0 and USCI_A1. See the device-specific data sheet to determine which USCI modules, if any, are implemented on which devices. The USCI_Ax modules support: - UART mode - Pulse shaping for IrDA communications - Automatic baud rate detection for LIN communications - SPI mode The USCI_Bx modules support: - I2C mode - SPI mode 19-2 Universal Serial Communication Interface, UART Mode 19.2 USCI Introduction: UART Mode USCI Introduction: UART Mode In asynchronous mode, the USCI_Ax modules connect the MSP430 to an external system via two external pins, UCAxRXD and UCAxTXD. UART mode is selected when the UCSYNC bit is cleared. UART mode features include: - 7- or 8-bit data with odd, even, or non-parity - Independent transmit and receive shift registers - Separate transmit and receive buffer registers - LSB-first or MSB-first data transmit and receive - Built-in idle-line and address-bit communication protocols for multiprocessor systems - Receiver start-edge detection for auto-wake up from LPMx modes - Programmable baud rate with modulation for fractional baud rate support - Status flags for error detection and suppression - Status flags for address detection - Independent interrupt capability for receive and transmit Figure 19−1 shows the USCI_Ax when configured for UART mode. Universal Serial Communication Interface, UART Mode 19-3 USCI Introduction: UART Mode Figure 19−1. USCI_Ax Block Diagram: UART Mode (UCSYNC = 0) UCMODEx UCSPB UCDORM 2 Receive State Machine UCRXEIE UCRXBRKIE Error Flags Set Flags Set RXIFG UCRXERR UCPE UCFE UCOE Set UC0RXIFG Set UCBRK Set UCADDR/UCIDLE Receive Buffer UC0RXBUF Receive Shift Register UCIRRXPL UCIRRXFLx UCIRRXFE UCIREN 6 UCLISTEN 1 IrDA Decoder 1 0 UC0RX 0 0 1 UCPEN UCPAR UCMSB UC7BIT UCABEN UCSSELx Receive Baudrate Generator UC0CLK ACLK SMCLK SMCLK UC0BRx 00 01 10 BRCLK 16 Prescaler/Divider 11 Modulator 4 3 UCBRFx UCBRSx UCOS16 Receive Clock Transmit Clock UCPEN UCPAR UCMSB UC7BIT UCIREN Transmit Shift Register 0 Transmit Buffer UC0TXBUF 1 IrDA Encoder 6 UCIRTXPLx Transmit State Machine Set UC0TXIFG UCTXBRK UCTXADDR 2 UCMODEx UCSPB UC0TX 19-4 Universal Serial Communication Interface, UART Mode USCI Operation: UART Mode 19.3 USCI Operation: UART Mode In UART mode, the USCI transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USCI. The transmit and receive functions use the same baud rate frequency. 19.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition. When set, the UCSWRST bit resets the UCAxRXIE, UCAxTXIE, UCAxRXIFG, UCRXERR, UCBRK, UCPE, UCOE, UCFE, UCSTOE and UCBTOE bits and sets the UCAxTXIFG bit. Clearing UCSWRST releases the USCI for operation. Note: Initializing or Re-Configuring the USCI Module The recommended USCI initialization/re-configuration process is: 1) Set UCSWRST (BIS.B #UCSWRST,&UCAxCTL1) 2) Initialize all USCI registers with UCSWRST = 1 (including UCAxCTL1) 3) Configure ports. 4) Clear UCSWRST via software (BIC.B #UCSWRST,&UCAxCTL1) 5) Enable interrupts (optional) via UCAxRXIE and/or UCAxTXIE 19.3.2 Character Format The UART character format, shown in Figure 19−2, consists of a start bit, seven or eight data bits, an even/odd/no parity bit, an address bit (address-bit mode), and one or two stop bits. The UCMSB bit controls the direction of the transfer and selects LSB or MSB first. LSB-first is typically required for UART communication. Figure 19−2. Character Format ST D0 [Optional Bit, Condition] D6 D7 AD PA SP SP Mark Space [2nd Stop Bit, UCSPB = 1] [Parity Bit, UCPEN = 1] [Address Bit, UCMODEx = 10] [8th Data Bit, UC7BIT = 0] Universal Serial Communication Interface, UART Mode 19-5 USCI Operation: UART Mode 19.3.3 Asynchronous Communication Formats When two devices communicate asynchronously, no multiprocessor format is required for the protocol. When three or more devices communicate, the USCI supports the idle-line and address-bit multiprocessor communication formats. Idle-Line Multiprocessor Format When UCMODEx = 01, the idle-line multiprocessor format is selected. Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 19−3. An idle receive line is detected when 10 or more continuous ones (marks) are received after the one or two stop bits of a character. The baud rate generator is switched off after reception of an idle line until the next start edge is detected. When an idle line is detected the UCIDLE bit is set. The UCIDLE bit is reset by software or by reading the UCAxRXBUF. The first character received after an idle period is an address character. The UCIDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. Figure 19−3. Idle-Line Format Blocks of Characters UCAxTXD/RXD UCAxTXD/RXD Expanded Idle Periods of 10 Bits or More UCAxTXD/RXD ST Address SP ST Data SP ST Data SP First Character Within Block Is Address. It Follows Idle Period of 10 Bits or More Character Within Block Character Within Block Idle Period Less Than 10 Bits 19-6 Universal Serial Communication Interface, UART Mode USCI Operation: UART Mode The UCDORM bit is used to control data reception in the idle-line multiprocessor format. When UCDORM = 1, all non-address characters are assembled but not transferred into the UCAxRXBUF, and interrupts are not generated. When an address character is received, the character is transferred into UCAxRXBUF, UCAxRXIFG is set, and any applicable error flag is set when UCRXEIE = 1. When UCRXEIE = 0 and an address character is received but has a framing error or parity error, the character is not transferred into UCAxRXBUF and UCAxRXIFG is not set. If an address is received, user software can validate the address and must reset UCDORM to continue receiving data. If UCDORM remains set, only address characters will be received. When UCDORM is cleared during the reception of a character the receive interrupt flag will be set after the reception completed. The UCDORM bit is not modified by the USCI hardware automatically. For address transmission in idle-line multiprocessor format, a precise idle period can be generated by the USCI to generate address character identifiers on UCAxTXD. The double-buffered UCTXADDR flag indicates if the next character loaded into UCAxTXBUF is preceded by an idle line of 11 bits. UCTXADDR is automatically cleared when the start bit is generated. Transmitting an Idle Frame The following procedure sends out an idle frame to indicate an address character followed by associated data: 1) Set UCTXADDR, then write the address character to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). This generates an idle period of exactly 11 bits followed by the address character. UCTXADDR is reset automatically when the address character is transferred from UCAxTXBUF into the shift register. 2) Write desired data characters to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). The data written to UCAxTXBUF is transferred to the shift register and transmitted as soon as the shift register is ready for new data. The idle-line time must not be exceeded between address and data transmission or between data transmissions. Otherwise, the transmitted data will be misinterpreted as an address. Universal Serial Communication Interface, UART Mode 19-7 USCI Operation: UART Mode Address-Bit Multiprocessor Format When UCMODEx = 10, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 19−4. The first character in a block of characters carries a set address bit which indicates that the character is an address. The USCI UCADDR bit is set when a received character has its address bit set and is transferred to UCAxRXBUF. The UCADDR bit is reset by software or by reading the UCAxRXBUF. The UCDORM bit is used to control data reception in the address-bit multiprocessor format. When UCDORM is set, data characters with address bit = 0 are assembled by the receiver but are not transferred to UCAxRXBUF and no interrupts are generated. When a character containing a set address bit is received, the character is transferred into UCAxRXBUF, UCAxRXIFG is set, and any applicable error flag is set when UCRXEIE = 1. When UCRXEIE = 0 and a character containing a set address bit is received, but has a framing error or parity error, the character is not transferred into UCAxRXBUF and UCAxRXIFG is not set. If an address is received, user software can validate the address and must reset UCDORM to continue receiving data. If UCDORM remains set, only address characters with address bit = 1 will be received. The UCDORM bit is not modified by the USCI hardware automatically. When UCDORM = 0 all received characters will set the receive interrupt flag UCAxRXIFG. If UCDORM is cleared during the reception of a character the receive interrupt flag will be set after the reception is completed. For address transmission in address-bit multiprocessor mode, the address bit of a character is controlled by the UCTXADDR bit. The value of the UCTXADDR bit is loaded into the address bit of the character transferred from UCAxTXBUF to the transmit shift register. UCTXADDR is automatically cleared when the start bit is generated. 19-8 Universal Serial Communication Interface, UART Mode Figure 19−4. Address-Bit Multiprocessor Format UCAxTXD/UCAxRXD Blocks of Characters USCI Operation: UART Mode UCAxTXD/UCAxRXD Expanded Idle Periods of No Significance UCAxTXD/UCAxRXD ST Address 1 SP ST Data 0 SP ST Data 0 SP First Character Within Block Is an Address. AD Bit Is 1 AD Bit Is 0 for Data Within Block. Idle Time Is of No Significance Break Reception and Generation When UCMODEx = 00, 01, or 10 the receiver detects a break when all data, parity, and stop bits are low, regardless of the parity, address mode, or other character settings. When a break is detected, the UCBRK bit is set. If the break interrupt enable bit, UCBRKIE, is set, the receive interrupt flag UCAxRXIFG will also be set. In this case, the value in UCAxRXBUF is 0h since all data bits were zero. To transmit a break set the UCTXBRK bit, then write 0h to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). This generates a break with all bits low. UCTXBRK is automatically cleared when the start bit is generated. Universal Serial Communication Interface, UART Mode 19-9 USCI Operation: UART Mode 19.3.4 Automatic Baud Rate Detection When UCMODEx = 11 UART mode with automatic baud rate detection is selected. For automatic baud rate detection, a data frame is preceded by a synchronization sequence that consists of a break and a synch field. A break is detected when 11 or more continuous zeros (spaces) are received. If the length of the break exceeds 21 bit times the break timeout error flag UCBTOE is set. The synch field follows the break as shown in Figure 19−5. Figure 19−5. Auto Baud Rate Detection − Break/Synch Sequence Break Delimiter Synch For LIN conformance the character format should be set to 8 data bits, LSB first, no parity and one stop bit. No address bit is available. The synch field consists of the data 055h inside a byte field as shown in Figure 19−6. The synchronization is based on the time measurement between the first falling edge and the last falling edge of the pattern. The transmit baud rate generator is used for the measurement if automatic baud rate detection is enabled by setting UCABDEN. Otherwise, the pattern is received but not measured. The result of the measurement is transferred into the baud rate control registers UCAxBR0, UCAxBR1, and UCAxMCTL. If the length of the synch field exceeds the measurable time the synch timeout error flag UCSTOE is set. Figure 19−6. Auto Baud Rate Detection − Synch Field Synch 8 Bit Times Start Bit 0 1 2 3 4 5 6 7 Stop Bit The UCDORM bit is used to control data reception in this mode. When UCDORM is set, all characters are received but not transferred into the UCAxRXBUF, and interrupts are not generated. When a break/synch field is detected the UCBRK flag is set. The character following the break/synch field is transferred into UCAxRXBUF and the UCAxRXIFG interrupt flag is set. Any applicable error flag is also set. If the UCBRKIE bit is set, reception of the break/synch sets the UCAxRXIFG. The UCBRK bit is reset by user software or by reading the receive buffer UCAxRXBUF. 19-10 Universal Serial Communication Interface, UART Mode USCI Operation: UART Mode When a break/synch field is received, user software must reset UCDORM to continue receiving data. If UCDORM remains set, only the character after the next reception of a break/synch field will be received. The UCDORM bit is not modified by the USCI hardware automatically. When UCDORM = 0 all received characters will set the receive interrupt flag UCAxRXIFG. If UCDORM is cleared during the reception of a character the receive interrupt flag will be set after the reception is complete. The counter used to detect the baud rate is limited to 07FFFh (32767) counts. This means the minimum baud rate detectable is 488 Baud in oversampling mode and 30 Baud in low-frequency mode. The automatic baud rate detection mode can be used in a full-duplex communication system with some restrictions. The USCI can not transmit data while receiving the break/sync field and if a 0h byte with framing error is received any data transmitted during this time gets corrupted. The latter case can be discovered by checking the received data and the UCFE bit. Transmitting a Break/Synch Field The following procedure transmits a break/synch field: 1) Set UCTXBRK with UMODEx = 11. 2) Write 055h to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). This generates a break field of 13 bits followed by a break delimiter and the synch character. The length of the break delimiter is controlled with the UCDELIMx bits. UCTXBRK is reset automatically when the synch character is transferred from UCAxTXBUF into the shift register. 3) Write desired data characters to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). The data written to UCAxTXBUF is transferred to the shift register and transmitted as soon as the shift register is ready for new data. Universal Serial Communication Interface, UART Mode 19-11 USCI Operation: UART Mode 19.3.5 IrDA Encoding and Decoding When UCIREN is set the IrDA encoder and decoder are enabled and provide hardware bit shaping for IrDA communication. IrDA Encoding The encoder sends a pulse for every zero bit in the transmit bit stream coming from the UART as shown in Figure 19−7. The pulse duration is defined by UCIRTXPLx bits specifying the number of half clock periods of the clock selected by UCIRTXCLK. Figure 19−7. UART vs. IrDA Data Format Start Bit Data Bits Stop Bit UART IrDA IrDA Decoding To set the pulse time of 3/16 bit period required by the IrDA standard the BITCLK16 clock is selected with UCIRTXCLK = 1 and the pulse length is set to 6 half clock cycles with UCIRTXPLx = 6 − 1 = 5. When UCIRTXCLK = 0, the pulse length tPULSE is based on BRCLK and is calculated as follows: UCIRTXPLx + tPULSE 2 fBRCLK * 1 When the pulse length is based on BRCLK the prescaler UCBRx must to be set to a value greater or equal to 5. The decoder detects high pulses when UCIRRXPL = 0. Otherwise it detects low pulses. In addition to the analog deglitch filter an additional programmable digital filter stage can be enabled by setting UCIRRXFE. When UCIRRXFE is set, only pulses longer than the programmed filter length are passed. Shorter pulses are discarded. The equation to program the filter length UCIRRXFLx is: UCIRRXFLx + (tPULSE * tWAKE) 2 fBRCLK * 4 where: tPULSE: tWAKE: Minimum receive pulse width Wake time from any low power mode. Zero when MSP430 is in active mode. 19-12 Universal Serial Communication Interface, UART Mode USCI Operation: UART Mode 19.3.6 Automatic Error Detection Glitch suppression prevents the USCI from being accidentally started. Any pulse on UCAxRXD shorter than the deglitch time tτ (approximately 150 ns) will be ignored. See the device-specific data sheet for parameters. When a low period on UCAxRXD exceeds tτ a majority vote is taken for the start bit. If the majority vote fails to detect a valid start bit the USCI halts character reception and waits for the next low period on UCAxRXD. The majority vote is also used for each bit in a character to prevent bit errors. The USCI module automatically detects framing errors, parity errors, overrun errors, and break conditions when receiving characters. The bits UCFE, UCPE, UCOE, and UCBRK are set when their respective condition is detected. When the error flags UCFE, UCPE or UCOE are set, UCRXERR is also set. The error conditions are described in Table 19−1. Table 19−1.Receive Error Conditions Error Condition Error Flag Framing error UCFE Parity error UCPE Receive overrun UCOE Break condition UCBRK Description A framing error occurs when a low stop bit is detected. When two stop bits are used, both stop bits are checked for framing error. When a framing error is detected, the UCFE bit is set. A parity error is a mismatch between the number of 1s in a character and the value of the parity bit. When an address bit is included in the character, it is included in the parity calculation. When a parity error is detected, the UCPE bit is set. An overrun error occurs when a character is loaded into UCAxRXBUF before the prior character has been read. When an overrun occurs, the UCOE bit is set. When not using automatic baud rate detection, a break is detected when all data, parity, and stop bits are low. When a break condition is detected, the UCBRK bit is set. A break condition can also set the interrupt flag UCAxRXIFG if the break interrupt enable UCBRKIE bit is set. When UCRXEIE = 0 and a framing error, or parity error is detected, no character is received into UCAxRXBUF. When UCRXEIE = 1, characters are received into UCAxRXBUF and any applicable error bit is set. When UCFE, UCPE, UCOE, UCBRK, or UCRXERR is set, the bit remains set until user software resets it or UCAxRXBUF is read. UCOE must be reset by reading UCAxRXBUF. Otherwise it will not function properly. To detect overflows reliably the following flow is recommended. After a character was received and UCAxRXIFG is set, first read UCAxSTAT to check the error flags including the overflow flag UCOE. Read UCAxRXBUF next. This will clear all Universal Serial Communication Interface, UART Mode 19-13 USCI Operation: UART Mode error flags except UCOE if UCAxRXBUF was overwritten between the read access to UCAxSTAT and to UCAxRXBUF. So the UCOE flag should be checked after reading UCAxRXBUF to detect this condition. Note, in this case the UCRXERR flag is not set. 19.3.7 USCI Receive Enable The USCI module is enabled by clearing the UCSWRST bit and the receiver is ready and in an idle state. The receive baud rate generator is in a ready state but is not clocked nor producing any clocks. The falling edge of the start bit enables the baud rate generator and the UART state machine checks for a valid start bit. If no valid start bit is detected the UART state machine returns to its idle state and the baud rate generator is turned off again. If a valid start bit is detected a character will be received. When the idle-line multiprocessor mode is selected with UCMODEx = 01 the UART state machine checks for an idle line after receiving a character. If a start bit is detected another character is received. Otherwise the UCIDLE flag is set after 10 ones are received and the UART state machine returns to its idle state and the baud rate generator is turned off. 19.3.8 Receive Data Glitch Suppression Glitch suppression prevents the USCI from being accidentally started. Any glitch on UCAxRXD shorter than the deglitch time tτ (approximately 150 ns) will be ignored by the USCI and further action will be initiated as shown in Figure 19−8. See the device-specific data sheet for parameters. Figure 19−8. Glitch Suppression, USCI Receive Not Started URXDx URXS tτ When a glitch is longer than tτ, or a valid start bit occurs on UCAxRXD, the USCI receive operation is started and a majority vote is taken as shown in Figure 19−9. If the majority vote fails to detect a start bit the USCI halts character reception. 19-14 Universal Serial Communication Interface, UART Mode Figure 19−9. Glitch Suppression, USCI Activated Majority Vote Taken URXDx URXS tτ USCI Operation: UART Mode 19.3.9 USCI Transmit Enable The USCI module is enabled by clearing the UCSWRST bit and the transmitter is ready and in an idle state. The transmit baud rate generator is ready but is not clocked nor producing any clocks. A transmission is initiated by writing data to UCAxTXBUF. When this occurs, the baud rate generator is enabled and the data in UCAxTXBUF is moved to the transmit shift register on the next BITCLK after the transmit shift register is empty. UCAxTXIFG is set when new data can be written into UCAxTXBUF. Transmission continues as long as new data is available in UCAxTXBUF at the end of the previous byte transmission. If new data is not in UCAxTXBUF when the previous byte has transmitted, the transmitter returns to its idle state and the baud rate generator is turned off. 19.3.10 UART Baud Rate Generation The USCI baud rate generator is capable of producing standard baud rates from non-standard source frequencies. It provides two modes of operation selected by the UCOS16 bit. Low-Frequency Baud Rate Generation The low-frequency mode is selected when UCOS16 = 0. This mode allows generation of baud rates from low frequency clock sources (e.g. 9600 baud from a 32768Hz crystal). By using a lower input frequency the power consumption of the module is reduced. Using this mode with higher frequencies and higher prescaler settings will cause the majority votes to be taken in an increasingly smaller window and thus decrease the benefit of the majority vote. In low-frequency mode the baud rate generator uses one prescaler and one modulator to generate bit clock timing. This combination supports fractional divisors for baud rate generation. In this mode, the maximum USCI baud rate is one-third the UART source clock frequency BRCLK. Timing for each bit is shown in Figure 19−10. For each bit received, a majority vote is taken to determine the bit value. These samples occur at the N/2 − 1/2, N/2, and N/2 + 1/2 BRCLK periods, where N is the number of BRCLKs per BITCLK. Universal Serial Communication Interface, UART Mode 19-15 USCI Operation: UART Mode Figure 19−10. BITCLK Baud Rate Timing with UCOS16 = 0 Bit Start BRCLK Counter BITCLK Majority Vote: (m= 0) (m= 1) N/2 N/2−1 N/2−2 1 N/2 N/2−1 N/2−2 1 0 N/2 N/2−1 1 N/2 N/2−1 1 0 N/2 INT(N/2) + m(= 0) INT(N/2) + m(= 1) m: corresponding modulation bit R: Remainder from N/2 division Bit Period NEVEN: INT(N/2) NODD : INT(N/2) + R(= 1) Modulation is based on the UCBRSx setting as shown in Table 19−2. A 1 in the table indicates that m = 1 and the corresponding BITCLK period is one BRCLK period longer than a BITCLK period with m = 0. The modulation wraps around after 8 bits but restarts with each new start bit. Table 19−2.BITCLK Modulation Pattern UCBRSx Bit 0 (Start Bit) 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 Bit 1 0 1 1 1 1 1 1 1 Bit 2 0 0 0 0 0 1 1 1 Bit 3 0 0 0 1 1 1 1 1 Bit 4 0 0 0 0 0 0 0 1 Bit 5 0 0 1 1 1 1 1 1 Bit 6 0 0 0 0 0 0 1 1 Bit 7 0 0 0 0 1 1 1 1 Oversampling Baud Rate Generation The oversampling mode is selected when UCOS16 = 1. This mode supports sampling a UART bit stream with higher input clock frequencies. This results in majority votes that are always 1/16 of a bit clock period apart. This mode also easily supports IrDA pulses with a 3/16 bit-time when the IrDA encoder and decoder are enabled. This mode uses one prescaler and one modulator to generate the BITCLK16 clock that is 16 times faster than the BITCLK. An additional divider and modulator stage generates BITCLK from BITCLK16. This combination supports fractional divisions of both BITCLK16 and BITCLK for baud rate 19-16 Universal Serial Communication Interface, UART Mode USCI Operation: UART Mode generation. In this mode, the maximum USCI baud rate is 1/16 the UART source clock frequency BRCLK. When UCBRx is set to 0 or 1 the first prescaler and modulator stage is bypassed and BRCLK is equal to BITCLK16. Modulation for BITCLK16 is based on the UCBRFx setting as shown in Table 19−3. A 1 in the table indicates that the corresponding BITCLK16 period is one BRCLK period longer than the periods m=0. The modulation restarts with each new bit timing. Modulation for BITCLK is based on the UCBRSx setting as shown in Table 19−2 as previously described. Table 19−3.BITCLK16 Modulation Pattern UCBRFx 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Number of BITCLK16 Clocks After Last Falling BITCLK Edge 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000000000000000 0100000000000000 0100000000000001 0110000000000001 0110000000000011 0111000000000011 0111000000000111 0111100000000111 0111100000001111 0111110000001111 0111110000011111 0111111000011111 0111111000111111 0111111100111111 0111111101111111 0111111111111111 Universal Serial Communication Interface, UART Mode 19-17 USCI Operation: UART Mode 19.3.11 Setting a Baud Rate For a given BRCLK clock source, the baud rate used determines the required division factor N: N + fBRCLK Baudrate The division factor N is often a non-integer value thus at least one divider and one modulator stage is used to meet the factor as closely as possible. If N is equal or greater than 16 the oversampling baud rate generation mode can be chosen by setting UCOS16. Low-Frequency Baud Rate Mode Setting In the low-frequency mode, the integer portion of the divisor is realized by the prescaler: UCBRx = INT(N) and the fractional portion is realized by the modulator with the following nominal formula: UCBRSx = round( ( N − INT(N) ) × 8 ) Incrementing or decrementing the UCBRSx setting by one count may give a lower maximum bit error for any given bit. To determine if this is the case, a detailed error calculation must be performed for each bit for each UCBRSx setting. Oversampling Baud Rate Mode Setting In the oversampling mode the prescaler is set to: UCBRx = INT(N/16). and the first stage modulator is set to: UCBRFx = round( ( (N/16) − INT(N/16) ) × 16 ) When greater accuracy is required, the UCBRSx modulator can also be implemented with values from 0 − 7. To find the setting that gives the lowest maximum bit error rate for any given bit, a detailed error calculation must be performed for all settings of UCBRSx from 0 − 7 with the initial UCBRFx setting and with the UCBRFx setting incremented and decremented by one. 19-18 Universal Serial Communication Interface, UART Mode USCI Operation: UART Mode 19.3.12 Transmit Bit Timing The timing for each character is the sum of the individual bit timings. Using the modulation features of the baud rate generator reduces the cumulative bit error. The individual bit error can be calculated using the following steps. Low−Frequency Baud Rate Mode Bit Timing In low-frequency mode, calculate the length of bit i Tbit,TX[i] based on the UCBRx and UCBRSx settings: Tbit,TX[i] + 1 fBRCLK ǒUCBRx ) mUCBRSx[i]Ǔ where: mUCBRSx[i]: Modulation of bit i from Table 19−2 Oversampling Baud Rate Mode Bit Timing In oversampling baud rate mode calculate the length of bit i Tbit,TX[i] based on the baud rate generator UCBRx, UCBRFx and UCBRSx settings: ǒ ȍ Ǔ 15 Tbit,TX[i] + 1 fBRCLK ǒ16 ) mUCBRSx[i]Ǔ @ UCBRx ) mUCBRFx[j] j+0 where: ȍ15 mUCBRFx[j]: j+0 mUCBRSx[i]: Sum of ones from the corresponding row in Table 19−3 Modulation of bit i from Table 19−2 This results in an end-of-bit time tbit,TX[i] equal to the sum of all previous and the current bit times: ȍi tbit,TX[i] + Tbit,TX[j] j+0 To calculate bit error, this time is compared to the ideal bit time tbit,ideal,TX[i]: tbit,ideal,TX[i] + 1 Baudrate (i ) 1) This results in an error normalized to one ideal bit time (1/baudrate): ErrorTX[i] + ǒtbit,TX[i] * Ǔ tbit,ideal,TX[i] @ Baudrate @ 100% Universal Serial Communication Interface, UART Mode 19-19 USCI Operation: UART Mode 19.3.13 Receive Bit Timing Receive timing error consists of two error sources. The first is the bit-to-bit timing error similar to the transmit bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USCI module. Figure 19−11 shows the asynchronous timing errors between data on the UCAxRXD pin and the internal baud-rate clock. This results in an additional synchronization error. The synchronization error tSYNC is between −0.5 BRCLKs and +0.5 BRCLKs, independent of the selected baud rate generation mode. Figure 19−11.Receive Error i tideal BRCLK 0 1 2 t0 t1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 UCAxRXD ST D0 D1 RXD synch. ST D0 D1 tactual t0 t1 t2 Synchronization Error ± 0.5x BRCLK Sample RXD synch. Majority Vote Taken Majority Vote Taken Majority Vote Taken The ideal sampling time tbit,ideal,RX[i] is in the middle of a bit period: tbit,ideal,RX[i] + 1 Baudrate (i ) 0.5) The real sampling time tbit,RX[i] is equal to the sum of all previous bits according to the formulas shown in the transmit timing section, plus one half BITCLK for the current bit i, plus the synchronization error tSYNC. This results in the following tbit,RX[i] for the low-frequency baud rate mode ȍ ǒ Ǔ i*1 tbit,RX[i] + tSYNC ) j+0 Tbit,RX[j] ) 1 fBRCLK INT(12 UCBRx) ) mUCBRSx[i] where: Tbit,RX[i] + 1 fBRCLK ǒUCBRx ) mUCBRSx[i]Ǔ mUCBRSx[i]: Modulation of bit i from Table 19−2 19-20 Universal Serial Communication Interface, UART Mode USCI Operation: UART Mode For the oversampling baud rate mode the sampling time tbit,RX[i] of bit i is calculated by: ȍi*1 tbit,RX[i] + tSYNC ) Tbit,RX[j] j+0 ǒ ȍ Ǔ ) 1 fBRCLK 7)mUCBRSx[i] ǒ8 ) mUCBRSx[i]Ǔ @ UCBRx ) mUCBRFx[j] j+0 where: ǒ ȍ Ǔ 15 Tbit,RX[i] + 1 fBRCLK ǒ16 ) mUCBRSx[i]Ǔ @ UCBRx ) mUCBRFx[j] j+0 ȍ 7)mUCBRSx[i] mUCBRFx[j]: j+0 Sum of ones from columns 0 − 7 ) mUCBRSx[i] from the corresponding row in Table 19−3 mUCBRSx[i]: Modulation of bit i from Table 19−2 This results in an error normalized to one ideal bit time (1/baudrate) according to the following formula: ErrorRX[i] + ǒtbit,RX[i] * Ǔ tbit,ideal,RX[i] @ Baudrate @ 100% 19.3.14 Typical Baud Rates and Errors Standard baud rate data for UCBRx, UCBRSx and UCBRFx are listed in Table 19−4 and Table 19−5 for a 32,768 Hz crystal sourcing ACLK and typical SMCLK frequencies. Please ensure that the selected BRCLK frequency does not exceed the device specific maximum USCI input frequency. Please refer to the device-specific data sheet. The receive error is the accumulated time versus the ideal scanning time in the middle of each bit. The worst case error is given for the reception of an 8-bit character with parity and one stop bit including synchronization error. The transmit error is the accumulated timing error versus the ideal time of the bit period. The worst case error is given for the transmission of an 8-bit character with parity and stop bit. Universal Serial Communication Interface, UART Mode 19-21 USCI Operation: UART Mode Table 19−4.Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 BRCLK Frequency [Hz] 32,768 32,768 32,768 32,768 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,048,576 1,048,576 1,048,576 1,048,576 1,048,576 4,000,000 4,000,000 4,000,000 4,000,000 4,000,000 4,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 12,000,000 12,000,000 12,000,000 12,000,000 12,000,000 12,000,000 12,000,000 Baud Rate [Baud] 1200 2400 4800 9600 9600 19200 38400 57600 115200 9600 19200 38400 57600 115200 9600 19200 38400 57600 115200 230400 9600 19200 38400 57600 115200 230400 460800 9600 19200 38400 57600 115200 230400 460800 UCBRx UCBRSx UCBRFx Max TX Error [%] Max RX Error [%] 27 2 13 6 6 7 3 3 104 1 52 0 26 0 17 3 8 6 109 2 54 5 27 2 18 1 9 1 416 6 208 3 104 1 69 4 34 6 17 3 833 2 416 6 208 3 138 7 69 4 34 6 17 3 1250 0 625 0 312 4 208 2 104 1 52 0 26 0 0 −2.8 1.4 −5.9 2.0 0 −4.8 6.0 −9.7 8.3 0 −12.1 5.7 −13.4 19.0 0 −21.1 15.2 −44.3 21.3 0 −0.5 0.6 −0.9 1.2 0 −1.8 0 −2.6 0.9 0 −1.8 0 −3.6 1.8 0 −2.1 4.8 −6.8 5.8 0 −7.8 6.4 −9.7 16.1 0 −0.2 0.7 −1.0 0.8 0 −1.1 1.0 −1.5 2.5 0 −2.8 1.4 −5.9 2.0 0 −4.6 3.3 −6.8 6.6 0 −1.1 10.7 −11.5 11.3 0 −0.2 0.2 −0.2 0.4 0 −0.2 0.5 −0.3 0.8 0 −0.5 0.6 −0.9 1.2 0 −0.6 0.8 −1.8 1.1 0 −2.1 0.6 −2.5 3.1 0 −2.1 4.8 −6.8 5.8 0 −0.1 0 −0.2 0.1 0 −0.2 0.2 −0.2 0.4 0 −0.2 0.5 −0.3 0.8 0 −0.7 0 −0.8 0.6 0 −0.6 0.8 −1.8 1.1 0 −2.1 0.6 −2.5 3.1 0 −2.1 4.8 −6.8 5.8 0 0 0 −0.05 0.05 0 0 0 −0.2 0 0 −0.2 0 −0.2 0.2 0 −0.5 0.2 −0.6 0.5 0 −0.5 0.6 −0.9 1.2 0 −1.8 0 −2.6 0.9 0 −1.8 0 −3.6 1.8 19-22 Universal Serial Communication Interface, UART Mode USCI Operation: UART Mode Table 19−4.Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 (Continued) BRCLK Frequency [Hz] 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 Baud Rate [Baud] 9600 19200 38400 57600 115200 230400 460800 UCBRx UCBRSx UCBRFx Max TX Error [%] Max RX Error [%] 1666 6 833 2 416 6 277 7 138 7 69 4 34 6 0 −0.05 0.05 −0.05 0.1 0 −0.1 0.05 −0.2 0.1 0 −0.2 0.2 −0.2 0.4 0 −0.3 0.3 −0.5 0.4 0 −0.7 0 −0.8 0.6 0 −0.6 0.8 −1.8 1.1 0 −2.1 0.6 −2.5 3.1 Universal Serial Communication Interface, UART Mode 19-23 USCI Operation: UART Mode Table 19−5.Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1 BRCLK frequency [Hz] 1,000,000 1,000,000 1,048,576 1,048,576 4,000,000 4,000,000 4,000,000 4,000,000 4,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 12,000,000 12,000,000 12,000,000 12,000,000 12,000,000 12,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 Baud Rate [Baud] 9600 19200 9600 19200 9600 19200 38400 57600 115200 9600 19200 38400 57600 115200 230400 9600 19200 38400 57600 115200 230400 9600 19200 38400 57600 115200 230400 460800 UCBRx UCBRSx UCBRFx Max. TX Error [%] Max. RX Error [%] 6 0 3 0 6 0 3 1 26 0 13 0 6 0 4 5 2 3 52 0 26 0 13 0 8 0 4 5 2 3 78 0 39 0 19 0 13 0 6 0 3 0 104 0 52 0 26 0 17 0 8 0 4 5 2 3 8 −1.8 0 −2.2 0.4 4 −1.8 0 −2.6 0.9 13 −2.3 0 −2.2 0.8 6 −4.6 3.2 −5.0 4.7 1 0 0.9 0 1.1 0 −1.8 0 −1.9 0.2 8 −1.8 0 −2.2 0.4 3 −3.5 3.2 −1.8 6.4 2 −2.1 4.8 −2.5 7.3 1 −0.4 0 −0.4 0.1 1 0 0.9 0 1.1 0 −1.8 0 −1.9 0.2 11 0 0.88 0 1.6 3 −3.5 3.2 −1.8 6.4 2 −2.1 4.8 −2.5 7.3 2 0 0 −0.05 0.05 1 0 0 0 0.2 8 −1.8 0 −1.8 0.1 0 −1.8 0 −1.9 0.2 8 −1.8 0 −2.2 0.4 4 −1.8 0 −2.6 0.9 3 0 0.2 0 0.3 1 −0.4 0 −0.4 0.1 1 0 0.9 0 1.1 6 0 0.9 −0.1 1.0 11 0 0.9 0 1.6 3 −3.5 3.2 −1.8 6.4 2 −2.1 4.8 −2.5 7.3 19-24 Universal Serial Communication Interface, UART Mode USCI Operation: UART Mode 19.3.15 Using the USCI Module in UART Mode with Low-Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition. After the USCI module returns to the idle condition, control of the clock source reverts to the settings of its control bits. Automatic clock activation is not provided for ACLK. When the USCI module activates an inactive clock source, the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected. For example, a timer using SMCLK will increment while the USCI module forces SMCLK active. 19.3.16 USCI Interrupts The USCI has one interrupt vector for transmission and one interrupt vector for reception. USCI Transmit Interrupt Operation The UCAxTXIFG interrupt flag is set by the transmitter to indicate that UCAxTXBUF is ready to accept another character. An interrupt request is generated if UCAxTXIE and GIE are also set. UCAxTXIFG is automatically reset if a character is written to UCAxTXBUF. UCAxTXIFG is set after a PUC or when UCSWRST = 1. UCAxTXIE is reset after a PUC or when UCSWRST = 1. USCI Receive Interrupt Operation The UCAxRXIFG interrupt flag is set each time a character is received and loaded into UCAxRXBUF. An interrupt request is generated if UCAxRXIE and GIE are also set. UCAxRXIFG and UCAxRXIE are reset by a system reset PUC signal or when UCSWRST = 1. UCAxRXIFG is automatically reset when UCAxRXBUF is read. Additional interrupt control features include: - When UCAxRXEIE = 0 erroneous characters will not set UCAxRXIFG. - When UCDORM = 1, non-address characters will not set UCAxRXIFG in multiprocessor modes. In plain UART mode no characters will set UCAxRXIFG. - When UCBRKIE = 1 a break condition will set the UCBRK bit and the UCAxRXIFG flag. Universal Serial Communication Interface, UART Mode 19-25 USCI Operation: UART Mode USCI Interrupt Usage USCI_Ax and USCI_Bx share the same interrupt vectors. The receive interrupt flags UCAxRXIFG and UCBxRXIFG are routed to one interrupt vector, the transmit interrupt flags UCAxTXIFG and UCBxTXIFG share another interrupt vector. Shared Interrupt Vectors Software Example The following software example shows an extract of an interrupt service routine to handle data receive interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode. USCIA0_RX_USCIB0_RX_ISR BIT.B #UCA0RXIFG, &IFG2 ; USCI_A0 Receive Interrupt? JNZ USCIA0_RX_ISR USCIB0_RX_ISR? ; Read UCB0RXBUF (clears UCB0RXIFG) ... RETI USCIA0_RX_ISR ; Read UCA0RXBUF (clears UCA0RXIFG) ... RETI The following software example shows an extract of an interrupt service routine to handle data transmit interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode. USCIA0_TX_USCIB0_TX_ISR BIT.B #UCA0TXIFG, &IFG2 ; USCI_A0 Transmit Interrupt? JNZ USCIA0_TX_ISR USCIB0_TX_ISR ; Write UCB0TXBUF (clears UCB0TXIFG) ... RETI USCIA0_TX_ISR ; Write UCA0TXBUF (clears UCA0TXIFG) ... RETI 19-26 Universal Serial Communication Interface, UART Mode USCI Registers: UART Mode 19.4 USCI Registers: UART Mode The USCI registers applicable in UART mode are listed in Table 19−6 and Table 19−7. Table 19−6.USCI_A0 Control and Status Registers Register USCI_A0 control register 0 USCI_A0 control register 1 USCI_A0 Baud rate control register 0 USCI_A0 Baud rate control register 1 USCI_A0 modulation control register USCI_A0 status register USCI_A0 Receive buffer register USCI_A0 Transmit buffer register USCI_A0 Auto Baud control register USCI_A0 IrDA Transmit control register USCI_A0 IrDA Receive control register SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form UCA0CTL0 UCA0CTL1 UCA0BR0 UCA0BR1 UCA0MCTL UCA0STAT UCA0RXBUF UCA0TXBUF UCA0ABCTL UCA0IRTCTL UCA0IRRCTL IE2 IFG2 Register Type Address Read/write 060h Read/write 061h Read/write 062h Read/write 063h Read/write 064h Read/write 065h Read 066h Read/write 067h Read/write 05Dh Read/write 05Eh Read/write 05Fh Read/write 001h Read/write 003h Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC Note: Modifying SFR bits To avoid modifying control bits of other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. Table 19−7.USCI_A1 Control and Status Registers Register USCI_A1 control register 0 USCI_A1 control register 1 USCI_A1 Baud rate control register 0 USCI_A1 Baud rate control register 1 USCI_A1 modulation control register USCI_A1 status register USCI_A1 Receive buffer register USCI_A1 Transmit buffer register USCI_A1 Auto Baud control register USCI_A1 IrDA Transmit control register USCI_A1 IrDA Receive control register USCI_A1/B1 interrupt enable register USCI_A1/B1 interrupt flag register Short Form UCA1CTL0 UCA1CTL1 UCA1BR0 UCA1BR1 UCA1MCTL UCA1STAT UCA1RXBUF UCA1TXBUF UCA1ABCTL UCA1IRTCTL UCA1IRRCTL UC1IE UC1IFG Register Type Address Read/write 0D0h Read/write 0D1h Read/write 0D2h Read/write 0D3h Read/write 0D4h Read/write 0D5h Read 0D6h Read/write 0D7h Read/write 0CDh Read/write 0CEh Read/write 0CFh Read/write 006h Read/write 007h Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC Universal Serial Communication Interface, UART Mode 19-27 USCI Registers: UART Mode UCAxCTL0, USCI_Ax Control Register 0 7 UCPEN rw−0 6 UCPAR rw−0 5 UCMSB rw−0 4 UC7BIT rw−0 3 UCSPB rw−0 2 1 UCMODEx rw−0 rw−0 0 UCSYNC=0 rw−0 UCPEN Bit 7 UCPAR Bit 6 UCMSB Bit 5 UC7BIT Bit 4 UCSPB Bit 3 UCMODEx Bits 2−1 UCSYNC Bit 0 Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. Parity select. UCPAR is not used when parity is disabled. 0 Odd parity 1 Even parity MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data Stop bit select. Number of stop bits. 0 One stop bit 1 Two stop bits USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. 00 UART Mode. 01 Idle-Line Multiprocessor Mode. 10 Address-Bit Multiprocessor Mode. 11 UART Mode with automatic baud rate detection. Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode 19-28 Universal Serial Communication Interface, UART Mode UCAxCTL1, USCI_Ax Control Register 1 USCI Registers: UART Mode 7 6 UCSSELx rw−0 rw−0 5 UCRXEIE rw−0 4 UCBRKIE rw−0 3 2 1 0 UCDORM UCTXADDR UCTXBRK UCSWRST rw−0 rw−0 rw−0 rw−1 UCSSELx Bits 7-6 UCRXEIE Bit 5 UCBRKIE Bit 4 UCDORM Bit 3 UCTXADDR Bit 2 UCTXBRK Bit 1 UCSWRST Bit 0 USCI clock source select. These bits select the BRCLK source clock. 00 UCLK 01 ACLK 10 SMCLK 11 SMCLK Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and UCAxRXIFG is not set 1 Erroneous characters received will set UCAxRXIFG Receive break character interrupt-enable 0 Received break characters do not set UCAxRXIFG. 1 Received break characters set UCAxRXIFG. Dormant. Puts USCI into sleep mode. 0 Not dormant. All received characters will set UCAxRXIFG. 1 Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG. Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. 0 Next frame transmitted is data 1 Next frame transmitted is an address Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer. 0 Next frame transmitted is not a break 1 Next frame transmitted is a break or a break/synch Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state. Universal Serial Communication Interface, UART Mode 19-29 USCI Registers: UART Mode UCAxBR0, USCI_Ax Baud Rate Control Register 0 7 6 5 4 3 2 1 0 UCBRx − low byte rw rw rw rw rw rw rw rw UCAxBR1, USCI_Ax Baud Rate Control Register 1 7 6 5 4 3 2 1 0 UCBRx − high byte rw rw rw rw rw rw rw rw UCBRx Clock prescaler setting of the Baud rate generator. The 16-bit value of (UCAxBR0 + UCAxBR1 × 256) forms the prescaler value UCBRx. UCAxMCTL, USCI_Ax Modulation Control Register 7 rw−0 6 5 UCBRFx rw−0 rw−0 4 rw−0 3 rw−0 2 UCBRSx rw−0 1 rw−0 0 UCOS16 rw−0 UCBRFx UCBRSx UCOS16 Bits 7−4 Bits 3−1 Bit 0 First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0. Table 19−3 shows the modulation pattern. Second modulation stage select. These bits determine the modulation pattern for BITCLK. Table 19−2 shows the modulation pattern. Oversampling mode enabled 0 Disabled 1 Enabled 19-30 Universal Serial Communication Interface, UART Mode UCAxSTAT, USCI_Ax Status Register 7 UCLISTEN rw−0 6 UCFE rw−0 5 UCOE rw−0 4 UCPE rw−0 USCI Registers: UART Mode 3 UCBRK rw−0 2 UCRXERR rw−0 1 UCADDR UCIDLE rw−0 0 UCBUSY r−0 UCLISTEN Bit 7 UCFE Bit 6 UCOE Bit 5 UCPE Bit 4 UCBRK Bit 3 UCRXERR Bit 2 UCADDR Bit 1 UCIDLE UCBUSY Bit 0 Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver. Framing error flag 0 No error 1 Character received with low stop bit Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred Parity error flag. When UCPEN = 0, UCPE is read as 0. 0 No error 1 Character received with parity error Break detect flag 0 No break condition 1 Break condition occurred Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read. 0 No receive errors detected 1 Receive error detected Address received in address-bit multiprocessor mode. 0 Received character is data 1 Received character is an address Idle line detected in idle-line multiprocessor mode. 0 No idle line detected 1 Idle line detected USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving Universal Serial Communication Interface, UART Mode 19-31 USCI Registers: UART Mode UCAxRXBUF, USCI_Ax Receive Buffer Register 7 6 5 4 3 2 1 0 UCRXBUFx r r r r r r r r UCRXBUFx Bits 7−0 The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCAxRXBUF resets the receive-error bits, the UCADDR or UCIDLE bit, and UCAxRXIFG. In 7-bit data mode, UCAxRXBUF is LSB justified and the MSB is always reset. UCAxTXBUF, USCI_Ax Transmit Buffer Register 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw UCTXBUFx Bits 7−0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UCAxTXD. Writing to the transmit data buffer clears UCAxTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data and is reset. 19-32 Universal Serial Communication Interface, UART Mode UCAxIRTCTL, USCI_Ax IrDA Transmit Control Register USCI Registers: UART Mode 7 rw−0 6 rw−0 5 4 UCIRTXPLx rw−0 rw−0 3 rw−0 2 rw−0 1 UCIR TXCLK rw−0 0 UCIREN rw−0 UCIRTXPLx UCIRTXCLK Bits 7−2 Bit 1 UCIREN Bit 0 Transmit pulse length Pulse Length tPULSE = (UCIRTXPLx + 1) / (2 × fIRTXCLK) IrDA transmit pulse clock select 0 BRCLK 1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK IrDA encoder/decoder enable. 0 IrDA encoder/decoder disabled 1 IrDA encoder/decoder enabled UCAxIRRCTL, USCI_Ax IrDA Receive Control Register 7 rw−0 6 rw−0 5 4 UCIRRXFLx rw−0 rw−0 3 rw−0 2 rw−0 1 0 UCIRRXPL UCIRRXFE rw−0 rw−0 UCIRRXFLx UCIRRXPL Bits 7−2 Bit 1 UCIRRXFE Bit 0 Receive filter length. The minimum pulse length for receive is given by: tMIN = (UCIRRXFLx + 4) / (2 × fBRCLK) IrDA receive input UCAxRXD polarity 0 IrDA transceiver delivers a high pulse when a light pulse is seen 1 IrDA transceiver delivers a low pulse when a light pulse is seen IrDA receive filter enabled 0 Receive filter disabled 1 Receive filter enabled Universal Serial Communication Interface, UART Mode 19-33 USCI Registers: UART Mode UCAxABCTL, USCI_Ax Auto Baud Rate Control Register 7 6 Reserved 5 4 UCDELIMx 3 UCSTOE 2 UCBTOE r−0 r−0 rw−0 rw−0 rw−0 rw−0 1 0 Reserved UCABDEN r−0 rw−0 Reserved Bits 7-6 UCDELIMx Bits 5−4 UCSTOE Bit 3 UCBTOE Bit 2 Reserved UCABDEN Bit 1 Bit 0 Reserved Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times Synch field time out error 0 No error 1 Length of synch field exceeded measurable time. Break time out error 0 No error 1 Length of break field exceeded 22 bit times. Reserved Automatic baud rate detect enable 0 Baud rate detection disabled. Length of break and synch field is not measured. 1 Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly. 19-34 Universal Serial Communication Interface, UART Mode USCI Registers: UART Mode IE2, Interrupt Enable Register 2 7 6 5 4 3 2 1 0 UCA0TXIE UCA0RXIE rw−0 rw−0 UCA0TXIE Bits 7-2 Bit 1 UCA0RXIE Bit 0 These bits may be used by other modules. See device-specific data sheet. USCI_A0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled IFG2, Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UCA0 TXIFG UCA0 RXIFG rw−1 rw−0 UCA0 TXIFG UCA0 RXIFG Bits 7-2 Bit 1 Bit 0 These bits may be used by other modules (see the device-specific data sheet). USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending Universal Serial Communication Interface, UART Mode 19-35 USCI Registers: UART Mode UC1IE, USCI_A1 Interrupt Enable Register 7 6 5 4 3 Unused Unused Unused Unused rw−0 rw−0 rw−0 rw−0 2 1 0 UCA1TXIE UCA1RXIE rw−0 rw−0 Unused UCA1TXIE Bits 7-4 Bits 3-2 Bit 1 UCA1RXIE Bit 0 Unused These bits may be used by other USCI modules (see the device-specific data sheet). USCI_A1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled UC1IFG, USCI_A1 Interrupt Flag Register 7 6 5 4 3 Unused Unused Unused Unused rw−0 rw−0 rw−0 rw−0 2 1 0 UCA1 TXIFG UCA1 RXIFG rw−1 rw−0 Unused UCA1 TXIFG UCA1 RXIFG Bits 7-4 Bits 3-2 Bit 1 Bit 0 Unused These bits may be used by other USCI modules (see the device-specific data sheet). USCI_A1 transmit interrupt flag. UCA1TXIFG is set when UCA1TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_A1 receive interrupt flag. UCA1RXIFG is set when UCA1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending 19-36 Universal Serial Communication Interface, UART Mode Chapter 20 Universal Serial Communication Interface, SPI Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. Topic Page 20.1 USCI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.2 USCI Introduction: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3 USCI Operation: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.4 USCI Registers: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 Universal Serial Communication Interface, SPI Mode 20-1 USCI Overview 20.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers. For example, if one device has two USCI_A modules, they are named USCI_A0 and USCI_A1. See the device-specific data sheet to determine which USCI modules, if any, are implemented on which devices. The USCI_Ax modules support: - UART mode - Pulse shaping for IrDA communications - Automatic baud rate detection for LIN communications - SPI mode The USCI_Bx modules support: - I2C mode - SPI mode 20-2 Universal Serial Communication Interface, SPI Mode USCI Introduction: SPI Mode 20.2 USCI Introduction: SPI Mode In synchronous mode, the USCI connects the MSP430 to an external system via three or four pins: UCxSIMO, UCxSOMI, UCxCLK, and UCxSTE. SPI mode is selected when the UCSYNC bit is set and SPI mode (3-pin or 4-pin) is selected with the UCMODEx bits. SPI mode features include: - 7- or 8-bit data length - LSB-first or MSB-first data transmit and receive - 3-pin and 4-pin SPI operation - Master or slave modes - Independent transmit and receive shift registers - Separate transmit and receive buffer registers - Continuous transmit and receive operation - Selectable clock polarity and phase control - Programmable clock frequency in master mode - Independent interrupt capability for receive and transmit - Slave operation in LPM4 Figure 20−1 shows the USCI when configured for SPI mode. Universal Serial Communication Interface, SPI Mode 20-3 USCI Introduction: SPI Mode Figure 20−1. USCI Block Diagram: SPI Mode Receive State Machine Receive Buffer UCxRXBUF Receive Shift Register UCMSB UC7BIT Set UCOE Set UCxRXIFG UCLISTEN UCMST UCxSOMI 1 0 0 1 UCSSELx Bit Clock Generator N/A ACLK SMCLK SMCLK UCxBRx 00 01 10 BRCLK 16 Prescaler/Divider 11 UCCKPH UCCKPL Clock Direction, Phase and Polarity UCxCLK UCMSB UC7BIT Transmit Shift Register Transmit Buffer UCxTXBUF Transmit State Machine UCMODEx 2 Transmit Enable Control UCxSIMO UCxSTE Set UCFE Set UCxTXIFG 20-4 Universal Serial Communication Interface, SPI Mode USCI Operation: SPI Mode 20.3 USCI Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, UCxSTE, is provided to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: - UCxSIMO Slave in, master out Master mode: UCxSIMO is the data output line. Slave mode: UCxSIMO is the data input line. - UCxSOMI Slave out, master in Master mode: UCxSOMI is the data input line. Slave mode: UCxSOMI is the data output line. - UCxCLK USCI SPI clock Master mode: UCxCLK is an output. Slave mode: UCxCLK is an input. - UCxSTE Slave transmit enable. Used in 4-pin mode to allow multiple masters on a single bus. Not used in 3-pin mode. Table 20−1 describes the UCxSTE operation. Table 20−1.UCxSTE Operation UCMODEx UCxSTE Active State 01 high 10 low UCxSTE 0 1 0 1 Slave inactive active active inactive Master active inactive inactive active Universal Serial Communication Interface, SPI Mode 20-5 USCI Operation: SPI Mode 20.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition. When set, the UCSWRST bit resets the UCxRXIE, UCxTXIE, UCxRXIFG, UCOE, and UCFE bits and sets the UCxTXIFG flag. Clearing UCSWRST releases the USCI for operation. Note: Initializing or Re-Configuring the USCI Module The recommended USCI initialization/re-configuration process is: 1) Set UCSWRST (BIS.B #UCSWRST,&UCxCTL1) 2) Initialize all USCI registers with UCSWRST=1 (including UCxCTL1) 3) Configure ports. 4) Clear UCSWRST via software (BIC.B #UCSWRST,&UCxCTL1) 5) Enable interrupts (optional) via UCxRXIE and/or UCxTXIE 20.3.2 Character Format The USCI module in SPI mode supports 7- and 8-bit character lengths selected by the UC7BIT bit. In 7-bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. The UCMSB bit controls the direction of the transfer and selects LSB or MSB first. Note: Default Character Format The default SPI character transmission is LSB first. For communication with other SPI interfaces it MSB-first mode may be required. Note: Character Format for Figures Figures throughout this chapter use MSB first format. 20-6 Universal Serial Communication Interface, SPI Mode 20.3.3 Master Mode Figure 20−2. USCI Master and External Slave USCI Operation: SPI Mode MASTER UCxSIMO Receive Buffer UCxRXBUF Transmit Buffer UCxTXBUF Px.x UCxSTE Receive Shift Register Transmit Shift Register UCx SOMI SIMO SLAVE SPI Receive Buffer STE SS Port.x SOMI Data Shift Register (DSR) MSP430 USCI UCxCLK SCLK COMMON SPI Figure 20−2 shows the USCI as a master in both 3-pin and 4-pin configurations. The USCI initiates data transfer when data is moved to the transmit data buffer UCxTXBUF. The UCxTXBUF data is moved to the TX shift register when the TX shift register is empty, initiating data transfer on UCxSIMO starting with either the most-significant or least-significant bit depending on the UCMSB setting. Data on UCxSOMI is shifted into the receive shift register on the opposite clock edge. When the character is received, the receive data is moved from the RX shift register to the received data buffer UCxRXBUF and the receive interrupt flag, UCxRXIFG, is set, indicating the RX/TX operation is complete. A set transmit interrupt flag, UCxTXIFG, indicates that data has moved from UCxTXBUF to the TX shift register and UCxTXBUF is ready for new data. It does not indicate RX/TX completion. To receive data into the USCI in master mode, data must be written to UCxTXBUF because receive and transmit operations operate concurrently. Universal Serial Communication Interface, SPI Mode 20-7 USCI Operation: SPI Mode Four-Pin SPI Master Mode In 4-pin master mode, UCxSTE is used to prevent conflicts with another master and controls the master as described in Table 20−1. When UCxSTE is in the master-inactive state: - UCxSIMO and UCxCLK are set to inputs and no longer drive the bus - The error bit UCFE is set indicating a communication integrity violation to be handled by the user. - The internal state machines are reset and the shift operation is aborted. If data is written into UCxTXBUF while the master is held inactive by UCxSTE, it will be transmit as soon as UCxSTE transitions to the master-active state. If an active transfer is aborted by UCxSTE transitioning to the master-inactive state, the data must be re-written into UCxTXBUF to be transferred when UCxSTE transitions back to the master-active state. The UCxSTE input signal is not used in 3-pin master mode. 20-8 Universal Serial Communication Interface, SPI Mode 20.3.4 Slave Mode Figure 20−3. USCI Slave and External Master USCI Operation: SPI Mode MASTER SIMO SPI Receive Buffer Px.x STE SOMI Data Shift Register DSR UCxSIMO SLAVE Transmit Buffer UCxTXBUF Receive Buffer UCxRXBUF UCxSTE SS Port.x UCx SOMI Transmit Shift Register Receive Shift Register SCLK COMMON SPI UCxCLK MSP430 USCI Figure 20−3 shows the USCI as a slave in both 3-pin and 4-pin configurations. UCxCLK is used as the input for the SPI clock and must be supplied by the external master. The data-transfer rate is determined by this clock and not by the internal bit clock generator. Data written to UCxTXBUF and moved to the TX shift register before the start of UCxCLK is transmitted on UCxSOMI. Data on UCxSIMO is shifted into the receive shift register on the opposite edge of UCxCLK and moved to UCxRXBUF when the set number of bits are received. When data is moved from the RX shift register to UCxRXBUF, the UCxRXIFG interrupt flag is set, indicating that data has been received. The overrun error bit, UCOE, is set when the previously received data is not read from UCxRXBUF before new data is moved to UCxRXBUF. Four-Pin SPI Slave Mode In 4-pin slave mode, UCxSTE is used by the slave to enable the transmit and receive operations and is provided by the SPI master. When UCxSTE is in the slave-active state, the slave operates normally. When UCxSTE is in the slave-inactive state: - Any receive operation in progress on UCxSIMO is halted - UCxSOMI is set to the input direction - The shift operation is halted until the UCxSTE line transitions into the slave transmit active state. The UCxSTE input signal is not used in 3-pin slave mode. Universal Serial Communication Interface, SPI Mode 20-9 USCI Operation: SPI Mode 20.3.5 SPI Enable When the USCI module is enabled by clearing the UCSWRST bit it is ready to receive and transmit. In master mode the bit clock generator is ready, but is not clocked nor producing any clocks. In slave mode the bit clock generator is disabled and the clock is provided by the master. A transmit or receive operation is indicated by UCBUSY = 1. The UCBUSY flag is set by writing UCxTXBUF in master mode and in slave mode with UCCKPH=1. In slave mode with UCCKPH=0 UCBUSY is set with the first UCLK edge. UCBUSY is reset by the following conditions: - In master mode when transfer completed and UCxTXBUF empty. - In slave mode with UCCKPH=0 when transfer completed. - In slave mode with UCCKPH=1 when transfer completed and UCxTXBUF empty. A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated. Transmit Enable In master mode, writing to UCxTXBUF activates the bit clock generator and the data will begin to transmit. In slave mode, transmission begins when a master provides a clock and, in 4-pin mode, when the UCxSTE is in the slave-active state. Receive Enable The SPI receives data when a transmission is active. Receive and transmit operations operate concurrently. 20-10 Universal Serial Communication Interface, SPI Mode USCI Operation: SPI Mode 20.3.6 Serial Clock Control UCxCLK is provided by the master on the SPI bus. When UCMST = 1, the bit clock is provided by the USCI bit clock generator on the UCxCLK pin. The clock used to generate the bit clock is selected with the UCSSELx bits. When UCMST = 0, the USCI clock is provided on the UCxCLK pin by the master, the bit clock generator is not used, and the UCSSELx bits are don’t care. The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer. The 16-bit value of UCBRx in the bit rate control registers UCxxBR1 and UCxxBR0 is the division factor of the USCI clock source, BRCLK. The maximum bit clock that can be generated in master mode is BRCLK. Modulation is not used in SPI mode and UCAxMCTL should be cleared when using SPI mode for USCI_A. The UCAxCLK/UCBxCLK frequency is given by: fBitClock + fBRCLK UCBRx Serial Clock Polarity and Phase The polarity and phase of UCxCLK are independently configured via the UCCKPL and UCCKPH control bits of the USCI. Timing for each case is shown in Figure 20−4. Figure 20−4. USCI SPI Timing with UCMSB = 1 UC UC CKPH CKPL Cycle# 1 2 3 4 5 6 7 8 0 0 UCxCLK 0 1 UCxCLK 1 0 UCxCLK 1 1 UCxCLK UCxSTE 0 X UCxSIMO/ UCxSOMI MSB LSB 1 X UCxSIMO UCxSOMI MSB LSB Move to UCxTXBUF TX Data Shifted Out RX Sample Points Universal Serial Communication Interface, SPI Mode 20-11 USCI Operation: SPI Mode 20.3.7 Using the SPI Mode with Low Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition. After the USCI module returns to the idle condition, control of the clock source reverts to the settings of its control bits. Automatic clock activation is not provided for ACLK. When the USCI module activates an inactive clock source, the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected. For example, a timer using SMCLK will increment while the USCI module forces SMCLK active. In SPI slave mode no internal clock source is required because the clock is provided by the external master. It is possible to operate the USCI in SPI slave mode while the device is in LPM4 and all clock sources are disabled. The receive or transmit interrupt can wake up the CPU from any low power mode. 20.3.8 SPI Interrupts The USCI has one interrupt vector for transmission and one interrupt vector for reception. SPI Transmit Interrupt Operation The UCxTXIFG interrupt flag is set by the transmitter to indicate that UCxTXBUF is ready to accept another character. An interrupt request is generated if UCxTXIE and GIE are also set. UCxTXIFG is automatically reset if a character is written to UCxTXBUF. UCxTXIFG is set after a PUC or when UCSWRST = 1. UCxTXIE is reset after a PUC or when UCSWRST = 1. Note: Writing to UCxTXBUF in SPI Mode Data written to UCxTXBUF when UCxTXIFG = 0 may result in erroneous data transmission. SPI Receive Interrupt Operation The UCxRXIFG interrupt flag is set each time a character is received and loaded into UCxRXBUF. An interrupt request is generated if UCxRXIE and GIE are also set. UCxRXIFG and UCxRXIE are reset by a system reset PUC signal or when UCSWRST = 1. UCxRXIFG is automatically reset when UCxRXBUF is read. 20-12 Universal Serial Communication Interface, SPI Mode USCI Operation: SPI Mode USCI Interrupt Usage USCI_Ax and USCI_Bx share the same interrupt vectors. The receive interrupt flags UCAxRXIFG and UCBxRXIFG are routed to one interrupt vector, the transmit interrupt flags UCAxTXIFG and UCBxTXIFG share another interrupt vector. Shared Interrupt Vectors Software Example The following software example shows an extract of an interrupt service routine to handle data receive interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode. USCIA0_RX_USCIB0_RX_ISR BIT.B #UCA0RXIFG, &IFG2 ; USCI_A0 Receive Interrupt? JNZ USCIA0_RX_ISR USCIB0_RX_ISR? ; Read UCB0RXBUF (clears UCB0RXIFG) ... RETI USCIA0_RX_ISR ; Read UCA0RXBUF (clears UCA0RXIFG) ... RETI The following software example shows an extract of an interrupt service routine to handle data transmit interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode. USCIA0_TX_USCIB0_TX_ISR BIT.B #UCA0TXIFG, &IFG2 ; USCI_A0 Transmit Interrupt? JNZ USCIA0_TX_ISR USCIB0_TX_ISR ; Write UCB0TXBUF (clears UCB0TXIFG) ... RETI USCIA0_TX_ISR ; Write UCA0TXBUF (clears UCA0TXIFG) ... RETI Universal Serial Communication Interface, SPI Mode 20-13 USCI Registers: SPI Mode 20.4 USCI Registers: SPI Mode The USCI registers applicable in SPI mode for USCI_A0 and USCI_B0 are listed in Table 20−2. Registers applicable in SPI mode for USCI_A1 and USCI_B1 are listed in Table 20−3. Table 20−2.USCI_A0 and USCI_B0 Control and Status Registers Register USCI_A0 control register 0 USCI_A0 control register 1 USCI_A0 Baud rate control register 0 USCI_A0 Baud rate control register 1 USCI_A0 modulation control register USCI_A0 status register USCI_A0 Receive buffer register USCI_A0 Transmit buffer register USCI_B0 control register 0 USCI_B0 control register 1 USCI_B0 Bit rate control register 0 USCI_B0 Bit rate control register 1 USCI_B0 status register USCI_B0 Receive buffer register USCI_B0 Transmit buffer register SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form UCA0CTL0 UCA0CTL1 UCA0BR0 UCA0BR1 UCA0MCTL UCA0STAT UCA0RXBUF UCA0TXBUF UCB0CTL0 UCB0CTL1 UCB0BR0 UCB0BR1 UCB0STAT UCB0RXBUF UCB0TXBUF IE2 IFG2 Register Type Address Read/write 060h Read/write 061h Read/write 062h Read/write 063h Read/write 064h Read/write 065h Read 066h Read/write 067h Read/write 068h Read/write 069h Read/write 06Ah Read/write 06Bh Read/write 06Dh Read 06Eh Read/write 06Fh Read/write 001h Read/write 003h Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 001h with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC Note: Modifying SFR bits To avoid modifying control bits of other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 20-14 Universal Serial Communication Interface, SPI Mode USCI Registers: SPI Mode Table 20−3.USCI_A1 and USCI_B1 Control and Status Registers Register USCI_A1 control register 0 USCI_A1 control register 1 USCI_A1 Baud rate control register 0 USCI_A1 Baud rate control register 1 USCI_A1 modulation control register USCI_A1 status register USCI_A1 Receive buffer register USCI_A1 Transmit buffer register USCI_B1 control register 0 USCI_B1 control register 1 USCI_B1 Bit rate control register 0 USCI_B1 Bit rate control register 1 USCI_B1 status register USCI_B1 Receive buffer register USCI_B1 Transmit buffer register USCI_A1/B1 interrupt enable register USCI_A1/B1 interrupt flag register Short Form UCA1CTL0 UCA1CTL1 UCA1BR0 UCA1BR1 UCA1MCTL UCA1STAT UCA1RXBUF UCA1TXBUF UCB1CTL0 UCB1CTL1 UCB1BR0 UCB1BR1 UCB1STAT UCB1RXBUF UCB1TXBUF UC1IE UC1IFG Register Type Address Read/write 0D0h Read/write 0D1h Read/write 0D2h Read/write 0D3h Read/write 0D4h Read/write 0D5h Read 0D6h Read/write 0D7h Read/write 0D8h Read/write 0D9h Read/write 0DAh Read/write 0DBh Read/write 0DDh Read 0DEh Read/write 0DFh Read/write 006h Read/write 007h Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 001h with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC Universal Serial Communication Interface, SPI Mode 20-15 USCI Registers: SPI Mode UCAxCTL0, USCI_Ax Control Register 0 UCBxCTL0, USCI_Bx Control Register 0 7 UCCKPH rw-0 6 UCCKPL rw-0 5 UCMSB rw-0 4 UC7BIT rw-0 3 UCMST rw-0 2 1 UCMODEx rw-0 rw-0 0 UCSYNC=1 rw-0 UCCKPH Bit 7 UCCKPL Bit 6 UCMSB Bit 5 UC7BIT Bit 4 UCMST Bit 3 UCMODEx Bits 2-1 UCSYNC Bit 0 Clock phase select. 0 Data is changed on the first UCLK edge and captured on the following edge. 1 Data is captured on the first UCLK edge and changed on the following edge. Clock polarity select. 0 The inactive state is low. 1 The inactive state is high. MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data Master mode select 0 Slave mode 1 Master mode USCI Mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-Pin SPI 01 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 10 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 11 I2C Mode Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode 20-16 Universal Serial Communication Interface, SPI Mode UCAxCTL1, USCI_Ax Control Register 1 UCBxCTL1, USCI_Bx Control Register 1 USCI Registers: SPI Mode 7 6 UCSSELx rw-0 rw-0 † UCAxCTL1 (USCI_Ax) ‡ UCBxCTL1 (USCI_Bx) 5 rw-0† r0‡ 4 3 2 Unused rw-0 rw-0 rw-0 1 0 UCSWRST rw-0 rw-1 UCSSELx Bits 7-6 Unused UCSWRST Bits 5-1 Bit 0 USCI clock source select. These bits select the BRCLK source clock in master mode. UCxCLK is always used in slave mode. 00 NA 01 ACLK 10 SMCLK 11 SMCLK Unused in synchronous mode (UCSYNC=1). Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state. Universal Serial Communication Interface, SPI Mode 20-17 USCI Registers: SPI Mode UCAxBR0, USCI_Ax Bit Rate Control Register 0 UCBxBR0, USCI_Bx Bit Rate Control Register 0 7 6 5 4 3 2 1 0 UCBRx − low byte rw rw rw rw rw rw rw rw UCAxBR1, USCI_Ax Bit Rate Control Register 1 UCBxBR1, USCI_Bx Bit Rate Control Register 1 7 rw UCBRx 6 5 4 3 2 1 0 UCBRx − high byte rw rw rw rw rw rw rw Bit clock prescaler setting. The 16-bit value of (UCxxBR0+UCxxBR1×256) form the prescaler value UCBRx. 20-18 Universal Serial Communication Interface, SPI Mode UCAxSTAT, USCI_Ax Status Register UCBxSTAT, USCI_Bx Status Register USCI Registers: SPI Mode 7 UCLISTEN 6 UCFE rw-0 rw-0 † UCAxSTAT (USCI_Ax) ‡ UCBxSTAT (USCI_Bx) 5 UCOE rw-0 4 Unused rw-0† r0‡ 3 Unused rw-0 2 Unused rw-0 1 Unused 0 UCBUSY rw-0 r-0 UCLISTEN Bit 7 UCFE Bit 6 UCOE Bit 5 Unused UCBUSY Bits 4−1 Bit 0 Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. The transmitter output is internally fed back to the receiver. Framing error flag. This bit indicates a bus conflict in 4-wire master mode. UCFE is not used in 3-wire master or any slave mode. 0 No error 1 Bus conflict occurred Overrun error flag. This bit is set when a character is transferred into UCxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred Unused in synchronous mode (UCSYNC=1). USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving Universal Serial Communication Interface, SPI Mode 20-19 USCI Registers: SPI Mode UCAxRXBUF, USCI_Ax Receive Buffer Register UCBxRXBUF, USCI_Bx Receive Buffer Register 7 6 5 4 3 2 1 0 UCRXBUFx r r r r r r r r UCRXBUFx Bits 7-0 The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCxRXBUF resets the receive-error bits, and UCxRXIFG. In 7-bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. UCAxTXBUF, USCI_Ax Transmit Buffer Register UCBxTXBUF, USCI_Bx Transmit Buffer Register 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw UCTXBUFx Bits 7-0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted. Writing to the transmit data buffer clears UCxTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. 20-20 Universal Serial Communication Interface, SPI Mode IE2, Interrupt Enable Register 2 7 6 5 4 USCI Registers: SPI Mode 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 UCB0TXIE Bits 7-4 Bit 3 UCB0RXIE Bit 2 UCA0TXIE Bit 1 UCA0RXIE Bit 0 These bits may be used by other modules. See device-specific data sheet. USCI_B0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled Universal Serial Communication Interface, SPI Mode 20-21 USCI Registers: SPI Mode IFG2, Interrupt Flag Register 2 7 6 5 4 3 UCB0 TXIFG rw-1 2 UCB0 RXIFG rw-0 1 UCA0 TXIFG rw-1 0 UCA0 RXIFG rw-0 UCB0 TXIFG UCB0 RXIFG UCA0 TXIFG UCA0 RXIFG Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 These bits may be used by other modules. See device-specific data sheet. USCI_B0 transmit interrupt flag. UCB0TXIFG is set when UCB0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_B0 receive interrupt flag. UCB0RXIFG is set when UCB0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF empty. 0 No interrupt pending 1 Interrupt pending USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending 20-22 Universal Serial Communication Interface, SPI Mode USCI Registers: SPI Mode UC1IE, USCI_A1/USCI_B1 Interrupt Enable Register 7 Unused 6 Unused 5 Unused 4 Unused 3 2 1 0 UCB1TXIE UCB1RXIE UCA1TXIE UCA1RXIE rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Unused UCB1TXIE Bits 7-4 Bit 3 UCB1RXIE Bit 2 UCA1TXIE Bit 1 UCA1RXIE Bit 0 Unused USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled Universal Serial Communication Interface, SPI Mode 20-23 USCI Registers: SPI Mode UC1IFG, USCI_A1/USCI_B1 Interrupt Flag Register 7 Unused 6 Unused 5 Unused 4 Unused 3 UCB1 TXIFG rw−0 rw−0 rw−0 rw−0 rw−1 2 UCB1 RXIFG rw−0 1 UCA1 TXIFG rw−1 0 UCA1 RXIFG rw−0 Unused UCB1 TXIFG UCB1 RXIFG UCA1 TXIFG UCA1 RXIFG Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Unused USCI_B1 transmit interrupt flag. UCB1TXIFG is set when UCB1TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_B1 receive interrupt flag. UCB1RXIFG is set when UCB1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending USCI_A1 transmit interrupt flag. UCA1TXIFG is set when UCA1TXBUF empty. 0 No interrupt pending 1 Interrupt pending USCI_A1 receive interrupt flag. UCA1RXIFG is set when UCA1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending 20-24 Universal Serial Communication Interface, SPI Mode Chapter 21 Universal Serial Communication Interface, I 2C Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the I2C mode. Topic Page 21.1 USCI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.2 USCI Introduction: I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.3 USCI Operation: I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.4 USCI Registers: I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 Universal Serial Communication Interface, I2C Mode 21-1 USCI Overview 21.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers. For example, if one device has two USCI_A modules, they are named USCI_A0 and USCI_A1. See the device-specific data sheet to determine which USCI modules, if any, are implemented on which devices. The USCI_Ax modules support: - UART mode - Pulse shaping for IrDA communications - Automatic baud rate detection for LIN communications - SPI mode The USCI_Bx modules support: - I2C mode - SPI mode 21-2 Universal Serial Communication Interface, I2C Mode 21.2 USCI Introduction: I2C Mode USCI Introduction: I2C Mode In I2C mode, the USCI module provides an interface between the MSP430 and I2C-compatible devices connected by way of the two-wire I2C serial bus. External components attached to the I2C bus serially transmit and/or receive serial data to/from the USCI module through the 2-wire I2C interface. The I2C mode features include: - Compliance to the Philips Semiconductor I2C specification v2.1 J 7-bit and 10-bit device addressing modes J General call J START/RESTART/STOP J Multi-master transmitter/receiver mode J Slave receiver/transmitter mode J Standard mode up to 100 kbps and fast mode up to 400 kbps support - Programmable UCxCLK frequency in master mode - Designed for low power - Slave receiver START detection for auto-wake up from LPMx modes - Slave operation in LPM4 Figure 21−1 shows the USCI when configured in I2C mode. Universal Serial Communication Interface, I2C Mode 21-3 USCI Introduction: I2C Mode Figure 21−1. USCI Block Diagram: I2C Mode UCA10 UCGCEN Own Address UC1OA Receive Shift Register Receive Buffer UC1RXBUF I2C State Machine Transmit Buffer UC1TXBUF Transmit Shift Register Slave Address UC1SA UCSLA10 UCSSELx Bit Clock Generator UC1CLK ACLK SMCLK SMCLK UCxBRx 00 01 10 BRCLK 16 Prescaler/Divider 11 UCMST UCxSDA UCxSCL 21-4 Universal Serial Communication Interface, I2C Mode USCI Operation: I2C Mode 21.3 USCI Operation: I2C Mode The I2C mode supports any slave or master I2C-compatible device. Figure 21−2 shows an example of an I2C bus. Each I2C device is recognized by a unique address and can operate as either a transmitter or a receiver. A device connected to the I2C bus can be considered as the master or the slave when performing data transfers. A master initiates a data transfer and generates the clock signal SCL. Any device addressed by a master is considered a slave. I2C data is communicated using the serial data pin (SDA) and the serial clock pin (SCL). Both SDA and SCL are bidirectional, and must be connected to a positive supply voltage using a pullup resistor. Figure 21−2. I2C Bus Connection Diagram Serial Data (SDA) Serial Clock (SCL) VCC MSP430 Device A Device B Device C Note: SDA and SCL Levels The MSP430 SDA and SCL pins must not be pulled up above the MSP430 VCC level. Universal Serial Communication Interface, I2C Mode 21-5 USCI Operation: I2C Mode 21.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition. To select I2C operation the UCMODEx bits must be set to 11. After module initialization, it is ready for transmit or receive operation. Clearing UCSWRST releases the USCI for operation. Configuring and reconfiguring the USCI module should be done when UCSWRST is set to avoid unpredictable behavior. Setting UCSWRST in I2C mode has the following effects: - I2C communication stops - SDA and SCL are high impedance - UCBxI2CSTAT, bits 6-0 are cleared - UCBxTXIE and UCBxRXIE are cleared - UCBxTXIFG and UCBxRXIFG are cleared - All other bits and registers remain unchanged. Note: Initializing or Reconfiguring the USCI Module The recommended USCI initialization/re-configuration process is: 1) Set UCSWRST (BIS.B #UCSWRST,&UCxCTL1) 2) Initialize all USCI registers with UCSWRST=1 (including UCxCTL1) 3) Configure ports. 4) Clear UCSWRST via software (BIC.B #UCSWRST,&UCxCTL1) 5) Enable interrupts (optional) via UCxRXIE and/or UCxTXIE 21-6 Universal Serial Communication Interface, I2C Mode USCI Operation: I2C Mode 21.3.2 I2C Serial Data One clock pulse is generated by the master device for each data bit transferred. The I2C mode operates with byte data. Data is transferred most significant bit first as shown in Figure 21−3. The first byte after a START condition consists of a 7-bit slave address and the R/W bit. When R/W = 0, the master transmits data to a slave. When R/W = 1, the master receives data from a slave. The ACK bit is sent from the receiver after each byte on the 9th SCL clock. Figure 21−3. I2C Module Data Transfer SDA MSB SCL START 1 2 Condition (S) Acknowledgement Signal From Receiver Acknowledgement Signal From Receiver 789 R/W ACK 12 8 9 ACK STOP Condition (P) START and STOP conditions are generated by the master and are shown in Figure 21−3. A START condition is a high-to-low transition on the SDA line while SCL is high. A STOP condition is a low-to-high transition on the SDA line while SCL is high. The bus busy bit, UCBBUSY, is set after a START and cleared after a STOP. Data on SDA must be stable during the high period of SCL as shown in Figure 21−4. The high and low state of SDA can only change when SCL is low, otherwise START or STOP conditions will be generated. Figure 21−4. Bit Transfer on the I2C Bus SDA Data Line Stable Data SCL Change of Data Allowed Universal Serial Communication Interface, I2C Mode 21-7 USCI Operation: I2C Mode 21.3.3 I2C Addressing Modes The I2C mode supports 7-bit and 10-bit addressing modes. 7-Bit Addressing In the 7-bit addressing format, shown in Figure 21−5, the first byte is the 7-bit slave address and the R/W bit. The ACK bit is sent from the receiver after each byte. Figure 21−5. I2C Module 7-Bit Addressing Format 1 7 1 1 S Slave Address R/W ACK 8 Data 1 ACK 8 Data 11 ACK P 10-Bit Addressing In the 10-bit addressing format, shown in Figure 21−6, the first byte is made up of 11110b plus the two MSBs of the 10-bit slave address and the R/W bit. The ACK bit is sent from the receiver after each byte. The next byte is the remaining 8 bits of the 10-bit slave address, followed by the ACK bit and the 8-bit data. Figure 21−6. I2C Module 10-Bit Addressing Format 1 7 1 1 8 1 S Slave Address 1st byte R/W ACK Slave Address 2nd byte ACK 1 1 1 1 0XX 8 Data 11 ACK P Repeated Start Conditions The direction of data flow on SDA can be changed by the master, without first stopping a transfer, by issuing a repeated START condition. This is called a RESTART. After a RESTART is issued, the slave address is again sent out with the new data direction specified by the R/W bit. The RESTART condition is shown in Figure 21−7. Figure 21−7. I2C Module Addressing Format with Repeated START Condition 1 7 11 S Slave Address R/W ACK 1 8 11 Data ACK S Any Number 7 11 Slave Address R/W ACK 1 8 11 Data ACK P Any Number 21-8 Universal Serial Communication Interface, I2C Mode USCI Operation: I2C Mode 21.3.4 I2C Module Operating Modes In I2C mode the USCI module can operate in master transmitter, master receiver, slave transmitter, or slave receiver mode. The modes are discussed in the following sections. Time lines are used to illustrate the modes. Figure 21−8 shows how to interpret the time line figures. Data transmitted by the master is represented by grey rectangles, data transmitted by the slave by white rectangles. Data transmitted by the USCI module, either as master or slave, is shown by rectangles that are taller than the others. Actions taken by the USCI module are shown in grey rectangles with an arrow indicating where in the the data stream the action occurs. Actions that must be handled with software are indicated with white rectangles with an arrow pointing to where in the data stream the action must take place. Figure 21−8. I2C Time line Legend Other Master Other Slave USCI Master USCI Slave ... Bits set or reset by software ... Bits set or reset by hardware Universal Serial Communication Interface, I2C Mode 21-9 USCI Operation: I2C Mode Slave Mode The USCI module is configured as an I2C slave by selecting the I2C mode with UCMODEx = 11 and UCSYNC = 1 and clearing the UCMST bit. Initially the USCI module must be configured in receiver mode by clearing the UCTR bit to receive the I2C address. Afterwards, transmit and receive operations are controlled automatically depending on the R/W bit received together with the slave address. The USCI slave address is programmed with the UCBxI2COA register. When UCA10 = 0, 7-bit addressing is selected. When UCA10 = 1, 10-bit addressing is selected. The UCGCEN bit selects if the slave responds to a general call. When a START condition is detected on the bus, the USCI module will receive the transmitted address and compare it against its own address stored in UCBxI2COA. The UCSTTIFG flag is set when address received matches the USCI slave address. I2C Slave Transmitter Mode Slave transmitter mode is entered when the slave address transmitted by the master is identical to its own address with a set R/W bit. The slave transmitter shifts the serial data out on SDA with the clock pulses that are generated by the master device. The slave device does not generate the clock, but it will hold SCL low while intervention of the CPU is required after a byte has been transmitted. If the master requests data from the slave the USCI module is automatically configured as a transmitter and UCTR and UCBxTXIFG become set. The SCL line is held low until the first data to be sent is written into the transmit buffer UCBxTXBUF. Then the address is acknowledged, the UCSTTIFG flag is cleared, and the data is transmitted. As soon as the data is transferred into the shift register the UCBxTXIFG is set again. After the data is acknowledged by the master the next data byte written into UCBxTXBUF is transmitted or if the buffer is empty the bus is stalled during the acknowledge cycle by holding SCL low until new data is written into UCBxTXBUF. If the master sends a NACK succeeded by a STOP condition the UCSTPIFG flag is set. If the NACK is succeeded by a repeated START condition the USCI I2C state machine returns to its address-reception state. Figure 21−9 illustrates the slave transmitter operation. 21-10 Universal Serial Communication Interface, I2C Mode USCI Operation: I2C Mode Figure 21−9. I2C Slave Transmitter Mode Reception of own address and S SLA/R transmission of data bytes UCTR= 1(Transmitter) UCSTTIFG= 1 UCBxTXIFG= 1 UCSTPIFG=?0 UCBxTXBUF discarded A DATA A DATA A DATA AP Write data to UCBxTXBUF UCBxTXIFG= 1 UCBxTXIFG= 0 UCSTPIFG= 1 UCSTTIFG= 0 Bus stalled (SCL held low) until data available Write data to UCBxTXBUF Repeated start − continue as slave transmitter DATA A S SLA/R UCBxTXIFG=0 UCTR= 1(Transmitter) UCSTTIFG= 1 UCBxTXIFG= 1 UCBxTXBUF discarded Repeated start − continue as slave receiver Arbitration lost as master and addressed as slave A UCALIFG= 1 UCMST= 0 UCTR= 1(Transmitter) UCSTTIFG= 1 UCBxTXIFG= 1 UCSTPIFG= 0 DATA A S SLA/W UCBxTXIFG= 0 UCTR= 0(Receiver) UCSTTIFG= 1 Universal Serial Communication Interface, I2C Mode 21-11 USCI Operation: I2C Mode I2C Slave Receiver Mode Slave receiver mode is entered when the slave address transmitted by the master is identical to its own address and a cleared R/W bit is received. In slave receiver mode, serial data bits received on SDA are shifted in with the clock pulses that are generated by the master device. The slave device does not generate the clock, but it can hold SCL low if intervention of the CPU is required after a byte has been received. If the slave should receive data from the master the USCI module is automatically configured as a receiver and UCTR is cleared. After the first data byte is received the receive interrupt flag UCBxRXIFG is set. The USCI module automatically acknowledges the received data and can receive the next data byte. If the previous data was not read from the receive buffer UCBxRXBUF at the end of a reception, the bus is stalled by holding SCL low. As soon as UCBxRXBUF is read the new data is transferred into UCBxRXBUF, an acknowledge is sent to the master, and the next data can be received. Setting the UCTXNACK bit causes a NACK to be transmitted to the master during the next acknowledgment cycle. A NACK is sent even if UCBxRXBUF is not ready to receive the latest data. If the UCTXNACK bit is set while SCL is held low the bus will be released, a NACK is transmitted immediately, and UCBxRXBUF is loaded with the last received data. Since the previous data was not read that data will be lost. To avoid loss of data the UCBxRXBUF needs to be read before UCTXNACK is set. When the master generates a STOP condition the UCSTPIFG flag is set. If the master generates a repeated START condition the USCI I2C state machine returns to its address reception state. Figure 21−10 illustrates the the I2C slave receiver operation. 21-12 Universal Serial Communication Interface, I2C Mode USCI Operation: I2C Mode Figure 21−10. I2C Slave Receiver Mode Reception of own address and data S SLA/W A DATA A DATA A bytes. All are acknowledged. UCTR= 0(Receiver) UCSTTIFG= 1 UCSTPIFG= 0 UCBxRXIFG= 1 Bus stalled (SCL held low) if UCBxRXBUF not read Read data from UCBxRXBUF DATA A P or S Refer to: Slave Transmitter Timing Diagram Last byte is not acknowledged. Reception of the general call address. Gen Call A UCTR= 0(Receiver) UCSTTIFG= 1 UCGC= 1 Arbitration lost as master and addressed as slave A UCALIFG= 1 UCMST= 0 UCTR= 0 (Receiver) UCSTTIFG= 1 (UCGC= 1if general call) UCBxTXIFG= 0 UCSTPIFG= 0 DATA A P or S UCTXNACK= 1 Bus not stalled even if UCBxRXBUF not read UCTXNACK= 0 Universal Serial Communication Interface, I2C Mode 21-13 USCI Operation: I2C Mode I2C Slave 10-Bit Addressing Mode The 10-bit addressing mode is selected when UCA10 = 1 and is as shown in Figure 21−11. In 10-bit addressing mode, the slave is in receive mode after the full address is received. The USCI module indicates this by setting the UCSTTIFG flag while the UCTR bit is cleared. To switch the slave into transmitter mode the master sends a repeated START condition together with the first byte of the address but with the R/W bit set. This will set the UCSTTIFG flag if it was previously cleared by software and the USCI modules switches to transmitter mode with UCTR = 1. Figure 21−11.I2C Slave 10-bit Addressing Mode Slave Receiver Reception of own address and data bytes. All are acknowledged. S 11110 xx/W A SLA (2.) A UCTR= 0( Receive)r UCSTTIFG= 1 UCSTPIFG= 0 DATA A DATA UCBxRXIFG= 1 A P or S Reception of the general call address. Gen Call A UCTR= 0(Receiver) UCSTTIFG= 1 UCGC= 1 DATA A DATA UCBxRXIFG= 1 A P or S Slave Transmitter Reception of own address and S 11110 xx/W A SLA (2.) transmission of data bytes UCTR= 0(Receiver) UCSTTIFG= 1 UCSTPIFG= 0 A S 11110 xx/R A DATA A P or S UCSTTIFG= 0 UCTR= 1(Transmitter) UCSTTIFG= 1 UCBxTXIFG= 1 UCSTPIFG= 0 21-14 Universal Serial Communication Interface, I2C Mode USCI Operation: I2C Mode Master Mode The USCI module is configured as an I2C master by selecting the I2C mode with UCMODEx = 11 and UCSYNC = 1 and setting the UCMST bit. When the master is part of a multi-master system, UCMM must be set and its own address must be programmed into the UCBxI2COA register. When UCA10 = 0, 7-bit addressing is selected. When UCA10 = 1, 10-bit addressing is selected. The UCGCEN bit selects if the USCI module responds to a general call. I2C Master Transmitter Mode After initialization, master transmitter mode is initiated by writing the desired slave address to the UCBxI2CSA register, selecting the size of the slave address with the UCSLA10 bit, setting UCTR for transmitter mode, and setting UCTXSTT to generate a START condition. The USCI module checks if the bus is available, generates the START condition, and transmits the slave address. The UCBxTXIFG bit is set when the START condition is generated and the first data to be transmitted can be written into UCBxTXBUF. As soon as the slave acknowledges the address the UCTXSTT bit is cleared. Note: Handling of TXIFG in a multi-master system In a multi−master system (UCMM =1), if the bus is unavailable, the USCI module waits and checks for bus release. Bus unavailability can occur even after the UCTXSTT bit has been set. While waiting for the bus to become available, the USCI may update the TXIFG based on SCL clock line activity. Checking the UCTXSTT bit to verify if the START condition has been sent ensures that the TXIFG is being serviced correctly. The data written into UCBxTXBUF is transmitted if arbitration is not lost during transmission of the slave address. UCBxTXIFG is set again as soon as the data is transferred from the buffer into the shift register. If there is no data loaded to UCBxTXBUF before the acknowledge cycle, the bus is held during the acknowledge cycle with SCL low until data is written into UCBxTXBUF. Data is transmitted or the bus is held as long as the UCTXSTP bit or UCTXSTT bit is not set. Setting UCTXSTP will generate a STOP condition after the next acknowledge from the slave. If UCTXSTP is set during the transmission of the slave’s address or while the USCI module waits for data to be written into UCBxTXBUF, a STOP condition is generated even if no data was transmitted to the slave. When transmitting a single byte of data, the UCTXSTP bit must be set while the byte is being transmitted, or anytime after transmission begins, without writing new data into UCBxTXBUF. Otherwise, only the address will be transmitted. When the data is transferred from the buffer to the shift register, UCBxTXIFG will become set indicating data transmission has begun and the UCTXSTP bit may be set. Universal Serial Communication Interface, I2C Mode 21-15 USCI Operation: I2C Mode Setting UCTXSTT will generate a repeated START condition. In this case, UCTR may be set or cleared to configure transmitter or receiver, and a different slave address may be written into UCBxI2CSA if desired. If the slave does not acknowledge the transmitted data the not-acknowledge interrupt flag UCNACKIFG is set. The master must react with either a STOP condition or a repeated START condition. If data was already written into UCBxTXBUF it will be discarded. If this data should be transmitted after a repeated START it must be written into UCBxTXBUF again. Any set UCTXSTT is discarded, too. To trigger a repeated start, UCTXSTT needs to be set again. Figure 21−12 illustrates the I2C master transmitter operation. 21-16 Universal Serial Communication Interface, I2C Mode Figure 21−12. I2C Master Transmitter Mode Successful transmission to a slave receiver S SLA/W A DATA A DATA 1) UCTR= 1(Transmitter) 2) UCTXSTT= 1 UCBxTXIFG= 1 UCBxTXBUF discarded Next transfer started with a repeated start condition UCTXSTT= 0 UCBxTXIFG= 1 Bus stalled (SCL held low) until data available Write data to UCBxTXBUF USCI Operation: I2C Mode A DATA AP UCTXSTP= 0 UCTXSTP= 1 UCBxTXIFG=0 DATA A S SLA/W 1) UCTR= 1(Transmitter) 2) UCTXSTT= 1 Not acknowledge received after slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave UCTXSTT= 0 UCNACKIFG= 1 UCBxTXIFG= 0 UCBxTXBUF discarded UCTXSTP= 1 DATA A S SLA/R 1) UCTR= 0(Receiver) 2) UCTXSTT= 1 3) UCBxTXIFG= 0 A P UCTXSTP= 0 S SLA/W 1) UCTR= 1(Transmitter) 2) UCTXSTT= 1 UCBxTXIFG= 1 UCBxTXBUF discarded A S SLA/R UCNACKIFG= 1 UCBxTXIFG= 0 UCBxTXBUF discarded 1) UCTR= 0(Receiver) 2) UCTXSTT= 1 Other master continues Other master continues UCALIFG= 1 UCMST= 0 (UCSTTIFG= 0) UCALIFG= 1 UCMST= 0 (UCSTTIFG= 0) A Other master continues UCALIFG= 1 UCMST= 0 UCTR= 0(Receiver) UCSTTIFG= 1 (UCGC= 1if general call) UCBxTXIFG= 0 UCSTPIFG= 0 USCI continues as Slave Receiver Universal Serial Communication Interface, I2C Mode 21-17 USCI Operation: I2C Mode I2C Master Receiver Mode After initialization, master receiver mode is initiated by writing the desired slave address to the UCBxI2CSA register, selecting the size of the slave address with the UCSLA10 bit, clearing UCTR for receiver mode, and setting UCTXSTT to generate a START condition. The USCI module checks if the bus is available, generates the START condition, and transmits the slave address. As soon as the slave acknowledges the address the UCTXSTT bit is cleared. After the acknowledge of the address from the slave the first data byte from the slave is received and acknowledged and the UCBxRXIFG flag is set. Data is received from the slave as long as UCTXSTP or UCTXSTT is not set. If UCBxRXBUF is not read the master holds the bus during reception of the last data bit and until the UCBxRXBUF is read. If the slave does not acknowledge the transmitted address the not-acknowledge interrupt flag UCNACKIFG is set. The master must react with either a STOP condition or a repeated START condition. Setting the UCTXSTP bit will generate a STOP condition. After setting UCTXSTP, a NACK followed by a STOP condition is generated after reception of the data from the slave, or immediately if the USCI module is currently waiting for UCBxRXBUF to be read. If a master wants to receive a single byte only, the UCTXSTP bit must be set while the byte is being received. For this case, the UCTXSTT may be polled to determine when it is cleared: BIS.B #UCTXSTT,&UCB0CTL1 ;Transmit START cond. POLL_STT BIT.B #UCTXSTT,&UCB0CTL1 ;Poll UCTXSTT bit JC POLL_STT ;When cleared, BIS.B #UCTXSTP,&UCB0CTL1 ;transmit STOP cond. Setting UCTXSTT will generate a repeated START condition. In this case, UCTR may be set or cleared to configure transmitter or receiver, and a different slave address may be written into UCBxI2CSA if desired. Figure 21−13 illustrates the I2C master receiver operation. Note: Consecutive Master Transactions Without Repeated Start When performing multiple consecutive I2C master transactions without the repeated start feature, the current transaction must be completed before the next one is initiated. This can be done by ensuring that the transmit stop condition flag UCTXSTP is cleared before the next I2C transaction is initiated with setting UCTXSTT = 1. Otherwise, the current transaction might be affected. 21-18 Universal Serial Communication Interface, I2C Mode USCI Operation: I2C Mode Figure 21−13. I2C Master Receiver Mode Successful reception from a S SLA/R A DATA A DATA A slave transmitter 1) UCTR= 0 (Receiver) 2) UCTXSTT= 1 UCTXSTT= 0 UCBxRXIFG= 1 DATA AP UCTXSTP= 1 UCTXSTP= 0 Next transfer started with a repeated start condition Not acknowledge received after slave address Arbitration lost in slave address or data byte Arbitration lost and addressed as slave DATA A S SLA/W 1) UCTR= 1(Transmitter) 2) UCTXSTT= 1 A UCTXSTT= 0 UCNACKIFG= 1 DATA A S SLA/R UCTXSTP= 1 1) UCTR=0 (Receiver) 2) UCTXSTT= 1 P UCTXSTP= 0 S SLA/W S SLA/R 1) UCTR=1 (Transmitter) 2) UCTXSTT= 1 UCBxTXIFG= 1 1) UCTR=0 (Receiver) 2) UCTXSTT= 1 Other master continues Other master continues UCALIFG= 1 UCMST= 0 (UCSTTIFG= 0) UCALIFG= 1 UCMST= 0 (UCSTTIFG= 0) A Other master continues UCALIFG= 1 UCMST= 0 UCTR= 1( Transmitte)r UCSTTIFG= 1 UCBxTXIFG= 1 UCSTPIFG= 0 USCI continues as Slave Transmitter Universal Serial Communication Interface, I2C Mode 21-19 USCI Operation: I2C Mode I2C Master 10-Bit Addressing Mode The 10-bit addressing mode is selected when UCSLA10 = 1 and is shown in Figure 21−14. Figure 21−14. I2C Master 10-bit Addressing Mode Master Transmitter Successful transmission to a slave receiver S 11110 xx/W A SLA (2.) A DATA A 1) UCTR=1 (Transmitter) 2) UCTXSTT= 1 UCBxTXIFG= 1 UCTXSTT= 0 UCBxTXIFG = 1 DATA AP UCTXSTP= 1 UCTXSTP= 0 Master Receiver Successful reception from a slave transmitter S 11110 xx/W A SLA (2.) A S 11110 xx/R A DATA A DATA AP 1) UCTR= 0 (Receiver) 2) UCTXSTT= 1 UCTXSTT= 0 UCBxRXIFG= 1 UCTXSTP= 0 UCTXSTP= 1 21-20 Universal Serial Communication Interface, I2C Mode USCI Operation: I2C Mode Arbitration If two or more master transmitters simultaneously start a transmission on the bus, an arbitration procedure is invoked. Figure 21−15 illustrates the arbitration procedure between two devices. The arbitration procedure uses the data presented on SDA by the competing transmitters. The first master transmitter that generates a logic high is overruled by the opposing master generating a logic low. The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value. The master transmitter that lost arbitration switches to the slave receiver mode, and sets the arbitration lost flag UCALIFG. If two or more devices send identical first bytes, arbitration continues on the subsequent bytes. Figure 21−15. Arbitration Procedure Between Two Master Transmitters Bus Line SCL Data From Device #1 Data From Device #2 Bus Line SDA n 1 0 1 0 1 Device #1 Lost Arbitration and Switches Off 0 0 1 1 0 0 1 1 If the arbitration procedure is in progress when a repeated START condition or STOP condition is transmitted on SDA, the master transmitters involved in arbitration must send the repeated START condition or STOP condition at the same position in the format frame. Arbitration is not allowed between: - A repeated START condition and a data bit - A STOP condition and a data bit - A repeated START condition and a STOP condition Universal Serial Communication Interface, I2C Mode 21-21 USCI Operation: I2C Mode 21.3.5 I2C Clock Generation and Synchronization The I2C clock SCL is provided by the master on the I2C bus. When the USCI is in master mode, BITCLK is provided by the USCI bit clock generator and the clock source is selected with the UCSSELx bits. In slave mode the bit clock generator is not used and the UCSSELx bits are don’t care. The 16-bit value of UCBRx in registers UCBxBR1 and UCBxBR0 is the division factor of the USCI clock source, BRCLK. The maximum bit clock that can be used in single master mode is fBRCLK/4. In multi-master mode the maximum bit clock is fBRCLK/8. The BITCLK frequency is given by: fBitClock + fBRCLK UCBRx The minimum high and low periods of the generated SCL are tLOW,MIN + tHIGH,MIN + UCBRxń2 fBRCLK when UCBRx is even and tLOW,MIN + tHIGH,MIN + (UCBRx * 1)ń2 fBRCLK when UCBRx is odd. The USCI clock source frequency and the prescaler setting UCBRx must to be chosen such that the minimum low and high period times of the I2C specification are met. During the arbitration procedure the clocks from the different masters must be synchronized. A device that first generates a low period on SCL overrules the other devices forcing them to start their own low periods. SCL is then held low by the device with the longest low period. The other devices must wait for SCL to be released before starting their high periods. Figure 21−16 illustrates the clock synchronization. This allows a slow slave to slow down a fast master. Figure 21−16. Synchronization of Two I2C Clock Generators During Arbitration SCL From Device #1 SCL From Device #2 Bus Line SCL Wait State Start HIGH Period 21-22 Universal Serial Communication Interface, I2C Mode Clock Stretching USCI Operation: I2C Mode The USCI module supports clock stretching and also makes use of this feature as described in the operation mode sections. The UCSCLLOW bit can be used to observe if another device pulls SCL low while the USCI module already released SCL due to the following conditions: - USCI is acting as master and a connected slave drives SCL low. - USCI is acting as master and another master drives SCL low during arbitration. The UCSCLLOW bit is also active if the USCI holds SCL low because it is waiting as transmitter for data being written into UCBxTXBUF or as receiver for the data being read from UCBxRXBUF. The UCSCLLOW bit might get set for a short time with each rising SCL edge because the logic observes the external SCL and compares it to the internally generated SCL. 21.3.6 Using the USCI Module in I2C Mode With Low-Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition. After the USCI module returns to the idle condition, control of the clock source reverts to the settings of its control bits. Automatic clock activation is not provided for ACLK. When the USCI module activates an inactive clock source, the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected. For example, a timer using SMCLK will increment while the USCI module forces SMCLK active. In I2C slave mode no internal clock source is required because the clock is provided by the external master. It is possible to operate the USCI in I2C slave mode while the device is in LPM4 and all internal clock sources are disabled. The receive or transmit interrupts can wake up the CPU from any low power mode. Universal Serial Communication Interface, I2C Mode 21-23 USCI Operation: I2C Mode 21.3.7 USCI Interrupts in I2C Mode Their are two interrupt vectors for the USCI module in I2C mode. One interrupt vector is associated with the transmit and receive interrupt flags. The other interrupt vector is associated with the four state change interrupt flags. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt request. DMA transfers are controlled by the UCBxTXIFG and UCBxRXIFG flags on devices with a DMA controller. I2C Transmit Interrupt Operation The UCBxTXIFG interrupt flag is set by the transmitter to indicate that UCBxTXBUF is ready to accept another character. An interrupt request is generated if UCBxTXIE and GIE are also set. UCBxTXIFG is automatically reset if a character is written to UCBxTXBUF or if a NACK is received. UCBxTXIFG is set when UCSWRST = 1 and the I2C mode is selected. UCBxTXIE is reset after a PUC or when UCSWRST = 1. I2C Receive Interrupt Operation The UCBxRXIFG interrupt flag is set when a character is received and loaded into UCBxRXBUF. An interrupt request is generated if UCBxRXIE and GIE are also set. UCBxRXIFG and UCBxRXIE are reset after a PUC signal or when UCSWRST = 1. UCxRXIFG is automatically reset when UCxRXBUF is read. I2C State Change Interrupt Operation. Table 21−1 Describes the I2C state change interrupt flags. Table 21−1.I2C State Change Interrupt Flags Interrupt Flag UCALIFG UCNACKIFG UCSTTIFG UCSTPIFG Interrupt Condition Arbitration-lost. Arbitration can be lost when two or more transmitters start a transmission simultaneously, or when the USCI operates as master but is addressed as a slave by another master in the system. The UCALIFG flag is set when arbitration is lost. When UCALIFG is set the UCMST bit is cleared and the I2C controller becomes a slave. Not-acknowledge interrupt. This flag is set when an acknowledge is expected but is not received. UCNACKIFG is automatically cleared when a START condition is received. Start condition detected interrupt. This flag is set when the I2C module detects a START condition together with its own address while in slave mode. UCSTTIFG is used in slave mode only and is automatically cleared when a STOP condition is received. Stop condition detected interrupt. This flag is set when the I2C module detects a STOP condition while in slave mode. UCSTPIFG is used in slave mode only and is automatically cleared when a START condition is received. 21-24 Universal Serial Communication Interface, I2C Mode USCI Operation: I2C Mode Interrupt Vector Assignment USCI_Ax and USCI_Bx share the same interrupt vectors. In I2C mode the state change interrupt flags UCSTTIFG, UCSTPIFG, UCNACKIFG, UCALIFG from USCI_Bx and UCAxRXIFG from USCI_Ax are routed to one interrupt vector. The I2C transmit and receive interrupt flags UCBxTXIFG and UCBxRXIFG from USCI_Bx and UCAxTXIFG from USCI_Ax share another interrupt vector. Shared Interrupt Vectors Software Example The following software example shows an extract of the interrupt service routine to handle data receive interrupts from USCI_A0 in either UART or SPI mode and state change interrupts from USCI_B0 in I2C mode. USCIA0_RX_USCIB0_I2C_STATE_ISR BIT.B #UCA0RXIFG, &IFG2 ; USCI_A0 Receive Interrupt? JNZ USCIA0_RX_ISR USCIB0_I2C_STATE_ISR ; Decode I2C state changes ... ; Decode I2C state changes ... ... RETI USCIA0_RX_ISR ; Read UCA0RXBUF ... − clears UCA0RXIFG ... RETI The following software example shows an extract of the interrupt service routine that handles data transmit interrupts from USCI_A0 in either UART or SPI mode and the data transfer interrupts from USCI_B0 in I2C mode. USCIA0_TX_USCIB0_I2C_DATA_ISR BIT.B #UCA0TXIFG, &IFG2 ; USCI_A0 Transmit Interrupt? JNZ USCIA0_TX_ISR USCIB0_I2C_DATA_ISR BIT.B #UCB0RXIFG, &IFG2 JNZ USCIB0_I2C_RX USCIB0_I2C_TX ; Write UCB0TXBUF... − clears UCB0TXIFG ... RETI USCIB0_I2C_RX ; Read UCB0RXBUF... − clears UCB0RXIFG ... RETI USCIA0_TX_ISR ; Write UCA0TXBUF ... − clears UCA0TXIFG ... RETI Universal Serial Communication Interface, I2C Mode 21-25 USCI Registers: I2C Mode 21.4 USCI Registers: I2C Mode The USCI registers applicable in I2C mode for USCI_B0 are listed in Table 21−2 and for USCI_B1 in Table 21−3. Table 21−2.USCI_B0 Control and Status Registers Register USCI_B0 control register 0 USCI_B0 control register 1 USCI_B0 bit rate control register 0 USCI_B0 bit rate control register 1 USCI_B0 I2C interrupt enable register USCI_B0 status register USCI_B0 receive buffer register USCI_B0 transmit buffer register USCI_B0 I2C own address register USCI_B0 I2C slave address register SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form UCB0CTL0 UCB0CTL1 UCB0BR0 UCB0BR1 UCB0I2CIE UCB0STAT UCB0RXBUF UCB0TXBUF UCB0I2COA UCB0I2CSA IE2 IFG2 Register Type Address Read/write 068h Read/write 069h Read/write 06Ah Read/write 06Bh Read/write 06Ch Read/write 06Dh Read 06Eh Read/write 06Fh Read/write 0118h Read/write 011Ah Read/write 001h Read/write 003h Initial State 001h with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC Note: Modifying SFR bits To avoid modifying control bits of other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. Table 21−3.USCI_B1 Control and Status Registers Register USCI_B1 control register 0 USCI_B1 control register 1 USCI_B1 baud rate control register 0 USCI_B1 baud rate control register 1 USCI_B1 I2C Interrupt enable register USCI_B1 status register USCI_B1 receive buffer register USCI_B1 transmit buffer register USCI_B1 I2C own address register USCI_B1 I2C slave address register USCI_A1/B1 interrupt enable register USCI_A1/B1 interrupt flag register Short Form UCB1CTL0 UCB1CTL1 UCB1BR0 UCB1BR1 UCB1I2CIE UCB1STAT UCB1RXBUF UCB1TXBUF UCB1I2COA UCB1I2CSA UC1IE UC1IFG Register Type Address Read/write 0D8h Read/write 0D9h Read/write 0DAh Read/write 0DBh Read/write 0DCh Read/write 0DDh Read 0DEh Read/write 0DFh Read/write 017Ch Read/write 017Eh Read/write 006h Read/write 007h Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC 21-26 Universal Serial Communication Interface, I2C Mode UCBxCTL0, USCI_Bx Control Register 0 USCI Registers: I2C Mode 7 UCA10 rw−0 6 UCSLA10 rw−0 5 UCMM rw−0 4 Unused rw−0 3 UCMST rw−0 2 1 UCMODEx=11 rw−0 rw−0 0 UCSYNC=1 r−1 UCA10 Bit 7 UCSLA10 Bit 6 UCMM Bit 5 Unused UCMST Bit 4 Bit 3 UCMODEx Bits 2−1 UCSYNC Bit 0 Own addressing mode select 0 Own address is a 7-bit address 1 Own address is a 10-bit address Slave addressing mode select 0 Address slave with 7-bit address 1 Address slave with 10-bit address Multi-master environment select 0 Single master environment. There is no other master in the system. The address compare unit is disabled. 1 Multi master environment Unused Master mode select. When a master looses arbitration in a multi-master environment (UCMM = 1) the UCMST bit is automatically cleared and the module acts as slave. 0 Slave mode 1 Master mode USCI Mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-pin SPI 01 4−Pin SPI (master/slave enabled if STE = 1) 10 4−Pin SPI (master/slave enabled if STE = 0) 11 I2C mode Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode Universal Serial Communication Interface, I2C Mode 21-27 USCI Registers: I2C Mode UCBxCTL1, USCI_Bx Control Register 1 7 6 UCSSELx rw−0 rw−0 5 Unused r0 4 UCTR rw−0 3 2 1 0 UCTXNACK UCTXSTP UCTXSTT UCSWRST rw−0 rw−0 rw−0 rw−1 UCSSELx Bits 7-6 Unused UCTR Bit 5 Bit 4 UCTXNACK Bit 3 UCTXSTP Bit 2 UCTXSTT Bit 1 UCSWRST Bit 0 USCI clock source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK Unused Transmitter/Receiver 0 Receiver 1 Transmitter Transmit a NACK. UCTXNACK is automatically cleared after a NACK is transmitted. 0 Acknowledge normally 1 Generate NACK Transmit STOP condition in master mode. Ignored in slave mode. In master receiver mode the STOP condition is preceded by a NACK. UCTXSTP is automatically cleared after STOP is generated. 0 No STOP generated 1 Generate STOP Transmit START condition in master mode. Ignored in slave mode. In master receiver mode a repeated START condition is preceded by a NACK. UCTXSTT is automatically cleared after START condition and address information is transmitted. Ignored in slave mode. 0 Do not generate START condition 1 Generate START condition Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state. 21-28 Universal Serial Communication Interface, I2C Mode UCBxBR0, USCI_Bx Baud Rate Control Register 0 USCI Registers: I2C Mode 7 6 5 4 3 2 1 0 UCBRx − low byte rw rw rw rw rw rw rw rw UCBxBR1, USCI_Bx Baud Rate Control Register 1 7 rw UCBRx 6 5 4 3 2 1 0 UCBRx − high byte rw rw rw rw rw rw rw Bit clock prescaler setting. The 16-bit value of (UCBxBR0 + UCBxBR1 × 256} forms the prescaler value. Universal Serial Communication Interface, I2C Mode 21-29 USCI Registers: I2C Mode UCBxSTAT, USCI_Bx Status Register 7 Unused rw−0 6 UC SCLLOW r−0 5 UCGC rw−0 4 UCBBUSY r−0 3 UCNACK IFG rw−0 2 1 UCSTPIFG UCSTTIFG rw−0 rw−0 0 UCALIFG rw−0 Unused UC SCLLOW Bit 7 Bit 6 UCGC Bit 5 UCBBUSY Bit 4 UCNACK IFG Bit 3 UCSTPIFG Bit 2 UCSTTIFG Bit 1 UCALIFG Bit 0 Unused. SCL low 0 SCL is not held low 1 SCL is held low General call address received. UCGC is automatically cleared when a START condition is received. 0 No general call address received 1 General call address received Bus busy 0 Bus inactive 1 Bus busy Not-acknowledge received interrupt flag. UCNACKIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending Stop condition interrupt flag. UCSTPIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP condition is received. 0 No interrupt pending 1 Interrupt pending Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending 21-30 Universal Serial Communication Interface, I2C Mode UCBxRXBUF, USCI_Bx Receive Buffer Register USCI Registers: I2C Mode 7 6 5 4 3 2 1 0 UCRXBUFx r r r r r r r r UCRXBUFx Bits 7−0 The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCBxRXBUF resets UCBxRXIFG. UCBxTXBUF, USCI_Bx Transmit Buffer Register 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw UCTXBUFx Bits 7−0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted. Writing to the transmit data buffer clears UCBxTXIFG. Universal Serial Communication Interface, I2C Mode 21-31 USCI Registers: I2C Mode UCBxI2COA, USCIBx I2C Own Address Register 15 14 13 12 11 UCGCEN 0 0 0 0 rw−0 r0 r0 r0 r0 10 9 8 0 I2COAx r0 rw−0 rw−0 7 rw−0 6 rw−0 5 rw−0 4 3 I2COAx rw−0 rw−0 2 rw−0 1 rw−0 0 rw−0 UCGCEN I2COAx Bit 15 Bits 9-0 General call response enable 0 Do not respond to a general call 1 Respond to a general call I2C own address. The I2COAx bits contain the local address of the USCI_Bx I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB. UCBxI2CSA, USCI_Bx I2C Slave Address Register 15 14 13 12 11 10 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 9 8 I2CSAx rw−0 rw−0 7 rw−0 6 rw−0 5 rw−0 4 3 I2CSAx rw−0 rw−0 2 rw−0 1 rw−0 0 rw−0 I2CSAx Bits I2C slave address. The I2CSAx bits contain the slave address of the external 9-0 device to be addressed by the USCI_Bx module. It is only used in master mode. The address is right-justified. In 7-bit slave addressing mode Bit 6 is the MSB, Bits 9-7 are ignored. In 10-bit slave addressing mode Bit 9 is the MSB. 21-32 Universal Serial Communication Interface, I2C Mode UCBxI2CIE, USCI_Bx I2C Interrupt Enable Register USCI Registers: I2C Mode 7 rw−0 6 5 Reserved rw−0 rw−0 4 rw−0 3 2 UCNACKIE UCSTPIE rw−0 rw−0 1 UCSTTIE rw−0 0 UCALIE rw−0 Reserved UCNACKIE Bits 7−4 Bit 3 UCSTPIE Bit 2 UCSTTIE Bit 1 UCALIE Bit 0 Reserved Not-acknowledge interrupt enable 0 Interrupt disabled 1 Interrupt enabled Stop condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled Start condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled Arbitration lost interrupt enable 0 Interrupt disabled 1 Interrupt enabled Universal Serial Communication Interface, I2C Mode 21-33 USCI Registers: I2C Mode IE2, Interrupt Enable Register 2 7 6 5 4 3 2 1 0 UCB0TXIE UCB0RXIE rw−0 rw−0 UCB0TXIE Bits 7-4 Bit 3 UCB0RXIE Bit 2 Bits 1-0 These bits may be used by other modules (see the device-specific data sheet). USCI_B0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled These bits may be used by other modules (see the device-specific data sheet). IFG2, Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UCB0 TXIFG UCB0 RXIFG rw−1 rw−0 UCB0 TXIFG UCB0 RXIFG Bits 7-4 Bit 3 Bit 2 Bits 1-0 These bits may be used by other modules (see the device-specific data sheet). USCI_B0 transmit interrupt flag. UCB0TXIFG is set when UCB0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_B0 receive interrupt flag. UCB0RXIFG is set when UCB0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules (see the device-specific data sheet). 21-34 Universal Serial Communication Interface, I2C Mode USCI Registers: I2C Mode UC1IE, USCI_B1 Interrupt Enable Register 7 6 5 4 3 2 1 0 Unused Unused Unused Unused UCB1TXIE UCB1RXIE rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Unused UCB1TXIE Bits 7-4 Bit 3 UCB1RXIE Bit 2 Bits 1-0 Unused USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled These bits may be used by other USCI modules (see the device-specific data sheet). UC1IFG, USCI_B1 Interrupt Flag Register 7 6 5 4 3 2 1 0 Unused Unused Unused Unused UCB1 TXIFG UCB1 RXIFG rw−0 rw−0 rw−0 rw−0 rw−1 rw−0 Unused UCB1 TXIFG UCB1 RXIFG Bits 7-4 Bit 3 Bit 2 Bits 1-0 Unused. USCI_B1 transmit interrupt flag. UCB1TXIFG is set when UCB1TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_B1 receive interrupt flag. UCB1RXIFG is set when UCB1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules (see the device-specific data sheet). Universal Serial Communication Interface, I2C Mode 21-35 21-36 Universal Serial Communication Interface, I2C Mode Chapter 22 OA The OA is a general purpose operational amplifier. This chapter describes the OA. Three OA modules are implemented in the MSP430FG43x and MSP430xG461x devices. Two OA modules are implemented in the MSP430FG42x0 and MSP430FG47x devices. Topic Page 22.1 OA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2 OA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.3 OA Modules in MSP430FG42x0 Devices . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4 OA Modules in MSP430FG47x Devices . . . . . . . . . . . . . . . . . . . . . . . . 22-16 22.5 OA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.6 OA Registers in MSP430FG42x0 Devices . . . . . . . . . . . . . . . . . . . . . 22-27 22.7 OA Registers in MSP430FG47x Devices . . . . . . . . . . . . . . . . . . . . . . . 22-31 OA 22-1 OA Introduction 22.1 OA Introduction The OA op amps support front-end analog signal conditioning prior to analog-to-digital conversion. Features of the OA include: - Single supply, low-current operation - Rail-to-rail output - Software selectable rail-to-rail input - Programmable settling time vs power consumption - Software selectable configurations - Software selectable feedback resistor ladder for PGA implementations Note: Multiple OA Modules Some devices may integrate more than one OA module. If more than one OA module is present on a device, the multiple OA modules operate identically. Throughout this chapter, nomenclature appears such as OAxCTL0 to describe register names. When this occurs, the x is used to indicate which OA module is being discussed. In cases where operation is identical, the register is simply referred to as OAxCTL0. The block diagram of the OA module is shown in Figure 22−1. 22-2 OA Figure 22−1. OA Block Diagram OA Introduction OAPx=3 OAFCx=6 OANx=3 OAPx A12 ext. (OA0) A13 ext. (OA1) A14 ext. (OA2) OAADC0 0 A12 int. (OA0) A13 int. (OA1) 1 A14 int. (OA2) OAxI0 OA0I1 (FG43x) OAxI1 (FG461x) Int. DAC12_0OUT Int. DAC12_1OUT 00 01 0 10 11 1 OA1TAP (OA0) OA2TAP (OA1) OANx OA0TAP (OA2) OAPMx + OAx − OAxOUT 1 0 1 1 OAADC1 OAFCx=0 A1 int./ext., OA0O (OA0) A3 int./ext., OA1O (OA1) A5 int./ext., OA2O (OA2) OAxI0 OAxI1 Int. DAC12_0OUT Int. DAC12_1OUT 00 01 10 00 11 RBOTTOM 01 10 NA 11 OAADC1 OAFCx={2,4,5,6} 1 1 OAFCx=1 OAFCx={2 − 7} OAFBRx OANx = 0 OAFCx = 7 OA1RBOTTOM (OA0) OA2RBOTTOM (OA1) OA0RBOTTOM (OA2) OAFCx = {0,1,3} OAxTAP 3 000 001 010 011 100 101 110 111 RBOTTOM RTOP 4R 4R 2R OAFCx 2R 3 R 000 unused R 001 OAxOUT R 010 R 011 reserved OAFBRx > 0 AV CC 100 101 reserved 00 01 110 10 111 unused 11 OAxI0 OAxI1 OA2OUT (OA0) OA0OUT (OA1) OA1OUT (OA2) OANx OA 22-3 OA Operation 22.2 OA Operation The OA module is configured with user software. The setup and operation of the OA is discussed in the following sections. 22.2.1 OA Amplifier The OA is a configurable low-current rail-to-rail operational amplifier. It can be configured as an inverting amplifier or a non-inverting amplifier, or it can be combined with other OA modules to form differential amplifiers. The output slew rate of the OA can be configured for optimized settling time vs power consumption with the OAPMx bits. When OAPMx = 00, the OA is off, and the output is high-impedance. When OAPMx > 0, the OA is on. See the device-specific data sheet for parameters. 22.2.2 OA Input The OA has configurable input selection. The signals for the + and − inputs are individually selected with the OANx and OAPx bits and can be selected as external signals or internal signals from one of the DAC12 modules. One of the non-inverting inputs is tied together internally for all OA modules. The OA input signal swing is software selectable with the OARRIP bit. When OARRIP = 0, rail-to-rail input mode is selected, and the OA uses higher quiescent current. See the device data sheet for parameters. 22.2.3 OA Output The OA has configurable output selection. The OA output signals can be routed to ADC12 inputs A12 (OA0), A13 (OA1), or A14 (OA2) with the OAADC0 bit. When OAADC0 = 1 and OAPMx > 0, the OA output is connected internally to the corresponding ADC input, and the external ADC input is not connected. The OA output signals can also be routed to ADC12 inputs A1 (OA0), A3 (OA1), or A5 (OA2) when OAFCx = 0 or when OAADC1 = 1. In this case, the OA output is connected to both the ADC12 input internally and the corresponding pin on the device. The OA output is also connected to an internal R-ladder with the OAFCx bits. The R-ladder tap is selected with the OAFBRx bits to provide programmable gain amplifier functionality. 22-4 OA OA Operation 22.2.4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits. as listed in Table 22−1. Table 22−1.OA Mode Select OAFCx 000 001 010 011 100 101 110 111 OA Mode General-purpose op amp Unity gain buffer Reserved Comparator Non-inverting PGA amplifier Reserved Inverting PGA amplifier Differential amplifier General-Purpose Opamp Mode In this mode, the feedback resistor ladder is isolated from the OAx, and the OAxCTL0 bits define the signal routing. The OAx inputs are selected with the OAPx and OANx bits. The OAx output is connected internally to the ADC12 input channel as selected by the OAxCTL0 bits. Unity Gain Mode In this mode, the output of the OAx is connected to RBOTTOM, and the inverting input of the OAx providing a unity-gain buffer. The non-inverting input is selected by the OAPx bits. The external connection for the inverting input is disabled, and the OANx bits are don’t care. The OAx output is connected internally to the ADC12 input channel as selected by the OAxCTL0 bits. Comparator Mode In this mode, the output of the OAx is isolated from the resistor ladder. RTOP is connected to AVSS, and RBOTTOM is connected to AVCC. The OAxTAP signal is connected to the inverting input of the OAx, providing a comparator with a programmable threshold voltage selected by the OAFBRx bits. The non-inverting input is selected by the OAPx bits. Hysteresis can be added by an external positive feedback resistor. The external connection for the inverting input is disabled, and the OANx bits are don’t care. The OAx output is connected internally to the ADC12 input channel as selected by the OAxCTL0 bits. OA 22-5 OA Operation Non-Inverting PGA Mode In this mode, the output of the OAx is connected to RTOP, and RBOTTOM is connected to AVSS. The OAxTAP signal is connected to the inverting input of the OAx, providing a non-inverting amplifier configuration with a programmable gain of [1+ OAxTAP ratio]. The OAxTAP ratio is selected by the OAFBRx bits. If the OAFBRx bits = 0, the gain is unity. The non-inverting input is selected by the OAPx bits. The external connection for the inverting input is disabled, and the OANx bits are don’t care. The OAx output is connected internally to the ADC12 input channel as selected by the OAxCTL0 bits. Inverting PGA Mode In this mode, the output of the OAx is connected to RTOP, and RBOTTOM is connected to an analog multiplexer that multiplexes the OAxI0, OAxI1, or the output of one of the remaining OAs, selected with the OANx bits. The OAxTAP signal is connected to the inverting input of the OAx, providing an inverting amplifier with a gain of −OAxTAP ratio. The OAxTAP ratio is selected by the OAFBRx bits. The non-inverting input is selected by the OAPx bits. The OAx output is connected internally to the ADC12 input channel as selected by the OAxCTL0 bits. Differential Amplifier Mode This mode allows internal routing of the OA signals for a two-opamp or three-opamp instrumentation amplifier. Figure 22−2 shows a two-opamp configuration with OA0 and OA1. In this mode, the output of the OAx is connected to RTOP by routing through another OAx in the Inverting PGA mode. RBOTTOM is unconnected, providing a unity-gain buffer. This buffer is combined with one or two remaining OAx modules to form the differential amplifier. The OAx output is connected internally to the ADC12 input channel as selected by the OAxCTL0 bits. 22-6 OA OA Operation Figure 22−2 shows an example of a two-opamp differential amplifier using OA0 and OA1. The control register settings and are shown in Table 22−2. The gain for the amplifier is selected by the OAFBRx bits for OA1 and is shown in Table 22−3. The OAx interconnections are shown in Figure 22−3. Table 22−2.Two-Opamp Differential Amplifier Control Register Settings Register OA0CTL0 OA0CTL1 OA1CTL0 OA1CTL1 Settings (Binary) 00 xx xx 0 0 000 111 0 x 10 xx xx x x xxx 110 0 x Table 22−3.Two-Opamp Differential Amplifier Gain Settings OA1 OAFBRx 000 001 010 011 100 101 110 111 Gain 0 1/3 1 1 2/3 3 4 1/3 7 15 Figure 22−2. Two Opamp Differential Amplifier V2 V1 + OA0 − + OA1 − R1 R2 (V 2 − V 1) xR 2 Vdiff = R1 OA 22-7 OA Operation Figure 22−3. Two Opamp Differential Amplifier OAx Interconnections OAPx 00 01 V2 10 11 OAPx 00 01 V1 0 10 11 1 00 01 10 11 OAPMx + OA0 − 000 001 010 011 100 101 110 111 OAADC0 A13 ext. 0 1 A13 int. OAPMx 0 + 1 OA1 OAADC1 1 A3 int./ext., OA1O − 0 1 00 01 OAADC1 10 11 OAFBRx 3 000 001 010 011 100 101 110 111 OA1RBOTTOM 4R 4R 2R 2R R 000 R 001 R 010 R 011 100 101 00 01 110 10 111 11 OA0OUT 22-8 OA OA Operation Figure 22−4 shows an example of a three-opamp differential amplifier using OA0, OA1, and OA2. The control register settings are shown in Table 22−4. The gain for the amplifier is selected by the OAFBRx bits of OA0 and OA2. The OAFBRx settings for both OA0 and OA2 must be equal. The gain settings are shown in Table 22−5. The OAx interconnections are shown in Figure 22−5. Table 22−4.Three-Opamp Differential Amplifier Control Register Settings Register OA0CTL0 OA0CTL1 OA1CTL0 OA1CTL1 OA2CTL0 OA2CTL1 Settings (Binary) 00 xx xx 0 0 xxx 001 0 x 00 xx xx 0 0 000 111 0 x 11 11 xx x x xxx 110 0 x Table 22−5.Three-Opamp Differential Amplifier Gain Settings OA0/OA2 OAFBRx 000 001 010 011 100 101 110 111 Gain 0 1/3 1 1 2/3 3 4 1/3 7 15 Figure 22−4. Three-Opamp Differential Amplifier V2 + R1 R2 OA0 − + OA2 V1 + OA1 − (V 2 − V1)xR2 Vdiff = R1 − R1 R2 OA 22-9 OA Operation Figure 22−5. Three-Opamp Differential Amplifier OAx Interconnections OAPx OAADC0 00 01 V2 0 10 11 1 OAPMx + OA0 − OA0OUT OAFBRx 00 3 01 10 000 11 001 010 OA0TAP 011 100 101 110 111 OA0RBOTTOM OAPx 4R 4R 2R 2R R 000 R 001 R 010 R 011 100 101 00 OAPMx 110 01 V1 111 0 10 + 11 1 OA1 − 00 01 10 000 11 001 010 011 100 101 110 111 A14 ext. 0 1 A14 int. 0 1 OA0TAP 00 01 10 11 OAPMx + OA2 − OAADC1 1 A5 int./ext., OA2O 0 1 OAADC1 OAFBRx 3 000 001 010 011 100 101 110 111 OA2RBOTTOM 4R 4R 2R 2R R 000 R 001 R 010 R 011 100 101 00 01 110 10 111 11 OA1OUT 22-10 OA OA Modules in MSP430FG42x0 Devices 22.3 OA Modules in MSP430FG42x0 Devices In MSP430FG42x0 devices, two operational amplifiers, a DAC, and a sigma-delta converter are combined into a measurement front end. The DAC12 module and the SD16A_1 module are described in separate chapters. The block diagram of the operational amplifier is shown in Figure 22−6. Figure 22−6. FG42x0 Operational Amplifiers Block Diagram OACAL 1 OAPx 0 OAxI0 00 OA0I0 01 Int. DAC12 10 11 OAxP OAPMx + OAx − OANx OAxI1 00 OAxI2 01 Int. DAC12 10 0 11 1 OAFCx=001 OAN0 0 1 1 SWCTL3 (OA0) OAFCx SWCTL7 (OA1) 3 unused 000 unused 001 reserved ... reserved 101 110 unused 111 SWCTL2 (OA0) SWCTL6 (OA1) SWxC 1 2 SWCTL0/1 (OA0) SWCTL6/7 (OA1) Int. SD16_A.A0−(OA0) Int. SD16_A.A1−(OA1) OA0OUT/A0+ (OA0) OA1OUT/A1+ (OA1) OA0FB/A0− (OA0) OA1FB/A1− (OA1) OA 22-11 OA Modules in MSP430FG42x0 Devices 22.3.1 OA Amplifier Each OA is a configurable low-current operational amplifier that can be configured as an inverting amplifier or a non-inverting amplifier. 22.3.2 OA Inputs The OA has configurable input selection. The signals for the + and − inputs are individually selected with the OANx and OAPx bits and can be selected as external signals or internal signals from the DAC12 modules or VSS. One of the non-inverting inputs (OA0I0) is tied together internally for all OA modules. The SWCTL0, SWCTL1, SWCTL4, and SWCTL5 bits force settings of the OANx and OAPx bits. See section Switch Control for more details. 22.3.3 OA Outputs The OA outputs are routed to the respective output pin OAxOUT and the positive SD16_A inputs A0+ (OA0), or A1+ (OA1). 22.3.4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits as listed in Table 22−6. The SWCTL0, SWCTL1, SWCTL4, and SWCTL5 bits force settings of the OAFCx bits. See section Switch Control for more details. Table 22−6.FG42x0 OA Mode Select OAFCx 000 001 010 011 100 101 110 111 OA Mode General-purpose opamp Unity gain buffer Reserved Reserved Reserved Reserved Inverting amplifier Reserved General-Purpose Opamp Mode In this mode, the OAx inputs are selected with the OAPx and OANx bits. The OAx output is connected to the output pin and to the SD16_A input. Any feedback needs to be done externally from the output pins OAxOUT to one of the input pins OAxI0 to OAxI2. 22-12 OA Unity-Gain Mode OA Modules in MSP430FG42x0 Devices In this mode, the output of the OAx is connected directly to the inverting input of the OAx providing a unity-gain buffer. The non-inverting input is selected by the OAPx bits. The external connection for the inverting input is disabled, and the OANx bits are don’t care. Inverting Amplifier Mode In this mode, an additional feedback connection is provided as shown in Figure 22−7. The OANx bits select the inverting input signal, which is also connected to the feedback input and to the negative SD16_A input. The circuitry shown in Figure 22−7 mimics a low resistive multiplexer between the inputs OAxI1 and OAxI2. Because the current into the negative terminal of operational amplifier is very low, the voltage drop over the negative input multiplexer can be neglected. The multiplexer connecting the input OAxI1 or OAxI2 to the feedback path is included in the feedback loop, thus compensating for the voltage drop across this multiplexer. This mode is especially useful for transimpedance amplifiers as shown in Figure 22−12. The non-inverting input is selected by the OAPx bits. The OAx output is connected to the output pin and to the positive SD16_A input. Figure 22−7. Inverting Amplifier Configuration OAPx OAPMx OANx + OAx − OA0OUT/A0+ (OA0) OA1OUT/A1+ (OA1) OAxI1 00 OAxI2 01 10 11 0 OA0FB/A0− (OA0) 1 OA1FB/A1− (OA1) OA 22-13 OA Modules in MSP430FG42x0 Devices Figure 22−8. Transimpedance Amplifier With Two Current Inputs OAPx 00 01 DAC12 10 11 OANx I1 I2 OAxI1 00 OAxI2 01 10 11 + OAx − to SD16_A OA0OUT/A0+ (OA0) OA1OUT/A1+ (OA1) OA0FB/A0− (OA0) OA1FB/A1− (OA1) RFB 22.3.5 Switch Control The switch control register SWCTL controls the low resistive switches to ground SW0C and SW1C as well as simplifies the operation of the operational amplifier as transimpedance amplifier. SWCTL2 closes the switch SW0C to ground, and SWCTL6 closes the switch SW1C. SWCTL3 shorts the external feedback resistor for OA0, and SWCTL7 shorts the external feedback resistor for OA1. SWCTL0 and SWCTL1 select the negative analog input to the transimpedance amplifier OA0, and SWCTL4 and SWCTL5 select them for OA1 as shown in Table 22−9. Table 22−7.Input Control of Transimpedance Amplifier SWCTL0 (OA0) SWCTL4 (OA1) 1 0 0 1 SWCTL1 (OA0) SWCTL5 (OA1) 0 1 0 1 Forced Settings OANx = 00 OAFCx = 110 OANx = 01 OAFCx = 110 No forced settings No forced settings 22-14 OA OA Modules in MSP430FG42x0 Devices 22.3.6 Offset Calibration Figure 22−9 shows the configuration for the offset measurement. To measure the offset of the operational amplifier OAx, the unity-gain buffer mode needs to be selected with OAFCx = 001, and the positive input of the amplifier needs to be connected to the negative input of the sigma-delta ADC by setting the calibration bit OACAL. The voltage that can be measured between the negative and the positive SD16_A input represents the offset voltage of the operational amplifier. The measurement result can be incorporated into the later measurement results to compensate for the offset of the amplifier. Figure 22−9. Offset Calibration OACAL OAxI0 OA0I0 Int. DAC12 OAPx 00 01 10 11 + OAx − 1 A0− (OA0) 0 A1− (OA1) VOffset to SD16_A A0+ (OA0) A1+ (OA1) OA 22-15 OA Modules in MSP430FG47x Devices 22.4 OA Modules in MSP430FG47x Devices In the MSP430FG47x devices, two operational amplifiers, two DAC modules, and a sigma-delta converter are combined into a measurement front end. The DAC12 modules and the SD16_A module are described in separate chapters. The block diagram of the operational amplifier is shown in Figure 22−10. 22-16 OA OA Modules in MSP430FG47x Devices Figure 22- 10. MSP430FG47x Operational Amplifiers 0/1 (OA0/1) Block Diagram DAC12OPSx OAPx SWCTLx 2 3 Control logic OA0I0 DAC12_x OAxI0 00 1 01 0 See Note 1 10 Vss 11 OANx SWCTLx 2 3 Control logic OAPMx + OAx - OAxI1 OAxI2 OAxI3 int. DAC12_x OAFCx = 001 00 01 0 10 1 11 OACALx 1 to 0 Ax- OAxO/Ax+ OAFCx = 110 10 SWCTL3 (OA0) SWCTL7 (OA1) 00 1 01 0 10 OAFCx = 110 & SWCTL9 (OA0) OAFCx = 110 & SWCTL13 (OA1) OAxFB 00 1 01 0 10 OAxRFB Note 1: DAC12_0 is routed to OA1. DAC12_1 is routed to OA0 only if DAC12OPS1 = 0. OA 22-17 OA Modules in MSP430FG47x Devices 22.4.1 OA Amplifier Each OA is a configurable low-current operational amplifier that can be configured as an inverting amplifier or a non-inverting amplifier. 22.4.2 OA Inputs The OA has configurable input selection. The signals for the + and − inputs are individually selected with the OANx and OAPx bits and can be selected as external signals or internal signals from the DAC12 module. One of the non-inverting inputs (OA0I0) is tied together internally for both OA modules. The SWCTL0, SWCTL1, SWCTL4, SWCTL5, SWCTL8, and SWCTL12 bits overwrite settings given by the OANx and OAPx bits. See section Switch Control for more details. Also the untiy gain buffer mode sets the input for the −input of the OAx module to the OAx output. 22.4.3 OA Outputs The OA outputs are routed to the respective output pin OAxOUT and the positive SD16_A inputs A0+ (OA0), or A1+ (OA1). 22.4.4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits as listed in Table 22−8. The SWCTL0, SWCTL1, SWCTL4, SWCTL5, SWCTL8, and SWCTL12 bits force settings of the OAFCx bits. See section Switch Control for more details. Table 22−8.MSP430FG47x OAx Mode Select OAFCx 000 001 010 011 100 101 110 111 OAx Mode General-purpose op amp Unity-gain buffer Reserved Reserved Reserved Reserved Inverting amplifier Reserved General-Purpose Opamp Mode In this mode the OAx inputs are selected with the OAPx and OANx bits. The OAx output is connected to the output pin and to the SD16_A inputs. Any feedback needs to be done externally from the output pins OAxOUT to one of the input pins OAxI0 to OAxI3. 22-18 OA Unity Gain Mode OA Modules in MSP430FG47x Devices In this mode the output of the OAx is connected directly to the inverting input of the OAx providing a unity gain buffer. The non-inverting input is selected by the OAPx bits. The external connection for the inverting input is disabled and the OANx bits are don’t care. Inverting Amplifier Mode In this mode an additional feedback connection is provided as shown in Figure 22−11. The OANx bits select the inverting input signal, which is also connected to the feedback input and to the negative SD16_A input. The circuitry shown in Figure 22−11 mimics a low resistive multiplexer between the inputs OAxI1 and OAxI2. Because the current into the negative terminal of operational amplifier is very low, the voltage drop over the negative input multiplexer can be neglected. The multiplexer connecting the input OAxI1 or OAxI2 to the feedback path is included in the feedback loop, thus compensating for the voltage drop across this multiplexer. This mode is especially useful for transimpedance amplifiers as shown in Figure 22−12. The non-inverting input is selected by the OAPx bits. The OAx output is connected to the output pin and to the positive SD16_A input. OA 22-19 OA Modules in MSP430FG47x Devices Figure 22- 11.Inverting Amplifier Configuration OAxI1 OAxI2 OAxI3 int. DAC12_x OANx SWCTLx 2 3 Control logic 00 01 10 11 OAPMx + OAx - 00 01 10 SWCTL9 (OA0) SWCTL13 (OA1) 00 1 01 0 10 OAxO/Ax+ OAxFB OAxRFB 22-20 OA OA Modules in MSP430FG47x Devices Figure 22- 12. Transimpedance Amplifier With Three Current Inputs DAC12OPSx OAPx SW CTLx 2 3 C ontrol lo g ic 1 DAC12_x 0 00 01 See Note 1 10 Vss 11 OANx SW CTLx 2 3 C ontrol lo g ic OAPMx + OAx - to SD16_ O A xO /A x+ O A xI1 00 O A xI2 01 O A xI3 10 11 O A xFB /A x- N o te 1 : D A C 12_0 is route d to O A 1. D A C 1 2_1 is rou ted to O A 0 on ly if D A C 1 2O P S 1 = 0. OA 22-21 OA Modules in MSP430FG47x Devices 22.4.5 Switch Control of the FG47x devices The switch control register OASWCTL0 simplifies the operation of the operational amplifier. SWCTL3 shorts the external feedback resistor for OA0 and SWCTL7 shorts the external feedback resistor for OA1. SWCTL0 and SWCTL1 select the negative analog input to the transimpedance amplifier OA0, SWCTL4 and SWCTL5 select them for OA1 as shown in Table 22−9. Table 22−9.Input Control of Transimpedance Amplifier OASWCTL0 Forced Settings Description SWCTLx BIT OAFCx OANx 0 8 110 00 Selects channel 0 at the − terminal of OA0. 1 9 110 01 Selects channel 1 at the − terminal of OA0. 2 10 − − Reserved. 3 11 − − OA0OUT and OA0FB are shorted. 4 12 110 00 Selects channel 0 at the − terminal of OA1. 5 13 110 01 Selects channel 1 at the − terminal of OA1. 6 14 − − Reserved. 7 15 − − OA1OUT and OA1FB are shorted. 8 0 110 10 Selects channel 2 at the − terminal of OA0. 9 1 − − Range switch control of OA0 (OA0RFB). 10 2 − − Reserved. 11 3 − − Reserved 12 4 110 10 Selects channel 2 at the − terminal of OA1. 13 5 − − Range switch control of OA1 (OA1RFB). 14 6 − − Reserved. 15 7 − − Reserved 22-22 OA OA Modules in MSP430FG47x Devices 22.4.6 Offset Calibration Figure 22−9 shows the configuration for the offset measurement. To measure the offset of the operational amplifier OAx the OAxCAL bit must be set. The voltage that can be measured between the negative and the positive SD16_A input represents the offset voltage of the operational amplifier. The measurement result can be incorporated into the later measurement results to compensate for the offset of the amplifier. For both OA modules the DAC12OPS bit of DAC12_0 module selects if the internal or the external DAC12_x is used. Figure 22−13. Offset Calibration OACALx DAC 12_x OAPx 00 01 10 11 + OAx − 1 A0− (OA0) 0 A1− (OA1) VOffset to SD16_A A0+ (OA0) A1+ (OA1) OA 22-23 OA Registers 22.5 OA Registers The OA registers are listed in Table 22−10. Table 22−10. OA Registers Register OA0 control register 0 OA0 control register 1 OA1 control register 0 OA1 control register 1 OA2 control register 0 OA2 control register 1 Short Form OA0CTL0 OA0CTL1 OA1CTL0 OA1CTL1 OA2CTL0 OA2CTL1 Register Type Address Read/write 0C0h Read/write 0C1h Read/write 0C2h Read/write 0C3h Read/write 0C4h Read/write 0C5h Initial State Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 22-24 OA OAxCTL0, Opamp Control Register 0 OA Registers 7 6 OANx rw−0 rw−0 5 4 OAPx rw−0 rw−0 3 2 OAPMx rw−0 rw−0 1 OAADC1 rw−0 0 OAADC0 rw−0 OANx OAPx OAPMx OAADC1 OAADC0 Bits 7-6 Bits 5-4 Bits 3-2 Bit 1 Bit 0 Inverting input select. These bits select the input signal for the OA inverting input. 00 OAxI0 01 OAxI1 10 DAC0 internal 11 DAC1 internal Non-inverting input select. These bits select the input signal for the OA non-inverting input. 00 OAxI0 01 OA0I1 10 DAC0 internal 11 DAC1 internal Slew rate select These bits select the slew rate vs. current consumption for the OA. 00 Off, output high Z 01 Slow 10 Medium 11 Fast OA output select. This bit connects the OAx output to ADC12 input Ax and output pin OAxO when OAFCx > 0. 0 OAx output not connected to internal/external A1 (OA0), A3 (OA1), or A5 (OA2) signals 1 OAx output connected to internal/external A1 (OA0), A3 (OA1), or A5 (OA2) signals OA output select. This bit connects the OAx output to ADC12 input Ax when OAPMx > 0. 0 OAx output not connected to internal A12 (OA0), A13 (OA1), or A14 (OA2) signals 1 OAx output connected to internal A12 (OA0), A13 (OA1), or A14 (OA2) signals OA 22-25 OA Registers OAxCTL1, Opamp Control Register 1 7 rw−0 6 OAFBRx rw−0 5 rw−0 4 rw−0 3 OAFCx rw−0 2 rw−0 1 Reserved rw−0 0 OARRIP rw−0 OAFBRx Bits 7-5 OAFCx Bits 4-2 Reserved OARRIP Bit 1 Bit 0 OAx feedback resistor select 000 Tap 0 001 Tap 1 010 Tap 2 011 Tap 3 100 Tap 4 101 Tap 5 110 Tap 6 111 Tap 7 OAx function control. This bit selects the function of OAx 000 General purpose 001 Unity gain buffer 010 Reserved 011 Comparing amplifier 100 Non-inverting PGA 101 Reserved 110 Inverting PGA 111 Differential amplifier Reserved OA rail-to-rail input off. 0 OAx input signal range is rail-to-rail 1 OAx input signal range is limited. See the device-specific data sheet for parameters. 22-26 OA OA Registers in MSP430FG42x0 Devices 22.6 OA Registers in MSP430FG42x0 Devices The OA registers are listed in Table 22−10. Table 22−11. OA Registers Register OA0 control register 0 OA0 control register 1 OA1 control register 0 OA1 control register 1 Switch control register Short Form OA0CTL0 OA0CTL1 OA1CTL0 OA1CTL1 SWCTL Register Type Address Read/write 0C0h Read/write 0C1h Read/write 0C2h Read/write 0C3h Read/write 0CFh Initial State Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC OA 22-27 OA Registers in MSP430FG42x0 Devices OAxCTL0, Opamp Control Register 0 7 6 OANx rw−0 rw−0 5 4 OAPx rw−0 rw−0 3 2 OAPMx rw−0 rw−0 1 Reserved rw−0 0 Reserved rw−0 OANx Bits 7−6 OAPx Bits 5−4 OAPMx Bits 3−2 Reserved Bits 1−0 Inverting input select These bits select the input signal for the OAx inverting input. 00 OAxI1 01 OAxI2 10 DAC internal 11 VSS Non-inverting input select These bits select the input signal for the OAx non-inverting input. 00 OAxI0 01 OA0I0 10 DAC internal 11 VSS Slew rate select These bits select the slew rate vs. current consumption of the OAx. 00 Off, output high Z 01 Slow 10 Medium 11 Fast Reserved 22-28 OA OAxCTL1, Opamp Control Register 1 OA Registers in MSP430FG42x0 Devices 7 rw−0 6 Reserved rw−0 5 rw−0 4 rw−0 3 OAFCx rw−0 2 rw−0 1 OACAL rw−0 0 Reserved rw−0 Reserved OAFCx OACAL Reserved Bits 7−5 Bit 4−2 Bit 1 Bit 0 Reserved OAx function control These bits select the function of OAx 000 General purpose 001 Unity gain buffer 010 Reserved 011 Reserved 100 Reserved 101 Reserved 110 Inverting amplifier 111 Reserved Offset calibration This bit enables the offset calibration. 0 Offset calibration disabled 1 Offset calibration enabled Reserved OA 22-29 OA Registers in MSP430FG42x0 Devices SWCTL, Switch Control Register 7 SWCTL7 rw−0 6 SWCTL6 rw−0 5 SWCTL5 rw−0 4 SWCTL4 rw−0 3 SWCTL3 rw−0 2 SWCTL2 rw−0 1 SWCTL1 rw−0 0 SWCTL0 rw−0 SWCTL7 SWCTL6 SWCTL5, SWCTL4 SWCTL3 SWCTL2 SWCTL1, SWCTL0 Bit 7 Bit 6 Bits 5−4 Bit 3 Bit 2 Bits 1−0 Shunt switch for OA1 0 Switch open 1 OA1OUT and OA1FB shorted together SW1C control 0 Switch open 1 SW1C shorted to VSS OANx and OAFCx forced settings for OA1 00 No forced settings 01 OANx forced to 00; OAFCx forced to 110. 10 OANx forced to 01; OAFCx forced to 110. 11 No forced settings Shunt switch for OA0 0 Switch open 1 OA0OUT and OA0FB shorted together SW0C control 0 Switch open 1 SW0C shorted to VSS OANx and OAFCx forced settings for OA0 00 No forced settings 01 OANx forced to 00; OAFCx forced to 110. 10 OANx forced to 01; OAFCx forced to 110. 11 No forced settings 22-30 OA OA Registers in MSP430FG47x Devices 22.7 OA Registers in MSP430FG47x Devices The OA registers are listed in Table 22−12. Table 22−12. OA Registers Register OA0 control register 0 OA0 control register 1 OA1 control register 0 OA1 control register 1 OA Switch control register high byte OA Switch control register low byte OA switch control register word Short Form OA0CTL0 OA0CTL1 OA1CTL0 OA1CTL1 OASWCTL_H OASWCTL_L OASWCTL0 Register Type Address Read/write 0C0h Read/write 0C1h Read/write 0C2h Read/write 0C3h Read/write 0CEh Read/write 0CFh Read/write 0CEh Initial State Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC OA 22-31 OA Registers in MSP430FG47x Devices OAxCTL0, Opamp Control Register 0 7 6 OANx rw−0 rw−0 5 4 OAPx rw−0 rw−0 3 2 OAPMx rw−0 rw−0 1 Reserved r−0 0 Reserved r−0 OANx Bits 7−6 OAPx Bits 5−4 OAPMx Bits 3−2 Reserved Bits 1−0 Inverting input select These bits select the input signal for the OAx inverting input. 00 OAxI1 01 OAxI2 10 OAxI3 11 DAC12_0 (OA0), DAC12_1 (OA1) if the DAC12OPS bits are cleared. Non-inverting input select These bits select the input signal for the OAx non-inverting input. 00 OAxI0 01 OA0I0 if DAC12OPS is set. If DAC12OPS is 0 then DAC12_0 (OA0)/ DAC12_1 (OA1) is used. 10 DAC12_1 (OA0)/ DAC12_0 (OA1) 11 VSS Slew rate select These bits select the slew rate vs. current consumption of the OAx. 00 Off, output high Z 01 Slow 10 Medium 11 Fast Reserved 22-32 OA OAxCTL1, Opamp Control Register 1 OA Registers in MSP430FG47x Devices 7 6 5 Reserved r−0 r−0 r−0 4 rw−0 3 OAFCx rw−0 2 rw−0 1 OACAL rw−0 0 Reserved r−0 Reserved OAFCx OACAL Reserved Bits 7−5 Bit 4−2 Bit 1 Bit 0 Reserved OAx function control These bits select the function of OAx 000 General purpose 001 Unity gain buffer 010 Reserved 011 Reserved 100 Reserved 101 Reserved 110 Inverting amplifier 111 Reserved Offset calibration This bit enables the offset calibration. 0 Offset calibration disabled 1 Offset calibration enabled Reserved OA 22-33 OA Registers in MSP430FG47x Devices OASWCTL0, Switch Control Register 0 15 SWCTL7 rw−0 14 Reserved r−0 13 SWCTL5 rw−0 12 SWCTL4 rw−0 11 SWCTL3 rw−0 10 Reserved r−0 9 SWCTL1 rw−0 8 SWCTL0 rw−0 7 Reserved r−0 6 5 4 3 Reserved SWCTL13 SWCTL12 Reserved r−0 rw−0 rw−0 r−0 2 Reserved r−0 1 SWCTL9 rw−0 0 SWCTL8 rw−0 SWCTL7 Reserved SWCTL5 SWCTL4 SWCTL3 Reserved SWCTL1 SWCTL0 Reserved SWCTL13 SWCTL12 Reserved Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bits 7−6 Bit 5 Bit 4 Bits 3−2 Shunt switch for OA1 0 Switch open 1 OA1OUT and OA1FB shorted together Reserved OANx and OAFCx forced settings for OA1 0 No forced settings 1 OA1I2 enabled; OAFCx forced to 110. OANx and OAFCx forced settings for OA1 0 No forced settings 1 OA1I1 enabled; OAFCx forced to 110. Shunt switch for OA0 0 Switch open 1 OA0OUT and OA0FB shorted together Reserved OANx and OAFCx forced settings for OA0 0 No forced settings 1 OA0I2 enabled; OAFCx forced to 110. OANx and OAFCx forced settings for OA0 0 No forced settings 1 OA0I1 enabled; OAFCx forced to 110. Reserved Range switch control for OA1 0 Switch open 1 Switch closed. OANx and OAFCx forced settings for OA1 0 No forced settings 1 OA1I3 enabled; OAFCx forced to 110. Reserved 22-34 OA SWCTL9 SWCTL8 Bit 1 Bit 0 OA Registers in MSP430FG47x Devices Range feedback switch control for OA0 0 Switch open 1 Switch closed. OANx and OAFCx forced settings for OA0 0 No forced settings 1 OA0I3 enabled; OAFCx forced to 110. OA 22-35 22-36 OA Chapter 23 Comparator_A Comparator_A is an analog voltage comparator. This chapter describes Comparator_A. Comparator_A is implemented in all MSP430x4xx devices. Topic Page 23.1 Comparator_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.2 Comparator_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.3 Comparator_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 Comparator_A 23-1 Comparator_A Introduction 23.1 Comparator_A Introduction The comparator_A module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals. Features of Comparator_A include: - Inverting and non-inverting terminal input multiplexer - Software selectable RC-filter for the comparator output - Output provided to Timer_A capture input - Software control of the port input buffer - Interrupt capability - Selectable reference voltage generator - Comparator and reference generator can be powered down The Comparator_A block diagram is shown in Figure 23−1. 23-2 Comparator_A Figure 23−1. Comparator_A Block Diagram Comparator_A Introduction P2CA0 0 CA0 1 0 CA1 1 P2CA1 CAEX VCC 0V 10 CAON 0 1 ++ −− 0 1 CAF 0 0 1 1 Tau ~ 2.0ms CAREFx 0V 10 CARSEL 00 0 VCAREF 01 1 10 11 D G S 0.5x VCC 0.25x VCC CCI1B CAOUT Set_CAIFG Comparator_A 23-3 Comparator_A Operation 23.2 Comparator_A Operation The comparator_A module is configured with user software. The setup and operation of comparator_A is discussed in the following sections. 23.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals. If the + terminal is more positive than the – terminal, the comparator output CAOUT is high. The comparator can be switched on or off using control bit CAON. The comparator should be switched off when not in use to reduce current consumption. When the comparator is switched off, the CAOUT is always low. 23.2.2 Input Analog Switches The analog input switches connect or disconnect the two comparator input terminals to associated port pins using the P2CAx bits. Both comparator terminal inputs can be controlled individually. The P2CAx bits allow: - Application of an external signal to the + and – terminals of the comparator - Routing of an internal reference voltage to an associated output port pin Internally, the input switch is constructed as a T-switch to suppress distortion in the signal path. Note: Comparator Input Connection When the comparator is on, the input terminals should be connected to a signal, power, or ground. Otherwise, floating levels may cause unexpected interrupts and increased current consumption. The CAEX bit controls the input multiplexer, exchanging which input signals are connected to the comparator’s + and – terminals. Additionally, when the comparator terminals are exchanged, the output signal from the comparator is inverted. This allows the user to determine or compensate for the comparator input offset voltage. 23-4 Comparator_A Comparator_A Operation 23.2.3 Output Filter The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the input terminals is small. Internal and external parasitic effects and cross coupling on and between signal lines, power supply lines, and other parts of the system are responsible for this behavior as shown in Figure 23−2. The comparator output oscillation reduces accuracy and resolution of the comparison result. Selecting the output filter can reduce errors associated with comparator oscillation. Figure 23−2. RC-Filter Response at the Output of the Comparator + Terminal − Terminal Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT 23.2.4 Voltage Reference Generator The voltage reference generator is used to generate VCAREF, which can be applied to either comparator input terminal. The CAREFx bits control the output of the voltage generator. The CARSEL bit selects the comparator terminal to which VCAREF is applied. If external signals are applied to both comparator input terminals, the internal reference generator should be turned off to reduce current consumption. The voltage reference generator can generate a fraction of the device’s VCC or a fixed transistor threshold voltage of ~ 0.55 V. Comparator_A 23-5 Comparator_A Operation 23.2.5 Comparator_A, Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption. The CAPDx bits, when set, disable the corresponding P1 input buffer as shown in Figure 23−3. When current consumption is critical, any P1 pin connected to analog signals should be disabled with their associated CAPDx bit. Figure 23−3. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer VCC VI VCC CAPD.x = 1 VO ICC ICC 0 VSS VI VCC 23.2.6 Comparator_A Interrupts One interrupt flag and one interrupt vector are associated with the Comparator_A as shown in Figure 23−4. The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output, selected by the CAIES bit. If both the CAIE and the GIE bits are set, then the CAIFG flag generates an interrupt request. The CAIFG flag is automatically reset when the interrupt request is serviced or may be reset with software. Figure 23−4. Comparator_A Interrupt System SET_CAIFG VCC CAIES 0 D CAIE Q Reset 1 POR IRQ, Interrupt Service Requested IRACC, Interrupt Request Accepted 23-6 Comparator_A Comparator_A Operation 23.2.7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elements using single slope analog-to-digital conversion. For example, temperature can be converted into digital data using a thermistor, by comparing the thermistor’s capacitor discharge time to that of a reference resistor as shown in Figure 23−5. A reference resister Rref is compared to Rmeas. Figure 23−5. Temperature Measurement System Rref Px.x Rmeas Px.y CA0 ++ −− 0.25xVCC CCI1B Capture Input Of Timer_A The MSP430 resources used to calculate the temperature sensed by Rmeas are: - Two digital I/O pins to charge and discharge the capacitor. - I/O set to output high (VCC) to charge capacitor, reset to discharge. - I/O switched to high-impedance input with CAPDx set when not in use. - One output charges and discharges the capacitor via Rref. - One output discharges capacitor via Rmeas. - The + terminal is connected to the positive terminal of the capacitor. - The – terminal is connected to a reference level, for example 0.25 x VCC. - The output filter should be used to minimize switching noise. - CAOUT used to gate Timer_A CCI1B, capturing capacitor discharge time. More than one resistive element can be measured. Additional elements are connected to CA0 with available I/O pins and switched to high impedance when not being measured. Comparator_A 23-7 Comparator_A Operation The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 23−6. Figure 23−6. Timing for Temperature Measurement Systems VC VCC 0.25 × VCC Phase I: Charge Phase II: Discharge tref Phase III: Charge Phase IV: Discharge tmeas Rmeas Rref t The VCC voltage and the capacitor value should remain constant during the conversion, but are not critical since they cancel in the ratio: Nmeas Nref + –Rmeas –Rref C C ln Vref VCC ln Vref VCC Nmeas Nref + Rmeas Rref Rmeas + Rref Nmeas Nref 23-8 Comparator_A Comparator_A Registers 23.3 Comparator_A Registers The Comparator_A registers are listed in Table 23−1. Table 23−1.Comparator_A Registers Register Comparator_A control register 1 Comparator_A control register 2 Comparator_A port disable Short Form CACTL1 CACTL2 CAPD Register Type Address Read/write 059h Read/write 05Ah Read/write 05Bh Initial State Reset with POR Reset with POR Reset with POR Comparator_A 23-9 Comparator_A Registers CACTL1, Comparator_A Control Register 1 7 CAEX rw−(0) 6 CARSEL rw−(0) 5 4 CAREFx rw−(0) rw−(0) 3 CAON rw−(0) 2 CAIES rw−(0) 1 CAIE rw−(0) 0 CAIFG rw−(0) CAEX CARSEL CAREF CAON CAIES CAIE CAIFG Bit 7 Bit 6 Bits 5-4 Bit 3 Bit 2 Bit 1 Bit 0 Comparator_A exchange. This bit exchanges the comparator inputs and inverts the comparator output. Comparator_A reference select. This bit selects which terminal the VCAREF is applied to. When CAEX = 0: 0 VCAREF is applied to the + terminal 1 VCAREF is applied to the – terminal When CAEX = 1: 0 VCAREF is applied to the – terminal 1 VCAREF is applied to the + terminal Comparator_A reference. These bits select the reference voltage VCAREF. 00 Internal reference off. An external reference can be applied. 01 0.25*VCC 10 0.50*VCC 11 Diode reference is selected Comparator_A on. This bit turns on the comparator. When the comparator is off it consumes no current. The reference circuitry is enabled or disabled independently. 0 Off 1 On Comparator_A interrupt edge select 0 Rising edge 1 Falling edge Comparator_A interrupt enable 0 Disabled 1 Enabled The Comparator_A interrupt flag 0 No interrupt pending 1 Interrupt pending 23-10 Comparator_A CACTL2, Comparator_A Control Register 2 7 rw−(0) 6 5 Unused rw−(0) rw−(0) 4 rw−(0) 3 P2CA1 rw−(0) 2 P2CA0 rw−(0) Comparator_A Registers 1 CAF rw−(0) 0 CAOUT r−(0) Unused P2CA1 P2CA0 CAF CAOUT Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Unused. Pin to CA1. This bit selects the CA1 pin function. 0 The pin is not connected to CA1 1 The pin is connected to CA1 Pin to CA0. This bit selects the CA0 pin function. 0 The pin is not connected to CA0 1 The pin is connected to CA0 Comparator_A output filter 0 Comparator_A output is not filtered 1 Comparator_A output is filtered Comparator_A output. This bit reflects the value of the comparator output. Writing this bit has no effect. CAPD, Comparator_A Port Disable Register 7 CAPD7 rw−(0) 6 CAPD6 rw−(0) 5 CAPD5 rw−(0) 4 CAPD4 rw−(0) 3 CAPD3 rw−(0) 2 CAPD2 rw−(0) 1 CAPD1 rw−(0) 0 CAPD0 rw−(0) CAPDx Bits Comparator_A port disable. These bits individually disable the input buffer 7-0 for the pins of the port associated with Comparator_A. For example, the CAPDx bits can be used to individually enable or disable each P1.x pin buffer. CAPD0 disables P1.0, CAPD1 disables P1.1, etc. 0 The input buffer is enabled. 1 The input buffer is disabled. Comparator_A 23-11 23-12 Comparator_A Chapter 24 Comparator_A+ Comparator_A+ is an analog voltage comparator. This chapter describes the operation of the Comparator_A+ of the 4xx family. It is available on the MSP430F41x2 devices. Topic Page 24.1 Comparator_A+ Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.2 Comparator_A+ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.3 Comparator_A+ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10 Comparator_A+ 24-1 Comparator_A+ Introduction 24.1 Comparator_A+ Introduction The Comparator_A+ module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals. Features of Comparator_A+ include: - Inverting and non-inverting terminal input multiplexer - Software selectable RC-filter for the comparator output - Output provided to Timer_A capture input - Software control of the port input buffer - Interrupt capability - Selectable reference voltage generator - Comparator and reference generator can be powered down - Input Multiplexer The Comparator_A+ block diagram is shown in Figure 24−1. 24-2 Comparator_A+ Figure 24−1. Comparator_A+ Block Diagram Comparator_A+ Introduction P2CA4 P2CA0 00 CA0 01 CA1 10 CA2 11 VCC 0V CAEX 10 CASHORT 000 CA1 001 CA2 010 CA3 011 CA4 100 CA5 101 CA6 110 CA7 111 P2CA3 P2CA2 P2CA1 0 1 ++ −− 0 1 CAREFx CARSEL 00 0 VCAREF 01 1 10 11 CAON G CAF 0 0 1 1 Tau ~ 2.0ns 0V 10 0.5xVCC 0.25xVCC D S CCI1B CAOUT Set_CAIFG Comparator_A+ 24-3 Comparator_A+ Operation 24.2 Comparator_A+ Operation The Comparator_A+ module is configured with user software. The setup and operation of Comparator_A+ is discussed in the following sections. 24.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals. If the + terminal is more positive than the – terminal, the comparator output CAOUT is high. The comparator can be switched on or off using control bit CAON. The comparator should be switched off when not in use to reduce current consumption. When the comparator is switched off, the CAOUT is always low. 24.2.2 Input Analog Switches The analog input switches connect or disconnect the two comparator input terminals to associated port pins using the P2CAx bits. Both comparator terminal inputs can be controlled individually. The P2CAx bits allow: - Application of an external signal to the + and – terminals of the comparator - Routing of an internal reference voltage to an associated output port pin Internally, the input switch is constructed as a T-switch to suppress distortion in the signal path. Note: Comparator Input Connection When the comparator is on, the input terminals should be connected to a signal, power, or ground. Otherwise, floating levels may cause unexpected interrupts and increased current consumption. The CAEX bit controls the input multiplexer, exchanging which input signals are connected to the comparator’s + and – terminals. Additionally, when the comparator terminals are exchanged, the output signal from the comparator is inverted. This allows the user to determine or compensate for the comparator input offset voltage. 24-4 Comparator_A+ Comparator_A+ Operation 24.2.3 Input Short Switch The CASHORT bit shorts the comparator_A+ inputs. This can be used to build a simple sample-and-hold for the comparator as shown in Figure 24−2. Figure 24−2. Comparator_A+ Sample−And−Hold Sampling Capacitor, C s CASHORT Analog Inputs The required sampling time is proportional to the size of the sampling capacitor (CS), the resistance of the input switches in series with the short switch (Ri), and the resistance of the external source (RS). The total internal resistance (RI) is typically in the range of 2 − 10 kΩ. The sampling capacitor CS should be greater than 100pF. The time constant, Tau, to charge the sampling capacitor CS can be calculated with the following equation: Tau = (RI + RS) x CS Depending on the required accuracy 3 to 10 Tau should be used as a sampling time. With 3 Tau the sampling capacitor is charged to approximately 95% of the input signals voltage level, with 5 Tau it is charge to more than 99% and with 10 Tau the sampled voltage is sufficient for 12−bit accuracy. Comparator_A+ 24-5 Comparator_A+ Operation 24.2.4 Output Filter The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the input terminals is small. Internal and external parasitic effects and cross coupling on and between signal lines, power supply lines, and other parts of the system are responsible for this behavior as shown in Figure 24−3. The comparator output oscillation reduces accuracy and resolution of the comparison result. Selecting the output filter can reduce errors associated with comparator oscillation. Figure 24−3. RC-Filter Response at the Output of the Comparator + Terminal − Terminal Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT 24.2.5 Voltage Reference Generator The voltage reference generator is used to generate VCAREF, which can be applied to either comparator input terminal. The CAREFx bits control the output of the voltage generator. The CARSEL bit selects the comparator terminal to which VCAREF is applied. If external signals are applied to both comparator input terminals, the internal reference generator should be turned off to reduce current consumption. The voltage reference generator can generate a fraction of the device’s VCC or a fixed transistor threshold voltage of ~ 0.55 V. 24-6 Comparator_A+ Comparator_A+ Operation 24.2.6 Comparator_A+, Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption. The CAPDx bits, when set, disable the corresponding Px input and output buffers as shown in Figure 24−4. When current consumption is critical, any port pin connected to analog signals should be disabled with its CAPDx bit. Selecting an input pin to the comparator multiplexer with the P2CAx bits automatically disables the input and output buffers for that pin, regardless of the state of the associated CAPDx bit. Figure 24−4. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer VCC VI VO ICC ICC VCC VI 0 VCC CAPD.x = 1 VSS 24.2.7 Comparator_A+ Interrupts One interrupt flag and one interrupt vector are associated with the Comparator_A+ as shown in Figure 24−5. The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output, selected by the CAIES bit. If both the CAIE and the GIE bits are set, then the CAIFG flag generates an interrupt request. The CAIFG flag is automatically reset when the interrupt request is serviced or may be reset with software. Figure 24−5. Comparator_A+ Interrupt System SET_CAIFG VCC CAIES 0 D CAIE Q Reset 1 POR IRQ, Interrupt Service Requested IRACC, Interrupt Request Accepted Comparator_A+ 24-7 Comparator_A+ Operation 24.2.8 Comparator_A+ Used to Measure Resistive Elements The Comparator_A+ can be optimized to precisely measure resistive elements using single slope analog-to-digital conversion. For example, temperature can be converted into digital data using a thermistor, by comparing the thermistor’s capacitor discharge time to that of a reference resistor as shown in Figure 24−6. A reference resister Rref is compared to Rmeas. Figure 24−6. Temperature Measurement System Rref Px.x Rmeas Px.y CA0 ++ −− 0.25xVCC CCI1B Capture Input Of Timer_A The MSP430 resources used to calculate the temperature sensed by Rmeas are: - Two digital I/O pins to charge and discharge the capacitor. - I/O set to output high (VCC) to charge capacitor, reset to discharge. - I/O switched to high-impedance input with CAPDx set when not in use. - One output charges and discharges the capacitor via Rref. - One output discharges capacitor via Rmeas. - The + terminal is connected to the positive terminal of the capacitor. - The – terminal is connected to a reference level, for example 0.25 x VCC. - The output filter should be used to minimize switching noise. - CAOUT used to gate Timer_A CCI1B, capturing capacitor discharge time. More than one resistive element can be measured. Additional elements are connected to CA0 with available I/O pins and switched to high impedance when not being measured. 24-8 Comparator_A+ Comparator_A+ Operation The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 24−7. Figure 24−7. Timing for Temperature Measurement Systems VC VCC 0.25 × VCC Phase I: Charge Phase II: Discharge tref Phase III: Charge Phase IV: Discharge tmeas Rmeas Rref t The VCC voltage and the capacitor value should remain constant during the conversion, but are not critical since they cancel in the ratio: Nmeas Nref + –Rmeas –Rref C C ln Vref VCC ln Vref VCC Nmeas Nref + Rmeas Rref Rmeas + Rref Nmeas Nref Comparator_A+ 24-9 Comparator_A+ Registers 24.3 Comparator_A+ Registers The Comparator_A+ registers are listed in Table 24−1: Table 24−1.Comparator_A+ Registers Register Comparator_A+ control register 1 Comparator_A+ control register 2 Comparator_A+ port disable Short Form CACTL1 CACTL2 CAPD Register Type Address Read/write 059h Read/write 05Ah Read/write 05Bh Initial State Reset with POR Reset with POR Reset with POR 24-10 Comparator_A+ CACTL1, Comparator_A+ Control Register 1 Comparator_A+ Registers 7 CAEX rw−(0) 6 CARSEL rw−(0) 5 4 CAREFx rw−(0) rw−(0) 3 CAON rw−(0) 2 CAIES rw−(0) 1 CAIE rw−(0) 0 CAIFG rw−(0) CAEX CARSEL CAREF CAON CAIES CAIE CAIFG Bit 7 Bit 6 Bits 5-4 Bit 3 Bit 2 Bit 1 Bit 0 Comparator_A+ exchange. This bit exchanges the comparator inputs and inverts the comparator output. Comparator_A+ reference select. This bit selects which terminal the VCAREF is applied to. When CAEX = 0: 0 VCAREF is applied to the + terminal 1 VCAREF is applied to the – terminal When CAEX = 1: 0 VCAREF is applied to the – terminal 1 VCAREF is applied to the + terminal Comparator_A+ reference. These bits select the reference voltage VCAREF. 00 Internal reference off. An external reference can be applied. 01 0.25*VCC 10 0.50*VCC 11 Diode reference is selected Comparator_A+ on. This bit turns on the comparator. When the comparator is off it consumes no current. The reference circuitry is enabled or disabled independently. 0 Off 1 On Comparator_A+ interrupt edge select 0 Rising edge 1 Falling edge Comparator_A+ interrupt enable 0 Disabled 1 Enabled The Comparator_A+ interrupt flag 0 No interrupt pending 1 Interrupt pending Comparator_A+ 24-11 Comparator_A+ Registers CACTL2, Comparator_A+, Control Register 7 CASHORT rw−(0) 6 P2CA4 rw−(0) 5 P2CA3 rw−(0) 4 P2CA2 rw−(0) 3 P2CA1 rw−(0) 2 P2CA0 rw−(0) 1 CAF rw−(0) 0 CAOUT r−(0) CASHORT Bit 7 P2CA4 P2CA3 P2CA2 P2CA1 Bit 6 Bits 5-3 P2CA0 Bit 2 CAF Bit 1 CAOUT Bit 0 Input short. This bit shorts the + and − input terminals. 0 Inputs not shorted. 1 Inputs shorted. Input select. This bit together with P2CA0 selects the + terminal input when CAEX = 0 and the − terminal input when CAEX = 1. Input select. These bits select the − terminal input when CAEX = 0 and the + terminal input when CAEX = 1. 000 No connection 001 CA1 010 CA2 011 CA3 100 CA4 101 CA5 110 CA6 111 CA7 Input select. This bit, together with P2CA4, selects the + terminal input when CAEX = 0 and the − terminal input when CAEX = 1. 00 No connection 01 CA0 10 CA1 11 CA2 Comparator_A+ output filter 0 Comparator_A+ output is not filtered 1 Comparator_A+ output is filtered Comparator_A+ output. This bit reflects the value of the comparator output. Writing this bit has no effect. 24-12 Comparator_A+ CAPD, Comparator_A+, Port Disable Register Comparator_A+ Registers 7 CAPD7 rw−(0) 6 CAPD6 rw−(0) 5 CAPD5 rw−(0) 4 CAPD4 rw−(0) 3 CAPD3 rw−(0) 2 CAPD2 rw−(0) 1 CAPD1 rw−(0) 0 CAPD0 rw−(0) CAPDx Bits Comparator_A+ port disable. These bits individually disable the input 7-0 buffer for the pins of the port associated with Comparator_A+. For example, if CA0 is on pin P2.3, the CAPDx bits can be used to individually enable or disable each port pin buffer. CAPD0 disables the pin associated with CA0, CAPD1 disables the pin connected associated with CA1, etc. 0 The input buffer is enabled. 1 The input buffer is disabled. Comparator_A+ 24-13 24-14 Comparator_A+ Chapter 25 LCD Controller The LCD controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes LCD controller. The LCD controller is implemented on all MSP430x4xx devices, except the MSP430F41x2, MSP430x42x0, MSP430FG461x, MSP430F47x, MSP430FG47x, MSP430F47x3/4, and MSP430F471xx devices. Topic Page 25.1 LCD Controller Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.2 LCD Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3 LCD Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18 LCD Controller 25-1 LCD Controller Introduction 25.1 LCD Controller Introduction The LCD controller directly drives LCD displays by creating the ac segment and common voltage signals automatically. The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs. The LCD controller features are: - Display memory - Automatic signal generation - Configurable frame frequency - Blinking capability - Support for 4 types of LCDs: J Static J 2-mux, 1/2 bias J 3-mux, 1/3 bias J 4-mux, 1/3 bias The LCD controller block diagram is shown in Figure 25−1. Note: Max LCD Segment Control The maximum number of segment lines available differs with device. See the device-specific datasheet for details. 25-2 LCD Controller Figure 25−1. LCD Controller Block Diagram LCD Controller Introduction 0A4h Display Memory 20x 8-bits 091h SEG39 Mux S39 SEG38 Mux S38 Segment Output Control SEG1 Mux S1 SEG0 Mux S0 LCDP2 LCDP1 LCDP0 LCDMX1 LCDMX0 LCDSON LCDON f LCD (from Basic Timer) Timing Generator OSCOFF (from SR) Common Output Control COM3 COM2 COM1 COM0 VA VB VC VD V1 Analog V2 Voltage V3 Multiplexer V4 V5 R33 R23 R13 R03 R R R R R Rx Rx Rx Static 2Mux 3Mux 4Mux External Resistors Rx = Optional Contrast Control LCD Controller 25-3 LCD Controller Operation 25.2 LCD Controller Operation The LCD controller is configured with user software. The setup and operation of LCD controller is discussed in the following sections. 25.2.1 LCD Memory The LCD memory map is shown in Figure 25−2. Each memory bit corresponds to one LCD segment, or is not used, depending on the mode. To turn on an LCD segment, its corresponding memory bit is set. Figure 25−2. LCD Memory Associated 3 2 1 0 3 2 1 0 Common Pins Associated Address 7 0 n Segment Pins 0A4h -- -- -- -- -- -- -- -- 38 39, 38 0A3h -- -- -- -- -- -- -- -- 36 37, 36 0A2h -- -- -- -- -- -- -- -- 34 35, 34 0A1h -- -- -- -- -- -- -- -- 32 33, 32 0A0h -- -- -- -- -- -- -- -- 30 31, 30 09Fh -- -- -- -- -- -- -- -- 28 29, 28 09Eh -- -- -- -- -- -- -- -- 26 27, 26 09Dh -- -- -- -- -- -- -- -- 24 25, 24 09Ch 09Bh -- -- -- -- -- -- -- -- 22 -- -- -- -- -- -- -- -- 20 23, 22 21, 20 09Ah 099h 098h 097h -- -- -- -- -- -- -- -- 18 -- -- -- -- -- -- -- -- 16 -- -- -- -- -- -- -- -- 14 -- -- -- -- -- -- -- -- 12 19, 18 17, 16 15, 14 13, 12 096h -- -- -- -- -- -- -- -- 10 11, 10 095h -- -- -- -- -- -- -- -- 8 9, 8 094h -- -- -- -- -- -- -- -- 6 7, 6 093h -- -- -- -- -- -- -- -- 4 5, 4 092h -- -- -- -- -- -- -- -- 2 3, 2 091h -- -- -- -- -- -- -- -- 0 1, 0 Sn+1 Sn 25.2.2 Blinking the LCD The LCD controller supports blinking. The LCDSON bit is ANDed with each segment’s memory bit. When LCDSON = 1, each segment is on or off according to its bit value. When LCDSON = 0, each LCD segment is off. 25.2.3 LCD Timing Generation The LCD controller uses the fLCD signal from the Basic Timer1 to generate the timing for common and segment lines. The proper frequency fLCD depends on the LCD’s requirement for framing frequency and LCD multiplex rate. See the Basic Timer1 chapter for more information on configuring the fLCD frequency. 25-4 LCD Controller LCD Controller Operation 25.2.4 LCD Voltage Generation The voltages required for the LCD signals are supplied externally to pins R33, R23, R13, and R03. Using an equally weighted resistor divider ladder between these pins establishes the analog voltages as shown in Table 25−1. The resistor value R is typically 680 kW. Values of R from 100kW to 1MW can be used depending on LCD requirements. R33 is a switched-VCC output. This allows the power to the resistor ladder to be turned off eliminating current consumption when the LCD is not used. Table 25−1.External LCD Module Analog Voltage OSCOFF LCDMXx LCDON VA VB VC VD R33 x xx 0 0 0 0 0 Off 1 xx x 0 0 0 0 Off 0 00 1 V5/V1 V1/V5 V5/V1 V1/V5 On 0 01 1 V5/V1 V1/V5 V3/V3 V1/V5 On 0 1x 1 V5/V1 V2/V4 V4/V2 V1/V5 On LCD Contrast Control LCD contrast can be controlled by the R03 voltage level with external circuitry, typically an additional resistor Rx to GND. Increasing the voltage at R03 reduces the total applied segment voltage decreasing the LCD contrast. 25.2.5 LCD Outputs Some LCD segment, common, and Rxx functions are multiplexed with digital I/O functions. These pins can function either as digital I/O or as LCD functions. The pin functions for COMx and Rxx, when multiplexed with digital I/O, are selected using the applicable PxSELx bits as described in the Digital I/O chapter. The LCD segment functions, when multiplexed with digital I/O, are selected using the LCDPx bits. The LCDPx bits selects the LCD function for groups of pins. When LCDPx = 0, no multiplexed pin is set to LCD function. When LCDPx = 1, segments S0 to S15 are selected as LCD function. When LCDPx > 1, LCD segment functions are selected in groups of four. For example, when LCDPx = 2, segments S0 to S19 are selected as LCD function. Note: LCDPx Bits Do Not Affect Dedicated LCD Segment Pins The LCDPx bits only affect pins with multiplexed LCD segment functions and digital I/O functions. Dedicated LCD segment pins are not affected by the LCDPx bits. LCD Controller 25-5 LCD Controller Operation 25.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment, and one common line, COM0, is used. Figure 25−3 shows some example static waveforms. Figure 25−3. Example Static Waveforms V1 COM0 V5 fframe V1 SP1 V5 COM0 V1 SP2 V5 SP1 SP6 a V1 b SP2 Resulting Voltage for SP7 Segment a (COM0−SP1) Segment Is On. 0V SP3 V1 SP5 SP8 SP4 Resulting Voltage for Segment b (COM0−SP2) 0V Segment Is Off. SP = Segment Pin 25-6 LCD Controller LCD Controller Operation Figure 25−4 shows an example static LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 25−4. Static LCD Example LCD a fg b a fg b a fg b a fg b e c e ce ce c d h d h d h d h Pinout and Connections Connections ’430 Pins LCD Pinout S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 COM0 COM1 COM2 COM3 PIN COM0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 NC NC NC 1a 1b 1c 1d 1e 1f 1g 1h 2a 2b 2c 2d 2e 2f 2g 2h 3a 3b 3c 3d 3e 3f 3g 3h 4a 4b 4c 4d 4e 4f 4g 4h COM0 Display Memory COM 3 2 1 0 3 2 1 0 MAB 0A0h -- -- -- h -- -- -- g 09Fh -- -- -- f -- -- -- e 09Eh -- -- -- d -- -- -- c 09Dh -- -- -- b -- -- -- a 09Ch -- -- -- h -- -- -- g 09Bh -- -- -- f -- -- -- e 09Ah -- -- -- d -- -- -- c 099h -- -- -- b -- -- -- a 098h -- -- -- h -- -- -- g 097h -- -- -- f -- -- -- e 096h -- -- -- d -- -- -- c 095h -- -- -- b -- -- -- a 094h -- -- -- h -- -- -- g 093h -- -- -- f -- -- -- e 092h -- -- -- d -- -- -- c 091h -- -- -- b -- -- -- a n = 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 Digit 4 Digit 3 Digit 2 Digit 1 A B G0 3 3 2 1 0 3 2 1 0 0 3 G A B Parallel-Serial Conversion Sn+1 Sn LCD Controller 25-7 LCD Controller Operation Static Mode Software Example ; All eight segments of a digit are often located in four ; display memory bytes with the static display method. ; a EQU 001h b EQU 010h c EQU 002h d EQU 020h e EQU 004h f EQU 040h g EQU 008h h EQU 080h ; The register content of Rx should be displayed. : The Table represents the ’on’−segments according to the ; content of Rx. MOV.B Table (Rx),RY MOV.B Ry,&LCDn RRA Ry MOV.B Ry,&LCDn+1 RRA Ry MOV.B Ry,&LCDn+2 RRA Ry MOV.B Ry,&LCDn+3 ; Load segment information ; into temporary memory. ; (Ry) = 0000 0000 hfdb geca ; Note: ; All bits of an LCD memory ’ byte are written ; (Ry) = 0000 0000 0hfd bgec ; Note: ; All bits of an LCD memory ; byte are written ; (Ry) = 0000 0000 00hf dbge ; Note: ; All bits of an LCD memory ’ byte are written ; (Ry) = 0000 0000 000h fdbg ; Note: ; All bits of an LCD memory ’ byte are written ........... ........... ; Table DB a+b+c+d+e+f DB b+c; ........... ........... DB ........... ; displays ”0” ; displays ”1” 25-8 LCD Controller LCD Controller Operation 25.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments, and two common lines, COM0 and COM1, are used. Figure 25−5 shows some example 2-mux waveforms. Figure 25−5. Example 2-Mux Waveforms COM1 V1 COM0 V3 fframe V5 V1 COM1 V3 V5 COM0 V1 SP1 V5 V1 SP2 b V5 SP1 V1 Resulting Voltage for V3 SP4 h Segment h (COM0−SP2) SP2 Segment Is On. 0V −V3 SP3 −V1 SP = Segment Pin V1 Resulting Voltage for V3 Segment b (COM1−SP2) 0V Segment Is Off. −V3 −V5 LCD Controller 25-9 LCD Controller Operation Figure 25−6 shows an example 2-mux LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application completely depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 25−6. 2−Mux LCD Example LCD a fg b a fg b e c d h DIGIT8 e c d h DIGIT1 Pinout and Connections Connections ’430 Pins LCD Pinout PIN COM0 COM1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 NC NC 1f 1a 1h 1b 1d 1c 1e 1g 2f 2a 2h 2b 2d 2c 2e 2g 3f 3a 3h 3b 3d 3c 3e 3g 4f 4a 4h 4b 4d 4c 4e 4g 5f 5a 5h 5b 5d 5c 5e 5g 6f 6a 6h 6b 6d 6c 6e 6g 7f 7a 7h 7b 7d 7c 7e 7g 8f 8a 8h 8b 8d 8c 8e 8g COM0 COM1 Display Memory COM 3 2 1 0 3 2 1 MAB 0A0h -- -- g e -- -- c 09Fh -- -- b h -- -- a 09Eh -- -- g e -- -- c 09Dh -- -- b h -- -- a 09Ch -- -- g e -- -- c 09Bh -- -- b h -- -- a 09Ah -- -- g e -- -- c 099h -- -- b h -- -- a 098h -- -- g e -- -- c 097h -- -- b h -- -- a 096h -- -- g e -- -- c 095h -- -- b h -- -- a 094h -- -- g e -- -- c 093h -- -- b h -- -- a 092h -- -- g e -- -- c 091h -- -- b h -- -- a A B G0 3 3 2 1 0 3 2 1 Sn+1 Sn 0 d n = 30 1/2 Digit 8 f 28 d 26 Digit 7 f 24 d f 22 Digit 6 20 d 18 f 16 Digit 5 d 14 Digit 4 f 12 d 10 f 8 Digit 3 d 6 f 4 Digit 2 d 2 Digit 1 f 0 0 Parallel- 0 3 G A B Serial Conversion 25-10 LCD Controller LCD Controller Operation 2-Mux Mode Software Example ; All eight segments of a digit are often located in two ; display memory bytes with the 2mux display rate ; a EQU 002h b EQU 020h c EQU 008h d EQU 004h e EQU 040h f EQU 001h g EQU 080h h EQU 010h ; The register content of Rx should be displayed. ; The Table represents the ’on’−segments according to the ; content of Rx. ; ........... ........... MOV.B Table(Rx),Ry ; Load segment information into ; temporary memory. MOV.B Ry,&LCDn ; (Ry) = 0000 0000 gebh cdaf ; Note: ; All bits of an LCD memory byte ; are written RRA Ry ; (Ry) = 0000 0000 0geb hcda RRA Ry ; (Ry) = 0000 0000 00ge bhcd MOV.B Ry,&LCDn+1 ; Note: ; All bits of an LCD memory byte ; are written ........... ........... ........... Table DB a+b+c+d+e+f ; displays ”0” ........... DB a+b+c+d+e+f+g+ ; displays ”8” ........... ........... DB ........... ; LCD Controller 25-11 LCD Controller Operation 25.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments, and three common lines, COM0, COM1 and COM2 are used. Figure 25−7 shows some example 3-mux waveforms. Figure 25−7. Example 3-Mux Waveforms COM2 V1 COM0 V2 V4 fframe V5 V1 COM1 COM1 V2 V4 V5 COM0 V1 COM2 V2 V4 V5 V1 V2 SP1 V4 V5 e V1 d SP2 SP1 SP3 V5 SP2 V1 SP = Segment Pin V2 SP3 V4 V5 V1 Resulting Voltage for Segment e (COM0−SP1) 0V Segment Is Off. −V1 V1 Resulting Voltage for Segment d (COM0−SP2) 0V Segment Is On. −V1 25-12 LCD Controller LCD Controller Operation Figure 25−8 shows an example 3-mux LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 25−8. 3-Mux LCD Example LCD ya fg b e c d h DIGIT10 ya fg b e c d h DIGIT1 Pinout and Connections Connections ’430 Pins LCD Pinout PIN COM0 COM1 COM2 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 NC 1e 1f 1y 1d 1g 1a 1h 1c 1b 2e 2f 2y 2d 2g 2a 2h 2c 2b 3e 3f 3y 3d 3g 3a 3h 3c 3b 4e 4f 4y 4d 4g 4a 4h 4c 4b 5e 5f 5y 5d 5g 5a 5h 5c 5b 6e 6f 6y 6d 6g 6a 6h 6c 6b 7e 7f 7y 7d 7g 7a 7h 7c 7b 8e 8f 8y 8d 8g 8a 8h 8c 8b 9e 9f 9y 9d 9g 9a 9h 9c 9b 10e 10f 10y 10d 10g 10a 10h 10c 10b COM0 COM1 COM2 Display Memory COM 3 2 1 0 3 2 1 0 MAB 09Fh -- a g d -- y f e n = 30 09Eh -- b c h -- a g d 09Dh -- y f e -- b c h 09Ch -- a g d -- y f e 09Bh -- b c h -- a g d -- y f e -- b c h 09Ah -- a g d -- y f e 099h -- b c h -- a g d 098h -- y f e -- b c h 097h -- a g d -- y f e 096h -- b c h -- a g d 095h -- y f e -- b c h 094h -- a g d -- y f e 28 Digit 10 26 Digit 9 24 22 Digit 8 20 Digit 7 18 16 Digit 6 14 Digit 5 12 10 Digit 4 8 Digit 3 6 093h -- b c h -- a g d 092h -- y f e -- b c h 091h -- a g d -- y f e 4 Digit 2 2 Digit 1 0 A G0 3 2 B3 10 3 2 1 0 0A 3G B ParallelSerial Conversion Sn+1 Sn LCD Controller 25-13 LCD Controller Operation 3-Mux Mode Software Example ; The 3mux rate can support nine segments for each ; digit. The nine segments of a digit are located in ; 1 1/2 display memory bytes. ; a EQU 0040h b EQU 0400h c EQU 0200h d EQU 0010h e EQU 0001h f EQU 0002h g EQU 0020h h EQU 0100h Y EQU 0004h ; The LSDigit of register Rx should be displayed. ; The Table represents the ’on’−segments according to the ; LSDigit of register of Rx. ; The register Ry is used for temporary memory ; ODDDIG RLA Rx ; LCD in 3mux has 9 segments per ; digit; word table required for ; displayed characters. MOV Table(Rx),Ry ; Load segment information to ; temporary mem. ; (Ry) = 0000 0bch 0agd 0yfe MOV.B Ry,&LCDn ; write ’a, g, d, y, f, e’ of ; Digit n (LowByte) SWPB Ry ; (Ry) = 0agd 0yfe 0000 0bch BIC.B #07h,&LCDn+1 ; write ’b, c, h’ of Digit n ; (HighByte) BIS.B Ry,&LCDn+1 ..... EVNDIG RLA Rx ; LCD in 3mux has 9 segments per ; digit; word table required for ; displayed characters. MOV Table(Rx),Ry ; Load segment information to ; temporary mem. ; (Ry) = 0000 0bch 0agd 0yfe RLA Ry ; (Ry) = 0000 bch0 agd0 yfe0 RLA Ry ; (Ry) = 000b ch0a gd0y fe00 RLA Ry ; (Ry) = 00bc h0ag d0yf e000 RLA Ry ; (Ry) = 0bch 0agd 0yfe 0000 BIC.B #070h,&LCDn+1 BIS.B Ry,&LCDn+1 ; write ’y, f, e’ of Digit n+1 ; (LowByte) SWPB Ry ; (Ry) = 0yfe 0000 0bch 0agd MOV.B Ry,&LCDn+2 ; write ’b, c, h, a, g, d’ of ; Digit n+1 (HighByte) ........... Table DW a+b+c+d+e+f ; displays ”0” DW b+c ; displays ”1” ........... ........... DW a+e+f+g ; displays ”F” 25-14 LCD Controller LCD Controller Operation 25.2.9 4-Mux Mode In 4-mux mode, each MSP430 segment pin drives four LCD segments, and all four common lines, COM0, COM1, COM2, and COM3 are used. Figure 25−9 shows some example 4-mux waveforms. Figure 25−9. Example 4-Mux Waveforms COM3 V1 COM0 V2 COM2 V4 fframe V5 V1 COM1 COM1 V2 V4 V5 COM0 V1 COM2 V2 V4 V5 V1 COM3 V2 V4 V5 e c V1 V2 SP1 V4 SP2 V5 SP1 SP = Segment Pin V1 V2 SP2 V4 V5 V1 Resulting Voltage for Segment e (COM1−SP1) 0V Segment Is Off. −V1 V1 Resulting Voltage for Segment c (COM1−SP2) 0V Segment Is On. −V1 LCD Controller 25-15 LCD Controller Operation Figure 25−10 shows an example 4-mux LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 25−10. 4-Mux LCD Example LCD a fg b a fg b e c d h DIGIT15 e c d h DIGIT1 Pinout and Connections Connections COM 3 ’430 Pins LCD Pinout PIN COM0 COM1 COM2COM3 MAB 09Fh a S0 1 1d 1e 1g 1f S1 2 1h 1c 1b 1a S2 3 2d 2e 2g 2f S3 4 2h 2c 2b 2a S4 5 3d 3e 3g 3f S5 6 3h 3c 3b 3a S6 7 4d 4e 4g 4f S7 8 4h 4c 4b 4a S8 9 5d 5e 5g 5f S9 10 5h 5c 5b 5a S10 11 6d 6e 6g 6f S11 12 6h 6c 6b 6a S12 13 7d 7e 7g 7f S13 14 7h 7c 7b 7a 09Eh a 09Dh a 09Ch a 09Bh a a 09Ah a 099h a 098h a 097h a 096h a 095h a S14 15 8d 8e 8g 8f S15 16 8h 8c 8b 8a S16 17 9d 9e 9g 9f 094h a 093h a S17 18 9h 9c 9b 9a 092h a S18 19 10d 10e 10g 10f S19 20 10h 10c 10b 10a 091h a S20 21 11d 11e 11g 11f S21 22 11h 11c 11b 11a S22 23 12d 12e 12g 12f S23 24 12h 12c 12b 12a S24 25 13d 13e 13g 13f A G0 3 B3 S25 26 13h 13c 13b 13a S26 27 14d 14e 14g 14f S27 28 14h 14c 14b 14a S28 29 15d 15e 15g 15f S29 30 15h 15c 15b 15a COM0 31 COM0 COM1 32 COM1 COM2 33 COM2 COM3 34 COM3 Display Memory 210 321 b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e 210 3 21 Sn+1 Sn 0 d n = 30 Digit 16 d 28 Digit 15 d 26 Digit 14 d 24 Digit 13 d 22 Digit 12 d 20 Digit 11 d 18 Digit 10 d 16 Digit 9 d 14 Digit 8 d 12 Digit 7 d 10 Digit 6 d 8 Digit 5 d 6 Digit 4 d 4 Digit 3 d 2 Digit 2 d 0 Digit 1 0 0 3G A B ParallelSerial Conversion 25-16 LCD Controller LCD Controller Operation 4-Mux Mode Software Example ; The 4mux rate supports eight segments for each digit. ; All eight segments of a digit can often be located in ; one display memory byte a EQU 080h b EQU 040h c EQU 020h d EQU 001h e EQU 002h f EQU 008h g EQU 004h h EQU 010h ; ; The LSDigit of register Rx should be displayed. ; The Table represents the ’on’−segments according to the ; content of Rx. ; MOV.B Table(Rx),&LCDn ; n = 1 ..... 15 ; all eight segments are ; written to the display ; memory ........... ........... Table DB a+b+c+d+e+f DB b+c ........... ........... DB b+c+d+e+g DB a+d+e+f+g DB a+e+f+g ; displays ”0” ; displays ”1” ; displays ”d” ; displays ”E” ; displays ”F” LCD Controller 25-17 LCD Controller Operation 25.3 LCD Controller Registers The LCD controller registers are listed in Table 25−2. Table 25−2.LCD Controller Registers Register LCD control register LCD memory 1 LCD memory 2 LCD memory 3 LCD memory 4 LCD memory 5 LCD memory 6 LCD memory 7 LCD memory 8 LCD memory 9 LCD memory 10 LCD memory 11 LCD memory 12 LCD memory 13 LCD memory 14 LCD memory 15 LCD memory 16 LCD memory 17 LCD memory 18 LCD memory 19 LCD memory 20 Short Form LCDCTL LCDM1 LCDM2 LCDM3 LCDM4 LCDM5 LCDM6 LCDM7 LCDM8 LCDM9 LCDM10 LCDM11 LCDM12 LCDM13 LCDM14 LCDM15 LCDM16 LCDM17 LCDM18 LCDM19 LCDM20 Register Type Address Read/write 090h Read/write 091h Read/write 092h Read/write 093h Read/write 094h Read/write 095h Read/write 096h Read/write 097h Read/write 098h Read/write 099h Read/write 09Ah Read/write 09Bh Read/write 09Ch Read/write 09Dh Read/write 09Eh Read/write 09Fh Read/write 0A0h Read/write 0A1h Read/write 0A2h Read/write 0A3h Read/write 0A4h Initial State Reset with PUC Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged 25-18 LCD Controller LCDCTL, LCD Control Register 7 rw−0 6 LCDPx rw−0 5 rw−0 4 3 LCDMXx rw−0 rw−0 LCD Controller Operation 2 LCDSON rw−0 1 Unused rw−0 0 LCDON rw−0 LCDPx LCDMXx LCDSON Unused LCDON Bits 7-5 Bits 4-3 Bit 2 Bit 1 Bit 0 LCD port select. These bits select the pin function to be port I/O or LCD function for groups of segments pins. These bits ONLY affect pins with multiplexed functions. Dedicated LCD pins are always LCD function. 000 No multiplexed pins are LCD function 001 S0-S15 are LCD function 010 S0-S19 are LCD function 011 S0-S23 are LCD function 100 S0-S27 are LCD function 101 S0-S31 are LCD function 110 S0-S35 are LCD function 111 S0-S39 are LCD function LCD mux rate. These bits select the LCD mode. 00 Static 01 2-mux 10 3-mux 11 4-mux LCD segments on. This bit supports flashing LCD applications by turning off all segment lines, while leaving the LCD timing generator and R33 enabled. 0 All LCD segments are off 1 All LCD segments are enabled and on or off according to their corresponding memory location. Unused LCD On. This bit turns on the LCD timing generator and R33. 0 LCD timing generator and Ron are off 1 LCD timing generator and Ron are on LCD Controller 25-19 25-20 LCD Controller Chapter 26 LCD_A Controller The LCD_A controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes the LCD_A controller. LCD_A controller is implemented on MSP430F41x2, MSP430x42x0, MSP430FG461x, MSP430F47x, MSP430FG47x, MSP430F47x3/4, and MSP430F471xx devices. Topic Page 26.1 LCD_A Controller Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.2 LCD_A Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.3 LCD_A Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21 LCD_A Controller 26-1 LCD_A Controller Introduction 26.1 LCD_A Controller Introduction The LCD_A controller directly drives LCD displays by creating the ac segment and common voltage signals automatically. The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs. The LCD controller features are: - Display memory - Automatic signal generation - Configurable frame frequency - Blinking capability - Regulated charge pump - Contrast control by software - Support for 4 types of LCDs: J Static J 2-mux, 1/2 bias or 1/3 bias J 3-mux, 1/2 bias or 1/3 bias J 4-mux, 1/2 bias or 1/3 bias The LCD controller block diagram is shown in Figure 26−1. Note: Maximum LCD Segment Control The maximum number of segment lines available differs with device. See the device-specific data sheet for available segment pins. 26-2 LCD_A Controller Figure 26−1. LCD_A Controller Block Diagram LCD_A Controller Introduction SEG39 0A4h Mux S39 Display Memory 20x 8−bits SEG38 Mux S38 Segment Output Control SEG1 Mux S1 SEG0 091h Mux S0 10 LCDSx LCDSON LCDFREQx LCDON ACLK 32768 Hz Divider fLCD /32 .. /512 Timing Generator LCDMXx Common Output Control COM3 COM2 COM1 COM0 VA VB VC VD V1 Analog V2 Voltage V3 Multiplexer V4 V5 VLCD OSCOFF (from SR) LCDMXx REXT R03EXT VLCDREFx VLCDx 4 Regulated Charge Pump/ Contrast Control V1 VLCD V2 LCD Bias Generator V3 V4 LCDCPEN LCDCAP/R33 LCDREF/R23 LCDREF/R13 R03 V5 LCD2B LCD_A Controller 26-3 LCD_A Controller Operation 26.2 LCD_A Controller Operation The LCD_A controller is configured with user software. The setup and operation of the LCD_A controller is discussed in the following sections. 26.2.1 LCD Memory The LCD memory map is shown in Figure 26−2. Each memory bit corresponds to one LCD segment, or is not used, depending on the mode. To turn on an LCD segment, its corresponding memory bit is set. Figure 26−2. LCD memory Associated 3 2 1 0 3 2 1 0 Common Pins Associated Address 7 0 n Segment Pins 0A4h -- -- -- -- -- -- -- -- 38 39, 38 0A3h -- -- -- -- -- -- -- -- 36 37, 36 0A2h -- -- -- -- -- -- -- -- 34 35, 34 0A1h -- -- -- -- -- -- -- -- 32 33, 32 0A0h -- -- -- -- -- -- -- -- 30 31, 30 09Fh -- -- -- -- -- -- -- -- 28 29, 28 09Eh -- -- -- -- -- -- -- -- 26 27, 26 09Dh -- -- -- -- -- -- -- -- 24 25, 24 09Ch 09Bh -- -- -- -- -- -- -- -- 22 -- -- -- -- -- -- -- -- 20 23, 22 21, 20 09Ah 099h 098h 097h -- -- -- -- -- -- -- -- 18 -- -- -- -- -- -- -- -- 16 -- -- -- -- -- -- -- -- 14 -- -- -- -- -- -- -- -- 12 19, 18 17, 16 15, 14 13, 12 096h -- -- -- -- -- -- -- -- 10 11, 10 095h -- -- -- -- -- -- -- -- 8 9, 8 094h -- -- -- -- -- -- -- -- 6 7, 6 093h -- -- -- -- -- -- -- -- 4 5, 4 092h -- -- -- -- -- -- -- -- 2 3, 2 091h -- -- -- -- -- -- -- -- 0 1, 0 Sn+1 Sn 26.2.2 Blinking the LCD The LCD controller supports blinking. The LCDSON bit is ANDed with each segment’s memory bit. When LCDSON = 1, each segment is on or off according to its bit value. When LCDSON = 0, each LCD segment is off. 26-4 LCD_A Controller LCD_A Controller Operation 26.2.3 LCD_A Voltage And Bias Generation The LCD_A module allows selectable sources for the peak output waveform voltage, V1, as well as the fractional LCD biasing voltages V2 − V5. VLCD may be sourced from AVCC, an internal charge pump, or externally. All internal voltage generation is disabled if the oscillator sourcing ACLK is turned off (OSCOFF = 1) or the LCD_A module is disabled (LCDON = 0). LCD Voltage Selection VLCD is sourced from AVCC when VLCDEXT = 0, VLCDx = 0, and VREFx = 0. VLCD is sourced from the internal charge pump when VLCDEXT = 0, VLCDPEN = 1, and VLCDx > 0. The charge pump is always sourced from DVCC. The VLCDx bits provide a software selectable LCD voltage from 2.6 V to 3.44 V (typical) independent of DVCC. See the device-specific data sheet for specifications. When the internal charge pump is used, a 4.7 μF or larger capacitor must be connected between pin LCDCAP and ground. Otherwise, irreversible damage can occur. When the charge pump is enabled, peak currents of 2 mA typical occur on DVCC. However, the charge pump duty cycle is approximately 1/1000, resulting in a 2 μA average current. The charge pump may be temporarily disabled by setting LCDCPEN = 0 with VLCDx > 0 to reduce system noise. In this case, the voltage present at the external capacitor is used for the LCD voltages until the charge pump is re-enabled. Note: Capacitor Required For Internal Charge Pump A 4.7 μF or larger capacitor must be connected from pin LCDCAP to ground when the internal charge pump is enabled. Otherwise, damage can occur. The internal charge pump may use an external reference voltage when VLCDREFx = 01. In this case, the charge pump voltage will be 3x the voltage applied externally to the LCDREF pin and the VLCDx bits are ignored. When VLCDEXT = 1, VLCD is sourced externally from the LCDCAP pin and the internal charge pump is disabled. The charge pump and internal bias generation require an input clock source of 32768 Hz +/− 10%. If neither is used, the input clock frequency may be different per the application needs. LCD Bias Generation The fractional LCD biasing voltages, V2 − V5 can be generated internally or externally, independent of the source for VLCD. The LCD bias generation block diagram is shown in Figure 26−3. LCD_A Controller 26-5 LCD_A Controller Operation To source the bias voltages V2 − V4 externally, REXT is set. This also disables the internal bias generation. Typically an equally weighted resistor divider is used with resistors ranging from 100 kW to 1 MW. When using an external resistor divider, the VLCD voltage may be sourced from the internal charge pump when VLCDEXT = 0. V5 can also be sourced externally when R03EXT is set. When using an external resistor divider R33 may serve as a switched-VLCD output when VLCDEXT = 0. This allows the power to the resistor ladder to be turned off eliminating current consumption when the LCD is not used. When VLCDEXT = 1, R33 serves as a VLCD input. Figure 26−3. Bias Generation DVCC AV CC VLCDx > 0 VLCDREFx > 0 Charge Pump VLCD 0 Internal VLCD 1 LCD Off LCDCAP/R33 R R23 R R LCDREF/R13 VLCDEXT 0 0 0 LCD2B V1 (VLCD) REXT V2 int. 0 1 V2 (2/3 VLCD) V3 int. 0 1 V3 (1/2 VLCD) R R V4 int. 0 1 V4 (1/3 VLCD) Rx Rx Rx Static 1/2 Bias 1/3 Bias R03 Optional External Resistors Rx = Optional Contrast Control 0 V5 1 R03EXT 26-6 LCD_A Controller LCD_A Controller Operation The internal bias generator supports 1/2 bias LCDs when LCD2B = 1, and 1/3 bias LCDs when LCD2B = 0 in 2-mux, 3-mux, and 4-mux modes. In static mode, the internal divider is disabled. Some devices share the LCDCAP, R33, and R23 functions. In this case, the charge pump cannot be used together with an external resistor divider with 1/3 biasing. When R03 is not available externally, V5 is always AVSS. LCD Contrast Control The peak voltage of the output waveforms together with the selected mode and biasing determine the contrast and the contrast ratio of the LCD. The LCD contrast can be controlled in software by adjusting the LCD voltage generated by the integrated charge pump using the VLCDx settings. The contrast ratio depends on the used LCD display and the selected biasing scheme. Table 26−1 shows the biasing configurations that apply to the different modes together with the RMS voltages for the segments turned on (VRMS,ON) and turned off (VRMS,OFF) as functions of VLCD. It also shows the resulting contrast ratios between the on and off states. Table 26−1.LCD Voltage and Biasing Characteristics Mode Static 2−mux 2−mux 3−mux 3−mux 4−mux 4−mux Bias Config Static 1/2 1/3 1/2 1/3 1/2 1/3 LCDMx LCD2B 00 X 01 1 01 0 10 1 10 0 11 1 11 0 COM Lines 1 2 2 3 3 4 4 Voltage Levels V1, V5 V1, V3, V5 V1, V2, V4, V5 V1, V3, V5 V1, V2, V4, V5 V1, V3, V5 V1, V2, V4, V5 VRMS,OFF/ VLCD 0 0.354 0.333 0.408 0.333 0.433 0.333 VRMS,ON/ VLCD 1 0.791 0.745 0.707 0.638 0.661 0.577 Contrast Ratio VRMS,ON/ VRMS,OFF 1/0 2.236 2.236 1.732 1.915 1.528 1.732 A typical approach to determine the required VLCD is by equating VRMS,OFF with a defined LCD threshold voltage, typically when the LCD exhibits approximately 10% contrast (Vth,10%): VRMS,OFF = Vth,10%. Using the values for VRMS,OFF/VLCD provided in the table results in VLCD = Vth,10%/(VRMS,OFF/VLCD). In the static mode, a suitable choice is VLCD greater or equal than 3 times Vth,10%. In 3-mux and 4-mux mode typically a 1/3 biasing is used but a 1/2 biasing scheme is also possible. The 1/2 bias reduces the contrast ratio but the advantage is a reduction of the required full-scale LCD voltage VLCD. LCD_A Controller 26-7 LCD_A Controller Operation 26.2.4 LCD Timing Generation The LCD_A controller uses the fLCD signal from the integrated ACLK prescaler to generate the timing for common and segment lines. ACLK is assumed to be 32768 Hz for generating fLCD. The fLCD frequency is selected with the LCDFREQx bits. The proper fLCD frequency depends on the LCD’s requirement for framing frequency and the LCD multiplex rate and is calculated by: fLCD = 2 × mux × fFrame For example, to calculate fLCD for a 3-mux LCD, with a frame frequency of 30 Hz to 100 Hz: fFrame (from LCD data sheet) = 30 Hz to 100 Hz fLCD = 2 × 3 × fFrame fLCD(min) = 180 Hz fLCD(max) = 600 Hz select fLCD = 32768/128 = 256 Hz or 2768/96 = 341 Hz or 32768/64 = 512 Hz. The lowest frequency has the lowest current consumption. The highest frequency has the least flicker. 26.2.5 LCD Outputs Some LCD segment, common, and Rxx functions are multiplexed with digital I/O functions. These pins can function either as digital I/O or as LCD functions. The pin functions for COMx and Rxx, when multiplexed with digital I/O, are selected using the applicable PxSELx bits as described in the Digital I/O chapter. The LCD segment functions, when multiplexed with digital I/O, are selected using the LCDSx bits in the LCDAPCTLx registers. Note: Using shared pins as digital I/Os If pins that share digital I/O and LCD functions are used as digital I/Os they should not be toggled at frequencies >10kHz while the LCD is enabled (LCDON=1); otherwise, increased current consumption could be observed. The LCDSx bits selects the LCD function in groups of four pins. When LCDSx = 0, no multiplexed pin is set to LCD function. When LCDSx = 1, the complete group of four is selected as LCD function. Note: LCDSx Bits Do Not Affect Dedicated LCD Segment Pins The LCDSx bits only affect pins with multiplexed LCD segment functions and digital I/O functions. Dedicated LCD segment pins are not affected by the LCDSx bits. 26-8 LCD_A Controller LCD_A Controller Operation 26.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and one common line, COM0, is used. Figure 26−4 shows some example static waveforms. Figure 26−4. Example Static Waveforms V1 COM0 V5 fframe V1 SP1 V5 COM0 V1 SP2 V5 SP1 SP6 a V1 b SP2 Resulting Voltage for SP7 Segment a (COM0−SP1) Segment Is On. 0V SP3 V1 SP5 SP8 SP4 Resulting Voltage for Segment b (COM0−SP2) 0V Segment Is Off. SP = Segment Pin LCD_A Controller 26-9 LCD_A Controller Operation Figure 26−5 shows an example static LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 26−5. Static LCD Example LCD a fg b a fg b a fg b a fg b e c d h DIGIT4 e d ce h d ce c h d h DIGIT1 Pinout and Connections Connections ’430 Pins LCD Pinout S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 COM0 COM1 COM2 COM3 PIN COM0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 NC NC NC 1a 1b 1c 1d 1e 1f 1g 1h 2a 2b 2c 2d 2e 2f 2g 2h 3a 3b 3c 3d 3e 3f 3g 3h 4a 4b 4c 4d 4e 4f 4g 4h COM0 Display Memory COM 3 2 1 0 3 2 1 0 MAB 0A0h -- -- -- h -- -- -- g 09Fh -- -- -- f -- -- -- e 09Eh -- -- -- d -- -- -- c 09Dh -- -- -- b -- -- -- a 09Ch -- -- -- h -- -- -- g 09Bh -- -- -- f -- -- -- e 09Ah -- -- -- d -- -- -- c 099h -- -- -- b -- -- -- a 098h -- -- -- h -- -- -- g 097h -- -- -- f -- -- -- e 096h -- -- -- d -- -- -- c 095h -- -- -- b -- -- -- a 094h -- -- -- h -- -- -- g 093h -- -- -- f -- -- -- e 092h -- -- -- d -- -- -- c 091h -- -- -- b -- -- -- a n = 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 Digit 4 Digit 3 Digit 2 Digit 1 A G0 3 B3 2 1 0 3 2 1 0 0 3 G A B Parallel-Serial Conversion Sn+1 Sn 26-10 LCD_A Controller LCD_A Controller Operation Static Mode Software Example ; All eight segments of a digit are often located in four ; display memory bytes with the static display method. ; a EQU 001h b EQU 010h c EQU 002h d EQU 020h e EQU 004h f EQU 040h g EQU 008h h EQU 080h ; The register content of Rx should be displayed. : The Table represents the ’on’−segments according to the ; content of Rx. MOV.B Table (Rx),RY MOV.B Ry,&LCDn RRA Ry MOV.B Ry,&LCDn+1 RRA Ry MOV.B Ry,&LCDn+2 RRA Ry MOV.B Ry,&LCDn+3 ; Load segment information ; into temporary memory. ; (Ry) = 0000 0000 hfdb geca ; Note: ; All bits of an LCD memory ’ byte are written ; (Ry) = 0000 0000 0hfd bgec ; Note: ; All bits of an LCD memory ; byte are written ; (Ry) = 0000 0000 00hf dbge ; Note: ; All bits of an LCD memory ’ byte are written ; (Ry) = 0000 0000 000h fdbg ; Note: ; All bits of an LCD memory ’ byte are written ........... ........... ; Table DB a+b+c+d+e+f DB b+c; ........... ........... DB ........... ; displays ”0” ; displays ”1” LCD_A Controller 26-11 LCD_A Controller Operation 26.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and two common lines, COM0 and COM1, are used. Figure 26−6 shows some example 2-mux, 1/2 bias waveforms. Figure 26−6. Example 2-Mux Waveforms COM1 V1 COM0 V3 fframe V5 V1 COM1 V3 V5 COM0 V1 SP1 V5 V1 SP2 b V5 SP1 V1 Resulting Voltage for V3 SP4 h Segment h (COM0−SP2) SP2 Segment Is On. 0V −V3 SP3 −V1 SP = Segment Pin V1 Resulting Voltage for V3 Segment b (COM1−SP2) 0V Segment Is Off. −V3 −V5 26-12 LCD_A Controller LCD_A Controller Operation Figure 26−7 shows an example 2-mux LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application completely depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 26−7. 2−Mux LCD Example LCD a fg b a fg b e c d h DIGIT8 e c d h DIGIT1 Pinout and Connections Connections ’430 Pins LCD Pinout PIN COM0 COM1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 NC NC 1f 1a 1h 1b 1d 1c 1e 1g 2f 2a 2h 2b 2d 2c 2e 2g 3f 3a 3h 3b 3d 3c 3e 3g 4f 4a 4h 4b 4d 4c 4e 4g 5f 5a 5h 5b 5d 5c 5e 5g 6f 6a 6h 6b 6d 6c 6e 6g 7f 7a 7h 7b 7d 7c 7e 7g 8f 8a 8h 8b 8d 8c 8e 8g COM0 COM1 Display Memory COM 3 2 1 0 3 2 1 MAB 0A0h -- -- g e -- -- c 09Fh -- -- b h -- -- a 09Eh -- -- g e -- -- c 09Dh -- -- b h -- -- a 09Ch -- -- g e -- -- c 09Bh -- -- b h -- -- a 09Ah -- -- g e -- -- c 099h -- -- b h -- -- a 098h -- -- g e -- -- c 097h -- -- b h -- -- a 096h -- -- g e -- -- c 095h -- -- b h -- -- a 094h -- -- g e -- -- c 093h -- -- b h -- -- a 092h -- -- g e -- -- c 091h -- -- b h -- -- a A B G0 3 3 2 1 0 3 2 1 Sn+1 Sn 0 d n = 30 1/2 Digit 8 f 28 d 26 Digit 7 f 24 d f 22 Digit 6 20 d 18 f 16 Digit 5 d 14 Digit 4 f 12 d 10 f 8 Digit 3 d 6 f 4 Digit 2 d 2 Digit 1 f 0 0 Parallel- 0 3 G A B Serial Conversion LCD_A Controller 26-13 LCD_A Controller Operation 2-Mux Mode Software Example ; All eight segments of a digit are often located in two ; display memory bytes with the 2mux display rate ; a EQU 002h b EQU 020h c EQU 008h d EQU 004h e EQU 040h f EQU 001h g EQU 080h h EQU 010h ; The register content of Rx should be displayed. ; The Table represents the ’on’−segments according to the ; content of Rx. ; ........... ........... MOV.B Table(Rx),Ry ; Load segment information into ; temporary memory. MOV.B Ry,&LCDn ; (Ry) = 0000 0000 gebh cdaf ; Note: ; All bits of an LCD memory byte ; are written RRA Ry ; (Ry) = 0000 0000 0geb hcda RRA Ry ; (Ry) = 0000 0000 00ge bhcd MOV.B Ry,&LCDn+1 ; Note: ; All bits of an LCD memory byte ; are written ........... ........... ........... Table DB a+b+c+d+e+f ; displays ”0” ........... DB a+b+c+d+e+f+g ; displays ”8” ........... ........... DB ........... ; 26-14 LCD_A Controller LCD_A Controller Operation 26.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments and three common lines (COM0, COM1, and COM2) are used. Figure 26−8 shows some example 3-mux, 1/3 bias waveforms. Figure 26−8. Example 3-Mux Waveforms COM2 V1 COM0 V2 V4 fframe V5 V1 COM1 COM1 V2 V4 V5 COM0 V1 COM2 V2 V4 V5 V1 V2 SP1 V4 V5 e V1 d SP2 SP1 SP3 V5 SP2 V1 SP = Segment Pin SP3 V5 V1 Resulting Voltage for Segment e (COM0−SP1) 0V Segment Is Off. −V1 V1 Resulting Voltage for Segment d (COM0−SP2) 0V Segment Is On. −V1 LCD_A Controller 26-15 LCD_A Controller Operation Figure 26−9 shows an example 3-mux LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 26−9. 3-Mux LCD Example LCD ya fg b e c d h DIGIT10 ya fg b e c d h DIGIT1 Pinout and Connections Connections ’430 Pins LCD Pinout PIN COM0 COM1 COM2 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 NC 1e 1f 1y 1d 1g 1a 1h 1c 1b 2e 2f 2y 2d 2g 2a 2h 2c 2b 3e 3f 3y 3d 3g 3a 3h 3c 3b 4e 4f 4y 4d 4g 4a 4h 4c 4b 5e 5f 5y 5d 5g 5a 5h 5c 5b 6e 6f 6y 6d 6g 6a 6h 6c 6b 7e 7f 7y 7d 7g 7a 7h 7c 7b 8e 8f 8y 8d 8g 8a 8h 8c 8b 9e 9f 9y 9d 9g 9a 9h 9c 9b 10e 10f 10y 10d 10g 10a 10h 10c 10b COM0 COM1 COM2 Display Memory COM 3 2 1 0 3 2 1 0 MAB 09Fh -- a g d -- y f e n = 30 09Eh -- b c h -- a g d 09Dh -- y f e -- b c h 09Ch -- a g d -- y f e 09Bh -- b c h -- a g d -- y f e -- b c h 09Ah -- a g d -- y f e 099h -- b c h -- a g d 098h -- y f e -- b c h 097h -- a g d -- y f e 096h -- b c h -- a g d 095h -- y f e -- b c h 094h -- a g d -- y f e 28 Digit 10 26 Digit 9 24 22 Digit 8 20 Digit 7 18 16 Digit 6 14 Digit 5 12 10 Digit 4 8 Digit 3 6 093h -- b c h -- a g d 092h -- y f e -- b c h 091h -- a g d -- y f e 4 Digit 2 2 Digit 1 0 A G0 3 B3 2 10 3 2 1 0 0 3G A B ParallelSerial Conversion Sn+1 Sn 26-16 LCD_A Controller LCD_A Controller Operation 3-Mux Mode Software Example ; The 3mux rate can support nine segments for each ; digit. The nine segments of a digit are located in ; 1 1/2 display memory bytes. ; a EQU 0040h b EQU 0400h c EQU 0200h d EQU 0010h e EQU 0001h f EQU 0002h g EQU 0020h h EQU 0100h Y EQU 0004h ; The LSDigit of register Rx should be displayed. ; The Table represents the ’on’−segments according to the ; LSDigit of register of Rx. ; The register Ry is used for temporary memory ; ODDDIG RLA Rx ; LCD in 3mux has 9 segments per ; digit; word table required for ; displayed characters. MOV Table(Rx),Ry ; Load segment information to ; temporary mem. ; (Ry) = 0000 0bch 0agd 0yfe MOV.B Ry,&LCDn ; write ’a, g, d, y, f, e’ of ; Digit n (LowByte) SWPB Ry ; (Ry) = 0agd 0yfe 0000 0bch BIC.B #07h,&LCDn+1 ; write ’b, c, h’ of Digit n ; (HighByte) BIS.B Ry,&LCDn+1 ..... EVNDIG RLA Rx ; LCD in 3mux has 9 segments per ; digit; word table required for ; displayed characters. MOV Table(Rx),Ry ; Load segment information to ; temporary mem. ; (Ry) = 0000 0bch 0agd 0yfe RLA Ry ; (Ry) = 0000 bch0 agd0 yfe0 RLA Ry ; (Ry) = 000b ch0a gd0y fe00 RLA Ry ; (Ry) = 00bc h0ag d0yf e000 RLA Ry ; (Ry) = 0bch 0agd 0yfe 0000 BIC.B #070h,&LCDn+1 BIS.B Ry,&LCDn+1 ; write ’y, f, e’ of Digit n+1 ; (LowByte) SWPB Ry ; (Ry) = 0yfe 0000 0bch 0agd MOV.B Ry,&LCDn+2 ; write ’b, c, h, a, g, d’ of ; Digit n+1 (HighByte) ........... Table DW a+b+c+d+e+f ; displays ”0” DW b+c ; displays ”1” ........... ........... DW a+e+f+g ; displays ”F” LCD_A Controller 26-17 LCD_A Controller Operation 26.2.9 4-Mux Mode In 4-mux mode, each MSP430 segment pin drives four LCD segments and all four common lines (COM0, COM1, COM2, and COM3) are used. Figure 26−10 shows some example 4-mux, 1/3 bias waveforms. Figure 26−10. Example 4-Mux Waveforms COM3 V1 COM0 V2 COM2 V4 fframe V5 V1 COM1 COM1 V2 V4 V5 COM0 V1 COM2 V2 V4 V5 V1 COM3 V2 V4 V5 e c V1 V2 SP1 V4 SP2 V5 SP1 SP = Segment Pin V1 V2 SP2 V4 V5 V1 Resulting Voltage for Segment e (COM1−SP1) 0V Segment Is Off. −V1 V1 Resulting Voltage for Segment c (COM1−SP2) 0V Segment Is On. −V1 26-18 LCD_A Controller LCD_A Controller Operation Figure 26−11 shows an example 4-mux LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 26−11.4-Mux LCD Example LCD a fg b a fg b e c d h DIGIT15 e c d h DIGIT1 Pinout and Connections Connections COM 3 ’430 Pins LCD Pinout PIN COM0 COM1 COM2COM3 MAB 09Fh a S0 1 1d 1e 1g 1f S1 2 1h 1c 1b 1a S2 3 2d 2e 2g 2f S3 4 2h 2c 2b 2a S4 5 3d 3e 3g 3f S5 6 3h 3c 3b 3a S6 7 4d 4e 4g 4f S7 8 4h 4c 4b 4a S8 9 5d 5e 5g 5f S9 10 5h 5c 5b 5a S10 11 6d 6e 6g 6f S11 12 6h 6c 6b 6a S12 13 7d 7e 7g 7f S13 14 7h 7c 7b 7a 09Eh a 09Dh a 09Ch a 09Bh a a 09Ah a 099h a 098h a 097h a 096h a 095h a S14 15 8d 8e 8g 8f S15 16 8h 8c 8b 8a S16 17 9d 9e 9g 9f 094h a 093h a S17 18 9h 9c 9b 9a 092h a S18 19 10d 10e 10g 10f S19 20 10h 10c 10b 10a 091h a S20 21 11d 11e 11g 11f S21 22 11h 11c 11b 11a S22 23 12d 12e 12g 12f S23 24 12h 12c 12b 12a S24 25 13d 13e 13g 13f A G0 3 B3 S25 26 13h 13c 13b 13a S26 27 14d 14e 14g 14f S27 28 14h 14c 14b 14a S28 29 15d 15e 15g 15f S29 30 15h 15c 15b 15a COM0 31 COM0 COM1 32 COM1 COM2 33 COM2 COM3 34 COM3 Display Memory 210 321 b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e b ch fg e 210 3 21 Sn+1 Sn 0 d n = 30 Digit 16 d 28 Digit 15 d 26 Digit 14 d 24 Digit 13 d 22 Digit 12 d 20 Digit 11 d 18 Digit 10 d 16 Digit 9 d 14 Digit 8 d 12 Digit 7 d 10 Digit 6 d 8 Digit 5 d 6 Digit 4 d 4 Digit 3 d 2 Digit 2 d 0 Digit 1 0 0 3G A B ParallelSerial Conversion LCD_A Controller 26-19 LCD_A Controller Operation 4-Mux Mode Software Example ; The 4mux rate supports eight segments for each digit. ; All eight segments of a digit can often be located in ; one display memory byte a EQU 080h b EQU 040h c EQU 020h d EQU 001h e EQU 002h f EQU 008h g EQU 004h h EQU 010h ; ; The LSDigit of register Rx should be displayed. ; The Table represents the ’on’−segments according to the ; content of Rx. ; MOV.B Table(Rx),&LCDn ; n = 1 ..... 15 ; all eight segments are ; written to the display ; memory ........... ........... Table DB a+b+c+d+e+f DB b+c ........... ........... DB b+c+d+e+g DB a+d+e+f+g DB a+e+f+g ; displays ”0” ; displays ”1” ; displays ”d” ; displays ”E” ; displays ”F” 26-20 LCD_A Controller LCD_A Controller Operation 26.3 LCD Controller Registers The LCD Controller registers are listed in Table 26−2. Table 26−2.LCD Controller Registers Register LCD_A control register LCD memory 1 LCD memory 2 LCD memory 3 LCD memory 4 LCD memory 5 LCD memory 6 LCD memory 7 LCD memory 8 LCD memory 9 LCD memory 10 LCD memory 11 LCD memory 12 LCD memory 13 LCD memory 14 LCD memory 15 LCD memory 16 LCD memory 17 LCD memory 18 LCD memory 19 LCD memory 20 LCD_A port control 0 LCD_A port control 1 LCD_A voltage control 0 LCD_A voltage control 1 Short Form LCDACTL LCDM1 LCDM2 LCDM3 LCDM4 LCDM5 LCDM6 LCDM7 LCDM8 LCDM9 LCDM10 LCDM11 LCDM12 LCDM13 LCDM14 LCDM15 LCDM16 LCDM17 LCDM18 LCDM19 LCDM20 LCDAPCTL0 LCDAPCTL1 LCDAVCTL0 LCDAVCTL1 Register Type Address Read/write 090h Read/write 091h Read/write 092h Read/write 093h Read/write 094h Read/write 095h Read/write 096h Read/write 097h Read/write 098h Read/write 099h Read/write 09Ah Read/write 09Bh Read/write 09Ch Read/write 09Dh Read/write 09Eh Read/write 09Fh Read/write 0A0h Read/write 0A1h Read/write 0A2h Read/write 0A3h Read/write 0A4h Read/write 0ACh Read/write 0ADh Read/write 0AEh Read/write 0AFh Initial State Reset with PUC Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC LCD_A Controller 26-21 LCD_A Controller Operation LCDACTL, LCD_A Control Register 7 rw−0 6 LCDFREQx rw−0 5 rw−0 4 3 LCDMXx rw−0 rw−0 2 LCDSON rw−0 1 Unused rw−0 0 LCDON rw−0 LCDFREQx Bits 7-5 LCDMXx Bits 4-3 LCDSON Bit 2 Unused LCDON Bit 1 Bit 0 LCD frequency select. These bits select the ACLK divider for the LCD frequency. 000 Divide by 32 001 Divide by 64 010 Divide by 96 011 Divide by 128 100 Divide by 192 101 Divide by 256 110 Divide by 384 111 Divide by 512 LCD mux rate. These bits select the LCD mode. 00 Static 01 2-mux 10 3-mux 11 4-mux LCD segments on. This bit supports flashing LCD applications by turning off all segment lines, while leaving the LCD timing generator and R33 enabled. 0 All LCD segments are off 1 All LCD segments are enabled and on or off according to their corresponding memory location. Unused LCD On. This bit turns on the LCD_A module. 0 LCD_A module off. 1 LCD_A module on. 26-22 LCD_A Controller LCDAPCTL0, LCD_A Port Control Register 0 LCD_A Controller Operation 7 LCDS28 rw−0 6 LCDS24 rw−0 5 LCDS20 rw−0 4 LCDS16 rw−0 3 LCDS12 rw−0 2 LCDS8 rw−0 1 LCDS4 rw−0 0 LCDS0† rw−0 † Segments S0−S3 on the MSP430FG461x devices are disabled from LCD functionality when charge pump is enabled. LCDS28 LCDS24 LCDS20 LCDS16 LCDS12 LCDS8 LCDS4 LCDS0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCD segment 28 to 31 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCD segment 24 to 27 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCD segment 20 to 23 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCD segment 16 to 19 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCD segment 12 to 15 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCD segment 8 to 11 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCD segment 4 to 7 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCD segment 0 to 3 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCD_A Controller 26-23 LCD_A Controller Operation LCDAPCTL1, LCD_A Port Control Register 1 7 rw−0 6 rw−0 5 4 Unused rw−0 rw−0 3 rw−0 2 rw−0 1 LCDS36 rw−0 0 LCDS32 rw−0 Unused LCDS36 LCDS32 Bits 7−2 Bit 1 Bit 0 Unused LCD segment 36 to 39 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCD segment 32 to 35 enable This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions 26-24 LCD_A Controller LCDAVCTL0, LCD_A Voltage Control Register 0 7 Unused rw−0 6 R03EXT rw−0 5 REXT rw−0 4 3 VLCDEXT LCDCPEN rw−0 rw−0 LCD_A Controller Operation 2 1 VLCDREFx rw−0 rw−0 0 LCD2B rw−0 Unused R03EXT Bit 7 Bit 6 REXT Bit 5 VLCDEXT Bit 4 LCDCPEN Bit 3 VLCDREFx Bits 2−1 LCD2B Bit 0 Unused V5 voltage select. This bit selects the external connection for the lowest LCD voltage. R03EXT is ignored if there is no R03 pin available. 0 V5 is AVSS 1 V5 is sourced from the R03 pin V2 − V4 voltage select. This bit selects the external connections for voltages V2 − V4. 0 V2 − V4 are generated internally 1 V2 − V4 are sourced externally and the internal bias generator is switched off VLCD source select 0 VLCD is generated internally 1 VLCD is sourced externally Charge pump enable. 0 Charge pump disabled. 1 Charge pump enabled when VLCD is generated internally (VLCDEXT = 0) and VLCDx > 0 or VLCDREFx > 0. Charge pump reference select 00 Internal 01 External 10 Reserved 11 Reserved Bias select. LCD2B is ignored when LCDMx = 00. 0 1/3 bias 1 1/2 bias LCD_A Controller 26-25 LCD_A Controller Operation LCDAVCTL1, LCD_A Voltage Control Register 1 7 rw−0 6 Unused rw−0 5 rw−0 4 rw−0 3 2 VLCDx rw−0 rw−0 1 rw−0 0 Unused rw−0 Unused VLCDx Unused Bits 7−5 Bits 4−1 Bit 0 Unused Charge pump voltage select. LCDCPEN must be 1 for the charge pump to be enabled. AVCC is used for VLCD when VLCDx = 0000 and VREFx = 00 and VLCDEXT = 0. 0000 Charge pump disabled 0001 VLCD = 2.60 V 0010 VLCD = 2.66 V 0011 VLCD = 2.72 V 0100 VLCD = 2.78 V 0101 VLCD = 2.84 V 0110 VLCD = 2.90 V 0111 VLCD = 2.96 V 1000 VLCD = 3.02 V 1001 VLCD = 3.08 V 1010 VLCD = 3.14 V 1011 VLCD = 3.20 V 1100 VLCD = 3.26 V 1101 VLCD = 3.32 V 1110 VLCD = 3.38 V 1111 VLCD = 3.44 V Unused 26-26 LCD_A Controller Chapter 27 ADC10 The ADC10 module is a high-performance 10-bit analog-to-digital converter. This chapter describes the operation of the ADC10 module of the 4xx family. The ADC10 is implemented on the MSP4340F41x2 devices. Topic Page 16.1 ADC10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 ADC10 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.3 ADC10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 ADC10 27-1 ADC10 Introduction 27.1 ADC10 Introduction The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC). The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention. The module can be configured with user software to support a variety of applications. ADC10 features include: - Greater than 200 ksps maximum conversion rate - Monotonic10-bit converter with no missing codes - Sample-and-hold with programmable sample periods - Conversion initiation by software or Timer_A - Software selectable on-chip reference voltage generation (1.5 V or 2.5 V) - Software selectable internal or external reference - Up to twelve external input channels - Conversion channels for internal temperature sensor, VCC, and external references - Selectable conversion clock source - Single-channel, repeated single-channel, sequence, and repeated sequence conversion modes - ADC core and reference voltage can be powered down separately - Data transfer controller for automatic storage of conversion results The block diagram of ADC10 is shown in Figure 27−1. 27-2 ADC10 Figure 27−1. ADC10 Block Diagram ADC10 Introduction A0 A1 A2 A3 A4 A5 A6 A7 A12† A13† A14† A15† VeREF+ REFOUT SREF1 0 VREF+ 1 REFBURST ADC10SR VREF−/VeREF− INCHx 4 Auto CONSEQx AVCC 11 10 01 00 AVSS 2_5V 1 on 0 1.5V or 2.5V Reference Ref_x REFON INCHx=0Ah AVCC SREF1 SREF0 ADC10OSC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AVCC SREF2 10 ADC10ON ADC10SSELx ADC10DIVx Sample and Hold S/H VR− VR+ 10−bit SAR Convert BUSY Divider /1 .. /8 ADC10CLK ISSH SAMPCON Sample Timer SHI 0 /4/8/16/64 1 ADC10DF ADC10SHTx MSC 00 01 ACLK 10 MCLK 11 SMCLK ENC Sync SHSx 00 01 10 11 ADC10SC TA0_1 TA 1_0 TA1_1 INCHx=0Bh Ref_x ADC10MEM R Data Transfer Controller n RAM, Flash, Peripherials ADC10SA R AVSS ADC10CT ADC10TB ADC10B1 †Not all devices support all channels. See the devices specific datasheet for details. ADC10 27-3 ADC10 Operation 27.2 ADC10 Operation The ADC10 module is configured with user software. The setup and operation of the ADC10 is discussed in the following sections. 27.2.1 10-Bit ADC Core The ADC core converts an analog input to its 10-bit digital representation and stores the result in the ADC10MEM register. The core uses two programmable/selectable voltage levels (VR+ and VR−) to define the upper and lower limits of the conversion. The digital output (NADC) is full scale (03FFh) when the input signal is equal to or higher than VR+, and zero when the input signal is equal to or lower than VR−. The input channel and the reference voltage levels (VR+ and VR−) are defined in the conversion-control memory. Conversion results may be in straight binary format or 2s-complement format. The conversion formula for the ADC result when using straight binary format is: NADC + 1023 Vin – VR– VR)– VR– The ADC10 core is configured by two control registers, ADC10CTL0 and ADC10CTL1. The core is enabled with the ADC10ON bit. With few exceptions the ADC10 control bits can only be modified when ENC = 0. ENC must be set to 1 before any conversion can take place. Conversion Clock Selection The ADC10CLK is used both as the conversion clock and to generate the sampling period. The ADC10 source clock is selected using the ADC10SSELx bits and can be divided from 1-8 using the ADC10DIVx bits. Possible ADC10CLK sources are SMCLK, MCLK, ACLK and an internal oscillator ADC10OSC . The ADC10OSC, generated internally, is in the 5-MHz range, but varies with individual devices, supply voltage, and temperature. See the device-specific datasheet for the ADC10OSC specification. The user must ensure that the clock chosen for ADC10CLK remains active until the end of a conversion. If the clock is removed during a conversion, the operation will not complete, and any result will be invalid. 27-4 ADC10 ADC10 Operation 27.2.2 ADC10 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 27−2. The input multiplexer is also a T-switch to minimize the coupling between channels. Channels that are not selected are isolated from the A/D and the intermediate node is connected to analog ground (VSS) so that the stray capacitance is grounded to help eliminate crosstalk. The ADC10 uses the charge redistribution method. When the inputs are internally switched, the switching action may cause transients on the input signal. These transients decay and settle before causing errant conversion. Figure 27−2. Analog Multiplexer R ~ 100Ohm INCHx Ax Input ESD Protection Analog Port Selection The ADC10 external inputs Ax, VeREF+, and VREF− share terminals with general purpose I/O ports, which are digital CMOS gates (see device-specific datasheet). When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption. The ADC10AEx bits provide the ability to disable the port pin input and output buffers. ; P7.5 on MSP430x41x2 device configured for analog input BIS.B #01h,&ADC10AE0 ; P7.5 ADC10 function and enable ADC10 27-5 ADC10 Operation 27.2.3 Voltage Reference Generator The ADC10 module contains a built-in voltage reference with two selectable voltage levels. Setting REFON = 1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V. When REF2_5V = 0, the reference is 1.5 V. The internal reference voltage may be used internally and, when REFOUT = 0, externally on pin VREF+. External references may be supplied for VR+ and VR− through pins A4 and A3 respectively. When external references are used, or when VCC is used as the reference, the internal reference may be turned off to save power. An external positive reference VeREF+ can be buffered by setting SREF0 = 1 and SREF1 = 1. This allows using an external reference with a large internal resistance at the cost of the buffer current. When REFBURST = 1 the increased current consumption is limited to the sample and conversion period. External storage capacitance is not required for the ADC10 reference source as on the ADC12. Internal Reference Low-Power Features The ADC10 internal reference generator is designed for low power applications. The reference generator includes a band-gap voltage source and a separate buffer. The current consumption of each is specified separately in the device-specific datasheet. When REFON = 1, both are enabled and when REFON = 0 both are disabled. The total settling time when REFON becomes set is  30 μs. When REFON = 1, but no conversion is active, the buffer is automatically disabled and automatically re-enabled when needed. When the buffer is disabled, it consumes no current. In this case, the band-gap voltage source remains enabled. When REFOUT = 1, the REFBURST bit controls the operation of the internal reference buffer. When REFBURST = 0, the buffer will be on continuously, allowing the reference voltage to be present outside the device continuously. When REFBURST = 1, the buffer is automatically disabled when the ADC10 is not actively converting, and automatically re-enabled when needed. The internal reference buffer also has selectable speed vs. power settings. When the maximum conversion rate is below 50 ksps, setting ADC10SR = 1 reduces the current consumption of the buffer approximately 50%. 27.2.4 Auto Power-Down The ADC10 is designed for low power applications. When the ADC10 is not actively converting, the core is automatically disabled and automatically re-enabled when needed. The ADC10OSC is also automatically enabled when needed and disabled when not needed. When the core or oscillator is disabled, it consumes no current. 27-6 ADC10 ADC10 Operation 27.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following for MSP430F41x2: - The ADC10SC bit - The Timer_A0 Output Unit 1 - The Timer_A1 Output Unit 0 - The Timer_A1 Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit. The SHTx bits select the sample period tsample to be 4, 8, 16, or 64 ADC10CLK cycles. The sampling timer sets SAMPCON high for the selected sample period after synchronization with ADC10CLK. Total sampling time is tsample plus tsync.The high-to-low SAMPCON transition starts the analog-to-digital conversion, which requires 11 ADC10CLK cycles as shown in Figure 27−3. Figure 27−3. Sample Timing Start Sampling Stop Start Sampling Conversion Conversion Complete SHI SAMPCON ADC10CLK tsync tsample 13 x ADC10CLKs tconvert Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time tsample, as shown below in Figure 27−4. An internal MUX-on input resistance RI (max. 2 kΩ) in series with capacitor CI (max. 27 pF) is seen by the source. The capacitor CI voltage VC must be charged to within ½ LSB of the source voltage VS for an accurate 10-bit conversion. ADC10 27-7 ADC10 Operation Figure 27−4. Analog Input Equivalent Circuit MSP430 RS VI RI VS VC CI VI = Input voltage at pin Ax VS = External source voltage RS = External source resistance RI = Internal MUX-on input resistance CI = Input capacitance VC = Capacitance-charging voltage The resistance of the source RS and RI affect tsample.The following equations can be used to calculate the minimum sampling time for a 10-bit conversion. tsample u (RS ) RI) ln(211) CI Substituting the values for RI and CI given above, the equation becomes: tsample u (RS ) 2k) 7.625 27pF For example, if RS is 10 kΩ, tsample must be greater than 2.47 μs. When the reference buffer is used in burst mode, the sampling time must be greater than the sampling time calculated and the settling time of the buffer, tREFBURST: NJ tsample u (RS ) RI) tREFBURST ln(211) CI For example, if VRef is 1.5 V and RS is 10 kΩ, tsample must be greater than 2.47 μs when ADC10SR = 0, or 2.5 μs when ADC10SR = 1. See the device-specific datasheet for parameters. To calculate the buffer settling time when using an external reference, the formula is: tREFBURST + SR VRef * 0.5ms Where: SR: Vref: Buffer slew rate (~1 μs/V when ADC10SR = 0 and ~2 μs/V when ADC10SR = 1) External reference voltage 27-8 ADC10 ADC10 Operation 27.2.6 Conversion Modes The ADC10 has four operating modes selected by the CONSEQx bits as discussed in Table 27−1. Table 27−1.Conversion Mode Summary CONSEQx Mode Operation 00 Single channel A single channel is converted once. single-conversion 01 Sequence-of- channels A sequence of channels is converted once. 10 Repeat single channel A single channel is converted repeatedly. 11 Repeat sequence- A sequence of channels is converted of-channels repeatedly. ADC10 27-9 ADC10 Operation Single-Channel Single-Conversion Mode A single channel selected by INCHx is sampled and converted once. The ADC result is written to ADC10MEM. Figure 27−5 shows the flow of the single-channel, single-conversion mode. When ADC10SC triggers a conversion, successive conversions can be triggered by the ADC10SC bit. When any other trigger source is used, ENC must be toggled between each conversion. Figure 27−5. Single-Channel Single-Conversion Mode CONSEQx = 00 ADC10 Off ADC10ON = 1 ENC = x = INCHx Wait for Enable ENC = SHS = 0 and ENC = ENC = 1 or and ADC10SC = Wait for Trigger ENC = 0 SAMPCON = (4/8/16/64) x ADC10CLK ENC = 0† Sample, Input Channel ENC = 0† x = input channel Ax † Conversion result is unpredictable Convert 12 x ADC10CLK 1 x ADC10CLK Conversion Completed, Result to ADC10MEM, ADC10IFG is Set 27-10 ADC10 ADC10 Operation Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence stops after conversion of channel A0. Figure 27−6 shows the sequence-of-channels mode. When ADC10SC triggers a sequence, successive sequences can be triggered by the ADC10SC bit . When any other trigger source is used, ENC must be toggled between each sequence. Figure 27−6. Sequence-of-Channels Mode CONSEQx = 01 ADC10 Off ADC10ON = 1 ENC = x = INCHx Wait for Enable ENC = SHS = 0 and ENC = ENC = 1 or and ADC10SC = Wait for Trigger If x > 0 then x = x −1 SAMPCON = x=0 (4/8/16/64) x ADC10CLK Sample, Input Channel Ax If x > 0 then x = x −1 MSC = 1 and x≠0 Convert 12 x ADC10CLK 1 x ADC10CLK Conversion Completed, Result to ADC10MEM, ADC10IFG is Set MSC = 0 and x ≠0 x = input channel Ax ADC10 27-11 ADC10 Operation Repeat-Single-Channel Mode A single channel selected by INCHx is sampled and converted continuously. Each ADC result is written to ADC10MEM. Figure 27−7 shows the repeat-single-channel mode. Figure 27−7. Repeat-Single-Channel Mode CONSEQx = 10 ADC10 Off ADC10ON = 1 ENC = x = INCHx Wait for Enable ENC = SHS = 0 and ENC = ENC = 1 or and ADC10SC = Wait for Trigger SAMPCON = Sample, Input Channel Ax (4/8/16/64) × ADC10CLK ENC = 0 MSC = 1 and ENC = 1 x = input channel Ax Convert 12 x ADC10CLK 1 x ADC10CLK Conversion Completed, Result to ADC10MEM, ADC10IFG is Set MSC = 0 and ENC = 1 27-12 ADC10 ADC10 Operation Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence ends after conversion of channel A0, and the next trigger signal re-starts the sequence. Figure 27−8 shows the repeat-sequence-of-channels mode. Figure 27−8. Repeat-Sequence-of-Channels Mode CONSEQx = 11 ADC10 Off ADC10ON = 1 ENC = x = INCHx Wait for Enable ENC = SHS = 0 and ENC = ENC = 1 or and ADC10SC = Wait for Trigger SAMPCON = Sample Input Channel Ax (4/8/16/64) x ADC10CLK If x = 0 then x = INCH else x = x −1 If x = 0 then x = INCH else x = x −1 12 x ADC10CLK MSC = 1 and (ENC = 1 or x ≠ 0) Convert 1 x ADC10CLK Conversion Completed, Result to ADC10MEM, ADC10IFG is Set MSC = 0 and (ENC = 1 or x ≠ 0) ENC = 0 and x=0 x = input channel Ax ADC10 27-13 ADC10 Operation Using the MSC Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1 and CONSEQx > 0 the first rising edge of the SHI signal triggers the first conversion. Successive conversions are triggered automatically as soon as the prior conversion is completed. Additional rising edges on SHI are ignored until the sequence is completed in the single-sequence mode or until the ENC bit is toggled in repeat-single-channel, or repeated-sequence modes. The function of the ENC bit is unchanged when using the MSC bit. Stopping Conversions Stopping ADC10 activity depends on the mode of operation. The recommended ways to stop an active conversion or conversion sequence are: - Resetting ENC in single-channel single-conversion mode stops a conversion immediately and the results are unpredictable. For correct results, poll the ADC10BUSY bit until reset before clearing ENC. - Resetting ENC during repeat-single-channel operation stops the converter at the end of the current conversion. - Resetting ENC during a sequence or repeat sequence mode stops the converter at the end of the sequence. - Any conversion mode may be stopped immediately by setting the CONSEQx=0 and resetting the ENC bit. Conversion data is unreliable. 27-14 ADC10 ADC10 Operation 27.2.7 ADC10 Data Transfer Controller The ADC10 includes a data transfer controller (DTC) to automatically transfer conversion results from ADC10MEM to other on-chip memory locations. The DTC is enabled by setting the ADC10DTC1 register to a nonzero value. When the DTC is enabled, each time the ADC10 completes a conversion and loads the result to ADC10MEM, a data transfer is triggered. No software intervention is required to manage the ADC10 until the predefined amount of conversion data has been transferred. Each DTC transfer requires one CPU MCLK. To avoid any bus contention during the DTC transfer, the CPU is halted, if active, for the one MCLK required for the transfer. A DTC transfer must not be initiated while the ADC10 is busy. Software must ensure that no active conversion or sequence is in progress when the DTC is configured: ; ADC10 activity test BIC.W #ENC,&ADC10CTL0 ; busy_test BIT.W #BUSY,&ADC10CTL1; JNZ busy_test ; MOV.W #xxx,&ADC10SA ; Safe MOV.B #xx,&ADC10DTC1 ; ; continue setup ADC10 27-15 ADC10 Operation One-Block Transfer Mode The one-block mode is selected if the ADC10TB is reset. The value n in ADC10DTC1 defines the total number of transfers for a block. The block start address is defined anywhere in the MSP430 address range using the 16-bit register ADC10SA. The block ends at ADC10SA+2n–2. The one-block transfer mode is shown in Figure 27−9. Figure 27−9. One-Block Transfer DTC TB=0 ’n’th transfer ADC10SA+2n−2 ADC10SA+2n−4 2nd transfer 1st transfer ADC10SA+2 ADC10SA The internal address pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to ‘n’. The internal pointer and counter are not visible to software. The DTC transfers the word-value of ADC10MEM to the address pointer ADC10SA. After each DTC transfer, the internal address pointer is incremented by two and the internal transfer counter is decremented by one. The DTC transfers continue with each loading of ADC10MEM, until the internal transfer counter becomes equal to zero. No additional DTC transfers will occur until a write to ADC10SA. When using the DTC in the one-block mode, the ADC10IFG flag is set only after a complete block has been transferred. Figure 27−10 shows a state diagram of the one-block mode. 27-16 ADC10 ADC10 Operation Figure 27−10. State Diagram for Data Transfer Control in One-Block Transfer Mode n=0 (ADC10DTC1) DTC reset n=0 n≠0 Wait for write to ADC10SA DTC init Initialize Start Address in ADC10SA Write to ADC10SA x=n AD = SA n is latched in counter ’x’ Write to ADC10SA or n=0 Wait until ADC10MEM is written DTC idle Write to ADC10SA Write to ADC10MEM completed Wait for CPU ready Synchronize with MCLK x>0 Write to ADC10SA 1 x MCLK cycle Transfer data to Address AD AD = AD + 2 x=x−1 x=0 ADC10IFG=1 ADC10TB = 0 and ADC10CT = 1 ADC10TB = 0 and ADC10CT = 0 Prepare DTC DTC operation ADC10 27-17 ADC10 Operation Two-Block Transfer Mode The two-block mode is selected if the ADC10TB bit is set. The value n in ADC10DTC1 defines the number of transfers for one block. The address range of the first block is defined anywhere in the MSP430 address range with the 16-bit register ADC10SA. The first block ends at ADC10SA+2n–2. The address range for the second block is defined as SA+2n to SA+4n–2. The two-block transfer mode is shown in Figure 27−11. Figure 27−11.Two-Block Transfer TB=1 2 x ’n’th transfer ADC10SA+4n−2 ADC10SA+4n−4 DTC ’n’th transfer ADC10SA+2n−2 ADC10SA+2n−4 2nd transfer 1st transfer ADC10SA+2 ADC10SA The internal address pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to ‘n’. The internal pointer and counter are not visible to software. The DTC transfers the word-value of ADC10MEM to the address pointer ADC10SA. After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one. The DTC transfers continue, with each loading of ADC10MEM, until the internal transfer counter becomes equal to zero. At this point, block one is full and both the ADC10IFG flag the ADC10B1 bit are set. The user can test the ADC10B1 bit to determine that block one is full. The DTC continues with block two. The internal transfer counter is automatically reloaded with ’n’. At the next load of the ADC10MEM, the DTC begins transferring conversion results to block two. After n transfers have completed, block two is full. The ADC10IFG flag is set and the ADC10B1 bit is cleared. User software can test the cleared ADC10B1 bit to determine that block two is full. Figure 27−12 shows a state diagram of the two-block mode. 27-18 ADC10 ADC10 Operation Figure 27−12. State Diagram for Data Transfer Control in Two-Block Transfer Mode n=0 (ADC10DTC1) DTC reset ADC10B1 = 0 ADC10TB = 1 n=0 n ≠0 Wait for write to ADC10SA DTC init Initialize Start Address in ADC10SA Write to ADC10SA x=n If ADC10B1 = 0 then AD = SA n is latched in counter ’x’ Write to ADC10SA or n=0 Wait until ADC10MEM is written DTC idle Write to ADC10SA Write to ADC10MEM completed Wait for Synchronize CPU ready with MCLK x>0 Write to ADC10SA 1 x MCLK cycle Transfer data to Address AD AD = AD + 2 x=x−1 x=0 ADC10IFG=1 Toggle ADC10B1 ADC10B1 = 1 or ADC10CT=1 ADC10CT = 0 and ADC10B1 = 0 Prepare DTC DTC operation ADC10 27-19 ADC10 Operation Continuous Transfer A continuous transfer is selected if ADC10CT bit is set. The DTC will not stop after block one in (one-block mode) or block two (two-block mode) has been transferred. The internal address pointer and transfer counter are set equal to ADC10SA and n respectively. Transfers continue starting in block one. If the ADC10CT bit is reset, DTC transfers cease after the current completion of transfers into block one (in the one-block mode) or block two (in the two-block mode) have been transfer. DTC Transfer Cycle Time For each ADC10MEM transfer, the DTC requires one or two MCLK clock cycles to synchronize, one for the actual transfer (while the CPU is halted), and one cycle of wait time. Because the DTC uses MCLK, the DTC cycle time is dependent on the MSP430 operating mode and clock system setup. If the MCLK source is active, but the CPU is off, the DTC uses the MCLK source for each transfer, without re-enabling the CPU. If the MCLK source is off, the DTC temporarily restarts MCLK, sourced with DCOCLK, only during a transfer. The CPU remains off and after the DTC transfer, MCLK is again turned off. The maximum DTC cycle time for all operating modes is show in Table 27−2. Table 27−2.Maximum DTC Cycle Time CPU Operating Mode Clock Source Maximum DTC Cycle Time Active mode MCLK=DCOCLK 3 MCLK cycles Active mode MCLK=LFXT1CLK 3 MCLK cycles Low-power mode LPM0/1 MCLK=DCOCLK 4 MCLK cycles Low-power mode LPM3/4 MCLK=DCOCLK 4 MCLK cycles + 2 μs† Low-power mode LPM0/1 MCLK=LFXT1CLK 4 MCLK cycles Low-power mode LPM3 MCLK=LFXT1CLK 4 MCLK cycles Low-power mode LPM4 MCLK=LFXT1CLK 4 MCLK cycles + 2 μs† † The additional 2 μs are needed to start the DCOCLK. See device-datasheet for parameters. 27-20 ADC10 ADC10 Operation 27.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc. The typical temperature sensor transfer function is shown in Figure 27−13. When using the temperature sensor, the sample period must be greater than 30 μs. The temperature sensor offset error is large. Deriving absolute temperature values in the application requires calibration. See the device-specific datasheet for the parameters. Selecting the temperature sensor automatically turns on the on-chip reference generator as a voltage source for the temperature sensor. However, it does not enable the VREF+ output or affect the reference selections for the conversion. The reference choices for converting the temperature sensor are the same as with any other channel. Figure 27−13. Typical Temperature Sensor Transfer Function Volts 1.300 1.200 1.100 1.000 0.900 0.800 VTEMP=0.00355(TEMPC)+0.986 0.700 −50 0 Celsius 50 100 ADC10 27-21 ADC10 Operation 27.2.9 ADC10 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small, unwanted offset voltages that can add to or subtract from the reference or input voltages of the A/D converter. The connections shown in Figure 27--14 help avoid this. In addition to grounding, ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result. A noise-free design is important to achieve high accuracy. Figure 27- 14. ADC10 Grounding and Noise Considerations (internal Vref). Digital Power Supply Decoupling 10uF Analog Power Supply Decoupling (if available) 10uF 100nF 100nF DVCC DVSS AVCC AVSS Figure 27- 15. ADC10 Grounding and Noise Considerations (external Vref). Digital Power Supply Decoupling Analog Power Supply Decoupling (if available) 10uF 10uF 100nF 100nF Using an External Positive Reference Using an External Negative Reference DVCC DVSS AVCC AVSS VREF+/VeREF+ VREF-/VeREF- 27-22 ADC10 ADC10 Operation 27.2.10 ADC10 Interrupts One interrupt and one interrupt vector are associated with the ADC10 as shown in Figure 27−16. When the DTC is not used (ADC10DTC1 = 0) ADC10IFG is set when conversion results are loaded into ADC10MEM. When DTC is used (ADC10DTC1 > 0) ADC10IFG is set when a block transfer completes and the internal transfer counter ’n’ = 0. If both the ADC10IE and the GIE bits are set, then the ADC10IFG flag generates an interrupt request. The ADC10IFG flag is automatically reset when the interrupt request is serviced or may be reset by software. Figure 27−16. ADC10 Interrupt System ADC10IE Set ADC10IFG ’n’ = 0 ADC10CLK D Q Reset POR IRQ, Interrupt Service Requested IRACC, Interrupt Request Accepted ADC10 27-23 ADC10 Registers 27.3 ADC10 Registers The ADC10 registers are listed in Table 27−3. Table 27−3.ADC10 Registers Register Short Form ADC10 Input enable register 0 ADC10AE0 ADC10 Input enable register 1 ADC10AE1 ADC10 control register 0 ADC10CTL0 ADC10 control register 1 ADC10CTL1 ADC10 memory ADC10MEM ADC10 data transfer control register 0 ADC10DTC0 ADC10 data transfer control register 1 ADC10DTC1 ADC10 data transfer start address ADC10SA Register Type Address Read/write 04Ah Read/write 04Bh Read/write 01B0h Read/write 01B2h Read 01B4h Read/write 048h Read/write 049h Read/write 01BCh Initial State Reset with POR Reset with POR Reset with POR Reset with POR Unchanged Reset with POR Reset with POR 0200h with POR 27-24 ADC10 ADC10CTL0, ADC10 Control Register 0 ADC10 Registers 15 rw−(0) 14 SREFx rw−(0) 13 rw−(0) 12 11 ADC10SHTx rw−(0) rw−(0) 10 ADC10SR rw−(0) 9 8 REFOUT REFBURST rw−(0) rw−(0) 7 MSC rw−(0) 6 REF2_5V rw−(0) 5 REFON rw−(0) 4 3 2 ADC10ON ADC10IE ADC10IFG rw−(0) rw−(0) rw−(0) 1 ENC rw−(0) 0 ADC10SC rw−(0) Modifiable only when ENC = 0 SREFx Bits 15-13 ADC10 SHTx Bits 12-11 ADC10SR Bit 10 REFOUT Bit 9 REFBURST Bit 8 Select reference 000 VR+ = VCC and VR− = VSS 001 VR+ = VREF+ and VR− = VSS 010 VR+ = VeREF+ and VR− = VSS 011 VR+ = Buffered VeREF+ and VR− = VSS 100 VR+ = VCC and VR− = VREF−/ VeREF− 101 VR+ = VREF+ and VR− = VREF−/ VeREF− 110 VR+ = VeREF+ and VR− = VREF−/ VeREF− 111 VR+ = Buffered VeREF+ and VR− = VREF−/ VeREF− ADC10 sample-and-hold time 00 4 x ADC10CLKs 01 8 x ADC10CLKs 10 16 x ADC10CLKs 11 64 x ADC10CLKs ADC10 sampling rate. This bit selects the reference buffer drive capability for the maximum sampling rate. Setting ADC10SR reduces the current consumption of the reference buffer. 0 Reference buffer supports up to ~200 ksps 1 Reference buffer supports up to ~50 ksps Reference output 0 Reference output off 1 Reference output on Reference burst. 0 Reference buffer on continuously 1 Reference buffer on only during sample-and-conversion ADC10 27-25 ADC10 Registers MSC Bit 7 REF2_5V Bit 6 REFON Bit 5 ADC10ON Bit 4 ADC10IE Bit 3 ADC10IFG Bit 2 ENC Bit 1 ADC10SC Bit 0 Multiple sample and conversion. Valid only for sequence or repeated modes. 0 The sampling requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed Reference-generator voltage. REFON must also be set. 0 1.5 V 1 2.5 V Reference generator on 0 Reference off 1 Reference on ADC10 on 0 ADC10 off 1 ADC10 on ADC10 interrupt enable 0 Interrupt disabled 1 interrupt enabled ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion result. It is automatically reset when the interrupt request is accepted, or it may be reset by software. When using the DTC this flag is set when a block of transfers is completed. 0 No interrupt pending 1 Interrupt pending Enable conversion 0 ADC10 disabled 1 ADC10 enabled Start conversion. Software-controlled sample-and-conversion start. ADC10SC and ENC may be set together with one instruction. ADC10SC is reset automatically. 0 No sample-and-conversion start 1 Start sample-and-conversion 27-26 ADC10 ADC10CTL1, ADC10 Control Register 1 15 rw−(0) 14 13 INCHx rw−(0) rw−(0) 12 rw−(0) ADC10 Registers 11 10 SHSx rw−(0) rw−(0) 9 ADC10DF rw−(0) 8 ISSH rw−(0) 7 rw−(0) 6 ADC10DIVx rw−(0) 5 rw−(0) 4 3 ADC10SSELx rw−(0) rw−(0) 2 1 CONSEQx rw−(0) rw−(0) 0 ADC10 BUSY r−0 Modifiable only when ENC = 0 INCHx SHSx ADC10DF ISSH Bits 15-12 Bits 11-10 Bit 9 Bit 8 Input channel select. These bits select the channel for a single-conversion or the highest channel for a sequence of conversions. 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 1001 1010 VeREF+ VREF− /VeREF− Temperature sensor 1011 1100 1101 1110 1111 (VCC – VSS) / 2 (VCC – VSS) / 2, A12 on MSP430x22xx devices (VCC – VSS) / 2, A13 on MSP430x22xx devices (VCC – VSS) / 2, A14 on MSP430x22xx devices (VCC – VSS) / 2, A15 on MSP430x22xx devices Sample-and-hold source select. For The MSP430F41x2 devices: 00 ADC10SC bit 01 Timer_A0.OUT1 10 Timer_A1.OUT0 11 Timer_A1.OUT1 ADC10 data format 0 Straight binary 1 2’s complement Invert signal sample-and-hold 0 The sample-input signal is not inverted. 1 The sample-input signal is inverted. ADC10 27-27 ADC10 Registers ADC10DIVx Bits 7-5 ADC10 Bits SSELx 4-3 CONSEQx Bits 2-1 ADC10 BUSY Bit 0 ADC10 clock divider 000 /1 001 /2 010 /3 011 /4 100 /5 101 /6 110 /7 111 /8 ADC10 clock source select 00 ADC10OSC 01 ACLK 10 MCLK 11 SMCLK Conversion sequence mode select 00 Single-channel-single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels ADC10 busy. This bit indicates an active sample or conversion operation 0 No operation is active. 1 A sequence, sample, or conversion is active. 27-28 ADC10 ADC10AE0, Analog (Input) Enable Control Register 0 7 rw−(0) 6 rw−(0) 5 rw−(0) 4 3 ADC10AE0x rw−(0) rw−(0) 2 rw−(0) ADC10 Registers 1 0 rw−(0) rw−(0) ADC10AE0x Bits 7-0 ADC10 analog enable. These bits enable the corresponding pin for analog input. BIT0 corresponds to A0, BIT1 corresponds to A1, etc. 0 Analog input disabled 1 Analog input enabled ADC10AE1, Analog (Input) Enable Control Register 1 7 rw−(0) 6 5 ADC10AE1x rw−(0) rw−(0) 4 rw−(0) 3 Reserved rw−(0) 2 Reserved rw−(0) 1 Reserved rw−(0) 0 Reserved rw−(0) ADC10AE1x Bits 7-4 ADC10 analog enable. These bits enable the corresponding pin for analog input. BIT4 corresponds to A12, BIT5 corresponds to A13, BIT6 corresponds to A14, and BIT7 corresponds to A15. 0 Analog input disabled 1 Analog input enabled ADC10 27-29 ADC10 Registers ADC10MEM, Conversion-Memory Register, Binary Format 15 14 13 12 11 10 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 Conversion Results r r r r r r 9 8 Conversion Results r r 1 0 r r Conversion Bits Results 15-0 The 10-bit conversion results are right justified, straight-binary format. Bit 9 is the MSB. Bits 15-10 are always 0. ADC10MEM, Conversion-Memory Register, 2’s Complement Format 15 14 13 12 11 10 9 8 Conversion Results r r r r r r r r 7 6 5 4 3 2 1 0 Conversion Results 0 0 0 0 0 0 r r r0 r0 r0 r0 r0 r0 Conversion Bits Results 15-0 The 10-bit conversion results are left-justified, 2’s complement format. Bit 15 is the MSB. Bits 5-0 are always 0. 27-30 ADC10 ADC10DTC0, Data Transfer Control Register 0 ADC10 Registers 7 6 5 4 3 2 1 0 Reserved ADC10TB ADC10CT ADC10B1 ADC10 FETCH r0 r0 r0 r0 rw−(0) rw−(0) r−(0) rw−(0) Reserved ADC10TB Bits 7-4 Bit 3 ADC10CT Bit 2 ADC10B1 Bit 1 ADC10 FETCH Bit 0 Reserved. Always read as 0. ADC10 two-block mode. 0 One-block transfer mode 1 Two-block transfer mode ADC10 continuous transfer. 0 Data transfer stops when one block (one-block mode) or two blocks (two-block mode) have completed. 1 Data is transferred continuously. DTC operation is stopped only if ADC10CT cleared, or ADC10SA is written to. ADC10 block one. This bit indicates for two-block mode which block is filled with ADC10 conversion results. ADC10B1 is valid only after ADC10IFG has been set the first time during DTC operation. ADC10TB must also be set. 0 Block 2 is filled 1 Block 1 is filled This bit should normally be reset. ADC10 27-31 ADC10 Registers ADC10DTC1, Data Transfer Control Register 1 7 rw−(0) 6 rw−(0) 5 rw−(0) 4 3 DTC Transfers rw−(0) rw−(0) 2 rw−(0) 1 rw−(0) 0 rw−(0) DTC Bits Transfers 7-0 DTC transfers. These bits define the number of transfers in each block. 0 DTC is disabled 01h-0FFh Number of transfers per block ADC10SA, Start Address Register for Data Transfer 15 rw−(0) 14 rw−(0) 13 rw−(0) 12 11 ADC10SAx rw−(0) rw−(0) 10 rw−(0) 7 rw−(0) 6 rw−(0) 5 rw−(0) 4 ADC10SAx rw−(0) 3 rw−(0) 2 rw−(0) 9 rw−(1) 1 rw−(0) 8 rw−(0) 0 0 r0 ADC10SAx Bits 15-1 Unused Bit 0 ADC10 start address. These bits are the start address for the DTC. A write to register ADC10SA is required to initiate DTC transfers. Unused, Read only. Always read as 0. 27-32 ADC10 Chapter 28 ADC12 The ADC12 module is a high-performance 12-bit analog-to-digital converter (ADC). This chapter describes the ADC12. The ADC12 is implemented in the MSP430x43x MSP430x44x, and MSP430FG461x devices. Topic Page 28.1 ADC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.2 ADC12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.3 ADC12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20 ADC12 28-1 ADC12 Introduction 28.1 ADC12 Introduction The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. ADC12 features include: - Greater than 200-ksps maximum conversion rate - Monotonic 12-bit converter with no missing codes - Sample-and-hold with programmable sampling periods controlled by software or timers. - Conversion initiation by software, Timer_A, or Timer_B - Software selectable on-chip reference voltage generation (1.5 V or 2.5 V) - Software selectable internal or external reference - Eight individually configurable external input channels (twelve on MSP430FG43x and MSP430FG461x devices) - Conversion channels for internal temperature sensor, AVCC, and external references - Independent channel-selectable reference sources for both positive and negative references - Selectable conversion clock source - Single-channel, repeat-single-channel, sequence, and repeat-sequence conversion modes - ADC core and reference voltage can be powered down separately - Interrupt vector register for fast decoding of 18 ADC interrupts - 16 conversion-result storage registers The block diagram of ADC12 is shown in Figure 28−1. 28-2 ADC12 Figure 28−1. ADC12 Block Diagram ADC12 Introduction A0 A1 A2 A3 A4 A5 A6 A7 A12† A13† A14† A15† VeREF+ VREF+ VREF− / VeREF− REF2_5V on 1.5 V or 2.5 V Reference REFON INCHx=0Ah AVCC INCHx 4 AVCC 11 10 01 00 AVSS Ref_x SREF1 SREF0 ADC12OSC 0000 SREF2 10 ADC12ON ADC12SSELx 0001 0010 ADC12DIVx 0011 0100 0101 0110 0111 1000 1001 Sample and Hold S/H VR− VR+ 12−bit SAR Convert 00 Divider 01 /1 .. /8 10 11 ADC12CLK ACLK MCLK SMCLK 1010 1011 1100 1101 1110 1111 AVCC SHP 1 SAMPCON 0 BUSY SHT0x ISSH 4 Sample Timer SHI 0 /4 .. /1024 1 4 ENC Sync SHSx 00 01 10 11 SHT1x MSC INCHx=0Bh ADC12SC TA1 TB0 TB1 Ref_x R CSTARTADDx R AVSS CONSEQx ADC12MEM0 − 16 x 12 Memory Buffer − ADC12MEM15 ADC12MCTL0 − 16 x 8 Memory Control − ADC12MCTL15 † MSP430FG43x and MSP430FG461x devices only ADC12 28-3 ADC12 Operation 28.2 ADC12 Operation The ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed in the following sections. 28.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation and stores the result in conversion memory. The core uses two programmable/selectable voltage levels (VR+ and VR−) to define the upper and lower limits of the conversion. The digital output (NADC) is full scale (0FFFh) when the input signal is equal to or higher than VR+, and zero when the input signal is equal to or lower than VR−. The input channel and the reference voltage levels (VR+ and VR−) are defined in the conversion-control memory. The conversion formula for the ADC result NADC is: NADC + 4095 Vin * VR* VR) * VR* The ADC12 core is configured by two control registers, ADC12CTL0 and ADC12CTL1. The core is enabled with the ADC12ON bit. The ADC12 can be turned off when not in use to save power. With few exceptions the ADC12 control bits can only be modified when ENC = 0. ENC must be set to 1 before any conversion can take place. Conversion Clock Selection The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse sampling mode is selected. The ADC12 source clock is selected using the ADC12SSELx bits and can be divided by 1 to 8 using the ADC12DIVx bits. Possible ADC12CLK sources are SMCLK, MCLK, ACLK, and an internal oscillator, ADC12OSC. The ADC12OSC, generated internally, is in the 5-MHz range but varies with individual devices, supply voltage, and temperature. See the device-specific data sheet for the ADC12OSC specification. The user must ensure that the clock chosen for ADC12CLK remains active until the end of a conversion. If the clock is removed during a conversion, the operation will not complete and any result will be invalid. 28-4 ADC12 ADC12 Operation 28.2.2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 28−2. The input multiplexer is also a T-switch to minimize the coupling between channels. Channels that are not selected are isolated from the A/D and the intermediate node is connected to analog ground (AVSS) so that the stray capacitance is grounded to help eliminate crosstalk. The ADC12 uses the charge redistribution method. When the inputs are internally switched, the switching action may cause transients on the input signal. These transients decay and settle before causing errant conversion. Figure 28−2. Analog Multiplexer R ~ 100 Ohm ADC12MCTLx.0−3 Input Ax ESD Protection Analog Port Selection The ADC12 inputs are multiplexed with the port P6 pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption. The P6SELx bits provide the ability to disable the port pin input and output buffers. ; P6.0 and P6.1 configured for analog input BIS.B #3h,&P6SEL ; P6.1 and P6.0 ADC12 function ADC12 28-5 ADC12 Operation 28.2.3 Voltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectable voltage levels, 1.5 V and 2.5 V. Either of these reference voltages may be used internally and externally on pin VREF+. Setting REFON=1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V, the reference is 1.5 V when REF2_5V = 0. The reference can be turned off to save power when not in use. For proper operation the internal voltage reference generator must be supplied with storage capacitance across VREF+ and AVSS. The recommended storage capacitance is a parallel combination of 10-μF and 0.1-μF capacitors. From turn-on, a maximum of 17 ms must be allowed for the voltage reference generator to bias the recommended storage capacitors. If the internal reference generator is not used for the conversion, the storage capacitors are not required. Note: Reference Decoupling Approximately 200 μA is required from any reference used by the ADC12 while the two LSBs are being resolved during a conversion. A parallel combination of 10-μF and 0.1-μF capacitors is recommended for any reference used as shown in Figure 28−11. External references may be supplied for VR+ and VR− through pins VeREF+ and VREF−/VeREF− respectively. 28.2.4 Auto Power-Down The ADC12 is designed for low power applications. When the ADC12 is not actively converting, the core is automatically disabled and automatically re-enabled when needed. The ADC12OSC is also automatically enabled when needed and disabled when not needed. The reference is not automatically disabled, but can be disabled by setting REFON = 0. When the core, oscillator, or reference are disabled, they consume no current. 28-6 ADC12 ADC12 Operation 28.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following: - The ADC12SC bit - The Timer_A Output Unit 1 - The Timer_B Output Unit 0 - The Timer_B Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit. The SAMPCON signal controls the sample period and start of conversion. When SAMPCON is high, sampling is active. The high-to-low SAMPCON transition starts the analog-to-digital conversion, which requires 13 ADC12CLK cycles. Two different sample-timing methods are defined by control bit SHP, extended sample mode and pulse mode. Extended Sample Mode The extended sample mode is selected when SHP = 0. The SHI signal directly controls SAMPCON and defines the length of the sample period tsample. When SAMPCON is high, sampling is active. The high-to-low SAMPCON transition starts the conversion after synchronization with ADC12CLK. See Figure 28−3. Figure 28−3. Extended Sample Mode Start Sampling Stop Sampling Start Conversion Conversion Complete SHI SAMPCON ADC12CLK tsample t sync 13 x ADC12CLK tconvert ADC12 28-7 ADC12 Operation Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used to trigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period tsample. The sampling timer keeps SAMPCON high after synchronization with AD12CLK for a programmed interval tsample. The total sampling time is tsample plus tsync. See Figure 28−4. The SHTx bits select the sampling time in 4x multiples of ADC12CLK. SHT0x selects the sampling time for ADC12MCTL0 to 7 and SHT1x selects the sampling time for ADC12MCTL8 to 15. Figure 28−4. Pulse Sample Mode Start Sampling Stop Start Sampling Conversion Conversion Complete SHI SAMPCON ADC12CLK tsync tsample 13 x ADC12CLK tconvert 28-8 ADC12 ADC12 Operation Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time tsample, as shown below in Figure 28−5. An internal MUX-on input resistance RI (maximum 2 kΩ) in series with capacitor CI (maximum 40 pF) is seen by the source. The capacitor CI voltage VC must be charged to within 1/2 LSB of the source voltage VS for an accurate 12-bit conversion. Figure 28−5. Analog Input Equivalent Circuit MSP430 VS RS VI RI VC CI VI = Input voltage at pin Ax VS = External source voltage RS = External source resistance RI = Internal MUX-on input resistance CI = Input capacitance VC = Capacitance-charging voltage The resistance of the source RS and RI affect tsample. The following equation can be used to calculate the minimum sampling time tsample for a 12-bit conversion: tsample u (RS ) RI) ln(213) CI ) 800ns Substituting the values for RI and CI given above, the equation becomes: tsample u (RS ) 2kW) 9.011 40pF ) 800ns For example, if RS is 10 kΩ, tsample must be greater than 5.13 μs. ADC12 28-9 ADC12 Operation 28.2.6 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversion results. Each ADC12MEMx is configured with an associated ADC12MCTLx control register. The SREFx bits define the voltage reference and the INCHx bits select the input channel. The EOS bit defines the end of sequence when a sequential conversion mode is used. A sequence rolls over from ADC12MEM15 to ADC12MEM0 when the EOS bit in ADC12MCTL15 is not set. The CSTARTADDx bits define the first ADC12MCTLx used for any conversion. If the conversion mode is single-channel or repeat-single-channel the CSTARTADDx points to the single ADC12MCTLx to be used. If the conversion mode selected is either sequence-of-channels or repeat-sequence-of-channels, CSTARTADDx points to the first ADC12MCTLx location to be used in a sequence. A pointer, not visible to software, is incremented automatically to the next ADC12MCTLx in a sequence when each conversion completes. The sequence continues until an EOS bit in ADC12MCTLx is processed - this is the last control byte processed. When conversion results are written to a selected ADC12MEMx, the corresponding flag in the ADC12IFGx register is set. 28.2.7 ADC12 Conversion Modes The ADC12 has four operating modes selected by the CONSEQx bits as discussed in Table 28−1. Table 28−1.Conversion Mode Summary CONSEQx Mode Operation 00 Single channel A single channel is converted once. single-conversion 01 Sequence-of- channels A sequence of channels is converted once. 10 Repeat-single- A single channel is converted repeatedly. channel 11 Repeat-sequence- A sequence of channels is converted of-channels repeatedly. 28-10 ADC12 ADC12 Operation Single-Channel Single-Conversion Mode A single channel is sampled and converted once. The ADC result is written to the ADC12MEMx defined by the CSTARTADDx bits. Figure 28−6 shows the flow of the Single-Channel, Single-Conversion mode. When ADC12SC triggers a conversion, successive conversions can be triggered by the ADC12SC bit. When any other trigger source is used, ENC must be toggled between each conversion. Figure 28−6. Single-Channel, Single-Conversion Mode CONSEQx = 00 ADC12 off ADC12ON = 1 ENC = x = CSTARTADDx Wait for Enable ENC = SHSx = 0 and ENC = ENC = 1 or and ADC12SC = Wait for Trigger ENC = 0 ENC = 0† SAMPCON = Sample, Input Channel Defined in ADC12MCTLx SAMPCON = 1 SAMPCON = 12 x ADC12CLK ENC = 0† Convert 1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx †Conversion result is unpredictable ADC12 28-11 ADC12 Operation Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The ADC results are written to the conversion memories starting with the ADCMEMx defined by the CSTARTADDx bits. The sequence stops after the measurement of the channel with a set EOS bit. Figure 28−7 shows the sequence-of-channels mode. When ADC12SC triggers a sequence, successive sequences can be triggered by the ADC12SC bit. When any other trigger source is used, ENC must be toggled between each sequence. Figure 28−7. Sequence-of-Channels Mode CONSEQx = 01 ADC12 off ADC12ON = 1 ENC = x = CSTARTADDx Wait for Enable ENC = SHSx = 0 and ENC = ENC = 1 or and ADC12SC = Wait for Trigger SAMPCON = EOS.x = 1 If x < 15 then x = x + 1 else x = 0 Sample, Input Channel Defined in ADC12MCTLx SAMPCON = 1 If x < 15 then x = x + 1 else x = 0 SAMPCON = MSC = 1 and SHP = 1 and EOS.x = 0 Convert 12 x ADC12CLK 1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set (MSC = 0 or SHP = 0) and EOS.x = 0 x = pointer to ADC12MCTLx 28-12 ADC12 ADC12 Operation Repeat-Single-Channel Mode A single channel is sampled and converted continuously. The ADC results are written to the ADC12MEMx defined by the CSTARTADDx bits. It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion. Figure 28−8 shows repeat-single-channel mode Figure 28−8. Repeat-Single-Channel Mode CONSEQx = 10 ADC12 off ADC12ON = 1 ENC = x = CSTARTADDx Wait for Enable ENC = SHSx = 0 and ENC = ENC = 1 or and ADC12SC = Wait for Trigger SAMPCON = Sample, Input Channel Defined in ADC12MCTLx SAMPCON = 1 MSC = 1 and SHP = 1 and ENC = 1 SAMPCON = Convert 12 x ADC12CLK 1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set (MSC = 0 or SHP = 0) and ENC = 1 x = pointer to ADC12MCTLx ENC = 0 ADC12 28-13 ADC12 Operation Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDx bits. The sequence ends after the measurement of the channel with a set EOS bit and the next trigger signal re-starts the sequence. Figure 28−9 shows the repeat-sequence-of-channels mode. Figure 28−9. Repeat-Sequence-of-Channels Mode CONSEQx = 11 ADC12 off ADC12ON = 1 ENC = x = CSTARTADDx Wait for Enable ENC = SHSx = 0 and ENC = ENC = 1 or and ADC12SC = Wait for Trigger SAMPCON = ENC = 0 and SAMPCON = 1 EOS.x = 1 Sample, Input Channel Defined in ADC12MCTLx If EOS.x = 1 then x = CSTARTADDx SAMPCON = else {if x < 15 then x = x + 1 else x = 0} If EOS.x = 1 then x = CSTARTADDx else {if x < 15 then x = x + 1 else x = 0} Convert 12 x ADC12CLK MSC = 1 and SHP = 1 and (ENC = 1 or EOS.x = 0) 1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set (MSC = 0 or SHP = 0) and (ENC = 1 or EOS.x = 0) x = pointer to ADC12MCTLx 28-14 ADC12 ADC12 Operation Using the Multiple Sample and Convert (MSC) Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1, CONSEQx > 0, and the sample timer is used, the first rising edge of the SHI signal triggers the first conversion. Successive conversions are triggered automatically as soon as the prior conversion is completed. Additional rising edges on SHI are ignored until the sequence is completed in the single-sequence mode or until the ENC bit is toggled in repeat-single-channel, or repeated-sequence modes. The function of the ENC bit is unchanged when using the MSC bit. Stopping Conversions Stopping ADC12 activity depends on the mode of operation. The recommended ways to stop an active conversion or conversion sequence are: - Resetting ENC in single-channel single-conversion mode stops a conversion immediately and the results are unpredictable. For correct results, poll the busy bit until reset before clearing ENC. - Resetting ENC during repeat-single-channel operation stops the converter at the end of the current conversion. - Resetting ENC during a sequence or repeat-sequence mode stops the converter at the end of the sequence. - Any conversion mode may be stopped immediately by setting the CONSEQx = 0 and resetting ENC bit. Conversion data are unreliable. Note: No EOS Bit Set For Sequence If no EOS bit is set and a sequence mode is selected, resetting the ENC bit does not stop the sequence. To stop the sequence, first select a single-channel mode and then reset ENC. ADC12 28-15 ADC12 Operation 28.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc. The typical temperature sensor transfer function is shown in Figure 28−10. When using the temperature sensor, the sample period must be greater than 30 μs. The temperature sensor offset error can be large, and may need to be calibrated for most applications. See device-specific data sheet for parameters. Selecting the temperature sensor automatically turns on the on-chip reference generator as a voltage source for the temperature sensor. However, it does not enable the VREF+ output or affect the reference selections for the conversion. The reference choices for converting the temperature sensor are the same as with any other channel. Figure 28−10. Typical Temperature Sensor Transfer Function Volts 1.300 1.200 1.100 1.000 0.900 0.800 VTEMP=0.00355(TEMPC)+0.986 0.700 −50 0 Celsius 50 100 28-16 ADC12 ADC12 Operation 28.2.9 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small, unwanted offset voltages that can add to or subtract from the reference or input voltages of the A/D converter. The connections shown in Figure 28−11 help avoid this. In addition to grounding, ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result. A noise-free design using separate analog and digital ground planes with a single-point connection is recommend to achieve high accuracy. Figure 28−11.ADC12 Grounding and Noise Considerations Digital Power Supply + Decoupling 10 uF 100 nF Analog Power Supply Decoupling + 10 uF 100 nF Using an External + Positive Reference 10 uF 100 nF Using the Internal + Reference Generator 10 uF 100 nF Using an External + Negative Reference 10 uF 100 nF DVCC DVSS AV CC AV SS VeREF+ VREF+ VREF− / VeREF− ADC12 28-17 ADC12 Operation 28.2.10 ADC12 Interrupts The ADC12 has 18 interrupt sources: - ADC12IFG0-ADC12IFG15 - ADC12OV, ADC12MEMx overflow - ADC12TOV, ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result. An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set. The ADC12OV condition occurs when a conversion result is written to any ADC12MEMx before its previous conversion result was read. The ADC12TOV condition is generated when another sample-and-conversion is requested before the current conversion is completed. The DMA is triggered after the conversion in single channel modes or after the completion of a sequence−of−channel modes. ADC12IV, Interrupt Vector Generator All ADC12 interrupt sources are prioritized and combined to source a single interrupt vector. The interrupt vector register ADC12IV is used to determine which enabled ADC12 interrupt source requested an interrupt. The highest priority enabled ADC12 interrupt generates a number in the ADC12IV register (see register description). This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled ADC12 interrupts do not affect the ADC12IV value. Any access, read or write, of the ADC12IV register automatically resets the ADC12OV condition or the ADC12TOV condition if either was the highest pending interrupt. Neither interrupt condition has an accessible interrupt flag. The ADC12IFGx flags are not reset by an ADC12IV access. ADC12IFGx bits are reset automatically by accessing their associated ADC12MEMx register or may be reset with software. If another interrupt is pending after servicing of an interrupt, another interrupt is generated. For example, if the ADC12OV and ADC12IFG3 interrupts are pending when the interrupt service routine accesses the ADC12IV register, the ADC12OV interrupt condition is reset automatically. After the RETI instruction of the interrupt service routine is executed, the ADC12IFG3 generates another interrupt. 28-18 ADC12 ADC12 Operation ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead. The ADC12IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. The latencies are: - ADC12IFG0 - ADC12IFG14, ADC12TOV and ADC12OV 16 cycles - ADC12IFG15 14 cycles The interrupt handler for ADC12IFG15 shows a way to check immediately if a higher prioritized interrupt occurred during the processing of ADC12IFG15. This saves nine cycles if another ADC12 interrupt is pending. ; Interrupt handler for ADC12. INT_ADC12 ; Enter Interrupt Service Routine 6 ADD &ADC12IV,PC; Add offset to PC 3 RETI ; Vector 0: No interrupt 5 JMP ADOV ; Vector 2: ADC overflow 2 JMP ADTOV ; Vector 4: ADC timing overflow 2 JMP ADM0 ; Vector 6: ADC12IFG0 2 ... ; Vectors 8-32 2 JMP ADM14 ; Vector 34: ADC12IFG14 2 ; ; Handler for ADC12IFG15 starts here. No JMP required. ; ADM15 MOV &ADC12MEM15,xxx ; Move result, flag is reset ... ; Other instruction needed? JMP INT_ADC12 ; Check other int pending ; ; ADC12IFG14-ADC12IFG1 handlers go here ; ADM0 MOV &ADC12MEM0,xxx ; Move result, flag is reset ... ; Other instruction needed? RETI ; Return 5 ; ADTOV ... ; Handle Conv. time overflow RETI ; Return 5 ; ADOV ... ; Handle ADCMEMx overflow RETI ; Return 5 ADC12 28-19 ADC12 Registers 28.3 ADC12 Registers The ADC12 registers are listed in Table 28−2 . Table 28−2.ADC12 Registers Register ADC12 control register 0 ADC12 control register 1 ADC12 interrupt flag register ADC12 interrupt enable register ADC12 interrupt vector word ADC12 memory 0 ADC12 memory 1 ADC12 memory 2 ADC12 memory 3 ADC12 memory 4 ADC12 memory 5 ADC12 memory 6 ADC12 memory 7 ADC12 memory 8 ADC12 memory 9 ADC12 memory 10 ADC12 memory 11 ADC12 memory 12 ADC12 memory 13 ADC12 memory 14 ADC12 memory 15 ADC12 memory control 0 ADC12 memory control 1 ADC12 memory control 2 ADC12 memory control 3 ADC12 memory control 4 ADC12 memory control 5 ADC12 memory control 6 ADC12 memory control 7 ADC12 memory control 8 ADC12 memory control 9 ADC12 memory control 10 ADC12 memory control 11 ADC12 memory control 12 ADC12 memory control 13 ADC12 memory control 14 ADC12 memory control 15 Short Form ADC12CTL0 ADC12CTL1 ADC12IFG ADC12IE ADC12IV ADC12MEM0 ADC12MEM1 ADC12MEM2 ADC12MEM3 ADC12MEM4 ADC12MEM5 ADC12MEM6 ADC12MEM7 ADC12MEM8 ADC12MEM9 ADC12MEM10 ADC12MEM11 ADC12MEM12 ADC12MEM13 ADC12MEM14 ADC12MEM15 ADC12MCTL0 ADC12MCTL1 ADC12MCTL2 ADC12MCTL3 ADC12MCTL4 ADC12MCTL5 ADC12MCTL6 ADC12MCTL7 ADC12MCTL8 ADC12MCTL9 ADC12MCTL10 ADC12MCTL11 ADC12MCTL12 ADC12MCTL13 ADC12MCTL14 ADC12MCTL15 Register Type Address Read/write 01A0h Read/write 01A2h Read/write 01A4h Read/write 01A6h Read 01A8h Read/write 0140h Read/write 0142h Read/write 0144h Read/write 0146h Read/write 0148h Read/write 014Ah Read/write 014Ch Read/write 014Eh Read/write 0150h Read/write 0152h Read/write 0154h Read/write 0156h Read/write 0158h Read/write 015Ah Read/write 015Ch Read/write 015Eh Read/write 080h Read/write 081h Read/write 082h Read/write 083h Read/write 084h Read/write 085h Read/write 086h Read/write 087h Read/write 088h Read/write 089h Read/write 08Ah Read/write 08Bh Read/write 08Ch Read/write 08Dh Read/write 08Eh Read/write 08Fh Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR 28-20 ADC12 ADC12CTL0, ADC12 Control Register 0 15 rw−(0) 14 13 SHT1x rw−(0) rw−(0) 12 rw−(0) 11 rw−(0) ADC12 Registers 10 9 SHT0x rw−(0) rw−(0) 8 rw−(0) 7 MSC rw−(0) 6 REF2_5V rw−(0) 5 REFON rw−(0) 4 3 ADC12ON ADC12OVIE rw−(0) rw−(0) 2 ADC12 TOVIE rw−(0) 1 ENC rw−(0) 0 ADC12SC rw−(0) Modifiable only when ENC = 0 SHT1x SHT0x Bits 15-12 Bits 11-8 Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15. Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM0 to ADC12MEM7. SHTx Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC12CLK cycles 4 8 16 32 64 96 128 192 256 384 512 768 1024 1024 1024 1024 ADC12 28-21 ADC12 Registers MSC Bit 7 REF2_5V Bit 6 REFON Bit 5 ADC12ON Bit 4 ADC12OVIE Bit 3 ADC12 TOVIE Bit 2 ENC Bit 1 ADC12SC Bit 0 Multiple sample and conversion. Valid only for sequence or repeated modes. 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed. Reference generator voltage. REFON must also be set. 0 1.5 V 1 2.5 V Reference generator on 0 Reference off 1 Reference on ADC12 on 0 ADC12 off 1 ADC12 on ADC12MEMx overflow-interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 conversion-time-overflow interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Conversion time overflow interrupt disabled 1 Conversion time overflow interrupt enabled Enable conversion 0 ADC12 disabled 1 ADC12 enabled Start conversion. Software-controlled sample-and-conversion start. ADC12SC and ENC may be set together with one instruction. ADC12SC is reset automatically. 0 No sample-and-conversion-start 1 Start sample-and-conversion 28-22 ADC12 ADC12CTL1, ADC12 Control Register 1 15 rw−(0) 14 13 CSTARTADDx rw−(0) rw−(0) 12 rw−(0) 11 10 SHSx rw−(0) rw−(0) ADC12 Registers 9 SHP rw−(0) 8 ISSH rw−(0) 7 rw−(0) 6 ADC12DIVx rw−(0) 5 rw−(0) 4 3 ADC12SSELx rw−(0) rw−(0) 2 1 CONSEQx rw−(0) rw−(0) 0 ADC12 BUSY r−(0) Modifiable only when ENC = 0 CSTART ADDx Bits 15-12 SHSx Bits 11-10 SHP Bit 9 ISSH Bit 8 ADC12DIVx Bits 7-5 Conversion start address. These bits select which ADC12 conversion-memory register is used for a single conversion or for the first conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15. Sample-and-hold source select 00 ADC12SC bit 01 Timer_A.OUT1 10 Timer_B.OUT0 11 Timer_B.OUT1 Sample-and-hold pulse-mode select. This bit selects the source of the sampling signal (SAMPCON) to be either the output of the sampling timer or the sample-input signal directly. 0 SAMPCON signal is sourced from the sample-input signal. 1 SAMPCON signal is sourced from the sampling timer. Invert signal sample-and-hold 0 The sample-input signal is not inverted. 1 The sample-input signal is inverted. ADC12 clock divider 000 /1 001 /2 010 /3 011 /4 100 /5 101 /6 110 /7 111 /8 ADC12 28-23 ADC12 Registers ADC12 Bits SSELx 4-3 CONSEQx Bits 2-1 ADC12 BUSY Bit 0 ADC12 clock source select 00 ADC12OSC 01 ACLK 10 MCLK 11 SMCLK Conversion sequence mode select 00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels ADC12 busy. This bit indicates an active sample or conversion operation. 0 No operation is active. 1 A sequence, sample, or conversion is active. ADC12MEMx, ADC12 Conversion Memory Registers 15 14 13 12 11 10 9 8 0 0 0 0 Conversion Results r0 r0 r0 r0 rw rw rw rw 7 6 5 4 3 2 1 0 Conversion Results rw rw rw rw rw rw rw rw Conversion Bits Results 15-0 The 12-bit conversion results are right-justified. Bit 11 is the MSB. Bits 15-12 are always 0. Writing to the conversion memory registers will corrupt the results. 28-24 ADC12 ADC12MCTLx, ADC12 Conversion Memory Control Registers ADC12 Registers 7 EOS rw−(0) 6 rw−(0) 5 SREFx rw−(0) 4 rw−(0) 3 rw−(0) 2 1 INCHx rw−(0) rw−(0) 0 rw−(0) Modifiable only when ENC = 0 EOS SREFx INCHx Bit 7 Bits 6-4 Bits 3-0 End of sequence. Indicates the last conversion in a sequence. 0 Not end of sequence 1 End of sequence Select reference 000 VR+ = AVCC and VR− = AVSS 001 VR+ = VREF+ and VR− = AVSS 010 VR+ = VeREF+ and VR− = AVSS 011 VR+ = VeREF+ and VR− = AVSS 100 VR+ = AVCC and VR− = VREF−/ VeREF− 101 VR+ = VREF+ and VR− = VREF−/ VeREF− 110 VR+ = VeREF+ and VR− = VREF−/ VeREF− 111 VR+ = VeREF+ and VR− = VREF−/ VeREF− Input channel select 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 1001 1010 VeREF+ VREF− /VeREF− Temperature sensor 1011 1100 1101 1110 1111 (AVCC – AVSS) / 2 (AVCC – AVSS) / 2, A12 on ’FG43x and ’FG461x devices (AVCC – AVSS) / 2, A13 on ’FG43x and ’FG461x devices (AVCC – AVSS) / 2, A14 on ’FG43x and ’FG461x devices (AVCC – AVSS) / 2, A15 on ’FG43x and ’FG461x devices ADC12 28-25 ADC12 Registers ADC12IE, ADC12 Interrupt Enable Register 15 14 13 12 11 10 9 8 ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IE9 ADC12IE8 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 ADC12IE7 ADC12IE6 ADC12IE5 ADC12IE4 ADC12IE3 ADC12IE2 ADC12IE1 ADC12IE0 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) ADC12IEx Bits 15-0 Interrupt enable. These bits enable or disable the interrupt request for the ADC12IFGx bits. 0 Interrupt disabled 1 Interrupt enabled ADC12IFG, ADC12 Interrupt Flag Register 15 ADC12 IFG15 rw−(0) 14 ADC12 IFG14 rw−(0) 13 ADC12 IFG13 rw−(0) 12 ADC12 IFG12 rw−(0) 11 ADC12 IFG11 rw−(0) 10 ADC12 IFG10 rw−(0) 9 ADC12 IFG9 rw−(0) 8 ADC12 IFG8 rw−(0) 7 ADC12 IFG7 rw−(0) 6 ADC12 IFG6 rw−(0) 5 ADC12 IFG5 rw−(0) 4 ADC12 IFG4 rw−(0) 3 ADC12 IFG3 rw−(0) 2 ADC12 IFG2 rw−(0) 1 ADC12 IFG1 rw−(0) 0 ADC12 IFG0 rw−(0) ADC12IFGx Bits 15-0 ADC12MEMx Interrupt flag. These bits are set when corresponding ADC12MEMx is loaded with a conversion result. The ADC12IFGx bits are reset if the corresponding ADC12MEMx is accessed, or may be reset with software. 0 No interrupt pending 1 Interrupt pending 28-26 ADC12 ADC12IV, ADC12 Interrupt Vector Register ADC12 Registers 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 ADC12IVx 0 r0 r0 r−(0) r−(0) r−(0) r−(0) r−(0) r0 ADC12IVx Bits 15-0 ADC12 interrupt vector value ADC12IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h Interrupt Source No interrupt pending ADC12MEMx overflow Conversion time overflow ADC12MEM0 interrupt flag ADC12MEM1 interrupt flag ADC12MEM2 interrupt flag ADC12MEM3 interrupt flag ADC12MEM4 interrupt flag ADC12MEM5 interrupt flag ADC12MEM6 interrupt flag ADC12MEM7 interrupt flag ADC12MEM8 interrupt flag ADC12MEM9 interrupt flag ADC12MEM10 interrupt flag ADC12MEM11 interrupt flag ADC12MEM12 interrupt flag ADC12MEM13 interrupt flag ADC12MEM14 interrupt flag ADC12MEM15 interrupt flag Interrupt Flag − − − ADC12IFG0 ADC12IFG1 ADC12IFG2 ADC12IFG3 ADC12IFG4 ADC12IFG5 ADC12IFG6 ADC12IFG7 ADC12IFG8 ADC12IFG9 ADC12IFG10 ADC12IFG11 ADC12IFG12 ADC12IFG13 ADC12IFG14 ADC12IFG15 Interrupt Priority Highest Lowest ADC12 28-27 28-28 ADC12 Chapter 29 SD16 The SD16 module is a multichannel 16-bit sigma-delta analog-to-digital converter. This chapter describes the SD16 of the MSP430x4xx family. The SD16 module is implemented in the MSP430F42x, MSP430F42xA, MSP430FE42x, MSP430FE42xA, and MSP430FE42x2 devices. Topic Page 29.1 SD16 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.2 SD16 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3 SD16 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19 SD16 29-1 SD16 Introduction 29.1 SD16 Introduction The SD16 module consists of up to three independent sigma-delta analog-to-digital converters and an internal voltage reference. Each channel has up to 8 fully differential multiplexed analog input pairs including a built-in temperature sensor. The converters are based on second-order oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to 256. Additional filtering can be done in software. Features of the SD16 include: - 16-bit sigma-delta architecture - Up to three independent, simultaneously sampling ADC channels (The number of channels is device dependent, see the device-specific data sheet.) - Up to eight multiplexed differential analog inputs per channel (The number of inputs is device dependent, see the device-specific data sheet.) - Software selectable on-chip reference voltage generation (1.2 V) - Software selectable internal or external reference - Built-in temperature sensor accessible by all channels - Up to 1.048576-MHz modulator input frequency - Selectable low-power conversion mode The block diagram of the SD16 module is shown in Figure 29−1. 29-2 SD16 Figure 29−1. SD16 Block Diagram SD16 Introduction VREF Reference SD16VMIDON SD16REFON SD16 Control Block Reference 1.2V AV CC AV SS SD16SSELx SD16DIVx Divider 1/2/4/8 00 MCLK 01 SMCLK 10 ACLK 11 TACLK Temperature sensor Reference fM Temperature sensor SD16INCHx Reference Channel 0 Conversion Control fM (to prior channel) Channel 1 Group/Start Conversion Logic SD16GRP SD16SC SD16SNGL A1.0 A1.1 A1.2 A1.3 A1.4 A1.5 A1.6 A1.7 + − 000 + − 001 + − 010 + − 011 + − 100 + − 101 + − 110 + − 111 SD16GAINx PGA 1..32 2nd Order ΣΔ Modulator SD16LP Conversion Control (from next channel) SD16OSRx 15 0 SD16MEM1 7 0 SD16PRE1 SD16DF Channel 2 SD16 29-3 SD16 Operation 29.2 SD16 Operation The SD16 module is configured with user software. The setup and operation of the SD16 is discussed in the following sections. 29.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency fM. The resulting 1-bit data stream is averaged by the digital filter for the conversion result. 29.2.2 Analog Input Range and PGA The full-scale input voltage range for each analog input pair is dependent on the gain setting of the programmable gain amplifier of each channel. The maximum full-scale range is ±VFSR where VFSR is defined by: VFSR + VREFń2 GAINPGA For a 1.2V reference, the maximum full-scale input range for a gain of 1 is: " VFSR + 1.2Vń2 1 +" 0.6 V Refer to the device-specific data sheet for full-scale input specifications. 29.2.3 Voltage Reference Generator The SD16 module has a built-in 1.2V reference that can be used for each SD16 channel and is enabled by the SD16REFON bit. When using the internal reference an external 100nF capacitor connected from VREF to AVSS is recommended to reduce noise. The internal reference voltage can be used off-chip when SD16VMIDON = 1. The buffered output can provide up to 1mA of drive. When using the internal reference off-chip, a 470nF capacitor connected from VREF to AVSS is required. See device-specific data sheet for parameters. An external voltage reference can be applied to the VREF input when SD16REFON and SD16VMIDON are both reset. 29.2.4 Auto Power-Down The SD16 is designed for low power applications. When the SD16 is not actively converting, it is automatically disabled and automatically re-enabled when a conversion is started. The reference is not automatically disabled, but can be disabled by setting SD16REFON = 0. When the SD16 or reference are disabled, they consume no current. 29-4 SD16 SD16 Operation 29.2.5 Analog Input Pair Selection Each SD16 channel can convert up to 8 differential input pairs multiplexed into the PGA. Up to six input pairs (A0-A5) are available externally on the device. See the device-specific data sheet for analog input pin information. An internal temperature sensor is available to each channel using the A6 multiplexer input. Input A7 is a shorted connection between the + and − input pair and can be used to calibrate the offset of each SD16 input stage. Note that the measured offset depends on the impedance of the external circuitry; thus, the actual offset seen at any of the analog inputs may be different. Analog Input Setup The analog input of each channel is configured using the SD16INCTLx register. These settings can be independently configured for each SD16 channel. The SD16INCHx bits select one of eight differential input pairs of the analog multiplexer. The gain for each PGA is selected by the SD16GAINx bits. A total of six gain settings are available. During conversion any modification to the SD16INCHx and SD16GAINx bits will become effective with the next decimation step of the digital filter. After these bits are modified, the next three conversions may be invalid due to the settling time of the digital filter. This can be handled automatically with the SD16INTDLYx bits. When SD16INTDLY = 00h, conversion interrupt requests will not begin until the 4th conversion after a start condition. An external RC anti-aliasing filter is recommended for the SD16 to prevent aliasing of the input signal. The cutoff frequency should be < 10 kHz for a 1-MHz modulator clock and OSR = 256. The cutoff frequency may set to a lower frequency for applications that have lower bandwidth requirements. SD16 29-5 SD16 Operation 29.2.6 Analog Input Characteristics The SD16 uses a switched-capacitor input stage that appears as an impedance to external circuitry as shown in Figure 29−2. Figure 29−2. Analog Input Equivalent Circuit RS VS+ RS VS− MSP430 1 kW 1 kW VS+ = Positive external source voltage VS− = Negative external source voltage RS = External source resistance CS = Sampling capacitance CS AVCC / 2 CS The maximum modulator frequency fM may be calculated from the minimum settling time tSettling of the sampling circuit given by: tSettling w (RS ) 1kW) CS ǒGAIN 217 ln VREF ǓVAx where ǒŤ Ť Ť ŤǓ fM + 2 1 tSettling and VAx + max AVCC 2 * VS) , AVCC 2 * VS* , with VS+ and VS− referenced to AVSS. CS varies with the gain setting as shown in Table 29−1. Table 29−1.Sampling Capacitance PGA Gain 1 2, 4 8 16, 32 Sampling Capacitance CS 1.25 pF 2.5 pF 5 pF 10 pF 29-6 SD16 SD16 Operation 29.2.7 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC3 comb filter. The transfer function is described in the z-Domain by: ǒ Ǔ H(z) + 1 OSR 1 * z*OSR 3 1 * z*1 and in the frequency domain by: ȧȱȲ ǒ ǒ Ǔ Ǔȳȴȧ ȧȡȢ HǒfǓ + sinc OSRp f fM sinc p f fM 3 + 1 OSR ǒsin OSR ǒsin p 3 Ǔȣ p f fM ȧ f Ǔ Ȥ fM where the oversampling rate, OSR, is the ratio of the modulator frequency fM to the sample frequency fS. Figure 29−3 shows the filter’s frequency response for an OSR of 32. The first filter notch is at fS = fM/OSR. The notch frequency can be adjusted by changing the modulator frequency, fM, using SD16SSELx and SD16DIVx and the oversampling rate using SD16OSRx. The digital filter for each enabled ADC channel completes the decimation of the digital bit-stream and outputs new conversion results to the corresponding SD16MEMx register at the sample frequency fS. Figure 29−3. Comb Filter’s Frequency Response with OSR = 32 GAIN [dB] 0 −20 −40 −60 −80 −100 −120 −140 fS Frequency fM SD16 29-7 SD16 Operation Figure 29−4 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input. If the step occurs synchronously to the decimation of the digital filter the valid data will be available on the third conversion. An asynchronous step will require one additional conversion before valid data is available. Figure 29−4. Digital Filter Step Response and Conversion Points Asynchronous Step 1 4 3 0.8 Synchronous Step 1 3 2 0.8 % VFSR 0.6 0.6 2 0.4 0.4 0.2 1 0 Conversion 0.2 1 0 Conversion 29-8 SD16 SD16 Operation Digital Filter Output The number of bits output by each digital filter is dependent on the oversampling ratio and ranges from 16 to 24 bits. Figure 29−5 shows the digital filter output bits and their relation to SD16MEMx for each OSR. For example, for OSR = 256 and LSBACC = 0, the SD16MEMx register contains bits 23 − 8 of the digital filter output. When OSR = 32, the SD16MEMx LSB is always zero. The SD16LSBACC and SD16LSBTOG bits give access to the least significant bits of the digital filter output. When SD16LSBACC = 1 the 16 least significant bits of the digital filter’s output are read from SD16MEMx using word instructions. The SD16MEMx register can also be accessed with byte instructions returning only the 8 least significant bits of the digital filter output. When SD16LSBTOG = 1 the SD16LSBACC bit is automatically toggled each time the corresponding channel’s SD16MEMx register is read. This allows the complete digital filter output result to be read with two read accesses of SD16MEMx. Setting or clearing SD16LSBTOG does not change SD16LSBACC until the next SD16MEMx access. Figure 29−5. Used Bits of Digital Filter Output. OSR=256, LSBACC=0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSR=256, LSBACC=1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSR=128, LSBACC=0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSR=128, LSBACC=1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSR=64, LSBACC=0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSR=64, LSBACC=1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSR=32, LSBACC=x 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SD16 29-9 SD16 Operation 29.2.8 Conversion Memory Registers: SD16MEMx One SD16MEMx register is associated with each SD16 channel. Conversion results for each channel are moved to the corresponding SD16MEMx register with each decimation step of the digital filter. The SD16IFG bit for a given channel is set when new data is written to SD16MEMx. SD16IFG is automatically cleared when SD16MEMx is read by the CPU or may be cleared with software. Output Data Format The output data format is configurable in two’s complement or offset binary as shown in Table 29−2.The data format is selected by the SD16DF bit. Table 29−2.Data Format SD16DF Format Analog Input SD16MEMx† +FSR 0 Offset Binary ZERO −FSR FFFF 8000 0000 +FSR 7FFF 1 Two’s complement ZERO −FSR 0000 8000 † Independent of SD16OSRx setting; SD16LSBACC = 0. Digital Filter Output (OSR = 256) FFFFFF 800000 000000 7FFFFF 000000 800000 Figure 29−6 shows the relationship between the full-scale input voltage range from −VFSR to +VFSR and the conversion result. The digital values for both data formats are illustrated. Figure 29−6. Input Voltage vs Digital Output Offset Binary SD16MEMx 2’s complement SD16MEMx FFFFh 7FFFh 8000h −VFSR 0000h Input Voltage +V FSR −VFSR 0000h Input Voltage +V FSR 8000h 29-10 SD16 SD16 Operation 29.2.9 Conversion Modes The SD16 module can be configured for four modes of operation, listed in Table 29−3. The SD16SNGL and SD16GRP bits for each channel selects the conversion mode. Table 29−3.Conversion Mode Summary SD16SNGL SD16GRP{ Mode Operation 1 0 Single channel, A single channel is Single conversion converted once. 0 0 Single channel, A single channel is Continuous conversion converted continuously. 1 1 Group of channels, A group of channels is Single conversion converted once. 0 1 Group of channels, A group of channels is Continuous conversion converted continuously. † A channel is grouped and is the master channel of the group when SD16GRP = 0 if SD16GRP for the prior channel(s) is set. Single Channel, Single Conversion Setting the SD16SC bit of a channel initiates one conversion on that channel when SD16SNGL = 1 and it is not grouped with any other channels. The SD16SC bit is automatically cleared after conversion completion. Clearing SD16SC before the conversion is completed immediately stops conversion of the selected channel, the channel is powered down, and the corresponding digital filter is turned off. The value in SD16MEMx can change when SD16SC is cleared. It is recommended that the conversion data in SD16MEMx be read prior to clearing SD16SC to avoid reading an invalid result. Single Channel, Continuous Conversion When SD16SNGL = 0, continuous conversion mode is selected. Conversion of the selected channel begins when SD16SC is set and continues until the SD16SC bit is cleared by software when the channel is not grouped with any other channel. Clearing SD16SC immediately stops conversion of the selected channel, the channel is powered downs and the corresponding digital filter is turned off. The value in SD16MEMx can change when SD16SC is cleared. It is recommended that the conversion data in SD16MEMx be read prior to clearing SD16SC to avoid reading an invalid result. Figure 29−7 shows single channel operation for single conversion mode and continuous conversion mode. SD16 29-11 SD16 Operation Figure 29−7. Single Channel Operation − Example Channel 0 SD16SNGL = 1 SD16GRP = 0 SD16SC Conversion Set by SW Auto−clear Channel 1 SD16SNGL = 1 SD16GRP = 0 SD16SC Conversion Set by SW Auto−clear Channel 2 SD16SNGL = 0 SD16GRP = 0 SD16SC Conversion Set by SW Conversion = Result written to SD16MEMx Conversion Set by SW Auto−clear Conversion Conv Cleared by SW Time Group of Channels, Single Conversion Consecutive SD16 channels can be grouped together with the SD16GRP bit to synchronize conversions. Setting SD16GRP for a channel groups that channel with the next channel in the module. For example, setting SD16GRP for channel 0 groups that channel with channel 1. In this case, channel 1 is the master channel, enabling and disabling conversion of all channels in the group with its SD16SC bit. The SD16GRP bit of the master channel is always 0. The SD16GRP bit of last channel in SD16 has no function and is always 0. When SD16SNGL = 1 for a channel in a group, single conversion mode is selected. A single conversion of that channel will occur synchronously when the master channel SD16SC bit is set. The SD16SC bit of all channels in the group will automatically be set and cleared by SD16SC of the master channel. SD16SC for each channel can also be cleared in software independently. Clearing SD16SC of the master channel before the conversions are completed immediately stops conversions of all channels in the group, the channels are powered down and the corresponding digital filters are turned off. Values in SD16MEMx can change when SD16SC is cleared. It is recommended that the conversion data in SD16MEMx be read prior to clearing SD16SC to avoid reading an invalid result. 29-12 SD16 SD16 Operation Group of Channels, Continuous Conversion When SD16SNGL = 0 for a channel in a group, continuous conversion mode is selected. Continuous conversion of that channel occurs synchronously when the master channel SD16SC bit is set. SD16SC bits for all grouped channels are automatically set and cleared with the master channel’s SD16SC bit. SD16SC for each channel in the group can also be cleared in software independently. When SD16SC of a grouped channel is set by software independently of the master, conversion of that channel automatically synchronizes to conversions of the master channel. This ensures that conversions for grouped channels are always synchronous to the master. Clearing SD16SC of the master channel immediately stops conversions of all channels in the group the channels are powered down and the corresponding digital filters are turned off. Values in SD16MEMx can change when SD16SC is cleared. It is recommended that the conversion data in SD16MEMx be read prior to clearing SD16SC to avoid reading an invalid result. Figure 29−8 shows grouped channel operation for three SD16 channels. Channel 0 is configured for single conversion mode, SD16SNGL = 1, and channels 1 and 2 are in continuous conversion mode, SD16SNGL = 0. Channel two, the last channel in the group, is the master channel. Conversions of all channels in the group occur synchronously to the master channel regardless of when each SD16SC bit is set using software. Figure 29−8. Grouped Channel Operation − Example Channel 0 SD16SNGL = 1 SD16GRP = 1 SD16SC Channel 1 SD16SNGL = 0 SD16GRP =1 SD16SC Conversion (syncronized to master) Conversion Set by Ch2 Conversion Auto−clear Conv Set by SW Auto−clear (syncronized to master) Conversion Conv Set by Ch2 Cleared by SW Set by SW Cleared by Ch2 Channel 2 SD16SNGL = 0 SD16GRP = 0 SD16SC Conversion Set by SW = Result written to SD16MEMx Conversion Conversion Conv Cleared by SW Time SD16 29-13 SD16 Operation 29.2.10 Conversion Operation Using Preload When multiple channels are grouped the SD16PREx registers can be used to delay the conversion time frame for each channel. Using SD16PREx, the decimation time of the digital filter is increased by the specified number of fM clock cycles and can range from 0 to 255. Figure 29−9 shows an example using SD16PREx. Figure 29−9. Conversion Delay using Preload − Example SD16OSRx = 32 fM cycles: 32 Conversion 40 Delayed Conversion 32 Conversion Load SD16PREx: SD16PREx = 8 Preload applied Delayed Conversion Result Time The SD16PREx delay is applied to the beginning of the next conversion cycle after being written. The delay is used on the first conversion after SD16SC is set and on the conversion cycle following each write to SD16PREx. Following conversions are not delayed. After modifying SD16PREx, the next write to SD16PREx should not occur until the next conversion cycle is completed, otherwise the conversion results may be incorrect. The accuracy of the result for the delayed conversion cycle using SD16PREx is dependent on the length of the delay and the frequency of the analog signal being sampled. For example, when measuring a DC signal, SD16PREx delay has no effect on the conversion result regardless of the duration. The user must determine when the delayed conversion result is useful in their application. Figure 29−10 shows the operation of grouped channels 0 and 1. The preload register of channel 1 is loaded with zero resulting in immediate conversion whereas the conversion cycle of channel 0 is delayed by setting SD16PRE0 = 8. The first channel 0 conversion uses SD16PREx = 8, shifting all subsequent conversions by 8 fM clock cycles. 29-14 SD16 Figure 29−10. Start of Conversion using Preload − Example SD16OSRx = 32 fM cycles: SD16PRE0 = 8 40 Delayed Conversion 32 Conversion 32 Conversion SD16 Operation SD16PRE1 = 0 32 Conversion 1stSample Ch0 32 Conversion 32 Conversion Conversion Start of Conversion 1stSample Ch1 Time When channels are grouped, care must be taken when a channel or channels operate in single conversion mode or are disabled in software while the master channel remains active. Each time channels in the group are re-enabled and resynchronized with the master channel, the preload delay for that channel will be reintroduced. Figure 29−11 shows the re-synchronization and preload delays for channels in a group. It is recommended that SD16PREx = 0 for the master channel to maintain a consistent delay between the master and remaining channels in the group when they are re-enabled. Figure 29−11.Preload and Channel Synchronization Channel 0 SD16SNGL = 0 SD16GRP = 1 SD16SC Channel 1 SD16SNGL = 1 SD16GRP =1 SD16SC PRE0 Conversion Conv (syncronized to master) PRE0 Conv Set by Ch2 PRE1 Conversion Cleared by SW Set by SW (syncronized to master) PRE1 Conversion Set by Ch2 Auto−clear Set by SW Auto−clear Channel 2 SD16SNGL = 0 SD16GRP = 0 SD16SC Conversion Set by SW = Result written to SD16MEMx Conversion Conversion Conversion Time SD16 29-15 SD16 Operation 29.2.11 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input pair SD16INCHx = 110 and sets SD16REFON = 1. Any other configuration is done as if an external analog input pair was selected, including SD16INTDLYx and SD16GAINx settings. Because the internal reference must be on to use the temperature sensor, it is not possible to use an external reference for the conversion of the temperature sensor voltage. Also, the internal reference will be in contention with any used external reference. In this case, the SD16VMIDON bit may be set to minimize the affects of the contention on the conversion. The typical temperature sensor transfer function is shown in Figure 29−12. When switching inputs of an SD16 channel to the temperature sensor, adequate delay must be provided using SD16INTDLYx to allow the digital filter to settle and assure that conversion results are valid. The temperature sensor offset error can be large, and may need to be calibrated for most applications. See device-specific data sheet for temperature sensor parameters. Figure 29−12. Typical Temperature Sensor Transfer Function Volts 0.500 0.450 0.400 0.350 0.300 0.250 VSensor,typ = TCSensor(273 + T[oC]) + VOffset, sensor [mV] 0.200 −50 0 Celsius 50 100 29-16 SD16 SD16 Operation 29.2.12 Interrupt Handling The SD16 has 2 interrupt sources for each ADC channel: - SD16IFG - SD16OVIFG The SD16IFG bits are set when their corresponding SD16MEMx memory register is written with a conversion result. An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set. The SD16 overflow condition occurs when a conversion result is written to any SD16MEMx location before the previous conversion result was read. SD16IV, Interrupt Vector Generator All SD16 interrupt sources are prioritized and combined to source a single interrupt vector. SD16IV is used to determine which enabled SD16 interrupt source requested an interrupt. The highest priority SD16 interrupt request that is enabled generates a number in the SD16IV register (see register description). This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled SD16 interrupts do not affect the SD16IV value. Any access, read or write, of the SD16IV register has no effect on the SD16OVIFG or SD16IFG flags. The SD16IFG flags are reset by reading the associated SD16MEMx register or by clearing the flags in software. SD16OVIFG bits can only be reset with software. If another interrupt is pending after servicing of an interrupt, another interrupt is generated. For example, if the SD16OVIFG and one or more SD16IFG interrupts are pending when the interrupt service routine accesses the SD16IV register, the SD16OVIFG interrupt condition is serviced first and the corresponding flag(s) must be cleared in software. After the RETI instruction of the interrupt service routine is executed, the highest priority SD16IFG pending generates another interrupt request. Interrupt Delay Operation The SD16INTDLYx bits control the timing for the first interrupt service request for the corresponding channel. This feature delays the interrupt request for a completed conversion by up to four conversion cycles allowing the digital filter to settle prior to generating an interrupt request. The delay is applied each time the SD16SC bit is set or when the SD16GAINx or SD16INCHx bits for the channel are modified. SD16INTDLYx disables overflow interrupt generation for the channel for the selected number of delay cycles. Interrupt requests for the delayed conversions are not generated during the delay. SD16 29-17 SD16 Operation SD16 Interrupt Handling Software Example The following software example shows the recommended use of SD16IV and the handling overhead. The SD16IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. The latencies are: - SD16OVIFG, CH0 SD16IFG, CH1 SD16IFG 16 cycles - CH2 SD16IFG 14 cycles The interrupt handler for channel 2 SD16IFG shows a way to check immediately if a higher prioritized interrupt occurred during the processing of the ISR. This saves nine cycles if another SD16 interrupt is pending. ; Interrupt handler for SD16. INT_SD16 ; Enter Interrupt Service Routine 6 ADD &SD16IV,PC; Add offset to PC 3 RETI ; Vector 0: No interrupt 5 JMP ADOV ; Vector 2: ADC overflow 2 JMP ADM0 ; Vector 4: CH_0 SD16IFG 2 JMP ADM1 ; Vector 6: CH_1 SD16IFG 2 ; ; Handler for CH_2 SD16IFG starts here. No JMP required. ; ADM2 MOV &SD16MEM2,xxx ; Move result, flag is reset ... ; Other instruction needed? JMP INT_SD16 ; Check other int pending 2 ; ; Remaining Handlers ; ADM1 MOV &SD16MEM1,xxx ; Move result, flag is reset ... ; Other instruction needed? RETI ; Return 5 ; ADM0 MOV &SD16MEM0,xxx ; Move result, flag is reset RETI ; Return 5 ; ADOV ... ; Handle SD16MEMx overflow RETI ; Return 5 29-18 SD16 SD16 Registers 29.3 SD16 Registers The SD16 registers are listed in Table 29−4: Table 29−4.SD16 Registers Register SD16 Control SD16 Interrupt Vector SD16 Channel 0 Control SD16 Channel 0 Conversion Memory SD16 Channel 0 Input Control SD16 Channel 0 Preload SD16 Channel 1 Control SD16 Channel 1 Conversion Memory SD16 Channel 1 Input Control SD16 Channel 1 Preload SD16 Channel 2 Control SD16 Channel 2 Conversion Memory SD16 Channel 2 Input Control SD16 Channel 2 Preload Short Form SD16CTL SD16IV SD16CCTL0 SD16MEM0 SD16INCTL0 SD16PRE0 SD16CCTL1 SD16MEM1 SD16INCTL1 SD16PRE1 SD16CCTL2 SD16MEM2 SD16INCTL2 SD16PRE2 Register Type Address Read/write 0100h Read/write 0110h Read/write 0102h Read/write 0112h Read/write 0B0h Read/write 0B8h Read/write 0104h Read/write 0114h Read/write 0B1h Read/write 0B9h Read/write 0106h Read/write 0116h Read/write 0B2h Read/write 0BAh Initial State Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC SD16 29-19 SD16 Registers SD16CTL, SD16 Control Register 15 14 13 12 11 10 9 8 Reserved SD16LP r0 r0 r0 r0 r0 r0 r0 rw−0 7 6 SD16DIVx rw−0 rw−0 5 4 SD16SSELx rw−0 rw−0 3 SD16 VMIDON rw−0 2 SD16 REFON rw−0 1 0 SD16OVIE Reserved rw−0 r0 Reserved SD16LP Bits 15-9 Bit 8 SD16DIVx Bits 7-6 SD16SSELx Bits 5-4 SD16 VMIDON Bit 3 SD16 REFON Bit 2 SD16OVIE Bit 1 Reserved Bit 0 Reserved Low-power mode. This bit selects a reduced-speed reduced-power mode for the SD16. 0 Low-power mode is disabled 1 Low-power mode is enabled. The maximum clock frequency for the SD16 is reduced. SD16 clock divider 00 /1 01 /2 10 /4 11 /8 SD16 clock source select 00 MCLK 01 SMCLK 10 ACLK 11 External TACLK VMID buffer on 0 Off 1 On Reference generator on 0 Reference off 1 Reference on SD16 overflow interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Overflow interrupt disabled 1 Overflow interrupt enabled Reserved 29-20 SD16 SD16CCTLx, SD16 Channel x Control Register 15 14 13 12 11 Reserved r0 r0 r0 r0 r0 SD16 Registers 10 SD16SNGL rw−0 9 8 SD16OSRx rw−0 rw−0 7 SD16 LSBTOG rw−0 6 SD16 LSBACC rw−0 5 SD16 OVIFG rw−0 4 SD16DF rw−0 3 SD16IE rw−0 2 SD16IFG rw−0 1 SD16SC rw−0 0 SD16GRP r(w)−0 Reserved Bits 15-11 SD16SNGL Bit 10 SD16OSRx Bits 9-8 SD16 LSBTOG Bit 7 SD16 LSBACC Bit 6 SD16OVIFG Bit 5 SD16DF Bit 4 SD16IE Bit 3 Reserved Single conversion mode select 0 Continuous conversion mode 1 Single conversion mode Oversampling ratio 00 256 01 128 10 64 11 32 LSB toggle. This bit, when set, causes SD16LSBACC to toggle each time the SD16MEMx register is read. 0 SD16LSBACC does not toggle with each SD16MEMx read 1 SD16LSBACC toggles with each SD16MEMx read LSB access. This bit allows access to the upper or lower 16-bits of the SD16 conversion result. 0 SD16MEMx contains the most significant 16-bits of the conversion. 1 SD16MEMx contains the least significant 16-bits of the conversion. SD16 overflow interrupt flag 0 No overflow interrupt pending 1 Overflow interrupt pending SD16 data format 0 Offset binary 1 2’s complement SD16 interrupt enable 0 Disabled 1 Enabled SD16 29-21 SD16 Registers SD16IFG Bit 2 SD16SC Bit 1 SD16GRP Bit 0 SD16 interrupt flag. SD16IFG is set when new conversion results are available. SD16IFG is automatically reset when the corresponding SD16MEMx register is read, or may be cleared with software. 0 No interrupt pending 1 Interrupt pending SD16 start conversion 0 No conversion start 1 Start conversion SD16 group. Groups SD16 channel with next higher channel. Not used for the last channel. 0 Not grouped 1 Grouped SD16INCTLx, SD16 Channel x Input Control Register 7 6 SD16INTDLYx rw−0 rw−0 5 rw−0 4 SD16GAINx rw−0 3 rw−0 2 rw−0 1 SD16INCHx rw−0 0 rw−0 SD16 Bits INTDLYx 7-6 SD16GAINx Bits 5-3 SD16INCHx Bits 2-0 Interrupt delay generation after conversion start. These bits select the delay for the first interrupt after conversion start. 00 Fourth sample causes interrupt 01 Third sample causes interrupt 10 Second sample causes interrupt 11 First sample causes interrupt SD16 preamplifier gain 000 x1 001 x2 010 x4 011 x8 100 x16 101 x32 110 Reserved 111 Reserved SD16 channel differential pair input 000 Ax.0 001 Ax.1 010 Ax.2 011 Ax.3 100 Ax.4 101 Ax.5 110 Ax.6- Temperature Sensor 111 Ax.7- Short for PGA offset measurement 29-22 SD16 SD16MEMx, SD16 Channel x Conversion Memory Register 15 14 13 12 11 10 Conversion Results r r r r r r 7 6 5 4 3 2 Conversion Results r r r r r r SD16 Registers 9 8 r r 1 0 r r Conversion Bits Result 15-0 Conversion Results. The SD16MEMx register holds the upper or lower 16-bits of the digital filter output, depending on the SD16LSBACC bit. SD16PREx, SD16 Channel x Preload Register 7 rw−0 6 rw−0 5 rw−0 4 3 Preload Value rw−0 rw−0 2 rw−0 1 rw−0 0 rw−0 SD16 Bits SD16 digital filter preload value. Preload 7-0 Value SD16 29-23 SD16 Registers SD16IV, SD16 Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 SD16IVx 0 r0 r0 r0 r−0 r−0 r−0 r−0 r0 SD16IVx Bits 15-0 SD16 interrupt vector value SD16IV Contents Interrupt Source Interrupt Interrupt Flag Priority 000h No interrupt pending − 002h SD16MEMx overflow SD16CCTLx Highest SD16OVIFG† 004h SD16_0 Interrupt SD16CCTL0 SD16IFG 006h SD16_1 Interrupt SD16CCTL1 SD16IFG 008h SD16_2 Interrupt SD16CCTL1 SD16IFG 00Ah Reserved − 00Ch Reserved − 00Eh Reserved − 010h Reserved − Lowest † When an SD16 overflow occurs, the user must check all SD16CCTLx SD16OVIFG flags to determine which channel overflowed. 29-24 SD16 Chapter 30 SD16_A The SD16_A module is a multichannel 16-bit sigma-delta analog-to-digital converter (ADC). This chapter describes the SD16_A of the MSP430x4xx family. The SD16_A module is implemented in the MSP430F42x0, MSP430FG42x0, MSP430F47x , MSP430FG47x, MSP430F47x3/4, and MSP430F471xx devices. Topic Page 30.1 SD16_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.2 SD16_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.3 SD16_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22 SD16_A 30-1 SD16_A Introduction 30.1 SD16_A Introduction The SD16_A module consists of up to seven independent sigma-delta analog-to-digital converters, referred to as channels, and an internal voltage reference. Each channel has up to eight fully differential multiplexed analog input pairs including a built-in temperature sensor and a divided supply voltage. The converters are based on second-order oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to 1024. Additional filtering can be done in software. Features of the SD16_A include: - 16-bit sigma-delta architecture - Up to seven independent, simultaneously-sampling ADC channels. (The number of channels is device dependent, see the device-specific data sheet.) - Up to eight multiplexed differential analog inputs per channel (The number of inputs is device dependent, see the device-specific data sheet.) - Software selectable on-chip reference voltage generation (1.2 V) - Software selectable internal or external reference - Built-in temperature sensor accessible by all channels - Up to 1.1-MHz modulator input frequency - High impedance input buffer (not implemented on all devices, see the device-specific data sheet) - Selectable low-power conversion mode The block diagram of the SD16_A module is shown in Figure 30−1 for the MSP430F47x3/4 and MSP430F471xx. The block diagram of the SD16_A module is shown in Figure 30−2 for the MSP430F42x0, MSP430F47x, MSP430FG47x, and MSP430FG42x0. 30-2 SD16_A SD16_A Introduction Figure 30−1. Block Diagram of the MSP430F47x3/4 and MSP430F471xx SD16_A SD16REFON SD16_A Control Block VREF 0 Reference 1.2V SD16SSELx AVCC SD16XDIVx SD16DIVx 1 00 MCLK AVSS Reference Divider fM 1/3/16/48 Divider 1/2/4/8 01 SMCLK 10 ACLK 11 TACLK ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌSD1ÌÌ6VMÌÌIDOÌÌN ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌChaÌÌnneÌÌl0 Conversion Control Channel 1 (to prior channel) SD16INCHx Group/Start Conversion Logic SD16GRP SD16SC SD16SGNL A1.0 A1.1 A1.2 A1.3 A1.4 A1.5 A1.6 A1.7 + − 000 + − 001 + − 010 + − 011 + − 100 + − 101 + − 110 + − 111 SD16GAINx PGA 1..32 2ndOrder ΣΔ Modulator SD16LP Conversion Control (from next channel) SD16OSRx 15 0 SD16MEM1 SD16XOSR SD16PRE1 SD16UNI SD16DF ÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑRÌÌÑÑeferÌÌÑÑenceÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑÌÌÑÑTCÌÌÑÑehmapnÌÌÑÑenrealt3ÌÌÑÑur(eu.ÌÌÑÑpantodÌÌÑÑCVChchcaaÌÌÑÑnSnnneeneÌÌÑÑlls62e) Temp. sensor AVCC 1 SD16INCHx=101 5R R 5R Note: Ax.1 to Ax.4 not available on all devices. See device-specific data sheet. SD16_A 30-3 SD16_A Introduction Figure 30−2. Block Diagram of the MSP430F42x0, MSP430FG42x0, MSP430FG47x, and MSP430F47x SD16_A SD16REFON VREF 0 Reference 1.2V 1 AV SS Reference SD16VMIDON SD16INCHx SD16SSELx AV CC SD16XDIVx SD16DIVx Divider fM 1/3/16/48 Divider 1/2/4/8 00 MCLK 01 SMCLK 10 ACLK 11 TACLK Start Conversion Logic SD16SC SD16SNGL A0 + − 000 A1 A2 A3 A4 + − + − 001 010 SD16BUFx SD16GAINx + − 011 + − 100 BUF PGA 1..32 2ndOrder ΣΔ Modulator SD16OSRx 15 0 SD16MEM0 A5 + − 101 A6 + − 110 A7 + − 111 Reference SD16LP SD16XOSR SD16UNI SD16DF Temp. sensor AVCC 1 SD16INCHx=101 5R R 5R 30-4 SD16_A SD16_A Operation 30.2 SD16_A Operation The SD16_A module is configured with user software. The setup and operation of the SD16_A is discussed in the following sections. 30.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency fM. The resulting 1-bit data stream is averaged by the digital filter for the conversion result. 30.2.2 Analog Input Range and PGA The full-scale input voltage range for each analog input pair is dependent on the gain setting of the programmable gain amplifier of each channel. The maximum full-scale range is ±VFSR where VFSR is defined by: VFSR + VREFń2 GAINPGA For a 1.2V reference, the maximum full-scale input range for a gain of 1 is: " VFSR + 1.2Vń2 1 +" 0.6V See the device-specific data sheet for full-scale input specifications. 30.2.3 Voltage Reference Generator The SD16_A module has a built-in 1.2V reference. It can be used for each SD16_A channel and is enabled by the SD16REFON bit. When using the internal reference an external 100nF capacitor connected from VREF to AVSS is recommended to reduce noise. The internal reference voltage can be used off-chip when SD16VMIDON = 1. The buffered output can provide up to 1mA of drive. When using the internal reference off-chip, a 470nF capacitor connected from VREF to AVSS is required. See device-specific data sheet for parameters. An external voltage reference can be applied to the VREF input when SD16REFON and SD16VMIDON are both reset. 30.2.4 Auto Power-Down The SD16_A is designed for low power applications. When the SD16_A is not actively converting, it is automatically disabled and automatically re-enabled when a conversion is started. The reference is not automatically disabled, but can be disabled by setting SD16REFON = 0. When