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数字锁相环

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本书是介绍数字锁相环方面知识的书籍

DIGITAL PHASE LOCK LOOPS Digital Phase Lock Loops Architectures and Applications by SALEH R. AL-ARAJI Etisalat University College, Sharjah, UAE ZAHIR M. HUSSAIN RMIT University, Melbourne, Australia and MAHMOUD A. AL-QUTAYRI Etisalat University College, Sharjah, UAE A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN-10 0-387-32863-7 (HB) ISBN-13 978-0-387-32863-8 (HB) ISBN-10 0-387-32864-5 (e-book) ISBN-13 978-0-387-32864-5 (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com Printed on acid-free paper All Rights Reserved © 2006 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed in the Netherlands. This book is dedicated to our families Contents Preface xi Acknowledgement xv Acronyms xvii 1 General Review of Phase-Locked Loops 1 1.1 Overview of Phase-Locked Synchronization Schemes . . . . . . . 1 1.2 The Synchronization Challenge . . . . . . . . . . . . . . . . . . 3 1.3 Phase-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1 Analog Phase-locked Loops . . . . . . . . . . . . . . . . 4 1.3.2 PLL Basic Components . . . . . . . . . . . . . . . . . . 6 1.3.3 PLL analysis . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Digital Phase Lock Loops 15 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Classification of DPLLs . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3 The Time-Delay Digital Tanlock Loops (TDTLs) 31 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 Structure and System Equation . . . . . . . . . . . . . . . . . . 32 3.2.1 Structure of the TDTL . . . . . . . . . . . . . . . . . . . 32 3.2.2 System Equation . . . . . . . . . . . . . . . . . . . . . . 32 3.2.3 The Characteristic Function . . . . . . . . . . . . . . . . 34 3.3 System Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3.1 First-order TDTL . . . . . . . . . . . . . . . . . . . . . . 35 3.3.2 Second-Order TDTL . . . . . . . . . . . . . . . . . . . . 43 3.4 Locking Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.1 Convergence of the First-Order TDTL . . . . . . . . . . 46 3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 vii viii CONTENTS 4 Hilbert Transformer and Time-Delay 51 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 Statistical Behavior of HT and Time-Delay in i.i.d. Additive Gaussian Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2.1 Input-Output Relationships in the Presence of Noise . . 53 4.2.2 Joint PDF of the Amplitude and Phase Random Variables 54 4.2.3 PDF of the Phase Random Variable . . . . . . . . . . . . 56 4.2.4 PDF of the Phase Noise . . . . . . . . . . . . . . . . . . 57 4.2.5 Expectation and Variance of the Phase Noise . . . . . . 58 4.2.6 The phase Estimator and Ranges of Cramer-Rao Bounds 62 4.2.7 A Symmetric Transformation . . . . . . . . . . . . . . . 65 4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5 The Time-delay Digital Tanlock Loop in Noise 69 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2 Noise Analysis of the TDTL . . . . . . . . . . . . . . . . . . . . 70 5.2.1 System Equation . . . . . . . . . . . . . . . . . . . . . . 70 5.2.2 Statistical Behavior of TDTL Phase Error Detector . . . 71 5.2.3 Phase Estimation and Cramer-Rao Bounds . . . . . . . . 74 5.2.4 Statistical Behavior of the TDTL in Gaussian Noise . . . 77 5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6 Architectures for Improved Performance 85 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.2 Simulation Results of First-Order TDTL . . . . . . . . . . . . . 85 6.3 Improved First-Order TDTL Architectures . . . . . . . . . . . . 88 6.3.1 Delay Switching Architecture . . . . . . . . . . . . . . . 89 6.3.2 Adaptive Gain Architecture . . . . . . . . . . . . . . . . 94 6.3.3 Combined Delay Switching and Adaptive Gain . . . . . . 100 6.3.4 Sample Sensing Adaptive Architecture . . . . . . . . . . 105 6.3.5 Early Error Sensing Adaptive Architecture . . . . . . . . 113 6.4 Simulation Results of Second-Order TDTL . . . . . . . . . . . . 115 6.5 Improved Second-Order TDTL Architectures . . . . . . . . . . . 121 6.5.1 Adaptive Filter Coefficients Second-Order TDTL . . . . 121 6.5.2 Adaptive Loop Gain Second-Order TDTL . . . . . . . . 123 6.6 A Variable Order TDTL Architecture . . . . . . . . . . . . . . . 123 6.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7 FPGA Reconfigurable TDTL 137 7.1 Overview of Reconfigurable Systems . . . . . . . . . . . . . . . . 137 7.2 FPGA Structure and Operation . . . . . . . . . . . . . . . . . . 138 CONTENTS ix 7.3 Xtreme DSP Development System . . . . . . . . . . . . . . . . . 142 7.4 TDTL FPGA Implementation . . . . . . . . . . . . . . . . . . . 149 7.4.1 The CORDIC Arctangent Block . . . . . . . . . . . . . . 151 7.4.2 The Digital Controlled Oscillator . . . . . . . . . . . . . 152 7.4.3 The CORDIC Divider . . . . . . . . . . . . . . . . . . . 154 7.5 Real-Time TDTL Results . . . . . . . . . . . . . . . . . . . . . 156 7.5.1 First-Order TDTL . . . . . . . . . . . . . . . . . . . . . 157 7.5.2 Second-Order TDTL . . . . . . . . . . . . . . . . . . . . 157 7.5.3 Sample Sensing Adaptive TDTL . . . . . . . . . . . . . . 159 7.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8 Selected Applications 165 8.1 PM Demodulation Using TDTL . . . . . . . . . . . . . . . . . . 165 8.2 Performance in Gaussian Noise . . . . . . . . . . . . . . . . . . 169 8.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . 171 8.4 FSK and FM Demodulation . . . . . . . . . . . . . . . . . . . . 172 8.5 Wideband FM Signal Detection . . . . . . . . . . . . . . . . . . 173 8.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Bibliography 179 Index 189 Preface Since their introduction by de Bellescize in 1936, analogue Phase-Locked Loops (PLLs) have continued to play a major role in the advancement of several fields such as communications, signal processing and control [11]. Despite their performance advantages, analogue PLLs suffer from major drawbacks related to their analogue nature. These include aging and temperature drift effects, the sensitivity to component tolerances and operating conditions. In an attempt to combat the aforementioned drawbacks, Digital Phase-Locked Loops (DPLLs) were introduced in the 1970s as a result of the advent of digital technology and the urgent need for robust methods of synchronization for space communications [12]. One of the most promising versions of the DPLL is the Digital Tanlock Loop(DTL), which was introduced [13]. This loop offered many appealing features such as the linearity of the phase characteristics and the insensitivity to the variations in signal power. However, it did not gain a lot of popularity due to the complexities faced in the design of the Hilbert transformer, one of its major components. Recently, an approach was proposed to rid the DTL from the Hilbert Transformer and its complexities by replacing it with a fixed time delay unit. This approach preserves most of the desirable characteristics of the DTL except for the linearity. The loop was named the Time Delay Digital Tanlock Loop (TDTL) [71]. Motivated by the desirable features of the TDTL, this book aims at analyzing the performance of the TDTL and implementing it as a reconfigurable system, which will serve as a testbed for future experimentations. The flexibility offered by reconfigurable computing devices, especially Field Programmable Gate Arrays (FPGAs), is being utilized in most communication systems to implement complex high-speed algorithms [14]. In addition to that, it will facilitate in upgrading and modifying of the TDTL testbed with minimum effort and complexity. FPGAs are on the verge of revolutionizing digital signal processing in the manner digital signal processors did two decades ago. This is expected since FPGAs offer various attractive features such as rapid prototyping, on-the-fly xi xii PREFACE upgradeability, code reuse and reduction in size and power consumption [14, 15]. The Main Contributions The main contribution offered by this book is the introduction of modified architectures of the newly proposed TDTL that overcome the inherent limitations of the loop and undermines the tradeoffs between the locking range and speed of acquisition requirements. The proposed architectures are purely digital, therefore lending themselves to the implementation using reconfigurable modules without a significant increase in the complexity of implementation or design procedures. Another major contribution offered is what may be considered as the first documented implementation of the TDTL using FPGAs. The implemented system will serve as a testbed for the performance enhancement and optimization of the loop. Organization of Book The first chapter provides a general review of phase-lock loops. Chapter two reviews the uniform and non-uniform type Digital Phase Lock Loops (DPLL). Chapter three covers the Time Delay Digital Tanlock Loop (TDTL) and it’s convergence behavior. The following two chapters will focus on the Hilbert Transformer and Time-Delay, and the analysis of the TDTL in noise. The sixth chapter will cover the analysis, modified architectures, and the simulation results of the various TDTL architectures for improved performance. Chapter seven documents the design and implementation of a reconfigurable TDTL system using Field Programmable Gate Arrays, and analyzes the acquired results. Finally, chapter eight covers selected applications of the TDTL. About the Authors Professor Saleh Al-Araji Prof. Al-Araji received the B.Sc., M.Sc., and Ph.D. degrees from the University of Wales Swansea, (UK), all in electrical engineering in 1968, 1969, and 1972 respectively. Since September 2002, Professor Al-Araji was appointed Professor PREFACE xiii and Head of Communications Engineering Department at Etisalat University College (Emirates Telecommunication Cooperation), Sharjah, UAE. Prior to that and for six years he was working at the Transmission Network Systems, Scientific-Atlanta, Atlanta, Georgia, USA as Senior Staff Electrical Engineer. During the academic year 1995/1996, Prof. Al-Araji was visiting professor at the Ohio State University, Columbus, Ohio, USA. He was visiting professor at King’s College, University of London, England, during the summers of 1988 and 1989. Prof. Al-Araji was professor and Department Head at the University of Baghdad, Iraq, and the University of Yarmouk, Jordan. Prof. Al-Araji was awarded the British IERE Clerk Maxwell Premium for a paper published in 1976 and the Scientific-Atlanta award for outstanding achievement in the year 2000. He was an Iraqi National member of URSI Commissions C and D, and the ITU (CCIR Group 8). His research interests include synchronization techniques, communication signal processing, and CATV systems and networks. He has published over 50 papers in international Journals and Conferences and holds 6 US Patents and one International Patent. He is a reviewer to a number of international conferences and journals, and is involved in the organization of a number of international conferences in various capacities. Prof. Al-Araji is a senior member of the IEEE. His e-mail address is: alarajis@euc.ac.ae. Associate Professor Zahir M. Hussain Zahir M. Hussain took the first rank in Iraq in the General Baccalaureate Examinations 1979 with an average of 99%. He received the B.Sc. and M.Sc. degrees in electrical engineering from the University of Baghdad, Iraq, in 1983 and 1989, respectively, and the PhD degree in electrical engineering from Queensland University of Technology (QUT), Brisbane, Australia in 2002. He has over 15 years of experience in teaching and research in various universities. He worked in several projects including the EEG biomedical project at QUT (1999-2001), where he contributed to solving the problem of instantaneous frequency estimation of multicomponent signals. In July 2001 he joined the School of Electrical and Computer Engineering, RMIT University, Melbourne, Australia as a Research Fellow in a 3G commercial project, then Lecturer of Signal Processing and the academic leader of another 3G communications project in November 2001. In March 2002 he was promoted to Senior Lecturer. In November 2005 he was promoted to Associate Professor and received the RMIT Publications Award. Since 2001, he has been the principal supervisor of nine PhD students; six of them have recently completed their studies successfully. Dr. Hussain is the author/co-author for over 120 technical papers on various fields. His current research interests are signal processing, communications, xiv PREFACE and mathematics. His joint work with Queensland University of Technology on single-bit processing has been acknowledged by the Australian Research Council (ARC) through an ARC Discovery Grant. Dr. Hussain is a member of Engineers Australia (previously IEAust), IEE, and a senior member of IEEE. He is a reviewer for the IEEE, Elsevier, and many other Journals on signal processing and communications. His e-mail address is zmhussain@ieee.org. Dr. Mahmoud Al-Qutayri Dr. Mahmoud Al-Qutayri received the B.Eng. degree in electrical engineering from Concordia University, Quebec, Canada, in 1984, the M.Sc. degree in electronic engineering from Manchester University, UK, in 1987, and the Ph.D. degree in electronic engineering from University of Bath, UK, in 1992. He has over fifteen year of experience in teaching and research at various universities. From 1988-1992 he was a research officer at the University of Bath, UK were he worked on testing techniques for analogue and mixed-signal integrated circuits. The project was in collaboration with another two universities and an integrated circuits design company. Dr. Al-Qutayri has also carried out consultancy work for a number of companies including ViewLogic, Lucas, Gent, Philips and others. From 1992-1996 he was a Senior Lecturer at DeMontfort University, Leicester, UK. He subsequently joined Etisalat (Telecommunications) University College in the UAE where he is currently an Associate Professor in the Department of Electronic Engineering. His research interests include testing and design for testability of mixed-signal integrated circuits, and application of reconfigurable computing to signal processing and communication systems, steganography and steganalysis. He published over forty technical papers in international journals and conferences. He is a reviewer to a number of international conferences and journals, and is involved in the organization of a number of international conferences in various capacities. Dr. Al-Qutayri is a Senior Member of the IEEE, member of the IEE and Chartered Engineer (Ceng.) in the UK. His e-mail address is: mqutayri@euc.ae. Acknowledgement The authors would like to express their sincere thanks and appreciation to all persons who helped during the course of writing and producing this book. In particular, we would like to thank our students Nawaf Al-Moosa, Khaled AlZaabi, and Abdullah Al-Zaabi of Etisalat University College. We would also like to extend our thanks to our institutions Etisalat University College, Sharjah, UAE, and RMIT University, Melbourne, Australia for providing the facilities to conduct and support the research work presented in this book. We would also like to thank the reviewers for their suggestions on how to improve this book. The authors are grateful to the IEEE, SPIE, Elsevier and TRLabs for permission to reproduce some of the material in publications [70–73], [82–85], [104–107], 110 and 111. Full details of these publications are given in the bibliography section of this book. The editorial staff of Springer has been highly supportive from the beginning of this project. We thankfully recognize the contributions and encouragement of Mark de Jongh, Senior Publishing Editor/Electrical Engineering, and we greatly appreciate the efforts and effectiveness of Cindy Zitter. Finally, we would like to acknowledge the support and invaluable encouragement of our families throughout the course of writing this book. xv Acronyms ADC CDTL CR DCO DPLL DTL FIR FM FT HT IF i.i.d. PLL MSB PDF PED SNR TDTL var VCO ZC-DPLL VD-TDTL SS-ATDTL EES-ATDTL ATDTL VO-TDTL analog-to-digital converter conventional digital tanlock loop Cramer-Rao (bound) digital controlled oscillator digital phase-locked loop digital tanlock loop finite impulse response frequency modulated signal Fourier transform Hilbert transformer instantaneous frequency independent and identically distributed phase-locked loop most significant bit probability density function phase error detector signal-to-noise ratio time-delay digital tanlock loop variance voltage controlled oscillator zero-crossing digital phase-locked loop variable delay TDTL sample sensing adaptive TDTL early error sensing adaptive TDTL adaptive TDTL variable order TDTL xvii Chapter 1 General Review of Phase-Locked Loops 1.1 Overview of Phase-Locked Synchronization Schemes Although not explicitly stated, the presence of transmitter-receiver synchronization is usually assumed in analyzing the performance of communication systems. For example, in the case of coherent Phase-Shift Keying (PSK) demodulation, the receiver is required to perform maximum-likelihood symbol decisions by comparing the incoming signals with a set of internally-generated reference signals. Generating these reference signals, which are assumed to be identical to those of the signaling alphabet at the transmitter, requires the receiver to be synchronized with the received carrier. This means that the there has to be phase alignment between the incoming carrier and the generated replica at the receiver, and therefore, the incoming carrier and the replica in the receiver would pass through zero simultaneously if there were no information modulated on the incoming carrier. The receiver in this state is said to be in phase-lock with the transmitter, and this condition must be closely approximated if coherently modulated signals are going to be accurately demodulated [6, 80]. Being in phase-lock means that the receiver’s local oscillator is synchronized in both frequency and phase with the received carrier. In addition to that, phase-lock must also be established with the received subcarriers if the information-bearing signal is not modulated directly on the carrier. If the carrier and subcarrier are not kept in phase concurrence by the transmitter, the receiver is required to generate a replica of the subcarrier and control it’s phase separately from that of the carrier replica, and therefore, enabling the receiver to achieve phase-lock on both the carrier and subcarrier [5]. 1 2 CHAPTER 1 The receiver is also required to achieve Symbol Synchronization by tracking the start and end of incoming symbols. These are required to determine the proper intervals for integrating the energy of symbols, and ensure making correct symbol decisions. This is achieved by producing a square wave whose zero transitions are aligned with the incoming signal’s transitions between symbols in order to reach a symbol-lock state. The typically large number of carrier cycles per symbol period necessitate that achieving this level of synchronization with different circuitry than that used for phase synchronization [6, 7]. In the context of communication systems, synchronization is also required in a higher level, namely frame synchronization. Since information is usually organized into blocks, which are coded for forward error control and multiple access purposes, the knowledge of the boundaries between code words must be available at the decoder to ensure correct message or data extraction. In Time Division Multiple Access (TDMA), where multiple users are time-sharing common channels, it is necessary to know where the boundaries between channel users are in order to distribute the information appropriately. Similar to symbol synchronization, frame synchronization is equivalent to being able to generate a square wave at the frame rate, with the zero crossings matching the transitions from one frame to the next [6, 7]. All levels of synchronization, namely phase, symbol and frame, are required in most digital communication systems employing coherent modulation techniques. Conversely, noncoherent-modulation-based system usually make use of symbol and frame synchronization, and another level called frequency synchronization, in which the replica of the carrier generated by the receiver is allowed to have an arbitrary constant phase offset from the received carrier. The choice between coherent and noncoherent modulation methods is governed by the desired performance and complexity of implementation [80]. Although so far it seems that the synchronization is related only to the receiver, there are some communication systems that utilize the transmitter in performing a great deal of the synchronization role by tuning the timing and frequency of its transmissions to match the expectations of the receiver. For example, many terrestrial terminals in satellite communication networks are directing their transmissions toward a single satellite receiver. These transmitters rely on the receiver return paths to determine the accuracy of their synchronization, and therefore, transmitter synchronization often implies twoway communications or a network in order to be successful. Thus, transmitter synchronization is often called network synchronization [6]. GENERAL REVIEW OF PHASE-LOCKED LOOPS 3 1.2 The Synchronization Challenge As mentioned earlier, there is a compromise between the performance and the implementation complexity. Extra levels of synchronization come at the cost of additional hardware or software in the receiver for acquisition and tracking. There are also costs associated with the synchronization overhead, energy and power consumption. However, the outcome of improved performance and versatility still outweighs the aforementioned costs, and communications system designers are always oriented towards designing systems with high degree of synchronization [7]. An example of this design strategy is the case of commercial analogue radio broadcast employing Amplitude Modulation (AM). This system is usually comprised of a central transmitter serving multiple receivers within its coverage area, and involves no synchronization. However, the passband of the receiver must be wide enough to house the modulating (information-bearing) signal, and account for its abrupt shifts in frequency due to the fluctuations in the output frequency of the local oscillator generating the carrier [6]. With this extra requirement, the performance of the receiver will degrade due to the fact that extra noise energy will be passed to the detector, which was not accounted for in the theoretical analysis. Adding the element of synchronization to this receiver will solve the problem, and improve the performance considerably. If the receiver contains extra circuitry for tracking the incoming carrier, the receiving filter will be centered about the carrier even if it fluctuates, and the detected noise energy will be decreased leading to a lower signal-to-noise-ratio (SNR) [6]. Moving to the digital communications domain, the same compromise can be demonstrated in the choice of modulations schemes. For example, noncoherent Binary Frequency Shift-Keying (BFSK) is considered among the simplest digital receivers in terms of implementation, requiring only symbol and frequency synchronization. However, choosing this modulating scheme will result in a 4-dB penalty in terms of bit error performance, i.e. the more complex coherent BPSK receiver can achieve the same bit error probability with 4 dB less SNR [7]. The trade-off between complexity and performance is further extended with the use of error-control coding algorithms. While they offer better performance under stringent operating conditions, they also result in more complex implementations, and require higher levels of synchronization between blocks, messages, and frames [81, 80]. Having discussed the principles and levels of synchronization, and the trade-offs between implementation costs and performance, the next section will explain the basic building block of almost all synchronization systems, namely the Phase-Locked Loop (PLL). 4 v1(t) vd(t) Phase Detector CHAPTER 1 vf (t) Loop Filter v2 (t) Voltgae Controlled Oscillator Figure 1.1: Block Diagram of the PLL. 1.3 Phase-Locked Loops The PLL represents one of the most active topics in signal processing and communication theory. The initial ideas started as early as 1919 in the context of synchronization of oscillators. The theory of phase-locked loop was based on the theory of feedback amplifiers. The PLL contributed significantly to communications and motor servo systems. Due to the rapid development of integrated circuits (IC’s) since the 1970’s, PLLs are widely used in modern signal processing and communication systems, and it is expected that PLL will contribute to improvement in performance and reliability of future communication systems. The applications of PLLs include filtering, frequency synthesis, motorspeed control, frequency modulation, demodulation, signal detection, frequency tracking and many other applications [1, 9, 10, 11]. 1.3.1 Analog Phase-locked Loops A PLL is defined as a circuit that enables a particular system to track another one. More precisely, a PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in the frequency as well as in phase [5]. In the synchronized or the locked state, the phase error between the oscillator’s output and the reference signal is either zero or an arbitrary constant. In the case of a phase error building up, the oscillator is tuned by a control mechanism in order to reduce the phase error to a minimum. In such a control system, the phase of the output signal is actually locked to the phase of the reference input. This is the reason behind calling this specific control system a PhaseLocked Loop [5]. The basic functional components of a PLL are: A voltage controlled oscillator (VCO), A phase detector (PD), and A loop filter (LF). GENERAL REVIEW OF PHASE-LOCKED LOOPS 5 The signals of interest in the PLL block diagram shown in Figure 1.1 are de- fined as follows: The reference (or input signal) v1(t) with an angular frequency ω1, The output signal v2(t) of the VCO with an angular frequency ω2, The output signal vd(t) of the phase detector, The output signal vf (t) of the loop filter, and The phase error θe, defined as the phase difference between signals v1(t) and v2(t). The VCO oscillates at an angular frequency ω2 which is determined by the output signal vf of the loop filter. The angular frequency ω2 is given by ω2(t) = ωo + Kovf (t) (1.1) Where ωo is the centre frequency of the VCO and K o is the VCO gain. The PD compares the phase of the output signal with the phase of the reference signal and generates an output signal vd that is approximately proportional to the phase error θe, the former signal is given by: vd(t) = Kdθe, θe → 0 (1.2) where Kd represents the gain of the PD. The output signal vd(t) consists of a dc component and a superimposed ac component. Since the latter is undesired, it is cancelled by the loop filter. Assuming the angular frequency of the input signal v1(t) is equal to the centre frequency ωo, the VCO then operates at its centre frequency ωo, and the phase error is zero, indicating the output signal of the loop filter vf is also zero. If the phase error θe was not initially zero, the PD would develop a nonzero output signal vd. After some delay the loop filter would also produce a finite signal vf , which will cause the VCO to change its operating frequency in such a way that the phase error finally vanishes. Now, assume that the frequency of the input signal is changed suddenly at a time instant to by the amount of ∆ω. This will cause the phase of the input signal to lead the phase of the output signal, and a phase error will build up and increase with time. The PD develops a time-increasing signal vd(t), which will cause vf (t) to rise after some delay introduced by the loop filter. This causes the VCO to increase its frequency in order to minimize the phase error, and after some settling time the VCO will oscillate at a frequency that is exactly the frequency of the input signal. Depending on the type of the loop filter used, the final phase error will have been reduced to zero or to a finite value. The VCO now operates at a frequency that is greater than its center frequency ωo by an amount ∆ω, this will force the signal vf (t) to settle at a final value of vf = ∆ω/Ko. If the centre frequency of the input signal is frequency modulated by an arbitrary low-frequency signal, then the output signal of the loop filter is the demodulated signal. The PLL can consequently be used as an 6 Reference Signal VCO Signal Vd Vd-max - − /2 /2 CHAPTER 1 Figure 1.2: Classical Mixing Phase Detector. FM demodulator, or in more general terms, it can be used as a demodulator of any scheme that stores the information in the frequency of the phase of the modulated carrier [5]. One of the most interesting capabilities of the PLL is its ability to suppress noise superimposed on its input signal. Assuming that the input signal of the PLL is degraded by noise, the PD will attempt to measure the phase error between the input and output signal. The noise at the input causes the zero crossings of the input signal v1(t) to be advanced or delayed in a stochastic manner, causing the PD output signal vd(t) to jitter around an average value. If the cut-off frequency of the loop filter is low enough so that almost no noise will be noticeable in the signal vf (t) and the VCO will operate in such a way that the phase of the signal v2(t) is equal to the average phase of the input signal v1(t), it can be stated that the PLL is able to detect a signal that is badly degraded by noise. These simplified considerations show that the PLL is a typical servo system that controls the phase of the output signal v2(t) [1, 5]. 1.3.2 PLL Basic Components The Phase Detector As previously mentioned the function of the phase detector block is to compare the phases of the input and output signals and generate an error signal proportional to the phase deviation between them. The most prevalent device capable of achieving this function is the mixer, which generates the sums and differences of the frequencies at its input terminals. The mixing phase detector shown in Figure 1.2 will be discussed later in Section 1.3.3. This PD has a superior noise performance to all the other detectors, GENERAL REVIEW OF PHASE-LOCKED LOOPS 7 due to the fact that it operates on the entire amplitude of the input and VCO signals, rather than quantizing them to 1 bit [12]. Balanced mixers are best suited for PLL applications in the microwave frequency range as well as in low noise frequency synthesizers. However, this results in a loop whose gain is dependent upon the signal amplitude. Furthermore, nonidealities in the circuit implementation of the mixer result in nonlinear responses. When noise is not an issue, it is advantageous to move to a detector that has immunity to these effects [1, 2, 3, 4]. The Voltage-Controlled Oscillator The actual clock generated by a PLL comes from the voltage-controlled oscillator (VCO), which generates a periodic oscillation. The frequency of this oscillation can be controlled by modulating some control voltage. In a PLL, the control voltage corresponds to some filtered form of the phase error. In response to this, the VCO adjusts its frequency. As the VCO frequency is slewed by the control voltage, the phase error is driven towards zero. This frequency adjustment to achieve phase lock results in the model of a VCO as an integrator [1, 5]. VCOs are generally of the form of a ring oscillator, relaxation oscillator or a resonant oscillator. The ring oscillator takes the form of an odd number of inverters connected in a feedback loop. The relaxation oscillator uses a Schmitttrigger to generate a stable square wave [2]. The latter puts a resonant circuit in the positive feedback path of a voltage to current amplifier as shown in Figure 1.3. The resonant circuit in the positive feedback path has poles close to the jω axis. Consider the bandpass filter: F (s) = 2ζ ωo s s2 + 2ζωos + ωo2 and G(s) = K < 1. Then (1.3) V CO(s) = G(s) = K s2 + 2ζωos + ωo2 1 − G(s)F (s) s2 + 2ζ1ωos + ωo2 (1.4) where ζ1 = (1 − K)ζ. The lowering of the damping ratio is called “Q amplification” (Q = 1/2ζ) and moves the poles even closer to the jω axis. The frequency is controlled by altering the capacitance of the resonator by using a varactor diode as a capacitor. A simple circuit diagram for a resonant circuit VCO is shown in Figure 1.4, where the frequency is controlled by adjusting the reverse bias of the varactor diode C1 [1]. Other forms of VCOs, such as crystal 8 CHAPTER 1 R G(s) R L CL C1 C2 F(s) (a) (b) (c) Figure 1.3: (a) Block Diagram of an Oscillator implemented as a positive feedback loop between a Voltage to current amplifier through a resonant circuit. (b) Resonant LC Tank (c) Resonant p network. oscillators and YIG oscillators essentially run on the same principle, but modify the resonant circuit [1, 3, 4]. For the all digital and software PLLs, the VCO is replaced by a digitally or numerically controlled oscillator (DCO/NCO). In this case, the input voltage is replaced by some digital value, and the output is a digital oscillating waveform [5, 7]. The Loop Filter As noted earlier, there is conceptually always a loop filter. Typical analysis ignores the high frequency low pass filter and other dynamics that do not affect the behaviour of the loop at the time constants of the phase. Since PLLs are mostly second order and as the VCO is modelled as an integrator, loop filters are of the lead lag type. More specifically, the loop filter contains an integrator which is able to track a phase ramp, and this corresponds to tracking a step in frequency [4, 7]. For a double integrator system, the loop filter needs a minimum phase zero to obtain stability. This is true whether the filter is implemented as an analogue or digital filter. Higher order loops can be obtained by adding extra pole/zero pairs to the filter [2]. The analogue circuits in Figure 1.5 show typical implementations active and passive loop filters [1]. The transfer function of the active section shown in Figure 1.5-b filter is fairly general and given by: Vo = sR2(C2 + C3) + 1 Va − Vb sR1C2(sR2C3 + 1) (1.5) GENERAL REVIEW OF PHASE-LOCKED LOOPS 9 Vc R L C1 C2 C3 Figure 1.4: A VCO implemented through a PI network. C3 C2 R R1 R2 C Va − Vo Vb + R1 R R2 C3 C2 Figure 1.5: Typical Analogue Filter Sections (a) Passive Lead Lag (b) Active Lead Lag. 10 Asin(ωit+θi) LoopFilter CHAPTER 1 Reference Signal Cos(ωot+θo) Signal Phase-Locked to Reference Voltage Controlled Oscillator VCO Control Voltage Figure 1.6: Classical Mixing PLL. 1.3.3 PLL analysis Figure 1.6 shows the classical mixing PLL, which is mostly used to describe and analyze the PLL theoretically. However, practical loops usually resemble Figure 1.7, in which a differential amplifier, acting as a high frequency low pass filter, is used to attenuate the double frequency term and a bandpass filter is used to limit the bandwidth of input signals to the loop. A general sinusoidal signal at the reference input of a PLL as shown in Figure 1.7 can be written as: vi = A sin(ωit + θi) (1.6) The output signal from the Voltage Controlled Oscillator (VCO) into the mixer is given by vo = VCOout(t) = cos(ωot + θo) (1.7) The output of the mixer in Figure 1.7 is then given by vd = Mixerout(t) = AKm sin(ωit + θi) cos(ωot + θo) (1.8) where Km is the gain of the mixer. Typically, analysis of such a PLL is done by taking several simplifying steps. Using the familiar trigonometric identity in terms of the PLL 2 sin(ωit + θi) cos(ωot + θo) (1.9) sin[(ωi + ωo)t + θi + θo] + sin[(ωi − ωo)t + θi − θo] (1.10) GENERAL REVIEW OF PHASE-LOCKED LOOPS 11 Vi Reference Signal Bandpass Filter Differential Amplifier LPF Loop Filter Signal Phase-Locked to Reference Vo Voltage Controlled Oscillator VCO Control Voltage Figure 1.7: Practical PLL block diagram. and then making the two fundamental assumptions below will lead to the commonly used model of the analogue PLL. Let θd = θi − θo. Then these assumptions are 1. The first term in (1.9) is attenuated by the high frequency low pass filter in Figure 1.7 and by the low pass nature of the PLL itself. 2. ωi ≈ ωo, so that the difference can be incorporated into θd. This means that the VCO can be modelled as an integrator. The problem is that this is still a nonlinear system, and as such is in general difficult to analyze. The typical methods of analysis include: 1) Linearization: For θd small and slowly varying we have sin(θd) ≈ θd, cos θd ≈ 1, and θd2 ≈ 0. While this is useful for studying loops that are near lock, it does not help for analyzing the loop when θd is large. 2) Phase plane portraits: This method is a classical graphical method of analyzing the behaviour of low order nonlinear systems about a singular point. The disadvantage is that phase plane portraits can only completely describe first and second order systems. The linearized model is shown in Figure 1.8. This is what is used for most analysis methods and measurements of PLLs. Changing the phase detector and 12 Σ q i qd Kdsin(...) CHAPTER 1 F(s) qo Ko S Figure 1.8: Linearized Model of the PLL. VCO can result in a system for which this model is very accurate. Although this linear model contains useful information about the phase behaviour of the PLL, it has some very important omissions that show up in the simulating or constructing the classical PLL ,and these are [1, 5]: 1) As seen in (1.8), the amplitude of the phase error is dependent upon A, the input signal amplitude. The linearized model has a loop gain that is dependent upon the loop components. Thus, in practical loop design, the input amplitude must either be regulated or its effects on the loop must be anticipated. 2) The equations of a PLL are stiff, that is, the loop has a component at baseband and one at 2ωo. The simulations of that sample fast enough to characterize the latter are often far too slow (due to the huge number of sample points) to effectively characterize the former. The PLL model in Figure 1.8 is a closed-loop feedback system. The complimentary sensitivity transfer function from reference phase input to VCO phase output, T (s), can be obtained as T (s) = θo(s) = KdKvF (s) θi(s) s + KdKvF (s) (1.11) Similarly, the sensitivity transfer function from the reference phase input to the phase error, S(s), is S(s) = θd(s) = s θi(s) s + KdKvF (s) (1.12) GENERAL REVIEW OF PHASE-LOCKED LOOPS 13 Among the basic properties of interest in this transfer function are the order and stability of the loop. The order of the PLL system is determined by the order of the denominator of (1.10). The stability of the system can be determined by a variety of methods including root locus, Bode plots, Nyquist plots, and Nichols charts [1]. The Hold Range The hold range, ∆ωH, is defined as the frequency range over which the PLL is able to statically maintain phase tracking. It is determined by calculating the frequency offset at the reference input that causes the phase error to be beyond the range of linear analysis. Since loops will be permanently out of lock if the frequency offset at the input is greater than the hold range, this quantity has negligible effect practically, and it can be calculated for a classical PLL (sinusoidal phase detector) as [5, 11]: ∆ωH = KoKdF (0). (1.13) The Lock Range The lock range, ∆ωL, is defined as the frequency range within which the PLL locks within one single-beat note between the reference frequency and output frequency [1]. The lock range must be calculated from a nonlinear equation, but there are several useful approximations that are made. In particular, if the relative order of numerator and denominator of the PLL are 1, then the loop can be said to behave like a first order loop at higher frequencies, and thus the lock range can be estimated as [11]: ∆ωL ≈ ±KoKdF (∞) (1.14) 1.4 Conclusions In this chapter we have presented a general review of phase lock loops (PLL) that included the importance of synchronization in communication, control and measurement applications. The basic components of an analog PLL were described and a complete linear analysis of the loop was given. The main parameters that describe the loop performance were also given. Chapter 2 Digital Phase Lock Loops 2.1 Introduction The analog PLLs (APLLs) are still widely used, but digital PLLs (DPLLs) are attracting more attention for the significant advantages of digital systems over their analog counterparts. These advantages include superiority in performance, speed, reliability, and reduction in size and cost. DPLLs alleviated many problems associated with APLLs. The following is a brief comparison: 1. APLLs suffer from the sensitivity of the voltage-controlled oscillator (which decides the center frequency) to temperature and power supply variations, hence the need for initial calibration and periodic adjustments. DPLLs do not suffer from such a problem [12, 17, 68]. 2. The most familiar error detectors used in APLLs utilize analog multipliers (balanced modulators) which are sensitive to d.c. drifts [10, 18], a problem that does not exist in DPLLs. 3. DPLLs can operate at very low frequencies that create problems in APLLs [17, 18]. These problems are related to the operation of the analog low-pass filter in extracting the lower frequency component [11, 18],as it needs larger time for better frequency resolution, and this will reduce the locking speed. 4. Self-acquisition of APLLs is often slow and unreliable, while DPLLs, a basic block diagram is shown in Figure 2.1, have faster locking speeds [17]. This is due to the basic operation of the analog low-pass filter and the analog multiplier in the phase detector (PD). The low pass filter cannot extract the lower frequency within few input cycles since the narrow time windowing will destroy the information in the frequency domain (due to the time frequency resolution tradeoff). Same reasoning applies for the balanced modulator in the PD. In contrast, a digital filter operation is based on a difference equation with convergence decided by the coefficients of the equation, and the PD operation 15 16 CHAPTER 2 is related to the instant of sampling rather than to frequency comparison. This is why a DPLL can achieve locking within few cycles (see Chapter 3). Hence DPLLs are tackled with concentration on sinusoidal DPLLs. The development of DPLLs started in the 1970’s. The analysis of the positive-going zero-crossing sinusoidal DPLL was presented in 1980 using fixed point theorems [50, 51]. The second significant step in sinusoidal DPLLs was the digital tanlock loop (DTL) in 1982 [13] that is based on the arctan phase detector which gave linear system equation. Since 1982 many efforts were made to improve the performance of DTL [52, 53, 54, 59]. In this book we emphasize a new DPLL that combines the two major approaches in the field: the approach of sinusoidal DPLL with fixed point analysis and the approach of DTL with the arctan phase detector. The main advantages of this DPLL, called the time delay digital tanlock loop (TDTL), is the reduced complexity of the loop, wider lock range of the first-order loop and faster convergence speed under certain choice of the TDTL parameters. Input Signal Phase Error Detector Phase Error Digital Filter DCO Pulses Digital Controlled Oscillator (DCO) Output Pulses Figure 2.1: Basic block diagram of the digital phase locked loop. 2.2 Classification of DPLLs Digital phase-locked loops can be classified into two major categories depending on the type of sampling process [12] 1. Uniform sampling DPLLs 2. Non-uniform sampling DPLLs The DPLLs can be also classified according to the mechanization of the phase detector into five types as follows [12] 1. The flip-flop DPLL (FF-DPLL) DIGITAL PHASE LOCK LOOPS 17 2. The Nyquist-rate DPLL (NR-DPLL) 3. The lead-lag DPLL (LL-DPLL), a.k.a binary-quantized DPLL (BQ-DPLL) 4. Exclusive-OR DPLL (XOR-DPLL) 5. Zero-crossing DPLL (ZC-DPLL) Types 2 above belongs to uniform sampling, while the others belong to nonuniform sampling. A brief discussion of each type is given below. Flip-flop DPLL This kind of DPLLs was proposed in the literature by a number of authors [19], [20], [21] and [22]. In this type the phase detector is realized by a set-clear flip-flop and a counter as shown in Figure 2.2. The sinusoidal input signal is converted into a square wave through an operational amplifier acting as a comparator. The output “Q” of the flip-flop is set to logic “1” on the positive-going edge of the comparator, and to logic “0” on the positive-going edge of the digital controlled oscillator (DCO). Hence the duration when Q is at level “1” will be proportional to phase error between the input signal and the DCO. This error is used to gate the counter clock which has a frequency of 2M fo where fo is the center frequency of the DPLL and 2M is the number of quantization levels of the phase error over period of 2π. The counter is zeroed and starts counting on the positive-going edge of the flip-flop waveform. The content of the counter, No, which is proportional to the phase error, is applied to the N-bit first-order digital filter which consists of proportional and accumulation paths. The output of the digital filter K controls the period of the DCO which consists basically of a programmable divide-by-K counter. It is the phase of the input signal that undergoes non-uniform sampling here rather than the amplitude. Nyquist-rate DPLL This DPLL was proposed in [23, 24] and subsequently developed by the works in [25], [26] and [27]. Nyquist sampling on the phase of the input signal rather than the amplitude was reported in [28]. In this DPLL the sinusoidal input signal is sampled uniformly at the Nyquist rate fs and converted to N -bit digital signal by an analog-to-digital converter (ADC), then it is multiplied digitally by the DCO output v(k) to form an error signal. This error signal is applied to 18 CHAPTER 2 Sinusoidal + Input Signal - Clear x(t) Set Q Clear Q- DCO Pulses Counter No Digital Filter Clock M f=2 f o K DCO x(t) DCO Pulses Q K t Figure 2.2: The flip-flop DPLL. Above: A block diagram. Below: Waveforms as a function of time. N -bit digital filter whose output controls the period of the DCO as shown in Figure 2.3. The DCO used in NR-DPLL is of algorithmic type [26]. It is constructed by utilizing the basic idea of the analog VCO. The analog VCO output can be given as in [29] t v(t) = B cos ωot + Go y(τ )dτ −∞ (2.1) DIGITAL PHASE LOCK LOOPS 19 Sinusoidal Input Signal x(t) x(k) ADC e(k) Digital Filter fs v(k) Algorithmic y(k) DCO Go y(k-1) Input 2 π fo /fs q(k-1) q(k) Unit Delay z -1 v(k) sq[.] Output Figure 2.3: The Nyquist-rate DPLL. Above: A block diagram. Below: The algorithmic DCO. where ωo = center frequency of the VCO Go = sensitivity of the VCO (rad/sec.volt) y(t) = input voltage In the discrete time domain, (2.1) can be expressed as follows k−1 v(kTs) = B cos 2πkfo/fs + Go y(n) n=0 (2.2) where Ts = 1/fs is the sampling period and y(n) = y(nTs). The sinusoidal function v(kTs) is converted to a square wave v(k) as follows k−1 v(k) = sq 2πkfo/fs + Go y(n) n=0 (2.3) 20 CHAPTER 2 where sq(x) = 1 0 ≤ x < π = −1 π ≤ x < 2π sq(x) = sq(x + 2π) The direct implementation of (2.2) above is rather difficult due to the timevarying term 2πkfo/fs. However, (2.2) can be written in the following form k−1 v(k) = sq {2πkfo/fs + y(n)} = sq[q(k)] n=0 (2.4) where k−1 q(k) = {2πkfo/fs + y(n)} n=0 It can be shown that (2.5) q(k) = q(k − 1) + 2πfo/fs + Goy(k − 1) Figure 2.3 shows the algorithmic DCO block diagram based on (2.3). (2.6) Lead-Lag DPLL This type of DPLLs has been developed by the work in [30, 31] and extended in [32] to include a second-order sequential filter with memory. The LL-DPLL is characterized by the binary output of the phase detector that indicates whether the DCO waveform leads or lags the input signal. Due to this quantization it is often named “binary quantized DPLL”. The input sinusoidal signal should be converted to a square wave by a comparator. On the occurrence of a DCO pulse, either “lead” or “lag” terminal of the phase detector will give a pulse depending on the state of the input signal being “high” or “low”, respectively, as shown in Figure 2.4. These pulses are applied to a special type of digital filters known as “sequential filter.” The sequential filter deals with the input “lead” and “lag” pulses statistically; it observes them for a variable duration of time and gives a decision when a reliable limit is reached. Figure 2.4 shows that the sequential filter is composed of an up-down counter whose length is 2N + 1. A pulse at the “lead” terminal causes the content of the counter to increase by 1, while the “lag” pulse behaves conversely. When the content of the counter reaches 2N or zero, the corresponding “Retard” (or: “Advance”) output gives a pulse that resets the counter to “N ” and triggers the phase controller. A “Retard” pulse causes the phase controller to delete one pulse DIGITAL PHASE LOCK LOOPS Sinusoidal + Input Signal - a Phase d Detector c 21 Sequential Loop Filter (2N+1 Up-Down Counter) Up Down 0 2N Advance Reset to N Retard Output Signal e f b . . L Phase Controller Counter g Clock a b c d e f g Figure 2.4: The lead-lag DPLL with associated waveforms. from the clock pulse train that is applied to the divide-by-L counter, forcing the DCO phase to retard by 2π/L, where L is the number of quantization levels of the period 2π. An “Advance pulse does the contrary. When “lead” and “lag” pulses are equally probable, a case that indicates locking, the counter cycle has maximum duration. Other types of sequential filters exist like the N -before-M filter [12] and the variable reset random walk filter [32]. 22 CHAPTER 2 Exclusive-OR DPLL Greer has utilized an exclusive-OR gate as a phase detector [17]. He used a K-counter as a digital filter and an increment-decrement (I/D) counter with a divide-by-N counter as a DCO. Figure 2.5 shows a block diagram of the Exclusive-OR DPLL. The phase error detector (PED) compares the phase of the input signal, φin, with that of the loop output, φout, and gives an error signal φd defined as follows φd = Ko φe (2.7) where Ko is the gain of the PED and φe = φin − φout. The output of the PED can also be expressed as follows φd = (%H − %L)/100(cycles) (2.8) where %H and %L represent percentage “high” and “low” logic levels, respectively, during one cycle. Hence φd (in cycles) varies between +1 and -1. When φe = 1/4 cycle (π/2 rad) then %H = %L as shown in Figure 2.5-b, hence φd = 0 ≡ 2π (mod 2π) = 1 cycle, therefore Ko = 4. The output of the phase detector controls the operation of the K-counter which consists of two divide-by-K counters, an up-counter and a down-counter, both triggered by a clock of rate M fo, where fo is the center frequency and M is an integer. The output “C” of this counter, which is connected to the increment input (INR) of the I/D counter, generates a pulse when the K-counter ends an “up” cycle, while the “borrow” output B which is connected to the decrement input (DCR) generates a pulse on the end of a “down” cycle. A pulse applied to the “INR” input adds 1/2 cycle to the I/D output, while a pulse on the “DCR” input deletes 1/2 cycle. The I/D counter clock runs at a frequency of 2N fo, where N is the modulus of the divide-by-N counter that follows the I/D counter. The I/D counter is merely a divide-by-2 counter if no “INR” or “DCR” pulses are applied, hence its output frequency can be given by F = N fo + 1/2[KoφeM fo/K] (Hz) = N fo + 2φeM fo/K (2.9) The factor 1/2 above came from the fact that the I/D counter adds or deletes half a cycle when “INR” or “DCR” pulses are applied, respectively. The output frequency can be expressed as fout = fo + 2φeM fo/(KN ) (Hz) (2.10) DIGITAL PHASE LOCK LOOPS 23 Since φd varies between +1 and −1, φe varies between +1/4 and −1/4 cycles, hence lock range can be derived as follows ∆ = |fin − fo|max = |fout − fo|max = M fo/(2KN ) lock range = 2∆ = M fo/(KN ) (2.11) There exists a phase error between the input and the output signals even at locking, i.e. when fout = fin, which is given by [17] φe = KN (fin − fo)/(2M fo) (2.12) Figure 2.5-d clarifies this relationship. 24 fin (φ in) fout (φout) CHAPTER 2 f1 = M fo Vd D/-U C K-Counter B MSB . . N Counter [a] F DCR INR I/D Counter (divide-by-2) f2 = 2 N fo (b) f in f out Vd fin = fo φe = 1/4 φd = 1 +∆ fin (c) f out Vd φe (cycles) 1/4 (d) -1/4 fo - ∆ fin = fo + ∆ /2 φe = 1/8 φd = 1/2 fo fo+ ∆ fin Figure 2.5: The Exclusive-OR DPLL with associated waveforms. (a) Block diagram. (b) Waveforms at fin = fo + ∆. (c) Waveforms at fin = fo + ∆/2. (d) Transfer function at lock. DIGITAL PHASE LOCK LOOPS 25 Zero-Crossing DPLL This type of DPLLs accepts sinusoidal signals and samples the input signal at or near zero crossings, hence the name zero-crossing DPLL (ZC-DPLL). There are two variations of ZC-DPLLs. The first, named ZC1 − DPLL, samples only on the positive-going zero crossings, while the other type, ZC2 − DPLL, samples on both positive and negative-going zero crossings. The first type is the most important type of DPLLs since it is the simplest to implement, the easiest to model, and its operation and performance are indicative of the general behavior of any DPLL [12]. Although ZC2 − DPLL locks faster, it has additional design complications over ZC1 − DPLL [12, 111], hence the latter dominated. ZC2 − DPLL has been proposed first in [33] and developed later as discussed in [34] and [35]. ZC1 − DPLL has been developed by the work in [36, 37, 38, 39, 40, 41, 42]. The systematic statistical analysis of ZC1 − DPLL is provided in [43] where it presents a numerical solution to the Chapman-Kolmogorov equation. Other studies on this have also been presented in the literature [44, 45, 46, 47, 48, 49, 50, 51]. In 1982 a new classification was imposed on DPLLs by the advent of the digital tanlock loop (DTL) [13]. ZC1 − DPLL and ZC2 − DPLL were given the name “sinusoidal ZC-DPLL” or simply “sinusoidal DPLL” [13], based on the phase detection technique. DTL is a new type of ZC1 − DPLLs that has distinguished phase detection mechanism and significant advantages over other types of DPLLs. Many efforts have been made to improve the characteristics of DTL and its application in communication systems [52, 53, 59]. A brief description of the sinusoidal ZC1 − DPLL and DTL is given below. Sinusoidal ZC1 − DPLL Figure 2.6 shows the block diagram of sinusoidal ZC1 − DPLL with the associated waveforms. Here the function of phase detection is merged with that of non-uniform sampling since the instant of sampling determines the phase error [38, 50]. The main parts of this DPLL are explained below. The N-bit Digital Filter This filter modifies the analog-to-digital converter (ADC) samples, which are applied to the DCO, in such a way that leads the phase error to reach a constant value and hence locking occurs. The digital filter consists of proportional and accumulation paths. The order of the digital filter represents the order of its difference equation, hence the nth-order digital filter can be described in the z-domain by the 26 Sinusoidal Input Signal x(t) Sampler ADC v(t) CHAPTER 2 x(k) N-bit y(k) Digital Filter DCO t(0) x(t) ° ← T(1) t(1) t(2) → °← T(2) →° x(k) x(0) x(1) x(2) v(t) time Figure 2.6: The Sinusoidal ZC1 − DPLL with associated waveforms. following transfer function [39] D(z) = κ (z + c1)(z + c2)...(z + cn) (z + p1)(z + p2)...(z + pn) (2.13) Since the present value of the phase error depends on the previous value, the order of the loop equals the order of the digital filter plus one. Hence in the firstorder loop the digital filter is just a proportional path, while the second-order loop utilizes a first-order digital filter with the following transfer function D(z) = κ(z + c1)/(z + p1) (2.14) For the second-order sinusoidal ZC1 − DPLL to lock on zero phase error, p1 must equal −1 [39], hence (2.14) may be written in a more convenient form as follows DIGITAL PHASE LOCK LOOPS 27 D(z) = G1 + G2/(1 − z−1) which gives in the time domain the following input-output relation (2.15) n y(n) = G1 x(n) + G2 x(k) k=0 (2.16) where x(k) and y(k) are the discrete input and output signals, respectively. The Digital Controlled Oscillator (DCO) The digital controlled oscillator consists of a programmable counter, a binary subtracter, and zero detector. Figure 2.7 shows a block diagram of DCO with associated waveforms. Subtraction is performed using a 2’s complementer and a full adder. The counter content is decremented by one on the occurrence of each clock pulse. When it reaches zero, the counter generates a pulse at the output. This pulse is used to load the counter with the binary number M − K where M is a constant number and K is the input number. The number M decides the DCO free-running frequency fo when the input number K is zero as follows fo = fc/M (2.17) where fc is the frequency of the counter clock. The period between the (k − 1)th and the kth pulses is given by where Tc = 1/fc. The Phase Equation T (k) = (M − K) Tc (2.18) The input signal x(t) is assumed to be in the form x(t) = A sin{ωot + θ(t)} + n(t) (2.19) where A is the signal amplitude, ωo = 2πfo, θ(t) is the information bearing phase, and n(t) is Gaussian additive noise. For a frequency step input θ(t) is given by θ(t) = (ω − ωo)t + θo (2.20) where θo is a phase constant and ω is the input frequency. Under such condition the (nonlinear) difference equations representing the first-order loop (with 28 CHAPTER 2 M fc 2’s Complementer Full Adder Programmable Counter M-K Zero Detector Load M-K K (Input Number) DCO Output Counter Content M-K 2 M-K 3 M M-K 1 t DCO Pulses Tc T(1) T(2) t Figure 2.7: The digital controlled oscillator with associated waveforms. D(z) = G1) and the second-order loop (with D(z) = G1 + G2z/(z − 1)) can be respectively given by [50, 51] φ(k + 1) = φ(k) − K1 sin{φ(k)} − K2n(k) + Λo (2.21) and φ(k + 1) = 2φ(k) − φ(k − 1) + K1 sin{φ(k)} −K2n(k) − r[K1 sin{φ(k)} + K2n(k)] (2.22) where φ(k) is the phase error at the instant k, K1 = ωG1 A, K2 = ωG1, Λo = 2π(ω − ωo)/ωo, and r = 1 + G2/G1. From these equations it can be shown that the noise-free steady-state phase error of the first-order loop is given by φss = sin−1(Λo/K1) (2.23) while the second-order loop locks on zero phase error. DIGITAL PHASE LOCK LOOPS Sinusoidal Input Signal Sampler I Hilbert Transformer (90 o ) DCO I Digital Filter 29 tan-1 (I / Q) Q Sampler II Figure 2.8: Structure of the digital tanlock loop. Although sinusoidal DPLL has many advantages over other types of DPLLs [12], it has the shortcomings of sensitivity to the variations in the input signal power and rather limited lock range. The DTL explained below has solved these problems. The Digital Tanlock Loop (DTL) This DPLL was introduced in [13]. Figure 2.8 shows a block diagram of DTL. It is composed of 90o phase shifter, two samplers, a phase error detector, a digital loop filter, and a digital controlled oscillator (DCO). Sampler I takes a sample I of the incoming signal, and sampler II takes a sample Q of the phase-shifted version of the incoming signal simultaneously. The phase error, which is determined by the sampling instant, is extracted by the tan−1 function at the phase error detector. This phase error is modified by the digital filter whose output controls the period of the digital controlled oscillator (DCO). This technique in the phase detection along with the use of a Hilbert transformer led to a linear phase difference equation. The noise-free difference equations of the first and second-order DTLs are given respectively by [13] φ(k + 1) = (1 − K1)φ(k) + Λo (2.24) and φ(k + 2) = (2 − rK1)φ(k + 1) + (K1 − 1)φ(k) (2.25) where all symbols are defined in the paragraph of sinusoidal ZC1 − DPLL. 30 CHAPTER 2 The steady-state phase error of the first-order DTL is φss = Λo/K1 (2.26) and the second-order DTL locks on zero phase error. Due to dividing the input signal by its phase-shifted version at the phase error detector, DTL noise-free performance is independent of the signal amplitude A, hence under noise-free condition DTL is insensitive to the variations in signal power. The first-order DTL has wider lock range than the sinusoidal DPLL. The analysis of sinusoidal DPLL is nonlinear and based on “fixed point theorems” [50, 51], while the analysis of the DTL is linear. Our work in this book combines the two major approaches in the field: the approach of sinusoidal DPLL built on fixed point analysis and the approach of tanlock based on the arctan phase detection. Our main objective is to reduce the complicated structure of DTL while preserving its advantages. 2.3 Conclusions In this chapter we have presented a survey of digital phase-locked loops (DPLLs). The survey included the major classification of DPLLs according to the sampling scheme where they are classified as uniform and non-uniform sampling DPLLs. Further classification according to the phase detection scheme was also considered. The main parts in each class are clarified. It has been shown that the most important kind of DPLLs is the nonuniform sampling sinusoidal zero-crossing DPLL (ZC-DPLL). Hence we will concentrate on this kind of DPLLs in this book. Developments in this respect are presented. Two major approaches exist in this field: the original approach of sinusoidal DPLL built on fixed point analysis and the approach of tanlock phase detection. In this book we will present a combination of the above two approaches that will give many advantages over the existing types of DPLLs. Chapter 3 The Time-Delay Digital Tanlock Loops (TDTLs) 3.1 Introduction Phase-locked loops play an important role in communication systems since they contribute significantly to a variety of applications like filtering, frequency synthesis, frequency modulation, demodulation, signal detection, motor-speed control and many other applications [11]. Digital phase-locked loops (DPLLs) were introduced to alleviate some of the problems associated with the analog loops like sensitivity to d.c. drifts and the need for initial calibration and periodic adjustments. Nonuniform sampling DPLLs are the most important digital phase-locked loops because they are simple to implement and easy to model [12]. Digital tanlock loop (DTL), proposed in [13], has introduced several significant advantages over other nonuniform sampling digital phase locked loops. It allows a wider locking range of the first-order loop and a reduced sensitivity of the locking conditions to the variation of the input signal power [13]. DTL proved to be efficient for many applications in digital communications (see, for example, [53, 54]). The constant 90o phase-shifter is a vital part of this conventional DTL (CDTL) and all of its modifications (see, for instance, [56, 57]). In fact, a digital Hilbert transformer introduces approximations and imposes limitations on the range of input frequencies, especially when implemented on a microprocessor [60, 61]. In this chapter, a constant time-delay unit is used to produce a phaseshifted version of the incoming signal. This method reduces the complexity of the phase-shifter and avoids the limitations and other problems that accompany the 90o phase-shifter. Except for the linearity of the characteristic function of the phase error detector, the main advantages of CDTL are maintained by TDTL despite its 31 32 CHAPTER 3 reduced structure. First, under noise-free conditions its performance is not affected by the variation of signal power. Second, the first-order loop can have wider lock range than other sinusoidal DPLLs (including CDTL) if the circuit parameters are properly chosen. The region of locking independently of initial phase errors in the first-order loop can be made larger than that of the firstorder CDTL since the conditions of independent locking are less stringent in TDTL as a result of non-linearity. Although the lock range of the second-order TDTL is reduced as compared to that of CDTL, this reduction is not a severe short-coming since it mainly concerns high values of the loop gain K1 which are not desired [13]. In fact, any range of input frequencies can be handled after a suitable arrangement of the circuit parameters. In the following section, a general description of TDTL is given. In Section 3.3, the system is analyzed and locking conditions are derived for the first- and second-order TDTLs. 3.2 Structure and System Equation 3.2.1 Structure of the TDTL The structure of TDTL is similar to that of CDTL in Figure 2.8 except for the technique of phase-shifting. A block diagram of TDTL is shown in Figure 3.1. It is composed of a time-delay unit (τ ), two samplers, a phase error detector, a digital loop filter, and a digital controlled oscillator (digital clock). Sampler I takes a sample x(k) of the time-delayed version of the incoming signal, and sampler II takes a sample y(k) of the incoming signal simultaneously. The phase detector takes the function Tan−1[x(k)/y(k)] at every sampling instant, where Tan−1 is the four-quadrant arctan function. The output of the phase error detector, e(k), is a function of the phase error between the incoming signal and the digital clock at the kth sampling instant in modulo (2π) sense. The digital filter is used to modify the output of the phase error detector e(k) and provide a control signal to the digital clock to decide the next sampling instant at the two samplers. Hence the sampling is nonuniform, and the loop arranges its frequency at the digital clock to be, in the limit, equal to the input frequency with a minimum phase difference. 3.2.2 System Equation Under noise-free conditions, the loop accepts a sinusoidal input signal y(t) having a radian frequency ω with a frequency offset ∆ω(= ω −ωo) from the nominal THE TIME-DELAY DIGITAL TANLOCK LOOPS (TDTLS) 33 Incoming Signal y(t) Time x(t) Sampler Delay I x(k) (τ) Output Digital c(k) Digital e(k) Phase Error Detector Pulses Clock Filter Tan-1 [x(k)/y(k)] Sampler II y(k) Figure 3.1: Block diagram of the time-delay digital tanlock loop. radian frequency ωo of the digital clock. The input signal is given by y(t) = A sin[ωot + θ(t)] (3.1) where A is the signal amplitude and θ(t)=∆ωt+θo is the phase process of the incoming signal, θo being a constant. The signal is assumed not to have a d.c. component. The time-delay unit introduces a constant time-delay τ in the input signal which causes a phase lag ψ(= ωτ ) proportional to input radian frequency ω. It is worth noting that in the CDTL of Figure 2.8, the phase lag is frequency-independent ψ = π/2 ∀ω. Hence, the following analysis can contain the CDTL as a special case. The time-delayed version of the TDTL input signal, denoted by x(t), can be expressed as x(t) = A sin[ωot + θ(t) − ψ] (3.2) At the kth sampling instant, the sampled values of y(t) and x(t) are given respectively by y(k) = A sin[ωot(k) + θ(k)] (3.3) and x(k) = A sin[ωot(k) + θ(k) − ψ] (3.4) where θ(k) = θ[t(k)]. The sampling interval between the sampling instants t(k) and t(k − 1) is given by T (k) = To − c(k − 1) (3.5) 34 CHAPTER 3 where To(= 2π ωo ) is the nominal period of the digital clock and c(i) is the output of the digital filter at the ith sampling instant. Assuming t(0) = 0, the total time t(k) up to the kth sampling instant is k k−1 t(k) = T (i) = kTo − c(i) i=1 i=0 Thus, y(k) and x(k) can be written as (3.6) k−1 y(k) = A sin[θ(k) − ωo c(i)] i=0 and k−1 x(k) = A sin[θ(k) − ωo c(i) − ψ] i=0 The phase error φ(k) is defined as (3.7) (3.8) k−1 φ(k) = θ(k) − ωo c(i) − ψ i=0 Now y(k) and x(k) can be expressed as (3.9) y(k) = A sin[φ(k) + ψ] (3.10) and x(k) = A sin[φ(k)] From equations (3.6) and (3.9) it can be shown that (3.11) φ(k + 1) = φ(k) − ωc(k) + Λo (3.12) where Λo = 2π ω−ωo ωo . This is the system equation of TDTL; it is similar to that of CDTL. Note that if D(z) is the transfer function of the digital filter, then c(k) = hD(k) ∗ e(k), where hD(k) ←Z.→T. D(z) and e(k) is the output of the phase error detector at the kth sampling instant. 3.2.3 The Characteristic Function If we define f [α] = −π + {(α + π) modulo (2π)}, then e(k) is given by e(k) = f Tan−1 sin{φ(k)} sin{φ(k) + ψ} (3.13) THE TIME-DELAY DIGITAL TANLOCK LOOPS (TDTLS) 35 Thus, the characteristic function hψ(φ) of the phase error detector is non- linear and depends on the input frequency ω and the time delay τ ; it is given by hψ(φ) = f Tan−1 sin(φ) sin(φ + ψ) (3.14) The function hψ(φ) can equivalently be expressed in terms of the ratio W {= ωo ω } and the nominal phase shift ψo(= ωoτ ) as follows hψ(φ) = f Tan−1 sin(φ) sin(φ + ψo W ) (3.15) The four-quadrant Tan−1( x y ) function used by the phase detector can distin- guish between the four quadrants according to the signs of x and y unlike the ordinary tan−1(.) function. Using this property of the phase detector it can be shown that the function hψ(φ) is continuous in φ over the interval (−π, π) by taking the limits at the suspected points where sin(φ+ψ) = 0, also we can prove that dhψ (φ) dφ is continuous over (−π, π) (see Appendix). The continuity of hψ (φ) and its first derivative makes it possible to analyze the circuit performance using fixed point theorems [50, 51]. 3.3 System Analysis In this section the performance of the first- and second-order TDTLs is studied in the absence of noise for an input with a frequency offset. Locking conditions, locking independently of initial phase error, and steady-state phase error are considered. Comparisons with CDTL are made whenever appropriate. 3.3.1 First-order TDTL The first-order loop utilizes a digital filter having just a positive proportionality constant G1. Thus the system equation (3.12) becomes φ(k + 1) = φ(k) − K1 hψ[φ(k)] + Λo (3.16) where K1 = ωG1. If K1 is defined to be ωoG1 then K1 = K1/W . A. Locking Conditions To see whether the system represented by (3.16) will finally reach a steady- state, we follow the same analysis given by Osborne [50]. First, we seek a fixed point of the equation g(φ) = φ − K1 hψ(φ) + Λo (3.17) 36 CHAPTER 3 that is, a solution φss such that φss = g(φss) (3.18) The sequence {φ(k)} defined by (3.16) will converge (locally) to the solution φss, i.e., lim [φ(k)] = φss if k→∞ |g (φss)| < 1 (3.19) provided that g(φ) is continuously differentiable at the fixed point φss. Knowing that hψ(φ) is continuously differentiable over (−π, π), it is easy to see that g(φ) is also continuously differentiable over (−π, π). Now from (3.13), (3.14), (3.17), and(3.18) it can be shown that ess = f Tan−1 sin(φss) sin(φss + ψ) = Λo K1 (3.20) where ess is the steady-state output of the phase error detector. Since |f [.]| < π, we must have |Λo/K1| < π (3.21) From (3.20) it can be shown that sin(ψ)tan(η) tan (φss) = 1 − cos(ψ)tan(η) (3.22) where η = Λo/K1. We now postpone the task of finding the exact expression for φss and define β and α by sin(ψ)tan(η) sin(ψ) β = 1 − cos(ψ)tan(η) = cot(η) − cos(ψ) (3.23) α = tan−1(β) (3.24) where tan−1(.) is the ordinary arctan over(− π 2 , π 2 ). Then it follows that φss = α + jπ , j ∈ {−1, 0, 1} (3.25) From (3.14), (3.17) and (3.19) we obtain |1 − K1 sin(ψ) sin2(φss) + sin2(φss + | ψ) <1 Using (3.24) we get (3.26) |1 − K1 sin(ψ) sin2(α) + sin2(α + | ψ) <1 (3.27) THE TIME-DELAY DIGITAL TANLOCK LOOPS (TDTLS) 37 Knowing that K1 = K1/W, ψ = ψo/W, and Λo = 2π(1 − W )/W, the inequalities (3.21) and (3.27) lead to sin2(α) + sin2(α + ψ) 2|1 − W | < K1 < 2W sin(ψ) or equivalently 2|1 − W | < K1 < 2W sin2(α) + sin2(α + ψo/W ) sin(ψo/W ) (3.28) Since K1 > 0, we must have 0 < f [ψ] < π (3.29) The inequality (3.28) can be solved numerically to find the lock range of the first-order TDTL. Figure 3.2 shows the major range of locking for different values of ψo. If ψo increases beyond π, the lock range begins to separate. It can also be seen that under a suitable choice of ψo (e.g. ψo = π), TDTL can have wider lock range than CDTL. B. The Region of Independent Locking Inequality (3.28) ensures locking only in a neighborhood of φss where φ(k) leads to φ(k + 1) inside (−π, π) such that the phase “locks” finally on φss. Hence locking occurs for some range of values of the initial phase error φ(0) but not necessarily for all values. If the incoming signal has a single frequency (not modulated) within the lock range, changing the initial phase error would result in locking. But in many applications, like tracking M -ary FSK signals, the input frequency is modulated, i.e. having different values. Transition from one frequency to another gives different steady-state phase errors φss according to equations (3.22-3.25). Each φss would be the initial phase error φ(0) for the next incoming frequency. To track (demodulate) such signals, the loop should lock on all incoming frequencies (within the lock range) for all possible values of φ(0) in the range (−π, π), i.e. independently of the initial phase error. Since independent locking entails further condition(s), the range of independent locking is always a subspace of the range of lock. Inside the lock range of the first-order CDTL, the region in which |φ(k + 1)| can exceed π is excluded entirely from the range of independent locking [13]. For TDTL this is no longer true owing to the non-linearity of the characteristic function h(φ). At some points of the lock range, the case when |φ(k + 1)| > π may only cause some cycle slips, therefore these points cannot be excluded from the range of independent locking. 38 6 5 CHAPTER 3 (5) 4 (3) 3 K1 2 (4) (1) 1 (2) 0 0 0.5 1 1.5 2 2.5 W Figure 3.2: Major range of locking of the first-order TDTL for different values of ψo = ωoτ . Note: the region enclosed by (1), (2), and (3) is for CDTL; the region enclosed by (1), (2) and (4) is for TDTL when ψo=π/2; and the region enclosed by (1) and (5) is for TDTL when ψo = π. It is true, however, that if |φ(k + 1)| < π for all φ(k) ∈ (−π, π) at some point of the lock range, then this point is in the range of independent locking. This is ensured if the extrema of the function y given below lie inside (−π, π). y = φ − K1 hψ(φ) + Λo, φ ∈ (−π, π) (3.30) These extrema can occur at φ = ±π or at the critical points of y which exist only when | K1 sin(ψ)−1 cos(ψ) | < 1 and can be expressed after suitable manipulations as φi = f [1{ π(i + n ) − ψ + (1 − 2(i 2 2 modulo(2)))sin−1(κ)}] (3.31) where i ∈ {0, 1, 2, 3}, κ = (K1sin(ψ) − 1)/|cos(ψ)|, n = 1 or -1 according as f [ψ] < π 2 or f [ψ] > π 2 , respectively, keeping in mind that 0 < f [ψ] < π. The case f [ψ] = π 2 is excluded here as it corresponds to conventional DTL. Hence, if the function y above intersects the line y1(φ) = φ at a point φ = φ∗ ∈ (−π, π) such that |y (φ∗)| < 1, then TDTL is inside the lock range according to (3.19), and it would lock on the input frequency with φss = φ∗ THE TIME-DELAY DIGITAL TANLOCK LOOPS (TDTLS) 39 independently of the initial phase error φ(0) if the above extrema of y lie inside (−π, π). If one of these extrema exceeds the range (−π, π), there are two cases to handle: 1) if y does not intersect the line y2(φ) = φ + 2π or the line y3(φ) = φ − 2π, φ ∈ (−π, π), then locking occurs independently of initial phase error φ(0). 2) if y intersects either y2 or y3 at a point φ = φ∗∗ ∈ (−π, π), then locking occurs independently of the initial phase error only when |y (φ∗∗)| > 1. This leads to the following condition | 1 − K1 sin(ψ) sin2(α1) + sin2(α1 + ψ) |> 1 (3.32) where α1 = tan−1 sin(ψ)tan(η ± 2π ) K1 1 − cos(ψ)tan(η ± 2π ) K1 If this case happens for CDTL, we have y (φ∗∗) = y (φ∗) due to linearity, hence |y (φ∗∗)| < 1 and locking would be dependent on the initial phase error. Thus the actual range of independent locking for TDTL can be found only by a numerical search throughout the range of locking. Figure 3.3 shows this range for ψo = π 2 ; it is wider than that of first-order CDTL. C. The Steady-state Phase Error φss Let the four quadrants of phase be defined as Q1 = [0, π 2 ], Q2 = ( π 2 , π), Q3 = (−π, − π 2 ), and Q4 = [− π 2 , 0), noting that ±π are excluded. The actual value of φss can be obtained from (3.20) by careful consideration of the four quadrants. For example, let η {= Λo/K1} ∈ Q2 and consider all angles to be measured modulo (2π) so that f [.] can be dropped off. Then we have (i) sin(φss) > 0, which implies φss ∈ Q1 or Q2. (ii) sin(φss + ψ) < 0, which implies φss + ψ ∈ Q3 or Q4 Thus, ψ ∈ Q1 implies that φss ∈ Q2 or Q3, and ψ ∈ Q2 implies φss ∈ Q1 or Q2 (noting that 0 < ψ < π). The steady-state phase error φss can now be expressed as ⎧ ⎨α φss = ⎩ −π + α π+α β > 0 and ψ ∈ Q2 β > 0 and ψ ∈ Q1 β<0 Noting that β > 0 implies ψ ∈ Q2, φss can be re-expressed as φss = α π+α β>0 β<0 40 CHAPTER 3 4 K1 3.5 3 2.5 2 1.5 1 (4)− − → 0.5 0 0 (2) 0.5 (5) (2) (3) (6) (1) 1 1.5 2 2.5 W Figure 3.3: The range of independent locking of the first-order TDTL when ψo=π/2. Note: the region enclosed by (1), (2), and (6) and the region enclosed by (1), (3), (2), and (5) are for TDTL; the region enclosed by the tetragon is for CDTL. Following the same reasoning as above and noting that β = 0 implies and is implied by η = 0 ∈ Q1, it can be shown that ⎧ ⎪⎪⎪⎪⎨ α φss = ⎪⎪⎪⎪⎩ f [α + π] if η ∈ Q1 and β ≥ 0 , η ∈ Q2 and β > 0 , η ∈ Q3 and β < 0 , or η ∈ Q4 and β > 0 otherwise. More succinctly, φss can be expressed as φss = α f [α + π] β sin(η) ≥ 0 otherwise. (3.33) For the first-order CDTL we have φss = η = Λo/K1, which is dependent on W = ωo/ω and K1 = K1/W . For the first-order TDTL, φss is a function of the above parameters in addition to ψ = ψo/W , as can be seen from eqs.(3.33), (3.24) and (3.23). Hence, for the same W and K1, the relationship between the steady-state phase errors of CDTL and TDTL is decided by ψo = ωoτ . THE TIME-DELAY DIGITAL TANLOCK LOOPS (TDTLS) 41 D. Simulation Results Example 1: Consider a modulation-free input signal y(t) = sin(ωt + θo), θo = constant. Assume that the loop center frequency ωo and the time-delay τ are arranged such that ψo = ωoτ = π/3, and that G1 is chosen such that K1 = G1ωo = 1.4. Note that the specific choice of ωo is application dependent and not important in this analysis since only the ratio W = ωo/ω and the product ωoτ are considered. Once chosen, ωo and τ are constant. Now let the incoming frequency be such that W = 0.9 (i.e. the incoming frequency ω is more than the loop center frequency ωo). This value is inside the lock range since it satisfies (3.28). It is also inside the range of independent locking since all of the extrema of y, (3.30), lie inside (−π, π). Figure 3.4 shows the locking phase process of TDTL for initial phase error φ(0) = θo − ψ = −1 (rad). The phase plane is plotted modulo (2π). Figure 3.4 also shows the sampling process of TDTL on the delayed version of the input signal, x(t), as in (3.11). TDTL arranges its frequency to be equal to the input frequency ω in few steps. The steady-state phase error is φss = 0.5001 (rad), in accordance with (3.33). To study the convergence (locking) speed, we define the relative error between the input frequency ω and TDTL output frequency at the kth sampling interval as E(k) = |ω − 2π T (k) | ω and the convergence indicator kc as kc = k at which E(k + n) < for n = 0, 1, 2, ... where is a small positive number. This indicator decides the locking (convergence) speed and is important in dealing with modulated signals. In this example = 0.01 is considered and we have kc = 3, i.e. locking occurs approximately at the third sampling instant. For CDTL with same parameters K1, W and φ(0) as above we have kc = 7. The same ratio between the convergence indicators of TDTL and CDTL is approximately true for all values of the initial phase error φ(0) in this example. Therefore, the convergence speed is nearly doubled in this case by using TDTL with ψo = π/3. Further studies on convergence behavior would be presented later in this chapter. 42 3 2 1 0 −1 −2 −3 −3 φ (k+1), rad φ (1) φ ss φ (0) −2 −1 0 1 φ (k), rad CHAPTER 3 φ (2) 2 3 t(0) t(1) t(2) t(3) t(10) 1 ° ←T(1) ° → ° °° ° ° ° ° ° ° Input signal 0.5 0 −0.5 −1 0 1 2 3 4 5 6 7 8 9 10 Time Figure 3.4: Above: Locking phase process of the first-order TDTL for ψo = ωoτ = π/3, K1 = 1.4, W = 0.9 and φ(0) = −1 (rad), plotted modulo (2π). Locking occurs independently of the initial phase error φ(0). Below: Sampling process of TDTL on the delayed version of the input signal, x(t), for the above parameters. Example 2: Now we consider a binary FSK input signal with two frequencies ω1 and ω2 such that W1 = ωo/ω1 = 0.8 and W2 = ωo/ω2 = 1.1. Assume ψo = ωoτ = π/2 and K1 = G1ωo = 1. According to Figure 3.2, the loop can lock on both frequencies independently of the initial phase errors. The minimum value of the input frequencies, which is decided by fo and the range of independent locking, should be reasonably larger than the symbol rate R to ensure locking. THE TIME-DELAY DIGITAL TANLOCK LOOPS (TDTLS) 43 Output of phase error detector, e (t (k)) 3 2 1 0 −1 −2 −3 0 20 40 60 80 100 120 Time Figure 3.5: Tracking a binary FSK signal using the first-order TDTL with W1 = ωo/ω1 = 0.8, W2 = ωo/ω2 = 1.1, ψo = ωoτ = π/2 and K1 = G1ωo = 1. A loop with higher convergence speed can handle higher R for a fixed fo. For clarity we take in this example fo/R = 20. Figure 3.5 shows the output of the phase error detector, e(k), as a function of time for this signal. The two values of ess are 1.2566 (rad) and -0.6283 (rad), in accordance with (3.20). 3.3.2 Second-Order TDTL The second-order TDTL utilizes a proportional-plus accumulation digital filter with a transfer function D(z) given by D(z) = G1 + G2/(1 − z−1) (3.34) where G1 and G2 are positive constants. From eqs.(3.34) and (3.12), the system equation of the second-order TDTL can be obtained as φ(k + 2) = 2φ(k + 1) − φ(k) − rK1e(k + 1) + K1e(k) where r = 1 + G2/G1 and K1 = G1ω. A. Locking Conditions (3.35) In the steady-state we have φ(k+2) = φ(k+1) = φ(k), hence e(k+1) = e(k). Therefore, the steady-state value of the output of the phase detector ess is zero. From (3.13) it is evident that the steady-state phase error φss is nπ (n being an integer). Since f [φss] = ±π we must have f [φss] = 0, hence φss = 2mπ (m being an integer). 44 CHAPTER 3 Following the same fixed point analysis as that given by Osborne [51], the locking conditions can be obtained from the condition that the eigenvalues of the matrix G given by 0 1 G = −1 + K1 csc(ψ) 2 − rK1 csc(ψ) must be less than 1. If 0 < f [ψ] < π, then the matrix G is similar to that given in [51], (2.9), with K1 replaced by K1csc(ψ). Thus, we have the following conditions 4 0 < K1 < 1 + W r sin ψo W , r>1 (3.36) If −π < f [ψ] < 0, G will be similar to the matrix in (2.11) obtained [51] with K1 replaced by −K1csc(ψ) and conditions that are mutually exclusive with (3.35) are obtained. Therefore, we will consider f [ψ] to be in the interval (0, π) only, adding the following condition 0 < f [ψ] < π (3.37) Figure 3.6 shows the major range of locking of the second-order TDTL for different values of ψo. Although the lock range is reduced in comparison to the lock range of the second-order CDTL, any range of input frequencies can be handled after suitable modification of the circuit parameters, keeping in mind that high values of K1 in the lock range of CDTL are not desired [13]. B. The Region of Independent Locking As for the range of locking independently of initial phase errors φ(0) and φ(1), numerical search throughout the lock range has showed that the range of independent locking is still bounded by the conditions of independent locking for the second-order CDTL given by 2W 4W r + 1 < K1 < r + 1 (3.38) and 2W 0 < K1 < r − 1 (3.39) These conditions can also be obtained from (3.35) by assuming that |φ(k + 2)| < π when |φ(k + 1)| = |φ(k)| = π, and noting that lim hψ(φ) = π, lim hψ(φ) = −π, φ→π− φ→−π+ THE TIME-DELAY DIGITAL TANLOCK LOOPS (TDTLS) 45 8 7 CDTL → TDTL, ψo = 5π/4 6 5 K1 4 3 TDTL, ψo = π/2 2 TDTL, ψo = π/4 1 0 0 1 2 3 4 5 6 7 8 W Figure 3.6: Major range of locking of the second-order CDTL and TDTL for different values of ψo (r = 1.2). Note: lock range is the area under the suitable curve. The ranges of independent locking for CDTL and TDTLs are the areas enclosed by the dashed line and the appropriate curves. and that the other limits, lim hψ(φ) and lim hψ(φ), are not considered as they φ→π+ φ→−π− are outside the interval (−π, π). It is worth noting that the above two conditions are independent of ψo. Figure 3.6 shows the boundaries of independent locking with r = 1.2 for the second-order CDTL and TDTL with different values of ψo. 3.4 Locking Speed In this section, the convergence behavior of the TDTL in the absence of noise is analyzed. This analysis concentrates on the actual number of steps necessary for convergence of the phase error to within a radius of the steady-state phase error. In [50] and [52], the convergence behavior of the first-order sinusoidal DPLL and CDTL are analyzed based on Lipschitz constant. We adopt the similar approach here, using different values of the circuit parameters. 46 CHAPTER 3 3.4.1 Convergence of the First-Order TDTL The first-order TDTL utilizes a digital filter with a positive proportionality constant G1 only. The system equation is given by (3.16) as follows: φ(k + 1) = φ(k) − K1 hψ[φ(k)] + Λo where K1 = ωG1, K1 = ωoG1, and K1 = K1/W . The locking range of the first-order TDTL is shown in Figure 3.2 for different values of ψo. In the analysis below, it should be noted that the choice of the loop parameters ωo and τ will decide the lock range as in Figure 3.2, where ψo = ωoτ , while the choice of the parameter K1 and the frequency ratio W = ωo/ω should ensure that the loop is inside the lock range. The steady-state phase error at the input of the phase error detector was derived as [70]. φss = α f [α + π] β sin(λ) ≥ 0 otherwise, (3.40) where λ = Λo/K1 sin(ψ) β = cot(λ) − cos(ψ) α = tan−1(β). (3.41) The characteristic function hψ(φ) and its first derivative are continuously differentiable in the principal interval (−π, π), hence fixed point analysis is applicable to the TDTL [70]. Following fixed point analysis developed in [50] for the sinusoidal digital phase-locked loop, the Lipschitz constant for the firstorder TDTL can be given by L = max g(φ) − g(φss) φ − φss (3.42) where g(φ) = φ − K1hψ(φ) + Λo. The asymptotic estimate (upper bound) to the number of steps required for convergence of the phase error φ(k) within a radius of the fixed point φss is given by [50] m = int ln( /|φ − φss|) + 1 ln(L) (3.43) where int[.] is the integer function. It can be shown that the time required to reach the fixed point φss is given by Tc = mToW + (φ(m) − θo + ψ)/ω ≈ mToW (3.44) THE TIME-DELAY DIGITAL TANLOCK LOOPS (TDTLS) 47 35 normalized convergence time, Tc / To 30 * * TDTL time 25 + + CDTL time 20 15 10 asymptotic bound, TDTL 5 asymptotic bound, CDTL 0 0 0.5 1 1.5 2 2.5 3 Initial phase error, φ o , rad Figure 3.7: Normalized convergence time with asymptotic bounds for the first-order TDTL (ψo = π/3) and CDTL with phase step input (W = 1), = 0.01, and K1 = 0.25. where (φ(m) − θo + ψ) ≪ ω. This is the same as CDTL case, with Lipschitz bound m = |1 − K1| [52]. Numerical simulation showed that, unlike the case of CDTL, Lipschitz bound m is not a tight limit for M , the true number of steps for convergence. This is true for all values of TDTL parameters. The difference m − M increases with the absolute difference of the initial phase φo from the steady-state phase error φss. Figure 3.7 shows the normalized convergence time, Tc/To, based on simulation, along with the asymptotic normalized convergence time based on Lipschitz constant as given by (3.44), for a phase step input (i.e. W = 1), ψo = π/3, and K1 = 0.25. For a phase step input we have φss = 0, as in (3.40). Although the asymptotic convergence time for TDTL is higher than the actual convergence time, the actual convergence time is essentially the same as that of CDTL for all values of K1 and ψo. Figure 3.8 shows the normalized convergence time with the asymptotic bound for a frequency step input W = 0.9 (i.e. the input frequency, ω, is higher than the nominal loop frequency, ωo), K1 = 0.25, and ψo = π/3. Note that for both CDTL and TDTL, the loop converges instantly at φo = φss. Although the asymptotic convergence time for TDTL is higher than that of CDTL, the actual convergence time is much less. Hence, for a robust estimation of the convergence time of TDTL, a numerical study is essential. This is rather similar to the discrepancy found in [50] for the sinusoidal DPLL. Note that the characteristic 48 CHAPTER 3 normalized convergence time, Tc / To 20 18 16 14 12 10 8 6 4 2 0 0 +++ TDTL time CDTL time asymptotic bound, TDTL asymptotic bound, CDTL 0.5 1 1.5 2 2.5 3 Initial phase error,φo, rad Figure 3.8: Normalized convergence time with asymptotic bounds for the first-order TDTL (ψo = π/3) and CDTL with frequency step input (W = 0.9), = 0.01, and K1 = 0.25. function of the phase error detector is non-linear for TDTL and the sinusoidal DPLL, while it is linear for CDTL. In Figure 3.9, the normalized convergence times for CDTL and TDTL for the same parameters as above and different values of TDTL nominal phase shift ψo. The value of ψo is decided by the center frequency ωo and the time-delay τ . Hence, by a suitable arrangement of the parameters ωo, K1, and τ , the locking speed of TDTL can be made higher than that of CDTL. 3.5 Conclusions A nonuniform-sampling time-delay digital tanlock loop (TDTL) has been presented, where the conventional constant 90o phase-shifter is replaced by a timedelay unit. This is to avoid many of the practical problems associated with the implementation of the digital Hilbert transformer which is an essential part of CDTL and all of its modifications. These problems include approximations, frequency limitations, and implementation complexity. Although non-linearity is introduced in the analysis of the loop, the most important merits of CDTL over other sinusoidal DPLLs are preserved. The first-order TDTL has wider lock range, wider range of independent locking, and faster convergence than CDTL if the circuit parameters are properly chosen. THE TIME-DELAY DIGITAL TANLOCK LOOPS (TDTLS) 49 normalized convergence time, Tc / To 20 18 16 CDTL 14 TDTL, ψ o = π/2 12 10 8 TDTL, ψ o = 2 π /5 6 4 TDTL,ψ o = π /3 2 0 0 0.5 1 1.5 2 2.5 3 Initial phase error, φ o , rad Figure 3.9: Normalized convergence time for the first-order TDTL (different values of ψo) and CDTL with frequency step input (W = 0.9), = 0.01, and K1 = 0.25. We discussed the convergence behavior of the first-order TDTL. It is found that, unlike the conventional digital tanlock loop (CDTL), the asymptotic bound of the number of steps required for convergence based on Lipschitz constant diverges from the actual number of steps. This difference increases with the absolute difference of the initial phase from the steady-state phase error. For both CDTL and TDTL, convergence speed decreases as the initial phase error diverges from the steady-state phase error. Numerical study showed that the first-order TDTL locks as fast as CDTL for a phase step input for all ranges of the effective parameters, although the Lipschitz asymptotic bound for TDTL is higher than that of CDTL in this case. For a frequency step input, the firstorder TDTL locks faster than CDTL under suitable arrangement of the loop parameters: the time-delay τ , the center frequency ωo, and the loop gain K1. Appendix The characteristic function hψ(φ), defined by (3.14), is continuous in φ over the interval (−π, π). This can be seen by considering the limits when φ approaches the suspected points at which sin(φ + ψ) = 0. Consider 0 < ψ < π, which is the basic version of the locking condition 0 < f [ψ] < π (see Section 3.3). Now in the interval (−π, π), sin(φ + ψ) = 0 implies φ + ψ = 0 or π. Consider the point at which φ + ψ = π. Hence 0 < φ < π and sin(φ) > 0. Then the left and 50 CHAPTER 3 right limits of the characteristic function are equal at this point as follows lim f Tan−1 sin(φ) φ+ψ→π− sin(φ + ψ) = lim f Tan−1 sin(φ) φ+ψ→π− 0+ ππ = lim f = φ+ψ→π− 2 2 and lim f Tan−1 sin(φ) φ+ψ→π+ sin(φ + ψ) = lim f φ+ψ→π− Tan−1 sin(φ) 0− 3π π = lim f − = φ+ψ→π− 22 The point at which φ + ψ = 0 can be handled similarly. Since α and f [α] = −π + {(α + π)modulo (2π)} differ only by a constant, their derivatives are the same. Hence we have after some manipulations dhψ(φ) dφ = sin2(φ) sin(ψ) + sin2(φ + ψ) It is clear that for 0 < f [ψ] < π, which is a locking condition for both first and second-order TDTLs (Section 3.3), the denominator of dhψ (φ) dφ is always positive, hence dhψ (φ) dφ is continuous in φ over the interval (−π, π). Chapter 4 Hilbert Transformer and Time-Delay 4.1 Introduction Hilbert Transform (HT) is a significant tool in mathematics, physics, and signal analysis wherever Fourier techniques are used to represent or analyze functions or signals. In the continuous-time domain the Hilbert transform s(t) of the function s(t) is given by the following linear operation [61] 1 ∞ s(r) s(t) = H[s(t)] = P dr π −∞ t − r 1 = lim L→∞ π δ→0 t−δ s(r) L s(r) dr + dr −L t − r t+δ t − r (4.1) where the Cauchy principal value (P) is used here to ensure convergence of the integral. It is apparent that H[s(t)] represents the convolution of s(t) with 1/πt. If the signal is causal, the real and the imaginary parts of its Fourier trans- form are related by Hilbert transform integral, a fact of importance in signal analysis [62]. Hilbert transformers are widely used in modulation theory [61, 63]. The statistical properties of a signal s(t) in noise can be obtained in a more suc- cinct fashion by utilizing Hilbert Transform representation of the signal and the concept of the analytic signal z(t) associated with s(t) which is defined as [63, 64] z(t) = s(t) + j H[s(t)] (4.2) In time-frequency signal analysis, which is a powerful tool to deal with nonstationary signals, the discretization of the time-frequency distribution (TFD) 51 52 CHAPTER 4 of any signal s(t) creates aliasing problem that reduces the acceptable signal frequency range to ωmax ≤ ωs/4 instead of the Nyquist bound ωmax ≤ ωs/2 in the continuous-time analysis [64] (ωmax being the highest frequency in the signal and ωs the sampling radian frequency). However, the introduction of the analytic signal (defined above) eliminates the aliasing problem by eliminating the negative frequencies from the spectrum of the signal s(t), which results in significant enlargement of the frequency range and clearer study of the signal [64, 65]. The transfer function H(jw) of the system represented by (4.1) is given in continuous-time by [61] ⎧ ⎨ −j ω ≥ 0 H(jω) = ⎩ 0 j ω=0 ω<0 (4.3) and in discrete-time by [62] ⎧ ⎨ −j H(ejω) = ⎩ 0 j 0≤ω<π ω=0 −π ≤ ω < 0 (4.4) The above transfer functions, in continuous-time or discrete-time, represent a −90o phase-shift operation on the input signal s(t) in the frequency range 0 ≤ ω < ∞ in the continuous time and 0 ≤ ω < π in the discrete-time. The output signal is a delayed version of the input signal and therefore HT is considered in this general sense as a time-delay phase-shifting system. The difference is that HT produces a signal-dependent delay and signal-independent phase-shift, while the time-delay system gives a signal-independent delay and signal dependent phase-shift. Hence in some signal processing systems it may be possible to replace a HT by a time-delay. If this is possible, significant reduction in the system complexity can be achieved since the time-delay is much easier to implement than the complicated Hilbert transformer [61, 62]. Recently this idea has been proposed in the area of digital phase-locked loops [70, 71] (see also Chapter 2) in an attempt to reduce the complexity of the signal processing system and to avoid the limitations and other problems that accompany the implementation of the HT [61, 60]. This resulted in similar performance of the new system except that non-linearity was introduced in the system equation. In addition, locking speed can be doubled and locking range of the first-order loop can be extended by suitable arrangement of the time-delay with other circuit parameters, a fact that is not verified by the signal-independent system using Hilbert transformer. This idea may be applied to other areas in signal processing. HILBERT TRANSFORMER AND TIME-DELAY 53 The behavior of the HT in additive Gaussian noise was considered in [13] in a context of digital phase-locked loops (DPLLs). In this chapter we concentrate on the behavior of the time-delay τ as a phase-shifter for sinusoidal signals in the presence of Gaussian noise. Noise analysis of the HT reduces to a special case of this general analysis. The study is based on the statistical characteristics of the phase estimation. The Cramer-Rao bound, which was missing in the treatment of the HT in [13], is included to know the limitations of the phase estimator and to present better comparison between the time-delay and Hilbert transform. This comparison is based on considering an ideal Hilbert transformer that gives exactly −90o phase shift without phase or amplitude distortion or other practical problems associated with the HT implementation. In the next section the joint probability density function (pdf) of the input signal and its time-delayed (or: phase-shifted) version is derived in additive Gaussian noise, from which the pdf of the phase estimator is obtained and analyzed under various values of the effective parameters: the phase shift ψ, the true phase value φ, and the signal-to-noise ratio SNR. 4.2 Statistical Behavior of HT and Time-Delay in i.i.d. Additive Gaussian Noise 4.2.1 Input-Output Relationships in the Presence of Noise For sinusoidal signals we have the relationship H(cos(ωt)) = sin(ωt). The input and the output of the time-delay are given under noise-free condition by x(t) = A sin(ωt + ψ) and y(t + τ ) = A sin(ωt), where A is the signal amplitude and ψ = ωτ is the signal-dependent phase shift. In a causal system we have the following range of ψ 0 < f [ψ] < π (4.5) where f [ψ] = −π + {(ψ + π) modulo (2π)} (4.6) In the presence of noise the input-output relationships become x(t) = A sin(φ(t) + ψ) + n(t) y(t + τ ) = A sin(φ(t)) + n (t) (4.7) (4.8) where φ(t) = wt, n(t) is assumed to be Gaussian noise of zero mean and variance σn2, and n (t) is the time-delayed version of n(t). Apparently n (t) is also Gaussian with the same mean and variance as n(t). It follows that x(t) and 54 CHAPTER 4 y(t) are also Gaussian random variables with variance σn2 and ensemble means given at any time instant t by E[x(t)] = A sin(φ(t) + ψ) E[y(t + τ )] = A sin(φ(t)) (4.9) (4.10) In the presence of noise both x(t) and its phase-shifted version y(t + τ ) are random both in amplitude and in phase. To find the pdf of the random phase of x(t) and y(t + τ ) and its relationship to the deterministic phase at any time instant t, we should first write the sample functions x(t) and y(t + τ ) in terms of two new sample functions R(t) (for amplitude) and (t) (for phase) such that the sample functions x(t) and y(t) maintain the same relationship between them as in the deterministic (noise-free) case. This gives in the case of time-delay (τ ) the following transformations x(t) = R(t) sin (t) + ψ y(t + τ ) = R(t) sin (t) (4.11) (4.12) This is the same assumption made in reference [13] for the Hilbert transformer case. It is equivalent to defining a set of two new random variables (R, ) in terms of the original random variables (x, y) according to the mappings f1 and f2 defined by R = f1(x, y) = ⎛ x − co⎧s(ψ)y ⎫⎞ sin(ψ) cos ⎝Tan−1 ⎨ ⎩ 1 sin(ψ) − y cos(ψ) ⎬ ⎠ ⎭ x and ⎡ ⎧ ⎫⎤ = f2(x, y) = f ⎣Tan−1 ⎨ ⎩1 sin(ψ) − y cos(ψ) ⎬ ⎦ ⎭ x where f [.] is defined in (4.6) and Tan−1 is the four-quadrant inverse tangent. The above choice of the relationships between (R, ) and (x, y) makes sense when a comparison is made between the noise-free and noisy expressions for the original variables x and y in terms of amplitude and phase. This comparison constitutes the basis of this work. Figure 4.1 summarizes these relationships for HT and time-delay. 4.2.2 Joint PDF of the Amplitude and Phase Random Variables In this analysis we concentrate on the discrete case and assume that the discrete noise process {n(k)} is a sequence of i.i.d. (independent and identically HILBERT TRANSFORMER AND TIME-DELAY 55 x(t ) = A sin [φ(t ) + π/2] ( noise − free ) x(t ) = R(t ) sin [ε (t ) + π/2] ( in noise) HT Hilbert transform phase shift = π/2 y(t+τ ′ ) = A sin [φ(t )] ( noise − free ) y(t+τ ′ ) = R(t ) sin [ε (t )] ( in noise ) x(t ) = A sin [φ(t ) + ψ] ( noise − free ) x(t ) = R(t ) sin [ε (t ) + ψ] ( in noise) τ Timedelay phase shift = ψ = ω τ y(t+τ) = A sin [φ(t )] ( noise − free ) y(t+τ ) = R(t ) sin [ε (t )] ( in noise ) Figure 4.1: Input-output relationships for Hilbert transformer and time-delay τ under noise-free and noise conditions. R(t) is the amplitude random variable, (t) is the phase random variable, and ω is the input radian frequency. τ is the practical delay caused by FIR implementation of HT. distributed) Gaussian random variables. It follows that the phase shifted noise process {n (k)} is also a sequence of i.i.d. Gaussian random variables with same mean and variance, and that the two random variables {n(k)} and {n (k)} are independent at any sampling instant k. Hence the discrete versions of x and y in (4.7) and (4.8) are also independent Gaussian random variables at any sampling instant k with joint probability density function (pdf) given at any sampling instant k by 1 gψ,φ(x, y) = exp 2πσn2 1 − 2σn2 x − A sin(φ + ψ) 2 + y − A sin(φ) 2 (4.13) where for simplicity x, y, φ, R, and will be used to represent x(k), y(k + τ ), φ(k), R(k), and (k) respectively. In the presence of noise the relationship between x and its phase-shifted version y in terms of the amplitude and phase random variables R and would 56 CHAPTER 4 be as in (4.11) and (4.12). Hence the joint pdf of R and is given by [74] Pψ,φ(R, ) = gψ,φ R sin( + ψ), R sin( ) × sin( + ψ) R cos( + ψ) sin( ) R cos( ) (4.14) where gx,y is given by (4.13) with x and y written in terms of R and as in (4.11) and (4.12). 4.2.3 PDF of the Phase Random Variable In this chapter we concentrate on phase estimation rather than amplitude estimation. The pdf of the phase random variable is given by ∞ pψ,φ( ) = Pψ,φ(R, ) dR 0 (4.15) which can be given, after some trigonometric manipulations, in the following functional form pψ,φ( ) = hψ( ) 1 × 2π exp{−µψ,φα} + µψ,φα cos π Hψ,φ( ) × exp{−µψ,φα sin2 Hψ,φ( ) } 1 × + erf{ 2 2µψ,φα cos Hψ,φ( ) } (4.16) where α = A2/2σn2 (signal − to − noise ratio) hψ( ) = f [Tan−1{ sin( ) }] sin( + ψ) hψ( ) = dhψ ( d ) = sin2( sin(ψ) ) + sin2( + ψ) sin(ψ) µψ,φ = hψ(φ) Hψ,φ( ) = hψ( ) − hψ(φ) erf(x) = √1 x e−t2/2dt 2π 0 (4.17) (4.18) (4.19) (4.20) (4.21) (4.22) HILBERT TRANSFORMER AND TIME-DELAY 57 and f [.] is defined in (4.6). Note that Tan−1 is the four-quadrant inverse tangent. It is clear that pψ,φ( ) is non-Gaussian. For high values of SNR, pψ,φ( ) can be approximated by pψ,φ( ) = hψ( ) µψ,φα cos π Hψ,φ( ) × exp{−µψ,φα sin2 Hψ,φ( ) } 1 × 2 + erf{ 2µψ,φα cos Hψ,φ( ) } (4.23) The above approximation can be used even for as low values of SNR as 1 dB, but the minimum value of pψ,φ( ) would be slightly negative; and this has no effect on the general shape of pψ,φ( ). If ψ = π/2, we have hψ( ) = 1, Hψ,φ( ) = f [ ]−f [φ] = −φ in the principal interval (−π, π), and µψ,φ = 1 see (4.18) - (4.21) , hence (4.16) reduces to the Hilbert transform case obtained in [13] in a context of DPLLs pψ,φ( ) = 1 exp(−α) + 2π α cos( − φ) exp {−α sin2( − φ)} π × 1 + √ erf{ 2α cos( − φ)} (4.24) 2 Note that pψ,φ( ) for HT is symmetric about = φ with a peak that depends only on SNR. In this case, the function pψ,φ( ) = zψ(φ, ), which is periodic in for each φ with a period of 2π, has its peak exactly along the lines = f [φ]+2mπ in the (φ, ) plane (for all integer m). This peak has a maximum value that is constant for a given SNR. In the general case (time-delay case) the peaks are slightly biased from = f [φ]+2mπ and have variable maximum value depending on SNR, ψ, and the true value of the phase, f [φ]. The bias of the pdf peak decreases as SNR increases or ψ approaches π/2. It is worth noting that this bias of the pdf peak at any φ does not mean that the expected value of the phase random variable is shifted by the same amount from the true value of the phase, f [φ], since this pdf is non-symmetric. In fact, the expected value of − f [φ] is nearly zero for any φ when SNR is not very low, as will be shown in Subsection (4.2.5). The 2-D plot of pψ,φ( ) for SNR=10 dB and ψ = π/3 is shown in Figure 4.2 along with the contour plot to reveal the approximate symmetry about the line = φ in the (φ, ) plane. 4.2.4 PDF of the Phase Noise From the above subsection we conclude that in the principal interval (−π, π), the phase can be generally decomposed into a deterministic term f [φ] and a random variable η as follows 58 CHAPTER 4 = f [φ] + η (4.25) where η is in the interval (−π − f [φ], π − f [φ]). This is similar to the result obtained for the Hilbert transformer [13] when the phase shift was π/2. The pdf of the phase noise η is given by ρψ,φ(η) = pψ,φ( − f [φ]) (4.26) which is generally dependent on ψ and f [φ] when the phase shift ψ = π/2. We can obtain this pdf from pψ,φ( ) for any value of ψ and φ by the intersection with the suitable plane. The intersection of a plane φ = constant with pψ,φ( ) is symmetric when ψ = π/2 (HT case), while it is non-symmetric for general ψ except for high SNR. This can be seen in Figure 4.2. Although the contour plot is approximately symmetric about = φ, its boundaries are slightly varying, not straight parallel lines, giving non-symmetry when a plane φ = constant intersects the pψ,φ( ) plot. As SNR increases, the boundaries of the contour plot approach straight parallel lines and consequently pψ,φ(η) becomes symmetric. Figure 4.3 shows ρψ,φ(η) when f [φ] = 0 for different values of SNR (ψ = π/3) and different values of ψ (SNR = 10 dB). Only the principal period (−π, π) is considered. It is clear that ρψ,φ(η) is more symmetric and concentrated around η = 0 for higher values of SNR. From (4.16) and (4.26) it is possible to show that ρψ,φ(η) has the following anti-symmetry in the interval (−π, π) ρψ,φ(η) = ρπ−ψ,φ(−η) This anti-symmetry is clarified in Figure 4.3. (4.27) 4.2.5 Expectation and Variance of the Phase Noise The expected value and the variance of the phase noise η when f [φ] = 0 are shown in Figure 4.4 for different values of ψ and SNR. Note that the symmetry in the expected value and the similarity in the variance result from the antisymmetry in (4.27). For this value of f [φ] the Hilbert transform case (ψ = π/2) gives the minimum variance, but this is not always true for the whole range of f [φ]. Figure 4.5 shows the expected value and the variance of the phase noise η for ψ = π/3 and different values of f [φ] as compared to the HT case. The HT phase pdf is φ-independent and give the same plots for the absolute expectation (which is zero) and the variance of the phase noise η for all values of f [φ]. For the time-delay with any value of ψ, changing the value of f [φ] would result in changing the maximum of ρψ,φ(η). This difference results in a slight difference HILBERT TRANSFORMER AND TIME-DELAY 59 3 2 ε (rad) 1 ψ = π/3, SNR = 10 dB 0 −1 −2 −3 −3 −2 −1 0 1 2 3 φ (rad) Figure 4.2: Above: the probability density function of the phase random variable, pψ,φ( ) = zψ(φ, ), for ψ = π/3 and SNR = 10 dB. Below: contour plot of the above pψ,φ( ) at the level of 0.5 for one period in the (φ, ) plane. Dotted line is the = φ line. It is clear that pψ,φ( ) is nearly symmetric about = φ line. As SNR increases, the contour plot becomes two parallel lines. in the expected value and the variance of η for different values of f [φ] as shown in Figure 4.5 for ψ = π/3 and different values of f [φ]. For some values of f [φ] the variance can go below the HT case. However, the performance is measured by considering the expectation and the variance of η for the whole range of f [φ]. Therefore the (ideal) Hilbert transformer outperforms the time-delay in all cases. ρψ,φ(η) 60 4 3.5 3 2.5 2 1.5 1 0.5 0 −3 ψ = π/3 f[φ] = 0 −2 −1 0 η (rad) CHAPTER 4 SNR = 15 dB SNR = 10 dB SNR = 5 dB 1 2 3 ρψ,φ(η) 4 3.5 SNR = 10 dB 3 f[φ] = 0 2.5 2 ψ = π/8 1.5 ψ = 7π/8 1 0.5 ψ = π/2 0 −3 −2 −1 0 1 2 3 η (rad) Figure 4.3: The probability density function ρψ,φ(η) of the phase noise η when f [φ] = 0. Above: ρψ,φ(η) for ψ = π/3 and different values of SNR. Below: ρψ,φ(η) for SNR = 10 dB and different values of ψ. Note that the dashed curve (ψ = π/2) is symmetric and represents the Hilbert transform (HT) case. The two solid curves clarify the ψ anti-symmetry of the phase noise pdf. Note that this comparison is based on considering an ideal Hilbert transformer that gives exactly −90o phase shift without phase or amplitude distortion or other practical problems associated with the implementation [61, 60]. HILBERT TRANSFORMER AND TIME-DELAY 61 E (η), rad 0.08 0.06 ψ = π/4 ψ = π/3 0.04 ψ = 2π/5 ψ = π/2 (HT) 0.02 0 −0.02 −0.04 ψ = 3π/5 −0.06 ψ = 3π/4 ψ = 2π/3 ( f[φ] = 0 ) −0.08 10 11 12 13 14 15 16 17 18 19 20 Input SNR (dB) variance (η ) (dB) −10 −12 ψ = 2π/5 & 3π/5 −14 ψ = π/3 & 2π/3 ψ = π/4 & 3π/4 −16 −18 ψ = π/2 ( HT ) −20 −22 ( f[φ] = 0 ) −24 10 11 12 13 14 15 16 17 18 19 20 Input SNR (dB) Figure 4.4: The expected value (above) and the variance (below) of the phase noise η for different values of ψ and SNR (f [φ] = 0). The case ψ = π/2 is the Hilbert transform (HT) case which gives minimum value for the variance and the absolute expectation (approximately zero) of the phase noise η. The symmetry of the expected value about zero and the similarity of the variance for ψ and π − ψ cases are due to the ψ anti-symmetry of the phase noise pdf. In all the cases studied above for the time-delay, the expected value of the phase noise η is approximately zero and decreases when SNR increases, also the variance decreases substantially when SNR increases. 62 CHAPTER 4 | E (η) |, rad 0.035 0.03 0.025 0.02 0.015 − − f[φ] = 0 * * f[φ] = −π/2 & π/2 x x f[φ] = −π/4 + + f[φ] = π/4 (ψ = π/3 ) 0.01 0.005 ( HT ) 0 10 11 12 13 14 15 16 17 18 19 20 Input SNR (dB) −10 + + f[φ] = π/4 * * f[φ] = −π/2 & π/2 −15 (ψ = π/3 ) variance (η) (dB) − − f[φ] = 0 −20 x x f[φ] = −π/4 (ψ = π/3 ) ( for HT ) −25 10 11 12 13 14 15 16 17 18 19 20 Input SNR (dB) Figure 4.5: The expected value (above) and the variance (below) of the phase noise η for different values of f [φ] and SNR when ψ = π/3. The solid line represents the HT case which is φ-independent. 4.2.6 The phase Estimator and Ranges of Cramer-Rao Bounds From the above analysis, the random phase variable can be used as a phase estimator, φˆ. It can be expressed in the interval (−π, π) in terms of ψ, x, and HILBERT TRANSFORMER AND TIME-DELAY 63 y according to (4.11) and (4.12) as follows ⎡ ⎧ ⎫⎤ = φˆ = f ⎣Tan−1 ⎨ ⎩ 1 sin(ψ) − y cos(ψ) ⎬ ⎦ ⎭ x (4.28) where f [.] is defined in (4.6) and Tan−1 is the four-quadrant inverse tangent. Since φˆ is approximately unbiased for reasonable values of SNR (a minimum of 10 dB is acceptable in all cases), its variance is lower-bounded by the Cramer- Rao (CR) bound [75], which can be expressed in this case as follows var(φˆ) = E( − φ)2 ≥ E 1 ∂ ln{pψ,φ( )} 2 ∂φ 1 = π−f [φ] −π−f [φ] ∂ ln{pψ,φ( ∂φ )} 2 pψ,φ( )d = CRψ(φ) (4.29) There is no analytic expression for the CR bound CRψ(φ), hence it should be found numerically using (4.29) and (4.16). Figure 4.6 shows the variance of the time-delay phase estimator var(φˆ) and its CR bound for ψ = π/3 and f [φ] = 0. The variance converges to its CR bound as SNR increases. This is true for all values of ψ = π/3 and f [φ]. For HT, the variance of the phase estimator, var(φˆ), is nearly identical with the CR bound in the range of SNR shown in Figure 4.6. Figure 4.6 also shows the approximate ranges of CR bounds of the timedelay phase estimator when ψ = π/7 & 6π/7 (the area between dotted lines) and ψ = π/3 & 2π/3 (the area between dashed lines) as f [φ] ranges throughout the interval (−π, π]. The range is found numerically for each ψ by calculating CR bounds for all values of f [φ] in the principal interval −π < f [φ] ≤ π. Similarity in CR bounds between ψ and π − ψ cases is due to the ψ antisymmetry of pψ,φ discussed earlier. The solid line represents CR bound of the HT phase estimator, which is independent of the phase true value f [φ]. As ψ approaches π/2, the range of CR bounds approaches the HT case. The performance of the time-delay for each ψ is measured by considering the least upper bound {CRψ(φ) | − π < f [φ] ≤ π}. As such the (ideal) Hilbert transformer outperforms the time-delay in all cases. It is clear that the performance of the time-delay phase estimator, regarding both the expectation and the variance of the phase noise, decreases as ψ goes far from π/2, especially for low SNR. Hence if a constant time-delay τ is to replace the Hilbert Transform in some signal processing system while keeping highest possible performance in the presence of noise, the appropriate choice of 64 CHAPTER 4 Variance of Phase Estimator, dB −12 – – – Cramer–Rao bound −14 ψ = π/3 , f[φ] = 0 −16 −18 −20 −22 −24 10 11 12 13 14 15 16 17 18 19 20 Input SNR (dB) 0 −5 CR bounds, dB −10 −15 −20 −25 −30 10 11 12 13 14 15 16 17 18 19 20 Input SNR (dB) Figure 4.6: Above: the variance and the Cramer-Rao bound of the time-delay phase estimator for ψ = π/3 and f [φ] = 0. The variance converges to the CR bound as SNR increases. Below: approximate ranges of the CR bounds of the time-delay phase estimator for ψ = π/7 & 6π/7 (the area between dotted lines), and ψ = π/3 & 2π/3 (the area between dashed lines). The range is found numerically for each ψ by calculating the CR bounds for all values of f [φ] in the principal interval −π < f [φ] ≤ π. Similarity in the CR bounds between ψ and π − ψ is due to the ψ anti-symmetry of the phase pdf. The solid line represents the CR bound of the HT phase estimator, which is independent of the phase true value f [φ]. As ψ approaches π/2, the range of the CR bounds approaches the HT case. HILBERT TRANSFORMER AND TIME-DELAY 65 τ would be application dependent. The proper value of τ should keep ψ = ωτ as near to π/2 as possible throughout the expected range of the input frequencies. However, this condition on the choice of τ becomes less strict as SNR increases. Also the performance regarding the expected value of the phase can be made the same as in the HT case by utilizing a phase transformation that makes the phase pdf symmetric as shown in the following subsection. 4.2.7 A Symmetric Transformation As shown above, the pdf of the phase estimator is non-symmetric. However, this pdf can be transformed into a symmetric pdf by the following transformation of the random variable ξ = hψ( ) = f Tan−1 sin( ) sin( + ψ) (4.30) From (4.6) and (4.19) we can deduce that both the numerator and the denominator of h ( ) = dh( )/d are positive. Therefore h ( ) is always positive and h( ) is monotonically (in fact: strictly) increasing in the principal interval (−π, π). Hence the pdf of ξ can be given by [74] pψ,φ(ξ) = pψ,φ h−ψ 1(ξ) d dξ (4.31) From (4.16), (4.21), (4.30), and (4.31) we obtain 1 pψ,φ(ξ) = 2π exp{−µψ,φα} + µψ,φα cos π ξ − hψ(φ) × exp{−µψ,φα sin2 ξ − hψ(φ) } 1 × + erf{ 2 2µψ,φα cos ξ − hψ(φ) } (4.32) which is symmetric about ξ = hψ(φ), hence ξ − hψ(φ) has zero expected value irrespective of φ and ψ. Therefore ξ can be decomposed as follows ξ =Φ+ν (4.33) where Φ = hψ(φ) is the deterministic transformed phase and ν is a non-Gaussian phase noise with zero mean. However, the variance of ξ is still dependent on ψ and φ. Numerical calculations showed that, for every value of ψ, the l.u.b of the CR bounds of ξ converges for reasonable SNR’s to that of discussed in the previous subsection. If ψ is not far from π/2, these two l.u.b.’s are nearly identical. Hence ideal improvement in the expectation and no improvement in 66 CHAPTER 4 the variance of the phase estimator are obtained by this transformation. Since the mapping hψ : φ → Φ is one-valued and strictly increasing in the principal interval of φ (i.e. (−π, π)), h−ψ1 is also one-valued in the principal interval (−π, π) [76]. Hence there is no ambiguity in transforming (4.32) in terms of Φ (rather than φ) as long as we consider a period of 2π. The actual expression of h−ψ1 can be given after some manipulations in the following form φ = h−ψ1(Φ) = a f [a + π] b sin(Φ) ≥ 0 otherwise. (4.34) where sin(ψ) tan(Φ) b = 1 − cos(ψ) tan(Φ) a = tan−1(b) (4.35) (4.36) and f [.] is defined in (4.6). The function tan−1 is the ordinary inverse tangent. The function hψ(.) defined in (4.18) was originally proposed as the char- acteristic function of the phase error detector of a new DPLL, the time-delay digital tanlock loop (TDTL), in an attempt to replace the HT by a time-delay in DPLLs [70, 71] (see also Chapter 3). However, it appears form the analysis in this chapter that this function has an inherent relationship to the statistical behavior of the time-delay in the presence of Gaussian noise. For TDTL, this symmetric transformation of the phase random variable would result in high performance of the TDTL in the presence of noise that is essentially equivalent to the performance when HT is utilized for reasonable values of SNR. Hence if it is possible to replace a HT by a time-delay τ (as a phase-shifter) with the above phase transformation in some signal processing system (like in DPLLs), the choice of τ would be mainly related to the noise-free performance of the system, especially for high SNR. 4.3 Conclusions A time-delay has been introduced in Chapter 3 as a substitute for the Hilbert transformer (HT) in digital phase-locked loops (DPLLs) for the purpose of phase shifting. This resulted in a major reduction in the system complexity. This chapter has shown that if this replacement is possible under noise-free conditions in some signal processing system, it would also be successful in the presence of additive Gaussian noise. For sinusoidal signals, the performance of a timedelay τ (which produces a signal-dependent phase-shift ψ = ωτ , ω being the signal radian frequency) is comparable to the performance of a Hilbert transformer (which produces a signal-independent 90o phase-shift) in the presence of independent and identically distributed (i.i.d.) additive Gaussian noise. The HILBERT TRANSFORMER AND TIME-DELAY 67 performance of the time-delay approaches that of Hilbert transformer for high signal-to-noise ratios (SNRs) and the proper choice of τ . In case τ is constant and a range of ω is expected, the performance of the time-delay is best when τ is chosen to keep the range of ψ as near as possible to π/2 throughout the expected range of the input frequencies. However, this condition on the choice of τ becomes less strict as SNR increases. Also, the performance regarding the expected value of the phase can be made the same as in the HT case by utilizing a proposed phase transformation that makes the phase probability density function (pdf) symmetric. The criterion used in this analysis is the effect of noise on the phase of the input signal and its time-delayed (or: phase-shifted) version such that similar relationship between them is maintained as in the noise-free case. In additive Gaussian noise the time-delay phase estimator can be approximated by the noise-free phase plus a non-Gaussian phase noise. The pdf of the phase noise in the case of time-delay is non-symmetric with a peak that depends on ψ, the deterministic phase φ, and SNR. However, as SNR increases, the expected value of the time-delay phase estimator approaches the true phase value and its variance substantially decreases and converges to the Cramer-Rao bound for all ranges of the effective parameters: the phase shift ψ, the true phase value φ, and the signal-to-noise ratio SNR. Chapter 5 The Time-delay Digital Tanlock Loop in Noise 5.1 Introduction In Chapter 3, a constant time-delay unit is used to produce a phase-shifted version of the incoming signal, giving rise to the time-delay digital tanlock loop (TDTL) [70, 71]. This method reduces the complexity of the phase-shifter and avoids the limitations and other problems that accompanies the 90o phaseshifter in the conventional DTL (CDTL) [13]. The main advantages of CDTL are maintained by TDTL despite its reduced structure (see Chapter 3). In Chapter 4, we analyzed the performance of the time-delay, which produces a signal-dependent phase shift, in the presence of additive Gaussian noise. We compared its performance with that of the (ideal) Hilbert transformer. The result is of general interest in signal processing. In this chapter we analyze the performance of the first- and second-order TDTLs in the presence of additive Gaussian noise [72]. Specifically, we investigate the effect of additive Gaussian noise on the sytem equation, the input and output of the phase error detector, locking conditions, and the steady-state phase errors. It is shown that, in the presence of additive Gaussian noise, the phase at the output of the phase error detector (PED) can be represented by the noise-free phase plus a non-Gaussian phase errors. Cramer-Rao bound, which was missing in the treatment of CDTL in [13], is included in this study for better understanding of the circuit performance. The mean value of the steady-state phase errors at the input and the output of the phase error detector are shown to be the same as the noise-free steady-state phase errors φss and ess, respectively, while the variance decreases as the signal-to-noise ratio (SNR) increases and converges to the Cramer-Rao bound for all values of the effective parameters: ψ, K1, and SNR. The locking ranges of the circuit parameters are 69 70 CHAPTER 5 the same as those under noise-free conditions. The best possible performance can be ensured in TDTL design when the time-delay τ is chosen to give a phase shift ψ = ωτ as near as possible to π/2 from both sides during the expected range of the input frequency ω. 5.2 Noise Analysis of the TDTL In this section we investigate the effect of additive Gaussian noise on the performance of the first- and second-order TDTLs. 5.2.1 System Equation The noise-free system analysis was given in Chapter 3. Here we present the main equations in the presence of additive Gaussian noise. The loop accepts a sinusoidal input signal y(t) having a radian frequency ω with a frequency offset ∆ω(= ω − ωo) from the nominal radian frequency ωo of the digital clock. The input signal is given by y(t) = A sin[ωot + θ(t)] + n(t) (5.1) where A is the signal amplitude, θ(t)(= ∆ωt + θo) is the phase process of the incoming signal, θo being a constant, and n(t) is additive Gaussian noise with zero mean and variance σn2. The time-delay unit introduces a constant time-delay τ in the input signal which causes a phase lag ψ(= ωτ ) proportional to input radian frequency ω. The time-delayed version of the input signal, denoted by x(t), can be expressed as x(t) = A sin[ωot + θ(t) − ψ] + n (t) (5.2) where n (t) is the phase-shifted version of n(t). At the kth sampling instant, the sampled values of y(t) and x(t) are given respectively by y(k) = A sin[ωot(k) + θ(k)] + n(k) x(k) = A sin[ωot(k) + θ(k) − ψ] + n (k) (5.3) (5.4) where θ(k) = θ[t(k)], n(k) = n(t(k)), and n (k) = n (t(k)). The sampling interval between the sampling instants t(k) and t(k − 1) is given by T (k) = To − c(k − 1) (5.5) where To(= 2π ωo ) is the nominal period of the digital clock and c(i) is the output of the digital filter at the ith sampling instant. Assuming t(0) = 0, the total THE TIME-DELAY DIGITAL TANLOCK LOOP IN NOISE 71 time t(k) up to the kth sampling instant is k k−1 t(k) = T (i) = kTo − c(i) i=1 i=0 Thus, y(k) and x(k) can be written as (5.6) k−1 y(k) = A sin θ(k) − ωo c(i) + n(k) i=0 k−1 x(k) = A sin θ(k) − ωo c(i) − ψ + n (k) i=0 The phase error φ(k) is defined as [70, 71] (see also Chapter 3) (5.7) (5.8) k−1 φ(k) = θ(k) − ωo c(i) − ψ i=0 (5.9) Now y(k) and x(k) in the presence of additive Gaussian noise can be expressed as y(k) = A sin[φ(k) + ψ] + n(k) x(k) = A sin[φ(k)] + n (k) (5.10) (5.11) The phase equation was given in Chapter 3 as follows φ(k + 1) = φ(k) − ωc(k) + Λo (5.12) where Λo = 2π ω−ωo ωo . This is the general phase equation of TDTL based on the definition of phase error. Under noise-free conditions this leads to the results shown in Chapter 3. In the presence of noise, there would be phase noise in addition to the noise-free phase process. To find this noise we should analyze the effect of noise on the input and the output of the phase error detector. 5.2.2 Statistical Behavior of TDTL Phase Error Detector Assuming that the sampled noise process {n(k)} is a sequence of i.i.d. (independent and identically distributed) Gaussian random variables with zero mean and a variance of σn2, it follows that the phase shifted noise process {n (k)} is also a sequence of i.i.d. Gaussian random variables with same mean and variance, and that the two noise processes {n(k)} and {n (k)} are independent. Hence 72 CHAPTER 5 y and x in (5.10) and (5.11) are also independent Gaussian random variables with joint probability density function (pdf) given at any sampling instant k by 1 gψ,φ(x, y) = exp 2πσn2 1 − 2σn2 (x − A sin(φ) 2 + (y − A sin(φ + ψ)2 (5.13) where for simplicity x, y, and φ are used to represent x(k), y(k), and φ(k), respectively. In CDTL the characteristic function is linear and there is no phase transformation. Hence noise analysis at the input of the Phase Error Detector (PED) is sufficient [13]. For TDTL the characteristic function of the PED, (3.14) and (3.15) in Chapter 2, performs non-linear transformation of the input phase. Hence in the next two sub-subsections we will study the statistical behavior of the phase at the input and at the output of the PED separately. A. Phase PDF at the Input of the PED In the presence of noise both y and its phase-shifted version x would be random in amplitude and phase. To find the pdf of the random phase of y and x and its relationship to the deterministic phase, we should first write x and y in terms of two new random variables R (for amplitude) and (for phase) such that the random variables x and y keep the same relationship between them as in the deterministic case. This gives in the case of TDTL the following transformations x = R sin( ) y = R sin( + ψ) (5.14) (5.15) hence the joint pdf of R and is given by [74] Pψ,φ(R, ) = g R sin( ), R sin( + ψ) R sin(ψ) (5.16) In DPLLs the concentration is on the phase rather than on the amplitude. The pdf of the input phase random variable is given by ∞ pψ,φ( ) = Pψ,φ(R, ) dR 0 (5.17) which can be given in the following form pψ,φ( ) = hψ( ) 1 2π exp{−µψ,φα} + µψ,φα cos π Hψ,φ( ) × exp{−µψ,φα sin2 Hψ,φ( ) } × 1 + erf{ 2 2µψ,φα cos Hψ,φ( ) } (5.18) THE TIME-DELAY DIGITAL TANLOCK LOOP IN NOISE 73 where α = A2/2σn2 (signal − to − noise ratio) hψ( ) = dhψ ( d ) = sin2( sin(ψ) ) + sin2( + ψ) sin(ψ) µψ,φ = hψ(φ) Hψ,φ( ) = hψ( ) − hψ(φ) erf(x) = √1 x e−t2/2dt 2π 0 (5.19) (5.20) (5.21) (5.22) (5.23) and f [.] is defined in (4.6). It is clear that pψ,φ( ) is non-Gaussian and periodic in and φ with periods of 2π. It is also non-symmetric about the plane = φ for ψ = π/2. If ψ = π/2, we have hψ( ) = 1, Hψ,φ( ) = f [ ] − f [φ] = − φ in the principal interval (−π, π), and µψ,φ = 1 see (5.19) - (5.22) , hence (5.18) reduces to the Hilbert transform case obtained for CDTL in [13]. B. Phase PDF at the Output of the PED Now the phase at the output of the phase error detector is also a nonGaussian random variable ξ given by ξ = hψ( ) = f Tan−1 sin( ) sin( + ψ) (5.24) where Tan−1 is the four-quadrant arctan function. In Chapter 3, the function hψ( ) was shown to be continuous over the principal interval (−π, π) (see Ap- pendix, Chapter 3). Also we have dhψ (φ) dφ > 0 since 0 < sin(ψ) < 1. Therefore hψ(φ) is monotonically increasing in the principal interval. Hence the pdf of ξ can be given by [74] pψ,φ(ξ) = pψ,φ h−ψ 1(ξ) d dξ (5.25) From (3.14), (5.18), (5.24), and (5.25) we obtain 1 pψ,φ(ξ) = 2π exp{−µψ,φα} + µψ,φα cos π ξ − hψ(φ) × exp{−µψ,φα sin2 ξ − hψ(φ) } × 1 + erf 2 2µψ,φα cos ξ − hψ(φ) (5.26) which is periodic in ξ of period 2π. It has a maximum at ξ = hψ(φ), hence ξ − hψ(φ) has zero expected value irrespective of φ and ψ. Therefore ξ can be 74 CHAPTER 5 decomposed as follows ξ =e+η (5.27) where e = hψ(φ) is the deterministic transformed phase and η is a non-Gaussian phase noise with zero mean. If we consider ξ in the main interval (−π, π), then the phase noise η lies in the interval (−π − e, π − e). The pdf of the phase noise η can be given explicitly as follows 1 ρψ,e(η) = 2π exp(−mψ,eα) + × mψ,eα π cos(η) exp{−mψ,eα sin2(η)} 1 + erf 2 2mψ,eα cos(η) (5.28) where mψ,e = µψ,h−ψ 1(e) (5.29) This pdf has a form similar to the result obtained for the CDTL [13], except for the additional factor mψ,e. This factor has no effect on the expected value of η which is always zero as in the CDTL case. However, the variance of η is now dependent on ψ and e. Using (5.22), (5.26), and (5.27) we have the following ψ symmetry ρψ,e(η) = ρπ−ψ,e(η) (5.30) Since the mapping hψ : φ → e is one-valued and strictly increasing in the principal interval of φ (i.e. (−π, π)), h−ψ1 is also one-valued [76]. Hence there is no ambiguity in transforming the above pdfs in terms of e (rather than φ) as long as we consider a period of 2π. The actual expression of h−ψ1 is similar to that of φss given in (5.33) with φss replaced by h−ψ1(e). Figure 5.1 shows the 2-D plot of pψ,φ(ξ) for ψ = π/3 and SNR = 10 dB and the contour plot of this pdf as compared to that of CDTL. Figure 5.2 shows ρψ,e(η) when e = 0 for different values of ψ and SNR. 5.2.3 Phase Estimation and Cramer-Rao Bounds Since the random phase ξ at the output of the PED gives the deterministic phase e plus a phase noise as in (5.27), it can be used as a phase estimator eˆ. As η = ξ − e has zero expected value for all ψ and φ, this estimator is unbiased THE TIME-DELAY DIGITAL TANLOCK LOOP IN NOISE 75 and therefore its variance var(eˆ) is lower-bounded by the Cramer-Rao bound [75], which is given in this case by var(eˆ) = E(ξ − e)2 ≥⎧ 1 ⎫ ⎨ E⎩ ∂ ln{pψ,h−ψ1(e)(ξ)} ∂e 2⎬ ⎭ 1 = π−e −π−e ∂ ln{pψ,h−ψ1(e)(ξ)} ∂e 2 pψ,h−ψ1(e)(ξ) dξ = CRψ(e) (5.31) where E is the expectation functional. Since the mapping h−ψ1 is one-valued in the principal interval as shown in the previous subsection, there is no ambiguity in evaluating the above integral as long as we consider a period of 2π. Numerical calculations showed that the variance of ξ is approximately identical with the Cramer-Rao (CR) bound for reasonable values of SNR. Hence we will use CR bounds for the purpose of performance assessment and comparison. It is evident from (5.31) that the CR bound is dependent on ψ = ψo/W , e, and SNR. Hence in TDTL case we expect ranges of CR bounds rather than single CR bound for CDTL. For every value of ψ, CR bound can go below the CDTL case for some values of e. However, for every ψ, the performance is measured by considering all the range of CR bounds for all possible e. In this case we consider the least upper bound {CRψ(e) | − π < e ≤ π}. Therefore the (ideal) CDTL outperforms TDTL in the presence of noise in all cases. As ψ approaches π/2, the range of CR bounds approach the (ideal) CDTL CramerRao bound. Hence the difference in performance is less evident as ψ approaches π/2. It follows that for the best possible performance in the presence of noise we should choose the time-delay τ such that we keep ψ = ωτ as near as possible to π/2 throughout the expected range of ω which is supposed to be fit inside the locking range of TDTL for some value of ψo = ωoτ (that decides the value of ωo) and a low value of K1. The natural choice in this case is {(ω1 + ω2)/2}τ = π/2. Figure 5.3 shows the ranges of CR bounds for different values of ψ = ψo/W and SNR. It is apparent that the range of the CR bounds approaches the CDTL bound as ψ approaches π/2. According to the above performance measure, the (ideal) CDTL outperforms TDTL in the presence of noise in all cases when the variance is considered, while the performance is similar regarding the expected value of the phase error. However, the difference in performance is less evident 76 CHAPTER 5 3 2 ψ = π/3 SNR = 10 dB 1 ξ (rad) 0 −1 −2 −3 −3 −2 −1 0 1 2 3 e = h [φ] (rad) Figure 5.1: Above: the probability density function of the phase random variable ξ at the output of the phase error detector (PED) of TDTL, pψ,φ(ξ), for ψ = π/3 and SNR = 10 dB. Note that φ and e = h[φ] are the deterministic phase errors at the input and the output of the PED, respectively. Below: contour plot of the above pψ,φ(ξ) at the level of 0.5 for one period in the (e, ξ) plane (solid line) as compared to the that of CDTL (dashed line). Dotted line is the ξ = e line. As SNR increases, the solid contour plot becomes two parallel lines as in the CDTL case. as ψ approaches π/2. Note that this comparison is built on considering an ideal Hilbert transformer in CDTL, without taking into account the approximations and other practical problems associated with the implementation of the Hilbert transformer that are definitely reflected on the performance of the practical CDTL. THE TIME-DELAY DIGITAL TANLOCK LOOP IN NOISE ρψ,e(η) 3 2.5 2 1,5 1 0.5 0 −3 ψ = π/3 e = h[φ] = 0 −2 −1 SNR = 15 dB SNR = 10 dB SNR = 5 dB 0 1 2 η (rad) 77 3 ρψ,e(η) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 −3 SNR = 10 dB e = h[φ] = 0 −2 −1 0 η (rad) ψ = π/2 (CDTL) ψ = π/3 & 2π/3 ψ = π/5 & 4π/5 1 2 3 Figure 5.2: The probability density function ρψ,e(η) of the phase noise η at the output of the phase error detector (PED) of TDTL when e = h[φ] = 0. Above: ρψ,e(η) for ψ = π/3 and different values of SNR. Below: ρψ,e(η) for SNR = 10 dB and different values of ψ. The expected value of η is always zero, but the variance is dependent on ψ and e. Similarity between curves is due to the ψ symmetry of ρψ,e(η). 5.2.4 Statistical Behavior of the TDTL in Gaussian Noise In this subsection we study the steady-state pdf, expectation and variance of the modulo (2π) phase error at the input and the output of the phase error detector (PED) for the first and second-order TDTLs. 78 CHAPTER 5 CR bounds, dB −8 −10 −12 −14 −16 −18 −20 −22 −24 −26 10 11 12 13 14 15 16 17 18 19 20 Input SNR (dB) Figure 5.3: Ranges of the Cramer-Rao bounds of the phase estimator ξ at the output of the phase error detector of TDTL for ψ = π/3 & 2π/3 (the area between dashed lines), and ψ = 3π/7 & 4π/7 (the area between dotted lines). The range is found numerically for each ψ by calculating the CR bounds for the two extreme values of mψ,e in the principal interval −π < e ≤ π. Similarity in the CR bounds between ψ and π − ψ is due to the ψ symmetry of the phase pdf. The solid line represents the CR bound of the (ideal) CDTL phase estimator, which is independent of the output phase true value e. As ψ approaches π/2, the range of the CR bounds approaches the CDTL case. A. First-Order TDTL (i) Steady-State PDFs of the PED Input and Output Phase Errors: Since the two noise processes {n(k)} and {n (k)} discussed in Subsection (5.2.1) are independent, it follows that there effect on the phase would result in noise samples {η(k)} that are independent for different sampling instants k. The system equation of the first-order TDTL in the presence of noise can be obtained from (3.16) and (5.27) as follows φ(k + 1) = φ(k) − K1hψ[φ(k)] + Λo − K1η(k) (5.32) where φ(k) is the phase error at the input of the phase error detector (PED) and hψ(φ(k)) = e(k) is the phase error at the output of the PED. Following the same analysis as in [13] and [43] we reach at the following Chapman-Kolmogorov THE TIME-DELAY DIGITAL TANLOCK LOOP IN NOISE 79 iterative equation ∞ pψ,k+1(φ|φo) = qψ,k(φ|u)pψ,k(u|φo)du −∞ (5.33) where φo = φ(0), pψ,k(φ|φo) is the pdf of φ(k + 1) given φo, and qk(φ|u) is the pdf of φ(k + 1) given φ(k) = u, which can be given in the case of TDTL by qψ,k(φ|u) 1 = 2πK1 exp(−µψ,uα) + 1 µψ,uα cos φ − ν K1 π K1 × 1 + erf 2 2µψ,uα cos exp −µψ,uα sin2 φ−ν K1 φ−ν K1 (5.34) where ν = u − K1hψ[u] + Λo and the range of φ is the interval (u + Λo − K1π, u + Λo + K1π). The above iteration can be solved numerically by the Weinberg-Liu method explained in [13] and [43] to get the pdf of the steady-state phase error at the input of the PED, pψ(φ). The steady-state pdf of the phase error at the output of the PED, P(e) can be given by Pψ(e) = pψ h−ψ1(e) |dφ/de| (5.35) where e = hψ(φ). From the above analysis we can deduce that the steadystate input and output phase error pdfs, pψ(φ) and Pψ(e), are dependent on Λo = 2π(1 − W )/W , ψ = ψo/W , K1 = K1/W , and SNR. The CDTL phase error pdf was dependent on Λo, K1, and SNR only [13]. (ii) Steady-State Expectation of the PED Input and Output Phase Errors: In the steady-state we have E(φ(k + 1)) = E(φ(k)) at the input of the phase error detector (PED). Also we have E(e(k + 1)) = E(e(k)) at the PED output. It is worth noting that the steady-state phase errors φss and ess are random variables in the presence of noise. Taking the expectation E of both sides of (5.32) under steady-state condition and solving for E(φss) we have E(ess) = E(hψ[φss]) = {Λo − K1E(η)}/K1 (5.36) where ess is the steady-state output of the PED. Since ρψ,φ(η) is symmetric about zero, we have E(η) = 0, hence we obtain E (ess) = Λo/K1 (5.37) 80 CHAPTER 5 which is the same as the noise-free expression of ess given by (3.33). No additional condition in the presence of noise is implied by the above equation on λ = Λo/K1. Hence only the noise-free condition on λ [given in (3.21)] is effective. It is not straightforward to prove that the expectation functional E and the function hψ can be interchanged. However, according to the TDTL structure, a steady-state condition at the input of the PED implies a steady-state condition at the output of the PED. Therefore, the steady-state phase error at the output of the PED, E(ess), should be in the following form E(ess) = hψ[E(φss)] (5.38) Using (3.14), (5.37), and (5.38) we obtain the following expression for E(φss) by manipulations similar to those used in obtaining φss in Section (3.3.1-C) E(φss) = α f [α + π] β sin(λ) ≥ 0 otherwise. (5.39) where λ = Λo/K1, α and β are defined in (3.23) and (3.25). This is the same as the noise-free expression of φss given by (3.33). Hence in additive Gaussian noise, the first-order TDTL does not lose tracking of the input phase since the expected value of the phase error equals its deterministic value. (iii) Steady-State Variance of the PED Input and Output Phase Errors: Unlike CDTL, the variance of the steady-state input and output phase errors, φss and ess, cannot be given in closed-form expressions in terms of E(η2) and K1. However, it can be obtained numerically from the steady-state pdfs pψ(φ) and Pψ(e) obtained in Subsection (5.2.4 - A (i)) above. For all values of ψ, the input variance and the output variance are decreasing functions of SNR. They are functions of ψ, K1, and SNR. Numerical calculations have shown that, as in the case of CDTL, Λo only affects the expectation and has no effect on the variance. Also numerical calculations have shown that, for any ψ and SNR, the variance of the steady-state input and output phase errors is always positive inside the noise-free range of the effective parameters Λo and K1. Hence no additional conditions are implied by the variance of the phase errors in the presence of noise. Figure 5.4 shows the variance of the steady-state phase error at the output of the PED, var(ess), of the first-order TDTL with ψ = π/3 and ψ = 2π/5 as compared to that of CDTL for the same parameters Λo = 0 and K1 = 0.7 and 1. As ψ approaches π/2, TDTL variance approaches that of CDTL. Both CDTL THE TIME-DELAY DIGITAL TANLOCK LOOP IN NOISE 81 and TDTL has E(ess) exactly at the noise-free value of ess, which is Λo/K1, for all values of the parameters ψ, Λo and K1. Note that the curves related to ψ = 2π/3 and ψ = 3π/5 are the same as the curves related to ψ = π/3 and ψ = 2π/5, respectively, due to the ψ symmetry of the phase pdf as given in (5.30). B. Second-Order TDTL We now discuss briefly the behavior of the second-order TDTL in noise since it can be obtained by analysis similar to that of the first-order TDTL discussed earlier. In the presence of noise the system equation of the second-order TDTL can be obtained using (3.13), (3.35), and (5.27) as follows φ(k + 2) = 2φ(k + 1) − φ(k) − rK1{h[φ(k + 1)] + η(k + 1)} + K1{h[φ(k)] + η(k)} (5.40) Applying analysis similar to that in Subsection (5.2.4-A) above, we can obtain the steady-state pdf of the phase error at the input and the output of the phase error detector (PED). Taking the steady-state expectation of both sides of the above equation and noting that E(η) = 0 at any sampling instant k, we obtain the expected value of the phase error at the output of the PED as follows E(ess) = 0 (5.41) which is the same as the noise-free value of ess. By a reasoning similar to that in the previous Subsection, we obtain the expected value of the phase error at the input of the PED as follows E(φss) = 0 (5.42) which is also the same as the noise-free value of φss. As in the case of the first-order TDTL, the variance of the steady-state phase errors φss and ess can be obtained numerically. It is now dependent on ψ, K1, r, and SNR. Numerical calculations have shown that the variance is not affected by Λo and decreases as SNR increases or K1 decreases. Also it decreases as r decreases. The variance is positive for all values of the parameters in the noise-free locking range, hence no additional conditions are implied on the second-order TDTL in the presence of Gaussian noise. 5.3 Conclusions In this chapter we have analyzed the performance of the time-delay digital tanlock loop (TDTL) in the presence of additive Gaussian noise. The conventional 82 CHAPTER 5 variance (ess), dB −6 −8 −10 −12 + + TDTL, ψ=π/3, K1′ = 1 TDTL, ψ=π/3, K1′ = 0.7 . .x x TDTL, ψ=2π/5, K1′ = 1 TDTL, ψ=2π/5, K1′ = 0.7 −14 −16 −18 −20 −22 −24 CDTL, K1′ = 1 CDTL, K1′ = 0.7 −26 10 11 12 13 14 15 16 17 18 19 20 Input SNR (dB) Figure 5.4: Variance of the steady-state phase error, ess, at the output of the phase error detector of the first-order TDTL with ψ = π/3 and ψ = 2π/5 as compared to that of CDTL for the same parameters Λo = 0 and K1 = 0.7 and 1. Note that Λo decides the expected value of ess and has no effect on the variance. As ψ approaches π/2, TDTL variance approaches that of CDTL. Both CDTL and TDTL has E(ess) exactly at the noise-free value of ess, which is Λo/K1. Note that the curves related to ψ = 2π/3 and ψ = 3π/5 are the same as the curves related to ψ = π/3 and ψ = 2π/5, respectively, due to the ψ symmetry of the phase pdf. digital tanlock loop (CDTL) introduced significant advantages over other sinusoidal DPLLs, except for the complexity of the loop, and TDTL has the same merits with a reduced complexity. We have shown in Chapter 3 that although TDTL has a reduced structure as compared to the CDTL, it has a performance comparable to that of CDTL under noise-free conditions. In this chapter we have shown that the performance of TDTL in the presence of additive Gaussian noise is also successful and comparable to that of CDTL, especially under careful choice of the circuit parameters. Under the steady-state condition of operation, the first and second-order TDTLs have expected values of the phase error at the input and the output of the phase error detector (PED) exactly the same as their noise-free values, while the variance of the phase error is a decreasing function of the signal-to-noise ratio (SNR) and the loop parameter K1 (in addition to r for the second-order TDTL). The variance also decreases and approaches CDTL case as the phase shift ψ (introduced by the time-delay) approaches π/2 from both sides. Hence TDTL does not lose tracking of the input phase in additive Gaussian noise in all cases. However, it is better in TDTL design to THE TIME-DELAY DIGITAL TANLOCK LOOP IN NOISE 83 choose a time-delay τ that gives a phase shift ψ = ωτ as near to π/2 as possible during the expected range of the input frequency ω. No change in TDTL locking ranges is implied by the presence of Gaussian noise. Chapter 6 Architectures for Improved Performance 6.1 Introduction This chapter presents the simulation results of the conventional first-order and second-order TDTLs. The simulations show the behavior of both loops as they get subjected to various frequency disturbances. It also shows a variety of modified first-order TDTL architectures that are designed to enhance the performance of the conventional loop. The performance of the modified architectures is compared with that of the conventional first-order loop through a study of the transient responses and phase plane plots as the loops get subjected to large frequency steps. Similarly, modified second-order architectures are discussed and their performance is compared with the conventional second-order TDTL. Finally a variable order TDTL architecture that combines the desirable features of the first-order and the second-order is presented and its behavior is studied through simulation. 6.2 Simulation Results of First-Order TDTL The first-order loop was tested by subjecting it to negative as well as positive input frequency steps. A negative step results in an input signal with frequency lower than that of the free running DCO, while a positive step has the opposite effect. An example of a negative frequency step is shown in Figure 6.1. In this case, the time delay and free running frequency of the DCO have been arranged so that the initial phase lag parameter ψo = ωoτ = π/2, and the gain has been chosen as K1 = G1ωo = 1.5. When an input with a frequency ratio W = ωo/ωi = 1.6 is applied to the loop (i.e., an input frequency which is 1.6 85 86 CHAPTER 6 Figure 6.1: Top: Negative step input. Bottom: Loop response to the negative frequency step. times less than the free running frequency), the loop converges to a steadystate of phase error since the input is within its locking range. This scenario is demonstrated in Figure 6.1. Initially, an input of the same frequency as ωo is applied, and it is clear that the phase error converges to zero before the negative frequency step occurs as shown in the bottom graph in Figure 6.1. Once the frequency change is applied, the phase error assumes a negative value owing to the fact that the input is of a less frequency. The TDTL then converges to a steady state phase error, i.e., the loop is in a lock-state and the DCO is tracking the input frequency. The convergence to a non-zero steady state phase error is a unique property of the first order loop. This is caused by the proportional filter, which is incapable of providing sufficient error signal to drive the phase error to zero. The sampling process of the DCO is shown in Figure 6.2, where it is clear that the DCO locks to positive-going zero crossing before applying the frequency step, and varies its period until it matches the new input frequency after the frequency change is applied. The effect of converging to a non-zero phase error is evident from the phase offset positive-going zero crossings and the DCO pulses. The first-order loop has also been tested for positive frequency steps, i.e., for input signals with frequency higher than ωo, and an example is shown in ARCHITECTURES FOR IMPROVED PERFORMANCE 87 Figure 6.2: Sampling process of the first-order TDTL (negative step). Figure 6.3. The time delay τ and the free running frequency ωo have been arranged such that ψo = π/3, and the gain has been chosen as K1 = G1ωo = 1.3. A frequency step with W = ωo/ωi = 0.5 (i.e., twice ωo) is applied to the loop, and as shown in Figure 6.3, the phase error reaches a positive steady state value indicating that the loop is in-lock with the input frequency. The above results demonstrate that the TDTL has fast acquisition as it is capable of locking to an input signal within a few samples. It also has a wide locking range which enables it to deal with large frequency steps as show in Figures 6.1 and 6.3 above. However, due to the nonlinear characteristics of the TDTL optimality cannot be achieved in terms of the loop parameters. In other words, the advantageous performance characteristics, such as the fast acquisition and the wide locking range, are dependent on a set of parameters such as the loop gain K1 and the nominal phase lag ψo. Tuning these parameters however, is based on trial and error and there is always a trade-off between the wide locking range and the fast acquisition characteristics [82]. The next section presents different modifications of the loop that enable the control of the loop gain and phase lag and hence improve its performance. The nonzero steady state phase error of the first order TDTL, as shown in Figures 6.1 and 6.3, is due to the loop filter which is only a gain block in this 88 CHAPTER 6 Figure 6.3: Top: Positive step input. Bottom: Loop response to the positive frequency step. case. This disadvantage can be eliminated by increasing the order of the loop to second order. However, this will be at the expense of a reduction in the loop locking range. Therefore, depending on the application in which the loop is to be used the appropriate order of the loop should be selected. For example, the nonzero steady state phase error of the first order TDTL would indicates the existence of a phase offset between the input and the recovered carrier, hence violating the conditions of coherent demodulation [3, 80] and effectively precluding its use in such applications. 6.3 Improved First-Order TDTL Architectures This section discusses modified first-order TDTL architectures that overcome some of the loop limitations and improve it’s performance in terms of speed and locking range width. These modifications are based on the use of finite-state machines to control particular loop parameters and hence achieve the desired performance. The proposed architectures and their associated simulation results are described in the subsections below. ARCHITECTURES FOR IMPROVED PERFORMANCE 89 x1(t) d(k) Delay 1 Finite State Machine (FSM) Sampler 1 x(k) Delay 2 x2(t) y(t) DCO Digital Filter Phase Detector arctan (X/Y) y(k) Sampler 2 Figure 6.4: Variable delay TDTL architecture. 6.3.1 Delay Switching Architecture Since the value of the time delay is of great influence on the convergence behavior of the loop. The conflicting requirements of fast acquisition and wide locking range necessitate the inclusion of more than one time delay [82, 83]. The structure of the variable delay TDTL (VD-TDTL) is shown in Figure 6.4. It is clear that it resembles the TDTL discussed earlier; however, the time delay unit has been exchanged with a dual delay structure, which is controlled by a finite state machine (FSM) block. The time delay units generate two phase shifted versions of the input signal, which are given by x1(t) = A sin [ωot + θ(t) − ψ1] (6.1) x2(t) = A sin [ωot + θ(t) − ψ2] (6.2) The control signal d(k), which is the output of the FSM, decides which of the signals given in (6.1) and (6.2) are to be passed to Sampler 1 in order to produce the following discrete time signal x(k) = A sin [ωot(k) + θ(k) − ψi] (6.3) where i is a subscript indicating the time delay block. The signal in (6.3) can be redefined in terms of the phase error as x(k) = A sin [φ(k)] (6.4) 90 CHAPTER 6 and therefore, the error signal can be re-written as e(k) = f Tan−1 sin [φ(k)] sin [φ(k) + ψi] (6.5) where Tan−1 is the 4-quad arctan. Since the proposed variable delay TDTL is implemented as a first-order loop, the system difference equation will be the same as that given in (3.16), and consequently the locking range can be found by solving the following inequality: 2 |1 − W| < K1 < 2W sin2(α) + sin2(α sin(ψoi) + ψoi) (6.6) where ψoi is the nominal phase shift. In the proposed system, the time-delay units have been arranged so that ψo1 = π/2 and ψo2 = π/3, which will produce the locking range curves shown in Figure 6.5. This will ensure a symmetric tracking range from W = 0.5 up to W = 1.5. Hence, the system will exploit the wide range and fast acquisition characteristics of ψo1 in the area where W > 1, and of ψo2 in the area where W < 1. The loop gain K1 = 1.13 has been selected to ensure good performance and wide locking range for both values of the time-delay. The states of the FSM are defined by the phase error and the control signal d(k). If the system is subjected to a frequency step causing the input signal frequency to go higher than ωo, i.e. W < 1, and the phase error is greater than a predefined threshold ε1 > 0, the control signal d(k) will allow the signal x2(t) to pass to Sampler 1. If the system is subjected to a frequency step which causes the input frequency to go lower than ωo, i.e., W > 1, the FSM will monitor the phase error until it is below another threshold ε2 < 0, then the control signal d(k) will allow the signal x1(t) to pass to Sampler 1. The parameters ε1 and ε2 allow fine-tuning of the FSM behavior for any intended region of operation of the loop in order to ensure fast acquisition behavior. Figure 6.6-a shows the transient response of the single delay loop with ψo1 = π/2 and K1 = 1.13 to a frequency step with W = 0.5. Since this mode of operation is outside the locking range of the loop, the phase error diverges to an unstable state, thus throwing the loop in the unlocked mode. This is also illustrated in Figure 6.6-b, which shows the phase plane plot for the same frequency step; where it is clear that the phase does not converge to a steady state value. The result of applying the same frequency step to the same TDTL but with ψo2 is shown in Figure 6.7-a. It can be clearly seen that the phase error settles within a few samples. The same result can also be depicted by examining the phase plane plot of Figure 6.7-b, which indicates the convergence of the phase error. ARCHITECTURES FOR IMPROVED PERFORMANCE 91 Figure 6.5: Locking range of first-order TDTL with different values of ψo, the tracking range is the bold line (1). 92 CHAPTER 6 (a) (b) Figure 6.6: (a)Transient response of the single delay TDTL with ψo1 = π/2 and K1 = 1.13 to a frequency step with W = 0.5 (b) Phase plane behavior. ARCHITECTURES FOR IMPROVED PERFORMANCE 93 (a) (b) Figure 6.7: (a)Transient response of the single delay TDTL with ψo2 = π/3 and K1 = 1.13 to a frequency step with W = 0.5 (b) Phase plane behavior. 94 CHAPTER 6 Figure 6.8: Transient response of the single delay TDTL with ψo2 = π/3 and K1 = 1.13 to a frequency step with W = 1.25. Another scenario is illustrated in Figure 6.8 with a negative frequency step. It is clear that the transient response of the single delay TDTL with ψo2 = π/3 and K1 = 1.13 to a frequency step with W = 1.25 is poor as the phase error is not converging to a steady state value within an acceptable time. Whereas the transient response of the same TDTL with ψo2 = π/3 for the same frequency step, demonstrated in Figure 6.9, shows that the phase error converges to a steady state value in two samples. The merit of using the VD-TDTL is that it is capable of distinguishing, in both of the aforementioned situations, the delay that yields the optimum performance. Thus, the previous graphs with steadystate phase error are corresponding to the response of the VD-TDTL under the same operating conditions. 6.3.2 Adaptive Gain Architecture If the conventional TDTL is thrown out of lock due to a sudden change in the input frequency, it will stay out of lock unless an external signal forces the digitally controlled oscillator (DCO) back into the locking region. In order to ensure stable operation of the TDTL, it has to keep operating within the ARCHITECTURES FOR IMPROVED PERFORMANCE 95 Figure 6.9: Transient response of the single delay TDTL with ψo1 = π/2 and K1 = 1.13 to a frequency step with W = 1.25. 96 y(t) x(t) Delay Sampler 1 x(k) FSM g(k) DCO Digital Filter y(k) Sampler 2 CHAPTER 6 Phase Detector arctan (X/Y) Figure 6.10: Structure of the adaptive gain TDTL. locking boundaries, and this can be achieved by adapting the gain in response to out-of-range frequency signals [84]. The proposed architecture to achieve this is shown in Figure 6.10. The adaptive TDTL in Figure 6.10 is created by utilizing a variable gain digital filter, which is controlled by means of an appropriate FSM. Choosing the nominal phase lag of the loop ψo to be equal to π/2 ensures the best state of linearity in the phase detector output. Thus, the phase error is approximately proportional to the radian frequency of the input, and can be used as an indicator of the operating point of the loop within the locking boundary shown in Figure 6.11. The scenario given below explains the operating principles of the adaptive gain TDTL. Assuming that the first-order loop is initialized with a loop gain K1 of 0.5, this has the advantage of reducing the TDTL performance degradation due to noise, since the variance of the phase error is a decreasing function of the loop gain K1 and the signal to noise ratio [82]. The locking range boundary indicates that the loop can acquire the frequencies of all inputs bounded by the points A1 and A2 in Figure 6.11. However, it is very likely that the loop will be subjected to some disturbances or large frequency steps that will throw the system out of lock, e.g., the system will be thrown to point B or D. Normally, this will not be recovered by the conventional TDTL and the loop will carry on in the unlocked state. However, the adaptive gain TDTL in Figure 6.10 senses, using the phase error, that the operating point has been moved outside the locking boundary, ARCHITECTURES FOR IMPROVED PERFORMANCE 97 Figure 6.11: Locking boundary of the adaptive TDTL. and therefore the FSM updates the gain of the digital filter, thereby moving to points C or E, which are inside the locking boundary of the system. The overall locking range of this implementation has been extended symmetrically from W = 0.6 to W = 1.4. The mathematical analysis of the adaptive gain TDTL is similar to that of the original TDTL discussed earlier. The improved loop in Figure 6.10 was tested by subjecting it to large frequency steps (large phase errors) that force the system to go outside the nominal locking range, such as points B and D, in Figure 6.11. In both test cases the system senses the phase error through its FSM and accordingly adjusts the gain of the digital filter in such a way that out of lock operating points B and D are pulled to in lock points C and E respectively. The settling behavior of the loop at points B and C is shown in Figure 6.12. The locking behavior at the same points is also demonstrated by the phase plane plots in Figure 6.13. The plots show that when the loop is at point C it converges into a steady state condition within an acceptable number of samples, whereas when the loop is at point B it stays in the unlocked condition. When the loop is subjected to a large step in frequency causing the system to go outside the locking range, e.g. point D in Figure 6.11, the system senses 98 CHAPTER 6 (a) (b) Figure 6.12: (a) Transient response of the system at point B. (b) Transient response of the system at point C. ARCHITECTURES FOR IMPROVED PERFORMANCE 99 (a) (b) Figure 6.13: (a) Phase plane of unsettled system at point B. (b) Phase plane of settled system at point C. 100 CHAPTER 6 this error through the FSM and updates the gain of the digital filter to bring the operating point within the locking region at point E. The settling time of the loop at points D and E are shown in Figure 6.14, and the phase plots are illustrated for the same operating points in Figure 6.15. 6.3.3 Combined Delay Switching and Adaptive Gain The previously mentioned methods of TDTL enhancement offer attractive aspects in terms of locking range and acquisition characteristics. However, the outcome of improvement can be increased by combing the two techniques into the TDTL, which yields a loop with faster acquisition, wider locking range and more resilience to frequency disturbances. The proposed loop architecture is depicted in Figure 6.16, where as can be seen it is a combination of the two previously mentioned architectures [85]. However, the FSM is being fed by discrete time outputs of the samplers, namely x(k) and y(k). On the other hand, the gain of the digital filter and the active time delay unit is controlled by the g(k) and d(k) respectively, which are the output signals of the FSM. Signals x1(k) and x2(k) are the same as those described by (6.1) and (6.2). Following the same analysis, the difference equation of the system is given by φ(k + 1) = φ(k) − ωGsh [φ(k)] + Λo (6.7) Where Gs denotes the variable gain of the digital filter, and s is a unique code corresponding to each state of the FSM. The locking range can be acquired by solving the inequality given by (6.6), resulting in a locking range which is similar to that of the conventional TDTL in Chapter 3. The operating point of the TDTL is defined in terms of the frequency ratio W , the nominal phase shift ψoi and the loop gain K1. Since the two latter parameters are usually predefined, the changes in the operating point are dependent on an external parameter, which is the frequency of the input signal; this will move the operating point either inside or outside the locking boundary of the loop. The resilience of the loop to frequency disturbances is increased in the adaptive gain and delay TDTL by introducing two extra degrees of freedom, namely the digital filter gain Gs and the nominal phase shift Ψoi. These will be tuned by the FSM to ensure that the loop operates within the locking range of the loop regardless of changes in the input frequency. The time delay units have been arranged so that ψo1 = π/2 and ψo1 = π/3, and areas of operation have been mapped to the states of the FSM, where each state will have a unique gain Gs and phase shift Ψoi. The system will switch between the delays according to the frequency of the input, so that ψo1 operates in the area where W > 1, ARCHITECTURES FOR IMPROVED PERFORMANCE 101 (a) (b) Figure 6.14: (a) Transient response of the system at point D. (b) Transient response of the system at point E. 102 CHAPTER 6 (a) (b) Figure 6.15: (a) Transient response of the system at point D. (b) Transient response of the system at point E. ARCHITECTURES FOR IMPROVED PERFORMANCE 103 x1(t) Delay 1 d(k) Sampler 1 x(k) FSM Delay 2 x2(t) g(k) y(t) DCO Digital Filter Phase Detector arctan (X/Y) y(k) Sampler 2 Figure 6.16: Adaptive gain and delay TDTL. and ψo2 operates in the area where W < 1, and this is mainly due to the wide range offered by each delay in its defined region of operation. Therefore, the overall locking range of the proposed system will increase and a new locking boundary can be defined as shown in Figure 6.17, which also shows the tracking range of the system (the bold line inside the locking boundary). It encapsulates the different possibilities of loop operation points. It is clear that this range extends from W = 0.4 up to W = 1.65. The FSM ensures mapping each change of frequency to its desired operating point within the tracking range. Two main measures are provided by the FSM to counter the effect of frequency changes, the first is to set the active time delay, and the second is to make any necessary changes in the value of the digital filter gain. The FSM criteria for state transition is based on the signs of the signals x(k) and y(k), which provide meaningful information about the frequency of the input signal. To illustrate the improvement in the system performance that the architecture in Figure 6.16 gives, a frequency step of W = 0.4 is applied to the original TDTL in Figure 3.1 with ψo1 = π/2 and K1 = 1. This drives the loop into the unlocked state, and the therefore the phase error will assume an unstable behavior as illustrated in Figure 6.18. When the same frequency input is applied to the adaptive gain and delay TDTL, it yields the transient response illustrated in Figure 6.19-a. As the figure shows, the phase error oscillates during the first two samples, indicating an out-of-range frequency, however, the FSM then forces the system back into the locked state, which is clearly shown as 104 CHAPTER 6 Figure 6.17: Unified locking range of the adaptive gain and delay TDTL. ARCHITECTURES FOR IMPROVED PERFORMANCE 105 Figure 6.18: Transient response of the single delay TDTL with ψo1 = π/2 and K1 = 1 to a frequency step with W = 0.4. the phase error converges to a steady state value afterwards. The phase plane portrait shown in Figure 6.19-b also supports this result. Another test case is conducted at the low frequency part. Figure 6.20-a demonstrates the transient response due to a frequency step of W = 1.65, where the loop responds rapidly and converges to a steady state phase error within five samples, two of which are consumed by the FSM to decide on the operating point. The phase plane portrait shown in Figure 6.20-b also demonstrates this result. 6.3.4 Sample Sensing Adaptive Architecture Figure 6.21 shows an improved TDTL architecture that uses an error-sensing block to monitor the samples in the delayed path of the loop before they get fed to the arc-tan phase detector. The error-sensing block includes an FSM whose output G(k) is used to control the gain of the digital filter. The appropriate adjustment of the filter gain ensures that the loop remains in lock when subjected to large frequency disturbances that would otherwise result in out of lock condition. The error-sensing block has a fast response, as it does not need to wait for the arc-tan phase detector to finish processing a sample. Overall the new loop offers enhanced performance compared with the original TDTL designs [105]. 106 CHAPTER 6 (a) (b) Figure 6.19: (a) Transient response, adaptive gain and delay TDTL response to a frequency step with W = 0.4. (b) Phase plane behavior. ARCHITECTURES FOR IMPROVED PERFORMANCE 107 (a) (b) Figure 6.20: (a) Adaptive gain and delay TDTL transient response to a frequency step with W = 1.65. (b) Phase plane behavior. 108 y(t) CHAPTER 6 Time Delay x(t) Sampler I Digital Controlled Oscillator (DCO) x(k) Error Sensing Block c(k) G(k) Digital Filter e(k) Phase Detector [tan -1 (x/y)] Sampler II y(k) Figure 6.21: Sample sensing adaptive TDTL. Figure 6.22 depicts the locking boundary of the sample sensing adaptive TDTL (SS-ATDTL) with ψo = π/2. In the original TDTL, if the system is thrown out of lock due to a sudden change in the input frequency it will stay out of lock unless an external signal forces the DCO back into the locking region. In the case of the system shown in Figure 6.21, the error-sensing block with its adaptive capabilities ensures that the loop stays in a locked state even if it is subjected to large phase errors. The behaviors of the SS-ATDTL and the original TDTL were studied assuming that the initial stable point of operation for each loop is point A in Figure 6.22, where W = 1 and K1 = 0.5. This choice would result in a good signal to noise ratio for the overall system. Subjecting the conventional TDTL to frequency disturbances that drive to say point C or D in Figure 6.22 will drive the system out of lock. However, subjecting the SS-ATDTL to the same disturbances will make the error sensing block generate an error signal that corresponds to a unique step value of the input frequency, consequently the FSM adjusts the digital filter gain to a new value Gs that forces the DCO to adjust to the new frequency before the system goes out of lock. The same process is followed for both positive and negative steps, that is for W < 1 and W > 1 respectively. For example, if the proposed system gets driven by a frequency step to point C in Figure 6.22 where K1 = 0.5, it regains stability by increasing G1 until K1 = 1 and hence move the system to point B. Similarly, if the system is driven to point D it stabilizes by moving to point E. As can be seen in Figure 6.22, both points B and E are within the locking range of the loop. ARCHITECTURES FOR IMPROVED PERFORMANCE 109 ωo G 1 = K 1 gain, 6 5 4 3 2 1 0 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Frequency ratio, W = ωo / ω Loop Figure 6.22: The locking range of the TDTL at ψo1 = π/2. An example of comparing the SS-ATDTL and the original TDTL responses to a positive frequency step is shown in Figure 6.23. In this test, the time delay and free running frequency of the DCO have been arranged so that ψo = π/2, and the gain of the TDTL has been chosen as K1 = 0.5, and an input frequency step of 0.3 with W = 0.769. Initially the frequency of the input was equal to ωo, therefore the phase error settled at zero. Then a positive frequency step was applied to the loop, causing the phase error to jump to a positive value indicating that the input frequency is higher than the loop frequency. The loop then locks to the new input frequency but with a phase shift settling at a constant positive value. Figure 6.23 shows that the SS-ATDTL locks to the input step faster than the conventional TDTL but with a bit larger steady state phase error value. The phase plane plots in Figure 6.24 and the DCO sampling process shown in Figure 6.25 confirm the above results. The figures give an indication of the relative speed of locking. Figure 6.25 also shows the constant phase error in the two loops, which is due to the fact the both loops are of the first order type. 110 CHAPTER 6 (a) (b) (c) Figure 6.23: (a) Positive frequency step. (b) Original TDTL response. (c) SSATDTL response. ARCHITECTURES FOR IMPROVED PERFORMANCE 111 (a) (b) Figure 6.24: Phase plane plots: (a) Conventional TDTL (b) ATDTL. 112 CHAPTER 6 Input signal + DCO pulses 1 0.5 0 −0.5 −1 26 27 28 29 30 31 32 33 Time(s) (a) Input + DCO pulses 1 0.5 0 −0.5 −1 26 27 28 29 30 31 32 33 34 Time(s) (b) Figure 6.25: DCO Sampling process of (a) original TDTL (b) SS-ATDTL. ARCHITECTURES FOR IMPROVED PERFORMANCE 113 m(t) L.P.F. f(t) F.S.M. Time Delay x(t) Sampler I x(k) g(t) y(t) c(k) e (k) DCO Digital Filter tan-1[x(k)/y(k)] Sampler y(k) II Figure 6.26: Early error sensing adaptive TDTL. 6.3.5 Early Error Sensing Adaptive Architecture This section describes an early error sensing adaptive TDTL (EES-ATDTL) architecture. A block diagram of the EES-ATDTL is depicted in Figure 6.26. The architecture exploits the fact that the phase shift introduced by the time delay unit is directly proportional to the input frequency, this means that any frequency shift that occurs at the input can be detected by calculating the phase difference between the signals in the two arms of the TDTL [106], namely y(t) and x(t). To find the phase difference, the error detector uses a multiplier followed by a low pass filter and an FSM. Under noise-free conditions, the loop accepts a sinusoidal input y(t) having a radian frequency ω with a frequency offset ∆ω = ω − ωo from the nominal radian frequency ωo of the DCO. The input signal is given by y(t) = A sin[ωot + θ(t)] (6.8) Where A is the signal amplitude and θ(t) is the phase of the incoming signal. Assuming a frequency step at the input then θ(t) = (ω − ωo)t + θo (6.9) 114 CHAPTER 6 where ω is the radian frequency of the input signal and θo is a constant. The time delay unit introduces a constant time-delay τ in the input signal, which causes a phase lag ψ = ωt. Therefore, the time-delayed signal can be expressed as x(t) = A sin[ωot + θ(t) − ψ] (6.10) and the output of the multiplier is m(t) = x(t) · y(t) = A2 sin[ωot + θ(t) − ψ] · sin[ωot + θ(t)] = (A2/2)[cos(ψ) − cos(2ω0t + 2θ(t) − ψ)] (6.11) Equation (6.11) shows that the output of the multiplier consists of two parts, the first one is a function of only the phase difference of the two signals, and the second term is at a frequency that is twice the signal frequency plus the sum of the two phases. In Figure 6.26 the low pass filter bandwidth is quite small so that it both filters out the noise and the unwanted double frequency term. If initially no frequency shift is applied to the input then the phase difference will be zero (actually ψo = π/2) and consequently the dc output of the filter will also be zero. On the other hand, when a frequency step is applied to the input, a phase error will be generated, resulting in a nonzero dc output as a function of the applied step as shown in Figure 6.27. As an example, consider an input signal with initial frequency of 1 Hz. If a step of 0.2 is applied to the input, that is a frequency shift from 1 to 1.2 Hz, this will result in a phase shift of ψ = 1.88 rad ≡ 108o and the dc output is cos(1.88)/2 = −0.15. Another factor that affects the dc output is the amplitude of the input signal (denoted as A in (6.11)) which causes the detector dc to change. Therefore, the locking range of the EES-ATDTL is limited to a certain range of input amplitudes within which the FSM of the loop can operate properly as illustrated in Figure 6.27. The proposed TDTL utilizes a variable gain block that is controlled by the FSM. Each value of the gain corresponds to a unique state of the of FSM, therefore φ(k + 1) = φ(k) − Kih[φ(k)] + Λo (6.12) where Ki = ωGi, Gi is a gain corresponds to a state i. If Ki is defined to be ωoGi, then Ki = Ki/W , with W = ωo/ω. The operating conditions and simulation scenarios of the EES-ATDTL are similar to those of the SS-ATDTL. Therefore, the EES-TDTL in Figure 6.26 was tested by subjecting it to different frequency steps, which in the case of ARCHITECTURES FOR IMPROVED PERFORMANCE 115 Figure 6.27: Characteristic function of the multiplier dc output. Delineated area shows the locking range of the loop in Figure 6.26. the conventional TDTL can throw the system outside the locking range shown in Figure 6.22. The results of the simulation show that the loop responds and converges to a steady state phase error within few samples. These few samples correspond to the time taken by the newly introduced phase error detection circuit to respond. For example, a frequency step of -0.4 with W = 1.6, K1 = 1 and ψo1 = π/2 was applied to both the conventional and the new loop and their responses are shown in Figure 6.28. The locking performance of both loops is also demonstrated by the phase plane plots illustrated in Figure 6.29. The plots show that the conventional TDTL stays in the unlocked condition, whereas the new one converges into a steady state condition within an acceptable time. 6.4 Simulation Results of Second-Order TDTL As was the case with the first-order TDTL, negative and positive frequency steps were applied to the second-order loop in order to observe its response. Figure 6.30 shows the response of the loop to a negative frequency step. The initial phase shift ψo is arranged as π/2 and K1 is equal to unity. Referring to the second-order locking characteristics discussed earlier, it is obvious that the locking range is narrower and imposes restrictions on the choice of frequency ratios, making the second-order loop more susceptible to inputs causing instability. 116 CHAPTER 6 Phase error output 3 2 1 0 −1 −2 −3 −4 10 20 30 40 50 60 70 80 90 100 Time(s) (a) 0.5 0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 10 20 30 40 50 60 70 80 90 100 Time(s) (b) Figure 6.28: (a) The conventional TDTL response to a frequency step with W = 1.6 (b) The proposed TDTL response to the same frequency step. Phase Error Output ARCHITECTURES FOR IMPROVED PERFORMANCE 117 φ (k+1) 3 2 1 φo 0 −1 −2 −3 −4 −4 −3 −2 −1 0 1 2 3 φ (k) (a) 0.5 0 −0.5 −1 −1.5 −2 −2.5 φss −3 −3.5 −3.5 −3 −2.5 −2 −1.5 φ(k) (b) −1 −0.5 φo 0 0.5 φ(k+1) Figure 6.29: (a) Phase plane of the conventional TDTL for a W = 1.6 (b) Phase plane of the proposed system for W=1.6. 118 CHAPTER 6 Frequency Step Phase Error Time Time Figure 6.30: Tracking a negative frequency step with the second-order TDTL: (Top) input frequency step (Bottom) loop phase error. The effect of applying an input signal with W = 1.67 to the loop, and the phase error response are shown in Figure 6.30. The most prevalent difference compared with the first-order loop is that the phase error converges to zero, i.e., the loop tracks both the frequency and the phase of the input signal. This fact is also confirmed in Figure 6.31, where it is clear the DCO samples are converging towards the positive going zero crossings of the input waveform. The same behavior also applies for positive frequency steps as illustrated in Figure 6.32, in which a positive frequency step is applied to the second-order loop with the same set of parameters used in the negative step case. The phase error in this case converges to zero, causing the DCO to track the frequency and the phase of the input signal. ARCHITECTURES FOR IMPROVED PERFORMANCE 119 Figure 6.31: Sampling process of the second-order TDTL (negative step). 120 CHAPTER 6 Figure 6.32: Tracking a positive frequency step with the second-order TDTL(Top) input frequency step (Bottom) loop phase error. ARCHITECTURES FOR IMPROVED PERFORMANCE 121 6.5 Improved Second-Order TDTL Architectures This section discusses modified second-order TDTL architectures that improve the performance of the loop in terms of speed and locking range width. As in the case of the first-order, these modifications are based on the use of finite-state machines to control particular loop parameters and hence achieve the desired performance. The proposed architectures and their associated simulation results are described in the subsections below. 6.5.1 Adaptive Filter Coefficients Second-Order TDTL In the fixed bandwidth TDTL, if the system is thrown out of lock due to a sudden change in the input frequency it will stay out of lock unless an external signal forces the digital controlled oscillator (DCO) back into the locking region. The TDTL can retain the lock state if it was always kept within the locking boundaries, and this can be achieved by adapting the coefficients of the filter in response to frequency steps, which will cause large errors. The Adaptive Filter Coefficients Second-Order TDTL, shown in Figure 6.33, is created by utilizing digital filter with its coefficients controlled by an appropriate FSM. The FSM states are defined by the input phase error signal e(k) and the output control signals d(k) and g(k). The phase error serves as an indicator of the operating point of the TDTL, therefore, the FSM can decide on the value of the filter coefficients G1 and G2 which will keep the loop inside its locking boundary. Since the system can acquire frequency steps such as point A in Figure 6.34, that is resulted from an input signal frequency with lower frequency than the DCO free running frequency ωo, i.e., W > 1, the FSM keep the filter coefficients the same and does not alter them. When the system is subjected to a frequency step that causes the input signal frequency to go higher than ωo, i.e., W < 1 such as point C in Figure 6.34, the FSM will update the control signals d(k) and g(k) in order to choose the appropriate values of G1 and G2 that ensure operating within the locking boundary of the loop. The system in Figure 6.33 was tested by subjecting it to a step input change in frequency that pushes the loop to point C in Figure 6.34, where W = 0.75 and K1 = 1, and comparing its behavior with that of the conventional secondorder TDTL. The conventional loop goes into unlocked state and does not recover. However, the modified architecture in Figure 6.33 senses the error through its FSM and accordingly changes the digital filter coefficients so that the operating point is pushed to point I, which is within the locking boundary of the second order loop. The settling behaviors of the conventional loop as well as the adaptive filter coefficients second-order loop to the above step frequency input are illustrated by the transient responses in Figure 6.35 and the phase 122 CHAPTER 6 Time x(t) Delay Sampler 1 Digitally y(t) Controlled Oscillator (DCO) Sampler 2 Finite State Machine (FSM) x(k) d(k) g(k) + Delay Unit + G1 G2 e(k) Phase Detector arctan(x/y) y(k) Figure 6.33: Adaptive filter coefficients second-order TDTL Architecture. Figure 6.34: Locking range of adaptive gain second-order TDTL. ARCHITECTURES FOR IMPROVED PERFORMANCE 123 plane plots in Figure 6.36. Both figures show that when the loop is at point I, it converges into a steady state condition, whereas, when it is at point C, it stays in the unlock condition. 6.5.2 Adaptive Loop Gain Second-Order TDTL The Adaptive Loop Gain Second-Order TDTL shown in Figure 6.37 offers wider locking range than the conventional second-order TDTL. The adaptive loop is designed to operate at the nominal point N, where K1 = 1 and W = 1, shown in Figure 6.38 [107]. As the frequency changes around the carrier, i.e., 1 < W or W > 1, the loop is maintained in lock by the FSM block by changing the DCO frequency and the loop filter coefficients in order to keep K1 = 1. The FSM block has two inputs, e(k) and y(k). The criterion for state transitions is based on the magnitude of e(k) and the sign of y(k). The outputs of the FSM are the control signals d(k) and g(k), where d(k) decides the operating frequency of the DCO and g(k) decides the values of the filter coefficients that keeps the loop gain K1 = 1. The Adaptive Loop Gain Second-Order TDTL was evaluated by subjecting it to different frequency steps. The extensive results produced indicate that the adaptive TDTL has an improved locking performance when compared to the conventional TDTL. This can be illustrated by applying a frequency step that takes the loop to a point B of Figure 6.38, where W = 0.58 and K1 = 1. This frequency step will drove the conventional Second Order TDTL out of lock as shown by the transient response and the phase plane Figure 6.39. The locking performance of the adaptive loop gain system for the same frequency step is shown in the phase plane plot shown in Figure 6.40. It can be seen that, while the system in Figure 6.37 manages to settle through its adaptation mechanism within acceptable time when applying the same frequency step to it, the conventional second order TDTL failed to do so because of its limited locking range. 6.6 A Variable Order TDTL Architecture The Variable Order TDTL, shown in Figure 6.41, enhances the performance of the original loop by utilizing the wide bandwidth of the first order loop and the high signal to noise ratio with zero steady state phase error of the second order loop. This is achieved by varying the order of the digital filter block within the TDTL and hence changing the overall order of the loop in order to maintain acquisition status. 124 CHAPTER 6 (a) (b) Figure 6.35: Transient response of (a) Conventional second-order TDTL (b) Adaptive filter coefficients second-order TDTL. ARCHITECTURES FOR IMPROVED PERFORMANCE 125 (a) (b) Figure 6.36: Phase plane plots of (a) Conventional second-order TDTL (b) Adaptive filter coefficients second-order TDTL. 126 CHAPTER 6 Figure 6.37: Adaptive loop gain second-order TDTL architecture. Loop Gain (K1) 6 5 4 3 2 1 B* *N A* 0 0 0.5 1 1.5 2 2.5 3 Frequency Ratio (W) Figure 6.38: Locking range of adaptive second-order TDTL. ARCHITECTURES FOR IMPROVED PERFORMANCE 127 (a) (b) Figure 6.39: (a) Conventional second-order TDTL (a) Transient response (b) Phase plane. 128 CHAPTER 6 Figure 6.40: Phase plane of the adaptive loop gain second-order TDTL. ARCHITECTURES FOR IMPROVED PERFORMANCE 129 Time x(t) Delay Sampler 1 Finite State Machine (FSM) x(k) z(k) y(t) Digitally Controlled Oscillator (DCO) c(k) Proportional Accumulative Filter e(k) Phase Detector arctan(x/y) y(k) Sampler 2 Figure 6.41: Variable order TDTL structure. The loop in Figure 6.41 is similar to the conventional TDTL structure except for the filter bank and the use of the FSM block. The FSM decides on the filter order that is to be used in order to provide the best achievable locking on the input signal according to the introduced frequency disturbances. The system is designed to operate at point N of Figure 6.42, where K1 = 1 and W = 1, with the second-order loop as a default order due to its zero steady state phase error and high SNR. Due to its narrow bandwidth, the second order TDTL is more susceptible to inputs with higher frequency than the DCO free running frequency, which will cause more instability than the first order loop. The loop architecture in Figure 6.41 combines both the first-order and second-order loops to get a more reliable system with zero steady state error and high SNR when the frequency step is within the locking range of the second order TDTL and a stable system with a small steady state error when it is outside the locking range of the second order loop. The FSM in Figure 6.41 senses the phase error signal and switches from second order to first order TDTL whenever the frequency step exceeds a predefined positive threshold that is on the boundaries of the locking range of the second order loop. The FSM also switches the loop back to the second order TDTL mode when the effect of the frequency step is either omitted or reduced to within the locking range boundaries of the second order loop. This loop mode control mechanism of the Variable Order TDTL results in an improved locking range compared with single mode loop as shown in Figure 6.42. 130 CHAPTER 6 Figure 6.42: Variable order TDTL locking range with ψo1 = π/2. As mentioned in the previous chapter, VO-TDTL combines first- and secondorder TDTLs in order to enhance the locking performance of the loop and improves its noise immunity to frequency disturbances. The first-order TDTL provides fast acquisition and hence improved locking range, and the secondorder loop offers high signal to noise ratio and zero steady-state error, which makes the DCO follow the input signal frequency very closely. We will take K1 = 1 and assume two points, A at W > 1.5 and B at W < 0.75. The settling behavior of the first order TDTL at those points is shown in Figure 6.43. Point A is selected to be outside the locking range of the first-order TDTL, therefore, the loop stays in the unlock condition. The phase plane plot of Figure 6.44 demonstrates this. The phase plane plot of Figure 6.45 shows the loop locking performance at point B. It shows that when the disturbance is within the locking boundaries of the loop, it converges to a steady state condition within acceptable time. Testing the second-order TDTL response at the same set of points with the same K1 and referring to the loop locking characteristics resulted in the settling behavior an shown in Figure 6.46. The phase plane plot of Figure 6.47 shows the loop locking performance at point A. It can be seen that the phase started at zero and after few samples it reached to the steady state phase error value, where it converged to zero. Since point B is outside the second order loop locking range which resulted in the unlock condition shown in the phase plane plot of Figure 6.48. Due to the previously mentioned desirable features of the second order TDTL for many communication applications, the proposed system works as a second order TDTL until the loop is subjected to a large positive frequency step causing the second order TDTL to go outside the locking range such as point B with W < 0.75. The system senses this error through its FSM and switches to ARCHITECTURES FOR IMPROVED PERFORMANCE 131 Figure 6.43: Transient response of the first-order TDTL at points A and B. Figure 6.44: Phase plane at point A. Figure 6.45: Phase plane at point B. 132 CHAPTER 6 Figure 6.46: Transient response of the second-order TDTL at points A and B. ARCHITECTURES FOR IMPROVED PERFORMANCE 133 Figure 6.47: Phase plane at point A. the first order loop, which brings the loop to the locking state. The system also monitors the frequency disturbances until it is reduced to an amount that can be handled by the second order TDTL, where the FSM switches the loop back to second order. With reference to Figure 6.42, the transient response of the Variable Order TDTL for a sequence of frequency steps that take the operating point of the loop to points A and B respectively is shown in Figure 6.49. The variable order TDTL improves the performance of the loop and provides a wide symmetrical locking range for acquiring both positive and negative frequency steps. In addition to the TDTL architectures discussed in this book, a technique that widens the locking range for both first and second order TDTLs was reported in [112]. It achieves this through modification of the free running sampling rate and the digital filter output. 6.7 Conclusions In this chapter we presented the simulation results of the original TDTL and compared them with those obtained from the improved TDTL architectures. The objectives of the improved architectures were to enhance the overall performance of both the first-order and second-order TDTL systems. The results illustrated that the new architectures achieved the desired objectives with varied degrees of success. For the first-order TDTL the following improved architectures were presented: delay switching, adaptive gain, combined delay switching and adaptive 134 CHAPTER 6 Figure 6.48: Phase plane at point B. Figure 6.49: Transient response of the variable order TDTL at points A and B. ARCHITECTURES FOR IMPROVED PERFORMANCE 135 gain, sample sensing and early error sensing. The combined delay switching and adaptive gain architecture results in the best improvement in the TDTL locking range, while the early error sensing architecture enhances the acquisition time of the loop. In the case of the second-order TDTL, the adaptive filter coefficients and the adaptive loop gain architectures were shown to improve the system performance. The results indicate that the two architectures have comparable performance, with the adaptive loop gain having marginally faster acquisition capabilities. We finally presented the variable order architecture that harnessed the desirable characteristics of the first-order and second-order TDTLs. The variable order architecture achieved a wide locking ranged compared with the fixed order loop. However, under fast switching conditions the loop performance tends to get degraded. Chapter 7 FPGA Reconfigurable TDTL Some of the TDTL architectures that were presented earlier were implemented on a reconfigurable field-programmable gate array (FPGA) based system. The synthesis and subsequent implementation process required the conversion of the loop blocks to hardware realizable circuitry. This chapter gives an overview of reconfigurable computing systems and then presents a brief introduction to FPGA technology, which is the main driver of reconfigurable systems. This is followed with a detailed discussion of the process of converting the TDTL Matlab/Simulink models to FPGA implementation and the real-time results that were obtained. 7.1 Overview of Reconfigurable Systems In traditional computing systems, the execution of algorithms is carried out by two dominant methods. The first is to perform the operation in hardware via the use of an Application Specific Integrated Circuit (ASIC). As these ASICs are designed and well optimized to specifically perform a given computation, they are very fast and efficient when executing the exact computation for which they were designed. However, once fabricated these circuits cannot be altered because they are hard-wired. On the other hand, microprocessor based systems execute algorithms with a high degree of flexibility. In this method, the processor performs the required computations by executing a set of instructions. The functionality of processor-based systems can be easily changed by simply changing the software instructions or program without making any form of alteration to the hardware. However, the performance of microprocessor-based system is far below that of an ASIC. The reason being that the processor performs computation by completing a fetch-decode-execute cycle for each instruction; which involves 137 138 CHAPTER 7 reading an instruction from memory, interpreting it and then executing it. The net result is a high execution overhead for each individual operation. Reconfigurable computing is a paradigm for system design that is intended to fill the gap between the hardware and software computing systems discussed above. Its primary aim is to achieve higher performance than software, while maintaining a higher level of flexibility than hardware. Reconfigurable computing utilizes hardware modules that can be adapted at run-time to facilitate greater flexibility without compromising performance. Reconfigurable architectures can exploit fine-grain and coarse-grain parallelism available in the application due to their adaptability. Exploiting this parallelism provides significant performance advantages compared with conventional microprocessors. The reconfigurability of the hardware permits adaptation of the hardware for specific computations in each application to achieve higher performance compared to software [86, 88]. Complex functions can be mapped onto the architecture achieving higher silicon utilization and reducing the instruction fetch and execute bottleneck. Due to their inherent parallelism and reconfigurability, FPGAs are currently the main building blocks of reconfigurable computing systems for a wide range of applications [91]. The application areas of FPGA-based reconfigurable systems include digital communications, digital signal processing, communication security, high performance computing and many others. The next section presents an overview of FPGA architectures. 7.2 FPGA Structure and Operation FPGAs are general-purpose digital integrated circuits that consist of programmable or configurable logic blocks along with configurable interconnects between these blocks. Depending on the implementation technology used, some FPGAs may be programmed a single time, while others may be reprogrammed as many times as needed. In all cases, FPGA programming is done by the user hence the “field programmable” part of the FPGA’s name. The configurable aspect of FPGAs is one of the main factors that differentiate them from ASICs. The general structure of an FPGA is shown in Figure 7.1. It contains three major types of resources: logic blocks, input/output (I/O) blocks to connect to the chip pins, and interconnection wires and switches. The logic blocks, which may include dedicated look-up tables (LUTs), registers, multipliers, dual port memories, tri-state buffers, multiplexers, digital clock managers and others, are arranged in a two-dimensional array that can be configured to implement a wide range of arithmetic and logic functions. The interconnect wires are organized in dedicated horizontal and vertical routing channels between rows and columns FPGA RECONFIGURABLE TDTL 139 I/O Block I/O Block I/O Block Logic Block I/O Block Interconnection Switch Figure 7.1: General structure of an FPGA. of logic blocks. The routing channels contain wires and programmable switches that allow the computing logic blocks and I/O resources to be linked in various ways to form systems under the control of the device configuration bitstream. [92, 93, 94]. FPGA performance is derived from the ability they provide to construct highly parallel architectures for processing data. In contrast with a microprocessor or DSP processor, where performance is tied to the clock rate at which the processor can run, FPGA performance is tied to the amount of parallelism that can be brought to bear in the application algorithms. A combination of increasingly high system clock rates and highly distributed memory architectures give the system designer an ability to exploit parallelism in processing of data streams. All FPGAs need to be configured or programmed in order to synthesize the required digital system. There are three major circuit technologies for configuring an FPGA: SRAM, antifuse, and flash. These technologies are discussed briefly below. 140 READ/WRITE DATA (a) CHAPTER 7 Q Q P (b) Figure 7.2: (a) Programming SRAM Cell. (b) Programmable routing connection. Static RAM (SRAM): In SRAM-based FPGAs programmable connections are made using transmission gates, or multiplexers that are controlled by SRAM cells. Figure 7.2 depicts an SRAM-based programmable cell [96]. The output (Q) in Figure 7.2-a drives the input (P) of the programmable routing connection in Figure 7.2-b. In SRAM technology devices can be configured dynamically over and over again. This distinct property results in many advantages that include: new ideas can be quickly implemented and tested, it allows fast in-circuit reconfiguration, and an FPGA can be programmed to perform self-test or system test as well as its main task. Furthermore, SRAM-based FPGA are at the forefront of technology and that enables them to benefit from the technological developments in standard SRAM manufacturing. The major disadvantage of SRAM-based FPGAs is that they have to be reconfigured every time the system is powered up. This requires the use of a special external memory device, which adds to the cost and size of the overall system. Another disadvantage is that SRAM cells are larger than antifuses and flash cells. Antifuse: An anti-fuse resides in a high-impedance state, and can be programmed into low impedance or “fused” state. Figure 7.3 shows an antifuse device before and after programming [94]. Antifuses are one-time programmable devices, which when “blown” create a via-connection, while when “unblown” act FPGA RECONFIGURABLE TDTL 141 Oxide Amorphous Silicon Metal-1 Metal-2 Oxide Oxide Substrate (a) Polysilicon via Metal-1 Metal-2 Oxide Substrate (b) Figure 7.3: Antifuse Device (a) Before Programming (b) After Programming. as an open circuit with very high resistance. The disadvantage of this technology is that it is one time programmable and offers less design flexibility compared with SRAM technology. The main advantage of antifuse-based FPGAs is that their configuration information is non-volatile, which means they do not need to be reconfigured on power up. Flash: Flash memory is a form of EEPROM (electrically erasable programmable ROM) that can be rapidly erased. Flash uses a floating-point gate structure in which a low-leakage capacitor holds voltage that controls a transistor gate. Components based on flash have a variety of architectures. Figure 7.4 shows a possible flash programmed cell [95, 108]. The main advantage of flash-based FPGAs is that they can be reprogrammed without external storage for reconfiguration. However, flash devices require five additional processing steps more than SRAMs and they tend to have high static power dissipation. The vast majority of FPGAs are based on SRAM technology due to their flexibility and ease of reconfigurability as outlined above. The remainder of this chapter will use SRAM-based FPGAs. Figure 7.1 showed an abstract top-view of an FPGA. Each logic block in Figure 7.1 has a small number of inputs and one output. In most FPGAs the logic block is a look-up table (LUT), which contains SRAM cells and multiplexers. An n-input LUT can implement any possible n-input combinational logic function. Figure 7.5 illustrates a three-input LUT. It has eight SRAM cells because 142 Flash Transistor Floating Gate Programme d Transistor Word Line CHAPTER 7 Figure 7.4: Flash Based FPGA Switch. the truth table of a three-variable function has eight rows. Adding more inputs allows an LUT to represent more complex functions. Most current FPGAs tend to use 4-input LUTs as they offer an optimal balance of device utilization and performance. The multiplexers in an LUT are normally implemented in the form of transmission gates. The LUT is combined with other components to form the core building block of an FPGA. In the case of Xilinx FPGAs this is called a logic cell (LC). As shown in Figure 7.6, an LC consists of a 4-input LUT, which can also act as 16x1 RAM or a 16-bit shift register, a multiplexer and a register. The register can be configured to act as a flip-flop or a latch. In the case of Xilinx FPGAs, joining two LCs results in what is called a slice as illustrated in Figure 7.7. The LUT, multiplexer and register in each LC have their own data inputs and outputs. However, the slice has one set of clock, clock enable and set/reset signals that are common to both LCs. The highest level of the hierarchy in Xilinx FPGAs is called a configurable logic block (CLB) [96, 97]. Depending on the particular FPGA device, a CLB consists of either two or four slices. Figure 7.8 shows a 4-slice CLB. A complete CLB represents a single logic block of those shown in Figure 7.1. The CLB schematic of an actual Xilinx 4000 FPGA series is shown in Figure 7.9 [96]. 7.3 Xtreme DSP Development System The Xtreme DSP Development Kit-II was the implementation platform of the reconfigurable TDTL in this work. The development board, shown in Figure 7.10, is powered by a Virtex-II FPGA chip from Xilinx. In addition to that, it provides dual channel high performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), enabling the development of FPGA RECONFIGURABLE TDTL 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 A B C SRAM Cells MUX Figure 7.5: Three-Input LUT. 143 F 144 CHAPTER 7 Xilinx FPGA Logic Cell A B C D E Clock Clock Enable Set/ Clear 4-bit LUT (16x1 RAM) (16-bit SR) Y M U X Q Flip-Flop Figure 7.6: A simplified Xilinx FPGA logic cell. FPGA RECONFIGURABLE TDTL 145 Xilinx FPGA Slice 4-bit LUT (16x1 RAM) (16-bit SR) FPGA Logic Cell M Flip-Flop U (Register) X 4-bit LUT (16x1 RAM) (16-bit SR) FPGA Logic Cell M Flip-Flop U (Register) X Figure 7.7: Xilinx FPGA slice. 146 XILINX FPGA Configurable Logic Block Slice Slice Logic Cell Logic Cell LUT M R U E X G. LUT M R U E X G. LUT Logic Cell M R U E X G. LUT Logic Cell M R U E X G. LUT LUT Slice Logic Cell M R U E X G. Logic Cell M R U E X G. LUT LUT Slice Logic Cell M R U E X G. Logic Cell M R U E X G. CHAPTER 7 Figure 7.8: Configurable logic block. G4 Logic G3 Function G2 of G1 G1-G4 F4 Logic F3 Function F2 of F1 F1-F4 K (CLOCK) H1 DIN S/R EC DIN F' G' H' Logic Function G' of H' F', G', and H1 DIN F' G' H' H' F' S/R Control 1 S/R Control 1 D SD Q Bypass YQ EC RD Q Y D SD Q Bypass XQ EC RD Q X Figure 7.9: Configurable logic block of Xilinx 4000 Series FPGA. FPGA RECONFIGURABLE TDTL 147 Figure 7.10: Xtreme DSP development board. such applications as software defined radio, wireless networking, HDTV, video imaging and many others [98]. The block diagram of the Xtreme DSP development board is shown in Figure 7.11, where it is clearly seen that the board is composed from three Xilinx FPGA chips. The first is the Virtex-II XC2V3000, which has a capacity of three million gates. This chip is called the Main User FPGA, since it is used to implement the bitstreams developed by the user. The second FPGA chips is the VirtexII XC2V80, which is configured by the user for the purposes of clocking and I/O management. The third FPGA is the Spartan-II interface FPGA, which is preconfigured for the purpose of communication with the PC using the PCI bus or the USB [98]. The Xilinx System Generator serves as the software development platform of the reconfigurable TDTL system. It consists of a MATLAB/ Simulink library called the Xilinx Blockset, and software to translate a Simulink model into a hardware realization of the model. The System Generator maps system parameters defined in Simulink (e.g., as mask variables in Xilinx Blockset blocks), into entities and architectures, ports, signals, and attributes in a hardware realization. In addition to that, System Generator automatically produces command files for FPGA synthesis, hardware description language (HDL) simulation, and implementation tools, so that the user can work entirely in graphical environments in going from system specification to hardware realization [99]. 148 CHAPTER 7 Figure 7.11: Xtreme DSP block diagram. FPGA RECONFIGURABLE TDTL 149 The Xilinx Blockset is accessible in the Simulink library browser, and elements can be freely combined with other Simulink elements. Only those subsystems denoted as Xilinx black boxes, and blocks and subsystems consisting of blocks from the Xilinx Blockset are translated by System Generator into a hardware realization. The generation process is controlled from the System Generator block found in the Xilinx Blockset Basic Elements library. The System Generator parameterization graphical user interface (GUI) allows the user to choose the target FPGA device, target system clock period, and other implementation options. The System Generator translates the Simulink model into a hardware realization by mapping Xilinx Blockset elements into Intellectual Property (IP) library modules, inferring control signals and circuitry from system parameters (e.g., sample periods), and converting the Simulink hierarchy into a hierarchical VHDL netlist [98, 99]. Furthermore, the System Generator creates the necessary command files to create the IP block netlists using CORE Generator, invokes CORE Generator, and creates project and script files for HDL simulation, synthesis, technology mapping, placement, routing, and bit stream generation. To ensure efficient compilation of multi-rate systems, the System Generator creates constraint files for the physical implementation tools. The System Generator also creates an HDL test bench for the generated realization, including test vectors computed during Simulink simulation. A graphical representation of the design flow using the Xilinx System Generator is shown in Figure 7.12 [99]. 7.4 TDTL FPGA Implementation The implementation of the TDTL discussed in Section 3.2 into an FPGA requires the translation of the major components of the loop, which were previously modelled using MATLAB/Simulink blocks, into hardware-mappable blocks. After that, these blocks can be simulated on a bit and cycle true basis and then complied into a HDL script. Xilinx System Generator includes plenty of these blocks, and these were used to modify the architecture of the TDTL into the reconfigurable model shown in Figure 7.13. The reconfigurable TDTL, shown in Figure 7.13, has undergone some modification in order to optimize the utilisation of resources. While the TDTL shown in Figure 3.1 suggests using two sample and hold (S/H) or ADC circuits, this implementation is expensive in terms of size, cost and power consumption. Thus, the TDTL was modified to include a single ADC sampled at the system clock rate, which is much higher than the free running frequency of the loop. The ADC digitizes the continuous-time input signal so that further processing, including the delay operation, can be carried out digitally. In addition to 150 CHAPTER 7 Library (including Xillinx Blockset) Simulation including S-functions Synthesis MATLAB Environment Input System Model + Z−1 k Simulink Output Simulation Data VHDL Core Parameters Xilinx Design Tools Environment Synthetic Compiler EDIF CORE Parameters Test Vectors FPGA Place & Route EDIF + Timing Logic Simulation Bit stream Pass/Fail Figure 7.12: Design flow using Xilinx System Generator. FPGA RECONFIGURABLE TDTL 151 Figure 7.13: Reconfigurable FPGA-based TDTL implementation. that, each S/H block can be replaced by a latch, as shown in Figure 7.13. The latches perform the same conceptual function as that of S/H blocks in Figure 3.1; however, they are operating fully in the digital domain. The DAC blocks are used to propagate the phase error and the output of the DCO to the outside world, in order to observe the performance of the loop and perform data acquisition and logging. The following subsections will explain the major components of the reconfigurable TDTL. 7.4.1 The CORDIC Arctangent Block The COordinate Rotational DIgital Computer (CORDIC) algorithm is an iterative method of calculating trigonometric and hyperbolic functions using mainly shift and add operations. This feature made the algorithm an attractive option for hardware implementation. Specifically, it lends itself for the architecture of FPGAs in applications such as digital signal processing, digital control, filtering and matrix algebra [100]. The CORDIC algorithm is used to implement the 4-quad Tan−1(x/y) function of the phase detector, converging to angles between ±π within eleven system clock cycles. The architecture of the CORDIC arctangent block is shown in Figure 7.14. The CORDIC Tan−1(x/y) algorithm is implemented in 3 steps: Step 1: Coarse Angle Rotation. At this stage, the algorithm converges only for 152 CHAPTER 7 Figure 7.14: CORDIC implementation of Tan−1(x/y) function. angles between −π/2 and π/2, so that if x < 0, the input vector is reflected to the 1st or 3rd quadrant by making the x-coordinate non-negative. Step 2: Fine Angle Rotation. For rectangular-to-polar conversion, the resulting vector is rotated through progressively smaller angles, such that y goes to zero. In the ith stage, the angular rotation is by either ±arctan(1/2i), depending on whether or not its input y is less than or greater than zero. Step 3: Angle Correction. If there was a reflection applied in Step 1, this step applies the appropriate angle correction by subtracting it from ±π [101, 102]. 7.4.2 The Digital Controlled Oscillator The architecture of the DCO is of great influence on the performance of the loop. Usually, DCOs are implemented by using modulo-m or divide-by-m counters. These counter circuits are clocked by a high frequency source, and the output frequency of the counter source frequency divided by the control word m. The disadvantage of using such counter is the poor frequency resolution. Therefore, it was not preferred as a choice of DCO implementation. The DCO was implemented using a Direct Digital Synthesis (DDS) block, which can be described as a frequency-controlled synthesizer of sinusoidal waveforms. The DDS block diagram is shown in Figure 7.15 [103]. The idea of direct digital synthesis revolves around storing the values of a sinusoidal waveform FPGA RECONFIGURABLE TDTL 153 Figure 7.15: Block Diagram of the DDS Block. over a quarter of a cycle in a look-up table (LUT), which maps a certain phase argument to produce the output waveform. As shown in Figure 7.15, the phase increment, which can be thought of as the digital word determining the output frequency, is received and then applied to a phase accumulator consisting of adder A1 and register D1. The slope of the phase accumulator is then mapped to a sinusoid by the look-up table T1. However, the high precision output of the phase accumulator is reduced to a low precision one which matches the input width of the look-up table. This is performed using the quantizer Q1 and presents the slope to the address port of a look-up table that performs the mapping from phase-space to time. The quality of a signal formed by recalling samples of a sinusoid from a look-up table is affected by both the phase and amplitude quantization of the process. The length and width of the look-up table affect the signal’s phase angle resolution and the signal’s amplitude resolution respectively [103]. The output frequency of the DDS is a function of the system clock frequency fclk, the number of bits Bθ(n) in the phase accumulator and the phase increment value ∆θ. The output frequency fout can be calculated in Hertz as follows fout = fclk∆θ 2Bθ(n) (7.1) The DDS block is capable of providing fine frequency resolutions reaching up to 0.02 Hz at fclk = 100 MHz. Another advantage of using the aforementioned block is the regeneration of the sinusoidal input to the TDTL directly and without the need for extra processing blocks, which is not possible with other architectures. The DCO pulses, which trigger the latches, can be created by squaring up the output of the DDS block. In addition to that, extra logic gates are required to form an edge detection circuit as shown in Figure 7.16, and this is due to the fact that the latch blocks provided by Xilinx Blockset are level 154 CHAPTER 7 Figure 7.16: Implementation of the DCO. triggered. Hence, they will stay active during the high state of the DCO pulses, unless the formers become high only during transitions. The free running frequency of the loop fo has been set to 250 KHz, and this requires a phase increment ∆θo of 212 , for a system clock of 65 MHz. The input phase increment is the result of adding ∆θo with the modified output of the digital filter c(k), therefore the output frequency of the DCO can be defined as fout = fclk[∆θ + c(k)] 2Bθ(n) (7.2) 7.4.3 The CORDIC Divider As mentioned above, the output frequency of the DCO will be updated according to (7.2). However, this violates the condition stated in Section 3.2, which states that the period of the DCO is to be updated at each sampling instant according to (3.5), which is given again below T (k) = To − c(k − 1). Therefore, in order for the DCO to function properly, the output of the digital filter, which will be denoted as cΛ(k) must be mapped through the following function in order to obtain the required output c(k) c(k) = −∆θo 1 1+ cΛ(k)fo − 1 (7.3) FPGA RECONFIGURABLE TDTL 155 Figure 7.17: CORDIC divider implementation. Equation (7.3) above must be implemented in hardware in order to bridge the output of the digital filter with the input of the DCO. The equation requires addition, multiplication and division operations. While the first two can be easily implemented using fixed-point hardware, the third one is the most complex and demanding in terms of hardware implementation. Several algorithms can be used to perform non-power-of-two division, and the one used in the synthesized system is the CORDIC divider shown in Figure 7.17. The steps involved in the implementation of the CORDIC divider algorithm are as follows: Step 1: Co-ordinate Rotation. The CORDIC algorithm converges only for positive values of x, so if x < zero, the input vector is reflected to the 1st or 3rd quadrant by making the x-coordinate non-negative. For normalizing x and y, y is always mapped to a non-negative value. The Divider circuit has been designed to converge for all values of x and y, except for the most negative value. Step 2: Normalization. The CORDIC algorithm converges only for y greater than or equal to 2x. For x greater than y, both the inputs x and y are shifted to the left till they have a 1 in the most significant bit (MSB). The relative shift of y over x is recorded and passed on to the Quadrant Correct Stage. Step 3: Linear Rotations. For ratio calculation, the resulting vector is rotated through progressively smaller angles, such that y goes to zero. In the i -th 156 CHAPTER 7 Figure 7.18: Hardware Implementation of Equation (7.3). stage, the rotation yields ± y/x, depending on whether the input y is less than or greater than zero. Step 4: Co-ordinate Correction. If the axis was rotated Step 1 and a relative shift was applied to y over x, this step assigns the appropriate sign to the resulting ratio and multiplies it with 2 (relative shift of y/x) [101, 102]. This operation is expensive in terms of complexity and time, since it consumes 34 system clocks, and therefore it imposes restrictions on the free running frequency of the TDTL. The hardware realization of (7.3) is shown in Figure 7.18. 7.5 Real-Time TDTL Results The following sub-sections present some of the real-time results that were achieved following the FPGA conversion and subsequent implementation of some of the TDTL architectures that were discussed in Chapter 7. The results include those of the first-order TDTL, second-order TDTL and the sample-sensing adaptive TDTL. The performance of the reconfigurable TDTL implemented in this section are compared with those obtained through simulations earlier in order to ascertain that the overall functionality of the synthesized systems is acceptable. Complete verification of embedded phase lock loops requires the application of more tests as discussed in [109]. FPGA RECONFIGURABLE TDTL 157 7.5.1 First-Order TDTL The first-order loop is designed by multiplying the output of the phase detector with G1. The loop gain K1 has been selected as unity, therefore, G1 will be equal to 1/2π = 0.1592. In order to induce a nominal phase shift of π/2 to the input signal, the time-delay unit should be equal to quarter the period of fo, namely 1 microsecond. Since the smallest delay possible is equal to the period of the system clock (1/65 MHz), the number of delay stages required is the ratio between the time delay and the system period, which is approximately equal to 68 in this case. The implementation of the TDTL has consumed a total of 54,751 gates out of the total capacity of the Virtex-II, which is around 3 million system gates. Figure 7.19-a shows the behaviour of the phase error when the first-order reconfigurable TDTL is subjected to a positive frequency step. In this case, the initial input frequency was 260 KHz, and a sudden increase caused the input frequency to rise to 280 KHz. As the figure shows, the TDTL follows the change in frequency and settles rapidly. An interesting observation in the captured phase error is the existence of noise-like ripples, which contradict with the theoretical simulations shown in Figure 7.19-b, in which the phase error is smooth in its steady state condition. The ripples in the real-time response of Figure 7.19-a do not indicate that the loop is out of lock. In fact they are the result of various practical factors not taken into consideration in the simulation. These are mainly caused by quantization noise, which is related to the resolution of the ADC, the truncation and calculation errors, since the loop is performing critical calculations in hardware using a limited number of bits. The limited frequency resolution of the DCO also introduces errors in calculations, and it can be stated that a ripple free output requires a synthesiser with a frequency resolution that approaches minus infinity [110]. 7.5.2 Second-Order TDTL The second-order TDTL shares the same implementation issues with the first order loop except for the digital filter, which is implemented as a proportional accumulative (PA) filter with the transfer function described in section 3.3.2. The loop gain has been chosen as 1.5 with a nominal phase shift of π/2. The hardware implementation of the PA filter is shown in Figure 7.20, and the total gate count of the implemented second order loop was equal to 55940 gates. Due to the existence of an accumulator in the digital filter, it is expected that the truncation and calculation errors are also going to accumulate at each clock cycle, causing the performance to be very sensitive to frequency changes, and in most cases oscillatory. 158 CHAPTER 7 (a) (b) Figure 7.19: Transient response of the first-order TDTL for a frequency step from 260 KHz to 280 KHz. (a) Actual real-time response. (b) Simulated response. FPGA RECONFIGURABLE TDTL 159 Figure 7.20: Realization of the PA loop filter. Since the phase error of the second-order loop is always converging to zero for inputs within its lock range, the existence of a frequency step can be read from the phase error output by observing the existence of sudden impulses that will slowly decay to a steady state level. This is demonstrated by the real-time response in Figure 7.21-a, where the input frequency of the implemented TDTL was suddenly increased from 175KHz to 205KHz. The decaying positive impulse is obvious, so is the effect of error accumulation, where it is clear that the oscillations are growing with time after the step was subjected to the loop. Figure 7.21-b depicts the theoretical response of the second-order TDTL to the same frequency step. The error accumulation is negligible in the theoretical response since all calculations are done using double precision arithmetic operations. 7.5.3 Sample Sensing Adaptive TDTL The sample sensing adaptive first-order TDTL (SS-ATDTL) discussed in Chapter 6 was converted for FPGA implementation as shown in Figure 7.22. The architecture in Figure 7.22 includes a finite state machine (FSM) block. In this work, the FSM was designed using Moore state machine approach, which consists of mainly the next state logic, state register and output logic. The System Generator provides different methods for implementing Moore FSM, such as using block and distributed memory, using Black box block with VHDL instructions or using MCode block to implement the transition function, and 160 CHAPTER 7 (a) (b) Figure 7.21: Transient response of the second-order loop for a frequency step from 175 KHz to 205 KHz. (a) Actual real-time response. (b) Simulated response. FPGA RECONFIGURABLE TDTL 161 Figure 7.22: FPGA Implementation of sample sensing adaptive first-order TDTL. registers to implement state variables. The last method was used to implement the FSM as it gives more flexibility and support using Matlab instructions in the design of the logic. Figure 7.18 shows the hardware implementation of the FSM. The behaviour of the SS-ATDTL shown in Figure 7.22 was studied by subjecting it to various frequency steps and comparing it with that of the TDTL in Figure 7.23. The real-time results of the FPGA-based systems to a positive frequency step that changed from 140KHz to 156KHz are illustrated in Figure 7.24. From the figure, it can be clearly seen that SS-ATDTL settles rapidly while the TDTL gets out of lock. This confirms the simulation results discussed in Chapter 6. 7.6 Conclusions This chapter presented an overview of the field of reconfigurable computing and the FPGA technology that is used to implement such systems. It then detailed the design flow of the Xtreme DSP system that was used to implement reconfigurable TDTLs. The process of implementing the TDTL on an FPGA required the transformation of the MATLAB/ Simulink model to one that is FPGA synthesizable. Following the transformation process the first-order, second-order as well as some of the improved architectures of each type were downloaded to the FPGA based Xtreme DSP system and real-time results were illustrated. Comparison of the real-time results with those obtained from MATLAB/ Simulink simulations 162 CHAPTER 7 Figure 7.23: FSM hardware implementation. indicates that they are broadly in agreement. In addition to illustrating the feasibility of implementing the TDTL on an FPGA, the above results show the flexibility of reconfigurable systems and advantages they offer in applications such as software defined radio. FPGA RECONFIGURABLE TDTL 163 (a) (b) Figure 7.24: Positive frequency step transient response of the (a) SS-ATDTL and (b) TDTL. Chapter 8 Selected Applications The previous chapters discussed in detail the structure, mathematical model and behaviour of the TDTL. We also presented a number of architectures that enhanced the performance of the loop and showed the process of implementing the TDTL on an FPGA based reconfigurable system. Synchronization and frequency tracking remain as the main applications of any DPLL in communications or signal processing. In addition, we further investigate in this chapter the capability of the TDTL in demodulating angle-modulated signals in the presence of additive Gaussian noise. Significant improvement over analog techniques of nearly 20 dB is obtained [104]. This is mainly due to the to its fast locking performance and its less sensitivity to amplitude variation. The TDTL was also tested for real time demodulation of FSK as well as wide band FM as will be shown in the following sections. 8.1 PM Demodulation Using TDTL PM signals convey the information message m(t) in the phase of a sinusoidal carrier with center frequency ωo = 2πfo such that the phase is linearly proportional to the message as follows x(t) = Ao sin[ωot + ∆pm(t) + γo] (8.1) where ∆p is a constant called the phase sensitivity and γo is the initial phase. For testing purposes we will consider the message to be a single-tone signal m(t) = Am sin(ωmt) such that the PM signal will be x(t) = Ao sin[ωot + β sin(ωmt) + γo] (8.2) where β = Am∆p is the modulation index and γo is a constant. 165 166 CHAPTER 8 h(φ) 3 2 1 0 −1 −2 −3 −3 −2 −1 0 1 2 3 φ Figure 8.1: Characteristic function of the time-delay digital tanlock loop (TDTL) when ψo = π/2. Solid line is for the frequency ratio W = ωo/ω = 1, dashed line for W = 1.1, and dotted line for W = 0.9. Now we consider the characteristic function of the TDTL h(φ), which is a non-linear function as shown in (3.15) except in the case when ψo = π/2 and W = ωo/ω = 1, which gives hψ(φ) = φ. If we arrange ψo = π/2, then for small values of the phase error φ(k) (which can be ensured in case the frequency ratio W = ωo/ω is inside the lock range), the TDTL characteristic function can still be approximated by (8.3) and as shown in Figure 8.1 hψ(φ) ≈ φ for small φ. (8.3) Now if we arrange the parameter K1 in (3.16) of the first-order TDTL to be 1 and the carrier frequency to be the loop center frequency ωo, then by using equations (3.9), (3.13), (3.16), (8.1), and (8.3) it can be shown that m(k) ≈ 1 ∆p k e(k) + γo. i=0 (8.4) Hence, a PM signal can be demodulated by adding up the PED output samples then using a low-pass analog filter for reconstruction as shown in Figure 8.2. However, this is true only if the incoming frequency range is inside the locking range. In Chapter 3, the locking conditions of the first-order TDTL were given by: 2|1 − W | < K1 < 2W sin2(α) + sin2(α + ψo/W ) sin(ψo/W ) SELECTED APPLICATIONS 167 Incoming Signal y (t ) x (t ) Sampler - I τ x (k ) Delay Output Pulses c (k ) e (k ) DCO DF PED Clock r (t ) LPF Σ Sampler - II y (k ) Figure 8.2: Block diagram of the TDTL PM-demodulator. Bold lines represent multi-bit connections. where α = tan−1(ρ) sin(ψ)tan(ζ ) sin(ψ) ρ = 1 − cos(ψ)tan(ζ) = cot(ζ) − cos(ψ) ζ = ess = f [Tan−1( sin(φss) )] sin(φss + ψ) = Λo K1 noting that ess is the steady-state output of the phase error detector and φss is the steady-state value of the phase error process φ(k) as defined in (3.9). As shown in Figure 8.3, for K1 = 1 the lock range can approximately be determined from the left-hand side of the above inequality. The instantaneous frequency of the above single-tone PM signal x(t) is given by [65] ωi(t) = d[φ(t)]/dt = ωo + βωm cos(ωmt) (8.5) where the maximum and the minimum frequencies are given by ωo±βωm. Using (8.5) and the above discussion we can find the conditions for demodulating the single-tone PM as follows βωm/ωo < 1/3. (8.6) If a similar PM demodulation technique is implemented using the conventional DTL, a dynamic range as in (8.6) will be obtained. It is evident that, despite the reduced structure, TDTL has a performance similar to that of the DTL in many aspects. The above dynamic range in TDTL and CDTL for PM demodulation is much wider than the limit of βωm/ωo < 1/(2π + 1) ≈ 0.13 obtained for the sinusoidal DPLL in [50], [38]. 168 CHAPTER 8 Loop gain, K1 = G1 ωo 3 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 Frequency ratio, W = ωo / ω Figure 8.3: Lock range of the TDTL for ψo = π/2. From Chapter 2, the steady state phase error at the output of the PED can be given by: ess = hψ(φss) = f Tan−1 sin(φss) sin(φss + ψ) = Λo K1 where |Λo/K1| < π from which the steady-state phase error φss is given by 3.33) as follows φss = α f (α + π) ρ sin(λ) ≥ 0 otherwise. (8.7) where λ = Λo/K1 and ρ= sin(ψ) = sin(ψo/W ) cot(λ) − cos(ψ) cot(λ) − cos(ψo/W ) α = tan−1(ρ) noting that tan−1(.) is the ordinary arctan function over(−π/2, π/2). From eqs.(8.5) and the above discussion, the PED output phase in the case of tonePM demodulation will range between ess|max and ess|min as follows ess max = Λo K1 = To max G1 1 1− 1 + βωm/ωo (8.8) SELECTED APPLICATIONS 169 ess min = Λo K1 = − To min G1 1 − 1 βωm/ωo − 1 . (8.9) The above results are generally true as long as the carrier frequency fo is much higher than the message maximum frequency fm such that an approximate locking can occur. This is the case in practical PM and FM transmission systems. 8.2 Performance in Gaussian Noise We now consider the performance of the above PM demodulator in additive Gaussian noise (AWGN) environment. In Chapter 4 we have shown that if the input signal is affected by AWGN as follows: y(t) = A sin[ωot + θ(t)] + n(t) (8.10) where n(t) is additive Gaussian noise with zero mean and variance σn2, then the output of the PED, ξ, can be expressed as follows ξ =e+η (8.11) where e = hψ(φ) is the deterministic output phase and η is a non-Gaussian phase noise with zero mean. The sampling index k is removed for simplicity. The pdf of the phase noise η was given in Chapter 4 as follows: ρψ,e(η) = 1 2π exp(−mψ,eα) + mψ,eα cos(η) π × exp[−mψ,eα sin2(η)] × 1 + erf{ 2 2mψ,eα cos(η)} where α = A2/2σn2 sin(ψ) µψ,φ = hψ(φ) mψ,e = µψ,h−ψ 1(e) erf(r) = √1 r e−v2/2dv. 2π 0 170 CHAPTER 8 Amplitude, volt 1 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 0 10 20 30 40 50 60 70 80 90 100 Time, sec Figure 8.4: Demodulation of a tone-modulated PM signal using the first-order TDTL with Am = 1, Ao = 1, fo = 1 Hz, fm = 0.05 Hz, β = 0.1, γo = −0.5, and ψo = π/2. When ψ = π/2, the above pdf reduces to: 1 ρo(η) = exp(−α) + 2π α cos(η) × exp[−α sin2(η)] π × 1 + √ erf{ 2α cos(η)} . 2 (8.12) The variance of ξ is ψ-dependent. In noisy PM demodulation, (8.4) becomes: mo(k) ≈ 1k ∆p ξ(k) + γo i=0 1k = m(k) + η(k) ∆p i=0 = m(k) + no(k) (8.13) where 1k no(k) = ∆p η(k). i=0 (8.14) The output noise no(k) is the sum of several non-Gaussian random variables with zero mean and different values of variance (ψ-dependent). The Central Limit Theorem [74] is applicable here, which confirms that no(k) is Gaussian with zero mean. SELECTED APPLICATIONS 171 Phase error, rad 1 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 0 10 20 30 40 50 60 70 80 90 100 Time, sec Figure 8.5: Phase error process associated with the demodulation of a tonemodulated PM signal using the first-order TDTL with Am = 1, Ao = 1, fo = 1 Hz, fm = 0.05 Hz, β = 0.1, γo = −0.5, and ψo = π/2. 8.3 Simulation Results The above system for PM demodulation has been simulated for the following incoming signal: x(t) = Ao sin[ωot + β sin(ωmt) + γo] (8.15) with Am = 1, Ao = 1, fo = 1 Hz, fm = 0.05 Hz, β = 0.1, γo = −0.5, and ψo = π/2. Except for a transient disturbance in case of a non-zero initial phase γo, the TDTL can efficiently demodulate the information from the carrier as shown in Figure 8.4 and Figure 8.5. The PED output phase error ranges between ess|max = 0.031 and ess|min = -0.031 as per eqs.(8.8) and (8.9). Figure 8.6 shows the time-domain performance of the above system in the presence of AWGN for SNR = 20 dB. Figure 8.7 shows the performance of the above system in the presence of AWGN for different values of the input (received) signal-to-noise ratios (SNR’s) and the modulation index β. The performance is measured in terms of the output SNR (SNRo) versus the input SNR relation as compared to the case of baseband transmission where the two SNR’s are equal. Figure 8.8 shows the performance of the above system versus analog PM demodulation in which the output SNR is related to the input SNR (or baseband SNR, SNRb) as follows [79]: SNRo = β2PmSNRb. (8.16) where Pm = pm/M 2 is the message power pm normalized with respect to M 2 = [max(m(t))]2, given by 1/2 for a tone PM. It is evident that the TDTL-based 172 CHAPTER 8 0.5 β m(t) (volt) 0 −0.5 0 10 20 30 40 50 60 70 80 90 100 Time, sec 0.5 PED Output, e(k) 0 −0.5 0 10 20 30 40 50 60 70 80 90 100 Time, sec Figure 8.6: TDTL demodulation for noisy tone PM signal with Am = 1, Ao = 1, fo = 1 Hz, fm = 0.05 Hz, γo = −0.5 rad, ψo = π/2, and β = 0.5 and received SNR = 20 dB. Dotted curves are for the noiseless case. Output SNR, dB 80 70 60 50 40 30 5 20 3 2 10 1.5 SNR b 1 0 β = 0.5 −10 −20 0 5 10 15 20 25 30 35 40 Received SNR, dB Figure 8.7: Performance of TDTL for noisy tone PM demodulation with Am = 1, Ao = 1, fo = 1 Hz, fm = 0.05 Hz, γo = 0, ψo = π/2, and different values for β. The dotted line labelled as SNRb is for baseband transmission. PM demodulation outperforms analog demodulation techniques by nearly 20 dB. 8.4 FSK and FM Demodulation This section demonstrates the results of utilizing the TDTL for the demodulation of FSK and FM signals. For these applications, the first-order loop is more suitable than the second-order one. This is due to the fact that the output level of the phase error is preserved during frequency changes, since the loop will always converge to a nonzero steady-state phase error. This is not the case SELECTED APPLICATIONS 173 Output SNR, dB 80 70 60 50 40 30 ATDnaTlLogtotnoenePMPMDeDmemodoudlualtaiotino,nβ, = β 5 = 5 20 10 SNR b 0 −10 −20 0 5 10 15 20 25 30 35 40 Received SNR, dB Figure 8.8: Performance of TDTL demodulation versus analog demodulation for noisy tone PM signal with Am = 1, Ao = 1, fo = 1 Hz, fm = 0.05 Hz, γo = 0, ψo = π/2, and β = 5. The dotted line labelled as SNRb is for baseband transmission. in the second-order loop, where each change in frequency results in a decaying impulse at the phase error, i.e., the need for extra circuitry to determine the level of the transmitted bit is prevalent. Two examples of FSK demodulation application are shown in Figure 8.9 In the first case, the modulating frequencies are chosen as 260 KHz and 280 KHz respectively, and applied to the input of the loop with a bit rate of 13 Kbps. Figure 8.9-a shows the output of the phase detector in response to the FSK input, and it is clear that this output can be sent directly to decision devices without the need for extra circuitry. This fact is also demonstrated by Figure 8.9-b, which shows the demodulated FSK bit stream of an input with a bit rate of 9 Kbps and modulating frequencies of 225 KHz and 275 KHz. The first-order TDTL can be also utilized for the detection of analogue angle modulated signals. A testing scenario was depicted, where a 10 KHz sinusoidal signal is used to frequency-modulate a carrier of 250 KHz. The FM input is then applied to the TDTL and the base-band sinusoid is recovered from the phase detector as shown in Figure 8.10. 8.5 Wideband FM Signal Detection The second-order TDTL and the adaptive second-order TDTL were used in the detection of wideband FM signals. Figure 8.11-a and Figure 8-12a show the outputs of the two loops when FM input signal with β = 7 was applied. The 174 CHAPTER 8 (a) (b) Figure 8.9: FSK demodulation using the first-order TDTL. (a) Bit rate of 13 Kbps. (b) Bit rate of 9 Kbps. SELECTED APPLICATIONS 175 Figure 8.10: FM demodulation using the first-order TDTL. 176 CHAPTER 8 Figure 8.11: Second-order TDTL response for wideband FM signal: (a) non-filtered (b) filtered. ripples were smoothed using a smoothing filter. The outputs of the two TDTL systems after the smoothing filters are illustrated in Figure 8.11-b and Figure 8.12-b. It can be clearly seen that the adaptive second-order TDTL is much better at detecting the applied wideband FM signal than the basic one. 8.6 Conclusions This chapter has presented some selected applications of the TDTL. Most importantly, it has been shown that the time-delay digital tanlock loop (TDTL) is capable of demodulating PM (and hence FM) signals in additive Gaussian noise. The basic idea was approximating the non-linear characteristic function of the loop phase error detector (and hence the system equation) under a specific arrangement of the nominal phase-shift to be a right angle. It is shown that the performance of the TDTL as a PM demodulator is comparable to that of the conventional digital tan lock loop (DTL) and is nearly 20-dB better in performance than analog PM demodulators. SELECTED APPLICATIONS 177 Figure 8.12: Adaptive second-order TDTL response for wideband FM signal: (a) non-filtered (b) filtered. Bibliography [1] D. Abramovitch, “Phase-Locked Loops: A Control Centric Tutorial,” Proceedings of the 2002 American Control Conference, AACC, IEEE, 8-10 May, 2002. [2] J. Crawford, Frequency Synthesizer Design Handbook , Artech House, 1994. [3] Sun, Yichuang, Wireless Communication Circuits and Systems, The IEE London, UK, 2004. [4] B. Razavi, RF Microelectronics, Prentice-Hall, 1998. [5] R. Best, Phase Lock Loops: Theory, Design and Applications, Prentice- Hall, 2001. [6] B. Sklar, Digital Communications Fundamentals and Applications, Prentice-Hall, 2001. [7] H. Meyer,M. Moeneclay, and S. Fechtel, Digital Communications Re- ceivers: Channel Estimation and Signal Processing, John Wiley and Sons, 1998. [8] W. Peterson and E. Weldon, Error Correcting Codes, The MIT Press, Cambridge, Mass., 2001. [9] D. R. Stephens, Phase-Locked Loops for Wireless Communications, Kluwer Academic Publishers, Boston, 1998. [10] J. L. Stensby, Phase-Locked Loops: Theory and Applications, CRC Press, New York, 1997. [11] G. Hsieh and C. Hung, “Phase-locked loop techniques - A survey,” IEEE Trans. Ind. Elect., vol. 43, no. 6, pp. 609-615, Dec. 1996. [12] W. C. Lindsey and C. M. Chie, “A survey of digital phase-locked loops,” Proc. IEEE, vol. 69, pp. 410-431, Apr. 1981. 179 180 BIBLIOGRAPHY [13] J. C. Lee and C. K. Un, “Performance analysis of digital tanlock loop,” IEEE Trans. Com., vol. COM-30, no. 10, pp. 2398-2411, Oct. 1982. [14] U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, Springer-Verlag, 2001. [15] R. Srikanteswara, R. Chembil Palat, J. H. Reed, and P. Athanas, “An overview of Configurable Computing Machines for Software Radio Handsets”, IEEE Communications Magazine, pp. 134-141, July 2003. [16] T. Wysocki, H. Razavi, and B. Honary (editors), Digital Signal Processing for Communication Systems, Kluwer Academic Publishers, Boston, 1997. [17] W. T. Greer, “Digital phase-locked loops move into analog territory,” Electronic Design, pp. 95-100, March 1982. [18] F. M. Gardner, Phase-Locked Techniques, John Wiley and Sons, New York, 1979. [19] E. M. Drogin, “Steering on course to safer air travel,” Electron., vol. 27, pp. 95-102, Nov. 1967. [20] G. Pasternack and R. L. Whalin, “Analysis and synthesis of a digital phase locked loop for FM demodulation,” Bell Sys. Tech. J., pp. 2207-2237, Dec. 1968. [21] H. Goto, “A digital phase locked loop for synchronizing digital networks,” Proc. IEEE Int. Conf. Communications, June 1970. [22] M. Yamashita et al., “Jitter reduction of a phase-locked loop,” Proc. IEEE, vol. 64, pp. 1640-1641, Nov. 1976. [23] W. E. Larimore, “Synthesis of digital phase-locked loops,” in 1968 EASCON Rec., pp. 14-20, Oct. 1968. [24] W. E. Larimore, “Design and performance of a second-order digital phaselocked loop,” Proceedings of the Symp. Computer Processing in Communications, Polytech. Inst. of Brooklyn, New York, pp. 343-357, Apr. 8-10, 1969. [25] J. Greco, J. Garodnick, and D. L. Schilling, “An all digital phase locked loop for FM demodulation,” in Proc. IEEE Int. Conf. Communications, pp. 13:7-13:12, June 1972. BIBLIOGRAPHY 181 [26] J. Greco and D. L. Schilling, “An all digital phase locked loop for FM demodulation,” in Proc. IEEE Int. Conf. Communications, vol. II, pp. 43:37-43:41, June 1973. [27] J. Garodnick, J. Greco, and D. L. Schilling, “Response of an all digital phase-locked loop,” IEEE Trans. Comm., vol. COM-22, no. 6, pp. 751-764, June 1974. [28] C. R. Cahn and D. . Leimer, “Digital phase sampling for microcomputer implementation of carrier acquisition and coherent tracking,” IEEE Trans. Comm., vol. COM-28, pp. 1190-1196, Aug. 1980. [29] H. Taub and D. L. Schilling, Principles of Communication Systems, McGraw-Hill, New York, 1986. [30] J. R. Cessna and J. D. M. Levy, “Phase noise and transient times for a binary quantized digital phase-locked loop in white Gaussian noise,” IEEE Trans. Comm. Technology, vol. COM-20, pp. 94-104, Apr. 1972. [31] J. R. Cessna, “Digital phase locked loops with sequential loop filters: A case for coarse quantization,” in Proc. Int. Telemetering Conf., vol. VIII, pp. 136-148, Oct. 1972. [32] A. Yamamoto and S. Mori, “Performance of a binary quantized all digital phase-locked loop with a new class of a sequential filter,” IEEE Trans. Communications, vol. COM-26, Jan. 1978. [33] J. K. Holmes, “Performance of a first-order transition sampling digital phase-locked loop using random walk models,” IEEE Trans. Commun. Tech., vol. COM-20, pp. 119-131, Apr. 1972. [34] C. R. Tegnelia, “A simple second-order digital phase-locked loop,” Proc. Int. Telemetring Conf., vol. VIII, pp. 108-118, Oct. 1972. [35] J. K. Holmes and C. R. Tegnelia, “A second-order all digital phase-locked loop,” IEEE Trans. Commun. Tech., vol. COM-22, pp. 62-68, Jan 1974. [36] F. D. Natali, “Accurate digital detection of angle modulated signals,” 1968 EASCON Rec., pp. 407-412, Oct. 1968. [37] F. D. Natali, “All digital coherent demodulator techniques,” Proc. Int. Telemetering Conf., vol. VIII, pp. 89-108, Oct. 1972. [38] G. S. Gill and S. C. Gupta, “First-order discrete phase-locked loop with applications to demodulation of angle-modulated carrier,” IEEE Trans. Commun. Tech., vol. COM-20, pp. 454-462, June 1972. 182 BIBLIOGRAPHY [39] G. S. Gill and S. C. Gupta, “On higher order discrete phase-locked loops,” IEEE Trans. Aerosp. Electron. Syst., vol. AES-8, pp. 615-623, Sep. 1972. [40] C. P. Reddy and S. C. Gupta, “Demodulation of FM signals by a discrete phase-locked loop,” Proc. Int. Telemetering Conf., vol. VIII, pp. 124-133, Oct. 1972. [41] C. P. Reddy and S. C. Gupta, “A class of all digital phase-locked loops: Modelling and analysis,” IEEE Transactions on Industrial Electronics and Control Instrumentation, vol. IECI-20, no. 4, pp. 239-251, Nov. 1973. [42] C. P. Reddy and S. C. Gupta, “An all digital phase-locked loop for synchronization of a sinusoidal signal embedded in white gaussian noise,” Proc. Nat. Telecommun. Conf., pp. 6E:1-9, Nov. 1973. [43] A. Weinberg and B. Liu, “Discrete time analyses of non-uniform sampling first and second-order digital phase-locked loops,” IEEE Trans. Com. Tech., vol. COM-22, pp. 123-137, Feb. 1974. [44] T. Korizumi and H. Miyakawa, “Statistical analyses of digital phase-locked loops,” IEEE Trans. Com., vol. COM-26, pp. 731-735, July 1977. [45] C. M. Chie, “Mathematical analogies between first-order digital and analog phase-locked loops,” IEEE Trans. Com., vol. COM-26, pp. 860-865, June 1978. [46] W. C. Lindsey and C. M. Chie, “Acquisition behavior of a first-order digital phase-locked loop,” IEEE Trans. Commun., vol. COM-26, pp. 13641370. [47] N. A. D’Andrea and F. Russo, “A binary quantized digital phaselocked loop: A graphical analysis,” IEEE Trans. Com., vol. COM-26, pp. 1355-1364, Sept. 1978. [48] F. Russo, “Graphical analysis of a digital phase-locked loop,” IEEE Trans. Aerosp. Electron. Syst., vol. AES-15, pp. 88-94, Jan. 1979. [49] L. F. Rocha, “Simulation of a discrete PLL with variable parameters,” Proc. IEEE, vol. 67, pp. 440-442, March 1979. [50] H. C. Osborne, “Stability analysis of an N-th power digital phase-locked loop - Part I: First-order DPLL,” IEEE Trans. Com., vol. COM-28, pp. 1343-1354, Aug. 1980. BIBLIOGRAPHY 183 [51] H. C. Osborne, “Stability analysis of an N-th power digital phase-locked loop - Part II: Second- and third-order DPLL’s,” IEEE Trans. Com, vol. COM-28, pp. 1355-1364, Aug. 1980. [52] W. D. Cho and C. K. Un, “On improving the performance of a digital tanlock loop,” Proc. IEEE, vol. 75, no. 4, p. 520-522, April 1987. [53] R. Tervo and R. Enriquez, “Analysis of digital tanlock loop with adaptive filtering,” IEEE Pacific Rim conference on Communications, Computers and Signal Processing, vol. 1, pp. 5-8, 1993. [54] Che-Ho-Wei and Wen-Jiang-Chen, “Digital tanlock loop for tracking pi/4-DQPSK signals in digital cellular radio,” IEEE Tr. Veh. Tech., vol. 43, no. 3, pp. 474-9, Aug. 1994. [55] Che-Ho-Wei and Wen-Jiang-Chen, “Digital tanlock loop for tracking pi/4-DQPSK signals in digital cellular radio,” IEEE Tr. Veh. Tech., vol. 43, no. 3, pp. 474-9, Aug. 1994. [56] J. A. Bisson and R. W. Donaldson, “Characterization and simulation of a multisampling digital tanlock loop,” IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 354-8, 1989. [57] M. Hagiwara and M. Nakagawa, “Performance of the multisampling digital tanlock loop and its extension,” Electronics - and - Communications - in - Japan - Part-1 -(Communications), vol. 72, no. 9, pp. 45-52, Sept. 1989. [58] R. Hati et al., “On the performance of a modified first-order tanlock digital phase-locked loop(DPLL),” Journal of Electrical and Electronics Engineering - Australia, vol. 18, no. 1, pp. 21-26, June 1998. [59] R. Hati et al., “Simulation studies on the dynamical behaviour of a second order Tanlock digital phase locked loop (DPLL),” Journal of Electrical and Electronics Engineering - Australia, vol. 18, no. 1, pp. 27-32, June 1998. [60] L. R. Rabiner and R. W. Shafer, “On the behaviour of minimax FIR digital Hilbert transformers,” The Bell System Technical Journal, vol. 53, Feb. 1974. [61] S. L. Hahn, Hilbert Transforms in Signal Processing, Artech House, 1996. [62] A. V. Oppenheim, R. W. Shaffer, and J. R. Buck, Discrete-Time Signal Processing, Prentice-Hall, New Jersey, 1999. 184 BIBLIOGRAPHY [63] M. Schwartz, W. R. Bennett, and S. Stein, Communication Systems and Techniques, IEEE Press, New York, 1995. [64] B. Boashash (editor), Time-Frequency Signal Analysis, Longman Cheshire, Melbourne, Australia, 1992. [65] B. Boashash, “Estimating and interpreting the instantaneous frequency of a signal,” Proc. IEEE, vol. 8, no. 4, pp. 520-568, 1992. [66] B. Boashash, “Time-frequency signal analysis,” In: Advances in Spectrum Estimation (S. Haykin: editor), Prentice-Hall, NJ, 1991. [67] B. Boashash, “Note on the use of the Wigner distribution for timefrequency analysis,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 36, no. 9, pp. 1518-1521, Sept. 1988. [68] J. C. Lee and C. K. Un, “Performance analysis of digital tanlock loop,” IEEE Transactions on Communications, vol. COM-30, no. 10, pp. 2398-2411, Oct. 1982. [69] L. R. Rabiner and R. W. Shafer, “On the behavior of minimax FIR digital Hilbert transformers,” The Bell System Technical Journal, vol. 53, Feb. 1974. [70] Z. M. Hussain, B. Boashash, and S. R. Al-Araji, “A time-delay digital tanlock loop,” Proceedings of the Fifth International Symposium on Signal Processing and its Applications (ISSPA’99), vol. 1, pp. 391-394, Brisbane, Queensland, Australia, 22-25 Aug. 1999. [71] Z. M. Hussain, B. Boashash, M. Hassan-Ali, and S. R. Al-Araji, “A time-delay digital tanlock loop,” IEEE Transactions on Signal Processing, vol. 49, no. 8, Aug. 2001. [72] Z. M. Hussain and B. Boashash, “Statistical analysis of the time-delay digital tanlock loop in the presence of Gaussian noise,” IEEE International Symposium on Circuits and Systems, Sydney, May 6-9, 2001. [73] Z. M. Hussain, “Performance Analysis of the Time-Delay Phase-Shifter in Additive Gaussian Noise: A Statistical Comparison with Hilbert Transformer,” Proceedings of the Sixth International Symposium on Signal Processing and Its Applications (ISSPA’2001), Kuala Lumpur, 13-16 Aug. 2001. [74] P. Z. Peebles, Jr., Probability, Random Variables, and Random Signal Principles, McGraw-Hill, New York, 1993. BIBLIOGRAPHY 185 [75] S. M. Kay, Modern Spectral Estimation: Theory and Application, PrenticeHall, New Jersey, 1988. [76] J. Pierpont, Lectures on the Theory of Functions of Real Variables, Dover Publications, New York, 1912. [77] A. V. Oppenheim, A. S. Willsky, and S. H. Nawab, Signals and Systems, Prentice Hall, New Jersey, 1997. [78] M. Abramowitz and I. A. Stegun (editors), Handbook of Mathematical Functions, U.S. Govt. Printing Office, Washington, 1972. [79] J. Proakis and M. Salehi, Communications Systems Engineering, Prentice-Hall, 2002. [80] J. Proakis, Digital Communications, 4th ed., New York, McGraw-Hill, 2000. [81] W. Peterson and E. Weldon, Error Correcting Codes, The MIT Press, Cambridge, Mass., 1972. [82] Z. M. Hussain, B. Boashash, Statistical Analysis of the Time Delay Digital Tanlock Loop, Proc. of the IEEE International Symposium on Circuits and Systems, vol. 4, 6-9 May 2001, pp 21-24. [83] N. Al-Moosa, S. Al-Araji and M. Al-Qutayri, Fast Acquisition Digital Tanlock Loop with Adaptive Time Delay, IEEE Region 10 Technical Conference on Analog and Digital Techniques in Electrical Engineering, Bangkok, Thailand, 21-24 November 2004. [84] S. Al-Araji, M. Al-Qutayri and N. Al-Moosa, An Adaptive Time Delay Digital Tanlock Loop with Improved Range, Proceedings of the 16th Annual International Conference on Wireless Communications, Calgary, Canada, 12-14 July 2004. [85] S. Al-Araji, M. Al-Qutayri and N. Al-Moosa, Digital Tanlock Loop with Extended Locking Range using Variable Time Delay, Proceedings of the IEEE Midwest Symposium on Circuits and Systems, Hiroshima, Japan, 25-28 July, 2004. [86] S. Hauck, The Roles of FPGAs in Reprogrammable Systems, Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-638, April 1998. [87] K. Compton and S. Hauck, Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Surveys, Vol. 34, No. 2. pp. 171-210. June 2002. 186 BIBLIOGRAPHY [88] K. Bondalapati and V. Prasanna, Reconfigurable Computing systems, Proceedings of the IEEE, Vol. 90, No. 7, pp. 1201-1217, July 2002. [89] D. A. Buell, J. P. Davis and G. Quan, Reconfigurable Computing Applied to Problems in Communications Security, Proc. 5th MAPLD Int. Conference, Sept. 10-12, 2002. [90] J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, “Architecture of FieldProgrammable Gate Arrays”, Proceedings of the IEEE, Vol. 81, No. 7, pp. 1013-1029, July 1993. [91] S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw Hill, 2000. [92] J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, Architecture of FieldProgrammable Gate Arrays, Proceedings of the IEEE, Vol. 81, No. 7, pp. 1013-1029, July 1993. [93] S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw Hill, 2000. [94] C. Maxfield, The Design Warrior’s Guide to FPGAs: Devices, Tools and Flows, Newnes-Elsevier, 2004. [95] W. Wolf, FPGA-Based System Design, Prentice Hall, 2004. [96] The Programmable Logic Data Book , Xilinx Inc., 1994. [97] D. Van den Bout, The Practical Xilinx Designer Lab Book , Prentice Hall, 1999. [98] XtremeDSP Development Kit-II User guide. NT107-0196. Nallatech Limited. 2003. [99] Xilinx System Generator V2.1 Reference Guide. [100] Andraka, Ray, A Survey of CORDIC Algorithms for FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, Feb. 22-24, 1998, Monterey, CA. pp. 191-200. [101] J. S. Walther, A Unified Algorithm for Elementary Functions, Spring Joint Computer Conference (1971) pp. 379-385. [102] Yu Hen Hu, CORDIC-Based VLSI Architectures for Digital Signal Processing, IEEE Signal Processing Magazine, pp. 17-34, July 1992. BIBLIOGRAPHY 187 [103] Xilinx LogiCore Direct Digital Synthesizer V4.1 , Xilinx Inc. March 2001. [104] Z. M. Hussain, “Performance of the Time-Delay Digital Tanlock Loop as PM Demodulator in Additive Gaussian Noise,” Proceedings of IEEE TENCON 2005, Melbourne, Australia, Nov. 2005. [105] S. Al-Araji, M. Al-Qutayri and A. Al-Zaabi, Adaptive TDTL with Enhanced Performance using Sample Sensing Technique, Proceedings of the IEEE Int. Symp. on Circuits and Systems, Greece, 21-24 May, 2006. [106] A. Al-Zaabi, M. Al-Qutayri, S. Al-Araji, Nonuniform Sampling Digital PLL with Fast Error Correction Technique, Proceedings of the IEEE Int. Conference on Electronic Circuits and Systems, Tunisia, 11-14 Dec., 2005. [107] K. Al-Zaabi, S. Al-Araji and M. Al-Qutayri, Wideband FM Detection using an Adaptive Second Order TDTL, Proceedings of the IEEE Int. Symp. on Consumer Electronics, Hong Khong, 14-16 June, 2005. [108] T. Speers, J. J. Wang, B. Cronquist, J. McCollum, H. Tseng, R. Katz and I. Kleyner, 0.25 micron FLASH memory based FPGA for space applications, Proc. MAPLD Int. Conference, Sept. 28-30, 1999. [109] T. Egan and S. Mourad, A Framework for the Characterization and Verification of Embedded Phase-Locked Loops, IEEE Transactions on Instrumentation and Measurement, Vol. 51, No. 6, pp. 1234-1239, Dec. 2002. [110] M. Al-Qutayri, S. Al-Araji and N. Al-Moosa, Implementation of Reconfigurable Time Delay Digital Tanlock Loop, SPIE Int. Symposium on Smart Structures, Devices, and Systems II (Smart Materials, Nano- and MicroSmart Systems), pp. 110-117, Sydney, Australia, 12-15 Dec. 2004. [111] S. Al-Araji, M. Al-Qutayri and M. Al-Qayed, Rapid Acquisition Adaptive Zero-Crossing DPLL, SPIE Int. Symposium on Smart Structures, Devices, and Systems II (Smart Materials, Nano- and Micro-Smart Systems), pp. 659-665, Sydney, Australia, 12-15 Dec. 2004. [112] S. Al-Araji, B. Majeed, and Z. Hussain, A High Performance Time Delay Digital Tanlock Loop, Proceedings of the International Signal Processing Conference (ISPC), Dallas, Texas, March 31-April 3, 2003. Index Acquisition, 3, 10, 15, 87, 89–90, 123, 130, 135, 151 Adaptive gain, 94–103, 104f, 106f, 107f, 122f, 133, 135 Arctan, 16, 30, 32, 36, 73, 90, 152, 168 AWGN, 169, 171 Bandwidth, 10, 114, 121, 123, 129 Central limit theory, 170 Configurable logic block, 138, 142, 146f Convergence, 15–16, 41, 43, 45–49, 51, 86, 89–90 CORDIC, 151–152, 154–156 Cramer-Rao bounds, 62–65, 74–76, 78f Delay switching, 89–94, 100–105, 133, 135 Delay unit, 31–33, 69–70, 89, 100, 113–114, 122f, 157 Digital controlled oscillator (DCO), 16f, 17, 27, 28f, 29, 32, 108f, 121, 152–154 Digital filter, 8, 15, 16f, 17–18, 22, 25–26, 29, 32, 34–35, 43, 46, 70, 89f, 96–97, 100, 103, 105, 108, 113, 121, 123, 133, 154–155, 157 Digital phase locked loops (DPLL) - Exclusive-OR, 17, 22–23, 24f - Flip-flop, 16–17, 18f, 142, 144f, 145f - Lead-lag, 17, 20, 21f - Nonuniform sampling, 17, 30–31, 48 - Nyquist rate, 17–18, 19f, 20 - Uniform sampling, 16–17, 25, 30 - Zero-Crossing, 16–17, 25, 30 Digital tanlock loop (DTL), 16, 25, 29, 31–49, 66, 69–83, 166f, 176 Direct digital synthesis (DDS), 152 Error Sensing, 105, 108, 113–115, 135 Field programmable gate arrays (FPGA) - Antifuse, 139–140, 141f - Flash, 139–141, 142f - Interconnect, 138 - Logic block, 139f, 141–142, 146f - Static RAM, 140 Filter coefficients, 121, 122f, 123, 124f, 125f, 135 Finite state machine (FSM), 88–89, 121, 122f, 129f, 159 Fixed point analysis, 16, 30, 44, 46 Frequency ratio (W), 46, 85, 100, 109f, 115, 126, 166f, 168f Frequency shift keying (FSK), 3, 37, 42, 43f, 165, 172–173, 174f Hilbert transformer, 29, 31, 48, 51–67, 69, 76 Hold range, 13 189 190 Independent locking, 32, 37–42, 44–48 Lock Range, 13, 16, 23, 29–30, 32, 37–38, 41, 44–46, 48, 159, 166–168 Locking boundary, 96–97, 100, 103, 108, 121 Locking speed, 15, 41, 45–48, 52 Look-up table (LUT), 138, 141–142, 143f–146f, 153 Loop filter, 4–6, 8–10, 11f, 21f, 29, 32, 87, 123, 159f Loop gain (K1), 12, 32, 49, 87, 90, 96, 100, 109f, 123, 126f, 128f, 135, 157, 168f Matlab/Simulink, 137, 147, 149, 161 Modulation index, 165, 171 Multiplexers, 138, 140–142 Negative step, 85, 86f, 108, 118, 119f Noise analysis, 53, 70–81 PM demodulation, 165–172, 173f Positive step, 85, 88f Phase detector (PD), 4–6, 11, 13, 15–17, 20, 22, 32, 35, 43, 89f, 96, 103f, 105, 108f, 122f, 129f, 151, 157, 173 Phase error, 4–7, 12–13, 16–17, 22–23, 25–26, 29–32, 33f, 34–37, 39, 41, 42f, 43, 45–49, 66, 69, 71–74, 81–82, 86–89, 90, 94, 96–97, 103, 105, 109, 114, 115f, 116f, 118f, 120–121, 123, 129–130, 151, 157, 159, 166–168, 171–173, 176 Phase error detector (PED), 16f, 22, 29–32, 33f, 34–36, 43, 46, 48, 66, 69, 71–73, 77–79, 81–82, 167, 176 INDEX Phase estimator, 62–63, 64f, 65–67, 74–77, 78f Phase locked loop (PLL) - Analog, 4–6 - Digital, 16f, 46 - Linear, 11–13 Phase noise - Variance, 58–63, 77f, 169 - PDF, 57–58 Phase plane, 11, 41, 85, 90, 92f, 93f, 97, 99f, 105, 106f, 107f, 109, 111f, 115, 117f, 125f, 127f–128f, 130, 131f, 133f–134f Probability density function (PDF), 54–58, 59f, 60f, 67, 72–74, 76f, 77f Real-time TDTL results, 137, 156–157, 158f, 159, 160f, 161 Reconfigurable systems, 137–138, 162 Sample and Hold, 149 Sample sensing, 105–113, 135, 156, 159–161 Sampler, 26f, 29, 32, 33f, 89–90, 96f, 100, 103f, 108f, 113f, 122f, 129f, 167f Signal to noise ratio (SNR), 3, 53, 67, 69, 82, 96, 108, 123, 130, 171 Steady state phase error, 28, 30, 39–40, 79–80, 82f, 86–88, 105, 109, 115, 123, 129–130, 168, 172 Symmetric transformation, 65–66 Synchronization, 1–4, 13, 165 Time delay, 16, 31–49, 51–67, 69–83, 85, 87f, 89–90, 100, 103, 108f, 109, 113f, 114, 122f, 129f, 157, 166f, 176 INDEX Time delay tanlock loop (TDTL) - First order TDTL, 35–43, 46–49, 78–83, 85–91, 115, 129–133, 157–175 - Second order TDTL, 32, 81–82, 115–123, 124f, 125f, 126f, 127f, 128f, 129–130, 132f, 133–135, 157–159, 173f, 176, 177f - Variable order TDTL, 85, 120–123, 130f, 133, 134f Tracking, 2–4, 8, 13, 37, 43f, 80, 82, 86, 90, 91f, 103, 118f, 120f, 165 191 Transient response, 90, 92f, 93f, 94, 95f, 98f, 101f–102f, 103, 105, 106f, 107f, 123, 124f, 127f, 131f–132f, 133, 134f, 158f, 160f, 163f Voltage controlled oscillator (VCO), 4–5, 7–10, 11f, 15, 18 Wide band FM, 165 Xilinx, 142, 144f, 145f, 146f, 147, 149, 150f, 153 Xtreme DSP, 142–146, 147f, 148f, 161 Zero-crossing PLL, 16–17, 25–30
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