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TH1621B中文资料

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    HT1621B中文资料

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    HT1621/HT1621G RAM Mapping 32´4 LCD Controller for I/O MCU PATENTED PAT No. : TW 099352 Features · Operating voltage: 2.4V~5.2V · Built-in 256kHz RC oscillator · External 32.768kHz crystal or 256kHz frequency source input · Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty LCD applications · Internal time base frequency sources · Two selectable buzzer frequencies (2kHz/4kHz) · Power down command reduces power consumption · Built-in time base generator and WDT · Time base or WDT overflow output · 8 kinds of time base/WDT clock sources · 32´4 LCD driver · Built-in 32´4 bit display RAM · 3-wire serial interface · Internal LCD driving frequency source · Software configuration feature · Data mode and command mode instructions · R/W address auto increment · Three data accessing modes · VLCD pin for adjusting LCD operating voltage · HT1621: 44-pin LQFP package HT1621B: 48-pin SSOP/LQFP packages HT1621G: Gold bumped chip General Description The HT1621 is a 128 pattern (32´4), memory mapping, and multi-function LCD driver. The S/W configuration feature of the HT1621 makes it suitable for multiple LCD applications including LCD modules and display sub- systems. Only three or four lines are required for the interface between the host controller and the HT1621. The HT1621 contains a power down command to reduce power consumption. Selection Table HT162X HT1620 COM 4 SEG 32 Built-in Osc. ¾ Crystal Osc. Ö HT1621 4 32 Ö Ö HT1622 8 32 Ö ¾ HT16220 8 32 ¾ Ö HT1623 8 48 Ö Ö HT1625 8 64 Ö Ö HT1626 16 48 Ö Ö Rev. 3.20 1 November 25, 2014 Block Diagram PATENTED HT1621/HT1621G O SCO O SCI CS RD WR D ATA VDD VSS BZ BZ C o n tro l and T im in g C ir c u it D is p la y R A M L C D D r iv e r / B ia s C ir c u it T o n e F re q u e n c y G e n e ra to r W a tc h d o g T im e r and T im e B a s e G e n e r a to r COM 0 COM 3 SEG 0 S E G 31 V LC D IR Q Note: CS: Chip selection BZ, BZ: Tone outputs WR, RD, DATA: Serial interface COM0~COM3, SEG0~SEG31: LCD outputs IRQ: Time base or WDT overflow output Pin Assignment SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 CS RD WR D ATA VSS O SCO O SCI V LC D VDD IR Q BZ BZ COM 0 COM 1 COM 2 COM 3 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 H T1621B 4 8 S S O P -A SEG 8 SEG 9 S E G 10 S E G 11 S E G 12 S E G 13 S E G 14 S E G 15 S E G 16 S E G 17 S E G 18 S E G 19 S E G 20 S E G 21 S E G 22 S E G 23 S E G 24 S E G 25 S E G 26 S E G 27 S E G 28 S E G 29 S E G 30 S E G 31 S E G 24 S E G 25 S E G 26 S E G 28* S E G 27* S E G 29 S E G 30 S E G 31 COM 3 COM 2 COM 1 COM 0 S E G 22 S E G 23 S E G 24 S E G 25 S E G 26 S E G 27 S E G 28 S E G 29 S E G 30 S E G 31 COM 3 S E G 11 S E G 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 S E G 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 CS RD WR D ATA VSS V LC D VDD BZ COM 0 COM 1 COM 2 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 H T1621 29 6 28 7 4 4 L Q F P -A 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 S E G 11 S E G 12 S E G 13 S E G 14 S E G 15 S E G 16 S E G 17 S E G 18 S G E 19 S E G 20 S E G 21 CS RD WR D ATA VSS O SCO O SCI V LC D VDD IR Q BZ BZ 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 H T1621B 31 7 4 8 L Q F P -A 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 S E G 12 S E G 13 S E G 14 S E G 15 S E G 16 S E G 17 S E G 18 S G E 19 S E G 20 S E G 21 S E G 22 S E G 23 N o te : * P le a s e n o te th a t in th e 4 8 - p in L Q F P p a c k a g e , th e S E G 2 7 a n d S E G 2 8 p in s a r e n o t in s e q u e n tia l o r d e r . Rev. 3.20 2 November 25, 2014 Pad Assignment PATENTED HT1621/HT1621G S E G 15 S E G 14 S E G 13 S E G 12 S E G 11 S E G 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 CS 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RD 2 WR 3 D ATA 4 (0 ,0 ) VSS 5 O SCO 6 O SCI 7 V LC D 8 VDD 9 IR Q 10 11 12 13 14 15 16 17 18 19 32 S E G 16 31 S E G 17 30 S E G 18 29 S E G 19 28 S E G 20 27 S E G 21 26 S E G 22 25 S E G 23 24 S E G 24 23 S E G 25 22 S E G 26 21 S E G 27 20 S E G 28 S E G 29 S E G 30 S E G 31 COM 3 COM 2 COM 1 COM 0 BZ BZ Chip size: 82 ´ 83 (mil)2 Bump height: 18mm ± 3mm Min. Bump spacing: 23.02mm Bump size: 76 ´ 76mm2 * The IC substrate should be connected to VDD in the PCB layout artwork. Rev. 3.20 3 November 25, 2014 PATENTED HT1621/HT1621G Pad Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 X -802.951 -927.055 -927.055 -927.055 -925.358 -925.358 -925.785 -925.785 -925.699 -896.840 -637.515 -452.726 -288.935 -189.915 -84.350 14.669 114.260 213.320 312.380 925.915 925.915 925.915 925.915 925.915 Y 939.295 343.250 244.230 89.374 -52.510 -151.360 -566.516 -675.287 -773.697 -939.537 -935.685 -935.685 -935.685 -935.685 -935.685 -935.685 -940.130 -940.130 -940.130 -867.615 -768.555 -669.495 -570.435 -437.375 Pad No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 X 925.915 925.915 925.915 925.915 925.915 925.915 925.915 925.915 849.589 750.530 651.469 552.409 453.349 354.289 255.230 156.169 57.109 -41.951 -141.010 -240.070 -339.130 -438.190 -537.250 -636.310 Unit: mm Y -338.315 -239.255 -140.195 -41.134 57.925 156.986 256.046 355.106 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 Pad Description Pad No. Pad Name 1 CS 2 RD 3 WR 4 DATA 5 VSS 7 OSCI 6 OSCO 8 9 10 11, 12 13~16 48~17 VLCD VDD IRQ BZ, BZ COM0~COM3 SEG0~SEG31 I/O Function Chip selection input with pull-high resistor When the CS is logic high, the data and command read from or written to I the HT1621 are disabled. The serial interface circuit is also reset. But if CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1621 are all enabled. READ clock input with pull-high resistor I Data in the RAM of the HT1621 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the DATA line. The host control- ler can use the next rising edge to latch the clocked out data. WRITE clock input with pull-high resistor I Data on the DATA line are latched into the HT1621 on the rising edge of the WR signal. I/O Serial data input/output with pull-high resistor ¾ Negative power supply, ground I The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But O if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. I LCD power input ¾ Positive power supply O Time base or WDT overflow flag, NMOS open drain output O 2kHz or 4kHz tone frequency output pair O LCD common outputs O LCD segment outputs Rev. 3.20 4 November 25, 2014 PATENTED HT1621/HT1621G Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+5.5V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50oC to 125oC Operating Temperature...........................-40oC to 85oC Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter VDD Operating Voltage Test Conditions VDD Conditions ¾ ¾ Min. 2.4 IDD1 Operating Current 3V No load/LCD ON ¾ 5V On-chip RC oscillator ¾ IDD2 Operating Current 3V No load/LCD ON ¾ 5V Crystal oscillator ¾ IDD3 Operating Current 3V No load/LCD ON ¾ 5V External clock source ¾ ISTB Standby Current 3V ¾ No load, Power down mode 5V ¾ VIL Input Low Voltage 3V 0 DATA, WR, CS, RD 5V 0 VIH Input High Voltage 3V 2.4 DATA, WR, CS, RD 5V 4.0 IOL1 DATA, BZ, BZ, IRQ 3V VOL=0.3V 5V VOL=0.5V IOH1 DATA, BZ, BZ 3V VOH=2.7V 5V VOH=4.5V IOL2 LCD Common Sink Current 3V VOL=0.3V 5V VOL=0.5V 3V VOH=2.7V IOH2 LCD Common Source Current 5V VOH=4.5V IOL3 LCD Segment Sink Current 3V VOL=0.3V 5V VOL=0.5V 3V VOH=2.7V IOH3 LCD Segment Source Current 5V VOH=4.5V 0.5 1.3 -0.4 -0.9 80 150 -80 -120 60 120 -40 -70 RPH Pull-high Resistor 3V 60 DATA, WR, CS, RD 5V 30 Typ. ¾ 150 300 60 120 100 200 0.1 0.3 ¾ ¾ ¾ ¾ 1.2 2.6 -0.8 -1.8 150 250 -120 -200 120 200 -70 -100 120 60 Ta=25°C Max. Unit 5.2 V 300 mA 600 mA 120 mA 240 mA 200 mA 400 mA 5 mA 10 mA 0.6 V 1.0 V 3.0 V 5.0 V ¾ mA ¾ mA ¾ mA ¾ mA ¾ mA ¾ mA ¾ mA ¾ mA ¾ mA ¾ mA ¾ mA ¾ mA 200 kW 100 kW Rev. 3.20 5 November 25, 2014 PATENTED HT1621/HT1621G A.C. Characteristics Ta=25°C Symbol Parameter fSYS1 fSYS2 fSYS3 System Clock System Clock System Clock fLCD LCD Clock tCOM fCLK1 LCD Common Period Serial Data Clock (WR pin) Test Conditions VDD Conditions Min. Typ. Max. Unit 3V On-chip RC oscillator 192 256 320 kHz ¾ Crystal oscillator ¾ 32768 ¾ Hz ¾ External clock source ¾ 256 ¾ kHz ¾ On-chip RC oscillator ¾ fSYS1/1024 ¾ Hz ¾ Crystal oscillator ¾ fSYS2/128 ¾ Hz ¾ External clock source ¾ fSYS3/1024 ¾ Hz ¾ n: Number of COM ¾ n/fLCD ¾ s 3V Duty cycle 50% 5V 4 ¾ 150 kHz 4 ¾ 300 kHz fCLK2 fTONE tCS Serial Data Clock (RD pin) Tone Frequency (2kHz) Tone Frequency (4kHz) Serial Interface Reset Pulse Width (Figure 3) 3V Duty cycle 50% 5V ¾ ¾ 75 kHz ¾ ¾ 150 kHz 1.5 2.0 2.5 kHz 3V On-chip RC oscillator 3.0 4.0 5.0 kHz ¾ CS 250 300 ¾ ns tCLK WR, RD Input Pulse Width (Figure 1) Write mode 3V Read mode Write mode 5V Read mode 3.34 ¾ 6.67 ¾ 1.67 ¾ 3.34 ¾ 125 ms ¾ 125 ms ¾ tr, tf Rise/Fall Time Serial Data Clock Width (Figure 1) ¾ ¾ ¾ 120 160 ns tsu Setup Time for DATA to WR, RD Clock Width (Figure 2) ¾ ¾ 60 120 ¾ ns th Hold Time for DATA to WR, RD Clock Width (Figure 2) ¾ ¾ 250 300 ¾ ns tsu1 Setup Time for CS to WR, RD Clock Width (Figure 3) ¾ ¾ 500 600 ¾ ns th1 Hold Time for CS to WR, RD Clock Width (Figure 3) ¾ ¾ 250 300 ¾ ns tOFF VDD OFF Times (Figure 4) ¾ VDD drop down to 0V 20 ¾ ¾ ms tSR VDD Rising Slew Rate (Figure 4) ¾ ¾ 0.05 ¾ ¾ V/ms tRSTD Delay Time after Reset (Figure 4) ¾ ¾ 1 ¾ ¾ ms Note: 1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal Power-on Reset (POR) circuit will not operate normally. 2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for 20ms (min.) before rising to the normal operating voltage. Rev. 3.20 6 November 25, 2014 PATENTED HT1621/HT1621G tf tr V a lid D a ta V DD W R ,R D 90% C lo c k 50% 10% tC L K tC L K V DD DB GND 50% ts u th GND Figure 1 W R ,R D C lo c k V DD 50% GND Figure 2 CS W R ,R D C lo c k tC S 50% ts u 1 th 1 50% F ir s t C lo c k L a s t C lo c k Figure 3 VDD V DD GND 0V V DD GND CS tS R tO F F 0 .9 V D D tR S T D Figure 4 Power-on Reset Timing Rev. 3.20 7 November 25, 2014 PATENTED HT1621/HT1621G Functional Description Display Memory - RAM The static display memory (RAM) is organized into 32´4 bits and stores the displayed data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE, and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD pattern: COM 3 COM 2 COM 1 COM 0 SEG 0 0 SEG 1 1 SEG 2 SEG 3 2 3 A d d r e s s 6 b its (A 5 , A 4 , ..., A 0 ) S E G 31 D3 D2 D1 D0 D a ta 4 b its (D 3 , D 2 , D 1 , D 0 ) 31 A ddr D a ta RAM Mapping System Oscillator The HT1621 system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The source of the clock may be from an on-chip RC oscillator (256kHz), a crystal oscillator (32.768kHz), or an external 256kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is, however, available only for the on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT lose its function as well. The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case in the external 256kHz clock source operation. At the initial system power on, the HT1621 is at the SYS DIS state. Time Base and Watchdog Timer (WDT) The time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate an accurate time base. The watch dog timer (WDT), on the other hand, is composed of an 8-stage time base generator along with a 2-stage count-up counter, and is designed to break the host controller or other subsystems from abnormal states such as unknown or unwanted jump, execution errors, etc. The WDT time-out will result in the setting of an internal WDT time-out flag. The outputs of the time base generator and of the WDT time-out flag can be connected to the IRQ output by a command option. There are totally eight frequency sources available for the time base generator and the WDT clock. The frequency is calculated by the following equation. 32kHz fWDT = 2n where the value of n ranges from 0 to 7 by command options. The 32kHz in the above equation indicates that the source of the system frequency is derived from a crystal oscillator of 32.768kHz, an on-chip oscillator (256kHz), or an external frequency of 256kHz. If an on-chip oscillator (256kHz) or an external 256kHz frequency is chosen as the source of the system frequency, the frequency source is by default prescaled to 32kHz by a 3-stage prescaler. Employing both the time base generator and the WDT related commands, one should be careful since the time base generator and WDT share the same 8-stage counter. For example, invoking the WDT DIS command disables the time base generator whereas executing the WDT EN command not only enables the time base generator but activates the WDT time-out flag output (connect the WDT O SCI O SCO C r y s ta l O s c illa to r 32768H z E x te r n a l C lo c k S o u r c e 256kH z 1 /8 O n - c h ip R C O s c illa to r 256kH z System Oscillator Configuration S y s te m C lo c k Rev. 3.20 8 November 25, 2014 PATENTED HT1621/HT1621G T im e r /W D T S y s te m C lo c k C lo c k S o u r c e s /2 n /2 5 6 f= 3 2 k H z n=0~7 T IM E R E N /D IS V D D W D T E N /D IS IR Q D Q W DT /4 CK R C LR W D T Timer and WDT Configurations IR Q E N /D IS time-out flag to the IRQ pin). After the TIMER EN command is transferred, the WDT is disconnected from the IRQ pin, and the output of the time base generator is connected to the IRQ pin. The WDT can be cleared by executing the CLR WDT command, and the contents of the time base generator is cleared by executing the CLR WDT or the CLR TIMER command. The CLR WDT or the CLR TIMER command should be executed prior to the WDT EN or the TIMER EN command respectively. Before executing the IRQ EN command the CLR WDT or CLR TIMER command should be executed first. The CLR TIMER command has to be executed before switching from the WDT mode to the time base mode. Once the WDT time-out occurs, the IRQ pin will stay at a logic low level until the CLR WDT or the IRQ DIS command is issued. After the IRQ output is disabled the IRQ pin will remain at the floating state. The IRQ output can be enabled or disabled by executing the IRQ EN or the IRQ DIS command, respectively. The IRQ EN makes the output of the time base generator or of the WDT time-out flag appear on the IRQ pin. The configuration of the time base generator along with the WDT are as shown. In the case of on-chip RC oscillator or crystal oscillator, the power down mode can reduce power consumption since the oscillator can be turned on or off by the corresponding system commands. At the power down mode the time base/WDT loses all its functions. On the other hand, if an external clock is selected as the source of system frequency the SYS DIS command turns out invalid and the power down mode fails to be carried out. That is, after the external clock source is selected, the HT1621 will continue working until system power fails or the external clock source is removed. After the system power on, the IRQ will be disabled. Tone Output A simple tone generator is implemented in the HT1621. The tone generator can output a pair of differential driving signals on the BZ and BZ, which are used to generate a single tone. By executing the TONE4K and TONE2K commands there are two tone frequency outputs selectable. The TONE4K and TONE2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned on or off by invoking the TONE ON or the TONE OFF command. The tone outputs, namely BZ and BZ, are a pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ outputs will remain at low level. LCD Driver The HT1621 is a 128 (32´4) pattern LCD driver. It can be configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of LCD driver by the S/W configuration. This feature makes the HT1621 suitable for multiply LCD applications. The LCD driving clock is derived from the system clock. The value of the driving clock is always 256Hz even when it is at a 32.768kHz crystal oscillator frequency, an on-chip RC oscillator frequency, or an external frequency. The LCD corresponding commands are summarized in the table. The bold form of 1 0 0, namely 1 0 0, indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command, will be omitted. The LCD OFF command turns the LCD display off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns the LCD display on by enabling the LCD bias generator. The BIAS and COM are the LCD panel related com- Name LCD OFF LCD ON BIAS & COM Command Code 10000000010X 10000000011X 1000010abXcX Function Turn off LCD outputs Turn on LCD outputs c=0: 1/2 bias option c=1: 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option Rev. 3.20 9 November 25, 2014 PATENTED HT1621/HT1621G mands. Using the LCD related commands, the HT1621 can be compatible with most types of LCD panels. Command Format The HT1621 can be configured by the S/W setting. There are two mode commands to configure the HT1621 resources and to transfer the LCD display data. The configuration mode of the HT1621 is called command mode, and its command mode ID is 1 0 0. The command mode consists of a system configuration command, a system frequency selection command, a LCD configuration command, a tone frequency selection command, a timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following are the data mode IDs and the command mode ID: Operation Mode ID Read Write Read-Modify-Write Command Data Data Data Command 110 101 101 100 The mode command should be issued before the data or command is transferred. If successive commands have been issued, the command mode ID, namely 1 0 0, can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to ²1² and the previous operation mode will be reset also. Once the CS pin returns to ²0² a new operation mode ID should be issued first. Interfacing Only four lines are required to interface with the HT1621. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1621. If the CS pin is set to 1, the data and command issued between the host controller and the HT1621 are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the HT1621. The DATA line is the serial data input/output line. Data to be read or written or commands to be written have to be passed through the DATA line. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DATA line. It is recommended that the host controller read in correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DATA line are all clocked into the HT1621 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1621. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by being connected with the IRQ pin of the HT1621. Crystal Selection A 32768Hz crystal can be directly connected to the HT1621 via OSCI and OSCO. In order to obtain the correct frequency, two additional load capacities (C1, C2) are needed. The value of the capacity depends on how accurate the crystal is. We suggest that you can follow the table, which suggests the value of capacities. The table illustrates the suggestion value of capacities (C1, C2). O SCI 32768H z C1 C2 O SCO Crystal Error ±10ppm 10~20ppm Capacity Value 0~10p 10~20p Timing Diagrams READ Mode (Command Code : 1 1 0) CS WR RD D ATA 1 1 0 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) 1 1 0 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 ) Rev. 3.20 10 November 25, 2014 PATENTED READ Mode (Successive Address Reading) CS HT1621/HT1621G WR RD D ATA 1 1 0 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) WRITE Mode (Command Code : 1 0 1) CS WR D ATA 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 ) WRITE Mode (Successive Address Writing) CS WR D ATA 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) Read-Modify-Write Mode (Command Code : 1 0 1) CS WR RD D ATA 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) D a ta (M A 1 ) 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 ) Rev. 3.20 11 November 25, 2014 PATENTED Read-Modify-Write Mode (Successive Address Accessing) HT1621/HT1621G CS WR RD D ATA 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 1 ) D a ta (M A + 2 ) Command Mode (Command Code : 1 0 0) CS WR D ATA 1 0 0 C8 C7 C6 C5 C4 C3 C2 C1 C0 C8 C7 C6 C5 C4 C3 C2 C1 C0 C om m and 1 C o m m a n d ... C om m and i C om m and or D a ta M o d e Mode (Data and Command Mode) CS WR D ATA RD C om m and or A d d re s s & D a ta D a ta M o d e C om m and or A d d re s s a n d D a ta D a ta M o d e C om m and or A d d re s s a n d D a ta D a ta M o d e Note: It is recommended that the host controller should read in the data from the DATA line between the rising edge of the RD line and the falling edge of the next RD line. Rev. 3.20 12 November 25, 2014 PATENTED HT1621/HT1621G Application Circuits Host Controller with an HT1621 Display System M CU C lo c k u t E x te r n a l C o lc k 1 E x te r n a l C o lc k 2 n -c h p S C C ry s ta l 32768H z C1 C2 CS * RD VDD WR V LC D D ATA H T1621B *R BZ IR Q SCI BZ SC C M 0 ~ C M 3 S E G 0~S E G 31 1 /2 o r 1 /3 B a s ; 1 /2 , 1 /3 o r 1 /4 D u ty LC D P anel * VR P ezo Note: The connection of IRQ and RD pin can be selected depending on the requirement of the MCU. The voltage applied to VLCD pin must be equal to or lower than VDD. Adjust VR to fit user's LCD panel display voltage (VLCD) Adjust R (external pull-high resistance) to fit user¢s time base clock. In order to obtain the correct frequency, two additional load capacities (C1, C2) are needed. The value of the capacity depends on how accurate the crystal is. We suggest that you can follow the table, which suggests the value of capacities. The table illustrates the suggestion value of capacities (C1,C2) Crystal Error Capacity Value ±10ppm 0~10p 10~20ppm 10~20p Command Summary Name READ WRITE READ-MODIFYWRITE SYS DIS SYS EN LCD OFF LCD ON TIMER DIS WDT DIS TIMER EN WDT EN ID Command Code D/C Function Def. 1 1 0 A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM 1 0 1 A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM 1 0 1 A5A4A3A2A1A0D0D1D2D3 D READ and WRITE to the RAM 1 0 0 0000-0000-X 100 100 100 100 100 100 100 0000-0001-X 0000-0010-X 0000-0011-X 0000-0100-X 0000-0101-X 0000-0110-X 0000-0111-X C Turn off both system oscillator and LCD bias generator Yes C Turn on system oscillator C Turn off LCD bias generator Yes C Turn on LCD bias generator C Disable time base output C Disable WDT time-out flag output C Enable time base output C Enable WDT time-out flag output Rev. 3.20 13 November 25, 2014 PATENTED HT1621/HT1621G Name TONE OFF TONE ON CLR TIMER CLR WDT XTAL 32K RC 256K EXT 256K BIAS 1/2 BIAS 1/3 TONE 4K TONE 2K IRQ DIS IRQ EN F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL ID 100 100 100 100 100 100 100 Command Code 0000-1000-X 0000-1001-X 0000-11XX-X 0000-111X-X 0001-01XX-X 0001-10XX-X 0001-11XX-X 1 0 0 0010-abX0-X 1 0 0 0010-abX1-X 100 100 100 100 010X-XXXX-X 011X-XXXX-X 100X-0XXX-X 100X-1XXX-X 1 0 0 101X-X000-X 1 0 0 101X-X001-X 1 0 0 101X-X010-X 1 0 0 101X-X011-X 1 0 0 101X-X100-X 1 0 0 101X-X101-X 1 0 0 101X-X110-X 1 0 0 101X-X111-X 1 0 0 1110-0000-X 1 0 0 1110-0011-X D/C Function Def. C Turn off tone outputs Yes C Turn on tone outputs C Clear the contents of time base generator C Clear the contents of WDT stage C System clock source, crystal oscillator C System clock source, on-chip RC oscillator Yes C System clock source, external clock source LCD 1/2 bias option C ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option LCD 1/3 bias option C ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option C Tone frequency, 4kHz C Tone frequency, 2kHz C Disable IRQ output Yes C Enable IRQ output C Time base/WDT clock output:1Hz The WDT time-out flag after: 4s C Time base/WDT clock output:2Hz The WDT time-out flag after: 2s C Time base/WDT clock output:4Hz The WDT time-out flag after: 1s C Time base/WDT clock output:8Hz The WDT time-out flag after: 1/2s C Time base/WDT clock output:16Hz The WDT time-out flag after: 1/4s C Time base/WDT clock output:32Hz The WDT time-out flag after: 1/8s C Time base/WDT clock output:64Hz The WDT time-out flag after: 1/16s C Time base/WDT clock output:128Hz The WDT time-out flag after: 1/32s Yes C Test mode, user don¢t use. C Normal mode Yes Note: X : Don,t care A5~A0 : RAM addresses D3~D0 : RAM data D/C : Data/command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 256kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 256kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1621 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1621. Rev. 3.20 14 November 25, 2014 PATENTED HT1621/HT1621G Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 3.20 15 November 25, 2014 PATENTED 44-pin LQFP (10mm´10mm) (FP2.0mm) Outline Dimensions C D 33 23 34 22 F AB E 44 12 1 11 HT1621/HT1621G H G I K a J Symbol A B C D E F G H I J K a Symbol A B C D E F G H I J K a Min. ¾ ¾ ¾ ¾ ¾ 0.012 0.053 ¾ 0.002 0.018 0.004 0° Min. ¾ ¾ ¾ ¾ ¾ 0.30 1.35 ¾ 0.05 0.45 0.09 0° Dimensions in inch Nom. 0.472 BSC 0.394 BSC 0.472 BSC 0.394 BSC 0.032 BSC 0.015 0.055 ¾ ¾ 0.024 ¾ ¾ Dimensions in mm Nom. 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.80 BSC 0.37 1.40 ¾ ¾ 0.60 ¾ ¾ Max. ¾ ¾ ¾ ¾ ¾ 0.018 0.057 0.063 0.006 0.030 0.008 7° Max. ¾ ¾ ¾ ¾ ¾ 0.45 1.45 1.60 0.15 0.75 0.20 7° Rev. 3.20 16 November 25, 2014 PATENTED 48-pin SSOP (300mil) Outline Dimensions HT1621/HT1621G 48 A 1 C C' D E Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Min. 0.395 0.291 0.008 0.620 0.095 ¾ 0.008 0.020 0.005 0° Min. 10.03 7.39 0.20 15.75 2.41 ¾ 0.20 0.51 0.13 0° 25 B 24 G F a Dimensions in inch Nom. ¾ 0.295 ¾ 0.625 0.102 0.025 BSC 0.012 ¾ ¾ ¾ Dimensions in mm Nom. ¾ 7.49 ¾ 15.88 2.59 0.64 BSC 0.30 ¾ ¾ ¾ H Max. 0.420 0.299 0.014 0.630 0.110 ¾ 0.016 0.040 0.010 8° Max. 10.67 7.59 0.34 16.00 2.79 ¾ 0.41 1.02 0.25 8° Rev. 3.20 17 November 25, 2014 PATENTED 48-pin LQFP (7mm´7mm) Outline Dimensions C D 36 25 HT1621/HT1621G H G I 37 24 AB 48 Symbol A B C D E F G H I J K a Symbol A B C D E F G H I J K a 1 Min. ¾ ¾ ¾ ¾ ¾ 0.007 0.053 ¾ 0.002 0.018 0.004 0° Min. ¾ ¾ ¾ ¾ ¾ 0.17 1.35 ¾ 0.05 0.45 0.09 0° F E 13 K 12 Dimensions in inch Nom. 0.354 BSC 0.276 BSC 0.354 BSC 0.276 BSC 0.020 BSC 0.009 0.055 ¾ ¾ 0.024 ¾ ¾ Dimensions in mm Nom. 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.22 1.40 ¾ ¾ 0.60 ¾ ¾ a J Max. ¾ ¾ ¾ ¾ ¾ 0.011 0.057 0.063 0.006 0.030 0.008 7° Max. ¾ ¾ ¾ ¾ ¾ 0.27 1.45 1.60 0.15 0.75 0.20 7° Rev. 3.20 18 November 25, 2014 PATENTED HT1621/HT1621G Copyright Ó 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 3.20 19 November 25, 2014

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