作者：A. Goel，A. Rylyakov，H. Ainspan，D. Friedman
摘要：A digital PLL, realized in 45nm SOI CMOS, features a dual LC-tank DCO with nested inductors, achieving an octave of tuning range and area of 0.111 mm² . Digital control of coupled LC-tanks creates new capabilities, enabling a 10% increase in tuning range and a 28 times reduction of DCO gain. The rms jitter, integrated from fc/1667 to fc/2, is 362 fs at 12 GHz and 274 fs at 6 GHz.
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