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Design Guidelines for RCD Snubber of Flyback Converters

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Design  Guidelines  for  RCD  Snubber  of  Flyback  Converters

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Application Note AN-4147
Design Guidelines for RCD Snubber of Flyback Converters
Abstract
This article presents some design guidelines for the RCD
snubber of flyback converters. When the MOSFET turns off,
a high-voltage spike occurs on the drain pin because of a res-
onance between the leakage inductor (L
lk
)
of the main trans-
former and the output capacitor (C
OSS
) of the MOSFET. The
excessive voltage on the drain pin may lead to an avalanche
breakdown and eventually damage the MOSFET. Therefore,
it is necessary to add an additional circuit to clamp the volt-
age.
is derived from a buck-boost converter by replacing filter
inductors with coupled inductors, such as gapped core trans-
formers. When the main switch turns on, the energy is stored
in the transformer as a flux form and is transferred to output
during the main switch off-time. Since the transformer needs
to store energy during the main switch on-time, the core
should be gapped. Since flyback converters need very few
components, it is a very popular topology for low- and
medium-power applications such as battery chargers, adapt-
ers, and DVD players.
Figure 1 shows a flyback converter operating in continuous
conduction mode (CCM) and discontinuous conduction
mode (DCM) with several parasitic components, such as pri-
mary and secondary leakage inductors, an output capacitor
of MOSFET, and a junction capacitor of a secondary diode.
Introduction
One of the most simple topologies is a flyback converter. It
i
d
i
D
i
d
i
D
diode reverse
recovery current
i
d
t
C
j
n:
1
V
in
L
lk2
L
m
i
m
i
D
+
Vo
V
ds
resonance between
L
lk1
and C
oss
V
in
+nVo
L
lk1
(b) CCM operation
i
d
+
V
ds
C
oss
i
d
i
D
i
d
i
D
i
d
t
(a) Configuration with parasitic components
resonance between
L
m
and C
oss
t
V
in
+nVo
V
in
V
ds
resonance between
L
lk1
and C
oss
(c) DCM operation
t
Figure 1. Flyback Converter; (a) Configuration with Parasitic Components, (b) CCM Operation, (c) DCM Operation
© 2006 Fairchild Semiconductor Corporation
Rev. 1.1.0
www.fairchildsemi.com
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AN-4147
APPLICATION NOTE
When the MOSFET turns off, the primary current (i
d
)
charges C
OSS
of the MOSFET in a short time. When the
voltage across C
OSS
(V
ds
) exceeds the input voltage plus
reflected output voltage (V
in
+nV
o
), the secondary diode
turns on, so that the voltage across the magnetizing inductor
(L
m
) is clamped to nV
o
. There is, therefore, a resonance
between L
lk1
and C
OSS
with high-frequency and high-volt-
age surge. This excessive voltage on the MOSFET may
cause failure. In the case of the CCM operation, the second-
ary diode remains turned on until the MOSFET is gated on.
When the MOSFET turns on, a reverse recovery current of
the secondary diode is added to the primary current, and
there is a large current surge on the primary current at the
turn-on instance. Meanwhile, since the secondary current
runs dry before the end of one switching period in the case of
the DCM operation, there is a resonance between L
m
and
C
OSS
of the MOSFET.
i
d
i
peak
i
sn
t
s
i
D
Snubber design
The excessive voltage due to resonance between L
lk1
and
C
OSS
should be suppressed to an acceptable level by an addi-
tional circuit to protect the main switch. The RCD snubber
circuit and key waveforms are shown in Figures 2 and 3. The
RCD snubber circuit absorbs the current in the leakage
inductor by turning on the snubber diode (D
sn
) when V
ds
exceeds V
in
+nV
o
. It is assumed that the snubber capacitance
is large enough that its voltage does not change during one
switching period.
When the MOSFET turns off and V
ds
is charged to V
in
+nV
o
,
the primary current flows to C
sn
through the snubber diode
(D
sn
). The secondary diode turns on at the same time. There-
fore, the voltage across L
lk1
is V
sn
-nV
o
. The slope of i
sn
is as
follows:
V
ds
V
sn
V
in
nV
o
Figure 3. Key Waveforms of
the
Flyback Converter with
RCD Snubber in DCM Operation
where i
sn
is the current that flows into the snubber circuit,
V
sn
is the voltage across the snubber capacitor C
sn
, n is the
turns ratio of the main transformer, and L
lk1
is the leakage
inductance of the main transformer. The time t
s
is obtained
by:
V
nV
o
di
sn
= − ⎜
sn
dt
L
lk1
i
D
V
in
V
sn
+
C
sn
D
sn
R
sn
L
lk
i
sn
i
d
+
V
ds
n:1
+
Vo
(1)
t
s
=
L
lk1
×
i
peak
V
sn
nV
o
(2)
where i
peak
is the peak current of the primary current.
The snubber capacitor voltage (V
sn
) should be determined at
the minimum input voltage and full-load condition. Once V
sn
is determined, the power dissipated in the snubber circuit at
the minimum input voltage and full-load condition is
obtained by:
P
sn
=
V
sn
i
peak
t
s
2
f
s
=
V
sn
1
L
lk
i
peak 2
f
s
2
V
sn
nV
o
(3)
where f
s
is the switching frequency of the flyback converter.
V
sn
should be 2~2.5 times of nV
o
. Very small V
sn
results in a
severe loss in the snubber circuit, as shown in the above
equation.
Figure 2. Flyback Converter with RCD Snubber
© 2006 Fairchild Semiconductor Corporation
Rev. 1.1.0
2
www.fairchildsemi.com
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AN-4147
APPLICATION NOTE
On the other hand, since the power consumed in the snubber
resistor (R
sn
) is V
sn2
/R
sn
, the resistance is obtained by:
Example
An adapter using FSDM311 has following specifications:
85V
ac
to 265V
ac
input voltage range, 10W output power, 5V
output voltage, and 67kHz switching frequency. When the
RCD snubber uses a 1nF snubber capacitor and 480kΩ snub-
ber resistor, Figure 4 shows several waveforms with 265V
ac
at the instance of the AC switch turn-on.
R
sn
=
V
sn 2
V
sn
1
L
lk1
i
peak 2
f
s
2
V
sn
nV
o
(4)
The snubber resistor with the proper rated power should be
chosen based on the power loss. The maximum ripple of the
snubber capacitor voltage is obtained as follows:
Δ
V
sn
=
V
sn
C
sn
R
sn
f
s
(5)
In general, 5~10% ripple is reasonable. Therefore, the snub-
ber capacitance is calculated using the above equation.
When the converter is designed to operate in CCM, the peak
drain current, together with the snubber capacitor voltage,
decreases as the input voltage increases. The snubber capaci-
tor voltage under maximum input voltage and full-load con-
dition is obtained as follows:
V
sn2
=
nV
o
+
( nV
o
)
2
+
2R
sn
L
lk1
f
s
( I
peak 2
)
2
2
(6)
Figure 4. Start-up Waveforms with 1nF Snubber Capacitor
and 480kΩ Snubber Resistor
where f
s
is the switching frequency of the flyback converter,
L
lk1
is the primary-side leakage inductance, n is the turns
ratio of the transformer, R
sn
is the snubber resistance, and
I
peak2
is the primary peak current at the maximum input volt-
age and full-load condition. When the converter operates in
CCM at the maximum input voltage and full-load condition,
the I
peak2
is obtained as follows:
I
peak 2
=
P
in
(V
DC max
+
nV
o
)
V
DC
max
×
nV
o
+
V
DC max
×
nV
o
2L
m
f
s
(V
DC
max
In Figures 4-7, Channel 1 through 4 stand for the drain volt-
age (V
ds
, 200V/div), the supply voltage (V
CC
, 5V/div), the
feedback voltage (V
fb
, 1V/div), and the drain current (I
d
,
0.2A/div), respectively. The maximum voltage stress on the
internal SenseFET is around 675V, as shown in Figure 4.
The voltage rating of FSDM311 is 650V, according to the
datasheet. There are two reasons for the excess of the voltage
ratings: the wrong transformer design and/or the wrong
snubber design. Figure 5 shows the reason.
+
nV
o
)
(7)
When the converter operates in DCM at the maximum input
voltage and full-load condition, the I
peak2
is obtained by:
574V
451V
I
peak 2
=
2P
in
f
s
L
m
(8)
where P
in
is the input power, L
m
is the magnetizing induc-
tance of the transformer, and V
DCmax
is the rectified maxi-
mum input voltage in DC value.
Verify that the maximum value of V
ds
is below 90% and
80% of the rated voltage of the MOSFET (BV
dss
), at the
transient period and steady-state period, respectively. The
voltage rating of the snubber diode should be higher than
BV
dss
. Usually an ultra-fast diode with 1A current rating is
used for the snubber circuit.
Figure 5. Steady-State Waveforms with 1nF Snubber
Capacitor
and 480kΩ Snubber Resistor
© 2006 Fairchild Semiconductor Corporation
Rev. 1.1.0
3
www.fairchildsemi.com
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AN-4147
APPLICATION NOTE
For the reliability, the maximum voltage stress at the steady
state should be equal to 80% of the rated voltage (650V
* 0.8
= 520V).
Figure 5 shows the voltage stress on the internal
SenseFET is above 570V with V
in
= 265V
ac
at steady state.
However, the fact that V
in
+nV
o
is around 450V (=
375V +
15 * 5V)
implies the turns ratio of the transformer is 15,
which is a reasonable value. Therefore, the snubber circuit
should be redesigned.
Let V
sn
be twice that of nV
o
, 150V, and L
lk1
and i
peak
is 150
µH and 400mA by measuring, respectively. Obtain the
snubber resistance as follows:
V
sn 2
V
sn
1
L
lk1
i
peak 2
f
s
2
V
sn
nV
o
150
2
1
150
×
150
μ
×
0.4
2
×
×
67k
2
150
75
(9)
R
sn
=
=
=
14k
Figure 7. Steady-State Waveforms with 10nF Snubber
Capacitor and 14kΩ Snubber Resistor
The power emission from R
sn
is calculated as follows:
The voltage stresses on the internal SenseFET are 593V and
524V at the startup and steady state, respectively. These are
around 91.2% and 80.6% of the rated voltage of FSDM311,
respectively.
(10)
V
sn 2
150
2
P
=
=
=
1.6W
R
sn
14k
Let the maximum ripple of the snubber capacitor voltage be
10% and the snubber capacitance is obtained as follows:
C
sn
=
V
sn
150
=
=
10nF
Δ
V
sn
R
sn
f
s
15
×
14k
×
67k
(11)
The results with 14k
Ω
(3W) and 10nF are shown in Figures
6 and 7.
Figure 6. Start-up Waveforms with 10nF Snubber
Capacitor and 14kΩ Snubber Resistor
© 2006 Fairchild Semiconductor Corporation
Rev. 1.1.0
4
www.fairchildsemi.com
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AN-4147
APPLICATION NOTE
by Gwan-Bon Koo/ Ph. D
FPS Application Group / Fairchild Semiconductor
Phone +82-32-680-1327
Fax
+82-32-680-1317
E-mail koogb@fairchildsemi.co.kr
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or
(b) support or sustain life, or
(c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in significant injury to the user.
© 2006 Fairchild Semiconductor Corporation
Rev. 1.1.0
5
2.A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its
safety or effectiveness.
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