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基于L6561的反激式变换器设计步骤

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基于L6561的反激式变换器设计步骤

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®
AN1059
APPLICATION NOTE
DESIGN EQUATIONS OF HIGH-POWER-FACTOR
FLYBACK CONVERTERS BASED ON THE L6561
by Claudio Adragna
Despite specific for Power Factor Correction circuits using boost topology, the L6561 can be suc-
cessfully used to control flyback converters. Among the various configurations that an L6561-based
flyback converter can assume, the high-PF one is particularly interesting because of both its peculiar-
ity and the advantages it is able to offer. AC-DC adapters for mobile or office equipment, off-line bat-
tery chargers and low-power SMPS are the most noticeable examples of application that this configu-
ration can fit.
This paper describes the equations governing such a kind of flyback converter with the aim of provid-
ing a number of relationships useful to the system designer.
INTRODUCTION
Figure 1a. TM Flyback Configuration
Three different configurations that an L6561-based
Vout
flyback converter can assume have been identified.
Vac
They are illustrated in fig. 1.
C
Configurations a) and b) are basically conventional
flyback converters. The former works in TM (Transi-
tion Mode, i.e. on the boundary between continuous
DISABLE
and discontinuous inductor current mode), therefore
at a frequency depending on both input voltage and
ZCD
VCC
output current. The latter works at a fixed frequency,
L6561
imposed by the synchronisation signal, and is there-
GD
fore completely equivalent to a flyback converter
OPTO
+
based on a standard PWM controller.
TL431
Configuration c), which most exploits the aptitude of
the L6561 for performing power factor correction,
works in TM too but quite differently: the input ca-
pacitance is so small that the input voltage is very close to a rectified sinusoid. Besides, the control loop
has a narrow bandwidth so as to be little sensitive to the twice mains frequency ripple appearing at the
output.
BULK
Figure 1b. Synchronised Flyback Configuration
Figure 1c. High-PF Flyback Configuration
Vout
Vac
C
BULK
SYNCH
Vac
C
IN
Vout
DISABLE
DISABLE
ZCD
VCC
ZCD MULT VCC
L6561
GD
OPTO
+
TL431
L6561
COMP
INV
GD
OPTO
+
TL431
(B
W
<100 Hz)
September 2003
1/20
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AN1059 APPLICATION NOTE
Actually, the high power factor (PF) exhibited by this topology can be considered just as an additional
benefit but not the main reason that makes this solution attractive. In fact, despite a PF greater than 0.9
can be easily achieved, it is a real challenge to comply with EMC norms regarding the THD of line cur-
rent, especially in universal mains applications.
There are, however, several applications in the low-power range (to which EMC norms do not apply) that
can benefit from the advantages offered by a high-PF flyback converter. These advantages can be sum-
marised as follows:
q
for a given power rating, the input capacitance can be 200 times less, thus the bulky and costly high
voltage electrolytic capacitor after the rectifier bridge will be replaced by a small-size, cheaper film ca-
pacitor.
q
efficiency is high at heavy load, more than 90% is achievable: TM operation ensures low turn-on
losses in the MOSFET and the high PF reduces dissipation in the rectifier bridge. This, in turn, mini-
mises requirements on heatsinks;
q
low parts count, which helps reduce encumbrance and assembly cost.
In addition, the unique features of the L6561 offer remarkable advantages in numerous applications:
q
efficiency is high even at very light load: the low current consumption of the L6561 minimises the
power dissipated by both the start-up resistor and the self-supply circuit. An L6561-based high-PF fly-
back converter can easily meet Blue Angel regulations;
q
additional functions available: the L6561 provides overvoltage protection as well as the possibility to
enable/disable the converter by means of its ZCD pin.
There are, on the other hand, some drawbacks, inherent in high-PF topologies, limiting the applications
that such a converter can fit (AC-DC adaptors, battery chargers, low-power SMPS, etc.) and which one
has to be aware of:
q
twice-mains-frequency ripple on the output: unavoidable if a high PF is desired. A large output ca-
pacitance will reduce its amount. Speeding up the control loop may lead to a compromise between a
reasonably low output ripple and a PF still reasonably high;
q
poor transient response: as to this point too, speeding up the control loop may lead to a compromise
between an acceptable transient response and a reasonably high PF;
Figure 2. Internal Block Diagram of the L6561.
COMP
2
INV
1
2.5V
-
+
MULT
3
4
40K
CS
MULTIPLIER
VOLTAGE
REGULATOR
OVER-VOLTAGE
DETECTION
+
-
5pF
V
CC
8
V
CC
INTERNAL
SUPPLY 7V
R1
+
UVLO
R
S
DRIVER
Q
7
20V
GD
R2
V
REF2
2.1V
1.6V
ZERO CURRENT
DETECTOR
STARTER
6
GND
2/20
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-
+
-
DISABLE
5
ZCD
D97IN547D
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AN1059 APPLICATION NOTE
large output capacitance (in the thousand
µF,
depending on the output power) is required: however,
cheap standard capacitors and not costly high-quality parts are needed. In fact, a low ESR and an
adequate AC current capability are automatically achieved. Besides, in conventional flyback convert-
ers there is usually plenty of output capacitance too, thus this is not so dramatic as it may seem at
first sight;
q
secondary post-regulation will be required where tight specifications on the output ripple and/or on
the transient behaviour are given. However, this is true also for a standard flyback;
q
the system is unable to cope with line missing cycles at heavy load unless an exceedingly high output
capacitance is used.
In the following, the operation of a high-PF flyback converter will be discussed in details and numerous
relationships, useful for its design, will be established.
q
Preliminary statements
In order to generate the equations governing the operation of a high-PF flyback converter working in TM,
refer also to the internal block diagram of the L6561(see fig. 2). For details concerning the operation of
the L6561, please refer to Ref. [1].
The following assumptions will be made:
1. the line voltage is perfectly sinusoidal and the rectifier bridge is ideal, thus the voltage downstream
the bridge, sensed by the input of the L6561’s multiplier (MULT, pin 3) is a rectified sinusoid:
V
in
(t) = V
PK
|sin (2
⋅ π ⋅
f
L
t)|
where V
PK
is equal to the RMS line voltage, V
RMS
, times the square root of 2, and f
L
is the line fre-
quency (usually 50 or 60 Hz).
2. the output of L6561’s Error Amplifier (V
COMP
) is constant for a given line half-cycle;
3. transformer’s efficiency is 1 and its windings are perfectly coupled.
4. ZCD circuit’s delay is negligible thus the converter works exactly on the boundary between continuous
and discontinuous current conduction mode (TM operation).
As a result of the first two assumptions, the peak primary current is enveloped by a rectified sinusoid:
I
pkp
(t) = I
PKp
|sin (2
⋅ π ⋅
f
L
t)| (1)
One consequence of assumption 3 is that the peak secondary current is proportional to the primary one,
depending on transformer’s primary-to-secondary turns ratio n:
I
pks
(t) = n
I
pkp
(t)
To simplify the notation, in the following the phase angle
θ
= 2
⋅ π ⋅
f
L
t of the sinusoidal quantities will
be indicated and all the quantities depending on the instantaneous line voltage will be considered as a
function of
θ,
instead of time.
Timing relationships
The ON-time of the power switch is expressed by:
T
ON
=
L
p
I
pkp
(θ)
L
p
I
PKp
(2),
=
V
PK
V
in
(θ)
where L
p
is the inductance of transformer’s primary winding. Eqn. (2) shows that T
ON
is constant over a
line half-cycle, exactly like in boost topology. The OFF-time is instead variable:
n
I
pkp
(θ)
L
s
I
pks
(θ)
n
2
L
p
I
PKp
|sin
(θ)|
T
OFF
=
=
=
n
⋅ (V
out
+V
f
)
(V
out
+
V
f
)
(V
out
+
V
f
)
L
p
(3),
3/20
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AN1059 APPLICATION NOTE
where L
s
is the inductance of the secondary winding, I
pks
(θ) the peak secondary current, V
out
the output
voltage of the converter (supposed to be a regulated DC value) and V
f
the forward drop on the output
catch diode.
Since the system works in TM, the sum of the ON and the OFF times equals the switching period:
T
=
T
ON
+
T
OFF
=
L
p
I
PKp
V
PK
V
PK
⋅ 
1
+
|sin(θ)|
V
R
(4)
where V
R
= n
(V
out
+ V
f
) is the so-called reflected voltage.
The switching frequency f
sw
= T
-1
, therefore, varies with the instantaneous line voltage:
f
sw
=
V
PK
L
p
I
PKp
1
1
+
V
PK
|sin(θ)|
V
R
and reaches its minimum value on the peak of the sinusoid (sin (θ)=1):
f
sw min
=
V
PK
L
p
I
PKp
1
V
PK
1
+
V
R
(5)
This value, calculated at the minimum line voltage, must be greater than the maximum one of the inter-
nal starter of the L6561 (≈14 kHz ), in order to ensure a correct TM operation. To accomplish with this
requirement, the primary inductance L
p
will be properly selected (not exceeding an upper limit). Actually,
to minimise the size of the transformer, the minimum frequency will usually be selected quite higher than
15 kHz, say 25-30 kHz or more, so the value of L
p
needs not have a tight tolerance.
The duty cycle, that is the ratio between the ON-time and the switching period, will vary with the instan-
taneous line voltage as well (because of the variation of T
OFF
), as it is possible to find by dividing eqn.(2)
by (4):
D
=
T
ON
=
T
1
V
PK
1
+
|sin(θ)|
V
R
(5’)
Equations (2) and (4) show that T
ON
and T, respectively, can be short at will if I
PKp
(i.e. the load) tends to
zero, especially at high input voltage. In the real-world operation, it must be considered that T
ON
cannot
go below a minimum amount and so will do the switching period as well. This minimum (typically, 0.4-
0.5µs) is imposed by the internal delay of the L6561 and by the turn-off delay of the MOSFET.
When this minimum is reached, the energy drawn each cycle exceeds the short-term demand from the
load, thus the control loop causes some cycles to be skipped so as to maintain the long-term energy bal-
ance. When the load is so low that many cycles need to be skipped, the amplitude of the drain voltage
ringing becomes so small that it can no longer trigger the ZCD Block of the L6561. In that case the inter-
nal starter of the IC will start a new switching cycles sequence.
Something similar applies to the duty cycle as well, which eqn. (5’) predicts to be unity when
θ
= 0, that
is at the zero-crossings of the mains voltage. In reality, a number of parasitic effects cause T
ON
and T
OFF
not to follow the ideal relationships (2) and (3). The effect of that on the overall operation is however
negligible because the energy processed near a zero-crossing is very little.
In the following, the ratio between the line peak voltage V
PK
and the reflected voltage V
R
will be indi-
cated with K
v
:
K
v
=
V
PK
V
R
Energetic relationships
Apart from the duty cycle, all the quantities expressed in the timing relationships depend on the through-
put power, which is represented in the above equations by I
PKp
, the peak primary current occurring at
4/20
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AN1059 APPLICATION NOTE
the peak of the sinusoid of the primary voltage.
The following relationships relate I
PKp
to the input power P
in
and allow both to explicate the timing rela-
tionships and to calculate all the currents circulating in the circuit.
Figure 3. High-PF Flyback current waveforms
Secondary current
peak envelope
Primary current
peak envelope
Average
primary current
SWITCH
ON
OFF
The primary current I
p
(t) is triangular-shaped and flows only during the switch ON-time, as illustrated by
the shaded triangles shown in fig. 3. As earlier stated by equation (1), during each half-cycle the height
of these triangles varies with the instantaneous line voltage:
I
pkp
(θ) = I
PKp
|sin (θ)|,
their width is constant but they are spaced out by a variable amount given by (3).
Looking at the primary on a "f
L
" time scale, the current I
in
(θ) downstream the bridge rectifier is the aver-
age value of each triangle over a switching cycle (the thick black curve of fig. 3):
I
in
(θ) =
|sin
(θ)|
1
1
I
pkp
(θ) ⋅
D
= ⋅
I
PKp
2
2
1
+
K
v
|sin
(θ)|
Figure 4b. Line Current (@ f
L
time scale)
1
Kv=0.5
Kv=1
Kv=2
Kv=4
before
the
bridge
Figure 4a. Primary Current (@ f
L
time scale)
1
0.75
Iin(θ)
after the
0.5
bridge
0.5
Kv=0.5
Kv=1
Kv=2
Kv=4
Iin(θ)
0
0.25
0.5
0
0
1.57
3.14
4.71
6.28
1
0
1.57
3.14
4.71
6.28
θ
θ
5/20
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