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反激电源的参考设计Design Considerations for Switched-Mode Power Supplies

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反激电源的参考设计Design  Considerations  for  Switched-Mode  Power  Supplies

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www.fairchildsemi.com
Application Note AN-4105
Design Considerations for Switched-Mode Power Supplies
Using a Fairchild Power Switch (FPS) in a Flyback
Converter
Introduction
Flyback, switched-mode power supplies (SMPS) are among
the most frequently used power circuits in household and
consumer electronics. The basic function of an SMPS is to
supply regulated power to the load on the secondary, or out-
put, side. An SMPS typically incorporates a power trans-
former, secondary-side rectifier diodes, a switching
semiconductor device with control IC, and peripheral cir-
cuitry. If the level of integration of the switching and control
circuitry is not high enough, then additional, separate circuits
are required to accommodate all functions. Such additional
components raise the overall SMPS cost and sometimes
reduce reliability.
Fairchild power switches are highly integrated ICs for power
supply applications. They combine a high-voltage power
MOSFET (SenseFET) and pulse width modulation (PWM)-
based control IC in one package. Moreover, they provide
enhanced IC functionality, thereby minimizing the number
of additional components needed in an SMPS. Fairchild
Power Switch (FPS) ICs are widely used in the power
circuits of a variety of equipment, such as color TVs,
printers, PCs, monitors, battery chargers, and AC adapters.
They typically incorporate a variety of enhanced protection
functions and they greatly reduce power consumption in
standby modes.
This application note considers the three major functional
blocks of an SMPS: Fairchild Power Switch (FPS), flyback
converter, and transformer. It discusses a variety of issues
important to their design and use in the overall SMPS.
Vcc
3
6.3V
2μA
Feedback
Soft-Start
& Sync.
4
1mA
Sync.
Vck
OSC.
2.5R
32V
UVLO
Voltage
Ref.
1 Drain
S
Q
R
5
R
Voffset
5V
Rsense
LEB
Sense
2
Source
GND
Reset
S
7.5V
Reset
Thermal
Protection
OVP
Control IC
R
Q
SenseFET
Figure1. Internal block diagram of a Fairchild Power Switch (FPS)
REV. 1.0.4 • 5/19/06
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AN-4105
APPLICATION NOTE
1. Block Diagram and Basic Operation
of a Fairchild Power Switch (FPS)
1.1 Block Diagram
Figure 1 presents a block diagram of a Fairchild Power
Switch (FPS). It can be divided into several large, functional
sections: under-voltage lockout circuitry (UVLO); reference
voltage; oscillator (OSC); pulse width modulation (PWM)
block; protection circuits; and gate driving circuits.
(Figure 2) charges to 15V. Because only a small current
(<1mA) is allowed to flow in through the resistor during
normal operation, this technique reduces the current dissi-
pation in the SMPS start-up resistor.
DC
LINK
Rg
Ccc
Vcc
3
Internal Bias
Power On
Reset
Latch
Comparator
15V/10V
UVLO
6V
Vz
Good Logic
+
1.2 Under-Voltage Lockout (UVLO)
A Fairchild Power Switch (FPS) under-voltage lockout
(UVLO) circuitry (Figure 2) guarantees stable operation of
the IC’s control circuit by stopping and starting it as a
function of the value of V
CC
(Figure 3). The turn off and turn
on voltage thresholds are fixed internally at 10V and 15V,
respectively; therefore, the UVLO circuitry turns off the
control circuit when V
CC
is lower than 10V and starts it
when V
CC
is higher than 15V. Once the control circuit starts
operating, V
CC
must drop below the 10V level for the
UVLO to stop the circuit again. Before switching starts, the
IC current is less than 300µA. IC operation starts when C
CC
Icc
[mA]
5V
Vref
Fairchild Power
Switch (FPS)
Figure 2. Detail of the under-voltage lockout (UVLO)
circuitry in a Fairchild Power Switch. The gate
operating circuit holds in a low state during UVLO,
thereby maintaining the SenseFET at turn-off
20
Power On
Reset Range
0.3
6V
10V
15V
Vz
Vc
[V]
Figure 3. Fairchild Power Switch (FPS) control circuit status vs. V
cc
1.3 Feedback Control Circuit
The Fairchild Power Switch (FPS) control IC uses a current
mode PWM and operates such that MOSFET current is
proportional to the feedback voltage V
fb
. This limits the
MOSFET current at every cycle. It also offers other
advantages, such as a well-regulated SMPS output voltage
with input voltage changes. This method of control also
works successfully in SMPSs used for monitors, which may
have a broad range of synchronizing frequencies to
accommodate. As shown in Figure 4, the Fairchild Power
Switch (FPS) oscillator turns on the MOSFET. The feedback
comparator operates to turn it off again when the MOSFET
current reaches a set value proportional to V
fb
. The
MOSFET turn-off operation is as follows: (1) the internal
(R+2.5R) voltage divider sets the voltage fed back to one
input of the feedback comparator at V
fb
/3.5; (2) a current
proportional to the drain current flows to the MOSFET sense
terminal, making V
sense
proportional to the drain current;
and, (3) when V
sense
becomes greater than V
fb
, the output of
the feedback comparator goes high, turning off the
MOSFET. Figure 4 also shows that the circuit is designed to
REV. 1.0.4 • 5/19/06
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use an opto isolator in the feedback loop. This is appropriate
for an off-line design where input to output isolation is
required. C
fb
improves the noise characteristics. If the
control IC incorporates an error amp as in Fairchild’s
KA3842B/3B/4B/5B current mode PWM controller ICs for
SMPSs, a resistor and capacitor are required to provide the
feedback to the error amp. This would provide the same
functions as those provided by the circuit of Figure 4; fine
control of the output voltage through Vfb. Similarly, other
appropriate devices are Fairchild’s LM431/TL431/KA431
series of three terminal shunt regulators. These have a very
sharp turn-on characteristic much like a Zener diode and are
widely used in SMPS secondary-side error amplifiers.
Precision
Current Source
2uA
Vfb
#4
5V
Cfb
Vfb*
Vss
Css
Reset
Rsense
R
#5
Vsense
Off
2.5R
S
On
R
1mA
OSC.
Vck
Fairchild Power Switch (FPS)
SPS
Idrain
#1
Q
Sense
Ioffset
#2
Isense
Figure 4. Fairchild Power Switch (FPS) feedback circuit appropriate for off-line SMPS use (current mode PWM)
1.4 Example Fairchild Power Switch (FPS)
Control Circuit
Figure 5 shows two approaches to control feedback with a
Fairchild Power Switch (FPS). The design in Figure 5a uses
the LM431 regulator and that of Figure 5b uses a Zener diode.
Even though the Zener diode approach is cost effective, the
output regulation is relatively poor.
In Figure 5a, C1, together with R1, produces a high-frequency
pole formed by the internal 3.5kΩ resistor and C
fb
in the
compensation network. R4 limits the maximum current of the
photodiode to 2.3mA [(12V - 2.5V - 2V) /3.3KΩ, where 2.5V
is the LM431's saturation voltage and 2 V is the photodiode's
voltage drop]. C
fb
should be determined by considering the
shutdown delay time (see Section 2.1). In Figure 5b, R3 sets a
fixed current to the Zener diode to stabilize its voltage.
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AN-4105
APPLICATION NOTE
2uA
Vo, 80V
R3
1k
R4
3.3k
10n
R2
1k
C2
KA431
12V
PC817
Vfb
#4
C1
33n
R1
33k
Cfb
33n
1mA
OSC.
2k
Vfb*
1k
R
2R
Vck
Fairchild Power Switch(FPS)
SPS
S
Q
R
Ioffset
Rsense
Sense
LM431
(a)
Control Circuit using KA431(LM431) Control IC
Control circuit that used KA431(LM431)
Fairchild Power Switch(FPS)
2uA
Vo, 80V
R1
33k
R3
1k
2.2k
12V
PC817
Vfb
Cfb
33n
#4
1mA
OSC.
2k
Vfb*
1k
R
2R
Vck
SPS
S
Q
R
Ioffset
Rsense
Sense
C1
0.1u
R2
Vz
(b)
Control Circuit using a
used the zener diode
Control circuit that
Zener Diode Control IC
Figure 5. Fairchild Power Switch (FPS) feedback control circuit
1.5 Soft-Start Operation
Normally, the SMPS output voltage increases from start up
with a fixed time constant. This is due to the capacitive
component of the load. At start up, therefore, the feedback
signal applied to the PWM comparator's inverting input
reaches its maximum value (1V) because the feedback loop
is effectively open. Also at this time, the drain current is at
its peak value (I
peak
) and maximum allowable power is being
delivered to the secondary load. When the SMPS pushes
maximum power to the secondary side for this initial fixed
time, the entire circuit is seriously stressed. Use of a soft-
start function avoids such stresses. Figure 6 shows how to
implement a soft-start for a Fairchild Power Switch (FPS).
At turn on, the soft-start capacitor C
S
on pin 5 of the
Fairchild Power Switch (FPS) starts to charge through the
1mA current source. When the voltage across C
S
reaches 3V,
diode D
S
turns off. No more current flows to it from the
1mA current source. Cs then continues to charge to 5V
through the 50kΩ resistor.
REV. 1.0.4 • 5/19/06
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1 0V
2
1
Fa irc hild Pow
(FPS)
Fairchild Power Switch
e r
Sw itc h (SPS)
PW M
Co mp a ra to r
50k
5V
Ds
#4
Cs
A
#5
KA5XX Series
E xte rn a l
S yn c In put
KA2SXX
Rs
K A 5S X X
KA3SXX
K A 5Q X X
B
S eries
absence of an external sync signal, the voltage across C
t
oscil-
lates at the basic frequency of 20kHz. In the presence of a
sync signal, however, the Set signal goes high because V
Ct
charges to the high threshold following the external sync
signal and, ultimately, the Set signal, which determines the
switching frequency, synchronizes to the external sync signal.
It is necessary to limit the Set signal's high duration to 5% or
less of the full cycle. As the Set signal drops low, the gate
turns on. If the device is not synchronized to the horizontal
scan of the monitor, noise appears on the screen. When the Set
signal goes high, the sync is synchronized with the horizontal
scan flyback. Because the high duration is 5% (maximum) of
the full cycle, the start of the horizontal scan (as the Set signal
goes low) turns-on the switch. The switch turn-on noise,
therefore, is hidden in the horizontal blanking period at the far
left of the monitor display.
Figure 6. Soft-start circuit
When the voltage across C
S
exceeds 3V, the voltage at the
comparator’s inverting terminal no longer follows the voltage
across C
S
. Instead, it follows the output voltage feedback
signal. In shutdown or protection circuit operation, capacitor
C
S
is discharged, to enable it to charge from 0V at restart.
Fairchild Power Switch(FPS)
SPS
1㎃
5V
1.6 Synchronization
In an SMPS intended for use with monitors, synchronization
is handled differently from a general purpose SMPS. For
monitor use, it is necessary to prevent noise from appearing on
the monitor display. To accomplish this, it is necessary to
synchronize the SMPS switching frequency with the
monitor’s horizontal sync frequency. The monitor’s horizontal
scan flyback signal is commonly used as the external sync
signal for the SMPS. By synchronizing the switching with the
horizontal scan’s flyback, the switching noise is positioned at
the far left of the monitor display where it cannot be seen.
Figure 7 shows how to implement the external circuit for
synchronization. The external sync signal, applied across
resistor R
s
, cannot drop below 0.6V because of diode D
sync
.
After the conclusion of the initial soft start, the voltage across
C
s
remains at 5V until the external sync signal is applied, at
which point, it looks like V
Rs
of Figure 8. The sync
comparator compares V
Cs
against a 6.3V level and produces
the comparator output waveform, V
comp
of Figure 8.
A Fairchild Power Switch (FPS) has an internal timing
capacitor, C
t
. Figure 8 shows that when the voltage on C
t
, V
Ct
,
reaches an upper threshold, it begins to discharge; then, when
it reaches a lower threshold, it again starts to charge. This
operation is controlled by the internal oscillator. The oscillator
output signal, V
Ck
in Figure 8, which goes low when C
t
recharges and high when it discharges, is applied to the
Fairchild Power Switch (FPS) S/R Latch Set terminal. In the
V
CS
External
Sync
Input
Cs
V
RS
Rs
Dsync
V
COMP
6.3V
#5
PWM
comparator
OSC.
Sync
comparator
Figure 7. Synchronization circuit
V
RS
2V
0V
V
CS
5V
0V
V
C OMP
0V
V
CT
0V
V ck
0V
V
ThH
V
ThL
Figure 8. Synchronization circuit operation
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