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    Transactions on Electromagnetic Compatibility Simplified Methodology for Optimal Decoupling Capacitors Selection and Placement Journal: Transactions on Electromagnetic Compatibility Manuscript ID: TEMC-303-2013 Manuscript Type: Paper Date Submitted by the Author: 21-Aug-2013 Complete List of Authors: han, guobing; Amphenol Corporation, Yang, Long; Intel Corporation, Key Words: Power distribution, Power capacitors, Decoupling of systems For Peer Review Page 1 of 4 Transactions on Electromagnetic Compatibility Simplified Methodology for Optimal Decoupling Capacitors Selection and Placement Guobing Han, Long Yang robin.han@amphenol-tcs.com,long.yang@intel.com For Peer Review Abstract—Simplified methodology for optimization of onboard decoupling capacitors is introduced, which can be performed easily based on Math tools or general EDA tools. This methodology is based on simple formula of capacitor models, and it can both simplify the process and achieve good results when finding the optimal solution. To perform this methodology, first prepare the network parameters of package or PCB, then set up the optimization topology and perform the optimization by some kind of optimizer, finally, we will get the optimum selection and placement scheme of capacitors with the minimal impedance profile. Detailed applications of practical cases demonstrate the proposed methodology with reasonable goals achieved. I. INTRODUCTION As operating frequencies increase over multi-GHz, signal integrity analysis in high-speed digital systems is becoming more and more important. Recently, among various reasons which cause signal integrity problems, power integrity (PI) issues have been considered to be the principle concerns. The power integrity issues, such as simultaneous switching noise (SSN), can cause the voltage fluctuations at a position between Power/Ground plane pair, so as to cause voltage reference problem, and as well as extra noise through power to signal coupling, even cause system fail and heavy electromagnetic interference (EMI) issues. The root-cause of PI issues is not in time-domain as appearance, but in frequency domain. It’s the big inductance of power distribution network (PDN) or bad power impedance design that causes the PI issues. Thus, decoupling capacitors are often required to minimize the SSN and maintain small power distribution network impedance. Researchers have done many valuable works on the selecting of decoupling capacitors [1-3]. But, some researches were limited to the placement of a decoupling capacitor near the active component. The others have the limitation of large cost consuming. Om P. Mandhana and Jin have presented an effective methodology for on-package decoupling capacitors selection with the considerations of minimizing the PDN noise in [4], but it’s not automatic. Based on that, we presented another methodology with considerations of automatically selecting the optimal de-caps types, locations and numbers. However, this methodology is a little complicated and hard to cover too many types of capacitors [5]. To solve these issues, in this paper we further develop an efficient and simplified methodology to optimize the selection and placement of the decoupling capacitors in the PDN design. This methodology can be performed easily with the help of optimizers of math tools or general EDA tools. Based on simple formula of capacitor models, which can cover as many as enough types of de-caps and it can both simplify the process and achieve good results when finding the optimal solution. Detailed applications of practical cases demonstrate the proposed methodology, with results showing that reasonable goals can be achieved by suggested optimization methodology. II. CONVENTIONAL PDN MODELLING AND DE-CAPS SELECTION METHODOLOGY Fig.1 Model of the PDN structure as a multi-ports network Suppose a PDN structure has 2m points which are connected with external circuit components such as the decoupling capacitors for suppressing SSN, then the structure can be taken on as an m-port network with different loads at each port, as shown in Fig. 1. If a current source j(t) is added at one port and other ports are respectively connected with m-1 impedance loads zi ( i = 2,3,…, m-1), the circuit equation of such multi-port network shown in Fig. 1 is constructed as follows[6]:  1 0  0 Z11 Z12  Z1n  V1  0   0 1  0 Z 21 Z 22  Z 2 n   V2   0                0 0 1  z1 0 0 1 z2   1 0 0 Z n1 1 0 Zn2 0 1    Z nn 0     Vn   I1      0 1   J 0  I2  0                   001 zn000 1  In   0 A( f ) X( f ) E Y( f ) (1) In the above equation, Zij substitutes the self or mutual impedance. The eigen-mode expansion method (EEM), momentum method (MoM) and finite element method (FEM) Transactions on Electromagnetic Compatibility Page 2 of 4 etc, are conventional methods to compute the input or transfer impedance of PDN plane pair structures. Thus, the conventional methodology to selecting de-caps is that: first, place the decoupling capacitors at multiple locations which may be with large impedance; second, calculate the impedance responses over a frequency range of interest; then, if the impedances at some frequency points are over tolerance, change the placement and value of decoupling capacitors and calculate the impedance response again. It is obvious that the process includes considerable iterations and consumes a great deal of computation time and resources. (a) III. OPTIMAL METHODOLOGY 1 AND 2 A. Optimal Methodology 1 For Peer Review In [5], to improve the conventional methodology, we presented a methodology with considerations of automatically selecting the optimal de-caps types, locations and numbers. First, extract the broadband network parameters of PCB without de-cap loaded by conventional EEM, MoM or FEM methods or commercial tools as mentioned in [4], the electromagnetic computation is required only once here. Then, (b) set up the optimization topology in math tools, Agilent ADS or Ansys Designer[7-8] with the goals of minimal impedances , and variables of numbers of kinds of capacitors at different locations; if the number is zero it means that there is none of such kind of capacitor required at that location, so it decides the distribution or placement indirectly. Finally, after several steps of calculations by some kinds of optimizers, the optimum selection and placement scheme of decoupling capacitors with the minimal impedance profile can be found. For reference, the scheme and setting in ADS environment is shown in Fig.2 and Fig.3, and it can also be easily achieved in other tools such as Designer, Matlab or just by programming. (c) Fig. 3. Detailed settings of methodology 1 in ADS (a) Connection of S parameter model, loads and ports (b) goals (c) DECAPS model The above process is very efficient since the EM computation is required only once. In addition, the proposed methodology is very flexible, which can be performed by many types of parameter extracting tools and optimizer tools or just by mathematical programming directly. However, from Fig.2 and Fig.3, we can found that this methodology is a little complicated and hard to cover too many types of capacitors; besides, we have to take a very small number, such as 1e-15 to approximate the de-cap number of 0. Fig. 2. Whole scheme of optimal methodology 1 B. Optimal Methodology 2 To simplify the above methodology and cover as many as enough types of decoupling capacitors, here comes the optimal methodology 2. The key element of this novel Page 3 of 4 Transactions on Electromagnetic Compatibility improved methodology is that an empirical formula of capacitor values is introduced, that is, C=1.5m10n nF, m=0~5, n=-4~4 (2) The results before optimization are shown in Fig.7~Fig.8. They illustrate the impedance profiles and SSN with none and all initial configured DECAPS, respectively. For example, when n=0, the formula covers capacitor values: 1nF, 1.5nF, 2.2nF, 3.3nF, 5.0nF, 7.5nF. The optimal methodology 2 is generally similar to methodology 1, but the setting is much simpler than the later, as shown in Fig.4 and Fig.5; and it’s more effective since it covers as many as enough types of capacitors and has less variables. (a) For Peer Review Fig. 4. Whole scheme of optimal methodology 2 Fig. 5. DECAPS model setting in ADS IV. EXAMPLE AND RESULTS The example board is shown in Fig.6. Its broadband network parameters [S] are extracted by Sigrity PowerSI or Ansys SIwave[9-10], and they will be involved in ADS or Ansys Designer as a block connected to DECAPS and interest ports, as shown in Fig.4. In ADS or Designer, the network parameters [S] will be converted to [S’] or [Z’] with DECAPS loaded. The self and transfer input impedance of PDN at the die location on the top layer of the board will be evaluated. The whole optimization schemes will be controlled and performed by ADS or Designer recursively till the goals are achieved or the recursive times are achieved. (b) Fig. 7. results with none DECAPS (a)impedance (b)SSN (a) Fig. 6. Layout of the example board (b) Fig. 8. results with all initial configured DECAPS (a)impedance (b)SSN For Peer Review Transactions on Electromagnetic Compatibility Page 4 of 4 It can be found from the above results that the impedance profiles before optimization, both the initial ones and the ones with all suggested DECAPS loaded, are very high. The uncontrolled inductive effect and resonance cause the high impedance and so as to induce large SSN. The results of the impedance profiles and SSN after optimization are shown in Fig.9. (Cdie) loaded. The peak to peak SSN voltage is nearly reduced by 100mv without Cdie and 180mv with Cdie. Thus, the optimal selection and placement of DECAPS was found. Besides, the optimization process is very fast and the total number of finally applied DECAPS is about half of all the initial suggested ones. Thus, this methodology is simple, effective, efficient and economic. V. CONCLUSION A simple and efficient methodology to optimize the selection and placement of the decoupling capacitors in the PDN is presented in this paper. This methodology can be performed easily by common EDA or mathematic tools. Based on the combination of broadband multiport model and efficient optimization algorithms, it saves both the computation time and cost greatly. In addition, the proposed methodology can also be performed with alternate parameter extracting tools and optimizer tools or just with mathematical tools directly. (a) REFERENCES [1] R.Downing, et al., “Decoupling capacitor effects on switching noise”, IEEE Trans. On Components, Hybrids, and Manufacturing Technology, vol. no.5,pp.484-489,August 1993. [2] J.Prymak, “Advance decoupling using ceramic MLC Capacitors,” 40th Electronic Components and Conference, vol.2, pp.1014-1023,1990. [3] J.Choi, et al., “A methodology for the placement and optimization of decoupling capacitors in Gigahertz Package and Broad,” 13th international conference on VLSI,pp.156-161,Jan.2000. [4] Om P. Mandhana, Jin Zhao, “Methodology for On-Package Decoupling Capacitor Selection with Considerations of Coupled Core and TO Power Delivery Network and Simultaneous Switching Noise Effects”, 2005 IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging. [5] Guobing Han, “Novel Methodology for Optimal Decoupling Capacitor Selection and Placement”, 2009 IEEE International Symposium on Electromagnetic Compatibility [6] G. J. Burke, E. K. Miller, S. Chakrabarti, and K. Demarest, “Using model-based parameter estimation to increase the efficiency of (b) computing electromagnetic transfer functions,” IEEE Trans. Magn, vol.25,pp.2807-2809,July 1989 [7] Agilent ADS manual [8] Ansys Designer manual [9] Sigrity PowerSI manual [10] Ansys SIwave manual (c) Fig. 9. Results with optimized DECAPS (a)impedance (b)SSN (c) SSN It can also be found from Fig.9 that the impedance profiles after optimization are much lower than those before optimization. The goals are generally achieved before 0.6GHz as setting, and totally achieved with extra on-die capacitance

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