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    nly O gy nolo ech Intellect T roup G onfidential for C datasheet OBJECTIVE SPECIFICATION medical bridge processor OV420 nly O gy nolo ech Intellect T roup G onfidential for C i 00Copyright © 2009 OmniVision Technologies, Inc. All rights reserved. This document is provided “as is” with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. nly OmniVision Technologies, Inc. and all its affiliates disclaim all liability, including liability for infringement of any proprietary O y rights, relating to the use of information in this document. No license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. g lo The information contained in this document is considered proprietary to OmniVision Technologies, Inc. and all its o affiliates. This information may be distributed to individuals or organizations authorized by OmniVision Technologies, Inc. chn to receive said information. Individuals and/or organizations are not allowed to re-distribute said information. e T Trademark Information t OmniVision and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc.wCSP is a trademark of OmniVision c Technologies, Inc. lle All other trademarks used herein are the property of their respective owners. te In roup G r l fo tia medical bridge processor n datasheet (wCSP) e OBJECTIVE SPECIFICATION fid version 0.2 n july 2009 o C To learn more about OmniVision Technologies, visit www.ovt.com. OmniVision Technologies is publicly traded on NASDAQ under the symbol OVTI. 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor nly O gy nolo ech Intellect T roup G onfidential for C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 iii 00applications ordering information medical endoscopes industrial endoscopes image processor for OV6930 OV00420-A36G (lead-free) 36-pin wCSP™ nly O 00features OV420 bridge chip converts analog video to digital low cost, single-chip solution for the OV6930 medical chip SCCB interface support high bandwidth ADC, supporting up to 16MHz external system clock or independent crystal operation y g lo o n auto gain/exposure control ech T black level calibration (BLC) digital signal processor (DSP) ct RAW output with 10-bit parallel digital video port lle (DVP) te In roup 00key specifications G r power supply: core: 1.8V ± 10% I/O: 3.3V ± 10% analog: 3.3V ± 10% ntial fo e fid n o C temperature range: -30°C to 70°C power requirements: TBD package dimensions: 3.17 mm x 3.17 mm 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor nly O gy nolo ech Intellect T roup G onfidential for C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 v 00table of contents 1 signal descriptions 2 system level description 2.1 overview 1-1 2-1 2-1 nly O 2.2 functional block description 2-1gy 2.2.1 camera interface 2.2.2 black level calibration olo22--11 2.2.3 auto exposure control (AEC) n 2-1 2.2.4 digital signal processor (DSP) 2.2.5 SCCB serial interface 2.2.6 two-wire interface 2.2.7 synchronized color bar for data path performance 2.2.8 phase-locked loop (PLL) ech ct T 2-1 2-1 2-1 2-2 2-2 3 register tables lle 3-1 4 operating specifications 4.1 absolute maximum ratings 4.2 functional temperature Inte 4-1 4-1 4-1 4.3 DC characteristics 5 mechanical specifications 5.1 physical specifications roup 4-2 5-1 5-1 5.2 IR reflow specifications G 5-2 r l fo tia n e fid n o C 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor nly O gy nolo ech Intellect T roup G onfidential for C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 vii 00list of figures figure 1-1 figure 2-1 figure 2-2 figure 2-3 figure 5-1 figure 5-2 pin diagram OV420 medical system block diagram OV420 functional block diagram OV420 reference schematic package specifications IR reflow ramp rate requirements 1-2 2-1 2-2 nly O 2-3gy olo55--21 n ch e T ct lle te In roup G onfidential for C 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor nly O gy nolo ech Intellect T roup G onfidential for C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 ix 00list of tables table 1-1 signal descriptions table 3-1 system control registers table 3-2 GPIO control registers table 3-3 SCCB master registers table 3-4 SCCB slave registers table 3-5 SDRAM registers table 3-6 BLC control registers table 3-7 AEC control registers table 3-8 AEC_pk control registers table 3-9 DVP control registers table 3-10 ISP_top registers table 3-11 LENC control registers table 3-12 AWB control registers table 3-13 DPC control registers table 3-14 windowing control registers 1-1 3-1 3-3 nly O 3-7gy olo33--87 n 3-11 ch 3-12 e 3-15 T 3-16 llect 3-17 3-18 3-20 te 3-22 In 3-22 table 3-15 AVERAGE registers table 4-1 absolute maximum ratings table 4-2 functional temperature roup table 4-3 DC characteristics G table 5-1 table 5-2 package dimensions r l fo reflow conditions tia fiden on 3-23 4-1 4-1 4-2 5-1 5-2 C 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor nly O gy nolo ech Intellect T roup G onfidential for C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 1-1 1 signal descriptions table 1-1 lists the signal descriptions and their corresponding pin numbers for the OV420 bridge chip. The package information is shown in section 5. nly O table 1-1 pin number A1 A2 A3 A4 A5 A6 B1 B2 B3 signal descriptions (sheet 1 of 2) y pin signal name type description g lo voltage DVDD SIOCH SIODS power I/O I/O power for digital circuit host SCCB clock sensor SCCB data ch–1–n.8 o RESETB I/O XVCLK I/O e reset, active low (with internal pull-up T resistor) ct system clock input – – DOVDD power lle power for I/O circuit 3.3 VSYNC DGND SIOCS I/O ground I/O DVP VSYNC output te ground for digital circuit In sensor SCCB clock – 0 – B4 CBAR I/O up color bar test mode – B5 DOGND B6 V330 ground power roground for I/O circuit sensor power output 0 3.3 C1 NC – G r no connect – C2 C3 PCLK SIODH I/O l foI/O DVP PCLK output host SCCB data – – C4 ACLK tia I/O sensor clock output – C5 n TM I/O e test mode, active high (with internal pull-down resistor) – C6 D1 nfNDiC3d – no connect I/O DVP data output port 3 – – o D2 D0 I/O DVP data output port 0 – C D3 D7 I/O DVP data output port 7 – D4 D9 I/O DVP data output port 9 – D5 PWDN I/O power down, active high (with internal pull-down resistor) – 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 1-1 signal descriptions (sheet 2 of 2) pin pin number signal name type D6 NC – description no connect ly voltage n– E1 DOVDD power power for I/O circuit O 3.3 E2 D2 E3 D6 E4 D8 E5 AVDD E6 AIN F1 D4 F2 D1 F3 D5 F4 DOGND F5 HREF F6 AGND I/O DVP data output port 2 y – I/O I/O g DVP data output port 6 olo DVP data output port 8 – – power n power for analog circuit 3.3 I/O ch sensor analog input – I/O e DVP data output port 4 – I/O T DVP data output port 1 – I/O ctDVP data output port 5 – ground lle I/O Inte ground I/O ground DVP HREF output ground for analog circuit 0 – 0 figure 1-1 up pin diagram ro G onfidential for C A1 A2 A3 A4 A5 A6 DVDD SIOCH SIODS RESETB XVCLK DOVDD B1 B2 B3 B4 B5 B6 VSYNC DGND SIOCS CBAR DOGND V33O C1 C2 C3 C4 C5 C6 NC PCLK SIODH ACLK TM NC D1 D2 D3 D4 D5 D6 D3 D0 D7 D9 PWDN NC E1 E2 E3 E4 E5 E6 DOVDD D2 D6 D8 AVDD AIN F1 F2 F3 F4 F5 F6 D4 D1 D5 DOGND HREF AGND 420_CSP_DS_1_1 proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 2-1 2 system level description 2.1 overview nly The OV420 is a single chip solution for the OV6930 medical application. When the OV420 is combined with the OV6930, the OV6930 provides an integrated analog to digital data conversion using a built-in A/D converter (ADC), black level O y calibration (BLC) and a final digital video parallel output (DVP). As shown in figure 2-1, the OV420 provides a standard SCCB interface to communicate with the system and manipulate the above mentioned functions. g lo During operation, the OV420 synchronizes the analog output from the OV6930 through an ADC by a predefined o communication protocol. The generated digital signals will then be processed by a digital signal processor (DSP). Then n finally, standard DVP outputs are sent out. ech figure 2-1 OV420 medical system block diagram OV6930 image sensor OV420 bridge processor T customer ct medical lle system Inte420_DS_2_1 2.2 functional block description 2.2.1 camera interface roup G The analog input interface supports a bandwidth up to 8 MHz, which is the clock used by the OV6930 output. 2.2.2 black level calibration r o The OV6930 uses data from black pixels to perform calibration. l f 2.2.3 auto exposure control (AEC) tia When the AEC/AGC of the OV6930 is disabled, the OV420 can provide the OV6930 with the right exposure/gain. en 2.2.4 digital signal processor (DSP) fid The DSP of the OV420 includes LENC correction, auto white balance, defect pixel cancellation, windowing and test pattern generation. n o 2.2.5 SCCB serial interface C The SCCB interface controls the chip operation. The OV420 is considered to be the SCCB ’slave’ when the customer writes or reads the registers of the OV420. But when the customer wants to write and read the registers of the OV6930, the OV420 can be considered the SCCB master. 2.2.6 two-wire interface The customer can write or read the registers of the OV6930 through the two-wire interface. 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor 2.2.7 synchronized color bar for data path performance When the "test pin" is activated, it will create a PLL bypass mode and enable a direct output path from the color bar block to the DVP output pins. 2.2.8 phase-locked loop (PLL) nly O The internal PLL is used for synchronous clocking and may be enabled or disabled as needed. The functional block diagram for the OV420 is shown in figure 2-2. y g figure 2-2 OV420 functional block diagram lo o OV420 n ADC memory controller BLC ecDShP DVP T OV6930 image sensor SCCB master llect AEC/AGC te system In control SCCB slave SCCB serial interface customer medical system p u PLL ro G onfidential for C 420_DS_2_2 proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 2-3 figure 2-3 OV420 reference schematic J2 HEADER 3 DOVDD 1 V330 2 S_DOVDD 3 SIOCS R1 SIODS R2 SCL R3 SDA R4 10k_0603 10k_0603 10k_0603 10k_0603 *To USB board D3 D5 D7 D9 HREF VSYNC YPCLK PWR D1 1 Y3 3 Y5 5 Y7 7 Y9 9 RESET 11 NC 13 HREF 15 VSYNC 17 PCLK 19 PWR 21 PWR 23 Y1 25 NC 27 NC 29 NC 31 GND J1CON32A Y2 2 D2 Y4 4 D4 Y6 6 D6 Y8 8 D8 PWDN 10 PWDN SDA 12 SDA SCL 14 SCL GND 16 GND 18 XCLK 20 XCLK GND 22 Y0 24 D0 NC 26 NC 28 NC 30 GND 32 XVCLK DGND GND AIN E6 AIN SIOCH A2 SCL SIODH C3 SDA SIOCS B3 SIOCS SIODS A3 SIODS AGND F6 DGND B2 DOGND F4 DOGND B5 AGND AVDD DVDD DOVDD V330 A1 DVDD E5 AVDD E1 DOVDD A6 DOVDD B6 V330 C1 NC1 C6 NC2 D6 NC3 75-0603 C11 0.1μF-0603 C12 0.1-0603 C13 0.1-0603 C14 0.1μF-0603 R6 J5 CON8A J4 HEADER1 AIN 1 AVDD 3 S_DOVDD 5 2 GND l 4 ACLK 6 SIOCS AGND 7 8 SIODS ntia *Put on top_left side of PCB e fid n o C for TM CBAR RESETB PWDN XVCLK ACLK VSYNC HREF YPCLK C5 TM B4 CBAR A4 RESETB D5 PWDN A5 XVCLK C4 ACLK B1 VSYNC F5 HREF C2 PCLK U4 OV420 p wCSP u ro G ct lle D9 D4 D9 e D8 E4 D8 tD7 D3 D7 nD6 E3 D6 I D5 F3 D5 D4 F1 D4 D3 D1 D3 D2 E2 D2 D1 F2 D1 D0 D2 D0 R5 220-0603 D1 C7 0.1μF-0603 C8 10μF/6V-EIA-A C9 0.1μF-0603 C4 0.1μF-0603 C5 10μF/6V-EIA-A C6 0.1μF-0603 C1 0.1μF-0603 C2 10μF/6V-EIA-A C3 0.1μF-0603 U1 5V XC62FP3302-SOT89 2 VIN OUT 3 1 GND DOVDD y g 5V U2 XC6203E182P lo oDVDD 2 VIN OUT 3 1.8v chn 1 GND e T U3 5V XC62FP3302-SOT89 2 VIN OUT 3 1 GND AVDD C10 22U/16V + 5V L1 10UH PWR DC+5V J3 HEADER 4 TM 1 CBAR 2 RESETB 3 PWDN 4 420_wCSP_DS_2_2 nly O 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor nly O gy nolo ech Intellect T roup G onfidential for C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-1 3 register tables table 3-1 system control registers (sheet 1 of 2) nly default O address register name value 0x3000 SC_CTRL00 0x04 R/W RW description y Bit[7:4]: Reserved g Bit[3]: Bit[2]: Bit[1]: Disable software reset of SRB Global SRAM enable System sleep mode olo 0: Normal work mode n Bit[0]: 1: Software sleep power down mode h System software reset c 0: Normal work mode e 1: Software reset mode Bit[7]: Bit[6]: T Invert input clock for PLL of OV6930 t 0: Normal input clock of PLL c 1: Invert the phase of the PLL clock Invert ADC clock lle 0: Normal ADC clock Inte Bit[5]: 1: Invert the phase of the ADC clock ADC clock enable 0: Disable ADC clock 1: Enable ADC clock 0x3001 SC_CTRL01 0x31 RW p Bit[4]: u ro Bit[3]: Bit[2:0]: Enable input clock for the PLL of OV6930 0: Disable 1: Enable Reserved Divide system clock for the input clock of the G r l fo tia n e 0x3002 fid SC_CTRL02 0x00 RW n o C PLL in the OV6930 000: Disable clock 001: Divide by 1 010: Divide by 2 011: Divide by 4 Others: Divide by 8 Reset for Individual Block (0: enable block; 1: reset block) Bit[7]: Reset CBAR Bit[6]: Reset SCCB master Bit[5]: Reset DVP Bit[4]: Reset ISP Bit[3]: Reset average block Bit[2]: Reset AEC Bit[1]: Reset BLC Bit[0]: Reset D_SRAM 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-1 system control registers (sheet 2 of 2) address register name default value R/W description ly n Clock Enable Control (0: disable clock; 1: enable clock) 0x3003 SC_CTRL03 0x3004 SC_CTRL04 0x3005~ 0x300C RSVD O Bit[7]: Enable CBAR clock Bit[6]: Enable SCCB master clock y Bit[5]: Enable DVP clock 0x7F RW Bit[4]: Bit[3]: Bit[2]: Enable ISP clock g Enable average block clock lo Enable AEC clock Bit[1]: Bit[0]: Enable BLC clock no Enable D_SRAM clock Clock Divider for the PLL of the OV6930 ch Bit[7]: Reserved 0x00 RW Bit[6]: e Bit[5:4]: ct T Bit[3:2]: Bypass sys_div Divide the output clock of the PLL PLL_DIV Divide the loop clock in the PLL lle Bit[1:0]: PRE_DIV Divide the reference clock in the PLL – te– Reserved In Bit[7:5]: Reserved 0x300D SC_CTRL0D p0x01 u RW Bit[4:0]: VTS[12:8] high byte Vertical total size 0x300E ro SC_CTRL0E 0xB0 RW Bit[7:0]: VTS[7:0] G Bit[7:2]: Reserved Bit[1]: DVP hsub2 r This bit is 1’b1 when the output image is half l fo 0x300F SC_CTRL0F 0x00 RW the full size in the horizontal direction Bit[0]: DVP hsub4 This bit is 1’b1 when the output image is a tia quarter of the full size in the horizontal direction n0x3010 SC_CTRL10 0x00 RW Bit[7:0]: Chip ID[15:8] high byte e 0x3011 fid 0x3012 SC_CTRL11 SC_CTRL12 0x00 RW Bit[7:0]: Chip ID[7:0] low byte 1’b0 RW Bit[0]: 5060 selection n o C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-3 table 3-2 GPIO control registers (sheet 1 of 4) address register name default value R/W description I/O Pad Drive Strength Control nly Bit[7]: Bit[6]: Bit[5]: Reserved GPIO pad 14 drive strength GPIO pad 13 drive strength O y 0x3100 GPIO_CTRL00 0x00 RW Bit[4]: Bit[3]: Bit[2]: Bit[1]: GPIO pad 12 drive strength GPIO pad 11 drive strength GPIO pad 10 drive strength GPIO pad 9 drive strength g olo Bit[0]: GPIO pad 8 drive strength n I/O Pad Drive Strength Control Bit[7]: GPIO pad 7 drive strength ch e Bit[6]: GPIO pad 6 drive strength 0x3101 GPIO_CTRL01 0x00 RW Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: GPIO pad 5 drive strength T GPIO pad 4 drive strength t GPIO pad 3 drive strength c GPIO pad 2 drive strength lle GPIO pad 1 drive strength GPIO pad 0 drive strength te I/O Pad Output Enable Control (0: enable; 1: disable) Bit[7]: Bit[6]: In Reserved I/O pad 14 output enable 0x3102 GPIO_CTRL02 0x20 RW p Bit[5]: I/O pad 13 output enable Bit[4]: I/O pad 12 output enable u Bit[3]: I/O pad 11 output enable roBit[2]: Bit[1]: I/O pad 10 output enable I/O pad 9 output enable G Bit[0]: I/O pad 8 output enable 0x3103 r tial fo GPIO_CTRL03 0x00 RW n e I/O Pad Output Enable Control (0: enable; 1: disable) Bit[7]: I/O pad 7 output enable Bit[6]: I/O pad 6 output enable Bit[5]: I/O pad 5 output enable Bit[4]: I/O pad 4 output enable Bit[3]: I/O pad 3 output enable Bit[2]: I/O pad 2 output enable Bit[1]: I/O pad 1 output enable Bit[0]: I/O pad 0 output enable 0x3104~ 0x3105 RSfViDd n – – Reserved o C 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-2 GPIO control registers (sheet 2 of 4) address register name default value R/W description ly n I/O Pad Pull-down/Pull-up Control (0: pull-down; 1: pull-up) O Bit[7]: Reserved Bit[6]: I/O pad 14 pull-down/pull-up control 0x3106 0x3107 GPIO_CTRL06 GPIO_CTRL07 y Bit[5]: I/O pad 13 pull-down/pull-up control 0x00 RW Bit[4]: Bit[3]: Bit[2]: I/O pad 12 pull-down/pull-up control g I/O pad 11 pull-down/pull-up control lo I/O pad 10 pull-down/pull-up control Bit[1]: Bit[0]: I/O pad 9 pull-down/pull-up control no I/O pad 8 pull-down/pull-up control I/O Pad Pull-down/Pull-up Control (0: pull-down; 1: pull-up) ch Bit[7]: I/O pad 7 pull-down/pull-up control 0x00 RW Bit[6]: e Bit[5]: T Bit[4]: Bit[3]: ctBit[2]: I/O pad 6 pull-down/pull-up control I/O pad 5 pull-down/pull-up control I/O pad 4 pull-down/pull-up control I/O pad 3 pull-down/pull-up control I/O pad 2 pull-down/pull-up control lleBit[1]: Bit[0]: I/O pad 1 pull-down/pull-up control I/O pad 0 pull-down/pull-up control Inte I/O Pad Input Enable Control Bit[7]: Reserved Bit[6]: I/O pad 14 input enable control Bit[5]: I/O pad 13 input enable control 0x3108 p GPIO_CTRL08 0x7F u ro G r tial fo 0x3109 GPIO_CTRL09 0xFF n e fid n o 0x310A GPIO_CTRL0A 0x00 C RW Bit[4]: I/O pad 12 input enable control Bit[3]: I/O pad 11 input enable control Bit[2]: I/O pad 10 input enable control Bit[1]: I/O pad 9 input enable control Bit[0]: I/O pad 8 input enable control I/O Pad Input Enable Control Bit[7]: I/O pad 7 input enable control Bit[6]: I/O pad 6 input enable control Bit[5]: I/O pad 5 input enable control RW Bit[4]: I/O pad 4 input enable control Bit[3]: I/O pad 3 input enable control Bit[2]: I/O pad 2 input enable control Bit[1]: I/O pad 1 input enable control Bit[0]: I/O pad 0 input enable control I/O Pad Output Value (Register Value) Bit[7]: Reserved Bit[6]: I/O pad 14 output value Bit[5]: I/O pad 13 output value RW Bit[4]: I/O pad 12 output value Bit[3]: I/O pad 11 output value Bit[2]: I/O pad 10 output value Bit[1]: I/O pad 9 output value Bit[0]: I/O pad 8 output value proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-5 table 3-2 GPIO control registers (sheet 3 of 4) address register name default value R/W description I/O Pad Output Value (Register Value) nly 0x310B GPIO_CTRL0B 0x00 0x310C GPIO_CTRL0C 0x00 Bit[7]: I/O pad 7 output value Bit[6]: I/O pad 6 output value O Bit[5]: I/O pad 5 output value y RW Bit[4]: I/O pad 4 output value Bit[3]: I/O pad 3 output value Bit[2]: I/O pad 2 output value Bit[1]: I/O pad 1 output value Bit[0]: I/O pad 0 output value g nolo I/O Pad Output Selection Bit[7]: Reserved ch Bit[6]: Bit[5]: Bit[4]: I/O pad 14 output selection e 0: Normal data path (sensor clock output) T 1: Register control value I/O pad 13 output selection ct 0: v33_o (data output of two-wire interface) 1: Register control value le I/O pad 12 output selection l 0: DVP VSYNC output te 1: Register control value or ADC sync signal RW Inoutput Bit[3]: I/O pad 11 output selection p 0: DVP HREF output 1: Register control value or ADC clock output u Bit[2]: I/O pad 10 output selection ro 0: DVP PCLK output 1: Register control value or ADC data[10] G Bit[1]: r l fo Bit[0]: tia n e fid n o output I/O pad 9 output selection 0: DVP data[9] output 1: Register control value or ADC data[9] output I/O pad 9 output selection 0: DVP data[8] output 1: Register control value or ADC data[8] output C 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-2 GPIO control registers (sheet 4 of 4) address register name default value R/W description I/O Pad Output Selection nly 0x310D GPIO_CTRL0D Bit[7]: I/O pad 7 output selection 0: DVP data[7] output O y 1: Register control value or ADC data[7] output Bit[6]: Bit[5]: Bit[4]: I/O pad 6 output selection g 0: DVP data[6] output lo 1: Register control value or ADC data[6] output I/O pad 5 output selection o 0: DVP data[5] output n 1: Register control value or ADC data[5] output h I/O pad 4 output selection c 0: DVP data[4] output 0x00 RW e1: Register control value or ADC data[4] output Bit[3]: ct T Bit[2]: I/O pad 3 output selection 0: DVP data[3] output 1: Register control value or ADC data[3] output I/O pad 2 output selection lle 0: DVP data[2] output 1: Register control value or ADC data[2] output te Bit[1]: I/O pad 1 output selection 0: DVP data[1] output In 1: Register control value or ADC data[1] output Bit[0]: I/O pad 0 output selection p u 0x310E ro GPIO_CTRL0E – R 0: DVP data[0] output 1: Register control value or ADC data[0] output Input Value of Pads 8~14 Bit[7:0]: Input value or pads 8~14 0x310F r G GPIO_CTRL0F – l fo tia 0x3110 GPIO_CTRL10 0x00 n e fid n o R Input Value of Pads 0~7 Bit[7:0]: Input value or pads 0~7 Bit[7:2]: Reserved Bit[2]: I/O data pad driving strength control of SCCB master RW Bit[1]: I/O clock pad driving strength control of SCCB master Bit[0]: I/O data pad driving strength control of SCCB slave C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-7 table 3-3 SCCB master registers address 0x3900 register name MS_ID default value 0x6C R/W RW description Bit[7:0]: Master ID nly 0x3901~ 0x3902 0x3903 0x3904 0x3905 0x3906 0x3907 table 3-4 address 0x3200 O NOT USED – – Not Used y MA_DO 0xF1 RW Bit[7:0]: Default exposure value g MS_SP 0x01 RW Bit[7:0]: SCCB speed control lo MS_B 0x00 RW Bit[7:3]: Bit[2]: Bit[1]: Bit[0]: o Reserved n Sensor gain no delay h Enable AEC operation for sensor c Support 16-bit address or 8-bit address SN_CMD 0x37 RW Te Bit[7:0]: Operation command for sensor SN_EXP 0x20 RW Bit[7]: Reserved ct Bit[6:0]: Sensor exposure lle SCCB slave registers (sheet 1 of 2) te default In register name value p R/W description SCCB_CTRL 0x00 Bit[7:4]: uBit[3]: ro RW Bit[2:0]: Reserved r_sda_dly_en Enable SDA delay r_sda_dly G Adjust SDA output timing when slave is r l fo tia n 0x3201 e SCCB_OPT 0x12 RW fid n o C transmitting Bit[7:5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Reserved en_ss_addr_inc Enable address increase when sequential read and write r_sda_byp_sync 0: Two clock stage sync for sda_i 1: No sync for sda_i r_scl_byp_sync 0: Two clock stage sync for scl_i 1: No sync for scl_i r_msk_glitch Mask glitch before ACK r_msk_stop Mask stop state of SCCB Bit[7:4]: r_sda_glitch_num 0x3202 SCCB_FILTER 0x00 RW Remove the number of glitches on SDA Bit[3:0]: r_scl_glitch_num Remove the number of glitches on SCL 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-4 SCCB slave registers (sheet 2 of 2) address register name default value R/W description Bit[7]: Reserved nly 0x3203 0x3204 0x3205 0x3206 O Bit[6:4]: PLL reset selection Determines when to disable the reset of PLL SCCB_SYSREG 0x00 RW y Bit[3]: Reset the register setting in SCCB master RSVD Bit[2]: Bit[1]: Bit[0]: Soft reset of the SRB g Reset the register setting in SCCB slave lo Soft reset of the PLL – – Reserved no Bit[7:5]: h Bit[4]: ec Bit[3]: Reserved r_srb_clk_syn_en Clock domain synchronize enable in SRB pwup_dis2 T PWUP_DIS 0x01 t RW Bit[2]: llecBit[1]: te Bit[0]: PADCLK_DIV In p0xFF RW Bit[7:6]: Bit[5:0]: u ro Disable reset of the PLL during wakeup pwup_dis1 Disable reset of the SCCB during wakeup System clock selection 0: System clock from pad clock 1: System clock from PLL pwup_dis0 Disable the reset signal during wakeup Reserved Pad clock divider table 3-5 G SDRAM registers (sheet 1 of 3) r l fo address register name tia 0x3300 DSRAM_CTRL00 default value 0x60 R/W RW description Bit[7:0]: lpix Adjust first pixel location in one line n0x3301 e DSRAM_CTRL01 0x37 RW Bit[7:0]: lrow Adjust last pixel location in one line nfid 0x3302 0x3303 DSRAM_CTRL02 0x32 DSRAM_CTRL03 0x01 RW RW Bit[7:0]: Line sample array location Bit[7:1]: Reserved Bit[0]: Line end location[8] o C 0x3304 DSRAM_CTRL04 0x2C RW Bit[7:0]: Line end location[7:0] Bit[7:2]: Reserved 0x3305 DSRAM_CTRL05 0x00 RW Bit[1:0]: vsync_st[9:8] Adjust the VSYNC signal start point 0x3306 SRAM_CTRL06 0x00 RW Bit[7:0]: vsync_St[7:0] Adjust the VSYNC signal start point proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-9 table 3-5 SDRAM registers (sheet 2 of 3) address register name default value R/W description Bit[7:2]: Reserved nly 0x3307 SRAM_CTRL07 0x00 RW Bit[1:0]: vsync_ed[9:8] Adjust the VSYNC signal end point O 0x3308 SRAM_CTRL08 0x01 0x3309 SRAM_CTRL09 0x00 RW RW Bit[7:0]: vsync_ed[7:0] Adjust the VSYNC signal end point Bit[7:2]: Reserved Bit[1:0]: vref_st[9:8] gy olo n Adjust the VREF signal start point 0x330A SRAM_CTRL0A 0x0C RW h Bit[7:0]: vref_st[7:0] c Adjust the VREF signal start point 0x330B SRAM_CTRL0B 0x03 0x330C SRAM_CTRL0C 0x2C RW RW Bit[7:2]: Bit[1:0]: Bit[7:0]: e Reserved T vref_ed[9:8] t Adjust the VREF signal end point c vref_ed[7:0] lle Adjust the VREF signal end point 0x330D SRAM_CTRL0D 0x01 RW Bit[7:2]: Reserved te Bit[1:0]: add_ed[9:8] InNumber of data points 0x330E SRAM_CTRL0E 0x8F 0x330F SRAM_CTRL0F 0x00 0x3310 SRAM_CTRL10 r 0x1A l fo 0x3311 tia SRAM_CTRL11 0x03 n e 0x3312 nfid SRAM_CTRL12 0x00 o RW p Bit[7:0]: u ro Bit[7:2]: RW Bit[1:0]: G RW Bit[7:0]: Bit[7:2]: Bit[1]: RW Bit[0]: Bit[7:4]: RW Bit[3:2]: Bit[1]: Bit[0]: add_ed[7:0] Number of data points Reserved rblc[9:8] BLC protocol end point rblc[7:0] BLC protocol end point Reserved strobe_blc Perform black line correction in strobe mode blc_agc Perform black line correction when AGC changes Reserved bist_result bist_busy bist_en C 0x3313~ 0x3318 RSVD – – Reserved 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-5 SDRAM registers (sheet 3 of 3) address register name default value R/W description VSYNC1 nly 0x3319 0x331A 0x331B 0x331C 0x331D 0x331E DSRAM_CTRL19 DSRAM_CTRL1A DSRAM_CTRL1B DSRAM_CTRL1C DSRAM_CTRL1D DSRAM_CTRL1E 0xA4 RW O Bit[7]: OV6930 VSYNC selection 0: Not valid 1: OV6930 y 0x3C g Bit[6:0]: Interval between VSYNC and first HREF RW VSYNC2 olo Bit[7:0]: Interval between VSYNC and last HREF 0x0A 0x5F RW RW n Bit[7:0]: dmy_line Number of dummy line ch Bit[7:0]: pixel_dly_w eHow many pixels are blanket 0x31 0xC8 t T RW Bit[7:0]: pixel_dly_r How many pixels are blanket llec RW Bit[7:0]: hsize Horizontal size[8:1] high byte Inte ADC Sync Control Bit[7:5]: reserved Bit[4]: Horizontal size[0] low byte Bit[3]: VYSNC start selection 0x331F up DSRAM_CTRL1F 0x46 ro RW Bit[2]: 0: VSYNC signal will assert 127 sclk after sync rising edge 1: VSYNC signal will assert 63 sclk after sync rising edge Strobe mode enable G Bit[1]: AGC mode enable r Bit[0]: Image mirror enable l fo 0x3320 DSRAM_CTRL20 0x00 tia 0x3321 DSRAM_CTRL21 0xA4 n RW RW Bit[7:1]: Reserved Bit[0]: r_vref_dly[8] VREF end point Bit[7:0]: r_vref_dly[7:0] VREF end point e 0x3322 nfid 0x3323 DSRAM_CTRL22 0x03 DSRAM_CTRL23 0xFF RW RW Bit[7:2]: Reserved Bit[1:0]: Strobe counter[9:8] high byte Bit[7:0]: Strobe counter[7:0] low byte o C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-11 table 3-6 BLC control registers (sheet 1 of 2) address 0x3400~ 0x3401 register name RSVD default value – R/W description – Reserved nly O 0x3402 BLC_CTRL02 0x45 0x3403 BLC_CTRL03 0x08 0x3404 RSVD – 0x3405 BLC_CTRL05 0x18 RW Bit[7]: Bit[6]: Bit[5:0]: BLC will redo N frames after format change y input is high g BLC auto enable lo Frame number BLC will redo after reset Bit[7]: Bit[6]: o BLC will redo N frames after BLC redo enable n Freeze enable RW Bit[5:0]: BLC offsets will not update priority lower than h always update c Manual frame number e Frame number BLC will redo after some T conditions like manual calibration BLC redo – enable occurred, and format changed ct Reserved lle Bit[7:2]: Reserved RW te Bit[1]: BLC always update enable 0: Enable In1: Disable Bit[0]: Reserved 0x3406~ 0x3408 0x3409 RSVD BLC_CTRL09 – 0x10 – up Reserved ro RW Black Target Level 0x340A~ 0x342B RSVD – –G r 0x342C BLC_CTRL2C – l fo R 0x342D tia BLC_CTRL2D – R 0x342E en BLC_CTRL2E – R 0x342F fid BLC_CTRL2F – R n o 0x3430 BLC_CTRL30 – R C 0x3431 BLC_CTRL31 – R Reserved Bit[7:4]: Reserved Bit[3:0]: Blacklevel00 high 4 bits for B Bit[7:0]: Blacklevel00 low 8 bits for B (including 3 bits for fractions) Bit[7:4]: Reserved Bit[3:0]: Blacklevel01 high 4 bits for Gb Bit[7:0]: Blacklevel01 low 8 bits for Gb (including 3 bits for fractions) Bit[7:4]: Reserved Bit[3:0]: Blacklevel10 high 4 bits for Gr Bit[7:0]: Blacklevel10 low 8 bits for Gr (including 3 bits for fractions) 0x3432 BLC_CTRL32 – R Bit[7:4]: Reserved Bit[3:0]: Blacklevel11 high 4 bits for R 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-6 BLC control registers (sheet 2 of 2) address register name 0x3433 BLC_CTRL33 default value – R/W R description ly n Bit[7:0]: Blacklevel11 low 8 bits for R (including 3 bits for fractions) O 0x3434~ 0x344B RSVD – – Reserved gy 0x344C BLC_CTRL4C – R Bit[7:6]: Reserved olo Bit[5:0]: Black line number send to BLC module 0x344D 0x344E BLC_CTRL4D BLC_CTRL4E – 0xFF R RW Bit[7:6]: Reserved n Bit[5:0]: Black line number used for statistics ch Specify Max Black Level e Bit[7]: Stable range enable T Redo BLC 1 frame when the difference of two 0x344F BLC_CTRL4F 0x7F RW ct lle Bit[6:0]: frames out the stable range 0: Disable 1: Enable Stable range value te table 3-7 p In AEC control registers (sheet 1 of 3) u default ro address register name value R/W description G Bit[7]: Reserved Bit[6]: Less than one line enable r 0: Disable l fo Bit[5]: 1: Enable Band enable 0: Disable tia 0x3500 AEC_CTRL00 0x78 n e RW Bit[4]: Bit[3]: 1: Enable Less than one band enable 0: Disable 1: Enable AEC start selection nfid Bit[2]: Bit[1]: Bit[0]: Reserved New balance Freeze o 0x3501 AEC_CTRL01 0x04 RW Bit[7:0]: Min exposure C 0x3502 AEC_CTRL02 0x0F RW Bit[7:0]: Max exposure for 60Hz[15:8] high byte 0x3503 AEC_CTRL03 0xE0 RW Bit[7:0]: Max exposure for 60Hz[7:0] low byte 0x3504 RSVD – – Reserved proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-13 table 3-7 AEC control registers (sheet 2 of 3) address register name default value R/W description Bit[7]: F50 reverse nly 0x3505 AEC_CTRL05 0x30 0x3506 AEC_CTRL06 0x10 0x3507 AEC_CTRL07 0x18 0x3508 AEC_CTRL08 0x00 0x3509 AEC_CTRL09 0x98 0x350A AEC_CTRL0A 0x00 0x350B AEC_CTRL0B 0x7F 0: Hold 50Hz/60Hz detect input RW 1: Switch 50Hz/60Hz detect input Bit[6]: Frame insert enable O y Bit[5]: Step auto enable Bit[4:0]: Step auto ratio Bit[7:5]: Reserved RW Bit[4:0]: step_man1 Increase mode fast step g nolo Bit[7:4]: step_man2 RW Slow step Bit[3:0]: step_man3 ech T Decrease mode fast step RW t Bit[7:2]: Reserved c Bit[1:0]: b50_step[9:8] lle AEC band50 width RW te Bit[7:0]: b50_step[7:0] AEC band50 width In Bit[7:2]: Reserved RW Bit[1:0]: b60_step[9:8] p AEC band60 width rou RW Bit[7:0]: b60_step[7:0] AEC band60 width G 0x350C AEC_CTRL0C r 0xE4 RW l fo 0x350D tia AEC_CTRL0D 0x04 RW n 0x350E e AEC_CTRL0E 0x03 RW fid n 0x350F AEC_CTRL0F 0x78 RW o Bit[7:4]: Bit[3:0]: e1_max Max exposure when less than one line mode e1_min Min exposure when less than one line mode Bit[7:6]: Reserved Bit[5:0]: b60_max 60Hz max band in one frame Bit[7:6]: Reserved Bit[5:0]: b50_max 50Hz max band in one frame Stable Range High Limit Bit[7:0]: WPT Stable range high threshold 1 C 0x3510 AEC_CTRL10 0x68 Stable Range Low Limit RW Bit[7:0]: BPT Stable range low threshold 1 0x3511 AEC_CTRL11 0xD0 RW Fast Zone High Limit Bit[7:0]: vpt_high 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-7 AEC control registers (sheet 3 of 3) address 0x3512 register name AEC_CTRL12 default value 0x00 R/W RW description Bit[7:0]: Manual average value nly 0x3513 RSVD – – Reserved O 0x3514 0x3515 0x3516~ 0x3517 AEC_CTRL14 AEC_CTRL15 RSVD 0x3518 AEC_CTRL18 0x0E 0x40 – 0x01 RW y Bit[7:0]: Max exposure for 50Hz[15:8] high byte RW log Bit[7:0]: Max exposure for 50Hz[7:0] low byte – Reserved o n RW Bit[7:2]: Reserved h Bit[1:0]: g_snr_ceil[9:8] high byte ecSensor gain ceiling 0x3519 0x351A 0x351B 0x351C~ 0x351D 0x351E AEC_CTRL19 AEC_CTRL1A AEC_CTRL1B 0xFF RW T Bit[7:0]: ctBit[7:0]: g_snr_ceil[7:0] low byte Sensor gain ceiling diff_min 0x04 RWlle Minimum difference when integral frame exposure 0x78InteRW Stable Range High Limit Bit[7:0]: WPT2 RSVD p– u ro AEC_CTRL1E 0x68 – Reserved RW Stable Range Low Limit Bit[7:0]: BPT2 0x351F G AEC_CTRL1F 0x40 r l fo 0x3520 AEC_CTRL20 0x20 tia n e 0x3521 AEC_CTRL21 0x78 nfid 0x3522~ 0x3524 RSVD – o RW Fast Zone Low Limit Bit[7:0]: VPT_LOW Bit[7]: BLC enable Bit[6:3]: BLC RW Bit[2]: Strobe option Bit[1]: Manual average enable Bit[0]: Exposure no change enable Bit[7]: Reserved RW Bit[6:4]: Number of frames inserted Bit[3:0]: Reserved – Reserved Bit[7:5]: Reserved C 0x3525 AEC_CTRL25 0x00 RW Bit[4:2]: Freeze counter Bit[1:0]: Reserved 0x3526~ 0x354F RSVD – – Reserved 0x3550 AEC_CTRL50 – R Bit[7:0]: average[7:0] proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-15 table 3-8 AEC_pk control registers address register name 0x3600 AEC_PK_CTRL00 0x3601 AEC_PK_CTRL01 0x3602 AEC_PK_CTRL02 0x3603 AEC_PK_CTRL03 0x3604 AEC_PK_CTRL04 0x3605 AEC_PK_CTRL05 0x3606~ 0x3607 NOT USED default value 0x00 0x02 0x00 0x00 – – – R/W RW RW RW RW R R – description AEC Exposure Value in AEC PK nly Bit[7:4]: Reserved Bit[3:0]: expo_pk[19:16] O y AEC Exposure Value in AEC PK g Bit[7:0]: expo_pk[15:8] lo AEC Exposure Value in AEC PK o Bit[7:0]: expo_pk[7:0] n Bit[7:2]: Reserved h Bit[1]: AGC manual enable ec Bit[0]: AEC manual enable Gain to Sensor T Bit[7:2]: Reserved ct Bit[1:0]: pk_gain_o[9:8] lle Gain to Sensor Bit[7:0]: pk_gain_o[7:0] te Not Used In Gain to Sensor 0x3608 AEC_PK_CTRL08 0x00 0x3609 AEC_PK_CTRL09 0x00 RW Bit[7:2]: Reserved upBit[1:0]: gain_pk[9:8] ro RW Gain to Sensor Bit[7:0]: gain_pk[7:0] 0x360A~ 0x360B NOT USED – r G– 0x360C AEC_PK_CTRL0C l 0xf0o0 RW 0x360D tia AEC_PK_CTRL0D0 0x00 RW n e fid n o Not Used Adding VTS Bit[7:0]: add_vts_pk[15:8] Adding VTS Bit[7:0]: add_vts_pk[7:0] C 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-9 DVP control registers address 0x3700 0x3701 0x3702 0x3703 register name RSVD DVP_CTRL01 DVP_CTRL02 DVP_CTRL03 0x3704 DVP_CTRL04 0x3705 DVP_CTRL05 0x3706 DVP_CTRL06 0x3707 DVP_CTRL07 default value – R/W – description Reserved nly 0x01 RW O Bit[7:0]: VSYNC length – line count 0x00 RW gy Bit[7:0]: VSYNC length – pixel count high byte 0x00 RW lo Bit[7:0]: VSYNC length – pixel count low byte 0x0 RW Bit[7:4]: Bit[3:2]: Bit[1]: Bit[0]: Reserved o r_vsyncout_sel n r_vsync3_mod ch r_vsync2_mod 0x00 RW Bit[7:0]: SOF/EOF negative edge to VSYNC positive Teedge high byte 0x00 RW Bit[7:0]: SOF/EOF negative edge to VSYNC positive ct edge middle byte 0x00 lle RW Bit[7:0]: SOF/EOF negative edge to VSYNC positive edge low byte te Bit[7]: Clock DDR mode enable In Bit[6]: Reserved Bit[5]: VSYNC gate clock enable 0x3708 DVP_CTRL08 p0x01 u RW Bit[4]: Bit[3]: Bit[2]: HREF gate clock enable No first for FIFO HREF polarity ro Bit[1]: VSYNC polarity Bit[0]: PCLK polarity / PCLK gate low enable G Bit[7]: fifo_bypass mode r Bit[6:4]: Data bit swap l fo 0x3709 DVP_CTRL09 0x00 RW Bit[3]: Bit[2]: Bit[1]: Bit mode test mode Bit mode 10-bit test Bit mode 8-bit test tia Bit[0]: Bit mode test enable Bit[7:5]: Reserved n0x370A DVP_CTRL0A 0x00 RW Bit[4]: HREF selection e Bit[3:0]: Bypass selection fid n o C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-17 table 3-10 ISP_top registers (sheet 1 of 2) address register name default value R/W description Bit[7]: Enable filter nly Bit[6]: Enable BLC Bit[5]: Enable LENC O 0x4000 ISP_CTRL00 0xFF RW Bit[4]: Enable AWB Bit[3]: Enable AWB gain gy Bit[2]: Enable white pixel correction Bit[1]: Enable black pixel correction lo Bit[0]: Enable window cut o Bit[7]: r_squ_bw Bit[6]: r_rnd_same Bit[5:4]: r_bar_style n ch 0x4001 ISP_CTRL01 0x00 RW Bit[3]: r_isp_test e Bit[2]: Bit[1]: Bit[0]: r_trans r_rolling r_test_en ct T 0x4002 ISP_CTRL02 0x41 RW Bit[7]: Bit[6]: Bit[5:4]: Bit[3:0]: Reserved e r_avg_sel ll r_test_sel te r_rnd_seed 0x4003 ISP_CTRL03 0x00 RW In Bit[7:1]: Reserved Bit[0]: r_ln_number[8] 0x4004 ISP_CTRL04 0x01 RW up Bit[7:0]: 0x4005 ISP_CTRL05 0x00 Bit[7:5]: ro RW Bit[4]: Bit[3]: G Bit[2:0]: 0x4006 ISP_CTRL06 r l fo 0x00 RW tia Bit[7:6]: Bit[5]: Bit[4]: Bit[3:2]: Bit[1:0]: 0x4007 en ISP_CTRL07 0x00 RW Bit[7:1]: Bit[0]: 0x4008 fid ISP_CTRL08 n 0x4009 ISP_CTRL09 o 0x00 0x00 RW RW Bit[7:0]: Bit[7:1]: Bit[0]: r_ln_number[7:0] r_dmy_ratio r_dmy_half r_dmy_man r_dmy_line Reserved r_rblue r_hswap r_lenc_hskip r_lenc_vskip Reserved r_lenc_x_start[8] r_lenc_x_start[7:0] Reserved r_lenc_y_start[8] C 0x400A ISP_CTRL0A 0x00 RW Bit[7:0]: r_lenc_y_start[7:0] Bit[7:3]: r_blackline_num 0x400B ISP_CTRL0B 0x14 RW Bit[2]: r_lenc_bias_plus Bit[1]: r_gain_man_en Bit[0]: r_bias_man_en 0x400C ISP_CTRL0C 0x00 RW Bit[7:0]: r_bias_man 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-10 ISP_top registers (sheet 2 of 2) address 0x400D register name ISP_CTRL0D default value 0x00 R/W RW description Bit[7:0]: r_gain_man nly 0x400E ISP_CTRL0E 0x400F 0x4010 0x4011 0x4012 ISP_CTRL0F ISP_CTRL10 ISP_CTRL11 ISP_CTRL12 0x4013 ISP_CTRL13 0x4014 ISP_CTRL14 0x00 RW Bit[7:1]: Reserved Bit[0]: wbc_bist_en O y 0x01 RW Bit[7:1]: Reserved g lo Bit[0]: r_isp_hsize_in[8] 0x90 RW o Bit[7:0]: r_isp_hsize_in[7:0] 0x01 0x90 RW RW n Bit[7:1]: Reserved Bit[0]: r_isp_vsize_in[8] ech Bit[7:0]: r_isp_vsize_in[7:0] 0x00 RW r_isp_hvoffs_in T Bit[7:4]: Horizontal offset ctBit[3:0]: Vertical offset 0x00 teRWlle Bit[7:3]: Bit[2]: Bit[1]: Bit[0]: Reserved r_mirror r_blk_flip r_img_flip In table 3-11 p LENC control registers (sheet 1 of 2) u ro address register name default value R/W description 0x4080 G RED_X0 r 0x4081 l fo 0x4082 RED_X0 RED_Y0 0x4083 ntia 0x4084 RED_Y0 RED_A1 e 0x4085 RED_A2 fid 0x4086 RED_B1 n 0x4087 RED_B2 o 0x4088 GRN_X0 0x01 0x88 0x01 0x2A 0x22 0x07 0xC2 0x08 0x01 RW Red Center Horizontal Position (x0) high bits RW Red Center Horizontal Position (x0) low eight bits RW Red Center Vertical Position (y0) high bits RW Red Center Vertical Position (y0) low eight bits RW Red Parameter a1 RW Red Parameter a2 RW Red Parameter b1 RW Red Parameter b2 RW Green Center Horizontal Position high bits C 0x4089 GRN_X0 0x88 RW Green Center Horizontal Position low eight bits 0x408A GRN_Y0 0x01 RW Green Center Vertical Position (y0) high bits 0x408B GRN_Y0 0x2A RW Green Center Vertical Position (y0) low eight bits 0x408C GRN_A1 0x22 RW Green Parameter a1 proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-19 table 3-11 LENC control registers (sheet 2 of 2) address 0x408D register name GRN_A2 default value 0x07 R/W RW description Green Parameter a2 nly 0x408E GRN_B1 0xC2 RW Green Parameter b1 O 0x408F 0x4090 0x4091 0x4092 0x4093 0x4094 0x4095 0x4096 0x4097 GRN_B2 BLU_X0 BLU_X0 BLU_Y0 BLU_Y0 BLU_A1 BLU_A2 BLU_B1 BLU_B2 0x4098 LENC_CTRL00 0x4099 LENC_COEF_TH 0x08 0x01 0x88 0x01 0x2A 0x22 0x07 0xC2 0x08 0x0C 0x80 RW Green Parameter b2 y RW RW g Blue Center Horizontal Position high bits olo Blue Center Horizontal Position low eight bits RW n Green Center Vertical Position (y0) high bits RW ch Green Center Vertical Position (y0) low eight bits RW Blue Parameter a1 e RW Blue Parameter a2 T RW Blue Parameter b1 ct RW Blue Parameter b2 lle Bit[7:4]: Reserved te Bit[3]: Seed reset enable RW In Resets seed when VSYNC starts Bit[2]: Round enable p To generate random round bit Bit[1]: Coefficient manual mode enable u Bit[0]: LENC gain coefficient enable ro RW LENC Coefficient Threshold 0x409A G LENC_GAIN_THRE1 0x06 RW 0x409B r LENC_GAIN_THRE2 0x0C RW 0x409C COEF_MAN l fo 0x80 RW tia n e fid n o LENC Gain Low Threshold (T1) LENC Gain High Threshold (T2) Coefficient Manual Set Input C 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-12 AWB control registers (sheet 1 of 2) address register name 0x4100 AWB_CTRL00 0x4101 AWB_DELTA 0x4102 STABLE_RANGE default value R/W description Bit[7]: hsize_man_en nly 0x00 RW O Enable manual setting horizontal size Bit[6]: fast_awb y Use fast AWB calculation or not g Bit[5]: freeze_gain_en lo Freeze current gain value Bit[4]: freeze_sum_en o Freeze current sum and average value Bit[3]: echn Bit[2]: gain_man_en Manual set the gain value start_sel 0: Select the after gain to trigger AWB start signal T ctBit[7:6]: 0x20 lle RW Bit[5:0] te Bit[7:0]: In 0x04 RW 1: Select the before gain to trigger AWB start signal Reserved awb_delta[5:0] Delta value to increase or decrease the gains stable_range Stable range to define the stable status from unstable to stable p 0x4103 u STABLE_RANGEW 0x08 RW ro Bit[7:0]: stable_rangew[7:0] Wide stable range to determine whether it is in stable status when it is already in stable status 0x4104 G HSIZE_MAN r 0x4105 HSIZE_MAN tial fo 0x4106 RED_GAIN en0x4107 RED_GAIN fid 0x4108 GRN_GAIN n o C 0x4109 GRN_GAIN 0x01 RW 0xE0 RW 0x04 RW 0x00 RW 0x04 RW 0x00 RW Bit[7:4]: Reserved Bit[3:0]: Manual horizontal size bits[11:8] Bit[7:0]: Manual horizontal size bits[7:0] Bit[7:4]: Reserved Bit[3:0]: red_gain[11:8] high byte Manual set red gain Bit[7:0]: red_gain[7:0] low byte Manual set red gain Bit[7:4]: Reserved Bit[3:0]: grn_gain[11:8] high byte Manual set green gain Bit[7:0]: grn_gain[7:0] low byte Manual set green gain 0x410A BLU_GAIN 0x04 RW Bit[7:4]: Reserved Bit[3:0]: blu_gain[11:8] high byte Manual set blue gain proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-21 table 3-12 AWB control registers (sheet 2 of 2) address register name 0x410B BLU_GAIN default value 0x00 R/W RW description Bit[7:0]: blu_gain[7:0] low byte Manual set blue gain nly O 0x410C GAIN_R_LIMIT 0xF0 0x410D GAIN_G_LIMIT 0xF0 0x410E GAIN_B_LIMIT 0xF0 0x410F AWB_FRAME_CNT 0x02 RW gain_r_limit y Red gain is within the range {gain_r_up_limit,FF} and g {gain_r_dn_limit,00} Bit[7:4]: gain_r_up_limit olo Bit[3:0]: gain_r_dn_limit gain_g_limit n RW Green gain is within the range {gain_r_up_limit,FF} and h {gain_r_dn_limit,00} c Bit[7:4]: gain_g_up_limit e Bit[3:0]: gain_g_dn_limit RW T gain_b_limit t Blue gain is within the range {gain_r_up_limit,FF} and c {gain_r_dn_limit,00} Bit[7:4]: gain_b_up_limit lle Bit[3:0]: gain_b_dn_limit te Bit[7:4]: Reserved RW In Bit[3:0]: awb_frame_cnt[3:0] Defines how many frames to do AWB 0x4110 CURR_RED_GAIN – 0x4111 CURR_RED_GAIN – r 0x4112 l fo CURR_GRN_GAIN – 0x4113 tia CURR_GRN_GAIN – n 0x4114 e CURR_BLU_GAIN – 0x4115 nfid CURR_BLU_GAIN – o C 0x4116 RED_BFG_AVG – pBit[7:4]: R uBit[3:0]: Gro R Bit[7:0]: Bit[7:4]: R Bit[3:0]: R Bit[7:0]: Bit[7:4]: R Bit[3:0]: R Bit[7:0]: R Bit[7:0]: Reserved curr_red_gain[11:8] high byte Current red gain curr_red_gain[7:0] low byte Current red gain Reserved curr_grn_gain[11:8] high byte Current green gain curr_grn_gain[7:0] low byte Current green gain Reserved curr_blu_gain[11:8] high byte Current blue gain curr_blu_gain[7:0] low byte Current blue gain red_bfg_avg[7:0] high byte Red average after gain 0x4117 GRN_BFG_AVG – R Bit[7:0]: grn_bfg_avg[7:0] high byte Green average after gain 0x4118 BLU_BFG_AVG – R Bit[7:0]: blu_bfg_avg[7:0] high byte Blue average after gain 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-13 DPC control registers address register name default value R/W description nly 0x4280 DPC_CTRL00 0x4281 DPC_CTRL01 0x4282 DPC_CTRL02 Bit[7]: Reserved O y Bit[6]: white_en Enable correction of the white pixel Bit[5]: black_en g Bit[4]: Enable correction of the black pixel lo sc_en o Enable same channel detection 0x78 RW n Bit[3]: dc_en ech Bit[2]: Enable different channel detection smooth_en Enable using average G values when doing recovery T Bit[1]: bwsnr_en ctBit[0]: Enable the B/W sensor Reserved 0x13 lle Bit[7:5]: Reserved RW Bit[4]: Enable the color line te Bit[3:0]: Option for padding the boundary pixel In 3'h4 RW Bit[2:0]: Vertical line number table 3-14 p u ro windowing control registers (sheet 1 of 2) r G address register name l fo 0x4300 WINDOW_CTRL00 tia 0x4301 WINDOW_CTRL01 n e 0x4302 WINDOW_CTRL02 nfid 0x4303 WINDOW_CTRL03 o 0x4304 WINDOW_CTRL04 C default value 0x00 0x00 0x00 0x00 0x10 R/W RW RW RW RW RW description Bit[7:5]: Reserved Bit[4:0]: xstart[12:8] Start address in horizontal Bit[7:0]: xstart[7:0] Bit[7:4]: Reserved Bit[3:0]: ystart[11:8] Start address in vertical Bit[7:0]: ystart[7:0] Bit[7:5]: Reserved Bit[4:0]: x_win[12:8] Selects whole zone width 0x4305 WINDOW_CTRL05 0xA0 RW Bit[7:0]: x_win[7:0] 0x4306 WINDOW_CTRL06 0x0C RW Bit[7:4]: Reserved Bit[3:0]: y_win[11:8] Selects whole zone height proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 3-23 table 3-14 windowing control registers (sheet 2 of 2) address 0x4307 register name WINDOW_CTRL07 default value 0x78 R/W RW description Bit[7:0]: y_win[7:0] nly Bit[7:1]: Reserved O 0x4308 WINDOW_CTRL08 0x00 RW Bit[0]: win_man_en y 0: Window size from window top g 1: Window size from register 0x4300 to lo register 0x4307 Bit[7:5]: Reserved o 0x4309 WINDOW_CTRL09 – R Bit[4:0]: px_cntt[12:8] n 0x430A WINDOW_CTRL0A – R Pixel count from input image in horizontal ch Bit[7:0]: px_cnt[7:0] 0x430B WINDOW_CTRL0B – 0x430C WINDOW_CTRL0C – R R e Bit[7:4]: Reserved T Bit[3:0]: ln_cnt[11:8] t Line count from input image in vertical llec Bit[7:0]: ln_cnt[7:0] te table 3-15 AVERAGE registers (sheet 1 of 2) In default p address register name value u R/W description 0x4380 AVG_CTRL00 0x00 Gro RW Bit[7:5]: Bit[4:0]: Reserved AVG start position[12:8] at horizontal 0x4381 AVG_CTRL01 r 0x00 RW Bit[7:0]: AVG start position[7:0] at horizontal 0x4382 AVG_CTRL02 l fo 0x00 RW Bit[7:5]: Reserved Bit[4:0]: AVG start position[11:8] at vertical 0x4383 0x4384 tia AVG_CTRL03 0x00 n AVG_CTRL04 0x10 RW RW Bit[7:0]: AVG start position[7:0] at vertical Bit[7:5]: Reserved Bit[4:0]: Select whole zone width[12:8] 0x4385 0x4386 e AVG_CTRL05 nfid AVG_CTRL06 0xA0 0x0C RW RW Bit[7:0]: Select whole zone width[7:0] Bit[7:5]: Reserved Bit[4:0]: Select whole zone height[11:8] o 0x4387 AVG_CTRL07 0x78 RW Bit[7:0]: Select whole zone height[7:0] C 0x4388 AVG_CTRL08 0x11 RW Bit[7:4]: Weight of zone01 Bit[3:0]: Weight of zone00 0x4389 AVG_CTRL09 0x11 RW Bit[7:4]: Weight of zone03 Bit[3:0]: Weight of zone02 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor table 3-15 AVERAGE registers (sheet 2 of 2) address register name 0x438A AVG_CTRL0A default value 0x11 R/W RW description Bit[7:4]: Weight of zone11 Bit[3:0]: Weight of zone10 nly O 0x438B AVG_CTRL0B 0x11 RW Bit[7:4]: Weight of zone13 gy Bit[3:0]: Weight of zone12 0x438C AVG_CTRL0C 0x11 RW Bit[7:4]: Weight of zone 21 olo Bit[3:0]: Weight of zone20 0x438D AVG_CTRL0D 0x438E AVG_CTRL0E 0x11 0x11 RW RW Bit[7:4]: Bit[3:0]: Bit[7:4]: Weight of zone23 n Weight of zone22 ch Weight of zone31 e Bit[3:0]: Weight of zone30 0x438F AVG_CTRL0F 0x4390 AVG_CTRL10 0x11 T RW Bit[7:4]: Bit[3:0]: ctBit[7:2]: lle Bit[1]: te 0x11 RW In Bit[0]: Weight of zone33 Weight of zone32 Reserved Avg add option 0: Sum = (4*B+9*G*2+10*R)/8 1: Sum = B+G*2+R Average size manual mode 0: Window size from window top 1: Window size from register 0x4300 to p register 0x4307 0x4391 u AVG_CTRL11 – R Bit[7:0]: Sum of weight ro Bit[7:1]: Reserved 0x4392 G AVG_CTRL12 – R Bit[0]: Average calculated indicating signal for SCCB read l for 0x4393 AVG_CTRL13 – tia n e fid n o R Bit[7:0]: High 8 bits of whole image average output C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 4-1 4 operating specifications 4.1 absolute maximum ratings nly O table 4-1 absolute maximum ratings y parameter g absolute maximum ratinga ambient storage temperature -40°C to +125°C olo supply voltage (with respect to ground) electro-static discharge (ESD) VDD-A VDD-IO human body model 4.5V 4.5V 2000V n ech machine model T 200V all input/output voltages (with respect to ground) ct-0.3V to VDD-IO + 1V I/O current on any input or output pin + 200 mA lle peak solder temperature (10 second dwell time) 245°C te a. exceeding the absolute maximum ratings shown above invalidates all AC and DC electrical specifications and may In result in permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. p u 4.2 functional temperature ro G r table 4-2 functional temperature l fo parameter range tia operating temperature rangea -30°C to +70°C n stable image temperature rangeb 0°C to 50°C a. b. e sensor functions but image quality may be noticeably different at temperatures outside of stable image range fid image quality remains stable throughout this temperature range n o C 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor 4.3 DC characteristics table 4-3 DC characteristics nly symbol parameter condition min typ O max unit supply gy AVDD supply voltage (analog) 3.3V ±10% 3.0 lo 3.3 3.6 V DOVDD supply voltage (digital I/O) 3.3V ±10% 3.0 o3.3 3.6 n V DVDD supply voltage (digital core) 1.8V ±10% ch 1.62 1.8 1.98 V IDDS IDDA IL suspend mode current active (operating) current input/output leakage e T ct GND VDD_IO na na 10 µA mA µA lle digital inputs (typical conditions: AVDD = 3.3V, DOVDD =3.3V) VIH input voltage HIGH te CMOS 0.7 x VDD_IO V VIL input voltage lOW InCMOS 0.3 x VDD_IO V p digital outputs (standard loading 25 pF) VOH u output voltage HIGH CMOS 0.9 x VDD_IO V VOL ro output voltage LOW CMOS 0.1 x VDD_IO V G onfidential for C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 5-1 5 mechanical specifications 5.1 physical specifications figure 5-1 package specifications nly O table 5-1 A S A1 D D1 e/2 5x e E X A1 corner aaa (4x) Y bbb C ccc C detail B (rotate 90°) Z seating plane note 2 package dimensions detail B A1 corner y 654321 A g A B C olo A 36x Øb Øeee M C note 1 D E n F ch 5x e e e/2 Øddd M C A B T E1 view A-A ct note 1 dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. le note 2 datum Z (seating plane) is defined by the spherical tel crowns of the solder balls. 420_wCSP_DS_5_1 In parameter symbol up dimensions package size in X E ro3.21 package size in Y G D 3.21 total thickness Ar 0.54 ± 0.055 pitch wafer thickness l foe S 0.5 0.3 ± 0.025 ball diameter tia 0.3 stand off n A1 0.21 ~ 0.27 e ball/bump width fid package edge tolerance b 0.29 ~ 0.35 aaa 0.05 n wafer flatness bbb 0.1 o coplanarity ccc 0.075 C ball/bump offset (package) ddd 0.15 units mm mm mm mm mm mm mm mm mm mm mm mm ball/bump offset (ball) eee 0.05 mm edge ball center-to-center in X E1 2.5 mm edge ball center-to-center in Y D1 2.5 mm 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies temperature (°C) -22 -2 18 38 58 78 98 118 138 158 178 198 218 238 258 278 298 318 338 358 369 OV420 medical bridge processor 5.2 IR reflow specifications note The OV420 uses a lead free package. figure 5-2 300.0 280.0 260.0 240.0 220.0 200.0 180.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 IR reflow ramp rate requirements Z1 Z2 Z3 Z4 Z5 Z6 ly Z7 n end O gy nolo ech Intellect T roup table 5-2 G reflow conditions r condition l fo average ramp-up rate (30°C to 217°C) tia > 100°C > 150°C en> 217°C nfid peak temperature cool-down rate (peak to 50°C) o time from 30°C to 245°C C time (sec) 420 DS 5 2 exposure less than 3°C per second between 330 - 600 seconds at least 210 seconds at least 30 seconds (30 ~ 120 seconds) 245°C less than 6°C per second no greater than 390 seconds proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 rev-1 revision history version 0.1 11.13.2008 nly • initial release O version 0.2 • • • y 07.10.2009 g lo on page iii, changed ordering part number and description to "OV00420-A36G" and "36-pin o wCSP™" n on page iii, added "low cost, single-chp solution for the OV6930 medical chip", "auto gain/exposure control", and "digital signal processor (DSP)" to features ch on page iii, removed "low voltage 1.5V (core), 3.3V (analog) and 3.3V (I/O) operation" from features e and changed "supports 10 bits digital parallel output" to "RAW output with 10-bit parallel digital video port (DVP)" T • on page iii, changed power supply (core) to "1.8V ± 10%", power supply (I/O) to "3.3V ± 10%", and ct power supply (analog) to "3.3V ± 10%" • lle on page iii, changed temperature range to "-30°C to 70°C" and package dimensions to "3.17 mm x 3.17 mm" • in section 1, replaced table 1-1 and figure 1-1 te • • In in section 2, replaced figure 2-1 and figure 2-2 and removed figure 2-3 and figure 2-4 in section 2, added reference schematic (new figure 2-3) • in section 2, renamed subsection 2.2.1 p • u in section 2, added subsection 2.2.3, auto exposure (AEC), subsection 2.2.4, digital signal o processor (DSP), subsection 2.2.6, two-wire interface, and subsection 2.2.7, synchronized color r bar for data path performance G • in section 3, replaced all tables in section 3, register tables r • restructured and renamed section 4, operating specifications • l fo in section 5, replaced figure 5-1 and table 5-1 tia n e fid n o C 07.10.2009 OBJECTIVE SPECIFICATION proprietary to OmniVision Technologies OV420 medical bridge processor nly O gy nolo ech Intellect T roup G onfidential for C proprietary to OmniVision Technologies OBJECTIVE SPECIFICATION version 0.2 nly O gy nolo ech Intellect T roup G onfidential for C the clear advantage™ nly O gy nolo ech Intellect T roup G r l fo OmniVision Technologiest,iIanc. n UNITED STATES e FINLAND fid 4275 Burton Drive Santa Clara, CA 95054 Mouhijärvi + 358 3 341 1898 n tel: + 1 408 567 3000 o fax: + 1 408 567 3001 GERMANY Munich +49 89 63 81 99 88 C email: salesamerican@ovt.com JAPAN Tokyo + 81 3 5765 6321 KOREA Seoul + 82 2 3478 2812 CHINA SINGAPORE + 65 6562 8250 UNITED KINGDOM Hampshire + 44 1256 744 610 Beijing + 86 10 6580 1690 Shanghai + 86 21 6105 5100 TAIWAN Shenzhen + 86 755 8384 9733 Hong Kong + 852 2403 4011 Taipei + 886 2 2657 9800 ext.#100 website: www.ovt.com

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