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H61主板原理图

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    5 4 3 2 1 Model V1.0 D Name:BLIZZARD D 01 COVER SHEET 26 MODULE_ESATA/PATA 02 CHANGE HISTORY 27 MODULE_SSD 03 BLOCK DIAGRAM 28 MODULE_BLUETOOTH 04 CLOCK MAP 29 MODULE_DDR3 CHANNEL A 05 RESET MAP 30 MODULE_DDR3 CHANNEL B 06 GPIO MAP 31 SANDY BRIDGE-1(MISC) 07 POWER MAP 32 SANDY BRIDGE-2(PEGDMIFDI) 08 POWER SEQUENCE 33 SANDY BRIDGE-3(MEMORY) C 09 MECHANIC 34 SANDY BRIDGE-4(POWER) C 10 BLANK 35 SANDY BRIDGE-5(GND) 11 MODULE_CLOCK 36 COUGAR POINT-1(PCI) 12 MODULE_SIO 37 COUGAR POINT-2(DMIUSBPCIE) 13 MODULE_PS/2 38 COUGAR POINT-3(SATA) 14 MODULE_FAN 39 COUGAR POINT-4(GPIO) 15 MODULE_FRONT PANEL 40 COUGAR POINT-5(NVRAM) 16 MODULE_HALO 41 COUGAR POINT-6(DISPLAY) 17 MODULE_ATX POWER 42 COUGAR POINT-7(FDI) B 18 MODULE_PCIE 43 COUGAR POINT-8(CLOCK) B 19 MODULE_PCI 44 COUGAR POINT-9(POWER) 20 MODULE_SPI 45 COUGAR POINT-10(GND) 21 MODULE_VGA/HDMI 46 VR_VCORE 22 MODULE_SATA 47 VR_VAXG 23 MODULE_USB 48 VR_VTT 24 MODULE_LAN 49 VR_DDR 25 MODULE_AUDIO 50 VR_DISCRETE A A ShenZhen Topstar Inductor Co.,Ltd Page Name COVER SHEET Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet Rev 1.0 1 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 Model D VN1.0ame:BLIZZARD DATE Change Item Reason C B A 5 4 3 2 1 D C B A ShenZhen Topstar Inductor Co.,Ltd Page Name CHANGE HISTORY Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet Rev 1.0 2 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 2 1 5 D C B A 5 4 BLOCK DIAGRAM VR12 VGA/HDMI AUDIO USB PORTS 10 SERIAL ATA 4 LPT 4 3 2 Model Name:BLIZZARD LGA1155 CHA DIMM1 CHB DIMM2 PCI EXPRESS X16 FDI DMI PCH LPC SIO PCI EXPRESS X1 PCI EXPRESS X1 PCIE LAN TPM SPI BIOS PS2 FRONT PANEL FAN CONTROL 3 2 1 D C B A ShenZhen Topstar Inductor Co.,Ltd Page Name BLOCK DISGRAM Size Project Name D F-H61 Rev 1.0 Date: Friday, March 15, 2013 Sheet 3 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 1 5 D 4 3 Processor TS_DBG 2 CHA CHB DMI DMI/BCLK 100MHz FDI C DMI/# DP/# PCH CLKOUT_ITPXDP PEG Gen 2X2 100MHz CPU0/0# CLKOUT_PEG_A:B/# PCIE Graphics Slot SATA 100MHz SRC & SATA/# CLKIN_SATA_P/N PCIE-e Gen 2.0 100MHz B CK505 DOT96/# DOT 96 MHz CLKOUT_SRC7:0/7:0# CLKIN_DOT96_P/N PCIE PCIE-e Gen 2.0 100MHz SRC1/1# CLKOUTPCILOOPBACK CLKIN_DMI_P/N PCI 33MHz loopback REF REF 14.318MHz REFCLK14IN CLKOUTPCI_4:0 SIO_48MHz 14/33/48/MHz X4 CLKOUTFLEX[3:0] SIO EC/TPM/etc A 14.31818MHz 25.000MHz 5 4 3 2 1 D C B A ShenZhen Topstar Inductor Co.,Ltd Page Name CLOCK MAP Size Project Name D F-H61 Rev 1.0 Date: Friday, March 15, 2013 Sheet 4 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 1 5 4 3 2 1 D Processor D RSTIN# BUFFER IDE ATX C PWRGD_PS PWROK Logic FWH C PCH PCIE SIO PLTRST# B FRONTPANEL PWRBTN# PWRON B SYS_RESET# PCIRST# A 5 PCI 4 ShenZhen Topstar Inductor Co.,Ltd Page Name RESET MAP Size Project Name A F-H61 Rev A 1.0 Date: Friday, March 15, 2013 Sheet 5 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3 2 1 5 4 3 2 1 D D GPIO TYPE TOLERANCE POWER WELL DEFAULT BLINK USAGE GPIO TYPE TOLERANCE POWER WELL DEFAULT BLINK USAGE GPIO0 I/O 3.3V VCC3 GPI YES AC_DET GPIO36 I/O 3.3V VCC3 GPI NO SPIEN GPIO1 I/O 3.3V VCC3 GPI YES NO GPIO37 I/O 3.3V VCC3 GPI NO NO GPIO2 I/O 5V VCC3 GPI YES PCI_INTE- GPIO38 I/O 3.3V VCC3 GPI NO GP38_MFG_MODE_N GPIO3 I/O 5V VCC3 GPI YES PCI_INTF- GPIO39 I/O 3.3V VCC3 GPI NO NO GPIO4 I/O 5V VCC3 GPI YES PCI_INTG- GPIO40 I/O 3.3V SB3V Native NO -USBOC1 GPIO5 I/O 5V VCC3 GPI YES PCI_INTH- GPIO41 I/O 3.3V SB3V Native NO -USBOC2 GPIO6 I/O 3.3V VCC3 GPI YES NO GPIO42 I/O 3.3V SB3V Native NO -USBOC3 GPIO7 I/O 3.3V VCC3 GPI YES NO GPIO43 I/O 3.3V SB3V Native NO -USBOC4 GPIO8 I/O 3.3V SB3V GPO YES IGC_EN_N GPIO44 I/O 3.3V SB3V Native NO NO GPIO9 I/O 3.3V SB3V Native YES -USBOC5 GPIO45 I/O 3.3V SB3V Native NO NO GPIO10 I/O 3.3V SB3V Native YES -USBOC6 GPIO46 I/O 3.3V SB3V Native NO NO GPIO11 I/O 3.3V SB3V Native YES NO GPIO47 I/O 3.3V SB3V Native NO NO GPIO12 I/O 3.3V SB3V GPI YES LAN_DISABLE_N GPIO48 I/O 3.3V VCC3 GPI NO NO GPIO13 I/O 3.3V SB3V GPI YES IO_PME_N GPIO49 I/O 3.3V VCC3 GPI NO NO C GPIO14 I/O 3.3V SB3V Native YES NO GPIO50 I/O 5V VCC3 Native NO P_REQ1- C GPIO15 I/O 3.3V SB3V GPO YES NO/STRAP GPIO51 I/O 3.3V VCC3 Native NO P_GNT1- GPIO16 I/O 3.3V VCC3 GPI YES H_SKTOCC_N GPIO52 I/O 5V VCC3 Native NO P_REQ2- GPIO17 I/O 3.3V VCC3 GPI YES NO GPIO53 I/O 3.3V VCC3 Native NO P_GNT2- GPIO18 I/O 3.3V VCC3 Native YES NO GPIO54 I/O 5V VCC3 Native NO P_REQ3- GPIO19 I/O 3.3V VCC3 GPI YES NO GPIO55 I/O 3.3V VCC3 Native NO P_GNT3- GPIO20 I/O 3.3V VCC3 Native YES NO GPIO56 I/O 3.3V SB3V Native NO NO GPIO21 I/O 3.3V VCC3 GPI YES NO GPIO57 I/O 3.3V SB3V GPI NO NO GPIO22 I/O 3.3V VCC3 GPI YES PCH_CONFIG GPIO58 I/O 3.3V SB3V Native NO NO GPIO23 I/O 3.3V VCC3 Native YES NO GPIO59 I/O 3.3V SB3V Native NO -USBOC0 GPIO24 I/O 3.3V SB3V GPO YES NO GPIO60 I/O 3.3V SB3V Native NO NO GPIO25 I/O 3.3V SB3V Native YES 1_WATT_CTRL_1 GPIO61 I/O 3.3V SB3V Native NO L_LPCPD_N GPIO26 I/O 3.3V SB3V Native YES NO GPIO62 I/O 3.3V SB3V Native NO NO GPIO27 I/O 3.3V SB3V GPO YES PWR_LED_N GPIO63 I/O 3.3V SB3V Native NO NO GPIO28 I/O 3.3V SB3V GPO YES NO GPIO64 I/O 3.3V VCC3 Native NO NO GPIO29 I/O 3.3V SB3V GPO YES SLP_LAN_N GPIO65 I/O 3.3V VCC3 Native NO NO GPIO30 I/O 3.3V SB3V GPO YES SUS_PWR_ACK GPIO66 I/O 3.3V VCC3 Native NO NO GPIO31 I/O 3.3V VCC3 GPO YES NO GPIO67 I/O 3.3V VCC3 Native NO NO GPIO32 I/O 3.3V VCC3 GPO NO PCH_THRM_UP GPIO72 I/O 3.3V SB3V Native NO 1_WATT_CTRL_2 B GPIO33 I/O 3.3V VCC3 GPO NO NO GPIO73 I/O 3.3V SB3V Native NO NO B GPIO34 I/O 3.3V VCC3 GPO NO NO GPIO74 I/O 3.3V SB3V Native NO NO GPIO35 I/O 3.3V VCC3 GPO NO NO GPIO75 I/O 3.3V SB3V Native NO NO A A ShenZhen Topstar Inductor Co.,Ltd Page Name GPIO MAP Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet Rev 1.0 6 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 ATX P/S D CPU 2X2 +12VIN +5V PSU 2X12 +5V_SB +3D3V +12V -12V C CPU VCORE 100A ISL6334 4PH V_1P1_VTT 35A RT9214 V_AXG 20A ISL6314 +5V_SB -12V +3D3V +5V +12V +12VIN 5VDUAL 3VDUAL VCORE DDRVSM DDRVTT V_1P8_SFR V_CPU_VCCIO V_1P05_PCH V_1P05_ME VCCRTC DDRVSM 1.5V 25A +5V RT9214 1.5V B +5V_SB +5V 5VDUAL 3VDUAL 1.5A L1084 +3D3V V_1P8_SFR 2A Liner 1.8V A V_1P05V_PCH 7.5A Linear 1.05V DDRVTT 2A RT9173 0.9V 5 4 3 2 1 D CPU C PCH B DIMM A ShenZhen Topstar Inductor Co.,Ltd Page Name POWER MAP Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet Rev 1.0 7 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 1 5 D 4 3 2 1 & SLP_S3# SLP_S3# EN_VTT D VCCIO_PG EN 1.05V_PCH V_CPU 5V VCCIO 12V 12V EN V_SA LINER 5V VCC VAGX SLP_S4# EN VR V_SM VCCIO DIMM C 5VDUAL Processor C V_SM 12V RSTIN# BUFFER IDE SM_DRAMPWRGOODUNCOREPWROK FWH PCIE DRAMPWROK PROCPWOK PLTRST# SLP_S3# SLP_S3# SIO SUSB# LINER SLP_S3# EN PCH SLP_S4# PWRBTN# SLP_S4# PWRBTN# SUSC# PWRON B B 12V 1.05_PCH PCIRST# SYS_RESET# FRONTPANEL PANSWH V_SM PWROK APWROK RSMRST# DPRWOK RSMRST# RSMRST# PSON# FOR NOT SUPORT DEEP S4/S5 FOR NONE AMT PCH_PWROK 3.3VDUAL A 5 & PWRGD3_V SLP_S3# ATX A PWRGD_PS PWRGD_PS PSON PSON# ShenZhen Topstar Inductor Co.,Ltd Page Name POWER SEQUENCE Size Project Name Custom F-H61 Rev 1.0 Date: Friday, March 15, 2013 Sheet 8 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 4 3 2 1 5 4 3 2 NB HEATSINK PCB SPB(NB) JIAOTIAO D FD1 FD2 HEATSINK SPB 1 K1_ICT/X 1& 1 K1_ICT/X 1& JIAOTIAO PCB MH1 1 18 2 17 3 NEW SYMBOL 16 4 15 5 2007.11.30 14 6 13 1& MH2 1 18 2 17 3 NEW SYMBOL 16 4 15 5 2007.11.30 14 6 13 1& MH3 1 18 2 17 3 NEW SYMBOL 16 4 15 5 2007.11.30 14 6 13 1& 12 11 10 9 8 7 7 8 9 10 11 12 12 11 10 9 8 7 C MH4 1 18 2 17 3 NEW SYMBOL 16 4 15 5 2007.11.30 14 6 13 1& MH5 1 18 2 17 3 NEW SYMBOL 16 4 15 5 2007.11.30 14 6 13 1& 12 11 10 9 8 7 12 11 10 9 8 7 B 1 D C B ShenZhen Topstar Inductor Co.,Ltd A A Page Name MECHANIC Size B Project Name F-H61 Rev 1.0 Date: Friday, March 15, 2013 Sheet 9 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 D D C C B B ShenZhen Topstar Inductor Co.,Ltd Page Name BLACK A Size Project Name Rev A A F-H61 1.0 Date: Friday, March 15, 2013 Sheet 10 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 BSEL BIASING RESISTORS D FSA CPU 0 266MHz 1 133MHz GSEL 1 (PULL HIGH) Pin3/4 is DOT96 0 (PULL LOW) Pin3/4 is PCIE0 C BSEL[2:0] CPU 101 100MHz 001 133MHz D 011 166MHz 010 200MHz 000 266MHz 100 333MHz 110 400MHz 111 Reserve C B B A A Title BLIZZARD Size Document Number A Rev 1.0 Date: Friday, March 15, 2013 Sheet 11 of 50 5 4 3 2 1 5 4 3 2 1 POWER 3VDUAL SC1 SC2 0805 0402 4.7UF/10V 0.1UF/16V +3D3V SC3 0805 4.7UF/10V SC4 0402 0.1UF/16V D SIO_AVCC3 D +3D3V 0402 SR1 330-5% 3 D SQ6 2N7002 G 1SIO_PSON# S G SFB10603 60OHM/100MHz/650mA 1 SC5 SC6 0603 1206 Note: 1UF/16V 10UF/10VPlace SC5,SC6 close to SIO VCORE V_CPU_VCCIO +12V +5V DDRVSM +5V_SB 2 SOT23 0402 0402 0402 0402 0402 0402 SR2 SR3 SR4 SR5 SR6 SR7 3VDUAL SR8 10 4&0 2 2.2K-5% SR9 0 4 0 2 10K-5% SR10 0 4 0 2 10K-5% 5VSB_CTL# PWRON# RSMRST_N_SIO <27> RTS1# <27> DSR1# <27> SOUT1 <27> SIN1 <27> DTR1# <27> DCD1# <27> RI1# <27> CTS1# RTS1#/JP2 DSR1# SOUT1/JP3 SIN1 DTR1#/JP4 DCD1# RI1# CTS1# PCH_C PCH_D VIN0 VIN1 VIN2 VIN3 VIN0 VIN1 VIN2 VIN3 VIN4 10K-1% 10K-1% 10K-1% 15K-1% 10K-1% 10K-1% NC 0402 0402 SR11 0 4 0 2 10K-5% PWR_LED_N SC7 SC8 SR12 SR13 SC9 0402 VIN3(+5V_SEN) VIN2(+12V_SEN) 49 VIN1/VDIMM_STR(1.5V) 50 VIN0/VCORE(1.1V) 51 AVCC3 52 GNDD 53 VLDT_EN/PCH_D/GP65 54 26 SUSWARN#/SST/AMDTSI_D VCORE_EN/PCH_C/FAN_CTRL4 55 RTS1#/JP2 56 DSR1#/GP45 57 SOUT1/JP3 58 SIN1/GP41 59 DTR1#/JP4 60 DCD1#/GP33 61 RI1#/GP32 62 CTS1#/GP31 63 SR14N0 4C0 2 10K-5% RI1# 64 SU1 SIOVREF Note: SIOVREF 0402 0402 0.1UF/16V 0.1UF/16V 2K-1% 10K-1%0402 0.1UF/16V SR16 20K-5% NC 64-LQFP SC10 Place C3 close to SIO, and Do 0603 Not remove this 1uF Cap. of +3D3V 1UF/16VVREF. SR15 0 4 0 2 2.2K-5% SR18 0 4 0 2 2.2K-5% SR21 0 4 0 2 1K-5% PWRGD1 PWRGD3 PCIRST3 C <39> SML1CLK_PCH SR26N0 4C0 2 0-5% PCH_C <14> CPUFAN_TAC <14> CPUFAN_CTL <14> SYSFAN_TAC <17> PWRGD_PS 3VDUAL CPUFAN_TAC CPUFAN_CTL SYSFAN_TAC GP36 5VSB_CTL# SR19 0 4 0 2 0-5% ATXPG GP23 GP22 PWRGD1 GP12 SC13 SC14 0805 0402 SC11 SC12 1& 4.7UF/10V0.1UF/16V 0402 0603 0.1UF/16V 2.2UF/6.3V 1 2 FAN_TAC2/GP52 3 FAN_CTL2/GP51 4 FAN_TAC3/GP37 5 FAN_CTL3/GP36 6 5VSB_CTL# 7 ATXPG/GP30 8 DPWROK/CPU_PG/GP23 IT8772 9 GP22 10 SUSACK#/PWRGD1 11 PCIRST1#/GP12 12 3VSB 13 VCORE 14 LRESET# 15 SERIRQ 16 LFRAME# LAD0 48 5VDUAL/VLDT_12/VIN4 47 VREF 46 TMPIN1 45 TMPIN2 44 GNDA/TSD- 43 RSMRST#/CIRRX1/GP55 42 PCIRST3#/GP10 41 MCLK/GP56 40 MDAT/GP57 39 KCLK/GP60 38 KDAT/GP61 37 3VSBSW#/GP40 36 PWRGD3 35 SUSC#/GP53 34 PSON#/GP42 33 PANSWH#/GP43 VIN4 TMPIN1 GNDA PCIRST3 PWRGD3 PSON# A RSMRST_N_SIO SR20 0 4 0 2 33-5% SIO_MCLK <13> SIO_MDAT <13> SIO_KCLK <13> SIO_KDAT <13> SR22 0 4 0 2 33-5% SIO_LPC_SMI <39> SR4210 4&0 2 0-5% SR23 0 4 0 2 33-5% SR25 0 4 0 2 33-5% SR17 0 4 0 2 0-5% RSMRST_N_SIO <16> -PCIE_RST <16,18,24> PWRGD_3V <38,39> SLP_S4_N <39,49> SIO_PSON# <17> PANSWH# <15> SFB20603 60OHM/100MHz/650mA 1 DVT:ADD SFB2 Hardware monitor TMPIN1 SR24 0 4 0 2 10K-1% SIOVREF 1 C SC19 Note:Don't remove SC15 SRT1 PME#/GP54 32 PWRON#/GP44 31 SUSB# 30 VBAT 29 COPEN# 28 SYS_3VSB 27 PECI/AMDTSI_C 25 CLKIN 24 GPO50/JP1 23 PCICLK 22 GA20 21 KRST#/GP62 20 LAD3 19 LAD2 18 LAD1 <39> SML1DATA_PCH SR27N0 4C0 2 0-5% PCH_D 0603 Pin 33 Damping 1UF/16V resister. 0402 0.1UF/16V 10K-5% t <15> PWR_LED_N <15> BEEP- SR28 0 4 0 2 0-5% SR29N0 4C0 2 0-5% SR30 0 4 0 2 0-5% SR31N0 4C0 2 0-5% GP22 GP36 GP12 GP23 <16,39> PLTRST_N <38> SER_IRQ <39> L_FRAME_N <39> L_AD0 <39> L_AD1 <39> L_AD2 <39> L_AD3 <38> KBRST_N <38> A20GATE <43> CK_PCH_33M_SIO PLTRST_N SER_IRQ L_FRAME_N L_AD0 L_AD1 L_AD2 L_AD3 KBRST_N A20GATE CK_PCH_33M_SIO JP1 17 SYS_3VSB 0603 PME PULL UP NEAR CHIPSET IO_PME_N PWRON# SLP_S3_N IO_PME_N <39> SW_ON_N <39> SIO_VBAT SLP_S3_N <16,17,39,50> NC SR32 0 4 0 2 1M-5% SR33 0 4 0 2 1K-5% SC18 1UF/16V SIO_VBAT 3VDUAL SC16 SC17 0805 0603 4.7UF/10V 1UF/16V 2 placed near SIO Tantalum cap. <43> CK_PCH_48M_SIO CK_PCH_48M_SIO SR34 0 4 0 2 100-5% (Spare for battery installation glitch) Place SC17 close to Layout Note: (24MHz or 48MHz) PECI 0-5% 0 4 0 2 SR35 SIO as possible H_PECI <31,38> *Recommended net "VBAT" minimum trace width 12mils. *Isolated the SIO's VBAT & ICH's VCCRTC pin Power-On Strapping Symbol Value Description JP1 DSW_EUP_SEL 1 EUP(default) If without use these pins, Please pull-up. Don't let it floating Pin-23 JP2 Pin-57 WDT_EN 0 DSW 1 Disable WDT to reset PWROK(default) 0 Enable WDT to reset PWROK 1.Pin 6:ATXPG 2.Pin 30:SUSB# JP3 FAN_CTL_SEL 1 EC Index 6Bh/73h default = 80h 3.Pin Pin 23 / Pin 57/ Pin 59/ Pin61 B Pin-59 0 EC Index 6Bh/73h default = 00h 4.Pin38-41 KCLK/KDAT/MCLK/MDAT B JP4 Pin-61 K8PWR_EN 1 Disable K8 Power Sequence(default) 0 Enable K8 Power Sequence 5.Pin 63 pull high to 3VSB 3VDUAL SSSRRR433379NNN000 444CCC000 222 680-5% 680-5% 680-5% JP1 RTS1#/JP2 SOUT1/JP3 DTR1#/JP4 SR36 0 4 0 2 1K-5% SR38 0 4 0 2 8.2K-5% SR40 0 4 0 2 8.2K-5% SR41 0 4 0 2 8.2K-5% Note: If 75232 is connected, please use 680 ohm to be the pull down resistor value. Since powered by 12V, 75232 has a very strong internal pull-up. It is hard to be pulled low. (Please see specification for detail of power on strapping setting) A A ShenZhen Topstar Inductor Co.,Ltd Page Name SUPER IO_8718 Size Custom Project Name F-H61 Date: Friday, March 15, 2013 Sheet 12 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 JKB(1-2) YELLOW D D +5V_SB +5V USE 15-20-MIL TRACE ON KB/MOUSE POWER PS/2 PORT JKB 1 2 3 FB2 0805 100OHM/100MHz/1.5A 1 KEYBRD_PWR RN1 8 6 4 2 470PF/50V 0402 C4 0402 0.1UF/16V C5 0603 0603 0603 0603 PS/2 KEYBRD_PWR 1 3 5 7 <12> SIO_KDAT 8.2K-5% FB3 0603 60OHM/100MHz/650mA 1 SIO_KBDATA_FB PS2/P/2/W_SHIELD PS/2 C SIO_MSDATA_FB 7 10 C <12> SIO_KCLK FB4 0603 60OHM/100MHz/650mA 1 SIO_KBCLOCK_FB 8 SIO_MSCLOCK_FB 11 12 MS 9 <12> SIO_MDAT FB5 0603 60OHM/100MHz/650mA 1 SIO_MSDATA_FB SIO_KBDATA_FB 1 2 SIO_KBCLOCK_FB 5 6 4 KB 3 13 14 15 16 17 <12> SIO_MCLK FB6 0603 60OHM/100MHz/650mA 1 SIO_MSCLOCK_FB C7 C8 C9 C10 0402 0402 0402 0402 B B 220PF/50V220PF/50V220PF/50V220PF/50V ShenZhen Topstar Inductor Co.,Ltd A A Page Name PS/2 Size B Project Name F-H61 Date: Friday, March 15, 2013 Sheet 13 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 +5V D D R5 4.7K-5% +12V <12> CPUFAN_CTL R6 0 4 0 2 100-5% 0402 0402 0402 1 4321 CPU_FAN D1 R7 4.7K-5% 4 C Control 1N4148 C SENSE 3 R8 0 4 0 2 27K-5% CPUFAN_TAC <12> 2 +12V GND 1 CPU_FAN_1X4 C11 C22 0402 1206 0.1UF/16V 4.7uF/16V R9 10K-5% CPU FAN B <12> SYSFAN_TAC A 5 0402 0402 +12V B R11 0402 R10 10K-5% 15K-5% R12 0402 C12 5.1K-5% 0.047uF/50V NC 0402 C13 0.1UF/16V 4 SYS_FAN 3 DET 2 VCC 1 GND FAN ShenZhen Topstar Inductor Co.,Ltd SYS FAN Page Name FAN Size Project Name A F-H61 Rev A 1.0 Date: Friday, March 15, 2013 Sheet 14 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3 2 1 5 4 3 2 D <12> BEEP- 3 2 SOT23 0402 SOT23 0402 0402 +3D3V +3D3V R484 R486 R61510 4&0 2 0-5% 4.7K-5% 0402 1G R485 1K-5% G 4.7K-5% D Q39 S 2N7002 <39> SPKR +3D3V BUZZER +5V +5V R14 NC 1K-5% 0402 R17 1K-5% 0402 R18 1K-5% 0402 R15 10K-5% D2 1 3 2 BAT54C 3 2 SOT23 R16 0 4 0 2 10-5% C Q1 1B B E 0402 C14 FHS3904-ME 0.1UF/16V SPEAK JSPEAKER 1 2 3 4 1X4 1 D C C 3VDUAL +5V +5V TO BE SURE: R21 R20 R22 INTEL FRONT PANEL 0402 0402 0402 PH TO 3D3 OR 3VDUAL 330-5% 330-5% 4.7K-5% F_PANEL 1 2 HDD_LED_F 3 4 PWRLED- <31,39> FP_RST_N R23 0 4 0 2 33-5% -RESET 5 6 7 8 9 -PWRBTSW C17 C18 R24 2X5 0402 0402 0402 300-5% B 0.1uF/1467V0PF/50V B <38> PCH_SATA_LED_N D3 1 1N4148 HDD_LED_F A <12> PANSWH# 5 3VDUAL R27 4.7K-5% R31 33-5% -PWRBTSW 0402 0402 C19 0.1UF/16V 0402 C20 470PF/50V 4 0402 0402 <12> PWR_LED_N +5V R25 330-5% R28 N0 C4 0 2 330-5% PWRLED- 3 2 SOT23 C Q2 R30 0 4 0 2 1K-5% 1B B E FHS3904-ME ShenZhen Topstar Inductor Co.,Ltd A Page Name FRONT PANEL Size Project Name Custom F-H61 Date: Friday, March 15, 2013 Sheet 15 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3 2 1 5 4 3 2 1 3VDUAL D D CAD NOTE: PLACE NEAR CPU 3VDUAL V_CPU_VCCIO R48 100-1% 0402 R32 10K-5% 0402 0402 R49 1K-1% H_CPURST_N 3 2 SOT23 3 2 SOT23 C Q11 PLTRST_RN50 0 4 0 2 4.7K-5% 1 C23 1B B C Q12 B B E FHS3904-ME E FHS3904-ME NC0402 1UF/6.3V H_CPURST_N <31> 3 2 SOT23 <12,17,39,50> SLP_S3_N R39 0 4 0 2 10K-5% 1 C Q4 B B E FHS3904-ME R40 0 4 0 2 100-5% C Q5 R41 0 4 0 2 1K-51% B B E FHS3904-ME VR_READY <46> 3 2 SOT23 C C EN_VTT <46> C Q9 R45 0 4 0 2 1K-51% B B E FHS3904-ME C21 0603 2.2UF/6.3V 3 2 SOT23 3VDUAL PCH_DPWROK <39> R79 1& 0402 0402 0402 3VDUAL 3VDUAL 1K-1% 3 2 SOT23 3 2 SOT23 B R80 -PCIE_RST <12,18,24> B R72 0 4 0 2 0-5% PCH_RSMRST_N <39> R69 1& 4.7K-5% 1& Stuff for DEEP S4/S5 NOT SUPPORT 4.7K-5% 1& C Q17 1B DavidWang: <12,39> PLTRST_N R82 10 4&0 2 2.2K-5% 1& C Q18 1B B E FHS3904-ME <12> RSMRST_N_SIO 0-5% 0 4 0 2 R66 20110224 DVT FIX POWER ON ISSUE B E FHS3904-ME 1& 0603 C29 1UF/16V 0402 NC R73 100K-5% 3VDUAL A 5 <46> VR_READY 0402 R88 10K-5% R90 0 4 0 2 0-5% NC PCH_SYSPWROK <39> ShenZhen Topstar Inductor Co.,Ltd A Page Name POWER SEQUENCE 0402 R94 C32 10K-5% 0805 22uF/6.3V NC NC Size B Project Name F-H61 Date: Friday, March 15, 2013 Sheet 16 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 4 3 2 1 5 4 3 2 1 DavidWang: 20110224 DVT VR8 NOT NC D D +5V_SB PD1 NC 1N4148 1 0402 PR3 22K-5% ATX POWER CONNECTOR -12V +3D3V ATXPWR 13 1 3.3V 3.3V 14 -12V 3.3V 2 15 3 GND GND +3D3V 0603 PC1 1UF/16V 0402 +5V PR1 8.2K-5% <12> SIO_PSON# PR2 0 4 0 2 33-5% 16 PSON 5V 4 +5V 3 2 SOT23 NC C PQ1 0603 PC2 17 5 GND GND <12,16,39,50> SLP_S3_N PR4 N0 C4 0 2 4.7K-5% 1B 1UF/16V 18 6 GND 5V +5V B E 3904 19 7 GND GND C 20 8 -5V POK PWRGD_PS <12> C +5V 21 9 5V 5VSB +5V_SB +5V 22 5V 10 12V +12V 0603 PC3 0603 PC4 1UF/16V 1UF/16V 0603 PC5 1UF/16V 23 5V 11 12V 24 GND 3.3V 12 +3D3V 0603 PC6 0603 PC7 1UF/16V 1UF/16V PC8 PC9 0402 0402 0.1UF/16V 470PF/50V 0603 PC10 1UF/16V PC11 0402 470PF/50V ATX-POWET-SOCKET 2*12 VCORE PC13 +5V +3D3V +5V_SB 3VDUAL +12VIN 0402 B 0.1UF/16V + CE17 C40 C42 ATX12V B DVT ADD EMI 电容 8*12 1000uF/6.3V 0805 10UF/6.3V 0805 10UF/6.3V R37 2 GND2 12V2 4 1K-5% 1 3 GND1 12V1 PC75 0402 1 LED_POWER ATX12V 2X2P 0.1UF/16V 0805 PC12 4.7UF/10V +5V BL-HB335A-TRB 0402 0805 2 ShenZhen Topstar Inductor Co.,Ltd A A Page Name ATX POWER +3D3V Size B Project Name F-H61 Date: Friday, March 15, 2013 Sheet 17 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3VDUAL +3D3V +12V <29,30,39> SMB_CLK_MAIN <29,30,39> SMB_DATA_MAIN D <24,39> WAKE_N <32> EXP_A_TX_0_DP <32> EXP_A_TX_0_DN C39 0.1UF/16V C41 0.1UF/16V 04020402 <32> EXP_A_TX_1_DP <32> EXP_A_TX_1_DN <32> EXP_A_TX_2_DP <32> EXP_A_TX_2_DN <32> EXP_A_TX_3_DP <32> EXP_A_TX_3_DN 04020402 C43 0.1UF/16V C45 0.1UF/16V 04020402 C48 0.1UF/16V C49 0.1UF/16V C51 0.1UF/16V C53 0.1UF/16V 04020402 <32> EXP_A_TX_4_DP <32> EXP_A_TX_4_DN C <32> EXP_A_TX_5_DP <32> EXP_A_TX_5_DN <32> EXP_A_TX_6_DP <32> EXP_A_TX_6_DN <32> EXP_A_TX_7_DP <32> EXP_A_TX_7_DN 04020402 C55 0.1UF/16V C57 0.1UF/16V 04020402 C59 0.1UF/16V C61 0.1UF/16V 04020402 C63 0.1UF/16V C65 0.1UF/16V C68 0.1UF/16V C69 0.1UF/16V 04020402 <32> EXP_A_TX_8_DP <32> EXP_A_TX_8_DN <32> EXP_A_TX_9_DP <32> EXP_A_TX_9_DN <32> EXP_A_TX_10_DP <32> EXP_A_TX_10_DN <32> EXP_A_TX_11_DP <32> EXP_A_TX_11_DN <32> EXP_A_TX_12_DP B <32> EXP_A_TX_12_DN <32> EXP_A_TX_13_DP <32> EXP_A_TX_13_DN <32> EXP_A_TX_14_DP <32> EXP_A_TX_14_DN <32> EXP_A_TX_15_DP <32> EXP_A_TX_15_DN 04020402 C71 0.1UF/16V C72 0.1UF/16V 04020402 C73 0.1UF/16V C74 0.1UF/16V 04020402 C75 0.1UF/16V C76 0.1UF/16V 04020402 C77 0.1UF/16V C78 0.1UF/16V 04020402 C79 0.1UF/16V C80 0.1UF/16V 04020402 C81 0.1UF/16V C82 0.1UF/16V 04020402 C83 0.1UF/16V C84 0.1UF/16V C85 0.1UF/16V C86 0.1UF/16V 04020402 All AC Coupling caps. should be placed within 250 mils of the connector PCIE_16X1 B1 B2 12V_1(P) B3 12V_2(P) B4 12V_3(P) B5 GND_1(P) B6 SMCLK(B) B7 SMDAT(B) B8 GND_2(P) B9 3_3V_1(P) B10 JTAG1(B) B11 3_3VAUX(I) WAKE*(B) A1 PRSNT1#(B) A2 12V_4(P) A3 12V_5(P) A4 GND_3(P) A5 JTAG2(B) A6 JTAG3(B) A7 JTAG4(B) A8 JTAG5(B) A9 3_3V_2(P) A10 3_3V_3(P) PERST# A11 KEY B12 B13 RSVD_1(B) B14 GND_4(P) B15 HSOP0(I) B16 HSON0(I) B17 GND_5(P) B18 PRSNT2#_1(I) GND_6(P) A12 GND_7(P) A13 REFCLK+(I) A14 REFCLK-(I) A15 GND_8(P) A16 HSIP0(O) A17 HSIN0(O) A18 GND_9(P) B19 B20 HSOP1(I) B21 HSON1(I) B22 GND_10(P) B23 GND_11(P) B24 HSOP2(I) B25 HSON2(I) B26 GND_12(P) B27 GND_13(P) B28 HSOP3(I) B29 HSON3(I) B30 GND_14(P) B31 RSVD_2(B) B32 PRSNT2#_2(I) GND_15(P) A19 RSVD_3(B) A20 GND_16(P) A21 HSIP1(O) A22 HSIN1(O) A23 GND_17(P) A24 GND_18(P) A25 HSIP2(O) A26 HSIN2(O) A27 GND_19(P) A28 GND_20(P) A29 HSIP3(O) A30 HSIN3(O) A31 GND_21(P) A32 RSVD_4(B) B33 B34 B35 HSOP4(I) HSON4(I) B36 GND_22(P) B37 GND_23(P) B38 HSOP5(I) B39 HSON5(I) B40 GND_24(P) B41 GND_25(P) B42 HSOP6(I) B43 HSON6(I) B44 GND_26(P) B45 GND_27(P) B46 HSOP7(I) B47 HSON7(I) B48 GND_28(P) B49 PRSNT2#_3(B) GND_29(P) A33 RSVD_5(B) GND_30(P) A34 A35 HSIP4(O) A36 HSIN4(O) A37 GND_31(P) A38 GND_32(P) A39 HSIP5(O) A40 HSIN5(O) A41 GND_33(P) A42 GND_34(P) A43 HSIP6(O) A44 HSIN6(O) A45 GND_35(P) A46 GND_36(P) A47 HSIP7(O) A48 HSIN7(O) A49 GND_37(P) B50 B51 HSOP8(I) B52 HSON8(I) B53 B54 GND_38(P) GND_39(P) B55 HSOP9(I) B56 HSON9(I) B57 GND_40(P) B58 GND_41(P) B59 HSOP10(I) B60 HSON10(I) B61 GND_42(P) B62 GND_43(P) B63 HSOP11(I) B64 HSON11(I) B65 GND_44(P) B66 GND_45(P) B67 HSOP12(I) B68 HSON12(I) B69 GND_46(P) B70 GND_47(P) B71 HSOP13(I) B72 B73 HSON13(I) GND_48(P) B74 GND_49(P) B75 HSOP14(I) B76 HSON14(I) B77 GND_50(P) B78 GND_51(P) B79 HSOP15(I) B80 HSON15(I) B81 GND_52(P) B82 PRSNT2#_4(I) RSVD_6(I) RSVD_7(B) A50 A51 GND_53(P) A52 HSIP8(O) HSIN8(O) A53 A54 GND_54(P) A55 GND_55(P) A56 HSIP9(O) A57 HSIN9(O) A58 GND_56(P) A59 GND_57(P) A60 HSIP10(O) A61 HSIN10(O) A62 GND_58(P) A63 GND_59(P) A64 HSIP11(O) A65 HSIN11(O) A66 GND_60(P) A67 GND_61(P) A68 HSIP12(O) A69 HSIN12(O) A70 GND_62(P) A71 GND_63(P) HSIP13(O) A72 A73 HSIN13(O) A74 GND_64(P) A75 GND_65(P) A76 HSIP14(O) A77 HSIN14(O) A78 GND_66(P) A79 GND_67(P) A80 HSIP15(O) A81 HSIN15(O) A82 GND_68(P) PCIE164 +3D3V +12V 3 -PCIE_RST <12,16,24> CK_PE_16PORT_PCH_DP <43> CK_PE_16PORT_PCH_DN <43> EXP_A_RX_0_DP <32> EXP_A_RX_0_DN <32> EXP_A_RX_1_DP <32> EXP_A_RX_1_DN <32> EXP_A_RX_2_DP <32> EXP_A_RX_2_DN <32> EXP_A_RX_3_DP <32> EXP_A_RX_3_DN <32> EXP_A_RX_4_DP <32> EXP_A_RX_4_DN <32> EXP_A_RX_5_DP <32> EXP_A_RX_5_DN <32> EXP_A_RX_6_DP <32> EXP_A_RX_6_DN <32> EXP_A_RX_7_DP <32> EXP_A_RX_7_DN <32> EXP_A_RX_8_DP <32> EXP_A_RX_8_DN <32> EXP_A_RX_9_DP <32> EXP_A_RX_9_DN <32> EXP_A_RX_10_DP <32> EXP_A_RX_10_DN <32> EXP_A_RX_11_DP <32> EXP_A_RX_11_DN <32> EXP_A_RX_12_DP <32> EXP_A_RX_12_DN <32> EXP_A_RX_13_DP <32> EXP_A_RX_13_DN <32> EXP_A_RX_14_DP <32> EXP_A_RX_14_DN <32> EXP_A_RX_15_DP <32> EXP_A_RX_15_DN <32> 2 +12V + CE1 8*12 470uF/16V +12V 3VDUAL +3D3V +3D3V + CE5 8*12 1000uF/6.3V C90 0402 0402 0402 C91 0.1UF/16V 0805 C92 0402 C93 0402 C94 4.7UF/10V 0.1UF/16V 0.1UF/16V 1 D C89 0.1UF/16V 0.1UF/16V PCIE_1X_1 3GIO_X1 <29,30,39> SMB_CLK_MAIN <29,30,39> SMB_DATA_MAIN <24,39> WAKE_N +12V +3D3V 3VDUAL B1 B2 B3 12V 12V B4 RSVD B5 GND B6 SMCLK B7 SMDAT B8 GND B9 3.3V B10 JTAG1 B11 3.3VAUX WAKE* A1 PRSNT1* 12V A2 A3 12V A4 +12V C GND A5 JTAG2 A6 JTAG3 A7 JTAG4 A8 JYAG5 A9 3.3V A10 +3D3V 3.3V A11 PWRGD -PCIE_RST <12,16,24> <37> HSO5_DP <37> HSO5_DN 04020402 C96 0.1UF/16V C97 0.1UF/16V B12 B13 RVSD B14 GND B15 HSOP0 B16 HSON0 B17 GND B18 PRSNT2* GND KEY A12 GND A13 REFCLK+ A14 REFCLK- A15 GND A16 HSIP0 A17 HSIN0 A18 GND CK_PCIE1X_1_DP <43> CK_PCIE1X_1_DN <43> HSI5_DP <37> HSI5_DN <37> PCI-E/1X-36P/BK/OL B A A ShenZhen Topstar Inductor Co.,Ltd Page Name PCIE16X Size Custom Project Name F-H61 Date: Friday, March 15, 2013 Sheet 18 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 D D C C B B ShenZhen Topstar Inductor Co.,Ltd Page Name BLACK A Size Project Name Rev A A F-H61 1.0 Date: Friday, March 15, 2013 Sheet 19 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 D <39> SPI_CS0_FLASH <39> SPI_MISO_FLASH C 4 3 2 1 3VDUAL C100 C101 D 0603 0402 SPI BIOS1 1UF/16V 0.1UF/16V SST25VF080B/[10HP4-172580-01R] SPI_WP- 1 CS# 2 SO 3 WP# 4 VSS 8 VDD HOLD# 7 6 SCK SI 5 SPI_HOLD_N_0 SPI_CLK_FLASH <39> SPI_MOSI_FLASH <39> C B A 5 SPI_MOSI_FLASH SPI_CS0_FLASH SPI_MISO_FLASH SPI_HOLD_N_0 SPI_WP- 3VDUAL R99 0 4 0 2 8.2K-5% R100 0 4 0 2 8.2K-5% R101 0 4 0 2 8.2K-5% R102 0 4 0 2 1K-1% R103 0 4 0 2 1K-1% 4 3 B ShenZhen Topstar Inductor Co.,Ltd Page Name SPI Size Project Name A F-H61 Rev A 1.0 Date: Friday, March 15, 2013 Sheet 20 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 2 1 5 4 3 2 1 <42> VGA_RED <42> VGA_GREEN <42> VGA_BLUE FB7 0603 60OHM/100MHz/650mA FB8 01603 60OHM/100MHz/650mA FB9 10603 60OHM/100MHz/650mA 1 RED_A GREEN_A BLUE_A +5V_CON +5V VGA_DDCSDA_5V R107 0 4 0 2 100-5% DDC_SDA D5 D VGA_DDCSCL_5V R108 0 4 0 2 100-5% DDC_SCL 1 FU2 1 1812 1.6A/8V +5V_CON D BUF_HSYNC_A BUF_VSYNC_A SSM5817 R109 150-1% R110 150-1% R111 150-1% C106 C109 C112 3.3PF/50V 3.3PF/50V 3.3PF/50V C107 C110 C113 3.3PF/50V 3.3PF/50V 3.3PF/50V C105 C108 C111 C114 18PF/50V 18PF/50V 18PF/50V 18PF/50V 0402 C117 0.1UF/16V 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 V_BUFF <42> VGA_HSYNC_3V VGA_HSYNC_3V U5 1 5 2 3 4 C345 0.1UF/16V BUF_HSYNC_A +5V V_BUFF SN74HCT R616 0 6 0 3 0-5% 0-5% N0 4C0 2 R112 V_BUFF +3D3V R617N0 6C0 3 0-5% V_BUFF <42> VGA_VSYNC_3V VGA_VSYNC_3V U6 1 5 2 3 4 0402 C346 0.1UF/16V BUF_VSYNC_A SN74HCT 0-5% N0 4C0 2 R116 VGA 16 16 +3D3V D15 C37 SOT23 0402 6 GND 6 2 +3D3V +5V_CON 0402 RED_A 470PF/50VNCC102 EMICAP1 GREEN_A DDC_SDA 1 11 1 RED 11 GND 7 2 GRN SDA 12 GND 8 RED_A 3 1 BAT54S 0.1UF/16V BLUE_A 3 BLU HSYNC +5V_CON +3D3V BUF_HSYNC_A 13 0402 0402 R411 R410 +3D3V R105 R106 470PF/50VNCC103 EMICAP2 VCC 9 4 VSYNC D16 C46 0402 0402 C 2.2K-1%2.2K-1% 2.2K-5% 2.2K-5% BUF_VSYNC_A 14 C104 2 C 1 DDC_SCL 15 10 GND 10 0402 GREEN_A 3 0.1UF/16V SOT23 D G 2N7002 G Q23 3 VGA_DDCSDA_5V 5 GND 15 SCL 5 0.1UF/16V 1 <42> VGA_PCH_DDCSDA VGA_PCH_DDCSDA2 SOT23 S 17 17 BAT54S +3D3V +3D3V I191 VGACONN DB15_R D17 C47 2 1 0402 SOT23 G 2N7002 <42> VGA_PCH_DDCSCL VGA_PCH_DDCSCL S 2 SOT23 D G Q24 3 VGA_DDCSCL_5V BLUE_A 3 1 BAT54S 0.1UF/16V 04020402 04020402 04020402 04020402 <42> DDSP_D_TX_0_DP <42> DDSP_D_TX_0_DN C116 C115 0.1UF/16V 0.1UF/16V <42> DDSP_D_TX_1_DP <42> DDSP_D_TX_1_DN C118 C119 0.1UF/16V 0.1UF/16V <42> DDSP_D_TX_2_DP C120 0.1UF/16V <42> DDSP_D_TX_2_DN C121 0.1UF/16V B <42> DDSP_D_TX_3_DP <42> DDSP_D_TX_3_DN C122 C123 0.1UF/16V 0.1UF/16V DVI_TX2_DP DVI_TX2_DN DVI_TX1_DP DVI_TX1_DN DVI_TX0_DP DVI_TX0_DN DVI_CLK_DP DVI_CLK_DN 0 4 0 2R618 0 4 0 2R619 0 4 0 2R620 0 4 0 2R621 0 4 0 2R622 0 4 0 2R623 0 4 0 2R624 0 4 0 2R625 680-5% 680-5% 680-5% 680-5% 680-5% 680-5% 680-5% 680-5% 3 2 SOT23 +3D3V R113 0 4 0 2 4.7K-5%1 G G D Q25 2N7002 S +3D3V +3D3V +5V_CON 0402 0402 <42> PCH_I2C_CLK_DVI <42> PCH_I2C_DATA_DVI 0402 R131 2.2K-5% PCH_I2C_CLK_DVI +3D3V R137 2.2K-5% PCH_I2C_DATA_DVI 1 S G 2N7002 2 SOT23 +3D3V D G Q29 3 1 S G 2N7002 2 SOT23 D G Q30 3 0402 R132 2.2K-5% DVI_SCL +5V_CON R133 2.2K-5% DVI_SDA A +5V_CON +3D3V 0402 <42> PCH_DVI_HPD Q31 2N7002 D G1 S G R626 0 4 0 2 10K-5% 2 SOT23 3 0402 R134 2.2K-5% DVI__HPD R628 100K-5% 5 4 DVI C1 C2 C1 C3 C2 C4 C3 C5 C4 C6 C5 C6 +5V_CON DVI_TX2_DN 1 DVI_TX2_DP 2 TMDS Data2- 17 9 1 0402 C124 0402 C125 0402 C142 3 TMDS Data2+ 4 TMDS Data2/4 Shield 0.1UF/16V 0.1UF/16V 0.1UF/16V DVI_SCL 5 TMDS Data46 TMDS Data4+ DVT:ADD C125 C142 DVI_SDA 7 DDC Clock 8 DDC Data DVI_TX1_DN 9 NC DVI_TX1_DP 10 TMDS Data1- 11 TMDS Data1+ B +5V_CON 12 TMDS Data1/3 Shield 24 16 8 13 TMDS Data3- 14 TMDS Data3+ C3 C1 15 +5V Power C4 C2 DVI__HPD R627 0 4 0 2 10K-5D%VI__HPD_CON 16 GND (for +5V) C5 DVI_TX0_DN 17 Hot Plug Detect DVI_TX0_DP 18 TMDS Data0- TOPSTAR 19 TMDS Data0+ MODULE SCH 20 TMDS Data0/5 Shield DVI-I 21 TMDS Data5- 2007-01-07 22 TMDS Data5+ DVI_CLK_DP 23 TMDS Clock Shield DVI_CLK_DN 24 TMDS Clock+ TMDS Clock- 25 26 CASE CASE#M3 DVI A ShenZhen Topstar Inductor Co.,Ltd Page Name VGA/HDMI Size Custom Project Name F-H61 Date: Friday, March 15, 2013 Sheet 21 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3 2 1 5 04020402 SATA1TXP C126 SATA1TXN C127 0.01UF/25V 0.01UF/25V SATA1RXN C130 D SATA1RXP C132 0.01UF/25V 0.01UF/25V 04020402 4 SATA1 2 3 TX+ (I) TX- (I) 8 1 5 6 RX- (O) RX+ (O) 2 3 4 1 4 GND1 (P) 7 GND2 (P) 5 6 7 8 9 GND3 (P) G1 G2 9 SERIAL_ATA 04020402 SATA0TXP C134 C SATA0TXN C136 0.01UF/25V 0.01UF/25V SATA0RXN C138 SATA0RXP C140 0.01UF/25V 0.01UF/25V 04020402 SATA2 2 3 TX+ (I) TX- (I) 8 1 5 6 RX- (O) RX+ (O) 2 3 4 1 4 7 8 GND1 (P) GND2 (P) GND3 (P) 9 G1 5 6 7 9 G2 SERIAL_ATA B <38> SATA1RXN <38> SATA1RXP <38> SATA1TXN <38> SATA1TXP <38> SATA0RXN <38> SATA0RXP <38> SATA0TXN <38> SATA0TXP SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1 SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 <38> SATA5RXN SATA_RXN5 <38> SATA5RXP SATA_RXP5 <38> SATA5TXN SATA_TXN5 <38> SATA5TXP SATA_TXP5 A <38> SATA4RXN SATA_RXN4 <38> SATA4RXP SATA_RXP4 <38> SATA4TXN SATA_TXN4 <38> SATA4TXP SATA_TXP4 5 4 3 2 1 04020402 SATA3 SATA4TXP C135 0.01UF/25V 2 SATA4TXN C137 0.01UF/25V 3 TX+ (I) TX- (I) 8 1 04020402 SATA4RXN C139 SATA4RXP C141 0.01UF/25V 0.01UF/25V 5 6 RX- (O) RX+ (O) 2 3 4 D 1 4 GND1 (P) 7 8 9 GND2 (P) GND3 (P) G1 5 6 7 9 G2 SERIAL_ATA 04020402 SATA4 SATA5TXP C128 SATA5TXN C129 0.01UF/25V 0.01UF/25V 2 3 TX+ (I) TX- (I) 8 C SATA5RXN C131 SATA5RXP C133 0.01UF/25V 0.01UF/25V 04020402 1 5 6 RX- (O) RX+ (O) 2 3 4 1 4 7 GND1 (P) GND2 (P) 5 6 7 8 GND3 (P) 9 G1 G2 9 SERIAL_ATA B ShenZhen Topstar Inductor Co.,Ltd Page Name SATA Size Project Name A F-H61 Rev A 1.0 Date: Friday, March 15, 2013 Sheet 22 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3 2 1 5 +5V FU3 1812 1 2A/8V D 0402 C149 + CE9 0.1UF/16V 6.3*12 220UF/16V DVT 4 REAR USB PORT 0402 C143 0402 C144 0402 C145 0.1UF/16V 470PF/50V 4700PF/50V DVT:ADD C145 C146 C149 USBP10N USBP10P 5V_REAR_USB USB1 G3 G1 U1 U5 U2 U6 U3 U7 U4 U8 G4 G2 USBCON COLAY LANUSB2 R139 0 4 0 2 10K-5% USBP11N USBP11P R140 15K-5% -USBOC5 <37> C 0402 C151 0402 C152 0402 C146 0.1UF/16V 470PF/50V 4700PF/50V DVT USBP8N USBP8P 5V_REAR_USB LAN_USBA UG1 UG3 U1 VCC VCC U5 U2 D0- D1- U6 U3 D0+ D1+U7 U4 GNDGND U8 UG2 UG4 USBP9N USBP9P B USB_RJ45 CHASISS GND DESIGN NOTE: OC0# Port0,Port1,Port4,Port5 OC1# Not used OC2# Not used OC3# Not used OC4# Port8,Port9,Por10,Port11 OC5# Not used OC6# Not used OC7# Not used <37> USBP0N <37> USBP0P <37> USBP1N <37> USBP1P <37> USBP10N <37> USBP10P <37> USBP11N <37> USBP11P <37> USBP8N <37> USBP8P <37> USBP9N <37> USBP9P A 5 4 0402 0402 3 2 FRONT USB PORT 1 D C +5V FU6 1812 1 2A/8V + CE10 6.3*12 220UF/16V 0402 C147 0402 C148 0.1UF/16V 470PF/50V FUSB1 JUSB1 R143 0 4 0 2 10K-5% -USBOC0 <37> 1 2 USBP0N 3 4 USBP1N USBP0P 5 6 USBP1P R144 15K-5% 7 8 10 B 2X5NC9 A ShenZhen Topstar Inductor Co.,Ltd Page Name USB Size Custom Project Name F-H61 Date: Friday, March 15, 2013 Sheet 23 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3 2 1 5 Connector LAN_USBB TD+ L1 TX+ VCC VCC TD- L2 TX- RX+ L3 RX+ mct1 L4 GNDGND L5 D RX- L6 RX- mct2 L7 L8 USB_RJ45 G1 G2 G4 G3 L9 VDD33 L10 L12 L11 LR31 0 6 0 375-5% LR32 0 6 0 375-5% LED0 0 4 0 2 LED1/EESK 0 4 0 2 R147 330-5% NC 330-5% R148 CHASISS GND 0805 HV LHC2 1000pF/2kV mct1 LG1 CHASISS GND C APG2247B mct2 LR30 0 8 0 5 0-5% CHASISS GND 4 TX+ mct1 TXRXmct2 RX+ LU6 16 TX+ 15 CMT2 14 TX- 9 RX- 10 CMT1 11 RX+ H16107DF 8105E 1 TD+ 2 CT2 3 TD- 7 CT1 RD- 8 6 RD+ MDI0+ V_DAC MDI0V_DAC LC30 MDI1MDI1+ 0.01UF/25V HV 0603 LR24 0 4 0 2 0-5% LR25 0 4 0 2 0-5% LR26 0 4 0 2 0-5% LHC1 1000pF/2KV CHASISS GND VDD10 13 SMBCLK 14 SMBDATA 15 CLKREQB 16 HSIP 17 HSIN 18 REFCLK+ 19 REFCLK- 20 EVDD10 21 HSOP 22 HSON 23 24 3 2 1 XTAL1 RTL8111E/8105E LR1 X1 11 2 0603 1M-5% LC3215MHz LC32 0402 0402 27PF/50V 27PF/50V XTAL2 LR3 0402 2.49K-1% Controller VDD33 LR2 10K-5% CLKREQB 0402 LR6 10K-5% LANWAKEB 0402 RSET* LR1 value should be 2.49K (1%) 10K ohm close to Host side D for all application. VDD33 VDD33 VDD10 XTAL2 XTAL1 VDD33 VDD10 LED0 VDD33 GPO LED1/EESK VDD33 MDI0+ MDI0- MDI1+ MDI1- VDD10 VDD10 VDD10 VDD33 LU2 G1 G2 G1 G3 G2 G3 1 2 MDIP0 3 MDIN0 4 AVDD10 5 MDIP1 6 7 MDIN1 AVDD10(NC) 8 MDIP2(NC) 9 MDIN2(NC) 10 AVDD10(NC) 11 MDIP3(NC) 12 MDIN3(NC) AVDD33(NC) 48 AVDD33 47 AVDD33 46 RSET 45 AVDD10 44 CKXTAL2 43 CKXTAL1 42 AVDD33 41 DVDD10(NC) 40 LED0 39 DVDD3 38 GPO/SMBALERT 37 LED1/EESK RTL8105E VDD33 36 REGOUT 35 VDDREG 34 VDDREG 33 ENSWREG 32 EEDI LED3/EEDO 31 30 EECS 29 DVDD10 28 LANWAKEB 27 DVDD33 26 ISOLATEB 25 PERSTB REGOUT AVDD33_REG AVDD33_REG ENSWREG EEDI LED3/EEDO EECS VDD10 LANWAKEB VDD33 ISOLATEB PERSTB 0402 LR9 PH For Enable Switch Regulator. 0-5% PD For Disable Switch Regulator. LR22 0 4 0 2 LR23 0 4 0 2 +3D3V 1K-5% ( Main Power ) 15K-5% DVDD10 SMBCLK(NC) SMBDATA(NC) CLKREQB HSIP HSIN REFCLK_P REFCLK_N EVDD10 HSOP HSON GND G4 G5 G4 G6 G5 G6 C G7 G8 G7 G9 G8 G9 ESD Protection Design for LAN Port +5V_SB MDI0+ LC36 0402 0.1UF/16V MDI1- B LU3 4 5 6 VCC ACZ009-04S VSS 3 2 1 MSEA53025V06A0 MDI0- MDI1+ INTERFACE <18,39> WAKE_N <12,16,18> -PCIE_RST A <43> CK_GLAN_DP <43> CK_GLAN_DN <37> HSI1_DP <37> HSI1_DN <37> HSO1_DP <37> HSO1_DN mismatch <=5MIL 04020402 LC24 LC27 0.1UF/16V 0.1UF/16V 04020402 LC28 LC29 0.1UF/16V 0.1UF/16V PLaced near BRIGDE LANWAKEB PERSTB REFCLK+ REFCLK- HSOP HSON HSIP HSIN 5 REGOUT LL1 LR27 0 8 0 5 0-5% UDEF 1 4.7u/2A Pls. refer to LC53 0805 22uF/6.3V LC35 0402 0.1UF/16V 8111E Layout Guide for Lx, Cout1, Cout2 selection criteria. Remove For Disable Switch Regulator (Accept External 1.05V Power Supply ) Power * LC3 to LC9 are for VDD10 pins-- 3, 6, 9, 13, 29, 41, 45. VDD10 LC38 LC39 LC33 LC34 LC40 LC41 LC42 0402 0402 0402 0402 0402 0402 0402 LC3 to LC9 0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V Close To LU1 LR28 0 6 0 3 0-5% * LC10 ,LC11 are for EVDD10 pins--21. EVDD10 LC15 0603 1UF/16V LC44 0402 0.1UF/16V LC10 LC11 Close To LU1 Pin 21. 3VDUAL * LC12 to LC17 are for VDD33 pins-- 12, 27, 39, 42, 47, 48. VDD33 LR29 0 8 0 5 0-5% LC54 LC46 LC47 LC48 LC49 LC50 0805 0402 0402 0402 0402 0402 10UF/6.3V0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V LC12 to LC17 Close To LU1 LR34 0 6 0 3 0-5% LC55 0805 22uF/6.3V AVDD33_REG LC52 0402 Remove For Disable 0.1UF/16V Switch Regulator (Accept External 1.05V Power Supply ) 4 3 Function (EEPROM,Efuse,ASF) LR5 0 4 0 2 10K-5% SMBDATA RTL8111E NOTE: 8111E: 使用93C46或EFUSE时,SMBDATA 10K接地;使用93C56时,10K上拉。 8105E: SMBDATA PIN NC VDD33 EECS LED1/EESK EEDI LED3/EEDO LU1 1 2 3 1C&S SK VCC DC 8 7 6 4 DI ORG 5 DO GND LC37 0402 0.1UF/16V 93C46 B EEDI EECS LR7 0 4 0 2 10K-5% LR8 0 4 0 2 10K-5% SMBCLK LR14 0 4 0 2 1K-5% NC SMBDATA LR16 0 4 0 2 1K-5% NC GPO LR19 0 4 0 2 1K-5% VDD33 A ShenZhen Topstar Inductor Co.,Ltd Page Name RTL8111E/8105E Size Project Name Custom F-H61 Date: Friday, March 15, 2013 Sheet 24 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 2 1 5 4 Audio Chip MIC1-VREFOUT-R LINE2-VREFO MIC2-VREFO LDOVDD D MIC1-VREFOUT-L Sense B FRONT-L FRONT-R 0603 +5VA AR14 0-5% AC3 0805 4.7UF/10V ALC887 0402 AC4 0.1UF/16V AU1 AC5 0805 4.7UF/10V 25 AVDD1 26 AVSS1 27 VREF 28 MIC1-VREFO-L 29 LINE1-VREFO-L/AFILT1 30 MIC2-VREFO/AFILT2 31 LINE2-VREFO/JD4 32 MIC1-VREFO-R/FMIC2 33 DCVOL/VREFO2 34 Sense B/FMIC1 35 FRONT-L 36 FRONT-R +5VA AC7 0805 0402 4.7UF/10V AC6 0.1UF/16V 37 LINE1-VREFO-R 24 LINE1-R 38 AVDD2 23 LINE1-L 39 SURR-L 22 MIC1-R AR3 0 4 0 2 20K-5% 40 JDREF/NC/JD3 21 MIC1-L 41 SURR-R 20 CD-R 42 AVSS2 19 CD-GND 43 CEN 44 LFE ALC662 18 CD-L 17 MIC2-R/JD1 45 SIDESURR-L/GPIO0 16 MIC2-L/JD2 46 SIDESURR-R/XTLSEL 15 LINE2-R/AUX-R C 47 SPDIFI/EAPD 14 LINE2-L/AUX-L SPDIFO 48 SPDIFO 13 Sense A/Phone LINE1-R LINE1-L MIC1-R MIC1-L MIC2-R MIC2-L LINE2-R LINE2-L Sense A 12 PCBEEP 11 RESET# 10 SYNC 9 DVDD2 8 SDATA-IN 7 DVSS2 6 BIT-CLK 5 SDATA-OUT DVSS1 3 GPIO1/XTLO 2 GPIO0/XTLI 1 DVDD1 +3D3V 4 AC19 0402 0805 4.7UF/10V AR34 AC38 AC20 0.1UF/16V 0805 0-5% ALC887 ALC883/662 10UF/6.3V 0402 FRONT-IO-PRESENCE# SDOUT 0402 AC25 39PF/50V ALC883 RESET# SYNC SDIN BCLK DESIGN NOTE: THE RES IN SERIES SDIN SHOULD PLACE NEAR CODE +3D3V AC21 0402 0.1UF/16V (ALC662 Jack Detect) B Sense A AR6 0 4 0 2 5.1K-5% AR7 0 4 0 2 10K-1% AR8 0 4 0 2 20K-1% FRONT-JD LINE1-JD MIC1-JD Sense B AR12 0 4 0 2 20K-1% AUD-RET-R AR13 0 4 0 2 39K-5% AUD-RET-L Interface A <39> FP_AUD_DETECT <39> AUD_LINK_BCLK <39> AUD_LINK_RST <39> AUD_LINK_SDI2 <39> AUD_LINK_SDO <39> AUD_LINK_SYNC AR29 0 4 0 2 0-5% NC BCLK RESET# SDIN SDOUT SYNC FRONT-IO-PRESENCE# +5VA Signals and Power +5V_SB ALC887 LDOVDD AFB13 0603 1 60OHM/100MHz/650mA AC39AC40 ALC887 0805 0402 ALC887 10UF/6.30V.1UF/16V ALC887AD3 1N4148 +12V 0805 1 2 GND FB12 60OHM/100MHz/1.5A ALC662/883 +5V AU2 1 KIA78L05 NVCOUT VIN 3 AC34 AC33 1& NC 0805 0402 10UF/6.3V 0.1uF/16V + ACE6 61.3&*7 100UF/25V DGND AR21N0 C4 0 2 0-5% AR24N0 C4 0 2 0-5% AR27N0 C4 0 2 0-5% 2 1 CP1 2 1 CP2 2 1 CP3 EMI AGND Tied at three point 1.near the codec 2.near 78L05 3.front panel 5 4 0402 0402 0402 0402 1 3 2 1 Rear Conn Audio Jack LINE IN C (UAJ) SURR OUT F (UAJ) LINE OUT B (UAJ) CEN/LFE E (UAJ) (ALC880 Jack Detect) MIC IN A (UAJ) SIDE SURR OUT D (UAJ) D LINE1-R AC1 LINE1-L AC2 0603 1UF/16V 1UF/16V LINE1-JD AFB1 0603 1 60OHM/100MHz/650mA AFB2 0603 1 60OHM/100MHz/650mA PJ1-32 PJ1-33 PJ1-34 PJ1-35 0603 0603 ++ 5*7 5*7 FRONT-R ACE1 FRONT-L ACE2 AUD-FRONT-R 100uF/10V AUD-FRONT-L 100uF/10V AR1 0 4 0 2 33-5% FRONT-JD AR2 0 4 0 2 33-5% MIC1-R AC8 MIC1-L AC9 0603 1UF/16V 1UF/16V MIC1-JD AFB3 0603 1 60OHM/100MHz/650mA AFB4 0603 1 60OHM/100MHz/650mA AFB5 0603 1 60OHM/100MHz/650mA AFB6 0603 1 60OHM/100MHz/650mA PJ1-22 PJ1-23 PJ1-24 PJ1-25 PJ1-2 PJ1-3 PJ1-4 PJ1-5 PJ1-1 AC10 100PF/50V AC11 100PF/50V AC12 100PF/50V AC13 100PF/50V AC14 100PF/50V AC15 100PF/50V MIC1-VREFOUT-R MIC1-VREFOUT-L AR4 2.2K-5% 0402 0402 AR5 2.2K-5% 0402 0402 0402 0402 0402 0402 AUDIO 33 C4 34 C3 32 C5 PJ1-33 PJ1-34 PJ1-32 35 GND C2 PJ1-35 C G2 G4 5 4 1 3 2 25 24 23 22 35 34 33 32 G1 G3 G1 G2 MH2 MH3 23 B4 24 B3 22 B5 25 GND B2 3 A4 4 A3 2 A5 5 GND A2 1 A1 G3 MH4 G4 MH5 PJ1-23 PJ1-24 PJ1-22 PJ1-25 PJ1-3 PJ1-4 PJ1-2 PJ1-5 PJ1-1 VERTICAL AUDIO AZALIA JACK (No SIDESURR for ALC662) B Front Header MIC2-VREFO LINE2-VREFO 3 3 AD1 AD2 NC SOT23 BAT54A SOT23 BAT54A 2 1 2 1 MIC2-L MIC2-R LINE2-R LINE2-L AC36 AC37 ACE4 ACE5 1UF/16V 1UF/16V 100uF/10V 100uF/10V ++ 5*7 5*706030603 AR16 4.7K-5% AR22 AR23 AR25 0 4 0 2 33-5% 0 4 0 2 33-5% 0 4 0 2 33-5% AR17 AR18 AR19 4.7K-5% NC NC 4.7K-5% 4.7K-5% AR28 0 4 0 2 33-5% 0402 0402 0402 0402 AR30 AR31 AR32 AR33 NC NC NC NC 22K-1%22K-1%22K-1%22K-1% F_AUDIO 12 34 56 7 9 10 2X5 +3D3V 0402 AR20 10K-5% AUD-RET-R AUD-RET-L AR26N0C4 0 2 0-5% FRONT-IO-PRESENCE# 3 2 SPDIFO +5V AC16 0.1UF/16V JSPDIF 1 2 3 0402 A ShenZhen Topstar Inductor Co.,Ltd Page Name ALC883/662 Size Custom Project Name F-H61 Date: Friday, March 15, 2013 Sheet Rev 1.0 25 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 1 5 4 3 2 1 D D C C B B ShenZhen Topstar Inductor Co.,Ltd Page Name BLACK A Size Project Name Rev A A F-H61 1.0 Date: Friday, March 15, 2013 Sheet 26 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 U8 GD75232 D <12> DCD1# <12> DSR1# <12> SIN1 <12> RTS1# <12> SOUT1 <12> CTS1# <12> DTR1# DCD1# DSR1# RXD1 RTS1# TXD1 CTS1# DTR1# <12> RI1# 19 18 RY1 17 RY2 16 RY3 15 DA1 14 13 DA2 RY4 12 DA3 RY5 RA1 2 3 RA2 4 RA3 5 DY1 6 DY2 RA4 7 8 DY3 9 RA5 NDCD1# NDSR1# NRXD1 NRTS1# NTXD1 NCTS1# NDTR1# NRI1# D8 +5V -12V D6 11 1 1N4148 10 GND -12V 20 5V 1 12V 1 1N4148 +12V NC NC NC NC NC NC NC NC 0402 0402 0402 0402 0402 0402 0402 0402 D7 1 100PF/50V C168 100PF/50V C169 100PF/50V C170 100PF/50V C171 100PF/50V C172 100PF/50V C173 100PF/50V C174 100PF/50V C175 1N4148 Optional D NDCD1# NTXD1 NRTS1# NRI1# JCOM1 1 2 3 4 5 6 7 8 9 NRXD1 NDTR1# NDSR1# NCTS1# 2X5 C C B B A A ShenZhen Topstar Inductor Co.,Ltd Page Name COM/LPT/TPM Size Project Name Custom F-H61 Date: Friday, March 15, 2013 Sheet 27 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 D D C C B B ShenZhen Topstar Inductor Co.,Ltd Page Name BLACK A Size Project Name Rev A A F-H61 1.0 Date: Friday, March 15, 2013 Sheet 28 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 DIMM1 DDRVTT 198 49 FREE1 48 FREE2 187 FREE3 NC DDR3 79 RSVD 77 M_ODT_A1 ODT1 195 M_ODT_A0 ODT0 M_ODT_A1 <33> M_ODT_A0 <33> D 240 D 120 VTT1 68 VTT2 NC-PAR_IN 53 NC-ERR_OUT 167 239 NC_TEST4 235 GND1 232 GND2 229 GND3 226 GND4 39 223 GND5 CB0 40 220 GND6 CB1 45 217 GND7 CB2 46 214 GND8 CB3 158 211 GND9 CB4 159 208 GND10 CB5 164 205 GND11 CB6 165 202 GND12 CB7 199 GND13 M_DQS_A_DP[0..7] <33> 166 GND14 163 GND15 M_DQS_A_DN[0..7] <33> 160 GND16 7 M_DQS_A_DP0 157 GND17 DQS0 6 M_DQS_A_DN0 154 GND18 DQS0- 151 GND19 16 M_DQS_A_DP1 148 GND20 DQS1 15 M_DQS_A_DN1 145 GND21 DQS1- 142 GND22 25 M_DQS_A_DP2 139 GND23 DQS2 24 M_DQS_A_DN2 136 GND24 DQS2- 133 GND25 34 M_DQS_A_DP3 130 GND26 DQS3 33 M_DQS_A_DN3 127 GND27 DQS3- DDRVSM DDRVSM 124 GND28 85 M_DQS_A_DP4 121 GND29 DQS4 84 M_DQS_A_DN4 119 GND30 116 SA2 DQS494 M_DQS_A_DP5 CPU_DIMM_VREF_A <33> 113 GND32 DQS5 93 M_DQS_A_DN5 110 GND33 DQS5- 0402 0402 0402 107 GND34 103 M_DQS_A_DP6 1K-1% R172 0-5% 1K-1% 104 GND35 DQS6 102 M_DQS_A_DN6 0402 C202 R171 0402 C203 R173 101 GND36 98 GND37 DQS6112 M_DQS_A_DP7 0.1UF/16V 0.1UF/16V 95 GND38 DQS7 111 M_DQS_A_DN7 92 GND39 DQS7- R174 0 4 0 2 0-5% DIMM_DQ_VREF_A R175 0 4 0 2 0-5% DIMM_CA_VREF_A 89 GND40 43 86 GND41 DQS8 42 83 GND42 DQS8- 80 GND43 0402 0402 47 GND44 1K-1% 0402 C204 1K-1% C 44 GND45 41 GND46 38 GND47 125 DM0_DQS9 126 R176 0.1UF/16V R177 0402 C205 0.1UF/16V C 35 GND48 NC_DQS9- 32 GND49 134 29 GND50 DM1_DQS10 135 26 GND51 NC_DQS10- 23 GND52 143 20 GND53 DM2_DQS11 144 17 GND54 NC_DQS11- 14 GND55 152 11 GND56 DM3_DQS12 153 8 GND57 NC_DQS12- 5 GND58 203 2 GND59 DM4_DQS13 204 DDRVSM GND60 NC_DQS13- 212 197 DM5_DQS14 213 194 VDD1 NC_DQS14- 191 VDD2 221 189 VDD3 DM6_DQS15 222 186 VDD4 NC_DQS15- 183 VDD5 230 182 VDD6 DM7_DQS16 231 179 VDD7 176 VDD8 173 VDD9 NC_DQS16161 DM8_DQS17 162 <18,30,39> SMB_DATA_MAIN <18,30,39> SMB_CLK_MAIN R178 0 4 0 2 0-5% R179 0 4 0 2 0-5% SMB_DATA_OPTION <30> SMB_CLK_OPTION <30> 170 VDD10 NC_DQS17- 78 VDD11 75 VDD12 72 VDD13 69 VDD14 66 VDD15 65 VDD16 3 M_D_A0 M_D_A[0..63] <33> 62 VDD17 DQ0 4 M_D_A1 DDRVSM 60 VDD18 DQ1 9 M_D_A2 57 VDD19 DQ2 10 M_D_A3 54 VDD20 DQ3 122 M_D_A4 51 VDD21 DQ4 123 M_D_A5 1UF/16V C206 1UF/16V C207 1UF/16V C208 1UF/16V C209 +3D3V VDD22 DQ5 128 M_D_A6 DQ6 129 M_D_A7 236 DQ7 12 M_D_A8 0603 0603 0603 0603 VDDSPD DQ8 13 M_D_A9 DQ9 18 M_D_A10 DIMM_CA_VREF_A 67 DQ10 19 M_D_A11 DIMM_DQ_VREF_A 1 VREFCA DQ11 131 M_D_A12 VREFDQ DQ12 132 M_D_A13 DQ13 137 M_D_A14 <30> SMB_CLK_OPTION <30> SMB_DATA_OPTION 118 238 SCL SDA DQ14 DQ15 DQ16 138 M_D_A15 21 M_D_A16 22 M_D_A17 Channel A (Each DIMM must have 4 X 1.0UF capacitors) B DQ17 27 M_D_A18 B 237 DQ18 28 M_D_A19 117 SA1 DQ19 140 M_D_A20 DDRVTT SA0 DQ20 141 M_D_A21 <33> M_SBS_A[0..2] M_SBS_A2 52 DQ21 146 M_D_A22 DQ22 147 M_D_A23 M_SBS_A1 190 BA2 DQ23 30 M_D_A24 M_SBS_A0 71 BA1 DQ24 31 M_D_A25 BA0 DQ25 36 M_D_A26 DQ26 37 M_D_A27 0402 C210 0805 C211 <33> M_SCKE_A1 <33> M_SCKE_A0 M_SCKE_A1 M_SCKE_A0 169 50 CKE1 CKE0 DQ27 DQ28 DQ29 149 M_D_A28 150 M_D_A29 155 M_D_A30 0.1UF/16V 4.7UF/10V DQ30 156 M_D_A31 <33> M_SCS_A_N1 <33> M_SCS_A_N0 M_SCS_A_N1 M_SCS_A_N0 76 193 S1- S0- DQ31 81 DQ32 82 DQ33 87 M_D_A32 M_D_A33 M_D_A34 DQ34 88 M_D_A35 <33> CLK_M_DDR1_A_DN <33> CLK_M_DDR1_A_DP <33> CLK_M_DDR0_A_DN <33> CLK_M_DDR0_A_DP 64 63 CK1_NU185 CK1_NU 184 CK0- CK0 DQ35 DQ36 DQ37 DQ38 DQ39 200 M_D_A36 201 M_D_A37 206 M_D_A38 207 M_D_A39 90 M_D_A40 Channel A VTT Decoupling Caps <33> M_MAA_A[0..15] M_MAA_A0 188 DQ40 91 M_D_A41 DQ41 96 M_D_A42 M_MAA_A1 181 A0 DQ42 97 M_D_A43 M_MAA_A2 61 A1 DQ43 209 M_D_A44 M_MAA_A3 180 A2 DQ44 210 M_D_A45 M_MAA_A4 59 A3 DQ45 215 M_D_A46 M_MAA_A5 58 A4 DQ46 216 M_D_A47 M_MAA_A6 178 A5 DQ47 99 M_D_A48 M_MAA_A7 56 A6 DQ48 100 M_D_A49 M_MAA_A8 177 A7 DQ49 105 M_D_A50 M_MAA_A9 175 A8 DQ50 106 M_D_A51 M_MAA_A10 70 A9 DQ51 218 M_D_A52 M_MAA_A11 55 A10_AP DQ52 219 M_D_A53 M_MAA_A12 174 A11 DQ53 224 M_D_A54 M_MAA_A13 196 A12 DQ54 225 M_D_A55 M_MAA_A14 172 A13 DQ55 108 M_D_A56 M_MAA_A15 171 A14 DQ56 109 M_D_A57 A15 DQ57 114 M_D_A58 DQ58 115 M_D_A59 <30,33> DDR3_DRAMRST_N <33> M_CAS_A_N <33> M_RAS_A_N <33> M_WE_A_N 168 74 RESET- 192 CAS73 RASWE- DQ59 DQ60 DQ61 DQ62 DQ63 227 M_D_A60 228 M_D_A61 233 M_D_A62 234 M_D_A63 A DDR3/240P/DIMM A ShenZhen Topstar Inductor Co.,Ltd Page Name DDR3 CHANNELA Size Custom Project Name F-H61 Date: Friday, March 15, 2013 Sheet 29 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 DDRVTT DIMM2 198 49 FREE1 48 FREE2 187 FREE3 NC 240 120 VTT1 VTT2 239 235 GND1 232 GND2 229 GND3 226 GND4 223 GND5 220 GND6 217 GND7 D 214 GND8 211 GND9 208 GND10 205 GND11 202 GND12 199 GND13 166 GND14 163 GND15 160 GND16 157 GND17 154 GND18 151 GND19 148 GND20 145 GND21 142 GND22 139 GND23 136 GND24 133 GND25 130 GND26 127 GND27 124 GND28 121 GND29 119 GND30 116 SA2 113 GND32 110 GND33 107 GND34 104 GND35 101 GND36 98 GND37 95 GND38 92 GND39 89 GND40 86 GND41 83 GND42 80 GND43 47 GND44 44 GND45 41 GND46 38 GND47 35 GND48 32 GND49 29 GND50 26 GND51 23 GND52 20 GND53 17 GND54 14 GND55 11 GND56 8 GND57 C 5 GND58 2 GND59 DDRVSM GND60 +3D3V 197 194 VDD1 191 VDD2 189 VDD3 186 VDD4 183 VDD5 182 VDD6 179 VDD7 176 VDD8 173 VDD9 170 VDD10 78 VDD11 75 VDD12 72 VDD13 69 VDD14 66 VDD15 65 VDD16 62 VDD17 60 VDD18 57 VDD19 54 VDD20 51 VDD21 VDD22 236 VDDSPD DIMM_CA_VREF_B DIMM_DQ_VREF_B 67 1 VREFCA VREFDQ <29> SMB_CLK_OPTION <29> SMB_DATA_OPTION +3D3V <33> M_SBS_B[0..2] M_SBS_B2 M_SBS_B1 M_SBS_B0 118 238 SCL SDA 237 117 SA1 SA0 52 190 BA2 71 BA1 BA0 B <33> M_SCKE_B1 <33> M_SCKE_B0 M_SCKE_B1 M_SCKE_B0 <33> M_SCS_B_N1 <33> M_SCS_B_N0 M_SCS_B_N1 M_SCS_B_N0 169 50 CKE1 CKE0 76 193 S1S0- <33> CLK_M_DDR1_B_DN <33> CLK_M_DDR1_B_DP <33> CLK_M_DDR0_B_DN <33> CLK_M_DDR0_B_DP <33> M_MAA_B[0..15] M_MAA_B0 M_MAA_B1 M_MAA_B2 M_MAA_B3 M_MAA_B4 M_MAA_B5 M_MAA_B6 M_MAA_B7 M_MAA_B8 M_MAA_B9 M_MAA_B10 M_MAA_B11 M_MAA_B12 M_MAA_B13 M_MAA_B14 M_MAA_B15 64 63 CK1_NU185 CK1_NU 184 CK0- CK0 188 181 A0 61 A1 180 A2 59 A3 58 A4 178 A5 56 A6 177 A7 175 A8 70 A9 55 A10_AP 174 A11 196 A12 172 A13 171 A14 A15 <29,33> DDR3_DRAMRST_N <33> M_CAS_B_N <33> M_RAS_B_N <33> M_WE_B_N 168 74 RESET- 192 CAS73 RASWE- DDR3 DDR3/240P/DIMM 79 RSVD 77 M_ODT_B1 ODT1 195 M_ODT_B0 ODT0 68 NC-PAR_IN 53 NC-ERR_OUT 167 NC_TEST4 M_ODT_B1 <33> M_ODT_B0 <33> 39 CB0 40 CB1 45 CB2 46 CB3 158 CB4 159 CB5 164 CB6 165 CB7 7 DQS0 6 DQS0- M_DQS_B_DP0 M_DQS_B_DN0 16 M_DQS_B_DP1 DQS1 15 M_DQS_B_DN1 DQS1- 25 M_DQS_B_DP2 DQS2 24 M_DQS_B_DN2 DQS2- 34 M_DQS_B_DP3 DQS3 33 M_DQS_B_DN3 DQS3- 85 M_DQS_B_DP4 DQS4 84 M_DQS_B_DN4 DQS4- 94 M_DQS_B_DP5 DQS5 93 M_DQS_B_DN5 DQS5- 103 M_DQS_B_DP6 DQS6 102 M_DQS_B_DN6 DQS6- 112 M_DQS_B_DP7 DQS7 111 M_DQS_B_DN7 DQS7- 43 DQS8 42 DQS8- M_DQS_B_DP[0..7] <33> M_DQS_B_DN[0..7] <33> 125 DM0_DQS9 126 NC_DQS9- 134 DM1_DQS10 135 NC_DQS10- 143 DM2_DQS11 144 NC_DQS11- 152 DM3_DQS12 153 NC_DQS12- 203 DM4_DQS13 204 NC_DQS13- 212 DM5_DQS14 213 NC_DQS14- 221 DM6_DQS15 222 NC_DQS15- 230 DM7_DQS16 231 NC_DQS16- 161 DM8_DQS17 162 NC_DQS17- DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 3 M_D_B0 4 M_D_B1 9 M_D_B2 10 M_D_B3 122 M_D_B4 123 M_D_B5 128 M_D_B6 129 M_D_B7 12 M_D_B8 13 M_D_B9 18 M_D_B10 19 M_D_B11 131 M_D_B12 132 M_D_B13 137 M_D_B14 138 M_D_B15 21 M_D_B16 22 M_D_B17 27 M_D_B18 28 M_D_B19 140 M_D_B20 141 M_D_B21 146 M_D_B22 147 M_D_B23 30 M_D_B24 31 M_D_B25 36 M_D_B26 37 M_D_B27 149 M_D_B28 150 M_D_B29 155 M_D_B30 156 M_D_B31 81 M_D_B32 82 M_D_B33 87 M_D_B34 88 M_D_B35 200 M_D_B36 201 M_D_B37 206 M_D_B38 207 M_D_B39 90 M_D_B40 91 M_D_B41 96 M_D_B42 97 M_D_B43 209 M_D_B44 210 M_D_B45 215 M_D_B46 216 M_D_B47 99 M_D_B48 100 M_D_B49 105 M_D_B50 106 M_D_B51 218 M_D_B52 219 M_D_B53 224 M_D_B54 225 M_D_B55 108 M_D_B56 109 M_D_B57 114 M_D_B58 115 M_D_B59 227 M_D_B60 228 M_D_B61 233 M_D_B62 234 M_D_B63 DDRVSM CPU_DIMM_VREF_B <33> DDRVSM 0402 C212 0.1UF/16V 0402 1K-1% R180 R181 0-5% 0402 R183 0 4 0 2 0-5% DIMM_DQ_VREF_B 0402 C213 0.1UF/16V 0402 1K-1% R182 R184 0 4 0 2 0-5% DIMM_CA_VREF_B 0402 1K-1% R185 0402 C214 0.1UF/16V M_D_B[0..63] <33> 0402 1K-1% R186 0402 C215 0.1UF/16V <18,29,39> SMB_DATA_MAIN <18,29,39> SMB_CLK_MAIN R187 0 4 0 2 0-5% R188 0 4 0 2 0-5% SMB_DATA_OPTION <29> SMB_CLK_OPTION <29> DDRVSM 0603 0603 0603 0603 1UF/16V C216 1UF/16V C217 1UF/16V C218 1UF/16V C219 Channel B (Each DIMM must have 4 X 1.0UF capacitors) DDRVTT 0402 C220 0.1UF/16V 0805 C221 4.7UF/10V Channel B VTT Decoupling Caps 1 D C B A A ShenZhen Topstar Inductor Co.,Ltd Page Name DDR3 CHANNELB Size Custom Project Name F-H61 Date: Friday, March 15, 2013 Sheet 30 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 D D 0402 0402 0402 0402 V_CPU_VCCIO +5V CAD NOTE: Place these RES near CPU R189 90.9-1% R190 110-1% R191 75-1% J33E 0402 R198 10K-5% TO BE SURE<<4466>> H_VIDSCK_VR H_VIDSOUT_VR <46> H_VIDALERT_N_VR H_VIDSCK_VR H_VIDSOUT_VR H_VIDALERT_N_VR R192 0 4 0 2 0-5% H_VIDSCLK R193 0 4 0 2 0-5% H_VIDSOUT R194 0 4 0 2 0-5% H_VIDALERT_N <43> CK_PE_100M_MCP_DP <43> CK_PE_100M_MCP_DN R195 0 4 0 2 44.2-1% VIDALERT_N W2 W1 BCLK[0] BCLK#[0] C37 B37 VIDSCLK A37 VIDSOUT VIDALERT# SKT_H2 LGA1155 MISC P33 VCCIO_SELECT P34 VCCSA_VID_0 T2 VCCSA_SENSE A36 VCC_SENSE B36 VSS_SENSE VCCSA_VID <50> VCCSA_SENSE <50> VCC_SENSE <46> VSS_SENSE <46> 0402 VCCIO_SEL <48> R199 4.7K-5% DDRVSM R197 0 4 0 2 200-1% H_DRAMPWRGD V_CPU_VCCIO DESIGN NOTE: FOR RICHTEK VR DEBUG R200N0 C4 0 2 100-1% <39> H_PWRGD <39> H_DRAMPWRGD <16> H_CPURST_N H_PWRGD J40 H_DRAMPWRGD120-5%0 4 0 2 R196 AJ19 H_CPURST_N F36 <38> H_PM_SYNC_0 <12,38> H_PECI H_PM_SYNC_0 H_PECI H_CATERR_N E38 J35 E37 UNCOREPWRGOOD SM_DRAMPWROK RESET# PM_SYNC PECI VCCIO_SENSE VSSIO_SENSE VCCAXG_SENSE VSSAXG_SENSE TDO AB4 AB3 L32 M32 L39 L40 H_TDO H_TDI VCCIO_SENSE <48> VSSIO_SENSE <48> VCCAXG_SENSE <46> VSSAXG_SENSE <46> C R201N0 C4 0 2 51-5% H_PWRGD 1K-5% 0 4 0 2 R202 DVT:ADD C349 <46> H_PROCHOT_N <38> H_THERMTRIP_N H_PROCHOT_N H_THERMTRIP_N H34 CATERR# G35 PROCHOT# THERMTRIP# H_SKTOCC_N AJ33 TDI TCK TMS TRST# M40 L38 J39 K38 H_TCK H_TMS H_TRST_N H_PRDY_N C C349 0.1UF/16V H_SNB_N K32 SKTOCC# PRDY# K40 H_PREQ_N 0402 R204N0 C4 0 2 1K-5% H_PECI If an alteernative host controller is used,then the H_SM_VREF FC_K32 AJ22 SM_VREF PREQ# E39 DBR# C40 BCLK_ITP D40 R203 0 4 0 2 0-5% FP_RST_N <15,39> processor PECI interface cannot to be connected to the BCLK_ITP# R205N0 C4 0 2 1K-5% H_CATERR_N R207 0 4 0 2 51-5% H_PROCHOT_N R210 0 4 0 2 51-5% H_THERMTRIP_N intel PCH CFG Default value is "1" CFG[1:0] Reserved CFG[2] PCIE Static X16 Lane Number Reversal -1=Normal operation -0=Lane numbers reversed CFG[3] PCIE Static X4 Lane Number Reversal -1=Normal operation -0=Lane numbers reversed CFG[4] Reserved CFG[6:5] -00=1X8.2X4 PCIE -01=reserved -10=2X8 PCIE -11=1X16 PCIE CFG[17:7] reserved H36 J36 J37 K36 L36 N35 L37 M36 J38 L35 M38 N36 N38 N39 N37 N40 G37 G36 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] H40 BPM#[0] H38 BPM#[1] G38 BPM#[2] G40 BPM#[3] G39 BPM#[4] F38 BPM#[5] E40 BPM#[6] F40 BPM#[7] B39 RSVD5 J33 RSVD6 L34 RSVD7 L33 RSVD8 K34 RSVD9 N33 RSVD10 M34 RSVD11 R227 0 4 0 2 51-5% R229 0 4 0 2 51-5% V_CPU_VCCIO H_PRDY_N 51-5%N0 4C0 2 R214 H_PREQ_N 51-5%N0 4C0 2 R216 H_TDO H_TDI H_TMS H_TCK H_TRST_N 51-5% 0 4 0 2 R221 51-5% 0 4 0 2 R223 51-5% 0 4 0 2 R225 AT14 AY3 H7 H8 RSVD1 RSVD2 RSVD3 RSVD4 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 AV1 AW2 L9 J9 K9 L31 B RSVD17 B J31 VCC_VALIDATION_SENSE K31 VSSU_VALIDATION_SENSE AD34 VCCAXG_VALIDATION_SENSE AD35 VSSGT_VALIDATION_SENSE 5 OF 11 SANDY BRIDGE SKY <39,46> H_SKTOCC_R_N 0402 3VDUAL DVT:R234 不再NC R234 1K-5% R236 0 4 0 2 0-5% H_SKTOCC_N 0402 NC R237 10K-5% DDRVSM 0402 R235 100-1% H_SM_VREF R238 100-1% 0402 C222 0.1UF/16V 0402 V_1P8_SFR A A <40> NVR_CLE R239 2.2K-5% 4.7K-5% 0 4 0 2 R240 H_SNB_N ShenZhen Topstar Inductor Co.,Ltd 0402 C223 0.1UF/16V Page Name SAND BRIDGE_MISC Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 31 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 D C B A 5 4 3 2 <18> EXP_A_RX_0_DP <18> EXP_A_RX_0_DN <18> EXP_A_RX_1_DP <18> EXP_A_RX_1_DN <18> EXP_A_RX_2_DP <18> EXP_A_RX_2_DN <18> EXP_A_RX_3_DP <18> EXP_A_RX_3_DN <18> EXP_A_RX_4_DP <18> EXP_A_RX_4_DN <18> EXP_A_RX_5_DP <18> EXP_A_RX_5_DN <18> EXP_A_RX_6_DP <18> EXP_A_RX_6_DN <18> EXP_A_RX_7_DP <18> EXP_A_RX_7_DN <18> EXP_A_RX_8_DP <18> EXP_A_RX_8_DN <18> EXP_A_RX_9_DP <18> EXP_A_RX_9_DN <18> EXP_A_RX_10_DP <18> EXP_A_RX_10_DN <18> EXP_A_RX_11_DP <18> EXP_A_RX_11_DN <18> EXP_A_RX_12_DP <18> EXP_A_RX_12_DN <18> EXP_A_RX_13_DP <18> EXP_A_RX_13_DN <18> EXP_A_RX_14_DP <18> EXP_A_RX_14_DN <18> EXP_A_RX_15_DP <18> EXP_A_RX_15_DN <37> DMI_IT_MR_0_DP <37> DMI_IT_MR_0_DN <37> DMI_IT_MR_1_DP <37> DMI_IT_MR_1_DN <37> DMI_IT_MR_2_DP <37> DMI_IT_MR_2_DN <37> DMI_IT_MR_3_DP <37> DMI_IT_MR_3_DN V_CPU_VCCIO R241 0 4 0 2 24.9-1% J33C B11 B12 PEG_RX[0] D12 PEG_RX#[0] D11 PEG_RX[1] C10 PEG_RX#[1] C9 PEG_RX[2] E10 PEG_RX#[2] E9 PEG_RX[3] B8 PEG_RX#[3] B7 PEG_RX[4] C6 PEG_RX#[4] C5 PEG_RX[5] A5 PEG_RX#[5] A6 PEG_RX[6] E2 PEG_RX#[6] E1 PEG_RX[7] F4 PEG_RX#[7] F3 PEG_RX[8] G2 PEG_RX#[8] G1 PEG_RX[9] H3 PEG_RX#[9] H4 PEG_RX[10] J1 PEG_RX#[10] J2 PEG_RX[11] K3 PEG_RX#[11] K4 PEG_RX[12] L1 PEG_RX#[12] L2 PEG_RX[13] M3 PEG_RX#[13] M4 PEG_RX[14] N1 PEG_RX#[14] N2 PEG_RX[15] PEG_RX#[15] W5 W4 DMI_RX[0] V3 DMI_RX#[0] V4 DMI_RX[1] Y3 DMI_RX#[1] Y4 DMI_RX[2] AA4 DMI_RX#[2] AA5 DMI_RX_3 DMI_RX#[3] P3 P4 PE_RX[0] R2 PE_RX#[0] R1 PE_RX[1] T4 PE_RX#[1] T3 PE_RX[2] U2 PE_RX#[2] U1 PE_RX[3] PE_RX#[3] B5 C4 PEG_ICOMPO B4 PEG_RCOMPO PEG_ICOMPI SANDY BRIDGE SKT_H2 LGA1155 PEG DMI GEN 3 OF 11 C13 PEG_TX[0] C14 PEG_TX#[0] E14 PEG_TX[1] E13 PEG_TX#[1] G14 PEG_TX[2] G13 PEG_TX#[2] F12 PEG_TX[3] F11 PEG_TX#[3] J14 PEG_TX[4] J13 PEG_TX#[4] D8 PEG_TX[5] D7 PEG_TX#[5] D3 PEG_TX[6] C3 PEG_TX#[6] E6 PEG_TX[7] E5 PEG_TX#[7] F8 PEG_TX[8] F7 PEG_TX#[8] G10 PEG_TX[9] G9 PEG_TX#[9] G5 PEG_TX[10] G6 PEG_TX#[10] K7 PEG_TX[11] K8 PEG_TX#[11] J5 PEG_TX[12] J6 PEG_TX#[12] M8 PEG_TX[13] M7 PEG_TX#[13] L6 PEG_TX[14] L5 PEG_TX#[14] N5 PEG_TX[15] N6 PEG_TX#[15] V7 DMI_TX[0] V6 DMI_TX#[0] W7 DMI_TX[1] W8 DMI_TX#[1] Y6 DMI_TX[2] Y7 DMI_TX#[2] AA7 DMI_TX[3] AA8 DMI_TX#[3] P8 PE_TX[0] P7 PE_TX#[0] T7 PE_TX[1] T8 PE_TX#[1] R6 PE_TX[2] R5 PE_TX#[2] U5 PE_TX[3] U6 PE_TX#[3] SKY EXP_A_TX_0_DP <18> EXP_A_TX_0_DN <18> EXP_A_TX_1_DP <18> EXP_A_TX_1_DN <18> EXP_A_TX_2_DP <18> EXP_A_TX_2_DN <18> EXP_A_TX_3_DP <18> EXP_A_TX_3_DN <18> EXP_A_TX_4_DP <18> EXP_A_TX_4_DN <18> EXP_A_TX_5_DP <18> EXP_A_TX_5_DN <18> EXP_A_TX_6_DP <18> EXP_A_TX_6_DN <18> EXP_A_TX_7_DP <18> EXP_A_TX_7_DN <18> EXP_A_TX_8_DP <18> EXP_A_TX_8_DN <18> EXP_A_TX_9_DP <18> EXP_A_TX_9_DN <18> EXP_A_TX_10_DP <18> EXP_A_TX_10_DN <18> EXP_A_TX_11_DP <18> EXP_A_TX_11_DN <18> EXP_A_TX_12_DP <18> EXP_A_TX_12_DN <18> EXP_A_TX_13_DP <18> EXP_A_TX_13_DN <18> EXP_A_TX_14_DP <18> EXP_A_TX_14_DN <18> EXP_A_TX_15_DP <18> EXP_A_TX_15_DN <18> DMI_MT_IR_0_DP DMI_MT_IR_0_DN DMI_MT_IR_1_DP DMI_MT_IR_1_DN DMI_MT_IR_2_DP DMI_MT_IR_2_DN DMI_MT_IR_3_DP DMI_MT_IR_3_DN <37> <37> <37> <37> <37> <37> <37> <37> <41> FDI_FSYNC0 <41> FDI_LSYNC0 <41> FDI_FSYNC1 <41> FDI_LSYNC1 V_CPU_VCCIO <41> FDI_INT R242 0 4 0 2 24.9-1% J33D AC5 AC4 FDI_FSYNC_0 FDI_LSYNC_0 SKT_H2 LGA1155 FDI LINK AE5 AE4 FDI_LSYNC_1 FDI_FSYNC_1 AG3 AE2 AE1 FDI_INT FDI_COMPIO FDI_ICOMPO SANDY BRIDGE 4 OF 11 FDI_TX[0] FDI_TX#[0] FDI_TX[1] FDI_TX#[1] FDI_TX[2] FDI_TX#[2] FDI_TX[3] FDI_TX#[3] FDI_TX[4] FDI_TX#[4] FDI_TX[5] FDI_TX#[5] FDI_TX[6] FDI_TX#[6] FDI_TX[7] FDI_TX#[7] AC8 AC7 AC2 AC3 AD2 AD1 AD4 AD3 AD7 AD6 AE7 AE8 AF3 AF2 AG2 AG1 SKY FDI_TX_0_DP <41> FDI_TX_0_DN <41> FDI_TX_1_DP <41> FDI_TX_1_DN <41> FDI_TX_2_DP <41> FDI_TX_2_DN <41> FDI_TX_3_DP <41> FDI_TX_3_DN <41> FDI_TX_4_DP <41> FDI_TX_4_DN <41> FDI_TX_5_DP <41> FDI_TX_5_DN <41> FDI_TX_6_DP <41> FDI_TX_6_DN <41> FDI_TX_7_DP <41> FDI_TX_7_DN <41> 4 3 2 1 D C B A ShenZhen Topstar Inductor Co.,Ltd Page Name SANDY BRIDGE_PEG/DMI/FDI Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 32 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 1 5 4 3 2 1 D D J33B M_D_A[0..63] <29> M_D_A[0..63] M_D_A0 M_D_A1 M_D_A2 M_D_A3 AJ3 AJ4 SA_DQ[0] AL3 SA_DQ[1] AL4 SA_DQ[2] SKT_H2 LGA1155 J33A SA_MA[0] SA_MA[1] SA_MA[2] AV27 AY24 AW24 AW23 M_MAA_A0 M_MAA_A1 M_MAA_A2 M_MAA_A3 M_MAA_A[0..15] <29> <30> M_D_B[0..63] M_D_B0 M_D_B1 M_D_B2 M_D_B3 M_D_B4 AG7 AG8 AJ9 AJ8 AG5 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SKT_H2 LGA1155 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] AK24 AM20 AM19 AK18 AP19 M_MAA_B0 M_MAA_B1 M_MAA_B2 M_MAA_B3 M_MAA_B4 M_MAA_B[0..15] <30> M_D_A4 M_D_A5 M_D_A6 AJ2 SA_DQ[3] AJ1 SA_DQ[4] AL2 SA_DQ[5] DDR_A SA_MA[3] SA_MA[4] SA_MA[5] AV23 AT24 AT23 M_MAA_A4 M_MAA_A5 M_MAA_A6 M_D_B5 M_D_B6 M_D_B7 AG6 AJ6 AJ7 SB_DQ[4] SB_DQ[5] SB_DQ[6] DDR_B SB_MA[4] AP18 SB_MA[5] AM18 SB_MA[6] AL18 M_MAA_B5 M_MAA_B6 M_MAA_B7 M_D_A7 AL1 SA_DQ[6] SA_MA[6] AU22 M_MAA_A7 DESIGN NOTE: M_D_B13 AL7 SB_DQ[7] SB_MA[7] AN18 M_MAA_B8 M_D_A8 AN1 SA_DQ[7] SA_MA[7] AV22 M_MAA_A8 DQ REMAPPING IMPLEMENTED M_D_B9 AM7 SB_DQ[8] SB_MA[8] AY17 M_MAA_B9 M_D_A9 AN4 SA_DQ[8] SA_MA[8] AT22 M_MAA_A9 TO IMPROVE BREAKOUT AND MINIMIZE CH-2-CH COUPLING M_D_B11 AM10 SB_DQ[9] SB_MA[9] AN23 M_MAA_B10 M_D_A10 AR3 SA_DQ[9] SA_MA[9] AV28 M_MAA_A10 M_D_B15 AL10 SB_DQ[10] SB_MA[10] AU17 M_MAA_B11 M_D_A11 AR4 SA_DQ[10] SA_MA[10] AU21 M_MAA_A11 M_D_B12 AL6 SB_DQ[11] SB_MA[11] AT18 M_MAA_B12 M_D_A12 AN2 SA_DQ[11] SA_MA[11] AT21 M_MAA_A12 M_D_B8 AM6 SB_DQ[12] SB_MA[12] AR26 M_MAA_B13 M_D_A13 AN3 SA_DQ[12] SA_MA[12] AW32 M_MAA_A13 M_D_B14 AL9 SB_DQ[13] SB_MA[13] AY16 M_MAA_B14 M_D_A14 AR2 SA_DQ[13] SA_MA[13] AU20 M_MAA_A14 M_D_B10 AM9 SB_DQ[14] SB_MA[14] AV16 M_MAA_B15 M_D_A15 AR1 SA_DQ[14] SA_MA[14] AT20 M_MAA_A15 M_D_B16 AP7 SB_DQ[15] SB_MA[15] M_D_A16 M_D_A17 M_D_A18 M_D_A19 M_D_A20 M_D_A21 M_D_A22 AV2 AW3 AV5 AW5 AU2 AU3 AU5 SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_MA[15] SA_WE# SA_CAS# SA_RAS# AW29 AV30 AU28 AY29 M_SBS_A0 M_WE_A_N <29> M_CAS_A_N <29> M_RAS_A_N <29> M_SBS_A[0..2] <29> M_D_B17 M_D_B18 M_D_B19 M_D_B20 M_D_B21 M_D_B22 M_D_B23 AR7 AP10 AR10 AP6 AR6 AP9 AR9 SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_WE# SB_CAS# SB_RAS# SB_BS[0] SB_BS[1] AR25 AK25 AP24 AP23 AM24 AW17 M_SBS_B0 M_SBS_B1 M_SBS_B2 M_WE_B_N <30> M_CAS_B_N <30> M_RAS_B_N <30> M_SBS_B[0..2] <30> M_D_A23 AY5 SA_DQ[22] SA_BS[0] AW28 M_SBS_A1 M_D_B24 AM12 SB_DQ[23] SB_BS[2] M_D_A24 AY7 SA_DQ[23] SA_BS[1] AV20 M_SBS_A2 M_D_B25 AM13 SB_DQ[24] M_D_A25 AU7 SA_DQ[24] SA_BS[2] M_D_B26 AR13 SB_DQ[25] AN25 M_SCS_B_N0 M_D_A26 AV9 SA_DQ[25] M_D_B27 AP13 SB_DQ[26] SB_CS#[0] AN26 M_SCS_B_N1 M_SCS_B_N0 <30> M_D_A27 AU9 SA_DQ[26] AU29 M_SCS_A_N0 M_D_B28 AL12 SB_DQ[27] SB_CS#[1] AL25 M_SCS_B_N1 <30> M_D_A28 AV7 SA_DQ[27] SA_CS#[0] AV32 M_SCS_A_N1 M_SCS_A_N0 <29> M_D_B29 AL13 SB_DQ[28] SB_CS#[2] AT26 C M_D_A29 AW7 SA_DQ[28] M_D_A30 AW9 SA_DQ[29] SA_CS#[1] AW30 SA_CS#[2] AU33 M_SCS_A_N1 <29> M_D_B30 AR12 SB_DQ[29] M_D_B31 AP12 SB_DQ[30] SB_CS#[3] AU16 M_SCKE_B0 C M_D_A31 AY9 SA_DQ[30] SA_CS#[3] M_D_B32 AR28 SB_DQ[31] SB_CKE[0] AY15 M_SCKE_B1 M_SCKE_B0 <30> M_D_A32 AU35 SA_DQ[31] AV19 M_SCKE_A0 M_D_B33 AR29 SB_DQ[32] SB_CKE[1] AW15 M_SCKE_B1 <30> M_D_A33 AW37 SA_DQ[32] SA_CKE[0] AT19 M_SCKE_A1 M_SCKE_A0 <29> M_D_B34 AL28 SB_DQ[33] SB_CKE[2] AV15 M_D_A34 AU39 SA_DQ[33] SA_CKE[1] AU18 M_SCKE_A1 <29> M_D_B35 AL29 SB_DQ[34] SB_CKE[3] M_D_A35 AU36 SA_DQ[34] SA_CKE[2] AV18 M_D_B36 AP28 SB_DQ[35] AL26 M_ODT_B0 M_D_A36 AW35 SA_DQ[35] SA_CKE[3] M_D_B37 AP29 SB_DQ[36] SB_ODT[0] AP26 M_ODT_B1 M_ODT_B0 <30> M_D_A37 AY36 SA_DQ[36] AV31 M_ODT_A0 M_D_B38 AM28 SB_DQ[37] SB_ODT[1] AM26 M_ODT_B1 <30> M_D_A38 AU38 SA_DQ[37] SA_ODT[0] AU32 M_ODT_A1 M_ODT_A0 <29> M_D_B39 AM29 SB_DQ[38] SB_ODT[2] AK26 M_D_A39 AU37 SA_DQ[38] SA_ODT[1] AU30 M_ODT_A1 <29> M_D_B40 AP32 SB_DQ[39] SB_ODT[3] M_D_A40 AR40 SA_DQ[39] SA_ODT[2] AW33 M_D_B41 AP31 SB_DQ[40] M_D_A41 AR37 SA_DQ[40] SA_ODT[3] M_D_B42 AP35 SB_DQ[41] M_D_A42 AN38 SA_DQ[41] M_D_B43 AP34 SB_DQ[42] M_D_A43 M_D_A44 M_D_A45 M_D_A46 M_D_A47 M_D_A48 M_D_A49 AN37 AR39 AR38 AN39 AN40 AL40 AL37 SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_CK[0] SA_CK#[0] SA_CK[1] SA_CK#[1] AY25 AW25 AU24 AU25 AW27 CLK_M_DDR0_A_DP CLK_M_DDR0_A_DN CLK_M_DDR1_A_DP CLK_M_DDR1_A_DN <29> <29> <29> <29> M_D_B44 M_D_B45 M_D_B46 M_D_B47 M_D_B48 M_D_B52 M_D_B55 AR32 AR31 AR35 AR34 AM32 AM31 AL35 SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_CK[0] SB_CK#[0] SB_CK[1] SB_CK#[1] SB_CK[2] SB_CK#[2] AL21 AL22 AL20 AK20 AL23 AM22 AP21 CLK_M_DDR0_B_DP CLK_M_DDR0_B_DN CLK_M_DDR1_B_DP CLK_M_DDR1_B_DN <30> <30> <30> <30> M_D_A50 AJ38 SA_DQ[49] SA_CK[2] AY27 M_D_B51 AL32 SB_DQ[50] SB_CK[3] AN21 M_D_A51 AJ37 SA_DQ[50] SA_CK#[2] AV26 M_D_B54 AM34 SB_DQ[51] SB_CK#[3] M_D_A52 AL39 SA_DQ[51] SA_CK[3] AW26 M_D_B49 AL31 SB_DQ[52] M_D_A53 M_D_A54 M_D_A55 M_D_A56 AL38 AJ39 AJ40 AG40 SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_CK#[3] AW18 SM_DRAMRST# R243 0 4 0 2 0-5% DDR3_DRAMRST_N <29,30> M_D_B53 M_D_B50 M_D_B56 M_D_B57 AM35 AL34 AH35 AH34 SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] AH1 SB_DIMM_DQVREF AH4 SA_DIMM_DQVREF CPU_DIMM_VREF_B <30> CPU_DIMM_VREF_A <29> M_D_A57 AG37 SA_DQ[56] M_D_B58 AE34 SB_DQ[57] M_D_A58 AE38 SA_DQ[57] M_D_B59 AE35 SB_DQ[58] M_D_A59 AE37 SA_DQ[58] 0402 C224 M_D_B60 AJ35 SB_DQ[59] M_D_A60 AG39 SA_DQ[59] M_D_A61 AG38 SA_DQ[60] 0.1UF/16V M_D_B61 AJ34 SB_DQ[60] M_D_B62 AF33 SB_DQ[61] M_D_A62 AE39 SA_DQ[61] M_D_B63 AF35 SB_DQ[62] <29> M_DQS_A_DP[0..7] M_D_A63 AE40 SA_DQ[62] SA_DQ[63] <30> M_DQS_B_DP[0..7] SB_DQ[63] M_DQS_B_DP0 AH7 M_DQS_B_DP1 AM8 SB_DQS[0] AN16 SB_DQS[8] AN15 M_DQS_A_DP0 AK3 AV13 M_DQS_B_DP2 AR8 SB_DQS[1] SB_DQS#[8] B M_DQS_A_DP1 AP3 SA_DQS[0] SA_DQS[8] AV12 M_DQS_B_DP3 AN13 SB_DQS[2] AL16 B M_DQS_A_DP2 AW4 SA_DQS[1] SA_DQS#[8] M_DQS_B_DP4 AN29 SB_DQS[3] SB_ECC_CB[0] AM16 M_DQS_A_DP3 AV8 SA_DQS[2] AU12 M_DQS_B_DP5 AP33 SB_DQS[4] SB_ECC_CB[1] AP16 M_DQS_A_DP4 AV37 SA_DQS[3] SA_ECC_CB[0] AU14 M_DQS_B_DP6 AL33 SB_DQS[5] SB_ECC_CB[2] AR16 M_DQS_A_DP5 AP38 SA_DQS[4] SA_ECC_CB[1] AW13 M_DQS_B_DP7 AG35 SB_DQS[6] SB_ECC_CB[3] AL15 M_DQS_A_DP6 AK38 M_DQS_A_DP7 AF38 SA_DQS[5] SA_DQS[6] SA_ECC_CB[2] AY13 SA_ECC_CB[3] AU13 <30> M_DQS_B_DN[0..7] SB_DQS[7] M_DQS_B_DN0 AH6 SB_ECC_CB[4] AM15 SB_ECC_CB[5] AR15 <29> M_DQS_A_DN[0..7] SA_DQS[7] M_DQS_A_DN0 AK2 SA_ECC_CB[4] AU11 SA_ECC_CB[5] AY12 M_DQS_B_DN1 AL8 SB_DQS#[0] M_DQS_B_DN2 AP8 SB_DQS#[1] SB_ECC_CB[6] AP15 SB_ECC_CB[7] M_DQS_A_DN1 AP2 SA_DQS#[0] SA_ECC_CB[6] AW12 M_DQS_B_DN3 AN12 SB_DQS#[2] M_DQS_A_DN2 AV4 SA_DQS#[1] SA_ECC_CB[7] M_DQS_B_DN4 AN28 SB_DQS#[3] M_DQS_A_DN3 AW8 SA_DQS#[2] M_DQS_B_DN5 AR33 SB_DQS#[4] M_DQS_A_DN4 AV36 SA_DQS#[3] M_DQS_B_DN6 AM33 SB_DQS#[5] M_DQS_A_DN5 AP39 SA_DQS#[4] M_DQS_A_DN6 AK39 SA_DQS#[5] M_DQS_B_DN7 AG34 SB_DQS#[6] SB_DQS#7] 2 OF 11 M_DQS_A_DN7 AF39 SA_DQS#[6] SA_DQS#[7] 1 OF 11 SKY SANDY BRIDGE SKY SANDY BRIDGE A A ShenZhen Topstar Inductor Co.,Ltd Page Name SANDY BRIDGE_MEMORY Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 33 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 VCORE VCORE VAXG J33F J33G A12 A13 VCC1 SKT_H2 VCC82 F32 F33 A14 A15 VCC2 VCC3 LGA1155 VCC83 VCC84 F34 G15 AB33 AB34 AB35 AB36 VCCAXG1 VCCAXG2 VCCAXG3 SKT_H2 LGA1155 A16 VCC4 VCC85 G16 D A18 A24 VCC5 VCC6 CPU POWERVVCCCC8867 G18 G19 AB37 AB38 VVCCCCAAXXGGG45 FX POWER AB39 VCCAXG6 A25 VCC7 VCC88 G21 AB40 VCCAXG7 A27 VCC8 VCC89 G22 AC33 VCCAXG8 A28 VCC9 VCC90 G24 AC34 VCCAXG9 B15 VCC10 VCC91 G25 AC35 VCCAXG10 B16 VCC11 VCC92 G27 AC36 VCCAXG11 B18 VCC12 VCC93 G28 AC37 VCCAXG12 B24 VCC13 VCC94 G30 AC38 VCCAXG13 B25 VCC14 VCC95 G31 AC39 VCCAXG14 B27 VCC15 VCC96 G32 AC40 VCCAXG15 B28 VCC16 VCC97 G33 T33 VCCAXG16 B30 VCC17 VCC98 H13 T34 VCCAXG17 B31 VCC18 VCC99 H14 T35 VCCAXG18 B33 VCC19 VCC100 H15 T36 VCCAXG19 B34 VCC20 VCC101 H16 T37 VCCAXG20 C15 VCC21 VCC102 H18 T38 VCCAXG21 C16 VCC22 VCC103 H19 T39 VCCAXG22 C18 VCC23 VCC104 H21 T40 VCCAXG23 C19 VCC24 VCC105 H22 U33 VCCAXG24 C21 VCC25 VCC106 H24 U34 VCCAXG25 C22 VCC26 VCC107 H25 U35 VCCAXG26 C24 VCC27 VCC108 H27 U36 VCCAXG27 C25 VCC28 VCC109 H28 U37 VCCAXG28 C27 VCC29 VCC110 H30 U38 VCCAXG29 C28 VCC30 VCC111 H31 U39 VCCAXG30 C30 VCC31 VCC112 H32 U40 VCCAXG31 C31 VCC32 VCC113 J12 W33 VCCAXG32 C33 VCC33 VCC114 J15 W34 VCCAXG33 C34 VCC34 VCC115 J16 W35 VCCAXG34 C36 VCC35 VCC116 J18 W36 VCCAXG35 D13 VCC36 VCC117 J19 W37 VCCAXG36 D14 VCC37 VCC118 J21 W38 VCCAXG37 D15 VCC38 VCC119 J22 Y33 VCCAXG38 D16 VCC39 VCC120 J24 Y34 VCCAXG39 D18 VCC40 VCC121 J25 Y35 VCCAXG40 D19 VCC41 VCC122 J27 Y36 VCCAXG41 C D21 VCC42 D22 VCC43 VCC123 J28 VCC124 J30 Y37 VCCAXG42 Y38 VCCAXG43 D24 VCC44 VCC125 K15 VCCAXG44 D25 VCC45 VCC126 K16 D27 VCC46 D28 VCC47 VCC127 K18 VCC128 K19 7 OF 11 D30 VCC48 D31 VCC49 VCC129 K21 VCC130 K22 SANDY BRIDGE SKY D33 VCC50 VCC131 K24 D34 VCC51 VCC132 K25 D35 VCC52 VCC133 K27 D36 VCC53 VCC134 K28 E15 VCC54 VCC135 K30 E16 VCC55 VCC136 L13 E18 VCC56 VCC137 L14 E19 VCC57 VCC138 L15 E21 VCC58 VCC139 L16 E22 VCC59 VCC140 L18 E24 VCC60 VCC141 L19 E25 VCC61 VCC142 L21 E27 VCC62 VCC143 L22 E28 VCC63 VCC144 L24 E30 VCC64 VCC145 L25 E31 VCC65 VCC146 L27 E33 VCC66 VCC147 L28 E34 VCC67 VCC148 L30 E35 VCC68 VCC149 M14 F15 VCC69 VCC150 M15 F16 VCC70 VCC151 M16 F18 VCC71 VCC152 M18 F19 VCC72 VCC153 M19 F21 VCC73 VCC154 M21 F22 VCC74 VCC155 M22 F24 VCC75 VCC156 M24 V_1P8_SFR V_SA F25 VCC76 VCC157 M25 F27 VCC77 VCC158 M27 F28 VCC78 VCC159 M28 F30 VCC79 VCC160 M30 B F31 VCC80 VCC161 VCC81 6 OF 11 SANDY BRIDGE SKY 0805 C261 0805 C271 0805 C225 10UF/6.3V10UF/6.3V10UF/6.3V 0805 C226 10UF/6.3V VCORE 2 1 V_CPU_VCCIO J33H DDRVSM M13 VCCIO1 SKT_H2 A11 A7 VCCIO2 LGA115V5DDQ1 AJ13 AJ14 AA3 VCCIO3 VDDQ2 AJ23 AB8 VCCIO4 VDDQ3 AJ24 AF8 VCCIO5 VDDQ4 AR20 AG33 VCCIO6 VDDQ5 AR21 D AJ16 VCCIO7 VDDQ6 AR22 AJ17 VCCIO8 VDDQ7 AR23 AJ26 VCCIO9 VDDQ8 AR24 AJ28 VCCIO10 VDDQ9 AU19 AJ32 VCCIO11 VDDQ10 AU23 AK15 VCCIO12 VDDQ11 AU27 AK17 VCCIO13 VDDQ12 AU31 AK19 VCCIO14 VDDQ13 AV21 AK21 VCCIO15 VDDQ14 AV24 AK23 VCCIO16 VDDQ15 AV25 AK27 VCCIO17 VDDQ16 AV29 AK29 VCCIO18 VDDQ17 AV33 AK30 VCCIO19 VDDQ18 AW31 B9 VCCIO20 VDDQ19 AY23 D10 VCCIO21 VDDQ20 AY26 D6 VCCIO22 VDDQ21 AY28 E3 VCCIO23 VDDQ22 E4 VCCIO24 G3 VCCIO25 G4 VCCIO26 AJ20 J3 VCCIO27 VDDQ23 J4 VCCIO28 J7 J8 VCCIO29 VCCIO30 IO/SA/PLL L3 L4 VCCIO31 VCCIO32 POWER L7 VCCIO33 N3 VCCIO34 N4 VCCIO35 N7 VCCIO36 R3 VCCIO37 R4 VCCIO38 R7 VCCIO39 U3 VCCIO40 U4 VCCIO41 U7 VCCIO42 V_SA V8 VCCIO43 W3 VCCIO44 C VCCIO45 V_1P8_SFR H10 H11 H12 J10 K10 K11 L11 L12 M10 M11 M12 AK11 AK12 VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA9 VCCSA10 VCCSA11 VCCPLL1 VCCPLL2 8 OF 11 SANDY BRIDGE SKY B VAXG NC 0805 C227 0805 C228 0805 C229 0805 C230 0805 C231 0805 C232 0805 C233 0805 C234 0805 C235 0805 C236 0805 C237 0805 C238 0805 C239 0805 C240 0805 C241 0805 C242 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 1& 1& NC NC 0805 C249 0805 C250 0805 C251 0805 C252 0805 C253 0805 C254 0805 C255 0805 C256 0805 C257 0805 C258 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V V_CPU_VCCIO DDRVSM V_CPU_VCCIO A 0805 C259 0805 C260 10UF/6.3V 10UF/6.3V 1& NC NC 0805 C264 0805 C265 0805 C266 0805 C267 0805 C268 0805 C269 0805 C274 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 0805 C262 0805 C263 0805 C270 10UF/6.3V 10UF/6.3V 10UF/6.3V 0805 C272 0805 C273 0805 C275 0402 C282 10UF/6.3V 10UF/6.3V 10UF/6.3V0.1UF/16V 5 4 3 2 A ShenZhen Topstar Inductor Co.,Ltd Page Name SANDY BRIDGE_POWER Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 34 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 1 5 4 J33I A17 AM27 D A23 VSS1 A26 VSS2 SKT_H2 VSS91 AM3 VSS92 AM30 A29 VSS3 A35 VSS4 LGA1155 VSS93 AM36 VSS94 AM37 AA33 VSS5 VSS95 AM38 AA34 VSS6 VSS96 AM39 AA35 VSS7 AA36 VSS8 GND VSS97 AM4 VSS98 AM40 AA37 VSS9 VSS99 AM5 AA38 VSS10 VSS100 AN10 AA6 VSS11 VSS101 AN11 AB5 VSS12 VSS102 AN14 AC1 VSS13 VSS103 AN17 AC6 VSS14 VSS104 AN19 AD33 VSS15 VSS105 AN22 AD36 VSS16 VSS106 AN24 AD38 VSS17 VSS107 AN27 AD39 VSS18 VSS108 AN30 AD40 VSS19 VSS109 AN31 AD5 VSS20 VSS110 AN32 AD8 VSS21 VSS111 AN33 AE3 VSS22 VSS112 AN34 AE33 VSS23 VSS113 AN35 AE36 VSS24 VSS114 AN36 AF1 VSS25 VSS115 AN5 AF34 VSS26 VSS116 AN6 AF36 VSS27 VSS117 AN7 AF37 VSS28 VSS118 AN8 AF40 VSS29 VSS119 AN9 AF5 VSS30 VSS120 AP1 AF6 VSS31 VSS121 AP11 AF7 VSS32 VSS122 AP14 AG36 VSS33 VSS123 AP17 AH2 VSS34 VSS124 AP22 AH3 VSS35 VSS125 AP25 AH33 VSS36 VSS126 AP27 AH36 VSS37 VSS127 AP30 C AH37 VSS38 AH38 VSS39 VSS128 AP36 VSS129 AP37 AH39 VSS40 VSS130 AP4 AH40 VSS41 VSS131 AP40 AH5 VSS42 VSS132 AP5 AH8 VSS43 VSS133 AR11 AJ12 VSS44 VSS134 AR14 AJ15 VSS45 VSS135 AR17 AJ18 VSS46 VSS136 AR18 AJ21 VSS47 VSS137 AR19 AJ25 VSS48 VSS138 AR27 AJ27 VSS49 VSS139 AR30 AJ36 VSS50 VSS140 AR36 AJ5 VSS51 VSS141 AR5 AK1 VSS52 VSS142 AT1 AK10 VSS53 VSS143 AT10 AK13 VSS54 VSS144 AT12 AK14 VSS55 VSS145 AT13 AK16 VSS56 VSS146 AT15 AK22 VSS57 VSS147 AT16 AK28 VSS58 VSS148 AT17 AK31 VSS59 VSS149 AT2 AK32 VSS60 VSS150 AT25 AK33 VSS61 VSS151 AT27 AK34 VSS62 VSS152 AT28 AK35 VSS63 VSS153 AT29 AK36 VSS64 VSS154 AT3 AK37 VSS65 VSS155 AT30 AK4 VSS66 VSS156 AT31 AK40 VSS67 VSS157 AT32 AK5 VSS68 VSS158 AT33 AK6 VSS69 VSS159 AT34 AK7 VSS70 VSS160 AT35 AK8 VSS71 VSS161 AT36 AK9 VSS72 VSS162 AT37 AL11 VSS73 VSS163 AT38 AL14 VSS74 VSS164 AT39 AL17 VSS75 VSS165 AT4 B AL19 VSS76 VSS166 AT40 AL24 VSS77 VSS167 AT5 AL27 VSS78 VSS168 AT6 AL30 VSS79 VSS169 AT7 AL36 VSS80 VSS170 AT8 AL5 VSS81 VSS171 AT9 AM1 VSS82 VSS172 AU1 AM11 VSS83 VSS173 AU15 AM14 VSS84 VSS174 AU26 AM17 VSS85 VSS175 AU34 AM2 VSS86 VSS176 AU4 AM21 VSS87 VSS177 AU6 AM23 VSS88 VSS178 AU8 AM25 VSS89 VSS179 AV10 A4 VSS90 VSS180 AV39 VSS_NCTF1 VSS_NCTF2 9 OF 11 SANDY BRIDGE SKY A 5 4 3 J33J AB7 AD37 AG4 AJ29 AJ30 AJ31 AV34 AW34 P35 P37 P39 R34 R36 R38 R40 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 SKT_H2 LGA1155 SPARES RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 AT11 AP20 AN20 AU10 AY10 RSVD38 RSVD39 RSVD40 RSVD41 AF4 AB6 AE6 AJ11 A38 AU40 AW38 C2 D1 NCTF1 NCTF2 NCTF3 NCTF4 NCTF5 D38 RSVD42 C39 RSVD43 C38 RSVD44 J34 RSVD45 N34 RSVD46 10 OF 11 SANDY BRIDGE SKY 3 2 1 J33K AV11 G8 AV14 VSS181 VSS271 H1 AV17 AV3 VSS182 VSS183 SKT_H2 VSS272 VSS273 H17 H2 D AV35 AV38 VSS184 VSS185 LGA1155VVSSSS227745 H20 H23 AV6 VSS186 VSS276 H26 AW10 AW11 VSS187 VSS188 GND VSS277 H29 VSS278 H33 AW14 VSS189 VSS279 H35 AW16 VSS190 VSS280 H37 AW36 VSS191 VSS281 H39 AW6 VSS192 VSS282 H5 AY11 VSS193 VSS283 H6 AY14 VSS194 VSS284 H9 AY18 VSS195 VSS285 J11 AY35 VSS196 VSS286 J17 AY4 VSS197 VSS287 J20 AY6 VSS198 VSS288 J23 AY8 VSS199 VSS289 J26 B10 VSS200 VSS290 J29 B13 VSS201 VSS291 J32 B14 VSS202 VSS292 K1 B17 VSS203 VSS293 K12 B23 VSS204 VSS294 K13 B26 VSS205 VSS295 K14 B29 VSS206 VSS296 K17 B32 VSS207 VSS297 K2 B35 VSS208 VSS298 K20 B38 VSS209 VSS299 K23 B6 VSS210 VSS300 K26 C11 VSS211 VSS301 K29 C12 VSS212 VSS302 K33 C17 VSS213 VSS303 K35 C20 VSS214 VSS304 K37 C23 VSS215 VSS305 K39 C26 VSS216 VSS306 K5 C29 VSS217 VSS307 K6 C32 VSS218 VSS308 L10 C35 VSS219 C7 VSS220 VSS309 L17 VSS310 L20 C C8 VSS221 VSS311 L23 D17 VSS222 VSS312 L26 D2 VSS223 VSS313 L29 D20 VSS224 VSS314 L8 D23 VSS225 VSS315 M1 D26 VSS226 VSS316 M17 D29 VSS227 VSS317 M2 D32 VSS228 VSS318 M20 D37 VSS229 VSS319 M23 D39 VSS230 VSS320 M26 D4 VSS231 VSS321 M29 D5 VSS232 VSS322 M33 D9 VSS233 VSS323 M35 E11 VSS234 VSS324 M37 E12 VSS235 VSS325 M39 E17 VSS236 VSS326 M5 E20 VSS237 VSS327 M6 E23 VSS238 VSS328 M9 E26 VSS239 VSS329 N8 E29 VSS240 VSS330 P1 E32 VSS241 VSS331 P2 E36 VSS242 VSS332 P36 E7 VSS243 VSS333 P38 E8 VSS244 VSS334 P40 F1 VSS245 VSS335 P5 F10 VSS246 VSS336 P6 F13 VSS247 VSS337 R33 F14 VSS248 VSS338 R35 F17 VSS249 VSS339 R37 F2 VSS250 VSS340 R39 F20 VSS251 VSS341 R8 F23 VSS252 VSS342 T1 F26 VSS253 VSS343 T5 F29 VSS254 VSS344 T6 F35 VSS255 VSS345 U8 F37 VSS256 VSS346 V1 F39 VSS257 VSS347 V2 B F5 VSS258 VSS348 V33 F6 VSS259 VSS349 V34 F9 VSS260 VSS350 V35 G11 VSS261 VSS351 V36 G12 VSS262 VSS352 V37 G17 VSS263 VSS353 V38 G20 VSS264 VSS354 V39 G23 VSS265 VSS355 V40 G26 VSS266 VSS356 V5 G29 VSS267 VSS357 W6 G34 VSS268 VSS358 Y5 G7 VSS269 VSS359 Y8 AY37 VSS270 VSS360 B3 VSS_NCTF3 VSS_NCTF4 11 OF 11 SANDY BRIDGE SKY A ShenZhen Topstar Inductor Co.,Ltd Page Name SANDY BRIDGE_GND Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 35 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 2 1 5 4 3 2 1 3VDUAL +3D3V R244N0 C4 0 2 8.2K-5% P_PME_N U10A BH8 BF15 D R245 0 4 0 2 8.2K-5% P_DEVSEL_N <43> CK_PCH_33M_FB R246 0 4 0 2 8.2K-5% P_IRDY_N P_DEVSEL_N CK_PCH_33M_FB P_IRDY_N BH9 BD15 AV14 BF11 PAR DEVSEL# CLKIN_PCILOOPBACK PCIRST# AD0 BF17 AD1 BT7 AD2 AD3 BT13 BG12 D R247 0 4 0 2 8.2K-5% P_SERR_N P_PME_N P_SERR_N AV15 IRDY# BR6 PME# AD4 BN11 AD5 BJ12 GNT0/GPIO19 R248 0 4 0 2 8.2K-5% P_STOP_N P_STOP_N BC12 SERR# AD6 BU9 GNT1 SATA1GP Boot Device R249 0 4 0 2 8.2K-5% P_PLOCK_N P_PLOCK_N BA17 STOP# AD7 BR12 0 0 LPC R250 0 4 0 2 8.2K-5% P_TRDY_N P_TRDY_N BC8 PLOCK# AD8 BJ3 0 1 NAND R251 0 4 0 2 8.2K-5% P_PERR_N P_PERR_N BM3 TRDY# AD9 BR9 1 0 1 1 PCI SPI * R252 0 4 0 2 8.2K-5% P_FRAME_N P_FRAME_N BC11 PERR# FRAME# PCI AD10 AD11 BJ10 BM8 AD12 BF3 <38> SATA1GP C SATA1GP P_GNT_N0 P_GNT_N1 RRR222555345NNN000CCC444 000 2 2 2 1K-5% 1K-5% 1K-5% P_GNT_N2 R256N0 C4 0 2 1K-5% P_GNT_N3 R257N0 C4 0 2 1K-5% A16 SWAP OVERRIDE IF SAMPLED LOW +3D3V P_GNT_N0 P_GNT_N1 P_GNT_N2 P_GNT_N3 BA15 AV8 BU12 BE2 GNT0# GNT1#_GPIO51 GNT2#_GPIO53 GNT3#_GPIO55 AD13 BN2 AD14 BE4 AD15 BE6 AD16 BG15 AD17 BC6 AD18 AD19 BT11 BA14 C DESIGN NOTE: AD20 BL2 Wake internal PH on GNT DEFAULT SPI BOOT DEVCE R258 0 4 0 2 8.2K-5% R259 0 4 0 2 8.2K-5% R260 0 4 0 2 8.2K-5% R261 0 4 0 2 8.2K-5% P_REQ_N0 P_REQ_N1 P_REQ_N2 P_REQ_N3 P_REQ_N0 P_REQ_N1 P_REQ_N2 P_REQ_N3 BG5 BT5 BK8 AV11 REQ0# REQ1#_GPIO50 REQ2#_GPIO52 REQ3#_GPIO54 AD21 AD22 AD23 AD24 AD25 AD26 AD27 BC4 BL4 BC2 BM13 BA9 BF9 BA8 R262 0 4 0 2 8.2K-5% P_INTA_N P_INTA_N BK10 AD28 BF8 R263 0 4 0 2 8.2K-5% P_INTB_N R264 0 4 0 2 8.2K-5% P_INTC_N P_INTB_N P_INTC_N BJ5 PIRQA# BM15 PIRQB# AD29 AV17 AD30 BK12 R265 0 4 0 2 8.2K-5% P_INTD_N P_INTD_N BP5 PIRQC# AD31 R266 0 4 0 2 8.2K-5% P_INTE_N P_INTE_N BN9 PIRQD# R267 0 4 0 2 8.2K-5% P_INTF_N P_INTF_N AV9 PIRQE#_GPIO2 R268 0 4 0 2 8.2K-5% P_INTG_N P_INTG_N BT15 PIRQF#_GPIO3 BN4 R269 0 4 0 2 8.2K-5% P_INTH_N P_INTH_N BR4 PIRQG#_GPIO4 C_BE0# BP7 B PIRQH#_GPIO5 C_BE1# BG2 B C_BE2# BP13 C_BE3# DavidWang: 20110224 DVT FIX GHOST ISSUE 1 OF 12 COUGAR POINT SKY ShenZhen Topstar Inductor Co.,Ltd Page Name CPT_PCI A Size Project Name Rev A A F-H61 1.0 Date: Friday, March 15, 2013 Sheet 36 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 D U10B C V_1P05_PCH <32> DMI_MT_IR_0_DN <32> DMI_MT_IR_0_DP <32> DMI_IT_MR_0_DN <32> DMI_IT_MR_0_DP <32> DMI_MT_IR_1_DN <32> DMI_MT_IR_1_DP <32> DMI_IT_MR_1_DN <32> DMI_IT_MR_1_DP <32> DMI_MT_IR_2_DN <32> DMI_MT_IR_2_DP <32> DMI_IT_MR_2_DN <32> DMI_IT_MR_2_DP <32> DMI_MT_IR_3_DN <32> DMI_MT_IR_3_DP <32> DMI_IT_MR_3_DN <32> DMI_IT_MR_3_DP R277 0 4 0 2 49.9-1% DMI_COMP 100M_DMI_PCH_DN 100M_DMI_PCH_DP D33 B33 DMI0RXN J36 DMI0RXP H36 DMI0TXN A36 DMI0TXP B35 DMI1RXN P38 DMI1RXP R38 DMI1TXN B37 DMI1TXP C36 DMI2RXN H38 DMI2RXP J38 DMI2TXN E37 DMI2TXP F38 DMI3RXN M41 DMI3RXP P41 DMI3TXN B31 DMI3TXP E31 DMI_IRCOMP DMI_ZCOMP P33 R33 CLKIN_DMI_N CLKIN_DMI_P J20 L20 PERN1 F25 PERP1 DMI USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USB USBP9P USBP10N USBP10P USBP11N USBP11P BF36 BD36 BC33 BA33 BM33 BM35 BT33 BU32 BR32 BT31 BN29 BM30 BK33 BJ33 BF31 BD31 BN27 BR29 BR26 BT27 BK25 BJ25 BJ31 BK31 BD27 USBP0N <23> USBP0P <23> USBP1N <23> USBP1P <23> USBP8N <23> USBP8P <23> USBP9N <23> USBP9P <23> USBP10N <23> USBP10P <23> USBP11N <23> USBP11P <23> 3VDUAL -USBOC0 -USBOC1 -USBOC2 -USBOC3 -USBOC4 -USBOC5 -USBOC6 -USBOC7 R270 0 4 0 2 8.2K-5% R271 0 4 0 2 8.2K-5% R272 0 4 0 2 8.2K-5% R273 0 4 0 2 8.2K-5% R274 0 4 0 2 8.2K-5% R275 0 4 0 2 8.2K-5% R276 0 4 0 2 8.2K-5% R278 0 4 0 2 8.2K-5% DESIGN NOTE: Port6\7\12\13 are disabled on H61 AND OC[X]PINS REQUIRE PH TO VCCSUS3D3 WHEN CONFIGURED AS OC 100M_DMI_PCH_DN F23 PETN1 USBP12P BF27 100M_DMI_PCH_DP <24> HSI1_DN <24> HSI1_DP <24> HSO1_DN <24> HSO1_DP P20 PETP1 R20 PERN2 C22 PERP2 A22 PETN2 H17 PETP2 USBP12N USBP13P USBP13N OC0#_GPIO59 BK27 BJ27 BM43 BD41 -USBOC0 -USBOC1 -USBOC0 <23> J17 PERN3 OC1#_GPIO40 BG41 -USBOC2 E21 PERP3 OC2#_GPIO41 BK43 -USBOC3 0402 0402 R279 R280 B21 PETN3 OC3#_GPIO42 BP43 -USBOC4 10K-5% 10K-5% P17 PETP3 M17 PERN4 OC4#_GPIO43 BJ41 OC5#_GPIO9 BT45 -USBOC5 -USBOC6 -USBOC5 <23> F18 PERP4 OC6#_GPIO10 BM45 -USBOC7 <18> HSI5_DN <18> HSI5_DP <18> HSO5_DN <18> HSO5_DP E17 PETN4 N15 PETP4 M15 PERN5 B17 PERP5 C16 PETN5 J15 PETP5 PCI-E OC7#_GPIO14 USBRBIAS# USBRBIAS CLKIN_DOT_96N BP25 BM25 BD38 BF38 USBRBIAS_PCH R281 0 4 0 2 22.6-1% CK_96M_DREF_DN CK_96M_DREF_DP CAD NOTE: USBRBIS: TIE TRACE TOGETHER CLOSE TO PINS WITH LENGTH NO LONGER 450MILS TO RESISTOR L15 PERN6 CLKIN_DOT_96P A16 PERP6 A32 RBIAS_CPY R282 0 4 0 2 750-1% B15 PETN6 DMI2RBIAS J12 PETP6 H12 PERN7 CAD NOTE: F15 PERP7 rbias_phy: TIE TRACE TOGETHER CLOSE TO PINS F13 PETN7 WITH LENGTH NO LONGER 450MILS TO RESISTOR H10 PETP7 J10 PERN8 B13 PERP8 CK_96M_DREF_DN D13 PETN8 PETP8 CK_96M_DREF_DP B 2 OF 12 COUGAR POINT SKY 0402 0402 R283 10K-5% R284 10K-5% 1 D C B A A ShenZhen Topstar Inductor Co.,Ltd Page Name CPT_DMI/USB/PCIE Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 37 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 D D U10C <12,39> PWRGD_3V R285 0 4 0 2 0-5% PCH_MEPWROK_R BA50 BF50 BF49 BC46 CLINK CL_CLK1 CL_DATA1 CL_RST1# APWROK SATA0RXN SATA3 SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP AC56 AB55 AE46 AE44 AA53 AA56 AG49 AG47 AL50 SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1 SATA0RXN <22> SATA0RXP <22> SATA0TXN <22> SATA0TXP <22> SATA1RXN <22> SATA1RXP <22> SATA1TXN <22> SATA1TXP <22> BN21 SATA2RXN AL49 BT21 PWM0 SATA2RXP AL56 +3D3V DESIGN NOTE: FAN FUNCTION IS NOT SPUORT ON DESKTOP BM20 PWM1 BN19 PWM2 SATA2TXN AL53 SATA2TXP AN46 NOTE: Port2 and 3 are disabled on H61 10K-5% 0 4 0 2 R286 HEC_GP6 PWM3FAN SATA2 SATA3RXN SATA3RXP AN44 AN56 And only suport SATA2.0 10K-5% 0 4 0 2 R287 TEST_SETUP_MENU PCH_GP17_PU BT17 SATA3TXN AM55 DESIGN NOTE: 20K-5% 0 4 0 2 R288 SV_ADVANCE_GP48 10K-5% 0 4 0 2 R289 PCH_GP17_PU 10K-5% 0 4 0 2 R290 PCH_GP1_PU 10K-5% 0 4 0 2 R291 PCH_GP7_PU 10K-5% 0 4 0 2 R292 PCH_GP68_PU 10K-5% 0 4 0 2 R293 BOARD_DIFF 10K-5% 0 4 0 2 R294 PCH_GP71_PU 10K-5% 0 4 0 2 R297 PCH_CONFIG_JUMPER 10K-5% 0 4 0 2 R298 GP38_CRB_DETECT PCH_GP1_PU HEC_GP6 PCH_GP7_PU PCH_GP68_PU TEST_SETUP_MENU BOARD_DIFF PCH_GP71_PU BR19 BA22 BR16 BU16 BM18 BN17 BP15 BC43 TACH0_GPIO17 TACH1_GPIO1 TACH2_GPIO6 TACH3_GPIO7 TACH4_GPIO68 TACH5_GPIO69 TACH6_GPIO70 TACH7_GPIO71 SATA3TXP SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP AN49 AN50 AT50 AT49 AT46 AT44 AV50 AV49 SATA_RXN4 SATA_RXP4 SATA_TXN4 SATA_TXP4 SATA_RXN5 SATA_RXP5 SATA_TXN5 SATA_TXP5 SATA4RXN <22> SATA4RXP <22> SATA4TXN <22> SATA4TXP <22> SATA5RXN <22> SATA5RXP <22> SATA5TXN <22> SATA5TXP <22> The check list requre down to gnd through 8.2k if unused as GP OR GPIO R295N0 C4 0 2 1K-5% CDC_DWN_DISABLE R296 0 4 0 2 1K-5% DMI RX TERMINATION VOLTAGE OVERRIDE +3D3V C PCH_CONFIG_JUMPER GP38_CRB_DETECT BA53 BE54 SST SCLOCK_GPIO22 AF55 CLKIN_SATA_N AG56 CLKIN_SATA_P CK_SATA_PCH_DN CK_SATA_PCH_DP C R299N0 C4 0 2 1K-5% PCH_GP37 R300 0 4 0 2 1K-5% FDI RX TERMINATION VOLTAGE OVERRIDE GP39_GFX_CRB_DETECT SV_ADVANCE_GP48 BF55 SLOAD_GPIO38 AW53 SDATAOUT0_GPIO39 BF57 SATALED# AJ55 PCH_SATA_LED_N PCH_SATA_LED_N <15> V_1P05_PCH +3D3V 10K-5%N0 4C0 2 R301 10K-5% 0 4 0 2 R303 GP39_GFX_CRB_DETECT SDATAOUT1_GPIO48 SATAICOMPI AJ53 SATAICOMPO SATARBIAS_PCH R302 0 4 0 2 37.4-1% GP37 GFX STYLE GP49 BOARD STYLE GPIO AY20 NC SATA0GP_GPIO21 SATA1GP_GPIO19 SATA2GP_GPIO36 SATA3GP_GPIO37 SATA4GP_GPIO16 SATA5GP_GPIO49 BC54 AY52 BB55 BG53 AU56 BA56 SATA0GP SATA1GP CDC_DWN_DISABLE PCH_GP37 SATA4GP AIO_DETECT SATA1GP <36> 0 NORMAL GFX 1 CUSTOMER GFX 0 NON AIO 1 AIO AIO_DETECT R304N0 C4 0 2 10K-5% R305 0 4 0 2 10K-5% +3D3V AE54 SATA3COMPI AE52 SATA3RCOMPO SATA3COMP_PCH R306 0 4 0 2 49.9-1% V_1P05_PCH AE50 TP16 AC52 RBIAS_SATA3 SATA3RBIAS R307 0 4 0 2 750-1% +3D3V COUGAR POINT A20GATE HOST INIT3_3V# RCIN# SERIRQ THRMTRIP# PECI PMSYNCH BB57 BN56 BG56 AV52 E56 H48 F55 3 OF 12 SKY INIT3_3VB R309 0 4 0 2 0-5% R311N0 C4 0 2 0-5% A20GATE <12> KBRST_N <12> SER_IRQ <12> H_THERMTRIP_N <31> H_PECI <12,31> H_PM_SYNC_0 <31> 1K-5% 0N4 0C2 R314 SATA0GP SATA1GP SATA4GP A20GATE INIT3_3VB KBRST_N SER_IRQ PCH_SATA_LED_N R308 0 4 0 2 10K-5% R310 0 4 0 2 10K-5% R312 0 4 0 2 10K-5% R313 0 4 0 2 10K-5% R315 0 4 0 2 10K-5% R316 0 4 0 2 10K-5% R317 0 4 0 2 10K-5% B B CK_SATA_PCH_DN CK_SATA_PCH_DP 0402 0402 R318 10K-5% R319 10K-5% A A ShenZhen Topstar Inductor Co.,Ltd Page Name SATA/FAN Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 38 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 +3D3V 3VDUAL U10D FP_AUD_DETECT 10K-5% 0 4 0 2 R322 BA20 JME(2-3) <12> L_AD0 <12> L_AD1 <12> L_AD2 <12> L_AD3 BK15 BJ17 BJ20 BG20 BK17 LDRQ1#_GPIO23 FWH0_LAD0 FWH1_LAD1 FWH2_LAD2 LPC FWH3_LAD3 YELLOW DavidWang: 20110224 <12> L_FRAME_N BG17 LDRQ0# FWH4_LFRAME# D DVT ADD JME JUMPER R325 0 4 0 2 33-5% AUD_LINK_BCLK_RBU22 <25> AUD_LINK_BCLK R339 0 4 0 2 33-5% AUD_LINK_RST_R_BNC22 HDA_BCLK 3VDUAL CAD NOTE: <25> AUD_LINK_RST BD22 HDA_RST# JME PLACE AT PCH CODEC R343 0 4 0 2 1K-5% 1 2 AUD_LINK_SDO_R <25> AUD_LINK_SDI2 BF22 R327 0 4 0 2 33-5% AUD_LINK_SDI2_R BK22 BJ22 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 AUDIO R347 0 4 0 2 1K-5% 3 R348 0 4 0 2 33-5% AUD_LINK_SDO_R BT23 HDA_SDIN3 <25> AUD_LINK_SDO R350 0 4 0 2 33-5% AUD_LINK_SYNC_RBP23 HDA_SDO <25> AUD_LINK_SYNC HDA_SYNC AUD_LINK_SDO_R----IBX INTERPOSER NAND POWERED BY CORE WHEN SAMPLED LOW.STBY WHEN SAMPLED HI CPT FLASH DESCRIPTOR OVERRIDE.HI FOR OVERRIDE VCCQ PWR WE<<L22L00>>SESSLPPII__MMIOSSOI__FFLLAASSHH <20> SPI_CS0_FLASH <20> SPI_CLK_FLASH TP1 SPI_CS1_N AU53 AT55 AT57 AR54 AR56 SPI_MOSI SPI_MISO SPI_CS0# SPI_CLK SPI_CS1# SPI 3VDUAL BMBUSY#_GPIO0 CLKRUN#_GPIO32 HDA_DOCK_EN#_GPIO33 STP_PCI#_GPIO34 GPIO35 GPIO8 LAN_PHY_PWR_CTRL_GPIO12 HDA_DOCK_RST#_GPIO13 GPIO15 GPIO24_MEM_LED GPIO28 SLP_LAN#_GPIO29 PCIECLKRQ2#_GPIO20 PCIECLKRQ5#_GPIO44 PCIECLKRQ6#_GPIO45 PCIECLKRQ7#_GPIO46 GPIO57 SYS_PWROK RI# PLTRST# WAKE# SLP_A# SLP_S3# SLP_S4# AW55 FP_AUD_DETECT BC56 PCH_GPO32_PD BC25 SOP_ENABLE_GP33 BL56 PCH_PU_GP34 BJ57 2X12_POWER_DETECT FP_AUD_DETECT <25> BP51 BK50 BA25 BM55 BP53 BJ55 BH49 AV43 BL54 AV44 BP55 BT53 BJ53 BJ48 BK48 BC44 BC41 BM53 BN52 IGC_EN_N LAN_DISABLE_N IO_PME_N 1_WATT_CTRL_1 0-5% N0 4C0 2 R354 V_MINI_PCIE_EN SLP_LAN_N PCH_GP20_PU PCH_GP44 PCH_GP45 PCH_GP46 GP57_SV_DETECT IO_PME_N <12> H_SKTOCC_R_N <31,46> DVT:ADD R354 位置 PCH_RI_PU PCH_SYSPWROK <16> WAKE_N PCH_SLP_A PLTRST_N <12,16> WAKTEP_2N <18,24> SLP_S3_N <12,16,17,50> SLP_S4_N <12,49> PCH_GPO32_PD PCH_PU_GP34 PCH_GP20_PU 10K-5% 0 4 0 2 R328 10K-5% 0 4 0 2 R323 10K-5% 0 4 0 2 R331 1K-5%N0 4C0 2 R332 SOP_ENABLE_GP33 2X12_POWER_DETECT 10K-5% 0 4 0 2 R334 SYS_RESET_L 10K-5% 0 4 0 2 R337 IGC_EN_N 10K-5% N0 4C0 2 R351 3VDUAL IGC_EN_N R356 0 4 0 2 1K-5% THROUGH MODE CLOCK VALIDATION STRAP EMPTY JUMPER FOR BUFFER THROUGH MODE Is not need for soft strap 10K-5%N0 4C0 2 R329 LAN_DISABLE_N 10K-5% 0 4 0 2 R330 SLP_LAN_N 10K-5%N0 4C0 2 R324 IO_PME_N 10K-5% 0 4 0 2 R335 PCH_RI_PU 10K-5% 0 4 0 2 R336 WAKE_N 1K-5% 0 4 0 2 R338 D 1_WATT_CTRL_2 10K-5% 0 4 0 2 R326 SUS_PWR_ACK 10K-5% 0 4 0 2 R341 SUS_WARNB 10K-5% 0 4 0 2 R342 LED_DRIVE_GP27 10K-5% 0 4 0 2 R345 PCH_GPI31_PU 10K-5% 0 4 0 2 R346 SLP_SUSB 10K-5%N0 4C0 2 R349 FP_RST_N 220-5%N0 4C0 2 R353 3VDUAL BH50 R359N0 C4 0 2 1K-5A%UD_LINK_SYNC_R SLP_S5#_GPIO63 BN54 SUS_STAT#_GPIO61 BA47 TP_SUSCLK TP3 3VDUAL OD PLL VR SUPPLY SEL SUSCLK_GPIO62 AV46 1_WATT_CTRL_2 1.8V SUPPLY WHEN SAMPLED LOW BATLOW#_GPIO72 BP45 SUS_PWR_ACK 1_WATT_CTRL_1 4.7K-5% 0 4 0 2 R360 PCH_GP44 10K-5% 0 4 0 2 R361 1.5V SUPPLY WHEN SAMPLED HIGH PCH_RTCX1 PCH_RTCX2 PCH_RTCRST SRTCRSTB BR39 BN39 BT41 BN37 RTCX1 RTCX2 RTCRST# SUSACK# BU46 SUSWARN#-SUS_PWR_DN_ACK-GPIO30 BG46 DRAMPWROK SUS_WARNB ? H_DRAMPWRGD <31> LOW:TLS CIPHER SUITE WITH NO CONFIDENTIALITY. HIGH:TLS CIPHER SUITE WITH CONFIDENTIALITY. PCH_GP45 PCH_GP46 47K-1% 0 4 0 2 R364 GP57_SV_DETECT 10K-5% 0 4 0 2 R362 1K-5% 0 4 0 2 R363 10K-5% N0 4C0 2 R365 PCH_INTRUDERBM38 SRTCRST# BJ43 LED_DRIVE_GP27 <12,38> PWRGD_3V <16> PCH_RSMRST_N PWRGD_3V BJ38 PCH_RSMRST_NBK38 PCH_INTVRMENBN41 INTRUDER# PWROK RSMRST# RTC PM_GPIO(DSWGP)IO27 BG43 GPIO31 BD43 PCH_GPI31_PU SLP_SUSB OD PLL VR ENABLE DISABLED WHEN SAMPLED LOW 3VDUAL PCH_RTCX1 PCH_RTCX2 <16> PCH_DPWROK BT37 INTVRMEN DSWODVREN BR42 DPWROK DSWVRMEN PCH_PORT80_LEDBN49 SLP_SUS# PWRBTN# SYS_RESET# SPKR BT43 BE52 BE56 SYS_RESET_1L00-5% 0 4 0 2 R368 SW_ON_N <12> FP_RST_N <15,31> SPKR <15> R366N0 C4 0 2 1K-5% V_MINI_PCIE_EN1K-5% 0 4 0 2 R367 R369 0 6 0 3 10M-5% C X2 32.768KHz <18,29,30> SMB_CLK_MAIN <18,29,30> SMB_DATA_MAIN BT47 Mismatch 500MIL BR49 PCH_GP60 BU49 SMLINK0_CLK BT51 SMBALERT#_GPIO11 SMBCLK SMBDATA SML0ALERT#_GPIO60 D53 PROCPWRGD H_PWRGD <31> 1K-5%N0 4C0 2 R370 PCH_GP44 C 1 2 SMLINK0_DATA BM50 SML0CLK DFX TEST MODE RINGS OSCILLATOR BYPASS WHEN LOW PCHHOT BR46 SML0DATA 3 C276 0402 4 0402 C277 <12> SML1CLK_PCH <12> SML1DATA_PCH SML1CLK_PCH BJ46 SML1ALERT#_PCHHOT#_GPIO74 SML1DATA_PCH BK46 SML1CLK_GPIO58 SML1DATA_GPIO75 10K-5% N0 4C0 2 R373 PCH_GP45 18PF/50V 18PF/50V SMB BC49 PCH_JTAG_RST_R TP12 BA43 PCH_JTAG_TCK_FILTER 4 OF 12 JTAG(SUS) JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS BC52 PCH_JTAG_TDI BF47 PCH_JTAG_TDO BC50 PCH_JTAG_TMS JTAG CLK FILTER BYPASS WHEN LOW 100-1% N0 4C0 2 R374 PCH_GP46 DavidWang: 20110225 DVT CHANGE FOOTPRINT TO xd4_r_70 COUGAR POINT SKY 0603 06030603 VCCRTC DESIGN NOTE: 3VDUAL DC DELAY TIME 18ms~25ms 3VDUAL 3VDUAL 3VDUAL 3VDUAL 1 3VDUAL D11 1 3 1K-5% 0 4 0 2 R384 2 BAT54C SOT23 R375 0 4 0 2 20K-1% PCH_RTCRST C278 R376 0 4 0 2 20K-1% SRTCRSTB C279 1UF/16V 1UF/16V R381 0 4 0 2 1M-5% PCH_INTRUDER R385 0 4 0 2 390K-5% PCH_INTVRMENR38210 4&0 2 1K-5% IINTEGRATED 1.05V SUS VRM ENABLE SUS VRM ENABLED WHEN SAMPLED HIGH R386 0 4 0 2 390K-5% DSWODVREN 0402 R383 20K-1% PCH_JTAG_RST_R PCH_JTAG_TCK_FILTER PCH_JTAG_TDI 0402 R377 200-1% PCH_JTAG_TDO R388 R389 0402 R378 200-1% PCH_JTAG_TMS R390 0402 R379 200-1% R391 0402 R380 4.7K-5% SLP_S3_N 3VDUAL 0402 0402 0402 0402 + BAT BAT DSWODVREN HI FOR ALL PRODUCTS EVEN NOT WHEN NOT SUPPORTING DSW 0402 R387 10K-5% 51-5% 100-1% 100-1% 100-1% 0402 R392 - C280 1UF/16V SIO_VBAT B 4.7K-5% B 2 SIO_VBAT SLP_S4_N 正极+ BATTERY 负极CR2032 JCMOS 1 PCH_RTCRST 2 3 C281 0402 0.1UF/16V 0402 JCMOS(1-2) YELLOW R393 4.7K-5% 3VDUAL PCH_GP20_PU R444 0 4 0 2 0-5% SIO_LPC_SMI SIO_LPC_SMI <12> R394 0 4 0 2 10K-5% PCH_PORT80_LED R395 0 4 0 2 2.7K-5% R396 0 4 0 2 2.7K-5% SMB_CLK_MAIN SMB_DATA_MAIN R397 0 4 0 2 2.2K-5% R398 0 4 0 2 2.2K-5% R399 0 4 0 2 2.2K-5% R400 0 4 0 2 10K-5% R401 0 4 0 2 2.2K-5% R402 0 4 0 2 2.2K-5% PCH_GP60 SMLINK0_CLK SMLINK0_DATA PCHHOT SML1CLK_PCH SML1DATA_PCH A A CAD NOTE: PLACE NEAR CLOCK DESIGN NOTE: RESUME AND MAIN LOGIC ShenZhen Topstar Inductor Co.,Ltd Page Name CPT_LPC/GPIO/HD Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 39 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 D U10E M48 AB50 <31> NVR_CLE R47 Y41 RESERVED_29 DF_TVS RESERVED_22 RESERVED_21 Y50 AB49 M50 RESERVED_6 RESERVED_14 AB44 M49 RESERVED_4 RESERVED_13 U49 U43 RESERVED_3 RESERVED_12 R44 J57 RESERVED_2 RESERVED_11 U50 RESERVED_1 RESERVED_10 U46 RESERVED_9 U44 RESERVED_8 H50 NVRAMRREESSEERRVVEEDD__270 K46 L56 RESERVED_19 J55 C RESERVED_18 RESERVED_17 F53 H52 RESERVED_16 E52 RESERVED_15 RESERVED_28 RESERVED_27 RESERVED_26 RESERVED_25 K50 K49 AB46 G56 RESERVED_24 Y44 L53 RESERVED_23 RESERVED_5 R50 5 OF 12 COUGAR POINT SKY B 1 D C B ShenZhen Topstar Inductor Co.,Ltd Page Name CPT_NVRAM A Size Project Name Rev A A F-H61 1.0 Date: Friday, March 15, 2013 Sheet 40 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 D C B A 5 4 U10G H31 J31 TP21 C29 E29 TP25 TP29 TP33 J27 L27 F28 E27 TP22 TP26 TP30 TP34 J25 L25 C26 TP23 TP27 B27 TP31 TP35 L22 J22 TP24 B25 TP28 D25 TP32 TP36 3 2 FDILINK C42 FDI_RXN0 B43 FDI_RXP0 FDI_RXN1 FDI_RXP1 F45 F43 H41 FDI_RXN2 J41 FDI_RXP2 FDI_RXN3 FDI_RXP3 C46 D47 B45 FDI_RXN4 A46 FDI_RXP4 FDI_RXN5 FDI_RXP5 B47 C49 J43 FDI_RXN6 H43 FDI_RXP6 FDI_RXN7 FDI_RXP7 M43 P43 B51 FDI_FSYNC0 FDI_LSYNC0 FDI_FSYNC1 E49 C52 D51 FDI_LSYNC1 FDI_INT H46 FDI_TX_0_DN <32> FDI_TX_0_DP <32> FDI_TX_1_DN <32> FDI_TX_1_DP <32> FDI_TX_2_DN <32> FDI_TX_2_DP <32> FDI_TX_3_DN <32> FDI_TX_3_DP <32> FDI_TX_4_DN <32> FDI_TX_4_DP <32> FDI_TX_5_DN <32> FDI_TX_5_DP <32> FDI_TX_6_DN <32> FDI_TX_6_DP <32> FDI_TX_7_DN <32> FDI_TX_7_DP <32> FDI_FSYNC0 FDI_LSYNC0 FDI_FSYNC1 FDI_LSYNC1 <32> <32> <32> <32> FDI_INT <32> 7 OF 12 COUGAR POINT SKY 1 D C B ShenZhen Topstar Inductor Co.,Ltd Page Name CPT_FDU Size Project Name A F-H61 Rev A 1.0 Date: Friday, March 15, 2013 Sheet 41 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 4 3 2 1 5 4 3 2 1 D D U10F T1 AR4 VGA_HSYNC R405 0 4 0 2 33-5% VGA_HSYNC_3V N2 DDPB_HPD CRT_HSYNC AR2 VGA_VSYNC R406 0 4 0 2 33-5% VGA_VSYNC_3V <21> PCH_DVI_HPD M1 DDPC_HPD DDPD_HPD CRT_VSYNC AN6 VGA_RED R407 0 4 0 2 150-1% R8 CRT_RED AN2 VGA_GREEN R408 0 4 0 2 150-1% R9 DDPB_AUXP U14 DDPB_AUXN U12 N6 DDPC_AUXP DDPC_AUXN DISPLAY CRT_GREEN CRT_BLUE CRT_IRTN AM1 VGA_BLUE AM6 R409 0 4 0 2 150-1% VGA_HSYNC_3V VGA_VSYNC_3V VGA_HSYNC_3V <21> VGA_VSYNC_3V <21> R6 DDPD_AUXP VGA_RED DDPD_AUXN VGA_GREEN VGA_RED <21> R14 AW1 VGA_PCH_DDCSDA VGA_BLUE VGA_GREEN <21> R12 DDPB_0P CRT_DDC_DATA AW3 VGA_PCH_DDCSCL VGA_PCH_DDCSDA <21> VGA_BLUE <21> M11 DDPB_0N CRT_DDC_CLK VGA_PCH_DDCSCL <21> M12 DDPB_1P AT3 VGA_DACREFSETR412 0 4 0 2 1K-1% H8 DDPB_1N DAC_IREF C K8 DDPB_2P C L5 DDPB_2N M3 DDPB_3P L2 DDPB_3N J3 DDPC_0P Y18 G2 DDPC_0N TP6 Y17 G4 DDPC_1P TP7 AB18 F3 DDPC_1N TP8 AB17 F5 DDPC_2P TP9 E4 DDPC_2N E2 DDPC_3P <21> DDSP_D_TX_0_DP <21> DDSP_D_TX_0_DN <21> DDSP_D_TX_1_DP <21> DDSP_D_TX_1_DN <21> DDSP_D_TX_2_DP <21> DDSP_D_TX_2_DN <21> DDSP_D_TX_3_DP <21> DDSP_D_TX_3_DN DDSP_D_TX_0_DP DDSP_D_TX_0_DN DDSP_D_TX_1_DP DDSP_D_TX_1_DN DDSP_D_TX_2_DP DDSP_D_TX_2_DN DDSP_D_TX_3_DP DDSP_D_TX_3_DN D5 B5 C6 DDPC_3N DDPD_0P DDPD_0N D7 DDPD_1P B7 DDPD_1N C9 E11 DDPD_2P DDPD_2N B11 DDPD_3P DDPD_3N U2 T3 SDVO_INTP SDVO_INTN DDPC_CTRLCLK AL12 AL14 DDPC_CTRLDATA B W3 U5 SDVO_STALLP SDVO_STALLN AL9 DDPD_CTRLCLK DDPD_CTRLDATA AL8 PCH_I2C_CLK_DVI PCH_I2C_DATA_DVI PCH_I2C_CLK_DVI <21> PCH_I2C_DATA_DVI <21> B U8 U9 SDVO_TVCLKINP SDVO_TVCLKINN AL15 SDVO_CTRLCLK AL17 SDVO_CTRLDATA 6 OF 12 COUGAR POINT SKY ShenZhen Topstar Inductor Co.,Ltd A A Page Name CPT_DISPLAY Size B Project Name F-H61 Date: Friday, March 15, 2013 Sheet 42 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 U10H CLKIN_GND1_N CLKIN_GND1_P R27 CK_100M_CPHY_PCH_IN_DN P27 CK_100M_CPHY_PCH_IN_DP R414 0 4 0 2 10K-5% R415 0 4 0 2 10K-5% AT11 CLKOUT_PCI0 W53 CK_CSI_PCH_IN_DN CLKIN_GND0_N CLKIN_GND0_P V52 CK_CSI_PCH_IN_DP R416 0 4 0 2 10K-5% R417 0 4 0 2 10K-5% D AN14 R52 D CLKOUT_PCI1 CLKOUT_ITPXDP_N N52 <36> CK_PCH_33M_FB R413 0 4 0 2 22-5% CK_P_33M_PCI2AT12 CLKOUT_PCI2 CLKOUT_ITPXDP_P AE2 <12> CK_PCH_33M_SIO R419 0 4 0 2 22-5%CLKOUT_PCI_3_R AT17 CLKOUT_PCI3 CLKOUT_PCIE7N CLKOUT_PCIE7P AF1 AT14 CLKOUT_PCI4 P31 CLKOUT_DMI_N CLKOUT_DMI_P R31 CK_PE_100M_MCP_DN <31> CK_PE_100M_MCP_DP <31> <12> CK_PCH_48M_SIO R420 0 4 0 2 22-5% AT9 BA5 AW5 BA2 CLKOUTFLEX0_GPIO64 CLKOUTFLEX1_GPIO65 CLKOUTFLEX2_GPIO66 CLKOUTFLEX3_GPIO67 N56 CLKOUT_DP_N M55 CLKOUT_DP_P CLKOUT_PCIE0N AE6 AC6 CLKOUT_PCIE0P CK_PCIE1X_1_DN <18> CK_PCIE1X_1_DP <18> V_1P05_PCH R421 0 4 0 2 90.9-1% XCLK_RCOMP AL2 XCLK_RCOMP CLKOUT_PCIE1N CLKOUT_PCIE1P AA5 W5 CK_14M_PCH AN8 REFCLK14IN AB12 CLKOUT_PCIE2N AB14 CLKOUT_PCIE2P CK_GLAN_DN <24> CK_GLAN_DP <24> AB9 R422 CLOCK CLKOUT_PCIE3N AB8 CLKOUT_PCIE3P 0402 C 10K-5% CLKOUT_PCIE4N Y9 Y8 C CLKOUT_PCIE4P AF3 CLKOUT_PCIE5N CLKOUT_PCIE5P AG2 AB3 CLKOUT_PCIE6N CLKOUT_PCIE6P AA2 XTAL_25M_PCH_OUATJ5 XTAL_25M_PCH_IN AJ3 XTAL25_OUT XTAL25_IN CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_PEG_B_N CLKOUT_PEG_B_P AG8 AG9 AE12 AE11 CK_PE_16PORT_PCH_DN <18> CK_PE_16PORT_PCH_DP <18> XTAL_25M_PCH_OUT XTAL_25M_PCH_IN B R423 0 6 0 3 1M-5% B X3 11 2 25MHz 0402 C284 20PF/50V 0402 C285 20PF/50V A 5 COUGAR POINT 8 OF 12 4 3 ShenZhen Topstar Inductor Co.,Ltd A Page Name CPT_CLOCK SKY Size B Project Name F-H61 Rev 1.0 Date: Friday, March 15, 2013 Sheet 43 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 2 1 5 4 3 2 V_1P05_PCH V_1P05_PCH U10I U10K F20 AC24 1.6A F30 VCCIO_24 VCCCORE_1 AC26 V_REF5V_SUS V_REF5V1MA BF1 V25 VCCIO_25 VCCCORE_2 AC28 3VDUAL V5REF 159MA C286 0.1UF/16V 0402 V27 VCCIO_26 V31 VCCIO_27 VCCCORE_3 AC30 VCCCORE_4 AC32 1MA BT25 V5REF_SUS VCCVRM_1 AJ1VCC_XCKPLL R2 VCCADMI_VRM_R2 R427 0 4 0 2 0-5% R424 0 4 0 2 0-5% V_1P8_SFR V33 VCCIO_28 VCCCORE_5 AE24 +3D3V 10MA AV28 VCCVRM_4 R54VCC_XCKPLL_AFDI Y24 VCCIO_29 VCCCORE_6 AE28 VCCSUSHDA VCCVRM_3 R56 R428 0 4 0 2 0-5% Y26 VCCIO_30 VCCCORE_7 AE30 409MA AU20 VCCVRM_2 Y30 VCCIO_31 VCCCORE_8 AE32 AV20 VCC3_3_9 Y32 VCCIO_32 VCCCORE_9 AE34 PLACE NEAR PCH Near AU22 C288 AU22 VCC3_3_10 Y34 VCCIO_33 VCCIO_34 4.07A VCCCORE_10 AE36 VCCCORE_11 AG32 VCCCORE_12 AG34 3VDUAL 0603 V_3P3_EPW 1UF/16V R425N0 C4 0 2 0-5% 20MA AN52 VCC3_3_7 VCCSPI T55 VCCPNAND_01 T57 VCCPNAND_02 V_1P8_SFR VCCCORE_13 AJ32 VCCCORE_14 AJ34 +5V_SB D12 ? C289 0603 +3D3V C317 0603 0402 C287 D VCCCORE_15 AJ36 VCCCORE_16 AL32 1 BAT54C 3 1UF/16V AL38 VCC3_3_5 AN38 1UF/16V 0.1UF/16V SOT23 VCCCORE_17 AL34 2 VCC3_3_6 VCCCORE_18 AN32 VCCCORE_19 AN34 VCCCORE_20 AR32 R426 0 4 0 2 10-5% V_REF5V_SUS POWER BC17 VCCCORE_21 AR34 C291 VCC3_3_2 BD17 AA34 VCCCORE_22 0402 C290 0603 3VDUAL V_3P3_EPW VCC3_3_3 BD20 AA36 VCCIO_22 VCCIO_23 0.1UF/16V 1UF/16V VCC3_3_4 V22 Y20 VCCIO_35 Y22 VCCIO_36 VCCIO_37 POWER +5V +3D3V D13 1 BAT54C 3 2 R429 0 4 0 2 0-5% A12 VCC3_3_8 AF57 VCC3_3_1 +3D3V C292 0402 0.1UF/16V 0402 C293 0.1UF/16V SOT23 R430 0 4 0 2 10-5% V_REF5V 0402 C294 0.1UF/16V C295 0603 1UF/16V 1 D 3VDUAL V_CPU_VCCIO V_1P05_ME BT35 AG24 1.61A VCCSUS3_3_11 57MA B41 VCCASW_4 AG26 AV30 97MA VCCDMI_2 VCCASW_5 AG28 VCCSUS3_3_2 AV32 E41 VCCASW_6 AJ24 C297 C298 VCCSUS3_3_3 AY31 C299 0402 C296 V_1P05_PCH VCCDMI_1 VCCASW_7 AJ26 VCCASW_8 AJ28 0603 0603 1UF/16V 1UF/16V VCCSUS3_3_4 AY33 VCCSUS3_3_5 BJ36 0402 0.1UF/16V 0.1UF/16V C AL40 AN40 VCCIO_8 VCCASW_9 AL24 VCCASW_10 AL28 VCCSUS3_3_6 BK36 VCCSUS3_3_7 BM36 C AN41 VCCIO_9 VCCASW_11 AN22 VCCSUS3_3_8 VCCIO_10 VCCASW_12 AN24 AT40 AG38 VCCASW_13 AN26 VCCSUS3_3_9 AU38 V_3P3_A 3VDUAL AG40 VCCIO_20 VCCASW_14 AN28 VCCSUS3_3_10 VCCIO_21 AG41 VCCASW_15 AR24 VCCASW_16 AR26 +3D3PV CI U31 VCCSUS3_3_1 R431 0 4 0 2 0-5% VCCIO_7 VCCASW_17 AR28 AV40 3MA C300 0.1UF/16V 0402 VCCASW_18 AR30 VCCDSW3_3 VCCASW_19 AR36 VCCASW_20 AR38 D55 V_PROC_IO B56 1MA+1MAV_CPU_VCCIO VCCASW_21 AU30 C301 C302 C305 C306 V_PROC_IO_NCTF VCCASW_22 AU36 0402 0402 0603 0805 A39 V_1P1_USBC307 1UF/16V NC 0603 VCCASW_23 V_1P05_ME 0.1UF/16V0.1UF/16V 1UF/16V 10UF/6.3V DCPSUS_3 AA32 VCCRTC DCPSUS_1 VCCSATA_PLL_PCH V_1P05_PCH VCCDMI_PLL_PCH U56 BA38 B53 VCCAPLLSATA VCCIO_19 VCCAPLLEXP VCCASW_3 VCCASW_2 VCCASW_1 VCCDIFFCLKN_1 VCCDIFFCLKN_2 VCCDIFFCLKN_3 VCCCLKDMI VCCIO_18 VCCSSC_1 VCCSSC_2 VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_4 AU34 AV36 AU32 V_1P05_PCH AE15 55MA AE17 AG15 AJ20 V_1P05_PCH_SRC2MA AE40 AC20 AE20 105MA AV24 AV26 AY25 AY27 V_1P05_PCH V_3P3_DAC_FB_R VCCA_DPLLA VCCA_DPLLB 68MA AT1 100MA AB1 100MA AC2 VCCADAC VCCADPLLA VCCADPLLB VCCRTC DCPRTC DCPRTC_NCTF DCPSUS_2 DCPSUSBYP DCPSST 11 OF 12 0402 0402 BU42 C308 0.1UF/16V BR54 V_1P5_RTC_INTC309 BT56 AT41 TP4 0.1UF/16V AV41 TP5 BA46 V_1P5_STBY_INTC310 0.1UF/16V 0402 TP6 TP_VCCIPL_PLL_PCH C54 VCCAFDIPLL V36 VCCIO_13 COUGAR POINT SKY Y36 VCCIO_12 3VDUAL USB B TP7 TP_VCCCLK_PLL_PCHAL5 VCCACLK AJ38 VCCIO_11 CLASSIC B VCCUSB3_PLL_PCH A19 VCCAPLLDMI2 9 OF 12 Y28 VCCIO_14 FILTER C311 C312 V_1P05_PCH COUGAR POINT SKY +3D3V 0402 0402 0.1UF/16V0.1UF/16V VCCPUSB PLACE V3P3_STBY DCPL CAPS AT ENDS OF POWER CORRIDOR (VCCP_USB) V_1P05_PCH PCI EXPRESS DECOUPLING FILTER NC L1 0603 1 1UH/360mA VCCSATA_PLL_PCH C314 NC0603 1UF/16V PLACE VCCSATA DCPL CAPS AT ENDS OF POWER CORRIDOR 0402 R434 0-5% C315 C316 0603 0603 1UF/16V 1UF/16V NC L2 0603 1 1UH/360mA C320 NC0603 1UF/16V VCCDMI_PLL_PCH V_1P05_PCH NC L3 0603 1 1UH/360mA VCCUSB3_PLL_PCH C322 NC0603 1UF/16V L4 0603 1 1UH/360mA A L5 0603 1 1UH/360mA DavidWang: 20110224 DVT L1~L6 TO 0603 C321 TO 0805 L6 0603 1 1UH/360mA FB10 1 V_3P3_DAC_FB_R 60OHM/100MHz-650mA C318 0603 1UF/16V VCCA_DPLLA C348 C323 0805 0603 10UF/6.3V 1UF/16V VCCA_DPLLB C347 C332 0805 0603 10UF/6.3V 1UF/16V V_1P05_PCH_SRC C343 C344 0805 0603 10UF/6.3V 1UF/16V V_1P05_ME V_1P05_PCH +3D3V V_1P05_PCH V_1P05_PCH PCH CORE POWER RN6 1 2 3 4 5 6 7 8 PLACE NEAR PCH C329 C328 0402 0805 0.1UF/16V4.7UF/10V +3D3SV ATA BG C327 0402 0.1UF/16V C330 C331 0603 0603 1UF/16V 1UF/16V SATA RX/TX C325 C324 0603 0805 1UF/16V 10UF/6.3V 0-5%-08P4R 0402 C326 0.1UF/16V A V_CPU_VCCIO C333 C334 0805 0603 4.7UF/10V 1UF/16V C335 C336 0402 0402 0.1UF/16V 0.1UF/16V PLACE 4.7UF EAST CORNER OF PCH V_1P05_PCH FOR PCH DECOUPLING C341 C342 C337 C338 C339 C340 0402 0402 0402 0402 0805 0805 0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V 10UF/6.3V10UF/6.3V ShenZhen Topstar Inductor Co.,Ltd Page Name CPT_POWER Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 44 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 U10J BC15 A26 BC20 VSS_125 VSS_5 A29 BC27 VSS_126 VSS_6 A42 BC31 VSS_127 VSS_7 A49 BC36 VSS_128 VSS_8 A9 BC38 VSS_129 BC47 VSS_130 GND VSS_9 AA20 VSS_10 AA22 BC9 VSS_131 VSS_11 AA24 BD25 VSS_132 VSS_12 AA26 BD33 VSS_133 VSS_13 AA28 BF12 VSS_134 VSS_14 AA30 D BF20 VSS_135 VSS_15 AA38 BF25 VSS_136 VSS_16 AB11 BF33 VSS_137 VSS_17 AB15 BF41 VSS_138 VSS_18 AB40 BF43 VSS_139 VSS_19 AB41 BF46 VSS_140 VSS_20 AB43 BF52 VSS_141 VSS_21 AB47 BF6 VSS_142 VSS_22 AB52 BG22 VSS_143 VSS_23 AB57 BG25 VSS_144 VSS_24 AB6 BG27 VSS_145 VSS_25 AC22 BG31 VSS_146 VSS_26 AC34 BG33 VSS_147 VSS_27 AC36 BG36 VSS_148 VSS_28 AC38 BG38 VSS_149 VSS_29 AC4 BH52 VSS_150 VSS_30 AC54 BH6 VSS_151 VSS_31 AE14 BJ1 VSS_152 VSS_32 AE18 BJ15 VSS_153 VSS_33 AE22 BK20 VSS_154 VSS_34 AE26 BK41 VSS_155 VSS_35 AE38 BK52 VSS_156 VSS_36 AE4 BK6 VSS_157 VSS_37 AE47 BM10 VSS_158 VSS_38 AE8 BM12 VSS_159 VSS_39 AE9 BM16 VSS_160 VSS_40 AF52 BM22 VSS_161 VSS_41 AF6 BM23 VSS_162 VSS_42 AG11 BM26 VSS_163 VSS_43 AG14 BM28 VSS_164 VSS_44 AG20 BM32 VSS_165 VSS_45 AG22 BM40 VSS_166 VSS_46 AG30 BM42 VSS_167 VSS_47 AG36 BM48 VSS_168 VSS_48 AG43 BM5 VSS_169 VSS_49 AG44 BN31 VSS_170 VSS_50 AG46 BN47 VSS_171 VSS_51 AG5 C BN6 VSS_172 BP3 VSS_173 VSS_52 AG50 VSS_53 AG53 BP33 VSS_174 VSS_54 AH52 BP35 VSS_175 VSS_55 AH6 BR22 VSS_176 VSS_56 AJ22 BR52 VSS_177 VSS_57 AJ30 BU19 VSS_178 VSS_58 AJ57 BU26 VSS_179 VSS_59 AK52 BU29 VSS_180 VSS_60 AK6 BU36 VSS_181 VSS_61 AL11 BU39 VSS_182 VSS_62 AL18 C19 VSS_183 VSS_63 AL20 C32 VSS_184 VSS_64 AL22 C39 VSS_185 VSS_65 AL26 C4 VSS_186 VSS_66 AL30 D15 VSS_187 VSS_67 AL36 D23 VSS_188 VSS_68 AL41 D3 VSS_189 VSS_69 AL46 D35 VSS_190 VSS_70 AL47 D43 VSS_191 VSS_71 AM52 D45 VSS_192 VSS_73 AM3 E19 VSS_193 VSS_72 AM57 E39 VSS_194 VSS_74 AN11 E54 VSS_195 VSS_75 AN12 E6 VSS_196 VSS_76 AN15 E9 VSS_197 VSS_77 AN17 F10 VSS_198 VSS_78 AN18 F12 VSS_199 VSS_79 AN20 F16 VSS_200 VSS_80 AN30 F22 VSS_201 VSS_81 AN36 F26 VSS_202 VSS_82 AN4 F32 VSS_203 VSS_83 AN43 F33 VSS_204 VSS_84 AN47 F35 VSS_205 VSS_85 AN54 F36 VSS_206 VSS_86 AN9 F40 VSS_207 VSS_87 AR20 F42 VSS_208 VSS_88 AR22 F46 VSS_209 VSS_89 AR52 B F48 VSS_210 VSS_90 AR6 F50 VSS_211 VSS_91 AT15 F8 VSS_212 VSS_92 AT18 AV18 VSS_213 VSS_93 AT43 AV22 VSS_104 VSS_94 AT47 AV34 VSS_105 VSS_95 AT52 AV38 VSS_106 VSS_96 AT6 AV47 VSS_107 VSS_97 AT8 AV6 VSS_108 VSS_98 AU24 AW57 VSS_109 VSS_99 AU26 AY38 VSS_110 VSS_100 AU28 AY6 VSS_111 VSS_101 AU5 B23 VSS_112 VSS_102 AV12 BA11 VSS_113 VSS_103 BA49 BA12 VSS_114 VSS_119 BB1 BA31 VSS_115 VSS_120 BB3 BA41 VSS_116 VSS_121 BB52 BA44 VSS_117 VSS_122 BB6 G54 VSS_118 VSS_123 BC14 H15 VSS_214 VSS_124 M33 H20 VSS_215 VSS_241 M36 H22 VSS_216 VSS_242 M46 H25 VSS_217 VSS_243 M52 H27 VSS_218 VSS_244 M57 H33 VSS_219 VSS_245 M6 H6 VSS_220 VSS_246 M8 J1 VSS_221 VSS_247 M9 J33 VSS_222 VSS_248 N4 J46 VSS_223 VSS_249 N54 J48 VSS_224 VSS_250 R11 J5 VSS_225 VSS_251 R15 J53 VSS_226 VSS_252 R17 K52 VSS_227 VSS_253 R22 K6 VSS_228 VSS_254 R4 K9 VSS_229 VSS_255 R41 VSS_230 VSS_256 R43 VSS_257 R46 A VSS_258 R49 10 OF 12 VSS_259 COUGAR POINT SKY 5 4 3 2 1 U10L D L12 L33 L17 VSS_231 TP3 AE49 L38 VSS_232 TP13 BA36 L41 VSS_233 TP17 AY36 L43 M20 VSS_234 VSS_235 GND TP18 TP19 Y14 Y12 M22 VSS_236 TP20 P22 M25 VSS_237 TP1 M38 M27 VSS_238 TP4 P25 M31 VSS_239 VSS_296 R25 T52 VSS_240 VSS_295 P36 T6 VSS_260 VSS_294 R36 U11 VSS_261 VSS_293 L31 U15 VSS_262 TP2 L36 U17 VSS_263 TP5 AL44 U20 VSS_264 VSS_292 AL43 U22 VSS_265 VSS_291 U25 VSS_266 AE41 U27 VSS_267 TP14 AE43 U33 VSS_268 TP15 U36 VSS_269 BA27 U38 VSS_270 TP11 U41 VSS_271 U47 VSS_272 U53 VSS_273 V20 VSS_274 V38 VSS_275 V6 VSS_276 W1 VSS_277 W55 VSS_278 BM46 W57 VSS_279 TP10 Y11 VSS_280 Y15 VSS_281 AG12 Y38 VSS_282 L_BKLTCTL AG18 Y40 VSS_283 L_BKLTEN AG17 Y43 VSS_284 Y46 VSS_285 L_VDD_EN C Y47 VSS_286 Y49 VSS_287 Y52 VSS_288 Y6 VSS_289 VSS_290 A4 A6 B2 BM1 BM57 BP1 BP57 BT2 BU4 BU52 BU54 BU6 D1 F1 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 B AY22 C12 AE56 BR36 AU2 A54 A52 F57 D57 VSS_4 VSS_3 VSS_1 VSS_2 VSSADAC TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4 12 OF 12 COUGAR POINT SKY A ShenZhen Topstar Inductor Co.,Ltd Page Name CPT_GND Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 45 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3 2 1 5 4 3 2 1 +12VIN VL1 1.0uH/12A ISL6363CRZ 1 2 STAND 12 VIN + VC2 5mm VCE1 + VCE2 + VCE3 1206 8*11.5 8*11.5 8*11.5 10UF/16V 270uF/16V 270uF/16V 270uF/16V VIN D VQ1 VC1 0603 1UF/16V VC4 1206 10UF/16V 3 2 TO252 DVT D 4-phase/95W/112A +3D3V R17=168K R99=23.06K V_CPU_VCCIO V_CPU_VCCIO +12VIN H_SKTOCC_R_N State H CPU NOT IN SOCKET L CPU IN SOCKET 3-phase/95W/112A R17=79.8K R99=435K <31,39> H_SKTOCC_R_N 3 2 SOT23 0402 54.9-1% 0 4 0 2 VR5 90.9-1% 0 4 0 2 VR6 110-1% 0 4 0 2 VR7 0402 0402 0402 0402 0402 VR155 22K-5% COMP 0402 1G D VQ20 G S 2N7002 VR112 1K-5% VC61 0402 0.1UF/16V 1& VR10 200-1% VR154 1K-5% 1& VR110 VR11 10K-5% 200-1% 1& VR138 VC62 1K-5%0402 0.1UF/25V +5V VC63 0603 1UF/16V 0805 VR111 2.2-5% V6363 0805 0805 +12VIN VR142 2.2-5% VC81 +12VIN VR113 2.2-5% VBOOT= 0V Schematic VU1 3 0603 1UF/16V VCC NC <16> <16> <16> VR_READY VR_READY ENV_RV2T0T0 4 0 2 0-5% VR21 0 4 0 2 0-5% 18 2 VR_ON 22 PGOOD PGOODG 43 PVCC 32 PVCCG VC68 0603 1UF/16V 1G DCR:AVG 0.8m ohm, VR2 G S N0201NY MAX 1.5m ohm 0402 UG1 VR120 6 0 3 0-5% 10K-5% D NC 0.56uH/28A STAND PH1 LG1 D VR140 6 0 3 0-5%1 G VQ2 G S N0202NY 3 2 TO252 VR15 0603 2 1 21 5mm 2.2-5% VL2 1 VCP1 VC10 0603 1000PF/50V 2 2 1 VCP2 VCORE VSUM+ 3.6K-1% VR124 0402 PHASE1 ISENSE1 ISEN1 VSUM- 0.22uF/10V 0402 VC65 0402 VR0141072 10K-5% VR156 100K-5% NC 0402 VR123 10-5% PHASE1 ISENSE1 <31> H_VIDSOUT_VR <31> H_VIDALERT_N_VR <31> H_VIDSCK_VR <31> H_PROCHOT_N VR16 0 4 0 2 0-5% 0402 VR100 1000PF/50VNCVC56 0 4N0 2C 200K-5% VCORE VR130 220K-5%0 4 0 2 0402 0402 VR1370 42002 0K-5% VCVC6970 470PF/50V 100PF/50V 0402 VC71 1000PF/50V 0603 VR133 8.06K-1% COMP 19 20 SDA 21 ALERT# SCLK 31 VR_HOT# 15 VW 14 COMP 13 FB 45 BOOT1 46 UGATE1 47 PHASE1 44 LGATE1 BT1 VR0161043 2.2-5% 0603 VC64 0.22UF/16V UG1 PH1 LG1 41 BT2 VR0161053 2.2-5% BOOT2 0603 VC67 0.22UF/16V VIN D VQ3 1G VC16 0603 1UF/16V VC17 1206 10UF/16V Close PWM 3 2 TO252 VR34 100-5% VC72 680PF/50V 0402 VR1350 4 0 2 499-1% VR13044 0 2 4.7K-5% NC VC66 0402 VR1160 4 0 2 100-5% 11 NC PSICOMP 330PF-/50V 40 UGATE2 39 PHASE2 UG2 PH2 UG2 VR380 6 0 3 0-5% 0402 G 10K-5% VR28 NC S N0201NY 0.56uH/28A 0402 STAND 3 2 TO252 <31> VCC_SENSE VR39 0 4 0 2 0-5% 10 VSEN 42 LGATE2 LG2 PH2 D VQ4 2 1 21 5mm VSUM+ 3.6K-1% VR128 0402 NC0402 VC24 <31> VSS_SENSE VR410 4 0 2 0-5% 0.1UF/16V NC0402 VC25 0.1UF/16V NC0402 VC26 NC 12 RTN 38 PWM3 PWM3 VR01420N22C 0-5% V6363 LG2 VR450 6 0 3 0-5%1 G 0603 VR42 2.2-5% VL3 1 1 VCP3 VCP4 G S N0202NY ISEN2 VR0142072 10K-5% PHASE2 0402 C VR43 100-5% 0.1UF/16V VR10 14 082 300K-5% VC75 VC73 1000PF/50V 37 PWM4 PWM4 0402 VR125 0-5% V6363 0402 VC33 0.22uF/10V VR157 C 0603 0402 100K-5% 2 2 0402 0402 0402 0402 VAXG 0402 NC 1000PF/50V VC58 V0R4 01201 NC10-5% 0402 VR119 0402 VR35 100-5% 0 4 0 2 VR150 100-5% VC82 330PF-/50V 220K-5% VC74 0402 220PF/50V VR120 8.2K-5% 39PF/50V 24 VWG 25 COMPG 26 FBG 6 ISEN1 7 ISEN2 8 ISNE3 ISEN1 ISEN2 ISEN3 <47> UGS <47> PHS <47> LGS <47> ISUMPG <47> ISUMNG 1000PF/50V PHASE2 ISENSE2 VSUM- VC76 NC 0402 VR126 10-5% ISENSE2 Close PWM <31> VCCAXG_SENSE VR55 0 4 0 2 0-5% VC79 0 4 0 2 VR141 3.3K-5% 9 ISEN4 NC <31> VSSAXG_SENSE VR580 4 0 2 0-5% 330PF-/50V 27 RTNG 0402 0402 0402 VR36 100-5% VC78 0402 1000PF/50V NC VC83 1000PF/50V NC Disable VAXG V6363 VR153 NC 00-450%2 ISUMP ISUMN ISUMPG ISUMNG 4 ISUMP 5 ISUMN 28 ISUMPG 29 ISUMNG 17 IMON 34 BOOTG 35 UGATEG 36 PHASEG 33 LGATEG VC77 BTSVR0162013 2.2-5% 0.22UF/16V UGS PHS LGS 0603 0.1UF/25V 0603 VC41 VIN D VQ6 VC38 0603 1UF/16V VC39 1206 10UF/16V 3 2 TO252 VSUM+ VR146 2.8K-1% 0402 0402 VC87 0.047uF/50V VC88 0402 0402 ISUMP ISUMN VC91 NC330PF-/50V V6363 VR144 0-5% 0 4 0 2 NC 23 IMONG 48 ADDR 1 SCOMP 0402 0402 VC85 VR139 VC84 0603 VR131 0603 VR132 3.6K-1% 0402 0.22UF/16V 10K-5% 0.22UF/16V 10K-5% VC86 0.1UF/16V 0402 0402 VR136 10K-5% NC ISL6363 G1 G2 GND1 G3 GND2 G4 GND3 G5 GND4 G6 GND5 G7 GND6 G8 GND7 G9 GND8 GND9 16 NTC 30 NTCG 0603 20110617 for layour VR145 3.83K-5% 0603 VR140 3.83K-5% +12VIN VR74 0603 2.2-5% 2.2-5% VR71 PH3 PVCC3 VCC3 LG3 VC57 0603 1UF/16V 0603 8 7 PHASE 6 PVCC 5 VCC LGATE VU2 1 UGATE 2 BOOT 3 PWM 4 GND ISL6612ACB UG3 BT3 PWM3 UG3 PH3 LG3 1G VR720 6 0 3 VR63 0402 G 10K-5% 0-5% NC S N0201NY D VR810 6 0 3 0-5%1 G VQ5 G S N0202NY 3 2 TO252 0.56uH/28A STAND VR82 0603 2 1 21 5mm 2.2-5% VL4 1 1 VCP5 VCP6 VC47 VSUM+ 3.6K-1% VR152 0402 ISEN3 0.22uF/10V 0402 0402 VR0145012 10K-5% VR158 100K-5% PHASE3 1 CLOSE VRT3 t L110K-5% 2 VSUM- 0402 10K-5% VR143 0.1UF/25V VC89 0.33uF/16V 0402 0402 0603 VR148 562-1% VR149 100-5% NC NC BOTTOM PAD CONNECT TO GND Through 8 VIAs 0603 VR147 28K-1% 0402 VRT1 470K-5% 0603 VR159 28K-1% 0402 VRT2 470K-5% 0603 1000PF/50V PHASE3 2 2 VSUM- VC80 NC 0402 VR129 10-5% ISENSE3 Close PWM B VC90 ISENSE3 B 0402 0.1UF/16V For now any resistor between 0Ohm and 13.2kOhm with the middle being typical (6.65k) will give you address 0/1, between 13.2k and 27k will give you address 2/3, etc. ERT-J0EV474J CLOSE Q7 ERT-J0EV474J CLOSE Q1 A 5 VCORE OS-CON + VCE4 + VCE5 + VCE6 + VCE7 + VCE8 8*8 8*8 8*8 8*8 8*8 560UF/2.5V 560UF/2.5V 560UF/2.5V 560UF/2.5V 560UF/2.5V VCORE OS-CON + VCE11 + VCE15 + VCE9 + VCE14 + VCE16 8*8 8*8 8*8 8*8 8*8 560UF/4V 560UF/4V 560UF/4V 560UF/4V 560UF/4V NC NC NC NC NC 4 3 A ShenZhen Topstar Inductor Co.,Ltd Page Name VR_VCORE Size Project Name D F-H61 Date: Friday, March 15, 2013 Sheet 46 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 2 1 5 4 3 2 1 D D VIN D VQ10 + VCE10 8*11.5 270uF/16V VC50 VC51 0603 1206 1UF/16V 10UF/16V 0402 3 2 TO252 1G DCR:AVG 1m ohm, MAX 1.5m ohm G S N0201NY C UGS VR940 6 0 3 0-5% VR92 VAXG C <46> UGS <46> PHS <46> LGS <46> ISUMPG PHS 10K-5% NC 1UH/24A VL5 2 1 STAND 21 5mm <46> ISUMNG D VQ11 0603 VR96 2.2-5% 1 1 VCP7 VCP8 LGS 0 6 0 3 0-5% 1 G + VCE12 + VCE13 VR97 8*8 8*8 G S N0202NY VC55 560UF/2.5V 560UF/2.5V 3 2 TO252 2 2 0603 1000PF/50V VR67 B VSUMG+ 0402 VSUMG+ ISUMPG B VSUMG- 3.6K-1% VR66 2.7K-5% 0402 0402 0402 0.047uF/50V VC95 VC93 VC92 0402 ISUMNG VC94 + VCE17 + VCE18 8*8 8*8 560UF/4V 560UF/4V 1 0402 VR69 39PF/50V 0.1UF/25V 0402 NC NC NC VRT4 10K-5% NC 220PF/50V Close to L4 t 10K-5% VR64 0402 0603 2 VSUMG- VR68 0402 VR65 100-5% NC 698-1% ShenZhen Topstar Inductor Co.,Ltd Page Name VR_VAXG A VC96 10-5% 0402 Size Project Name Custom F-H61 Rev A 1.0 0.1UF/25V Date: Friday, March 15, 2013 Sheet 47 of 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 +12VIN PR127 2.2-5% 0805 D D 1 0402 0402 VIN 0402 PR128 18K-5% @9214 PU9 PC76 0603 1UF/16V @9214 PD6 1N4148 0603 PC77 1206 PC78 1UF/16V 10UF/16V 5 VCC 0603 STAND 0402 0402 3 2 TO252 EN_VCCIO 7 OCSET/PH BOOT 1 PR1290 6 0 3 2.2-5% D PQ34 0402 PR130 10K-5% @6545 PC79 2 0603 1G UGATE 0-5% PR131 PC80 G S N0201NY PL4 3 2 TO252 0402 0603 PC81 0402 100PF/50V @6545 8 0603 0.1UF/16V PHASE 0-5% PR132 1 2 12 5mm C DavidWang: 20110224 DVT FIX VCCIO NOT STABLE 4700PF/50V @6545 PR137 6 FB 4 LGATE 0603 1G 0-5% PR133 PDQ35 PR134 2.2-5% 1.0uH/12A PC82 0402 NC PR135 100-5% PR136 0-5% G S N0202NY 0.1uF/16V 3 GND 0402 0402 0402 PR138 PC83 @2608 0-5% @6545 RT9214 15K-5% @6545 0603 1000PF/50V V_CPU_VCCIO + PCE26 + PCE27 + PCE30+ PCE29 C 8*8 8*8 8*8 8*8 560UF/2.5V 560UF/2.5V 560UF/4V 560UF/4V NC NC PR1390 4 0 2 220-5% @9214 PC84 1000PF/50V @9214 change from 4700pF NC FOR COST DOWN PR151 0-5% FB_VCCIO PR1410 4 0 2 2K-1% V_CPU_VCCIO PR142 3K-1% R2 DF@6545_750 OHM@9214 R1 100-5%NCPR143 0402 +5V_SB DF@6545_2.8K@9214 ISL6545/uP6103: B V_1P05_PCH 0402 PR144 4.7K-5% EN_VCCIO D PQ37 VDRAM=0.6*(1+R1/R2) PR15N00 4C0 2 0-5% VCCIO_SENSE <31> B VSSIO_SENSE <31> 3 2 SOT23 3 2 SOT23 1G C PQ38 G PR1450 4 0 2 4.7K-5%1 B S 2N7002 100-5%NCPR146 0402 B PC85 E FHS3904-ME 0603 1UF/16V DVT:CHANGE PQ38=3904 +5V PR1470 4 0 2 22K-1%FB_VCCIO 0402 PR148 10K-5% DF@6545_18K@9214 3 2 SOT23 PR1520 4 0 2 4.7K-5% 1G D PQ39 A G S 2N7002 ShenZhen Topstar Inductor Co.,Ltd A 3 2 SOT23 <31> VCCIO_SEL NC C PQ40 PR14N90 4C0 2 4.7K-5% 1 B B E FHS3904-ME VCCIO_SEL=H VID=01011010=1.05V VCCIO_SEL=L VID=01100010=1.00V Page Name VR_VCCIO Size Custom Project Name F-H61 Date: Friday, March 15, 2013 Sheet 48 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 +12V 0805 PR101 2.2-5% CPU_VDDIO_SUS@ 20A CPU_VTT_SUS@ 2A +5V D D 2 12 5mm 1 0402 0402 3 2 SOT23 3 2 SOT23 0402 PR49 18K-5% @9214 PU2 EN_DDR PR51 10K-5% 7 OCSET/PH 0402 @6545 PC36 0402 PC38 470PF/50V 0402 @6545 4700PF/50V @6545 6 FB 0402 0402 PR57 PR05-85% 0-5% @2608 @6545 RT9214 3 5 GND VCC PC33 0603 1UF/16V 1 BOOT 2 UGATE 8 PHASE 4 LGATE STAND PL2 1.0uH/12A 1 @9214 PD4 1N4148 PR50 0 6 0 3 2.2-5% 0603 0-5% 0603 0-5% PC37 0603 0.1UF/16V PR53 1G PR52 G 0402 PR59 15K-5% @6545 0603 1G 0-5% PR55 G 3 2 TO252 3 2 TO252 D PQ10 + PCE9 8*11.5 270uF/16V PC34 0603 1UF/16V PC35 1206 10UF/16V S N0201NY D PQ11 S N0202NY 0603 STAND 0402 1UH PR54 2 1 21 5mm 2.2-5% PL3 PC40 0603 1000PF/50V PC39 NC 0402 0.1uF/16V +1.5V @20A PR56 100-5% PCE11 + 8*11.5 1000uF/6.3V PCE12 PCE13 + + 8*11.5 NC 8*11.5 1000uF/6.3V 1000uF/6.3V DDRVSM NC FOR COST DOWN change from 4700pF PR60 0 4 0 2 220-5% PC41 1000PF/50V C @9214 @9214 C <12,39> SLP_S4_N +5V_SB 0402 PR62 4.7K-5% PR64 0 4 0 2 4.7K-5%1 G 1G D PQ14 G EN_DDR D PQ13 S 2N7002 PC49 G S 2N7002 0603 2.2UF/6.3V FB_DDR PR61 0 4 0 2 1.5K-1% PR63 1K-1% R2 R1 ISL6545/uP6103: VDRAM=0.6*(1+R1/R2) DF@6545_1.6K@9214 DDRVTT DDRVSM PR65 1K-1% PC88 0805 4.7UF/10V 0402 PR69 0402 PC44 1K-1% 0603 1UF/16V PU3 Vcntl=5V 1 8 2 VIN NC1 7 3 GND NC2 6 4 REFEN Vcntl 5 VOUT NC3 rp1210 PC89 0805 4.7UF/10V +5V PR66 0 6 0 3 0-5% PR67N0 C6 0 3 0-5% +3D3V DDRVTT G1 G2 G1 G3 G2 G4 G3 G4 0402 PC48 PR75 B B + PCE15 61.3&*7 100UF/25V 0603 2.2UF/6.3V NC 47-5% A A ShenZhen Topstar Inductor Co.,Ltd Page Name VR_DDR Size C Project Name F-H61 Date: Friday, March 15, 2013 Sheet 49 of Rev 1.0 50 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5 4 3 2 1 5 4 3 2 1 3VDUAL DDRVSM PR94 300-5% +12V PC90 + PCE17 0402 0402 +5V_SB 8*11.5 1000uF/6.3V 3 2 TO252 8 +5V_SB PU10 3VDUAL PR95 10K-5% 3 + PU5A 0.1UF/16V 1 D 1G PQ21 NC FOR COST DOWN 0402 3 2 SOT23 0402 D 3 2 VIN VO1 C PQ23PC51 PR96 140-1% 2 - G S AOD484 D 1 GND 3 2 SOT23 PC91 1206 10UF/10V 4 VO2 BL1085-CY PR107 PC72 PC73+ PCE28 0805 121-1% 0805 NC5*7 100uF/10V 1B B C PQ24 0603 E 1UF/16V FHS3904-ME 4 LM358 PR98 0 4 0 2 1K-5% 0402 3D3VADJ <12,16,17,39> SLP_S3_N PR97 0 4 0 2 2K-51% B B E FHS3904-ME PR99 0 4 0 2 1K-1% V_1P05_PCH 6.2A+1.8A 0402 PR108 200-1% PC92 + PCE18 0402 8*11.5 0.1UF/16V 1000uF/6.3V 0402 10UF/6.3V 10UF/6.3V PR1200 4 0 2 100-5% 3VDUAL V_CPU_VCCIO C +12V C 0402 PR109 2.49K-1% PC61 V_1P8_SFR +5V 1206 +3D3V 10UF/10V 3 2 TO252 8 PU11 NC FOR COST DOWN NC FOR COST DOWN PR1100 4 0 2 9.1K-1% VCCSA_CNTRL_INPUT 5 + PU5B 7 D 1G PQ25 3 2 SOT23 0402 1 GND PC66 3 VIN 0603 PC86 1UF/16V 1206 VO1 2 4 VO2 R445 1K-1% + PCE24 PC87 3VDUAL +5V PR11N1C 10K-5% 0402 D PQ26 1G PPRC16122 1K-1% 0603 1UF/16V 0402 6- 4 LM358 G PR1140 4 0 2 1K-1% S AOD484 3 2 SOT23 10UF/10V BL1085-CY 0402 R1 NC5*7 1206 100uF/10V 10UF/10V R2R443 475-1% 1.6A MAX <31> VCCSA_VID PR11N5C 10K-5% PR11N90 4C0 2 100-1% 0402 3 2 SOT23 0402 PR11N3C 10K-5% G NC C PQ27 1B B E FHS3904-ME NC C PQ28 1B B E FHS3904-ME S 2N7002 <31> VCCSA_SENSE V_SA VCCSA_VID=H VCCSA_VID=L PR1160 4 0 2 10-5% VSA_SENSEPR1170 4 0 2 100-1% 0.925v PC64 PC65 + PCE23 NC 1206 1206 8*8 10UF/10V10UF/10V 560UF/4V MAX 8.8A 0.85V 0.95V VOUT=1.25*(1+R2/R1) PR122 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