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ATMEL 8160 datasheet

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ATMEL 8160 Datasheet

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8-bit Atmel Microcontroller with 64KB In-System Programmable Flash ATmega64A Features • High-performance, Low-power Atmel® AVR® 8-bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – 64 Kbytes of In-System Reprogrammable Flash program memory – 2 Kbytes EEPROM – 4 Kbytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Up to 64 Kbytes Optional External Memory Space – Programming Lock for Software Security – SPI Interface for In-System Programming • JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Two 8-bit PWM Channels – 6 PWM Channels with Programmable Resolution from 1 to 16 Bits – 8-channel, 10-bit ADC • 8 Single-ended Channels • 7 Differential Channels • 2 Differential Channels with Programmable Gain (1x, 10x, 200x) – Byte-oriented Two-wire Serial Interface – Dual Programmable Serial USARTs – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with On-chip Oscillator – On-chip Analog Comparator • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby – Software Selectable Clock Frequency – ATmega103 Compatibility Mode Selected by a Fuse – Global Pull-up Disable • I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega64A • Speed Grades – 0 - 16 MHz for ATmega64A 8160D–AVR–02/2013 1. Pin Configuration Figure 1-1. Pinout ATmega64A TQFP/MLF 64 AVCC 63 GND 62 AREF 61 PF0 (ADC0) 60 PF1 (ADC1) 59 PF2 (ADC2) 58 PF3 (ADC3) 57 PF4 (ADC4/TCK) 56 PF5 (ADC5/TMS) 55 PF6 (ADC6/TDO) 54 PF7 (ADC7/TDI) 53 GND 52 VCC 51 PA0 (AD0) 50 PA1 (AD1) 49 PA2 (AD2) PEN 1 RXD0/(PDI) PE0 2 (TXD0/PDO) PE1 3 (XCK0/AIN0) PE2 4 (OC3A/AIN1) PE3 5 (OC3B/INT4) PE4 6 (OC3C/INT5) PE5 7 (T3/INT6) PE6 8 (ICP3/INT7) PE7 9 (SS) PB0 10 (SCK) PB1 11 (MOSI) PB2 12 (MISO) PB3 13 (OC0) PB4 14 (OC1A) PB5 15 (OC1B) PB6 16 48 PA3 (AD3) 47 PA4 (AD4) 46 PA5 (AD5) 45 PA6 (AD6) 44 PA7 (AD7) 43 PG2(ALE) 42 PC7 (A15) 41 PC6 (A14) 40 PC5 (A13) 39 PC4 (A12) 38 PC3 (A11) 37 PC2 (A10 36 PC1 (A9) 35 PC0 (A8) 34 PG1(RD) 33 PG0(WR) (OC2/OC1C) PB7 17 TOSC2/PG3 18 TOSC1/PG4 19 RESET 20 VCC 21 GND 22 XTAL2 23 XTAL1 24 (SCL/INT0) PD0 25 (SDA/INT1) PD1 26 (RXD1/INT2) PD2 27 (TXD1/INT3) PD3 28 (ICP1) PD4 29 (XCK1) PD5 30 (T1) PD6 31 (T2) PD7 32 Note: The bottom pad under the QFN/MLF package should be soldered to ground. ATmega64A [DATASHEET] 2 8160D–AVR–02/2013 2. Overview The ATmega64A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64A achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PF0 - PF7 VCC GND AVCC PORTF DRIVERS DATA REGISTER PORTF DATA DIR. REG. PORTF PA0 - PA7 PORTA DRIVERS DATA REGISTER PORTA DATA DIR. REG. PORTA PC0 - PC7 PORTC DRIVERS DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AREF PEN JTAG TAP ON-CHIP DEBUG BOUNDARYSCAN PROGRAMMING LOGIC ADC PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES USART0 STACK POINTER SRAM GENERAL PURPOSE REGISTERS X Y Z ALU STATUS REGISTER INTERNAL OSCILLATOR WATCHDOG TIMER MCU CONTROL REGISTER TIMER/ COUNTERS INTERRUPT UNIT EEPROM CALIB. OSC OSCILLATOR OSCILLATOR TIMING AND CONTROL SPI USART1 2-WIRE SERIAL INTERFACE XTAL1 XTAL2 RESET ANALOG COMPARATOR + - DATA REGISTER PORTE DATA DIR. REG. PORTE PORTE DRIVERS DATA REGISTER PORTB DATA DIR. REG. PORTB PORTB DRIVERS DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS DATA REG. DATA DIR. PORTG REG. PORTG PORTG DRIVERS PE0 - PE7 PB0 - PB7 PD0 - PD7 PG0 - PG4 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega64A provides the following features: 64 Kbytes In-System Programmable Flash with Read-WhileWrite capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 ATmega64A [DATASHEET] 3 8160D–AVR–02/2013 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run. The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega64A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega64A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. 2.2 ATmega103 and ATmega64A Compatibility The ATmega64A is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega64A. Most additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF (that is, in the ATmega103 internal RAM space). These location can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the extended Interrupt Vectors are removed. The ATmega64A is 100% pin compatible with ATmega103, and can replace the ATmega103 on current printed circuit boards. The application notes “Replacing ATmega103 by ATmega128” and “Migration between ATmega64 and ATmega128” describes what the user should be aware of replacing the ATmega103 by an ATmega128 or ATmega64. 2.2.1 ATmega103 Compatibility Mode By programming the M103C Fuse, the ATmega64A will be compatible with the ATmega103 regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new features in ATmega64A are not available in this compatibility mode, these features are listed below: • One USART instead of two, asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available. • One 16-bits Timer/Counter with two compare registers instead of two 16-bits Timer/Counters with three compare registers. • Two-wire serial interface is not supported. • Port G serves alternate functions only (not a general I/O port). • Port F serves as digital input only in addition to analog input to the ADC. ATmega64A [DATASHEET] 4 8160D–AVR–02/2013 • Boot Loader capabilities is not supported. • It is not possible to adjust the frequency of the internal calibrated RC Oscillator. • The External Memory Interface can not release any Address pins for general I/O, neither configure different wait states to different External Memory Address sections. • Only EXTRF and PORF exist in the MCUCSR Register. • No timed sequence is required for Watchdog Timeout change. • Only low-level external interrupts can be used on four of the eight External Interrupt sources. • Port C is output only. • USART has no FIFO buffer, so Data OverRun comes earlier. • The user must have set unused I/O bits to 0 in ATmega103 programs. 2.3 Pin Descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega64A as listed on page 72. 2.3.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega64A as listed on page 73. 2.3.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega64A as listed on page 76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active. 2.3.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega64A as listed on page 77. ATmega64A [DATASHEET] 5 8160D–AVR–02/2013 2.3.7 Port E (PE7:PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega64A as listed on page 80. 2.3.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs. The TDO pin is tri-stated unless TAP states that shift out data are entered. Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port F is an input port only. 2.3.9 Port G (PG4:PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are Oscillator pins. 2.3.10 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 29-3 on page 307. Shorter pulses are not guaranteed to generate a reset. 2.3.11 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.12 XTAL2 Output from the inverting Oscillator amplifier. 2.3.13 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.14 AREF AREF is the analog reference pin for the A/D Converter. ATmega64A [DATASHEET] 6 8160D–AVR–02/2013 2.3.15 PEN This is a programming enable pin for the SPI Serial Programming mode. By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN is internally pulled high. The pullup is shown in Figure 11-1 on page 49 and its value is given in Section 29.2 “DC Characteristics” on page 304. PEN has no function during normal operation. 3. Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 6. Capacitive touch sensing The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. ATmega64A [DATASHEET] 7 8160D–AVR–02/2013 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1. Block Diagram of the AVR MCU Architecture Flash Program Memory Instruction Register Instruction Decoder Control Lines Program Counter Data Bus 8-bit Status and Control 32 x 8 General Purpose Registrers ALU Interrupt Unit SPI Unit Watchdog Timer Analog Comparator Direct Addressing Indirect Addressing Data SRAM EEPROM I/O Module1 I/O Module 2 I/O Module n I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer ATmega64A [DATASHEET] 8 8160D–AVR–02/2013 for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16-bit or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses which can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega64A has Extended I/O space from 0x60 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 7.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 7.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.3.1 SREG – AVR Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ATmega64A [DATASHEET] 9 8160D–AVR–02/2013 • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared in software with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7.3.2 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input. • Two 8-bit output operands and one 8-bit result input. • Two 8-bit output operands and one 16-bit result input. • One 16-bit output operand and one 16-bit result input. Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. ATmega64A [DATASHEET] 10 8160D–AVR–02/2013 Figure 7-2. AVR CPU General Purpose Working Registers General Purpose Working Registers 7 0 R0 R1 R2 … R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file. 7.3.3 X-, Y-, and Z-register The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3. The X-, Y-, and Z-Registers 15 XH XL 0 X - register 7 07 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y - register 7 07 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z - register 7 07 0 R31 (0x1F) R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details). 7.4 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the ATmega64A [DATASHEET] 11 8160D–AVR–02/2013 Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. If software reads the Program Counter from the Stack after a call or an interrupt, unused bits (bit 15) should be masked out. The Stack Pointer points to the data SRAM Stack area where the subroutine and interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7.5 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 7-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. ATmega64A [DATASHEET] 12 8160D–AVR–02/2013 Figure 7-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 7.6 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 274 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 57. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 57 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-programming” on page 261. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. ATmega64A [DATASHEET] 13 8160D–AVR–02/2013 When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< xxx :. :. :. :. When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8 Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments 0x0000 RESET: ldi r16,high(RAMEND); Main program start 0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0002 ldi r16,low(RAMEND) 0x0003 0x0004 out SPL,r16 sei ; Enable interrupts 0x0005 xxx ; .org 0x7002 0x7002 jmp EXT_INT0 ; IRQ0 Handler 0x7004 jmp EXT_INT1 ; IRQ1 Handler :. :. :. ; 0x7044 jmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 8 Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code .org 0x0002 0x0002 jmp 0x0004 jmp Comments EXT_INT0 ; IRQ0 Handler EXT_INT1 ; IRQ1 Handler ATmega64A [DATASHEET] 59 8160D–AVR–02/2013 :. :. :. ; 0x0044 jmp SPM_RDY ; Store Program Memory Ready Handler ; .org 0x7000 0x7000 RESET: ldi r16,high(RAMEND); Main program start 0x7001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x7002 ldi r16,low(RAMEND) 0x7003 0x7004 out SPL,r16 sei ; Enable interrupts 0x7005 xxx When the BOOTRST Fuse is programmed, the Boot section size set to 8 Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments ; .org 0x7000 0x7000 jmp 0x7002 jmp RESET ; Reset handler EXT_INT0 ; IRQ0 Handler 0x7004 jmp EXT_INT1 ; IRQ1 Handler :. :. :. ; 0x7044 jmp SPM_RDY ; Store Program Memory Ready Handler 0x7046 RESET: ldi r16,high(RAMEND); Main program start 0x7047 out SPH,r16 ; Set Stack Pointer to top of RAM 0x7048 ldi r16,low(RAMEND) 0x7049 0x704A out SPL,r16 sei ; Enable interrupts 0x704B xxx 12.2.1 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. ATmega64A [DATASHEET] 60 8160D–AVR–02/2013 12.3 Register Description 12.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value 7 6 5 SRE SRW10 SE R/W R/W R/W 0 0 0 4 SM1 R/W 0 3 SM0 R/W 0 2 SM2 R/W 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write Self-programming” on page 261 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-programming” on page 261 for details on Boot Lock bits. • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See code examples below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also use prescaling. A Prescaler Reset will affect the prescaler period for all Timer/Counters it is connected to. 17.0.3 External Clock Source An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkT1/clkT2/clkT3). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 17-1 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT2/clkT3 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 17-1. Tn Pin Sampling Tn clkI/O DQ LE DQ DQ Tn_sync (To Clock Select Logic) Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) ATmega64A [DATASHEET] 8160D–AVR–02/2013 136 given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 17-2. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3(1) CK 10-BIT T/C PRESCALER Clear CK/8 CK/64 CK/256 CK/1024 PSR321 T3 0 CS30 CS31 CS32 T2 0 CS20 CS21 CS22 T1 0 CS10 CS11 CS12 TIMER/COUNTER3 CLOCK SOURCE clkT3 TIMER/COUNTER2 CLOCK SOURCE clkT2 TIMER/COUNTER1 CLOCK SOURCE clkT1 Note: 1. The synchronization logic on the input pins (T3/T2/T1) is shown in Figure 17-1. ATmega64A [DATASHEET] 8160D–AVR–02/2013 137 17.1 Register Description 17.1.1 SFIOR – Special Function IO Register Bit 7 6 5 4 0x20 (0x40) TSM – – – Read/Write R/W R R R Initial Value 0 0 0 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR0 R/W 0 0 PSR321 R/W 0 SFIOR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to PSR0 and PSR321 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit written zero, the PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 – PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 When this bit is one, the Timer/Counter3, Timer/Counter2, and Timer/Counter1 prescaler will be reset. The bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3 Timer/Counter2, and Timer/Counter1 share the same prescaler and a reset of this prescaler will affect all three timers. ATmega64A [DATASHEET] 8160D–AVR–02/2013 138 18. 8-bit Timer/Counter2 with PWM 18.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) 18.2 Overview Timer/Counter2 is a general purpose, single-channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 18-1. For the actual placement of I/O pins, refer to “Pin Configuration” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 150. Figure 18-1. 8-bit Timer/Counter Block Diagram TCCRn count clear direction Control Logic BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = clkTn Clock Select Edge Detector TOVn (Int.Req.) Tn ( From Prescaler ) Waveform Generation OCn (Int.Req.) OCn DATA BUS OCRn 18.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. ATmega64A [DATASHEET] 8160D–AVR–02/2013 139 The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T2 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC2). For details, see “Output Compare Unit” on page 141. The Compare Match event will also set the Compare Flag (OCF2) which can be used to generate an Output Compare interrupt request. 18.2.2 Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used (that is, TCNT2 for accessing Timer/Counter2 counter value and so on). The definitions in Table 18-1 are also used extensively throughout this section. Table 18-1. BOTTOM MAX TOP Definitions The counter reaches the BOTTOM when it becomes 0x00. The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation. 18.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS22:0) bits located in the Timer/Counter Control Register (TCCR2). For details on clock sources and prescaler, see “Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers” on page 136. 18.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 shows a block diagram of the counter and its surroundings. Figure 18-2. Counter Unit Block Diagram DATA BUS TOVn (Int.Req.) Clock Select TCNTn count clear Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count Increment or decrement TCNT2 by 1. ATmega64A [DATASHEET] 8160D–AVR–02/2013 140 direction Select between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn top Timer/counter clock, referred to as clkT0 in the following. Signalize that TCNT2 has reached maximum value. bottom Signalize that TCNT2 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR2). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC2. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 144. The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. 18.5 Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF2 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (see “Modes of Operation” on page 144). Figure 18-3 shows a block diagram of the Output Compare unit. ATmega64A [DATASHEET] 8160D–AVR–02/2013 141 Figure 18-3. Output Compare Unit, Block Diagram DATA BUS OCRn top bottom FOCn = (8-bit Comparator ) Waveform Generator TCNTn OCFn (Int.Req.) OCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. 18.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled). 18.5.2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 18.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. ATmega64A [DATASHEET] 8160D–AVR–02/2013 142 The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bits in Normal mode. The OC2 Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. 18.6 Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The Waveform Generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 18-4 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. If a System Reset occur, the OC2 Register is reset to “0”. Figure 18-4. Compare Match Output Unit, Schematic COMn1 COMn0 FOCn Waveform Generator DQ 1 OCn 0 OCn Pin DQ DATA BUS PORT DQ clkI/O DDR The general I/O port function is overridden by the Output Compare (OC2) from the Waveform Generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 150. ATmega64A [DATASHEET] 8160D–AVR–02/2013 143 18.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the Waveform Generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 18-3 on page 150. For fast PWM mode, refer to Table 18-4 on page 151, and for phase correct PWM refer to Table 18-5 on page 151. A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written. For nonPWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits. 18.7 Modes of Operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (see “Compare Match Output Unit” on page 143). For detailed timing information refer to Figure 18-8, Figure 18-9, Figure 18-10, and Figure 18-11 in “Timer/Counter Timing Diagrams” on page 148. 18.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 18.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 18-5. The counter value (TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared. ATmega64A [DATASHEET] 8160D–AVR–02/2013 144 Figure 18-5. CTC Mode, Timing Diagram OCn Interrupt Flag Set TCNTn OCn (Toggle) Period 1 2 3 4 (COMn1:0 = 1) An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: fOCn = -2-------N--------f-c--1-l-k--_-+--I-/--OO-----C----R----n---- The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 18.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 18-6. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent Compare Matches between OCR2 and TCNT2. ATmega64A [DATASHEET] 8160D–AVR–02/2013 145 Figure 18-6. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn OCn (COMn1:0 = 2) (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0 to three (see Table 18-4 on page 151). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: fOCnPWM = N-f--c---l-k--2_---I5-/-O--6- The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR2 Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 18.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation ATmega64A [DATASHEET] 8160D–AVR–02/2013 146 has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 18-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent Compare Matches between OCR2 and TCNT2. Figure 18-7. Phase Correct PWM Mode, Timing Diagram OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set TCNTn OCn OCn (COMn1:0 = 2) (COMn1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to three (see Table 18-5 on page 151). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: fOCnPCPWM = N-f--c---l-k--5_---I1-/-O--0- The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. ATmega64A [DATASHEET] 8160D–AVR–02/2013 147 At the very start of period 2 in Figure 18-7 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without a Compare Match. • OCR2 changes its value from MAX, like in Figure 18-7. When the OCR2 value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • The timer starts counting from a higher value than the one in OCR2, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 18.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT2) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 18-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 18-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O/1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 18-9 shows the same timing data, but with the prescaler enabled. Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn MAX - 1 MAX BOTTOM TOVn BOTTOM + 1 ATmega64A [DATASHEET] 8160D–AVR–02/2013 148 Figure 18-10 shows the setting of OCF2 in all modes except CTC mode. Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn OCRn - 1 OCRn OCRn + 1 OCRn + 2 OCRn OCRn Value OCFn Figure 18-11 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC) OCRn TOP - 1 TOP TOP BOTTOM BOTTOM + 1 OCFn ATmega64A [DATASHEET] 8160D–AVR–02/2013 149 18.9 Register Description 18.9.1 TCCR2 – Timer/Counter Control Register Bit 0x25 (0x45) Read/Write Initial Value 7 FOC2 W 0 6 WGM20 R/W 0 5 COM21 R/W 0 4 COM20 R/W 0 3 WGM21 R/W 0 2 CS22 R/W 0 1 CS21 R/W 0 0 CS20 R/W 0 TCCR2 • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero. • Bit 6, 3 – WGM21:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 18-2 and “Modes of Operation” on page 144. Table 18-2. Waveform Generation Mode Bit Description(1) Mode 0 1 2 WGM21 (CTC2) 0 0 1 WGM20 (PWM2) 0 1 0 Timer/Counter Mode of Operation Normal PWM, Phase Correct CTC TOP 0xFF 0xFF OCR2 Update of OCR2 Immediate TOP Immediate TOV2 Flag Set on MAX BOTTOM MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. • Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 18-3 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a Normal or CTC mode (non-PWM). Table 18-3. COM21 0 0 1 1 Compare Output Mode, non-PWM Mode COM20 Description 0 Normal port operation, OC2 disconnected. 1 Toggle OC2 on Compare Match. 0 Clear OC2 on Compare Match. 1 Set OC2 on Compare Match. ATmega64A [DATASHEET] 8160D–AVR–02/2013 150 Table 18-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 18-4. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM, (non-inverting mode). 1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM, (inverting mode). Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 145 for more details. Table 18-5 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 18-5. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when downcounting. 1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when downcounting. Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 146 for more details. • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 18-6. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/counter stopped). 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T2 pin. Clock on falling edge. 1 1 1 External clock source on T2 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 18.9.2 TCNT2 – Timer/Counter Register Bit 7 6 5 4 3 2 1 0 0x24 (0x44) TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modify- ATmega64A [DATASHEET] 8160D–AVR–02/2013 151 ing the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register. 18.9.3 OCR2 – Output Compare Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) OCR2[7:0] OCR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2 pin. 18.9.4 TIMSK – Timer/Counter Interrupt Mask Register Bit 0x37 (0x57) Read/Write Initial Value 7 OCIE2 R/W 0 6 TOIE2 R/W 0 5 TICIE1 R/W 0 4 OCIE1A R/W 0 3 OCIE1B R/W 0 2 TOIE1 R/W 0 1 OCIE0 R/W 0 0 TOIE0 R/W 0 TIMSK • Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match Interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs, for example, when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. • Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow Interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, for example, when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. 18.9.5 TIFR – Timer/Counter Interrupt Flag Register Bit 0x36 (0x56) Read/Write Initial Value 7 OCF2 R/W 0 6 TOV2 R/W 0 5 ICF1 R/W 0 4 OCF1A R/W 0 3 OCF1B R/W 0 2 TOV1 R/W 0 1 OCF0 R/W 0 0 TOV0 R/W 0 TIFR • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 6 – TOV2: Timer/Counter2 Overflow Flag The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. ATmega64A [DATASHEET] 8160D–AVR–02/2013 152 19. Output Compare Modulator (OCM1C2) 19.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter2. For more details about these Timer/Counters see “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page 106 and “8-bit Timer/Counter2 with PWM” on page 139. Note that this feature is not available in ATmega103 compatibility mode. Figure 19-1. Output Compare Modulator, Block Diagram Timer/Counter1 OC1C Timer/Counter2 OC2 Pin OC1C/ OC2/PB7 When the modulator is enabled, the two Output Compare channels are modulated together as shown in the block diagram (Figure 19-1). 19.2 Description The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The outputs of the Output Compare units (OC1C and OC2) overrides the normal PORTB7 Register when one of them is enabled (that is, when COMnx1:0 is not equal to zero). When both OC1C and OC2 are enabled at the same time, the modulator is automatically enabled. The functional equivalent schematic of the modulator is shown on Figure 19-2 on page 154. The schematic includes part of the Timer/Counter units and the Port B pin 7 output driver circuit. ATmega64A [DATASHEET] 8160D–AVR–02/2013 153 Figure 19-2. Output Compare Modulator, Schematic. COM21 COM20 COM1C1 COM1C0 ( From Waveform Generator ) DQ ( From Waveform Generator ) OC1C DQ OC2 DQ Modulator 0 1 1 0 DQ Vcc Pin OC1C / OC2 / PB7 PORTB7 DATA BUS DDRB7 When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. 19.2.1 Timing Example Figure 19-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter2 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 19-3. Output Compare Modulator, Timing Diagram clk I/O OC1C (FPWM Mode) OC2 (CTC Mode) PB7 (PORTB7 = 0) PB7 (PORTB7 = 1) (Period) 1 2 3 In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated by the Output Compare unit C of the Timer/Counter1.The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is equal to the number of system clock cycles of one period of the carrier (OC2). In this example the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure 19-3 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2 high time is one cycle longer than the period three high time, but the result on the PB7 output is equal in both periods. ATmega64A [DATASHEET] 8160D–AVR–02/2013 154 20. SPI – Serial Peripheral Interface 20.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 20.2 Overview Figure 20-1. SPI Block Diagram(1) DIVIDER /2/4/8/16/32/64/128 SPI2X SPI2X Note: 1. Refer to Figure 1-1 on page 2, and Table 14-6 on page 73 for SPI pin placement. The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega64A and peripheral devices or between several AVR devices. The interconnection between Master and Slave CPUs with SPI is shown in Figure 20-2. The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. ATmega64A [DATASHEET] 8160D–AVR–02/2013 155 When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the buffer register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of transmission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the buffer register for later use. Figure 20-2. SPI Master-Slave Interconnection MSB MASTER LSB 8 BIT SHIFT REGISTER MISO MISO MOSI MOSI MSB SLAVE LSB 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR SCK SS VCC SCK SS SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high period should be: Low periods: Longer than 2 CPU clock cycles. High periods: Longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 20-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 69. Table 20-1. Pin MOSI MISO SCK SS SPI Pin Overrides(1) Direction, Master SPI User Defined Input User Defined User Defined Direction, Slave SPI Input User Defined Input Input Note: 1. See “Alternate Functions of Port B” on page 73 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. ATmega64A [DATASHEET] 8160D–AVR–02/2013 156 DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRRnL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRnB = (1<> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. See “About Code Examples” on page 7. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ATmega64A [DATASHEET] 8160D–AVR–02/2013 174 21.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete n (RXCn) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not contain any unread data). If the receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable n (RXCIEn) in UCSRnB is set, the USART Receive Complete Interrupt will be executed as long as the RXCn flag is set (provided that global interrupts are enabled). When interruptdriven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn flag, otherwise a new interrupt will occur once the interrupt routine terminates. 21.7.4 Receiver Error Flags The USART Receiver has three error flags: Frame Error n (FEn), Data OverRun n (DORn) and USART Parity Error n (UPEn). All can be accessed by reading UCSRnA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error n (FEn) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn flag is zero when the stop bit was correctly read (as one), and the FEn flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The Data OverRun n (DORn) flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DORn flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCSRnA. The DORn flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The USART Parity Error n (UPEn) flag indicates that the next frame in the receive buffer had a Parity Error when received. If parity check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see “Parity Bit Calculation” on page 168 and “Parity Checker” on page 175. 21.7.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error n (UPEn) flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. ATmega64A [DATASHEET] 8160D–AVR–02/2013 175 21.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the receiver will no longer override the normal function of the RxD port pin. The receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 21.7.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn flag is cleared. The following code examples show how to flush the receive buffer. Assembly Code Example(1) USART_Flush: sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRnA & (1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck  12 MHz High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck  12 MHz 28.8.1 SPI Serial Programming Algorithm When writing serial data to the ATmega64A, data is clocked on the rising edge of SCK. When reading data from the ATmega64A, data is clocked on the falling edge of SCK. See Figure 28-11 for timing details. To program and verify the ATmega64A in the SPI Serial Programming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer cannot guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. ATmega64A [DATASHEET] 8160D–AVR–02/2013 288 As an alternative to using the RESET signal, PEN can be held low during Power-on Reset while SCK is set to “0”. In this case, only the PEN value at Power-on Reset is important. If the programmer cannot guarantee that SCK is held low during Power-up, the PEN method cannot be used. The device must be powered down in order to commence normal operation when using this method. 2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming Enable serial instruction to pin MOSI. 3. The SPI Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The Page size is found in Table 28-10 on page 278. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 28-14). Accessing the SPI Serial Programming interface before the Flash write operation completes can result in incorrect programming. 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 28-14). 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Note: If other commands that polling (read) are applied before any write operation (FLASH, EEPROM, Lock bits, Fuses) is completed, may result in incorrect programming. 28.8.2 Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip -erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 28-14 for tWD_FLASH value. 28.8.3 Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re- ATmega64A [DATASHEET] 8160D–AVR–02/2013 289 programmed without chip erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 28-14 for tWD_EEPROM value. Table 28-14. Minimum Wait Delay before Writing the Next Flash or EEPROM Location Symbol tWD_FUSE tWD_FLASH(1) tWD_EEPROM tWD_ERASE Minimum Wait Delay 4.5 ms 4.5 ms 9.0 ms 9.0 ms Note: 1. Flash write: per page Figure 28-11. SPI Serial Programming Waveforms SERIAL DATA INPUT MSB LSB (MOSI) SERIAL DATA OUTPUT MSB LSB (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE ATmega64A [DATASHEET] 8160D–AVR–02/2013 290 Table 28-15. SPI Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Programming Enable 1010 1100 0101 0011 xxxx xxxx Chip Erase Read Program Memory 1010 1100 0010 H000 100x xxxx xaaa aaaa xxxx xxxx bbbb bbbb Load Program Memory Page 0100 H000 xxxx xxxx xbbb bbbb Write Program Memory Page Read EEPROM Memory Write EEPROM Memory Read Lock Bits 0100 1100 xaaa aaaa bxxx xxxx 1010 0000 xxxx xaaa bbbb bbbb 1100 0000 xxxx xaaa bbbb bbbb 0101 1000 0000 0000 xxxx xxxx Write Lock Bits 1010 1100 111x xxxx xxxx xxxx Read Signature Byte Write Fuse Bits 0011 0000 xxxx xxxx xxxx xxbb 1010 1100 1010 0000 xxxx xxxx Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx Byte 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii xxxx xxxx oooo oooo iiii iiii xxoo oooo 11ii iiii oooo oooo iiii iiii iiii iiii xxxx xxii oooo oooo Operation Enable SPI Serial Programming after RESET goes low. Chip Erase EEPROM and Flash. Read H (high or low) data o from Program memory at word address a:b. Write H (high or low) data i to Program Memory page at word address b. Data low byte must be loaded before data high byte is applied within the same address. Write Program Memory Page at address a:b. Read data o from EEPROM memory at address a:b. Write data i to EEPROM memory at address a:b. Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 28-1 on page 274 for details. Write Lock bits. Set bits = “0” to program Lock bits. See Table 28-1 on page 274 for details. Read Signature Byte o at address b. Set bits = “0” to program, “1” to unprogram. See Table 28-5 on page 276 for details. Set bits = “0” to program, “1” to unprogram. See Table 28-4 on page 276 for details. Set bits = “0” to program, “1” to unprogram. See Table 28-5 on page 276 for details. Read Fuse bits. “0” = programmed, “1” = unprogrammed. See Table 28-5 on page 276 for details. ATmega64A [DATASHEET] 8160D–AVR–02/2013 291 Table 28-15. SPI Serial Programming Instruction Set (Continued) Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation Read Extendend Fuse Bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = pro-grammed, “1” = unprogrammed. See Table 28-5 on page 276 for details. Read Fuse High Bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. “0” = programmed, “1” = unprogrammed. See Table 28-4 on page 276 for details. Read Calibration Byte 0011 1000 00xx xxxx 0000 00bb oooo oooo Read Calibration Byte o at address b. Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care 28.8.4 SPI Serial Programming Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 309. 28.9 Programming Via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in running mode while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose. As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers. 28.9.1 Programming Specific JTAG Instructions The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for Programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 28-12. ATmega64A [DATASHEET] 8160D–AVR–02/2013 292 Figure 28-12. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 1 0 1 Capture-DR 0 1 Capture-IR 0 0 Shift-DR 0 Shift-IR 0 1 Exit1-DR 1 1 Exit1-IR 1 0 0 Pause-DR 0 Pause-IR 0 1 0 Exit2-DR 1 0 Exit2-IR 1 1 Update-DR 1 0 Update-IR 1 0 28.9.2 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the reset will be active as long as there is a logic 'one' in the Reset Chain. The output from this chain is not latched. The active states are: • Shift-DR: The Reset Register is shifted by the TCK input. 28.9.3 PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-bit Programming Enable Register is selected as data register. The active states are the following: • Shift-DR: the Programming enable signature is shifted into the data register. • Update-DR: The programming enable signature is compared to the correct value, and programming mode is entered if the signature is valid. ATmega64A [DATASHEET] 8160D–AVR–02/2013 293 28.9.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as data register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the data register. • Shift-DR: The data register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command. • Update-DR: The programming command is applied to the Flash inputs • Run-Test/Idle: One clock cycle is generated, executing the applied command (not always required, see Table 28-16 on page 296). 28.9.5 PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. The 1024-bit Virtual Flash Page Load Register is selected as data register. This is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the UpdateDR state is not used to transfer data from the Shift Register. The data are automatically transferred to the Flash page buffer byte-by-byte in the Shift-DR state by an internal state machine. This is the only active state: • Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically loaded into the Flash page one byte at a time. Note: The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used. 28.9.6 PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port. The 1032-bit Virtual Flash Page Read Register is selected as data register. This is a virtual scan chain with length equal to the number of bits in one Flash page plus eight. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer data to the Shift Register. The data are automatically transferred from the Flash page buffer byte-by-byte in the Shift-DR state by an internal state machine. This is the only active state: • Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the TCK input. The TDI input is ignored. Note: The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used. 28.9.7 Data Registers The data registers are selected by the JTAG instruction registers described in section “Programming Specific JTAG Instructions” on page 292. The data registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Virtual Flash Page Load Register • Virtual Flash Page Read Register 28.9.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering programming mode. A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out Period (refer to “Clock Sources” on page 35) after releasing the Reset Register. ATmega64A [DATASHEET] 8160D–AVR–02/2013 294 The output from this data register is not latched, so the reset will take place immediately, as shown in Figure 26-2 on page 243. 28.9.9 Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 28-13. Programming Enable Register TDI D A $A370 = T A D Q Programming Enable ClockDR & PROG_ENABLE TDO 28.9.10 Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 28-16. The state sequence when shifting in the programming commands is illustrated in Figure 28-15. Figure 28-14. Programming Command Register TDI S T R O B E S A Flash D EEPROM D Fuses R Lock Bits E S S / D A T A TDO ATmega64A [DATASHEET] 8160D–AVR–02/2013 295 Table 28-16. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx (2) 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9) 2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx 2f. Latch Data 0110111_00000000 xxxxxxx_xxxxxxxx (1) 1110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2g. Write Flash Page 0110111_00000000 xxxxxxx_xxxxxxxx (1) 0110101_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2h. Poll for Page Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9) 3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 3d. Read Data Low and High Byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo low byte high byte 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9) 4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 4e. Latch Data 0110111_00000000 xxxxxxx_xxxxxxxx (1) 1110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 4f. Write EEPROM Page 0110011_00000000 xxxxxxx_xxxxxxxx (1) 0110001_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9) 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx ATmega64A [DATASHEET] 8160D–AVR–02/2013 296 Table 28-16. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 6a. Enter Fuse Write 6b. Load Data Low Byte(6) 0100011_01000000 xxxxxxx_xxxxxxxx 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. Write Fuse Extended Byte 0111011_00000000 xxxxxxx_xxxxxxxx (1) 0111001_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_xxxxxxxx 6d. Poll for Fuse Write Complete 6e. Load Data Low Byte(7) 0111011_00000000 xxxxxox_xxxxxxxx (2) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. Write Fuse High Byte 0110111_00000000 xxxxxxx_xxxxxxxx (1) 0110101_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 6g. Poll for Fuse Write Complete 6h. Load Data Low Byte(8) 0110111_00000000 xxxxxox_xxxxxxxx (2) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. Write Fuse Low byte 0110011_00000000 xxxxxxx_xxxxxxxx (1) 0110001_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 6j. Poll for Fuse Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 7a. Enter Lock Bit Write 7b. Load Data Byte(9) 0100011_00100000 xxxxxxx_xxxxxxxx 0010011_11iiiiii xxxxxxx_xxxxxxxx (4) 7c. Write Lock Bits 0110011_00000000 xxxxxxx_xxxxxxxx (1) 0110001_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 7d. Poll for Lock Bit Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 8a. Enter Fuse/Lock Bit Read 8b. Read Fuse Extended Byte(6) 8c. Read Fuse High Byte(7) 8d. Read Fuse Low Byte(8) 8e. Read Lock Bits(9) 0100011_00000100 0111010_00000000 0111111_00000000 0111110_00000000 0111111_00000000 0110010_00000000 0110011_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx (5) xxxxxxx_xxoooooo ATmega64A [DATASHEET] 8160D–AVR–02/2013 297 Table 28-16. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 9c. Read Signature Byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo Note: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is normally the case). 2. Repeat until o = “1”. 3. Set bits to “0” to program the corresponding fuse, “1” to unprogram the fuse. 4. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged. 5. “0” = programmed, “1” = unprogrammed. 6. The bit mapping for Fuses Extended byte is listed in Table 28-3 on page 275. 7. The bit mapping for Fuses High byte is listed in Table 28-4 on page 276. 8. The bit mapping for Fuses Low byte is listed in Table 28-5 on page 276. 9. The bit mapping for Lock bits byte is listed in Table 28-1 on page 274. 10. Address bits exceeding PCMSB and EEAMSB (Table 28-9 and Table 28-10) are don’t care. ATmega64A [DATASHEET] 8160D–AVR–02/2013 298 Figure 28-15. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 1 0 1 Capture-DR 0 1 Capture-IR 0 0 Shift-DR 0 Shift-IR 0 1 Exit1-DR 1 1 Exit1-IR 1 0 0 Pause-DR 0 Pause-IR 0 1 0 Exit2-DR 1 0 Exit2-IR 1 1 Update-DR 1 0 Update-IR 1 0 28.9.11 Virtual Flash Page Load Register The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically transferred to the Flash page buffer byteby-byte. Shift in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to load the entire Flash page buffer before executing Page Write. ATmega64A [DATASHEET] 8160D–AVR–02/2013 299 Figure 28-16. Virtual Flash Page Load Register State Machine STROBES ADDRESS TDI D A T A Flash EEPROM Fuses Lock Bits TDO 28.9.12 Virtual Flash Page Read Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte-by-byte. The first eight cycles are used to transfer the first byte to the internal Shift Register, and the bits that are shifted out during these eight cycles should be ignored. Following this initialization, data are shifted out starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to read one full Flash page to verify programming. Figure 28-17. Virtual Flash Page Read Register State Machine STROBES ADDRESS Flash TDI EEPROM Fuses Lock Bits D A T A TDO 28.9.13 Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 28-16. ATmega64A [DATASHEET] 8160D–AVR–02/2013 300 28.9.14 Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 28.9.15 Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the Programming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. 28.9.16 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start chip erase using programming instruction 1a. 3. Poll for chip erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 1 on page 286). 28.9.17 Programming the Flash Before programming the Flash, a Chip Erase must be performed. See “Performing Chip Erase” on page 301. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address high byte using programming instruction 2b. 4. Load address low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH_FLASH (refer to Table 1 on page 286). 9. Repeat steps 3 to 7 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 28-9 on page 278) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGELOAD. 5. Load the entire page by shifting in all instruction words in the page, starting with the LSB of the first instruc- tion in the page and ending with the MSB of the last instruction in the page. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH_FLASH (refer to Table 1 on page 286). 9. Repeat steps 3 to 8 until all data have been programmed. 28.9.18 Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. ATmega64A [DATASHEET] 8160D–AVR–02/2013 301 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 28-9 on page 278) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page by shifting out all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Remember that the first eight bits shifted out should be ignored. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. 28.9.19 Programming the EEPROM Before programming the EEPROM, a Chip Erase must be performed. See “Performing Chip Erase” on page 301. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address high byte using programming instruction 4b. 4. Load address low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7. Write the data using programming instruction 4f. 8. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to Table 1 on page 286). 9. Repeat steps 3 to 8 until all data have been programmed. Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM. 28.9.20 Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM 28.9.21 Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data Low byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. 4. Write Fuse Extended byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 1 on page 286). 6. Load data Low byte using programming instructions 6e. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. ATmega64A [DATASHEET] 8160D–AVR–02/2013 302 7. Write Fuse High byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 1 on page 286). 9. Load data low byte using programming instructions 6h. A “0” will program the fuse, a “1” will unprogram the fuse. 10. Write Fuse low byte using programming instruction 6i. 11. Poll for Fuse write complete using programming instruction 6j, or wait for tWLRH (refer to Table 1 on page 286). 28.9.22 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding Lock bit, a “1” will leave the Lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 1 on page 286). 28.9.23 Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8f. To only read Fuse Extended byte, use programming instruction 8b. To only read Fuse High byte, use programming instruction 8c. To only read Fuse Low byte, use programming instruction 8d. To only read Lock bits, use programming instruction 8e. 28.9.24 Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address 0x00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 28.9.25 Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3. Load address 0x00 using programming instruction 10b. 4. Read the calibration byte using programming instruction 10c. ATmega64A [DATASHEET] 8160D–AVR–02/2013 303 29. Electrical Characteristics – TA = -40°C to 85°C 29.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins..................... 200.0 - 400.0mA 29.2 DC Characteristics TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min Typ VIL Input Low Voltage except XTAL1 and RESET pins VCC=2.7V - 5.5V -0.5 VIH Input High Voltage except XTAL1 and RESET pins VCC=2.7V - 5.5V 0.6 VCC(2) Input Low Voltage VIL1 XTAL1 pin VCC=2.7V - 5.5V -0.5 Input High Voltage VIH1 XTAL1 pin VCC=2.7V - 5.5V 0.7 VCC(2) Input Low Voltage VIL2 RESET pin VCC=2.7V - 5.5V -0.5 Input High Voltage VIH2 RESET pin VCC=2.7V - 5.5V 0.85 VCC(2) VOL Output Low Voltage(3) (Ports A,B,C,D, E, F, G) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V VOH Output High Voltage(4) (Ports A,B,C,D, E, F, G)) IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V 4.2 2.2 IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) RRST Reset Pull-up Resistor 30 RPEN PEN Pull-up Resistor 30 RPU I/O Pin Pull-up Resistor 20 Max 0.2 VCC(1) VCC + 0.5 0.1 VCC(1) VCC + 0.5 0.2 VCC(1) VCC + 0.5 0.9 0.6 1.0 1.0 60 60 50 Units V V V V V V V V V V µA µA k k k ATmega64A [DATASHEET] 8160D–AVR–02/2013 304 29.2 DC Characteristics TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Units Active 4 MHz, VCC = 3V 2.5 5 mA Power Supply Current Active 8 MHz, VCC = 5V ICC Idle 4 MHz, VCC = 3V Idle 8 MHz, VCC = 5V 8.1 20 mA 0.7 2 mA 2.8 12 mA Power-down mode(5) WDT enabled, VCC = 3V WDT disabled, VCC = 3V < 10 20 µA <4 10 µA VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 -40 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V 750 500 ns Note: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA. 3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA. 5] The sum of all IOL, for ports F0 - F7, should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA. 3] The sum of all IOH, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOH, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA. 5] The sum of all IOH, for ports F0 - F7, should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V. ATmega64A [DATASHEET] 8160D–AVR–02/2013 305 29.3 Speed Grades Figure 29-1. Maximum Frequency vs. Vcc 16 MHz 8 MHz Safe Operating Area 2.7V 29.4 Clock Characteristics 29.4.1 External Clock Drive Waveforms Figure 29-2. External Clock Drive Waveforms VIH1 VIL1 4.5V 5.5V 29.4.2 External Clock Drive Table 29-1. External Clock Drive(1) Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL tCLCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Change in period from one clock cycle to the next VCC = 2.7V to 5.5V Min Max 0 8 125 50 50 1.6 1.6 2 VCC = 4.5V to 5.5V Min Max 0 16 62.5 25 25 0.5 0.5 2 Units MHz ns ns ns s s % ATmega64A [DATASHEET] 8160D–AVR–02/2013 306 Note: 1. Refer to “External Clock” on page 40 for details. Table 29-2. External RC Oscillator, Typical Frequencies R [k](1) C [pF] 31.5 20 6.5 20 f(2) 650 kHz 2.0 MHz Note: 1. R should be in the range 3k - 100k, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout. 29.5 System and Reset Characteristics Table 29-3. Reset, Brown-out and internal Voltage reference Characteristics Symbol VPOT VRST tRST VBOT Parameter Power-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling)(1) RESET Pin Threshold Voltage Minimum pulse width on RESET Pin Brown-out Reset Threshold Voltage(2) tBOD Minimum low voltage period for Brown-out Detection VHYST VBG tBG IBG Brown-out Detector hysteresis Bandgap reference voltage Bandgap reference start-up time Bandgap reference current consumption Condition BODLEVEL = 1 BODLEVEL = 0 BODLEVEL = 1 BODLEVEL = 0 Min Typ Max 1.4 2.3 1.3 2.3 0.2 VCC 0.85 VCC 1.5 2.5 2.7 2.9 3.6 4.0 4.2 2 2 120 1.15 1.23 1.35 40 70 10 Units V V V µs V µs µs mV V µs µA Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). 2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. ATmega64A [DATASHEET] 8160D–AVR–02/2013 307 29.6 Two-wire Serial Interface Characteristics Table 29-4 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega64A Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 29-3. Table 29-4. Two-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys(1) VOL(1) tr(1) tof(1) tSP(1) Ii Ci(1) fSCL Input Low-voltage Input High-voltage Hysteresis of Schmitt Trigger Inputs Output Low-voltage Rise Time for both SDA and SCL Output Fall Time from VIHmin to VILmax Spikes Suppressed by Input Filter Input Current each I/O Pin Capacitance for each I/O Pin SCL Clock Frequency Rp Value of Pull-up resistor tHD;STA Hold Time (repeated) START Condition tLOW Low Period of the SCL Clock tHIGH High period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO tBUF Setup time for STOP condition Bus free time between a STOP and START condition Condition 3 mA sink current 10 pF < Cb < 400 pF(3) 0.1 VCC < Vi < 0.9 VCC fCK(4) > max(16fSCL, 250 kHz)(5) fSCL  100 kHz fSCL > 100 kHz fSCL  100 kHz fSCL > 100 kHz fSCL  100 kHz(5) fSCL > 100 kHz fSCL  100 kHz fSCL > 100 kHz fSCL  100 kHz fSCL > 100 kHz fSCL  100 kHz fSCL > 100 kHz fSCL  100 kHz fSCL > 100 kHz fSCL  100 kHz fSCL > 100 kHz fSCL  100 kHz Min -0.5 0.7 VCC 0.05 VCC(2) 0 20 + 0.1Cb(3)(2) 20 + 0.1Cb(3)(2) 0 -10 – 0 -V---C----C----–-----0---.--4---V--3mA -V---C----C----–-----0---.--4---V--3mA 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 0 250 100 4.0 0.6 4.7 Max 0.3 VCC VCC + 0.5 – 0.4 300 250 50(2) 10 10 400 1----0---C0----0b---n---s-3----0-C--0---b-n---s– – – – – – – – 3.45 0.9 – – – – – Units V V V V ns ns ns µA pF kHz   µs µs µs µs µs µs µs µs µs µs ns ns µs µs µs Notes: 1. In ATmega64A, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100 kHz. ATmega64A [DATASHEET] 8160D–AVR–02/2013 308 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all ATmega64A Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. Figure 29-3. Two-wire Serial Bus Timing SCL SDA tSU;STA tof tLOW tHD;STA tHIGH tHD;DAT tLOW tSU;DAT tr tSU;STO tBUF 29.7 SPI Timing Characteristics See Figure 29-4 on page 310 and Figure 29-5 on page 310 for details. Table 29-5. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period 2 SCK high/low 3 Rise/Fall time 4 Setup 5 Hold 6 Out to SCK 7 SCK to out 8 SCK to out high 9 SS low to out 10 SCK period 11 SCK high/low(1) 12 Rise/Fall time 13 Setup 14 Hold 15 SCK to out 16 SCK to SS high 17 SS high to tri-state 18 SS low to SCK Master See Table 20-5 Master 50% duty cycle Master 3.6 Master 10 Master 10 Master Master 0.5 • tsck ns 10 Master 10 Slave 15 Slave Slave Slave 4 • tck 2 • tck 1.6 µs Slave 10 Slave tck Slave 15 ns Slave 20 Slave 10 Slave 20 Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12 MHz - 3 tCLCL for fCK >12 MHz ATmega64A [DATASHEET] 8160D–AVR–02/2013 309 Figure 29-4. SPI Interface Timing Requirements (Master Mode) SS 6 SCK (CPOL = 0) SCK (CPOL = 1) MISO (Data Input) MOSI (Data Output) 45 MSB 7 MSB ... ... Figure 29-5. SPI Interface Timing Requirements (Slave Mode) 18 SS 9 SCK (CPOL = 0) SCK (CPOL = 1) 13 14 MOSI (Data Input) MSB ... 15 MISO (Data Output) MSB ... 1 2 2 LSB LSB 3 8 10 16 11 11 12 LSB 17 LSB X ATmega64A [DATASHEET] 8160D–AVR–02/2013 310 29.8 ADC Characteristics Table 29-6. ADC Characteristics, Single Ended Channels, -40C – 85C Symbol Parameter Condition Resolution Single Ended Conversion Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Absolute Accuracy (Including INL, DNL, Quantization Error, Gain and Offset Error) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Noise Reduction mode Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz Noise Reduction mode Integral Non-Linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Differential Non-Linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Gain Error Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Offset error Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Clock Frequency Conversion Time AVCC Analog Supply Voltage VREF VIN Reference Voltage Input Voltage ADC Conversion Output Input Bandwidth VINT RREF RAIN Internal Voltage Reference Reference Input Resistance Analog Input Resistance Notes: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. Min 50 13 VCC – 0.3(1) 2.0 GND 0 2.4 Typ 1.5 3 1.5 3 0.75 0.25 0.75 0.75 38.5 2.56 32 Max Units 10 Bits LSB LSB LSB LSB LSB LSB LSB LSB 1000 kHz 260 µs VCC + 0.3(2) V AVCC V VREF 1023 V LSB kHz 2.8 V k 100 M ATmega64A [DATASHEET] 8160D–AVR–02/2013 311 Table 29-7. ADC Characteristics, Differential Channels, -40C – 85C Symbol Parameter Condition Gain = 1x Resolution Gain = 10x Gain = 200x Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Absolute Accuracy Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Integral Non-Linearity (INL) (Accuracy after Calibration for Offset and Gain Error) Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 1x Gain Error Gain = 10x Gain = 200x Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Offset Error Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Clock Frequency Conversion Time AVCC Analog Supply Voltage VREF VIN VDIFF Reference Voltage Input Voltage Input Differential Voltage ADC Conversion Output Input Bandwidth Min 50 13 VCC – 0.3(1) 2.0 GND -VREF/Gain -511 Typ 16 16 8 0.75 0.75 2.5 1.6 1.6 0.3 1.5 1 6 4 Max Units 10 Bits 10 Bits 10 Bits LSB LSB LSB LSB LSB LSB % % % LSB LSB LSB 1000 260 VCC + 0.3(2) AVCC – 0.5 VCC VREF/Gain 511 kHz µs V V V V LSB kHz ATmega64A [DATASHEET] 8160D–AVR–02/2013 312 Table 29-7. ADC Characteristics, Differential Channels, -40C – 85C (Continued) Symbol Parameter Condition Min Typ Max VINT Internal Voltage Reference RREF Reference Input Resistance RAIN Analog Input Resistance Notes: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. 2.3 2.56 2.7 32 100 29.9 External Data Memory Timing Table 29-8. External Data Memory Characteristics, 4.5 - 5.5 volts, No Wait-state 8 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL Oscillator Frequency 0.0 16 1 tLHLL 2 tAVLL ALE Pulse Width Address Valid A to ALE Low 115 57.5 1.0tCLCL-10 0.5tCLCL-5(1) 3a tLLAX_ST Address Hold After ALE Low, write access 5 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 4 tAVLLC Address Valid C to ALE Low 57.5 0.5tCLCL-5(1) 5 tAVRL Address Valid to RD Low 115 1.0tCLCL-10 6 tAVWL Address Valid to WR Low 115 1.0tCLCL-10 7 tLLWL ALE Low to WR Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) 8 tLLRL ALE Low to RD Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) 9 tDVRH Data Setup to RD High 40 40 10 tRLDV Read Low to Data Valid 75 1.0tCLCL-50 11 tRHDX Data Hold After RD High 0 0 12 tRLRH 13 tDVWL RD Pulse Width Data Setup to WR Low 115 42.5 1.0tCLCL-10 0.5tCLCL-20(1) 14 tWHDX Data Hold After WR High 115 1.0tCLCL-10 15 tDVWH Data Valid to WR High 125 1.0tCLCL 16 tWLWH WR Pulse Width 115 1.0tCLCL-10 Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. Units V k M Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ATmega64A [DATASHEET] 8160D–AVR–02/2013 313 Table 29-9. External Data Memory Characteristics, 4.5 - 5.5 volts, 1 Cycle Wait-state 8 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 10 tRLDV 12 tRLRH 15 tDVWH 16 tWLWH Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 0.0 16 200 2.0tCLCL-50 240 2.0tCLCL-10 240 2.0tCLCL 240 2.0tCLCL-10 Table 29-10. External Data Memory Characteristics, 4.5 - 5.5 volts, SRWn1 = 1, SRWn0 = 0 4 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 10 tRLDV 12 tRLRH 15 tDVWH 16 tWLWH Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 0.0 16 325 3.0tCLCL-50 365 3.0tCLCL-10 375 3.0tCLCL 365 3.0tCLCL-10 Table 29-11. External Data Memory Characteristics, 4.5 - 5.5 volts, SRWn1 = 1, SRWn0 = 1 4 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL Oscillator Frequency 0.0 16 10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 14 tWHDX Data Hold After WR High 240 2.0tCLCL-10 15 tDVWH Data Valid to WR High 375 3.0tCLCL 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 Table 29-12. External Data Memory Characteristics, 2.7 - 5.5 volts, No Wait-state 4 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL Oscillator Frequency 1 tLHLL ALE Pulse Width 235 2 tAVLL Address Valid A to ALE Low 115 3a tLLAX_ST Address Hold After ALE Low, write access 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 4 tAVLLC Address Valid C to ALE Low 115 5 tAVRL Address Valid to RD Low 235 0.0 8 tCLCL-15 0.5tCLCL-10(1) 5 5 0.5tCLCL-10(1) 1.0tCLCL-15 Unit MHz ns ns ns ns Unit MHz ns ns ns ns Unit MHz ns ns ns ns ns Unit MHz ns ns ns ns ns ns ATmega64A [DATASHEET] 8160D–AVR–02/2013 314 Table 29-12. External Data Memory Characteristics, 2.7 - 5.5 volts, No Wait-state (Continued) 4 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 6 tAVWL Address Valid to WR Low 235 1.0tCLCL-15 7 tLLWL ALE Low to WR Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) 8 tLLRL ALE Low to RD Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) 9 tDVRH Data Setup to RD High 45 45 10 tRLDV Read Low to Data Valid 190 1.0tCLCL-60 11 tRHDX Data Hold After RD High 0 0 12 tRLRH RD Pulse Width 235 1.0tCLCL-15 13 tDVWL Data Setup to WR Low 105 0.5tCLCL-20(1) 14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 15 tDVWH Data Valid to WR High 250 1.0tCLCL 16 tWLWH WR Pulse Width 235 1.0tCLCL-15 Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. Unit ns ns ns ns ns ns ns ns ns ns ns Table 29-13. External Data Memory Characteristics, 2.7 - 5.5 volts, SRWn1 = 0, SRWn0 = 1 4 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 10 tRLDV 12 tRLRH 15 tDVWH 16 tWLWH Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 0.0 8 440 2.0tCLCL-60 485 2.0tCLCL-15 500 2.0tCLCL 485 2.0tCLCL-15 Table 29-14. External Data Memory Characteristics, 2.7 - 5.5 volts, SRWn1 = 1, SRWn0 = 0 4 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 10 tRLDV 12 tRLRH 15 tDVWH 16 tWLWH Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 0.0 8 690 3.0tCLCL-60 735 3.0tCLCL-15 750 3.0tCLCL 735 3.0tCLCL-15 Table 29-15. External Data Memory Characteristics, 2.7 - 5.5 volts, SRWn1 = 1, SRWn0 = 1 4 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 0 1/tCLCL 10 tRLDV 12 tRLRH Oscillator Frequency Read Low to Data Valid RD Pulse Width 0.0 8 690 3.0tCLCL-60 735 3.0tCLCL-15 Unit MHz ns ns ns ns Unit MHz ns ns ns ns Unit MHz ns ns ATmega64A [DATASHEET] 8160D–AVR–02/2013 315 Table 29-15. External Data Memory Characteristics, 2.7 - 5.5 volts, SRWn1 = 1, SRWn0 = 1 4 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max 14 tWHDX Data Hold After WR High 485 15 tDVWH Data Valid to WR High 750 16 tWLWH WR Pulse Width 735 2.0tCLCL-15 3.0tCLCL 3.0tCLCL-15 Figure 29-6. External Memory Timing (SRWn1 = 0, SRWn0 = 0 T1 T2 T3 System Clock (CLKCPU) 1 ALE A15:8 Prev. addr. DA7:0 Prev. data 4 7 2 3a 13 Address XX Address 15 Data 6 16 WR DA7:0 (XMBK = 0) RD 3b Address 5 8 9 Data 10 12 T4 14 11 Write Read Unit ns ns ns Figure 29-7. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 System Clock (CLKCPU) 1 ALE 4 7 A15:8 Prev. addr. DA7:0 Prev. data Address 2 3a 13 Address XX 15 Data 6 16 WR DA7:0 (XMBK = 0) RD 3b Address 5 10 8 9 Data 12 T5 14 11 Write Read ATmega64A [DATASHEET] 8160D–AVR–02/2013 316 Figure 29-8. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T4 System Clock (CLKCPU) 1 ALE 4 7 A15:8 Prev. addr. DA7:0 Prev. data WR 2 3a 13 Address XX 6 Address 15 Data 16 DA7:0 (XMBK = 0) 3b Address 5 10 8 9 Data 12 RD T5 T6 14 11 Write Read Figure 29-9. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T4 T5 System Clock (CLKCPU) 1 T6 T7 ALE 4 7 A15:8 Prev. addr. 2 3a 13 Address 15 DA7:0 Prev. data Address XX Data 6 16 14 WR 3b 9 11 DA7:0 (XMBK = 0) Address 5 10 Data 8 12 RD Write Read Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external). ATmega64A [DATASHEET] 8160D–AVR–02/2013 317 30. Electrical Characteristics – TA = -40°C to 105°C 30.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Current per I/O Pin ................................................ 40.0mA DC Current VCC and GND Pins..................... 200.0 - 400.0mA 30.2 DC Characteristics TA = -40C to 105C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min Typ VIL Input Low Voltage except XTAL1 and RESET pins VCC=2.7V - 5.5V -0.5 VIH Input High Voltage except XTAL1 and RESET pins VCC=2.7V - 5.5V 0.6 VCC(2) Input Low Voltage VIL1 XTAL1 pin VCC=2.7V - 5.5V -0.5 Input High Voltage VIH1 XTAL1 pin VCC=2.7V - 5.5V 0.7 VCC(2) Input Low Voltage VIL2 RESET pin VCC=2.7V - 5.5V -0.5 Input High Voltage VIH2 RESET pin VCC=2.7V - 5.5V 0.85 VCC(2) VOL Output Low Voltage(3) (Ports A,B,C,D, E, F, G) IOL = 20mA, VCC = 5V IOL = 10mA, VCC = 3V VOH Output High Voltage(4) (Ports A,B,C,D, E, F, G)) IOH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V 4.2 2.2 IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) RRST Reset Pull-up Resistor 30 RPEN PEN Pull-up Resistor 30 RPU I/O Pin Pull-up Resistor 20 Max 0.2 VCC(1) VCC + 0.5 0.1 VCC(1) VCC + 0.5 0.2 VCC(1) VCC + 0.5 0.9 0.6 Units V 1.0 µA 1.0 60 60 k 50 ATmega64A [DATASHEET] 8160D–AVR–02/2013 318 30.2 DC Characteristics TA = -40C to 105C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Units Active 4MHz, VCC = 3V 2.5 5 Power Supply Current Active 8MHz, VCC = 5V ICC Idle 4MHz, VCC = 3V Idle 8MHz, VCC = 5V 8.1 20 mA 0.7 2 2.8 12 Power-down mode(5) WDT enabled, VCC = 3V WDT disabled, VCC = 3V < 10 25 µA <4 10 VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 -40 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V 750 500 ns Note: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 400mA. 2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 100mA. 3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100mA. 4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100mA. 5] The sum of all IOL, for ports F0 - F7, should not exceed 100mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOH, for all ports, should not exceed 400mA. 2] The sum of all IOH, for ports A0 - A7, G2, C3 - C7 should not exceed 100mA. 3] The sum of all IOH, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100mA. 4] The sum of all IOH, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100mA. 5] The sum of all IOH, for ports F0 - F7, should not exceed 100mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V. ATmega64A [DATASHEET] 8160D–AVR–02/2013 319 31. Typical Characteristics – TA = -40°C to 85°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: Operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 31.1 Active Supply Current Figure 31-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) 2.5 5.5 V 2 5.0 V 4.5 V 4.0 V 1.5 3.6 V 3.3 V 2.7 V 1 ICC (mA) 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ATmega64A [DATASHEET] 8160D–AVR–02/2013 320 ICC (mA) Figure 31-2. Active Supply Current vs. Frequency (1 - 16 MHz) 20 16 12 8 3.3 V 4 2.7 V 5.5 V 5.0 V 4.5 V 3.6 V 4.0 V 0 0 2 4 6 8 10 12 14 Frequency (MHz) Figure 31-3. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 2.4 2.2 2 1.8 ICC (mA) 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 VCC (V) 16 85 °C 25 °C 0 °C -40 °C 5.5 ATmega64A [DATASHEET] 8160D–AVR–02/2013 321 Figure 31-4. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz,) 4.5 4 3.5 -40 °C 25 °C 85 °C ICC (mA) 3 2.5 2 1.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-5. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) 7 6 -40 °C 25 °C 85 °C 5 ICC (mA) 4 3 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 322 Figure 31-6. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 12 11 10 -40 °C 25 °C 85 °C 9 ICC (mA) 8 7 6 5 4 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-7. Active Supply Current vs. VCC (32 kHz External Oscillator) 90 25 °C 80 ICC (mA) 70 60 50 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 323 31.2 Idle Supply Current Figure 31-8. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.6 5.5 V 0.5 5.0 V 4.5 V 0.4 4.0 V 3.6 V 0.3 3.3 V 2.7 V 0.2 ICC (mA) 0.1 0 0.1 0.2 0.3 0.4 0,5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 31-9. Idle Supply Current vs. Frequency (1 - 16 MHz) 8 6 5.5 V 5.0 V 4.5 V ICC (mA) 4.0 V 4 3.6 V 2 3.3 V 2.7 V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) ATmega64A [DATASHEET] 8160D–AVR–02/2013 324 Figure 31-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.7 0.6 85 °C 25 °C -40 °C 0.5 ICC (mA) 0.4 0.3 0,2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0,4 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 325 Figure 31-12. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) 2.6 2.2 -40 °C 25 °C 85 °C ICC (mA) 1.8 1.4 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-13. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 5 4.5 -40 °C 25 °C 85 °C 4 ICC (mA) 3.5 3 2.5 2 1.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 326 Figure 31-14. Idle Supply Current vs. VCC (32 kHz External Oscillator) 30 25 25 °C 20 ICC (mA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 31.3 Power-Down Supply Current Figure 31-15. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 3.5 3 85 °C 2.5 ICC (uA) 2 -40 °C 1.5 25 °C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 327 Figure 31-16. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 25 21 17 85 °C 25 °C -40 °C ICC (uA) 13 9 5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 31.4 Power-Save Supply Current Figure 31-17. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled) 12 11 25 °C 10 ICC (uA) 9 8 7 6 5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 328 31.5 Standby Supply Current Figure 31-18. Standby Supply Current vs. VCC 0.16 0.14 6MHz Xtal 6MHz Res ICC (mA) 0.12 0.1 0.08 0.06 4MHz Res 4MHz Xtal 2MHz Res 2MHz Xtal 450kHz Re 1MHz Res 0.04 0.02 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-19. Standby Supply Current vs. VCC (CKOPT Programmed) 2 1.6 16MHz Xtal 12MHz Xtal ICC (mA) 1.2 6MHz Xtal 4MHz Xtal 0.8 0.4 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 329 31.6 Pin Pull-up Figure 31-20. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 100 IOP (uA) 80 60 40 20 25 °C -40 °C 85 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 31-21. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 50 IOP (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 VOP (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 330 Figure 31-22. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 80 IRESET (uA) 60 40 20 -40 °C 25 °C 0 85 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) Figure 31-23. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 40 IRESET (uA) 30 20 10 -40 °C 25 °C 0 85 °C 0 0.5 1 1.5 2 2.5 3 VRESET (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 331 Figure 31-24. PEN Pull-up Resistor Current vs. PEN Pin Voltage (VCC = 5V) 140 120 100 IPEN (uA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 VPEN (V) Figure 31-25. PEN Pull-up Resistor Current vs. PEN Pin Voltage (VCC = 2.7V) 80 70 60 50 IPEN (uA) 40 30 20 10 0 0 0.5 1 1.5 2 VPEN (V) 4 4.5 2.5 25 °C 85 °C -40 °C 5 25 °C 85 °C -40 °C 3 ATmega64A [DATASHEET] 8160D–AVR–02/2013 332 31.7 Pin Driver Strength Figure 31-26. I/O Pin Source Current vs. Output Voltage (VCC = 5V) 90 80 70 60 IOH (mA) 50 40 30 20 10 0 3 3.4 3.8 4.2 4.6 VOH (V) Figure 31-27. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) 35 30 25 IOH (mA) 20 15 10 5 0 0.5 1 1.5 2 2.5 VOH (V) -40 °C 25 °C 85 °C 5 -40 °C 25 °C 85 °C 3 ATmega64A [DATASHEET] 8160D–AVR–02/2013 333 Figure 31-28. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) IOL (mA) 90 80 70 60 50 40 30 20 10 0 0 0.4 0.8 1.2 1.6 VOL (V) Figure 31-29. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) 35 30 25 IOL (mA) 20 15 10 5 0 0 0.4 0.8 1.2 1.6 VOL (V) -40 °C 25 °C 85 °C 2 -40 °C 25 °C 85 °C 2 ATmega64A [DATASHEET] 8160D–AVR–02/2013 334 31.8 Pin Thresholds and Hysteresis Figure 31-30. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as '1') 3 2.6 85 °C 25 °C -40 °C Threshold (V) 2.2 1.8 1.4 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-31. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as '0') 2.5 2.2 -40 °C 85 °C 25 °C 1.9 Threshold (V) 1.6 1.3 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 335 Figure 31-32. I/O Pin Input Hysteresis vs. VCC 0.8 0.6 Input Hysteresis (mV) 0.4 0.2 0 2.5 3 3.5 4 4.5 5 VCC (V) Figure 31-33. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1') 2.4 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 VCC (V) 85 °C 25 °C -40 °C 5.5 -40 °C 25 °C 85 °C 5.5 ATmega64A [DATASHEET] 8160D–AVR–02/2013 336 Figure 31-34. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as '0') 2.4 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 VCC (V) Figure 31-35. Reset Input Pin Hysteresis vs. VCC 0.5 0.4 Input Hysteresis (mV) 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 VCC (V) -40 °C 25 °C 85 °C 5.5 -40 °C 25 °C 85 °C 5.5 ATmega64A [DATASHEET] 8160D–AVR–02/2013 337 31.9 BOD Thresholds and Analog Comparator Offset Figure 31-36. BOD Thresholds vs. Temperature (BODLEVEL is 4.0V) 3.92 Rising Vcc 3.9 3.88 Threshold (V) 3.86 3.84 3.82 3.8 3.78 Falling Vcc 3.76 -40 -25 -10 5 20 35 50 65 80 95 Temperature (°C) Figure 31-37. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) Threshold (V) 2.76 2.74 Rising Vcc 2.72 2.7 2.68 2.66 2.64 Falling Vcc 2.62 2.6 -40 -25 -10 5 20 35 50 65 80 95 Temperature (°C) ATmega64A [DATASHEET] 8160D–AVR–02/2013 338 Figure 31-38. Bandgap Voltage vs. VCC 1.215 1.21 85 °C 25 °C Bandgap Voltage (V) 1.205 1.2 -40 °C 1.195 1.19 1.185 1.18 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 31.10 Internal Oscillator Speed Figure 31-39. Watchdog Oscillator Frequency vs. VCC 1180 1160 25 °C -40 °C 85 °C 1140 FRC (kHz) 1120 1100 1080 1060 1040 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 339 Figure 31-40. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature 1.02 FRC (MHz) 1 5.5 V 0.98 5.0 V 4.5 V 0.96 4.0 V 3.6 V 3.3 V 0.94 2.7 V 0.92 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) Figure 31-41. Calibrated 1 MHz RC Oscillator Frequency vs. VCC 1.02 1 0.98 -40 °C 25 °C 85 °C FRC (MHz) 0.96 0.94 0.92 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 340 FRC (MHz) Figure 31-42. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value 1.8 25 °C 1.6 1.4 1.2 1 0.8 0.6 0.4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE Figure 31-43. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature 2.05 FRC (MHz) 2 5.5 V 1.95 5.0 V 4.5 V 1.9 4.0 V 3.6 V 3.3 V 1.85 3.0 V 2.7 V 1.8 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) ATmega64A [DATASHEET] 8160D–AVR–02/2013 341 Figure 31-44. Calibrated 2 MHz RC Oscillator Frequency vs. VCC 2.05 2 1.95 -40 °C 25 °C 85 °C FRC (MHz) 1.9 1.85 1.8 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-45. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value 3.6 25 °C 3.2 2.8 FRC (MHz) 2.4 2 1.6 1.2 0.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE ATmega64A [DATASHEET] 8160D–AVR–02/2013 342 Figure 31-46. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature 4.1 FRC (MHz) 4 5.5 V 3.9 5.0 V 4.5 V 3.8 4.0 V 3.6 V 3.3 V 3.7 2.7 V 3.6 3.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) Figure 31-47. Calibrated 4 MHz RC Oscillator Frequency vs. VCC 4.1 4 3.9 -40 °C 25 °C 85 °C FRC (MHz) 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 343 Figure 31-48. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value FRC (MHz) 8 25 °C 7 6 5 4 3 2 1 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE Figure 31-49. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature FRC (MHz) 8.4 8.2 8 7.8 5.5 V 5.0 V 7.6 4.5 V 7.4 4.0 V 7.2 3.6 V 3.3 V 7 6.8 2.7 V 6.6 6.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) ATmega64A [DATASHEET] 8160D–AVR–02/2013 344 Figure 31-50. Calibrated 8 MHz RC Oscillator Frequency vs. VCC FRC (MHz) 8.4 -40 °C 8.2 25 °C 8 7.8 85 °C 7.6 7.4 7.2 7 6.8 6.6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-51. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value 15 25 °C 13 11 FRC (MHz) 9 7 5 3 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE ATmega64A [DATASHEET] 8160D–AVR–02/2013 345 31.11 Current Consumption of Peripheral Units Figure 31-52. Brownout Detector Current vs. VCC 20 18 16 14 -40 °C 25 °C 85 °C ICC (uA) 12 10 8 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-53. ADC Current vs. VCC (ADC CLK = 50 kHz) 375 350 25 °C 85 °C -40 °C 325 ICC (uA) 300 275 250 225 200 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 346 Figure 31-54. Aref Current vs. VCC 200 175 25 °C 85 °C -40 °C 150 ICC (uA) 125 100 75 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-55. Analog Comparator Current vs. VCC 70 85 °C 65 60 25 °C 55 50 -40 °C ICC (uA) 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 347 Figure 31-56. Programming Current vs. VCC 8 7 6 5 -40 °C 25 °C 85 °C ICC (mA) 4 3 2 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 31.12 Current Consumption in Reset and Reset Pulse width Figure 31-57. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up) 3 5.5 V ICC (mA) 2.5 5.0 V 4.5 V 2 4.0 V 3.6 V 3.3 V 1.5 2.7 V 1 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ATmega64A [DATASHEET] 8160D–AVR–02/2013 348 Figure 31-58. Reset Supply Current vs. VCC (1 - 16 MHz, Excluding Current through the Reset Pull-up) 16 5.5 V 5.0 V 12 4.5 V 4.0 V 8 3.6 V 3.3 V 4 2.7 V ICC (mA) 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 31-59. Minimum Reset Pulse Width vs. VCC 800 600 Pulsewidth (ns) 400 85 °C 25 °C 200 -40 °C 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 349 32. Typical Characteristics – TA = -40°C to 105°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 32.1 Active Supply Current ICC (mA) Figure 32-1. Active Supply Current vs. Frequency (0.1 - 1.0MHz) 2.3 2.0 1.7 1.4 1.1 5.5V 5.0V 4.5V 4.0V 3.6V 3.3V 3.0V 2.7V 0.8 0.5 0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ATmega64A [DATASHEET] 8160D–AVR–02/2013 350 Figure 32-2. Active Supply Current vs. Frequency (1 - 16MHz) ICC (mA) 20 5.5V 18 16 5.0V 14 4.5V 12 4.0V 10 3.6V 8 6 3.3V 2.7V 4 2 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 32-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 12 11 10 9 ICC (mA) 8 7 6 5 4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 VCC (V) -40°C 25°C 85°C 105°C 5.5 ATmega64A [DATASHEET] 8160D–AVR–02/2013 351 Figure 32-4. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 7.0 6.5 6.0 5.5 ICC (mA) 5.0 4.5 4.0 3.5 3.0 2.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 VCC (V) -40°C 25°C 85°C 105°C 5.5 Figure 32-5. Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz) 4.5 4.0 3.5 -40°C 25°C 85°C 105°C ICC (mA) 3.0 2.5 2.0 1.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 352 Figure 32-6. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 2.5 2.3 2.1 105°C 85°C 25°C -40°C ICC (mA) 1.9 1.7 1.5 1.3 1.1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) 32.2 Idle Supply Current Figure 32-7. Idle Supply Current vs. Frequency (0.1 - 1.0MHz) ICC (mA) 0.59 0.53 0.47 0.41 0.35 0.29 0.23 0.17 0.11 0.05 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Frequency (MHz) 5.5V 5.0V 4.5V 4.0V 3.6V 3.3V 2.7V 1 ATmega64A [DATASHEET] 8160D–AVR–02/2013 353 Figure 32-8. Idle Supply Current vs. Frequency (1 - 16MHz) ICC (mA) 8 5.5V 7 5.0V 6 4.5V 5 4.0V 4 3 3.6V 3.3V 2 2.7V 1 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 32-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 5.1 4.6 4.1 -40°C 25°C 85°C 105°C ICC (mA) 3.6 3.1 2.6 2.1 1.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 354 Figure 32-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 2.8 2.5 2.2 -40°C 25°C 85°C 105°C ICC (mA) 1.9 1.6 1.3 1.0 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 32-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz) 1.23 1.13 1.03 0.93 ICC (mA) 0.83 0.73 0.63 0.53 0.43 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 VCC (V) 105°C 85°C 25°C -40°C 5.5 ATmega64A [DATASHEET] 8160D–AVR–02/2013 355 Figure 32-12. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.74 0.68 0.62 0.56 ICC (mA) 0.5 0.44 0.38 0.32 0.26 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 VCC (V) 105°C 85°C 25°C -40°C 5.5 32.3 Power-down Supply Current Figure 32-13. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 6 5 105°C 4 ICC (µA) 3 85°C 2 -40°C 1 25°C 0 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 356 Figure 32-14. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) ICC (µA) 27 105°C 25 85°C 23 25°C 21 -40°C 19 17 15 13 11 9 7 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) 32.4 Pin Pull-up Figure 32-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 100 IOP (µA) 80 60 40 25°C 20 85°C 105°C 0 -40°C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 357 Figure 32-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 50 IOP (µA) 40 30 20 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 VOP (V) 25°C 85°C -40°C 105°C 2.7 Figure 32-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) -40°C 25°C 85°C 105°C ATmega64A [DATASHEET] 8160D–AVR–02/2013 358 Figure 32-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 32.5 Pin Driver Strength Figure 32-19. I/O Pin Output Voltage vs. Source Current, Port B (VCC = 5V) 5 4.9 4.8 VOH (V) 4.7 4.6 4.5 4.4 4.3 0 2 4 6 8 10 12 14 16 18 IOH (mA) -40°C 25°C 85°C 105°C 20 ATmega64A [DATASHEET] 8160D–AVR–02/2013 359 Figure 32-20. I/O Pin Output Voltage vs. Source Current, Port B (VCC = 3V) 3.1 2.9 2.7 VOH (V) 2.5 2.3 2.1 1.9 0 2 4 6 8 10 12 14 16 18 IOH (mA) Figure 32-21. I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) 0.7 0.6 0.5 VOL (V) 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 IOL (mA) -40°C 25°C 85°C 105°C 20 105°C 85°C 25°C -40°C 20 ATmega64A [DATASHEET] 8160D–AVR–02/2013 360 Figure 32-22. I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 3V) 1.0 0.9 0.8 0.7 0.6 VOL (V) 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 IOL (mA) 105°C 85°C 25°C -40°C 20 32.6 Pin Thresholds and Hysteresis Figure 32-23. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.1 25°C 105°C 2.9 85°C -40°C 2.7 2.5 Threshold (V) 2.3 2.1 1.9 1.7 1.5 1.3 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 361 Figure 32-24. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2.4 105°C 85°C 2.2 25°C -40°C 2 Threshold (V) 1.8 1.6 1.4 1.2 1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 32-25. I/O Pin Input Hysteresis vs. VCC 0.70 0.65 0.60 105°C 85°C 25°C -40°C Input Hysteresis (mV) 0.55 0.50 0.45 0.40 0.35 0.30 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 362 Figure 32-26. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 85°C 105°C -40°C 25°C Figure 32-27. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 105°C 85°C 25°C -40°C ATmega64A [DATASHEET] 8160D–AVR–02/2013 363 Figure 32-28. Reset Input Pin Hysteresis vs. VCC -40°C 25°C 85°C 105°C 32.7 BOD Thresholds and Analog Comparator Offset Figure 32-29. BOD Thresholds vs. Temperature (BOD Level is 4.3V) Threshold (V) 3.915 3.895 Rising Vcc 3.875 3.855 3.835 3.815 3.795 3.775 Falling Vcc 3.755 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) ATmega64A [DATASHEET] 8160D–AVR–02/2013 364 Figure 32-30. BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.735 2.715 Rising Vcc 2.695 Threshold (V) 2.675 2.655 2.635 2.615 Falling Vcc 2.595 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature ( °C) Figure 32-31. Bandgap Voltage vs. Temperature 1.201 1.196 Bandgap Voltage (V) 1.191 1.186 5.5V 1.181 1.176 1.171 5.0V 1.166 1.161 4.5V 2.7V -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) ATmega64A [DATASHEET] 8160D–AVR–02/2013 365 32.8 Internal Oscillator Speed Figure 32-32. Watchdog Oscillator Frequency vs. VCC 1220 1200 1180 1160 -40°C 25°C 85°C 105°C FRC (kHz) 1140 1120 1100 1080 1060 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 32-33. Watchdog Oscillator Frequency vs. Temperature 1220 1200 1180 5.5V FRC (kHz) 1160 1140 5.0V 1120 4.5V 1100 4.0V 3.6V 1080 3.3 V 2.7 V 1060 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) ATmega64A [DATASHEET] 8160D–AVR–02/2013 366 Figure 32-34. Calibrated 1MHz RC Oscillator Frequency vs. Temperature Figure 32-35. Calibrated 1MHz RC Oscillator Frequency vs. VCC ATmega64A [DATASHEET] 8160D–AVR–02/2013 367 Figure 32-36. Calibrated 2MHz RC Oscillator Frequency vs. Temperature Figure 32-37. Calibrated 2MHz RC Oscillator Frequency vs. VCC ATmega64A [DATASHEET] 8160D–AVR–02/2013 368 Figure 32-38. Calibrated 4MHz RC Oscillator Frequency vs. Temperature Figure 32-39. Calibrated 4MHz RC Oscillator Frequency vs. VCC ATmega64A [DATASHEET] 8160D–AVR–02/2013 369 Figure 32-40. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8.4 8.2 8.0 FRC (MHz) 7.8 5.5 V 7.6 5.0 V 7.4 4.5 V 4.0 V 7.2 3.6 V 7.0 3.3 V 6.8 3.0 V 6.6 2.7 V -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 32-41. Calibrated 8 MHz RC Oscillator Frequency vs. VCC 8.5 8.2 7.9 7.6 -40°C 25°C 85°C 105°C FRC (MHz) 7.3 7.0 6.7 6.4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ATmega64A [DATASHEET] 8160D–AVR–02/2013 370 Figure 32-42. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value 32.9 Current Consumption of Peripheral Units Figure 32-43. Brownout Detector Current vs. VCC ATmega64A [DATASHEET] 8160D–AVR–02/2013 371 Figure 32-44. ADC Current vs. VCC (AREF = AVCC) 105°C 85°C 25°C -40°C Figure 32-45. AREF External Reference Current vs. VCC 105°C 85°C 25°C -40°C ATmega64A [DATASHEET] 8160D–AVR–02/2013 372 Figure 32-46. Watchdog Timer Current vs. VCC 105°C 85°C 25°C -40°C Figure 32-47. Analog Comparator Current vs. VCC 85°C 105°C 25°C -40°C ATmega64A [DATASHEET] 8160D–AVR–02/2013 373 Figure 32-48. Programming Current vs. VCC -40°C 25°C 85°C 105°C 32.10 Current Consumption in Reset and Reset Pulsewidth Figure 32-49. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) ATmega64A [DATASHEET] 8160D–AVR–02/2013 374 Figure 32-50. Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up) 2.7V 3.3V 5.5V 5.0V 4.5V 4.0V 3.6V Figure 32-51. Minimum Reset Pulse Width vs. VCC ATmega64A [DATASHEET] 8160D–AVR–02/2013 375 33. Register Summary Address (0xFF) : (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) Name Reserved Reserved Reserved UCSR1C UDR1 UCSR1A UCSR1B UBRR1L UBRR1H Reserved Reserved UCSR0C Reserved Reserved Reserved Reserved UBRR0H Reserved ADCSRB Reserved TCCR3C TCCR3A TCCR3B TCNT3H TCNT3L OCR3AH OCR3AL OCR3BH OCR3BL OCR3CH OCR3CL ICR3H ICR3L Reserved Reserved ETIMSK ETIFR Reserved TCCR1C OCR1CH OCR1CL Reserved Reserved Reserved TWCR TWDR TWAR TWSR TWBR OSCCAL Reserved XMCRA XMCRB Reserved EICRA Reserved SPMCSR Reserved Reserved PORTG DDRG PING PORTF DDRF Reserved SREG Bit 7 – – – – RXC1 RXCIE1 – – – – – – – – – – – – FOC3A COM3A1 ICNC3 – – – – – FOC1A – – – TWINT TWA6 TWS7 – – XMBK – ISC31 – SPMIE – – – – – PORTF7 DDF7 – I Bit 6 – – – UMSEL1 TXC1 TXCIE1 – – – UMSEL0 – – – – – – – – FOC3B COM3A0 ICES3 – – – – – FOC1B – – – TWEA TWA5 TWS6 – SRL2 – – ISC30 – RWWSB – – – – – PORTF6 DDF6 – T Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 – – – – – – – – – – – – – – – UPM11 UPM10 USBS1 UCSZ11 UCSZ10 USART1 I/O Data Register UDRE1 FE1 DOR1 UPE1 U2X1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 USART1 Baud Rate Register Low – – USART1 Baud Rate Register High – – – – – – – – – – UPM01 UPM00 USBS0 UCSZ01 UCSZ00 – – – – – – – – – – – – – – – – – – – – – – USART0 Baud Rate Register High – – – – – – – – ADTS2 ADTS1 – – – – – FOC3C – – – – COM3B1 COM3B0 COM3C1 COM3C0 WGM31 – WGM33 WGM32 CS32 CS31 Timer/Counter3 – Counter Register High Byte Timer/Counter3 – Counter Register Low Byte Timer/Counter3 – Output Compare Register A High Byte Timer/Counter3 – Output Compare Register A Low Byte Timer/Counter3 – Output Compare Register B High Byte Timer/Counter3 – Output Compare Register B Low Byte Timer/Counter3 – Output Compare Register C High Byte Timer/Counter3 – Output Compare Register C Low Byte Timer/Counter3 – Input Capture Register High Byte Timer/Counter3 – Input Capture Register Low Byte – – – – – – – – – – TICIE3 OCIE3A OCIE3B TOIE3 OCIE3C ICF3 OCF3A OCF3B TOV3 OCF3C – – – – – FOC1C – – – – Timer/Counter1 – Output Compare Register C High Byte Timer/Counter1 – Output Compare Register C Low Byte – – – – – – – – – – – – – – – TWSTA TWSTO TWWC TWEN – Two-wire Serial Interface Data Register TWA4 TWA3 TWA2 TWA1 TWA0 TWS5 TWS4 TWS3 – TWPS1 Two-wire Serial Interface Bit Rate Register Oscillator Calibration Register – – – – – SRL1 SRL0 SRW01 SRW00 SRW11 – – – XMM2 XMM1 – – – – – ISC21 ISC20 ISC11 ISC10 ISC01 – – – – – – RWWSRE BLBSET PGWRT PGERS – – – – – – – – – – – PORTG4 PORTG3 PORTG2 PORTG1 – DDG4 DDG3 DDG2 DDG1 – PING4 PING3 PING2 PING1 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 DDF5 DDF4 DDF3 DDF2 DDF1 – – – – – H S V N Z Bit 0 – – – UCPOL1 MPCM1 TXB81 – – UCPOL0 – – – – – ADTS0 – – WGM30 CS30 – – OCIE1C OCF1C – – – – – TWIE TWGCE TWPS0 – XMM0 – ISC00 – SPMEN – – PORTG0 DDG0 PING0 PORTF0 DDF0 – C Page 187 185 185 186 189 189 187 189 233 130 126 128 130 130 131 131 131 131 131 131 132 132 133 133 129 131 131 212 214 214 213 212 41 27 28 62 272 88 88 88 87 88 9 ATmega64A [DATASHEET] 8160D–AVR–02/2013 376 33. Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) SPH SPL XDIV Reserved EICRB EIMSK EIFR TIMSK TIFR MCUCR MCUCSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 OCDR WDTCR SFIOR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR0 UCSR0A UCSR0B UBRR0L ACSR ADMUX ADCSRA ADCH ADCL PORTE DDRE PINE PINF SP15 SP7 XDIVEN – ISC71 INT7 INTF7 OCIE2 OCF2 SRE JTD FOC0 – COM1A1 ICNC1 FOC2 IDRD/ OCDR7 – TSM – – PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC0 RXCIE0 ACD REFS1 ADEN PORTE7 DDE7 PINE7 PINF7 SP14 SP6 XDIV6 – ISC70 INT6 INTF6 TOIE2 TOV2 SRW10 – WGM00 – COM1A0 ICES1 WGM20 OCDR6 – – – – PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC0 TXCIE0 ACBG REFS0 ADSC PORTE6 DDE6 PINE6 PINF6 SP13 SP12 SP11 SP10 SP5 SP4 SP3 SP2 XDIV5 XDIV4 XDIV3 XDIV2 – – – – ISC61 ISC60 ISC51 ISC50 INT5 INT4 INT3 INT2 INTF5 INTF4 INTF3 INTF TICIE1 OCIE1A OCIE1B TOIE1 ICF1 OCF1A OCF1B TOV1 SE SM1 SM0 SM2 – JTRF WDRF BORF COM01 COM00 WGM01 CS02 Timer/Counter0 (8 Bit) Timer/Counter0 Output Compare Register – – AS0 TCN0UB COM1B1 COM1B0 COM1C1 COM1C0 – WGM13 WGM12 CS12 Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte Timer/Counter1 – Output Compare Register A High Byte Timer/Counter1 – Output Compare Register A Low Byte Timer/Counter1 – Output Compare Register B High Byte Timer/Counter1 – Output Compare Register B Low Byte Timer/Counter1 – Input Capture Register High Byte Timer/Counter1 – Input Capture Register Low Byte COM21 COM20 WGM21 CS22 Timer/Counter2 (8 Bit) Timer/Counter2 Output Compare Register SP9 SP1 XDIV1 – ISC41 INT1 INTF1 OCIE0 OCF0 IVSEL EXTRF CS01 OCR0UB WGM11 CS11 CS21 SP8 SP0 XDIV0 – ISC40 INT0 INTF0 TOIE0 TOV0 IVCE PORF CS00 TCR0UB WGM10 CS10 CS20 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 – – – – PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 – DORD UDRE0 UDRIE0 ACO ADLAR ADATE PORTE5 DDE5 PINE5 PINF5 WDCE WDE WDP2 WDP1 WDP0 – ACME PUD PSR0 PSR321 – – EEPROM Address Register High Byte EEPROM Address Register Low Byte EEPROM Data Register – EERIE EEMWE EEWE EERE PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 DDA4 DDA3 DDA2 DDA1 DDA0 PINA4 PINA3 PINA2 PINA1 PINA0 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 DDB4 DDB3 DDB2 DDB1 DDB0 PINB4 PINB3 PINB2 PINB1 PINB0 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 DDC4 DDC3 DDC2 DDC1 DDC0 PINC4 PINC3 PINC2 PINC1 PINC0 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 DDD4 DDD3 DDD2 DDD1 DDD0 PIND4 PIND3 PIND2 PIND1 PIND0 SPI Data Register – – – – SPI2X MSTR CPOL CPHA SPR1 SPR0 USART0 I/O Data Register FE0 DOR0 UPE0 U2X0 MPCM0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 USART0 Baud Rate Register Low ACI ACIE ACIC ACIS1 ACIS0 MUX4 MUX3 MUX2 MUX1 MUX0 ADIF ADIE ADPS2 ADPS1 ADPS0 ADC Data Register High Byte ADC Data Register Low byte PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 DDE4 DDE3 DDE2 DDE1 DDE0 PINE4 PINE3 PINE2 PINE1 PINE0 PINF4 PINF3 PINF2 PINF1 PINF0 11 11 41 63 63 64 104, 132, 152 105, 133, 152 27, 47, 61 54, 243 102 103 104 104 126 128 130 130 131 131 131 131 132 132 150 151 152 240 54 88, 105, 138, 216 29 29 30 30 86 86 86 86 86 86 86 86 87 87 87 87 162 162 161 185 185 186 189 216 230 232 233 233 87 87 87 88 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. ATmega64A [DATASHEET] 8160D–AVR–02/2013 377 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. ATmega64A [DATASHEET] 8160D–AVR–02/2013 378 34. Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. SBIW Rdl,K Subtract Immediate from Word AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One’s Complement NEG Rd Two’s Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register MUL Rd, Rr Multiply Unsigned MULS Rd, Rr Multiply Signed MULSU Rd, Rr Multiply Signed with Unsigned FMUL Rd, Rr Fractional Multiply Unsigned FMULS Rd, Rr Fractional Multiply Signed FMULSU Rd, Rr Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP Indirect Jump to (Z) JMP k Direct Jump RCALL k Relative Subroutine Call ICALL Indirect Call to (Z) CALL k Direct Subroutine Call RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled Operation Rd  Rd + Rr Rd  Rd + Rr + C Rdh:Rdl  Rdh:Rdl + K Rd  Rd - Rr Rd  Rd - K Rd  Rd - Rr - C Rd  Rd - K - C Rdh:Rdl  Rdh:Rdl - K Rd Rd  Rr Rd  Rd K Rd  Rd v Rr Rd Rd v K Rd  Rd  Rr Rd  0xFF  Rd Rd  0x00  Rd Rd  Rd v K Rd  Rd  (0xFF - K) Rd  Rd + 1 Rd  Rd  1 Rd  Rd  Rd Rd  Rd  Rd Rd  0xFF R1:R0  Rd x Rr R1:R0  Rd x Rr R1:R0  Rd x Rr R1:R0 ¨ (Rd x Rr) << 1 R1:R0 ¨ (Rd x Rr) << 1 R1:R0 ¨ (Rd x Rr) << 1 PC PC + k + 1 PC  Z PC k PC  PC + k + 1 PC  Z PC  k PC  STACK PC  STACK if (Rd = Rr) PC PC + 2 or 3 Rd  Rr Rd  Rr  C Rd  K if (Rr(b)=0) PC  PC + 2 or 3 if (Rr(b)=1) PC  PC + 2 or 3 if (P(b)=0) PC  PC + 2 or 3 if (P(b)=1) PC  PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC  PC + k + 1 if (Z = 0) then PC  PC + k + 1 if (C = 1) then PC  PC + k + 1 if (C = 0) then PC  PC + k + 1 if (C = 0) then PC  PC + k + 1 if (C = 1) then PC  PC + k + 1 if (N = 1) then PC  PC + k + 1 if (N = 0) then PC  PC + k + 1 if (N  V= 0) then PC  PC + k + 1 if (N  V= 1) then PC  PC + k + 1 if (H = 1) then PC  PC + k + 1 if (H = 0) then PC  PC + k + 1 if (T = 1) then PC  PC + k + 1 if (T = 0) then PC  PC + k + 1 if (V = 1) then PC  PC + k + 1 if (V = 0) then PC  PC + k + 1 if ( I = 1) then PC  PC + k + 1 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ATmega64A [DATASHEET] 8160D–AVR–02/2013 379 34. Instruction Set Summary (Continued) BRID k DATA TRANSFER INSTRUCTIONS MOV Rd, Rr MOVW Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LPM LPM Rd, Z LPM Rd, Z+ SPM IN Rd, P OUT P, Rr PUSH Rr POP Rd BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH MCU CONTROL INSTRUCTIONS Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG if ( I = 0) then PC  PC + k + 1 None 1/2 Rd  Rr Rd+1:Rd  Rr+1:Rr Rd  K Rd  (X) Rd  (X), X  X + 1 X  X - 1, Rd  (X) Rd  (Y) Rd  (Y), Y  Y + 1 Y  Y - 1, Rd  (Y) Rd  (Y + q) Rd  (Z) Rd  (Z), Z  Z+1 Z  Z - 1, Rd  (Z) Rd  (Z + q) Rd  (k) (X) Rr (X) Rr, X  X + 1 X  X - 1, (X)  Rr (Y)  Rr (Y)  Rr, Y  Y + 1 Y  Y - 1, (Y)  Rr (Y + q)  Rr (Z)  Rr (Z)  Rr, Z  Z + 1 Z  Z - 1, (Z)  Rr (Z + q)  Rr (k)  Rr R0  (Z) Rd  (Z) Rd  (Z), Z  Z+1 (Z)  R1:R0 Rd  P P  Rr STACK  Rr Rd  STACK None 1 None 1 None 1 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 3 None 3 None 3 None - None 1 None 1 None 2 None 2 I/O(P,b)  1 None 2 I/O(P,b)  0 None 2 Rd(n+1)  Rd(n), Rd(0)  0 Z,C,N,V 1 Rd(n)  Rd(n+1), Rd(7)  0 Z,C,N,V 1 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 Rd(n)  Rd(n+1), n=0:6 Z,C,N,V 1 Rd(3:0)Rd(7:4),Rd(7:4)Rd(3:0) None 1 SREG(s)  1 SREG(s) 1 SREG(s)  0 SREG(s) 1 T  Rr(b) T 1 Rd(b)  T None 1 C1 C 1 C0 C 1 N1 N 1 N0 N 1 Z1 Z 1 Z0 Z 1 I1 I 1 I 0 I 1 S1 S 1 S0 S 1 V1 V 1 V0 V 1 T1 T 1 T0 T 1 H1 H 1 H0 H 1 ATmega64A [DATASHEET] 8160D–AVR–02/2013 380 34. Instruction Set Summary (Continued) NOP SLEEP WDR BREAK No Operation Sleep Watchdog Reset Break None 1 (see specific descr. for Sleep function) None 1 (see specific descr. for WDR/timer) None 1 For On-chip Debug Only None N/A ATmega64A [DATASHEET] 8160D–AVR–02/2013 381 35. Ordering Information Speed (MHz) Power Supply 16 2.7 - 5.5 Ordering Code(2) ATmega64A-AU ATmega64A-AUR(3) ATmega64A-MU ATmega64A-MUR(3) ATmega64A-AN ATmega64A-ANR(3) ATmega64A-MN ATmega64A-MNR(3) Package(1) 64A 64A 64M1 64M1 64A 64A 64M1 64M1 Operation Range Industrial (-40C to 85C) Extended (-40C to 105C)(4) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Tape and Reel 4. See characterization specifications at 105C 64A 64M1 Package Type 64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATmega64A [DATASHEET] 8160D–AVR–02/2013 382 36. Packaging Information 36.1 64A PIN 1 e PIN 1 IDENTIFIER B E1 E D1 D C 0°~7° A1 A2 L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. A COMMON DIMENSIONS (Unit of measure = mm) SYMBOL MIN A – A1 0.05 A2 0.95 D 15.75 D1 13.90 E 15.75 E1 13.90 B 0.30 C 0.09 L 0.45 e NOM MAX – 1.20 – 0.15 1.00 1.05 16.00 16.25 14.00 14.10 16.00 16.25 14.00 14.10 – 0.45 – 0.20 – 0.75 0.80 TYP NOTE Note 2 Note 2 TITLE 2325 Orchard Parkway San Jose, CA 95131 64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness, 0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 2010-10-20 DRAWING NO. REV. 64A C ATmega64A [DATASHEET] 8160D–AVR–02/2013 383 36.2 64M1 D Marked Pin# 1 ID E TOP VIEW K L D2 Pin #1 Corner C SEATING PLANE A1 A 0.08 C SIDE VIEW 1 Option A Pin #1 2 Triangle 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) K b e BOTTOM VIEW Option C Pin #1 Notch (0.20 R) Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. SYMBOL A A1 b D D2 E E2 e L K MIN 0.80 – 0.18 8.90 5.20 8.90 5.20 0.35 1.25 TITLE 2325 Orchard Parkway 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, R San Jose, CA 95131 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) NOM MAX 0.90 1.00 0.02 0.05 0.25 0.30 9.00 9.10 5.40 5.60 9.00 9.10 5.40 5.60 0.50 BSC 0.40 0.45 1.40 1.55 NOTE 2010-10-19 DRAWING NO. REV. 64M1 H 37. Errata ATmega64A [DATASHEET] 8160D–AVR–02/2013 384 The revision letter in this section refers to the revision of the ATmega64A device. 37.1 ATmega64A, rev. D • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • Stabilizing time needed when changing XDIV Register • Stabilizing time needed when changing OSCCAL Register • IDCODE masks data from TDI input • Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix / Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 3. Stabilizing time needed when changing XDIV Register After increasing the source clock frequency more than 2% with settings in the XDIV register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The NOP instruction will always be executed correctly also right after a frequency change. Thus, the next 8 instructions after the change should be NOP instructions. To ensure this, follow this procedure: 1.Clear the I bit in the SREG Register. 2.Set the new pre-scaling factor in XDIV register. 3.Execute 8 NOP instructions 4.Set the I bit in SREG This will ensure that all subsequent instructions will execute correctly. Assembly Code Example: CLI ; clear global interrupt enable OUT XDIV, temp ; set new prescale value NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation SEI ; clear global interrupt enable ATmega64A [DATASHEET] 8160D–AVR–02/2013 385 4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata. 5. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround – If ATmega64A is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega64A by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega64A while reading the Device ID Registers of preceding devices of the boundary scan chain. – If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega64A must be the first device in the chain. 6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. ATmega64A [DATASHEET] 8160D–AVR–02/2013 386 38. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section refers to the document revision. 38.1 8160D – 02/2013 1. Applied the new template that includes new logo and new last page. 2. Added “Capacitive touch sensing” on page 7. 3. Note is added “Performing Page Erase by SPM” on page 267. 4. Note 6 and Note 7 below Table 29-4, “Two-wire Serial Bus Requirements,” on page 308 have been removed. 5. Formulas in Table 29-4, “Two-wire Serial Bus Requirements,” on page 308 have been updated. 6. Added “Electrical Characteristics – TA = -40°C to 105°C” on page 318. 7. Added “Typical Characteristics – TA = -40°C to 105°C” on page 350. 8. Updated “Ordering Information” on page 382 and added “Ordering Information” for 105C devices. 38.2 8160C – 07/09 1. Updated “Errata” on page 384. 38.3 8160B – 03/09 1. Updated “Typical Characteristics – TA = -40°C to 85°C” view. 2. Updated Figure 31-36 and Figure 31-37 on page 338 (BOD Thresholds Characteristics). 3. Updated the last page. 38.4 8160A – 08/08 1. Initial revision (Based on the ATmega64/L datasheet 2490N-AVR-06/08). 2. Changes done compared to ATmega64/L datasheet 2490N-AVR-06/08: – All Electrical Characteristics are moved to “Electrical Characteristics – TA = -40°C to 85°C” on page 304. – Register descriptions are moved to sub section at the end of each chapter. – Updated “DC Characteristics” on page 304 with new VOL Max (0.9V and 0.6V) and typical values for ICC. – Added “Speed Grades” on page 306. – Added “System and Reset Characteristics” on page 307. – New graphics in “Typical Characteristics – TA = -40°C to 85°C” on page 320. – New “Ordering Information” on page 382. ATmega64A [DATASHEET] 8160D–AVR–02/2013 387 Table of Contents Features ..................................................................................................... 1 1 Pin Configuration ..................................................................................... 2 2 Overview ................................................................................................... 3 2.1 Block Diagram ...................................................................................................3 2.2 ATmega103 and ATmega64A Compatibility .....................................................4 2.3 Pin Descriptions .................................................................................................5 3 Resources ................................................................................................. 7 4 Data Retention .......................................................................................... 7 5 About Code Examples ............................................................................. 7 6 Capacitive touch sensing ........................................................................ 7 7 AVR CPU Core .......................................................................................... 8 7.1 Overview ............................................................................................................8 7.2 ALU – Arithmetic Logic Unit ...............................................................................9 7.3 Status Register ..................................................................................................9 7.4 Stack Pointer ...................................................................................................11 7.5 Instruction Execution Timing ...........................................................................12 7.6 Reset and Interrupt Handling ...........................................................................13 7.7 Interrupt Response Time .................................................................................14 8 AVR Memories ........................................................................................ 15 8.1 In-System Reprogrammable Flash Program Memory .....................................15 8.2 SRAM Data Memory ........................................................................................16 8.3 EEPROM Data Memory ..................................................................................18 8.4 I/O Memory ......................................................................................................19 8.5 External Memory Interface ..............................................................................19 8.6 Register Description ........................................................................................27 9 System Clock and Clock Options ......................................................... 34 9.1 Clock Systems and their Distribution ...............................................................34 9.2 Clock Sources .................................................................................................35 9.3 Default Clock Source .......................................................................................35 9.4 Crystal Oscillator .............................................................................................35 9.5 Low-frequency Crystal Oscillator .....................................................................37 9.6 External RC Oscillator .....................................................................................37 ATmega64A [DATASHEET] i 8160D–AVR–02/2013 9.7 Calibrated Internal RC Oscillator .....................................................................39 9.8 External Clock .................................................................................................40 9.9 Timer/Counter Oscillator ..................................................................................40 9.10 Register Description ........................................................................................41 10 Power Management and Sleep Modes ................................................. 43 10.1 Idle Mode .........................................................................................................43 10.2 ADC Noise Reduction Mode ............................................................................43 10.3 Power-down Mode ...........................................................................................43 10.4 Power-save Mode ............................................................................................44 10.5 Standby Mode .................................................................................................44 10.6 Extended Standby Mode .................................................................................45 10.7 Minimizing Power Consumption ......................................................................45 10.8 Register Description ........................................................................................47 11 System Control and Reset .................................................................... 48 11.1 Internal Voltage Reference ..............................................................................51 11.2 Watchdog Timer ..............................................................................................52 11.3 Timed Sequences for Changing the Configuration of the Watchdog Timer ....52 11.4 Register Description ........................................................................................54 12 Interrupts ................................................................................................ 57 12.1 Overview ..........................................................................................................57 12.2 Interrupt Vectors in ATmega64A .....................................................................57 12.3 Register Description ........................................................................................61 13 External Interrupts ................................................................................. 62 13.1 Register Description ........................................................................................62 14 I/O Ports .................................................................................................. 65 14.1 Overview ..........................................................................................................65 14.2 Ports as General Digital I/O .............................................................................66 14.3 Alternate Port Functions ..................................................................................69 14.4 Register Description ........................................................................................86 15 8-bit Timer/Counter0 with PWM and Asynchronous Operation ........ 89 15.1 Features ..........................................................................................................89 15.2 Overview ..........................................................................................................89 15.3 Timer/Counter Clock Sources .........................................................................90 15.4 Counter Unit ....................................................................................................90 15.5 Output Compare Unit .......................................................................................91 ATmega64A [DATASHEET] ii 8160D–AVR–02/2013 15.6 Compare Match Output Unit ............................................................................92 15.7 Modes of Operation .........................................................................................93 15.8 Timer/Counter Timing Diagrams .....................................................................98 15.9 Asynchronous Operation of the Timer/Counter ...............................................99 15.10 Timer/Counter Prescaler ...............................................................................101 15.11 Register Description ......................................................................................102 16 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) ........... 106 16.1 Features ........................................................................................................106 16.2 Overview ........................................................................................................106 16.3 Accessing 16-bit Registers ............................................................................109 16.4 Timer/Counter Clock Sources .......................................................................111 16.5 Counter Unit ..................................................................................................111 16.6 Input Capture Unit .........................................................................................112 16.7 Output Compare Units ...................................................................................114 16.8 Compare Match Output Unit ..........................................................................116 16.9 Modes of Operation .......................................................................................117 16.10 Timer/Counter Timing Diagrams ...................................................................124 16.11 16-bit Timer/Counter Register Description ....................................................126 17 Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers .. 136 17.1 Register Description ......................................................................................138 18 8-bit Timer/Counter2 with PWM .......................................................... 139 18.1 Features ........................................................................................................139 18.2 Overview ........................................................................................................139 18.3 Timer/Counter Clock Sources .......................................................................140 18.4 Counter Unit ..................................................................................................140 18.5 Output Compare Unit .....................................................................................141 18.6 Compare Match Output Unit ..........................................................................143 18.7 Modes of Operation .......................................................................................144 18.8 Timer/Counter Timing Diagrams ...................................................................148 18.9 Register Description ......................................................................................150 19 Output Compare Modulator (OCM1C2) .............................................. 153 19.1 Overview ........................................................................................................153 19.2 Description .....................................................................................................153 20 SPI – Serial Peripheral Interface ......................................................... 155 20.1 Features ........................................................................................................155 ATmega64A [DATASHEET] iii 8160D–AVR–02/2013 20.2 Overview ........................................................................................................155 20.3 SS Pin Functionality ......................................................................................159 20.4 Data Modes ...................................................................................................159 20.5 Register Description ......................................................................................161 21 USART ................................................................................................... 163 21.1 Features ........................................................................................................163 21.2 Overview ........................................................................................................163 21.3 Clock Generation ...........................................................................................165 21.4 Frame Formats ..............................................................................................167 21.5 USART Initialization .......................................................................................168 21.6 Data Transmission – The USART Transmitter ..............................................169 21.7 Data Reception – The USART Receiver .......................................................172 21.8 Asynchronous Data Reception ......................................................................176 21.9 Multi-processor Communication Mode ..........................................................179 21.10 Examples of Baud Rate Setting .....................................................................180 21.11 Register Description ......................................................................................185 22 TWI – Two-wire Serial Interface .......................................................... 190 22.1 Features ........................................................................................................190 22.2 Overview ........................................................................................................190 22.3 Two-wire Serial Interface Bus Definition ........................................................192 22.4 Data Transfer and Frame Format ..................................................................193 22.5 Multi-master Bus Systems, Arbitration and Synchronization .........................195 22.6 Using the TWI ................................................................................................197 22.7 Transmission Modes .....................................................................................199 22.8 Multi-master Systems and Arbitration ............................................................211 22.9 TWI Register Description ...............................................................................212 23 Analog Comparator .............................................................................. 215 23.1 Analog Comparator Multiplexed Input ...........................................................215 23.2 Register Description ......................................................................................216 24 Analog to Digital Converter ................................................................. 218 24.1 Features ........................................................................................................218 24.2 Overview ........................................................................................................218 24.3 Operation .......................................................................................................219 24.4 Starting a Conversion ....................................................................................220 24.5 Prescaling and Conversion Timing ................................................................221 ATmega64A [DATASHEET] iv 8160D–AVR–02/2013 24.6 Changing Channel or Reference Selection ...................................................224 24.7 ADC Noise Canceler .....................................................................................225 24.8 ADC Conversion Result .................................................................................228 24.9 Register Description ......................................................................................230 25 JTAG Interface and On-chip Debug System ...................................... 235 25.1 Features ........................................................................................................235 25.2 Overview ........................................................................................................235 25.3 TAP – Test Access Port ................................................................................235 25.4 TAP Controller ...............................................................................................237 25.5 Using the Boundary -scan Chain ...................................................................238 25.6 Using the On-chip Debug system ..................................................................238 25.7 On-chip Debug Specific JTAG Instructions ...................................................239 25.8 Using the JTAG Programming Capabilities ...................................................239 25.9 On-chip Debug Related Register in I/O Memory ...........................................240 25.10 Bibliography ...................................................................................................240 26 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 241 26.1 Features ........................................................................................................241 26.2 Overview ........................................................................................................241 26.3 Data Registers ...............................................................................................241 26.4 Boundary-scan Specific JTAG Instructions ...................................................243 26.5 Boundary-scan Chain ....................................................................................244 26.6 ATmega64A Boundary-scan Order ...............................................................253 26.7 Boundary-scan Description Language Files ..................................................260 26.8 Boundary-scan Related Register in I/O Memory ...........................................260 27 Boot Loader Support – Read-While-Write Self-programming ......... 261 27.1 Features ........................................................................................................261 27.2 Overview ........................................................................................................261 27.3 Application and Boot Loader Flash Sections .................................................261 27.4 Read-While-Write and No Read-While-Write Flash Sections ........................261 27.5 Boot Loader Lock Bits ...................................................................................264 27.6 Entering the Boot Loader Program ................................................................265 27.7 Addressing the Flash During Self-programming ............................................266 27.8 Self-programming the Flash ..........................................................................266 27.9 Register Description ......................................................................................272 28 Memory Programming ......................................................................... 274 ATmega64A [DATASHEET] v 8160D–AVR–02/2013 28.1 Program and Data Memory Lock Bits ............................................................274 28.2 Fuse Bits ........................................................................................................275 28.3 Signature Bytes .............................................................................................276 28.4 Calibration Byte .............................................................................................277 28.5 Parallel Programming Parameters, Pin Mapping, and Commands ...............277 28.6 Parallel Programming ....................................................................................279 28.7 Serial Downloading ........................................................................................287 28.8 SPI Serial Programming Pin Mapping ...........................................................288 28.9 Programming Via the JTAG Interface ............................................................292 29 Electrical Characteristics – TA = -40°C to 85°C ................................. 304 29.1 Absolute Maximum Ratings* .........................................................................304 29.2 DC Characteristics .........................................................................................304 29.3 Speed Grades ...............................................................................................306 29.4 Clock Characteristics .....................................................................................306 29.5 System and Reset Characteristics ................................................................307 29.6 Two-wire Serial Interface Characteristics ......................................................308 29.7 SPI Timing Characteristics ............................................................................309 29.8 ADC Characteristics ......................................................................................311 29.9 External Data Memory Timing .......................................................................313 30 Electrical Characteristics – TA = -40°C to 105°C ............................... 318 30.1 Absolute Maximum Ratings* .........................................................................318 30.2 DC Characteristics .........................................................................................318 31 Typical Characteristics – TA = -40°C to 85°C .................................... 320 31.1 Active Supply Current ....................................................................................320 31.2 Idle Supply Current ........................................................................................324 31.3 Power-Down Supply Current .........................................................................327 31.4 Power-Save Supply Current ..........................................................................328 31.5 Standby Supply Current ................................................................................329 31.6 Pin Pull-up .....................................................................................................330 31.7 Pin Driver Strength ........................................................................................333 31.8 Pin Thresholds and Hysteresis ......................................................................335 31.9 BOD Thresholds and Analog Comparator Offset ..........................................338 31.10 Internal Oscillator Speed ...............................................................................339 31.11 Current Consumption of Peripheral Units ......................................................346 31.12 Current Consumption in Reset and Reset Pulse width .................................348 ATmega64A [DATASHEET] vi 8160D–AVR–02/2013 32 Typical Characteristics – TA = -40°C to 105°C .................................. 350 32.1 Active Supply Current ....................................................................................350 32.2 Idle Supply Current ........................................................................................353 32.3 Power-down Supply Current ..........................................................................356 32.4 Pin Pull-up .....................................................................................................357 32.5 Pin Driver Strength ........................................................................................359 32.6 Pin Thresholds and Hysteresis ......................................................................361 32.7 BOD Thresholds and Analog Comparator Offset ..........................................364 32.8 Internal Oscillator Speed ...............................................................................366 32.9 Current Consumption of Peripheral Units ......................................................371 32.10 Current Consumption in Reset and Reset Pulsewidth ..................................374 33 Register Summary ............................................................................... 376 34 Instruction Set Summary ..................................................................... 379 35 Ordering Information ........................................................................... 382 36 Packaging Information ........................................................................ 383 36.1 64A ................................................................................................................383 36.2 64M1 ..............................................................................................................384 37 Errata ..................................................................................................... 384 37.1 ATmega64A, rev. D .......................................................................................385 38 Datasheet Revision History ................................................................. 387 38.1 8160D – 02/2013 ...........................................................................................387 38.2 8160C – 07/09 ...............................................................................................387 38.3 8160B – 03/09 ...............................................................................................387 38.4 8160A – 08/08 ...............................................................................................387 Table of Contents....................................................................................... i ATmega64A [DATASHEET] vii 8160D–AVR–02/2013 Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Roa Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg 1-6-4 Osaki, Shinagawa-ku Tokyo 141-0032 JAPAN Tel: (+81) (3) 6417-0300 Fax: (+81) (3) 6417-0370 © 2013 Atmel Corporation. All rights reserved. / Rev.: 8160D–AVR–02/2013 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

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