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DDR4_On-board_Design_Guide

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标签: DDR4_On-board_Design_Guide

DDR4_On-board_Design_Guide.pdf

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DDR4 Onboard Design Guide Samsung Electronics August 2015 Contents 1 Introduction 2 Device Information DDR4 x16 Memory 3 PCB Design Guidelines for SIPIEMIESD Cross Section Recommendation Component Placement Examples PCB Design Guidelines for SI PCB Design Guidelines for PI PCB Design Guidelines for EMIESD DDR4 Feature DDR4 x16 PKG Miscellaneous 4 Routing details Feasibility Study Performance Prediction Channel Simulation DQ Performance Prediction......

DDR4 On-board Design Guide Samsung Electronics August, 2015 Contents 1. Introduction 2. Device Information: DDR4 x16 Memory 3. PCB Design Guidelines for SI/PI/EMI/ESD  Cross Section Recommendation  Component Placement Examples  PCB Design Guidelines for SI  PCB Design Guidelines for PI  PCB Design Guidelines for EMI/ESD  DDR4 Feature  DDR4 x16 PKG  Miscellaneous 4. Routing details & Feasibility Study  Performance Prediction (Channel Simulation) : DQ  Performance Prediction (Channel Simulation) : CA, Ctrl, CK  Criteria 1 Application Note 1. Introduction 1.1. Objectives  To provide consumer board design recommendations and guidelines for solder down applications with Samsung’s DDR4 x16 memory. 1.2. Coverage assumptions;  The design guides and feasibility studies in this document are based on the - Industrial standard memory controller (memory sub-system) - Board stack-up & Net topology - Samsung’s DDR4 x16 memory  Hence, this document is valid for reference use only.  It is highly recommended for each customer to conduct board level simulation prior to finalizing your design. 2 Application Note 2. Device Information: DDR4 x16 2.1. DDR4 Features Feature Component density Speed Vdd/Vddq (V) DDR4 4Gb ~16Gb 1.6 ~ 3.2 Gbps 1.2 (1.14~1.26) Internal Vref (need training) 2.5 Strobe Data I/O VPP Vref CMD, ADDR IO Page size (x4, 8, 16) Number of prefetch Number of banks Added functions Package type, balls Interface Core architecture Physical POD (34ohm) CTT Bi-directional, Diff 16 (4-bank group) 512B, 1KB, 2KB 8 bits Multi preamble 78 BGA (x4, x8) 96 BGA (x16) Yes 1 Fly-by & leveling CRC, Data Bus Inversion (DBI), Note 1. Controller must support the write leveling scheme for fly-by Command and Address net topology, which is used for all PC and Server applications. Refer to details in page8 3 Application Note 2. Device Information: DDR4 x16 2.2. DDR4 x16 PKG  PKG size: 7.5x13.3 (mm) PKG Ballout Side View Bottom View * Numbers are relevant to Samsung memory only * Dimensions in mm 4 Application Note
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