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An Innovative IC-Package Co-design Methodology for high pin-count FlipChip CSP_SH03

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  • 日期: 2013-11-01
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标签: innovativemethodologyforhigh

An  Innovative IC-Package Co-design Methodology for high pin-count FlipChip CSP_SH03

An Innovative IC-Package Co-design Methodology for high pin-count FlipChip CSP Steven Guo Senior Manager CDNLive 2013 Shanghai Sep 12,2013 Flip-Chip Package Types FCCSP or FCBGA FCBGA-OPL FCCSP or FCBGA FCCSP or FCBGA 2 © 2013 Cadence Design Systems, Inc. All rights reserved. Flip chip Package /FCCSP  Flip Chip on Leadframe (FCOL)  Flip Chip on Substrate (FCOS)  Thermal Compression Bonding (TCB)  Thermal Sonic Bonding (TSB) 3 © 2013 Cadence Design Systems, Inc. All rights reserved. Flipchip package Introduction 4 © 2013 Cadence Design Systems, Inc. All rights reserved. Redistribution Layer (RDL) • A Redistribution Layer (RDL) is an extra metal layer on a chip that makes the IO pads of an integrated circuit available in other locations. Aluminum Al RDL Cu RDL Cu/Ni/Au RDL 5 © 2013 Cadence Design Systems, Inc. All rights reserved. Background of new Codesign methodology Redistribution routing Time-consuming /low efficiency painful tasks for high pin count from I/O cell to bump fan out Not easy to find out the interconnection issue (chip floorplan, netlist, net mapping, ball out) current issues error-prone data transfer by using I/O cell pad /bump edtext /spreadsheet too many design iterations delay chip tapeout Engineering cost increasing Distributed Co-design -Instead of working concurrently, communications between different design domains can be achieved by data exchange -New data transfer interface and interchangeable easily 6 © 2013 Cadence Design Systems, Inc. All rights reserved. IC-PKG-PCB Codesign Solution from Cadence Encounter Virtuoso CDN SiP ACPDo-Design CDNOpStiiPon RDL Exchange I/O Pad  Bump Array I/O Pad to Package PRlaDcLemReonuttianngd Optimization RDPiLn RPhoyustiicnagl Design RI/DOLPRaodutingBump I/OanPdaMdodeliBngump IAntreragryaPtiolancweimthePnhtysical Floor- ArPraryaPmleatceerizmeednt palnandnOinpgttiomoilzsation anEdmObepdtidmedizPataiossnives Integration with Analog/RF Die Stacking design environment 3D Visualization 7 © 2013 Cadence Design Systems, Inc. All rights reserved. Allegro PCB Package Footprint Creation Schematic Symbol Creation I/O Pad to Package Pin Delays Package Pin Optimization IO area IO area IC-PKG-PCB Codesign Implementation BGA optimization in context of a PCB IBOBOupGmptAilmpacciCzreearmaetitaoeiotninotonaf naddniedbsuIiOzmetpothtboroubumagplhl absestitgenrmfloeonrt planning IO area Core size IO area Die size 8 © 2013 Cadence Design Systems, Inc. All rights reserved. Methodology for RDL Data Exchange Package domain fabric SiP Layout XL RDL Data (edi2sip) IC domain fabric Encounter /EDI edi rdl import vcadWriteRdlData Excel file Nets mapping file vcadRdlDataSetup csv file edi rdl update Control file RDL Data (sip2edi) Bump ioupdate file 9 © 2013 Cadence Design Systems, Inc. All rights reserved. vcadReadRdlData RDL Routing (SiP / EDI / Virtuoso) Smooth Co-design flow between IC (EDI) and Package (SiP Layout) Smooth Routing Push/Shove/Sliding Capability of SiP Layout Convenient functions of add/delete/move/swap bumps and IO Cell Bumps Pin of SiP Layout 45-degree or 90-degree route Limited routing IO PAD /Bump /RDL Route Any-angle routing support 10 © 2013 Cadence Design Systems, Inc. All rights reserved. RDL Exchange Process Flow • Write Die Abstract file EDI • Write RDL route data SIP • Add Codesign die > Place Die by Die abstract file • Import rdl route • IO cell and bump modify /swap /add /delete • Peripheral or area array IO cell to Bump RDL Routing • Update ioupdate and rdl data (sip2edi ) • Read sip2edi.data into EDI EDI • powerstripe /DRC/LVS 11 © 2013 Cadence Design Systems, Inc. All rights reserved. ADD Co-Desgin Die and RDL import In SiP select the menu Add/Co-Desgin Die 12 © 2013 Cadence Design Systems, Inc. All rights reserved. IO Cell and Bump Pattern Optimization 13 © 2013 Cadence Design Systems, Inc. All rights reserved. Update IO/Bump/RDL from SiP edi rdl update 14 © 2013 Cadence Design Systems, Inc. All rights reserved. RDL routing Data import into EDI (read from sip2edi_codesign.data) SIP 15 © 2013 Cadence Design Systems, Inc. All rights reserved. EDI Dia abstract File Compare and Report Extracted from Tape-out version EDI data base Extracted from Tape-out version SiP data base Avoid eyechecking 16 © 2013 Cadence Design Systems, Inc. All rights reserved. Benefits and ROI of Comparison • Flip-chip case – IO Cell pad : 830 – Total Bump : 1690 (Core power /Ground : 785 + peripheral: 905) Items Methods Virtuoso Layout XL only Full Chip RDL layer (Bump/Routing /DRC/DFM/Checking) Multiple Power/Ground nets map to one net and Signal IC/PKG netmap 3 -4Weeks Can’t support Encounter fcroute only 3-4Weeks Distributed Codesign Methodology (SiP Layout XL+ EDI) 4days /1week Can’t support Support Database Merge GDS II, Physical EDI , with Netlist EDI, with Netlist Differential Pair Rule /Push/Shove Interconnection checking and Die pad/bump information compare cross platforms Can’t support Eye-checking , Timeconsuming, Error-prone Can’t support Eye-checking , Timeconsuming, Error-prone Support By tools , automatically, easily, convenient ROI: Return of Investment 17 © 2013 Cadence Design Systems, Inc. All rights reserved. Summary • The new codesign methodology bridge cross domain database interchange easily and effectively • Enable to meet aggressive time-to-market demand, shorten the design cycle time, save engineering efforts and cost • A new approach to do IC-PKG-PCB interconnection checking, quality control and chip tape out signoff 18 © 2013 Cadence Design Systems, Inc. All rights reserved.
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