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( DOC No. HX8347-A-AN ) HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver Version 01 September, 2007 HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Contents September, 2007 1. Introduction ...................................................................................................................................................4 2. HX8347-A Chip Block Diagram....................................................................................................................5 3. HX8347-A PAD Assignment.........................................................................................................................6 3.1 Alignment mark ................................................................................................................................... 7 3.2 Bump size ........................................................................................................................................... 8 4. Pin Description..............................................................................................................................................9 5. HX8347-A Reference FPC circuit (For CMO 3.2” / 2.4” / 2.8”LCD Panel) ..............................................13 5.1 Command-parameter interface mode............................................................................................... 13 5.1.1 MPU Interface ....................................................................................................................... 13 5.1.2 RGB interface........................................................................................................................ 14 5.2 Register-content interface mode....................................................................................................... 15 5.2.1 MPU interface........................................................................................................................ 15 5.2.2 RGB with Serial interface ...................................................................................................... 16 6. LCD POWER GENERATION.......................................................................................................................18 6.1 LCD Power Generation Scheme ...................................................................................................... 18 6.2 Various Boosting Steps ..................................................................................................................... 19 7. Software Configuration ..............................................................................................................................20 7.1 Features ............................................................................................................................................ 20 7.1.1 Display................................................................................................................................... 20 7.1.2 Display module...................................................................................................................... 20 7.1.3 Display/Control interface ....................................................................................................... 20 7.1.4 Others.................................................................................................................................... 21 7.2 GRAM mapping ................................................................................................................................ 22 7.3 Scan Function ................................................................................................................................... 23 7.4 Interface Mode .................................................................................................................................. 24 7.4.1 Interface Mode Selection ...................................................................................................... 24 7.4.2 Register-Content Interface Mode .......................................................................................... 24 7.4.3 Serial Data Transfer interface ............................................................................................... 33 7.4.4 Command-Parameter Interface Mode................................................................................... 35 7.4.5 RGB Interface........................................................................................................................ 41 7.5 Initial Procedure ................................................................................................................................ 44 7.5.1 Power Supply Setting Flow ................................................................................................... 44 7.5.2 Display on/off Setting Flow.................................................................................................... 45 7.5.3 Standby Mode Setting Flow .................................................................................................. 46 7.6 Initial code for reference ................................................................................................................... 47 7.6.1 The reference setting of Normal Display for Command-Parameter Interface Mode ............ 47 7.6.2 The reference setting of Normal Display for Register-Content Interface Mode .................... 48 7.6.2.1 The reference setting of CMO 3.2” Panel.................................................................. 48 7.6.2.2 The reference setting of CMO 2.4” Panel.................................................................. 50 7.6.2.3 The reference setting of CMO 2.8” Panel.................................................................. 52 7.6.3 The reference setting of into Standby mode for Register-Content Interface Mode............... 54 7.6.4 The reference setting of exit Standby mode for Register-Content Interface Mode............... 55 8. Revision History..........................................................................................................................................56 Himax Confidential -P.1- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Figures September, 2007 Figure 2. 1 HX8347-A block diagram ............................................................................................................ 5 Figure 5. 1 Reference FPC circuit Command-parameter interface mode’s MPU interface ........................ 13 Figure 5. 2 Reference FPC circuit of Command-parameter interface mode’s Serial + RGB interface....... 14 Figure 5. 3 Reference FPC circuit of Register-content interface mode’s MPU interface............................ 15 Figure 6. 1 LCD power generation scheme ................................................................................................ 18 Figure 6. 2 Various boosting steps .............................................................................................................. 19 Figure 7. 1 Memory Map. (240RGBx320) ................................................................................................... 22 Figure 7. 2 MY, MX, MV Setting .................................................................................................................. 23 Figure 7. 3 Input Data Bus and GRAM Data Mapping in 8-Bit Bus System Interface with 18( 6 + 6 + 6 ) Bit-Data Input (“BS2, BS1, BS0”=”011”).................................................................................... 25 Figure 7. 4 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 16 Bit-Data Input (“BS2, BS1, BS0”=”000”)........................................................................................................... 25 Figure 7. 5 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 18(16+2) Bit-Data Input (“BS2, BS1, BS0”=”001”) ................................................................................................. 25 Figure 7. 6 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 18(6+6+6) Bit-Data Input (“BS2, BS1, BS0”=”100”) ................................................................................... 26 Figure 7. 7 Input Data Bus and GRAM Data Mapping in 18-Bit Bus System Interface (“BS2, BS1, BS0”=”010” or ”101”) ................................................................................................................. 26 Figure 7. 8 Register read/write Timing in Parallel Bus System Interface (for I80 series MPU) .................. 27 Figure 7. 9 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface (for I80 series MPU)..... 28 Figure 7. 10 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for I80 series MPU) ........... 29 Figure 7. 11 Register read/write Timing in Parallel Bus System Interface (for M68 series MPU)............... 30 Figure 7. 12 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface (for M68 series MPU). 31 Figure 7. 13 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for M68 series MPU) ......... 32 Figure 7. 14 Data Write Timing in Serial Bus System Interface .................................................................. 33 Figure 7. 15 Data Read Timing in Serial Bus System Interface.................................................................. 34 Figure 7. 16 GRAM Write Data Mapping for 16 bit interface ...................................................................... 36 Figure 7. 17 GRAM Write Data Mapping for 8 bit interface ........................................................................ 36 Figure 7. 18 Register Read/Write Timing in Parallel Bus System Interface (for I80 series MPU) .............. 37 Figure 7. 19 Register read/write Timing in Parallel Bus System Interface (for M68 series MPU) .............. 38 Figure 7. 20 GRAM Read/Write Timing in Parallel Bus System Interface (for I80 series MPU)................. 39 Figure 7. 21 GRAM Read/Write Timing in Parallel Bus System Interface (for M68 series MPU)............... 40 Figure 7. 22 RGB Interface Circuit Input Timing ......................................................................................... 41 Figure 7. 23 18 bit / pixel Data Input of RGB Interface ............................................................................... 42 Figure 7. 24 16 bit / pixel Data Input of RGB Interface ............................................................................... 43 Figure 7. 25 Power Supply Setting Flow ..................................................................................................... 44 Figure 7. 26 Display On/Off Setting Flow.................................................................................................... 45 Figure 7. 27 Standby Mode Setting Flow .................................................................................................... 46 Himax Confidential -P.2- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Tables September, 2007 Table 5. 1 Connected Capacitor.................................................................................................................. 17 Table 5. 2 Connected Schottkey diode........................................................................................................ 17 Table 7. 1 MY, MX, MV Setting ................................................................................................................... 23 Table 7. 2 Interface Mode Selection............................................................................................................ 24 Table 7. 3 MPU selection in Register-content Interface Circuit................................................................... 24 Table 7. 4 Interface Selection in Register-content Interface Mode ............................................................. 24 Table 7. 5 Data Pin Function for I80 Series CPU ........................................................................................ 24 Table 7. 6 Data Pin Function for M68 Series CPU ...................................................................................... 24 Table 7. 7 The Function of RS and R/W Bit bus ......................................................................................... 33 Table 7. 8 MPU selection in Command-Parameter Interface Circuit........................................................... 35 Table 7. 9 Interface Selection in Command-Parameter Interface Mode ..................................................... 35 Table 7. 10 Data Pin Function for I80 Series CPU ...................................................................................... 35 Table 7. 11 Data Pin Function for M68 Series CPU .................................................................................... 35 Table 7. 12 EPL bit Setting and Valid ENABLE Signal................................................................................ 41 Himax Confidential -P.3- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver Version 01 September, 2007 1. Introduction This document describes Himax’s HX8347-A 240RGBx320 dots resolution driving controller. The HX8347-A is designed to provide a single-chip solution that combines a gate driver, a source driver, power supply circuit for 262,144 colors to drive a TFT panel with 240RGBx320 dots at maximum. The HX8347-A can be operated in low-voltage (1.65V) condition for the interface and integrated internal boosters that produce the liquid crystal voltage, breeder resistance and the voltage follower circuit for liquid crystal driver. In addition, The HX8347-A also supports various functions to reduce the power consumption of a LCD system via software control. The HX8347-A is suitable for any small portable battery-driven and long-term driving products, such as small PDAs, digital cellular phones and bi-directional pagers. The HX8347-A supports three interface modes: Command-Parameter interface mode, Register-Content interface mode and RGB interface mode. Command-Parameter interface mode and Register-Content interface mode are selected by the external pins IFSEL0 setting, and RGB interface mode is selected by internal bit RGB_EN. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed -P.4- in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K-Color TFT Controller Driver 2. HX8347-A Chip Block Diagram APPLICATION NOTE V01 S1 ~ S720 BS2~0, IFSEL0 P 68 ,EXTC 8 NISD, BURN NCS NRD_E NWR_RNW DNC_SCL D17~0 18 SDI SDO ENABLE VSYNC HSYNC DOTCLK NRESET TEST3~1 3 TS8~0 9 Internal register MPU IF 18-bit 16-bit 8-bit OTP Serial IF RGB IF 18-bit 16-bit MPU IF Serial IF GRAM control GRAM Mode selection RGB IF VCI VBGP VDDD OSC Power Regulator Timing Control Generator Timing Source driver D/A Converter circuit Data Latch V0~63 Grayscale voltage generator VTEST VMONI Gamma adjusting circuit VGH/VGL Gate Driver G1~G320 RC OSC VSSD VSSA Step Up1 Step Up2 Step Up3 VCOM Cricuit C11A/ C11B CX 11A/ CX 11B DDVDH C21A/ C21B C22A/ C22B V GH V GL C12A/ C12B V CL V C OM H V C OML V C OM R V C OM TV COMHI TVMA G Figure 2. 1 HX8347-A block diagram Himax Confidential -P.5- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 3. HX8347-A PAD Assignment APPLICATION NOTE V01 Figure 3. 1 HX8347-A pad assignment Himax Confidential -P.6- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 3.1 Alignment mark A_MARK (A1) APPLICATION NOTE V01 A_MARK (A2) Himax Confidential -P.7- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 3.2 Bump size Input PAD APPLICATION NOTE V01 Output PAD Himax Confidential -P.8- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 4. Pin Description APPLICATION NOTE V01 Signals I/O P68, BS2,BS1,BS0 I IFSEL0 I EXTC I NCS I NWR_RNW I NRD_E I Pin Number 4 1 1 1 1 1 Connected with VSSD/ IOVCC MPU MPU MPU MPU MPU Input Parts Description Select the MPU interface mode as listed below Use with IFSEL0=1 Register-content interface mode P68 BS2 BS1 BS0 Interface mode DB pins 0 0 0 0 16-bit bus interface, 80-system, D17-D16: Unused, 65K-Color D15-D0: Data 0 0 0 1 16-bit bus interface, 80-system, D17-D16: Unused, 262K-color D15-D0: Data 0 0 1 0 18-bit bus interface, 262K-color 80-system, D17-D0: Data 0 0 1 1 8-bit bus interface, 80-system, 262-Color D17-D8: Unused D7-D0: Data 0 1 0 0 16-bit bus interface, 80-system, D17-D16: Unused, 262-Color D15-D0: Data 0 1 0 1 18-bit bus interface, 262K-color 80-system, D17-D0: Data 1 0 0 0 16-bit bus interface, 68-system, D17-D16: Unused, 65K-Color D15-D0: Data 1 0 0 1 16-bit bus interface, 68-system, D17-D16: Unused, 262K-color D15-D0: Data 1 0 1 0 18-bit bus interface, 262K-Color 68-system, D17-D0: Data 1 0 1 1 8-bit bus interface, 68-system, 262K-color D17-D8:Unused D7-D0: Data 1 1 0 0 16-bit bus interface, 68-system, D17-D16: Unused, 262K-Color D15-D0: Data 1 1 0 1 18-bit bus interface, 262K-color 68-system, D17-D0: Data X 1 1 ID Serial bus IF DNC_SCL, SDO,SDI Use with IFSEL0=0 Command-Parameter interface mode P68 BS2 BS1 BS0 Interface mode DB pins 0 0 1 X 16-bit bus interface, 80-system, D17-D16:Unused, D15-D0: Data 0 0 0 X 8-bit bus interface, 80-system, D17-D8:Unused, D7-D0: Data 1 0 1 X 16-bit bus interface, 68-system, D17-D16:Unused, D15-D0: Data 1 0 0 X 8-bit bus interface, 68-system, D17-D8:Unused, D7-D0: Data x 1 1 x Serial interface D17-D0:Unused SDI, SDO (Other setting is inhibited) Interface format select pin IFSEL0 Interface Format Selection 0 Command-Parameter interface mode 1 Register-content interface mode In this case, the IFSEL0 has to be connected to IOVCC. Extended command set enable. (Only support Command-Parameter Interface mode Æ IFSEL0=0) Low: extended command set is discarded High: extended command set is accepted If operate in Register-content interface mode, the EXTC can be connected to IOVCC or VSSD. Chip select signal. Low: chip can be accessed; High: chip cannot be accessed. Must be connected to VSSD if not in use. I80 system: Serves as a write signal and writes data at the rising edge. M68 system: 0: Write, 1: Read. Fix it to IOVCC or VSSD level when using serial buss interface. I80 system: Serves as a read signal and read data at the low level. M68 system: 0: Read/Write disable, 1: Read/Write enable. Fix it to IOVCC or VSSD level when using serial buss interface. Himax Confidential -P.9- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver Signals BURN SDI DNC_SCL VSYNC HSYNC ENABLE DOTCLK NRESET OSC VCOMR VGS APPLICATION NOTE V01 Input Parts I/O Pin Connected Number with Description Free Running mode I 1 MPU If BURN=Hi, this can enable free running mode for burn in test. The display data alternates between full black and full white independent of input data in free running mode. I 1 MPU Serial data input pin. If not used, please let it connected to IOVCC or VSSD. The signal for command or parameter select under parallel I 1 MPU mode(i.e. Not serial interface): Low: command. High: parameter. When under serial interface, it servers as SCL. I 1 MPU Frame synchronizing signal. Has to be fixed to IOVCC level if is not used. I 1 MPU Frame synchronizing signal. Has to be fixed to IOVCC level if is not used. I 1 MPU A data ENABLE signal in RGB I/F mode. Has to be fixed to VSSD level if unused (High active, if EPL=0). I 1 MPU Dot clock signal. Has to be fixed to VSSD level if is not used. I 1 MPU or reset Reset pin. Setting either pin low initializes the LSI. Must be reset circuit after power is supplied. I 1 Oscillation Oscillator input for test purpose. Resistor If not used, please let it open or connected to VSSD. A VcomH reference voltage. When adjusting VcomH externally, set I 1 Resistor or open registers to halt the VcomH internal adjusting circuit and place a variable resistor between VREG1 and VSSD. Otherwise, leave this pin open and adjust VcomH by setting the internal register of the HX8347-A. I 1 VSSD or external resistor Connect to a variable resistor to adjusting internal gamma reference voltage for matching the characteristic of different panel used. Signals S1~S720 G1~G320 VCOM TE SDO NISD Output Part I/O Pin Connected Number with Description O 720 LCD Output voltages applied to the liquid crystal. O 320 LCD Gate driver output pins. These pins output VGH, VGL.(If not used, should be open) O 1 TFT common electrode The power supply of common voltage in TFT driving. The voltage amplitude between VCOMH and VCOML is output. Connect this pin to the common electrode in TFT panel. O 1 MPU Tearing effect output. If not used, please open this pin. O 1 MPU Serial data output. If not use, let it to open. O 1 Open Image Sticking Discharge signal. This pin is used for monitoring image sticking discharge phenomena. When the NISD goes low, the VGL would be discharged to VSSA. When the NISD goes high, the VGL, Source and VCOM are normal operation. Himax Confidential -P.10- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 Signals I/O C11A,C11B C12A,C12B I/O CX11A, CX11B I/O C21A,C21B C22A,C22B I/O D17~0 I/O Pin Number 4 2 4 18 Input/Output Part Connected with Description Step-up Connect to the step-up capacitors according to the step-up factor. Capacitor Leave this pin open if the internal step-up circuit is not used. Step-up Connect to the step-up capacitors for step up circuit 1 operation. Capacitor Leave this pin open if the internal step-up circuit is not used. Step-up Capacitor Connect these pins to the capacitors for the step-up circuit 2. According to the step-up rate. When not using the step-up circuit2, disconnect them. MPU 1. 18-bit bi-directional data bus for system interface. 8-bit bus: use D7-D0 and D17-D8 unused. 16-bit bus: use D15-D0 and D17-D16 unused. 18-bit bus: use D17-D0 2. 18-bit data bus for RGB interface 16-bit bus: use D17-D13, D11-D1 and D12, D0 unused. 18-bit bus: use D17-D0 Connected unused pins to the VSSD level. Notice: When register RGB_EN=1 and pin ENABLE=1, D[17:0] is used as stream image data for display. It means MPU data bus and RGB data bus is shared. Signals IOVCC VCI VSSD VSSA VDDD REGVDD VBGP VREG1 VREG3 VCOMH VCOML VCL DDVDH VGH VGL Power Part I/O Pin Number Connected with Description P 1 Power Supply Digital IO Pad power supply P 1 Power Supply Analog power supply P 1 Ground Digital ground P 1 Ground Analog ground O 1 Stabilizing Output from internal logic voltage (1.6V). Connect to a stabilizing Capacitor capacitor If REGVDD = high, the internal VDDD regulator will be turned on. If I 1 MPU REGVDD = low, the internal VDDD regulator will be turned off, VDDD should connect to external power supply, the voltage range 1.65~1.95V. The REGVDD pin must be connected to IOVCC or VSSD. - 1 Open Band Gap Voltage. Let it to be open. P 1 Stabilizing Capacitor Internal generated stable power for source driver unit. P 1 Stabilizing Capacitor A reference voltage for VGH&VGL. P 1 Stabilizing capacitor Connect this pin to the capacitor for stabilization. This pin indicates a high level of VCOM amplitude generated in driving the VCOM alternation. P 1 Stabilizing When the VCOM alternation is driven, this pin indicates a low level capacitor of VCOM amplitude. Connect this pin to a capacitor for stabilization. P 1 Stabilizing capacitor A negative voltage for VCOML circuit, VCL=-VCI An output from the step-up circuit1. P 1 Stabilizing Connect to a stabilizing capacitor between VSSA and DDVDH. capacitor Place a schotkey barrier diode (see “configuration of the power supply”). An output from the step-up circuit2.or 4 ~ 6 time the VCI level. P 1 Stabilizing capacitor The step-up rate is determined with BT3-0 bits. Connect to a stabilizing capacitor between VSSD and VGH. Place a schottkey barrier diode between VCI and VGH. Place a schottkey barrier diode (see “configuration of the power supply”). An output from the step-up circuit2.or –3 ~ -5 time the VCI level. P 1 Stabilizing capacitor The step-up rate is determined with BT3-0 bits. Connect to a stabilizing capacitor between VSSD and VGL. Place a schottkey barrier diode between VSSD and VGL. Place a schottkey barrier diode (see “configuration of the power supply”). Himax Confidential -P.11- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 Signals I/O TEST3-1 I TS8~0 O VMONI O VTEST O TVCOMHI O TVMAG O DUMMYR14-15 - DUMMY1-13 DUMMY16-27 - IOGNDDUM O Pin Number 3 9 1 1 1 1 2 25 1 Test pin and others Connected with Description GND Test pin input (Internal pull low) Open A test pin. Disconnect it. Open A test pin. Disconnect it. Open Gamma voltage of Panel test pin output. Must be left open. Open A test pin output. Must be left open. Open A test pin output. Must be left open. Open Dummy pads. Available for measuring the COG contact resistance. DUMMYR14 and DUMMYR15 are short-circuited within the chip. Open Dummy pads Open Short-circuited within the chip Himax Confidential -P.12- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 16,777,216-Color TFT Controller Driver 5. HX8347-A Reference FPC circuit (For CMO 3.2” / 2.4” / 2.8”LCD Panel) 5.1 Command-parameter interface mode 5.1.1 MPU Interface APPLICATION NOTE V01 U3 HX8347-A C22A VCOM(Panel) VCOM(Panel) DUMMYR14 DUMMYR15 CX11B VX11B CX11A CX11A C11B C11B C21A C21A C21A C22B C22B C22B C22A C22A 100 C21B C12A C12A C21B C21B VGH VGH VGH C12B C12B C11A C11A VGL VGL VGL VREG3 VDDD VDDD VDDD 73 VREG3 VCL DDVDH DDVDH DDVDH 68 VCL VCOMH VCOMH VCOML VCOML VREG1 VREG1 VCOMR VSSD VSSD VSSD VCOM(IC) VCOM(IC) 55 VGS VBGP VSSA VSSA VSSA 50 VCI IOVCC VCI VCI VCI 45 IOVCC DNC_SCL NCS NISD BURN TE REGVDD IOVCC 37 NWR_RNW D0 SDO SDI NRD_E ENABLE D17 D16 D15 D14 D13 D12 D11 IFSEL0 NRESET VSYNC HSYNC DOTCLK VCOM(Panel) VCOM(Panel) OSC D5 D4 D3 D2 D1 D10 D9 D8 D7 D6 EXTC BS0 BS1 BS2 5 P68 109 110 101 102 103 104 105 106 107 108 96 97 98 99 91 92 93 94 95 86 87 88 89 90 78 79 80 81 82 83 84 85 74 75 76 77 69 70 71 72 61 62 63 64 65 66 67 56 57 58 59 60 51 52 53 54 46 47 48 49 38 39 40 41 42 43 44 33 34 35 36 28 29 30 31 32 23 24 25 26 27 15 16 17 18 19 20 21 22 10 11 12 13 14 6 7 8 9 1 2 3 4 VCOM OSC P68 EXTC BS0 BS1 BS2 NRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 NRD_E NWR_RNW DNC_SCL NCS NISD TE VBGP VSSA VSSD VCOM VCOMH VCOML VREG1 VCOMR VCL DDVDH VREG3 VDDD VGL VGH VCOM IOVCC C24 0603/1u/10V IOVCC VGS C22 0603/1u/10V C19 0603/1u/10V 2 R30 0603/0R 1 3 VR4 10K(OPEN) VCI C11AB1 0603/2.2u/10V CX11AB1 0603/2.2u/10V C15 0603/1u/10V C18 0805/1u/25V 2 1 VGL_D2 RB521S-30 C16 0805/1u/25V DDVDH_D2 RB521S-30 2 1 VCI C17 0603/1u/10V C21 0603/1u/10V 2 C20 0603/1u/10V 1 3 VR3 10K(OPEN) C10 0603/1u/10V C21AB1 C22AB1 C12AB1 0603/1u/10V 0603/1u/10V 0603/1u/10V 2 1 VCI VGH_D2 RB521S-30 C23 0805/1u/25V P68 BS2 BS1 BS0 Interface mode 0 0 0 X 8-bit bus interface, 80-system, 262K-Color 0 0 1 X 16-bit bus interface, 80-system, 262K-Color 1 0 0 X 8-bit bus interface, 68-system, 262K-Color 1 0 1 X 16-bit bus interface, 68-system, 262K-Color EXTC 0 1 Him ax Com m and Disable Enable 1. VCI = 2.3V~3.3V, IOVCC = 1.65V~3.3V. 2. SDO pin is output pin. SDO pin must be left floating when no use. 3. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description". VCI1 VCI IOVCC1 IOVCC VDDD1 DDVDH1 VCL1 VGH1 VGL1 VREG2 VREG4 VDDD DDVDH VCL VGH VGL VREG1 VREG3 VCOM1 VCOM VCOMR1 VCOMH1 VCOML1 VCOMR VCOMH VCOML VBGP1 VBGP VCI IOVCC VDDD DDVDH VCL VGH VGL VREG1 VREG3 VCOM VCOMR VCOMH VCOML VBGP EXT C P68 BS2 BS1 BS0 BL_V+ BL_V- VCI GND IOVCC NRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 NRD_E NWR_RNW DNC_SCL NCS TE GND GND 7 8 9 10 nRESET DB17 DB16 DB15 IOVCC 6 2 3 4 5 1 VCI VCI GND VCC R31 0603/0R R28 0603/0R VSSD VSSA NRESET1 NRESET NRD_E1 NRD_E NWR_RNW1 DNC_SCL1 NWR_RNW DNC_SCL NCS1 NCS OSC1 NISD1 TE1 OSC NISD TE 52 53 54 55 56 P68 51 47 48 49 50 42 43 44 45 46 37 38 39 40 41 29 30 31 32 33 34 35 36 24 25 26 27 28 20 21 22 23 DB6 19 12 13 14 15 16 17 18 NRESET NRD_E NWR_RNW DNC_SCL NCS OSC NISD TE BS2 BS1 BS0 GND BL+/NC BL_GND/NC NC NC NC EXTC NC NC NC NC NC SDO SDI NC NC NC nCS FLM GND NC VSYNC HSYNC DOTCLK ENABLE DB1 DB0 nRD_E NWR_RNW DNC_SCL DB5 DB4 DB3 DB2 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB14 11 J2 FPC56-0.5-4.0L GND3 GND4 GND GND Figure 5. 1 Reference FPC circuit Command-parameter interface mode’s MPU interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed -P.13- in whole or in part without prior written permission of Himax. September, 2007 September, 2007 in whole or in part without prior written permission of Himax. This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed -P.14- Himax Confidential GND5 GND6 GND GND J3 FPC56-0.5-4.0L Figure 5. 2 Reference FPC circuit of Command-parameter interface mode’s Serial + RGB interface 1 VCI VCI GND VCC 2 3 4 5 IOVCC 6 nRESET DB17 DB16 DB15 DB14 DB13 DB12 7 8 9 10 11 12 13 DB11 14 DB10 DB9 DB8 DB7 15 16 17 18 DB6 19 DB5 DB4 DB3 DB2 20 21 22 23 DB1 DB0 nRD_E NWR_RNW DNC_SCL nCS FLM GND 24 25 26 27 28 29 30 31 NC VSYNC HSYNC DOTCLK ENABLE 32 33 34 35 36 SDO SDI NC NC NC 37 38 39 40 41 NC NC NC NC NC 42 43 44 45 46 NC NC NC EXTC P68 BS2 BS1 BS0 47 48 49 50 51 52 53 54 GND BL+/NC BL_GND/NC 55 56 VCI GND IOVCC NRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DNC_SCL NCS TE GND VSYNC HSYNC DOTCLK ENABLE SDO SDI EXTC GND BL_V+ BL_V- NRESET SDO SDI DNC_SCL NCS OSC NISD TE VSSD VSSA R34 0603/0R R32 0603/0R NISD OSC2 OSC NCS2 NCS DNC_SCL2 DNC_SCL SDI1 SDI SDO1 SDO NRESET2 NRESET NISD2 VCI IOVCC VDDD DDVDH VCL VGH VGL VREG1 VREG3 VCOM VCOMR VCOMH VCOML VBGP TE TE2 Him ax Com m and Disable Enable EXTC 0 1 VBGP2 VBGP VCOMR2 VCOMH2 VCOML2 VCOMR VCOMH VCOML VCOM2 VCOM VGH VGL VREG1 VREG3 DDVDH VCL VDDD IOVCC2 IOVCC VCI2 VCI VDDD2 DDVDH2 VCL2 VGH2 VGL2 VREG6 VREG5 1. VCI = 2.3V~3.3V, IOVCC = 1.65V~1.95V. 2. SDO pin is output pin. SDO pin must be left floating when no use. 3. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description". C25 0603/1u/10V 3 VR5 10K(OPEN) C31 0603/1u/10V 1 2 C32 0603/1u/10V C28 0603/1u/10V R33 0603/0R 1 VCI 2 3 VR6 10K(OPEN) C35 0603/1u/10V VCI VCOM OSC 1 2 3 VCOM(Panel) VCOM(Panel) 4 OSC IOVCC EXTC 5 6 7 8 P68 EXTC BS0 BS1 9 BS2 NRESET VSYNC HSYNC DOTCLK 10 11 12 13 IFSEL0 NRESET VSYNC HSYNC ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 14 15 16 17 18 19 20 21 DOTCLK ENABLE D17 D16 D15 D14 D13 D12 DB10 DB9 DB8 DB7 DB6 22 23 24 25 26 D11 D10 D9 D8 D7 DB5 DB4 DB3 DB2 DB1 27 28 29 30 31 D6 D5 D4 D3 D2 IOVCC DB0 SDO SDI 32 33 34 35 36 D1 D0 SDO SDI NRD_E DNC_SCL NCS NISD TE 37 38 39 40 41 42 43 44 NWR_RNW DNC_SCL NCS NISD BURN TE REGVDD IOVCC IOVCC 45 46 47 48 IOVCC IOVCC VCI VCI 49 VCI VBGP VSSA 50 51 52 53 VCI VBGP VSSA VSSA VGS 54 VSSA C33 0603/1u/10V C30 0603/1u/10V 1 2 VSSD VCOM VCOMH 55 56 57 58 59 60 61 VGS VSSD VSSD VSSD VCOM(IC) VCOM(IC) VCOMH VCOML 62 VCOMH VREG1 VCOMR 63 64 65 66 VCOML VCOML VREG1 VREG1 67 VCOMR VCL DDVDH 68 69 70 71 VCL VCL DDVDH DDVDH 72 DDVDH C11AB2 0603/2.2u/10V CX11AB2 0603/2.2u/10V C26 0603/1u/10V C29 0805/1u/25V DDVDH_D3 RB521S-30 VREG3 VDDD 73 74 75 76 77 78 79 VREG3 VREG3 VDDD VDDD VDDD DUMMYR14 DUMMYR15 80 CX11B 2 81 82 83 84 VX11B CX11A CX11A C11B VGL_D3 RB521S-30 C27 0805/1u/25V 85 C11B 1 VGL 86 87 88 89 C11A C11A VGL VGL C21AB2 C12AB2 0603/1u/10V 0603/1u/10V 0603/1u/10V 2 VGH_D3 RB521S-30 C34 0805/1u/25V VGH 90 91 92 93 94 95 96 97 98 99 100 101 102 VGL VGH VGH VGH C12B C12B C12A C12A C21B C21B C21B C21A C21A 1 VCI C22AB2 103 104 105 106 107 C21A C22B C22B C22B C22A VCOM 108 109 110 C22A C22A VCOM(Panel) VCOM(Panel) APPLICATION NOTE V01 U4 HX8347-A HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 5.1.2 RGB interface HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 5.2 Register-content interface mode 5.2.1 MPU interface APPLICATION NOTE V01 U1 HX8347-A VCOM(Panel) C22B C22A C22A C22A VCOM(Panel) C21A C21A C21A C22B C22B VGH C12B C12B C12A C12A C21B C21B C21B VGL VGL VGL VGH VGH CX11A C11B C11B C11A C11A DUMMYR14 DUMMYR15 CX11B VX11B CX11A DDVDH DDVDH DDVDH VREG3 VREG3 VDDD VDDD VDDD 69 VCL VREG1 VREG1 VCOMR VCL VCOM(IC) VCOMH VCOMH VCOML VCOML VSSA VSSA VSSA VGS VSSD VSSD VSSD VCOM(IC) VCI VCI VCI VCI VBGP 46 IOVCC TE REGVDD IOVCC IOVCC NWR_RNW DNC_SCL NCS NISD BURN D4 D3 D2 D1 D0 SDO SDI NRD_E DOTCLK ENABLE D17 D16 EXTC BS0 BS1 BS2 IFSEL0 NRESET VSYNC HSYNC VCOM(Panel) VCOM(Panel) OSC 28 D5 D9 D8 D7 D6 23 D10 D14 D13 D12 D11 18 D15 5 P68 106 107 108 109 110 101 102 103 104 105 93 94 95 96 97 98 99 100 88 89 90 91 92 83 84 85 86 87 78 79 80 81 82 70 71 72 73 74 75 76 77 65 66 67 68 60 61 62 63 64 52 53 54 55 56 57 58 59 47 48 49 50 51 42 43 44 45 37 38 39 40 41 29 30 31 32 33 34 35 36 24 25 26 27 19 20 21 22 14 15 16 17 6 7 8 9 10 11 12 13 1 2 3 4 VCOM OSC P68 BS0 BS1 BS2 NRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 NRD_E NWR_RNW DNC_SCL NCS NISD TE VBGP VSSA VSSD VCOM VCOMH VCOML VREG1 VCOMR VCL DDVDH VREG3 VDDD VGL VGH VCOM IOVCC C8 0603/1u/10V IOVCC VGS C4 0603/1u/10V C2 0603/1u/10V 2 R26 0603/0R 1 3 VR1 10K(OPEN) VCI C11AB 0603/2.2u/10V CX11AB 0603/2.2u/10V C6 0603/1u/10V C3 0805/1u/25V 2 1 VGL_D1 RB521S-30 C9 0805/1u/25V DDVDH_D1 RB521S-30 2 1 VCI C13 0603/1u/10V C21AB C22AB C12AB 0603/1u/10V 0603/1u/10V 0603/1u/10V 2 1 VCI VGH_D1 RB521S-30 C11 0805/1u/25V P68 BS2 BS1 BS0 Interface mode 0 0 0 0 16-bit bus interface, 80-system, 65K-Color 0 0 0 1 16-bit bus interface, 80-system, 262K-Color 0 0 1 0 18-bit bus interface, 80-system, 262K-Color 0 0 1 1 8-bit bus interface, 80-system, 262K-Color 0 1 0 0 16-bit bus interface, 80-system, 262K-Color 0 1 0 1 18-bit bus interface, 80-system, 262K-Color 1 0 0 0 16-bit bus interface, 68-system, 65K-Color 1 0 0 1 16-bit bus interface, 68-system, 262K-Color 1 0 1 0 18-bit bus interface, 68-system, 262K-Color 1 0 1 1 8-bit bus interface, 68-system, 262K-Color 1 1 0 0 16-bit bus interface, 68-system, 262K-Color 1 1 0 1 18-bit bus interface, 68-system, 262K-Color C14 0603/1u/10V 2 C12 0603/1u/10V 1 3 VR2 10K(OPEN) C5 0603/1u/10V 1. VCI = 2.3V~3.3V, IOVCC = 1.65V~3.3V. 2. SDO pin is output pin. SDO pin must be left floating when no use. 3. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description". VCI IOVCC VCI IOVCC VDDD VDDD DDVDH VCL DDVDH VCL VGH VGH VGL VREG1 VREG3 VGL VREG1 VREG3 VCOM VCOM VCOMR VCOMH VCOML VCOMR VCOMH VCOML VBGP VBGP VCI IOVCC VDDD DDVDH VCL VGH VGL VREG1 VREG3 VCOM VCOMR VCOMH VCOML VBGP P68 BS2 BS1 BS0 BL_V+ BL_V- GND R23 0603/0R R24 0603/0R VSSD VSSA NRESET NRESET NRD_E NRD_E NWR_RNW NWR_RNW DNC_SCL DNC_SCL NCS NCS OSC NISD TE OSC NISD TE 56 51 52 53 54 55 43 44 45 46 47 48 49 50 NC 42 38 39 40 41 SDO 37 33 34 35 36 NC 32 28 29 30 31 20 21 22 23 24 25 26 27 DB6 19 15 16 17 18 NRESET NRD_E NWR_RNW DNC_SCL NCS OSC NISD TE BL+/NC BL_GND/NC P68 BS2 BS1 BS0 GND NC NC NC NC NC NC NC NC SDI NC NC NC VSYNC HSYNC DOTCLK ENABLE DNC_SCL nCS FLM GND DB5 DB4 DB3 DB2 DB1 DB0 nRD_E NWR_RNW DB10 DB9 DB8 DB7 DB11 14 10 11 12 13 DB15 DB14 DB13 DB12 J1 FPC56-0.5-4.0L GND1 GND2 GND GND Figure 5. 3 Reference FPC circuit of Register-content interface mode’s MPU interface VCI GND IOVCC NRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 NRD_E NWR_RNW DNC_SCL NCS TE GND DB16 9 2 3 4 5 6 7 8 1 VCI VCI GND VCC IOVCC nRESET DB17 Himax Confidential -P.15- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 September, 2007 in whole or in part without prior written permission of Himax. This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed -P.16- Himax Confidential GND1 GND2 GND GND J1 FPC56-0.5-4.0L Figure 5. 4 Reference FPC circuit of Register-content interface mode’s RGB interface 1 VCI VCI GND VCC IOVCC nRESET DB17 2 3 4 5 6 7 8 DB16 DB15 DB14 DB13 9 10 11 12 DB12 DB11 DB10 13 14 15 DB9 16 DB8 DB7 DB6 DB5 DB4 DB3 DB2 17 18 19 20 21 22 23 DB1 DB0 nRD_E NWR_RNW 24 25 26 27 DNC_SCL nCS FLM 28 29 30 GND 31 NC VSYNC HSYNC DOTCLK ENABLE SDO SDI 32 33 34 35 36 37 38 NC NC NC 39 40 41 NC 42 NC NC NC 43 44 45 NC 46 NC NC NC NC P68 BS2 BS1 47 48 49 50 51 52 53 BS0 GND BL+/NC 54 55 56 BL_GND/NC VCI GND IOVCC NRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DNC_SCL NCS TE GND VSYNC HSYNC DOTCLK ENABLE SDO SDI BS0 GND BL_V+ BL_V- NRESET SDO SDI DNC_SCL NCS OSC NISD TE VSSD VSSA R23 0603/0R R24 0603/0R NISD OSC OSC NCS NCS DNC_SCL DNC_SCL SDI SDO NRESET NRESET NISD SDI SDO VCI IOVCC VDDD DDVDH VCL VGH VGL VREG1 VREG3 VCOM VCOMR VCOMH VCOML VBGP TE TE 1 1 VBGP VBGP VCOMR VCOMH VCOML VCOMR VCOMH VCOML VCOM VCOM VGL VREG1 VREG3 VGL VREG1 VREG3 VGH VGH DDVDH VCL DDVDH VCL VDDD VDDD IOVCC VCI 0 0 IOVCC VCI SPI ID BS0 1. VCI = 2.3V~3.3V, IOVCC = 1.65V~3.3V. 2. SDO pin is output pin. SDO pin must be left floating when no use. 3. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description". C5 0603/1u/10V 3 VR2 10K(OPEN) C12 0603/1u/10V 1 2 C14 0603/1u/10V C13 0603/1u/10V R26 0603/0R 1 VCI 2 3 VR1 10K(OPEN) C8 0603/1u/10V VCI IOVCC IOVCC VCOM OSC BS0 NRESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI DNC_SCL NCS NISD TE IOVCC 1 2 C4 0603/1u/10V C2 0603/1u/10V VGS VBGP VSSA VCOML VSSD VCOM VCOMH VREG1 VCOMR VCL DDVDH VREG3 VDDD C11AB 0603/2.2u/10V CX11AB 0603/2.2u/10V C6 0603/1u/10V C3 0805/1u/25V DDVDH_D1 RB521S-30 2 VGL_D1 RB521S-30 C9 0805/1u/25V 1 VGL VGH C21AB C12AB 0603/1u/10V 0603/1u/10V 0603/1u/10V 2 VGH_D1 RB521S-30 C11 0805/1u/25V 1 VCI C22AB VCOM 1 2 VCOM(Panel) 3 4 5 VCOM(Panel) OSC P68 6 EXTC 7 8 9 10 11 12 13 BS0 BS1 BS2 IFSEL0 NRESET VSYNC HSYNC 14 15 16 17 DOTCLK ENABLE D17 D16 18 19 20 D15 D14 D13 21 D12 22 23 24 25 26 27 28 D11 D10 D9 D8 D7 D6 D5 29 30 31 D4 D3 D2 32 D1 33 34 35 D0 SDO SDI 36 NRD_E 37 38 39 40 41 42 43 NWR_RNW DNC_SCL NCS NISD BURN TE REGVDD 44 45 46 IOVCC IOVCC IOVCC 47 VCI 48 49 50 51 VCI VCI VCI VBGP 52 53 54 VSSA VSSA VSSA 55 56 57 58 VGS VSSD VSSD VSSD 59 60 61 VCOM(IC) VCOM(IC) VCOMH 62 VCOMH 63 64 65 66 VCOML VCOML VREG1 VREG1 67 68 69 VCOMR VCL VCL 70 71 72 73 DDVDH DDVDH DDVDH VREG3 74 75 76 VREG3 VDDD VDDD 77 VDDD 78 79 80 81 DUMMYR14 DUMMYR15 CX11B VX11B 82 83 84 CX11A CX11A C11B 85 86 87 88 C11B C11A C11A VGL 89 90 91 VGL VGL VGH 92 VGH 93 94 95 96 97 98 99 VGH C12B C12B C12A C12A C21B C21B 100 101 102 103 C21B C21A C21A C21A 104 105 106 C22B C22B C22B 107 C22A 108 109 110 C22A C22A VCOM(Panel) VCOM(Panel) APPLICATION NOTE V01 U1 HX8347-A HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 5.2.2 RGB with Serial interface HX8347-A 240RGB x 320 dot, 262K-Color TFT Controller Driver APPLICATION NOTE V01 The specification of FPC circuit and pins connection is shown as following table: Pad Name Connection Typical capacitance value (B characteristics) VCOMH Connect to Capacitor (Max 6V): VCOMH---(+)----| |--- (-)------ VSSA 1.0 uF VCOML Connect to Capacitor (Max 3V): VCOML ---(-)----| |--- (+)----- VSSA 1.0 uF VGL Connect to Capacitor (Max 16V): VGL ---(-)----| |--- (+)----- VSSA 1.0 uF VGH Connect to Capacitor (Max 21V): VGH ---(+)----| |--- (-)----- VSSA 1.0 uF VCL Connect to Capacitor (Max 5V): VCL ---(-)----| |--- (+)----- VSSA 1.0 uF C22A - C22B Connect to Capacitor (Max 7V): C22A ---(+)----| |--- (-)-----C22B 1.0 uF C21A - C21B Connect to Capacitor (Max 7V): C21A ---(+)----| |--- (-)-----C21B 1.0 uF CX11A - CX11B Connect to Capacitor (Max 7V): CX11A ---(+)----| |--- (-)-----CX11B 2.2 uF C11A - C11B Connect to Capacitor (Max 5V): C11A ---(+)----| |--- (-)-----C11B 2.2 uF C12A - C12B Connect to Capacitor (Max 5V): C12A ---(+)----| |--- (-)-----C12B 1.0 uF VREG1 Connect to Capacitor (Max 6V): VREG1 ---(+)----| |--- (-)-----VSSA 1.0 uF VREG3 Connect to Capacitor (Max 16V): VREG3 ---(+)----| |--- (-)-----VSSA 1.0 uF VDDD Connect to Capacitor (Max 6V): VDDD ---(+)----| |--- (-)-----VSSA 1.0 uF DDVDH Connect to Capacitor (Max 6V): DDVDH ---(+)----| |--- (-)-----VSSA 1.0 uF VCI Connect to Capacitor (Max 6V): VCI ---(+)----| |--- (-)-----VSSA 2.2 uF IOVCC Connect to Capacitor (Max 6V): IOVCC ---(+)----| |--- (-)-----VSSA 1.0 uF Note: The aforementioned capacitor must be connected otherwise it will cause poor display quality. Table 5. 1 Connected Capacitor Pins connection 1. VCI – VLCD 2. VCI – VGH 3. VSSD – VGL Feature VF < 0.4V / 20mA at 25°C, VR ≥30V (Recommended diode: RB521S-30) Table 5. 2 Connected Schottkey diode Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed -P.17- in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 6. LCD POWER GENERATION 6.1 LCD Power Generation Scheme The boost voltage generated is shown as below. APPLICATION NOTE V01 VCI (2.3 ~ 3.3V) IOVCC (1.65V~3.3V) VSSA, VSSD (0V) x 2~3 DC/DC VGH VGH(4 VCI~6 VCI) x 4~6 DC/DC DDVDH DDVDH (4.6V ~ 6.0V) VREG1 VCOMH VREG3 VREG1 (3.5 ~ (DDVDH-0.5)V) VCOMH VDDD VDDD(1.8V) VBGP(1.25V) VCOM Amplitude DC/DC x (-1) VCOML VCOML VCL DC/DC x (-3)~(-5) VGL VGL(-5 VCI ~ -3 VCI) Figure 6. 1 LCD power generation scheme Himax Confidential -P.18- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 6.2 Various Boosting Steps APPLICATION NOTE V01 The boost steps of each boosting voltage are selected according to how the external capacitors are connected. Different booster applications are shown as below. DDVDH C11A DDVDH C11B CX11A CX11B VGH, VGL C21A VGH C21B C22A VGL C22B VCL C12A VCL C12B Figure 6. 2 Various boosting steps Himax Confidential -P.19- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7. Software Configuration APPLICATION NOTE V01 7.1 Features 7.1.1 Display z Resolution: 240(H) x RGB(H) x 320(V) z Display Color modes A. Normal Display Mode On a. Command-Parameter interface mode i. 262,144(R(6),G(6),B(6)) colors b. Register-Content interface mode i. 262,144(R(6),G(6),B(6)) colors ii. 65,536(R(5),G(6),B(5)) colors B. Idle Mode On a. 8 (R(1),G(1),B(1)) colors. 7.1.2 Display module z AM-LCD glass 240xRGBx320 z Gamma correction (4 preset gamma curves) z On module VCOM control (-2.0 to 5.5V Common electrode output voltage range) z On module DC/DC converter A. DDVDH = 4.6 to 6.0V (Source output voltage range) B. VGH = +9.0 to +16.5V (Positive Gate output voltage range) C. VGL = -6.0 to -13.5V (Negative Gate output voltage range) z Frame Memory area 240 (H) x 320 (V) x 18 bit 7.1.3 Display/Control interface z Display Interface types supported A. Command-Parameter interface mode z 8-/16-bit MPU parallel interface. z Serial data transfer interface. z 16, 18 data lines parallel video (RGB) interface. B. Register-Content interface mode z 8-/16-/18-bit MPU parallel interface. z Serial data transfer interface. z 16, 18 data lines parallel video (RGB) interface. z Control Interface types supported A. Command-Parameter interface mode.( IFSEL0= 0 ) B. Register-Content interface mode (IFSEL0 = 1) z Logic voltage (IOVCC): A. HX8347-A00: 1.65V ~ 1.95V B. HX8347-A01: 1.65V ~ 3.3V z Driver power supply (VCI): 2.3 ~ 3.3V z Color modes A. 16 bit/pixel: R(5), G(6), B(5) B. 18 bit/pixel: R(6), G(6), B(6) Himax Confidential -P.20- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.1.4 Others APPLICATION NOTE V01 z Low power consumption, suitable for battery operated systems z Image sticking eliminated function z CMOS compatible inputs z Optimized layout for COG assembly z Temperature range: -40 ~ +85 °C z Proprietary multi phase driving for lower power consumption z Support external VDD for lower power consumption (such as 1.8 volts input) z Support RGB through mode with lower power consumption z Support normal black/normal white LCD z Support wide view angle display z Support burn-in mode for efficient test in module production z On-chip OTP (one-time-programming) non-volatile memory Himax Confidential -P.21- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.2 GRAM mapping APPLICATION NOTE V01 Pixel1 Pixel2 Pixel239 Pixel240 Source Out S1 S2 S3 S4 S5 S6 S715 S716 S717 S718 S719 S720 RA MY=0 MY=1 0 319 R0 5-0 1 318 2 317 3 316 4 315 5 314 6 313 7 312 8 311 9 310 10 309 11 308 : : : : : : : : : : : : : : : : : : 312 7 313 6 314 5 315 4 316 3 317 2 318 1 319 0 CA MX=0 MX= 1 G0 5-0 : : : : : : 0 239 B0 5-0 : : : : : : R1 5-0 : : : : : : G15-0 B15-0 : : : : : : : : : : : : 1 238 RGB Order :BGR=0 :BGR=1 -- ------------- --------- R238 G238 B238 R239 G239 B239 5-0 5-0 5-0 5-0 5-0 5-0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 238 1 RN 7-0 GN 7-0 239 0 BN 7-0 Note: RA = Row Address, CA = Column Address, MX = Mirror X-axis (Column address direction parameter), D6 parameter of Memory Access Control command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of Memory Access Control command BGR= Red, Green and Blue pixel position change, D3 parameter of Memory Access Control command Figure 7. 1 Memory Map. (240RGBx320) Himax Confidential -P.22- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.3 Scan Function APPLICATION NOTE V01 The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by “Memory Data Access Control” Command, Bits MY, MX, MV as described below. MADCTL CASET PASET MV MX MY Virtual to Physical Pointer Translator Physical Column Pointer (0 , 0) Physical axes (239 , 0) Physical Page Pointer (0 , 319) Figure 7. 2 MY, MX, MV Setting (239 , 319) MY MX MV CASET 0 0 0 Direct to Physical Column Pointer 0 0 1 Direct to Physical Column Pointer 0 1 0 Direct to (239-Physical Column Pointer) 0 1 1 Direct to (239-Physical Column Pointer) 1 0 0 Direct to Physical Page Pointer 1 0 1 Direct to (319-Physical Page Pointer) 1 1 0 Direct to Physical Page Pointer 1 1 1 Direct to (319-Physical Page Pointer) PASET Direct to Physical Page Pointer Direct to (319-Physical Page Pointer) Direct to Physical Page Pointer Direct to (319-Physical Page Pointer) Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (239-Physical Column Pointer) Direct to (239-Physical Column Pointer) Table 7. 1 MY, MX, MV Setting Himax Confidential -P.23- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.4 Interface Mode APPLICATION NOTE V01 7.4.1 Interface Mode Selection IFSEL0 0 0 1 1 RGB_EN Register Data Display Data 0 Command-parameter interface (Parallel interface) From SRAM 1 Command-parameter interface Sleep out Normal Display On : From RGB interface (Serial interface) Sleep out Partial Mode On : From SRAM 0 Register-content interface (Parallel interface) From SRAM 1 Register-content interface (Serial interface) Normal display: From RGB interface Partial Mode: From SRAM Table 7. 2 Interface Mode Selection 7.4.2 Register-Content Interface Mode P68 Input signal format selection 0 Format for I80 series MPU 1 Format for M68 series MPU Table 7. 3 MPU selection in Register-content Interface Circuit BS2 BS1 BS0 Interface Transferring Method of GRAM Transferring Method of data Command 0 0 0 16-bit system interface 16-bit 65K-color 0 0 1 16-bit system interface 18-bit 262K-color (16+2) 0 1 0 18-bit system interface 0 1 1 8-bit system interface 18-bit 262K-color 18-bit 262K-color (6+6+6) 8-bit collective 1 0 0 16-bit system interface 18-bit 262K-color (6+6+6) 1 0 1 18-bit system interface 18-bit 262K-color 1 1 ID Serial interface RGB_EN=0,Select by register 72h Table 7. 4 Interface Selection in Register-content Interface Mode Parallel Bus System Interface a. Data Pin Function for I80/M68 Series CPU Operations E_NWR RW_NRD Writes Indexes into IR 0 1 Reads internal status 1 0 Writes command into register or data into GRAM 0 1 Reads command from register or data from GRAM 1 0 Table 7. 5 Data Pin Function for I80 Series CPU DNC_SCL 0 0 1 1 Operations E_NWR RW_NRD Writes Indexes into IR 1 0 Reads internal status 1 1 Writes command into register or data into GRAM 1 0 Reads command from register or data from GRAM 1 1 Table 7. 6 Data Pin Function for M68 Series CPU DNC_SCL 0 0 1 1 Himax Confidential -P.24- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 b. Bit mapping of one pixel data: Input Data (8-/16-/18-bit Interface) Written to GRAM through Write Data Register Transfer Order 1 8-bit Data DDDDDD Input Data Bus 7 6 5 4 3 2 2 8-bit Data DDDDDD 765432 3 8-bit Data DDDDDD 765432 RRRRRR GRAM Data 5 4 3 2 1 0 GGGGGG 543210 B5 B4 B3 B2 B1 B0 262,144 Colors are avaliable Figure 7. 3 Input Data Bus and GRAM Data Mapping in 8-Bit Bus System Interface with 18(6+6+6) Bit-Data Input (“BS2, BS1, BS0”=”011”) Transfer Order DDDDD Input Data Bus 15 14 13 12 11 1 16-bit Data DDDDDDDDDDD 10 9 8 7 6 5 4 3 2 1 0 GRAM Data R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 G 3 G 2 G 1 G 0 B5 B4 B3 B2 B1 B0 65,536 Colors are avaliable Figure 7. 4 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 16 Bit-Data Input (“BS2, BS1, BS0”=”000”) Transfer Order 1 16-bit Data 2 2-bit Data D D D D D D D D D D D DD D D D D D Input Data Bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 GRAM Data R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 G 3 G 2 G 1 G 0 B5 B4 B3 B2 B1 B0 262,144 Colors are avaliable Figure 7. 5 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 18(16+2) Bit-Data Input (“BS2, BS1, BS0”=”001”) Himax Confidential -P.25- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 Figure 7. 6 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 18(6+6+6) Bit-Data Input (“BS2, BS1, BS0”=”100”) Figure 7. 7 Input Data Bus and GRAM Data Mapping in 18-Bit Bus System Interface (“BS2, BS1, BS0”=”010” or ”101”) Himax Confidential -P.26- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver i80- System Interface Timing Write to the register NCS DNC_SCL APPLICATION NOTE V01 NRD_E NWR_RNW D7-0 "index" write to index register Command write to the register Read the register NCS DNC_SCL NRD_E NWR_RNW D7-0 "index" write to index register Command read from the register Figure 7. 8 Register read/write Timing in Parallel Bus System Interface (for I80 series MPU) Himax Confidential -P.27- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 Figure 7. 9 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface (for I80 series MPU) Himax Confidential -P.28- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver Write to the graphic RAM (8-bit 262K Color) NCS DNC_SCL NRD_E NWR_RNW APPLICATION NOTE V01 D7-0 "22" h 1st write data 2nd write data 3rd write data 1st write data 2nd write data 3rd write data Read the graphic RAM (8-bit 262K Color) NCS DNC_SCL nth pixel ; Address = N (n+1)th pixel ; Address = N+1 NRD_E NWR_RNW D7-0 "22" h 1st read data 2nd read read 3rd read data R G B R G Dummy Read Data 1 pixel data (The format refer 8-bit Interface) Figure 7. 10 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for I80 series MPU) Himax Confidential -P.29- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver m68- System Interface Timing Write to the register NCS DNC_SCL NWR_RNW APPLICATION NOTE V01 NRD_E D7-0 "index" write to index register Command write to the register Read the register NCS DNC_SCL NWR_RNW NRD_E D7-0 "index" write to index register Command read from the register Figure 7. 11 Register read/write Timing in Parallel Bus System Interface (for M68 series MPU) Himax Confidential -P.30- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 Figure 7. 12 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface (for M68 series MPU) Himax Confidential -P.31- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 NCS DNC_SCL NWR_RNW NRD_E D7-0 "22" h 1st write data 2nd write data 3rd write data 1st write data 2nd write data 3rd write data nth pixel ; Address = N (n+1)th pixel ; Address = N+1 NCS DNC_SCL NWR_RNW NRD_E D7-0 "22" h 1st read data 2nd read data 3rd read data R G B R G Dummy Read Data 1 pixel data (The format refer 8-bit Interface) Figure 7. 13 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for M68 series MPU) Himax Confidential -P.32- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.4.3 Serial Data Transfer interface APPLICATION NOTE V01 RS R/W Function 0 0 Writes Indexes into IR 1 0 Writes command into register or data into GRAM 1 1 Reads command from register or data from GRAM Table 7. 7 The Function of RS and R/W Bit bus Serial Data Transfer interface Timing Figure 7. 14 Data Write Timing in Serial Bus System Interface Himax Confidential -P.33- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver A)TransferTiming Format in Serial Bus Interface for Register Read DNC_SCL (Input) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Start End NCS SDI (Input) SDO (Output) "01110" ID Device ID code Start byte RS RW Status read, register read D7 D6 D5 D4 D3 D2 D1 D0 Status read, register read APPLICATION NOTE V01 SCL (Input) NCS Start End SDI (Input) Start byte SDO (Output) Dummy read GRAM read 1 GRAM read 2 Note: A RAM data read operation follows 8bit dummy read operations . GRAM read 3 GRAM read 4 Figure 7. 15 Data Read Timing in Serial Bus System Interface Himax Confidential -P.34- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.4.4 Command-Parameter Interface Mode APPLICATION NOTE V01 P68 Input signal format selection 0 Format for I80 series MPU 1 Format for M68 series MPU Table 7. 8 MPU selection in Command-Parameter Interface Circuit BS2 BS1 BS0 Interface Transferring Method Transferring Method of of GRAM data Command 0 0 x 8-bit system interface 18-bit 262K-color (6 + 6 +6) 0 1 x 16-bit system interface 18-bit 262K-color ( 6 + 6 + 6) 8-bit collective 1 1 ID Serial interface 18-bit (6+6+6) X: Don’t care. Table 7. 9 Interface Selection in Command-Parameter Interface Mode Operations E_NWR RW_NRD Writes command code 0 1 Reads internal status 1 0 Writes parameter into command or data into GRAM 0 1 Reads parameter from command or data from GRAM 1 0 Table 7. 10 Data Pin Function for I80 Series CPU DNC_SCL 0 0 1 1 Operations E_NWR RW_NRD Writes command code 1 0 Reads internal status 1 1 Writes parameter into command or data into GRAM 1 0 Reads parameter from command or data from GRAM 1 1 Table 7. 11 Data Pin Function for M68 Series CPU DNC_SCL 0 0 1 1 Himax Confidential -P.35- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 16-bit Parallel Bus System Interface APPLICATION NOTE V01 Figure 7. 16 GRAM Write Data Mapping for 16 bit interface 8-bit Parallel Bus System Interface Figure 7. 17 GRAM Write Data Mapping for 8 bit interface Himax Confidential -P.36- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver Command-Parameter Interface Mode Timing Write to register 1 byte command 2 byte command n byte command APPLICATION NOTE V01 S CMD CMD PA1 CMD PA1 NCS DNC_SCL NRD_E NWR_RNW HOST D7-0 (MPU to LCD) Driver D7-0 ( LCD to MPU) CMD CMD PA1 CMD PA1 Hi - Z CMD: command code PA: parameter Read from register 2 byte command n byte command S CMD dummy PA1 NCS DNC _ SCL NRD_E NWR_RNW D7-0 HOST D7-0 ( MPU to LCD ) Driver D7-0 ( LCD to MPU) CMD CMD dummy PA1 Hi-Z Hi-Z dummy PA1 CMD dummy PAn-1 CMD dummy PAn-1 CMD Hi-Z CMD PAn-1 PAn-3 PAn-2 PA n-1 PAn-3 PAn-2 PA n-1 PA3 PA2 PA1 Hi-Z Hi-Z Hi-Z PA3 PA2 PA1 PA3 PA2 PA1 CMD: command code PA: parameter Figure 7. 18 Register Read/Write Timing in Parallel Bus System Interface (for I80 series MPU) Himax Confidential -P.37- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver Write to register 1 byte command 2 byte command n byte command S CMD CMD PA1 CMD PA1 NCS DNC_SCL NWR_RNW NRD_E HOST D7-0 (MPU to LCD) Driver D7-0 (LCD to MPU) CMD CMD PA1 CMD PA1 H i -Z CMD: command code PA: parameter Read from register 2 byte command n byte command S CMD dummy PA1 CMD dummy PAn-1 NCS DNC _ SCL NWR_RNW NRD_E DB 7 -0 HOST D7-0 ( MPU to LCD ) Driver D7-0 (LCD to MPU) CMD dummy PA1 CMD Hi-Z Hi-Z dummy PA1 CMD dummy PAn-1 CMD Hi-Z CMD PAn-1 Hi-Z Hi-Z Hi-Z CMD: command code PA: parameter APPLICATION NOTE V01 PAn-3 PAn-2 PA n-1 PAn-3 PAn-2 PA n-1 PA3 PA2 PA1 PA3 PA2 PA1 PA3 PA2 PA1 Figure 7. 19 Register read/write Timing in Parallel Bus System Interface (for M68 series MPU) Himax Confidential -P.38- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 Write to GRAM n pixel RAM data write NCS S 2Ch Data 1 DNC_SCL NRD_E NWR_RNW (MPU to LCD) (LCD to MPU) 2Ch Data 1 Hi - Z Data n-2 Data n-1 Data n Data n-2 Data n-1 Data n CMD: command code PA: parameter Read from GRAM n pixel RAM data read S 2Eh dummy Data 1 NCS DNC _ SCL NRD_E NWR_WNR ( MPU to LCD ) (LCD to MPU) 2Eh dummy Data1 2Eh Hi -Z dummy Data 1 Data n-2 Data n-1 Data n Hi -Z Hi -Z Hi -Z Data n-2 Data n-1 Data n Data n-2 Data n-1 Data n Figure 7. 20 GRAM Read/Write Timing in Parallel Bus System Interface (for I80 series MPU) Himax Confidential -P.39- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver Write to GRAM n pixel RAM data write APPLICATION NOTE V01 NCS S 2Ch Data 1 Data n-2 Data n-1 Data n DNC_SCL NWR_RNW NRD_E (MPU to LCD) (LCD to MPU) 2Ch Data 1 Hi -Z Data n-2 Data n-1 Data n CMD: command code PA: parameter Read from GRAM n pixel RAM data read S 2Eh dummy Data 1 NCS DNC _ SCL NWR_RNW NRD_E 2Eh dummy Data1 ( MPU to LCD ) (LCD to MPU) 2Eh Hi - Z dummy Data 1 Data n-2 Data n-1 Data n Hi -Z Hi -Z Hi -Z Data n-2 Data n-1 Data n Data n-2 Data n-1 Data n : Figure 7. 21 GRAM Read/Write Timing in Parallel Bus System Interface (for M68 series MPU) Himax Confidential -P.40- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.4.5 RGB Interface APPLICATION NOTE V01 EPL ENABLE Display 0 0 Disable 0 1 Enable 1 0 Enable 1 1 Disable Table 7. 12 EPL bit setting and Valid ENABLE Signal RGB Interface Timing (VSPL bit=0) VSYNC Vertical Back porch Display area for RAM data Display period Horizontal Back porch HSYNC DOTCLK ENABLE D17-0 ( HSPL bit = 0 ) ( DPL bit = 0 ) ( EPL bit = 0 ) Figure 7. 22 RGB Interface Circuit Input Timing Himax Confidential -P.41- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 (1) 18 bit/pixel color order (R 6-bit, G 6-bit, B 6-bit), 262,144 colors (CSEL (2-0) = “110”) Figure 7. 23 18 bit / pixel Data Input of RGB Interface Himax Confidential -P.42- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 (2) 16 bit/pixel color order (R 5-bit, G 6-bit, B 5-bit), 65,536 colors (CSEL (2-0) = “101”) Figure 7. 24 16 bit / pixel Data Input of RGB Interface Himax Confidential -P.43- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.5 Initial Procedure 7.5.1 Power Supply Setting Flow APPLICATION NOTE V01 Power ON flow Vcc,Vci,IOVcc ON Note 1 Note 2 Display OFF setting bits DTE="0",D[1-0]="00" GON="0" PON="0" DK="1" VCOMG="0" Power ON RESET & Display OFF Power supply setting initializing bits Set BT[2-0], VRH[3-0], VCM[6-0], VDV[4-0], VC1[2-0], VC3[2-0], For the setting before power supply startup Power Supply Operation Start setting bits AP[2-0]="100", PON="1" DK="0" For power-supply setting (1) Note 3 Power Supply Operation Start setting bits VCOMG="1" Note 4 For power-supply setting (2) For other mode settings Power OFF flow Display ON setting bits DTE = "1", D[1-0]="11" GON = "1" Normal Display Display OFF Set GON, DTE, D[1-0] Display OFF Sequence Power supply halt setting bits SAP[7-0]="00000000" AP[2-0]="000" PON="0" DK="1" VCOMG="0" Issue instructions for power-supply setting (2) Vcc,Vci,IVcc OFF Set SAP[7-0] Display ON sequence Set GON, DTE, D[1-0] Note1)1ms or more Note2)10ms or more Oscillation Circuit Stabilizing time Note3)40ms or more Step-up Circuit Stabilizing time Note4)100ms or more Operational Amplifier Stabilizing Time Figure 7. 25 Power Supply Setting Flow Himax Confidential -P.44- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.5.2 Display on/off Setting Flow APPLICATION NOTE V01 Display off flow Display off GON = "1" DTE = "1" D1-0 = "10" Wait 2 frames or more Display off GON = "1" DTE = "0" D1-0 = "10" Wait 2 frames or more Display off GON = "0" DTE = "0" D1-0 = "00" Power OFF Setting SAP[7-0] = "00000000" AP[2-0] ="000" PON ="0" DK ="1" VCOMG = "0" Display on flow Power ON setting Set SAP[7-0] Display on GON = "0" DTE = "0" D1-0 = "01" Wait 2 frames or more Display on GON = "1" DTE = "0" D1-0 = "01" Display on GON = "1" DTE = "0" D1-0 = "11" Wait 2 frames or more "Display off" Display on GON = "1" DTE = "1" D1-0 = "11" "Display on" Figure 7. 26 Display On/Off Setting Flow Himax Confidential -P.45- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.5.3 Standby Mode Setting Flow APPLICATION NOTE V01 Figure 7. 27 Standby Mode Setting Flow Himax Confidential -P.46- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.6 Initial code for reference APPLICATION NOTE V01 7.6.1 The reference setting of Normal Display for Command-Parameter Interface Mode void HX8347_Init(void) { RESET(); DelayX1ms(150); // After Inter-MicroP Program (load OTP) Set_NOKIA_CMD(0x11); // SLP out DelayX1ms(150); Set_NOKIA_CMD(0x29); // Display on DelayX1ms(150); } Himax Confidential -P.47- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 7.6.2 The reference setting of Normal Display for Register-Content Interface Mode 7.6.2.1 The reference setting of CMO 3.2” Panel void HX8347A_Init_CMO32(void) { RESET(); DelayX1ms(150); // After Inter-MicroP Program (load OTP) // Gamma for CMO 3.2” Set_LCD_8B_REG(0x0046,0x00A4); Set_LCD_8B_REG(0x0047,0x0053); Set_LCD_8B_REG(0x0048,0x0000); Set_LCD_8B_REG(0x0049,0x0044); Set_LCD_8B_REG(0x004A,0x0004); Set_LCD_8B_REG(0x004B,0x0067); Set_LCD_8B_REG(0x004C,0x0033); Set_LCD_8B_REG(0x004D,0x0077); Set_LCD_8B_REG(0x004E,0x0012); Set_LCD_8B_REG(0x004F,0x004C); Set_LCD_8B_REG(0x0050,0x0046); Set_LCD_8B_REG(0x0051,0x0044); //240x320 window setting Set_LCD_8B_REG(0x0002,0x0000); Set_LCD_8B_REG(0x0003,0x0000); Set_LCD_8B_REG(0x0004,0x0000); Set_LCD_8B_REG(0x0005,0x00EF); Set_LCD_8B_REG(0x0006,0x0000); Set_LCD_8B_REG(0x0007,0x0000); Set_LCD_8B_REG(0x0008,0x0001); Set_LCD_8B_REG(0x0009,0x003F); // Column address start2 // Column address start1 // Column address end2 // Column address end1 // Row address start2 // Row address start1 // Row address end2 // Row address end1 // Display Setting Set_LCD_8B_REG(0x0001,0x0006); // IDMON=0, INVON=1, NORON=1, PTLON=0 Set_LCD_8B_REG(0x0016,0x0048); // MY=0, MX=0, MV=0, ML=1, BGR=0, TEON=0 Set_LCD_8B_REG(0x0023,0x0095); Set_LCD_8B_REG(0x0024,0x0095); Set_LCD_8B_REG(0x0025,0x00FF); // N_DC=1001 0101 // PI_DC=1001 0101 // I_DC=1111 1111 Set_LCD_8B_REG(0x0027,0x0002); Set_LCD_8B_REG(0x0028,0x0002); Set_LCD_8B_REG(0x0029,0x0002); Set_LCD_8B_REG(0x002A,0x0002); Set_LCD_8B_REG(0x002C,0x0002); Set_LCD_8B_REG(0x002D,0x0002); // N_BP=0000 0010 // N_FP=0000 0010 // PI_BP=0000 0010 // PI_FP=0000 0010 // I_BP=0000 0010 // I_FP=0000 0010 Set_LCD_8B_REG(0x003A,0x0001); Set_LCD_8B_REG(0x003B,0x0000); Set_LCD_8B_REG(0x003C,0x00F0); Set_LCD_8B_REG(0x003D,0x0000); DelayX1ms(20); // N_RTN=0000, N_NW=001 // PI_RTN=0000, PI_NW=000 // I_RTN=1111, I_NW=000 // DIV=00 Himax Confidential -P.48- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver Set_LCD_8B_REG(0x0035,0x0038); // EQS=38h Set_LCD_8B_REG(0x0036,0x0078); // EQP=78h APPLICATION NOTE V01 Set_LCD_8B_REG(0x003E,0x0038); // SON=38h Set_LCD_8B_REG(0x0040,0x000F); // GDON=0Fh Set_LCD_8B_REG(0x0041,0x00F0); // GDOFF // Power Supply Setting Set_LCD_8B_REG(0x0019,0x0049); Set_LCD_8B_REG(0x0093,0x000F); DelayX1ms(10); // CADJ=0100, CUADJ=100(FR:60Hz), OSD_EN=1 // RADJ=1111, 100% Set_LCD_8B_REG(0x0020,0x0040); Set_LCD_8B_REG(0x001D,0x0007); Set_LCD_8B_REG(0x001E,0x0000); Set_LCD_8B_REG(0x001F,0x0004); // BT=0100 // VC1=111 // VC3=000 // VRH=0100 // VCOM Setting for CMO 3.2” Panel Set_LCD_8B_REG(0x0044,0x004D); Set_LCD_8B_REG(0x0045,0x0011); DelayX1ms(10); // VCM=100 1101 // VDV=1 0001 Set_LCD_8B_REG(0x001C,0x0004); DelayX1ms(20); Set_LCD_8B_REG(0x001B,0x0018); DelayX1ms(40); // AP=100 // GASENB=0, PON=1, DK=1, XDK=0, VLCD_TRI=0, STB=0 Set_LCD_8B_REG(0x001B,0x0010); // GASENB=0, PON=1, DK=0, XDK=0, VLCD_TRI=0, STB=0 DelayX1ms(40); Set_LCD_8B_REG(0x0043,0x0080); //Set VCOMG=1 DelayX1ms(100); // Display ON Setting Set_LCD_8B_REG(0x0090,0x007F); // SAP=0111 1111 Set_LCD_8B_REG(0x0026,0x0004); DelayX1ms(40); Set_LCD_8B_REG(0x0026,0x0024); Set_LCD_8B_REG(0x0026,0x002C); DelayX1ms(40); //GON=0, DTE=0, D=01 //GON=1, DTE=0, D=01 //GON=1, DTE=0, D=11 Set_LCD_8B_REG(0x0026,0x003C); //GON=1, DTE=1, D=11 // Internal register setting Set_LCD_8B_REG(0x0057,0x0002); Set_LCD_8B_REG(0x0095,0x0001); Set_LCD_8B_REG(0x0057,0x0000); //Test_Mode Enable // Set Display clock and Pumping clock to synchronize // Test_Mode Disable } Himax Confidential -P.49- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.6.2.2 The reference setting of CMO 2.4” Panel APPLICATION NOTE V01 void HX8347A_Init_CMO24(void) { RESET(); DelayX1ms(150); // After Inter-MicroP Program (load OTP) // Gamma for CMO 2.4” Set_LCD_8B_REG(0x0046,0x0094); Set_LCD_8B_REG(0x0047,0x0041); Set_LCD_8B_REG(0x0048,0x0000); Set_LCD_8B_REG(0x0049,0x0033); Set_LCD_8B_REG(0x004A,0x0023); Set_LCD_8B_REG(0x004B,0x0045); Set_LCD_8B_REG(0x004C,0x0044); Set_LCD_8B_REG(0x004D,0x0077); Set_LCD_8B_REG(0x004E,0x0012); Set_LCD_8B_REG(0x004F,0x00CC); Set_LCD_8B_REG(0x0050,0x0046); Set_LCD_8B_REG(0x0051,0x0082); //240x320 window setting Set_LCD_8B_REG(0x0002,0x0000); Set_LCD_8B_REG(0x0003,0x0000); Set_LCD_8B_REG(0x0004,0x0000); Set_LCD_8B_REG(0x0005,0x00EF); Set_LCD_8B_REG(0x0006,0x0000); Set_LCD_8B_REG(0x0007,0x0000); Set_LCD_8B_REG(0x0008,0x0001); Set_LCD_8B_REG(0x0009,0x003F); // Column address start2 // Column address start1 // Column address end2 // Column address end1 // Row address start2 // Row address start1 // Row address end2 // Row address end1 // Display Setting Set_LCD_8B_REG(0x0001,0x0006); // IDMON=0, INVON=1, NORON=1, PTLON=0 Set_LCD_8B_REG(0x0016,0x0048); // MY=0, MX=0, MV=0, ML=1, BGR=0, TEON=0 Set_LCD_8B_REG(0x0023,0x0095); Set_LCD_8B_REG(0x0024,0x0095); Set_LCD_8B_REG(0x0025,0x00FF); // N_DC=1001 0101 // PI_DC=1001 0101 // I_DC=1111 1111 Set_LCD_8B_REG(0x0027,0x0002); Set_LCD_8B_REG(0x0028,0x0002); Set_LCD_8B_REG(0x0029,0x0002); Set_LCD_8B_REG(0x002A,0x0002); Set_LCD_8B_REG(0x002C,0x0002); Set_LCD_8B_REG(0x002D,0x0002); // N_BP=0000 0010 // N_FP=0000 0010 // PI_BP=0000 0010 // PI_FP=0000 0010 // I_BP=0000 0010 // I_FP=0000 0010 Set_LCD_8B_REG(0x003A,0x0001); Set_LCD_8B_REG(0x003B,0x0000); Set_LCD_8B_REG(0x003C,0x00F0); Set_LCD_8B_REG(0x003D,0x0000); DelayX1ms(20); // N_RTN=0000, N_NW=001 // PI_RTN=0000, PI_NW=000 // I_RTN=1111, I_NW=000 // DIV=00 Set_LCD_8B_REG(0x0035,0x0038); // EQS=38h Set_LCD_8B_REG(0x0036,0x0078); // EQP=78h Himax Confidential -P.50- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver Set_LCD_8B_REG(0x003E,0x0038); // SON=38h APPLICATION NOTE V01 Set_LCD_8B_REG(0x0040,0x000F); // GDON=0Fh Set_LCD_8B_REG(0x0041,0x00F0); // GDOFF // Power Supply Setting Set_LCD_8B_REG(0x0019,0x0049); Set_LCD_8B_REG(0x0093,0x000F); DelayX1ms(10); // CADJ=0100, CUADJ=100(FR:60Hz), OSD_EN=1 // RADJ=1111, 100% Set_LCD_8B_REG(0x0020,0x0040); Set_LCD_8B_REG(0x001D,0x0007); Set_LCD_8B_REG(0x001E,0x0000); Set_LCD_8B_REG(0x001F,0x0004); // BT=0100 // VC1=111 // VC3=000 // VRH=0100 // VCOM Setting for CMO 2.4” Panel Set_LCD_8B_REG(0x0044,0x0040); Set_LCD_8B_REG(0x0045,0x0012); DelayX1ms(10); // VCM=100 0000 // VDV=1 0001 Set_LCD_8B_REG(0x001C,0x0004); DelayX1ms(20); Set_LCD_8B_REG(0x001B,0x0018); DelayX1ms(40); // AP=100 // GASENB=0, PON=1, DK=1, XDK=0, VLCD_TRI=0, STB=0 Set_LCD_8B_REG(0x001B,0x0010); // GASENB=0, PON=1, DK=0, XDK=0, VLCD_TRI=0, STB=0 DelayX1ms(40); Set_LCD_8B_REG(0x0043,0x0080); //Set VCOMG=1 DelayX1ms(100); // Display ON Setting Set_LCD_8B_REG(0x0090,0x007F); // SAP=0111 1111 Set_LCD_8B_REG(0x0026,0x0004); DelayX1ms(40); Set_LCD_8B_REG(0x0026,0x0024); Set_LCD_8B_REG(0x0026,0x002C); DelayX1ms(40); //GON=0, DTE=0, D=01 //GON=1, DTE=0, D=01 //GON=1, DTE=0, D=11 Set_LCD_8B_REG(0x0026,0x003C); //GON=1, DTE=1, D=11 // Internal register setting Set_LCD_8B_REG(0x0057,0x0002); Set_LCD_8B_REG(0x0095,0x0001); Set_LCD_8B_REG(0x0057,0x0000); //Test_Mode Enable // Set Display clock and Pumping clock to synchronize // Test_Mode Disable } Himax Confidential -P.51- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 7.6.2.3 The reference setting of CMO 2.8” Panel APPLICATION NOTE V01 void HX8347A_Init_CMO28(void) { RESET(); DelayX1ms(150); // After Inter-MicroP Program (load OTP) // Gamma for CMO 2.8 Set_LCD_8B_REG(0x46,0x95); Set_LCD_8B_REG(0x47,0x51); Set_LCD_8B_REG(0x48,0x00); Set_LCD_8B_REG(0x49,0x36); Set_LCD_8B_REG(0x4A,0x11); Set_LCD_8B_REG(0x4B,0x66); Set_LCD_8B_REG(0x4C,0x14); Set_LCD_8B_REG(0x4D,0x77); Set_LCD_8B_REG(0x4E,0x13); Set_LCD_8B_REG(0x4F,0x4C); Set_LCD_8B_REG(0x50,0x46); Set_LCD_8B_REG(0x51,0x46); //240x320 window setting Set_LCD_8B_REG(0x02,0x00); Set_LCD_8B_REG(0x03,0x00); Set_LCD_8B_REG(0x04,0x00); Set_LCD_8B_REG(0x05,0xEF); Set_LCD_8B_REG(0x06,0x00); Set_LCD_8B_REG(0x07,0x00); Set_LCD_8B_REG(0x08,0x01); Set_LCD_8B_REG(0x09,0x3F); // Column address start2 // Column address start1 // Column address end2 // Column address end1 // Row address start2 // Row address start1 // Row address end2 // Row address end1 // Display Setting Set_LCD_8B_REG(0x01,0x06); // IDMON=0, INVON=1, NORON=1, PTLON=0 Set_LCD_8B_REG(0x16,0x48); // MY=0, MX=0, MV=0, ML=1, BGR=0, TEON=0 Set_LCD_8B_REG(0x23,0x95); Set_LCD_8B_REG(0x24,0x95); Set_LCD_8B_REG(0x25,0xFF); // N_DC=1001 0101 // P_DC=1001 0101 // I_DC=1111 1111 Set_LCD_8B_REG(0x27,0x06); Set_LCD_8B_REG(0x28,0x06); Set_LCD_8B_REG(0x29,0x06); Set_LCD_8B_REG(0x2A,0x06); Set_LCD_8B_REG(0x2C,0x06); Set_LCD_8B_REG(0x2D,0x06); // N_BP=0000 0110 // N_FP=0000 0110 // P_BP=0000 0110 // P_FP=0000 0110 // I_BP=0000 0110 // I_FP=0000 0110 Set_LCD_8B_REG(0x3A,0x01); Set_LCD_8B_REG(0x3B,0x00); Set_LCD_8B_REG(0x3C,0xF0); Set_LCD_8B_REG(0x3D,0x00); DelayX1ms(20); // N_RTN=0000, N_NW=001 // P_RTN=0000, P_NW=000 // I_RTN=1111, I_NW=000 // DIV=00 Set_LCD_8B_REG(0x35,0x38); Set_LCD_8B_REG(0x36,0x78); // EQS=38h // EQP=78h Himax Confidential -P.52- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver Set_LCD_8B_REG(0x3E,0x38); // SON=38h APPLICATION NOTE V01 Set_LCD_8B_REG(0x40,0x0F); Set_LCD_8B_REG(0x41,0xF0); // GDON=0Fh // GDOFF // Power Supply Setting Set_LCD_8B_REG(0x19,0x49); Set_LCD_8B_REG(0x93,0x0C); DelayX1ms(10); // OSCADJ=10 0000, OSD_EN=1 //60Hz // RADJ=1100 Set_LCD_8B_REG(0x20,0x40); // BT=0100 Set_LCD_8B_REG(0x1D,0x07); Set_LCD_8B_REG(0x1E,0x00); Set_LCD_8B_REG(0x1F,0x04); // VC1=111 // VC3=000 // VRH=0100 // VCOM Setting for CMO 2.8” Panel Set_LCD_8B_REG(0x44,0x4D); Set_LCD_8B_REG(0x45,0x11); DelayX1ms(10); // VCM=101 0000 // VDV=1 0001 Set_LCD_8B_REG(0x1C,0x04); DelayX1ms(20); // AP=100 Set_LCD_8B_REG(0x1B,0x18); DelayX1ms(40); // GASENB=0, PON=1, DK=1, XDK=0, DDVDH_TRI=0, STB=0 Set_LCD_8B_REG(0x1B,0x10); DelayX1ms(40); // GASENB=0, PON=1, DK=0, XDK=0, DDVDH_TRI=0, STB=0 Set_LCD_8B_REG(0x43,0x80); DelayX1ms(100); //Set VCOMG=1 // Display ON Setting Set_LCD_8B_REG(0x90,0x7F); // SAP=0111 1111 Set_LCD_8B_REG(0x26,0x04); DelayX1ms(40); Set_LCD_8B_REG(0x26,0x24); Set_LCD_8B_REG(0x26,0x2C); DelayX1ms(40); //GON=0, DTE=0, D=01 //GON=1, DTE=0, D=01 //GON=1, DTE=0, D=11 Set_LCD_8B_REG(0x26,0x3C); //GON=1, DTE=1, D=11 // Internal register setting Set_LCD_8B_REG(0x0057,0x0002); Set_LCD_8B_REG(0x0095,0x0001); Set_LCD_8B_REG(0x0057,0x0000); //Test_Mode Enable // Set Display clock and Pumping clock to synchronize // Test_Mode Disable } Himax Confidential -P.53- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 7.6.3 The reference setting of into Standby mode for Register-Content Interface Mode void HX8347A_STB_INTO (void) { // Display Off Set_LCD_8B_REG(0x0026,0x0038); DelayX1ms (40); Set_LCD_8B_REG(0x0026,0x0028); DelayX1ms (40); Set_LCD_8B_REG(0x0026,0x0000); //GON=1, DTE=1, D=10 //GON=1, DTE=0, D=10 //GON=0, DTE=0, D=00 // Power Off Set_LCD_8B_REG(0x0043,0x0000); DelayX1ms(10); Set_LCD_8B_REG(0x001B,0x0000); DelayX1ms(10); Set_LCD_8B_REG(0x001B,0x0008); DelayX1ms(10); Set_LCD_8B_REG(0x001C,0x0000); DelayX1ms(10); Set_LCD_8B_REG(0x0090,0x0000); DelayX1ms(10); // VCOMG=0 // GASENB=0, PON=0, DK=0, XDK=0, // VLCD_TRI=0, STB=0 // GASENB=0, PON=0, DK=1, XDK=0, // VLCD_TRI=0, STB=0 // AP=000 // SAP=00000000 // Into STB mode Set_LCD_8B_REG(0x001B,00009); DelayX1ms(10); // GASSENB=0, PON=0, DK=1, XDK=0, // VLCD_TRI=0, STB=1 // Stop Oscillation Set_LCD_8B_REG(0x0019,0x0048); // CADJ=0100, CUADJ=100, OSD_EN=0 } Himax Confidential -P.54- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01 7.6.4 The reference setting of exit Standby mode for Register-Content Interface Mode void HX8347A_STB_EXIT (void) { // Start Oscillation Set_LCD_8B_REG(0x0019,0x0049); // OSCADJ=100 010(FR:60Hz), OSD_EN=1 DelayX1ms(10); // Exit STB mode Set_LCD_8B_REG(0x001B,0x0008); // NIDSENB=0, PON=0, DK=1, XDK=0, // VLCD_TRI=0, STB=0 // Power Supply Setting Set_LCD_8B_REG(0x0020,0x0040); Set_LCD_8B_REG(0x001D,0x0007); Set_LCD_8B_REG(0x001E,0x0000); Set_LCD_8B_REG(0x001F,0x0003); Set_LCD_8B_REG(0x0044,0x0020); Set_LCD_8B_REG(0x0045,0x000E); DelayX1ms(10); Set_LCD_8B_REG(0x001C,0x0004); DelayX1ms(20); Set_LCD_8B_REG(0x001B,0x0018); DelayX1ms(40); Set_LCD_8B_REG(0x001B,0x0010); DelayX1ms(40); Set_LCD_8B_REG(0x0043,0x0080); DelayX1ms(100); // BT=0100 // VC1=111 // VC3=000 // VRH=0011 // VCM=010 0000 // VDV=0 1110 // AP=100 // NIDSENB=0, PON=1, DK=1, XDK=0, // VLCD_TRI=0, STB=0 // NIDSENB=0, PON=1, DK=0, XDK=0, // VLCD_TRI=1, STB=0 // VCOMG=1 // Display ON Setting Set_LCD_8B_REG(0x0090,0x007F); // SAP=01111111 DelayX1ms(40); Set_LCD_8B_REG(0x0026,0x0004); DelayX1ms(40); Set_LCD_8B_REG(0x0026,0x0024); Set_LCD_8B_REG(0x0026,0x002C); DelayX1ms(40); //GON=0, DTE=0, D=01 //GON=1, DTE=0, D=01 //GON=1, DTE=0, D=11 Set_LCD_8B_REG(0x0026,0x003C); //GON=1, DTE=1, D=11 } Himax Confidential -P.55- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007 HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver 8. Revision History APPLICATION NOTE V01 Version 01 Date 2007/04/24 2007/05/22 2007/06/05 2007/06/28 2007/07/25 2007/07/26 2007/08/16 2007/08/21 2007/09/06 Description of changes New setup 1. Update Table 7.7.(P.33) 2. Update 5. HX8347-A Reference FPC circuit for CMO 3.2” LCD Panel.(P.13~P.16) 1. Update Initial code for Normal Display in Register-Content Interface mode.(P.48~P.49) 2. Add Normal Display Initial code for CMO 2.4” LCD in Register-Content Interface mode.(P.50~P51) 3. Modify Pin name in Figure 7.8~7.15 and. Figure 7.18~7.21.(P.21~P.40) 4. Modify SPI read GRAM timing.(P.33~P.34) 1. Update Initial code for Normal Display in Register-Content Interface mode. (Add VDC_SEL setting). (P.48~P.53) 2. Modify IOVCC input voltage range from 3.0V to 3.3V. (P.13~P.16) 1. Update Initial code for ESD protection in Register-Content Interface mode.(P.48~P.53) 1. Update Initial code. (P.48~P.53) 1. Add Normal Display Initial code for CMO 2.8” LCD in Register-Content Interface mode.(P.52~P.53) 2. Add Register R95h command for setting Display clock and Pumping clock to synchronize(P.48~P.53) 1. Update Reference FPC circuit.(P.13~P.16) 1. Update Initial code.(P.48~P.53) Himax Confidential -P.56- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007

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