首页资源分类IC设计及制造 > Datasheet.hk_icl7660s

Datasheet.hk_icl7660s

已有 445176个资源

下载专区

上传者其他资源

    文档信息举报收藏

    标    签:7660s

    分    享:

    文档简介

    IC 资料, 共电子电路设计开发人员查找及使用

    文档预览

    ® Data Sheet January 2004 ICL7660S FN3179.3 Super Voltage Converter The ICL7660S Super Voltage Converter is a monolithic CMOS voltage conversion IC that guarantees significant performance advantages over other similar devices. It is a direct replacement for the industry standard ICL7660 offering an extended operating supply voltage range up to 12V, with lower supply current. No external diode is needed for the ICL7660S. In addition, a Frequency Boost pin has been incorporated to enable the user to achieve lower output impedance despite using smaller capacitors. All improvements are highlighted in the Electrical Specifications section. Critical parameters are guaranteed over the entire commercial, industrial and military temperature ranges. The ICL7660S performs supply voltage conversion from positive to negative for an input range of 1.5V to 12V, resulting in complementary output voltages of -1.5V to -12V. Only 2 non-critical external capacitors are needed for the charge pump and charge reservoir functions. The ICL7660S can be connected to function as a voltage doubler and will generate up to 22.8V with a 12V input. It can also be used as a voltage multiplier or voltage divider. The chip contains a series DC power supply regulator, RC oscillator, voltage level translator, and four output power MOS switches. The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 5.0V. This frequency can be lowered by the addition of an external capacitor to the “OSC” terminal, or the oscillator may be over-driven by an external clock. The “LV” terminal may be tied to GND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (3.5V to 12V), the LV pin is left floating to prevent device latchup. Pinouts ICL7660S (PDIP, SOIC) TOP VIEW ICL7660S (CAN) TOP VIEW BOOST 1 CAP+ 2 GND 3 CAP- 4 8 V+ 7 OSC 6 LV 5 VOUT V+ (AND CASE) 8 BOOST 1 7 OSC CAP+ 2 6 LV GND 3 5 VOUT 4 CAP- Features • Guaranteed Lower Max Supply Current for All Temperature Ranges • Wide Operating Voltage Range 1.5V to 12V • 100% Tested at 3V • No External Diode Over Full Temperature and Voltage Range • Boost Pin (Pin 1) for Higher Switching Frequency • Guaranteed Minimum Power Efficiency of 96% • Improved Minimum Open Circuit Voltage Conversion Efficiency of 99% • Improved SCR Latchup Protection • Simple Conversion of +5V Logic Supply to ±5V Supplies • Simple Voltage Multiplication VOUT = (-)nVIN • Easy to Use - Requires Only 2 External Non-Critical Passive Components • Improved Direct Replacement for Industry Standard ICL7660 and Other Second Source Devices • Available in Lead Free Applications • Simple Conversion of +5V to ±5V Supplies • Voltage Multiplication VOUT = ±nVIN • Negative Supplies for Data Acquisition Systems and Instrumentation • RS232 Power Supplies • Supply Splitter, VOUT = ±VS/2 Ordering Information PART # TEMP. RANGE (oC) PACKAGE PKG. DWG. # ICL7660SCBA 0 to 70 8 Ld SOIC (N) M8.15 ICL7660SCPA 0 to 70 8 Ld PDIP E8.3 ICL7660SIBA -40 to 85 8 Ld SOIC (N) M8.15 ICL7660SIBAZ (Note 1) -40 to 85 8 Ld SOIC (N) (lead-free) M8.15 ICL7660SIBAZT -40 to 85 8 Ld SOIC (N) M8.15 (Note 1) (lead-free) Tape and Reel ICL7660SIPA -40 to 85 8 Ld PDIP E8.3 ICL7660SMTV -55 to 125 8 Pin Metal Can (Note 2) T8.C NOTES: 1. Intersil Lead Free products employ special lead free material sets; molding compounds / die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and lead free soldering operations. Intersil Lead Free products are MSL classified at lead free peak reflow temperatures that meet or exceed the lead free requirements of IPC/JEDEC J Std-020B. 2. Add /883B to part number if 883B processing is required. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL7660S Absolute Maximum Ratings Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V LV and OSC Input Voltage (Note 3) V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ -5.5V to V+ +0.3V Current into LV (Note 3) V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20µA Output Short Duration VSUPPLY ≤ 5.5V. . . . . . . . Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous -65oC to 150oC Thermal Information Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W) PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . 110 N/A Plastic SOIC. . . . . . . . . . . . . . . . . . . . . 160 N/A Metal Can. . . . . . . . . . . . . . . . . . . . . . . 160 70 Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range ICL7660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC ICL7660SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC ICL7660SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to “power up” of ICL7660S. 4. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Supply Current (Note 7) Supply Voltage Range - High (Note 8) V+ = 5V, TA = 25oC, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX I+ RL = ∞, 25oC 0oC < TA < +70oC -40oC < TA < 85oC -55oC < TA < 125oC - 80 160 - - 180 - - 180 - - 200 V+H RL = 10K, LV Open, TMIN < TA < TMAX 3.0 - 12 Supply Voltage Range - Low V+L RL = 10K, LV to GND, TMIN < TA < TMAX 1.5 - 3.5 Output Source Resistance ROUT IOUT = 20mA IOUT = 20mA, 0oC < TA < 70oC IOUT = 20mA, -25oC < TA < 85oC IOUT = 20mA, -55oC < TA < 125oC - 60 100 - - 120 - - 120 - - 150 0IOoUCT<=T3Am1000pF) the values of C1 and C2 should be increased to 100µF. FIGURE 12. ICL7660S TEST CIRCUIT In the ICL7660S, the 4 switches of Figure 13 are MOS power switches; S1 is a P-Channel devices and S2, S3 and S4 are N-Channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S3 and S4 must always remain reverse biased with respect to their sources, but not so much as to degrade their “ON” resistances. In addition, at circuit start up, and under output short circuit conditions (VOUT = V+), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latchup. This problem is eliminated in the ICL7660S by a logic network which senses the output voltage (VOUT) together with the level translators, and switches the substrates of S3 and S4 to the correct level to maintain necessary reverse bias. The voltage regulator portion of the ICL7660S is an integral part of the anti-latchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation “LV” pin should be connected to GND, disabling the regulator. For supply voltages greater than 3.5V the LV terminal must be left open to insure latchup proof operation, and prevent device damage. Theoretical Power Efficiency Considerations In theory a voltage converter can approach 100% efficiency if certain conditions are met: 1. The drive circuitry consumes minimal power. 2. The output switches have extremely low ON resistance and virtually no offset. 3. The impedance of the pump and reservoir capacitors are negligible at the pump frequency. 5 ICL7660S The ICL7660S approaches these conditions for negative voltage conversion if large values of C1 and C2 are used. ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined by: E = 1/2C1 (V12 - V22) where V1 and V2 are the voltages on C1 during the pump and transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (refer to Figure 13) compared to the value of RL, there will be substantial difference in the voltages V1 and V2. Therefore it is not only desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation. 8 S1 2 S2 VIN C1 3 3 S3 S4 4 C2 5 VOUT = -VIN 7 FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER Do’s and Don’ts 1. Do not exceed maximum supply voltages. 2. Do not connect LV terminal to GND for supply voltage greater than 3.5V. 3. Do not short circuit the output to V+ supply for supply voltages above 5.5V for extended periods, however, transient conditions including start-up are okay. 4. When using polarized capacitors, the + terminal of C1 must be connected to pin 2 of the ICL7660S and the + terminal of C2 must be connected to GND. 5. If the voltage supply driving the ICL7660S has a large source impedance (25Ω - 30Ω), then a 2.2µF capacitor from pin 8 to ground may be required to limit rate of rise of input voltage to less than 2V/µs. 6. User should insure that the output (pin 5) does not go more positive than GND (pin 3). Device latch up will occur under these conditions. A 1N914 or similar diode placed in parallel with C2 will prevent the device from latching up under these conditions. (Anode pin 5, Cathode pin 3). Typical Applications Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the ICL7660S for generation of negative supply voltages. Figure 14 shows typical connections to provide a negative supply where a positive supply of +1.5V to +12V is available. Keep in mind that pin 6 (LV) is tied to the supply negative (GND) for supply voltage below 3.5V. V+ 10µF + - 1 8 2 ICL7660S 7 3 6 4 5 - 10µF + VOUT = -V+ RO VOUT - V+ + 14A. 14B. FIGURE 14. SIMPLE NEGATIVE CONVERTER AND ITS OUTPUT EQUIVALENT The output characteristics of the circuit in Figure 14 can be approximated by an ideal voltage source in series with a resistance as shown in Figure 14B. The voltage source has a value of -(V+). The output impedance (RO) is a function of the ON resistance of the internal MOS switches (shown in Figure 13), the switching frequency, the value of C1 and C2, and the ESR (equivalent series resistance) of C1 and C2. A good first order approximation for RO is: RO ≅ 2(RSW1 + RSW3 + ESRC1) + 2(RSW2 + RSW4 + ESRC1) + 1 fPUMP x C1 + ESRC2 (fPUMP = fOSC 2 , RSWX = MOSFET switch resistance) Combining the four RSWX terms as RSW, we see that: RO ≅ 2 x RSW + 1 fPUMP x C1 + 4 x ESRC1 + ESRC2Ω RSW, the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance graphs), typically 23Ω at 25oC and 5V. Careful selection of C1 and C2 will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the 1/(fPUMP x C1) component, and low ESR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the 1/(fPUMP x C1) term, but may have the side effect of a net 6 ICL7660S increase in output impedance when C1 > 10µF and is not long enough to fully charge the capacitors every cycle. In a typical application where fOSC = 10kHz and C = C1 = C2 = 10µF: 1 RO ≅ 2 x 23 + (5 x 103 x 10 x 10-6) + 4 x ESRC1 + ESRC2 RO ≅ 46 + 20 + 5 x ESRCΩ Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/fPUMP x C1) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10Ω. Output Ripple ESR also affects the ripple voltage seen at the output. The total ripple is determined by 2 voltages, A and B, as shown in Figure 15. Segment A is the voltage drop across the ESR of C2 at the instant it goes from being charged by C1 (current flowing into C2) to being discharged through the load (current flowing out of C2). The magnitude of this current change is 2 x IOUT, hence the total drop is 2 x IOUT x ESRC2V. Segment B is the voltage change across C2 during time t2, the half of the cycle when C2 supplies current the load. The drop at B is IOUT x t2/C2V. The peak-to-peak ripple voltage is the sum of these voltage drops: V   RIPPLE ≅    ---------------------1---------------------2 × fPUMP × C2 + 2 ESRC2 × IOU  T  Again, a low ESR capacitor will result in a higher performance output. Paralleling Devices Any number of ICL7660S voltage converters may be paralleled to reduce output resistance. The reservoir capacitor, C2, serves all devices while each device requires its own pump capacitor, C1. The resultant output resistance would be approximately: ROUT = ROUT (of ICL7660S) n (number of devices) Cascading Devices The ICL7660S may be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. The output voltage is defined by: VOUT = -n(VIN), where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660S ROUT values. Changing the ICL7660S Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to alter the oscillator frequency. This can be achieved simply by one of several methods described below. By connecting the Boost Pin (Pin 1) to V+, the oscillator charge and discharge current is increased and, hence, the oscillator frequency is increased by approximately 31/2 times. The result is a decrease in the output impedance and ripple. This is of major importance for surface mount applications where capacitor size and cost are critical. Smaller capacitors, e.g. 0.1µF, can be used in conjunction with the Boost Pin in order to achieve similar output currents compared to the device free running with C1 = C2 = 10µF or 100µF. (Refer to graph of Output Source Resistance as a Function of Oscillator Frequency). Increasing the oscillator frequency can also be achieved by overdriving the oscillator from an external clock, as shown in Figure 18. In order to prevent device latchup, a 1kΩ resistor must be used in series with the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the addition of a 10kΩ pullup resistor to V+ supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be 1/2 of the clock frequency. Output transitions occur on the positive going edge of the clock. + 10µF- V+ V+ 1 8 2 ICL7660S 7 3 6 4 5 1kΩ CMOS GATE - VOUT + 10µF FIGURE 15. EXTERNAL CLOCKING It is also possible to increase the conversion efficiency of the ICL7660S at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is shown in Figure 19. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C1) and reservoir (C2) capacitors; this is overcome by increasing the values of C1 and C2 by the same factor that the frequency has been reduced. For example, the addition of a 100pF capacitor between pin 7 (OSC and V+ will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate corresponding increase in the value of C1 and C2 (from 10µF to 100µF). 7 ICL7660S C1 + - V+ 1 8 2 ICL7660S 7 3 6 4 5 COSC - VOUT + C2 FIGURE 16. LOWERING OSCILLATOR FREQUENCY Positive Voltage Doubling The ICL7660S may be employed to achieve positive voltage doubling using the circuit shown in Figure 20. In this application, the pump inverter switches of the ICL7660S are used to charge C1 to a voltage level of V+ -VF (where V+ is the supply voltage and VF is the forward voltage on C1 plus the supply voltage (V+) is applied through diode D2 to capacitor C2. The voltage thus created on C2 becomes (2V+) - (2VF) or twice the supply voltage minus the combined forward voltage drops of diodes D1 and D2. The source impedance of the output (VOUT) will depend on the output current, but for V+ = 5V and an output current of 10mA it will be approximately 60Ω. V+ 1 8 2 ICL7660S 7 3 6 4 5 D1 D2 + - C1 VOUT = (2V+) - (2VF) + - C2 NOTE: D1 and D2 can be any suitable diode. FIGURE 17. POSITIVE VOLTAGE DOUBLER Combined Negative Voltage Conversion and Positive Supply Doubling Figure 21 combines the functions shown in Figure 14 and Figure 20 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for example, suitable for generating +9V and -5V from an existing +5V supply. In this instance capacitors C1 and C3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors C2 and C4 are pump and reservoir respectively for the doubled positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin 2 of the device. + C1 - V+ 1 8 2 ICL7660S 7 D1 3 6 4 5 -+ D2 C2 VOUT = -VIN - C3 + VOUT = (2V+) (VFD1) - (VFD2) + - C4 FIGURE 18. COMBINED NEGATIVE VOLTAGE CONVERTER AND POSITIVE DOUBLER Voltage Splitting The bidirectional characteristics can also be used to split a high supply in half, as shown in Figure 22. The combined load will be evenly shared between the two sides, and a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure 17, +15V can be converted (via +7.5, and -7.5 to a nominal -15V, although with rather high series output resistance (∼250Ω). V+ + RL1 50µF - 1 8 VOUT = V+ - 2 V- + 50µF - 2 ICL7660S 7 3 6 RL2 4 5 + 50µF - V- FIGURE 19. SPLITTING A SUPPLY IN HALF Regulated Negative Voltage Supply In Some cases, the output impedance of the ICL7660S can be a problem, particularly if the load current varies substantially. The circuit of Figure 23 can be used to overcome this by controlling the input voltage, via an ICL7611 low-power CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the ICL7660S’s output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the ICL7660S, while maintaining adequate feedback. An increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than 5Ω to a load of 10mA. 8 ICL7660S +8V 56k 50k 100k 50k +8V - ICL7611 + ICL8069 + 100µF - 100Ω - 10µF + 1 8 2 7 ICL7660S 3 6 4 5 VOUT 800k 250k VOLTAGE ADJUST - + 100µF FIGURE 20. REGULATING THE OUTPUT VOLTAGE +5V LOGIC SUPPLY TTL DATA INPUT + 10µF - 16 4 15 1 8 2 7 ICL7660S 3 6 4 5 10µF - + 12 11 1 3 IH5142 13 14 RS232 + 5V DATA OUTPUT -5V FIGURE 21. RS232 LEVELS FROM A SINGLE 5V SUPPLY Other Applications Further information on the operation and use of the ICL7660S may be found in AN051 “Principles and Applications of the ICL7660 CMOS Voltage Converter”. 9 ICL7660S Dual-In-Line Plastic Packages (PDIP) INDEX AREA N 12 3 E1 N/2 -B- -A- D E BASE PLANE SEATING PLANE -C- A2 A L CL D1 D1 A1 eA B1 e B eC C 0.010 (0.25) M C A B S eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N 8 8 9 Rev. 0 12/93 10 ICL7660S Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B- 0.25(0.010) M B M 123 -AD SEATING PLANE A L h x 45o -C- µα e A1 C B 0.10(0.004) 0.25(0.010) M C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N 8 8 7 α 0o 8o 0o 8o - Rev. 0 12/93 11 ICL7660S Metal Can Packages (Can) A ØD ØD1 REFERENCE PLANE L L2 L1 A A Øe e1 ØD2 k1 2 N 1 Øb1 β α F Øb k CL Q BASE AND SEATING PLANE BASE METAL LEAD FINISH Øb1 Øb2 SECTION A-A NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. 3. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) from α, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. T8.C MIL-STD-1835 MACY1-X8 (A1) 8 LEAD METAL CAN PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.185 4.19 4.70 - Øb 0.016 0.019 0.41 0.48 1 Øb1 0.016 0.021 0.41 0.53 1 Øb2 0.016 0.024 0.41 0.61 - ØD 0.335 0.375 8.51 9.40 - ØD1 0.305 0.335 7.75 8.51 - ØD2 0.110 0.160 2.79 4.06 - e 0.200 BSC 5.08 BSC - e1 0.100 BSC 2.54 BSC - F - 0.040 - 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 L 0.500 0.750 12.70 19.05 1 L1 - 0.050 - 1.27 1 L2 0.250 - 6.35 - 1 Q 0.010 0.045 0.25 1.14 - α 45o BSC 45o BSC 3 β 45o BSC 45o BSC 3 N 8 8 4 Rev. 0 5/18/94 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12

    相关帖子

    逛论坛

      Top_arrow
      回到顶部
      EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。