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SMIC_0.18mm工艺 Design Rule

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标签: IC设计

IC设计,Integrated Circuit Design,或称为集成电路设计,是电子工程学和计算机工程学的一个学科,其主要内容是运用专业的逻辑和电路设计技术设计集成电路。

SMIC0.18um

IC设计,Integrated Circuit Design,或称为集成电路设计,是电子工程学和计算机工程学的一个学科,其主要内容是运用专业的逻辑和电路设计技术设计集成电路。

cadence

铿腾电子科技有限公司(Cadence Design Systems, Inc; NASDAQ:CDNS)是一个专门从事电子设计自动化(EDA)的软件公司,由SDA Systems和ECAD两家公司于1988年兼并而成。是全球最大的电子设计技术(Electronic Design Technologies)、程序方案服务和设计服务供应商。其解决方案旨在提升和监控半导体、计算机系统、网络工程和电信设备、消费电子产品以及其它各类型电子产品的设计。产品涵盖了电子设计的整个流程,包括系统级设计,功能验证,IC综合及布局布线,模拟、混合信号及射频IC设计,全定制集成电路设计,IC物理验证,PCB设计和硬件仿真建模等。 其总部位于美国加州圣何塞(San Jose),在全球各地设有销售办事处、设计及研发中心。

SMIC_0.18mm工艺 Design Rule设计文档

文档内容节选

Semiconductor Manufacturing International Corporation Doc No TDLO18DR2001 Doc Title 018m LOGIC 1P6M Salicide 18V33V Design Rules DocRev 4P Tech Dev Rev20 Page No 153 Document Level For Engineering Quality Document工程暨品质文件专用 Level 1 Manual Level 2 ProcedureSPECReport Level 3 Operation Instruction Security Level Security 1 SMIC Confidential Security 2 SMIC Restricted Security 3 SMIC Internal Document Chang......

Semiconductor Manufacturing International Corporation Doc. No.: TD-LO18-DR-2001 Doc. Title: 0.18µm LOGIC 1P6M Salicide 1.8V/3.3V Design Rules Doc.Rev: 4P Tech Dev Rev:2.0 Page No.: 1/53 Document Level: (For Engineering & Quality Document/工程暨品质文件专用)  Level 1 - Manual  Level 2 – Procedure/SPEC/Report  Level 3 - Operation Instruction Security Level:  Security 1 - SMIC Confidential  Security 2 - SMIC Restricted  Security 3 - SMIC Internal Document Change History Author Change Description Tech Dev. Effective Date Doc. Rev. 0T Rev. 2001-12-24 Allen Fan 范忠黎 Initiate 1T 2002-3-7 Feng Guang Tao In this new version 1T, the terminology is uniformed. And a number of verbal description errors and figure errors in previous version are also corrected. 1.1T 1.0 2003-06-10 JianHua_Ju Add Technology Develop Revision:1.0 2003-12-09 Stella_Huang 1) Delete ESD2 layer 2T 2.0 3P 4P 2.0 2.0 2) Add mask layer digitized area description 3) Add nwell resistor rule description 4) Add native device rule 5) Modify GT.10, GT.11, GT.12 6) Add GT.14 rule 7) Add GT density recommendation. 8) Add poly resistor rule recommendation 1.8g 9) Add NLL.14, PLL.14, NLH.14, PLH.14 rule 10) Modify metal dummy rule description M1.8, Mn.8, MT.7 Add Mn.9 rule to prevent BEOL crack issue Replace Fab/E1 with PIE for org. name change 2006-01-25 Matthew Shen 2007-07-31 Xiaoliang Tang Add guideline for polyimide layout minima, add the related RULE NO.; DESCRIPTION; LAYOUT GUIDELINE The information contained herein is the exclusive property of SMIC, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of SMIC. According to: Document Control Procedure; Attachment No.: QR-QUSM-02-2001-023; Rev.:0 Semiconductor Manufacturing International Corporation Doc.Rev: 4P Tech Dev Rev:2.0 Page No.: 2/53 Doc. No.: TD-LO18-DR-2001 Doc. Title: 0.18µm LOGIC 1P6M Salicide 1.8V/3.3V Design Rules 1.Title: 0.18µm LOGIC 1P6M Salicide 1.8V/3.3V Design Rules. 2.Purpose: To provide SMIC 0.18µm layout design rules for the customers use. 3.Scope: All SMIC Fabs. 4.Nomenclature: N/A 5.Reference: N/A 6.Responsibility: TD is responsible for this design rule maintenance before the technology is transferred to FAB; PIE is responsible for this design rule maintenance after the technology is transferred to FAB. 7.Subject Content: The information contained herein is the exclusive property of SMIC, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of SMIC. According to: Document Control Procedure; Attachment No.: QR-QUSM-02-2001-023; Rev.:0 Semiconductor Manufacturing International Corporation Doc. No.: TD-LO18-DR-2001 Doc. Title: 0.18µm LOGIC 1P6M Salicide 1.8V/3.3V Design Rules 0. USER GUIDE Content Doc.Rev: 4P Tech Dev Rev:2.0 Page No.: 3/53 Part I Description of SMIC Mask Layers Part II Suggestion for the Optimization of Circuit Design 1.0 LAYOUT RULE DESCRIPTION 1.1 Definition of the Layout Layers 1.2 N-Well 1.3 N-Well Resistor 1.4 NN (native device) rule 1.5 AA – Active Area 1.6 DG – Dual Gate 1.7 Poly 1.8 Poly Resistor 1.9 NLL – 1.8V NLDD Implantation 1.10 PLL – 1.8V PLDD Implantation 1.11 NLH – 3.3V NLDD Implantation 1.12 PLH – 3.3V PLDD Implantation 1.13 SN – S/D Implantation 1.14 SP – S/D Implantation 1.15 SAB – Salicide Block 1.16 CT – Contact 1.17 Metal 1 1.18 Via 1 1.19 Metal n (n=2,3,4,5) 1.20 Via n (n=2,3,4) 1.21 Via 5 1.22 Top Metal—Metal 6 2.0 METAL FUSE, ALIGNMENT MARK FOR LASER REPAIR AND STRESS RELIEF 2.1 Metal Fuse Rules 2.2 Alignment Mark for Laser Repairing 2.3 Guideline for polyimide layout minima The information contained herein is the exclusive property of SMIC, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of SMIC. According to: Document Control Procedure; Attachment No.: QR-QUSM-02-2001-023; Rev.:0 Semiconductor Manufacturing International Corporation Doc. No.: TD-LO18-DR-2001 Doc. Title: 0.18µm LOGIC 1P6M Salicide 1.8V/3.3V Design Rules Doc.Rev: 4P Tech Dev Rev:2.0 Page No.: 4/53 SMIC Key Process Sequence and Layer Digitized Area Digitized Area (Dark/Clear) 0 USER GUIDE Part I Description of SMIC Mask Layer Part II Suggestions for the Optimization of Circuit Design Part I No Layer Name AA 1 AR 2 KV 3 NW 4 PW 5 DG 6 GT 7 PLH 8 NLH 9 PLL 10 NLL 11 SP 12 SN 13 ESD1 14 SAB 15 16 CT 17 M1 18 V1 19 M2 20 V2 21 M3 22 V3 23 M4 24 V4 25 M5 26 V5 27 M6 28 PA PI 29 Pattern Description Active Area Reverse Active Area Alignment mark clear-out N-Well N-Well Dual Gate (thick oxide) Poly gate PMOS LDD implant for 3.3V NMOS LDD implant for 3.3V PMOS LDD implant for 1.8V NMOS LDD implant for 1.8V P+ implant N+ implant ESD implant for Boron (B) Salicide block area Contact Metal-1 VIA-1 Metal-2 VIA-2 Metal-3 VIA-3 Metal-4 VIA-4 Metal-5 VIA-5 Metal-6 Passivation/Pad Polyimide D C C C D D D C C C C C C C D C D C D C D C D C D C D C D The information contained herein is the exclusive property of SMIC, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of SMIC. According to: Document Control Procedure; Attachment No.: QR-QUSM-02-2001-023; Rev.:0 Semiconductor Manufacturing International Corporation Doc. No.: TD-LO18-DR-2001 Doc. Title: 0.18µm LOGIC 1P6M Salicide 1.8V/3.3V Design Rules Doc.Rev: 4P Tech Dev Rev:2.0 Page No.: 5/53 Part II Suggestion for the optimization of circuit design 1. Front-end concerns A. AA: add dummy patterns for isolated small structures or open areas around AA. B. Poly: add dummy poly patterns at the edge of isolated structures especially when the pattern density is less than 14%. C. Follow the antenna rules to ensure gate oxide reliability. D. For the leakage concern, avoid 90 degree bent poly designs, which should be replaced by 45 degree bent poly on AA with shortest length. E. Avoid island pattern designs for implantation layers. 2. Back-end concerns A. Add dog-bone or wider line end designs for metal lines. B. Use redundant contacts or Via’s if possible. C. Avoid small island structures for metal. The information contained herein is the exclusive property of SMIC, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of SMIC. According to: Document Control Procedure; Attachment No.: QR-QUSM-02-2001-023; Rev.:0
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talvikki
感谢分享!
2019-12-11 15:24:35回复
lvfei111
好资源,谢谢分享
2019-05-14 11:00:36回复
adon1314
怎么不能下载, 试了好多次, 我用了一个积分, 可是确一点下载的内容都没有, 一个积分就浪费了, 该怎么下载?
2019-04-19 10:44:42回复
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