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SMIC_0.18mm工艺设计参考手册

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标签: IC设计

IC设计,Integrated Circuit Design,或称为集成电路设计,是电子工程学和计算机工程学的一个学科,其主要内容是运用专业的逻辑和电路设计技术设计集成电路。

cadence

铿腾电子科技有限公司(Cadence Design Systems, Inc; NASDAQ:CDNS)是一个专门从事电子设计自动化(EDA)的软件公司,由SDA Systems和ECAD两家公司于1988年兼并而成。是全球最大的电子设计技术(Electronic Design Technologies)、程序方案服务和设计服务供应商。其解决方案旨在提升和监控半导体、计算机系统、网络工程和电信设备、消费电子产品以及其它各类型电子产品的设计。产品涵盖了电子设计的整个流程,包括系统级设计,功能验证,IC综合及布局布线,模拟、混合信号及射频IC设计,全定制集成电路设计,IC物理验证,PCB设计和硬件仿真建模等。 其总部位于美国加州圣何塞(San Jose),在全球各地设有销售办事处、设计及研发中心。

SMIC_0.18um

铿腾电子科技有限公司(Cadence Design Systems, Inc; NASDAQ:CDNS)是一个专门从事电子设计自动化(EDA)的软件公司,由SDA Systems和ECAD两家公司于1988年兼并而成。是全球最大的电子设计技术(Electronic Design Technologies)、程序方案服务和设计服务供应商。其解决方案旨在提升和监控半导体、计算机系统、网络工程和电信设备、消费电子产品以及其它各类型电子产品的设计。产品涵盖了电子设计的整个流程,包括系统级设计,功能验证,IC综合及布局布线,模拟、混合信号及射频IC设计,全定制集成电路设计,IC物理验证,PCB设计和硬件仿真建模等。 其总部位于美国加州圣何塞(San Jose),在全球各地设有销售办事处、设计及研发中心。

SMIC_0.18mm工艺设计参考手册

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SMIC 018um Reference Manual 28 May 2004 This manual contains information about the SMIC 018um MMRF 1P6M Salicide PDKs 1 Disclaimers Cadence Design Systems shall not be liable for the accuracy of this Process Design Kit The Process Design Kit contained herein is provided by Cadence Design Systems Inc on an AS IS basis without any warranty and Cadence Design Systems Inc has no obligation to support or otherwise maintain the informatio......

SMIC 0.18um Reference Manual 28 May 2004 This manual contains information about the SMIC 0.18um MM/RF 1P6M Salicide PDKs 1 Disclaimers Cadence Design Systems shall not be liable for the accuracy of this Process Design Kit. The Process Design Kit contained herein is provided by Cadence Design Systems, Inc on an "AS IS" basis without any warranty, and Cadence Design Systems, Inc has no obligation to support or otherwise maintain the information. Cadence Design Systems, Inc disclaims any representation that the information does not infringe any intellectual property rights or proprietary rights of any third parties. There are no other warranties given by Cadence Design Systems, Inc, whether express, implied or statutory, including, without limitation, implied warranties of merchantability and fitness for a particular purpose. STATEMENT OF USE This Process Design Kit contains confidential and proprietary information of Cadence Design Systems, Inc. and Semiconductor Manufacturing International Corporation. No part of this information may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any human or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of Cadence and SMIC. This information was prepared for informational purpose and is for use by Cadence Design Systems, Inc’s and SMIC’s customers only. Cadence Design Systems, Inc and SMIC reserve the right to make changes in the information at any time and without notice. 2 Overview The purpose of this document is to describe the technical details of the SMIC 0.18um Process Design Kit (PDK) provided by Cadence Design Systems, Inc. (Cadence). This PDK requires the UNIX environment variable CDS_Netlisting_Mode to be set to Analog. Training is not provided as part of this PDK. 3 Supported Design Tools Cadence Design Framework II, version 5.0 Virtuoso Custom Design Platform: - Virtuoso Schematic Editor - Virtuoso Analog Design Environment including Spectre, AMS, UltraSim, and HspiceD simulation - Virtuoso Aptivia - Technology file support for Preview - VirtuosoLE, VirtuosoXL, Virtuoso CCAR & Chip Editor - Assura DRC, LVS, and RCX - CDL netlisting - Stream In/Out 4 Foundry Data (cid:131) TD-LO18-DR-2001 (2T) • TD-MM18-DR-2001 (2P) 0.18um Logic 1P6M Salicide 1.8V/3.3V Design Rules 0.18um Mixed Signal 1P6M Salicide 1.8V/3.3V Design Rules • TD-LO18-DR-2004 (2T) Revision 2.0 Revision 2.0 Revision 0.3 0.18um Logic 1.8V/3.3V Antenna Ratio/Scribe Line and Guard Ring Guideline/Bond Pad Opening Design Guide • TD-MM18-SP-2001 (3T) Revision 1.2 0.18um Mixed Signal 1P6M (1P5M, 1P4M) with Mim Salicide 1.8V/3.3V Spice Model • TD-MM18-RM-2001 (2T) Revision 1.0 0.18um Mixed Signal 1P6M with Mim Salicide 1.8V/3.3V RF Spice Model 5 What makes up a PDK? PDK stands for Process Design Kit. A PDK Contains the process technology and needed information to do device-level design in the Cadence DFII environment. PDK PDK PDK Schematic Schematic Schematic Schematic Schematic Symbols Symbols Symbols Symbols Symbols & CDF & CDF & CDF & CDF & CDF Analog Analog Analog Analog Analog Simulation Simulation Simulation Simulation Simulation & callbacks & callbacks & callbacks & callbacks & callbacks Spectre Spectre Spectre Spectre Spectre Models Models Models Models Models Foundry Foundry Foundry Fixed Fixed Fixed Fixed Fixed Layouts Layouts Layouts Layouts Layouts Parameterized Parameterized Parameterized Parameterized Parameterized Cells Cells Cells Cells Cells Techfile: Techfile: Techfile: Techfile: Techfile: - Layer maps - Layer maps - Layer maps - Layer maps - Layer maps - Layer props - Layer props - Layer props - Layer props - Layer props - symbolics - symbolics - symbolics - symbolics - symbolics - Connectivity - Connectivity - Connectivity - Connectivity - Connectivity - VCR setup - VCR setup - VCR setup - VCR setup - VCR setup Physical Physical Physical Physical Physical Verification Verification Verification Verification Verification - DRC - DRC - DRC - DRC - DRC - LVS - LVS - LVS - LVS - LVS - LPE - LPE - LPE - LPE - LPE Cadence Tool Cadence Tool Cadence Tool Schematic (Composer) Schematic (Composer) Schematic (Composer) Simulation Simulation Simulation Simulation Simulation Spectre Spectre Spectre Spectre Spectre Analog Design Environment Analog Design Environment Analog Design Environment Analog Design Environment Device Generation/Cell Design Device Generation/Cell Design Device Generation/Cell Design Device Generation/Cell Design Virtuoso XL (Advanced Layout Editor) Virtuoso XL (Advanced Layout Editor) Virtuoso XL (Advanced Layout Editor) Virtuoso XL (Advanced Layout Editor) Interconnect Wire Editor/Routing Interconnect Wire Editor/Routing Interconnect Wire Editor/Routing Interconnect Wire Editor/Routing Virtuoso Custom Router (VCR) Virtuoso Custom Router (VCR) Virtuoso Custom Router (VCR) Virtuoso Custom Router (VCR) Interactive Physical Verification Interactive Physical Verification Interactive Physical Verification Interactive Physical Verification Diva, Dracula, Assura Diva, Dracula, Assura Diva, Dracula, Assura Diva, Dracula, Assura Analog Analog Analog Front-end Front-end Front-end Design Design Design VirtuosoXL VirtuosoXL VirtuosoXL Layout Layout Layout 6 Installation of the PDK The PDK is distributed in compressed tar format. The distribution file name contains the PDK name and release time stamp: The PDK name for 1P2M, 1P3M, 1P4M, and 1P5M processes follow the same naming conversion as above. smic18mm_1P6M_YYYYMMDDhhmm.tar.gz cd To install the PDK, logon to the computer as the user who will own and maintain the PDK. Choose a disk and directory under which the PDK will be installed. This disk should be exported to all client machines and must be mounted consistently across all client machines. Change working directory to the location where the PDK will be installed: Extract the PDK from the archive using the following commands: This will produce a single directory with a name similar to following format: This is the PDK installation directory for the SMIC 0.18um MM/RF 1P6M process. The default permissions on the PDK have already been set to allow only the owner to have write, read and execute access. Other users will have only read and execute access. gzip -dc …/smic18mm_1P6M_YYYYMMDDhhmm.tar.gz | tar -xvf - smic18mm_1P6M_YYYYMMDDhhmm
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陈嘉烨
下载了,感谢分享。
2020-02-17 13:32:22回复
瑞克111
感谢分享。。
2020-01-30 10:39:37回复
fffgh
想要0.18的规则文件,不过感谢分享
2020-01-15 10:47:18回复
lrwinqin
介绍了各个模型的参数和版图,感谢分享
2020-01-11 15:04:12回复
talvikki
不错 是想要的
2019-12-11 15:24:11回复
spz110
想看的是smic .18工艺的设计规则,粗略的看下好像没有,但是感谢分享
2019-08-29 22:58:21回复
阿公qy
谢谢分享!!
2018-07-27 14:04:29回复
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