SMIC 0.18um Reference Manual 28 May 2004 This manual contains information about the SMIC 0.18um MM/RF 1P6M Salicide PDKs 1 Disclaimers Cadence Design Systems shall not be liable for the accuracy of this Process Design Kit. The Process Design Kit contained herein is provided by Cadence Design Systems, Inc on an "AS IS" basis without any warranty, and Cadence Design Systems, Inc has no obligation to support or otherwise maintain the information. Cadence Design Systems, Inc disclaims any representation that the information does not infringe any intellectual property rights or proprietary rights of any third parties. There are no other warranties given by Cadence Design Systems, Inc, whether express, implied or statutory, including, without limitation, implied warranties of merchantability and fitness for a particular purpose. STATEMENT OF USE This Process Design Kit contains confidential and proprietary information of Cadence Design Systems, Inc. and Semiconductor Manufacturing International Corporation. No part of this information may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any human or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of Cadence and SMIC. This information was prepared for informational purpose and is for use by Cadence Design Systems, Inc’s and SMIC’s customers only. Cadence Design Systems, Inc and SMIC reserve the right to make changes in the information at any time and without notice. 2 Overview The purpose of this document is to describe the technical details of the SMIC 0.18um Process Design Kit (PDK) provided by Cadence Design Systems, Inc. (Cadence). This PDK requires the UNIX environment variable CDS_Netlisting_Mode to be set to Analog. Training is not provided as part of this PDK. 3 Supported Design Tools Cadence Design Framework II, version 5.0 Virtuoso Custom Design Platform: - Virtuoso Schematic Editor - Virtuoso Analog Design Environment including Spectre, AMS, UltraSim, and HspiceD simulation - Virtuoso Aptivia - Technology file support for Preview - VirtuosoLE, VirtuosoXL, Virtuoso CCAR & Chip Editor - Assura DRC, LVS, and RCX - CDL netlisting - Stream In/Out 4 Foundry Data TD-LO18-DR-2001 (2T) 0.18um Logic 1P6M Salicide 1.8V/3.3V Design Rules Revision 2.0 • TD-MM18-DR-2001 (2P) Revision 2.0 0.18um Mixed Signal 1P6M Salicide 1.8V/3.3V Design Rules • TD-LO18-DR-2004 (2T) Revision 0.3 0.18um Logic 1.8V/3.3V Antenna Ratio/Scribe Line and Guard Ring Guideline/Bond Pad Opening Design Guide • TD-MM18-SP-2001 (3T) Revision 1.2 0.18um Mixed Signal 1P6M (1P5M, 1P4M) with Mim Salicide 1.8V/3.3V Spice Model • TD-MM18-RM-2001 (2T) Revision 1.0 0.18um Mixed Signal 1P6M with Mim Salicide 1.8V/3.3V RF Spice Model 5 What makes up a PDK? PDK stands for Process Design Kit. A PDK Contains the process technology and needed information to do device-level design in the Cadence DFII environment. PDK Cadence Tool Schematic Symbols & CDF Analog Simulation & callbacks Spectre Models Foundry Fixed Layouts Parameterized Cells Techfile: - Layer maps - Layer props - symbolics - Connectivity - VCR setup Physical Verification - DRC - LVS - LPE Schematic (Composer) Simulation Spectre Analog Design Environment Analog Front-end Design Device Generation/Cell Design Virtuoso XL (Advanced Layout Editor) Interconnect Wire Editor/Routing Virtuoso Custom Router (VCR) Interactive Physical Verification Diva, Dracula, Assura VirtuosoXL Layout 6 Installation of the PDK The PDK is distributed in compressed tar format. The distribution file name contains the PDK name and release time stamp: smic18mm_1P6M_YYYYMMDDhhmm.tar.gz The PDK name for 1P2M, 1P3M, 1P4M, and 1P5M processes follow the same naming conversion as above. To install the PDK, logon to the computer as the user who will own and maintain the PDK. Choose a disk and directory under which the PDK will be installed. This disk should be exported to all client machines and must be mounted consistently across all client machines. Change working directory to the location where the PDK will be installed: cd
Extract the PDK from the archive using the following commands: gzip -dc …/smic18mm_1P6M_YYYYMMDDhhmm.tar.gz | tar -xvf - This will produce a single directory with a name similar to following format: smic18mm_1P6M_YYYYMMDDhhmm This is the PDK installation directory for the SMIC 0.18um MM/RF 1P6M process. The default permissions on the PDK have already been set to allow only the owner to have write, read and execute access. Other users will have only read and execute access. 7 PDK Install Directory Structure/Contents REVISION_HISTORY - ASCII file containing the PDK revision history. cds.lib – Cadence library definition file. smic18mm/display.drf – Cadence Display Resources File smic18mm/.cdsenv – file containing common design tool environment settings icc.rules - Virtuoso Custom Router rules file models - directory that will store the PDK models stream - directory containing the Cadence stream in and out maps techfile - ASCII version of technology file smic18mm – SMIC 0.18um MM/RF Process PDK Cadence Library docs - directory containing the Cadence PDK documentation assura_smic18mm_tech - directory containing the Assura verification files. This directory contains the techRuleSets file that initializes the Assura environment for the user. assura_tech.lib - file containing the Cadence Assura initialization path 8 Creation of a Design Project A unique directory should be created for each circuit design project. The following command can be executed in UNIX: mkdir ~/circuit_design cd ~/circuit_design All work by the user should be performed in this circuit design directory. The following file should be copied from the PDK install directory to begin the circuit design process. The following command can be used: cp /display.drf . Next the user should create a "cds.lib" file. Using any text editor the following entry should be put in the cds.lib file: INCLUDE /cds.lib Where "pdk_install_directory" is the path to where the smic18mm PDK was installed. The following UNIX links are optional but may aid the user in entering certain forms with the Cadence environment. In UNIX the following command can be used: ln -s /models ln -s /stream Where, again, "pdk_install_directory" is the path to where the smic18mm PDK was installed. 9 Techfile Methodology The smic18mm library techfile will be designated as the master techfile. This techfile will contain all required techfile information. There is an ASCII version of this techfile shipped with the PDK. This ASCII version represents the techfile currently compiled into the smic18mm library The attach method should be used for any design library that is created. This allows the design database techfile to be kept in sync with the techfile in the process PDK. To create a new library that uses an attached techfile, use the command File->New->Library from either the CIW or library manager and select the Attach to an existing techfile option. Select the smic18mm library when asked for the name of the Attach To Technology Library. 10 Customizing Layer Display Properties Using the display.drf File The display.drf can be autoloaded at Cadence start-up time or manually loaded during the Cadence session. For the file to be autoloaded, the display.drf file must be located in the Cadence start-up directory. To manually load the display.drf file (or load a new version), choose Tools->Display Resources>Merge Files... from the CIW and enter the location of the display.drf file that you want to use. If the display.drf file is not autoloaded and you do not manually load it, you will get error messages about missing packets when you try to open a schematic or layout view and you will not be able to see any process specific layers. The display.drf file can be found in the smic18mm directories of the PDK. Listed below are the packet, color, lineStyle, and stipplePattern definitions for a metal3 drawing layer. The packet info references predefined color, lineStyle, and stipplePattern definitions. Any of these can be changed to suit an individual user’s preferences in the project copy of the display.drf file. drDefinePacket( ;( DisplayName PacketName Fill Outline ) Stipple LineStyle ( display m3 dots solid green green ) ) drDefineColor( ;( DisplayName ColorName Red ( display green 0 204 ) Green Blue Blink ) 102 nil ) drDefineLineStyle( ;( DisplayName LineStyle ( display solid 1 ) Size (1 1 1) ) Pattern ) drDefineStipple( ;( DisplayName ( display dots StippleName Bitmap ) ( (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) 11 Schematic Design The user should follow the guidelines listed below while building schematics using Composer: Project libraries should list the primitive PDK library as a reference library in the library properties form. Users can add instances from the PDK library to designs stored in the project libraries. When performing hierarchical copy of schematic designs care should be taken to preserve the references to the PDK libraries. These references should not be copied locally to the project directories and the references set to the local copy of PDK cells. This would prevent your designs from inheriting any fixes done to the PDK library from an upgrade. Users should exercise caution when querying an instance and changing the name of the cell and replacing it with a reference to another cell. While like parameters will inherit values, callbacks are not necessarily executed. This would cause dependent parameters to have incorrect values. Schematics should be designed with schematic driven layout methodology in mind. Partitioning of schematics, hierarchical design, input and output ports, should be done in a clean and consistent fashion. Usage of pPar and iPar in a schematic design Contactext is discouraged. While this works fine in schematic design, this could lead to problems while performing schematic driven layout. 12 Library Device Setup 12.1 Resistors The resistors in the library consist of three types; metal, diffused and insulated. The diffused types include p+, n+, are 2 terminal resistors with diode backplates. The insulated resistors are those that are isolated from silicon by an insulator (oxide) such as poly resistors. These resistors are 2 terminal devices. The metal resistors are 2 terminal resistors with the resistive material being the appropriate metal process layer. Serpentine resistor layouts are not allowed. Units: The width is specified in meters for schematic simulation. All parameters entered into the resistor form must be integers or floating point numbers. No design variables are supported due to the calculations that must be performed on the entries. Calculation: The length of the resistor segment is calculated from the resistance value, the width, and the number of parallel or series segments specified. These calculations are based on the SMIC data provided in the design rule manuals and SPICE models provided by SMIC. See the Foundry Documents section for document names. The width and length are snapped to grid, and the resistances are recalculated and updated on the component form based on actual dimensions. Simulation: SMIC supplied models are used to model the resistors. 12.2 MOSFETS All mosfets in the PDK library are 4 terminal devices, with the body terminal explicitly connected. Units: Length and width are in meters, with areas and perimeters in meters squared and meters, respectively. Design variables are allowed for Length and Width entries. Calculation: The area and perimeter parameters for the sources and drains are calculated from the width and the number of fingers used. This calculation assumes that the drain will always have the less Simulation: capacitance (area) when there are an even number of fingers (odd number of diffusion areas). The Width per finger is calculated by dividing the width by the number of fingers. This parameter is for viewing by the designer. These mosfets are netlisted as their predefined device names for simulation purposes. SMIC’s model definitions are used for these devices. 12.3 Bipolar Transistors All BJT’s in the PDK library are 3 terminal. Units: Only fixed size devices are allowed. A cyclic is used to enter the desired size. Calculation: The area is calculated from the emitter size cyclic. Simulation: These BJTs are netlisted as their predefined device names for simulation purposes. SMIC’s model definitions are used for these devices. 12.4 Diodes All diodes in the PDK library are 2 terminal devices. Units: Length and width are in meters. Design variables are not allowed for Length and Width entries. Calculation: The area is calculated from the width and length entered. Simulation: simulation These diodes are netlisted as their predefined device names for purposes. SMIC’s model definitions are used for these devices. 12.5 Capacitors The capacitors in the PDK are mimcaps and varactors. The mimcaps are two-terminal metal capacitors and the varactors are two terminal voltage controlled capacitors. Units: The length and width of mimcaps are specified in meters for schematic simulation. The varactors are specified by the number of fingers or groups of unit-varactors. All parameters entered into the capacitor form must be integers or floating point numbers. No design variables are supported due to the calculations that must be performed on the entries. Calculation: The only user entered option on the mimcaps is the multiplier value. The varactor devices allow the user to enter multiplier values as well as the number of fingers. The appropriate model and number of instances is subsequently netlisted in the simulation environment. Simulation: SMIC’s model definitions are used for these devices. 12.6 Inductors The spiral inductor is a two-terminal square type with the number of turns, inner radius, and mutliplier factor variable by the user. Units: The user may specify the number of turns and the inner radius values. Calculation: Inductance is calculated from the specified number of turns and inner radius. The inductance value is an estimated value and is only for display. This value is not used in simulation or LVS. Simulation: These inductors are netlisted with the number of turns and inner radius. SMIC’s model definitions are used for these devices. 12.7 RF MOS Units: The RF MOS devices are four-terminal devices where the body is required and is to be explicitly connected by the user. There are a discrete number of supported devices that are chosen via a cyclic field by the user. The only other user entered parameter is the multiplier factor which must be an integer. Calculation: No calculations are made for AS, AD, PS, PD or any other parameters. The m factor for these devices represent an entire device and all of its fingers. This is not the same as standard mosfets where m represents the total number of fingers. Simulation: These devices are netlisted with the number of fingers, the gate length, and the gate width. SMIC’s model definitions are used for these devices. 13 Supported Devices 13.1 MOSFETS • n18 • n33 • nmvt18 • nmvt33 • nnt18 • nnt33 • p18 • p33 • pmvt18 1.8V nominal VT NMOS transistor 3.3V nominal VT NMOS transistor 1.8V medium VT NMOS transistor 3.3V medium VT NMOS transistor 1.8V native NMOS transistor 3.3V native NMOS transistor 1.8V nominal VT NMOS transistor 3.3V nominal VT NMOS transistor 1.8V medium VT NMOS transistor 13.2 Resistors • rndif • rpdif • rndifsab • rpdifsab • rnpo • rppo • rnposab • rpposab • rhrpo • rnwaa • rnwsti • rm1 • rm2 N+ diffusion resistor with salicide P+ diffusion resistor with salicide N+ diffusion resistor without salicide P+ diffusion resistor without salicide N+ poly resistor with salicide P+ poly resistor with salicide N+ poly resistor without salicide P+ poly resistor without salicide High resistance poly resistor Nwell resistor under active area Nwell resistor under STI Metal 1 resistor Metal 2 resistor • rm3 • rm4 • rm5 • rm6 • rndifsab_ckt_rf • rpdifsab_ckt_rf • rnposab_ckt_rf • rpposab_ckt_rf • rhrpo_ckt_rf Metal 3 resistor Metal 4 resistor Metal 5 resistor Metal 6 resistor N+ diffusion RF resistor without salicide P+ diffusion RF resistor without salicide N+ poly RF resistor without salicide P+ poly RF resistor without salicide High resistance poly RF resistor 13.3 Bipolars • npn18 • npn33 • pnp18 • pnp33 1.8V N+/Pwell/Deep Nwell bipolar transistor 3.3V N+/Pwell/Deep Nwell bipolar transistor 1.8V PNP bipolar transistor 3.3V PNP bipolar transistor 13.4 Diodes • ndio18 • pdio18 • ndio33 • pdio33 • nwdio • nndio18 • nndio33 • diobpw 1.8V N+/Psubstrate diode 1.8V P+/Nwell diode 3.3V N+/Psubstrate diode 3.3V P+/Nwell diode Nwell/Psubstrate diode 1.8V native N+/Pwell diode 3.3V native N+/Pwell diode Buried Pwell/Deep Nwell diode 13.5 Capacitors • capm5 • capm4 Metal 5 – MiM capacitor (1P6M process) Metal 4 – MiM capacitor (1P5M process) • capm3 • capm2 • mim_rf Metal 3 – MiM capacitor (1P4M process) Metal 2 - MiM capacitor (1P3M process) Metal(top-1) - MiM RF capacitor (! 1P2M process) 13.6 Inductors • ind_rf Rectangular spiral inductor 13.7 RF Mos • n18_ckt_rf • p18_ckt_rf • n33_ckt_rf • p33_ckt_rf 1.8V RF NMOS transistor 1.8V RF PMOS transistor 3.3V RF NMOS transistor 3.3V RF PMOS transistor 13.8 Varactors • pvar18_ckt_rf • pvardio18_ckt_rf NMOS in Nwell MOSFET Varactor P+/Nwell Junction Diode Varactor 14 Views Provided 14.1 14.2 14.3 14.4 14.5 14.6 MOSFETS • Four terminals (D, G, S, B) • symbol, spectre, ams, UltraSim, hspiceD, auLvs, auCdl, ivpcell, layout (Pcells) Resistors • Two terminals (PLUS, MINUS) • symbol, spectre, ams, UltraSim, hspiceD, auLvs, auCdl, ivpcell, layout (Pcells) Bipolar Junction Transistors • Three terminals (C, B, E) • symbol, spectre, ams, UltraSim, hspiceD, auLvs, auCdl, ivpcell, layout (Fixed layouts) Diodes • Two terminals (PLUS, MINUS) • symbol, spectre, ams, UltraSim, hspiceD, auLvs, auCdl, ivpcell, layout (Fixed layouts) Capacitors • Two terminals (PLUS, MINUS) • symbol, spectre, ams, UltraSim, hspiceD, auLvs, auCdl, ivpcell, layout (Pcells) Inductors • Two terminals (PLUS, MINUS) • symbol, spectre, ams, UltraSim, hspiceD, auLvs, auCdl, ivpcell, layout (Pcells) 14.7 RF MOSFETS • Four terminals (D, G, S, B) • symbol, spectre, ams, UltraSim, hspiceD, auLvs, auCdl, ivpcell, layout (Fixed layouts) 14.8 Varactors • Two terminals (PLUS, MINUS) • symbol, spectre, ams, UltraSim, hspiceD, auLvs, auCdl, ivpcell, layout (Pcells) 15 CDF parameters 15.1 MOSFETS • Multiplier - number of Parallel MOS devices • Model Name - spectre model name (non-editable) • Length (M) - gate length in meters • Total Width (M) - gate width in meters (sum of all fingers) • Finger Width - width of each gate finger/stripe • Fingers - number of poly gate fingers/stripes used in layout • Threshold – finger width at which to apply device folding of the layout. • Apply Threshold – button to apply threshold or not • Gate Connection – allow shorting of multi-finger devices and addition of contact heads to gate ends. • S/D Connection – allow shorting of source and/or drains on multi-finger devices. • S/D Metal Width – width of metal used to short sources/drains. • Switch S/D – source is defined as left-most diffusion region and alternating regions to the right. Pins are not automatically permuted and can be switched using this parameter. • Bodytie Type – None, Detached, or Integrated (butting source). - For Detached, user may select Left, Right, Top, and/or Bottom to specify the located of bodyties. Selection of all four creates a guardring. - For Detached, the user may specify Tap Extension (in microns) which sets the distance from the bodytie to the device. Maximum distance is 100 microns. - For Integrated, the user may select Left or Right for a device with an odd number of fingers (1, 3, 5, …). The user may select Left and Right for an even fingered device. This option does not apply to native and medium Vth devices. • Drain diffusion area, etc – several simulation parameters are presented. The area and perimeter parameters are calculated and netlisted in accordance with the foundry models. MOSFET ADD INSTANCE FORM 15.2 Resistors • Model name (model) – Spectre model name (non-editable) • Segments (segments) – Number of resistor segments • Segment Connection (connection) – Connection between segments (Parallel, Series) • Calculated Parameter (calculatedParam) – Parameter to be calculated (Resistance, Length) • Resistance (r) – Entry or calculated value for resistance • Segment Width (segW) – Entry value for segment width in meters • Segment Length (segL) – Entry or calculated value for segment Length in meters • Effective Width (effW) – Calculated value based on number of segments, segment width, and segment connection (non-editable) • Effective Length (effL) – Calculated value based on number of segments, segment length, and segment connection (non-editable) • Left Dummy (leftDummy) – Toggle for placement of dummy resistor segment on the left side • Right Dummy (rightDummy) – Toggle for placement of dummy resistor segment on the right side • Contact Rows (cntRows) – Entry value for number of contact rows in each segment head • Contact Columns (cntCols) – Calculated value for number of contact columns in each segment head (non-editable) RESISTOR ADD INSTANCE FORM 15.3 Bipolar Junction Transistors • Model name - Spectre model name (non-editable) • Emitter Area – cyclic of the area of the emitter (microns) • Multiplier - Number of Parallel Bipolar devices • Estimated Operating Region – Cyclic of Spectre model operating region BIPOLAR ADD INSTANCE FORM 15.4 Diodes • Model name - Spectre model name (non-editable) • Device Area - Calculated junction area in meters squared (non-editable) • Multiplier - Number of Parallel Diode devices • Length (M) - diode length in meters (non-editable) • Width (M) - diode width in meters (non-editable) DIODE ADD INSTANCE FORM 15.5 Capacitors • Model Name – Spectre model name (non-editable) • Multiplier - Number of Parallel capacitor devices • Total Capacitance – Unit capacitance corresponding to the length and width • Capacitance – Unit capacitance corresponding to the length and width • Width (M) - Capacitor width in meters • Length (M) - Capacitor length in meters • Aspect Ratio (w/l) – Aspect ratio of width to length • Unit Area Capacitance – Capacitance per unit area in F/m^2 (non- editable) • Unit Fringe Capacitance – Capacitance per unit length in F/m (non- editable) CAPACITOR ADD INSTANCE FORM 15.6 Inductor • Model – Spectre model name (non-editable) • Multiplier – Number of inductor devices in parallel • Inner Radius - Inductor inner radius in meters • Coil Turns – Number of inductor turns • Width (M) - Inductor width in meters (non-editable) • Spacing (M) – Inductor spacing in meters (non-editable) INDUCTOR ADD INSTANCE FORM 15.7 • • • • • • RF MOSFETS Model Name – Spectre model name (non-editable) l (M) – Length of finger in meters (non-editable) w (M) - Width per finger in meters (non-editable) Number of Fingers – Number of fingers (non-editable) Multiplier – Number of RF Mos devices in parallel Device Size – Cyclic field specifying device configuration used RFMOS ADD INSTANCE FORM 16 Component Label Defaults 16.1 MOSFETS • • • • 16.2 component parameters: model, l, w, m operating point: ids, vgs, vds, vth, vdsat model: vto, kp, gamma instance name prefix: NM, PM Resistors • • • • 16.3 component parameters: r, w, l, segments, connectionType operating point: v i res model: instance name prefix: R Bipolar Junction Transistors • component parameters: model, area, m • operating point: betadc, ic, Vce • model: bf, is, va • instance name prefix: Q 16.4 Diodes • component parameters: model, area, m • operating point: id, vd, reg • model: is, rs, n • instance name prefix: D 16.5 Capacitors • component parameters: c, w, l, m • operating point: cap • model: • instance name prefix: C 16.6 Inductors • • • • 16.7 component parameters: model, n, radius operating point: model: instance name prefix: L RF MOSFETS • component parameters: model, l, w, fingers, m • operating point: ids, vgs, vds, vth, vdsat • model: vto, kp, gamma • instance name prefix: NM, PM 17 Simulation Models The following simulators are supported in this PDK: Spectre hSpiceD AMS UltraSim The following model library setup for Spectre is done automatically when the user first opens the smic18mm library or uses a component from that library. The user may disable this feature by editing the libInit.il file found in the smic18mm library. pdk_install_directory/models/spectre/MS018_v1p2_spe.lib tt pdk_install_directory/models/spectre/MS018_v1p2_spe.lib res_tt pdk_install_directory/models/spectre/ms018_rf_v1p0_spe.lib tt pdk_install_directory/models/spectre/ms018_rf_v1p0_spe.lib res_tt Where pdk_install_directory is the path where the SMIC 0.18 MM/RF PDK is installed and the second entry is the simulation corner that the user wants to simulate. The user should follow the instructions provided with the device models from SMIC to ensure the proper selection of sections for simulation. 18 AddWire Utility Certain devices in the library have bulk pins (i.e n18, p33, n18_ckt_rf, etc.). A utility has been added to the PDK to automatically wire these bulk terminals to user specified signals (i.e. gnd!, vdd!, etc.). This will help reduce schematic clutter while maintaining required circuit hookup. The following picture shows the result of executing the smic18mm_addWire routine. There are no arguments to run the program, the user must type smic18mm_addWire() in the CIW. If you don’t have a schematic cellview open it will give you an error message. If the user has instances selected when they run addWire, it will prompt them for the label name for those specific instances and will only add the wires to those instances. It does nothing to the schematic hierarchy. If no instances are selected then the program will wire up all instances that have their bulk nodes unconnected. The user gets prompted for the label name for each type of instance, and they also have the option of running it down through the hierarchy or just at the current cellview. And, finally, if the user does not want to use gnd! or vdd! as the label name, there is an entry box for the user to type in an alternative net name. If another wire name is used, it will be added to the cyclic list of label name choices - but only for that DFII session. Once you exit the dfII session, the cyclic is reset to gnd! and vdd!. 19 UpdateCDFs Utility When changes are made to a device inside the PDK, these changes often affect circuit design which have already been created. For example, a sheet rho value may change on a resistor which affects the length of the device passed to the simulator and used to generate the layout. These parameters are not automatically updated in each of the designer’s circuit libraries. A function has been written and included as a part of the PDK to complete the update to an existing library such that all modifications made to a PDK since a previous release are reflected in each of the circuit designs inside a library. The procedure name as typed in the CIW is PasFlexUpdateLib. Executing the command in CIW brings up a GUI for updating design libraries. After specifying a design library, the procedure traverses the design library hierarchy and updates all the appropriate CDF informaiton. Please note, however, that possible LVS violations may arise as a result of running this routine depending upon what changes have been made to the PDK. For example, a sheet rho change as specified earlier could cause a resistor to shrink in length in the schematic thus causing a mismatch as far as LVS is concerned. Please be sure that you verify again each design in simulation, DRC, and LVS to insure that no unintended modifications have been overlooked. 20 Techfile Layers Techfile layers defined in the PDK are done in compliance with technology file supplied by SMIC. The technology file compiled with this PDK Contains all defined layer/levels as defined in the SMIC supplied techfile. Layer names and visibility /selectability may be altered from this technology file, if necessary. 21 Virtuoso XL The standard Cadence Virtuoso XL design flow is implemented. This includes basic connectivity of connection layers, wells, and substrate, and symbolic contacts. The M factor is used for device instance multiplier - there is no conflict with the parameter used in cell operation. Names are be displayed on the layout views to aid in schematic-layout instance correlation. Auto-abutment of MOSFET devices is supported. Pin permuting of MOSFET and Resistor device is also supported. The pcell layouts are compiled into the PDK. The users should follow the guidelines listed below for layout design: The VirtuosoXL tool requires a separate license for operation. Users obtain maximum leverage from the PDK by doing schematic driven layout in the Virtuoso XL environment. This flow will produce a correct design layout. The Virtuoso Custom Router (IC Craftsman) can be used to finish the interconnect in the layout. The VCR rules file for the target process is provided with the PDK. Abutment is currently supported only for MOS transistors. Note, abutment will work only on schematic driven layouts. Schematic Driven Layout is recommended over Netlist Driven Layout. NOTE: Skill pcell source code is not included in the PDK kit. 21.1 Symbolic Contacts • M1_AA • M1_GT • M1_NW • M1_SN • M1_SP • M1_SUB • M2_M1 • M3_M2 • M4_M3 • M5_M4 • M6_M5 Metal 1 to Active Area Contact Metal 1 to Poly Contact Metal 1 to Nwell Contact Metal 1 to N+ Active Area Contact Metal 1 to P+ Active Area Contact Metal 1 to P+ Substrate Contact Metal 2 to Metal 1 Via Metal 3 to Metal 2 Via Metal 4 to Metal 3 Via Metal 5 to Metal 4 Via Metal 6 to Metal 5 Via CREATE CONTACT FORM 22 Assura Support Cadence has incorporated the Assura drc, lvs, and rcx decks supplied by SMIC into the delivered PDK. The PDK has been developed using these verification decks as the benchmark for how the library devices are to be verified, netlisted, and compared using the Assura tool set. DRC The Assura drc rule files are located in the assura_smic18mm_tech/drc directory. These files are referenced by the techRuleSets file located in the assura_smic18mm_tech. LVS The Assura lvs rule files are located in the assura_smic18mm_tech/lvs directory. These files are referenced by the techRuleSets file located in the assura_smic18mm_tech. RCX The Assura rcx rule files are located in the assura_smic18mm_tech/rcx directory. These files are referenced by the techRuleSets file located in the assura_smic18mm_tech directory. ASSURA DRC FORM ASSURA LVS FORM ASSURA RCX FORM 23 Device Datasheets 23.1 n18 – 1.8V Nominal VT NMOS Spectre Netlist Spectre Model Name = “n18” NM0 (net82 net84 net85 VSS) n18 w=220n l=180n as=1.984e-13 ad=1.984e-13 \ ps=1.66u pd=1.66u m=1*1 CDL Netlist CDL Device Name = “n18” MMN1 D G S B n18 W=220n L=180n M=1.0 Assura Netlist Assura auLvs Device Name = “n18” C n18 MOS DRAIN B GATE B SOURCE B * 4 pins * 4 nets * 0 instances i MN1 n18 D G S B ; m 1 l 1.8e-07 w 220e-09 ; SUBSTRATE B ;; n18 (backend) Width Length Layer AA SN GT CT M1 Device Layers Color and Fill Device Recognition G D S B Device Derivation Layer Derivation AA AND SN CONTAINS GT GT AA AND SN NOT GT AA AND SN NOT GT Substrate Parameter Length Width LVS Comparison Calculation GT intersecting AA (illustrated above) GT inside AA (illustrated above) * S and D are PERMUTABLE 23.2 n33 – 3.3V Nominal Vt NMOS Spectre Netlist Spectre Model Name = “n33” NM1 (net78 net80 net81 VSS) n33 w=350n l=350n as=2.114e-13 ad=2.114e-13 \ ps=1.53u pd=1.53u m=1*1 CDL Netlist CDL Device Name = “n33” MMN1 D G S B n33 W=350n L=350n M=1.0 Assura Netlist Assura auLvs Device Name = “n33” c n33 MOS DRAIN B GATE B SOURCE B * 4 pins * 4 nets * 0 instances i MN1 p18 D G S B ; m 1 l 3.5e-07 w 3.5e-07 ; SUBSTRATE B ;; n33 (backend) Width Length Layer AA SN GT CT M1 DG Device Layers Color and Fill Device Recognition G D S B Device Derivation Layer Derivation AA AND SN AND DG CONTAINS GT GT AA AND SN AND DG NOT GT AA AND SN NOT GT Substrate LVS Comparison Parameter Calculation Length GT intersecting AA (illustrated above) Width GT inside AA (illustrated above) * S and D are PERMUTABLE 23.3 nmvt18 – 1.8V Medium Vt NMOS Spectre Netlist Spectre Model Name = “nmvt18” NM2 (net74 net76 net77 VSS) nmvt18 w=300n l=300n as=2.064e-13 \ ad=2.064e-13 ps=1.58u pd=1.58u m=1*1 CDL Netlist CDL Device Name = “nmvt18” MMN1 D G S B nmvt18 W=300n L=300n M=1.0 Assura Netlist Assura auLvs Device Name = “nmvt18” C nmvt18 MOS DRAIN B GATE B SOURCE B * 4 pins * 4 nets * 0 instances i MN1 nmvt18 D G S B ; m 1 3.0 e-07 w 3.0e-7 ; SUBSTRATE B ;; nmvt18 (backend) Width Length Layer AA SN GT CT M1 MVN Device Layers Color and Fill Device Recognition G D S B Device Derivation Layer Derivation AA AND SN AND MVN CONTAINS GT GT AA AND MVN AND SN NOT GT AA AND MVN AND SN NOT GT Substrate Parameter Length Width LVS Comparison Calculation GT intersecting AA (illustrated above) GT inside AA (illustrated above) * S and D are PERMUTABLE 23.4 nnt18 – 1.8V Native NMOS Spectre Netlist Spectre Model Name = “nnt18” NM3 (net70 net72 net73 VSS) nnt18 w=500n l=500n as=2.4e-13 ad=2.4e-13 \ ps=1.46u pd=1.46u m=1*1 CDL Netlist CDL Device Name = “nnt18” MMN1 D G S B nnt18 W=500n L=500n M=1.0 Assura Netlist Assura auLvs Device Name = “nnt18” C nnt18 MOS DRAIN B GATE B SOURCE B * 4 pins * 4 nets * 0 instances i MN1 nnt18 D G S B ; m 1 5.0e-07 w 5.0e-07 ; SUBSTRATE B ;; nnt18 (backend) Width Length Layer AA SN GT CT M1 NN Device Layers Color and Fill Device Recognition G D S B Device Derivation Layer Derivation AA AND SN AND NN CONTAINS GT GT AA AND SN AND NN NOT GT AA AND SN AND NN NOT GT Substrate Parameter Length Width * S and D are PERMUTABLE LVS Comparison Calculation GT intersecting AA (illustrated above) GT inside AA (illustrated above) 23.5 nnt33 – 3.3V Native NMOS Spectre Netlist Spectre Model Name = “nnt33” NM4 (net66 net68 net69 VSS) nnt33 w=1.2u l=1.2u as=5.76e-13 ad=5.76e-13 \ ps=2.16u pd=2.16u m=1*1 CDL Netlist CDL Device Name = “nnt33” MMN1 D G S B nnt33 W=1.2u L=1.2u M=1.0 Assura Netlist Assura auLvs Device Name = “nnt33” C nnt33 MOS DRAIN B GATE B SOURCE B * 4 pins * 4 nets * 0 instances i MN1 nnt33 D G S B ; m 1 l 1.2e-06 w 1.2e-06 ; SUBSTRATE B ;; nnt33 (backend) Width Length Layer AA SN GT CT M1 DG NN Device Layers Color and Fill Device Recognition G D S B Device Derivation Layer Derivation AA AND SN AND DG CONTAINS GT GT AA AND SN AND DG NOT GT AA AND SN AND DG NOT GT Substrate LVS Comparison Parameter Calculation Length GT intersecting AA (illustrated above) Width GT inside AA (illustrated above) * S and D are PERMUTABLE 23.6 nmvt33 – 3.3V Medium Vt NMOS Spectre Netlist Spectre Model Name = “nmvt18” NM5 (net62 net64 net65 VSS) nmvt18 w=300n l=300n as=2.064e-13 \ ad=2.064e-13 ps=1.58u pd=1.58u m=1*1 CDL Netlist CDL Device Name = “nmvt33” MMN1 D G S B nmvt33 W=300n L=300n M=1.0 Assura Netlist Assura auLvs Device Name = “nmvt33” c nmvt33 MOS DRAIN B GATE B SOURCE B * 4 pins * 4 nets * 0 instances i MN1 nmvt33 D G S B ; m 1 l 3.0e-07 w 3.0e-07 ; SUBSTRATE B ;; nmvt33 (backend) Width Length Layer M1 AA SN GT CT DG MVN Device Layers Color and Fill Device Recognition G D S B Device Derivation Layer Derivation AA AND SN AND DG AND MVN CONTAINS GT GT AA AND SN AND DG AND MVN NOT GT AA AND SN AND DG AND MVN NOT GT Substrate Parameter Length Width LVS Comparison Calculation GT intersecting AA (illustrated above) GT inside AA (illustrated above) * S and D are PERMUTABLE 23.7 p18 – 1.8V Nominal VT PMOS Spectre Netlist Spectre Model Name = “p18” PM0 (net54 net56 net57 VDD) p18 w=220n l=180n as=1.984e-13 ad=1.984e-13 \ ps=1.66u pd=1.66u m=1*1 CDL Netlist CDL Device Name = “p18” MMP1 D G S B p18 W=220n L=180n M=1.0 Assura Netlist Assura auLvs Device Name = “p18” C p18 MOS DRAIN B GATE B SOURCE B * 4 pins * 4 nets * 0 instances i MP1 p18 D G S B ; m 1 l 1.8e-07 w 2.2e-07 ; SUBSTRATE B ;; p18 (backend) Width Length Layer NW AA SP GT CT M1 Device Layers Color and Fill Device Recognition G D S B Device Derivation Layer Derivation NW AND AA AND SP CONTAINS GT GT NW AND AA AND SP NOT GT NW AND AA AND SP NOT GT Substrate Parameter Length Width LVS Comparison Calculation GT intersecting AA (illustrated above) GT inside AA (illustrated above) * S and D are PERMUTABLE 23.8 p33 – 3.3V Nominal VT PMOS Spectre Netlist Spectre Model Name = “p33” PM1 (net50 net52 net53 VDD) p33 w=300n l=300n as=2.064e-13 ad=2.064e-13 \ ps=1.58u pd=1.58u m=1*1 CDL Netlist CDL Device Name = “p33” MMP1 D G S B p33 W=300n L=300n M=1.0 Assura Netlist Assura auLvs Device Name = “p33” C p33 MOS DRAIN B GATE B SOURCE B * 4 pins * 4 nets * 0 instances i MP1 p33 D G S B ; m 1 l 3.0e-07 w 3.0e-7 ; SUBSTRATE B ;; p33 (backend) Width Length Layer NW AA SP GT CT M1 DG Device Layers Color and Fill Device Recognition G D S B Device Derivation Layer Derivation NW AND AA AND DG AND SP CONTAINS GT GT NW AND AA AND DG AND SP NOT GT NW AND AA AND DG AND SP NOT GT Substrate Parameter Length Width LVS Comparison Calculation GT intersecting AA (illustrated above) GT inside AA (illustrated above) * S and D are PERMUTABLE 23.9 pmvt18 – 1.8V Medium VT PMOS Spectre Netlist Spectre Model Name = “pmvt18” PM2 (net46 net48 net49 VDD) pmvt18 w=250n l=250n as=2.014e-13 \ ad=2.014e-13 ps=1.63u pd=1.63u m=1*1 CDL Netlist CDL Device Name = “pmvt18” MMP1 D G S B pmvt18 W=250n L=250n M=1.0 Assura Netlist Assura auLvs Device Name = “pmvt18” C pmvt18 MOS DRAIN B GATE B SOURCE B * 4 pins * 4 nets * 0 instances i MP1 pmvt18 D G S B ; m 1 l 2.5e-07 w 2.5e-07 ; SUBSTRATE B ;; pmvt18 (backend) Width Length Layer NW AA SP GT CT M1 MVN Device Layers Color and Fill Device Recognition G D S B Device Derivation Layer Derivation NW AND AA AND MVN AND SP CONTAINS GT GT NW AND AA AND MVN AND SP NOT GT NW AND AA AND MVN AND SP NOT GT Substrate Parameter Length Width LVS Comparison Calculation GT intersecting AA (illustrated above) GT inside AA (illustrated above) * S and D are PERMUTABLE 23.10 rndif – Silicide N+ Diffusion Resistor Spectre Netlist Spectre Model Name = “rndif” R1 (net0166 net21) rndif l=10u w=420n m=1 CDL Netlist CDL Device Name = “rndif” RR1 PLUS MINUS rndif L=10u W=420n M=1 Assura Netlist Assura auLvs Device Name = “rndif” c rndif RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rndif PLUS MINUS ; l 10.0u w 420n ; rndif (backend) Length Width Layer AA SN Res_AA CT M1 Device Layers Color and Fill Device Recognition PLUS MINUS Device Derivation Layer Derivation AA AND SN AND Res_AA AA NOT Res_AA AND SN AA NOT Res_AA AND SN Parameter Length Width Resistance LVS Comparison Calculation CT to CT (illustrated above) AA Width (illustrated above) sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.11 rpdif – Silicide P+ Diffusion Resistor Spectre Netlist Spectre Model Name = “rpdif” R1 (PLUS MINUS) rpdif l = 10u w = 420n CDL Netlist CDL Device Name = “rpdif” RR1 PLUS MINUS rpdif L=10u W=420n Assura Netlist Assura auLvs Device Name = “rpdif” c rpdif RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rpdif PLUS MINUS ; l 10u w 420n ; rpdif (backend) Length Width Layer AA SP Res_AA CT M1 Device Recognition PLUS MINUS Parameter Length Width Resistance Device Layers Color and Fill Device Derivation Layer Derivation AA AND SP AND Res_AA AA NOT Res_AA AND SP AA NOT Res_AA AND SP LVS Comparison Calculation CT to CT (illustrated above) AA Width (illustrated above) sheet resistance * Length / Width • PLUS and MINUS are PERMUTABLE 23.12 Non-Silicide N+ Diffusion Resistors Devices: rndifsab (Non-RF), rndifsab_ckt_rf (RF) Spectre Netlist Spectre Model Name = “rndifsab” / “rndifsab_ckt_rf” R1 (PLUS MINUS) rndifsab l=10u w=500n CDL Netlist CDL Device Name = “rndifsab” / “rndifsab_ckt_rf” RR1 PLUS MINUS rndifsab L=10u W=500n XRR1 PLUS MINUS rndifsab_ckt_rf L=10u W=500n Assura Netlist Assura auLvs Device Name = “rndifsab” / “rndifsab_ckt_rf” c rndifsab RES IN B OUT B;; * 2 pins * 2 nets * 0 instances i R1 rndifsab PLUS MINUS ; l 10u w 500n ; rndifsab, rndifsab_ckt_rf (backend) Length Width Layer AA Res_AA CT M1 SN SAB Device Layers Color and Fill RFDEV (only in RF device) Device Recognition PLUS MINUS Device Derivation Layer Derivation AA AND Res_AA AND SAB AND SN (Non-RF) AA AND Res_AA AND SAB AND SN AND RFDEV (RF) AA AND SN NOT Res_AA AA And SN NOT Res_AA LVS Comparison Parameter Calculation Length Res_AA (illustrated above) Width AA Width (illustrated above) Resistance sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.13 Non-Silicide P+ Diffusion Resistors Devices: rpdifsab (Non-RF), rpdifsab_ckt_rf (RF) Spectre Netlist Spectre Model Name = “rpdifsab” / “rpdifsab_ckt_rf” R1 (PLUS MINUS) rpdifsab l=10u w=500n CDL Netlist CDL Device Name = “rpdifsab” / “rpdifsab_ckt_rf” RR1 PLUS MINUS rpdifsab L=10u W=500n XRR1 PLUS MINUS rpdifsab_ckt_rf L=10u W=500n Assura Netlist Assura auLvs Device Name = “rpdifsab” / “rpdifsab_ckt_rf” c rpdifsab RES IN B OUT B;; * 2 pins * 2 nets * 0 instances i R1 rpdifsab PLUS MINUS ; l 10u w 500n ; rpdifsab, rpdifsab_ckt_rf (backend) Length Width Layer AA Res_AA CT M1 SP SAB Device Layers Color and Fill RFDEV (only in RF device) Device Recognition PLUS MINUS Parameter Length Width Resistance Device Derivation Layer Derivation AA AND Res_AA AND SAB AND SP (Non-RF) AA AND Res_AA AND SAB AND SP AND RFDEV (RF) AA AND SP NOT Res_AA AA And SP NOT Res_AA LVS Comparison Calculation Res_AA (illustrated above) AA Width (illustrated above) sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.14 rnwaa – Silicide Nwell Resistor Under AA Spectre Netlist Spectre Model Name = “rnwaa” R1 (PLUS MINUS) rnwaa l=10u w=2.1u CDL Netlist CDL Device Name = “rnwaa” RR1 PLUS MINUS rnwaa L=10u W=2.1u Assura Netlist Assura auLvs Device Name = “rnwaa” c rnwaa RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rnwaa PLUS MINUS ; l 10u w 2.1u ; rnwaa (backend) – due to complexity of this layout, please see SMIC documentation Width Length Layer NW Res_NW CT M1 SN AA Device Layers Color and Fill Device Recognition PLUS MINUS Parameter Length Width Resistance Device Derivation Layer Derivation NW AND Res_NW AND AA AND SAB NW NOT Res_NW NW NOT Res_NW LVS Comparison Calculation AA to AA NW Width (illustrated above) sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.15 rnwsti – Silicide Nwell Resistor Under STI Spectre Netlist Spectre Model Name = “rnwsti” R1 (PLUS MINUS) rnwsti l=10u w=2.1u CDL Netlist CDL Device Name = “rnwsti” RR1 PLUS MINUS rnwsti L=10u W=2.1u Assura Netlist Assura auLvs Device Name = “rnwsti” c rnwsti RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rnwsti PLUS MINUS ; l 10u w 2.1u ; rnwsti (backend) Width Length Layer NW Res_NW CT M1 SN AA Device Layers Color and Fill Device Derivation Device Layer Derivation Recognition NW AND Res_NW ANDNOT AA PLUS NW ANDNOT Res_NW MINUS NW ANDNOT Res_NW LVS Comparison Parameter Calculation Length AA to AA Width NW Width (illustrated above) Resistance sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.16 rnpo – Silicide N+ Poly Resistor Spectre Netlist Spectre Model Name = “rnpo” R1 (PLUS MINUS) rnpo l 10u w 2u CDL Netlist CDL Device Name = “rnpo” RR1 PLUS MINUS rnpo L=10u W=2u Assura Netlist Assura auLvs Device Name = “rnpo” c rnpo RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rnpo PLUS MINUS ; l 10u w 2u ; rnpo (backend) Width Length Layer GT Res_P1 CT M1 SN Device Layers Color and Fill Device Derivation Device Layer Derivation Recognition GT AND Res_P1 AND SN PLUS GT NOT Res_P1 MINUS GT NOT Res_P1 LVS Comparison Parameter Calculation Length CT to CT Width GT Width (illustrated above) Resistance Sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.17 rppo – Silicide P+ Poly Resistor Spectre Netlist Spectre Model Name = “rppo” R1 (PLUS MINUS) rppo l 10u w 2u CDL Netlist CDL Device Name = “rppo” RR1 PLUS MINUS rppo L=10u W=2u Assura Netlist Assura auLvs Device Name = “rppo” c rppo RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rppo PLUS MINUS ; l 10u w 2u ; rppo (backend) Width Length Layer GT Res_P1 CT M1 SP Device Layers Color and Fill Device Derivation Device Layer Derivation Recognition GT AND Res_P1 AND SP PLUS GT NOT Res_P1 MINUS GT NOT Res_P1 LVS Comparison Parameter Calculation Length CT to CT Width GT Width (illustrated above) Resistance Sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.18 Non-Silicide N+ Poly Resistors Devices: rnposab (Non-RF), rnposab_ckt_rf (RF) Spectre Netlist Spectre Model Name = “rnposab” / “rnposab_ckt_rf” R1 (PLUS MINUS) rnposab l=10u w=500n CDL Netlist CDL Device Name = “rnposab” / “rnposab_ckt_rf” RR1 PLUS MINUS rnposab L=10u W=500n XRR1 PLUS MINUS rnposab_ckt_rf L=10u W=500n Assura Netlist Assura auLvs Device Name = “rnposab” / “rnposab_ckt_rf” c rnposab RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rnposab PLUS MINUS ; l 10u w 500n ; rnposab, rnposab_ckt_rf (backend) Length Width Layer GT Res_P1 CT M1 SN SAB Device Layers Color and Fill RFDEV (only in RF device) Device Recognition PLUS MINUS Device Derivation Layer Derivation GT AND Res_P1 AND SAB AND SN (Non-RF) GT AND Res_P1 AND SAB AND SN AND RFDEV (RF) GT NOT Res_P1 GT NOT Res_P1 Parameter Length Width Resistance LVS Comparison Calculation Res_P1 (illustrated above) GT Width (illustrated above) sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.19 Non-Silicide P+ Poly Resistors Devices: rpposab (Non-RF), rpposab_ckt_rf (RF) Spectre Netlist Spectre Model Name = “rpposab” / “rpposab_ckt_rf” R1 (PLUS MINUS) rpposab l=10u w=500n CDL Netlist CDL Device Name = “rpposab” / “rpposab_ckt_rf” RR1 PLUS MINUS rpposab L=10u W=500n XRR1 PLUS MINUS rpposab_ckt_rf L=10u W=500n Assura Netlist Assura auLvs Device Name = “rpposab” / “rpposab_ckt_rf” c rpposab RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rpposab PLUS MINUS ; l 10u w 500n ; rpposab, rpposab_ckt_rf (backend) Length Width Layer AA Res_P1 CT M1 SP SAB Device Layers Color and Fill RFDEV (only in RF device) Device Recognition PLUS MINUS Device Derivation Layer Derivation GT AND Res_P1 AND SAB AND SP (Non-RF) GT AND Res_P1 AND SAB AND SP AND RFDEV (RF) GT AND SP NOT Res_P1 GT And SP NOT Res_P1 LVS Comparison Parameter Calculation Length Res_P1 (illustrated above) Width GT Width (illustrated above) Resistance sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.20 Non-Silicide HR Poly Resistors Devices: rhrpo (Non-RF), rhrpo_ckt_rf (RF) Spectre Netlist Spectre Model Name = “rhrpo” / “rhrpo_ckt_rf” R1 (PLUS MINUS) rhrpo l=10u w=2u CDL Netlist CDL Device Name = “rhrpo” / “rhrpo_ckt_rf” RR1 PLUS MINUS 5.15e3 rhrpo L=10u W=2u XRR1 PLUS MINUS rhrpo_ckt_rf L=10u W=2u Assura Netlist Assura auLvs Device Name = “rhrpo” / “rhrpo_ckt_rf” c rhrpo RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rhrpo PLUS MINUS ; l 10u w 2u ; rhrpo, rhrpo_ckt_rf (backend) Length Width Device Layers Layer Color and Fill GT HRPDMY CT M1 HRP SAB SP RFDEV (only in RF device) Device Recognition PLUS MINUS Device Derivation Layer Derivation GT AND HRP AND SAB AND HRPDMY (Non-RF) GT AND HRP AND SAB AND HRPDMY AND RFDEV (RF) GT AND SP NOT HRPDMY GT And SP NOT HRPDMY LVS Comparison Parameter Calculation Length HRPDMY (illustrated above) Width GT Width (illustrated above) Resistance sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.21 Metal Resistors Devices – rm1, rm2, …, rm6 Spectre Netlist Spectre Model Name = “rm1s”, “rm2_7s”, “rm8s” R1 (PLUS MINUS) rm1 l 230n w 230n CDL Netlist CDL Device Name = “rm1”, “rm2”, …, “rm6” RR1 PLUS MINUS rm6 L=230n W=230n Assura Netlist Assura auLvs Device Name = “rm1” c rm1 RES IN B OUT B ;; * 2 pins * 2 nets * 0 instances i R1 rm1 PLUS MINUS ; l 230n w 230n ; Metal Resistors (backend) Length Width Layer M1-M6 M1R-M6R Device Layers Color and Fill Device Derivation Device Layer Derivation Recognition M1 AND M1R PLUS M1 NOT M1R MINUS M1 NOT M1R LVS Comparison Parameter Calculation Length M1R Width Width M1 Width (illustrated above) Resistance Sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE 23.22 N+ Diffusion Diodes Devices – ndio18, ndio33 Spectre Netlist Spectre Model Name = “ndio18” / “ndio33” D0 ( PLUS MINUS ) ndio18 area=7.921e-13 pj=3.56u m=1 CDL Netlist CDL Device Name = “ndio18” / “ndio33” DD0 PLUS MINUS ndio18 AREA=7.921e-13 PJ=3.56u M=1 Assura Netlist Assura auLvs Device Name = “ndio18” / “ndio33” c ndio18 DIO POS B MINUS B ;; * 2 pins * 2 nets * 0 instances i D0 ndio18 PLUS MINUS ; area 7.921e-13 m 1 ; ndio18, ndio33 (backend) Due to the complexity of the device, please refer to the PDK for information on the layout construction of this device Device Recognition PLUS MINUS Parameter Area Device Derivation Layer Derivation DSTR AND SN DSTR AND SP DSTR AND SN LVS Comparison Calculation Area of SN 23.23 P+ Diffusion Diodes Devices – pdio18, pdio33 Spectre Netlist Spectre Model Name = “pdio18” / “pdio33” D0 ( PLUS MINUS ) pdio18 area=7.921e-13 pj=3.56u m=1 CDL Netlist CDL Device Name = “pdio18” / “pdio33” DD0 PLUS MINUS pdio18 AREA=7.921e-13 PJ=3.56e-06 Assura Netlist Assura auLvs Device Name = “pdio18” / “pdio33” c pdio18 DIO POS B MINUS B ;; * 2 pins * 2 nets * 0 instances i D0 pdio18 PLUS MINUS ; area 7.921e-13 m 1 ; pdio18, pdio33 (backend) Due to the complexity of the device, please refer to the PDK for information on the layout construction of this device Device Recognition PLUS MINUS Device Derivation Layer Derivation DSTR AND SN DSTR AND SP DSTR AND SN Parameter Area LVS Comparison Calculation Area of SN 23.24 Native N+ Diffusion Diodes Devices – nndio18, nndio33 Spectre Netlist Spectre Model Name = “nndio18” / “nndio33” D0 ( PLUS MINUS ) nndio18 area=7.921e-13 pj=3.56u m=1 CDL Netlist CDL Device Name = “nndio18” / “nndio33” DD0 PLUS MINUS nndio18 AREA=7.921e-13 PJ=3.56e-06 Assura Netlist Assura auLvs Device Name = “nndio18” / “nndio33” c nndio18 DIO POS B MINUS B ;; * 2 pins * 2 nets * 0 instances i D0 nndio18 PLUS MINUS ; area 7.921e-13 m 1 ; nndio18, nndio33 (backend) Due to the complexity of the device, please refer to the PDK for information on the layout construction of this device Device Recognition PLUS MINUS Device Derivation Layer Derivation DSTR AND SN AND NN DSTR AND SP DSTR AND SN Parameter Area LVS Comparison Calculation Area of SN 23.25 nwdio – Nwell/Pwell Diode Spectre Netlist Spectre Model Name = “nwdio” D0 ( PLUS MINUS ) nwdio area=4.452e-12 pj=8.44u m=1 CDL Netlist CDL Device Name = “nwdio” DD0 PLUS MINUS nwdio AREA=4.452e-12 PJ=8.44e-06 Assura Netlist Assura auLvs Device Name = “nwdio” c nwdio DIO POS B MINUS B ;; * 2 pins * 2 nets * 0 instances i D0 nwdio PLUS MINUS ; area 4.452e-12 m 1 ; nwdio (backend) Due to the complexity of the device, please refer to the PDK for information on the layout construction of this device Device Recognition PLUS MINUS Device Derivation Layer Derivation DSTR AND SN AND NW DSTR AND SP DSTR AND SN Parameter Area LVS Comparison Calculation Area of NW 23.26 diobpw – Buried Pwell/Deep Nwell Diode Spectre Netlist Spectre Model Name = “diobpw” D0 ( PLUS MINUS ) diobpw area=2.75625e-12 pj=6.65u m=1 CDL Netlist CDL Device Name = “diobpw” DD0 PLUS MINUS diobpw AREA=2.75625e-12 PJ=6.65e-06 Assura Netlist Assura auLvs Device Name = “diobpw” c diobpw DIO POS B MINUS B ;; * 2 pins * 2 nets * 0 instances i D0 diobpw PLUS MINUS ; area 2.75625e-12 m 1 ; diobpw (backend) Due to the complexity of the device, please refer to the PDK for information on the layout construction of this device Device Recognition PLUS MINUS Device Derivation Layer Derivation DSTR AND SN AND DNW DSTR AND SP DSTR AND SN Parameter Area LVS Comparison Calculation Area of DNW 23.27 Vertical Bipolar PNP Transistors Devices – pnp18, pnp33 Spectre Netlist Spectre Model Name = “pnp18” / “pnp33” Q0 ( C B E ) pnp18 m=1 CDL Netlist CDL Device Name = “pnp18” / “pnp33” QQ0 C B E pnp18 AREA=4e-12 M=1 Assura Netlist Assura auLvs Device Name = “pnp18” / “pnp33” c pnp18 BJT COLLECTOR B BASE B EMITTER B ;; * 3 pins * 3 nets * 0 instances i Q0 pnp18 C B E; area 4.0e-12 m 1 ; pnp18, pnp33 (backend) C B E Area Layer DMPNP NW SN / AA SP / AA CT M1 Device Recognition E B C Parameter Area Device Layers Color and Fill Device Derivation Layer Derivation DMPNP Contains SN AND SP DMPNP AND SP And AA AND NW DMPNP AND SN And AA AND NW substrate LVS Comparison Calculation Area of Emitter (illustrated above) 23.28 N+/Pwell/Deep Nwell Bipolar Transistors Devices – npn18, npn33 Spectre Netlist Spectre Model Name = “npn18” / “npn33” Q0 ( C B E ) npn18 m=1 CDL Netlist CDL Device Name = “npn18” / “npn33” QQ0 C B E npn18 AREA=4.0e-12 M=1 Assura Netlist Assura auLvs Device Name = “npn18” / “npn33” c npn18 BJT COLLECTOR B BASE B EMITTER B ;; * 3 pins * 3 nets * 0 instances i Q0 npn18 C B E; area 4.0e-12 m 1 ; npn18, npn33 (backend) C B E Area Layer DMPNP DNW (triggered by NW) SP / AA SN / AA CT M1 Device Recognition E B C Device Layers Color and Fill Device Derivation Layer Derivation DMPNP Contains SN AND SP DMPNP AND SN And AA AND DNW NOT NW DMPNP AND SP And AA AND NW AND DNW DMPNP AND SN And AA AND NW NOT DNW 23.29 ind_rf – Top Metal Inductor Spectre Netlist Spectre Model Name = “ind_rf” L1 (PLUS MINUS) r=60u n=2.5 m=1 CDL Netlist CDL Device Name = “ind_rf” XL1 PLUS MINUS ind_rf R=60u N=2.5 M=1 Assura Netlist Assura auLvs Device Name = “ind_rf” C ind_rf Generic PLUS B MINUS B ;; n=2.5 r=60u * 2 pins * 2 nets * 0 instances i L1 ind_rf PLUS MINUS ; n 2.5 ; ind_rf (backend) Due to the complexity of the device, please refer to the PDK for information on the layout construction of this device Device Recognition PLUS MINUS Device Derivation Layer Derivation INDMY AND RFDEV AND M6 M6 AND RFDEV BUTTING INDMY M5 AND RFDEV BUTTING INDMY Parameter N R LVS Comparison Calculation Number of turns Inner radius of inductor 23.30 MIM Capacitors Devices – capm5 (Non-RF), mim_rf (RF) Spectre Netlist Spectre Model Name = “capm5” C1 (PLUS MINUS) mimcap c=606.875f m=1 CDL Netlist CDL Device Name = “capm5” XC1 PLUS MINUS capm5 C=606.875f M=1 Assura Netlist Assura auLvs Device Name = “capm5” c capm5 CAP PLUS B MINUS B ;; * 2 pins * 2 nets * 0 instances i C1 capm5 PLUS MINUS ; m 1 c 606.875f; capm5, mim_rf (backend) Due to the complexity of the device, please refer to the PDK for information on the layout construction of this device 23.31 RFMOS – RF Mos devices Devices – n18_ckt_rf, n33_ckt_rf, p18_ckt_rf, p33_ckt_rf Spectre Netlist Spectre Model Name = “n18_ckt_rf” / “n33_ckt_rf” / “p18_ckt_rf” / “p33_ckt_rf” MN1 (D G S B) n18_ckt_rf lr=0.18u wr=5.0u nf=12 m=1 CDL Netlist CDL Device Name = “n18_ckt_rf” / “n33_ckt_rf” / “p18_ckt_rf” / “p33_ckt_rf” XNM1 D G S B n18_ckt_rf WR=5u LR=180.0n NF=12 M=1.0 Assura Netlist Assura auLvs Device Name = “n18_ckt_rf” / “n33_ckt_rf” / “p18_ckt_rf” / “p33_ckt_rf” C n18_ckt_rf DRAIN B GATE B SOURCE B SUB B ;; * 4 pins * 4 nets * 0 instances i MN1 n18_ckt_rf D G S B ; m 1 lr 1.8e-07 wr 5e-06 nf 12 ; RFMOS (backend) Due to the complexity of the device, please refer to the PDK for information on the layout construction of this device 23.32 Varactor –Mos Varactors & Junction Diodes Devices – pvar18_ckt_rf, pvardio18_ckt_rf Spectre Netlist Spectre Model Name = “pvar18_ckt_rf” / “pvardio18_ckt_rf” C1 (PLUS MINUS) pvar18_ckt_rf nf=4 lr=1u wr=15u m=1 CDL Netlist CDL Device Name = “pvar18_ckt_rf” / “pvardio18_ckt_rf” XC1 PLUS MINUS pvar18_ckt_rf NF=4 LR=1u WR=15u M=1 Assura Netlist Assura auLvs Device Name = “pvar18_ckt_rf” / “pvardio18_ckt_rf” C pvar18_ckt_rf PLUS B MINUS B ;; * 2 pins * 2 nets * 0 instances i C1 pvar18_ckt_rf PLUS MINUS ; m 1 nf 4 lr 1u wr 15u ; Varactor (backend) Due to the complexity of the device, please refer to the PDK for information on the layout construction of this device 24 Known Problems & Solutions Problem: While extracting and comparing the npn bipolar devices supplied with the PDK, a stamp error is generated in the region between the DMPNP and NW layers. Although this does not affect the results of LVS, it does create a false error which could potentially mask real errors. Solution: Generate an additional DMPNP shape that completely encloses the NW shape currently in the fixed layouts. SMIC will address this in a future release of the fixed layouts. Problem: There are two sets of models for resistors. One set is two terminal model files, and the other set is three terminal subcircuit definitions that utilize the two terminal models as subcircuit components. The resistors implemented in this PDK are two terminal resistors. The resistor callback calculates resistance based upon equations documented in TD-MM18-SP-2001, pages 65-68. The equations for the calculation include ‘Rint’ and ‘Rc’. However, the terminal resistor models do not take these parameters into account. This results in a discrepancy between resistance value based on simulation and the one calculated in the callback. The mismatch is greatest in the non-silicided resistors since they have non-zero ‘Rint’ parameter values. Solution: SMIC will supply updated models in a future release. Problem: There is a mismatch between resistance value based on simulation and the one calculated in the callback for RF resistors. Solution: SMIC will supply updated models in a future release. Problem: The resistors in this PDK have a set of parameters for placement of dummy resistors segments on the left or right side of the resistor. To avoid extraction of the dummy segments during LVS, the dummy segments are placed without the recognition layer extending over them. This feature has been disabled on several of the resistors since without the recognition layer, DRC violation is reported on the dummies. These resistors include ‘rnwaa’, ‘rhrpo’, and ‘rhrpo_ckt_rf’. Solution: This feature may be enabled in a future release once the SMIC supplied DRC deck is updated to take this construct into account. 
