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Exynos 4412 RISC Microprocessor Public Version September 2012  2012 Samsung Electronics Co., Ltd. All rights reserved. Important Notice Samsung Electronics Co. Ltd. (“Samsung”) reserves the right to make changes to the information in this publication at any time without prior notice. All information provided is for reference purpose only. Samsung assumes no responsibility for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. This publication on its own does not convey any license, either express or implied, relating to any Samsung and/or third-party products, under the intellectual property rights of Samsung and/or any third parties. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. Customers are responsible for their own products and applications. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could reasonably be expected to create a situation where personal injury or death may occur. Customers acknowledge and agree that they are solely responsible to meet all other legal and regulatory requirements regarding their applications using Samsung products notwithstanding any information provided in this publication. Customer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim (including but not limited to personal injury or death) that may be associated with such unintended, unauthorized and/or illegal use. WARNING No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung. This publication is intended for use by designated recipients only. This publication contains confidential information (including trade secrets) of Samsung protected by Competition Law, Trade Secrets Protection Act and other related laws, and therefore may not be, in part or in whole, directly or indirectly publicized, distributed, photocopied or used (including in a posting on the Internet where unspecified access is possible) by any unauthorized third party. Samsung reserves its right to take any and all measures both in equity and law available to it and claim full damages against any party that misappropriates Samsung‟s trade secrets and/or confidential information. 警 告 本文件仅向经韩国三星电子株式会社授权的人员提供, 其内容含有商业秘密保护相关法规规定并受其保护的三星电 子株式会社商业秘密,任何直接或间接非法向第三人披露、 传播、复制或允许第三人使用该文件全部或部分内容的行为 (包括在互联网等公开媒介刊登该商业秘密而可能导致不特 定第三人获取相关信息的行为)皆为法律严格禁止。此等违 法行为一经发现,三星电子株式会社有权根据相关法规对其 采取法律措施,包括但不限于提出损害赔偿请求。 Copyright  2012 Samsung Electronics Co., Ltd. Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City, Gyeonggi-Do, Korea 446-711 Contact Us: mobilesol.cs@samsung.com Home Page: http://www.samsungsemi.com Trademarks All brand names, trademarks and registered trademarks belong to their respective owners.  Exynos, Exynos4412, FlexOneNAND, and OneNAND are trademarks of Samsung Electronics.  ARM, Jazelle, TrustZone, and Thumb are registered trademarks of ARM Limited.  Cortex, ETM, ETB, Coresight, ISA, and Neon are trademarks of ARM Limited.  Java is a trademark of Sun Microsystems, Inc.  SD is a registered trademark of Toshiba Corporation.  MMC and eMMC are trademarks of MultiMediaCard Association.  JTAG is a registered trademark of JTAG Technologies, Inc.  Synopsys is a registered trademark of Synopsys, Inc.  I2S is a trademark of Phillips Electronics.  I2C is a trademark of Phillips Semiconductor Corp.  MIPI and Slimbus are registered trademarks of the Mobile Industry Processor Interface (MIPI) Alliance. All other trademarks used in this publication are the property of their respective owners. Chip Handling Guide Precaution against Electrostatic Discharge When using semiconductor devices, ensure that the environment is protected against static electricity: 1. Wear antistatic clothes and use earth band. 2. All objects that are in direct contact with devices must be made up of materials that do not produce static electricity. 3. Ensure that the equipment and work table are earthed. 4. Use ionizer to remove electron charge. Contamination Do not use semiconductor products in an environment exposed to dust or dirt adhesion. Temperature/Humidity Semiconductor devices are sensitive to:  Environment  Temperature  Humidity High temperature or humidity deteriorates the characteristics of semiconductor devices. Therefore, do not store or use semiconductor devices in such conditions. Mechanical Shock Do not to apply excessive mechanical shock or force on semiconductor devices. Chemical Do not expose semiconductor devices to chemicals because exposure to chemicals leads to reactions that deteriorate the characteristics of the devices. Light Protection In non- Epoxy Molding Compound (EMC) package, do not expose semiconductor IC to bright light. Exposure to bright light causes malfunctioning of the devices. However, a few special products that utilize light or with security functions are exempted from this guide. Radioactive, Cosmic and X-ray Radioactive substances, cosmic ray, or X-ray may influence semiconductor devices. These substances or rays may cause a soft error during a device operation. Therefore, ensure to shield the semiconductor devices under environment that may be exposed to radioactive substances, cosmic ray, or X-ray. EMS (Electromagnetic Susceptibility) Strong electromagnetic wave or magnetic field may affect the characteristic of semiconductor devices during the operation under insufficient PCB circuit design for Electromagnetic Susceptibility (EMS). Revision History Revision No. Date 1.00 Sep. 17, 2012  Initial version Description Author(s) Chongkun Lee Table of Contents 1 PRODUCT OVERVIEW .................................................................................1-1 1.1 Introduction .............................................................................................................................................. 1-1 1.2 Features ................................................................................................................................................... 1-2 1.2.1 Multi-Core Processing Unit ............................................................................................................... 1-4 1.2.2 Memory Subsystem .......................................................................................................................... 1-5 1.2.3 Multimedia ........................................................................................................................................ 1-6 1.2.4 Audio Subsystem.............................................................................................................................. 1-8 1.2.5 Image Signal Processing Subsystem ............................................................................................... 1-8 1.2.6 Connectivity ...................................................................................................................................... 1-9 1.2.7 System Peripheral .......................................................................................................................... 1-11 1.3 Conventions ........................................................................................................................................... 1-13 1.3.1 Register RW Conventions .............................................................................................................. 1-13 1.3.2 Register Value Conventions ........................................................................................................... 1-13 2 MEMORY MAP ..............................................................................................2-1 2.1 Overview .................................................................................................................................................. 2-1 2.2 SFR Base Address .................................................................................................................................. 2-2 3 CHIP ID..........................................................................................................3-1 3.1 Overview .................................................................................................................................................. 3-1 3.2 Register Description................................................................................................................................. 3-2 3.2.1 Register Map Summary .................................................................................................................... 3-2 4 GENERAL PURPOSE INPUT/OUTPUT (GPIO) CONTROL .........................4-1 4.1 Overview .................................................................................................................................................. 4-1 4.2 Features ................................................................................................................................................... 4-3 4.2.1 Input/Output Description ................................................................................................................... 4-3 4.3 Register Description................................................................................................................................. 4-5 4.3.1 Registers Summary .......................................................................................................................... 4-5 4.3.2 Part 1 .............................................................................................................................................. 4-20 4.3.3 Part 2 ............................................................................................................................................ 4-124 4.3.4 Part 3 ............................................................................................................................................ 4-289 4.3.5 Part 4 ............................................................................................................................................ 4-298 5 CLOCK MANAGEMENT UNIT ......................................................................5-1 5.1 Overview .................................................................................................................................................. 5-1 5.2 Clock Declaration ..................................................................................................................................... 5-2 5.2.1 Clocks from Clock Pads ................................................................................................................... 5-2 5.2.2 Clocks from CMU.............................................................................................................................. 5-3 5.3 Clock Relationship ................................................................................................................................... 5-4 5.3.1 Recommended PLL PMS Value for APLL and MPLL ...................................................................... 5-6 5.3.2 Recommended PLL PMS Value for EPLL........................................................................................ 5-7 5.3.3 Recommended PLL PMS Value for VPLL........................................................................................ 5-8 5.4 Clock Generation ..................................................................................................................................... 5-9 5.5 Clock Configuration Procedure .............................................................................................................. 5-14 5.5.1 Clock Gating ................................................................................................................................... 5-15 5.5.2 Clock Diving .................................................................................................................................... 5-15 5.6 Special Clock Description ...................................................................................................................... 5-16 5.6.1 Special Clock Table ........................................................................................................................ 5-16 5.7 CLKOUT................................................................................................................................................. 5-19 5.8 I/O Description ....................................................................................................................................... 5-22 5.9 Register Description............................................................................................................................... 5-23 5.9.1 Register Map Summary .................................................................................................................. 5-25 6 INTERRUPT CONTROLLER .........................................................................6-1 6.1 Overview .................................................................................................................................................. 6-1 6.2 Features ................................................................................................................................................... 6-2 6.2.1 Security Extensions Support ............................................................................................................ 6-2 6.2.2 Implementation-Specific Configurable Features .............................................................................. 6-3 6.3 Interrupt Source ....................................................................................................................................... 6-4 6.3.1 Interrupt Sources Connection ........................................................................................................... 6-4 6.3.2 GIC Interrupt Table ........................................................................................................................... 6-5 6.4 Functional Overview .............................................................................................................................. 6-13 6.5 Register Description............................................................................................................................... 6-14 6.5.1 Register Map Summary .................................................................................................................. 6-14 7 INTERRUPT COMBINER ..............................................................................7-1 7.1 Overview .................................................................................................................................................. 7-1 7.2 Features ................................................................................................................................................... 7-1 7.3 Functional Description ............................................................................................................................. 7-2 7.3.1 Block Diagram .................................................................................................................................. 7-2 7.4 Interrupt Sources...................................................................................................................................... 7-3 7.4.1 Interrupt Combiner............................................................................................................................ 7-3 7.5 Functional Description ............................................................................................................................. 7-8 7.6 Register Description................................................................................................................................. 7-9 7.6.1 Register Map Summary .................................................................................................................... 7-9 7.6.2 Interrupt Combiner.......................................................................................................................... 7-10 8 DIRECT MEMORY ACCESS CONTROLLER (DMAC) .................................8-1 8.1 Overview .................................................................................................................................................. 8-1 8.2 Features ................................................................................................................................................... 8-2 8.3 Register Description................................................................................................................................. 8-5 8.3.1 Register Map Summary .................................................................................................................... 8-5 8.4 Instruction............................................................................................................................................... 8-14 9 SROM CONTROLLER...................................................................................9-1 9.1 Overview .................................................................................................................................................. 9-1 9.2 Features ................................................................................................................................................... 9-1 9.3 Block Diagram .......................................................................................................................................... 9-1 9.4 Functional Description ............................................................................................................................. 9-2 9.4.1 nWAIT Pin Operation........................................................................................................................ 9-2 9.4.2 Programmable Access Cycle ........................................................................................................... 9-3 9.5 I/O Description ......................................................................................................................................... 9-4 9.6 Register Description................................................................................................................................. 9-5 9.6.1 Register Map Summary .................................................................................................................... 9-5 10 NAND FLASH CONTROLLER ..................................................................10-1 10.1 Overview .............................................................................................................................................. 10-1 10.2 Features ............................................................................................................................................... 10-1 10.3 Functional Description ......................................................................................................................... 10-2 10.3.1 Block Diagram .............................................................................................................................. 10-2 10.3.2 NAND Flash Memory Timing ........................................................................................................ 10-3 10.4 Software Mode ..................................................................................................................................... 10-4 10.4.1 Data Register Configuration ......................................................................................................... 10-4 10.4.2 1/4/8/12/16-bit ECC ...................................................................................................................... 10-5 10.4.3 2048 Byte 1-bit ECC Parity Code Assignment Table ................................................................... 10-6 10.4.4 32 Byte 1-bit ECC Parity Code Assignment Table ....................................................................... 10-6 10.4.5 1-bit ECC Module Features .......................................................................................................... 10-6 10.4.6 1-bit ECC Programming Guide ..................................................................................................... 10-7 10.4.7 4-bit ECC Programming Guide (ENCODING) .............................................................................. 10-8 10.4.8 4-bit ECC Programming Guide (DECODING) .............................................................................. 10-9 10.4.9 8/12/16-bit ECC Programming Guide (ENCODING).................................................................. 10-10 10.4.10 8/12/16-bit ECC Programming Guide (DECODING)................................................................ 10-11 10.4.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC ........................................................ 10-12 10.4.12 Lock Scheme for Data Protection............................................................................................. 10-13 10.5 Programming Constraints .................................................................................................................. 10-14 10.6 I/O Description ................................................................................................................................... 10-14 10.7 Register Description........................................................................................................................... 10-15 10.7.1 Register Map Summary .............................................................................................................. 10-15 10.7.2 NAND Flash Interface and 1/4-bit ECC Registers...................................................................... 10-17 10.7.3 ECC Registers for 8, 12 and 16-bit ECC .................................................................................... 10-29 11 PULSE WIDTH MODULATION TIMER .....................................................11-1 11.1 Overview .............................................................................................................................................. 11-1 11.2 Features ............................................................................................................................................... 11-4 11.3 PWM Operation.................................................................................................................................... 11-5 11.3.1 Prescaler and Divider ................................................................................................................... 11-5 11.3.2 Basic Timer Operation .................................................................................................................. 11-6 11.3.3 Auto-Reload and Double Buffering............................................................................................... 11-8 11.3.4 Timer Operation Example............................................................................................................. 11-9 11.3.5 Initialize Timer (Setting Manual-Up Data and Inverter) .............................................................. 11-10 11.3.6 PWM ........................................................................................................................................... 11-10 11.3.7 During Current ISR. (Interrupt Service Routine) Output Level Control ...................................... 11-11 11.3.8 Dead Zone Generator................................................................................................................. 11-12 11.4 I/O Description ................................................................................................................................... 11-13 11.5 Register Description........................................................................................................................... 11-14 11.5.1 Register Map Summary .............................................................................................................. 11-14 12 WATCHDOG TIMER..................................................................................12-1 12.1 Overview .............................................................................................................................................. 12-1 12.2 Features ............................................................................................................................................... 12-1 12.3 Functional Description ......................................................................................................................... 12-2 12.3.1 WDT Operation............................................................................................................................. 12-2 12.3.2 WTDAT and WTCNT .................................................................................................................... 12-3 12.3.3 WDT Start ..................................................................................................................................... 12-3 12.3.4 Consideration of Debugging Environment.................................................................................... 12-3 12.4 Register Description............................................................................................................................. 12-4 12.4.1 Register Map Summary ................................................................................................................ 12-4 13 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER.........13-1 13.1 Overview .............................................................................................................................................. 13-1 13.2 Features ............................................................................................................................................... 13-0 13.3 UART Description ................................................................................................................................ 13-1 13.3.1 Data Transmission........................................................................................................................ 13-2 13.3.2 Data Reception ............................................................................................................................. 13-2 13.3.3 AFC............................................................................................................................................... 13-3 13.3.4 Example of Non AFC (Controlling nRTS and nCTS by Software) ............................................... 13-4 13.3.5 Trigger Level of Tx/Rx FIFO and DMA Burst Size in DMA Mode ................................................ 13-4 13.3.6 RS-232C Interface ........................................................................................................................ 13-4 13.3.7 Interrupt/DMA Request Generation .............................................................................................. 13-5 13.3.8 UART Error Status FIFO .............................................................................................................. 13-7 13.4 UART Input Clock Description ........................................................................................................... 13-10 13.5 I/O Description ................................................................................................................................... 13-11 13.6 Register Description........................................................................................................................... 13-12 13.6.1 Register Map Summary .............................................................................................................. 13-12 14 INTER-INTEGRATED CIRCUIT.................................................................14-1 14.1 Overview .............................................................................................................................................. 14-1 14.2 Features ............................................................................................................................................... 14-2 14.3 Functional Description ......................................................................................................................... 14-2 14.3.1 Block Diagram .............................................................................................................................. 14-2 14.4 I2C-Bus Interface Operation ................................................................................................................ 14-3 14.4.1 Start and Stop Conditions............................................................................................................. 14-4 14.4.2 Data Transfer Format ................................................................................................................... 14-5 14.4.3 ACK Signal Transmission ............................................................................................................. 14-6 14.4.4 Read-Write Operation................................................................................................................... 14-7 14.4.5 Bus Arbitration Procedures........................................................................................................... 14-7 14.4.6 Abort Conditions ........................................................................................................................... 14-7 14.4.7 Configuring I2C-Bus ..................................................................................................................... 14-7 14.4.8 Flowcharts of Operations in Each Mode ...................................................................................... 14-8 14.5 I/O Description ................................................................................................................................... 14-12 14.6 Register Description........................................................................................................................... 14-13 14.6.1 Register Map Summary .............................................................................................................. 14-13 15 SERIAL PERIPHERAL INTERFACE.........................................................15-1 15.1 Overview .............................................................................................................................................. 15-1 15.2 Features ............................................................................................................................................... 15-1 15.2.1 Operation of SPI ........................................................................................................................... 15-2 15.3 SPI Input Clock Description ................................................................................................................. 15-5 15.4 IO Description ...................................................................................................................................... 15-6 15.5 Register Description............................................................................................................................. 15-7 15.5.1 Register Map Summary ................................................................................................................ 15-7 16 DISPLAY CONTROLLER ..........................................................................16-1 16.1 Overview .............................................................................................................................................. 16-1 16.2 Features ............................................................................................................................................... 16-2 16.3 Functional Description ......................................................................................................................... 16-4 16.3.1 Brief Description ........................................................................................................................... 16-4 16.3.2 Data Flow...................................................................................................................................... 16-5 16.3.3 Overview of the Color Data .......................................................................................................... 16-8 16.3.4 Palette Usage ............................................................................................................................. 16-23 16.3.5 Window Blending ........................................................................................................................ 16-26 16.3.6 VTIME Controller Operation ....................................................................................................... 16-35 16.3.7 Virtual Display............................................................................................................................. 16-39 16.3.8 RGB Interface Specification ....................................................................................................... 16-40 16.3.9 LCD Indirect i80 System Interface.............................................................................................. 16-43 16.4 I/O Description ................................................................................................................................... 16-47 16.5 Register Description........................................................................................................................... 16-48 16.5.1 Register Map Summary .............................................................................................................. 16-49 16.5.2 Palette Memory........................................................................................................................... 16-56 16.5.3 Control Register .......................................................................................................................... 16-57 16.5.4 Gamma Lookup Table .............................................................................................................. 16-131 16.5.5 Shadow Windows Control ........................................................................................................ 16-134 16.5.6 Palette Ram .............................................................................................................................. 16-136 17 KEYPAD INTERFACE...............................................................................17-1 17.1 Overview .............................................................................................................................................. 17-1 17.2 Debouncing Filter ................................................................................................................................. 17-3 17.3 Filter Clock ........................................................................................................................................... 17-3 17.4 Wakeup Source.................................................................................................................................... 17-3 17.5 Keypad Scanning Procedure for Software Scan ................................................................................. 17-4 17.6 Keypad Scanning Procedure for Hardware Scan ................................................................................ 17-9 17.7 I/O Description ................................................................................................................................... 17-10 17.8 Register Description........................................................................................................................... 17-12 17.8.1 Register Map Summary .............................................................................................................. 17-12 18 ADC ...........................................................................................................18-1 18.1 Overview .............................................................................................................................................. 18-1 18.2 Features ............................................................................................................................................... 18-1 18.3 Functional Description ......................................................................................................................... 18-1 18.3.1 Block Diagram .............................................................................................................................. 18-1 18.3.2 ADC Selection .............................................................................................................................. 18-2 18.3.3 A/D Conversion Time.................................................................................................................... 18-2 18.3.4 ADC Conversion Mode ................................................................................................................. 18-2 18.3.5 Standby Mode............................................................................................................................... 18-3 18.4 ADC Input Clock Diagram .................................................................................................................... 18-4 18.5 I/O Descriptions.................................................................................................................................... 18-5 18.6 Register Description............................................................................................................................. 18-6 18.6.1 Register Map Summary ................................................................................................................ 18-6 List of Figures Figure Number Title Page Number Figure 4-1 GPIO Block Diagram ........................................................................................................................ 4-4 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Exynos 4412 Clock Generation Circuit (CPU, BUS, DRAM, ISP Clocks) ...................................... 5-11 Exynos 4412 Clock Generation Circuit (Special Clocks)................................................................ 5-13 Exynos 4412 CLKOUT Control Logic ............................................................................................. 5-19 Exynos 4412 Clock Controller Address Map .................................................................................. 5-24 Figure 6-1 Interrupt Sources Connection ........................................................................................................... 6-4 Figure 7-1 Block Diagram of Interrupt Combiner ............................................................................................... 7-2 Figure 8-1 Two DMA Tops ................................................................................................................................. 8-1 Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Block Diagram of SROMC Introduction ............................................................................................ 9-1 SROMC nWAIT Timing Diagram ...................................................................................................... 9-2 SROMC Read Timing Diagram ........................................................................................................ 9-3 SROMC Write Timing Diagram......................................................................................................... 9-3 Figure 10-1 Figure 10-2 Figure 10-3 Figure 10-4 NAND Flash Controller Block Diagram......................................................................................... 10-2 CLE and ALE Timing (TACLS = 1, TWRPH0 = 0, TWRPH1 = 0) ................................................ 10-3 nWE and nRE Timing (TWRPH0 = 0, TWRPH1 = 0) ................................................................... 10-3 Accessibility of NAND Area ........................................................................................................ 10-13 Figure 11-1 Figure 11-2 Figure 11-3 Figure 11-4 Figure 11-5 Figure 11-6 Figure 11-7 Figure 11-8 Simple Example of a PWM Cycle ................................................................................................. 11-2 PWM TIMER Clock Tree Diagram................................................................................................ 11-3 Timer Operations .......................................................................................................................... 11-6 Example of Double Buffering Feature .......................................................................................... 11-8 Example of a Timer Operation...................................................................................................... 11-9 Example of PWM ........................................................................................................................ 11-10 Inverter On/Off ............................................................................................................................ 11-11 Waveform when a Dead Zone Feature is Enabled..................................................................... 11-12 Figure 12-1 Watchdog Timer Block Diagram ................................................................................................... 12-2 Figure 13-1 Figure 13-2 Figure 13-3 Figure 13-4 Figure 13-5 Figure 13-6 Figure 13-7 Figure 13-8 Figure 13-9 Figure 13-10 Block Diagram of UART................................................................................................................ 13-1 UART AFC Interface ..................................................................................................................... 13-3 UART Receives the Five Characters Including Two Errors ......................................................... 13-7 IrDA Function Block Diagram ....................................................................................................... 13-8 Serial I/O Frame Timing Diagram (Normal UART) ....................................................................... 13-8 Infra-Red Transmit Mode Frame Timing Diagram ........................................................................ 13-9 Infra-Red Receive Mode Frame Timing Diagram......................................................................... 13-9 Input Clock Diagram for UART ................................................................................................... 13-10 nCTS and Delta CTS Timing Diagram ....................................................................................... 13-25 Block Diagram of UINTSP, UINTP, and UINTM....................................................................... 13-30 Figure 14-1 I2C-Bus Block Diagram ................................................................................................................ 14-2 Figure 14-2 Figure 14-3 Figure 14-4 Figure 14-5 Figure 14-6 Figure 14-7 Figure 14-8 Figure 14-9 Start and Stop Condition............................................................................................................... 14-4 I2C-Bus Interface Data Format..................................................................................................... 14-5 Data Transfer on the I2C-Bus....................................................................................................... 14-5 Acknowledgement on the I2C-Bus ............................................................................................... 14-6 Operations for Master/Transmitter Mode...................................................................................... 14-8 Operations for Master/Receiver Mode.......................................................................................... 14-9 Operations for Slave/Transmitter Mode...................................................................................... 14-10 Operations for Slave/Receiver Mode.......................................................................................... 14-11 Figure 15-1 Figure 15-2 Figure 15-3 SPI Transfer Format ..................................................................................................................... 15-4 Input Clock Diagram for SPI ......................................................................................................... 15-5 Auto Chip Select Mode Waveform (CPOL = 0, CPHA = 0, CH_WIDTH = Byte) ....................... 15-10 Figure 16-1 Figure 16-2 Figure 16-3 Figure 16-4 Figure 16-5 Figure 16-6 Figure 16-7 Figure 16-8 Figure 16-9 Figure 16-10 Figure 16-11 Figure 16-12 Figure 16-13 Figure 16-14 Figure 16-15 Figure 16-16 Figure 16-17 Figure 16-18 Figure 16-19 Figure 16-20 Figure 16-21 Figure 16-22 Figure 16-23 Figure 16-24 Figure 16-25 Figure 16-26 Figure 16-27 Figure 16-28 Figure 16-29 Figure 16-30 Figure 16-31 Block Diagram of Display Controller ............................................................................................. 16-1 Block Diagram of the Data Flow ................................................................................................... 16-6 Block Diagram of the Interface ..................................................................................................... 16-7 Memory Format of 25 BPP(A888) Display ................................................................................... 16-8 Memory Format of 32 BPP (8888) Display ................................................................................... 16-9 Memory Format of 24 BPP (A887) Display ................................................................................ 16-10 Memory Format of 24 BPP (888) Display................................................................................... 16-11 Memory Format of 19 BPP (A666) Display ................................................................................ 16-12 Memory Format of 18 BPP (666) Display ................................................................................... 16-13 Memory Format of 16 BPP (A555) Display .............................................................................. 16-14 Memory Format of 16 BPP (1555) Display............................................................................... 16-15 Memory Format of 16 BPP (565) Display ................................................................................. 16-16 16 BPP (5:6:5) Display Types................................................................................................... 16-17 Memory Format of 13 BPP (A444) Display .............................................................................. 16-18 Memory Format of 8 BPP (A232) Display ................................................................................ 16-19 Memory Format of 8 BPP Display ............................................................................................ 16-20 Memory Format of 4 BPP Display ............................................................................................ 16-21 Memory Format of 2 BPP Display ............................................................................................ 16-22 32 BPP (8:8:8:8) Palette Data Format ...................................................................................... 16-23 25 BPP (A: 8:8:8) Palette Data Format .................................................................................... 16-24 19 BPP (A: 6:6:6) Palette Data Format .................................................................................... 16-24 16 BPP (A: 5:5:5) Palette Data Format .................................................................................... 16-25 Blending Equation..................................................................................................................... 16-28 Blending Diagram ..................................................................................................................... 16-30 Blending Factor Decision .......................................................................................................... 16-31 Color-Key Function Configurations........................................................................................... 16-32 Blending and Color-Key Function ............................................................................................. 16-33 Blending Decision Diagram ...................................................................................................... 16-34 Example of Scrolling in Virtual Display ..................................................................................... 16-39 LCD RGB Interface Timing ....................................................................................................... 16-42 Indirect i80 System Interface Write Cycle Timing..................................................................... 16-45 Figure 17-1 Figure 17-2 Figure 17-3 Figure 17-4 Figure 17-5 Figure 17-6 Figure 17-7 Key Matrix Interface External Connection Guide.......................................................................... 17-2 Internal Debouncing Filter Operation............................................................................................ 17-3 Keypad Scanning Procedure ........................................................................................................ 17-4 Keypad Scanning Procedure II ..................................................................................................... 17-5 Keypad Scanning Procedure III .................................................................................................... 17-6 Keypad Scanning Procedure when the Two-key Pressed with Different Row ............................. 17-7 Keypad I/F Block Diagram ............................................................................................................ 17-8 Figure 18-1 Figure 18-2 Figure 18-3 Figure 18-4 ADC Top/Bottom Offset Error Diagram ........................................................................................ 18-1 ADC Functional Block Diagram .................................................................................................... 18-1 ADC Selection............................................................................................................................... 18-2 Input Clock Diagram for ADC & Touch Screen Interface ............................................................. 18-4 List of Tables Table Number Title Page Number Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Operating Frequencies in Exynos 4412............................................................................................. 5-1 APLL and MPLL PMS Value .............................................................................................................. 5-6 EPLL PMS Value ............................................................................................................................... 5-7 VPLL PMS Value ............................................................................................................................... 5-8 Special Clocks in Exynos 4412........................................................................................................ 5-16 I/O Clocks in Exynos 4412 ............................................................................................................... 5-18 CLKOUT Input Clock Selection Information .................................................................................... 5-20 I/O Description ................................................................................................................................. 5-22 Table 6-1 Table 6-2 Table 6-3 GIC Configuration Values .................................................................................................................. 6-3 GIC Interrupt Table (SPI[127:0]) ........................................................................................................ 6-5 GIC Interrupt Table (PPI[15:0]) ........................................................................................................ 6-12 Table 7-1 Interrupt Groups of Interrupt Combiner.............................................................................................. 7-3 Table 8-1 Features of DMA Controller ............................................................................................................... 8-2 Table 8-2 DMA Request Mapping Table ............................................................................................................ 8-2 Table 11-1 Minimum and Maximum Resolution Based on Prescaler and Clock Divider Values..................... 11-5 Table 13-1 Interrupts in Connection with FIFO ................................................................................................ 13-6 Table 16-1 Table 16-2 Table 16-3 Table 16-4 Table 16-5 Relation 16 BPP between VCLK and CLKVAL (TFT, Frequency of Video Clock Source = 60 MHz) 16-35 RGB Interface Signals of Display Controller ................................................................................ 16-40 LCD Indirect i80 System Interface Signals of Display Controller................................................. 16-43 Timing Reference Code (XY Definition)....................................................................................... 16-46 I/O Signals of Display Controller .................................................................................................. 16-47 Table 17-1 Keypad Inaterface I/O Description ............................................................................................... 17-10 List of Examples Example Number Title Page Number Example 16-1 Example 16-2 Example 16-3 Example 16-4 Example 16-5 Example 16-6 Example 16-7 Application............................................................................................................................... 16-26 Total Five Windows................................................................................................................. 16-26 Blending Equation ................................................................................................................... 16-27 Default Blending Equation ...................................................................................................... 16-28 Window Blending Factor Decision .......................................................................................... 16-30 Hue Equation ........................................................................................................................ 16-119 Coefficient Decision .............................................................................................................. 16-119 List of Conventions Register RW Access Type Conventions Type R W RW Definition Read Only Write Only Read & Write Description The application has permission to read the Register field. Writes to read-only fields have no effect. The application has permission to write in the Register field. The application has permission to read and writes in the Register field. The application sets this field by writing 1‟b1 and clears it by writing 1‟b0. Register Value Conventions Expression x X ? Device dependent Pin value Description Undefined bit Undefined multiple bits Undefined, but depends on the device or pin status The value depends on the device The value depends on the pin status Reset Value Conventions Expression 0 1 x Clears the register field Sets the register field Don't care condition Description Warning: Some bits of control registers are driven by hardware or write operation only. As a result the indicated reset value and the read value after reset might be different. Exynos 4412_UM 1 Product Overview 1 Product Overview 1.1 Introduction Exynos 4412 is a 32-bit RISC cost-effective, low power, performance optimized and Coretex-A9 Quad Core based micro-processor solution for smart phone applications. The memory system has dedicated DRAM ports and Static Memory port. The dedicated DRAM ports support LPDDR2 interface for high bandwidth. Static Memory Port supports NOR Flash and ROM type external memory and components. To reduce the total system cost and enhance the overall functionality, Exynos 4412 includes many hardware peripherals, such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, CSI-2, System Manager for power management, MIPI HSI, four UARTs, 24-channel DMA, Timers, General I/O Ports, three I2S, S/PDIF, eight IIC-BUS interface, three HS-SPI, USB Host 2.0, USB 2.0 Device operating at high speed (480 Mbps), two USB HSIC, four SD Host and high-speed Multimedia Card Interface, and four PLLs for clock generation. 1-1 Exynos 4412_UM 1 Product Overview 1.2 Features The features of Exynos 4412 are:  ARM Cortex-A9 based Quad CPU Subsystem with NEON  32/32/32/32 KB I/D Cache, 1 MB L2 Cache  Operating frequency up to 1.4 GHz  128-bit/64-bit Multi-layer bus architecture  Core-D domain for ARM Cortex-A9 Quad, CoreSight, and external memory interface  Operating frequency up to 200 MHz  Global D- domain mainly for multimedia components and external storage interfaces  Operating frequency up to 100 MHz  Core-P, Global-P domain mainly for other system component, such as system peripherals, peripheral DMAs, connectivity IPs and Audio interfaces.  Operating frequency up to 100 MHz  Audio domain for low power audio play  Advanced power management for mobile applications  64 KB ROM for secure booting and 256 KB RAM for security function  8-bit ITU 601/656 Camera Interface  2D Graphics Acceleration support.  1/2/4/ 8bpp Palletized or 8/16/24bpp Non-Palletized Color TFT recommend up to WXGA resolution  HDMI interface support for NTSC and PAL mode with image enhancer  MIPI-DSI and MIPI-CSI interface support  One AC-97 audio codec interface and 3-channel PCM serial audio interface  Three 24-bit I2S interface support  One TX only S/PDIF interface support for digital audio  Eight I2C interface support  Three SPI support  Four UART supports three Mbps ports for Bluetooth 2.0  On-chip USB 2.0 Device supports high-speed (480 Mbps, on-chip transceiver)  On-chip USB 2.0 Host support  Two on-chip USB HSIC  Four SD/ SDIO/HS-MMC interface support 1-2 Exynos 4412_UM 1 Product Overview  24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA)  Supports 14  8 key matrix  Configurable GPIOs  Real time clock, PLL, timer with PWM, and watch dog timer  Multi-core timer support for accurate tick time in power down mode (except sleep mode)  Memory Subsystem  Asynchronous SRAM/ ROM/NOR interface with x8 or x16 data bus  NAND interface with x8 data bus  LPDDR2 interface (800 Mbps/pin DDR) 1-3 Exynos 4412_UM 1 Product Overview 1.2.1 Multi-Core Processing Unit The features of main microprocessors are:  The ARM Cortex-A9 MPCore (quad core) processor integrates the proven and highly successful ARM MPCore technology along with further enhancements to simplify and broaden the adoption of multi-core solutions.  With the ability to scale in speed from 200 MHz to 1.4 GHz, the ARM Cortex-A9 MPCore quad processor meets the requirements of power-optimized mobile devices, which require operation in low power and performance-optimized consumer applications.  Other features of ARM Cortex-A9 MPCore quad core processor are:  Thumb-2 technology for greater performance, energy efficiency, and code density  NEONTM signal processing extensions  Jazelle RCT Java-acceleration technology  TrustZone technology for secure transactions and DRM  Floating-Point unit for significant acceleration for both single and double precision scalar Floating-Point operations  Optimized L1 caches for performance and power  Integrated 1 MB L2 Cache using standard compiled RAMs  Program Trace Macrocell and CoreSight  Generic Interrupt Controller  Supports three interrupt types o Software Generated Interrupt (SGI) o Private Peripheral Interrupt (PPI) o Shared Peripheral Interrupt (SPI)  Programmable interrupts that enable to set the o Security state for an interrupt o Priority level of an interrupt o Enabling or disabling of an interrupt o Processors that receive an interrupt  Enhanced security features 1-4 Exynos 4412_UM 1 Product Overview 1.2.2 Memory Subsystem The features of memory subsystem are:  High bandwidth Memory Matrix subsystem  Two independent external memory ports: o 1x16 Static Hybrid Memory port o 2x32 DRAM port  Matrix architecture increases the overall bandwidth with simultaneous access capability:  SRAM/ROM/NOR Interface o x8 or x16 data bus o Addresses range support: 23-bit o Supports asynchronous interface o Supports byte and half-word access  NAND Interface o Supports industry standard NAND interface o x8 data bus  LPDDR2 interface o x32 data bus up to 800 Mbps/pin o 1.2 V interface voltage o Density support up to 4-Gb per port (2CS) 1-5 Exynos 4412_UM 1 Product Overview 1.2.3 Multimedia The features of multimedia are:  Camera Interface  Multiple input support o ITU-R BT 601/656 mode o DMA (AXI 64-bit interface) mode o MIPI (CSI) mode o Direct FIFO mode (from LCDC)  Multiple output support o DMA (AXI 64-bit interface) mode o Direct FIFO mode (to LCDC)  Digital Zoom In (DZI) capability  Multiple camera input support  Programmable polarity of video sync signals  Image mirror and rotation (X-axis mirror, Y-axis mirror, 90, 180, and 270 rotation)  Various image formats generation  Capture frame control support  Image effect support  JPEG Codec supports:  Supported format of compression o Input raw image: YCbCr4:2:2 or RGB 565 o Output JPEG file: Baseline JPEG of YCbCr4:2:2 or YCbCr4:2:0  General-purpose color-space converter  2D Graphic Engine supports:  BitBLT  Window clipping, 90/180/270/Rotation, X Flip/Y Flip  Totally 4-operand raster operation (ROP4)  Alpha blending (user-specified constant alpha value/per-pixel alpha value)  8/16/24/32-bpp. Packed 24-bpp color format, Premultiplied/Non-premultiplied alpha format  1 bpp/4 bpp/8 bpp/16 bpp/32 bpp Mask format, YCbCr format 1-6 Exynos 4412_UM 1 Product Overview  Digital TV Interface supports:  High-Definition Multimedia Interface (HDMI) 1.4 a  Up to 1080 p 60 Hz and 8-channel/112 kHz/24-bit audio  480 p, 576 p, 720 p, 1080i (cannot support 480i)  HDCP V1.1  3D support  Rotator  Supported image format: YCbCr422 (Interleave), YCbCr420 (Non-interleave), and RGB565 and RGB888 (unpacked)  Supported rotate degree: 90, 180, 270, flip vertical, and flip horizontal  Video processor: The video processor supports:  BOB/2D-IPC mode  Production of YCbCr 4: 4: 4 output to help the mixer blend video and graphics  1/4X to 16X vertical scaling with 4-tap/16-phase polyphase filter  1/4X to 16X horizontal scaling with 8-tap/16-phase polyphase filter  Pan and scan, Letterbox, and NTSC/PAL conversion using scaling  Flexible scaled video positioning within display area  1/16 pixel resolution Pan and Scan modes  Flexible post video processing o Color saturation, brightness/contrast enhancement, edge enhancement o Color space conversion between BT.601 and BT.709  Video input source size up to 1920  1080  Video Mixer The Video Mixer supports:  Overlapping and blending input video and graphic layers  480p, 576p, 720p, and 1080i/p display size  Four layers (1 video layer, 2 graphic layer, and 1 background layer)  TFT-LCD Interface The TFT-LCD Interface supports:  24/18/16-bpp parallel RGB Interface LCD  8/6 bpp serial RGB Interface  Dual i80 Interface LCD  1/2/4/8 bpp Palletized or 8/16/24-bpp Non-Palletized Color TFT  Typical actual screen size: 1080  1024,1024  768, 800  480, 640  480, 320  240, 160  160, and so on  Virtual image up to 16M pixel (4K pixel  4K pixel)  Five Window Layers for PIP or OSD  Real-time overlay plane multiplexing  Programmable OSD window positioning  16-level alpha blending 1-7 Exynos 4412_UM 1.2.4 Audio Subsystem The features of audio subsystem are:  Reconfigurable Processor (RP) progresses audio processing  Low power audio subsystem  5.1 channel I2S with 32-bit-width 64-depth FIFO  128 KB audio play output buffer  Hardware mixer mixes primary and secondary sounds 1.2.5 Image Signal Processing Subsystem The features of ISP subsystem are:  Dual camera input  Image signal processing  Dynamic range correction  Face detection 1 Product Overview 1-8 Exynos 4412_UM 1 Product Overview 1.2.6 Connectivity The features of connectivity are:  PCM Audio Interface supports:  16-bit mono audio interface  Master mode only  3-port PCM interface  AC97 Audio Interface supports:  Independent channels for stereo PCM In, stereo PCM Out, and mono MIC In  16-bit stereo (2-channel) audio  Variable sampling rate AC97 Codec interface (48 kHz and below)  AC97 full specification  SPDIF Interface (TX only) supports:  Linear PCM up to 24-bit per sample support  2x24-bit buffers that are alternately filled with data  I2S Bus Interface supports:  Three I2S-bus for audio-codec interface with DMA-based operation  Serial and 8/16/24-bit per channel data transfers  I2S, MSB-justified, and LSB-justified data format  PCM 5.1 channel  Various bit clock frequency and codec clock frequency support o 16, 24, 32, and 48fs of bit clock frequency o 256, 384, 512, and 768fs of codec clock  One port for 5.1 channel I2S (in audio subsystem) and two ports for 2-channel I2S  I2C Bus Interface supports:  Eight Multi-Master IIC-Bus  Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbps in the standard mode  Up to 400 Kbps in the fast mode  MIPI-Slim bus Interface supports:  6 ports. Each port has 16 entry FIFO with 32-bit width  UART supports:  Four UART with DMA-based or interrupt-based operation  5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/ receive  Rx/Tx independent 256nbyte FIFO for UART0, 64 byte FIFO for UART1, and 16 byte FIFO for UART2/3/4  Programmable baud rate  IrDA 1.0 SIR (115.2 Kbps) mode  Loop back mode for testing  Non-integer clock divides in Baud clock generation 1-9 Exynos 4412_UM 1 Product Overview  USB 2.0 Device supports:  Complies to USB 2.0 Specification (Revision 1.0a) High-speed up to 480 Mbps  On-chip USB transceiver  USB Host 2.0 supports:  With the USB Host 2.0  High-speed up to 480 Mbps  On-chip USB transceiver  HS-MMC/SDIO Interface supports:  Multimedia Card Protocol version 4.3 compatible (HS-MMC)  SD Memory Card Protocol version 2.0 compatible  DMA based or interrupt based operation  128 word FIFO for Tx/Rx  Four ports HS-MMC or four ports SDIO  SPI Interface supports:  With three Serial Peripheral Interface Protocol version 2.11  Rx/Tx independent 64-Word FIFO for SPI0 and 16-Word FIFO for SPI1  DMA-based or interrupt-based operation  GPIO. 1-10 Exynos 4412_UM 1 Product Overview 1.2.7 System Peripheral The features of system peripheral are:  Real Time Clock  Full clock features: sec, min, hour, date, day, month, and year  32.768 kHz operation  Alarm interrupt  Time-tick interrupt  PLL  Four on-chip PLLs and APLL/MPLL/EPLL/VPLL  APLL generates ARM core and MSYS clocks  MPLL generates a system bus clock and special clocks  EPLL generates special clocks  VPLL generates clocks for video interface  Keypad  14  8 Key Matrix support  Provides internal de-bounce filter  Timer with Pulse Width Modulation  Five channel 32-bit internal timer with interrupt-based operation  Three channel 32-bit Timer with PWM  Programmable duty cycle, frequency, and polarity  Dead-zone generation  Supports external clock source  Multi-Core timer  64-bit global timer with four independent count comparators  Two 31-bit local timers  It can change interrupt interval without stopping reference tick timer DMA:  Micro-code programming based DMA  The specific instruction set provides flexibility to program DMA transfers  Supports linked list DMA function  Supports three enhanced built-in DMA with eight channels per DMA, so the total number of channels it supports are 32  Supports one Memory-to-memory type optimized DMA and two Peripheral-to-memory type optimized DMA  M2M DMA supports up to 16 burst and P2M DMA supports up to 8 burst  Watch Dog Timer  16-bit watch dog timer 1-11 Exynos 4412_UM 1 Product Overview  Thermal Management Unit (TMU)  Power Management  Clock-gating control for components  Various low power modes are available, such as Idle, Stop, Deep Stop, Deep Idle, and Sleep modes  Wake up sources in sleep mode are: o External interrupts o RTC alarm o Tick timer o Key interface  Wake up sources of Stop and Deep Stop mode are: o MMC o Touch screen interface o System timer o Entire wake up sources of Sleep mode  Wake up sources of Deep Idle mode are: o 5.1 channel I2S o Wake up source of Stop mode 1-12 Exynos 4412_UM 1 Product Overview 1.3 Conventions 1.3.1 Register RW Conventions Symbol R W RW R/WC R/WS Definition Read Only Write Only Read and Write Read and Write to clear Read and Write to set Description The application has permission to read the register field. Writes to read-only fields have no effect. The application has permission to write in the Register field. The application has permission to read and writes in the Register field. The application sets this field by writing 1‟b1 and clears it by writing 1‟b0. The application has permission to read and write in the register field. The application clears this field by writing 1‟b1. A register write of 1'b0 has no effect on this field. The application has permission to read and write in the register field. The application sets this field by writing 1‟b1. A register write of 1'b0 has no effect on this field. 1.3.2 Register Value Conventions Expression x X ? Device dependent Pin value Description Undefined bit Undefined multiple bits Undefined but depends on the device, or pin status The value depends on the device The value depends on the pin status 1-13 Exynos 4412_UM 2 Memory Map 2 Memory Map 2.1 Overview This section describes the base address of region. Base Address 0x0000_0000 0x0200_0000 0x0202_0000 0x0300_0000 0x0302_0000 0x0303_0000 0x0381_0000 0x0400_0000 0x0500_0000 0x0600_0000 0x0700_0000 0x0800_0000 0x0C00_0000 0x0CE0_0000 0x1000_0000 0x4000_0000 0xA000_0000 Limit Address 0x0001_0000 0x0201_0000 0x0206_0000 0x0302_0000 0x0303_0000 0x0303_9000 0x0383_0000 0x0500_0000 0x0600_0000 0x0700_0000 0x0800_0000 0x0C00_0000 0x0CD0_0000 0x0D00_0000 0x1400_0000 0xA000_0000 0x0000_0000 Size 64 KB 64 KB 256 KB 128 KB 64 KB 36 KB – 16 MB 16 MB 16 MB 16 MB 64 MB – – – 1.5 GB 1.5 GB Description iROM iROM (mirror of 0x0 to 0x10000) iRAM Data memory or general purpose of Samsung Reconfigurable Processor SRP. I-cache or general purpose of SRP. Configuration memory (write only) of SRP AudioSS's SFR region Bank0 of Static Read Only Memory Controller (SMC) (16-bit only) Bank1 of SMC Bank2 of SMC Bank3 of SMC Reserved Reserved SFR region of Nand Flash Controller (NFCON) SFR region Memory of Dynamic Memory Controller (DMC)-0 Memory of DMC-1 2-1 Exynos 4412_UM 2.2 SFR Base Address This section describes the base address of SFR. Base Address 0x1000_0000 0x1001_0000 0x1002_0000 0x1003_0000 0x1004_0000 0x1005_0000 0x1006_0000 0x1007_0000 0x100A_0000 0x100B_0000 0x100C_0000 0x1010_0000 0x1011_0000 0x1012_0000 0x1013_0000 0x1014_0000 0x1015_0000 0x1016_0000 0x1044_0000 0x1048_0000 0x1049_0000 0x1060_0000 0x1061_0000 0x106A_0000 0x106B_0000 0x106C_0000 0x1070_0000 0x1071_0000 0x1072_0000 0x1073_0000 0x1080_0000 0x1083_0000 0x1088_0000 0x1089_0000 IP CHIPID SYSREG Power Management Unit (PMU) CMU_TOP_PART CMU_CORE_ISP_PART Multi Core Timer (MCT) Watch Dog Timer (WDT) Real Time Clock (RTC) KEYIF HDMI_CEC Thermal Management Unit (TMU) SECKEY TZPC0 TZPC1 TZPC2 TZPC3 TZPC4 TZPC5 Int_combiner GIC_controller GIC_distributor DMC0 DMC1 PPMU_DMC_L PPMU_DMC_R PPMU_CPU TZASC_LR TZASC_LW TZASC_RR TZASC_RW G2D_ACP Security Sub System (SSS) Coresight Coresight 2 Memory Map 2-2 Exynos 4412_UM Base Address 0x108B_0000 0x10A4_0000 0x10A5_0000 0x1100_0000 0x1140_0000 0x1180_0000 0x1181_0000 0x1182_0000 0x1183_0000 0x1184_0000 0x1188_0000 0x1189_0000 0x11A2_0000 0x11A3_0000 0x11A4_0000 0x11A5_0000 0x11A6_0000 0x11C0_0000 0x11C8_0000 0x11E2_0000 0x1200_0000 0x1201_0000 0x1204_0000 0x1211_0000 0x1213_0000 0x1214_0000 0x1215_0000 0x1216_0000 0x1217_0000 0x1218_0000 0x1219_0000 0x121A_0000 0x121B_0000 0x121E_0000 0x121F_0000 0x1226_0000 0x1227_0000 IP Coresight SMMUG2D_ACP SMMUSSS GPIO_right GPIO_left FIMC0 FIMC1 FIMC2 FIMC3 JPEG MIPI_CSI0 MIPI_CSI1 SMMUFIMC0 SMMUFIMC1 SMMUFIMC2 SMMUFIMC3 SMMUJPEG FIMD0 MIPI_DSI0 SMMUFIMD0 FIMC_ISP FIMC_DRC_TOP FIMC_FD_TOP MPWM_ISP I2C0_ISP I2C1_ISP MTCADC_ISP PWM_ISP WDT_ISP MCUCTL_ISP UART_ISP SPI0_ISP SPI1_ISP GIC_C_ISP GIC_D_ISP sysMMU_FIMC-ISP sysMMU_FIMC-DRC 2-3 2 Memory Map Exynos 4412_UM Base Address 0x122A_0000 0x122B_0000 0x1239_0000 0x123A_0000 0x123B_0000 0x123C_0000 0x1248_0000 0x1249_0000 0x124A_0000 0x124B_0000 0x1250_0000 0x1251_0000 0x1252_0000 0x1253_0000 0x1254_0000 0x1255_0000 0x1256_0000 0x1257_0000 0x1258_0000 0x1259_0000 0x125B_0000 0x1268_0000 0x1269_0000 0x126C_0000 0x1281_0000 0x1284_0000 0x1285_0000 0x12A3_0000 0x12A4_0000 0x12C0_0000 0x12C1_0000 0x12D0_0000 0x12D1_0000 0x12D2_0000 0x12D3_0000 0x12D4_0000 0x12D5_0000 IP sysMMU_FIMC-FD sysMMU_ISPCPU FIMC_LITE0 FIMC_LITE1 sysMMU_FIMC-LITE0 sysMMU_FIMC-LITE1 USBDEV0 USBDEV0 USBDEV0 USBDEV0 Transport Stream Interface (TSI) SDMMC0 SDMMC1 SDMMC2 SDMMC3 SDMMC4 MIPI_HSI SROMC USBHOST0 USBHOST1 USBOTG1 PDMA0 PDMA1 General ADC Rotator sMDMA nsMDMA SMMURotator SMMUMDMA Video Processor (VP) Mixer HDMI0 HDMI1 HDMI2 HDMI3 HDMI4 HDMI5 2-4 2 Memory Map Exynos 4412_UM Base Address 0x12D6_0000 0x12E2_0000 0x1300_0000 0x1322_0000 0x1340_0000 0x1362_0000 0x1363_0000 0x1366_0000 0x1367_0000 0x1380_0000 0x1381_0000 0x1382_0000 0x1383_0000 0x1384_0000 0x1386_0000 0x1387_0000 0x1388_0000 0x1389_0000 0x138A_0000 0x138B_0000 0x138C_0000 0x138D_0000 0x138E_0000 0x1392_0000 0x1393_0000 0x1394_0000 0x1396_0000 0x1397_0000 0x1398_0000 0x1399_0000 0x139A_0000 0x139B_0000 0x139D_0000 2 Memory Map IP HDMI6 SMMUTV 3D Graphic Accelerator (G3D) PPMU_3D Multi Format Codec (MFC) SMMUMFC_L SMMUMFC_R PPMU_MFC_L PPMU_MFC_R Universal Asynchronous Receiver And Transmitter0 (UART) UART1 UART2 UART3 UART4 Inter-Integrated Circuit0 (I2C) I2C1 I2C2 I2C3 I2C4 I2C5 I2C6 I2C7 I2CHDMI Serial Peripheral Interface0 (SPI) SPI1 SPI2 I2S1 I2S2 PCM1 PCM2 AC97 SPDIF PWMTimer 2-5 Exynos 4412_UM 3 Chip ID 3 Chip ID 3.1 Overview The Exynos 4412 includes a Chip ID block for the Software (SW) that sends and receives Advanced Peripheral Bus (APB) interface signals to the bus system. 3-1 Exynos 4412_UM 3.2 Register Description 3.2.1 Register Map Summary  Base Address: 0x1000_0000 Register PRO_ID PACKAGE_ID Offset 0x0000 0x0004 Description Product information (ID, package, and revision) Package information (POP type and package) 3 Chip ID Reset Value 0xE441_2XXX 0xXXXX_XXXX 3.2.1.1 PRO_ID  Base Address: 0x1000_0000  Address = Base Address + 0x0000, Reset Value = 0xE441_2XXX Name Product ID RSVD Package MainRev SubRev Bit [31:12] [11:10] Type R R Product ID Reserved Description [9:8] R Package Information [7:4] R Main Revision Number [3:0] R Sub Revision Number Reset Value 0x4412 0x0 Exynos 4412: 0x2 0x1 0x1 NOTE: PRO_ID register[31:0] depends on the e-fuse ROM value. As power on sequence is progressing, it loads the e-fuse ROM values to the registers. It can read the loaded current e-fuse ROM values. An e-fuse ROM has main and sub revision numbers. 3.2.1.2 PACKAGE_ID  Base Address: 0x1000_0000  Address = Base Address + 0x0004, Reset Value = 0xXXXX_XXXX Name Package ID Bit [31:0] Type Description R Package information (POP type and package) NOTE: PACKAGE_ID register[31:0] depends on the e-fuse ROM value. Reset Value 0xXXXX_XXXX 3-2 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4 General Purpose Input/Output (GPIO) Control This chapter describes the General Purpose Input/Output (GPIO). 4.1 Overview Exynos 4412 contains 304 multi-functional input/output port pins and 164 memory port pins. There are 37 general port groups and two memory port groups. They are:  GPA0, GPA1: 14 in/out ports-3xUART with flow control, UART without flow control, and/or 2xI2C  GPB: 8 in/out ports-2xSPI and/or 2xI2C and/ or IEM  GPC0, GPC1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, and/or SPI  GPD0, GPD1: 8 in/out ports-PWM, 2xI2C, and/ or LCD I/F, MIPI  GPM0, GPM1, GPM2, GPM3, GPM4: 35 in/out ports-CAM I/F, and/ or TS I/F, HSI, and/ or Trace I/F  GPF0, GPF1, GPF2, GPF3: 30 in/out ports-LCD I/F  GPJ0, GPJ1: 13 in/out ports-CAM I/F  GPK0, GPK1, GPK2, GPK3: 28 in/out ports-4xMMC (4-bit MMC), and/or 2xMMC (8-bit MMC)), and/or GPS debugging I/F  GPL0, GPL1: 11 in/out ports-GPS I/F  GPL2: 8 in/out ports-GPS debugging I/F or Key pad I/F  GPX0, GPX1, GPX2, GPX3: 32 in/out ports-External wake-up, and/or Key pad I/F NOTE: These are in ALIVE region. 4-1 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control  GPZ: 7 in/out ports-low Power I2S and/or PCM  GPY0, GPY1, GPY2: 16 in/out ports-Control signals of EBI (SROM, NF, One NAND)  GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI (For more information about EBI configuration, refer to Chapter 5, and 6)  MP1_0-MP1_9: 78 DRAM1 ports NOTE: GPIO registers does not control these ports.  MP2_0-MP2_9: 78 DRAM2 ports NOTE: GPIO registers does not control these ports.  ETC0, ETC1, ETC6: 18 in/out ETC ports-JTAG, SLIMBUS, RESET, CLOCK  ETC7, ETC8 : 4 clock port for C2C Warning: When you do not use or connect port to an input pin without Pull-up/Pull-down then do not leave a port in Input Pull-up/Pull-down disable state. It may cause unexpected state and leakage current. Disable Pull-up/Pull-down when you use port as output function. 4-2 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.2 Features The features of GPIO include:  Controls 172 External Interrupts  Controls 32 External Wake-up Interrupts  252 multi-functional input/output ports  Controls pin states in Sleep Mode except GPX0, GPX1, GPX2, and GPX3 (GPX* pins are alive-pads) 4.2.1 Input/Output Description This section includes:  General Purpose Input/Output Block Diagram  Register Description 4-3 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.2.1.1 General Purpose Input/Output Block Diagram GPIO consists of two parts,  alive-part  off-part In Alive-part, you should supply power on sleep mode, but in off-part, it is not same. Therefore, registers in alivepart keep their values during sleep mode. Figure 4-1 illustrates the block diagram of GPIO. Register File Mux control Pad control APB Bus APB Interface External Interrupt Control Off Part Interrupt Controller Async Interface Mux control Register File External Interrupt Control Alive Part Figure 4-1 GPIO Block Diagram Pad control Interrupt Controller & Wake-up controller 4-4 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3 Register Description 4.3.1 Registers Summary  Base Address: 0x1140_0000 Register GPA0CON GPA0DAT GPA0PUD GPA0DRV GPA0CONPDN GPA0PUDPDN GPA1CON GPA1DAT GPA1PUD GPA1DRV GPA1CONPDN GPA1PUDPDN GPBCON GPBDAT GPBPUD GPBDRV GPBCONPDN GPBPUDPDN GPC0CON GPC0DAT GPC0PUD GPC0DRV GPC0CONPDN GPC0PUDPDN GPC1CON GPC1DAT GPC1PUD GPC1DRV GPC1CONPDN GPC1PUDPDN Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 Description Port group GPA0 configuration register Port group GPA0 data register Port group GPA0 pull-up/pull-down register Port group GPA0 drive strength control register Port group GPA0 power down mode configuration register Port group GPA0 power down mode pull-up/pull-down register Port group GPA1 configuration register Port group GPA1 data register Port group GPA1 pull-up/pull-down register Port group GPA1 drive strength control register Port group GPA1 power down mode configuration register Port group GPA1 power down mode pull-up/pull-down register Port group GPB configuration register Port group GPB data register Port group GPB pull-up/pull-down register Port group GPB drive strength control register Port group GPB power down mode configuration register Port group GPB power down mode pull-up/pull-down register Port group GPC0 configuration register Port group GPC0 data register Port group GPC0 Pull-up/pull-down register Port group GPC0 drive strength control register Port group GPC0 power down mode configuration register Port group GPC0 power down mode pull-up/pull-down register Port group GPC1 configuration register Port group GPC1 data register Port group GPC1 pull-up/pull-down register Port group GPC1 drive strength control register Port group GPC1 power down mode configuration register Port group GPC1 power down mode pull-up/pull-down Reset Value 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x0555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x0155 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x0155 0x00_0000 0x0000 0x0000 4-5 Exynos 4412_UM Register GPD0CON GPD0DAT GPD0PUD GPD0DRV GPD0CONPDN GPD0PUDPDN GPD1CON GPD1DAT GPD1PUD GPD1DRV GPD1CONPDN GPD1PUDPDN GPF0CON GPF0DAT GPF0PUD GPF0DRV GPF0CONPDN GPF0PUDPDN GPF1CON GPF1DAT GPF1PUD GPF1DRV GPF1CONPDN GPF1PUDPDN GPF2CON GPF2DAT GPF2PUD GPF2DRV GPF2CONPDN GPF2PUDPDN GPF3CON GPF3DAT 4 General Purpose Input/Output (GPIO) Control Offset 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x0180 0x0184 0x0188 0x018C 0x0190 0x0194 0x01A0 0x01A4 0x01A8 0x01AC 0x01B0 0x01B4 0x01C0 0x01C4 0x01C8 0x01CC 0x01D0 0x01D4 0x01E0 0x01E4 register Description Port group GPD0 configuration register Port group GPD0 data register Port group GPD0 pull-up/pull-down register Port group GPD0 drive strength control register Port group GPD0 power down mode configuration register Port group GPD0 power down mode pull-up/pull-down register Port group GPD1 configuration register Port group GPD1 data register Port group GPD1 Pull-up/pull-down register Port group GPD1 drive strength control register Port group GPD1 power down mode configuration register Port group GPD1 power down mode pull-up/pull-down register Port group GPF0 configuration register Port group GPF0 data register Port group GPF0 pull-up/pull-down register Port group GPF0 drive strength control register Port group GPF0 power down mode configuration register Port group GPF0 power down mode pull-up/pull-down register Port group GPF1 configuration register Port group GPF1 data register Port group GPF1 pull-up/pull-down register Port group GPF1 drive strength control register Port group GPF1 power down mode configuration register Port group GPF1 power down mode pull-up/pull-down register Port group GPF2 configuration register Port group GPF2 data register Port group GPF2 pull-up/pull-down register Port group GPF2 drive strength control register Port group GPF2 power down mode configuration register Port group GPF2 power down mode pull-up/pull-down register Port group GPF3 configuration register Port group GPF3 data register Reset Value 0x0000_0000 0x00 0x0055 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x0055 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 4-6 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Register GPF3PUD GPF3DRV GPF3CONPDN GPF3PUDPDN ETC1PUD ETC1DRV GPJ0CON GPJ0DAT GPJ0PUD GPJ0DRV GPJ0CONPDN GPJ0PUDPDN GPJ1CON GPJ1DAT GPJ1PUD GPJ1DRV GPJ1CONPDN GPJ1PUDPDN EXT_INT1_CON EXT_INT2_CON EXT_INT3_CON EXT_INT4_CON EXT_INT5_CON EXT_INT6_CON EXT_INT7_CON EXT_INT13_CON EXT_INT14_CON EXT_INT15_CON EXT_INT16_CON EXT_INT21_CON EXT_INT22_CON EXT_INT1_FLTCON0 EXT_INT1_FLTCON1 EXT_INT2_FLTCON0 Offset 0x01E8 0x01EC 0x01F0 0x01F4 0x0228 0x022C 0x0240 0x0244 0x0248 0x024C 0x0250 0x0254 0x0260 0x0264 0x0268 0x026C 0x0270 0x0274 0x0700 0x0704 0x0708 0x070C 0x0710 0x0714 0x0718 0x0730 0x0734 0x0738 0x073C 0x0740 0x0744 0x0800 0x0804 0x0808 Description Port group GPF3 pull-up/pull-down register Port group GPF3 drive strength control register Port group GPF3 power down mode configuration register Port group GPF3 power down mode pull-up/pull-down register Port group ETC1 pull-up/pull-down register Port group ETC1 drive strength control register Port group GPJ0 configuration register Port group GPJ0 data register Port group GPJ0 pull-up/pull-down register Port group GPJ0 drive strength control register Port group GPJ0 power down mode configuration register Port group GPJ0 power down mode pull-up/pull-down register Port group GPJ1 configuration register Port group GPJ1 data register Port group GPJ1 pull-up/pull-down register Port group GPJ1 drive strength control register Port group GPJ1 power down mode configuration register Port group GPJ1 power down mode pull-up/pull-down register External interrupt EXT_INT1 configuration register External interrupt EXT_INT2 configuration register External interrupt EXT_INT3 configuration register External interrupt EXT_INT4 configuration register External interrupt EXT_INT5 configuration register External interrupt EXT_INT6 configuration register External interrupt EXT_INT7 configuration register External interrupt EXT_INT13 configuration register External interrupt EXT_INT14 configuration register External interrupt EXT_INT15 configuration register External interrupt EXT_INT16 configuration register External interrupt EXT_INT21 configuration register External interrupt EXT_INT22 configuration register External interrupt EXT_INT1 filter configuration register 0 External interrupt EXT_INT1 filter configuration register 1 External interrupt EXT_INT2 filter configuration register 0 Reset Value 0x0555 0x00_0000 0x0000 0x0000 0x0005 0x00_0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x0155 0x00_0000 0x0000 0x0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 4-7 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Register EXT_INT2_FLTCON1 EXT_INT3_FLTCON0 EXT_INT3_FLTCON1 EXT_INT4_FLTCON0 EXT_INT4_FLTCON1 EXT_INT5_FLTCON0 EXT_INT5_FLTCON1 EXT_INT6_FLTCON0 EXT_INT6_FLTCON1 EXT_INT7_FLTCON0 EXT_INT7_FLTCON1 EXT_INT13_FLTCON0 EXT_INT13_FLTCON1 EXT_INT14_FLTCON0 EXT_INT14_FLTCON1 EXT_INT15_FLTCON0 EXT_INT15_FLTCON1 EXT_INT16_FLTCON0 EXT_INT16_FLTCON1 EXT_INT21_FLTCON0 EXT_INT21_FLTCON1 EXT_INT22_FLTCON0 EXT_INT22_FLTCON1 EXT_INT1_MASK EXT_INT2_MASK EXT_INT3_MASK EXT_INT4_MASK EXT_INT5_MASK EXT_INT6_MASK EXT_INT7_MASK EXT_INT13_MASK EXT_INT14_MASK EXT_INT15_MASK EXT_INT16_MASK EXT_INT21_MASK EXT_INT22_MASK EXT_INT1_PEND Offset 0x080C 0x0810 0x0814 0x0818 0x081C 0x0820 0x0824 0x0828 0x082C 0x0830 0x0834 0x0860 0x0864 0x0868 0x086C 0x0870 0x0874 0x0878 0x087C 0x0880 0x0884 0x0888 0x088C 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x0930 0x0934 0x0938 0x093C 0x0940 0x0944 0x0A00 Description External interrupt EXT_INT2 filter configuration register 1 External interrupt EXT_INT3 filter configuration register 0 External interrupt EXT_INT3 filter configuration register 1 External interrupt EXT_INT4 filter configuration register 0 External interrupt EXT_INT4 filter configuration register 1 External interrupt EXT_INT5 filter configuration register 0 External interrupt EXT_INT5 filter configuration register 1 External interrupt EXT_INT6 filter configuration register 0 External interrupt EXT_INT6 filter configuration register 1 External interrupt EXT_INT7 filter configuration register 0 External interrupt EXT_INT7 filter configuration register 1 External interrupt EXT_INT13 filter configuration register 0 External interrupt EXT_INT13 filter configuration register 1 External interrupt EXT_INT14 filter configuration register 0 External interrupt EXT_INT14 filter configuration register 1 External interrupt EXT_INT15 filter configuration register 0 External interrupt EXT_INT15 filter configuration register 1 External interrupt EXT_INT16 filter configuration register 0 External interrupt EXT_INT16 filter configuration register 1 External interrupt EXT_INT21 filter configuration register 0 External interrupt EXT_INT21 filter configuration register 1 External interrupt EXT_INT22 filter configuration register 0 External interrupt EXT_INT22 filter configuration register 1 External interrupt EXT_INT1 mask register External interrupt EXT_INT2 mask register External interrupt EXT_INT3 mask register External interrupt EXT_INT4 mask register External interrupt EXT_INT5 mask register External interrupt EXT_INT6 mask register External interrupt EXT_INT7 mask register External interrupt EXT_INT13 mask register External interrupt EXT_INT14 mask register External interrupt EXT_INT15 mask register External interrupt EXT_INT16 mask register External interrupt EXT_INT21 mask register External interrupt EXT_INT22 mask register External interrupt EXT_INT1 pending register Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_00FF 0x0000_003F 0x0000_00FF 0x0000_001F 0x0000_001F 0x0000_000F 0x0000_000F 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_003F 0x0000_00FF 0x0000_001F 0x0000_0000 4-8 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Register EXT_INT2_PEND EXT_INT3_PEND EXT_INT4_PEND EXT_INT5_PEND EXT_INT6_PEND EXT_INT7_PEND EXT_INT13_PEND EXT_INT14_PEND EXT_INT15_PEND EXT_INT16_PEND EXT_INT21_PEND EXT_INT22_PEND EXT_INT_SERVICE _XB EXT_INT_SERVICE _PEND_XB EXT_INT_GRPFIXPRI _XB EXT_INT1_FIXPRI EXT_INT2_FIXPRI EXT_INT3_FIXPRI EXT_INT4_FIXPRI EXT_INT5_FIXPRI EXT_INT6_FIXPRI EXT_INT7_FIXPRI EXT_INT13_FIXPRI EXT_INT14_FIXPRI EXT_INT15_FIXPRI EXT_INT16_FIXPRI EXT_INT21_FIXPRI EXT_INT22_FIXPRI PDNEN Offset 0x0A04 0x0A08 0x0A0C 0x0A10 0x0A14 0x0A18 0x0A30 0x0A34 0x0A38 0x0A3C 0x0A40 0x0A44 Description External interrupt EXT_INT2 pending register External interrupt EXT_INT3 pending register External interrupt EXT_INT4 pending register External interrupt EXT_INT5 pending register External interrupt EXT_INT6 pending register External interrupt EXT_INT7 pending register External interrupt EXT_INT13 pending register External interrupt EXT_INT14 pending register External interrupt EXT_INT15 pending register External interrupt EXT_INT16 pending register External interrupt EXT_INT21 pending register External interrupt EXT_INT22 pending register 0x0B08 Current service register 0x0B0C Current service pending register 0x0B10 External interrupt group fixed priority control register 0x0B14 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B44 0x0B48 0x0B4C 0x0B50 0x0B54 0x0B58 0x0F80 External interrupt 1 fixed priority control register External interrupt 2 fixed priority control register External interrupt 3 fixed priority control register External interrupt 4 fixed priority control register External interrupt 5 fixed priority control register External interrupt 6 fixed priority control register External interrupt 7 fixed priority control register External interrupt 13 fixed priority control register External interrupt 14 fixed priority control register External interrupt 15 fixed priority control register External interrupt 16 fixed priority control register External interrupt 21 fixed priority control register External interrupt 22 fixed priority control register Power down mode pad configure register Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x00 4-9 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control  Base Address: 0x1100_0000 Register GPK0CON GPK0DAT GPK0PUD GPK0DRV GPK0CONPDN GPK0PUDPDN GPK1CON GPK1DAT GPK1PUD GPK1DRV GPK1CONPDN GPK1PUDPDN GPK2CON GPK2DAT GPK2PUD GPK2DRV GPK2CONPDN GPK2PUDPDN GPK3CON GPK3DAT GPK3PUD GPK3DRV GPK3CONPDN GPK3PUDPDN GPL0CON GPL0DAT GPL0PUD GPL0DRV GPL0CONPDN GPL0PUDPDN GPL1CON GPL1DAT Offset 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00E0 0x00E4 Description Port group GPK0 configuration register Port group GPK0 data register Port group GPK0 pull-up/pull-down register Port group GPK0 drive strength control register Port group GPK0 power down mode configuration register Port group GPK0 power down mode pull-up/pull-down register Port group GPK1 configuration register Port group GPK1 data register Port group GPK1 pull-up/pull-down register Port group GPK1 drive strength control register Port group GPK1 power down mode configuration register Port group GPK1 power down mode pull-up/pull-down register Port group GPK2 configuration register Port group GPK2 data register Port group GPK2 pull-up/pull-down register Port group GPK2 drive strength control register Port group GPK2 power down mode configuration register Port group GPK2 power down mode pull-up/pull-down register Port group GPK3 configuration register Port group GPK3 data register Port group GPK3 pull-up/pull-down register Port group GPK3 drive strength control register Port group GPK3 power down mode configuration register Port group GPK3 power down mode pull-up/pull-down register Port group GPL0 configuration register Port group GPL0 data register Port group GPL0 pull-up/pull-down register Port group GPL0 drive strength control register Port group GPL0 power down mode configuration register Port group GPL0 power down mode pull-up/pull-down register Port group GPL1 configuration register Port group GPL1 data register Reset Value 0x0000_0000 0x00 0x1555 0x00_2AAA 0x0000 0x0000 0x0000_0000 0x00 0x1555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x1555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x1555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x1555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 4-10 Exynos 4412_UM Register GPL1PUD GPL1DRV GPL1CONPDN GPL1PUDPDN GPL2CON GPL2DAT GPL2PUD GPL2DRV GPL2CONPDN GPL2PUDPDN GPY0CON GPY0DAT GPY0PUD GPY0DRV GPY0CONPDN GPY0PUDPDN GPY1CON GPY1DAT GPY1PUD GPY1DRV GPY1CONPDN GPY1PUDPDN GPY2CON GPY2DAT GPY2PUD GPY2DRV GPY2CONPDN GPY2PUDPDN GPY3CON GPY3DAT GPY3PUD GPY3DRV GPY3CONPDN 4 General Purpose Input/Output (GPIO) Control Offset 0x00E8 0x00EC 0x00F0 0x00F4 0x0100 0x0104 0x0108 0x010C 0x0110 0x0114 0x0120 0x0124 0x0128 0x012C 0x0130 0x0134 0x0140 0x0144 0x0148 0x014C 0x0150 0x0154 0x0160 0x0164 0x0168 0x016C 0x0170 0x0174 0x0180 0x0184 0x0188 0x018C 0x0190 Description Port group GPL1 pull-up/pull-down register Port group GPL1 drive strength control register Port group GPL1 power down mode configuration register Port group GPL1 power down mode pull-up/pull-down register Port group GPL2 configuration register Port group GPL2 data register Port group GPL2 pull-up/pull-down register Port group GPL2 drive strength control register Port group GPL2 power down mode configuration register Port group GPL2 power down mode pull-up/pull-down register Port group GPY0 configuration register Port group GPY0 data register Port group GPY0 pull-up/pull-down register Port group GPY0 drive strength control register Port group GPY0 power down mode configuration register Port group GPY0 power down mode pull-up/pull-down register Port group GPY1 configuration register Port group GPY1 data register Port group GPY1 pull-up/pull-down register Port group GPY1 drive strength control register Port group GPY1 power down mode configuration register Port group GPY1 power down mode pull-up/pull-down register Port group GPY2 configuration register Port group GPY2 data register Port group GPY2 pull-up/pull-down register Port group GPY2 drive strength control register Port group GPY2 power down mode configuration register Port group GPY2 power down mode pull-up/pull-down register Port group GPY3 configuration register Port group GPY3 data register Port group GPY3 pull-up/pull-down register Port group GPY3 drive strength control register Port group GPY3 power down mode configuration register Reset Value 0x0005 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x0FFF 0x00_0AAA 0x0000 0x0000 0x0000_0000 0x00 0x00FF 0x00_00AA 0x0000 0x0000 0x0000_0000 0x00 0x0FFF 0x00_0AAA 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_AAAA 0x0000 4-11 Exynos 4412_UM Register GPY3PUDPDN GPY4CON GPY4DAT GPY4PUD GPY4DRV GPY4CONPDN GPY4PUDPDN GPY5CON GPY5DAT GPY5PUD GPY5DRV GPY5CONPDN GPY5PUDPDN GPY6CON GPY6DAT GPY6PUD GPY6DRV GPY6CONPDN GPY6PUDPDN ETC0PUD ETC0DRV ETC6PUD ETC6DRV GPM0CON GPM0DAT GPM0PUD GPM0DRV GPM0CONPDN GPM0PUDPDN GPM1CON GPM1DAT GPM1PUD GPM1DRV 4 General Purpose Input/Output (GPIO) Control Offset 0x0194 0x01A0 0x01A4 0x01A8 0x01AC 0x01B0 0x01B4 0x01C0 0x01C4 0x01C8 0x01CC 0x01D0 0x01D4 0x01E0 0x01E4 0x01E8 0x01EC 0x01F0 0x01F4 0x0208 0x020C 0x0228 0x022C 0x0260 0x0264 0x0268 0x026C 0x0270 0x0274 0x0280 0x0284 0x0288 0x028C Description Port group GPY3 power down mode pull-up/pull-down register Port group GPY4 configuration register Port group GPY4 data register Port group GPY4 pull-up/pull-down register Port group GPY4 drive strength control register Port group GPY4 power down mode configuration register Port group GPY4 power down mode pull-up/pull-down register Port group GPY5 configuration register Port group GPY5 data register Port group GPY5 pull-up/pull-down register Port group GPY5 drive strength control register Port group GPY5 power down mode configuration register Port group GPY5 power down mode pull-up/pull-down register Port group GPY6 configuration register Port group GPY6 data register Port group GPY6 pull-up/pull-down register Port group GPY6 drive strength control register Port group GPY6 power down mode configuration register Port group GPY6 power down mode pull-up/pull-down register Port group ETC0 pull-up/pull-down register Port group ETC0 drive strength control register Port group ETC6 pull-up/pull-down register Port group ETC6 drive strength control register Port group GPM0 configuration register Port group GPM0 data register Port group GPM0 pull-up/pull-down register Port group GPM0 drive strength control register Port group GPM0 power down mode configuration register Port group GPM0 power down mode pull-up/pull-down register Port group GPM1 configuration register Port group GPM1 data register Port group GPM1 pull-up/pull-down register Port group GPM1 drive strength control register Reset Value 0x0000 0x0000_0000 0x00 0x5555 0x00_AAAA 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_AAAA 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_AAAA 0x0000 0x0000 0x0400 0x00_0000 0xC000 0x00_0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x1555 0x00_0000 4-12 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Register GPM1CONPDN GPM1PUDPDN GPM2CON GPM2DAT GPM2PUD GPM2DRV GPM2CONPDN GPM2PUDPDN GPM3CON GPM3DAT GPM3PUD GPM3DRV GPM3CONPDN GPM3PUDPDN GPM4CON GPM4DAT GPM4PUD GPM4DRV GPM4CONPDN GPM4PUDPDN EXT_INT23_CON EXT_INT24_CON EXT_INT25_CON EXT_INT26_CON EXT_INT27_CON EXT_INT28_CON EXT_INT29_CON EXT_INT8_CON EXT_INT9_CON EXT_INT10_CON EXT_INT11_CON EXT_INT12_CON EXT_INT23_FLTCON0 EXT_INT23_FLTCON1 Offset 0x0290 0x0294 0x02A0 0x02A4 0x02A8 0x02AC 0x02B0 0x02B4 0x02C0 0x02C4 0x02C8 0x02CC 0x02D0 0x02D4 0x02E0 0x02E4 0x02E8 0x02EC 0x02F0 0x02F4 0x0708 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0x072C 0x0730 0x0734 0x0810 0x0814 Description Port group GPM1 power down mode configuration register Port group GPM1 power down mode pull-up/pull-down register Port group GPM2 configuration register Port group GPM2 data register Port group GPM2 pull-up/pull-down register Port group GPM2 drive strength control register Port group GPM2 power down mode configuration register Port group GPM2 power down mode pull-up/pull-down register Port group GPM3 configuration register Port group GPM3 data register Port group GPM3 pull-up/pull-down register Port group GPM3 drive strength control register Port group GPM3 power down mode configuration register Port group GPM3 power down mode pull-up/pull-down register Port group GPM4 configuration register Port group GPM4 data register Port group GPM4 pull-up/pull-down register Port group GPM4 drive strength control register Port group GPM4 power down mode configuration register Port group GPM4 power down mode pull-up/pull-down register External interrupt EXT_INT23 configuration register External interrupt EXT_INT24 configuration register External interrupt EXT_INT25 configuration register External interrupt EXT_INT26 configuration register External interrupt EXT_INT27 configuration register External interrupt EXT_INT28 configuration register External interrupt EXT_INT29 configuration register External interrupt EXT_INT8 configuration register External interrupt EXT_INT9 configuration register External interrupt EXT_INT10 configuration register External interrupt EXT_INT11 configuration register External interrupt EXT_INT12 configuration register External interrupt EXT_INT23 filter configuration register 0 External interrupt EXT_INT23 filter configuration register 1 Reset Value 0x0000 0x0000 0x0000_0000 0x00 0x0155 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 4-13 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Register EXT_INT24_FLTCON0 EXT_INT24_FLTCON1 EXT_INT25_FLTCON0 EXT_INT25_FLTCON1 EXT_INT26_FLTCON0 EXT_INT26_FLTCON1 EXT_INT27_FLTCON0 EXT_INT27_FLTCON1 EXT_INT28_FLTCON0 EXT_INT28_FLTCON1 EXT_INT29_FLTCON0 EXT_INT29_FLTCON1 EXT_INT8_FLTCON0 EXT_INT8_FLTCON1 EXT_INT9_FLTCON0 EXT_INT9_FLTCON1 EXT_INT10_FLTCON0 EXT_INT10_FLTCON1 EXT_INT11_FLTCON0 EXT_INT11_FLTCON1 EXT_INT12_FLTCON0 EXT_INT12_FLTCON1 EXT_INT23_MASK EXT_INT24_MASK EXT_INT25_MASK EXT_INT26_MASK EXT_INT27_MASK EXT_INT28_MASK EXT_INT29_MASK EXT_INT8_MASK EXT_INT9_MASK EXT_INT10_MASK EXT_INT11_MASK EXT_INT12_MASK EXT_INT23_PEND EXT_INT24_PEND EXT_INT25_PEND Offset 0x0818 0x081C 0x0820 0x0824 0x0828 0x082C 0x0830 0x0834 0x0838 0x083C 0x0840 0x0844 0x0848 0x084C 0x0850 0x0854 0x0858 0x085C 0x0860 0x0864 0x0868 0x086C 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0920 0x0924 0x0928 0x092C 0x0930 0x0934 0x0A08 0x0A0C 0x0A10 Description External interrupt EXT_INT24 filter configuration register 0 External interrupt EXT_INT24 filter configuration register 1 External interrupt EXT_INT25 filter configuration register 0 External interrupt EXT_INT25 filter configuration register 1 External interrupt EXT_INT26 filter configuration register 0 External interrupt EXT_INT26 filter configuration register 1 External interrupt EXT_INT27 filter configuration register 0 External interrupt EXT_INT27 filter configuration register 1 External interrupt EXT_INT28 filter configuration register 0 External interrupt EXT_INT28 filter configuration register 1 External interrupt EXT_INT29 filter configuration register 0 External interrupt EXT_int29 filter configuration register 1 External interrupt EXT_INT8 filter configuration register 0 External interrupt EXT_INT8 filter configuration register 1 External interrupt EXT_INT9 filter configuration register 0 External interrupt EXT_INT9 filter configuration register 1 External interrupt EXT_INT10 filter configuration register 0 External interrupt EXT_INT10 filter configuration register 1 External interrupt EXT_INT11 filter configuration register 0 External interrupt EXT_INT11 filter configuration register 1 External interrupt EXT_INT12 filter configuration register 0 External interrupt EXT_INT12 filter configuration register 1 External interrupt EXT_INT23 mask register External interrupt EXT_INT24 mask register External interrupt EXT_INT25 mask register External interrupt EXT_INT26 mask register External interrupt EXT_INT27 mask register External interrupt EXT_INT28 mask register External interrupt EXT_INT29 mask register External interrupt EXT_INT8 mask register External interrupt EXT_INT9 mask register External interrupt EXT_INT10 mask register External interrupt EXT_INT11 mask register External interrupt EXT_INT12 mask register External interrupt EXT_INT23 pending register External interrupt EXT_INT24 pending register External interrupt EXT_INT25 pending register Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_007F 0x0000_007F 0x0000_007F 0x0000_007F 0x0000_007F 0x0000_0003 0x0000_00FF 0x0000_00FF 0x0000_007F 0x0000_001F 0x0000_00FF 0x0000_00FF 0x0000_0000 0x0000_0000 0x0000_0000 4-14 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Register EXT_INT26_PEND EXT_INT27_PEND EXT_INT28_PEND EXT_INT29_PEND EXT_INT8_PEND EXT_INT9_PEND EXT_INT10_PEND EXT_INT11_PEND EXT_INT12_PEND EXT_INT_SERVICE _XA EXT_INT_SERVICE _PEND_XA EXT_INT_GRPFIXPRI _XA EXT_INT23_FIXPRI EXT_INT24_FIXPRI EXT_INT25_FIXPRI EXT_INT26_FIXPRI EXT_INT27_FIXPRI EXT_INT28_FIXPRI EXT_INT29_FIXPRI EXT_INT8_FIXPRI EXT_INT9_FIXPRI EXT_INT10_FIXPRI EXT_INT11_FIXPRI EXT_INT12_FIXPRI GPX0CON GPX0DAT GPX0PUD GPX0DRV GPX1CON GPX1DAT GPX1PUD GPX1DRV GPX2CON GPX2DAT Offset 0x0A14 0x0A18 0x0A1C 0x0A20 0x0A24 0x0A28 0x0A2C 0x0A30 0x0A34 Description External interrupt EXT_INT26 pending register External interrupt EXT_INT27 pending register External interrupt EXT_INT28 pending register External interrupt EXT_INT29 pending register External interrupt EXT_INT8 pending register External interrupt EXT_INT9 pending register External interrupt EXT_INT10 pending register External interrupt EXT_INT11 pending register External interrupt EXT_INT12 pending register 0x0B08 Current service register 0x0B0C Current service pending register 0x0B10 External interrupt group fixed priority control register 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0C00 0x0C04 0x0C08 0x0C0C 0x0C20 0x0C24 0x0C28 0x0C2C 0x0C40 0x0C44 External interrupt 23 fixed priority control register External interrupt 24 fixed priority control register External interrupt 25 fixed priority control register External interrupt 26 fixed priority control register External interrupt 27 fixed priority control register External interrupt 28 fixed priority control register External interrupt 29 fixed priority control register External interrupt 8 fixed priority control register External interrupt 9 fixed priority control register External interrupt 10 fixed priority control register External interrupt 11 fixed priority control register External interrupt 12 fixed priority control register Port group GPX0 configuration register Port group GPX0 data register Port group GPX0 pull-up/pull-down register Port group GPX0 drive strength control register Port group GPX1 configuration register Port group GPX1 data register Port group GPX1 pull-up/pull-down register Port group GPX1 drive strength control register Port group GPX2 configuration register Port group GPX2 data register Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000_0000 0x00 4-15 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Register GPX2PUD GPX2DRV GPX3CON GPX3DAT GPX3PUD GPX3DRV EXT_INT40_CON EXT_INT41_CON EXT_INT42_CON EXT_INT43_CON EXT_INT40_FLTCON0 EXT_INT40_FLTCON1 EXT_INT41_FLTCON0 EXT_INT41_FLTCON1 EXT_INT42_FLTCON0 EXT_INT42_FLTCON1 EXT_INT43_FLTCON0 EXT_INT43_FLTCON1 EXT_INT40_MASK EXT_INT41_MASK EXT_INT42_MASK EXT_INT43_MASK EXT_INT40_PEND EXT_INT41_PEND EXT_INT42_PEND EXT_INT43_PEND PDNEN Offset 0x0C48 0x0C4C 0x0C60 0x0C64 0x0C68 0x0C6C 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E80 0x0E84 0x0E88 0x0E8C 0x0E90 0x0E94 0x0E98 0x0E9C 0x0F00 0x0F04 0x0F08 0x0F0C 0x0F40 0x0F44 0x0F48 0x0F4C 0x0F80 Description Port group GPX2 pull-up/pull-down register Port group GPX2 drive strength control register Port group GPX3 configuration register Port group GPX3 data register Port group GPX3 pull-up/pull-down register Port group GPX3 drive strength control register External interrupt EXT_INT40 configuration register External interrupt EXT_INT41 configuration register External interrupt EXT_INT42 configuration register External interrupt EXT_INT43 configuration register External Interrupt EXT_INT40 filter configuration register 0 External interrupt EXT_INT40 filter configuration register 1 External interrupt EXT_INT41 filter configuration register 0 External interrupt EXT_INT41 filter configuration register 1 External interrupt EXT_INT42 filter configuration register 0 External interrupt EXT_INT42 filter configuration register 1 External interrupt EXT_INT43 filter configuration register 0 External interrupt EXT_INT43 filter configuration register 1 External interrupt EXT_INT40 mask register External interrupt EXT_INT41 mask register External interrupt EXT_INT42 mask register External interrupt EXT_INT43 mask register External interrupt EXT_INT40 pending register External interrupt EXT_INT41 pending register External interrupt EXT_INT42 pending register External interrupt EXT_INT43 pending register Power down mode pad configure register Reset Value 0x5555 0x00_0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x8080_8080 0x8080_8080 0x8080_8080 0x8080_8080 0x8080_8080 0x8080_8080 0x8080_8080 0x8080_8080 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x00 4-16 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control  Base Address: 0x0386_0000 Register GPZCON GPZDAT GPZPUD GPZDRV GPZCONPDN GPZPUDPDN EXT_INT50_CON EXT_INT50_FLTCON0 EXT_INT50_FLTCON1 EXT_INT50_MASK EXT_INT50_PEND EXT_INT_SERVICE _XD EXT_INT_SERVICE _PEND_XD EXT_INT_GRPFIXPRI _XD EXT_INT50_FIXPRI PDNEN Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0700 0x0800 0x0804 0x0900 0x0A00 0x0B08 0x0B0C 0x0B10 0x0B14 0x0F80 Description Port group GPIO group Z (GPZ) configuration register Port group GPZ data register Port group GPZ pull-up/pull-down register Port group GPZ drive strength control register Port group GPZ power down mode configuration register Port group GPZ power down mode pull-up/pull-down register External interrupt EXT_INT50 configuration register External interrupt EXT_INT50 filter configuration register 0 External interrupt EXT_INT50 filter configuration register 1 External interrupt EXT_INT50 mask register External interrupt EXT_INT50 pending register Current service register Current service pending register External interrupt group fixed priority control register External interrupt 50 fixed priority control register Power down mode pad configure register Reset Value 0x0000_0000 0x00 0x1555 0x00_0000 0x0000 0x0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_007F 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x00  Base Address: 0x106E_0000 Register GPV0CON GPV0DAT GPV0PUD GPV0DRV GPV0CONPDN GPV0PUDPDN GPV1CON GPV1DAT GPV1PUD GPV1DRV GPV1CONPDN GPV1PUDPDN Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 Description Port group GPV0 configuration register Port group GPV0 data register Port group GPV0 pull-up/pull-down register Port group GPV0 drive strength control register Port group GPV0 power down mode configuration register Port group GPV0 power down mode pull-up/pull-down register Port group GPV1 configuration register Port group GPV1 data register Port group GPV1 pull-up/pull-down register Port group GPV1 drive strength control register Port group GPV1 power down mode configuration register Port group GPV1 power down mode pull-up/pull-down register Reset Value 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 4-17 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Register ETC7PUD ETC7DRV GPV2CON GPV2DAT GPV2PUD GPV2DRV GPV2CONPDN GPV2PUDPDN GPV3CON GPV3DAT GPV3PUD GPV3DRV GPV3CONPDN GPV3PUDPDN ETC8PUD ETC8DRV GPV4CON GPV4DAT GPV4PUD GPV4DRV GPV4CONPDN GPV4PUDPDN EXT_INT30_CON EXT_INT31_CON EXT_INT32_CON EXT_INT33_CON EXT_INT34_CON EXT_INT30_FLTCON0 EXT_INT30_FLTCON1 EXT_INT31_FLTCON0 EXT_INT31_FLTCON1 EXT_INT32_FLTCON0 EXT_INT32_FLTCON1 EXT_INT33_FLTCON0 Offset 0x0048 0x004C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x00A8 0x00AC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x0700 0x0704 0x0708 0x070C 0x0710 0x0800 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 Description Port group ETC7 pull-up/pull-down register Port group ETC7 drive strength control register Port group GPV2 configuration register Port group GPV2 data register Port group GPV2 pull-up/pull-down register Port group GPV2 drive strength control register Port group GPV2 power down mode configuration register Port group GPV2 power down mode pull-up/pull-down register Port group GPV3 configuration register Port group GPV3 data register Port group GPV3 pull-up/pull-down register Port group GPV3 drive strength control register Port group GPV3 power down mode configuration register Port group GPV3 power down mode pull-up/pull-down register Port group ETC8 pull-up/pull-down register Port group ETC8 drive strength control register Port group GPV4 configuration register Port group GPV4 data register Port group GPV4 pull-up/pull-down register Port group GPV4 drive strength control register Port group GPV4 power down mode configuration register Port group GPV4 power down mode pull-up/pull-down register External interrupt EXT_INT30 configuration register External interrupt EXT_INT31 configuration register External interrupt EXT_INT32 configuration register External interrupt EXT_INT33 configuration register External interrupt EXT_INT34 configuration register External interrupt EXT_INT30 filter configuration register 0 External interrupt EXT_INT30 filter configuration register 1 External interrupt EXT_INT31 filter configuration register 0 External interrupt EXT_INT31 filter configuration register 1 External interrupt EXT_INT32 filter configuration register 0 External interrupt EXT_INT32 filter configuration register 1 External interrupt EXT_INT33 filter configuration register 0 Reset Value 0x0005 0x00_0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0000_0000 0x00 0x5555 0x00_0000 0x0000 0x0000 0x0005 0x00_0000 0x0000_0000 0x00 0x0005 0x00_0000 0x0000 0x0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 4-18 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Register EXT_INT33_FLTCON1 EXT_INT34_FLTCON0 EXT_INT34_FLTCON1 EXT_INT30_MASK EXT_INT31_MASK EXT_INT32_MASK EXT_INT33_MASK EXT_INT34_MASK EXT_INT30_PEND EXT_INT31_PEND EXT_INT32_PEND EXT_INT33_PEND EXT_INT34_PEND EXT_INT_SERVICE _XC EXT_INT_SERVICE _PEND_XC EXT_INT_GRPFIXPRI _XC EXT_INT30_FIXPRI EXT_INT31_FIXPRI EXT_INT32_FIXPRI EXT_INT33_FIXPRI EXT_INT34_FIXPRI PDNEN Offset 0x081C 0x0820 0x0824 0x0900 0x0904 0x0908 0x090C 0x0910 0x0A00 0x0A04 0x0A08 0x0A0C 0x0A10 0x0B08 0x0B0C 0x0B10 0x0B14 0x0B18 0x0B1C 0x0B20 0x0B24 0x0F80 Description External interrupt EXT_INT33 filter configuration register 1 External interrupt EXT_INT34 filter configuration register 0 External interrupt EXT_INT34 filter configuration register 1 External interrupt EXT_INT30 mask register External interrupt EXT_INT31 mask register External interrupt EXT_INT32 mask register External interrupt EXT_INT33 mask register External interrupt EXT_INT34 mask register External interrupt EXT_INT30 pending register External interrupt EXT_INT31 pending register External interrupt EXT_INT32 pending register External interrupt EXT_INT33 pending register External interrupt EXT_INT34 pending register Current service register Current service pending register External interrupt group fixed priority control register External interrupt 30 fixed priority control register External interrupt 31 fixed priority control register External interrupt 32 fixed priority control register External interrupt 33 fixed priority control register External interrupt 34 fixed priority control register Power down mode pad configure register Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_0003 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x00 4-19 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2 Part 1 For the following SFRs, Sets the value does not take effect immediately. It takes at least 800 APB clocks for the value to take effect after the SFR is actually changed: The SFRs are: GPA0PUD, GPA0DRV, GPA1PUD, GPA1DRV, GPBPUD, GPBDRV, GPC0PUD, GPC0DRV, GPC1PUD, GPC1DRV, GPD0PUD, GPD0DRV, GPD1PUD, GPD1DRV, GPF0PUD, GPF0DRV, GPF1PUD, GPF1DRV, GPF2PUD, GPF2DRV, GPF3PUD, GPF3DRV, GPJ0PUD, GPJ0DRV, GPJ1PUD, GPJ1DRV. 4-20 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.1 GPA0CON  Base Address: 0x1140_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_0000 Name GPA0CON[7] GPA0CON[6] GPA0CON[5] GPA0CON[4] GPA0CON[3] GPA0CON[2] GPA0CON[1] GPA0CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = UART_1_RTSn 0x3 = I2C_2_SCL 0x4 to 0xE = Reserved 0xF = EXT_INT1[7] 0x0 = Input 0x1 = Output 0x2 = UART_1_CTSn 0x3 = I2C_2_SDA 0x4 to 0xE = Reserved 0xF = EXT_INT1[6] 0x0 = Input 0x1 = Output 0x2 = UART_1_TXD 0x3 to 0xE = Reserved 0xF = EXT_INT1[5] 0x0 = Input 0x1 = Output 0x2 = UART_1_RXD 0x3 to 0xE = Reserved 0xF = EXT_INT1[4] 0x0 = Input 0x1 = Output 0x2 = UART_0_RTSn 0x3 to 0xE = Reserved 0xF = EXT_INT1[3] 0x0 = Input 0x1 = Output 0x2 = UART_0_CTSn 0x3 to 0xE = Reserved 0xF = EXT_INT1[2] 0x0 = Input 0x1 = Output 0x2 = UART_0_TXD 0x3 to 0xE = Reserved 0xF = EXT_INT1[1] 0x0 = Input 0x1 = Output 0x2 = UART_0_RXD 0x3 to 0xE = Reserved 0xF = EXT_INT1[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-21 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.2 GPA0DAT  Base Address: 0x1140_0000  Address = Base Address + 0x0004, Reset Value = 0x00 Name Bit GPA0DAT[7:0] [7:0] Type RWX Description When you configure port as input port, then corresponding bit is pin state. When configuring as output port the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.3 GPA0PUD  Base Address: 0x1140_0000  Address = Base Address + 0x0008, Reset Value = 0x5555 Name GPA0PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.2.4 GPA0DRV  Base Address: 0x1140_0000  Address = Base Address + 0x000C, Reset Value = 0x00_0000 Name GPA0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-22 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.5 GPA0CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0010, Reset Value = 0x0000 Name GPA0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.6 GPA0PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0014, Reset Value = 0x0000 Name GPA0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-23 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.7 GPA1CON  Base Address: 0x1140_0000  Address = Base Address + 0x0020, Reset Value = 0x0000_0000 Name GPA1CON[5] GPA1CON[4] GPA1CON[3] GPA1CON[2] GPA1CON[1] GPA1CON[0] Bit [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = UART_3_TXD 0x3 = Reserved 0x4 = UART_AUDIO_TXD 0x5 to 0xE = Reserved 0xF = EXT_INT2[5] 0x0 = Input 0x1 = Output 0x2 = UART_3_RXD 0x3 = Reserved 0x4 = UART_AUDIO_RXD 0x5 to 0xE = Reserved 0xF = EXT_INT2[4] 0x0 = Input 0x1 = Output 0x2 = UART_2_RTSn 0x3 = I2C_3_SCL 0x4 to 0xE = Reserved 0xF = EXT_INT2[3] 0x0 = Input 0x1 = Output 0x2 = UART_2_CTSn 0x3 = I2C_3_SDA 0x4 to 0xE = Reserved 0xF = EXT_INT2[2] 0x0 = Input 0x1 = Output 0x2 = UART_2_TXD 0x3 = Reserved 0x4 = UART_AUDIO_TXD 0x5 to 0xE = Reserved 0xF = EXT_INT2[1] 0x0 = Input 0x1 = Output 0x2 = UART_2_RXD 0x3 = Reserved 0x4 = UART_AUDIO_RXD 0x5 to 0xE = Reserved 0xF = EXT_INT2[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-24 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.8 GPA1DAT  Base Address: 0x1140_0000  Address = Base Address + 0x0024, Reset Value = 0x00 Name Bit GPA1DAT[5:0] [5:0] Type RWX Description When you configure port as input port, then corresponding bit is the pin state. When configuring as output port the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.9 GPA1PUD  Base Address: 0x1140_0000  Address = Base Address + 0x0028, Reset Value = 0x0555 Name GPA1PUD[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0555 4.3.2.10 GPA1DRV  Base Address: 0x1140_0000  Address = Base Address + 0x002C, Reset Value = 0x00_0000 Name GPA1DRV [n] Bit [23:16] [2n + 1:2n] n = 0 to 5 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-25 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.11 GPA1CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0030, Reset Value = 0x0000 Name GPA1[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.12 GPA1PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0034, Reset Value = 0x0000 Name GPA1[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-26 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.13 GPBCON  Base Address: 0x1140_0000  Address = Base Address + 0x0040, Reset Value = 0x0000_0000 Name GPBCON[7] GPBCON[6] GPBCON[5] GPBCON[4] GPBCON[3] GPBCON[2] GPBCON[1] GPBCON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = SPI_1_MOSI 0x3 to 0xE = Reserved 0xF = EXT_INT3[7] 0x0 = Input 0x1 = Output 0x2 = SPI_1_MISO 0x3 to 0xE = Reserved 0xF = EXT_INT3[6] 0x0 = Input 0x1 = Output 0x2 = SPI_1_nSS 0x3 = Reserved 0x4 = IEM_SPWI 0x5 to 0xE = Reserved 0xF = EXT_INT3[5] 0x0 = Input 0x1 = Output 0x2 = SPI_1_CLK 0x3 = Reserved 0x4 = IEM_SCLK 0x5 to 0xE = Reserved 0xF = EXT_INT3[4] 0x0 = Input 0x1 = Output 0x2 = SPI_0_MOSI 0x3 = I2C_5_SCL 0x4 to 0xE = Reserved 0xF = EXT_INT3[3] 0x0 = Input 0x1 = Output 0x2 = SPI_0_MISO 0x3 = I2C_5_SDA 0x4 to 0xE = Reserved 0xF = EXT_INT3[2] 0x0 = Input 0x1 = Output 0x2 = SPI_0_nSS 0x3 = I2C_4_SCL 0x4 to 0xE = Reserved 0xF = EXT_INT3[1] 0x0 = Input 0x1 = Output Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-27 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description 0x2 = SPI_0_CLK 0x3 = I2C_4_SDA 0x4 to 0xE = Reserved 0xF = EXT_INT3[0] Reset Value 4-28 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.14 GPBDAT  Base Address: 0x1140_0000  Address = Base Address + 0x0044, Reset Value = 0x00 Name Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as GPBDAT[7:0] [7:0] RWX output port the pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.15 GPBPUD  Base Address: 0x1140_0000  Address = Base Address + 0x0048, Reset Value = 0x5555 Name GPBPUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.2.16 GPBDRV  Base Address: 0x1140_0000  Address = Base Address + 0x004C, Reset Value = 0x00_0000 Name GPBDRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4 Reset Value 0x00 0x0000 4-29 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.17 GPBCONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0050, Reset Value = 0x0000 Name GPB[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.18 GPBPUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0054, Reset Value = 0x0000 Name GPB[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved, 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-30 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.19 GPC0CON  Base Address: 0x1140_0000  Address = Base Address + 0x0060, Reset Value = 0x0000_0000 Name GPC0CON[4] GPC0CON[3] GPC0CON[2] GPC0CON[1] GPC0CON[0] Bit [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = I2S_1_SDO 0x3 = PCM_1_SOUT 0x4 = AC97SDO 0x5 to 0xE = Reserved 0xF = EXT_INT4[4] 0x0 = Input 0x1 = Output 0x2 = I2S_1_SDI 0x3 = PCM_1_SIN 0x4 = AC97SDI 0x5 to 0xE = Reserved 0xF = EXT_INT4[3] 0x0 = Input 0x1 = Output 0x2 = I2S_1_LRCK 0x3 = PCM_1_FSYNC 0x4 = AC97SYNC 0x5 to 0xE = Reserved 0xF = EXT_INT4[2] 0x0 = Input 0x1 = Output 0x2 = I2S_1_CDCLK 0x3 = PCM_1_EXTCLK 0x4 = AC97RESETn 0x5 to 0xE = Reserved 0xF = EXT_INT4[1] 0x0 = Input 0x1 = Output 0x2 = I2S_1_SCLK 0x3 = PCM_1_SCLK 0x4 = AC97BITCLK 0x5 to 0xE = Reserved 0xF = EXT_INT4[0] Reset Value 0x00 0x00 0x00 0x00 0x00 4-31 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.20 GPC0DAT  Base Address: 0x1140_0000  Address = Base Address + 0x0064, Reset Value = 0x00 Name Bit GPC0DAT[4:0] [4:0] Type RWX Description When you configure as input port then corresponding bit is pin state. When configuring as output port the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.21 GPC0PUD  Base Address: 0x1140_0000  Address = Base Address + 0x0068, Reset Value = 0x0155 Name GPC0PUD[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0155 4.3.2.22 GPC0DRV  Base Address: 0x1140_0000  Address = Base Address + 0x006C, Reset Value = 0x00_0000 Name GPC0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 4 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-32 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.23 GPC0CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0070, Reset Value = 0x0000 Name GPC0[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.24 GPC0PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0074, Reset Value = 0x0000 Name GPC0[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-33 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.25 GPC1CON  Base Address: 0x1140_0000  Address = Base Address + 0x0080, Reset Value = 0x0000_0000 Name GPC1CON[4] GPC1CON[3] GPC1CON[2] GPC1CON[1] GPC1CON[0] Bit [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = I2S_2_SDO 0x3 = PCM_2_SOUT 0x4 = I2C_6_SCL 0x5 = SPI_2_MOSI 0x6 to 0xE = Reserved 0xF = EXT_INT5[4] 0x0 = Input 0x1 = Output 0x2 = I2S_2_SDI 0x3 = PCM_2_SIN 0x4 = I2C_6_SDA 0x5 = SPI_2_MISO 0x6 to 0xE = Reserved 0xF = EXT_INT5[3] 0x0 = Input 0x1 = Output 0x2 = I2S_2_LRCK 0x3 = PCM_2_FSYNC 0x4 = Reserved 0x5 = SPI_2_nSS 0x6 to 0xE = Reserved 0xF = EXT_INT5[2] 0x0 = Input 0x1 = Output 0x2 = I2S_2_CDCLK 0x3 = PCM_2_EXTCLK 0x4 = SPDIF_EXTCLK 0x5 = SPI_2_CLK 0x6 to 0xE = Reserved 0xF = EXT_INT5[1] 0x0 = Input 0x1 = Output 0x2 = I2S_2_SCLK 0x3 = PCM_2_SCLK 0x4 = SPDIF_0_OUT 0x5 to 0xE = Reserved 0xF = EXT_INT5[0] Reset Value 0x00 0x00 0x00 0x00 0x00 4-34 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.26 GPC1DAT  Base Address: 0x1140_0000  Address = Base Address + 0x0084, Reset Value = 0x00 Name Bit GPC1DAT[4:0] [4:0] Type RWX Description When you configure port as input port, corresponding bit is pin state. When configuring as output port, pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.27 GPC1PUD  Base Address: 0x1140_0000  Address = Base Address + 0x0088, Reset Value = 0x0155 Name GPC1PUD[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0155 4.3.2.28 GPC1DRV  Base Address: 0x1140_0000  Address = Base Address + 0x008C, Reset Value = 0x00_0000 Name GPC1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 4 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-35 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.29 GPC1CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0090, Reset Value = 0x0000 Name GPC1[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.30 GPC1PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0094, Reset Value = 0x0000 Name GPC1[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-36 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.31 GPD0CON  Base Address: 0x1140_0000  Address = Base Address + 0x00A0, Reset Value = 0x0000_0000 Name GPD0CON[3] GPD0CON[2] GPD0CON[1] GPD0CON[0] Bit [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = TOUT_3 0x3 = I2C_7_SCL 0x4 to 0xE = Reserved 0xF = EXT_INT6[3] 0x0 = Input 0x1 = Output 0x2 = TOUT_2 0x3 = I2C_7_SDA 0x4 to 0xE = Reserved 0xF = EXT_INT6[2] 0x0 = Input 0x1 = Output 0x2 = TOUT_1 0x3 = LCD_PWM 0x4 to 0xE = Reserved 0xF = EXT_INT6[1] 0x0 = Input 0x1 = Output 0x2 = TOUT_0 0x3 = LCD_FRM 0x4 to 0xE = Reserved 0xF = EXT_INT6[0] Reset Value 0x00 0x00 0x00 0x00 4-37 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.32 GPD0DAT  Base Address: 0x1140_0000  Address = Base Address + 0x00A4, Reset Value = 0x00 Name Bit GPD0DAT[3:0] [3:0] Type RWX Description When you configure port as input port then corresponding bit is pin state. When configuring as output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.33 GPD0PUD  Base Address: 0x1140_0000  Address = Base Address + 0x00A8, Reset Value = 0x0055 Name GPD0PUD[n] Bit [2n + 1:2n] n = 0 to 3 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0055 4.3.2.34 GPD0DRV  Base Address: 0x1140_0000  Address = Base Address + 0x00AC, Reset Value = 0x00_0000 Name GPD0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 3 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-38 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.35 GPD0CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x00B0, Reset Value = 0x0000 Name GPD0[n] Bit [2n + 1:2n] n = 0 to 3 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.36 GPD0PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x00B4, Reset Value = 0x0000 Name GPD0[n] Bit [2n + 1:2n] n = 0 to 3 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-39 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.37 GPD1CON  Base Address: 0x1140_0000  Address = Base Address + 0x00C0, Reset Value = 0x0000_0000 Name GPD1CON[3] GPD1CON[2] GPD1CON[1] GPD1CON[0] Bit [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = I2C_1_SCL 0x3 = MIPI1_ESC_CLK 0x4 to 0xE = Reserved 0xF = EXT_INT7[3] 0x0 = Input 0x1 = Output 0x2 = I2C_1_SDA 0x3 = MIPI1_BYTE_CLK 0x4 to 0xE = Reserved 0xF = EXT_INT7[2] 0x0 = Input 0x1 = Output 0x2 = I2C_0_SCL 0x3 = MIPI0_ESC_CLK 0x4 to 0xE = Reserved 0xF = EXT_INT7[1] 0x0 = Input 0x1 = Output 0x2 = I2C_0_SDA 0x3 = MIPI0_BYTE_CLK 0x4 to 0xE = Reserved 0xF = EXT_INT7[0] Reset Value 0x00 0x00 0x00 0x00 4-40 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.38 GPD1DAT  Base Address: 0x1140_0000  Address = Base Address + 0x00C4, Reset Value = 0x00 Name Bit GPD1DAT[3:0] [3:0] Type RWX Description When you configure port as input port then corresponding bit is pin state. When configuring as output port then pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.39 GPD1PUD  Base Address: 0x1140_0000  Address = Base Address + 0x00C8, Reset Value = 0x0055 Name GPD1PUD[n] Bit [2n + 1:2n] n = 0 to 3 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved, 0x3 = Enables Pull-up Reset Value 0x0055 4.3.2.40 GPD1DRV  Base Address: 0x1140_0000  Address = Base Address + 0x00CC, Reset Value = 0x00_0000 Name GPD1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 3 Type RW RW Description Reserved (should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-41 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.41 GPD1CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x00D0, Reset Value = 0x0000 Name GPD1[n] Bit [2n + 1:2n] n = 0 to 3 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.42 GPD1PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x00D4, Reset Value = 0x0000 Name GPD1[n] Bit [2n + 1:2n] n = 0 to 3 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-42 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.43 GPF0CON  Base Address: 0x1140_0000  Address = Base Address + 0x0180, Reset Value = 0x0000_0000 Name GPF0CON[7] GPF0CON[6] GPF0CON[5] GPF0CON[4] GPF0CON[3] GPF0CON[2] GPF0CON[1] GPF0CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = LCD_VD[3] 0x3 to 0xE = Reserved 0xF = EXT_INT13[7] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[2] 0x3 to 0xE = Reserved 0xF = EXT_INT13[6] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[1] 0x3 to 0xE = Reserved 0xF = EXT_INT13[5] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[0] 0x3 to 0xE = Reserved 0xF = EXT_INT13[4] 0x0 = Input 0x1 = Output 0x2 = LCD_VCLK 0x3 to 0xE = Reserved 0xF = EXT_INT13[3] 0x0 = Input 0x1 = Output, 0x2 = LCD_VDEN, 0x3 to 0xE = Reserved, 0xF = EXT_INT13[2] 0x0 = Input 0x1 = Output 0x2 = LCD_VSYNC 0x3 to 0xE = Reserved 0xF = EXT_INT13[1] 0x0 = Input 0x1 = Output 0x2 = LCD_HSYNC 0x3 to 0xE = Reserved 0xF = EXT_INT13[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-43 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.44 GPF0DAT  Base Address: 0x1140_0000  Address = Base Address + 0x0184, Reset Value = 0x00 Name Bit GPF0DAT[7:0] [7:0] Type RWX Description When you configure port as input port then corresponding bit is pin state. When configuring as output port the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.45 GPF0PUD  Base Address: 0x1140_0000  Address = Base Address + 0x0188, Reset Value = 0x5555 Name GPF0PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.2.46 GPF0DRV  Base Address: 0x1140_0000  Address = Base Address + 0x018C, Reset Value = 0x00_0000 Name GPF0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-44 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.47 GPF0CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0190, Reset Value = 0x0000 Name GPF0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.48 GPF0PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0194, Reset Value = 0x0000 Name GPF0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-45 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.49 GPF1CON  Base Address: 0x1140_0000  Address = Base Address + 0x01A0, Reset Value = 0x0000_0000 Name GPF1CON[7] GPF1CON[6] GPF1CON[5] GPF1CON[4] GPF1CON[3] GPF1CON[2] GPF1CON[1] GPF1CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = LCD_VD[11] 0x3 to 0xE = Reserved 0xF = EXT_INT14[7] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[10] 0x3 to 0xE = Reserved 0xF = EXT_INT14[6] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[9] 0x3 to 0xE = Reserved 0xF = EXT_INT14[5] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[8] 0x3 to 0xE = Reserved 0xF = EXT_INT14[4] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[7] 0x3 to 0xE = Reserved 0xF = EXT_INT14[3] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[6] 0x3 to 0xE = Reserved 0xF = EXT_INT14[2] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[5] 0x3 to 0xE = Reserved 0xF = EXT_INT14[1] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[4] 0x3 to 0xE = Reserved 0xF = EXT_INT14[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-46 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.50 GPF1DAT  Base Address: 0x1140_0000  Address = Base Address + 0x01A4, Reset Value = 0x00 Name Bit GPF1DAT[7:0] [7:0] Type RWX Description When you configure port as input port then corresponding bit is pin state. When configuring as output port the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.51 GPF1PUD  Base Address: 0x1140_0000  Address = Base Address + 0x01A8, Reset Value = 0x5555 Name GPF1PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.2.52 GPF1DRV  Base Address: 0x1140_0000  Address = Base Address + 0x01AC, Reset Value = 0x00_0000 Name GPF1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-47 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.53 GPF1CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x01B0, Reset Value = 0x0000 Name GPF1[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0, 0x1 = Outputs 1, 0x2 = Input, 0x3 = Previous state 4.3.2.54 GPF1PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x01B4, Reset Value = 0x0000 Name GPF1[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved, 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-48 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.55 GPF2CON  Base Address: 0x1140_0000  Address = Base Address + 0x01C0, Reset Value = 0x0000_0000 Name GPF2CON[7] GPF2CON[6] GPF2CON[5] GPF2CON[4] GPF2CON[3] GPF2CON[2] GPF2CON[1] GPF2CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = LCD_VD[19] 0x3 to 0xE = Reserved 0xF = EXT_INT15[7] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[18] 0x3 to 0xE = Reserved 0xF = EXT_INT15[6] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[17] 0x3 to 0xE = Reserved 0xF = EXT_INT15[5] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[16] 0x3 to 0xE = Reserved 0xF = EXT_INT15[4] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[15] 0x3 to 0xE = Reserved 0xF = EXT_INT15[3] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[14] 0x3 to 0xE = Reserved 0xF = EXT_INT15[2] 0x0 = Input 0x1 = Output, 0x2 = LCD_VD[13], 0x3 to 0xE = Reserved 0xF = EXT_INT15[1] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[12] 0x3 to 0xE = Reserved, 0xF = EXT_INT15[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-49 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.56 GPF2DAT  Base Address: 0x1140_0000  Address = Base Address + 0x01C4, Reset Value = 0x00 Name Bit GPF2DAT[7:0] [7:0] Type RWX Description When you configure port as input port then corresponding bit is pin state. When configuring as output port the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.57 GPF2PUD  Base Address: 0x1140_0000  Address = Base Address + 0x01C8, Reset Value = 0x5555 Name GPF2PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.2.58 GPF2DRV  Base Address: 0x1140_0000  Address = Base Address + 0x01CC, Reset Value = 0x00_0000 Name GPF2DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-50 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.59 GPF2CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x01D0, Reset Value = 0x0000 Name GPF2[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.60 GPF2PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x01D4, Reset Value = 0x0000 Name GPF2[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-51 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.61 GPF3CON  Base Address: 0x1140_0000  Address = Base Address + 0x01E0, Reset Value = 0x0000_0000 Name GPF3CON[5] GPF3CON[4] GPF3CON[3] GPF3CON[2] GPF3CON[1] GPF3CON[0] Bit [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = SYS_OE 0x3 to 0xE = Reserved 0xF = EXT_INT16[5] 0x0 = Input 0x1 = Output 0x2 = VSYNC_LDI 0x3 to 0xE = Reserved 0xF = EXT_INT16[4] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[23] 0x3 to 0xE = Reserved 0xF = EXT_INT16[3] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[22] 0x3 to 0xE = Reserved 0xF = EXT_INT16[2] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[21] 0x3 to 0xE = Reserved 0xF = EXT_INT16[1] 0x0 = Input 0x1 = Output 0x2 = LCD_VD[20] 0x3 to 0xE = Reserved 0xF = EXT_INT16[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-52 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.62 GPF3DAT  Base Address: 0x1140_0000  Address = Base Address + 0x01E4, Reset Value = 0x00 Name Bit GPF3DAT[5:0] [5:0] Type RWX Description When you configure port as input port then corresponding bit is pin state. When configuring as output port the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.63 GPF3PUD  Base Address: 0x1140_0000  Address = Base Address + 0x01E8, Reset Value = 0x0555 Name GPF3PUD[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0555 4.3.2.64 GPF3DRV  Base Address: 0x1140_0000  Address = Base Address + 0x01EC, Reset Value = 0x00_0000 Name GPF3DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 5 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4.3.2.65 GPF3CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x01F0, Reset Value = 0x0000 Name GPF3[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state Reset Value 0x00 4-53 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.66 GPF3PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x01F4, Reset Value = 0x0000 Name GPF3[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up 4.3.2.67 ETC1PUD  Base Address: 0x1140_0000  Address = Base Address + 0x0228, Reset Value = 0x0005 Name ETC1PUD[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up ETC1PUD[1:0] controls XsbusDATA. ETC1PUD[3:2] controls XsbusCLK. Reset Value 0x00 Reset Value 0x0005 4.3.2.68 ETC1DRV  Base Address: 0x1140_0000  Address = Base Address + 0x022C, Reset Value = 0x00_0000 Name ETC1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 5 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x ETC1PUD[1:0] controls XsbusDATA. ETC1PUD[3:2] controls XsbusCLK. Reset Value 0x00 0x0000 4-54 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.69 GPJ0CON  Base Address: 0x1140_0000  Address = Base Address + 0x0240, Reset Value = 0x0000_0000 Name GPJ0CON[7] GPJ0CON[6] GPJ0CON[5] GPJ0CON[4] GPJ0CON[3] GPJ0CON[2] GPJ0CON[1] GPJ0CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = CAM_A_DATA[4] 0x3 to 0xE = Reserved 0xF = EXT_INT21[7] 0x0 = Input 0x1 = Output 0x2 = CAM_A_DATA[3] 0x3 to 0xE = Reserved 0xF = EXT_INT21[6] 0x0 = Input 0x1 = Output 0x2 = CAM_A_DATA[2] 0x3 to 0xE = Reserved 0xF = EXT_INT21[5] 0x0 = Input 0x1 = Output 0x2 = CAM_A_DATA[1] 0x3 to 0xE = Reserved 0xF = EXT_INT21[4] 0x0 = Input 0x1 = Output 0x2 = CAM_A_DATA[0] 0x3 to 0xE = Reserved 0xF = EXT_INT21[3] 0x0 = Input 0x1 = Output 0x2 = CAM_A_HREF 0x3 to 0xE = Reserved 0xF = EXT_INT21[2] 0x0 = Input 0x1 = Output 0x2 = CAM_A_VSYNC 0x3 to 0xE = Reserved 0xF = EXT_INT21[1] 0x0 = Input 0x1 = Output 0x2 = CAM_A_PCLK 0x3 to 0xE = Reserved 0xF = EXT_INT21[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-55 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.70 GPJ0DAT  Base Address: 0x1140_0000  Address = Base Address + 0x0244, Reset Value = 0x00 Name Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as GPJ0DAT[7:0] [7:0] RWX output port the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.71 GPJ0PUD  Base Address: 0x1140_0000  Address = Base Address + 0x0248, Reset Value = 0x5555 Name GPJ0PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.2.72 GPJ0DRV  Base Address: 0x1140_0000  Address = Base Address + 0x024C, Reset Value = 0x00_0000 Name GPJ0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4 Reset Value 0x00 0x0000 4-56 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.73 GPJ0CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0250, Reset Value = 0x0000 Name GPJ0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.74 GPJ0PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0254, Reset Value = 0x0000 Name GPJ0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-57 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.75 GPJ1CON  Base Address: 0x1140_0000  Address = Base Address + 0x0260, Reset Value = 0x0000_0000 Name GPJ1CON[4] GPJ1CON[3] GPJ1CON[2] GPJ1CON[1] GPJ1CON[0] Bit [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = CAM_A_FIELD 0x3 to 0xE = Reserved 0xF = EXT_INT22[4] 0x0 = Input 0x1 = Output 0x2 = CAM_A_CLKOUT 0x3 to 0xE = Reserved 0xF = EXT_INT22[3] 0x0 = Input 0x1 = Output 0x2 = CAM_A_DATA[7] 0x3 to 0xE = Reserved 0xF = EXT_INT22[2] 0x0 = Input 0x1 = Output 0x2 = CAM_A_DATA[6] 0x3 to 0xE = Reserved 0xF = EXT_INT22[1] 0x0 = Input 0x1 = Output 0x2 = CAM_A_DATA[5] 0x3 to 0xE = Reserved 0xF = EXT_INT22[0] Reset Value 0x00 0x00 0x00 0x00 0x00 4-58 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.76 GPJ1DAT  Base Address: 0x1140_0000  Address = Base Address + 0x0264, Reset Value = 0x00 Name Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as GPJ1DAT[4:0] [4:0] RWX output port the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.2.77 GPJ1PUD  Base Address: 0x1140_0000  Address = Base Address + 0x0268, Reset Value = 0x0155 Name GPJ1PUD[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0155 4.3.2.78 GPJ1DRV  Base Address: 0x1140_0000  Address = Base Address + 0x026C, Reset Value = 0x00_0000 Name GPJ1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 4 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-59 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.79 GPJ1CONPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0270, Reset Value = 0x0000 Name GPJ1[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.2.80 GPJ1PUDPDN  Base Address: 0x1140_0000  Address = Base Address + 0x0274, Reset Value = 0x0000 Name GPJ1[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-60 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.81 EXT_INT1CON  Base Address: 0x1140_0000  Address = Base Address + 0x0700, Reset Value = 0x0000_0000 Name RSVD EXT_INT1_CON[7] RSVD EXT_INT1_CON[6] RSVD EXT_INT1_CON[5] RSVD EXT_INT1_CON[4] RSVD EXT_INT1_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT1[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT1[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT1[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT1[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT1[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-61 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT1_CON[2] RSVD EXT_INT1_CON[1] RSVD EXT_INT1_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT1[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT1[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT1[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-62 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.82 EXT_INT2CON  Base Address: 0x1140_0000  Address = Base Address + 0x0704, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT2_CON[5] RSVD EXT_INT2_CON[4] RSVD EXT_INT2_CON[3] RSVD EXT_INT2_CON[2] RSVD EXT_INT2_CON[1] Bit [31:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT2[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT2[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT2[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT2[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT2[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-63 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description RSVD [3] – Reserved Sets signaling method of EXT_INT2[0] 0x0 = Low level 0x1 = High level EXT_INT2_CON[0] [2:0] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 4-64 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.83 EXT_INT3CON  Base Address: 0x1140_0000  Address = Base Address + 0x0708, Reset Value = 0x0000_0000 Name RSVD EXT_INT3_CON[7] RSVD EXT_INT3_CON[6] RSVD EXT_INT3_CON[5] RSVD EXT_INT3_CON[4] RSVD EXT_INT3_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT3[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT3[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT3[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT3[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT3[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-65 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT3_CON[2] RSVD EXT_INT3_CON[1] RSVD EXT_INT3_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT3[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT3[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT3[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-66 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.84 EXT_INT4CON  Base Address: 0x1140_0000  Address = Base Address + 0x070C, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT4_CON[4] RSVD EXT_INT4_CON[3] RSVD EXT_INT4_CON[2] RSVD EXT_INT4_CON[1] RSVD EXT_INT4_CON[0] Bit [31:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT4[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT4[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT4[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT4[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT4[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-67 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.85 EXT_INT5CON  Base Address: 0x1140_0000  Address = Base Address + 0x0710, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT5_CON[4] RSVD EXT_INT5_CON[3] RSVD EXT_INT5_CON[2] RSVD EXT_INT5_CON[1] RSVD EXT_INT5_CON[0] Bit [31:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT5[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT5[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT5[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT5[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT5[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-68 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.86 EXT_INT6CON  Base Address: 0x1140_0000  Address = Base Address + 0x0714, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT6_CON[3] RSVD EXT_INT6_CON[2] RSVD EXT_INT6_CON[1] RSVD EXT_INT6_CON[0] Bit [31:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Type – – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT6[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT6[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT6[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT6[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-69 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.87 EXT_INT7CON  Base Address: 0x1140_0000  Address = Base Address + 0x0718, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT7_CON[3] RSVD EXT_INT7_CON[2] RSVD EXT_INT7_CON[1] RSVD EXT_INT7_CON[0] Bit [31:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Type – – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT7[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT7[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT7[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT7[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-70 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.88 EXT_INT13CON  Base Address: 0x1140_0000  Address = Base Address + 0x0730, Reset Value = 0x0000_0000 Name RSVD EXT_INT13_CON[7] RSVD EXT_INT13_CON[6] RSVD EXT_INT13_CON[5] RSVD EXT_INT13_CON[4] RSVD EXT_INT13_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT13[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT13[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT13[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT13[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT13[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-71 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT13_CON[2] RSVD EXT_INT13_CON[1] RSVD EXT_INT13_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT13[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT13[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT13[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-72 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.89 EXT_INT14CON  Base Address: 0x1140_0000  Address = Base Address + 0x0734, Reset Value = 0x0000_0000 Name RSVD EXT_INT14_CON[7] RSVD EXT_INT14_CON[6] RSVD EXT_INT14_CON[5] RSVD EXT_INT14_CON[4] RSVD EXT_INT14_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT14[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT14[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT14[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT14[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT14[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-73 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT14_CON[2] RSVD EXT_INT14_CON[1] RSVD EXT_INT14_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT14[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT14[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT14[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-74 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.90 EXT_INT15CON  Base Address: 0x1140_0000  Address = Base Address + 0x0738, Reset Value = 0x0000_0000 Name RSVD EXT_INT15_CON[7] RSVD EXT_INT15_CON[6] RSVD EXT_INT15_CON[5] RSVD EXT_INT15_CON[4] RSVD EXT_INT15_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT15[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT15[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT15[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT15[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT15[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-75 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT15_CON[2] RSVD EXT_INT15_CON[1] RSVD EXT_INT15_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT15[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT15[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT15[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-76 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.91 EXT_INT16CON  Base Address: 0x1140_0000  Address = Base Address + 0x073C, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT16_CON[5] RSVD EXT_INT16_CON[4] RSVD EXT_INT16_CON[3] RSVD EXT_INT16_CON[2] RSVD EXT_INT16_CON[1] Bit [31:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT16[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT16[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT16[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT16[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT16[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-77 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description RSVD [3] – Reserved Sets signaling method of EXT_INT16[0] 0x0 = Low level 0x1 = High level EXT_INT16_CON[0] [2:0] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 4-78 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.92 EXT_INT21CON  Base Address: 0x1140_0000  Address = Base Address + 0x0740, Reset Value = 0x0000_0000 Name RSVD EXT_INT21_CON[7] RSVD EXT_INT21_CON[6] RSVD EXT_INT21_CON[5] RSVD EXT_INT21_CON[4] RSVD EXT_INT21_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT21[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT21[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT21[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT21[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT21[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-79 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT21_CON[2] RSVD EXT_INT21_CON[1] RSVD EXT_INT21_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT21[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT21[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT21[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-80 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.93 EXT_INT22CON  Base Address: 0x1140_0000  Address = Base Address + 0x0744, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT22_CON[4] RSVD EXT_INT22_CON[3] RSVD EXT_INT22_CON[2] RSVD EXT_INT22_CON[1] RSVD EXT_INT22_CON[0] Bit [31:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Type – – RW – RW – RW – W – RW Description Reserved Reserved Sets signaling method of EXT_INT22[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT22[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT22[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT22[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT22[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-81 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.94 EXT_INT1_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0800, Reset Value = 0x0000_0000 Name FLTEN1[3] FLTWIDTH1[3] FLTEN1[2] FLTWIDTH1[2] FLTEN1[1] FLTWIDTH1[1] FLTEN1[0] FLTWIDTH1[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT1[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT1[3] Filter Enable for EXT_INT1[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT1[2] Filter Enable for EXT_INT1[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT1[1] Filter Enable for EXT_INT1[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT1[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-82 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.95 EXT_INT1_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x0804, Reset Value = 0x0000_0000 Name FLTEN1[7] FLTWIDTH1[7] FLTEN1[6] FLTWIDTH1[6] FLTEN1[5] FLTWIDTH1[5] FLTEN1[4] FLTWIDTH1[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT1[7] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT1[7] Filter Enable for EXT_INT1[6] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT1[6] Filter Enable for EXT_INT1[5] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT1[5] Filter Enable for EXT_INT1[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT1[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-83 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.96 EXT_INT2_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0808, Reset Value = 0x0000_0000 Name FLTEN2[3] FLTWIDTH2[3] FLTEN2[2] FLTWIDTH2[2] FLTEN2[1] FLTWIDTH2[1] FLTEN2[0] FLTWIDTH2[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT2[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT2[3] Filter Enable for EXT_INT2[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT2[2] Filter Enable for EXT_INT2[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT2[1] Filter Enable for EXT_INT2[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT2[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4.3.2.97 EXT_INT2_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x080C, Reset Value = 0x0000_0000 Name RSVD FLTEN2[5] FLTWIDTH2[5] FLTEN2[4] FLTWIDTH2[4] Bit [31:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW Description Reserved Filter Enable for EXT_INT2[5] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT2[5] Filter Enable for EXT_INT2[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT2[4] Reset Value 0x0000 0x0 0x00 0x0 0x00 4-84 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.98 EXT_INT3_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0810, Reset Value = 0x0000_0000 Name FLTEN3[3] FLTWIDTH3[3] FLTEN3[2] FLTWIDTH3[2] FLTEN3[1] FLTWIDTH3[1] FLTEN3[0] FLTWIDTH3[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT3[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT3[3] Filter Enable for EXT_INT3[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT3[2] Filter Enable for EXT_INT3[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT3[1] Filter Enable for EXT_INT3[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT3[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-85 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.99 EXT_INT3_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x0814, Reset Value = 0x0000_0000 Name FLTEN3[7] FLTWIDTH3[7] FLTEN3[6] FLTWIDTH3[6] FLTEN3[5] FLTWIDTH3[5] FLTEN3[4] FLTWIDTH3[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT3[7] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT3[7] Filter Enable for EXT_INT3[6] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT3[6] Filter Enable for EXT_INT3[5] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT3[5] Filter Enable for EXT_INT3[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT3[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-86 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.100 EXT_INT4_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0818, Reset Value = 0x0000_0000 Name FLTEN4[3] FLTWIDTH4[3] FLTEN4[2] FLTWIDTH4[2] FLTEN4[1] FLTWIDTH4[1] FLTEN4[0] FLTWIDTH4[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT4[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT4[3] Filter Enable for EXT_INT4[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT4[2] Filter Enable for EXT_INT4[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT4[1] Filter Enable for EXT_INT4[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT4[0] 4.3.2.101 EXT_INT4_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x081C, Reset Value = 0x0000_0000 Name RSVD FLTEN4[4] FLTWIDTH4[4] Bit [31:8] [7] [6:0] Type – RW RW Description Reserved Filter Enable for EXT_INT4[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT4[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x000000 0x0 0x00 4-87 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.102 EXT_INT5_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0820, Reset Value = 0x0000_0000 Name FLTEN5[3] FLTWIDTH5[3] FLTEN5[2] FLTWIDTH5[2] FLTEN5[1] FLTWIDTH5[1] FLTEN5[0] FLTWIDTH5[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT5[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT5[3] Filter Enable for EXT_INT5[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT5[2] Filter Enable for EXT_INT5[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT5[1] Filter Enable for EXT_INT5[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT5[0] 4.3.2.103 EXT_INT5_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x0824, Reset Value = 0x0000_0000 Name RSVD FLTEN5[4] FLTWIDTH5[4] Bit [31:8] [7] [6:0] Type – RW RW Description Reserved Filter Enable for EXT_INT5[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT5[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x000000 0x0 0x00 4-88 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.104 EXT_INT6_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0828, Reset Value = 0x0000_0000 Name FLTEN6[3] FLTWIDTH6[3] FLTEN6[2] FLTWIDTH6[2] FLTEN6[1] FLTWIDTH6[1] FLTEN6[0] FLTWIDTH6[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT6[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT6[3] Filter Enable for EXT_INT6[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT6[2] Filter Enable for EXT_INT6[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT6[1] Filter Enable for EXT_INT6[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT6[0] 4.3.2.105 EXT_INT6_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x082C, Reset Value = 0x0000_0000 Name RSVD Bit [31:0] Type – Reserved Description Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x00000000 4-89 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.106 EXT_INT7_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0830, Reset Value = 0x0000_0000 Name FLTEN7[3] FLTWIDTH7[3] FLTEN7[2] FLTWIDTH7[2] FLTEN7[1] FLTWIDTH7[1] FLTEN7[0] FLTWIDTH7[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT7[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT7[3] Filter Enable for EXT_INT7[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT7[2] Filter Enable for EXT_INT7[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT7[1] Filter Enable for EXT_INT7[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT7[0] 4.3.2.107 EXT_INT7_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x0834, Reset Value = 0x0000_0000 Name RSVD Bit [31:0] Type – Reserved Description Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x00000000 4-90 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.108 EXT_INT13_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0860, Reset Value = 0x0000_0000 Name FLTEN13[3] FLTWIDTH13[3] FLTEN13[2] FLTWIDTH13[2] FLTEN13[1] FLTWIDTH13[1] FLTEN13[0] FLTWIDTH13[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT13[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT13[3] Filter Enable for EXT_INT13[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT13[2] Filter Enable for EXT_INT13[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT13[1] Filter Enable for EXT_INT13[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT13[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-91 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.109 EXT_INT13_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x0864, Reset Value = 0x0000_0000 Name FLTEN13[7] FLTWIDTH13[7] FLTEN13[6] FLTWIDTH13[6] FLTEN13[5] FLTWIDTH13[5] FLTEN13[4] FLTWIDTH13[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT13[7] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT13[7] Filter Enable for EXT_INT13[6] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT13[6] Filter Enable for EXT_INT13[5] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT13[5] Filter Enable for EXT_INT13[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT13[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-92 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.110 EXT_INT14_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0868, Reset Value = 0x0000_0000 Name FLTEN14[3] FLTWIDTH14[3] FLTEN14[2] FLTWIDTH14[2] FLTEN14[1] FLTWIDTH14[1] FLTEN14[0] FLTWIDTH14[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT14[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT14[3] Filter Enable for EXT_INT14[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT14[2] Filter Enable for EXT_INT14[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT14[1] Filter Enable for EXT_INT14[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT14[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-93 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.111 EXT_INT14_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x086C, Reset Value = 0x0000_0000 Name FLTEN14[7] FLTWIDTH14[7] FLTEN14[6] FLTWIDTH14[6] FLTEN14[5] FLTWIDTH14[5] FLTEN14[4] FLTWIDTH14[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT14[7] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT14[7] Filter Enable for EXT_INT14[6] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT14[6] Filter Enable for EXT_INT14[5] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT14[5] Filter Enable for EXT_INT14[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT14[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-94 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.112 EXT_INT15_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0870, Reset Value = 0x0000_0000 Name FLTEN15[3] FLTWIDTH15[3] FLTEN15[2] FLTWIDTH15[2] FLTEN15[1] FLTWIDTH15[1] FLTEN15[0] FLTWIDTH15[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT15[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT15[3] Filter Enable for EXT_INT15[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT15[2] Filter Enable for EXT_INT15[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT15[1] Filter Enable for EXT_INT15[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT15[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-95 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.113 EXT_INT15_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x0874, Reset Value = 0x0000_0000 Name FLTEN15[7] FLTWIDTH15[7] FLTEN15[6] Bit [31] [30:24] [23] Type RW RW RW Description Filter Enable for EXT_INT15[7] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT15[7] Filter Enable for EXT_INT15[6] 0x0 = Disables filter 0x1 = Enables filter FLTWIDTH15[6] [22:16] RW Filtering width of EXT_INT15[6] FLTEN15[5] FLTWIDTH15[5] FLTEN15[4] FLTWIDTH15[4] [15] [14:8] [7] [6:0] Filter Enable for EXT_INT15[5] RW 0x0 = Disables filter 0x1 = Enables filter RW Filtering width of EXT_INT15[5] Filter Enable for EXT_INT15[4] RW 0x0 = Disables filter 0x1 = Enables filter RW Filtering width of EXT_INT15[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-96 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.114 EXT_INT16_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0878, Reset Value = 0x0000_0000 Name FLTEN16[3] FLTWIDTH16[3] FLTEN16[2] FLTWIDTH16[2] FLTEN16[1] FLTWIDTH16[1] FLTEN16[0] FLTWIDTH16[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT16[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT16[3] Filter Enable for EXT_INT16[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT16[2] Filter Enable for EXT_INT16[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT16[1] Filter Enable for EXT_INT16[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT16[0] 4.3.2.115 EXT_INT16_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x087C, Reset Value = 0x0000_0000 Name RSVD FLTEN16[5] FLTWIDTH16[5] FLTEN16[4] FLTWIDTH16[4] Bit [31:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW Description Reserved Filter Enable for EXT_INT16[5] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT16[5] Filter Enable for EXT_INT16[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT16[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x0000 0x0 0x00 0x0 0x00 4-97 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.116 EXT_INT21_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0880, Reset Value = 0x0000_0000 Name FLTEN17[3] FLTWIDTH17[3] FLTEN17[2] FLTWIDTH17[2] FLTEN17[1] FLTWIDTH17[1] FLTEN17[0] FLTWIDTH17[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT21[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT21[3] Filter Enable for EXT_INT21[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT21[2] Filter Enable for EXT_INT21[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT21[1] Filter Enable for EXT_INT21[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT21[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-98 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.117 EXT_INT21_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x0884, Reset Value = 0x0000_0000 Name FLTEN17[7] FLTWIDTH17[7] FLTEN17[6] FLTWIDTH17[6] FLTEN17[5] FLTWIDTH17[5] FLTEN17[4] FLTWIDTH17[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT21[7] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT21[7] Filter Enable for EXT_INT21[6] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT21[6] Filter Enable for EXT_INT21[5] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT21[5] Filter Enable for EXT_INT21[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT21[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-99 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.118 EXT_INT22_FLTCON0  Base Address: 0x1140_0000  Address = Base Address + 0x0888, Reset Value = 0x0000_0000 Name FLTEN18[3] FLTWIDTH18[3] FLTEN18[2] FLTWIDTH18[2] FLTEN18[1] FLTWIDTH18[1] FLTEN18[0] FLTWIDTH18[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT22[3] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT22[3] Filter Enable for EXT_INT22[2] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT22[2] Filter Enable for EXT_INT22[1] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT22[1] Filter Enable for EXT_INT22[0] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT22[0] 4.3.2.119 EXT_INT22_FLTCON1  Base Address: 0x1140_0000  Address = Base Address + 0x088C, Reset Value = 0x0000_0000 Name RSVD FLTEN18[4] FLTWIDTH18[4] Bit [31:8] [7] [6:0] Type – RW RW Description Reserved Filter Enable for EXT_INT22[4] 0x0 = Disables filter 0x1 = Enables filter Filtering width of EXT_INT22[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x000000 0x0 0x00 4-100 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.120 EXT_INT1_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0900, Reset Value = 0x0000_00FF Name RSVD EXT_INT1_MASK[7] EXT_INT1_MASK[6] EXT_INT1_MASK[5] EXT_INT1_MASK[4] EXT_INT1_MASK[3] EXT_INT1_MASK[2] EXT_INT1_MASK[1] EXT_INT1_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 4.3.2.121 EXT_INT2_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0904, Reset Value = 0x0000_003F Name RSVD EXT_INT2_MASK[5] EXT_INT2_MASK[4] EXT_INT2_MASK[3] EXT_INT2_MASK[2] EXT_INT2_MASK[1] EXT_INT2_MASK[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 0x1 4-101 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.122 EXT_INT3_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0908, Reset Value = 0x0000_00FF Name RSVD EXT_INT3_MASK[7] EXT_INT3_MASK[6] EXT_INT3_MASK[5] EXT_INT3_MASK[4] EXT_INT3_MASK[3] EXT_INT3_MASK[2] EXT_INT3_MASK[1] EXT_INT3_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-102 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.123 EXT_INT4_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x090C, Reset Value = 0x0000_001F Name RSVD EXT_INT4_MASK[4] EXT_INT4_MASK[3] EXT_INT4_MASK[2] EXT_INT4_MASK[1] EXT_INT4_MASK[0] Bit [31:5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 4.3.2.124 EXT_INT5_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0910, Reset Value = 0x0000_001F Name RSVD EXT_INT5_MASK[4] EXT_INT5_MASK[3] EXT_INT5_MASK[2] EXT_INT5_MASK[1] EXT_INT5_MASK[0] Bit [31:5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 4-103 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.125 EXT_INT6_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0914, Reset Value = 0x0000_000F Name RSVD EXT_INT6_MASK[3] EXT_INT6_MASK[2] EXT_INT6_MASK[1] EXT_INT6_MASK[0] Bit [31:4] [3] [2] [1] [0] Type – RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 4.3.2.126 EXT_INT7_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0918, Reset Value = 0x0000_000F Name RSVD EXT_INT7_MASK[3] EXT_INT7_MASK[2] EXT_INT7_MASK[1] EXT_INT7_MASK[0] Bit [31:4] [3] [2] [1] [0] Type – RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked Reset Value 0x0000000 0x1 0x1 0x1 0x1 Reset Value 0x0000000 0x1 0x1 0x1 0x1 4-104 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.127 EXT_INT13_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0930, Reset Value = 0x0000_00FF Name RSVD EXT_INT13_MASK[7] EXT_INT13_MASK[6] EXT_INT13_MASK[5] EXT_INT13_MASK[4] EXT_INT13_MASK[3] EXT_INT13_MASK[2] EXT_INT13_MASK[1] EXT_INT13_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-105 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.128 EXT_INT14_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0934, Reset Value = 0x0000_00FF Name RSVD EXT_INT14_MASK[7] EXT_INT14_MASK[6] EXT_INT14_MASK[5] EXT_INT14_MASK[4] EXT_INT14_MASK[3] EXT_INT14_MASK[2] EXT_INT14_MASK[1] EXT_INT14_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-106 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.129 EXT_INT15_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0938, Reset Value = 0x0000_00FF Name RSVD EXT_INT15_MASK[7] EXT_INT15_MASK[6] EXT_INT15_MASK[5] EXT_INT15_MASK[4] EXT_INT15_MASK[3] EXT_INT15_MASK[2] EXT_INT15_MASK[1] EXT_INT15_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 4.3.2.130 EXT_INT16_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x093C, Reset Value = 0x0000_003F Name RSVD EXT_INT16_MASK[5] EXT_INT16_MASK[4] EXT_INT16_MASK[3] EXT_INT16_MASK[2] EXT_INT16_MASK[1] EXT_INT16_MASK[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 0x1 4-107 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.131 EXT_INT21_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0940, Reset Value = 0x0000_00FF Name RSVD EXT_INT21_MASK[7] EXT_INT21_MASK[6] EXT_INT21_MASK[5] EXT_INT21_MASK[4] EXT_INT21_MASK[3] EXT_INT21_MASK[2] EXT_INT21_MASK[1] EXT_INT21_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 4.3.2.132 EXT_INT22_MASK  Base Address: 0x1140_0000  Address = Base Address + 0x0944, Reset Value = 0x0000_001F Name RSVD EXT_INT22_MASK[4] EXT_INT22_MASK[3] EXT_INT22_MASK[2] EXT_INT22_MASK[1] EXT_INT22_MASK[0] Bit [31:5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW Description Reserved 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked 0x0 = Enables interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 4-108 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.133 EXT_INT1_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A00, Reset Value = 0x0000_0000 Name RSVD EXT_INT1_PEND[7] EXT_INT1_PEND[6] EXT_INT1_PEND[5] EXT_INT1_PEND[4] EXT_INT1_PEND[3] EXT_INT1_PEND[2] EXT_INT1_PEND[1] EXT_INT1_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 =Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 4.3.2.134 EXT_INT2_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A04, Reset Value = 0x0000_0000 Name RSVD EXT_INT2_PEND[5] EXT_INT2_PEND[4] EXT_INT2_PEND[3] EXT_INT2_PEND[2] EXT_INT2_PEND[1] EXT_INT2_PEND[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 4-109 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.135 EXT_INT3_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A08, Reset Value = 0x0000_0000 Name RSVD EXT_INT3_PEND[7] EXT_INT3_PEND[6] EXT_INT3_PEND[5] EXT_INT3_PEND[4] EXT_INT3_PEND[3] EXT_INT3_PEND[2] EXT_INT3_PEND[1] EXT_INT3_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-110 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.136 EXT_INT4_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A0C, Reset Value = 0x0000_0000 Name RSVD EXT_INT4_PEND[4] EXT_INT4_PEND[3] EXT_INT4_PEND[2] EXT_INT4_PEND[1] EXT_INT4_PEND[0] Bit [31:5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 4.3.2.137 EXT_INT5_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A10, Reset Value = 0x0000_0000 Name RSVD EXT_INT5_PEND[4] EXT_INT5_PEND[3] EXT_INT5_PEND[2] EXT_INT5_PEND[1] EXT_INT5_PEND[0] Bit [31:5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 4-111 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.138 EXT_INT6_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A14, Reset Value = 0x0000_0000 Name RSVD EXT_INT6_PEND[3] EXT_INT6_PEND[2] EXT_INT6_PEND[1] EXT_INT6_PEND[0] Bit [31:4] [3] [2] [1] [0] Type – RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 4.3.2.139 EXT_INT7_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A18, Reset Value = 0x0000_0000 Name RSVD EXT_INT7_PEND[3] EXT_INT7_PEND[2] EXT_INT7_PEND[1] EXT_INT7_PEND[0] Bit [31:4] [3] [2] [1] [0] Type – RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x0000000 0x0 0x0 0x0 0x0 Reset Value 0x0000000 0x0 0x0 0x0 0x0 4-112 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.140 EXT_INT13_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A30, Reset Value = 0x0000_0000 Name RSVD EXT_INT13_PEND[7] EXT_INT13_PEND[6] EXT_INT13_PEND[5] EXT_INT13_PEND[4] EXT_INT13_PEND[3] EXT_INT13_PEND[2] EXT_INT13_PEND[1] EXT_INT13_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-113 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.141 EXT_INT14_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A34, Reset Value = 0x0000_0000 Name RSVD EXT_INT14_PEND[7] EXT_INT14_PEND[6] EXT_INT14_PEND[5] EXT_INT14_PEND[4] EXT_INT14_PEND[3] EXT_INT14_PEND[2] EXT_INT14_PEND[1] EXT_INT14_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-114 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.142 EXT_INT15_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A38, Reset Value = 0x0000_0000 Name RSVD EXT_INT15_PEND[7] EXT_INT15_PEND[6] EXT_INT15_PEND[5] EXT_INT15_PEND[4] EXT_INT15_PEND[3] EXT_INT15_PEND[2] EXT_INT15_PEND[1] EXT_INT15_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 4.3.2.143 EXT_INT16_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A3C, Reset Value = 0x0000_0000 Name RSVD EXT_INT16_PEND[5] EXT_INT16_PEND[4] EXT_INT16_PEND[3] EXT_INT16_PEND[2] EXT_INT16_PEND[1] EXT_INT16_PEND[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 4-115 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.144 EXT_INT21_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A40, Reset Value = 0x0000_0000 Name RSVD EXT_INT21_PEND[7] EXT_INT21_PEND[6] EXT_INT21_PEND[5] EXT_INT21_PEND[4] EXT_INT21_PEND[3] EXT_INT21_PEND[2] EXT_INT21_PEND[1] EXT_INT21_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 4.3.2.145 EXT_INT22_PEND  Base Address: 0x1140_0000  Address = Base Address + 0x0A44, Reset Value = 0x0000_0000 Name RSVD EXT_INT22_PEND[4] EXT_INT22_PEND[3] EXT_INT22_PEND[2] EXT_INT22_PEND[1] EXT_INT22_PEND[0] Bit [31:5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 4-116 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.146 EXT_INT_SERVICE_XB  Base Address: 0x1140_0000  Address = Base Address + 0x0B08, Reset Value = 0x0000_0000 Name RSVD SVC_Group_Num SVC_Num Bit [31:8] [7:3] [2:0] Type RW RW RW Description Reserved EXT_INT Service group number 0x1 = EXT_INT1 0x2 = EXT_INT2 0x3 = EXT_INT3 0x4 = EXT_INT4 0x5 = EXT_INT5 0x6 = EXT_INT6 0x7 = EXT_INT7 0x8 = EXT_INT13 0x9 = EXT_INT14 0xA = EXT_INT15 0xB = EXT_INT16 0xC = EXT_INT21 0xD = EXT_INT22 Interrupt number to be serviced 4.3.2.147 EXT_INT_SERVICE_PEND_XB  Base Address: 0x1140_0000  Address = Base Address + 0x0B0C, Reset Value = 0x0000_0000 Name RSVD SVC_PEND Bit [31:8] [7:0] Type RW RW Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x0000000 0x00 0x0 Reset Value 0x0000000 0x00 4-117 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.148 EXT_INT_GRPFIXPRI_XB  Base Address: 0x1140_0000  Address = Base Address + 0x0B10, Reset Value = 0x0000_0000 Name RSVD Highest_GRP_NUM Bit [31:4] [3:0] Type – RW Description Reserved When fixed group priority mode = 0 to 12, then group number should be of the highest priority. 0x0 = EXT_INT1 0x1 = EXT_INT2 0x2 = EXT_INT3 0x3 = EXT_INT4 0x4 = EXT_INT5 0x5 = EXT_INT6 0x6 = EXT_INT7 0x7 = EXT_INT13 0x8 = EXT_INT14 0x9 = EXT_INT15 0xA = EXT_INT16 0xB = EXT_INT21 0xC = EXT_INT22 Reset Value 0x0000000 0x00 4-118 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.149 EXT_INT1_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B14, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 0 (EXT_INT1) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.2.150 EXT_INT2_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B18, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 1 (EXT_INT2) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.2.151 EXT_INT3_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B1C, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 2 (EXT_INT3) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.2.152 EXT_INT4_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B20, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 3 (EXT_INT4) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-119 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.153 EXT_INT5_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B24, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 4 (EXT_INT5) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.2.154 EXT_INT6_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B28, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 5 (EXT_INT6) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.2.155 EXT_INT7_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B2C, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 6 (EXT_INT7) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-120 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.156 EXT_INT13_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B44, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 7 (EXT_INT13) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.2.157 EXT_INT14_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B48, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 8 (EXT_INT14) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.2.158 EXT_INT15_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B4C, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 9 (EXT_INT15) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.2.159 EXT_INT16_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B50, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 10 (EXT_INT16) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-121 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.160 EXT_INT21_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B54, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 11 (EXT_INT21) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.2.161 EXT_INT22_FIXPRI  Base Address: 0x1140_0000  Address = Base Address + 0x0B58, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 12 (EXT_INT22) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-122 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.2.162 PDNEN  Base Address: 0x1140_0000  Address = Base Address + 0x0F80, Reset Value = 0x00 Name RSVD PDNEN_CFG PDNEN Bit Type Description [7:2] – Reserved [1] RW 0 = Automatically by power down mode 1 = by PDNEN bit Power down mode pad state enable register. 0 = PADs Controlled by normal mode 1 = PADs Controlled by Power Down mode control registers [0] RW This bit is set to "1" automaticially when system enters into Power down mode and can be cleared by writing "0" to this bit or cold reset. After wake up from Power down mode, this bit maintains value "1" until writing "0" Reset Value 0x00 0x0 0x0 4-123 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3 Part 2 For the following SFRs, Sets the value does not take effect immediately. It takes at least 800 APB clocks for the value to take effect after the SFR is actually changed The SFRs are: GPK0PUD, GPK0DRV, GPK1PUD, GPK1DRV, GPK2PUD, GPK2DRV, GPK3PUD, GPK3DRV, GPL0PUD, GPL0DRV, GPL1PUD, GPL1DRV, GPL2PUD, GPL2DRV, GPY0PUD, GPY0DRV, GPY1PUD, GPY1DRV, GPY2PUD, GPY2DRV, GPY3PUD, GPY3DRV, GPY4PUD, GPY4DRV, GPY5PUD, GPY5DRV, GPY6PUD, GPY6DRV, GPM0PUD, GPM0DRV, GPM1PUD, GPM1DRV, GPM2PUD, GPM2DRV, GPM3PUD, GPM3DRV, GPM4PUD, GPM4DRV. 4-124 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.1 GPK0CON  Base Address: 0x1100_0000  Address = Base Address + 0x0040, Reset Value = 0x0000_0000 Name GPK0CON[6] GPK0CON[5] GPK0CON[4] GPK0CON[3] GPK0CON[2] GPK0CON[1] GPK0CON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = SD_0_DATA[3] 0x3 = SD_4_DATA[3] 0x4 to 0xE = Reserved 0xF = EXT_INT23[6] 0x0 = Input 0x1 = Output 0x2 = SD_0_DATA[2] 0x3 = SD_4_DATA[2] 0x4 to 0xE = Reserved 0xF = EXT_INT23[5] 0x0 = Input 0x1 = Output 0x2 = SD_0_DATA[1] 0x3 = SD_4_DATA[1] 0x4 to 0xE = Reserved 0xF = EXT_INT23[4] 0x0 = Input 0x1 = Output 0x2 = SD_0_DATA[0] 0x3 = SD_4_DATA[0] 0x4 to 0xE = Reserved 0xF = EXT_INT23[3] 0x0 = Input 0x1 = Output 0x2 = SD_0_CDn 0x3 = SD_4_CDn 0x4 = GNSS_GPIO[8] 0x5 to 0xE = Reserved 0xF = EXT_INT23[2] 0x0 = Input 0x1 = Output 0x2 = SD_0_CMD 0x3 = SD_4_CMD 0x4 to 0xE = Reserved 0xF = EXT_INT23[1] 0x0 = Input 0x1 = Output 0x2 = SD_0_CLK 0x3 = SD_4_CLK 0x4 to 0xE = Reserved 0xF = EXT_INT23[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-125 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.2 GPK0DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0044, Reset Value = 0x00 Name Bit GPK0DAT[6:0] [6:0] Type RWX Description When you configure port as input port, then corresponding bit is pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.3 GPK0PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0048, Reset Value = 0x1555 Name GPK0PUD[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x1555 4.3.3.4 GPK0DRV  Base Address: 0x1100_0000  Address = Base Address + 0x004C, Reset Value = 0x00_2AAA Name GPK0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 6 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x2AAA 4-126 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.5 GPK0CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0050, Reset Value = 0x0000 Name GPK0[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.6 GPK0PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0054, Reset Value = 0x0000 Name GPK0[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-127 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.7 GPK1CON  Base Address: 0x1100_0000  Address = Base Address + 0x0060, Reset Value = 0x0000_0000 Name GPK1CON[6] GPK1CON[5] GPK1CON[4] GPK1CON[3] GPK1CON[2] GPK1CON[1] GPK1CON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = SD_1_DATA[3] 0x3 = SD_0_DATA[7] 0x4 = SD_4_DATA[7] 0x5 to 0xE = Reserved 0xF = EXT_INT24[6] 0x0 = Input 0x1 = Output 0x2 = SD_1_DATA[2] 0x3 = SD_0_DATA[6] 0x4 = SD_4_DATA[6] 0x5 to 0xE = Reserved 0xF = EXT_INT24[5] 0x0 = Input 0x1 = Output 0x2 = SD_1_DATA[1] 0x3 = SD_0_DATA[5] 0x4 = SD_4_DATA[5] 0x5 to 0xE = Reserved 0xF = EXT_INT24[4] 0x0 = Input 0x1 = Output 0x2 = SD_1_DATA[0] 0x3 = SD_0_DATA[4] 0x4 = SD_4_DATA[4] 0x5 to 0xE = Reserved 0xF = EXT_INT24[3] 0x0 = Input 0x1 = Output 0x2 = SD_1_CDn 0x3 = GNSS_GPIO[9] 0x4 = SD_4_nRESET_OUT 0x5 to 0xE = Reserved 0xF = EXT_INT24[2] 0x0 = Input 0x1 = Output 0x2 = SD_1_CMD 0x3 to 0xE = Reserved 0xF = EXT_INT24[1] 0x0 = Input 0x1 = Output 0x2 = SD_1_CLK 0x3 to 0xE = Reserved Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-128 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description 0xF = EXT_INT24[0] Reset Value 4-129 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.8 GPK1DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0064, Reset Value = 0x00 Name Bit GPK1DAT[6:0] [6:0] Type RWX Description When you configure port as input port, the corresponding bit is the pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.9 GPK1PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0068, Reset Value = 0x1555 Name GPK1PUD[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x1555 4.3.3.10 GPK1DRV  Base Address: 0x1100_0000  Address = Base Address + 0x006C, Reset Value = 0x00_0000 Name GPK1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 6 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-130 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.11 GPK1CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0070, Reset Value = 0x0000 Name GPK1[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.12 GPK1PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0074, Reset Value = 0x0000 Name GPK1[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-131 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.13 GPK2CON  Base Address: 0x1100_0000  Address = Base Address + 0x0080, Reset Value = 0x0000_0000 Name GPK2CON[6] GPK2CON[5] GPK2CON[4] GPK2CON[3] GPK2CON[2] GPK2CON[1] GPK2CON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = SD_2_DATA[3] 0x3 to 0xE = Reserved 0xF = EXT_INT25[6] 0x0 = Input 0x1 = Output 0x2 = SD_2_DATA[2] 0x3 to 0xE = Reserved 0xF = EXT_INT25[5] 0x0 = Input 0x1 = Output 0x2 = SD_2_DATA[1] 0x3 to 0xE = Reserved 0xF = EXT_INT25[4] 0x0 = Input 0x1 = Output 0x2 = SD_2_DATA[0] 0x3 to 0xE = Reserved 0xF = EXT_INT25[3] 0x0 = Input 0x1 = Output 0x2 = SD_2_CDn 0x3 = GNSS_GPIO[10] 0x4 to 0xE = Reserved 0xF = EXT_INT25[2] 0x0 = Input 0x1 = Output 0x2 = SD_2_CMD 0x3 to 0xE = Reserved 0xF = EXT_INT25[1] 0x0 = Input 0x1 = Output 0x2 = SD_2_CLK 0x3 to 0xE = Reserved 0xF = EXT_INT25[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-132 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.14 GPK2DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0084, Reset Value = 0x00 Name Bit GPK2DAT[6:0] [6:0] Type RWX Description When you configure port as input port then corresponding bit is pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.15 GPK2PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0088, Reset Value = 0x1555 Name GPK2PUD[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x1555 4.3.3.16 GPK2DRV  Base Address: 0x1100_0000  Address = Base Address + 0x008C, Reset Value = 0x00_0000 Name GPK2DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 6 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-133 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.17 GPK2CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0090, Reset Value = 0x0000 Name GPK2[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.18 GPK2PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0094, Reset Value = 0x0000 Name GPK2[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Enables Reserved 0x3 = Pull-up Reset Value 0x00 Reset Value 0x00 4-134 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.19 GPK3CON  Base Address: 0x1100_0000  Address = Base Address + 0x00A0, Reset Value = 0x0000_0000 Name GPK3CON[6] GPK3CON[5] GPK3CON[4] GPK3CON[3] GPK3CON[2] GPK3CON[1] GPK3CON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = SD_3_DATA[3] 0x3 = SD_2_DATA[7] 0x4 to 0xE = Reserved 0xF = EXT_INT26[6] 0x0 = Input 0x1 = Output 0x2 = SD_3_DATA[2] 0x3 = SD_2_DATA[6] 0x4 to 0xE = Reserved 0xF = EXT_INT26[5] 0x0 = Input 0x1 = Output 0x2 = SD_3_DATA[1] 0x3 = SD_2_DATA[5] 0x4 to 0xE = Reserved 0xF = EXT_INT26[4] 0x0 = Input 0x1 = Output 0x2 = SD_3_DATA[0] 0x3 = SD_2_DATA[4] 0x4 to 0xE = Reserved 0xF = EXT_INT26[3] 0x0 = Input 0x1 = Output 0x2 = SD_3_CDn 0x3 = GNSS_GPIO[11] 0x4 to 0xE = Reserved 0xF = EXT_INT26[2] 0x0 = Input 0x1 = Output 0x2 = SD_3_CMD 0x3 to 0xE = Reserved 0xF = EXT_INT26[1] 0x0 = Input 0x1 = Output 0x2 = SD_3_CLK 0x3 to 0xE = Reserved 0xF = EXT_INT26[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-135 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.20 GPK3DAT  Base Address: 0x1100_0000  Address = Base Address + 0x00A4, Reset Value = 0x00 Name Bit GPK3DAT[6:0] [6:0] Type RWX Description When you configure port as input port, then corresponding bit is pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.21 GPK3PUD  Base Address: 0x1100_0000  Address = Base Address + 0x00A8, Reset Value = 0x1555 Name GPK3PUD[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x1555 4.3.3.22 GPK3DRV  Base Address: 0x1100_0000  Address = Base Address + 0x00AC, Reset Value = 0x00_0000 Name GPK3DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 6 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-136 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.23 GPK3CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x00B0, Reset Value = 0x0000 Name GPK3[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.24 GPK3PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x00B4, Reset Value = 0x0000 Name GPK3[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-137 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.25 GPL0CON  Base Address: 0x1100_0000  Address = Base Address + 0x00C0, Reset Value = 0x0000_0000 Name GPL0CON[6] GPL0CON[5] GPL0CON[4] GPL0CON[3] GPL0CON[2] GPL0CON[1] GPL0CON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = GNSS_RF_RSTN 0x3 to 0xE = Reserved 0xF = EXT_INT27[6] 0x0 = Input 0x1 = Output 0x2 to 0xE = Reserved 0xF = EXT_INT27[5] 0x0 = Input 0x1 = Output 0x2 = GNSS_QMAG 0x3 to 0xE = Reserved 0xF = EXT_INT27[4] 0x0 = Input 0x1 = Output 0x2 = GNSS_QSIGN 0x3 to 0xE = Reserved 0xF = EXT_INT27[3] 0x0 = Input 0x1 = Output 0x2 = GNSS_IMAG 0x3 to 0xE = Reserved 0xF = EXT_INT27[2] 0x0 = Input 0x1 = Output 0x2 = GNSS_ISIGN 0x3 to 0xE = Reserved 0xF = EXT_INT27[1] 0x0 = Input 0x1 = Output 0x2 = GNSS_SYNC 0x3 to 0xE = Reserved 0xF = EXT_INT27[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-138 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.26 GPL0DAT  Base Address: 0x1100_0000  Address = Base Address + 0x00C4, Reset Value = 0x00 Name Bit GPL0DAT[6:0] [6:0] Type RWX Description When you configure port as input port, then corresponding bit is pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.27 GPL0PUD  Base Address: 0x1100_0000  Address = Base Address + 0x00C8, Reset Value = 0x1555 Name GPL0PUD[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x1555 4.3.3.28 GPL0DRV  Base Address: 0x1100_0000  Address = Base Address + 0x00CC, Reset Value = 0x00_0000 Name GPL0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 6 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-139 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.29 GPL0CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x00D0, Reset Value = 0x0000 Name GPL0[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.30 GPL0PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x00D4, Reset Value = 0x0000 Name GPL0[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-140 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.31 GPL1CON  Base Address: 0x1100_0000  Address = Base Address + 0x00E0, Reset Value = 0x0000_0000 Name GPL1CON[1] GPL1CON[0] Bit Type Description 0x0 = Input 0x1 = Output [7:4] RW 0x2 = GNSS_SDA 0x3 to 0xE = Reserved 0xF = EXT_INT28[1] 0x0 = Input 0x1 = Output [3:0] RW 0x2 = GNSS_SCL 0x3 to 0xE = Reserved 0xF = EXT_INT28[0] Reset Value 0x00 0x00 4.3.3.32 GPL1DAT  Base Address: 0x1100_0000  Address = Base Address + 0x00E4, Reset Value = 0x00 Name Bit GPL1DAT[1:0] [1:0] Type RWX Description When you configure port as input port, then corresponding bit is pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.33 GPL1PUD  Base Address: 0x1100_0000  Address = Base Address + 0x00E8, Reset Value = 0x0005 Name GPL1PUD[n] Bit [2n + 1:2n] n = 0 to 1 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0005 4-141 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.34 GPL1DRV  Base Address: 0x1100_0000  Address = Base Address + 0x00EC, Reset Value = 0x00_0000 Name GPL1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 1 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x 4.3.3.35 GPL1CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x00F0, Reset Value = 0x0000 Name GPL1[n] Bit [2n + 1:2n] n = 0 to 1 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.36 GPL1PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x00F4, Reset Value = 0x0000 Name GPL1[n] Bit [2n + 1:2n] n = 0 to 1 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 0x0000 Reset Value 0x00 Reset Value 0x00 4-142 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.37 GPL2CON  Base Address: 0x1100_0000  Address = Base Address + 0x0100, Reset Value = 0x0000_0000 Name GPL2CON[7] GPL2CON[6] GPL2CON[5] GPL2CON[4] GPL2CON[3] GPL2CON[2] GPL2CON[1] GPL2CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = GNSS_GPIO[7] 0x3 = KP_COL[7] 0x4 to 0xE = Reserved 0xF = EXT_INT29[7] 0x0 = Input 0x1 = Output 0x2 = GNSS_GPIO[6] 0x3 = KP_COL[6] 0x4 to 0xE = Reserved 0xF = EXT_INT29[6] 0x0 = Input 0x1 = Output 0x2 = GNSS_GPIO[5] 0x3 = KP_COL[5] 0x4 to 0xE = Reserved 0xF = EXT_INT29[5] 0x0 = Input 0x1 = Output 0x2 = GNSS_GPIO[4] 0x3 = KP_COL[4] 0x4 to 0xE = Reserved 0xF = EXT_INT29[4] 0x0 = Input 0x1 = Output 0x2 = GNSS_GPIO[3] 0x3 = KP_COL[3] 0x4 to 0xE = Reserved 0xF = EXT_INT29[3] 0x0 = Input 0x1 = Output 0x2 = GNSS_GPIO[2] 0x3 = KP_COL[2] 0x4 to 0xE = Reserved 0xF = EXT_INT29[2] 0x0 = Input 0x1 = Output 0x2 = GNSS_GPIO[1] 0x3 = KP_COL[1] 0x4 to 0xE = Reserved 0xF = EXT_INT29[1] 0x0 = Input 0x1 = Output Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-143 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description 0x2 = GNSS_GPIO[0] 0x3 = KP_COL[0] 0x4 to 0xE = Reserved 0xF = EXT_INT29[0] Reset Value 4-144 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.38 GPL2DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0104, Reset Value = 0x00 Name Bit GPL2DAT[7:0] [7:0] Type RWX Description When you configure port as input port, then corresponding bit is pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.39 GPL2PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0108, Reset Value = 0x5555 Name GPL2PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Disables Pull-up Reset Value 0x5555 4.3.3.40 GPL2DRV  Base Address: 0x1100_0000  Address = Base Address + 0x010C, Reset Value = 0x00_0000 Name GPL2DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-145 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.41 GPL2CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0110, Reset Value = 0x0000 Name GPL2[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.42 GPL2PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0114, Reset Value = 0x0000 Name GPL2[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-146 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.43 GPY0CON  Base Address: 0x1100_0000  Address = Base Address + 0x0120, Reset Value = 0x0000_0000 Name GPY0CON[5] GPY0CON[4] GPY0CON[3] GPY0CON[2] GPY0CON[1] GPY0CON[0] Bit [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = EBI_WEn 0x4 to 0xF = Reserved 0x0 = Input 0x1 = Output 0x2 = EBI_OEn 0x4 to 0xF = Reserved 0x0 = Input 0x1 = Output 0x2 = SROM_CSn[3] 0x3 = NF_CSn[1] 0x4 = Reserved 0x5 = OND_CSn[1] 0x4 to 0xF = Reserved 0x0 = Input 0x1 = Output 0x2 = SROM_CSn[2] 0x3 = NF_CSn[0] 0x4 = Reserved 0x5 = OND_CSn[0] 0x4 to 0xF = Reserved 0x0 = Input 0x1 = Output 0x2 = SROM_CSn[1] 0x3 = NF_CSn[3] 0x4 to 0xF = Reserved 0x0 = Input 0x1 = Output 0x2 = SROM_CSn[0] 0x3 = NF_CSn[2] 0x4 to 0xF = Reserved Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-147 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.44 GPY0DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0124, Reset Value = 0x00 Name Bit GPY0DAT[5:0] [5:0] Type RWX Description When you configure port as input port, the corresponding bit is the pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.45 GPY0PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0128, Reset Value = 0x0FFF Name GPY0PUD[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0FFF 4.3.3.46 GPY0DRV  Base Address: 0x1100_0000  Address = Base Address + 0x012C, Reset Value = 0x00_0AAA Name GPY0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 5 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0AAA 4-148 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.47 GPY0CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0130, Reset Value = 0x0000 Name GPY0[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.48 GPY0PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0134, Reset Value = 0x0000 Name GPY0[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-149 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.49 GPY1CON  Base Address: 0x1100_0000  Address = Base Address + 0x0140, Reset Value = 0x0000_0000 Name GPY1CON[3] GPY1CON[2] GPY1CON[1] GPY1CON[0] Bit [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = EBI_DATA_RDn 0x4 to 0xF = Reserved 0x0 = Input 0x1 = Output 0x2 = SROM_WAITn 0x4 to 0xF = Reserved 0x0 = Input 0x1 = Output 0x2 = EBI_BEn[1] 0x4 to 0xF = Reserved 0x0 = Input 0x1 = Output 0x2 = EBI_BEn[0] 0x4 to 0xF = Reserved Reset Value 0x00 0x00 0x00 0x00 4-150 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.50 GPY1DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0144, Reset Value = 0x00 Name Bit GPY1DAT[3:0] [3:0] Type RWX Description When you configure port as input port, then corresponding bit is pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.51 GPY1PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0148, Reset Value = 0x00FF Name GPY1PUD[n] Bit [2n + 1:2n] n = 0 to 3 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Disables Pull-up Reset Value 0x00FF 4.3.3.52 GPY1DRV  Base Address: 0x1100_0000  Address = Base Address + 0x014C, Reset Value = 0x00_00AA Name GPY1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 3 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x00AA 4-151 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.53 GPY1CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0150, Reset Value = 0x0000 Name GPY1[n] Bit [2n + 1:2n] n = 0 to 3 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.54 GPY1PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0154, Reset Value = 0x0000 Name GPY1[n] Bit [2n + 1:2n] n = 0 to 3 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-152 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.55 GPY2CON  Base Address: 0x1100_0000  Address = Base Address + 0x0160, Reset Value = 0x0000_0000 Name GPY2CON[5] GPY2CON[4] GPY2CON[3] GPY2CON[2] GPY2CON[1] GPY2CON[0] Bit [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = NF_RnB[3] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = NF_RnB[2] 0x3= Reserved 0x4= Reserved 0x5 = OND_RPn 0x6 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = NF_RnB[1] 0x3= Reserved 0x4= Reserved 0x5 = OND_INT[1] 0x6 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = NF_RnB[0] 0x3= Reserved 0x4= Reserved 0x5 = OND_INT[0] 0x6 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = NF_ALE 0x3= Reserved 0x4= Reserved 0x5 = OND_SMCLK 0x6 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = NF_CLE 0x3= Reserved 0x4= Reserved 0x5 = OND_ADDRVALID 0x6 to 0xE = Reserved Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-153 Exynos 4412_UM Name Bit Type 0xF = – 4 General Purpose Input/Output (GPIO) Control Description Reset Value 4-154 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.56 GPY2DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0164, Reset Value = 0x00 Name Bit GPY2DAT[5:0] [5:0] Type RWX Description When you configure port as input port, the corresponding bit is the pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.57 GPY2PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0168, Reset Value = 0x0FFF Name GPY2PUD[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0 FFF 4.3.3.58 GPY2DRV  Base Address: 0x1100_0000  Address = Base Address + 0x016C, Reset Value = 0x00_0AAA Name GPY2DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 5 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0AAA 4-155 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.59 GPY2CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0170, Reset Value = 0x0000 Name GPY2[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.60 GPY2PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0174, Reset Value = 0x0000 Name GPY2[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-156 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.61 GPY3CON  Base Address: 0x1100_0000  Address = Base Address + 0x0180, Reset Value = 0x0000_0000 Name GPY3CON[7] GPY3CON[6] GPY3CON[5] GPY3CON[4] GPY3CON[3] GPY3CON[2] GPY3CON[1] GPY3CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[7] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output, 0x2 = EBI_ADDR[6] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[5] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[4] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[3] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[2] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[1] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[0] 0x3 to 0xE = Reserved 0xF = – Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-157 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.62 GPY3DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0184, Reset Value = 0x00 Name Bit GPY3DAT[7:0] [7:0] Type RWX Description When you configure port as input port, then corresponding bit is pin state. When configuring as output port, the pin state should be same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.63 GPY3PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0188, Reset Value = 0x5555 Name GPY3PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.64 GPY3DRV  Base Address: 0x1100_0000  Address = Base Address + 0x018C, Reset Value = 0x00_AAAA Name GPY3DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0xAAAA 4-158 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.65 GPY3CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0190, Reset Value = 0x0000 Name GPY3[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.66 GPY3PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0194, Reset Value = 0x0000 Name GPY3[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-159 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.67 GPY4CON  Base Address: 0x1100_0000  Address = Base Address + 0x01A0, Reset Value = 0x0000_0000 Name GPY4CON[7] GPY4CON[6] GPY4CON[5] GPY4CON[4] GPY4CON[3] GPY4CON[2] GPY4CON[1] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] Type RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[15] 0x3= Reserved 0x4 = XhsiCAREADY 0x5 to 0xE = Reserved, 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[14] 0x3= Reserved 0x4 = XhsiACFLAG 0x5 to 0xE = Reserved, 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[13] 0x3= Reserved 0x4 = XhsiACDATA 0x5 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[12] 0x3= Reserved 0x4 = XhsiACWAKE 0x5 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[11] 0x3= Reserved 0x4 = XhsiACREADY 0x5 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[10] 0x3= Reserved 0x4 = XhsiCAFLAG 0x5 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-160 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name GPY4CON[0] Bit Type Description 0x2 = EBI_ADDR[9] 0x3= Reserved 0x4 = XhsiCADATA 0x5 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_ADDR[8] [3:0] RW 0x3= Reserved 0x4 = XhsiCAWAKE 0x5 to 0xE = Reserved 0xF = – Reset Value 0x00 4-161 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.68 GPY4DAT  Base Address: 0x1100_0000  Address = Base Address + 0x01A4, Reset Value = 0x00 Name Bit GPY4DAT[7:0] [7:0] Type RWX Description When you configure port as input port then corresponding bit is pin state. When configuring as output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.69 GPY4PUD  Base Address: 0x1100_0000  Address = Base Address + 0x01A8, Reset Value = 0x5555 Name GPY4PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.70 GPY4DRV  Base Address: 0x1100_0000  Address = Base Address + 0x01AC, Reset Value = 0x00_AAAA Name GPY4DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0xAAAA 4-162 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.71 GPY4CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x01B0, Reset Value = 0x0000 Name GPY4[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.72 GPY4PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x01B4, Reset Value = 0x0000 Name GPY4[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-163 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.73 GPY5CON  Base Address: 0x1100_0000  Address = Base Address + 0x01C0, Reset Value = 0x0000_0000 Name GPY5CON[7] GPY5CON[6] GPY5CON[5] GPY5CON[4] GPY5CON[3] GPY5CON[2] GPY5CON[1] GPY5CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[7] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[6] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[5] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[4] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[3] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[2] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input ]0x1 = Output 0x2 = EBI_DATA[1] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input ]0x1 = Output 0x2 = EBI_DATA[0] 0x3 to 0xE = Reserved 0xF = – Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-164 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.74 GPY5DAT  Base Address: 0x1100_0000  Address = Base Address + 0x01C4, Reset Value = 0x00 Name Bit GPY5DAT[7:0] [7:0] Type RWX Description When you configure port as input port, then corresponding bit is pin state. When configuring as output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.75 GPY5PUD  Base Address: 0x1100_0000  Address = Base Address + 0x01C8, Reset Value = 0x5555 Name GPY5PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Disables Pull-up Reset Value 0x5555 4.3.3.76 GPY5DRV  Base Address: 0x1100_0000  Address = Base Address + 0x01CC, Reset Value = 0x00_AAAA Name GPY5DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0xAAAA 4-165 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.77 GPY5CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x01D0, Reset Value = 0x0000 Name GPY5[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.78 GPY5PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x01D4, Reset Value = 0x0000 Name GPY5[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Disables Pull-up Reset Value 0x00 Reset Value 0x00 4-166 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.79 GPY6CON  Base Address: 0x1100_0000  Address = Base Address + 0x01E0, Reset Value = 0x0000_0000 Name GPY6CON[7] GPY6CON[6] GPY6CON[5] GPY6CON[4] GPY6CON[3] GPY6CON[2] GPY6CON[1] GPY6CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[15] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[14] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[13] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[12] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[11] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[10] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[9] 0x3 to 0xE = Reserved 0xF = – 0x0 = Input 0x1 = Output 0x2 = EBI_DATA[8] 0x3 to 0xE = Reserved 0xF = – Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-167 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.80 GPY6DAT  Base Address: 0x1100_0000  Address = Base Address + 0x01E4, Reset Value = 0x00 Name Bit GPY6DAT[7:0] [7:0] Type RWX Description When you configure port as input port then corresponding bit is pin state. When configuring as output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.81 GPY6PUD  Base Address: 0x1100_0000  Address = Base Address + 0x01E8, Reset Value = 0x5555 Name GPY6PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.82 GPY6DRV  Base Address: 0x1100_0000  Address = Base Address + 0x01EC, Reset Value = 0x00_AAAA Name GPY6DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0xAAAA 4-168 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.83 GPY6CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x01F0, Reset Value = 0x0000 Name GPY6[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.84 GPY6PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x01F4, Reset Value = 0x0000 Name GPY6[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-169 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.85 ETC0PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0208, Reset Value = 0x0400 Name ETC0PUD[n] Bit [2n + 1:2n] n = 0 to 5 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up ETC0PUD[1:0] controls XjTRSTn. ETC0PUD[3:2] controls XjTMS. ETC0PUD[5:4] controls XjTCK. ETC0PUD[7:6] controls XjTDI. ETC0PUD[9:8] controls XjTDO. ETC0PUD[11:10] controls XjDBGSEL. Reset Value 0x0400 4.3.3.86 ETC0DRV  Base Address: 0x1100_0000  Address = Base Address + 0x020C, Reset Value = 0x00_0000 Name ETC0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 5 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x ETC0DRV[1:0] controls XjTRSTn. ETC0DRV[3:2] controls XjTMS. ETC0DRV[5:4] controls XjTCK. ETC0DRV[7:6] controls XjTDI. ETC0DRV[9:8] controls XjTDO. ETC0DRV[11:10] controls XjDBGSEL. Reset Value 0x00 0x0000 4-170 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.87 ETC6PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0228, Reset Value = 0xC000 Name ETC6PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up ETC6PUD[1:0] controls XnRESET. ETC6PUD[3:2] controls XCLKOUT. ETC6PUD[5:4] controls XnRSTOUT. ETC6PUD[9:8] controls XRTCCLKO. ETC6PUD[11:10] controls XuotgDRVVBUS. ETC6PUD[13:12] controls XuhostPWREN. ETC6PUD[15:14] controls XuhostOVERCUR. Reset Value 0xC000 4-171 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.88 ETC6DRV  Base Address: 0x1100_0000  Address = Base Address + 0x022C, Reset Value = 0x00_0000 Name ETC6DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x ETC6DRV[1:0] controls XnRESET. ETC6DRV[3:2] controls XCLKOUT. ETC6DRV[5:4] controls XnRSTOUT. ETC6DRV[7:6] controls XnWRESET. ETC6DRV[9:8] controls XRTCCLKO. ETC6DRV[11:10] controls XuotgDRVVBUS. ETC6DRV[13:12] controls XuhostPWREN. ETC6DRV[15:14] controls XuhostOVERCUR. Reset Value 0x00 0x0000 4-172 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.89 GPM0CON  Base Address: 0x1100_0000  Address = Base Address + 0x0260, Reset Value = 0x0000_0000 Name GPM0CON[7] GPM0CON[6] GPM0CON[5] GPM0CON[4] GPM0CON[3] GPM0CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = CAM_B_DATA[6] 0x4 = XhsiCAFLAG 0x5 = TraceData[6] 0x6 to 0xE = Reserved 0xF = EXT_INT8[7] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = CAM_B_DATA[5] 0x4 = XhsiCADATA 0x5 = TraceData[5] 0x6 to 0xE = Reserved 0xF = EXT_INT8[6] 0x0 = Input 0x1 = Output, 0x2 = Reserved 0x3 = CAM_B_DATA[4], 0x4 = XhsiCAWAKE, 0x5 = TraceData[4], 0x6 to 0xE = Reserved, 0xF = EXT_INT8[5] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = CAM_B_DATA[3] 0x4 = TS_ERROR 0x5 = TraceData[3] 0x6 to 0xE = Reserved 0xF = EXT_INT8[4] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = CAM_B_DATA[2] 0x4 = TS_DATA 0x5 = TraceData[2] 0x6 to 0xE = Reserved 0xF = EXT_INT8[3] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = CAM_B_DATA[1] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-173 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description 0x4 = TS_VAL 0x5 = TraceData[1] 0x6 to 0xE = Reserved 0xF = EXT_INT8[2] 0x0 = Input 0x1 = Output 0x2 = Reserved GPM0CON[1] [7:4] RW 0x3 = CAM_B_DATA[0] 0x4 = TS_SYNC 0x5 = TraceData[0] 0x6 to 0xE = Reserved 0xF = EXT_INT8[1] 0x0 = Input 0x1 = Output 0x2 = Reserved GPM0CON[0] [3:0] RW 0x3 = CAM_B_PCLK 0x4 = TS_CLK 0x5 = TraceClk 0x6 to 0xE = Reserved 0xF = EXT_INT8[0] Reset Value 0x00 0x00 4-174 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.90 GPM0DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0264, Reset Value = 0x00 Name Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as GPM0DAT[7:0] [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.91 GPM0PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0268, Reset Value = 0x5555 Name GPM0PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.92 GPM0DRV  Base Address: 0x1100_0000  Address = Base Address + 0x026C, Reset Value = 0x00_0000 Name GPM0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-175 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.93 GPM0CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0270, Reset Value = 0x0000 Name GPM0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.94 GPM0PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0274, Reset Value = 0x0000 Name GPM0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-176 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.95 GPM1CON  Base Address: 0x1100_0000  Address = Base Address + 0x0280, Reset Value = 0x0000_0000 Name GPM1CON[6] GPM1CON[5] GPM1CON[4] GPM1CON[3] GPM1CON[2] GPM1CON[1] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = CAM_BAY_RGB[13] 0x3 = Reserved 0x4 = Reserved 0x5 = TraceData[12] 0x6 to 0xE = Reserved 0xF = EXT_INT9[6] 0x0 = Input 0x1 = Output 0x2 = CAM_BAY_RGB[12] 0x3 = Reserved 0x4 = Reserved 0x5 = TraceData[11] 0x6 to 0xE = Reserved 0xF = EXT_INT9[5] 0x0 = Input 0x1 = Output 0x2 = CAM_BAY_RGB[11] 0x3 = Reserved 0x4 = XhsiCAREADY 0x5 = TraceData[10] 0x6 to 0xE = Reserved 0xF = EXT_INT9[4] 0x0 = Input 0x1 = Output 0x2 = CAM_BAY_RGB[10] 0x3 = Reserved 0x4 = XhsiACFLAG 0x5 = TraceData[9] 0x6 to 0xE = Reserved 0xF = EXT_INT9[3] 0x0 = Input 0x1 = Output 0x2 = CAM_BAY_RGB[9] 0x3 = Reserved 0x4 = XhsiACDATA 0x5 = TraceData[8] 0x6 to 0xE = Reserved 0xF = EXT_INT9[2] 0x0 = Input 0x1 = Output 0x2 = CAM_BAY_RGB[8] 0x3 = CAM_B_FIELD Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-177 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name GPM1CON[0] Bit Type Description 0x4 = XhsiACWAKE 0x5 = TraceCtl 0x6 to 0xE = Reserved 0xF = EXT_INT9[1] 0x0 = Input 0x1 = Output 0x2 = Reserved [3:0] RW 0x3 = CAM_B_DATA[7] 0x4 = XhsiACREADY 0x5 = TraceData[7] 0x6 to 0xE = Reserved 0xF = EXT_INT9[0] Reset Value 0x00 4-178 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.96 GPM1DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0284, Reset Value = 0x00 Name Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as GPM1DAT[6:0] [6:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.97 GPM1PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0288, Reset Value = 0x1555 Name GPM1PUD[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x1555 4.3.3.98 GPM1DRV  Base Address: 0x1100_0000  Address = Base Address + 0x028C, Reset Value = 0x00_0000 Name GPM1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 6 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-179 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.99 GPM1CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0290, Reset Value = 0x0000 Name GPM1[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.100 GPM1PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x0294, Reset Value = 0x0000 Name GPM1[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-180 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.101 GPM2CON  Base Address: 0x1100_0000  Address = Base Address + 0x02A0, Reset Value = 0x0000_0000 Name GPM2CON[4] GPM2CON[3] GPM2CON[2] GPM2CON[1] GPM2CON[0] Bit [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = CAM_GPIO[1] 0x3 = MPWM2_OUT_ISP 0x4 to 0xE = Reserved 0xF = EXT_INT10[4] 0x0 = Input 0x1 = Output 0x2 = CAM_GPIO[0] 0x3 = MPWM1_OUT_ISP 0x4 to 0xE = Reserved 0xF = EXT_INT10[3] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = CAM_B_CLKOUT 0x4 = Reserved 0x5 = TraceData[15] 0x6 to 0xE = Reserved 0xF = EXT_INT10[2] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = CAM_B_HREF 0x4 = Reserved 0x5 = TraceData[14] 0x6 to 0xE = Reserved 0xF = EXT_INT10[1] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = CAM_B_VSYNC 0x4 = Reserved 0x5 = TraceData[13] 0x6 to 0xE = Reserved 0xF = EXT_INT10[0] Reset Value 0x00 0x00 0x00 0x00 0x00 4-181 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.102 GPM2DAT  Base Address: 0x1100_0000  Address = Base Address + 0x02A4, Reset Value = 0x00 Name Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as GPM2DAT[4:0] [4:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.103 GPM2PUD  Base Address: 0x1100_0000  Address = Base Address + 0x02A8, Reset Value = 0x0155 Name GPM2PUD[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0155 4.3.3.104 GPM2DRV  Base Address: 0x1100_0000  Address = Base Address + 0x02AC, Reset Value = 0x00_0000 Name GPM2DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 4 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-182 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.105 GPM2CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x02B0, Reset Value = 0x0000 Name GPM2[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.106 GPM2PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x02B4, Reset Value = 0x0000 Name GPM2[n] Bit [2n + 1:2n] n = 0 to 4 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-183 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.107 GPM3CON  Base Address: 0x1100_0000  Address = Base Address + 0x02C0, Reset Value = 0x0000_0000 Name GPM3CON[7] GPM3CON[6] GPM3CON[5] GPM3CON[4] GPM3CON[3] GPM3CON[2] GPM3CON[1] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] Type RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = CAM_GPIO[9] 0x3 = RXD_UART_ISP 0x4 to 0xE = Reserved 0xF = EXT_INT11[7] 0x0 = Input 0x1 = Output 0x2 = CAM_GPIO[8] 0x3 = nCTS_UART_ISP 0x4 to 0xE = Reserved 0xF = EXT_INT11[6] 0x0 = Input 0x1 = Output 0x2 = CAM_GPIO[7] 0x3 = TXD_UART_ISP 0x4 to 0xE = Reserved 0xF = EXT_INT11[5] 0x0 = Input 0x1 = Output 0x2 = CAM_GPIO[6] 0x3 = nRTS_UART_ISP 0x4 to 0xE = Reserved 0xF = EXT_INT11[4] 0x0 = Input 0x1 = Output 0x2 = CAM_GPIO[5] 0x3 = MPWM6_OUT_ISP 0x4 = CAM_SPI1_MOSI 0x5 to 0xE = Reserved 0xF = EXT_INT11[3] 0x0 = Input 0x1 = Output 0x2 = CAM_GPIO[4] 0x3 = MPWM5_OUT_ISP 0x4 = CAM_SPI1_MISO 0x5 to 0xE = Reserved 0xF = EXT_INT11[2] 0x0 = Input 0x1 = Output 0x2 = CAM_GPIO[3] 0x3 = MPWM4_OUT_ISP 0x4 to 0xE = Reserved 0xF = EXT_INT11[1] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-184 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name GPM3CON[0] Bit Type Description 0x0 = Input 0x1 = Output [3:0] RW 0x2 = CAM_GPIO[2] 0x3 = MPWM3_OUT_ISP 0x4 to 0xE = Reserved 0xF = EXT_INT11[0] Reset Value 0x00 4-185 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.108 GPM3DAT  Base Address: 0x1100_0000  Address = Base Address + 0x02C4, Reset Value = 0x00 Name Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as GPM3DAT[7:0] [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.109 GPM3PUD  Base Address: 0x1100_0000  Address = Base Address + 0x02C8, Reset Value = 0x5555 Name GPM3PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.110 GPM3DRV  Base Address: 0x1100_0000  Address = Base Address + 0x02CC, Reset Value = 0x00_0000 Name GPM3DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-186 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.111 GPM3CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x02D0, Reset Value = 0x0000 Name GPM3[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.112 GPM3PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x02D4, Reset Value = 0x0000 Name GPM3[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-187 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.113 GPM4CON  Base Address: 0x1100_0000  Address = Base Address + 0x02E0, Reset Value = 0x0000_0000 Name GPM4CON[7] GPM4CON[6] GPM4CON[5] GPM4CON[4] GPM4CON[3] GPM4CON[2] GPM4CON[1] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] Type RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = CAM_SPI_MOSI 0x3 = CAM_GPIO[17] 0x4 to 0xE = Reserved 0xF = EXT_INT12[7] 0x0 = Input 0x1 = Output 0x2 = CAM_SPI_MISO 0x3 = CAM_GPIO[16] 0x4 to 0xE = Reserved 0xF = EXT_INT12[6] 0x0 = Input 0x1 = Output 0x2 = CAM_SPI_nSS 0x3 = CAM_GPIO[15] 0x4 to 0xE = Reserved 0xF = EXT_INT12[5] 0x0 = Input 0x1 = Output 0x2 = CAM_SPI_CLK 0x3 = CAM_GPIO[14] 0x4 to 0xE = Reserved 0xF = EXT_INT12[4] 0x0 = Input 0x1 = Output 0x2 = CAM_I2C1_SDA 0x3 = CAM_GPIO[13] 0x4 = CAM_SPI1_nSS 0x5 to 0xE = Reserved 0xF = EXT_INT12[3] 0x0 = Input 0x1 = Output 0x2 = CAM_I2C1_SCL 0x3 = CAM_GPIO[12] 0x4 = CAM_SPI1_CLK 0x5 to 0xE = Reserved 0xF = EXT_INT12[2] 0x0 = Input 0x1 = Output 0x2 = CAM_I2C0_SDA 0x3 = CAM_GPIO[11] 0x4 to 0xE = Reserved 0xF = EXT_INT12[1] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-188 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name GPM4CON[0] Bit Type Description 0x0 = Input 0x1 = Output [3:0] RW 0x2 = CAM_I2C0_SCL 0x3 = CAM_GPIO[10] 0x4 to 0xE = Reserved 0xF = EXT_INT12[0] Reset Value 0x00 4-189 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.114 GPM4DAT  Base Address: 0x1100_0000  Address = Base Address + 0x02E4, Reset Value = 0x00 Name Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as GPM4DAT[7:0] [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.115 GPM4PUD  Base Address: 0x1100_0000  Address = Base Address + 0x02E8, Reset Value = 0x5555 Name GPM4PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.116 GPM4DRV  Base Address: 0x1100_0000  Address = Base Address + 0x02EC, Reset Value = 0x00_0000 Name GPM4DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-190 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.117 GPM4CONPDN  Base Address: 0x1100_0000  Address = Base Address + 0x02F0, Reset Value = 0x0000 Name GPM4[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.3.118 GPM4PUDPDN  Base Address: 0x1100_0000  Address = Base Address + 0x02F4, Reset Value = 0x0000 Name GPM4[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-191 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.119 EXT_INT23CON  Base Address: 0x1100_0000  Address = Base Address + 0x0708, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT23_CON[6] RSVD EXT_INT23_CON[5] RSVD EXT_INT23_CON[4] RSVD EXT_INT23_CON[3] RSVD EXT_INT23_CON[2] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT23[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT23[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT23[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT23[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT23[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-192 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description RSVD [7] – Reserved Sets signaling method of EXT_INT23[1] 0x0 = Low level 0x1 = High level EXT_INT23_CON[1] [6:4] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved RSVD [3] – Reserved Sets signaling method of EXT_INT23[0] 0x0 = Low level 0x1 = High level EXT_INT23_CON[0] [2:0] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 4-193 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.120 EXT_INT24CON  Base Address: 0x1100_0000  Address = Base Address + 0x070C, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT24_CON[6] RSVD EXT_INT24_CON[5] RSVD EXT_INT24_CON[4] RSVD EXT_INT24_CON[3] RSVD EXT_INT24_CON[2] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT24[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT24[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT24[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT24[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT24[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-194 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description RSVD [7] – Reserved Sets signaling method of EXT_INT24[1] 0x0 = Low level 0x1 = High level EXT_INT24_CON[1] [6:4] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved RSVD [3] – Reserved Sets signaling method of EXT_INT24[0] 0x0 = Low level 0x1 = High level EXT_INT24_CON[0] [2:0] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 4-195 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.121 EXT_INT25CON  Base Address: 0x1100_0000  Address = Base Address + 0x0710, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT25_CON[6] RSVD EXT_INT25_CON[5] RSVD EXT_INT25_CON[4] RSVD EXT_INT25_CON[3] RSVD EXT_INT25_CON[2] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT25[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT25[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT25[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT25[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT25[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-196 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description RSVD [7] – Reserved Sets signaling method of EXT_INT25[1] 0x0 = Low level 0x1 = High level EXT_INT25_CON[1] [6:4] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved RSVD [3] – Reserved Sets signaling method of EXT_INT25[0] 0x0 = Low level 0x1 = High level, EXT_INT25_CON[0] [2:0] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 4-197 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.122 EXT_INT26CON  Base Address: 0x1100_0000  Address = Base Address + 0x0714, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT26_CON[6] RSVD EXT_INT26_CON[5] RSVD EXT_INT26_CON[4] RSVD EXT_INT26_CON[3] RSVD EXT_INT26_CON[2] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Type – – RW – RW – RW – W – RW Description Reserved Reserved Sets signaling method of EXT_INT26[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT26[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT26[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT26[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT26[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-198 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description RSVD [7] – Reserved Sets signaling method of EXT_INT26[1] 0x0 = Low level 0x1 = High level EXT_INT26_CON[1] [6:4] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved RSVD [3] – Reserved Sets signaling method of EXT_INT26[0] 0x0 = Low level 0x1 = High level EXT_INT26_CON[0] [2:0] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 4-199 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.123 EXT_INT27CON  Base Address: 0x1100_0000  Address = Base Address + 0x0718, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT27_CON[6] RSVD EXT_INT27_CON[5] RSVD EXT_INT27_CON[4] RSVD EXT_INT27_CON[3] RSVD EXT_INT27_CON[2] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT27[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT27[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT27[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT27[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT27[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-200 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description RSVD [7] – Reserved Sets signaling method of EXT_INT27[1] 0x0 = Low level 0x1 = High level EXT_INT27_CON[1] [6:4] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved RSVD [3] – Reserved Sets signaling method of EXT_INT27[0] 0x0 = Low level 0x1 = High level EXT_INT27_CON[0] [2:0] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 4-201 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.124 EXT_INT28CON  Base Address: 0x1100_0000  Address = Base Address + 0x071C, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT28_CON[1] RSVD EXT_INT28_CON[0] Bit [31:8] [7] [6:4] [3] [2:0] Type – – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT28[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT28[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x000000 0x0 0x0 0x0 0x0 4-202 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.125 EXT_INT29CON  Base Address: 0x1100_0000  Address = Base Address + 0x0720, Reset Value = 0x0000_0000 Name RSVD EXT_INT29_CON[7] RSVD EXT_INT29_CON[6] RSVD EXT_INT29_CON[5] RSVD EXT_INT29_CON[4] RSVD EXT_INT29_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT29[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT29[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT29[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT29[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT29[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-203 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT29_CON[2] RSVD EXT_INT29_CON[1] RSVD EXT_INT29_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT29[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT29[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT29[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-204 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.126 EXT_INT8CON  Base Address: 0x1100_0000  Address = Base Address + 0x0724, Reset Value = 0x0000_0000 Name RSVD EXT_INT8_CON[7] RSVD EXT_INT8_CON[6] RSVD EXT_INT8_CON[5] RSVD EXT_INT8_CON[4] RSVD EXT_INT8_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT8[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT8[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT8[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT8[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT8[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-205 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT8_CON[2] RSVD EXT_INT8_CON[1] RSVD EXT_INT8_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT8[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT8[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT8[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-206 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.127 EXT_INT9CON  Base Address: 0x1100_0000  Address = Base Address + 0x0728, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT9_CON[6] RSVD EXT_INT9_CON[5] RSVD EXT_INT9_CON[4] RSVD EXT_INT9_CON[3] RSVD EXT_INT9_CON[2] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Type – – RW – RW – RW – RW – W Description Reserved Reserved Sets signaling method of EXT_INT9[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT9[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT9[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT9[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT9[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-207 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name RSVD EXT_INT9_CON[1] RSVD EXT_INT9_CON[0] Bit Type Description [7] – Reserved Sets signaling method of EXT_INT9[1] 0x0 = Low level 0x1 = High level [6:4] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved [3] – Reserved Sets signaling method of EXT_INT9[0] 0x0 = Low level 0x1 = High level [2:0] RW 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 4-208 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.128 EXT_INT10CON  Base Address: 0x1100_0000  Address = Base Address + 0x072C, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT10_CON[4] RSVD EXT_INT10_CON[3] RSVD EXT_INT10_CON[2] RSVD EXT_INT10_CON[1] RSVD EXT_INT10_CON[0] Bit [31:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT10[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT10[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT10[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT10[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT10[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers falling edge 0x3 = Triggers rising edge 0x4 = Triggers both edge 0x5 to 0x7 = Reserved Reset Value 0x000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-209 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.129 EXT_INT11CON  Base Address: 0x1100_0000  Address = Base Address + 0x0730, Reset Value = 0x0000_0000 Name RSVD EXT_INT11_CON[7] RSVD EXT_INT11_CON[6] RSVD EXT_INT11_CON[5] RSVD EXT_INT11_CON[4] RSVD EXT_INT11_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT11[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT11[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT11[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT11[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT11[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Rising edge triggered 0x4 = Both edge triggered 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-210 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT11_CON[2] RSVD EXT_INT11_CON[1] RSVD EXT_INT11_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT11[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT11[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT11[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-211 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.130 EXT_INT12CON  Base Address: 0x1100_0000  Address = Base Address + 0x0734, Reset Value = 0x0000_0000 Name RSVD EXT_INT12_CON[7] RSVD EXT_INT12_CON[6] RSVD EXT_INT12_CON[5] RSVD EXT_INT12_CON[4] RSVD EXT_INT12_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT12[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT12[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT12[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT12[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT12[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-212 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT12_CON[2] RSVD EXT_INT12_CON[1] RSVD EXT_INT12_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT12[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT12[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT12[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-213 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.131 EXT_INT23_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0810, Reset Value = 0x0000_0000 Name FLTEN3[3] FLTWIDTH3[3] FLTEN3[2] FLTWIDTH3[2] FLTEN3[1] FLTWIDTH3[1] FLTEN3[0] FLTWIDTH3[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT23[3] 0x0 = Disables Filter 0x1 = Enabled Filter Filtering width of EXT_INT23[3] Filter Enable for EXT_INT23[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT23[2] Filter Enable for EXT_INT23[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT23[1] Filter Enable for EXT_INT23[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT23[0] 4.3.3.132 EXT_INT23_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0814, Reset Value = 0x0000_0000 Name RSVD FLTEN3[6] FLTWIDTH3[6] FLTEN3[5] FLTWIDTH3[5] FLTEN3[4] FLTWIDTH3[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW RW RW Description Reserved Filter Enable for EXT_INT23[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT23[6] Filter Enable for EXT_INT23[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT23[5] Filter Enable for EXT_INT23[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT23[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-214 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.133 EXT_INT24_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0818, Reset Value = 0x0000_0000 Name FLTEN4[3] FLTWIDTH4[3] FLTEN4[2] FLTWIDTH4[2] FLTEN4[1] FLTWIDTH4[1] FLTEN4[0] FLTWIDTH4[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT24[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT24[3] Filter Enable for EXT_INT24[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT24[2] Filter Enable for EXT_INT24[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT24[1] Filter Enable for EXT_INT24[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT24[0] 4.3.3.134 EXT_INT24_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x081C, Reset Value = 0x0000_0000 Name RSVD FLTEN4[6] FLTWIDTH4[6] FLTEN4[5] FLTWIDTH4[5] FLTEN4[4] FLTWIDTH4[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW RW RW Description Reserved Filter Enable for EXT_INT24[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT24[6] Filter Enable for EXT_INT24[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT24[5] Filter Enable for EXT_INT24[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT24[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-215 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.135 EXT_INT25_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0820, Reset Value = 0x0000_0000 Name FLTEN5[3] FLTWIDTH5[3] FLTEN5[2] FLTWIDTH5[2] FLTEN5[1] FLTWIDTH5[1] FLTEN5[0] FLTWIDTH5[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT25[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT25[3] Filter Enable for EXT_INT25[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT25[2] Filter Enable for EXT_INT25[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT25[1] Filter Enable for EXT_INT25[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT25[0] 4.3.3.136 EXT_INT25_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0824, Reset Value = 0x0000_0000 Name RSVD FLTEN5[6] FLTWIDTH5[6] FLTEN5[5] FLTWIDTH5[5] FLTEN5[4] FLTWIDTH5[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW RW RW Description Reserved Filter Enable for EXT_INT25[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT25[6] Filter Enable for EXT_INT25[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT25[5] Filter Enable for EXT_INT25[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT25[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-216 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.137 EXT_INT26_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0828, Reset Value = 0x0000_0000 Name FLTEN6[3] FLTWIDTH6[3] FLTEN6[2] FLTWIDTH6[2] FLTEN6[1] FLTWIDTH6[1] FLTEN6[0] FLTWIDTH6[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT26[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT26[3] Filter Enable for EXT_INT26[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT26[2] Filter Enable for EXT_INT26[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT26[1] Filter Enable for EXT_INT26[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT26[0] 4.3.3.138 EXT_INT26_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x082C, Reset Value = 0x0000_0000 Name RSVD FLTEN6[6] FLTWIDTH6[6] FLTEN6[5] FLTWIDTH6[5] FLTEN6[4] FLTWIDTH6[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW RW RW Description Reserved Filter Enable for EXT_INT26[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT26[6] Filter Enable for EXT_INT26[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT26[5] Filter Enable for EXT_INT26[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT26[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-217 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.139 EXT_INT27_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0830, Reset Value = 0x0000_0000 Name FLTEN7[3] FLTWIDTH7[3] FLTEN7[2] FLTWIDTH7[2] FLTEN7[1] FLTWIDTH7[1] FLTEN7[0] FLTWIDTH7[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT27[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT27[3] Filter Enable for EXT_INT27[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT27[2] Filter Enable for EXT_INT27[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT27[1] Filter Enable for EXT_INT27[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT27[0] 4.3.3.140 EXT_INT27_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0834, Reset Value = 0x0000_0000 Name RSVD FLTEN7[6] FLTWIDTH7[6] FLTEN7[5] FLTWIDTH7[5] FLTEN7[4] FLTWIDTH7[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW RW RW Description Reserved Filter Enable for EXT_INT27[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT27[6] Filter Enable for EXT_INT27[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT27[5] Filter Enable for EXT_INT27[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT27[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-218 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.141 EXT_INT28_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0838, Reset Value = 0x0000_0000 Name RSVD FLTEN8[1] FLTWIDTH8[1] FLTEN8[0] FLTWIDTH8[0] Bit [31:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW Description Reserved Filter Enable for EXT_INT28[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT28[1] Filter Enable for EXT_INT28[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT28[0] 4.3.3.142 EXT_INT28_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x083C, Reset Value = 0x0000_0000 Name RSVD Bit [31:0] Type – Reserved Description Reset Value 0 0x0 0x00 0x0 0x00 Reset Value 0x00000000 4-219 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.143 EXT_INT29_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0840, Reset Value = 0x0000_0000 Name FLTEN9[3] FLTWIDTH9[3] FLTEN9[2] FLTWIDTH9[2] FLTEN9[1] FLTWIDTH9[1] FLTEN9[0] FLTWIDTH9[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT29[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT29[3] Filter Enable for EXT_INT29[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT29[2] Filter Enable for EXT_INT29[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT29[1] Filter Enable for EXT_INT29[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT29[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-220 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.144 EXT_INT29_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0844, Reset Value = 0x0000_0000 Name FLTEN9[7] FLTWIDTH9[7] FLTEN9[6] FLTWIDTH9[6] FLTEN9[5] FLTWIDTH9[5] FLTEN9[4] FLTWIDTH9[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT29[7] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT29[7] Filter Enable for EXT_INT29[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT29[6] Filter Enable for EXT_INT29[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT29[5] Filter Enable for EXT_INT29[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT29[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-221 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.145 EXT_INT8_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0848, Reset Value = 0x0000_0000 Name FLTEN10[3] FLTWIDTH10[3] FLTEN10[2] FLTWIDTH10[2] FLTEN10[1] FLTWIDTH10[1] FLTEN10[0] FLTWIDTH10[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT8[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT8[3] Filter Enable for EXT_INT8[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT8[2] Filter Enable for EXT_INT8[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT8[1] Filter Enable for EXT_INT8[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT8[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-222 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.146 EXT_INT8_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x084C, Reset Value = 0x0000_0000 Name FLTEN10[7] FLTWIDTH10[7] FLTEN10[6] FLTWIDTH10[6] FLTEN10[5] FLTWIDTH10[5] FLTEN10[4] FLTWIDTH10[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT8[7] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT8[7] Filter Enable for EXT_INT8[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT8[6] Filter Enable for EXT_INT8[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT8[5] Filter Enable for EXT_INT8[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT8[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-223 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.147 EXT_INT9_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0850, Reset Value = 0x0000_0000 Name FLTEN11[3] FLTWIDTH11[3] FLTEN11[2] FLTWIDTH11[2] FLTEN11[1] FLTWIDTH11[1] FLTEN11[0] FLTWIDTH11[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT9[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT9[3] Filter Enable for EXT_INT9[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT9[2] Filter Enable for EXT_INT9[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT9[1] Filter Enable for EXT_INT9[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT9[0] 4.3.3.148 EXT_INT9_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0854, Reset Value = 0x0000_0000 Name RSVD FLTEN11[6] FLTWIDTH11[6] FLTEN11[5] FLTWIDTH11[5] FLTEN11[4] FLTWIDTH11[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW RW RW Description Reserved Filter Enable for EXT_INT9[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT9[6] Filter Enable for EXT_INT9[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT9[5] Filter Enable for EXT_INT9[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT9[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-224 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.149 EXT_INT10_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0858, Reset Value = 0x0000_0000 Name FLTEN12[3] FLTWIDTH12[3] FLTEN12[2] FLTWIDTH12[2] FLTEN12[1] FLTWIDTH12[1] FLTEN12[0] FLTWIDTH12[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT10[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT10[3] Filter Enable for EXT_INT10[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT10[2] Filter Enable for EXT_INT10[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT10[1] Filter Enable for EXT_INT10[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT10[0] 4.3.3.150 EXT_INT10_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x085C, Reset Value = 0x0000_0000 Name RSVD FLTEN12[4] FLTWIDTH12[4] Bit [31:8] [7] [6:0] Type – RW RW Description Reserved Filter Enable for EXT_INT10[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT10[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x000000 0x0 0x00 4-225 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.151 EXT_INT11_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0860, Reset Value = 0x0000_0000 Name FLTEN13[3] FLTWIDTH13[3] FLTEN13[2] FLTWIDTH13[2] FLTEN13[1] FLTWIDTH13[1] FLTEN13[0] FLTWIDTH13[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT11[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT11[3] Filter Enable for EXT_INT11[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT11[2] Filter Enable for EXT_INT11[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT11[1] Filter Enable for EXT_INT11[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT11[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-226 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.152 EXT_INT11_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0864, Reset Value = 0x0000_0000 Name FLTEN13[7] FLTWIDTH13[7] FLTEN13[6] FLTWIDTH13[6] FLTEN13[5] FLTWIDTH13[5] FLTEN13[4] FLTWIDTH13[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable For EXT_INT11[7] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT11[7] Filter Enable for EXT_INT11[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT11[6] Filter Enable for EXT_INT11[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT11[5] Filter Enable for EXT_INT11[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT11[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-227 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.153 EXT_INT12_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0868, Reset Value = 0x0000_0000 Name FLTEN14[3] FLTWIDTH14[3] FLTEN14[2] FLTWIDTH14[2] FLTEN14[1] FLTWIDTH14[1] FLTEN14[0] FLTWIDTH14[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT12[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT12[3] Filter Enable for EXT_INT12[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT12[2] Filter Enable for EXT_INT12[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT12[1] Filter Enable for EXT_INT12[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT12[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-228 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.154 EXT_INT12_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x086C, Reset Value = 0x0000_0000 Name FLTEN14[7] FLTWIDTH14[7] FLTEN14[6] FLTWIDTH14[6] FLTEN14[5] FLTWIDTH14[5] FLTEN14[4] FLTWIDTH14[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT12[7] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT12[7] Filter Enable for EXT_INT12[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT12[6] Filter Enable for EXT_INT12[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT12[5] Filter Enable for EXT_INT12[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT12[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-229 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.155 EXT_INT23_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0908, Reset Value = 0x0000_007F Name RSVD EXT_INT23_MASK[6] EXT_INT23_MASK[5] EXT_INT23_MASK[4] EXT_INT23_MASK[3] EXT_INT23_MASK[2] EXT_INT23_MASK[1] EXT_INT23_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 4.3.3.156 EXT_INT24_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x090C, Reset Value = 0x0000_007F Name RSVD EXT_INT24_MASK[6] EXT_INT24_MASK[5] EXT_INT24_MASK[4] EXT_INT24_MASK[3] EXT_INT24_MASK[2] EXT_INT24_MASK[1] EXT_INT24_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-230 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.157 EXT_INT25_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0910, Reset Value = 0x0000_007F Name RSVD EXT_INT25_MASK[6] EXT_INT25_MASK[5] EXT_INT25_MASK[4] EXT_INT25_MASK[3] EXT_INT25_MASK[2] EXT_INT25_MASK[1] EXT_INT25_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 4.3.3.158 EXT_INT26_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0914, Reset Value = 0x0000_007F Name RSVD EXT_INT26_MASK[6] EXT_INT26_MASK[5] EXT_INT26_MASK[4] EXT_INT26_MASK[3] EXT_INT26_MASK[2] EXT_INT26_MASK[1] EXT_INT26_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-231 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.159 EXT_INT27_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0918, Reset Value = 0x0000_007F Name RSVD EXT_INT27_MASK[6] EXT_INT27_MASK[5] EXT_INT27_MASK[4] EXT_INT27_MASK[3] EXT_INT27_MASK[2] EXT_INT27_MASK[1] EXT_INT27_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 4.3.3.160 EXT_INT28_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x091C, Reset Value = 0x0000_0003 Name RSVD EXT_INT28_MASK[1] EXT_INT28_MASK[0] Bit [31:2] [1] [0] Type – RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Reset Value 0x00000000 0x1 0x1 4-232 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.161 EXT_INT29_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0920, Reset Value = 0x0000_00FF Name RSVD EXT_INT29_MASK[7] EXT_INT29_MASK[6] EXT_INT29_MASK[5] EXT_INT29_MASK[4] EXT_INT29_MASK[3] EXT_INT29_MASK[2] EXT_INT29_MASK[1] EXT_INT29_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-233 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.162 EXT_INT8_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0924, Reset Value = 0x0000_00FF Name RSVD EXT_INT8_MASK[7] EXT_INT8_MASK[6] EXT_INT8_MASK[5] EXT_INT8_MASK[4] EXT_INT8_MASK[3] EXT_INT8_MASK[2] EXT_INT8_MASK[1] EXT_INT8_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-234 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.163 EXT_INT9_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0928, Reset Value = 0x0000_007F Name RSVD EXT_INT9_MASK[6] EXT_INT9_MASK[5] EXT_INT9_MASK[4] EXT_INT9_MASK[3] EXT_INT9_MASK[2] EXT_INT9_MASK[1] EXT_INT9_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 4.3.3.164 EXT_INT10_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x092C, Reset Value = 0x0000_001F Name RSVD EXT_INT10_MASK[4] EXT_INT10_MASK[3] EXT_INT10_MASK[2] EXT_INT10_MASK[1] EXT_INT10_MASK[0] Bit [31:5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 4-235 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.165 EXT_INT11_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0930, Reset Value = 0x0000_00FF Name RSVD EXT_INT11_MASK[7] EXT_INT11_MASK[6] EXT_INT11_MASK[5] EXT_INT11_MASK[4] EXT_INT11_MASK[3] EXT_INT11_MASK[2] EXT_INT11_MASK[1] EXT_INT11_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-236 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.166 EXT_INT12_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0934, Reset Value = 0x0000_00FF Name RSVD EXT_INT12_MASK[7] EXT_INT12_MASK[6] EXT_INT12_MASK[5] EXT_INT12_MASK[4] EXT_INT12_MASK[3] EXT_INT12_MASK[2] EXT_INT12_MASK[1] EXT_INT12_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-237 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.167 EXT_INT23_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A08, Reset Value = 0x0000_0000 Name RSVD EXT_INT23_PEND[6] EXT_INT23_PEND[5] EXT_INT23_PEND[4] EXT_INT23_PEND[3] EXT_INT23_PEND[2] EXT_INT23_PEND[1] EXT_INT23_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 4.3.3.168 EXT_INT24_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A0C, Reset Value = 0x0000_0000 Name RSVD EXT_INT24_PEND[6] EXT_INT24_PEND[5] EXT_INT24_PEND[4] EXT_INT24_PEND[3] EXT_INT24_PEND[2] EXT_INT24_PEND[1] EXT_INT24_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-238 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.169 EXT_INT25_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A10, Reset Value = 0x0000_0000 Name RSVD EXT_INT25_PEND[6] EXT_INT25_PEND[5] EXT_INT25_PEND[4] EXT_INT25_PEND[3] EXT_INT25_PEND[2] EXT_INT25_PEND[1] EXT_INT25_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 4.3.3.170 EXT_INT26_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A14, Reset Value = 0x0000_0000 Name RSVD EXT_INT26_PEND[6] EXT_INT26_PEND[5] EXT_INT26_PEND[4] EXT_INT26_PEND[3] EXT_INT26_PEND[2] EXT_INT26_PEND[1] EXT_INT26_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-239 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.171 EXT_INT27_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A18, Reset Value = 0x0000_0000 Name RSVD EXT_INT27_PEND[6] EXT_INT27_PEND[5] EXT_INT27_PEND[4] EXT_INT27_PEND[3] EXT_INT27_PEND[2] EXT_INT27_PEND[1] EXT_INT27_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 4.3.3.172 EXT_INT28_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A1C, Reset Value = 0x0000_0000 Name RSVD EXT_INT28_PEND[1] EXT_INT28_PEND[0] Bit [31:2] [1] [0] Type – RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x00000000 0x0 0x0 4-240 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.173 EXT_INT29_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A20, Reset Value = 0x0000_0000 Name RSVD EXT_INT29_PEND[7] EXT_INT29_PEND[6] EXT_INT29_PEND[5] EXT_INT29_PEND[4] EXT_INT29_PEND[3] EXT_INT29_PEND[2] EXT_INT29_PEND[1] EXT_INT29_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-241 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.174 EXT_INT8_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A24, Reset Value = 0x0000_0000 Name RSVD EXT_INT8_PEND[7] EXT_INT8_PEND[6] EXT_INT8_PEND[5] EXT_INT8_PEND[4] EXT_INT8_PEND[3] EXT_INT8_PEND[2] EXT_INT8_PEND[1] EXT_INT8_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-242 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.175 EXT_INT9_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A28, Reset Value = 0x0000_0000 Name RSVD EXT_INT9_PEND[6] EXT_INT9_PEND[5] EXT_INT9_PEND[4] EXT_INT9_PEND[3] EXT_INT9_PEND[2] EXT_INT9_PEND[1] EXT_INT9_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 4.3.3.176 EXT_INT10_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A2C, Reset Value = 0x0000_0000 Name RSVD EXT_INT10_PEND[4] EXT_INT10_PEND[3] EXT_INT10_PEND[2] EXT_INT10_PEND[1] EXT_INT10_PEND[0] Bit [31:5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 4-243 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.177 EXT_INT11_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A30, Reset Value = 0x0000_0000 Name RSVD EXT_INT11_PEND[7] EXT_INT11_PEND[6] EXT_INT11_PEND[5] EXT_INT11_PEND[4] EXT_INT11_PEND[3] EXT_INT11_PEND[2] EXT_INT11_PEND[1] EXT_INT11_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-244 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.178 EXT_INT12_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0A34, Reset Value = 0x0000_0000 Name RSVD EXT_INT12_PEND[7] EXT_INT12_PEND[6] EXT_INT12_PEND[5] EXT_INT12_PEND[4] EXT_INT12_PEND[3] EXT_INT12_PEND[2] EXT_INT12_PEND[1] EXT_INT12_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-245 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.179 EXT_INT_SERVICE_XA  Base Address: 0x1100_0000  Address = Base Address + 0x0B08, Reset Value = 0x0000_0000 Name RSVD SVC_Group_Num SVC_Num Bit [31:8] [7:3] [2:0] Type RW RW RW Description Reserved EXT_INT Service group number 0x1 = EXT_INT23 0x2 = EXT_INT24 0x3 = EXT_INT25 0x4 = EXT_INT26 0x5 = EXT_INT27 0x6 = EXT_INT28 0x7 = EXT_INT29 0x8 = EXT_INT8 0x9 = EXT_INT9 0xA = EXT_INT10 0xB = EXT_INT11 0xC = EXT_INT12 Interrupt number to be serviced 4.3.3.180 EXT_INT_SERVICE_PEND_XA  Base Address: 0x1100_0000  Address = Base Address + 0x0B0C, Reset Value = 0x0000_0000 Name RSVD SVC_PEND Bit [31:8] [7:0] Type RW RW Description Reserved 0x0 = Not occur 0x1 = Interrupt occurs Reset Value 0x0000000 0x00 0x0 Reset Value 0x0000000 0x00 4-246 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.181 EXT_INT_GRPFIXPRI_XA  Base Address: 0x1100_0000  Address = Base Address + 0x0B10, Reset Value = 0x0000_0000 Name RSVD Highest_GRP_NUM Bit [31:4] [3:0] Type – RW Description Reserved When fixed group priority mode = 0 to 11, then group number should be of the highest priority. 0x0 = EXT_INT23 0x1 = EXT_INT24 0x2 = EXT_INT25 0x3 = EXT_INT26 0x4 = EXT_INT27 0x5 = EXT_INT28 0x6 = EXT_INT29 0x7 = EXT_INT8 0x8 = EXT_INT9 0x9 = EXT_INT10 0xA = EXT_INT11 0xB = EXT_INT12 Reset Value 0x0000000 0x00 4-247 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.182 EXT_INT23_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B1C, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 0 (EXT_INT23) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.3.183 EXT_INT24_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B20, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 1 (EXT_INT24) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.3.184 EXT_INT25_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B24, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 2 (EXT_INT25) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-248 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.185 EXT_INT26_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B28, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 3 (EXT_INT26) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.3.186 EXT_INT27_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B2C, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 4 (EXT_INT27) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.3.187 EXT_INT28_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B30, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 5 (EXT_INT28) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.3.188 EXT_INT29_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B34, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 6 (EXT_INT29) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-249 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.189 EXT_INT8_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B38, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 7 (EXT_INT8) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.3.190 EXT_INT9_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B3C, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 8 (EXT_INT9) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.3.191 EXT_INT10_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B40, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 9 (EXT_INT10) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-250 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.192 EXT_INT11_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B44, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 10 (EXT_INT11) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.3.193 EXT_INT12_FIXPRI  Base Address: 0x1100_0000  Address = Base Address + 0x0B48, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 11 (EXT_INT12) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-251 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.194 GPX0CON  Base Address: 0x1100_0000  Address = Base Address + 0x0C00, Reset Value = 0x0000_0000 Name GPX0CON[7] GPX0CON[6] GPX0CON[5] GPX0CON[4] GPX0CON[3] GPX0CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = Reserved 0x4 = Reserved 0x5 = ALV_DBG[3] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT0[7] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = Reserved 0x4 = Reserved 0x5 = ALV_DBG[2] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT0[6] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = Reserved 0x4 = Reserved 0x5 = ALV_DBG[1] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT0[5] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = AUD_TRSTn 0x4 = GNSS_TRSTn 0x5 = ALV_DBG[0] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT0[4] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = AUD_TDO 0x4 = GNSS_TDO 0x5 = ALV_TDO 0x6 to 0xE = Reserved 0xF = WAKEUP_INT0[3] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = AUD_TDI Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-252 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name GPX0CON[1] GPX0CON[0] Bit Type Description 0x4 = GNSS_TDI 0x5 = ALV_TDI 0x6 to 0xE = Reserved 0xF = WAKEUP_INT0[2] 0x0 = Input 0x1 = Output 0x2 = Reserved [7:4] RW 0x3 = AUD_TMS 0x4 = GNSS_TMS 0x5 = ALV_TMS 0x6 to 0xE = Reserved 0xF = WAKEUP_INT0[1] 0x0 = Input 0x1 = Output 0x2 = Reserved [3:0] RW 0x3 = AUD_TCK 0x4 = GNSS_TCK 0x5 = ALV_TCK 0x6 to 0xE = Reserved 0xF = WAKEUP_INT0[0] Reset Value 0x00 0x00 4-253 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.195 GPX0DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0C04, Reset Value = 0x00 Name GPX0DAT[7:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.196 GPX0PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0C08, Reset Value = 0x5555 Name GPX0PUD[n] Bit [2n + 1:2n] N = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.197 GPX0DRV  Base Address: 0x1100_0000  Address = Base Address + 0x0C0C, Reset Value = 0x00_0000 Name GPX0DRV[n] Bit [23:16] [2n + 1:2n] N = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-254 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.198 GPX1CON  Base Address: 0x1100_0000  Address = Base Address + 0x0C20, Reset Value = 0x0000_0000 Name GPX1CON[7] GPX1CON[6] GPX1CON[5] GPX1CON[4] GPX1CON[3] GPX1CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_COL[7] 0x4 = Reserved 0x5 = ALV_DBG[11] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT1[7] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_COL[6] 0x4 = Reserved 0x5 = ALV_DBG[10] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT1[6] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_COL[5] 0x4 = Reserved 0x5 = ALV_DBG[9] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT1[5] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_COL[4] 0x4 = Reserved 0x5 = ALV_DBG[8] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT1[4] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_COL[3] 0x4 = Reserved 0x5 = ALV_DBG[7] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT1[3] 0x0 = Input, 0x1 = Output, 0x2 = Reserved 0x3 = KP_COL[2] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-255 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name GPX1CON[1] GPX1CON[0] Bit Type Description 0x4 = Reserved 0x5 = ALV_DBG[6] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT1[2] 0x0 = Input 0x1 = Output 0x2 = Reserved [7:4] RW 0x3 = KP_COL[1] 0x4 = Reserved 0x5 = ALV_DBG[5] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT1[1] 0x0 = Input 0x1 = Output 0x2 = Reserved [3:0] RW 0x3 = KP_COL[0] 0x4 = Reserved 0x5 = ALV_DBG[4] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT1[0] Reset Value 0x00 0x00 4-256 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.199 GPX1DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0C24, Reset Value = 0x00 Name GPX1DAT[7:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.200 GPX1PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0C28, Reset Value = 0x5555 Name GPX1PUD[n] Bit [2n + 1:2n] N = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.201 GPX1DRV  Base Address: 0x1100_0000  Address = Base Address + 0x0C2C, Reset Value = 0x00_0000 Name GPX1DRV[n] Bit [23:16] [2n + 1:2n] N = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-257 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.202 GPX2CON  Base Address: 0x1100_0000  Address = Base Address + 0x0C40, Reset Value = 0x0000_0000 Name GPX2CON[7] GPX2CON[6] GPX2CON[5] GPX2CON[4] GPX2CON[3] GPX2CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[7] 0x4 = Reserved 0x5 = ALV_DBG[19] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT2[7] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[6] 0x4 = Reserved 0x5 = ALV_DBG[18] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT2[6] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[5] 0x4 = Reserved 0x5 = ALV_DBG[17] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT2[5] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[4] 0x4 = Reserved 0x5 = ALV_DBG[16] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT2[4] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[3] 0x4 = Reserved 0x5 = ALV_DBG[15] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT2[3] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[2] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-258 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name GPX2CON[1] GPX2CON[0] Bit Type Description 0x4 = Reserved 0x5 = ALV_DBG[14] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT2[2] 0x0 = Input 0x1 = Output 0x2 = Reserved [7:4] RW 0x3 = KP_ROW[1] 0x4 = Reserved 0x5 = ALV_DBG[13] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT2[1] 0x0 = Input 0x1 = Output 0x2 = Reserved [3:0] RW 0x3 = KP_ROW[0] 0x4 = Reserved 0x5 = ALV_DBG[12] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT2[0] Reset Value 0x00 0x00 4-259 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.203 GPX2DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0C44, Reset Value = 0x00 Name GPX2DAT[7:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.204 GPX2PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0C48, Reset Value = 0x5555 Name GPX2PUD[n] Bit [2n + 1:2n] N = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.205 GPX2DRV  Base Address: 0x1100_0000  Address = Base Address + 0x0C4C, Reset Value = 0x00_0000 Name GPX2DRV[n] Bit [23:16] [2n + 1:2n] N = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-260 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.206 GPX3CON  Base Address: 0x1100_0000  Address = Base Address + 0x0C60, Reset Value = 0x0000_0000 Name GPX3CON[7] GPX3CON[6] GPX3CON[5] GPX3CON[4] GPX3CON[3] GPX3CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Type RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = HDMI_HPD 0x4 = Reserved 0x5 = ALV_DBG[27] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT3[7] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = HDMI_CEC 0x4 = Reserved 0x5 = ALV_DBG[26] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT3[6] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[13] 0x4 = Reserved 0x5 = ALV_DBG[25] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT3[5] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[12] 0x4 = Reserved 0x5 = ALV_DBG[24] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT3[4] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[11] 0x4 = Reserved 0x5 = ALV_DBG[23] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT3[3] 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = KP_ROW[10] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 4-261 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name GPX3CON[1] GPX3CON[0] Bit Type Description 0x4 = Reserved 0x5 = ALV_DBG[22] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT3[2] 0x0 = Input 0x1 = Output 0x2 = Reserved [7:4] RW 0x3 = KP_ROW[9] 0x4 = Reserved 0x5 = ALV_DBG[21] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT3[1] 0x0 = Input 0x1 = Output 0x2 = Reserved [3:0] RW 0x3 = KP_ROW[8] 0x4 = Reserved 0x5 = ALV_DBG[20] 0x6 to 0xE = Reserved 0xF = WAKEUP_INT3[0] Reset Value 0x00 0x00 4-262 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.207 GPX3DAT  Base Address: 0x1100_0000  Address = Base Address + 0x0C64, Reset Value = 0x00 Name GPX3DAT[7:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.3.208 GPX3PUD  Base Address: 0x1100_0000  Address = Base Address + 0x0C68, Reset Value = 0x5555 Name GPX3PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.3.209 GPX3DRV  Base Address: 0x1100_0000  Address = Base Address + 0x0C6C, Reset Value = 0x00_0000 Name GPX3DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-263 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.210 EXT_INT40CON  Base Address: 0x1100_0000  Address = Base Address + 0x0E00, Reset Value = 0x0000_0000 Name RSVD EXT_INT40_CON[7] RSVD EXT_INT40_CON[6] RSVD EXT_INT40_CON[5] RSVD EXT_INT40_CON[4] RSVD EXT_INT40_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT40[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT40[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT40[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT40[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT40[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-264 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT40_CON[2] RSVD EXT_INT40_CON[1] RSVD EXT_INT40_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT40[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT40[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT40[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-265 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.211 EXT_INT41CON  Base Address: 0x1100_0000  Address = Base Address + 0x0E04, Reset Value = 0x0000_0000 Name RSVD EXT_INT41_CON[7] RSVD EXT_INT41_CON[6] RSVD EXT_INT41_CON[5] RSVD EXT_INT41_CON[4] RSVD EXT_INT41_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT41[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT41[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT41[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT41[4] 0x0 = Low level 0x1 = High level 0x2 = Falling edge triggered 0x3 = Rising edge triggered 0x4 = Both edge triggered 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT41[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-266 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT41_CON[2] RSVD EXT_INT41_CON[1] RSVD EXT_INT41_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – W – RW Description Sets signaling method of EXT_INT41[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT41[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT41[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-267 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.212 EXT_INT42CON  Base Address: 0x1100_0000  Address = Base Address + 0x0E08, Reset Value = 0x0000_0000 Name RSVD EXT_INT42_CON[7] RSVD EXT_INT42_CON[6] RSVD EXT_INT42_CON[5] RSVD EXT_INT42_CON[4] RSVD EXT_INT42_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT42[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT42[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT42[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT42[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT42[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-268 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT42_CON[2] RSVD EXT_INT42_CON[1] RSVD EXT_INT42_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT42[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT42[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT42[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-269 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.213 EXT_INT43CON  Base Address: 0x1100_0000  Address = Base Address + 0x0E0C, Reset Value = 0x0000_0000 Name RSVD EXT_INT43_CON[7] RSVD EXT_INT43_CON[6] RSVD EXT_INT43_CON[5] RSVD EXT_INT43_CON[4] RSVD EXT_INT43_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT43[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT43[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT43[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT43[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT43[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-270 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT43_CON[2] RSVD EXT_INT43_CON[1] RSVD EXT_INT43_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT43[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT43[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT43[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-271 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.214 EXT_INT40_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0E80, Reset Value = 0x8080_8080 Name FLTEN15[3] FLTSEL15[3] FLTWIDTH15[3] FLTEN15[2] FLTSEL15[2] FLTWIDTH15[2] FLTEN15[1] FLTSEL15[1] FLTWIDTH15[1] FLTEN15[0] FLTSEL15[0] FLTWIDTH15[0] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Type RW RW RW RW RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT40[3] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT40[3] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT40[3] This value is valid when FLTSEL15 (of EXT_INT40) is 0x1. Filter Enable for EXT_INT40[2] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT40[2] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT40[2] This value is valid when FLTSEL15 (of EXT_INT40) is 0x1. Filter Enable for EXT_INT40[1] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT40[1] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT40[1] This value is valid when FLTSEL15 (of EXT_INT40) is 0x1. Filter Enable for EXT_INT40[0] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT40[0] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT40[0] This value is valid when FLTSEL15 (of EXT_INT40) is 0x1. Reset Value 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 4-272 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.215 EXT_INT40_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0E84, Reset Value = 0x8080_8080 Name FLTEN15[7] FLTSEL15[7] FLTWIDTH15[7] FLTEN15[6] FLTSEL15[6] FLTWIDTH15[6] FLTEN15[5] FLTSEL15[5] FLTWIDTH15[5] FLTEN15[4] FLTSEL15[4] FLTWIDTH15[4] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Type RW RW RW RW RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT40[7] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT40[7] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT40[7] This value is valid when FLTSEL15 (of EXT_INT40) is 0x1. Filter Enable for EXT_INT40[6] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT40[6] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT40[6] This value is valid when FLTSEL15 (of EXT_INT40) is 0x1. Filter Enable for EXT_INT40[5] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT40[5] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT40[5] This value is valid when FLTSEL15 (of EXT_INT40) is 0x1. Filter Enable for EXT_INT40[4] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT40[4] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT40[4] This value is valid when FLTSEL15 (of EXT_INT40) is 0x1. Reset Value 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 4-273 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.216 EXT_INT41_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0E88, Reset Value = 0x8080_8080 Name FLTEN16[3] FLTSEL16[3] FLTWIDTH16[3] FLTEN16[2] FLTSEL16[2] FLTWIDTH16[2] FLTEN16[1] FLTSEL16[1] FLTWIDTH16[1] FLTEN16[0] FLTSEL16[0] FLTWIDTH16[0] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Type RW RW RW RW RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT41[3] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT41[3] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT41[3] This value is valid when FLTSEL16 (of EXT_INT41) is 0x1. Filter Enable for EXT_INT41[2] 0x0 = Disables Filter 0x1 = Enables Filter Selection for EXT_INT41[2] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT41[2] This value is valid when FLTSEL16 (of EXT_INT41) is 0x1. Filter Enable for EXT_INT41[1] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT41[1] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT41[1] This value is valid when FLTSEL16 (of EXT_INT41) is 0x1. Filter Enable for EXT_INT41[0] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT41[0] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT41[0] This value is valid when FLTSEL16 (of EXT_INT41) is 0x1. Reset Value 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 4-274 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.217 EXT_INT41_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0E8C, Reset Value = 0x8080_8080 Name FLTEN16[7] FLTSEL16[7] FLTWIDTH16[7] FLTEN16[6] FLTSEL16[6] FLTWIDTH16[6] FLTEN16[5] FLTSEL16[5] FLTWIDTH16[5] FLTEN16[4] FLTSEL16[4] FLTWIDTH16[4] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Type RW RW RW RW RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT41[7] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT41[7] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT41[7] This value is valid when FLTSEL16 (of EXT_INT41) is 0x1. Filter Enable for EXT_INT41[6] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT41[6] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT41[6] This value is valid when FLTSEL16 (of EXT_INT41) is 0x1. Filter Enable for EXT_INT41[5] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT41[5] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT41[5] This value is valid when FLTSEL16 (of EXT_INT41) is 0x1. Filter Enable for EXT_INT41[4] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT41[4] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT41[4] This value is valid when FLTSEL16 (of EXT_INT41) is 0x1. Reset Value 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 4-275 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.218 EXT_INT42_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0E90, Reset Value = 0x8080_8080 Name FLTEN17[3] FLTSEL17[3] FLTWIDTH17[3] FLTEN17[2] FLTSEL17[2] FLTWIDTH17[2] FLTEN17[1] FLTSEL17[1] FLTWIDTH17[1] FLTEN17[0] FLTSEL17[0] FLTWIDTH17[0] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Type RW RW RW RW RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT42[3] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT42[3] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT42[3] This value is valid when FLTSEL17 (of EXT_INT42) is 0x1. Filter Enable for EXT_INT42[2] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT42[2] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT42[2] This value is valid when FLTSEL17 (of EXT_INT42) is 0x1. Filter Enable for EXT_INT42[1] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT42[1] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT42[1] This value is valid when FLTSEL17 (of EXT_INT42) is 0x1. Filter Enable for EXT_INT42[0] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT42[0] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT42[0] This value is valid when FLTSEL17 (of EXT_INT42) is 0x1. Reset Value 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 4-276 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.219 EXT_INT42_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0E94, Reset Value = 0x8080_8080 Name FLTEN17[7] FLTSEL17[7] FLTWIDTH17[7] FLTEN17[6] FLTSEL17[6] FLTWIDTH17[6] FLTEN17[5] FLTSEL17[5] FLTWIDTH17[5] FLTEN17[4] FLTSEL17[4] FLTWIDTH17[4] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Type RW RW RW RW RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT42[7] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT42[7] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT42[7] This value is valid when FLTSEL17 (of EXT_INT42) is 0x1. Filter Enable for EXT_INT42[6] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT42[6] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT42[6] This value is valid when FLTSEL17 (of EXT_INT42) is 0x1. Filter Enable for EXT_INT42[5] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT42[5] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT42[5] This value is valid when FLTSEL17 (of EXT_INT42) is 0x1. Filter Enable for EXT_INT42[4] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT42[4] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT42[4] This value is valid when FLTSEL17 (of EXT_INT42) is 0x1. Reset Value 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 4-277 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.220 EXT_INT43_FLTCON0  Base Address: 0x1100_0000  Address = Base Address + 0x0E98, Reset Value = 0x8080_8080 Name FLTEN18[3] FLTSEL18[3] FLTWIDTH18[3] FLTEN18[2] FLTSEL18[2] FLTWIDTH18[2] FLTEN18[1] FLTSEL18[1] FLTWIDTH18[1] FLTEN18[0] FLTSEL18[0] FLTWIDTH18[0] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Type RW RW RW RW RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT43[3] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT43[3] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT43[3] This value is valid when FLTSEL18 (of EXT_INT43) is 0x1. Filter Enable for EXT_INT43[2] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT43[2] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT43[2] This value is valid when FLTSEL18 (of EXT_INT43) is 0x1. Filter Enable for EXT_INT43[1] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT43[1] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT43[1] This value is valid when FLTSEL18 (of EXT_INT43) is 0x1. Filter Enable for EXT_INT43[0] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT43[0] 0x0 = Delays filter 0x1 = Digital filter(clock count) Filtering width of EXT_INT43[0] This value is valid when FLTSEL18 (of EXT_INT43) is 0x1. Reset Value 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 4-278 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.221 EXT_INT43_FLTCON1  Base Address: 0x1100_0000  Address = Base Address + 0x0E9C, Reset Value = 0x8080_8080 Name FLTEN18[7] FLTSEL18[7] FLTWIDTH18[7] FLTEN18[6] FLTSEL18[6] FLTWIDTH18[6] FLTEN18[5] FLTSEL18[5] FLTWIDTH18[5] FLTEN18[4] FLTSEL18[4] FLTWIDTH18[4] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Type RW RW RW RW RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT43[7] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT43[7] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT43[7] This value is valid when FLTSEL18 (of EXT_INT43) is 0x1. Filter Enable for EXT_INT43[6] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT43[6] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT43[6] This value is valid when FLTSEL18 (of EXT_INT43) is 0x1. Filter Enable for EXT_INT43[5] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT43[5] 0x0 = Delays filter 0x1 = Digital filter(clock count) Filtering width of EXT_INT43[5] This value is valid when FLTSEL18 (of EXT_INT43) is 0x1. Filter Enable for EXT_INT43[4] 0x0 = Disables Filter 0x1 = Enables Filter Filter Selection for EXT_INT43[4] 0x0 = Delays filter 0x1 = Digital filter (clock count) Filtering width of EXT_INT43[4] This value is valid when FLTSEL18 (of EXT_INT43) is 0x1. Reset Value 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 0x1 0x0 0x00 4-279 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.222 EXT_INT40_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0F00, Reset Value = 0x0000_00FF Name RSVD EXT_INT40_MASK[7] EXT_INT40_MASK[6] EXT_INT40_MASK[5] EXT_INT40_MASK[4] EXT_INT40_MASK[3] EXT_INT40_MASK[2] EXT_INT40_MASK[1] EXT_INT40_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-280 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.223 EXT_INT41_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0F04, Reset Value = 0x0000_00FF Name RSVD EXT_INT41_MASK[7] EXT_INT41_MASK[6] EXT_INT41_MASK[5] EXT_INT41_MASK[4] EXT_INT41_MASK[3] EXT_INT41_MASK[2] EXT_INT41_MASK[1] EXT_INT41_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-281 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.224 EXT_INT42_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0F08, Reset Value = 0x0000_00FF Name RSVD EXT_INT42_MASK[7] EXT_INT42_MASK[6] EXT_INT42_MASK[5] EXT_INT42_MASK[4] EXT_INT42_MASK[3] EXT_INT42_MASK[2] EXT_INT42_MASK[1] EXT_INT42_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-282 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.225 EXT_INT43_MASK  Base Address: 0x1100_0000  Address = Base Address + 0x0F0C, Reset Value = 0x0000_00FF Name RSVD EXT_INT43_MASK[7] EXT_INT43_MASK[6] EXT_INT43_MASK[5] EXT_INT43_MASK[4] EXT_INT43_MASK[3] EXT_INT43_MASK[2] EXT_INT43_MASK[1] EXT_INT43_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-283 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.226 EXT_INT40_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0F40, Reset Value = 0x0000_0000 Name RSVD EXT_INT40_PEND[7] EXT_INT40_PEND[6] EXT_INT40_PEND[5] EXT_INT40_PEND[4] EXT_INT40_PEND[3] EXT_INT40_PEND[2] EXT_INT40_PEND[1] EXT_INT40_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-284 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.227 EXT_INT41_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0F44, Reset Value = 0x0000_0000 Name RSVD EXT_INT41_PEND[7] EXT_INT41_PEND[6] EXT_INT41_PEND[5] EXT_INT41_PEND[4] EXT_INT41_PEND[3] EXT_INT41_PEND[2] EXT_INT41_PEND[1] EXT_INT41_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-285 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.228 EXT_INT42_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0F48, Reset Value = 0x0000_0000 Name RSVD EXT_INT42_PEND[7] EXT_INT42_PEND[6] EXT_INT42_PEND[5] EXT_INT42_PEND[4] EXT_INT42_PEND[3] EXT_INT42_PEND[2] EXT_INT42_PEND[1] EXT_INT42_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-286 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.229 EXT_INT43_PEND  Base Address: 0x1100_0000  Address = Base Address + 0x0F4C, Reset Value = 0x0000_0000 Name RSVD EXT_INT43_PEND[7] EXT_INT43_PEND[6] EXT_INT43_PEND[5] EXT_INT43_PEND[4] EXT_INT43_PEND[3] EXT_INT43_PEND[2] EXT_INT43_PEND[1] EXT_INT43_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-287 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.3.230 PDNEN  Base Address: 0x1100_0000  Address = Base Address + 0x0F80, Reset Value = 0x00 Name Bit Type Description RSVD [7:2] – Reserved PDNEN_CFG [1] RW 0 = Automatically by power down mode 1 = By PDNEN bit PDNEN Power down mode pad state enable register. 0 = PADs Controlled by normal mode This bit is set to "1" automatically when system enters [0] RW into Power down mode and clears by writing "0" to this bit or cold reset. After wake up from Power down mode, this bit maintains value "1" until writing "0" 1 = PADs Controlled by Power Down mode control registers Reset Value 0x00 0x0 0x0 4-288 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.4 Part 3 4.3.4.1 GPZCON  Base Address: 0x0386_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_0000 Name GPZCON[6] GPZCON[5] GPZCON[4] GPZCON[3] GPZCON[2] GPZCON[1] GPZCON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = I2S_0_SDO[2] 0x3 = ST_INT 0x4 to 0xE = Reserved 0xF = EXT_INT50[6] 0x0 = Input 0x1 = Output 0x2 = I2S_0_SDO[1] 0x3 = ST_TICK 0x4 to 0xE = Reserved 0xF = EXT_INT50[5] 0x0 = Input 0x1 = Output 0x2 = I2S_0_SDO[0] 0x3 = PCM_0_SOUT 0x4 to 0xE = Reserved 0xF = EXT_INT50[4] 0x0 = Input 0x1 = Output 0x2 = I2S_0_SDI 0x3 = PCM_0_SIN 0x4 to 0xE = Reserved 0xF = EXT_INT50[3] 0x0 = Input 0x1 = Output 0x2 = I2S_0_LRCK 0x3 = PCM_0_FSYNC 0x4 to 0xE = Reserved 0xF = EXT_INT50[2] 0x0 = Input 0x1 = Output 0x2 = I2S_0_CDCLK 0x3 = PCM_0_EXTCLK 0x4 to 0xE = Reserved 0xF = EXT_INT50[1] 0x0 = Input 0x1 = Output 0x2 = I2S_0_SCLK 0x3 = PCM_0_SCLK 0x4 to 0xE = Reserved 0xF = EXT_INT50[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-289 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.4.2 GPZDAT  Base Address: 0x0386_0000  Address = Base Address + 0x0004, Reset Value = 0x00 Name GPZDAT[6:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. While configuring as [6:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. 4.3.4.3 GPZPUD  Base Address: 0x0386_0000  Address = Base Address + 0x0008, Reset Value = 0x1555 Name GPZPUD[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up 4.3.4.4 GPZDRV  Base Address: 0x0386_0000  Address = Base Address + 0x000C, Reset Value = 0x00_0000 Name GPZDRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 6 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 Reset Value 0x1555 Reset Value 0x00 0x0000 4-290 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.4.5 GPZCONPDN  Base Address: 0x0386_0000  Address = Base Address + 0x0010, Reset Value = 0x0000 Name GPZ[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.4.6 GPZPUDPDN  Base Address: 0x0386_0000  Address = Base Address + 0x0014, Reset Value = 0x0000 Name GPZ[n] Bit [2n + 1:2n] n = 0 to 6 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-291 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.4.7 EXT_INT50CON  Base Address: 0x0386_0000  Address = Base Address + 0x0700, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT50_CON[6] RSVD EXT_INT50_CON[5] RSVD EXT_INT50_CON[4] RSVD EXT_INT50_CON[3] RSVD EXT_INT50_CON[2] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Type – – RW – RW – RW – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT50[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT50[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT50[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT50[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT50[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-292 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name Bit Type Description RSVD [7] – Reserved Sets signaling method of EXT_INT50[1] 0x0 = Low level 0x1 = High level EXT_INT50_CON[1] [6:4] RW 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved RSVD [3] – Reserved Sets signaling method of EXT_INT50[0] 0x0 = Low level 0x1 = High level EXT_INT50_CON[0] [2:0] RW 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 4-293 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.4.8 EXT_INT50_FLTCON0  Base Address: 0x0386_0000  Address = Base Address + 0x0800, Reset Value = 0x0000_0000 Name FLTEN1[3] FLTWIDTH1[3] FLTEN1[2] FLTWIDTH1[2] FLTEN1[1] FLTWIDTH1[1] FLTEN1[0] FLTWIDTH1[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT50[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT50[3] Filter Enable for EXT_INT50[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT50[2] Filter Enable for EXT_INT50[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT50[1] Filter Enable for EXT_INT50[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT50[0] 4.3.4.9 EXT_INT50_FLTCON1  Base Address: 0x0386_0000  Address = Base Address + 0x0804, Reset Value = 0x0000_0000 Name RSVD FLTEN1[6] FLTWIDTH1[6] FLTEN1[5] FLTWIDTH1[5] FLTEN1[4] FLTWIDTH1[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW RW RW Description Reserved Filter Enable for EXT_INT50[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT50[6] Filter Enable for EXT_INT50[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT50[5] Filter Enable for EXT_INT50[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT50[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 Reset Value 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-294 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.4.10 EXT_INT50_MASK  Base Address: 0x0386_0000  Address = Base Address + 0x0900, Reset Value = 0x0000_007F Name RSVD EXT_INT50_MASK[6] EXT_INT50_MASK[5] EXT_INT50_MASK[4] EXT_INT50_MASK[3] EXT_INT50_MASK[2] EXT_INT50_MASK[1] EXT_INT50_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 4.3.4.11 EXT_INT50_PEND  Base Address: 0x0386_0000  Address = Base Address + 0x0A00, Reset Value = 0x0000_0000 Name RSVD EXT_INT50_PEND[6] EXT_INT50_PEND[5] EXT_INT50_PEND[4] EXT_INT50_PEND[3] EXT_INT50_PEND[2] EXT_INT50_PEND[1] EXT_INT50_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = interrupt Occurs 0x0 = Not occur 0x1 = interrupt Occurs 0x0 = Not occur 0x1 = interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x0000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Reset Value 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-295 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.4.12 EXT_INT_SERVICE_XD  Base Address: 0x0386_0000  Address = Base Address + 0x0B08, Reset Value = 0x0000_0000 Name RSVD SVC_Group_Num SVC_Num Bit [31:8] [7:3] [2:0] Type RW RW RW Description Reserved EXT_INT Service group number 0x1 = EXT_INT50 Interrupt number to be serviced 4.3.4.13 EXT_INT_SERVICE_PEND_XD  Base Address: 0x0386_0000  Address = Base Address + 0x0B0C, Reset Value = 0x0000_0000 Name RSVD SVC_PEND Bit [31:8] [7:0] Type RW RW Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 4.3.4.14 EXT_INT_GRPFIXPRI_XD  Base Address: 0x0386_0000  Address = Base Address + 0x0B10, Reset Value = 0x0000_0000 Name RSVD Bit [31:4] Highest_GRP_NUM [3:0] Type – RW Description Reserved When fixed group priority mode = 0, then group number should be of the highest priority. 0x0 = EXT_INT50 Reset Value 0x0000000 0x00 0x0 Reset Value 0x0000000 0x00 Reset Value 0x0000000 0x00 4-296 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.4.15 EXT_INT50_FIXPRI  Base Address: 0x0386_0000  Address = Base Address + 0x0B14, Reset Value = 0x0000_0000 Name RSVD Bit [31:3] Highest_EINT_NUM [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 0 (EXT_INT50) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.4.16 PDNEN  Base Address: 0x0386_0000  Address = Base Address + 0x0F80, Reset Value = 0x00 Name RSVD PDNEN_CFG PDNEN Bit Type Description [7:2] – Reserved [1] RW 0 = Automatically by power down mode 1 = By PDNEN bit Power down mode pad state enable register. 0 = PADs Controlled by normal mode This bit is set to "1" automatically when system enters into Power down mode and clears by writing [0] RW "0" to this bit or cold reset. After wake up from Power down mode, this bit maintains value "1" until writing "0" 1 = PADs Controlled by Power Down mode control registers Reset Value 0x00 0x0 0x0 4-297 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5 Part 4 4.3.5.1 GPV0CON  Base Address: 0x106E_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_0000 Name GPV0CON[7] GPV0CON[6] GPV0CON[5] GPV0CON[4] GPV0CON[3] GPV0CON[2] GPV0CON[1] GPV0CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[7] 0x3 to 0xE = Reserved 0xF = EXT_INT30[7] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[6] 0x3 to 0xE = Reserved 0xF = EXT_INT30[6] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[5] 0x3 to 0xE = Reserved 0xF = EXT_INT30[5] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[4] 0x3 to 0xE = Reserved 0xF = EXT_INT30[4] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[3] 0x3 to 0xE = Reserved 0xF = EXT_INT30[3] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[2] 0x3 to 0xE = Reserved 0xF = EXT_INT30[2] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[1] 0x3 to 0xE = Reserved 0xF = EXT_INT30[1] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[0] 0x3 to 0xE = Reserved 0xF = EXT_INT30[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-298 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.2 GPV0DAT  Base Address: 0x106E_0000  Address = Base Address + 0x0004, Reset Value = 0x00 Name GPV0DAT[7:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.5.3 GPV0PUD  Base Address: 0x106E_0000  Address = Base Address + 0x0008, Reset Value = 0x5555 Name GPV0PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.5.4 GPV0DRV  Base Address: 0x106E_0000  Address = Base Address + 0x000C, Reset Value = 0x00_0000 Name GPV0DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-299 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.5 GPV0CONPDN  Base Address: 0x106E_0000  Address = Base Address + 0x0010, Reset Value = 0x0000 Name GPV0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.5.6 GPV0PUDPDN  Base Address: 0x106E_0000  Address = Base Address + 0x0014, Reset Value = 0x0000 Name GPV0[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-300 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.7 GPV1CON  Base Address: 0x106E_0000  Address = Base Address + 0x0020, Reset Value = 0x0000_0000 Name GPV1CON[7] GPV1CON[6] GPV1CON[5] GPV1CON[4] GPV1CON[3] GPV1CON[2] GPV1CON[1] GPV1CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[15] 0x3 to 0xE = Reserved 0xF = EXT_INT31[7] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[14] 0x3 to 0xE = Reserved 0xF = EXT_INT31[6] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[13] 0x3 to 0xE = Reserved 0xF = EXT_INT31[5] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[12] 0x3 to 0xE = Reserved 0xF = EXT_INT31[4] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[11] 0x3 to 0xE = Reserved 0xF = EXT_INT31[3] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[10] 0x3 to 0xE = Reserved 0xF = EXT_INT31[2] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[9] 0x3 to 0xE = Reserved 0xF = EXT_INT31[1] 0x0 = Input 0x1 = Output 0x2 = C2C_RXD[8] 0x3 to 0xE = Reserved 0xF = EXT_INT31[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-301 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.8 GPV1DAT  Base Address: 0x106E_0000  Address = Base Address + 0x0024, Reset Value = 0x00 Name GPV1DAT[7:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.5.9 GPV1PUD  Base Address: 0x106E_0000  Address = Base Address + 0x0028, Reset Value = 0x5555 Name GPV1PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.5.10 GPV1DRV  Base Address: 0x106E_0000  Address = Base Address + 0x002C, Reset Value = 0x00_0000 Name GPV1DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-302 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.11 GPV1CONPDN  Base Address: 0x106E_0000  Address = Base Address + 0x0030, Reset Value = 0x0000 Name GPV1[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.5.12 GPV1PUDPDN  Base Address: 0x106E_0000  Address = Base Address + 0x0034, Reset Value = 0x0000 Name GPV1[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-303 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.13 ETC7PUD  Base Address: 0x106E_0000  Address = Base Address + 0x0048, Reset Value = 0x0005 Name ETC7PUD[n] Bit [2n + 1:2n] n = 0 to 1 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up ETC7PUD[1:0] controls Xc2cRXCLK[0]. ETC7PUD[3:2] controls Xc2cRXCLK[1]. Reset Value 0x0005 4.3.5.14 ETC7DRV  Base Address: 0x106E_0000  Address = Base Address + 0x004C, Reset Value = 0x00_0000 Name ETC7DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 1 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x ETC7DRV[1:0] controls Xc2cRXCLK[0]. ETC7DRV[3:2] controls Xc2cRXCLK[1]. Reset Value 0x00 0x0000 4-304 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.15 GPV2CON  Base Address: 0x106E_0000  Address = Base Address + 0x0060, Reset Value = 0x0000_0000 Name GPV2CON[7] GPV2CON[6] GPV2CON[5] GPV2CON[4] GPV2CON[3] GPV2CON[2] GPV2CON[1] GPV2CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[7] 0x3 to 0xE = Reserved 0xF = EXT_INT32[7] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[6] 0x3 to 0xE = Reserved 0xF = EXT_INT32[6] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[5] 0x3 to 0xE = Reserved 0xF = EXT_INT32[5] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[4] 0x3 to 0xE = Reserved 0xF = EXT_INT32[4] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[3] 0x3 to 0xE = Reserved 0xF = EXT_INT32[3] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[2] 0x3 to 0xE = Reserved 0xF = EXT_INT32[2] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[1] 0x3 to 0xE = Reserved 0xF = EXT_INT32[1] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[0] 0x3 to 0xE = Reserved 0xF = EXT_INT32[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-305 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.16 GPV2DAT  Base Address: 0x106E_0000  Address = Base Address + 0x0064, Reset Value = 0x00 Name GPV2DAT[7:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.5.17 GPV2PUD  Base Address: 0x106E_0000  Address = Base Address + 0x0068, Reset Value = 0x5555 Name GPV2PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x5555 4.3.5.18 GPV2DRV  Base Address: 0x106E_0000  Address = Base Address + 0x006C, Reset Value = 0x00_0000 Name GPV2DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-306 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.19 GPV2CONPDN  Base Address: 0x106E_0000  Address = Base Address + 0x0070, Reset Value = 0x0000 Name GPV2[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.5.20 GPV2PUDPDN  Base Address: 0x106E_0000  Address = Base Address + 0x0074, Reset Value = 0x0000 Name GPV2[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-307 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.21 GPV3CON  Base Address: 0x106E_0000  Address = Base Address + 0x0080, Reset Value = 0x0000_0000 Name GPV3CON[7] GPV3CON[6] GPV3CON[5] GPV3CON[4] GPV3CON[3] GPV3CON[2] GPV3CON[1] GPV3CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW RW RW RW RW Description 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[15] 0x3 to 0xE = Reserved 0xF = EXT_INT33[7] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[14] 0x3 to 0xE = Reserved 0xF = EXT_INT33[6] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[13] 0x3 to 0xE = Reserved 0xF = EXT_INT33[5] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[12] 0x3 to 0xE = Reserved 0xF = EXT_INT33[4] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[11] 0x3 to 0xE = Reserved 0xF = EXT_INT33[3] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[10] 0x3 to 0xE = Reserved 0xF = EXT_INT33[2] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[9] 0x3 to 0xE = Reserved 0xF = EXT_INT33[1] 0x0 = Input 0x1 = Output 0x2 = C2C_TXD[8] 0x3 to 0xE = Reserved 0xF = EXT_INT33[0] Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4-308 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.22 GPV3DAT  Base Address: 0x106E_0000  Address = Base Address + 0x0084, Reset Value = 0x00 Name GPV3DAT[7:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as [7:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.5.23 GPV3PUD  Base Address: 0x106E_0000  Address = Base Address + 0x0088, Reset Value = 0x5555 Name GPV3PUD[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved, 0x3 = Enables Pull-up Reset Value 0x5555 4.3.5.24 GPV3DRV  Base Address: 0x106E_0000  Address = Base Address + 0x008C, Reset Value = 0x00_0000 Name GPV3DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 7 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x Reset Value 0x00 0x0000 4-309 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.25 GPV3CONPDN  Base Address: 0x106E_0000  Address = Base Address + 0x0090, Reset Value = 0x0000 Name GPV3[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.5.26 GPV3PUDPDN  Base Address: 0x106E_0000  Address = Base Address + 0x0094, Reset Value = 0x0000 Name GPV3[n] Bit [2n + 1:2n] n = 0 to 7 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 Reset Value 0x00 4-310 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.27 ETC8PUD  Base Address: 0x106E_0000  Address = Base Address + 0x00A8, Reset Value = 0x0005 Name ETC8PUD[n] Bit [2n + 1:2n] n = 0 to 1 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up ETC8PUD[1:0] controls Xc2cTXCLK[0]. ETC8PUD[3:2] controls Xc2cTXCLK[1]. Reset Value 0x0005 4.3.5.28 ETC8DRV  Base Address: 0x106E_0000  Address = Base Address + 0x00AC, Reset Value = 0x00_0000 Name ETC8DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 1 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x ETC8DRV[1:0] controls Xc2cTXCLK[0]. ETC8DRV[3:2] controls Xc2cTXCLK[1]. Reset Value 0x00 0x0000 4-311 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.29 GPV4CON  Base Address: 0x106E_0000  Address = Base Address + 0x00C0, Reset Value = 0x0000_0000 Name GPV4CON[1] GPV4CON[0] Bit Type Description 0x0 = Input 0x1 = Output [7:4] RW 0x2 = C2C_WKREQOUT 0x3 to 0xE = Reserved 0xF = EXT_INT34[1] 0x0 = Input 0x1 = Output [3:0] RW 0x2 = C2C_WKREQIN 0x3 to 0xE = Reserved 0xF = EXT_INT34[0] Reset Value 0x00 0x00 4.3.5.30 GPV4DAT  Base Address: 0x106E_0000  Address = Base Address + 0x00C4, Reset Value = 0x00 Name GPV4DAT[1:0] Bit Type Description When you configure port as input port then corresponding bit is pin state. When configuring as [1:0] RWX output port then pin state should be same as corresponding bit. When the port is configured as functional pin, the undefined value will be read. Reset Value 0x00 4.3.5.31 GPV4PUD  Base Address: 0x106E_0000  Address = Base Address + 0x00C8, Reset Value = 0x0005 Name GPV4PUD[n] Bit [2n + 1:2n] n = 0 to 1 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x0005 4-312 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.32 GPV4DRV  Base Address: 0x106E_0000  Address = Base Address + 0x00CC, Reset Value = 0x00_0000 Name GPV4DRV[n] Bit [23:16] [2n + 1:2n] n = 0 to 1 Type RW RW Description Reserved (Should be zero) 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x 4.3.5.33 GPV4CONPDN  Base Address: 0x106E_0000  Address = Base Address + 0x00D0, Reset Value = 0x0000 Name GPV4[n] Bit [2n + 1:2n] n = 0 to 1 Type RW Description 0x0 = Outputs 0 0x1 = Outputs 1 0x2 = Input 0x3 = Previous state 4.3.5.34 GPV4PUDPDN  Base Address: 0x106E_0000  Address = Base Address + 0x00D4, Reset Value = 0x0000 Name GPV4[n] Bit [2n + 1:2n] n = 0 to 1 Type RW Description 0x0 = Disables Pull-up/Pull-down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up Reset Value 0x00 0x0000 Reset Value 0x00 Reset Value 0x00 4-313 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.35 EXT_INT30CON  Base Address: 0x106E_0000  Address = Base Address + 0x0700, Reset Value = 0x0000_0000 Name RSVD EXT_INT30_CON[7] RSVD EXT_INT30_CON[6] RSVD EXT_INT30_CON[5] RSVD EXT_INT30_CON[4] RSVD EXT_INT30_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT30[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT30[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT30[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT30[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT30[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-314 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT30_CON[2] RSVD EXT_INT30_CON[1] RSVD EXT_INT30_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT30[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT30[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT30[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-315 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.36 EXT_INT31CON  Base Address: 0x106E_0000  Address = Base Address + 0x0704, Reset Value = 0x0000_0000 Name RSVD EXT_INT31_CON[7] RSVD EXT_INT31_CON[6] RSVD EXT_INT31_CON[5] RSVD EXT_INT31_CON[4] RSVD EXT_INT31_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT31[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT31[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT31[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT31[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT31[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-316 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT31_CON[2] RSVD EXT_INT31_CON[1] RSVD EXT_INT31_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT31[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT31[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT31[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-317 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.37 EXT_INT32CON  Base Address: 0x106E_0000  Address = Base Address + 0x0708, Reset Value = 0x0000_0000 Name RSVD EXT_INT32_CON[7] RSVD EXT_INT32_CON[6] RSVD EXT_INT32_CON[5] RSVD EXT_INT32_CON[4] RSVD EXT_INT32_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT32[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT32[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT32[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT32[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT32[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-318 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT32_CON[2] RSVD EXT_INT32_CON[1] RSVD EXT_INT32_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets the signaling method of EXT_INT32[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT32[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT32[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-319 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.38 EXT_INT33CON  Base Address: 0x106E_0000  Address = Base Address + 0x070C, Reset Value = 0x0000_0000 Name RSVD EXT_INT33_CON[7] RSVD EXT_INT33_CON[6] RSVD EXT_INT33_CON[5] RSVD EXT_INT33_CON[4] RSVD EXT_INT33_CON[3] RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] Type – RW – RW – RW – RW – RW – Description Reserved Sets signaling method of EXT_INT33[7] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT33[6] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT33[5] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT33[4] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT33[3] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-320 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control Name EXT_INT33_CON[2] RSVD EXT_INT33_CON[1] RSVD EXT_INT33_CON[0] Bit [10:8] [7] [6:4] [3] [2:0] Type RW – RW – RW Description Sets signaling method of EXT_INT33[2] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT33[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT33[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 4-321 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.39 EXT_INT34CON  Base Address: 0x106E_0000  Address = Base Address + 0x0710, Reset Value = 0x0000_0000 Name RSVD RSVD EXT_INT34_CON[1] RSVD EXT_INT34_CON[0] Bit [31:8] [7] [6:4] [3] [2:0] Type – – RW – RW Description Reserved Reserved Sets signaling method of EXT_INT34[1] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reserved Sets signaling method of EXT_INT34[0] 0x0 = Low level 0x1 = High level 0x2 = Triggers Falling edge 0x3 = Triggers Rising edge 0x4 = Triggers Both edge 0x5 to 0x7 = Reserved Reset Value 0x000000 0x0 0x0 0x0 0x0 4-322 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.40 EXT_INT30_FLTCON0  Base Address: 0x106E_0000  Address = Base Address + 0x0800, Reset Value = 0x0000_0000 Name FLTEN1[3] FLTWIDTH1[3] FLTEN1[2] FLTWIDTH1[2] FLTEN1[1] FLTWIDTH1[1] FLTEN1[0] FLTWIDTH1[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT30[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT30[3] Filter Enable for EXT_INT30[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT30[2] Filter Enable for EXT_INT30[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT30[1] Filter Enable for EXT_INT30[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT30[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-323 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.41 EXT_INT30_FLTCON1  Base Address: 0x106E_0000  Address = Base Address + 0x0804, Reset Value = 0x0000_0000 Name FLTEN1[7] FLTWIDTH1[7] FLTEN1[6] FLTWIDTH1[6] FLTEN1[5] FLTWIDTH1[5] FLTEN1[4] FLTWIDTH1[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT30[7] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT30[7] Filter Enable for EXT_INT30[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT30[6] Filter Enable for EXT_INT30[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT30[5] Filter Enable for EXT_INT30[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT30[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-324 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.42 EXT_INT31_FLTCON0  Base Address: 0x106E_0000  Address = Base Address + 0x0808, Reset Value = 0x0000_0000 Name FLTEN2[3] FLTWIDTH2[3] FLTEN2[2] FLTWIDTH2[2] FLTEN2[1] FLTWIDTH2[1] FLTEN2[0] FLTWIDTH2[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT31[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT31[3] Filter Enable for EXT_INT31[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT31[2] Filter Enable for EXT_INT31[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT31[1] Filter Enable for EXT_INT31[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT31[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-325 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.43 EXT_INT31_FLTCON1  Base Address: 0x106E_0000  Address = Base Address + 0x080C, Reset Value = 0x0000_0000 Name FLTEN2[7] FLTWIDTH2[7] FLTEN2[6] FLTWIDTH2[6] FLTEN2[5] FLTWIDTH2[5] FLTEN2[4] FLTWIDTH2[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT31[7] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT31[7] Filter Enable for EXT_INT31[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT31[6] Filter Enable for EXT_INT31[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT31[5] Filter Enable for EXT_INT31[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT31[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-326 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.44 EXT_INT32_FLTCON0  Base Address: 0x106E_0000  Address = Base Address + 0x0810, Reset Value = 0x0000_0000 Name FLTEN3[3] FLTWIDTH3[3] FLTEN3[2] FLTWIDTH3[2] FLTEN3[1] FLTWIDTH3[1] FLTEN3[0] FLTWIDTH3[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT32[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT32[3] Filter Enable for EXT_INT32[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT32[2] Filter Enable for EXT_INT32[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT32[1] Filter Enable for EXT_INT32[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT32[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-327 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.45 EXT_INT32_FLTCON1  Base Address: 0x106E_0000  Address = Base Address + 0x0814, Reset Value = 0x0000_0000 Name FLTEN3[7] FLTWIDTH3[7] FLTEN3[6] FLTWIDTH3[6] FLTEN3[5] FLTWIDTH3[5] FLTEN3[4] FLTWIDTH3[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT32[7] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT32[7] Filter Enable for EXT_INT32[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT32[6] Filter Enable for EXT_INT32[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT32[5] Filter Enable for EXT_INT32[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT32[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-328 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.46 EXT_INT33_FLTCON0  Base Address: 0x106E_0000  Address = Base Address + 0x0818, Reset Value = 0x0000_0000 Name FLTEN4[3] FLTWIDTH4[3] FLTEN4[2] FLTWIDTH4[2] FLTEN4[1] FLTWIDTH4[1] FLTEN4[0] FLTWIDTH4[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT33[3] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT33[3] Filter Enable for EXT_INT33[2] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT33[2] Filter Enable for EXT_INT33[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT33[1] Filter Enable for EXT_INT33[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT33[0] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-329 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.47 EXT_INT33_FLTCON1  Base Address: 0x106E_0000  Address = Base Address + 0x081C, Reset Value = 0x0000_0000 Name FLTEN4[7] FLTWIDTH4[7] FLTEN4[6] FLTWIDTH4[6] FLTEN4[5] FLTWIDTH4[5] FLTEN4[4] FLTWIDTH4[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Type RW RW RW RW RW RW RW RW Description Filter Enable for EXT_INT33[7] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT33[7] Filter Enable for EXT_INT33[6] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT33[6] Filter Enable for EXT_INT33[5] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT33[5] Filter Enable for EXT_INT33[4] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT33[4] Reset Value 0x0 0x00 0x0 0x00 0x0 0x00 0x0 0x00 4-330 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.48 EXT_INT34_FLTCON0  Base Address: 0x106E_0000  Address = Base Address + 0x0820, Reset Value = 0x0000_0000 Name RSVD FLTEN5[1] FLTWIDTH5[1] FLTEN5[0] FLTWIDTH5[0] Bit [31:16] [15] [14:8] [7] [6:0] Type – RW RW RW RW Description Reserved Filter Enable for EXT_INT34[1] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT34[1] Filter Enable for EXT_INT34[0] 0x0 = Disables Filter 0x1 = Enables Filter Filtering width of EXT_INT34[0] 4.3.5.49 EXT_INT34_FLTCON1  Base Address: 0x106E_0000  Address = Base Address + 0x0824, Reset Value = 0x0000_0000 Name RSVD Bit [31:0] Type – Reserved Description Reset Value 0 0x0 0x00 0x0 0x00 Reset Value 0x00000000 4-331 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.50 EXT_INT30_MASK  Base Address: 0x106E_0000  Address = Base Address + 0x0900, Reset Value = 0x0000_00FF Name RSVD EXT_INT30_MASK[7] EXT_INT30_MASK[6] EXT_INT30_MASK[5] EXT_INT30_MASK[4] EXT_INT30_MASK[3] EXT_INT30_MASK[2] EXT_INT30_MASK[1] EXT_INT30_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-332 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.51 EXT_INT31_MASK  Base Address: 0x106E_0000  Address = Base Address + 0x0904, Reset Value = 0x0000_00FF Name RSVD EXT_INT31_MASK[7] EXT_INT31_MASK[6] EXT_INT31_MASK[5] EXT_INT31_MASK[4] EXT_INT31_MASK[3] EXT_INT31_MASK[2] EXT_INT31_MASK[1] EXT_INT31_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-333 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.52 EXT_INT32_MASK  Base Address: 0x106E_0000  Address = Base Address + 0x0908, Reset Value = 0x0000_00FF Name RSVD EXT_INT32_MASK[7] EXT_INT32_MASK[6] EXT_INT32_MASK[5] EXT_INT32_MASK[4] EXT_INT32_MASK[3] EXT_INT32_MASK[2] EXT_INT32_MASK[1] EXT_INT32_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 4-334 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.53 EXT_INT33_MASK  Base Address: 0x106E_0000  Address = Base Address + 0x090C, Reset Value = 0x0000_00FF Name RSVD EXT_INT33_MASK[7] EXT_INT33_MASK[6] EXT_INT33_MASK[5] EXT_INT33_MASK[4] EXT_INT33_MASK[3] EXT_INT33_MASK[2] EXT_INT33_MASK[1] EXT_INT33_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked 4.3.5.54 EXT_INT34_MASK  Base Address: 0x106E_0000  Address = Base Address + 0x0910, Reset Value = 0x0000_0003 Name RSVD EXT_INT34_MASK[1] EXT_INT34_MASK[0] Bit [31:2] [1] [0] Type – RW RW Description Reserved 0x0 = Enables Interrupt 0x1 = Masked 0x0 = Enables Interrupt 0x1 = Masked Reset Value 0x000000 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Reset Value 0x00000000 0x1 0x1 4-335 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.55 EXT_INT30_PEND  Base Address: 0x106E_0000  Address = Base Address + 0x0A00, Reset Value = 0x0000_0000 Name RSVD EXT_INT30_PEND[7] EXT_INT30_PEND[6] EXT_INT30_PEND[5] EXT_INT30_PEND[4] EXT_INT30_PEND[3] EXT_INT30_PEND[2] EXT_INT30_PEND[1] EXT_INT30_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-336 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.56 EXT_INT31_PEND  Base Address: 0x106E_0000  Address = Base Address + 0x0A04, Reset Value = 0x0000_0000 Name RSVD EXT_INT31_PEND[7] EXT_INT31_PEND[6] EXT_INT31_PEND[5] EXT_INT31_PEND[4] EXT_INT31_PEND[3] EXT_INT31_PEND[2] EXT_INT31_PEND[1] EXT_INT31_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-337 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.57 EXT_INT32_PEND  Base Address: 0x106E_0000  Address = Base Address + 0x0A08, Reset Value = 0x0000_0000 Name RSVD EXT_INT32_PEND[7] EXT_INT32_PEND[6] EXT_INT32_PEND[5] EXT_INT32_PEND[4] EXT_INT32_PEND[3] EXT_INT32_PEND[2] EXT_INT32_PEND[1] EXT_INT32_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4-338 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.58 EXT_INT33_PEND  Base Address: 0x106E_0000  Address = Base Address + 0x0A0C, Reset Value = 0x0000_0000 Name RSVD EXT_INT33_PEND[7] EXT_INT33_PEND[6] EXT_INT33_PEND[5] EXT_INT33_PEND[4] EXT_INT33_PEND[3] EXT_INT33_PEND[2] EXT_INT33_PEND[1] EXT_INT33_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RWX RWX RWX RWX RWX RWX RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs 4.3.5.59 EXT_INT34_PEND  Base Address: 0x106E_0000  Address = Base Address + 0x0A10, Reset Value = 0x0000_0000 Name RSVD EXT_INT34_PEND[1] EXT_INT34_PEND[0] Bit [31:2] [1] [0] Type – RWX RWX Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x00000000 0x0 0x0 4-339 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.60 EXT_INT_SERVICE_XC  Base Address: 0x106E_0000  Address = Base Address + 0x0B08, Reset Value = 0x0000_0000 Name RSVD SVC_Group_Num SVC_Num Bit [31:8] [7:3] [2:0] Type RW RW RW Description Reserved EXT_INT Service group number 0x1 = EXT_INT30 0x2 = EXT_INT31 0x3 = EXT_INT32 0x4 = EXT_INT33 0x5 = EXT_INT34 Interrupt number to be serviced Reset Value 0x0000000 0x00 0x0 4.3.5.61 EXT_INT_SERVICE_PEND_XC  Base Address: 0x106E_0000  Address = Base Address + 0x0B0C, Reset Value = 0x0000_0000 Name RSVD SVC_PEND Bit [31:8] [7:0] Type RW RW Description Reserved 0x0 = Not occur 0x1 = Interrupt Occurs Reset Value 0x0000000 0x00 4.3.5.62 EXT_INT_GRPFIXPRI_XC  Base Address: 0x106E_0000  Address = Base Address + 0x0B10, Reset Value = 0x0000_0000 Name RSVD Highest_GRP_NUM Bit [31:4] [3:0] Type – RW Description Reserved Group number of the highest priority when fixed group priority mode: 0 to 4 0x0 = EXT_INT30 0x1 = EXT_INT31 0x2 = EXT_INT32 0x3 = EXT_INT33 0x4 = EXT_INT34 Reset Value 0x0000000 0x00 4-340 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.63 EXT_INT30_FIXPRI  Base Address: 0x106E_0000  Address = Base Address + 0x0B14, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 0 (EXT_INT30) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.5.64 EXT_INT31_FIXPRI  Base Address: 0x106E_0000  Address = Base Address + 0x0B18, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 1 (EXT_INT31) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.5.65 EXT_INT32_FIXPRI  Base Address: 0x106E_0000  Address = Base Address + 0x0B1C, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 2 (EXT_INT32) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-341 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.66 EXT_INT33_FIXPRI  Base Address: 0x106E_0000  Address = Base Address + 0x0B20, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 3 (EXT_INT33) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4.3.5.67 EXT_INT34_FIXPR  Base Address: 0x106E_0000  Address = Base Address + 0x0B24, Reset Value = 0x0000_0000 Name RSVD Highest_EINT_NUM Bit [31:3] [2:0] Type – RW Description Reserved Interrupt number of the highest priority in External Interrupt Group 4 (EXT_INT34) when fixed priority mode: 0 to 7 Reset Value 0x00000000 0x0 4-342 Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control 4.3.5.68 PDNEN  Base Address: 0x106E_0000  Address = Base Address + 0x0F80, Reset Value = 0x00 Name RSVD PDNEN_CFG PDNEN Bit Type Description [7:2] – Reserved [1] RW 0 = Automatically by power down mode 1 = by PDNEN bit Power down mode pad state enable register. 0 = PADs Controlled by normal mode 1 = PADs Controlled by Power Down mode control registers [0] RW This bit is set to "1" automatically when system enters into Power down mode and clears by writing "0" to this bit or cold reset. After wake up from Power down mode, this bit maintains value "1" until writing "0" Reset Value 0x00 0x0 0x0 4-343 Exynos 4412_UM 5 Clock Management Unit 5 Clock Management Unit 5.1 Overview This chapter describes the Clock Management Units (CMUs) of Exynos 4412. CMUs control Phase Locked Loops (PLLs) and generate system clocks for CPU, buses, and function clocks for individual IPs in Exynos 4412. They also communicate with the power management unit (PMU) in order to stop clocks before entering certain low power mode to reduce power consumption by minimizing clock toggling. Table 5-1 describes the typical operating frequencies for each function block in Exynos 4412. Table 5-1 Operating Frequencies in Exynos 4412 Function Block CPU DMC SSS LEFTBUS RIGHTBUS G3D MFC IMAGE LCD0 ISP CAM TV FSYS GPS MAUDIO PERI-L PERI-R Description Cortex-A9 MPCore It is a Quad Core processor. CoreSight DMC, 2D Graphics Engine Security Sub-System Data Bus/Peripheral Bus Data Bus/Peripheral Bus 3D Graphics Engine Multi-format Codec Rotator, MDMA FIMD0, MIE0, MIPI DSI0 ISP FIMC0, FIMC1, FIMC2, FIMC3 JPEG VP, MIXER, TVENC USB, PCIe, SDMMC, TSI, OneNANDC, SROMC, PDMA0, PDMA1, NFCON, MIPI-HIS, ADC GPS AudioSS, iROM, iRAM UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF, SECKEY, TZPC Typical Operating Frequency 200 MHz to 1.4 GHz 200 MHz/100 MHz 400 MHz (up to 200MHz for G2D) 200 MHz 200 MHz/100 MHz 200 MHz/100 MHz 440 MHz 200 MHz 200 MHz 160 MHz 160 MHz 160 MHz 160 MHz 133 MHz 133 MHz 192 MHz 100 MHz 100 MHz NOTE: Refer to Audio SubsystemChapter for more details on MAUDIO block clocks. 5-1 Exynos 4412_UM 5 Clock Management Unit 5.2 Clock Declaration The top-level clocks in Exynos 4412 are:  Clocks from clock pads, namely, XRTCXTI, XXTI, and XUSBXTI.  Clocks from CMUs For instance, ARMCLK, ACLK, HCLK, and SCLK ARMCLK specifies clock for Cortex-A9 MPCore (up to 800 MHz @ 1.0 V, 1 GHz @ 1.1 V). ACLK, HCLK, PCLK specify bus clocks. SCLK (Special clock) specifies all clocks except bus clocks and processor core clock.  Clocks from USB PHY  Clocks from HDMI_PHY  Clocks from GPIO pads 5.2.1 Clocks from Clock Pads The clock pads derive the clocks. They are:  XRTCXTI: Specifies the clock generated from the crystal pad of 32.768 KHz with XRTCXTI and XRTCXTO pins. XRTCXTI and XRTCXTO are the two pins of crystal pad. RTC uses this clock as a source to the realtime clock. It requires a parallel resistance of 10 M between the XUSBXTI and XUSBXTO pins.  XXTI: Specifies the clock from external oscillator with XXTI pins. The input frequency ranges from 12 to 50 MHz. When XXTI is not used, it should be pulled-down.  XUSBXTI: Specifies the clock from crystal pad with XUSBXTI and XUSBXTO pins. XUSBXTI and XUSBXTO use wide-range OSC pads. This clock is supplied to the USB PHY and the phase locked loops, namely, APLL, MPLL, VPLL, and EPLL. Refer to Chapter 36 USB HOST and Chapter 37 USB DEVICE, for more information. We recommend using a 24 MHz crystal as the iROM design is based on the 24 MHz input clock. It requires parallel resistance of 5 M between the XUSBXTI and XUSBXTO pins. 5-2 Exynos 4412_UM 5 Clock Management Unit 5.2.2 Clocks from CMU CMUs generate internal clocks with intermediate frequencies using from clocks from the clock pads. They are:  Clock pads, namely, XRTCXTI, XXTI, and XUSBXTI  Four PLLs, namely, APLL, MPLL, EPLL, and VPLL  USB PHY and HDMI PHY Some of these clocks are selected, pre-scaled, and provided to the corresponding modules. We recommend using 24 MHz input clock source for APLL, MPLL, EPLL, and VPLL. The components to generate internal clocks are:  APLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz.  MPLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz.  EPLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz. This PLL generates a 192 MHz clock for the Audio Sub-system. It divides EPLL output to generate 24 MHz SLIMbus clock.  VPLL uses FINPLL or SCLK_HDMI24M as input to generate frequencies from 22 to 1400 MHz. This PLL generates 54 MHz video clock or G3D clock.  USB Device PHY uses XUSBXTI to generate frequencies of 30 and 48 MHz.  HDMI PHY uses XUSBXTI to generate 54 MHz. In typical Exynos 4412 applications,  Cortex-A9 MPCore, CoreSight, and HPM use APLL.  DRAM, system bus clocks, and other peripheral clocks like audio IPs, and SPI use MPLL and EPLL.  Video clock uses VPLL.  G3D uses MPLL or VPLL as input clock source. Clock controllers allow bypassing of PLLs for low frequency clock. They also provide clock gating to each block, thereby reducing power consumption. 5-3 Exynos 4412_UM 5 Clock Management Unit 5.3 Clock Relationship The clock relationship between various clocks are:  CPU_BLK clocks  freq (ARMCLK)  freq (ACLK_COREM0)  freq (ACLK_COREM1)  freq (PERIPHCLK)  freq (ATCLK)  freq (PCLK_DBG)  DMC_BLK clocks = freq (MOUTCORE)/n, where n = 1 to 16 = freq (ARMCLK)/n, where n = 1 to 8 = freq (ARMCLK)/n, where n = 1 to 8 = freq (ARMCLK)/n, where n = 1 to 8 = freq (MOUTCORE)/n, where n = 1 to 8 = freq (ATCLK)/n, where n = 1 to 8  freq (SCLK_DMC)  freq (ACLK_DMCD)  freq (ACLK_DMCP)  freq (ACLK_ACP)  freq (PCLK_ACP) = freq (MOUTDMC_BUS)/n, where n = 1 to 8 = freq (SCLK_DMC)/n, where n = 1 to 8 = freq (ACLK_DMCD)/n, where n = 1 to 8 = freq (MOUTDMC_BUS)/n, where n = 1 to 8 = freq (ACLK_ACP)/n, where n = 1 to 8  freq (SCLK_C2C)  freq (ACLK_C2C)  LEFTBUS_BLK clocks = freq (MOUTC2C)/n, where n = 1 to 8 = freq (SCLK_C2C)/n, where n = 1 to 8  freq (ACLK_GDL)  freq (ACLK_GPL) = freq (MOUTGDL)/n, where n = 1 to 8 = freq (ACLK_GDL)/n, where n = 1 to 8  RIGHTBUS_BLK clocks  freq (ACLK_GDR)  freq (ACLK_GPR)  CMU_TOP clocks = freq (MOUTGDR)/n, where n = 1 to 8 = freq (ACLK_GDR)/n, where n = 1 to 8  freq (ACLK_400_MCUISP  freq (ACLK_200)  freq (ACLK_100)  freq (ACLK_160)  freq (ACLK_133)  freq (SCLK_ONENAND)  MAUDIO_BLK clocks = freq (MOUTACLK_400_mcuisp)/n, where n = 1 to 8 = freq (MOUTACLK_200)/n, where n = 1 to 8 = freq (MOUTACLK_100)/n, where n = 1 to 16 = freq (MOUTACLK_160)/n, where n = 1 to 8 = freq (MOUTACLK_133)/n, where n = 1 to 8 = freq (MOUTONENAND)/n, where n = 1 to 8  freq (RP_CLK) = freq (MOUTASS)/n, where n = 1 to 16  freq (BUS_CLK) = freq (MOUTRP)/n, where n = 1 to 16 NOTE: Figure 5-3 of Chapter 39 Audio Subsystem illustrates the clock names including iROM/iRAM and clock tree diagram of MAUDIO_BLK. Caution: Ensure that the ratio between the SCLK_DMC and ACLK_DMCD frequency should be 2:1 or 1:1 always. Do not change this ratio during the running state of DMC. You should also ensure that the ratio between the SCLK_C2C and ACLK_C2C frequency should be 2:1. You should not change this ratio during the running state of C2C. 5-4 Exynos 4412_UM 5 Clock Management Unit The values for high-performance operation are:  freq (ARMCLK)  freq (ACLK_COREM0)  freq (ACLK_COREM1)  freq (PERIPHCLK)  freq (ATCLK)  freq (PCLK_DBG)  freq (SCLK_DMC)  freq (ACLK_DMCD)  freq (ACLK_DMCP)  freq (ACLK_ACP)  freq (PCLK_ACP)  freq (SCLK_C2C)  freq (ACLK_C2C)  freq (ACLK_GDL)  freq (ACLK_GPL)  freq (ACLK_GDR)  freq (ACLK_GPR)  freq (ACLK_400_MCUISP)  freq (ACLK_200)  freq (ACLK_100)  freq (ACLK_160)  freq (ACLK_133)  freq (SCLK_ONENAND) = 1400 MHz = 350 MHz = 188 MHz = 1400 MHz = 214 MHz = 107 MHz = 400 MHz = 200 MHz = 100 MHz = 200 MHz = 100 MHz = 400 MHz = 200 MHz = 200 MHz = 100 MHz = 200 MHz = 100 MHz = 400 MHz = 160 MHz = 100 MHz = 160 MHz = 133 MHz = 160 MHz The PLL operations are:  APLL mainly drives the CPU_BLK clocks. It generates frequencies up to 1.4 GHz with a duty ratio of 49:51. APLL also generates DMC_BLK, LEFTBUS_BLK, RIGHTBUS_BLK, and CMU_TOP clocks as supplement of MPLL.  MPLL mainly drives the DMC_BLK, LEFTBUS_BLK, RIGHTBUS_BLK, and CMU_TOP clocks. It generates frequencies up to 1 GHz with a duty ratio of 49:51. MPLL also generates CPU_BLK clocks when it blocks APLL for locking during the Dynamic Voltage Frequency Scaling (DVFS).  EPLL mainly generates an audio clock.  VPLL mainly generates video system operating clock of 54 MHz, or a G3D clock, or 440 MHz clock at 1.1 V. 5-5 Exynos 4412_UM 5 Clock Management Unit 5.3.1 Recommended PLL PMS Value for APLL and MPLL Table 5-2 describes the recommended PLL PMS value for APLL and MPLL. Table 5-2 APLL and MPLL PMS Value FIN (MHz) Target FOUT (MHz) P M S FOUT (MHz) 24 200 3 100 2 200 24 300 4 200 2 300 24 400 3 100 1 400 24 500 3 125 1 500 24 600 4 200 1 600 24 700 3 175 1 700 24 800 3 100 0 800 24 900 4 150 0 900 24 1000 3 125 0 1000 24 1100 6 275 0 1100 24 1200 4 200 0 1200 24 1300 6 325 0 1300 24 1400 3 175 0 1400 NOTE: Although there is an equation for choosing PMS values, we strongly recommend only the values in the above table. If you have to use other values, please contact us. 5-6 Exynos 4412_UM 5 Clock Management Unit 5.3.2 Recommended PLL PMS Value for EPLL Table 5-3 describes the recommended PLL PMS value for EPLL. Table 5-3 EPLL PMS Value FIN (MHz) 24 24 24 24 24 24 24 24 24 Target FOUT (MHz) P M S 90 2 60 3 180 2 60 2 180.6 3 90 2 180.6336 3 90 2 192 2 64 2 200 3 100 2 400 3 100 1 408 2 68 1 416 3 104 1 K 0 0 19661 20762 0 0 0 0 0 FOUT (MHz) 90 180 108.6 180.6336 192 200 400 408 416 NOTE: 1. K value description "Positive value (Negative value)": Positive values is that you should write to EPLLCON/VPLLCON register. Negative value is that you can calculate PLL output frequency with it. 2. Although there is an equation for choosing PMS values, we strongly recommend only the values in the above table. If you have to use other values, please contact us. 5-7 Exynos 4412_UM 5 Clock Management Unit 5.3.3 Recommended PLL PMS Value for VPLL Table 5-4 describes the recommended PLL PMS value for VPLL. Table 5-4 VPLL PMS Value FIN (MHz) Target FOUT (MHz) P M S 100 3 100 3 160 3 160 3 24 266 3 133 2 350 3 175 2 440 3 110 1 K MFR MRR SSCG_EN 0   0 0   0 0   0 0 – – 0 0 – – 0 NOTE: 1. Although there is an equation for choosing PMS values, we strongly recommend only the values in the above table. If you have to use other values, please contact us. 2. K value description "Positive value (Negative value)": Positive values is that you should write to EPLLCON/VPLLCON register. Negative value is that you can calculate PLL output frequency with it. 5-8 Exynos 4412_UM 5 Clock Management Unit 5.4 Clock Generation Figure 5-1 and Figure 5-2, illustrates the block diagram of the clock generation logic. The clock generator consists of an external crystal clock that is connected to the oscillation amplifier. The PLL converts the incoming low frequency to a high frequency clock that is required by the Exynos 4412. The clock generator also includes a builtin logic to stabilize the clock frequency for each system reset. The clock requires a specified time for stabilization. Figure 5-1 and Figure 5-2 illustrates the two types of clock MUX. Clock MUX in grey color represents glitch-free clock MUX that is free of glitches while changing the clock selection. Clock MUX in white color represents nonglitch-free clock MUX that can suffer from glitches while changing the clock sources. You have to be careful while using each clock MUX. For glitch-free MUX, you should ensure that all clock sources are running while changing the clock selection. If not, it implies that the clock selection process is not complete and it results in clock output having unknown states. The clock MUX status registers are identified with a keyword that starts with CLK_MUX_STAT For non-glitch-free clock MUX, glitches may occur while changing the clock selection. To prevent glitch signals, we recommend disabling the output of a non-glitch-free MUX before any change of clock selection. After completing the clock change, you can re-enable the output of the non-glitch-free clock MUX. This is done to ensure that there are no glitches resulting due to the clock change selection. The outputs of non-glitch-free MUXES are masked by the clock source mask control registers. The clock source mask control registers are identified with a keyword that starts with CLK_SRC_MASK. Figure 5-1 and Figure 5-2 illustrates a clock divider that indicates possible dividing value in parentheses. The dividing values can be changed by clock divider registers during run-time. Some clock dividers have only one dividing value and you are not allowed to change the dividing value. Figure 5-1 illustrates the Exynos 4412 Clock Generation Circuit (CPU, BUS, DRAM, and ISP Clocks) diagram. Figure 5-2 illustrates the Exynos 4412 Clock Generation Circuit (Special Clocks) diagram. 5-9 Exynos 4412_UM 5 Clock Management Unit 0 glitch-free 0 1 mux 1 normal mux See 23) for more details on mux type Since APLL output is a very fast clock, clock gating cell is added not to let it toggle when it is not used CMU_CPU synchronous clocks SCLK_APLL ARMCLK XXTI 0 1 FINPLL APLL FOUTAPLL MUXAPLL 0 C 1 MOUTAPLL DIVAPLL (1~8) SCLKAPLL MUXCORE 0 C 1 DIVCORE (1~8) DIVCORE2 (1~8) MOUTCORE clock stop request upon ARM reset/isolation DIVCOREM0 (1~8) DIVCORES (1~8) DIVCOREM1 (1~8) DIVPERIPH (1~8) Voltage domain crossing Paired inverters are added before/after the line MOUTAPLL MUXMPLL_CTRL_USER_C 0 SCLKMPLL 1 DIVATB C (1~8) MU0 XHPM 1 DIVCOPY (1~8) MOUTHPM SCLKMPLL_USER_C C DOUTCOPY DIVPCLK_DBG (1~8) DIVHPM (1~8) ACLK_COREM0 ACLK_CORES ACLK_COREM1 PERIPHCLK ATCLK PCLK_DBG SCLK_HPM synchronous clocks SCLK_HPM PERIPHCLK C TRACECLK C CTMCLK C HCLK_CSSYS ATCLK PCLK_DBG C TSVALUECLK XusbXTI XOM[0] XXTI27 MPLL FINPLL CMU_DMC DIVC2C_ACLK (1~8) ACLK_C2C synchronous clocks ACLK_C2C CLKEN_C2C SCLKMPLL SCLKAPLL MUXC2C 0 1 MOUTC2C SCLKMPLL SCLKAPLL MUXDMC_BUS 0 1 MUXMPLL 0 C MOUTMPLL SCLKMPLL FOUTMP1LL MOUTDMC_BUS SCLKMPLL SCLKAPLL ACLK_DMCP PCLK_IEM_IEC DIVC2C C (1~8) DIVDMC C (1~8) DIVDMCD (1~8) DIVACP C (1~8) 0MUXDPHY PHY DLL clock DIVDPHY C 1 (1~8) MOUTDPHY DIVDPM (1~128) DIVDMCP (1~8) DIVACP_PCLK (1~8) SCLK_DPHY IECDPMCLKEN SCLK_C2C SCLK_DMC ACLK_DMCD synchronous clocks ACLK_DMCP ACLK_ACP PCLK_ACP synchronous clocks C SCLK_DPHY1_GATED(3) C SCLK_DPHY0_GATED(2) XXTI XusbXTI SCLK_HDMI27M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL SCLKEPLL SCLKVPLL DIVDVSEM (1~128) MUXPWI MOUTPWI IECDVSEMCLKEN gated when IEM_IEC clocks are turned off DIVPWI (1~16) C SCLK_PWI SCLKMPLL SCLKAPLL SCLKEPLL SCLKVPLL MUXG2D_ACP_0 0 1 MUXG2D_ACP 0 MOUTG2D_ACP_0 MUXG2D_ACP_1 1 0 MOUTG2D_ACP 1 MOUTG2D_ACP_1 DIVG2D_ACP C (1~16) SCLK_G2D_ACP CMU_TOP SCLKMPLL_USER_T MUXMPLL_CTRL_USER_T 0 SCLKMPLL 1 SCLKAPLL EPLL MUXEPLL 0 C 1 SCLKEPLL VPLL FOUTEPLL MUXVPLL 0 C 1 SCLKVPLL FOUTVPLL USB_PHY SCLK_USBPHY0 MIPI_PHY HDMI_PHY SCLK_HDMIPHY SCLK_HDMI24M MUXACLK_400_MC 0 UISP 1 DIVACLK_400_MC UISP C (1~8) MOUTACLK_400_MC MUXACLK_U2I0S0P 0 DIVACLK_200 C 1 (1~8) FINPLL MUXUSER_MUX_ACLK_400_MCUISP 0 ACLK_400_MCUISP 1 to MCUISP FINPLL MUXUSER_MUX_ACLK_200 0 ACLK_200 1 to ISP MOUTACLK_200 MUXACLK_266_GPS 0 B4 DIVACLK_266_GPS C 1 (1~8) FINPLL MUXUSER_MUX_ACLK_266_GPS 0 ACLK_266_GPS 1 to GPS MOUTACLK_266_GPS MUXACLK_100 0 DIVACLK_100 C 1 (1~16) MOUTACLK_100 ACLK_100 to MFC(PCLK), PERIL, PERIR MUXACLK_160 0 DIVACLK_160 C 1 (1~8) ACLK_160 to CAM, TV, LCD0 MOUTACLK_160 MUXACLK_133 0 1 DIVACLK_133 (1~8) MOUTACLK_133 ACLK_133 C MUXONENAND 0 MUXONENAND_1 0 1 DIVONENAND 1 MOUTONENAND (1~8) SCLKVPLL MOUTONENAND_1 SCLK_ONENAND to FSYS EBI 5-10 Exynos 4412_UM ACLK_GDL is also used for G3D ACLK for synchronization CMU_LEFTBUS MUXmpll_ctrl_user_L FINPLL 0 SCLKMPLL 1 SCLKAPLL MUXGDL 0 1 MOUTGDL DIVGDL (1~8) DIVGPL (1~8) ACLK_GDL ACLK_GPL synchronous clocks 5 Clock Management Unit MUXmpll_ctrl_user_R FINPLL 0 CMU_RIGHTBUS SCLKMPLL 1 SCLKAPLL MUXGDR 0 1 MOUTGDR DIVGDR (1~8) DIVGPR (1~8) ACLK_GDR ACLK_GPR synchronous clocks CMU_ISP synchronous clocks ACLK_400_MCUISP DIVMCUISPDIV0 (1~8) DIVMCUISPDIV1 (1~8) ACLK_400_MUXED ACLK_MCUISP_DIV0 ACLK_MCUISP_DIV1 synchronous clocks ACLK_200_MUXED ACLK_MCUISP ATCLK_MCUISP PCLKDBG_MCUISP ACLK_AXI_200 ACLK_200 DIVISPDIV0 (1~8) ACLK_DIV0 ACLK_AXI_DIV0 DIVISPDIV1 (1~8) ACLK_DIV1 DIVmpwmdiv (1~8) ACLK_DIV2 HCLK_AXI_DIV1 SCLK_MPWM_ISP Figure 5-1 Exynos 4412 Clock Generation Circuit (CPU, BUS, DRAM, ISP Clocks) 5-11 Exynos 4412_UM 5 Clock Management Unit CAM_BLK SCLKMPLL_USER_T SCLKAPLL SCLKEPLL SCLKVPLL MUXJPEG_0 0 1 MOUTJPEG_0 MUXJPEG_1 0 MUXJPEG 0 1 MOUTJPEG 1 MOUTJPEG_1 DIVJPEG (1~16) C ACLK_JPEG XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL MUXCSIS0,1 DIVCSIS0,1 MOUTCSIS0,1 (1~16) SCLK_CSIS0,1 MUXCAM0,1 DIVCAM0,1 MOUTCAM0,1 (1~16) SCLK_CAM0,1_GATED (PAD) MUXFIMC0~3_LCLK DIVFIMC0~3_LCLK (1~16) MOUTFIMC0~3_LCLK SCLK_FIMC0~3_LCLK PERIL_BLK XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL SCLKEPLL AUDIOCDCLK1 1'b0 SCLK_HDMI24M SCLK_USBPHY0 XXTI XusbXTI SCLKMPLL_USER_T SCLKEPLL SCLKVPLL AUDIOCDCLK2 1'b0 SCLK_HDMI24M SCLK_USBPHY0 XXTI XusbXTI SCLKMPLL_USER_T SCLKEPLL SCLKVPLL SCLK_AUDIO1~2 MUXSPI0~2 DIVSPI0~2 (1~16) MOUTSPI0~2 DIVSPI0~2_PRE (1~256) SCLK_SPI0~2 MUXUART0~4 DIVUART0~4 MOUTUART0~4 (1~16) SCLK_UART0~4 DIVSLIMBUS (1~16) MUXAUDIO1 DIVAUDIO1 B MOUTAUDIO1 (1~16) SCLK_SLIMBUS SCLK_AUDIO1 MUXAUDIO2 DIVAUDIO2 MOUTAUDIO2 (1~16) DIVPCM1~2 (1~256) SCLK_AUDIO2 SCLK_PCM1~2 SCLK_AUDIO1~2 DIVI2S1~2 (1~64) SCLK_I2S1~2 SCLK_AUDIO0 SCLK_AUDIO1 SCLK_AUDIO2 SPDIF_EXTCLK MUXSPDIF SCLK_SPDIF XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL LCD0_BLK SCLK_FIMC0~3_LCLK FIMD0 MUXFIMD0 MOUTFIMD0 DIVFIMD0 (1~16) SCLK_FIMD0 MUXMDNIE0 DIVMDNIE0 MOUTMDNIE0 (1~16) SCLK_MDNIE0 MUXMDNIE_PWM0 DIVMDNIE _PWM0 (1~16) DIVMDNIE_P WM0_PRE (1~16) SCLK_MDNIE_PWM0 MOUTMDNIE_PWM0 MUXMIPI0 SCLK_MIPIDPHY4L_GATED DIVMIPI0 (1~16) DIVMIPI0_PRE (1~16) SCLK_MIPI0 MOUTMIPI0 ISP_BLK XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI24M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL MUXPWM_ISP DIVPWM_ISP (1~16) C MOUTPWM_ISP SCLK_PWM_ISP MUXSPI0~2 DIVSPI0_ISP (1~16) C DIVSPI0_ISP_PRE SCLK_SPI0_ISP (1~256) MOUTSPI0~2 MUXSPI1_ISP DIVSPI1_ISP C (1~16) DIVSPI1_ISP_PRE (1~256) SCLK_SPI1_ISP MOUTSPI1_ISP MUXUART_ISP DIVUART_ISP (1~16) C MOUTUART_ISP SCLK_UART_ISP OSCCLK RTC_CLK ALIVE_WRAP OSCCLK_MTCADC CRYCLK_MTCADC_ISP RTC_CLK_OUT__MTCADC RTCCLK_MTCADC_ISP 5-12 Exynos 4412_UM 5 Clock Management Unit SCLKMPLL_USER_T SCLKAPLL SCLKEPLL SCLKVPLL MFC_BLK MUXMFC_0 0 1 MOUTMFC_0 MUXMFC_1 0 MUXMFC 0 1 MOUTMFC DIVMFC (1~16) 1 MOUTMFC_1 G3D_BLK SCLKMPLL_USER_T SCLKAPLL SCLKEPLL SCLKVPLL MUXG3D_0 0 1 MOUTG3D_0 MUXG3D_1 0 MUXG3D 0 1 MOUTG3D 1 MOUTG3D_1 DIVG3D (1~16) TV_BLK SCLK_MFC SCLK_G3D SCLKVPLL SCLK_HDMIPHY DIVTV_BLK (1~16) 0 SCLK_HDMI 1 MUXHDMI SCLK_PIXEL_GATED AUDIOCDCLK0 1'b0 SCLK_HDMI27M SCLK_USBPHY0 XXTI XusbXTI SCLKMPLL_USER_T SCLKEPLL SCLKVPLL MAUDIO_BLK MUXAUDIO0 DIVAUDIO0 MOUTAUDIO0 (1~16) DIVPCM0 (1~256) SCLK_AUDIO0 SCLK_PCM0 FSYS_BLK XXTI XusbXTI SCLK_HDMI27M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL XXTI XusbXTI SCLK_HDMI27M SCLK_USBPHY0 SCLK_HDMIPHY SCLKMPLL_USER_T SCLKEPLL SCLKVPLL MUXMMC0~3 DIVMMC0~3 (1~16) MOUTMMC0~3 DIVMMC0~3_PRE (1~256) SCLK_MMC0~3 MUXMMC4 DIVMMC4 (1~16) MOUTMMC0~4 DIVMMC4_PRE (1~256) SCLK_MMC4 SCLKMPLL_USER SCLKAPLL MUXMIPIHSI 0 1 DIVMIPIHSI C (1~16) SCLK_MIPIHSI MOUTMIPIHSI SCLK_MIPIHSI clock frequency is fixed at 200MHz. So the glitch-free mux is not used. Figure 5-2 Exynos 4412 Clock Generation Circuit (Special Clocks) NOTE: The SCLKuser_mpll In Figure 5-2 means SCLKuser_mpll_T. Caution: In Figure 5-1 and Figure 5-2, the MUX's with grey color are glitch-free. For glitch-free clock MUX, ensure that all clock sources are running while changing the clock selection. For clock dividers, ensure that input clock is running while changing the divider value. 5-13 Exynos 4412_UM 5 Clock Management Unit 5.5 Clock Configuration Procedure The rules for changing the clock configuration are:  All inputs of a glitch-free MUX should run.  When a PLL is turned OFF, you should not select the output of PLL. The basic SFR configuration requires change in system clock divider values that are:  CLK_DIV_CPU0[31:0] = target value0  CLK_DIV_DMC0[31:0] = target value1  CLK_DIV_TOP[31:0] = target value2  CLK_DIV_LEFTBUS[31:0] = target value3  CLK_DIV_RIGHTBUS[31:0] = target value4 Change the divider values for special clocks by setting CLK_DIV_XXX SFRs in CMU_TOP  CLK_DIV_XXX[31:0] = target value The following sequence shows turn on PLL procedure. Change PLL PMS values Set PMS values; // Set PDIV, MDIV, and SDIV values (Refer to (A, M, E, V) PLL_CON0 SFRs) Change other PLL control values (A, M, E, V)PLL_CON1[31:0] = target value; // Set K, AFC, MRR, MFR values if necessary (Refer to (A, M, E, V)PLL_CON1 SFRs) Turn on a PLL (A, M, E, V)PLL_CON0[31] = 1; // Turn on a PLL (Refer to (A, M, E, V)PLL_CON0 SFRs) wait_lock_time; // Wait until the PLL is locked MUX_(A, M, E, V)PLL_SEL = 1; // Select the PLL output clock instead of input reference clock, after PLL output clock is stabilized. (Refer to CLK_SRC_CPU SFR for APLL and MPLL, CLK_SRC_TOP0 for EPLL and VPLL) Once a PLL is turned on, do not turn it off. 5-14 Exynos 4412_UM 5 Clock Management Unit 5.5.1 Clock Gating Exynos 4412 can disable the clock operation of each IP, if it does not require. This reduces the dynamic power consumption. The two types of clock gating control register to disable or enable clock operations are:  Clock gating control register for function blocks  Clock gating control register for IP The two clock gating control registers are ANDed to generate the final clock gating enable signal. As a result, if it turns OFF either of the two registers filed, then the resulting clock will stop. For example, to stop the clocks provided to the Mixer module, you should set the CLK_MIXER field in CLK_GATE_IP_TV register to 0 or CLK_TV field in CLK_GATE_BLOCK register to 0. For latter case, all clocks in TV block, not only MIXER clocks, are turned off. Caution: Ensure that the software does not access the IPs whose clock is gated, as it may cause system failure. 5.5.2 Clock Diving Whenever clock divider control register is changed, it is recommended to check clock divider status registers before using the new clock output. This guarantees the corresponding divider finishes changing to a new dividing value before its output is used by other modules. 5-15 Exynos 4412_UM 5.6 Special Clock Description Special Clock Description section describes special clock in Exynos 4412. 5 Clock Management Unit 5.6.1 Special Clock Table Table 5-5 describes the special clocks in Exynos 4412. Name SCLK_ONENAND Table 5-5 Special Clocks in Exynos 4412 Description Range ONENAND operating clock 160 MHz SCLK_G3D G3D core operating clock 440 MHz SCLK_G2D G2D core operating clock 200 MHz SCLK_MFC MFC core operating clock 200 MHz SCLK_CAM0, SCLK_CAM1 SCLK_CSIS0, SCLK_CSIS1 SCLK_FIMC_LCLK0, SCLK_FIMC_LCLK1, SCLK_FIMC_LCLK2, SCLK_FIMC_LCLK3 SCLK_FIMD0 SCLK_MDNIE0 SCLK_MDNIE_PWM0 SCLK_MIPI0 SCLK_MIPIDPHY4L SCLK_HDMI SCLK_PIXEL Reference clock for external CAM device CSIS operating clock FIMC core operating clock FIMD operating clock MDNIE operating clock MDNIE PWM clock MIPI DSIM clock MIPI DPHY 4 Lane clock HDMI LINK clock HDMI PIXEL clock Range varies in accordance to the CAM specifications. 160 MHz 160 MHz 100 MHz 100 MHz 100 MHz 100 MHz 800 MHz 148.5 MHz 148.5 MHz SCLK_SPDIF SPDIF operating clock 83 MHz SCLK_MMC0, SCLK_MMC1, SCLK_MMC2, SCLK_MMC3, SCLK_MMC4 SCLK_USBPHY0 HSMMC operating clock 50 MHz USB device clock 48 MHz Source ACLK_160, ACLK_133 SCLKAPLL, SCLKMPLL, SCLKEPLL, SCLKVPLL SCLKAPLL, SCLKMPLL, SCLKEPLL, SCLKVPLL SCLKAPLL, SCLKMPLL, SCLKEPLL, SCLKVPLL All possible clock sources All possible clock sources All possible clock sources All possible clock sources All possible clock sources All possible clock sources All possible clock sources All possible clock sources All possible clock sources All possible clock sources SCLK_AUDIO0, SCLK_AUDIO1, SCLK_AUDIO2 All possible clock sources USB Device PHY clock out 5-16 Exynos 4412_UM Name SCLK_AUDIO0, SCLK_AUDIO1, SCLK_AUDIO2 Description AUDIO operating clock (I2S) Range 100 MHz SCLK_PCM0, AUDIO operating clock SCLK_PCM1, SCLK_PCM2 (PCM) 5 MHz SCLK_PWI SCLK_KEY SCLK_SPI0, SCLK_SPI1, SCLK_SPI2 SCLK_UART0, SCLK_UART1, SCLK_UART2, SCLK_UART3, SCLK_UART4 SCLK_SLIMBUS IEM APC operating clock KEY I/F or TSADC filter clock (fixed clock) SPI operating clock UART operating clock SLIMBUS clock 6 to 30 MHz 24 MHz 100 MHz 200 MHz 25 MHz ACLK_JPEG JPEG core operating clock 160 MHz SCLK_PWM_ISP SCLK_SPI0_ISP SCLK_SPI1_ISP SCLK_UART_ISP SCLK_MIPIHSI PWM_ISP operating clock SPI0_ISP operating clock SPI1_ISP operating clock UART_ISP operating clock MIPIHSI core operating clock 66 MHz 100 MHz 100 MHz 66 MHz 200 MHz 5 Clock Management Unit Source All possible clock sources, AUDIOCDCLKx SCLK_AUDIO0, SCLK_AUDIO1, SCLK_AUDIO2 All possible clock sources XXTI, XUSBXTI All possible clock sources All possible clock sources SCLKEPLL SCLKAPLL, SCLKMPLL, SCLKEPLL, SCLKVPLL All possible clock sources All possible clock sources All possible clock sources All possible clock sources SCLKAPLL, SCLKMPLL, 5-17 Exynos 4412_UM 5 Clock Management Unit  All possible clock sources include XXTI, XUSBXTI, SCLK_HDMI24M, SCLK_USBPHY, SCLK_HDMIPHY, SCLKMPLL, SCLKEPLL, and SCLKVPLL.  XXTI and XUSBXTI refer to external crystal.  SCLK_USBPHY refers to USB PHY 48 MHz output clock.  SCLK_HDMI24M refers to HDMI PHY (24 MHz reference clock for XUSBXTI) output.  SCLK_HDMIPHY refers to HDMI PHY (PIXEL_CLKO) output clock.  SCLKMPLL, SCLKEPLL, and SCLKVPLL refer to the output clock of MPLL, EPLL, and VPLL, respectively. Table 5-6 describes the I/O clocks in Exynos 4412. Table 5-6 I/O Clocks in Exynos 4412 Name IOCLK_AC97 IOCLK_I2S0, IOCLK_I2S1, IOCLK_I2S2 IOCLK_PCM0, IOCLK_PCM1, IOCLK_PCM2 IOCLK_SPDIF I/O Pad Input Xi2s1SCLK Input Xi2s0CDCLK Xi2s1CDCLK Xpcm2EXTCLK Input Xi2s0CDCLK Xi2s1CDCLK Xpcm2EXTCLK Input Xpcm2EXTCLK GPIO Function Func2: AC97BITCLK Func0: I2S_0_CDCLK Func0: I2S_1_CDCLK Func2: I2S_2_CDCLK Func1: PCM_0_EXTCLK Func1: PCM_1_EXTCLK Func0: PCM_2_EXTCLK Func1: SPDIF_EXTCLK Range 12.288 MHz 83.4 MHz 83.4 MHz 36.864 MHz Description AC97 Bit Clock I2S CODEC Clock PCM CODEC Clock SPDIF Input Clock 5-18 Exynos 4412_UM 5 Clock Management Unit 5.7 CLKOUT You can use the XCLKOUT port to monitor certain clocks in Exynos 4412. The six CMUs in Exynos 4412 contain the CLKOUT control logic. If necessary, you can select and divide one of the clocks in the CMU. It generates CLKOUT signal from each CMU and feeds this into the power management unit. It is then muxed with CLKOUT signals and XXTI, XUSBXTI, RTC_TICK_SRC, and RTCCLK. Figure 5-3 illustrates the CLKOUT control logic in Exynos 4412 . CMU_DMC DIV (1~64) CMU_TOP DIV (1~64) CMU_LEFTBUS DIV (1~64) CMU_RIGHTBUS DIV (1~64) CMU_CPU DIV (1~64) CMU_ISP DIV (1~64) PMU XCLKOUT XXTI XUSBXTI RTC_TICK_SRC RTCCLK Figure 5-3 Exynos 4412 CLKOUT Control Logic 5-19 Exynos 4412_UM 5 Clock Management Unit Table 5-7 describes the CLKOUT input clock selection information. Table 5-7 CLKOUT Input Clock Selection Information No. CMU_CPU CMU_DMC CMU_TOP CMU_RIGHTBUS CMU_LEFTBUS CMU_ISP PMU 0 APLL_ ACLK_DMCD EPLL_FOUT SCLK_MPLL/2 SCLK_MPLL/2 ACLK_ FOUT/2 MCUISP CMU_ DMC 1 Reserved ACLK_DMCP VPLL_FOUT SCLK_APLL/2 SCLK_APLL/2 PCLKDBG _MCUISP CMU_ TOP 2 Reserved ACLK_ACP SCLK_ HDMI24M ACLK_GDR ACLK_GDL ACLK_DIV0 CMU_ LEFTBUS 3 Reserved PCLK_ACP SCLK_ USBPHY0 ACLK_GPR ACLK_GPL ACLK_DIV1 CMU_ RIGHTBUS 4 ARMCLK/2 SCLK_DMC Reserved – – SCLK_ MPWM_ISP CMU_CPU 5 ACLK_ COREM0 SCLK_DPHY SCLK_ HDMIPHY – – – XXTI ACLK_ MPLL_ AUDIOCDC 6 COREM1 FOUT/2 LK0 – – – XUSBXTI ACLK_ AUDIOCDC 7 CORES SCLK_PWI LK1 – RTC_TICK – – _SRC AUDIOCDC 8 ATCLK  LK2 – – – RTCCLK 9 PERIPHCLK SCLK_C2C SPDIF_ – EXTCLK – – – 10 PCLK_ ACLK_C2C ACLK_160 – DBG – – – 11 SCLK_ – ACLK_133 – HPM – – – 12 – – ACLK_200 – – – – 13 – – ACLK_100 – – – – 14 – – SCLK_MFC – – – – 15 – – SCLK_G3D – – – – 16 – – ACLK_400_ MCUISP – – – – 17 – – CAM_A_ PCLK – – – – 18 – CAM_B_ – PCLK – – – – 19 – – S_RXBYTE CLKHS0_2L – – – – 20 – – S_RXBYTE CLKHS0_4L – – – – 21 – – RX_HALF_ – – – – 5-20 Exynos 4412_UM 5 Clock Management Unit No. CMU_CPU 22 – 23 – 24 – 25 – 26 – 27 – 28 – 29 – 30 – 31 – CMU_DMC – – – – – – – – – – CMU_TOP BYTE_CLK_ CSIS0 RX_HALF_ BYTE_CLK_ CSIS1 SCLK_JPE G SCLK_PWM _ISP SCLK_SPI0 _ISP SCLK_SPI1 _ISP SCLK_ UART_ISP SCLK_ MIPIHSI SCLK_HDMI SCLK_ FIMD0 SCLK_ PCM0 CMU_RIGHTBUS – – – – – – – – – – CMU_LEFTBUS – – – – – – – – – – CMU_ISP – – – – – – – – – – PMU – – – – – – – – – – 5-21 Exynos 4412_UM 5 Clock Management Unit 5.8 I/O Description Table 5-8 describes the I/O. Signal XXTI XUSBXTI XUSBXTO EPLLFILTER VPLLFILTER XCLKOUT Table 5-8 I/O Description I/O Input Input Output Input/Output Input/Output Output Description External oscillator pad Input pad for crystal Output pad for crystal Pad for EPLL loop filter capacitance Pad for VPLL loop filter capacitance Clock out pad Pad XXTI XUSBXTI XUSBXTO XEPLLFILTER XVPLLFILTER XCLKOUT Type Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated 5-22 Exynos 4412_UM 5 Clock Management Unit 5.9 Register Description The clock controller controls PLLs and clock generation units. This section describes the usage of Special Functional Registers (SFRs) in the clock controller. Do not change any reserved area. Any change in the reserved area leads to an unexpected behavior. The address map of Exynos 4412 clock controller consists of six CMUs. They are, CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_DMC, CMU_CPU, and CMU_ISP. Each CMU uses an address space of 16 KB for SFRs. The internal structure of address space for each CMU is similar for all CMUs. The six categories into which the address space is divided are:  Use 0x000 to 0x1FF for PLL control : PLL lock time and control  Use 0x200 to 0x4FF for MUX control : MUX selection, output masking, and status  Use 0x500 to 0x6FF for clock division : Divider ratio and status  0x700 to 0x8FF is reserved and you are not allowed to access the region.  Use 0x900 to 0x9FF for clock gating control : Clock gating of IPs and function blocks  Use 0xA00 to 0xAFF for CLKOUT : CLKOUT input clock selection and divider ratio NOTE: The CLK_GATE_IP_XXX registers in the CMU_LEFTBUS and CMU_RIGHTBUS are located at 0x800. Additionally, some CMUs use addresses beyond 0xAFF for other functions such as CPU control functions in CMU_CPU. Refer to register description for more information. 5-23 Exynos 4412_UM 5 Clock Management Unit In Figure 5-4, XXX in the register name shall be replaced with the function block name, i.e., LEFTBUS, RIGHTBUS, TOP, CAM, TV, MFC, G3D, IMAGE, LCD0, LCD1, MAUDIO, FSYS, PERIL, and PERIR. Figure 5-4 illustrates the Exynos 4412 clock controller address map. 0x1003_4000 CMU_LEFTBUS 0x1003_8000 CMU_RIGHTBUS 0x1003_C000 CMU_TOP 0x1004_0000 CMU_DMC 0x1004_4000 CMU_CPU 0x1004_8000 CMU_ISP 0x000 0x100 0x200 0x300 0x400 0x500 0x600 0x700 0x800 0x900 0xA00 xPLL_LOCK xPLL_CON CLK_SRC_XXX CLK_SRC_MASK_XXX CLK_MUX_STAT_XXX CLK_DIV_XXX CLK_DIV_STAT_XXX Reserved Reserved CLK_GATE_IP_XXX CLKOUT_CMU_XXX PLL lock time PLL control Mux selection Mux output masking Mux status Divider ratio Divider status IP clock gating CLKOUT control * XXX : function block name Figure 5-4 Exynos 4412 Clock Controller Address Map 5-24 Exynos 4412_UM 5 Clock Management Unit 5.9.1 Register Map Summary  Base Address: 0x1003_0000 Register CLK_SRC_LEFTBUS RSVD CLK_MUX_STAT_LEFTBUS RSVD CLK_DIV_LEFTBUS RSVD CLK_DIV_STAT_LEFTBUS RSVD CLK_GATE_IP_LEFTBUS RSVD CLK_GATE_IP_IMAGE RSVD CLKOUT_CMU_LEFTBUS CLKOUT_CMU_LEFTBUS_ DIV_STAT RSVD CLK_SRC_RIGHTBUS RSVD CLK_MUX_STAT_RIGHTBUS RSVD Offset 0x4200 0x4204 to 0x43FF 0x4400 0x4404 to 0x44FF 0x4500 0x4504 to 0x45FF 0x4600 0x4604 to 0x47FC 0x4800 0x4804 to 0x492C 0x4930 0x4934 to 0x49FC 0x4A00 0x4A04 0x4A08 to 0x81FF 0x8200 0x8204 to 0x83FF 0x8400 0x8404 to 0x84FF CLK_DIV_RIGHTBUS 0x8500 RSVD CLK_DIV_STAT_RIGHTBUS RSVD CLK_GATE_IP_RIGHTBUS RSVD 0x8504 to 0x85FF 0x8600 0x8604 to 0x87FC 0x8800 0x8804 to Description Selects clock source for CMU_LEFTBUS Reserved Clock MUX status for CMU_LEFTBUS Reserved Sets clock divider ratio for CMU_LEFTBUS Reserved Clock divider status for CMU_LEFTBUS Reserved Control IP clock gating for LEFTBUS_BLK Reserved Control IP clock gating for IMAGE_SS Reserved CLKOUT control register Clock divider status for CLKOUT Reserved Selects clock source for CMU_RIGHTBUS Reserved Clock MUX status for CMU_RIGHTBUS Reserved Sets clock divider ratio for CMU_RIGHTBUS Reserved Clock divider status for CMU_RIGHTBUS Reserved Control IP clock gating for RIGHTBUS_BLK Reserved Reset Value 0x0000_0000 Undefined 0x0000_0011 Undefined 0x0000_0000 Undefined 0x0000_0000 Undefined 0xFFFF_FFFF Undefined 0xFFFF_FFFF Undefined 0x0001_0000 0x0000_0000 Undefined 0x0000_0000 Undefined 0x0000_0011 Undefined 0x0000_0000 Undefined 0x0000_0000 Undefined 0xFFFF_FFFF Undefined 5-25 Exynos 4412_UM 5 Clock Management Unit Register CLK_GATE_IP_PERIR RSVD CLKOUT_CMU_RIGHTBUS CLKOUT_CMU_RIGHTBUS _DIV_STAT RSVD EPLL_LOCK RSVD VPLL_LOCK RSVD EPLL_CON0 EPLL_CON1 EPLL_CON2 RSVD VPLL_CON0 VPLL_CON1 VPLL_CON2 RSVD CLK_SRC_TOP0 CLK_SRC_TOP1 RSVD CLK_SRC_CAM0 CLK_SRC_TV CLK_SRC_MFC CLK_SRC_G3D RSVD CLK_SRC_LCD CLK_SRC_ISP CLK_SRC_MAUDIO CLK_SRC_FSYS RSVD Offset 0x895C 0x8960 0x8964 to 0x89FC 0x8A00 Description Controls IP clock gating for PERIR_S Reserved CLKOUT control register 0x8A04 Clock divider status for CLKOUT 0x8A08 to 0xC00F 0xC010 0xC014 to 0xC01F 0xC020 0xC024 to 0xC10F 0xC110 0xC114 0xC118 0xC11C 0xC120 0xC124 0xC128 0xC12C to 0xC20C 0xC210 0xC214 0xC218 to 0xC21F 0xC220 0xC224 0xC228 0xC22C 0xC230 0xC234 0xC238 0xC23C 0xC240 0xC244 to 0xC24C Reserved Controls PLL locking period for EPLL Reserved Controls PLL locking period for VPLL Reserved Controls PLL output frequency for EPLL Controls PLL output frequency for EPLL Controls PLL output frequency for EPLL Reserved Controls PLL output frequency for VPLL Controls PLL output frequency for VPLL Controls PLL output frequency for VPLL Reserved Selects clock source for CMU_TOP0 Selects clock source for CMU_TOP1 Reserved Selects clock source for CAM_BLK Selects clock source for TV_BLK Selects clock source for MFC_BLK Selects clock source for G3D_BLK Reserved Selects clock source for LCD_BLK Selects clock source for ISP_BLK Selects clock source for AUDIO_BLK Selects clock source for FSYS_BLK Reserved Reset Value 0xFFFF_FFFF Undefined 0x0001_0000 0x0000_0000 Undefined 0x0000_0FFF Undefined 0x0000_0FFF Undefined 0x0060_0302 0x6601_0000 0x0000_0080 Undefined 0x006F_0302 0x6601_6000 0x0000_0080 Undefined 0x0000_0000 0x0000_0000 Undefined 0x1111_1111 0x0000_0000 0x0000_0000 0x0000_0000 Undefined 0x0000_1111 0x0000_1111 0x0000_0005 0x0001_1111 Undefined 5-26 Exynos 4412_UM 5 Clock Management Unit Register CLK_SRC_PERIL0 CLK_SRC_PERIL1 CLK_SRC_CAM1 RSVD CLK_SRC_MASK_CAM0 CLK_SRC_MASK_TV RSVD CLK_SRC_MASK_LCD CLK_SRC_MASK_ISP CLK_SRC_MASK_MAUDIO CLK_SRC_MASK_FSYS RSVD CLK_SRC_MASK_PERIL0 CLK_SRC_MASK_PERIL1 RSVD CLK_MUX_STAT_TOP0 CLK_MUX_STAT_TOP1 RSVD CLK_MUX_STAT_MFC CLK_MUX_STAT_G3D RSVD CLK_MUX_STAT_CAM1 RSVD CLK_DIV_TOP RSVD CLK_DIV_CAM0 CLK_DIV_TV CLK_DIV_MFC CLK_DIV_G3D RSVD CLK_DIV_LCD Offset 0xC250 0xC254 0xC258 0xC25C to 0xC31F 0xC320 0xC324 0xC328 to 0xC333 0xC334 0xC338 0xC33C 0xC340 0xC344 to 0xC34F 0xC350 0xC354 0xC358 to 0xC40F 0xC410 0xC414 0xC418 to 0xC427 0xC428 0xC42C 0xC430 to 0xC454 0xC458 0xC45C to 0xC50C 0xC510 0xC514 to 0xC51F 0xC520 0xC524 0xC528 0xC52C 0xC530 0xC534 Description Selects clock source for connectivity IPs Selects clock source for connectivity IPs Selects clock source for CAM_BLK Reserved Clock source mask for CAM_BLK Clock source mask for TV_BLK Reserved Clock source mask for LCD_BLK Clock source mask for ISP_BLK Clock source mask for AUDIO_BLK Clock source mask for FSYS_BLK Reserved Clock source mask for PERIL_BLK Clock source mask for PERIL_BLK Reserved Clock MUX status for CMU_TOP Clock MUX status for CMU_TOP Reserved Clock MUX status for MFC_BLK Clock MUX status for G3D_BLK Reserved Clock MUX status for CAM_BLK Reserved Sets clock divider ratio for CMU_TOP Reserved Sets clock divider ratio for CAM_BLK Sets clock divider ratio for TV_BLK Sets clock divider ratio for MFC_BLK Sets clock divider ratio for G3D_BLK Reserved Sets clock divider ratio for LCD_BLK Reset Value 0x0001_1111 0x0111_0055 0x0000_0000 Undefined 0x1111_1111 0x0000_0111 Undefined 0x0000_1111 0x0000_1111 0x0000_0001 0x0101_1111 Undefined 0x0001_1111 0x0111_0111 Undefined 0x1111_1111 0x0111_1110 Undefined 0x0000_0111 0x0000_0111 Undefined 0x0000_0111 Undefined 0x0000_0000 Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Undefined 0x0070_0000 5-27 Exynos 4412_UM 5 Clock Management Unit Register CLK_DIV_ISP CLK_DIV_MAUDIO CLK_DIV_FSYS0 CLK_DIV_FSYS1 CLK_DIV_FSYS2 CLK_DIV_FSYS3 CLK_DIV_PERIL0 CLK_DIV_PERIL1 CLK_DIV_PERIL2 CLK_DIV_PERIL3 CLK_DIV_PERIL4 CLK_DIV_PERIL5 CLK_DIV_CAM1 RSVD CLKDIV2_RATIO RSVD CLK_DIV_STAT_TOP RSVD CLK_DIV_STAT_CAM0 CLK_DIV_STAT_TV CLK_DIV_STAT_MFC CLK_DIV_STAT_G3D RSVD CLK_DIV_STAT_LCD CLK_DIV_STAT_ISP CLK_DIV_STAT_MAUDIO CLK_DIV_STAT_FSYS0 CLK_DIV_STAT_FSYS1 CLK_DIV_STAT_FSYS2 CLK_DIV_STAT_FSYS3 CLK_DIV_STAT_PERIL0 CLK_DIV_STAT_PERIL1 CLK_DIV_STAT_PERIL2 CLK_DIV_STAT_PERIL3 Offset 0xC538 0xC53C 0xC540 0xC544 0xC548 0xC54C 0xC550 0xC554 0xC558 0xC55C 0xC560 0xC564 0xC568 0xC56C to 0xC57C 0xC580 0xC584 to 0xC60F 0xC610 0xC614 to 0xC61F 0xC620 0xC624 0xC628 0xC62C 0xC630 0xC634 0xC638 0xC63C 0xC640 0xC644 0xC648 0xC64C 0xC650 0xC654 0xC658 0xC65C Description Sets clock divider ratio for ISP_BLK Sets clock divider ratio for AUDIO_BLK Sets clock divider ratio for FSYS_BLK Sets clock divider ratio for FSYS_BLK Sets clock divider ratio for FSYS_BLK Sets clock divider ratio for FSYS_BLK Sets clock divider ratio for PERIL_BLK Sets clock divider ratio for PERIL_BLK Sets clock divider ratio for PERIL_BLK Sets clock divider ratio for PERIL_BLK Sets clock divider ratio for PERIL_BLK Sets clock divider ratio for PERIL_BLK Sets clock divider ratio for CAM_BLK Reserved Sets PCLK divider ratio in FSYS, CAM, LCD, TV, and GPS block Reserved Clock divider status for CMU_TOP Reserved Clock divider status for CAM_BLK Clock divider status for TV_BLK Clock divider status for MFC_BLK Clock divider status for G3D_BLK Reserved Clock divider status for LCD_BLK Clock divider status for ISP_BLK Clock divider status for AUDIO_BLK Clock divider status for FSYS_BLK Clock divider status for FSYS_BLK Clock divider status for FSYS_BLK Clock divider status for FSYS_BLK Clock divider status for PERIL_BLK Clock divider status for PERIL_BLK Clock divider status for PERIL_BLK Clock divider status for PERIL_BLK Reset Value 0x0000_0000 0x0000_0000 0x00B0_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Undefined 0x0111_1111 Undefined 0x0000_0000 Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 5-28 Exynos 4412_UM 5 Clock Management Unit Register CLK_DIV_STAT_PERIL4 CLK_DIV_STAT_PERIL5 CLK_DIV_STAT_CAM1 RSVD CLKDIV2_STAT RSVD CLK_GATE_BUS_FSYS1 RSVD CLK_GATE_IP_CAM CLK_GATE_IP_TV CLK_GATE_IP_MFC CLK_GATE_IP_G3D RSVD CLK_GATE_IP_LCD CLK_GATE_IP_ISP CLK_GATE_IP_FSYS RSVD CLK_GATE_IP_GPS CLK_GATE_IP_PERIL RSVD CLK_GATE_BLOCK RSVD CLKOUT_CMU_TOP CLKOUT_CMU_TOP_ DIV_STAT RSVD Offset 0xC660 0xC664 0xC668 0xC66C to 0xC67C 0xC680 0xC684 to 0xC740 0xC744 0xC748 to 0xC91F 0xC920 0xC924 0xC928 0xC92C 0xC930 0xC934 0xC938 0xC940 0xC944 to 0xC948 0xC94C 0xC950 0xC954 to 0xC96F 0xC970 0xC974 to 0xC9FF 0xCA00 Description Clock divider status for PERIL_BLK Clock divider status for PERIL_BLK Clock divider status for CAM_BLK Reserved PCLK divider status for FSYS, CAM, LCD, and TV block Reserved Control gating of AXI/AHB/APB clock for FSYS_BLK Reserved Controls IP clock gating for CAM_BLK Controls IP clock gating for TV_BLK Controls IP clock gating for MFC_BLK Controls IP clock gating for G3D_BLK Reserved Controls IP clock gating for LCD_BLK Controls IP clock gating for ISP_BLK Controls IP clock gating for FSYS_BLK Reserved Controls IP clock gating for GPS_BLK Controls IP clock gating for PERIL_BLK Reserved Clock gating control block Reserved CLKOUT control register 0xCA04 Clock divider status for CLKOUT 0xCA08 to 0x0004 Reserved Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 Undefined 0x0000_0000 Undefined 0xFFFF_FFFF Undefined 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF Undefined 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF Undefined 0xFFFF_FFFF 0xFFFF_FFFF Undefined 0xFFFF_FFFF Undefined 0x0001_0000 0x0000_0000 Undefined 5-29 Exynos 4412_UM 5 Clock Management Unit  Base Address 0x10040000 Register MPLL_LOCK RSVD MPLL_CON0 MPLL_CON1 RSVD CLK_SRC_DMC RSVD CLK_SRC_MASK_DMC RSVD CLK_MUX_STAT_DMC RSVD CLK_DIV_DMC0 CLK_DIV_DMC1 RSVD CLK_DIV_STAT_DMC0 CLK_DIV_STAT_DMC1 RSVD CLK_GATE_BUS_DMC0 CLK_GATE_BUS_DMC1 RSVD CLK_GATE_IP_DMC0 CLK_GATE_IP_DMC1 RSVD CLKOUT_CMU_DMC CLKOUT_CMU_DMC_ DIV_STAT RSVD DCGIDX_MAP0 DCGIDX_MAP1 Offset 0x0008 0x000C to 0x0104 0x0108 0x010C 0x0110 to 0x01FC 0x0200 0x0204 to 0x02FF 0x0300 0x0304 to 0x03FF 0x0400 0x0404 to 0x04FF 0x0500 0x0504 0x0508 to 0x05FF 0x0600 0x0604 0x0608 to 0x06FC 0x0700 0x0704 0x0708 to 0x08FC 0x0900 0x0904 0x0908 to 0x09FF 0x0A00 Description Controls PLL locking period for MPLL Reserved Controls PLL output frequency for MPLL Controls PLL AFC Reserved Selects clock source for CMU_DMC Reserved Clock source mask for DMC_BLK Reserved Clock MUX status for CMU_DMC Reserved Sets clock divider ratio for CMU_DMC Sets clock divider ratio for CMU_DMC Reserved Clock divider status for CMU_DMC Clock divider status for CMU_DMC Reserved Control gating of AXI clock for DMC_BLK Control gating of APB clock for DMC_BLK Reserved Control IP clock gating for DMC_BLK Control IP clock gating for DMC_BLK Reserved CLKOUT control register 0x0A04 Clock divider status for CLKOUT 0x0A08 to 0x0FFF 0x1000 0x1004 Reserved DCG index map0 DCG index map1 Reset Value 0x0000_0FFF Undefined 0x0064_0300 0x0080_3800 Undefined 0x0001_0000 Undefined 0x0001_0000 Undefined 0x1110_1111 Undefined 0x0000_0000 0x0000_1000 Undefined 0x0000_0000 0x0000_0000 Undefined 0xFFFF_FFFF 0xFFFF_FFFF Undefined 0xFFFF_FFFF 0xFFFF_FFFF Undefined 0x0001_0000 0x0000_0000 Undefined 0xFFFF_FFFF 0xFFFF_FFFF 5-30 Exynos 4412_UM Register DCGIDX_MAP2 RSVD DCGPERF_MAP0 DCGPERF_MAP1 RSVD DVCIDX_MAP RSVD FREQ_CPU FREQ_DPM RSVD DVSEMCLK_EN MAXPERF RSVD DMC_PAUSE_CTRL DDRPHY_LOCK_CTRL C2C_STATE RSVD APLL_LOCK RSVD APLL_CON0 APLL_CON1 RSVD CLK_SRC_CPU RSVD CLK_MUX_STAT_CPU RSVD CLK_DIV_CPU0 CLK_DIV_CPU1 RSVD 5 Clock Management Unit Offset 0x1008 0x100C to 0x101F 0x1020 0x1024 0x1028 to 0x103F 0x1040 0x1044 to 0x105F 0x1060 0x1064 0x1068 to 0x107F 0x1080 0x1084 0x1088 to 0x1090 0x1094 0x1098 0x109C 0x10A0 to 0x3FFC 0x4000 0x4004 to 0x40FC 0x4100 0x4104 0x4108 to 0x41FC 0x4200 0x4204 to 0x43FF 0x4400 0x4404 to 0x44FF 0x4500 0x4504 0x4508 to Description DCG index map2 Reserved DCG performance map0 DCG performance map1 Reserved DVC index map Reserved Maximum frequency of CPU Frequency of DPM Reserved DVS emulation clock enable Maximum performance enable Reserved Pause function of DREX2 for DVFS DDRPHY DLL lock control register when C2C is enabled Current state of C2C SEC FSM Reserved Control PLL locking period for APLL Reserved Control PLL output frequency for APLL Control PLL AFC Reserved Selects clock source for CMU_CPU Reserved Clock MUX status for CMU_CPU Reserved Sets clock divider ratio for CMU_CPU Sets clock divider ratio for CMU_CPU Reserved Reset Value 0xFFFF_FFFF Undefined 0xFFFF_FFFF 0xFFFF_FFFF Undefined 0x00FF_FFFF Undefined 0x0000_0000 0x0000_0000 Undefined 0x0000_0000 0x0000_0000 Undefined 0x0000_0000 0x0000_0000 0x0000_0000 Undefined 0x0000_0FFF Undefined 0x0064_0300 0x0080_3800 Undefined 0x0000_0000 Undefined 0x0011_0101 Undefined 0x0000_0000 0x0000_0000 Undefined 5-31 Exynos 4412_UM Register CLK_DIV_STAT_CPU0 CLK_DIV_STAT_CPU1 RSVD CLK_GATE_IP_CPU RSVD CLKOUT_CMU_CPU CLKOUT_CMU_CPU_ DIV_STAT RSVD ARMCLK_STOPCTRL ATCLK_STOPCTRL RSVD PWR_CTRL PWR_CTRL2 RSVD L2_STATUS RSVD CPU_STATUS RSVD PTM_STATUS CLK_DIV_ISP0 CLK_DIV_ISP1 CLK_DIV_STAT_ISP0 CLK_DIV_STAT_ISP1 RSVD CLK_GATE_IP_ISP0 CLK_GATE_IP_ISP1 5 Clock Management Unit Offset 0x45FF 0x4600 0x4604 0x4608 to 0x48FF 0x4900 0x4904 to 0x49FF 0x4A00 Description Clock divider status for CMU_CPU Clock divider status for CMU_CPU Reserved Controls IP clock gating for CMU_CPU Reserved CLKOUT control register Reset Value 0x0000_0000 0x0000_0000 Undefined 0xFFFF_FFFF Undefined 0x0001_0000 0x4A04 Clock divider status for CLKOUT 0x0000_0000 0x4A08 to 0x4FFF 0x5000 0x5004 0x500C to 0x501C 0x5020 0x5024 0x5028 to 0x53FC 0x5400 0x5404 to 0x540C 0x5410 0x5414 to 0x541C 0x5420 0x8300 0x8304 0x8400 0x8404 0x8408 to 0x87FC 0x8800 0x8804 Reserved Undefined ARM clock stop control register SCLK_APLL counts the number of cycles. ATCLK stop control register SCLK_APLL counts the number of cycles. 0x0404_0404 0x0000_0404 Reserved Undefined Power control register Power control register 0x0000_04FF 0x0000_0000 Reserved Undefined L2 cache status register 0x0000_0000 Reserved Undefined Cortex-A9 processor status register 0x0000_0000 Reserved Undefined Program trace macrocell (PTM) status register Set clock divider ratio for CMU_ISP0 Set clock divider ratio for MPWM in CMU_ISP1 Clock divider status for CMU_ISP0 Clock divider status for MPWM in CMU_ISP1 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Reserved Undefined Control IP clock gating for ISP_BLK register0 0xFFFF_FFFF Control IP clock gating for ISP_BLK register1 0xFFFF_FFFF 5-32 Exynos 4412_UM 5 Clock Management Unit Register RSVD CLKOUT_CMU_ISP CLKOUT_CMU_ISP_DIV _STAT CMU_ISP_SPARE0 CMU_ISP_SPARE1 CMU_ISP_SPARE2 CMU_ISP_SPARE3 Offset 0x8808 to 0x89FC 0x8A00 Description Reserved CLKOUT control register 0x8A04 Clock divider status for CLKOUT 0x8B00 0x8B04 0x8B08 0x8B0C CMU_ISP spare register0 CMU_ISP spare register1 CMU_ISP spare register2 CMU_ISP spare register3 Reset Value Undefined 0x0001_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 The six address spaces that SFRs fall into are: SFRs with address 0x0_4000 to 0x0_7FFF-These special function registers control clock-related logics for LEFTBUS block. They control clock source selection, clock divider ratio, and clock gating. SFRs with address 0x0_8000 to 0x0_BFFF-These special function registers control clock-related logics for RIGHTBUS block. They control clock source selection, clock divider ratio, and clock gating. SFRs with address 0x0_C000 to 0x0_FFFF-These special function registers control clock-related logics for MFC, G3D, TV, LCD, ISP, CAM, FSYS, PERIL, and PERIR blocks. They control EPLL and VPLL, clock source selection, clock divider ratio, and clock gating. SFRs with address 0x1_0000 to 0x1_3FFF-These special function registers control clock-related logics for DMC block. They control MPLL, clock source selection, clock divider ratio, and clock gating. SFRs with address 0x1_4000 to 0x1_7FFF-These special function registers control clock-related logics for CPU block. They control APLL, clock source selection, clock divider ratio and CPU-related logics. SFRs with address 0x1_8000 to 0x1_BFFF-These special function registers control clock-related logics for ISP block. They control clock source selection, clock divider ratio, and clock gating. 5-33 Exynos 4412_UM 5 Clock Management Unit 5.9.1.1 CLK_SRC_LEFTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x4200, Reset Value = 0x0000_0000 RSVD Name Bit [31:5] MUX_MPLL_USER_SEL_L [4] RSVD [3:1] MUX_GDL_SEL [0] Type  RW  RW Description Reserved Controls MUXMPLL 0 = FINPLL 1 = FOUTMPLL Reserved Controls MUXGDL 0 = SCLKMPLL 1 = SCLKAPLL 5.9.1.2 CLK_MUX_STAT_LEFTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x4400, Reset Value = 0x0000_0011 Name Bit Type Description RSVD MPLL_USER_SEL_L RSVD GDL_SEL [31:7] [6:4] [3:1] [2:0]  Reserved Selection Signal Status of MUXMPLL R 001 = FINMPLL 010 = FOUTMPL 1xx = Status that the mux is changing.  Reserved Selection Signal Status of MUXGDL R 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reset Value 0x0 0x0 0x0 0x0 Reset Value 0x0 0x1 0x0 0x1 5-34 Exynos 4412_UM 5 Clock Management Unit 5.9.1.3 CLK_DIV_LEFTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x4500, Reset Value = 0x0000_0000 Name RSVD GPL_RATIO RSVD GDL_RATIO Bit [31:7] [6:4] [3] [2:0] Type  RW  RW Description Reserved DIVGPL Clock Divider Ratio ACLK_GPL = MOUTGPL/(GPL_RATIO + 1) Reserved DIVGDL Clock Divider Ratio ACLK_GDL = MOUTGDL/(GDL_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 5.9.1.4 CLK_DIV_STAT_LEFTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x4600, Reset Value = 0x0000_0000 Name RSVD DIV_GPL RSVD DIV_GDL Bit [31:5] [4] [3:1] [0] Type  R  R Description Reserved DIVGPL Status 0 = Stable 1 = Status that the divider is changing Reserved DIVGDL Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 5-35 Exynos 4412_UM 5 Clock Management Unit 5.9.1.5 CLK_GATE_IP_LEFTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x4800, Reset Value = 0xFFFF_FFFF Name RSVD CLK_ASYNC_G3D RSVD CLK_ASYNC_MFCL CLK_ASYNC_TVX RSVD CLK_PPMULEFT CLK_GPIO_LEFT Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type  RW  RW RW  RW RW Description Reserved Gating all clocks for ASYNC_G3D 0 = Mask 1 = Pass Reserved Gating all clocks for ASYNC_MFCL 0 = Mask 1 = Pass Gating all clocks for ASYNC_TVX 0 = Mask 1 = Pass Reserved Gating all clocks for PPMULEFT 0 = Mask 1 = Pass Gating all clocks for GPIO_LEFT 0 = Mask 1 = Pass Reset Value 0x1FFFFFFF 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-36 Exynos 4412_UM 5 Clock Management Unit 5.9.1.6 CLK_GATE_IP_IMAGE  Base Address: 0x1003_0000  Address = Base Address + 0x4930, Reset Value = 0xFFFF_FFFF Name RSVD CLK_PPMUIMAGE RSVD RSVD RSVD CLK_SMMUMDMA Bit [31:10] [9] [8] [7] [6] [5] CLK_SMMUROTATOR [4] RSVD [3] CLK_MDMA [2] CLK_ROTATOR [1] RSVD [0] Type  RW –   RW RW  RW RW  Description Reserved Gating all clocks for PPMUIMAGE 0 = Mask 1 = Pass Reserved Reserved Reserved Gating all clocks for SMMUMDMA 0 = Mask 1 = Pass Gating all clocks for SMMUROTATOR 0 = Mask 1 = Pass Reserved Gating all clocks for MDMA 0 = Mask 1 = Pass Gating all clocks for ROTATOR 0 = Mask 1 = Pass Reserved Reset Value 0x3FFFFF 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-37 Exynos 4412_UM 5 Clock Management Unit 5.9.1.7 CLKOUT_CMU_LEFTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x4A00, Reset Value = 0x0001_0000 Name RSVD ENB_CLKOUT RSVD DIV_RATIO RSVD MUX_SEL Bit [31:17] [16] [15:14] [13:8] [7:5] [4:0] Type  RW  RW  RW Description Reserved Enable CLKOUT 0 = Disables 1 = Enables Reserved Divide Ratio Divide ratio = DIV_RATIO + 1 Reserved MUX selection 00000 = SCLK_MPLL/2 00001 = SCLK_APLL/2 00010 = ACLK_GDL 00011 = ACLK_GPL 5.9.1.8 CLKOUT_CMU_LEFTBUS_DIV_STAT  Base Address: 0x1003_0000  Address = Base Address + 0x4A04, Reset Value = 0x0000_0000 Name RSVD DIV_STAT Bit [31:1] [0] Type  R Description Reserved DIVCLKOUT Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x1 0x0 0x0 0x0 0x0 Reset Value 0x0 0x0 5-38 Exynos 4412_UM 5 Clock Management Unit 5.9.1.9 CLK_SRC_RIGHTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x8200, Reset Value = 0x0000_0000 RSVD Name MUX_MPLL_USER_SEL_R RSVD MUX_GDR_SEL Bit [31:5] [4] [3:1] [0] Type  RW  RW Description Reserved Controls MUXMPLL 0 = FINPLL 1 = FOUTMPLL Reserved Controls MUXGDR 0 = SCLKMPLL 1 = SCLKAPLL 5.9.1.10 CLK_MUX_STAT_RIGHTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x8400, Reset Value = 0x0000_0011 Name Bit Type Description RSVD MPLL_USER_SEL_R RSVD GDR_SEL [31:7] [6:4] [3] [2:0]  Reserved Selection Signal Status of MUXMPLL R 001 = FINMPLL 010 = FOUTMPLL 1xx = Status that the mux is changing  Reserved Selection Signal Status of MUXGDR R 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reset Value 0x0 0x0 0x0 0x0 Reset Value 0x0 0x1 0x0 0x1 5-39 Exynos 4412_UM 5 Clock Management Unit 5.9.1.11 CLK_DIV_RIGHTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x8500, Reset Value = 0x0000_0000 Name RSVD GPR_RATIO RSVD GDR_RATIO Bit [31:7] [6:4] [3] [2:0] Type  RW  RW Description Reserved DIVGPR Clock Divider Ratio ACLK_GPR = MOUTGPR/(GPR_RATIO + 1) Reserved DIVGDR Clock Divider Ratio ACLK_GDR = MOUTGDR/(GDR_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 5.9.1.12 CLK_DIV_STAT_RIGHTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x8600, Reset Value = 0x0000_0000 Name RSVD DIV_GPR RSVD DIV_GDR Bit [31:5] [4] [3:1] [0] Type  R  R Description Reserved DIVGPR Status 0 = Stable 1 = Status that the divider is changing Reserved DIVGDR Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 5-40 Exynos 4412_UM 5 Clock Management Unit 5.9.1.13 CLK_GATE_IP_RIGHTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x8800, Reset Value = 0xFFFF_FFFF Name RSVD Bit [31:10] CLK_ASYNC_ISPMX [9] RSVD [8] CLK_ASYNC_MAUDIOX [7] CLK_ASYNC_MFCR [6] CLK_ASYNC_FSYSD [5] RSVD [4] CLK_ASYNC_LCD0X [3] CLK_ASYNC_CAMX [2] CLK_PPMURIGHT [1] CLK_GPIO_RIGHT [0] Type  RW  RW RW RW  RW RW RW RW Description Reserved Gating all clocks for ASYNC_ISPMX 0 = Mask 1 = Pass Reserved Gating all clocks for ASYNC_MAUDIOX 0 = Mask 1 = Pass Gating all clocks for ASYNC_MFCR 0 = Mask 1 = Pass Gating all clocks for ASYNC_FSYSD 0 = Mask 1 = Pass Reserved Gating all clocks for ASYNC_LCD0X 0 = Mask 1 = Pass Gating all clocks for ASYNC_CAMX 0 = Mask 1 = Pass Gating all clocks for PPMURIGHT 0 = Mask 1 = Pass Gating all clocks for GPIO_RIGHT 0 = Mask 1 = Pass Reset Value 0x3FFFFF 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-41 Exynos 4412_UM 5 Clock Management Unit 5.9.1.14 CLK_GATE_IP_PERIR  Base Address: 0x1003_0000  Address = Base Address + 0x8960, Reset Value = 0xFFFF_FFFF Name RSVD CLK_CMU_ISPPART CLK_TMU_APBIF CLK_KEYIF CLK_RTC CLK_WDT CLK_MCT CLK_SECKEY CLK_HDMI_CEC CLK_TZPC5 CLK_TZPC4 CLK_TZPC3 CLK_TZPC2 CLK_TZPC1 Bit [31:19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] Type  RW RW RW RW RW RW RW RW RW RW RW RW RW Description Reserved Gating all clocks for CMU_ISPPART 0 = Mask 1 = Pass Gating all clocks for TMU_APBIF 0 = Mask 1 = Pass Gating all clocks for KEYIF 0 = Mask 1 = Pass Gating all clocks for RTC 0 = Mask 1 = Pass Gating all clocks for WDT 0 = Mask 1 = Pass Gating all clocks for System Timer 0 = Mask 1 = Pass Gating all clocks for SECKEY 0 = Mask 1 = Pass Gating all clocks for HDMI_CEC 0 = Mask 1 = Pass Gating all clocks for TZPC5 0 = Mask 1 = Pass Gating all clocks for TZPC4 0 = Mask 1 = Pass Gating all clocks for TZPC3 0 = Mask 1 = Pass Gating all clocks for TZPC2 0 = Mask 1 = Pass Gating all clocks for TZPC1 0 = Mask Reset Value 0x1FFF 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-42 Exynos 4412_UM 5 Clock Management Unit Name Bit Type Description 1 = Pass CLK_TZPC0 Gating all clocks for TZPC0 [5] RW 0 = Mask 1 = Pass Gating all clocks for CMU_COREPART CLK_CMU_COREPART [4] RW 0 = Mask 1 = Pass CLK_CMU_TOPPART Gating all clocks for CMU_TOPPART [3] RW 0 = Mask 1 = Pass CLK_PMU_APBIF Gating all clocks for PMU_APBIF [2] RW 0 = Mask 1 = Pass CLK_SYSREG Gating all clocks for SYSREG [1] RW 0 = Mask 1 = Pass CLK_CHIP_ID Gating all clocks for CHIP ID [0] RW 0 = Mask 1 = Pass Reset Value 0x1 0x1 0x1 0x1 0x1 0x1 5-43 Exynos 4412_UM 5.9.1.15 CLKOUT_CMU_RIGHTBUS  Base Address: 0x1003_0000  Address = Base Address + 0x8A00, Reset Value = 0x0001_0000 Name RSVD ENB_CLKOUT RSVD DIV_RATIO RSVD MUX_SEL Bit [31:17] [16] [15:14] [13:8] [7:5] [4:0] Type  RW  RW  RW Description Reserved Enable CLKOUT 0 = Disables 1 = Enables Reserved Divide Ratio Divide ratio = DIV_RATIO + 1 Reserved MUX Selection 00000 = SCLK_MPLL/2 00001 = SCLK_APLL/2 00010 = ACLK_GDR 00011 = ACLK_GPR 5 Clock Management Unit Reset Value 0x0 0x1 0x0 0x0 0x0 0x0 5-44 Exynos 4412_UM 5 Clock Management Unit 5.9.1.16 CLKOUT_CMU_RIGHTBUS_DIV_STAT  Base Address: 0x1003_0000  Address = Base Address + 0x8A04, Reset Value = 0x0000_0000 Name RSVD DIV_STAT Bit [31:1] [0] Type  R Description Reserved DIVCLKOUT Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 5.9.1.17 EPLL_LOCK  Base Address: 0x1003_0000  Address = Base Address + 0xC010, Reset Value = 0x0000_0FFF Name RSVD PLL_LOCKTIME Bit [31:16] [15:0] Type  RW Description Reserved Required period to generate a stable clock output Set (3000 cycles  PDIV) to PLL_LOCKTIME for the PLL maximum lock time. 1 cycle = 1/FREF = 1/(FIN/PDIV) The maximum PLL lock time is 250 usec where FIN is 24 MHz, PDIV is 2 and PLL_LOCKTIME is 6000. Reset Value 0x0 0xFFF The maximum lock time means the waiting time for locking in the worst case. Therefore, the user of this PLL must wait for more than the maximum lock time unconditionally before the PLL is locked. (Waiting time before locking ≥ the maximum locktime) 5-45 Exynos 4412_UM 5 Clock Management Unit 5.9.1.18 VPLL_LOCK  Base Address: 0x1003_0000  Address = Base Address + 0xC020, Reset Value = 0x0000_0FFF Name RSVD PLL_LOCKTIME Bit [31:16] [15:0] Type  RW Description Reserved Required period to generate a stable clock output Set (3000 cycles  PDIV) to PLL_LOCKTIME for the PLL maximum lock time. 1 cycle = 1/FREF = 1/(FIN/PDIV) The maximum PLL lock time is 250 usec where FIN is 24 MHz, PDIV is 2 and PLL_LOCKTIME is 6000. Reset Value 0x0 0xFFF The maximum lock time means the waiting time for locking in the worst case. Therefore, the user of this PLL must wait for more than the maximum lock time unconditionally before the PLL is locked. (Waiting time before locking ≥ the maximum locktime) 5-46 Exynos 4412_UM 5 Clock Management Unit 5.9.1.19 EPLL_CON0  Base Address: 0x1003_0000  Address = Base Address + 0xC110, Reset Value = 0x0060_0302 Name ENABLE RSVD LOCKED RSVD MDIV RSVD PDIV RSVD SDIV Bit [31] [30] [29] [28:25] [24:16] [15:14] [13:8] [7:3] [2:0] Type RW  R  RW  RW  RW Description PLL Enable Control 0 = Disables 1 = Enables Reserved PLL Locking Indication 0 = Unlocks 1 = Lockes This field is set after the locking time. EPLL_LOCK SFR register sets the locking time. It is a Read Only register. Reserved PLL M Divide Value Reserved PLL P Divide Value Reserved PLL S Divide Value Reset Value 0x0 0x0 0x0 0x0 0x60 0x0 0x3 0x0 0x2 The reset value of EPLL_CON0 generates a 192 MHz output clock for the input clock frequency of 24 MHz. The equation to calculate the output frequency is: FOUT = (MDIV + K/65536)  FIN/(PDIV  2SDIV) The conditions MDIV, PDIV, SDIV, and K should meet are:  PDIV: 1  PDIV  63  MDIV: 16  MDIV  511  SDIV: 0  SDIV  5  K: 0  K  65535  Fref = FIN/PDIV, where 4 MHz  Fref  30 MHz  FVCO= (MDIV + K/65536)  FIN/PDIV)  FOUT should fall in the range of: 22 MHz  FOUT  1400 MHz Do not set the value PDIV or MDIV to all zeros. Refer to the section 5.3.2 Recommended PLL PMS Value for EPLL for recommended PMS values. 5-47 Exynos 4412_UM 5 Clock Management Unit 5.9.1.20 EPLL_CON1  Base Address: 0x1003_0000  Address = Base Address + 0xC114, Reset Value = 0x6601_0000 Name RSVD SEL_PF MRR MFR K Bit [31] [30:29] [28:24] [23:16] [15:0] Type  RW RW RW RW Description Reserved Modulation Method Control 00 = Down spread 01 = Up spread 1x = Center spread Modulation Rate Control Modulation Frequency Control PLL 16-bit DSM (Delta-Sigma Modulator) Reset Value 0x0 0x3 0x6 0x1 0x0 Refer to the section 5.3.2 Recommended PLL PMS Value for EPLL for the recommended value of K. 5-48 Exynos 4412_UM 5 Clock Management Unit 5.9.1.21 EPLL_CON2  Base Address: 0x1003_0000  Address = Base Address + 0xC118, Reset Value = 0x0000_0080 Name RSVD EXTAFC DCC_ENB AFC_ENB SSCG_EN BYPASS FVCO_EN FSEL ICP_BOOST Bit [31:13] [12:8] [7] [6] [5] [4] [3] [2] [1:0] Type  RW RW RW RW RW RW RW RW Description Reserved AFC value Decides whether Duty Cycle Corrector (DCC) is enabled or not. 0 = Enables DCC 1 = Disables DCC It is an active low signal. Decides whether Adaptive Frequency Calibrator (AFC) is enabled or not. When AFC is enabled, it calibrates VCO automatically. 0 = Enables AFC 1 = Disables AFC It is an active low signal. Specifies if the dithered mode is enabled or not. 0 = Disables dithered mode 1 = Enables dithered mode If BYPASS = 1, then it enables bypass mode (FOUT = FIN) If BYPASS = 0, then PLL3600X operates normally. Enable pin for FVCO_OUT Pin selection for monitoring purposes. FVCO_OUT = FREF, if FSEL is set to 0 FVCO_OUT = FEED, FSEL is set to 1 ICP_BOOST Reset Value 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 If AFC_ENB is set to logic LOW, then it enables the AFC. If AFC_ENB is set to logic HIGH, then EXTAFC [4:0] controls the VCO frequency tuning range. EXTAFC specifies the decimal value of EXTAFC[4:0] as:  EXTAFC = EXTAFC[4:0] The hexadecimal values specified for EXTAFC[4:0] registers are:  5'b0 0000  EXTAFC[4:0]  5'b1 1111 NOTE: The other PLL control inputs should be set as: DCC_ENB = 1 ICP_BOOST = 0 SSCG_EN = 0 (Disable dithered mode) AFC_ENB = 0 EXTAFC = 0 5-49 Exynos 4412_UM 5 Clock Management Unit 5.9.1.22 VPLL_CON0  Base Address: 0x1003_0000  Address = Base Address + 0xC120, Reset Value = 0x006F_0302 Name ENABLE RSVD LOCKED RSVD MDIV RSVD PDIV RSVD SDIV Bit [31] [30] [29] [28:25] [24:16] [15:14] [13:8] [7:3] [2:0] Type RW  R  RW  RW  RW Description PLL Enable Control 0 = Disables 1 = Enables Reserved PLL Locking Indication 0 = Unlocks 1 = Locks Reserved PLL M Divide Value Reserved PLL P Divide Value Reserved PLL S Divide Value Reset Value 0x0 0x0 0x0 0x0 0x6F 0x0 0x3 0x0 0x2 The reset value of VPLL_CON0 generates a 222.75 MHz output clock for an input clock frequency of 24 MHz. Equation to calculate the output frequency is: FOUT = (MDIV + K/65535)  FIN/(PDIV  2SDIV) Where, MDIV, PDIV, SDIV, and K should meet the following conditions:  PDIV: 1  PDIV  63  MDIV: 16  MDIV  511  SDIV: 0  SDIV  5  K: 0  K  65535  Fref = FIN/PDIV) Fref should fall in the range of: 4 MHz  Fref  30 MHz  FVCO = (MDIV + K/v)  FIN/PDIV)  FOUT: 22 MHz  FOUT  1400 MHz Do not set the value PDIV or MDIV to all zeros. Refer to the section 5.3.3 Recommended PLL PMS Value for VPLL for the recommended PMS values. 5-50 Exynos 4412_UM 5 Clock Management Unit 5.9.1.23 VPLL_CON1  Base Address: 0x1003_0000  Address = Base Address + 0xC124, Reset Value = 0x6601_6000 Name RSVD SEL_PF MRR MFR K Bit [31] [30:29] [28:24] [23:16] [15:0] Type  RW RW RW RW Description Reserved Modulation Method Control 00 = Down spread 01 = Up spread 1x = Center spread Modulation Rate Control Modulation Frequency Control PLL DSM The equation to calculate the Modulation Frequency (MF) is: MF = FFIN/PDIV/MFR/32[Hz] The equation to calculate the Modulation Rate (MR) is:  MR = MFR  MRR/MDIV/64  100[%] The conditions that MFR and MRR should meet are:  MFR should fall in the range of: 0  MFR  255  MRR should fall in the range of: 1  MRR  31  0  MRR×MFR  512  SEL_PF[1:0]: 2'b00  SEL_PF  2'b10 Reset Value 0x0 0x3 0x6 0x1 0x464 5-51 Exynos 4412_UM 5 Clock Management Unit 5.9.1.24 VPLL_CON2  Base Address: 0x1003_0000  Address = Base Address + 0xC128, Reset Value = 0x0000_0080 Name RSVD EXTAFC DCC_ENB AFC_ENB SSCG_EN BYPASS FVCO_EN FSEL ICP_BOOST Bit [31:13] [12:8] [7] [6] [5] [4] [3] [2] [1:0] Type  RW RW RW RW RW RW RW RW Description Reserved AFC value Decides whether DCC is enabled or not. 0 = Enables DCC 1 = Disables DCC It is an active low signal. Decides whether AFC is enabled or not. When enabled, VCO is calibrated automatically. 0 = Enables AFC 1 = Disables AFC It is an active low signal. Specifies if the dithered mode is enabled or not. 0 = Disables dithered mode 1 = Enables dithered mode If BYPASS = 1, then it enables bypass mode (FOUT = FIN) IF BYPASS = 0, then the PLL3600X operates normally. Enable pin for FVCO_OUT Specifies pin selection for monitoring purposes FVCO_OUT = FREF, if FSEL is set to 0 FVCO_OUT = FEED, if FSEL is set to 1 ICP_BOOST Reset Value 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 If AFC_ENB is set to logic LOW, then it enables the AFC. If AFC_ENB is set to logic HIGH, then EXTAFC [4:0] controls the VCO frequency tuning range. EXTAFC specifies the decimal value of EXTAFC[4:0] as:  EXTAFC = EXTAFC[4:0] The hexadecimal values specified for EXTAFC[4:0] registers are:  5'b0 0000  EXTAFC[4:0]  5'b1 1111 NOTE: The other PLL control inputs should be set as: DCC_ENB = 1 ICP_BOOST = 0 AFC_ENB = 0 EXTAFC = 0 5-52 Exynos 4412_UM 5 Clock Management Unit 5.9.1.25 CLK_SRC_TOP0  Base Address: 0x1003_0000  Address = Base Address + 0xC210, Reset Value = 0x0000_0000 RSVD Name MUX_ONENAND_SEL RSVD MUX_ACLK_133_SEL RSVD MUX_ACLK_160_SEL RSVD MUX_ACLK_100_SEL RSVD MUX_ACLK_200_SEL RSVD MUX_VPLL_SEL RSVD MUX_EPLL_SEL RSVD MUX_ONENAND_1_SEL Bit [31:29] [28] [27:25] [24] [23:21] [20] [19:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  RW  RW  RW  RW  RW  RW  RW  RW Description Reserved Controls MUXONENAND 0 = ACLK_133 1 = ACLK_160 Reserved Controls MUXACLK_133 0 = SCLKMPLL 1 = SCLKAPLL Reserved Controls MUXACLK_160 0 = SCLKMPLL 1 = SCLKAPLL Reserved Controls MUXACLK_100 0 = SCLKMPLL 1 = SCLKAPLL Reserved Controls MUXACLK_200 0 = SCLKMPLL 1 = SCLKAPLL Reserved Controls MUXVPLL 0 = FINPLL 1 = FOUTVPLL Reserved Controls MUXEPLL 0 = FINPLL 1 = FOUTEPLL Reserved Controls MUXONENAND_1 0 = MOUTONENAND 1 = SCLKVPLL Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-53 Exynos 4412_UM 5 Clock Management Unit 5.9.1.26 CLK_SRC_TOP1  Base Address: 0x1003_0000  Address = Base Address + 0xC214, Reset Value = 0x0000_0000 Name RSVD MUX_ACLK_400_ MCUISP_SUB_SEL RSVD MUX_ACLK_200_ SUB_SEL RSVD MUX_ACLK_266_ GPS_SUB_SEL RSVD MUX_MPLL_USER_ SEL_T RSVD MUX_ACLK_400_ MCUISP_SEL RSVD MUX_ACLK_266_ GPS_SEL RSVD Bit [31:25] [24] [23:21] [20] [19:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:0] Type  RWX  RWX  RWX  RW  RW  RW  Description Reserved Controls MUXACLK_400_MCUISP_SUB 0 = FINPLL 1 = DIVOUT_ACLK_400_MCUISP Reserved Controls MUXACLK_200_SUB 0 = FINPLL 1 = DIVOUT_ACLK_200 Reserved Controls MUXACLK_266_GPS_SUB 0 = FINPLL 1 = DIVOUT_ACLK_266_GPS Reserved Controls MUXMPLL 0 = FINPLL 1 = SCLKMPLLL Reserved Controls MUXACLK_400_MCUISP 0 = SCLKMPLL_USER_T 1 = SCLKAPLL Reserved Controls MUXACLK_266_GPS 0 = SCLKMPLL_USER_T 1 = SCLKAPLL Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-54 Exynos 4412_UM 5 Clock Management Unit 5.9.1.27 CLK_SRC_CAM0  Base Address: 0x1003_0000  Address = Base Address + 0xC220, Reset Value = 0x1111_1111 Name CSIS1_SEL CSIS0_SEL CAM1_SEL CAM0_SEL Bit [31:28] [27:24] [23:20] [19:16] Type RW RW RW RW Description Controls MUXCSIS1 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXCSIS1 is the source clock of CSIS1. Controls MUXCSIS0 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXCSIS0 is the source clock of CSIS0. Controls MUXCAM1 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXCAM1 is the source clock of CAM_B_CLKOUT. Controls MUXCAM0 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL 0111 = SCLKEPLL 1000 = SCLKVPLL Reset Value 0x1 0x1 0x1 0x1 5-55 Exynos 4412_UM 5 Clock Management Unit Name FIMC3_LCLK_SEL FIMC2_LCLK_SEL FIMC1_LCLK_SEL FIMC0_LCLK_SEL Bit [15:12] [11:8] [7:4] [3:0] Type RW RW RW RW Description Others = Reserved MUXCAM0 is the source clock of CAM_A_CLKOUT. Controls MUXFIMC3_LCLK 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXFIMC3_LCLK is the source clock of FIMC3 local clock. Controls MUXFIMC2_LCLK 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXFIMC2_LCLK is the source clock of FIMC2 local clock. Controls MUXFIMC1_LCLK 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXFIMC1_LCLK is the source clock of FIMC1 local clock. Controls MUXFIMC0_LCLK 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved Reset Value 0x1 0x1 0x1 0x1 5-56 Exynos 4412_UM Name 5 Clock Management Unit Bit Type Description Reset Value MUXFIMC0_LCLK is the source clock of FIMC0 local clock. 5-57 Exynos 4412_UM 5 Clock Management Unit 5.9.1.28 CLK_SRC_TV  Base Address: 0x1003_0000  Address = Base Address + 0xC224, Reset Value = 0x0000_0000 Name RSVD HDMI_SEL Bit [31:1] [0] Type  RW Description Reserved Controls MUXHDMI 0 = SCLK_PIXEL 1 = SCLK_HDMIPHY MUXHDMI is the source clock of HDMI link. 5.9.1.29 CLK_SRC_MFC  Base Address: 0x1003_0000  Address = Base Address + 0xC228, Reset Value = 0x0000_0000 Name RSVD MFC_SEL RSVD MFC_1_SEL RSVD MFC_0_SEL Bit [31:9] [8] [7:5] [4] [3:1] [0] Type  RW  RW  RW Description Reserved Controls MUXMFC 0 = MOUTMFC_0 1 = MOUTMFC_1 MUXMFC is the source clock of MFC core. Reserved Controls MUXMFC_1 0 = SCLKEPLL 1 = SCLKVPLL MUXMFC_1 is the source clock of MFC core. Reserved Controls MUXMFC_0 0 = SCLKMPLL 1 = SCLKAPLL MUXMFC_0 is the source clock of MFC core. Reset Value 0x0 0x0 Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5-58 Exynos 4412_UM 5 Clock Management Unit 5.9.1.30 CLK_SRC_G3D  Base Address: 0x1003_0000  Address = Base Address + 0xC22C, Reset Value = 0x0000_0000 Name RSVD G3D_SEL RSVD G3D_1_SEL RSVD G3D_0_SEL Bit [31:9] [8] [7:5] [4] [3:1] [0] Type  RW  RW  RW Description Reserved Controls MUXG3D 0 = MOUTG3D_0 1 = MOUTG3D_1 MUXG3D is the source clock of G3D core. Reserved Controls MUXG3D_1 0 = SCLKEPLL 1 = SCLKVPLL MUXG3D_1 is the source clock of G3D core. Reserved Controls MUXG3D_0 0 = SCLKMPLL 1 = SCLKAPLL MUXG3D_0 is the source clock of G3D core. Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5-59 Exynos 4412_UM 5 Clock Management Unit 5.9.1.31 CLK_SRC_LCD0  Base Address: 0x1003_0000  Address = Base Address + 0xC234, Reset Value = 0x0000_1111 Name RSVD MIPI0_SEL MDNIE_PWM0 _SEL MDNIE0_SEL FIMD0_SEL Bit [31:16] [15:12] [11:8] [7:4] [3:0] Type  RW RW RW RW Description Reserved Controls MUXMIPI0 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXMIPI0 is the source clock of MIPI_DSIM0. Controls MUXMDNIE_PWM0 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXMDNIE_PWM0 is the source clock of MDNIE_PWM0. Controls MUXMDNIE0 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXMDNIE0 is the source clock of MDNIE0. Controls MUXFIMD0 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL Reset Value 0x0 0x1 0x1 0x1 0x1 5-60 Exynos 4412_UM 5 Clock Management Unit Name Bit Type Description 1000 = SCLKVPLL Others = Reserved MUXFIMD0 is the source clock of FIMD0. Reset Value 5-61 Exynos 4412_UM 5 Clock Management Unit 5.9.1.32 CLK_SRC_ISP  Base Address: 0x1003_0000  Address = Base Address + 0xC238, Reset Value = 0x0000_1111 Name RSVD UART_ISP _SEL SPI1_ISP _SEL SPI0_ISP _SEL PWM_ISP _SEL Bit [31:16] [15:12] [11:8] [7:4] [3:0] Type  RW RW RW RW Description Reserved Controls MUXUART_ISP 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXUART_ISP is the source clock of MIPI_DSIM1. Controls MUXSPI1_ISP 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXSPI1_ISP is the source clock of SPI1_ISP. Controls MUXSPI0_ISP 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXSPI0_ISP is the source clock of SPI0_ISP. Controls MUXPWM_ISP 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Reset Value 0x0 0x1 0x1 0x1 0x1 5-62 Exynos 4412_UM 5 Clock Management Unit Name Bit Type Description Others = Reserved MUXPWM_ISP is the source clock of PWM_ISP. Reset Value 5-63 Exynos 4412_UM 5 Clock Management Unit 5.9.1.33 CLK_SRC_MAUDIO  Base Address: 0x1003_0000  Address = Base Address + 0xC23C, Reset Value = 0x0000_0005 Name RSVD AUDIO0_SEL Bit [31:4] [3:0] Type  RW Description Reserved Controls MUXAUDIO0 0000 = AUDIOCDCLK0 0001 = Reserved 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0100 = XXTI 0101 = XusbXTI 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXAUDIO0 is the source clock of AUDIO0. Reset Value 0x0 0x5 5-64 Exynos 4412_UM 5 Clock Management Unit 5.9.1.34 CLK_SRC_FSYS  Base Address: 0x1003_0000  Address = Base Address + 0xC240, Reset Value = 0x0001_1111 Name RSVD MIPIHSI_SEL RSVD MMC4_SEL MMC3_SEL MMC2_SEL MMC1_SEL Bit [31:25] [24] [23:20] [19:16] [15:12] [11:8] [7:4] Type  RW - RW RW RW RW Description Reserved Control MUXMIPIHSI, which is the source clock of MIPIHSI 0 = SCLKMPLL_USER_T 1 = SCLKAPLL Reserved Controls MUXMMC4 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXMMC4 is the source clock of MMC4. Controls MUXMMC3 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXMMC3 is the source clock of MMC3. Controls MUXMMC2 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXMMC2 is the source clock of MMC2. Controls MUXMMC1 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M Reset Value 0x0 0x0 0x0 0x1 0x1 0x1 0x1 5-65 Exynos 4412_UM 5 Clock Management Unit Name MMC0_SEL Bit Type Description 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXMMC1 is the source clock of MMC1. Controls MUXMMC0 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 [3:0] RW 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXMMC0 is the source clock of MMC0. Reset Value 0x1 5-66 Exynos 4412_UM 5.9.1.35 CLK_SRC_PERIL0  Base Address: 0x1003_0000  Address = Base Address + 0xC250, Reset Value = 0x0001_1111 Name RSVD UART4_SEL UART3_SEL UART2_SEL UART1_SEL Bit [31:20] [19:16] [15:12] [11:8] [7:4] Type  RW RW RW RW Description Reserved It should be 1'b1. Controls MUXUART4 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXUART4 is the source clock of UART4. Controls MUXUART3 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXUART3 is the source clock of UART3. Controls MUXUART2 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXUART2 is the source clock of UART2. Controls MUXUART1 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 5-67 5 Clock Management Unit Reset Value 0x0 0x1 0x1 0x1 0x1 Exynos 4412_UM Name UART0_SEL Bit Type Description 1000 = SCLKVPLL Others = Reserved MUXUART1 is the source clock of UART1. Controls MUXUART0 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 [3:0] RW 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXUART0 is the source clock of UART0. 5 Clock Management Unit Reset Value 0x1 5-68 Exynos 4412_UM 5.9.1.36 CLK_SRC_PERIL1  Base Address: 0x1003_0000  Address = Base Address + 0xC254, Reset Value = 0x0111_0055 Name RSVD SPI2_SEL SPI1_SEL SPI0_SEL RSVD SPDIF_SEL AUDIO2 Bit [31:28] [27:24] [23:20] [19:16] [15:10] [9:8] [7:4] Type  RW RW RW  RW RW Description Reserved Controls MUXSPI2 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXSPI2 is the source clock of SPI2. Controls MUXSPI1 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXSPI1 is the source clock of SPI1. Controls MUXSPI0 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXSPI0 is the source clock of SPI0. Reserved Controls MUXSPDIF 00 = SCLK_AUDIO0 01 = SCLK_AUDIO1 10 = SCLK_AUDIO2 11 = SPDIF_EXTCLK MUXSPDIF is the source clock of SPDIF. Controls MUXAUDIO2 5-69 5 Clock Management Unit Reset Value 0x0 0x1 0x1 0x1 0x0 0x0 0x5 Exynos 4412_UM Name _SEL AUDIO1 _SEL Bit Type Description 0000 = AUDIOCDCLK2 0001 = Reserved 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0100 = XXTI 0101 = XusbXTI 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXAUDIO2 is the source clock of AUDIO2. Controls MUXAUDIO1 0000 = AUDIOCDCLK1 0001 = Reserved 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 [3:0] RW 0100 = XXTI 0101 = XusbXTI 0110 = SCLKMPLL_USER_T 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXAUDIO1 is the source clock of AUDIO1. 5 Clock Management Unit Reset Value 0x5 5-70 Exynos 4412_UM 5 Clock Management Unit 5.9.1.37 CLK_SRC_CAM1  Base Address: 0x1003_0000  Address = Base Address + 0xC258, Reset Value = 0x0000_0000 Name RSVD JPEG_SEL RSVD JPEG_1_SEL RSVD JPEG_0_SEL Bit [31:9] [8] [7:5] [4] [3:1] [0] Type  RW  RW  RW Description Reserved Controls MUXJPEG 0 = MOUTJPEG_0 1 = MOUTJPEG_1 MUXJPEG is the source clock of JPEG core. Reserved Controls MUXJPEG_1 0 = SCLKEPLL 1 = SCLKVPLL MUXJPEG_1 is the source clock of JPEG core. Reserved Controls MUXJPEG_0 0 = SCLKMPLL_USER_T 1 = SCLKAPLL MUXJPEG_0 is the source clock of JPEG core. Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5-71 Exynos 4412_UM 5 Clock Management Unit 5.9.1.38 CLK_SRC_MASK_CAM0  Base Address: 0x1003_0000  Address = Base Address + 0xC320, Reset Value = 0x1111_1111 Name RSVD CSIS1_MASK RSVD CSIS0_MASK RSVD CAM1_MASK RSVD CAM0_MASK RSVD FIMC3_LCLK_MASK RSVD FIMC2_LCLK_MASK RSVD FIMC1_LCLK_MASK RSVD FIMC0_LCLK_MASK Bit [31:29] [28] [27:25] [24] [23:21] [20] [19:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  RW  RW  RW  RW  RW  RW  RW  RW Description Reserved Mask output clock of MUXCSIS1 0 = Mask 1 = Unmask Reserved Mask output clock of MUXCSIS0 0 = Mask 1 = Unmask Reserved Mask output clock of MUXCAM1 0 = Mask 1 = Unmask Reserved Mask output clock of MUXCAM0 0 = Mask 1 = Unmask Reserved Mask output clock of MUXFIMC3_LCLK 0 = Mask 1 = Unmask Reserved Mask output clock of MUXFIMC2_LCLK 0 = Mask 1 = Unmask Reserved Mask output clock of MUXFIMC1_LCLK 0 = Mask 1 = Unmask Reserved Mask output clock of MUXFIMC0_LCLK 0 = Mask 1 = Unmask Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 5-72 Exynos 4412_UM 5 Clock Management Unit 5.9.1.39 CLK_SRC_MASK_TV  Base Address: 0x1003_0000  Address = Base Address + 0xC324, Reset Value = 0x0000_0111 Name RSVD HDMI_MASK Bit [31:1] [0] Type  RW Description Reserved Mask output clock of MUXHDMI 0 = Mask 1 = Unmask 5.9.1.40 CLK_SRC_MASK_LCD  Base Address: 0x1003_0000  Address = Base Address + 0xC334, Reset Value = 0x0000_1111 Name Bit Type Description RSVD [31:13] MIPI0_MASK [12] RSVD MDNIE_PWM0_M ASK RSVD [11:9] [8] [7:5] MDNIE0_MASK [4] RSVD [3:1] FIMD0_MASK [0]  Reserved Mask output clock of MUXMIPI0 RW 0 = Mask 1 = Unmask  Reserved Mask output clock of MUXMDNIE_PWM0 RW 0 = Mask 1 = Unmask  Reserved Mask output clock of MUXMDNIE0 RW 0 = Mask 1 = Unmask  Reserved Mask output clock of MUXFIMD0 RW 0 = Mask 1 = Unmask Reset Value 0x0 0x1 Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 5-73 Exynos 4412_UM 5 Clock Management Unit 5.9.1.41 CLK_SRC_MASK_ISP  Base Address: 0x1003_0000  Address = Base Address + 0xC338, Reset Value = 0x0000_1111 Name RSVD Bit [31:13] UART_ISP_MASK [12] RSVD [11:9] SPI1_ISP_MASK [8] RSVD [7:5] SPI0_ISP_MASK [4] RSVD [3:1] PWM_ISP_MASK [0] Type  RW  RW  RW  RW Description Reserved Mask output clock of MUXUART_ISP 0 = Mask 1 = Unmask Reserved Mask output clock of MUXSPI1_ISP 0 = Mask 1 = Unmask Reserved Mask output clock of MUXSPI0_ISP 0 = Mask 1 = Unmask Reserved Mask output clock of MUXPWM_ISP 0 = Mask 1 = Unmask 5.9.1.42 CLK_SRC_MASK_MAUDIO  Base Address: 0x1003_0000  Address = Base Address + 0xC33C, Reset Value = 0x0000_0001 Name Bit Type Description RSVD AUDIO0_MASK [31:1] [0]  Reserved Mask output clock of MUXAUDIO0 RW 0 = Mask 1 = Unmask Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 Reset Value 0x0 0x1 5-74 Exynos 4412_UM 5 Clock Management Unit 5.9.1.43 CLK_SRC_MASK_FSYS  Base Address: 0x1003_0000  Address = Base Address + 0xC340, Reset Value = 0x0101_1111 Name RSVD MIPIHSI_MASK RSVD MMC4_MASK RSVD MMC3_MASK RSVD MMC2_MASK RSVD MMC1_MASK RSVD MMC0_MASK Bit [31:25] [24] [23:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  RW  RW  RW  RW  RW  RW Description Reserved Mask output clock of MUXMIPIHSI 0 = Mask 1 = Unmask Reserved Mask output clock of MUXMMC4 0 = Mask 1 = Unmask Reserved Mask output clock of MUXMMC3 0 = Mask 1 = Unmask Reserved Mask output clock of MUXMMC2 0 = Mask 1 = Unmask Reserved Mask output clock of MUXMMC1 0 = Mask 1 = Unmask Reserved Mask output clock of MUXMMC0 0 = Mask 1 = Unmask Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 5-75 Exynos 4412_UM 5.9.1.44 CLK_SRC_MASK_PERIL0  Base Address: 0x1003_0000  Address = Base Address + 0xC350, Reset Value = 0x0001_1111 Name RSVD UART4_MASK RSVD UART3_MASK RSVD UART2_MASK RSVD UART1_MASK RSVD UART0_MASK Bit [31:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  RW  RW  RW  RW  RW Description Reserved Mask output clock of MUXUART4 0 = Mask 1 = Unmask Reserved Mask output clock of MUXUART3 0 = Mask 1 = Unmask Reserved Mask output clock of MUXUART2 0 = Mask 1 = Unmask Reserved Mask output clock of MUXUART1 0 = Mask 1 = Unmask Reserved Mask output clock of MUXUART0 0 = Mask 1 = Unmask 5 Clock Management Unit Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 5-76 Exynos 4412_UM 5.9.1.45 CLK_SRC_MASK_PERIL1  Base Address: 0x1003_0000  Address = Base Address + 0xC354, Reset Value = 0x0111_0111 Name RSVD SPI2_MASK RSVD SPI1_MASK RSVD SPI0_MASK RSVD SPDIF_MASK RSVD AUDIO2_MASK RSVD AUDIO1_MASK Bit [31:25] [24] [23:21] [20] [19:17] [16] [15:9] [8] [7:5] [4] [3:1] [0] Type  RW  RW  RW  RW  RW  RW Description Reserved Mask output clock of MUXSPI2 0 = Mask 1 = Unmask Reserved Mask output clock of MUXSPI1 0 = Mask 1 = Unmask Reserved Mask output clock of MUXSPI0 0 = Mask 1 = Unmask Reserved Mask output clock of MUXSPDIF 0 = Mask 1 = Unmask Reserved Mask output clock of MUXAUDIO2 0 = Mask 1 = Unmask Reserved Mask output clock of MUXAUDIO1 0 = Mask 1 = Unmask 5 Clock Management Unit Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 5-77 Exynos 4412_UM 5 Clock Management Unit 5.9.1.46 CLK_MUX_STAT_TOP  Base Address: 0x1003_0000  Address = Base Address + 0xC410, Reset Value = 0x1111_1111 Name RSVD ONENAND_SEL RSVD ACLK_133_SEL RSVD ACLK_160_SEL RSVD ACLK_100_SEL RSVD ACLK_200_SEL RSVD VPLL_SEL RSVD EPLL_SEL RSVD ONENAND_1_SEL Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Type  R  R  R  R  R  R  R  R Description Reserved Selection signal status of MUXONENAND 001 = DOUT133 010 = DOUT166 1xx = Status that the mux is changing Reserved Selection signal status of MUXACLK_133 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXACLK_160 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXACLK_100 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXACLK_200 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXVPLL 001 = FINVPLL 010 = FOUTVPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXEPLL 001 = FINPLL 010 = FOUTEPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXONENAND_1 001 = MOUTONENAND 010 = SCLKVPLL Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 5-78 Exynos 4412_UM Name 5 Clock Management Unit Bit Type Description 1xx = Status that the mux is changing Reset Value 5-79 Exynos 4412_UM 5 Clock Management Unit 5.9.1.47 CLK_MUX_STAT_TOP1  Base Address: 0x1003_0000  Address = Base Address + 0xC414, Reset Value = 0x0111_1110 Name RSVD ACLK_400_MCUISP _SUB_SEL RSVD ACLK_200_SUB _SEL RSVD ACLK_266_GPS _SUB_SEL RSVD MPLL_USER_SEL_T RSVD ACLK_400_MCUISP _SEL RSVD ACLK_266_GPS _SEL RSVD Bit [31:27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3:0] Type  R  R  R  R  R  R  Description Reserved Selection signal status of MUXACLK_400_MCUISP 001 = FINPLL 010 = FOUTPOST_ACLK_400_MCUISP 1xx = Status that the mux is changing Reserved Selection signal status of MUXACLK_200 001 = FINPLL 010 = FOUTPOST_ACLK_200 1xx = Status that the mux is changing Reserved Selection signal status of MUXACLK_266_GPS 001 = FINPLL 010 = FOUTPOST_ACLK_266_GPS 1xx = Status that the mux is changing Reserved Selection signal status of MUXMPLL 001 = FINMPLL 010 = FOUTMPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXACLK_400_MCUISP 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXACLK_266_GPS 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reserved Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 5-80 Exynos 4412_UM 5 Clock Management Unit 5.9.1.48 CLK_MUX_STAT_MFC  Base Address: 0x1003_0000  Address = Base Address + 0xC428, Reset Value = 0x0000_0111 Name RSVD MFC_SEL RSVD MFC_1_SEL RSVD MFC_0_SEL Bit [31:11] [10:8] [7] [6:4] [3] [2:0] Type  R  R  R Description Reserved Selection signal status of MUXMFC 001 = MOUTMFC_0 010 = MOUTMFC_1 1xx = Status that the mux is changing Reserved Selection signal status of MUXMFC_1 001 = SCLKEPLL 010 = SCLKVPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXMFC_0 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing 5.9.1.49 CLK_MUX_STAT_G3D  Base Address: 0x1003_0000  Address = Base Address + 0xC42C, Reset Value = 0x0000_0111 Name RSVD G3D_SEL RSVD G3D_1_SEL RSVD G3D_0_SEL Bit [31:11] [10:8] [7] [6:4] [3] [2:0] Type  R  R  R Description Reserved Selection signal status of MUXG3D 001 = MOUTG3D_0 010 = MOUTG3D_1 1xx = Status that the mux is changing Reserved Selection signal status of MUXG3D_1 001 = SCLKEPLL 010 = SCLKVPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXG3D_0 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 5-81 Exynos 4412_UM 5 Clock Management Unit 5.9.1.50 CLK_MUX_STAT_CAM1  Base Address: 0x1003_0000  Address = Base Address + 0xC458, Reset Value = 0x0000_0111 Name RSVD JPEG_SEL RSVD JPEG_1_SEL RSVD JPEG_0_SEL Bit [31:11] [10:8] [7] [6:4] [3] [2:0] Type  R  R  R Description Reserved Selection signal status of MUXJPEG 001 = MOUTJPEG_0 010 = MOUTJPEG_1 1xx = Status that the mux is changing Reserved Selection signal status of MUXJPEG_1 001 = SCLKEPLL 010 = SCLKVPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXJPEG_0 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 5-82 Exynos 4412_UM 5 Clock Management Unit 5.9.1.51 CLK_DIV_TOP  Base Address: 0x1003_0000  Address = Base Address + 0xC510, Reset Value = 0x0000_0000 Name RSVD ACLK_400_MCUISP _RATIO RSVD ACLK_266_GPS _RATIO RSVD ONENAND_RATIO RSVD ACLK_133_RATIO RSVD ACLK_160_RATIO ACLK_100_RATIO RSVD ACLK_200_RATIO Bit [31:27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7:4] [3] [2:0] Type  RW  RW  RW  RW  RW RW  RW Description Reserved DIVACLK_266 Clock Divider Ratio ACLK_400_MCUISP = [MOUTACLK_400_MCUISP/(ACLK_400_MCUI SP_RATIO + 1)] Reserved DIVACLK_266 Clock Divider Ratio ACLK_266_GPS = [MOUTACLK_266_GPS /(ACLK_266_GPS_RATIO + 1)] Reserved DIVONENAND Clock Divider Ratio SCLK_ONENAND = [MOUTONENAND_1 /(ONENAND_RATIO + 1)] Reserved DIVACLK_133 Clock Divider Ratio ACLK_133 = [MOUTACLK_133 /(ACLK_133_RATIO + 1)] Reserved DIVACLK_160 Clock Divider Ratio ACLK_160 = [MOUTACLK_160 /(ACLK_160_RATIO + 1)] DIVACLK_100 Clock Divider Ratio ACLK_100 = [MOUTACLK_100/(ACLK_100_RATIO + 1)] Reserved DIVACLK_200 Clock Divider Ratio ACLK_200 = [MOUTACLK_200/(ACLK_200_RATIO + 1)] Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-83 Exynos 4412_UM 5 Clock Management Unit 5.9.1.52 CLK_DIV_CAM0  Base Address: 0x1003_0000  Address = Base Address + 0xC520, Reset Value = 0x0000_0000 Name CSIS1_RATIO CSIS0_RATIO CAM1_RATIO CAM0_RATIO Bit [31:28] [27:24] [23:20] [19:16] FIMC3_LCLK_RATIO [15:12] FIMC2_LCLK_RATIO [11:8] FIMC1_LCLK_RATIO [7:4] FIMC0_LCLK_RATIO [3:0] Type RW RW RW RW RW RW RW RW Description DIVCSIS1 Clock Divider Ratio SCLK_CSIS1 = MOUTCSIS1/(CSIS1_RATIO + 1) DIVCSIS0 Clock Divider Ratio SCLK_CSIS0 = MOUTCSIS0/(CSIS0_RATIO + 1) DIVCAM1 Clock Divider Ratio SCLK_CAM1 = MOUTCAM1/(CAM1_RATIO + 1) DIVCAM0 Clock Divider Ratio SCLK_CAM0 = MOUTCAM0/(CAM0_RATIO + 1) DIVFIMC3_LCLK Clock Divider Ratio SCLKFIMC3_LCLK = [MOUTFIMC3_LCLK /(FIMC3_LCLK_RATIO + 1)] DIVFIMC2_LCLK Clock Divider Ratio SCLKFIMC2_LCLK = [MOUTFIMC2_LCLK /(FIMC2_LCLK_RATIO + 1)] DIVFIMC1_LCLK Clock Divider Ratio SCLKFIMC1_LCLK =[ MOUTFIMC1_LCLK /(FIMC1_LCLK_RATIO + 1)] DIVFIMC0_LCLK Clock Divider Ratio SCLKFIMC0_LCLK = [MOUTFIMC0_LCLK /(FIMC0_LCLK_RATIO + 1)] Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5.9.1.53 CLK_DIV_TV  Base Address: 0x1003_0000  Address = Base Address + 0xC524, Reset Value = 0x0000_0000 Name RSVD TV_BLK_RATIO Bit [31:4] [3:0] Type  RW Description Reserved DIVTV_BLK Clock Divider Ratio SCLK_PIXEL = SCLKVPLL/(TV_BLK_RATIO + 1) Reset Value 0x0 0x0 5-84 Exynos 4412_UM 5 Clock Management Unit 5.9.1.54 CLK_DIV_MFC  Base Address: 0x1003_0000  Address = Base Address + 0xC528, Reset Value = 0x0000_0000 Name RSVD MFC_RATIO Bit [31:4] [3:0] Type  RW Description Reserved DIVMFC Clock Divider Ratio SCLK_MFC = MOUTMFC/(MFC_RATIO + 1) Reset Value 0x0 0x0 5.9.1.55 CLK_DIV_G3D  Base Address: 0x1003_0000  Address = Base Address + 0xC52C, Reset Value = 0x0000_0000 Name Bit Type Description RSVD G3D_RATIO [31:4] [3:0]  Reserved RW DIVG3D Clock Divider Ratio SCLK_G3D= MOUTG3D/(G3D_RATIO + 1) Reset Value 0x0 0x0 5.9.1.56 CLK_DIV_LCD  Base Address: 0x1003_0000  Address = Base Address + 0xC534, Reset Value = 0x0070_0000 Name RSVD MIPI0_PRE_ RATIO MIPI0_RATIO MDNIE_PWM0 _PRE_RATIO MDNIE_PWM0 _RATIO MDNIE0_RATIO FIMD0_RATIO Bit [31:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type  RW RW RW RW RW RW Description Reserved DIVMIPI0_PRE Clock Divider Ratio SCLK_MIPI0 = DOUTMIPI0/(MIPI0_PRE_RATIO + 1) DIVMIPI0 Clock Divider Ratio SCLK_MIPIDPHY4L = MOUTMIPI0 /(MIPI0_RATIO + 1) DIVMDNIE_PWM0_PRE Clock Divider Ratio SCLK_MDNIE_PWM0 = DOUTMDNIE_PWM0 /(MDNIE_PWM0_PRE_RATIO + 1) DIVMDNIE_PWM0 Clock Divider Ratio DOUTMDNIE_PWM0 = MOUTMDNIE_PWM0 /(MDNIE_PWM0_RATIO + 1) DIVMDNIE0 Clock Divider Ratio SCLK_MDNIE0 = MOUTMDNIE0 /(MDNIE0_RATIO + 1) DIVFIMD0 Clock Divider Ratio SCLK_FIMD0 = MOUTFIMD0/(FIMD0_RATIO + 1) Reset Value 0x0 0x7 0x0 0x0 0x0 0x0 0x0 5-85 Exynos 4412_UM 5 Clock Management Unit 5.9.1.57 CLK_DIV_ISP  Base Address: 0x1003_0000  Address = Base Address + 0xC538, Reset Value = 0x0000_0000 Name UART_ISP _RATIO SPI1_ISP_PRE _RATIO SPI1_ISP_RATIO SPI0_ISP_PRE _RATIO SPI0_ISP_RATIO PWM_ISP_RATIO Bit [31:28] [27:20] [19:16] [15:8] [7:4] [3:0] Type RW RW RW RW RW RW Description DIVUART_ISP Clock Divider Ratio SCLK_UART_ISP = [DOUTUART_ISP/(UART_ISP_RATIO + 1)] DIVSPI1_ISP_PRE Clock Divider Ratio SCLK_SPI1_ISP = [DOUTSPI1_ISP /(SPI1_ISP_PRE_RATIO + 1)] DIVSPI1_ISP Clock Divider Ratio DOUTSPI1_ISP = [MOUTSPI1_ISP/(SPI1_ISP_RATIO + 1)] DIVSPI0_ISP_PRE Clock Divider Ratio SCLK_SPI0_ISP = [DOUTSPI0_ISP/(SPI0_ISP_PRE_RATIO + 1)] DIVSPI0_ISP Clock Divider Ratio DOUTSPI0_ISP = [MOUTSPI0_ISP/(SPI0_ISP_RATIO + 1)] DIVPWM_ISP Clock Divider Ratio SCLK_PWM_ISP = [MOUTPWM_ISP/(PWM_ISP_RATIO + 1)] Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5.9.1.58 CLK_DIV_MAUDIO  Base Address: 0x1003_0000  Address = Base Address + 0xC53C, Reset Value = 0x0000_0000 Name RSVD PCM0_RATIO AUDIO0_RATIO Bit [31:12] [11:4] [3:0] Type  RW RW Description Reserved DIVPCM0 Clock Divider Ratio SCLK_PCM0 = SCLK_AUDIO0/(PCM0_RATIO + 1) DIVAUDIO0 Clock Divider Ratio SCLK_AUDIO0 = MOUTAUDIO0/(AUDIO0_RATIO + 1) Reset Value 0x0 0x0 0x0 5-86 Exynos 4412_UM 5 Clock Management Unit 5.9.1.59 CLK_DIV_FSYS0  Base Address: 0x1003_0000  Address = Base Address + 0xC540, Reset Value = 0x00B0_0000 Name RSVD MIPIHSI_RATIO RSVD Bit [31:24] [23:20] [19:0] Type  RW  Description Reserved DIVMIPIHSI Clock Divider Ratio SCLK_MIPIHSI = [MOUTMIPIHSI/(MIPIHSI_RATIO + 1)] Reserved Reset Value 0x0 0xB 0x0 5.9.1.60 CLK_DIV_FSYS1  Base Address: 0x1003_0000  Address = Base Address + 0xC544, Reset Value = 0x0000_0000 Name MMC1_PRE_RATIO RSVD MMC1_RATIO MMC0_PRE_RATIO RSVD MMC0_RATIO Bit [31:24] [23:20] [19:16] [15:8] [7:4] [3:0] Type RW  RW RW  RW Description DIVMMC1_PRE Clock Divider Ratio SCLK_MMC1=DOUTMMC1/(MMC1_PRE_RATIO + 1)] Reserved DIVMMC1 Clock Divider Ratio DOUTMMC1 = MOUTMMC1/(MMC1_RATIO + 1) DIVMMC0_PRE Clock Divider Ratio SCLK_MMC0 =[DOUTMMC0/(MMC0_PRE_RATIO + 1)] Reserved DIVMMC0 Clock Divider Ratio DOUTMMC0 = MOUTMMC0/(MMC0_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5-87 Exynos 4412_UM 5 Clock Management Unit 5.9.1.61 CLK_DIV_FSYS2  Base Address: 0x1003_0000  Address = Base Address + 0xC548, Reset Value = 0x0000_0000 Name MMC3_PRE_RATIO RSVD MMC3_RATIO MMC2_PRE_RATIO RSVD MMC2_RATIO Bit [31:24] [23:20] [19:16] [15:8] [7:4] [3:0] Type RW  RW RW  RW Description DIVMMC3_PRE Clock Divider Ratio SCLK_MMC3 =[DOUTMMC3/(MMC3_PRE_RATIO + 1)] Reserved DIVMMC3 Clock Divider Ratio DOUTMMC3 = MOUTMMC3/(MMC3_RATIO + 1) DIVMMC2_PRE Clock Divider Ratio SCLK_MMC2 =[DOUTMMC2/(MMC2_PRE_RATIO + 1)] Reserved DIVMMC2 Clock Divider Ratio DOUTMMC2 = MOUTMMC2/(MMC2_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5.9.1.62 CLK_DIV_FSYS3  Base Address: 0x1003_0000  Address = Base Address + 0xC54C, Reset Value = 0x0000_0000 Name RSVD MMC4_PRE_RATIO RSVD MMC4_RATIO Bit [31:16] [15:8] [7:4] [3:0] Type  RW  RW Description Reserved DIVMMC4_PRE Clock Divider Ratio SCLK_MMC4 =[DOUTMMC4/(MMC4_PRE_RATIO + 1)] Reserved DIVMMC4 Clock Divider Ratio DOUTMMC4 = MOUTMMC4/(MMC4_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 5-88 Exynos 4412_UM 5 Clock Management Unit 5.9.1.63 CLK_DIV_PERIL0  Base Address: 0x1003_0000  Address = Base Address + 0xC550, Reset Value = 0x0000_0000 Name RSVD UART4_RATIO UART3_RATIO UART2_RATIO UART1_RATIO UART0_RATIO Bit [31:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type  RW RW RW RW RW Description Reserved DIVUART4 Clock Divider Ratio SCLK_UART4 = MOUTUART4/(UART4_RATIO + 1) DIVUART3 Clock Divider Ratio SCLK_UART3 = MOUTUART3/(UART3_RATIO + 1) DIVUART2 Clock Divider Ratio SCLK_UART2 = MOUTUART2/(UART2_RATIO + 1) DIVUART1 Clock Divider Ratio SCLK_UART1 = MOUTUART1/(UART1_RATIO + 1) DIVUART0 Clock Divider Ratio SCLK_UART0 = MOUTUART0/(UART0_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5.9.1.64 CLK_DIV_PERIL1  Base Address: 0x1003_0000  Address = Base Address + 0xC554, Reset Value = 0x0000_0000 Name SPI1_PRE_RATIO RSVD SPI1_RATIO SPI0_PRE_RATIO RSVD SPI0_RATIO Bit [31:24] [23:20] [19:16] [15:8] [7:4] [3:0] Type RW  RW RW  RW Description DIVSPI1_PRE Clock Divider Ratio SCLK_SPI1 = DOUTSPI1/(SPI1_PRE_RATIO + 1) Reserved DIVSPI1 Clock Divider Ratio DOUTSPI1 = MOUTSPI1/(SPI1_RATIO + 1) DIVSPI0_PRE Clock Divider Ratio SCLK_SPI0 = DOUTSPI0/(SPI0_PRE_RATIO + 1) Reserved DIVSPI0 Clock Divider Ratio DOUTSPI0 = MOUTSPI0/(SPI0_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5-89 Exynos 4412_UM 5 Clock Management Unit 5.9.1.65 CLK_DIV_PERIL2  Base Address: 0x1003_0000  Address = Base Address + 0xC558, Reset Value = 0x0000_0000 Name RSVD SPI2_PRE_RATIO RSVD SPI2_RATIO Bit [31:16] [15:8] [7:4] [3:0] Type  RW  RW Description Reserved DIVSPI2_PRE Clock Divider Ratio SCLK_SPI2 = DOUTSPI2/(SPI2_PRE_RATIO + 1) Reserved DIVSPI2 Clock Divider Ratio DOUTSPI2 = MOUTSPI2/(SPI2_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 5.9.1.66 CLK_DIV_PERIL3  Base Address: 0x1003_0000  Address = Base Address + 0xC55C, Reset Value = 0x0000_0000 Name RSVD SLIMBUS_RATIO RSVD Bit [31:8] [7:4] [3:0] Type  RW  Description Reserved DIVSLIMBUS Clock Divider Ratio SCLK_SLIMBUS = SCLKEPLL/(SLIMBUS_RATIO + 1) Reserved Reset Value 0x0 0x0 0x0 5-90 Exynos 4412_UM 5 Clock Management Unit 5.9.1.67 CLK_DIV_PERIL4  Base Address: 0x1003_0000  Address = Base Address + 0xC560, Reset Value = 0x0000_0000 Name RSVD PCM2_RATIO AUDIO2_RATIO RSVD PCM1_RATIO AUDIO1_RATIO Bit [31:28] [27:20] [19:16] [15:12] [11:4] [3:0] Type  RW RW  RW RW Description Reserved DIVPCM2 Clock Divider Ratio SCLK_PCM2 = SCLK_AUDIO2/(PCM2_RATIO + 1) DIVAUDIO2 Clock Divider Ratio SCLK_AUDIO2 = [MOUTAUDIO2/(AUDIO2_RATIO + 1)] Reserved DIVPCM1 Clock Divider Ratio SCLK_PCM1 = SCLK_AUDIO1/(PCM1_RATIO + 1) DIVAUDIO1 Clock Divider Ratio SCLK_AUDIO1 = [MOUTAUDIO1/(AUDIO1_RATIO + 1)] Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5.9.1.68 CLK_DIV_PERIL5  Base Address: 0x1003_0000  Address = Base Address + 0xC564, Reset Value = 0x0000_0000 Name RSVD I2S2_RATIO RSVD I2S1_RATIO Bit [31:14] [13:8] [7:6] [5:0] Type  RW  RW Description Reserved DIVI2S2 Clock Divider Ratio SCLK_I2S2 = SCLK_AUDIO2/(I2S2_RATIO + 1) Reserved DIVI2S1 Clock Divider Ratio SCLK_I2S1 = SCLK_AUDIO1/(I2S1_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 5.9.1.69 CLK_DIV_CAM1  Base Address: 0x1003_0000  Address = Base Address + 0xC568, Reset Value = 0x0000_0000 Name RSVD JPEG_RATIO Bit [31:4] [3:0] Type  RW Description Reserved DIVJPEG Clock Divider Ratio ACLK_JPEG = MOUTJPEG/(JPEG_RATIO + 1) Reset Value 0x0 0x0 5-91 Exynos 4412_UM 5 Clock Management Unit 5.9.1.70 CLKDIV2_RATIO  Base Address: 0x1003_0000  Address = Base Address + 0xC580, Reset Value = 0x0110_1011 Name RSVD GPS_BLK RSVD TV_BLK RSVD LCD_BLK RSVD CAM_BLK RSVD FSYS_BLK Bit [31:26] [25:24] [23:22] [21:20] [19:14] [13:12] [11:6] [5:4] [3:2] [1:0] Type  RW  RW  RW  RW  RW Description Reserved PCLK Divider Ratio in GPS_BLK 0 = Reserved 1 = Divides by 2 2 = Divides by 3 3 = Divides by 4 Reserved PCLK Divider Ratio in TV_BLK 0 = Reserved 1 = Divides by 2 2 = Divides by 3 3 = Divides by 4 Reserved PCLK Divider Ratio in LCD_BLK for 160 MHz domain 0 = Reserved 1 = Divides by 2 2 = Divides by 3 3 = Divides by 4 Reserved PCLK Divider Ratio in CAM_BLK 0 = Reserved 1 = Divides by 2 2 = Divides by 3 3 = Divides by 4 Reserved PCLK Divider Ratio in FSYS_BLK 0 = Reserved 1 = Divides by 2 2 = Divides by 3 3 = Divides by 4 Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 5-92 Exynos 4412_UM 5 Clock Management Unit 5.9.1.71 CLK_DIV_STAT_TOP  Base Address: 0x1003_0000  Address = Base Address + 0xC610, Reset Value = 0x0000_0000 RSVD Name DIV_ACLK_400_MCUISP RSVD DIV_ACLK_266_GPS RSVD DIV_ONENAND RSVD DIV_ACLK_133 RSVD DIV_ACLK_160 RSVD DIV_ACLK_100 RSVD DIV_ACLK_200 Bit [31:25] [24] [23:21] [20] [19:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  R  R  R  R  R  R  R Description Reserved DIVACLK_400_MCUISP Status 0 = Stable 1 = Status that the divider is changing Reserved DIVACLK_266_GPS Status 0 = Stable 1 = Status that the divider is changing Reserved DIVONENAND Status 0 = Stable 1 = Status that the divider is changing Reserved DIVACLK_133 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVACLK_160 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVACLK_100 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVACLK_200 Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-93 Exynos 4412_UM 5 Clock Management Unit 5.9.1.72 CLK_DIV_STAT_CAM0  Base Address: 0x1003_0000  Address = Base Address + 0xC620, Reset Value = 0x0000_0000 Name RSVD DIV_CSIS1 RSVD DIV_CSIS0 RSVD DIV_CAM1 RSVD DIV_CAM0 RSVD DIV_FIMC3_LCLK RSVD DIV_FIMC2_LCLK RSVD DIV_FIMC1_LCLK RSVD DIV_FIMC0_LCLK Bit [31:29] [28] [27:25] [24] [23:21] [20] [19:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  R  R  R  R  R  R  R  R Description Reserved DIVCSIS1 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVCSIS0 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVCAM1 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVCAM0 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVFIMC3_LCLK Status 0 = Stable 1 = Status that the divider is changing Reserved DIVFIMC2_LCLK Status 0 = Stable 1 = Status that the divider is changing Reserved DIVFIMC1_LCLK Status 0 = Stable 1 = Status that the divider is changing Reserved DIVFIMC0_LCLK Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-94 Exynos 4412_UM 5.9.1.73 CLK_DIV_STAT_TV  Base Address: 0x1003_0000  Address = Base Address + 0xC624, Reset Value = 0x0000_0000 Name RSVD DIV_TV_BLK Bit [31:1] [0] Type  R Description Reserved DIVTV_BLK Status 0 = Stable 1 = Status that the divider is changing 5.9.1.74 CLK_DIV_STAT_MFC  Base Address: 0x1003_0000  Address = Base Address + 0xC628, Reset Value = 0x0000_0000 Name Bit Type Description RSVD DIV_MFC [31:1] [0]  Reserved DIVMFC Status R 0 = Stable 1 = Status that the divider is changing 5.9.1.75 CLK_DIV_STAT_G3D  Base Address: 0x1003_0000  Address = Base Address + 0xC62C, Reset Value = 0x0000_0000 Name RSVD DIV_G3D Bit [31:1] [0] Type  R Description Reserved DIVG3D Status 0 = Stable 1 = Status that the divider is changing 5 Clock Management Unit Reset Value 0x0 0x0 Reset Value 0x0 0x0 Reset Value 0x0 0x0 5-95 Exynos 4412_UM 5 Clock Management Unit 5.9.1.76 CLK_DIV_STAT_LCD  Base Address: 0x1003_0000  Address = Base Address + 0xC634, Reset Value = 0x0000_0000 Name RSVD DIV_MIPI0_PRE RSVD DIV_MIPI0 RSVD DIV_MDNIE_ PWM0_PRE RSVD DIV_MDNIE_PWM0 RSVD DIV_MDNIE0 RSVD DIV_FIMD0 Bit [31:21] [20] [19:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  R  R  R  R  R  R Description Reserved DIVMIPI0_PRE Status 0 = Stable 1 = Status that the divider is changing Reserved DIVMIPI0 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVMDNIE_PWM0_PRE Status 0 = Stable 1 = Status that the divider is changing Reserved DIVMDNIE_PWM0 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVMDNIE0 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVFIMD0 Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-96 Exynos 4412_UM 5 Clock Management Unit 5.9.1.77 CLK_DIV_STAT_ISP  Base Address: 0x1003_0000  Address = Base Address + 0xC638, Reset Value = 0x0000_0000 RSVD Name DIV_UART_ISP RSVD DIV_SPI1_ISP_PRE RSVD DIV_SPI1_ISP RSVD DIV_SPI0_ISP_PRE RSVD DIV_SPI0_ISP RSVD DIV_PWM_ISP Bit [31:29] [28] [27:21] [20] [19:17] [16] [15:9] [8] [7:5] [4] [3:1] [0] Type  R  R  R  R  R  R Description Reserved DIVUART_ISP Status 0 = Stable 1 = Status that the divider is changing Reserved DIVSPI1_ISP_PRE Status 0 = Stable 1 = Status that the divider is changing Reserved DIVSPI1_ISP Status 0 = Stable 1 = Status that the divider is changing Reserved DIVSPI0_ISP_PRE Status 0 = Stable 1 = Status that the divider is changing Reserved DIVSPI0_ISP Status 0 = Stable 1 = Status that the divider is changing Reserved DIVPWM_ISP Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-97 Exynos 4412_UM 5 Clock Management Unit 5.9.1.78 CLK_DIV_STAT_MAUDIO  Base Address: 0x1003_0000  Address = Base Address + 0xC63C, Reset Value = 0x0000_0000 Name RSVD DIV_PCM0 RSVD DIV_AUDIO0 Bit [31:5] [4] [3:1] [0] Type  R  R Description Reserved DIVPCM0 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVAUDIO0 Status 0 = Stable 1 = Status that the divider is changing 5.9.1.79 CLK_DIV_STAT_FSYS0  Base Address: 0x1003_0000  Address = Base Address + 0xC640, Reset Value = 0x0000_0000 Name Bit Type Description RSVD DIV_MIPIHSI RSVD [31:21] [20] [19:0]  Reserved DIVMIPIHSI Status R 0 = Stable 1 = Status that the divider is changing  Reserved Reset Value 0x0 0x0 0x0 0x0 Reset Value 0x0 0x0 0x0 5-98 Exynos 4412_UM 5 Clock Management Unit 5.9.1.80 CLK_DIV_STAT_FSYS1  Base Address: 0x1003_0000  Address = Base Address + 0xC644, Reset Value = 0x0000_0000 Name RSVD DIV_MMC1_PRE RSVD DIV_MMC1 RSVD DIV_MMC0_PRE RSVD DIV_MMC0 Bit [31:25] [24] [23:17] [16] [15:9] [8] [7:1] [0] Type  R  R  R  R Description Reserved DIVMMC1_PRE Status 0 = Stable 1 = Status that the divider is changing Reserved DIVMMC1 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVMMC0_PR Status 0 = Stable 1 = Status that the divider is changing Reserved DIVMMC0 Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-99 Exynos 4412_UM 5 Clock Management Unit 5.9.1.81 CLK_DIV_STAT_FSYS2  Base Address: 0x1003_0000  Address = Base Address + 0xC648, Reset Value = 0x0000_0000 Name RSVD DIV_MMC3_PRE RSVD DIV_MMC3 RSVD DIV_MMC2_PRE RSVD DIV_MMC2 Bit [31:25] [24] [23:17] [16] [15:9] [8] [7:1] [0] Type  R  R  R  R Description Reserved DIVMMC3_PRE Status 0 = Stable 1 = Status that the divider is changing Reserved DIVMMC3 Stats 0 = Stable 1 = Status that the divider is changing Reserved DIVMMC2_PRE Status 0 = Stable 1 = Status that the divider is changing Reserved DIVMMC2 Status 0 = Stable 1 = Status that the divider is changing 5.9.1.82 CLK_DIV_STAT_FSYS3  Base Address: 0x1003_0000  Address = Base Address + 0xC64C, Reset Value = 0x0000_0000 Name Bit Type Description RSVD DIV_MMC4_PRE [31:9] [8]  Reserved DIVMMC4_PRE Status R 0 = Stable 1 = Status that the divider is changing RSVD DIV_MMC4 [7:1]  Reserved DIVMMC4 Status [0] R 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x0 0x0 0x0 0x0 5-100 Exynos 4412_UM 5 Clock Management Unit 5.9.1.83 CLK_DIV_STAT_PERIL0  Base Address: 0x1003_0000  Address = Base Address + 0xC650, Reset Value = 0x0000_0000 Name RSVD DIV_UART4 RSVD DIV_UART3 RSVD DIV_UART2 RSVD DIV_UART1 RSVD DIV_UART0 Bit [31:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  R  R  R  R  R Description Reserved DIVUART4 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVUART3 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVUART2 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVUART1 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVUART0 Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-101 Exynos 4412_UM 5 Clock Management Unit 5.9.1.84 CLK_DIV_STAT_PERIL1  Base Address: 0x1003_0000  Address = Base Address + 0xC654, Reset Value = 0x0000_0000 Name RSVD DIV_SPI1_PRE RSVD DIV_SPI1 RSVD DIV_SPI0_PRE RSVD DIV_SPI0 Bit [31:25] [24] [23:17] [16] [15:9] [8] [7:1] [0] Type  R  R  R  R Description Reserved DIVSPI1_PRE Status 0 = Stable 1 = Status that the divider is changing Reserved DIVSPI1 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVSPI0_PRE Status 0 = Stable 1 = Status that the divider is changing Reserved DIVSPI0 Status 0 = Stable 1 = Status that the divider is changing 5.9.1.85 CLK_DIV_STAT_PERIL2  Base Address: 0x1003_0000  Address = Base Address + 0xC658, Reset Value = 0x0000_0000 Name Bit Type Description RSVD DIV_SPI2_PRE [31:9] [8]  Reserved DIVSPI2_PRE Status R 0 = Stable 1 = Status that the divider is changing RSVD DIV_SPI2 [7:1]  Reserved DIVSPI2 Status [0] R 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value 0x0 0x0 0x0 0x0 5-102 Exynos 4412_UM 5 Clock Management Unit 5.9.1.86 CLK_DIV_STAT_PERIL3  Base Address: 0x1003_0000  Address = Base Address + 0xC65C, Reset Value = 0x0000_0000 Name RSVD DIV_SLIMBUS RSVD Bit [31:5] [4] [3:0] Type  R  Description Reserved DIVSLIMBUS Status 0 = Stable 1 = Status that the divider is changing Reserved 5.9.1.87 CLK_DIV_STAT_PERIL4  Base Address: 0x1003_0000  Address = Base Address + 0xC660, Reset Value = 0x0000_0000 Name RSVD DIV_PCM2 RSVD DIV_AUDIO2 RSVD DIV_PCM1 RSVD DIV_AUDIO1 Bit [31:21] [20] [19:17] [16] [15:5] [4] [3:1] [0] Type  R  R  R  R Description Reserved DIVPCM2 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVAUDIO2 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVPCM1 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVAUDIO1 Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-103 Exynos 4412_UM 5 Clock Management Unit 5.9.1.88 CLK_DIV_STAT_PERIL5  Base Address: 0x1003_0000  Address = Base Address + 0xC664, Reset Value = 0x0000_0000 Name RSVD DIV_I2S2 RSVD DIV_I2S1 Bit [31:9] [8] [7:1] [0] Type  R  R Description Reserved DIVI2S2 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVI2S1 Status 0 = Stable 1 = Status that the divider is changing 5.9.1.89 CLK_DIV_STAT_CAM1  Base Address: 0x1003_0000  Address = Base Address + 0xC668, Reset Value = 0x0000_0000 Name Bit Type Description RSVD DIV_JPEG [31:1] [0]  Reserved DIVJPEG Status R 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 Reset Value 0x0 0x0 5-104 Exynos 4412_UM 5 Clock Management Unit 5.9.1.90 CLKDIV2_STAT  Base Address: 0x1003_0000  Address = Base Address + 0xC680, Reset Value = 0x0000_0000 Name RSVD GPS_BLK RSVD TV_BLK RSVD LCD_BLK RSVD CAM_BLK RSVD FSYS_BLK Bit [31:25] [24] [23:21] [20] [19:13] [12] [11:5] [4] [3:1] [0] Type  R  R  R  R  R Description Reserved PCLK Divider Status in TV_BLK 0 = Stable 1 = Status that the divider is changing Reserved PCLK Divider Status in TV_BLK 0 = Stable 1 = Status that the divider is changing Reserved PCLK Divider Status in LCD_BLK for 160 MHz domain 0 = Stable 1 = Status that the divider is changing Reserved PCLK Divider Status in CAM_BLK 0 = Stable 1 = Status that the divider is changing Reserved PCLK Divider Status in FSYS_BLK 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-105 Exynos 4412_UM 5.9.1.91 CLK_GATE_BUS_FSYS1  Address = 0x1003_C744, Reset Value = 0xFFFF_FFFF Name RSVD Bit [31:23] PCLK_ASYNCAXIS _GPS_FSYSD [22] PCLK_AXI_FSYSS [21] PCLK_AXI_FSYSD [20] RSVD [19:18] PCLK_PPMUFILE [17] PCLK_ADC RSVD [16] [15:0] Type – RW RW RW – RW RW – Description Reserved Gating APB clock for ASYNCAXIS_GPS_FSYSD 0 = Mask 1 = Pass Gating APB clock for AXI_FSYSS 0 = Mask 1 = Pass Gating APB clock for AXI_FSYSD 0 = Mask 1 = Pass Reserved Gating APB clock for PPMUFILE 0 = Mask 1 = Pass Gating APB clock for FSYS ADC 0 = Mask 1 = Pass Reserved 5 Clock Management Unit Reset Value 0x1FF 0x1 0x1 0x1 0x3 0x1 0x1 0xFFFF 5-106 Exynos 4412_UM 5 Clock Management Unit 5.9.1.92 CLK_GATE_IP_CAM  Base Address: 0x1003_0000  Address = Base Address + 0xC920, Reset Value = 0xFFFF_FFFF Name RSVD RSVD CLK_PIXELASYN CM1 Bit [31:18] [19] [18] CLK_PIXELASYN CM0 [17] CLK_PPMUCAMIF [16] RSVD [12:15] CLK_SMMUJPEG [11] CLK_SMMUFIMC3 [10] CLK_SMMUFIMC2 [9] CLK_SMMUFIMC1 [8] CLK_SMMUFIMC0 [7] CLK_JPEG [6] CLK_CSIS1 [5] CLK_CSIS0 [4] CLK_FIMC3 [3] Type – – RW RW RW – RW RW RW RW RW RW RW RW RW Description Reserved Reserved Gating all clocks for PIXELASYNCM1 0 = Mask 1 = Pass Gating all clocks for PIXELASYNCM0 0 = Mask 1 = Pass Gating all clocks for PPMUCAMIF 0 = Mask 1 = Pass Reserved Gating all clocks for SMMUJPEG 0 = Mask 1 = Pass Gating all clocks for SMMUFIMC3 0 = Mask 1 = Pass Gating all clocks for SMMUFIMC2 0 = Mask 1 = Pass Gating all clocks for SMMUFIMC1 0 = Mask 1 = Pass Gating all clocks for SMMUFIMC0 0 = Mask 1 = Pass Gating all clocks for JPEG 0 = Mask 1 = Pass Gating all clocks for CSIS1 0 = Mask 1 = Pass Gating all clocks for CSIS0 0 = Mask 1 = Pass Gating all clocks for FIMC3 0 = Mask 1 = Pass Reset Value 0xFFF 0x1 0x1 0x1 0x1 0xF 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-107 Exynos 4412_UM Name CLK_FIMC2 CLK_FIMC1 CLK_FIMC0 Bit Type Description Gating all clocks for FIMC2 [2] RW 0 = Mask 1 = Pass Gating all clocks for FIMC1 [1] RW 0 = Mask 1 = Pass Gating all clocks for FIMC0 [0] RW 0 = Mask 1 = Pass 5 Clock Management Unit Reset Value 0x1 0x1 0x1 5-108 Exynos 4412_UM 5.9.1.93 CLK_GATE_IP_TV  Base Address: 0x1003_0000  Address = Base Address + 0xC924, Reset Value = 0xFFFF_FFFF Name RSVD CLK_PPMUTV CLK_SMMUTV CLK_HDMI RSVD CLK_MIXER CLK_VP Bit [31:6] [5] [4] [3] [2] [1] [0] Type  RW RW RW  RW RW Description Reserved Gating all clocks for PPMUTV 0 = Mask 1 = Pass Gating all clocks for SMMUTV 0 = Mask 1 = Pass Gating all clocks for HDMI link 0 = Mask 1 = Pass Reserved Gating all clocks for MIXER 0 = Mask 1 = Pass Gating all clocks for VP 0 = Mask 1 = Pass 5 Clock Management Unit Reset Value 0x3FFFFFF 0x1 0x1 0x1 0x1 0x1 0x1 5-109 Exynos 4412_UM 5 Clock Management Unit 5.9.1.94 CLK_GATE_IP_MFC  Base Address: 0x1003_0000  Address = Base Address + 0xC928, Reset Value = 0xFFFF_FFFF Name RSVD CLK_PPMUMFC_R CLK_PPMUMFC_L CLK_SMMUMFC_R CLK_SMMUMFC_L CLK_MFC Bit [31:5] [4] [3] [2] [1] [0] Type  RW RW RW RW RW Description Reserved Gating all clocks for PPMUMFC_R 0 = Mask 1 = Pass Gating all clocks for PPMUMFC_L 0 = Mask 1 = Pass Gating all clocks for SMMUMFC_R 0 = Mask 1 = Pass Gating all clocks for SMMUMFC_L 0 = Mask 1 = Pass Gating all clocks for MFC 0 = Mask 1 = Pass Reset Value 0x7FFFFFF 0x1 0x1 0x1 0x1 0x1 5-110 Exynos 4412_UM 5 Clock Management Unit 5.9.1.95 CLK_GATE_IP_G3D  Base Address: 0x1003_0000  Address = Base Address + 0xC92C, Reset Value = 0xFFFF_FFFF Name RSVD RSVD CLK_PPMUG3D CLK_G3D Bit [31:3] [2] [1] [0] Type  – RW RW Description Reserved Reserved Gating all clocks for PPMUG3D 0 = Mask 1 = Pass Gating all clocks for G3D 0 = Mask 1 = Pass 5.9.1.96 CLK_GATE_IP_LCD  Base Address: 0x1003_0000  Address = Base Address + 0xC934, Reset Value = 0xFFFF_FFFF Name RSVD CLK_PPMULCD0 CLK_SMMUFIMD0 CLK_DSIM0 CLK_MDNIE0 CLK_MIE0 CLK_FIMD0 Bit [31:6] [5] [4] [3] [2] [1] [0] Type  RW RW RW RW RW RW Description Reserved Gating all clocks for PPMULCD0 0 = Mask 1 = Pass Gating all clocks for SMMUFIMD0 0 = Mask 1 = Pass Gating all clocks for DSIM0 0 = Mask 1 = Pass Gating all clocks for MDNIE0 0 = Mask 1 = Pass Gating all clocks for MIE0 0 = Mask 1 = Pass Gating all clocks for FIMD0 0 = Mask 1 = Pass Reset Value 0x1FFFFFFF 0x1 0x1 0x1 Reset Value 0x3FFFFFF 0x1 0x1 0x1 0x1 0x1 0x1 5-111 Exynos 4412_UM 5 Clock Management Unit 5.9.1.97 CLK_GATE_IP_ISP  Base Address: 0x1003_0000  Address = Base Address + 0xC938, Reset Value = 0xFFFF_FFFF Name RSVD CLK_UART_ISP_SCLK CLK_SPI1_ISP_SCLK CLK_SPI0_ISP_SCLK CLK_PWM_ISP_SCLK Bit [31:4] [3] [2] [1] [0] Type  RW RW RW RW Description Reserved Gating SCLK clocks for UART_ISP 0 = Mask 1 = Pass Gating SCLK clocks for SPI1_ISP 0 = Mask 1 = Pass Gating SCLK clocks for SPI0_ISP 0 = Mask 1 = Pass Gating SCLK clocks for PWM_ISP 0 = Mask 1 = Pass Reset Value 0xFFFFFFF 0x1 0x1 0x1 0x1 5-112 Exynos 4412_UM 5.9.1.98 CLK_GATE_IP_FSYS  Base Address: 0x1003_0000  Address = Base Address + 0xC940, Reset Value = 0xFFFF_FFFF Name RSVD CLK_PPMUFILE Bit [31:18] [17] CLK_NFCON [16] CLK_ONENAND [15] RSVD [14] CLK_USBDEVICE [13] CLK_USBHOST [12] CLK_SROMC [11] CLK_MIPIHSI [10] CLK_SDMMC4 [9] CLK_SDMMC3 [8] CLK_SDMMC2 [7] CLK_SDMMC1 [6] CLK_SDMMC0 [5] CLK_TSI [4] Type – RW RW RW  RW RW RW RW RW RW RW RW RW RW Description Reserved Gating all clocks for PPMUFILE 0 = Mask 1 = Pass Gating all clocks for NFCON 0 = Mask 1 = Pass Gating all clocks for ONENAND 0 = Mask 1 = Pass Reserved Gating all clocks for USB Device 0 = Mask 1 = Pass Gating all clocks for USB HOST 0 = Mask 1 = Pass Gating all clocks for SROM 0 = Mask 1 = Pass Gating all clocks for MIPIHSI 0 = Mask 1 = Pass Gating all clocks for SDMMC4 0 = Mask 1 = Pass Gating all clocks for SDMMC3 0 = Mask 1 = Pass Gating all clocks for SDMMC2 0 = Mask 1 = Pass Gating all clocks for SDMMC1 0 = Mask 1 = Pass Gating all clocks for SDMMC0 0 = Mask 1 = Pass Gating all clocks for TSI 5-113 5 Clock Management Unit Reset Value 0x1FFF 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Exynos 4412_UM Name RSVD CLK_PDMA1 CLK_PDMA0 Bit Type Description 0 = Mask 1 = Pass [3:2]  Reserved Gating all clocks for PDMA1 [1] RW 0 = Mask 1 = Pass Gating all clocks for PDMA0 [0] RW 0 = Mask 1 = Pass 5 Clock Management Unit Reset Value 0x3 0x1 0x1 5-114 Exynos 4412_UM 5.9.1.99 CLK_GATE_IP_GPS  Base Address: 0x1003_0000  Address = Base Address + 0xC94C, Reset Value = 0xFFFF_FFFF Name RSVD RSVD CLK_PPMUGPS CLK_SMMUGPS CLK_GPS Bit [31:4] [3] [2] [1] [0] Type  – RW RW RW Description Reserved Reserved Gating all clocks for PPMUGPS 0 = Mask 1 = Pass Gating all clocks for SMMUGPS 0 = Mask 1 = Pass Gating all clocks for GPS 0 = Mask 1 = Pass 5 Clock Management Unit Reset Value 0xFFFFFFF 0x1 0x1 0x1 0x1 5-115 Exynos 4412_UM 5.9.1.100 CLK_GATE_IP_PERIL  Base Address: 0x1003_0000  Address = Base Address + 0xC950, Reset Value = 0xFFFF_FFFF Name RSVD CLK_AC97 CLK_SPDIF CLK_SLIMBUS CLK_PWM CLK_PCM2 CLK_PCM1 CLK_I2S2 CLK_I2S1 RSVD CLK_SPI2 CLK_SPI1 CLK_SPI0 RSVD CLK_I2CHDMI Bit [31:28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] Type  RW RW RW RW RW RW RW RW  RW RW RW  RW Description Reserved Gating all clocks for AC97 0 = Mask 1 = Pass Gating all clocks for SPDIF 0 = Mask 1 = Pass Gating all clocks for Slimbus 0 = Mask 1 = Pass Gating all clocks for PWM 0 = Mask 1 = Pass Gating all clocks for PCM2 0 = Mask 1 = Pass Gating all clocks for PCM1 0 = Mask 1 = Pass Gating all clocks for I2S2 0 = Mask 1 = Pass Gating all clocks for I2S1 0 = Mask 1 = Pass Reserved Gating all clocks for SPI2 0 = Mask 1 = Pass Gating all clocks for SPI1 0 = Mask 1 = Pass Gating all clocks for SPI0 0 = Mask 1 = Pass Reserved Gating all clocks for I2CHDMI 0 = Mask 1 = Pass 5-116 5 Clock Management Unit Reset Value 0xF 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Exynos 4412_UM Name CLK_I2C7 CLK_I2C6 CLK_I2C5 CLK_I2C4 CLK_I2C3 CLK_I2C2 CLK_I2C1 CLK_I2C0 RSVD CLK_UART4 CLK_UART3 CLK_UART2 CLK_UART1 CLK_UART0 Bit Type Description Gating all clocks for I2C7 [13] RW 0 = Mask 1 = Pass Gating all clocks for I2C6 [12] RW 0 = Mask 1 = Pass Gating all clocks for I2C5 [11] RW 0 = Mask 1 = Pass Gating all clocks for I2C4 [10] RW 0 = Mask 1 = Pass Gating all clocks for I2C3 [9] RW 0 = Mask 1 = Pass Gating all clocks for I2C2 [8] RW 0 = Mask 1 = Pass Gating all clocks for I2C1 [7] RW 0 = Mask 1 = Pass Gating all clocks for I2C0 [6] RW 0 = Mask 1 = Pass [5]  Reserved Gating all clocks for UART4 [4] RW 0 = Mask 1 = Pass Gating all clocks for UART3 [3] RW 0 = Mask 1 = Pass Gating all clocks for UART2 [2] RW 0 = Mask 1 = Pass Gating all clocks for UART1 [1] RW 0 = Mask 1 = Pass Gating all clocks for UART0 [0] RW 0 = Mask 1 = Pass 5 Clock Management Unit Reset Value 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-117 Exynos 4412_UM 5 Clock Management Unit 5.9.1.101 CLK_GATE_BLOCK  Base Address: 0x1003_0000  Address = Base Address + 0xC970, Reset Value = 0xFFFF_FFFF Name RSVD CLK_GPS RSVD CLK_LCD CLK_G3D CLK_MFC CLK_TV CLK_CAM Bit [31:8] [7] [6:5] [4] [3] [2] [1] [0] Type  RW  RW RW RW RW RW Description Reserved Gating all clocks for GPS_BLK (GPS) 0 = Mask 1 = Pass Reserved Gating all clocks for LCD_BLK (FIMD0, MIE0, and DSIM0) 0 = Mask 1 = Pass Gating all clocks for G3D_BLK (G3D) 0 = Mask 1 = Pass Gating all clocks for MFC_BLK (MFC) 0 = Mask 1 = Pass Gating all clocks for TV_BLK (VP, MIXER, TVENC, and HDMI) 0 = Mask 1 = Pass Gating all clocks for CAM_BLK (FIMC0, FIMC1, FIMC2, and FIMC3) 0 = Mask 1 = Pass Reset Value 0xFFFFFF 0x1 0x3 0x1 0x1 0x1 0x1 0x1 5-118 Exynos 4412_UM 5 Clock Management Unit 5.9.1.102 CLKOUT_CMU_TOP  Base Address: 0x1003_0000  Address = Base Address + 0xCA00, Reset Value = 0x0001_0000 Name RSVD ENB_CLKOUT RSVD DIV_RATIO RSVD MUX_SEL Bit [31:17] [16] [15:14] [13:8] [7:5] [4:0] Type  RW  RW  RW Description Reserved Enable CLKOUT 0 = Disables 1 = Enables Reserved Divide Ratio Divide ratio = DIV_RATIO + 1 Reserved MUX Selection 00000 = EPLL_FOUT 00001 = VPLL_FOUT 00010 = SCLK_HDMI24M 00011 = SCLK_USBPHY0 00101 = SCLK_HDMIPHY 00110 = AUDIOCDCLK0 00111 = AUDIOCDCLK1 01000 = AUDIOCDCLK2 01001 = SPDIF_EXTCLK 01010 = ACLK_160 01011 = ACLK_133 01100 = ACLK_200 01101 = ACLK_100 01110 = SCLK_MFC 01111 = SCLK_G3D 10000 = ACLK_400_MCUISP 10001 = CAM_A_PCLK 10010 = CAM_B_PCLK 10011 = S_RXBYTECLKHS0_2L 10100 = S_RXBYTECLKHS0_4L 10101 = RX_HALF_BYTE_CLK_CSIS0 10110 = RX_HALF_BYTE_CLK_CSIS1 10111 = SCLK_JPEG 11000 = SCLK_PWM_ISP 11001 = SCLK_SPI0_ISP 11010 = SCLK_SPI1_ISP 11011 = SCLK_UART_ISP 11100 = SCLK_MIPIHSI 11101 = SCLK_HDMI 11110 = SCLK_FIMD0 11111 = SCLK_PCM0 Reset Value 0x0 0x1 0x0 0x0 0x0 0x0 5-119 Exynos 4412_UM 5 Clock Management Unit 5.9.1.103 CLKOUT_CMU_TOP_DIV_STAT  Base Address: 0x1003_0000  Address = Base Address + 0xCA04, Reset Value = 0x0000_0000 Name RSVD DIV_STAT Bit [31:1] [0] Type Description  Reserved DIVCLKOUT Status R 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 5.9.1.104 MPLL_LOCK  Base Address: 0x1004_0000  Address = Base Address + 0x0008, Reset Value = 0x0000_0FFF Name Bit Type Description RSVD PLL_LOCKTIME [31:16] [15:0]  Reserved Required period to generate a stable clock output Set (270cycles  PDIV) to PLL_LOCKTIME for the PLL maximum lock time. RW 1 cycle = 1/FREF=1/(FIN/PDIV) The maximum PLL lock time is 22.5 usec where FIN is 24 MHz, PDIV is 2 and PLL_LOCKTIME is 540. Reset Value 0x0 0xFFF The maximum lock time means the waiting time for locking in the worst case. Therefore, the user of this PLL must wait for more than the maximum lock time unconditionally before the PLL is locked. (Waiting time before locking ≥ the maximum locktime) 5-120 Exynos 4412_UM 5 Clock Management Unit 5.9.1.105 MPLL_CON0  Base Address: 0x1004_0000  Address = Base Address + 0x0108, Reset Value = 0x0064_0300 Name ENABLE RSVD LOCKED RSVD FSEL RSVD MDIV RSVD PDIV RSVD SDIV Bit [31] [30] [29] [28] [27] [26] [25:16] [15:14] [13:8] [7:3] [2:0] Type RW  R  RW  RW  RW  RW Description PLL Enable Control 0 = Disables 1 = Enables Reserved PLL Locking Indication 0 = Unlocks 1 = Locks If ENABLE_LOCK_DET = 0, then this field is set to 1 after the locking time. The lock-time is set using the MPLL_LOCK SFR register. If ENABLE_LOCK_DET = 1, then this field is set when the hardware lock detector meets the PLL locking condition. This bit is Read only. Reserved Monitors Frequency Select Pin 0 = FVCO_OUT = FREF 1 = FVCO_OUT = FVCO Reserved PLL M Divide Value Reserved PLL P Divide Value Reserved PLL S Divide Value Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x64 0x0 0x3 0x0 0x0 The reset value of MPLL_CON0 generates a 800 MHz output clock for an input clock frequency of 24 MHz. The equation to calculate the output frequency is: FOUT = MDIV  FIN/(PDIV  2SDIV): 21.9 MHz  FOUT  1400 MHz  The conditions MDIV, PDIV, SDIV for APLL and MPLL should meet are:PDIV: 1  PDIV  63  MDIV: 64  MDIV  1023  SDIV: 0  SDIV  5  Fref = FIN/PDIV) Fref should fall in the range of: 2 MHz  Fref  12 MHzFVCO = MDIV  FIN/PDIV) FVCO should fall in the range of:700 MHz  FVCO  1400 MHz Refer to the section 5.3.1 Recommended PLL PMS Value for APLL and MPLL for recommended PMS values. 5-121 Exynos 4412_UM 5 Clock Management Unit 5.9.1.106 MPLL_CON1  Base Address: 0x1004_0000  Address = Base Address + 0x010C, Reset Value = 0x0080_3800 Name RSVD RESV1 RESV0 BYPASS DCC_ENB AFC_ENB RSVD RSVD FEED_EN LOCK_CON_OUT LOCK_CON_IN LOCK_CON_DLY RSVD AFC Bit [31:25] [24] [23] [22] [21] [20] [19:18] [17] [16] [15:14] [13:12] [11:8] [7:5] [4:0] Type  RW RW RW RW RW   RW RW RW RW  RW Description Reserved Specifies status of Linear-Region Detector (LDR) when it detects a low signal Specifies VCO range boost-up when the signal is high. If BYPASS = 1, then it enables bypass mode (FOUT = FIN) If BYPASS = 0, then the PLL3500X operates normally. Decides whether DCC is enabled or not. 0 = Enables DCC 1 = Disables DCC It is an active low signal. Decides whether AFC is enabled or not. 0 = Enables AFC 1 = Disables AFC It is an active low signal. Reserved Reserved Enable pin for FEED_OUT Specifies lock detector settings of the output margin. Specifies lock detector settings of the input margin. Specifies lock detector settings of the detection resolution. Reserved AFC value Reset Value 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 0x8 0x0 0x0 Refer to the section 5.3.1 Recommended PLL PMS Value for APLL and MPLL for recommended AFC_ENB and AFC values. NOTE: The other PLL control inputs should be set as: RESV1 = 0 RESV0 = 0 DCC_ENB = 1 EXTAFC = 0 LOCK_CON_IN = 3 LOCK_CON_OUT = 0 LOCK_CON_DLY = 8 AFC_ENB = 0 5-122 Exynos 4412_UM 5 Clock Management Unit 5.9.1.107 CLK_SRC_DMC  Base Address: 0x1004_0000  Address = Base Address + 0x0200, Reset Value = 0x0001_0000 Name RSVD MUX_G2D_ACP_S EL RSVD MUX_G2D_ACP_1 _SEL RSVD MUX_G2D_ACP_0 _SEL MUX_PWI_SEL RSVD MUX_MPLL_SEL RSVD MUX_DPHY_SEL RSVD MUX_DMC_BUS _SEL RSVD Bit [31:29] [28] [27:25] [24] [23:21] [20] [19:16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] Type  RW – RW – RW RW  RW  RW  RW  Description Reserved Control MUXG2D_ACP, which is the source clock of G2D_ACP core 0 = MOUTG2D_ACP_0 1 = MOUTG2D_ACP_1 Reserved Control MUXG2D_ACP_1, which is the source clock of G2D_ACP core 0 = SCLKEPLL 1 = SCLKVPLL Reserved Control MUXG2D_ACP_0, which is the source clock of G2D_ACP core 0 = SCLKMPLL 1 = SCLKAPLL Controls MUXPWI 0000 = XXTI 0001 = XusbXTI 0010 = SCLK_HDMI24M 0011 = SCLK_USBPHY0 0100 = SCLK_USBPHY1 0101 = SCLK_HDMIPHY 0110 = SCLKMPLL 0111 = SCLKEPLL 1000 = SCLKVPLL Others = Reserved MUXPWI is the clock source of PWI. Reserved Controls MUXMPLL 0 = FINPLL 1 = MOUTMPLLFOUT Reserved Controls MUXDPHY 0 = SCLKMPLL 1 = SCLKAPLL Reserved Controls MUXDMC_BUS 0 = SCLKMPLL 1 = SCLKAPLL Reserved Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-123 Exynos 4412_UM Name MUX_C2C_SEL Bit Type Description Controls MUXC2C [0] RW 0 = SCLKMPLL 1 = SCLKAPLL 5 Clock Management Unit Reset Value 0x0 5-124 Exynos 4412_UM 5.9.1.108 CLK_SRC_MASK_DMC  Base Address: 0x1004_0000  Address = Base Address + 0x0300, Reset Value = 0x0001_0000 Name RSVD PWI_MASK RSVD Bit [31:17] [16] [15:0] Type  RW  Description Reserved Mask output clock of MUXPWI 0 = Mask 1 = Unmask Reserved 5 Clock Management Unit Reset Value 0x0 0x1 0x0 5-125 Exynos 4412_UM 5 Clock Management Unit 5.9.1.109 CLK_MUX_STAT_DMC  Base Address: 0x1004_0000  Address = Base Address + 0x0400, Reset Value = 0x1110_1111 Name RSVD G2D_ACP_SEL RSVD G2D_ACP_1_SEL RSVD G2D_ACP_0_SEL RSVD MPLL_SEL DPHY_SEL RSVD DMC_BUS_SEL RSVD C2C_SEL Bit [31] [30:28] [27] [26:24] [23] [22:20] [19:15] [14:12] [10:8] [7] [6:4] [3] [2:0] Type  R – R – R  R R  R – R Description Reserved Selection signal status of MUXG2D_ACP 001 = MOUTG2D_ACP_0 010 = MOUTG2D_ACP_1 1xx = On changing Reserved Selection signal status of MUXG2D_ACP_1 001 = SCLKEPLL 010 = SCLKVPLL 1xx = On changing Reserved Selection signal status of MUXG2D_ACP_0 001 = SCLKMPLL 010 = SCLKAPLL 1xx = On changing Reserved Selection signal status of MUXMPLL 001 = FINPLL 010 = MOUTMPLLFOUT 1xx = Status that the mux is changing Selection signal status of MUXDMC0 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXDMC_BUS 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXC2C 001 = SCLKMPLL 010 = SCLKAPLL 1xx = Status that the mux is changing Reset Value 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x1 0x0 0x1 0x0 0x1 5-126 Exynos 4412_UM 5 Clock Management Unit 5.9.1.110 CLK_DIV_DMC0  Base Address: 0x1004_0000  Address = Base Address + 0x0500, Reset Value = 0x0000_0000 Name RSVD DMCP_RATIO RSVD DMCD_RATIO RSVD DMC_RATIO RSVD DPHY_RATIO RSVD ACP_PCLK_RATIO RSVD ACP_RATIO Bit [31:23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Type  RW  RW  RW  RW  RW  RW Description Reserved DIVCK133 Clock Divider Ratio ACLK_DMCP = ACLK_DMCD/(DMCP_RATIO + 1) Reserved DIVDMCD Clock Divider Ratio ACLK_DMCD = DOUTDMC/(DMCD_RATIO + 1) Reserved DIVDMC Clock Divider Ratio DOUTDMC = MOUTDMC_BUS/(DMC_RATIO + 1) Reserved DIVDPHY Clock Divider Ratio SCLK_DPHY = MOUTDPHY/(DPHY_RATIO + 1) Reserved DIVACP Clock Divider Ratio PCLK_ACP = ACLK_ACP/(ACP_PCLK_RATIO + 1) Reserved DIVACP Clock Divider Ratio ACLK_ACP = MOUTDMC_BUS/(ACP_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-127 Exynos 4412_UM 5 Clock Management Unit 5.9.1.111 CLK_DIV_DMC1  Base Address: 0x1004_0000  Address = Base Address + 0x0504, Reset Value = 0x0000_1000 Name RSVD DPM_RATIO RSVD DVSEM_RATIO RSVD C2C_ACLK_RATIO PWI_RATIO RSVD C2C_RATIO G2D_ACP_RATIO Bit [31] [30:24] [23] [22:16] [15] [14:12] [11:8] [7] [6:4] [3:0] Type  RW  RW  RW RW  RW RW Description Reserved DIVDPM Clock Divider Ratio It decides frequency of DPM channel clock. Reserved DIVDVSEM Clock Divider Ratio It decides frequency for PWM frame time slot in DVS emulation mode. Reserved C2C_ACLK Clock Divider Ratio ACLK_C2C = [MOUTC2C_ACLK/(C2C_ACLK_RATIO + 1)] DIVPWI Clock Divider Ratio SCLK_PWI = MOUTPWI/(PWI_RATIO + 1) Reserved C2C clock divider ratio SCLK_C2C = MOUTC2C/(C2C_RATIO + 1) DIVG2D_ACP clock divider ratio SCLK_G2D_ACP= MOUTG2D_ACP/(G2D_ACP_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x0 5-128 Exynos 4412_UM 5 Clock Management Unit 5.9.1.112 CLK_DIV_STAT_DMC0  Base Address: 0x1004_0000  Address = Base Address + 0x0600, Reset Value = 0x0000_0000 Name RSVD DIV_DMCP RSVD DIV_DMCD RSVD DIV_DMC RSVD DIV_DPHY RSVD DIV_ACP_PCLK RSVD DIV_ACP Bit [31:21] [20] [19:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  R  R  R  R  R  R Description Reserved DIVDMCP Status 0 = Stable 1 = Status that the divider is changing Reserved DIVDMCD Status 0 = Stable 1 = Status that the divider is changing Reserved DIVDMC Status 0 = Stable 1 = Status that the divider is changing Reserved DIVDPHY Status 0 = Stable 1 = Status that the divider is changing Reserved DIVACP_PCLK Status 0 = Stable 1 = Status that the divider is changing Reserved DIVACP Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-129 Exynos 4412_UM 5 Clock Management Unit 5.9.1.113 CLK_DIV_STAT_DMC1  Base Address: 0x1004_0000  Address = Base Address + 0x0604, Reset Value = 0x0000_0000 Name RSVD DIV_DPM RSVD DIV_DVSEM RSVD DIV_C2C_ACLK RSVD DIV_PWI RSVD DIV_C2C RSVD DIV_G2D_ACP Bit [31:25] [24] [23:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  R  R  R  R  R R Description Reserved DIVDPM Status 0 = Stable 1 = Status that the divider is changing Reserved DIVDVSEM Status 0 = Stable 1 = Status that the divider is changing Reserved DIVC2C_ACLK Status 0 = Stable 1 = Status that the divider is changing Reserved DIVPWI Status 0 = Stable 1 = Status that the divider is changing Reserved DIVC2C status 0 = Stable 1 = Divider is changing Reserved DIVG2D_ACP status 0 = Stable 1 = Divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-130 Exynos 4412_UM 5 Clock Management Unit 5.9.1.114 CLK_GATE_IP_DMC  Base Address: 0x1004_0000  Address = Base Address + 0x0900, Reset Value = 0xFFFF_FFFF Name Bit CLK_GPIOC2C [31] RSVD CLK_ASYNC_CPU _XIUR [30:29] [28] CLK_ASYNC_C2C _XIUL [27] CLK_C2C [26] RSVD [25] CLK_SMMUG2D _ACP [24] CLK_G2D_ACP [23] CLK_ASYNC_GDR [22] CLK_ASYNC_GDL [21] CLK_GIC [20] RSVD [19] CLK_IEM_IEC [18] CLK_IEM_APC [17] CLK_PPMUACP [16] Type RW – RW RW RW – RW RW RW RW RW  RW RW RW Description Gating all clocks for GPIOC2C 0 = Mask 1 = Pass Reserved Gating all clocks for ASYNC_CPU_XIUR 0 = Mask 1 = Pass Gating all clocks for ASYNC_C2C_XIUL 0 = Mask 1 = Pass Gating all clocks for C2C 0 = Mask 1 = Pass Reserved Gating all clocks for SMMUG2D_ACP 0 = Mask 1 = Pass Gating all clocks for G2D_ACP 0 = Mask 1 = Pass Gating all clocks for ASYNC_GDR 0 = Mask 1 = Pass Gating all clocks for ASYNC_GDL 0 = Mask 1 = Pass Gating all clocks for GIC 0 = Mask 1 = Pass Reserved Gating all clocks for IEM IEC 0 = Mask 1 = Pass Gating all clocks for IEM APC 0 = Mask 1 = Pass Gating all clocks for PPMUCPU 0 = Mask 1 = Pass Reset Value 0x1 0x3 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-131 Exynos 4412_UM 5 Clock Management Unit Name RSVD CLK_ID_ REMAPPER CLK_SMMUSSS RSVD CLK_PPMUCPU CLK_PPMUDMC1 CLK_PPMUDMC0 RSVD CLK_FBMDMC1 CLK_FBMDMC0 CLK_SSS RSVD CLK_INT_COMB RSVD CLK_DREX2 Bit [15:14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW  RW RW RW  RW RW RW  RW  RW Description Reserved Gating all clocks for ID_REMAPPER 0 = Mask 1 = Pass Gating all clocks for SMMUSSS 0 = Mask 1 = Pass Reserved Gating all clocks for PPMUCPU 0 = Mask 1 = Pass Gating all clocks for PPMUDMC1 0 = Mask 1 = Pass Gating all clocks for PPMUDMC0 0 = Mask 1 = Pass Reserved Gating all clocks for FBMDMC1 0 = Mask 1 = Pass Gating all clocks for FBMDMC0 0 = Mask 1 = Pass Gating all clocks for SSS 0 = Mask 1 = Pass Reserved Gating all clocks for INT_COMB 0 = Mask 1 = Pass Reserved Gating all clocks for DREX2 0 = Mask 1 = Pass Reset Value 0x3 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-132 Exynos 4412_UM 5.9.1.115 CLK_GATE_IP_DMC1  Base Address: 0x1004_0000  Address = Base Address + 0x0904, Reset Value = 0xFFFF_FFFF Name RSVD CLK_TZASC_LR CLK_TZASC_LW CLK_TZASC_RR CLK_TZASC_RW Bit [31:4] [3] [2] [1] [0] Type  RW RW RW RW Description Reserved Gating all clocks for TZASC_LR 0 = Mask 1 = Pass Gating all clocks for TZASC_LW 0 = Mask 1 = Pass Gating all clocks for TZASC_RR 0 = Mask 1 = Pass Gating all clocks for TZASC_RW 0 = Mask 1 = Pass 5 Clock Management Unit Reset Value 0xFFFFFFF 0x1 0x1 0x1 0x1 5-133 Exynos 4412_UM 5 Clock Management Unit 5.9.1.116 CLKOUT_CMU_DMC  Base Address: 0x1004_0000  Address = Base Address + 0x0A00, Reset Value = 0x0001_0000 Name RSVD ENB_CLKOUT RSVD DIV_RATIO RSVD MUX_SEL Bit [31:17] [16] [15:14] [13:8] [7:5] [4:0] Type  RW  RW  RW Description Reserved Enable CLKOUT 0 = Disables 1 = Enables Reserved Divide Ratio Divide ratio = DIV_RATIO + 1 Reserved MUX Selection 00000 = ACLK_DMCD 00001 = ACLK_DMCP 00010 = ACLK_ACP 00011 = PCLK_ACP 00100 = SCLK_DMC 00101 = SCLK_DPHY 00110 = MPLL_FOUT/2 00111 = SCLK_PWI 01000 = Reserved 01001 = SCLK_C2C 01010 = ACLK_C2C 5.9.1.117 CLKOUT_CMU_DMC_DIV_STAT  Base Address: 0x1004_0000  Address = Base Address + 0x0A04, Reset Value = 0x0000_0000 Name RSVD DIV_STAT Bit [31:1] [0] Type  R Description Reserved DIVCLKOUT Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x1 0x0 0x0 0x0 0x0 Reset Value 0x0 0x0 5-134 Exynos 4412_UM 5 Clock Management Unit 5.9.1.118 DCGIDX_MAP0  Base Address: 0x1004_0000  Address = Base Address + 0x1000, Reset Value = 0xFFFF_FFFF Name DCGIDX_MAP0 Bit [31:0] Type RW Description IEC Configuration for DCG Index Map[31:0] 5.9.1.119 DCGIDX_MAP1  Base Address: 0x1004_0000  Address = Base Address + 0x1004, Reset Value = 0xFFFF_FFFF Name DCGIDX_MAP1 Bit [31:0] Type RW Description IEC Configuration for DCG Index Map[63:32] 5.9.1.120 DCGIDX_MAP2  Base Address: 0x1004_0000  Address = Base Address + 0x1008, Reset Value = 0xFFFF_FFFF Name DCGIDX_MAP2 Bit [31:0] Type RW Description IEC Configuration for DCG Index Map[95:64] 5.9.1.121 DCGPERF_MAP0  Base Address: 0x1004_0000  Address = Base Address + 0x1020, Reset Value = 0xFFFF_FFFF Name DCGPERF_MAP0 Bit [31:0] Type RW Description DCG Performance Map[31:0] 5.9.1.122 DCGPERF_MAP1  Base Address: 0x1004_0000  Address = Base Address + 0x1024, Reset Value = 0xFFFF_FFFF Name DCGPERF_MAP1 Bit [31:0] Type RW Description DCG Performance Map[63:32] Reset Value 0xFFFFFFFF Reset Value 0xFFFFFFFF Reset Value 0xFFFFFFFF Reset Value 0xFFFFFFFF Reset Value 0xFFFFFFFF 5-135 Exynos 4412_UM 5 Clock Management Unit 5.9.1.123 DVCIDX_MAP  Base Address: 0x1004_0000  Address = Base Address + 0x1040, Reset Value = 0x00FF_FFFF Name RSVD DCGPERF_MAP0 Bit [31:24] [23:0] Type  RW Description Reserved IEC Configuration for DVC Index Map[23:0] 5.9.1.124 FREQ_CPU  Base Address: 0x1004_0000  Address = Base Address + 0x1060, Reset Value = 0x0000_0000 Name RSVD FREQ_CPU Bit [31:24] [23:0] Type  RW Description Reserved Maximum Frequency of CPU in KHz 5.9.1.125 FREQ_DPM  Base Address: 0x1004_0000  Address = Base Address + 0x1064, Reset Value = 0x0000_0000 Name RSVD FREQ_DPM Bit [31:24] [23:0] Type  RW Description Reserved Maximum Frequency of DPM 5.9.1.126 DVSEMCLK_EN  Base Address: 0x1004_0000  Address = Base Address + 0x1080, Reset Value = 0x0000_0000 Name RSVD DVSEMCLK_EN Bit [31:1] [0] Type  RW Description Reserved DVS Emulation Clock Enable Reset Value 0x0 0xFFFFFF Reset Value 0x0 0x0 Reset Value 0x0 0x0 Reset Value 0x0 0x0 5-136 Exynos 4412_UM 5 Clock Management Unit 5.9.1.127 MAXPERF  Base Address: 0x1004_0000  Address = Base Address + 0x1084, Reset Value = 0x0000_0000 Name RSVD MAXPERF_EN Bit [31:1] [0] Type  RW Description Reserved Maximum Performance Enable 0 = Disables 1 = Enables Reset Value 0x0 0x0 5.9.1.128 DMC_PAUSE_CTRL  Base Address: 0x1004_0000  Address = Base Address + 0x1094, Reset Value = 0x0000_0000 Name Bit Type Description RSVD STATE RSVD DMC_PAUSE _ENABLE [31:19] [18:16] [15:1] [0]  Reserved R Specifies current status for debugging  Reserved Enable pause function for DREX2 DVFS RW DREX2 pause function works when DMC_RATIO or DMCD_RATIO in CLK_DIV_DMC0 register is changed. Reset Value 0x0 0x0 0x0 0x0 5-137 Exynos 4412_UM 5 Clock Management Unit 5.9.1.129 DDRPHY_LOCK_CTRL  Base Address: 0x1004_0000  Address = Base Address + 0x1098, Reset Value = 0x0000_0000 Name USE_CTRL _LOCKED CTRL_START _ENABLE CTRL_RESYNC _ENABLE CTRL_RESYNC _MASK RSVD CURR_STATE DUR_LOCK_WAIT DUR_CTRL_ST _CLR Bit Type Description Use ctrl_locked signal coming from LPDDR_PHY to check DLL lock-time duration [31] RW 0 = Uses internal counter to measure DLL lock duration 1 = Uses ctrl_locked signal [30] RW Enable Clearing of ctrl_start signal [29] [28] [28:18] [17:16] [15:8] [7:0] RW Enable ctrl_resync pulse generation RW Mask ctrl_resync pulse form DREX2 during DDRPHY DLL Locking time  Reserved R Specifies current status for debugging RW Sets Duration for DLL Lock Wait of DDR_PHY RW Sets Duration for clearing ctrl_start signal of DDR_PHY Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5.9.1.130 C2C_STATE  Base Address: 0x1004_0000  Address = Base Address + 0x109C, Reset Value = 0x0000_0000 Name RSVD CURR_STATE Bit [31:3] [2:0] Type  R Description Reserved Current State ofC2C SEC FSM Reset Value 0x0 0x0 5-138 Exynos 4412_UM 5 Clock Management Unit 5.9.1.131 APLL_LOCK  Base Address: 0x1004_0000  Address = Base Address + 0x4000, Reset Value = 0x0000_0FFF Name RSVD PLL_LOCKTIME Bit [31:16] [15:0] Type  RW Description Reserved Required period to generate a stable clock output Set (270cycles  PDIV) to PLL_LOCKTIME for the PLL maximum lock time. 1 cycle = 1/FREF = 1/(FIN/PDIV) The maximum PLL lock time is 22.5 usec where FIN is 24 MHz, PDIV is 2 and PLL_LOCKTIME is 540. Reset Value 0x0 0xFFF The maximum lock time means the waiting time for locking in the worst case. Therefore, the user of this PLL must wait for more than the maximum lock time unconditionally before the PLL is locked. (Waiting time before locking ≥ the maximum locktime) 5-139 Exynos 4412_UM 5 Clock Management Unit 5.9.1.132 APLL_CON0  Base Address: 0x1004_0000  Address = Base Address + 0x4100, Reset Value = 0x0064_0300 Name ENABLE RSVD LOCKED RSVD FSEL RSVD MDIV RSVD PDIV RSVD SDIV Bit [31] [30] [29] [28] [27] [26] [25:16] [15:14] [13:8] [7:3] [2:0] Type RW  R  RWX  RWX  RWX  RWX Description PLL Enable Control 0 = Disables 1 = Enables Reserved PLL Locking Indication 0 = Unlocks 1 = Locks If ENABLE_LOCK_DET = 0, then this field is set to 1 after the locking time. The lock-time is set using the APLL_LOCK SFR register. If ENABLE_LOCK_DET = 1, then this field is set when the hardware lock detector meets the PLL locking condition. This bit is Read only. Reserved Monitors Frequency Select Pin 0 = FVCO_OUT = FREF 1 = FVCO_OUT = FVCO Reserved PLL M Divide Value Reserved PLL P Divide Value Reserved PLL S Divide Value Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0xC8 0x0 0x6 0x0 0x1 The reset value of APLL_CON0 generates an 800 MHz output clock for an input clock frequency of 24 MHz. The equation to calculate the output frequency is: FOUT = MDIV  FIN/(PDIV  2SDIV) FOUT should fall in the range of: 21.9 MHz  FOUT  1400 MHz The conditions MDIV, PDIV, SDIV for APLL and MPLL should meet are:  PDIV: 1  PDIV  63  MDIV: 64  MDIV  1023  SDIV: 0  SDIV  5  Fref = FIN/PDIV) Fref should fall in the range of: 2 MHz  Fref  12 MHz  FVCO = MDIV  FIN/PDIV) FVCO should fall in the range of: 700 MHz  FVCO  1400 MHz 5-140 Exynos 4412_UM 5 Clock Management Unit Refer to the section 5.3.1 Recommended PLL PMS Value for APLL and MPLL for recommended PMS values. 5-141 Exynos 4412_UM 5 Clock Management Unit 5.9.1.133 APLL_CON1  Base Address: 0x1004_0000  Address = Base Address + 0x4104, Reset Value = 0x0080_3800 Name RSVD RESV1 RESV0 BYPASS DCC_ENB AFC_ENB RSVD RSVD FEED_EN LOCK_CON_OUT LOCK_CON_IN LOCK_CON_DLY RSVD AFC Bit [31:25] [24] [23] [22] [21] [20] [19:18] [17] [16] [15:14] [13:12] [11:8] [7:5] [4:0] Type  RW RW RW RW RWX   RW RW RW RW  RWX Description Reserved Specifies status of Linear-Region Detector (LDR) when it detects a low signal. Specifies VCO range boost-up when the signal is high. If BYPASS = 1, bypass mode is enabled. (FOUT =FIN) If BYPASS = 0, PLL3500X operates normally. Decides whether the DCC is enabled or not. 0 = Enables DCC 1 = Disables DCC It is an active low signal. Decides whether AFC is enabled or not. When AFC is enabled, it calibrates VCO automatically. 0 = Enables AFC 1 = Disables AFC It is an active low signal. Reserved Reserved Enable signal for FEED_OUT Specifies Lock detector settings of the output margin. Specifies Lock detector settings of the input margin. Specifies Lock detector settings of the detection resolution. Reserved AFC value Reset Value 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 0x8 0x0 0x0 AFC automatically selects adaptive frequency curve of VCO using switched current bank for wide range, high phase noise (or Jitter), and fast lock time. Refer to the sectin 5.3.1 Recommended PLL PMS Value for APLL and MPLL for recommended AFC_ENB and AFC values. NOTE: The other PLL control inputs should be set as: RESV1 = 0 RESV0 = 0 DCC_ENB = 1 EXTAFC = 0 LOCK_CON_IN = 3 LOCK_CON_OUT = 0 LOCK_CON_DLY = 8 AFC_ENB = 0 5-142 Exynos 4412_UM 5.9.1.134 CLK_SRC_CPU  Base Address: 0x1004_0000  Address = Base Address + 0x4200, Reset Value = 0x0000_0000 RSVD Name MUX_MPLL_USER_SEL_C RSVD MUX_HPM_SEL RSVD MUX_CORE_SEL RSVD MUX_APLL_SEL Bit [31:25] [24] [23:21] [20] [19:17] [16] [15:1] [0] Type  RW  RW  RW  RW Description Reserved Controls MUXMPLL 0 = FINPLL 1 = FOUTMPLL Reserved Controls MUXHPM 0 = MOUTAPLL 1 = SCLKMPLL Reserved Controls MUXCORE 0 = MOUTAPLL 1 = SCLKMPLL Reserved Controls MUXAPLL 0 = FINPLL 1 = MOUTAPLLFOUT 5 Clock Management Unit Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-143 Exynos 4412_UM 5 Clock Management Unit 5.9.1.135 CLK_MUX_STAT_CPU  Address = 0x1004_4400, Reset Value = 0x0111_0001 Name RSVD MPLL_USER_SEL_C HPM_SEL RSVD CORE_SEL RSVD RSVD APLL_SEL Bit [31:27] [26:24] [22:20] [19] [18:16] [15:3] [7:3] [2:0] Type  R R  R   R Description Reserved Selection signal status of MUXMPLL 001 = FINMPLL 010 = FOUTMPLL 1xx = Status that the mux is changing Selection signal status of MUXHPM 001 = MOUTAPLL 010 = SCLKMPLL 1xx = Status that the mux is changing Reserved Selection signal status of MUXCORE 001 = MOUTAPLL 010 = SCLKMPLL 1xx = Status that the mux is changing Reserved Reserved Selection signal status of MUXAPLL 001 = FINPLL 010 = MOUTAPLLFOUT 1xx = Status that the mux is changing Reset Value 0x0 0x1 0x1 0x0 0x1 0x0 0x0 0x1 5-144 Exynos 4412_UM 5 Clock Management Unit 5.9.1.136 CLK_DIV_CPU0  Base Address: 0x1004_0000  Address = Base Address + 0x4500, Reset Value = 0x0000_0000 Name RSVD CORE2_RATIO RSVD APLL_RATIO RSVD PCLK_DBG_RATIO RSVD ATB_RATIO RSVD PERIPH_RATIO RSVD COREM1_RATIO RSVD Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] Type  RW  RW  RW  RW  RW  RW  Description Reserved DIVCORE2 Clock Divider Ratio ARMCLK = DOUTCORE/(CORE2_RATIO + 1) Reserved DIVAPLL Clock Divider Ratio SCLKAPLL = MOUTAPLL/(APLL_RATIO + 1) Reserved DIVPCLK_DBG Clock Divider Ratio PCLK_DBG = ATCLK/(PCLK_DBG_RATIO + 1) Reserved DIVATB Clock Divider Ratio ATCLK = MOUTCORE/(ATB_RATIO + 1) Reserved DIVPERIPH Clock Divider Ratio PERIPHCLK = DOUTCORE/(PERIPH_RATIO + 1) Reserved DIVCOREM1 Clock Divider Ratio ACLK_COREM1 = ARMCLK/(COREM1_RATIO +1) Reserved COREM0_RATIO DIVCOREM0 Clock Divider Ratio [6:4] RW ACLK_COREM0 = ARMCLK/(COREM0_RATIO +1) RSVD CORE_RATIO [3]  Reserved DIVCORE Clock Divider Ratio [2:0] RWX DIVCORE_OUT = MOUTCORE/(CORE_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-145 Exynos 4412_UM 5 Clock Management Unit 5.9.1.137 CLK_DIV_CPU1  Base Address: 0x1004_0000  Address = Base Address + 0x4504, Reset Value = 0x0000_0000 Name RSVD CORES_RATIO RSVD HPM_RATIO RSVD COPY_RATIO Bit [31:11] [10:8] [7] [6:4] [3] [2:0] Type  RW  RWX  RWX Description Reserved DIVCORES Clock Divider Ratio ACLK_CORES = ARMCLK/(CORES_RATIO + 1) Reserved DIVHPM Clock Divider Ratio SCLK_HPM = DOUTCOPY/(HPM_RATIO + 1) Reserved DIVCOPY Clock Divider Ratio DOUTCOPY = MOUTHPM/(COPY_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5-146 Exynos 4412_UM 5 Clock Management Unit 5.9.1.138 CLK_DIV_STAT_CPU0  Base Address: 0x1004_0000  Address = Base Address + 0x4600, Reset Value = 0x0000_0000 Name RSVD DIV_CORE2 RSVD DIV_APLL RSVD DIV_PCLK_DBG RSVD DIV_ATB RSVD DIV_PERIPH RSVD DIV_COREM1 RSVD DIV_COREM0 RSVD DIV_CORE Bit [31:29] [28] [27:25] [24] [23:21] [20] [19:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Type  R  R  R  R  R  R  R  R Description Reserved DIVCORE2 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVAPLL Status 0 = Stable 1 = Status that the divider is changing Reserved DIVPCLK_DBG Status 0 = Stable 1 = Status that the divider is changing Reserved DIVATB Status 0 = Stable 1 = Status that the divider is changing Reserved DIVPERIPH Status 0 = Stable 1 = Status that the divider is changing Reserved DIVCOREM1 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVCOREM0 Status 0 = Stable 1 = Status that the divider is changing Reserved DIVCORE Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-147 Exynos 4412_UM 5 Clock Management Unit 5.9.1.139 CLK_DIV_STAT_CPU1  Base Address: 0x1004_0000  Address = Base Address + 0x4604, Reset Value = 0x0000_0000 Name RSVD DIV_CORES RSVD DIV_HPM RSVD DIV_COPY Bit [31:9] [8] [7:5] [4] [3:1] [0] Type  R  R  R Description Reserved DIVCORES Status 0 = Stable 1 = Status that the divider is changing Reserved DIVHPM Status 0 = Stable 1 = Status that the divider is changing Reserved DIVCOPY Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5.9.1.140 CLK_GATE_IP_CPU  Base Address: 0x1004_0000  Address = Base Address + 0x4900, Reset Value = 0xFFFF_FFFF Name Bit Type Description RSVD CLK_CSSYS CLK_HPM [31:2] [1] [0]  Reserved Gating all clocks for CoreSight and SecureJTAG RW 0 = Mask 1 = Pass Gating all clocks for HPM RW 0 = Mask 1 = Pass Reset Value 0xFFFF_FFF3 0x1 0x1 5-148 Exynos 4412_UM 5 Clock Management Unit 5.9.1.141 CLKOUT_CMU_CPU  Base Address: 0x1004_0000  Address = Base Address + 0x4A00, Reset Value = 0x0001_0000 Name RSVD ENB_CLKOUT RSVD DIV_RATIO RSVD MUX_SEL Bit [31:17] [16] [15:14] [13:8] [7:5] [4:0] Type  RW  RW  RW Description Reserved Enable CLKOUT 0 = Disables 1 = Enables Reserved Divide Ratio Divide ratio = DIV_RATIO + 1 Reserved MUX Selection 00000 = APLL_FOUT/2 00001 = Reserved 00010 = Reserved 00011 = Reserved 00100 = ARMCLK/2 00101 = ACLK_COREM0 00110 = ACLK_COREM1 00111 = ACLK_CORES 01000 = ATCLK 01001 = PERIPHCLK 01010 = PCLK_DBG 01011 = SCLK_HPM ATCLK and PCLK_DBG are the gated clocks. You should not gate ATCLK or PCLK_DBG clocks before changing the DIV_RATIO value on selection of ATCLK or PCLK_DBG. Reset Value 0x0 0x1 0x0 0x0 0x0 0x0 5.9.1.142 CLKOUT_CMU_CPU_DIV_STAT  Base Address: 0x1004_0000  Address = Base Address + 0x4A04, Reset Value = 0x0000_0000 Name RSVD DIV_STAT Bit [31:1] [0] Type  R Description Reserved DIVCLKOUT Status 0 = Stable 1 = Status that the divider is changing Reset Value 0x0 0x0 5-149 Exynos 4412_UM 5 Clock Management Unit 5.9.1.143 ARMCLK_STOPCTRL  Base Address: 0x1004_0000  Address = Base Address + 0x5000, Reset Value = 0x0404_0404 Name L2_PRE_WAIT_CNT Bit [31:24] L2_POST_WAIT_CNT [23:16] PRE_WAIT_CNT [15:8] POST_WAIT_CNT [7:0] Type RW RW RW RW Description Specifies clock freeze cycle before the CLAMP_L2_0 and CLAMP_L2_1rising transition Specifies clock freeze cycle after the L2RET1N_0 and L2RET1N_1 rising transition Specifies clock freeze cycle before the ARM clamp (CLAMPCORE0, CLAMPCORE1, CLAMPCOREOUT, CLAMPL2_0, and CLAMPL2_1) or reset signal (nCPURESET, nDBGRESET, nSCURESET, L2nRESET, nWDRESET, nPERIPHRESET, and nPTMRESET) transition Specifies clock freeze cycle after the ARM clamp (CLAMPCORE0, CLAMPCORE1, CLAMPCOREOUT, CLAMPL2_0, and CLAMPL2_1) or reset signal (nCPURESET, nDBGRESET, nSCURESET, L2nRESET, nWDRESET, nPERIPHRESET, and nPTMRESET) transition Reset Value 0x4 0x4 0x4 0x4 5.9.1.144 ATCLK_STOPCTRL  Base Address: 0x1004_0000  Address = Base Address + 0x5004, Reset Value = 0x0000_0404 Name RSVD PRE_WAIT_CNT POST_WAIT_CNT Bit [31:16] [15:8] [7:0] Type  RW RW Description Reserved Specifies clock freeze cycle before the ATRESETn, nPRESETDBG, and CSSYS_nRESET signal transition Specifies clock freeze cycle after the ATRESETn, nPRESETDBG, and CSSYS_nRESET signal transition Reset Value 0x0 0x4 0x4 5-150 Exynos 4412_UM 5 Clock Management Unit 5.9.1.145 PWR_CTRL  Base Address: 0x1004_0000  Address = Base Address + 0x5020, Reset Value = 0x0000_04FF Name RSVD CORE2_RATIO RSVD CSCLK_AUTO_ ENB_IN_DEBUG RSVD CORE_RATIO RSVD F4D_CORESIGHT _EN DIVCORE2_ DOWN_ENB DIVCORE_DOWN _ENB USE_STANDBYWFE _ARM_CORE3 USE_STANDBYWFE _ARM_CORE2 USE_STANDBYWFE _ARM_CORE1 USE_STANDBYWFE _ARM_CORE0 USE_STANDBYWFI _ARM_CORE3 USE_STANDBYWFI _ARM_CORE2 USE_STANDBYWFI Bit [31] [30:28] [27:21] [20] [19] [18:16] [15:11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] Type  RW  RW  RW  RW RW RW RW RW RW RW RW RW RW Description Reserved DIVCORE2 on WFI/WFE Set DIVCORE2 clock divider ratio when both ARM cores are in Wait For Interrupt/Event state Reserved Forces CoreSight clocks to toggle when the debugger is attached 0 = Disables 1 = Enables Reserved DIVCORE on WFI/WFE Set DIVCORE clock divider ratio when both ARM cores are in Wait For Interrupt/Event state Reserved Gating F4D Coresight clocks both ARM cores in IDLE mode 0 = Mask 1 = Pass Enable ARMCLK Down feature when both ARM cores are in IDLE mode for DIVCORE2 0 = Disables 1 = Enables Enable ARMCLK Down feature when both ARM cores are in IDLE mode for DIVCORE 0 = Disables 1 = Enables Use ARM CORE3 STANDBYWFE to change ARMCLK frequency in ARM IDLE state Use ARM CORE2 STANDBYWFE to change ARMCLK frequency in ARM IDLE state Use ARM CORE1 STANDBYWFE to change ARMCLK frequency in ARM IDLE state Use ARM CORE0 STANDBYWFE to change ARMCLK frequency in ARM IDLE state Use ARM CORE3 STANDBYWFI to change ARMCLK frequency in ARM IDLE state Use ARM CORE2 STANDBYWFI to change ARMCLK frequency in ARM IDLE state Use ARM CORE1 STANDBYWFI to change Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-151 Exynos 4412_UM 5 Clock Management Unit Name _ARM_CORE1 USE_STANDBYWFI _ARM_CORE0 Bit Type Description ARMCLK frequency in ARM IDLE state [0] RW Use ARM CORE0 STANDBYWFI to change ARMCLK frequency in ARM IDLE state Reset Value 0x1 5-152 Exynos 4412_UM 5 Clock Management Unit 5.9.1.146 PWR_CTRL2  Base Address: 0x1004_0000  Address = Base Address + 0x5024, Reset Value = 0x0000_0000 Name RSVD DIVCORE2_UP_ENB DIVCORE_UP_ENB DUR_STANDBY2 DUR_STANDBY1 RSVD UP_CORE2_RATIO RSVD UP_CORE_RATIO Bit [31:26] [25] [24] [23:16] [15:8] [7] [6:4] [3] [2:0] Type  RW RW RW RW  RW  RW Description Reserved Enable ARMCLK Up feature when both ARM cores exit from IDLE mode for DIVCORE2 0 = Disables 1 = Enables Enable ARMCLK Up feature when both ARM cores exit from IDLE mode for DIVCORE 0 = Disables 1 = Enables Sets duration to change to the normal divider value from the middle divider value This bit should be left-shifted by 4-bit before comparing it to the counter value. Sets duration to change to the middle divider value from the divider value in ARM idle state. This bit should be left-shifted by 4-bit before comparing it to counter value. Reserved Specifies DIVCORE2 clock divider ratio when ARM0 or ARM1 cores are not in a wait state for an interrupt or event to occur. Reserved Specifies DIVCORE clock divider ratio when ARM0 or ARM1 cores are not in a wait state for an interrupt or event to occur. Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-153 Exynos 4412_UM 5 Clock Management Unit 5.9.1.147 L2_STATUS  Base Address: 0x1004_0000  Address = Base Address + 0x5400, Reset Value = 0x0000_0000 Name RSVD L2IDLE RSVD L2_CLKSTOPPED RSVD TAGSETUPLAT RSVD TAGREADLAT RSVD TAGWRITELAT RSVD DATASETUPLAT RSVD DATAREADLAT RSVD DATAWRITELAT Bit [31:29] [28] [27:25] [24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Type  R  R  R  R  R  R  R  R Description Reserved Indicates L2 cache controller is in idle state Reserved Indicates L2 cache controller is in standby-mode Reserved Setup Latency for Tag RAM Reserved Read access Latency for Tag RAM Reserved Write access Latency for Tag RAM Reserved Setup Latency for Data RAM Reserved Read access Latency for Data RAM Reserved Write access Latency for Data RAM Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-154 Exynos 4412_UM 5 Clock Management Unit 5.9.1.148 CPU_STATUS  Base Address: 0x1004_0000  Address = Base Address + 0x5410, Reset Value = 0x0000_0000 Name RSVD PMUPRIV PMUSECURE SMPnAMP Bit [31:12] [11:8] [7:4] [3:0] Type – R R R Description Reserved Returns status of the Cortex-A9 processor 0 = User mode 1 = Privileged mode Returns security status of the Cortex-A9 processor 0 = Non-secure state 1 = Secure state Specifies signals AMP or SMP mode for each Cortex-A9 processor 0 = Asymmetric signal 1 = Symmetric signal Reset Value 0x0 0x0 0x0 0x0 5.9.1.149 PTM_STATUS  Base Address: 0x1004_0000  Address = Base Address + 0x5420, Reset Value = 0x0000_0000 Name RSVD PTMPWRUP0 PTMPWRUP1 PTMIDLEnACK0 PTMIDLEnACK1 Bit [31:4] [3] [2] [1] [0] Type  R R R R Description Reserved PTM for CPU0 is active PTM for CPU1 is active PTM for CPU0 is an idle state indicator PTM for CPU1 is an idle state indicator Reset Value 0x0 0x0 0x0 0x0 0x0 5-155 Exynos 4412_UM 5 Clock Management Unit 5.9.1.150 CLK_DIV_ISP0  Base Address: 0x1004_0000  Address = Base Address + 0x8300, Reset Value = 0x0000_0000 Name RSVD ISPDIV1_RATIO RSVD ISPDIV0_RATIO Bit [31:7] [6:4] [3] [2:0] Type  RW  RW Description Reserved ISPDIV1 Clock Divider Ratio ISPDIV1_CLK = ACLK_200/(ISPDIV1_RATIO + 1) Reserved ISPDIV0 Clock Divider Ratio ISPDIV0_CLK = ACLK_200/(ISPDIV0_RATIO + 1) Reset Value 0x0 0x0 0x0 0x0 5.9.1.151 CLK_DIV_ISP1  Base Address: 0x1004_0000  Address = Base Address + 0x8304, Reset Value = 0x0000_0000 Name RSVD MCUISPDIV1 _RATIO RSVD MCUISPDIV0 _RATIO RSVD MPWMDIV _RATIO Bit [31:11] [10:8] [7] [6:4] [3] [2:0] Type  RW  RW  RW Description Reserved MCUISPDIV1 Clock Divider Ratio MCUISPDIV1_CLK = [MOUTMCUISPDIV0_CLK/(MCUISPDIV1_RATIO + 1)] Reserved MCUISPDIV0 Clock Divider Ratio MCUISPDIV0_CLK = [ACLK_400_MCUIPS /(MCUISPDIV0_RATIO + 1)] Reserved MPWM Clock Divider Ratio MPWMDIV_CLK = [MOUTISPDIV1_CLK /(MPWMDIV_RATIO + 1)] Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5-156 Exynos 4412_UM 5.9.1.152 CLK_DIV_STAT_ISP0  Base Address: 0x1004_0000  Address = Base Address + 0x8400, Reset Value = 0x0000_0000 Name RSVD DIV_ISPDIV1 RSVD DIV_ISPDIV0 Bit [31:5] [4] [3:1] [0] Type  R  R Description Reserved ISPDIV1 Status 0 = Stable 1 = Status that the divider is changing Reserved ISPDIV0 Status 0 = Stable 1 = Status that the divider is changing 5.9.1.153 CLK_DIV_STAT_ISP1  Base Address: 0x1004_0000  Address = Base Address + 0x8404, Reset Value = 0x0000_0000 Name Bit Type Description RSVD [31:9] DIV_MCUISPDIV1 [8] RSVD [7:5] DIV_MCUISPDIV0 [4] RSVD [3:1] DIV_MPWMDIV [0]  Reserved DIVMCUISP1 Status R 0 = Stable 1 = Status that the divider is changing  Reserved DIVMCUISP0 Status R 0 = Stable 1 = Status that the divider is changing  Reserved DIVMPWM Status R 0 = Stable 1 = Status that the divider is changing 5 Clock Management Unit Reset Value 0x0 0x0 0x0 0x0 Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 5-157 Exynos 4412_UM 5 Clock Management Unit 5.9.1.154 CLK_GATE_IP_ISP0  Base Address: 0x1004_0000  Address = Base Address + 0x8800, Reset Value = 0xFFFF_FFFF Name CLK_UART_ISP CLK_WDT_ISP RSVD CLK_PWM_ISP CLK_MTCADC_ISP CLK_I2C1_ISP CLK_I2C0_ISP CLK_MPWM_ISP CLK_MCUCTL_ISP RSVD CLK_PPMUISPX CLK_PPMUISPMX RSVD CLK_SMMU_LITE1 CLK_SMMU_LITE0 Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [13:19] [12] [11] Type RW RW  RW RW RW RW RW RW  RW RW  RW RW Description Gating all clocks for UART_ISP except SCLK 0 = Mask 1 = Pass Gating all clocks for WDT_ISP 0 = Mask 1 = Pass Reserved Gating all clocks for PWM_ISP except SCLK 0 = Mask 1 = Pass Gating all clocks for MTCADC_ISP 0 = Mask 1 = Pass Gating all clocks for I2C1_ISP 0 = Mask 1 = Pass Gating all clocks for I2C0_ISP 0 = Mask 1 = Pass Gating all clocks for MPWM_ISP 0 = Mask 1 = Pass Gating all clocks for MCUCTL_ISP 0 = Mask 1 = Pass Reserved Gating all clocks for PPMUISPX 0 = Mask 1 = Pass Gating all clocks for PPMUISPMX 0 = Mask 1 = Pass Reserved Gating all clocks for SMMU_LITE1 0 = Mask 1 = Pass Gating all clocks for SMMU_LITE0 0 = Mask 1 = Pass Reset Value 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x7F 0x1 0x1 5-158 Exynos 4412_UM Name CLK_SMMU_FD CLK_SMMU_DRC CLK_SMMU_ISP CLK_GICISP RSVD CLK_MCUISP CLK_LITE1 CLK_LITE0 CLK_FD CLK_DRC CLK_ISP Bit Type Description Gating all clocks for SMMU_FD [10] RW 0 = Mask 1 = Pass Gating all clocks for SMMU_DRC [9] RW 0 = Mask 1 = Pass Gating all clocks for SMMU_ISP [8] RW 0 = Mask 1 = Pass Gating all clocks for GICISP [7] RW 0 = Mask 1 = Pass [6]  Reserved Gating all clocks for MCUISP [5] RW 0 = Mask 1 = Pass Gating all clocks for LITE1 [4] RW 0 = Mask 1 = Pass Gating all clocks for LITE0 [3] RW 0 = Mask 1 = Pass Gating all clocks for FD [2] RW 0 = Mask 1 = Pass Gating all clocks for DRC [1] RW 0 = Mask 1 = Pass Gating all clocks for ISP [0] RW 0 = Mask 1 = Pass 5 Clock Management Unit Reset Value 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 5-159 Exynos 4412_UM 5 Clock Management Unit 5.9.1.155 CLK_GATE_IP_ISP1  Base Address: 0x1004_0000  Address = Base Address + 0x8804, Reset Value = 0xFFFF_FFFF Name RSVD CLK_SPI1_ISP CLK_SPI0_ISP RSVD CLK_SMMU_ISPCX RSVD CLK_ASYNCAXIM Bit [31:14] [13] [12] [11:5] [4] [3:1] [0] Type  RW RW  RW  RW Description Reserved Gating all clocks for SPI1_ISP except SCLK 0 = Mask 1 = Pass Gating all clocks for SPI0_ISP except SCLK 0 = Mask 1 = Pass Reserved Gating all clocks for CLK_SMMU_ISPCX 0 = Mask 1 = Pass Reserved Gating all clocks for CLK_ASYNCAXIM 0 = Mask 1 = Pass 5.9.1.156 CLKOUT_CMU_ISP  Base Address: 0x1004_0000  Address = Base Address + 0x8A00, Reset Value = 0x0001_0000 Name RSVD ENB_CLKOUT RSVD DIV_RATIO RSVD MUX_SEL Bit [31:17] [16] [15:14] [13:8] [7:5] [4:0] Type  RW  RW  RW Description Reserved Enable CLKOUT 0 = Disables 1 = Enables Reserved Divide Ratio Divide ratio = DIV_RATIO + 1 Reserved MUX Selection 00000 = ACLK_MCUISP 00001 = PCLKDBG_MCUISP 00010 = ACLK_DIV0 00011 = ACLK_DIV1 00100 = SCLK_MPWM_ISP Reset Value 0x3FFFF 0x1 0x1 0x7F 0x1 0x7 0x1 Reset Value 0x0 0x1 0x0 0x0 0x0 0x0 5-160 Exynos 4412_UM 5 Clock Management Unit 5.9.1.157 CLKOUT_CMU_ISP_DIV_STAT  Base Address: 0x1004_0000  Address = Base Address + 0x8A04, Reset Value = 0x0000_0000 Name RSVD DIV_STAT Bit [31:1] [0] Type  R Description Reserved DIVCLKOUT Status 0 = Stable 1 = Status that the divider is changing 5.9.1.158 CMU_ISP_SPARE0  Base Address: 0x1004_0000  Address = Base Address + 0x8B00, Reset Value = 0x0000_0000 Name SPARE Bit [31:0] Type Description RW CMU_ISP Spare Register 5.9.1.159 CMU_ISP_SPARE1  Base Address: 0x1004_0000  Address = Base Address + 0x8B04, Reset Value = 0x0000_0000 Name SPARE Bit [31:0] Type Description RW CMU_ISP Spare Register 5.9.1.160 CMU_ISP_SPARE2  Base Address: 0x1004_0000  Address = Base Address + 0x8B08, Reset Value = 0x0000_0000 Name SPARE Bit [31:0] Type Description RW CMU_ISP Spare Register 5.9.1.161 CMU_ISP_SPARE3  Base Address: 0x1004_0000  Address = Base Address + 0x8B0C, Reset Value = 0x0000_0000 Name SPARE Bit [31:0] Type Description RW CMU_ISP Spare Register Reset Value 0x0 0x0 Reset Value 0x0 Reset Value 0x0 Reset Value 0x0 Reset Value 0x0 5-161 Exynos 4412_UM 6 Interrupt Controller 6 Interrupt Controller 6.1 Overview Generic Interrupt Controller (GIC) is a centralized resource that supports and manages interrupts in a system. GIC provides:  Registers for managing interrupt sources, interrupt behavior, and interrupt routing to one or multiple processors  Support for  The ARM architecture Security Extensions  Enabling, disabling, and generating processor interrupts from hardware (peripheral) interrupt sources  Generating software interrupts  Interrupt masking and prioritization GIC takes the interrupts asserted at the system level and sends appropriate signals to each connected processor. When GIC implements the Security Extensions, it can implement two interrupt requests to a connected processor. The architecture identifies these requests as IRQ and FIQ. 6-1 Exynos 4412_UM 6 Interrupt Controller 6.2 Features The features of GIC are:  Supports three interrupt types:  Software Generated Interrupt (SGI)  Private Peripheral Interrupt (PPI)  Shared Peripheral Interrupt (SPI)  Programmable interrupts that enable you to set the:  Security state for an interrupt.  Priority level of an interrupt.  Enabling or disabling of an interrupt.  Processors that receive an interrupt. 6.2.1 Security Extensions Support The ARM GIC architecture Security Extensions support:  Configuring each interrupt as either Secure or Non-secure  Signaling Secure interrupts to the target processor by using either the IRQ or FIQ exception request  Handling priority of secure and Non-secure interrupts, which is a unified scheme.  Optional lockdown of the configuration of some Secure interrupts. In an implementation that includes the Security Extensions:  System software individually defines each implemented interrupt as either Secure or Non-secure.  The behavior of processor accesses to registers in the GIC depends on whether the access is Secure or Non- secure. When accessing GIC registers:  A Non-secure read of a register field that holds state information for a Secure interrupt returns zero  GIC ignores any Non-secure write to a register field that holds state information for a secure interrupt. Non-secure accesses can only read or set information corresponding to Non-secure interrupts. Secure accesses can read or set information corresponding to both Non-secure and Secure interrupts.  A Non-secure interrupt signals an IRQ interrupt request to a target processor.  A Secure interrupt can signal either an IRQ or FIQ interrupt request to a target processor. 6-2 Exynos 4412_UM 6 Interrupt Controller 6.2.2 Implementation-Specific Configurable Features During implementation of GIC, the features that depend on the configuration are:  Exynos 4412 GIC Configuration  Total 160 interrupts including Software Generated Interrupts (SGIs), Private Peripheral Interrupts (PPIs) and Shared Peripheral Interrupts (SPIs) are supported.  For SPI, you can service maximal 32  4 = 128 interrupt requests. Table 6-1 describes the GIC configuration values. Table 6-1 Items AMBA Protocol Software Generated Interrupts (SGI) Private Peripheral Interrupts (PPI) Shared Peripheral Interrupts (SPI) Priority Level Legacy interrupt Support Number of CPUs CPU Interface AXI ID Width Distributer AXI ID Width Security Domains Lockable SPIs Legacy dialog SGI Register Level Selection SPI Register Level Selection PPI Register Level Selection PPI sensitivity PPI Registering SPI Registering GIC Configuration Values Configuration Values AXI 16 8 128 256 No 2 10 10 2 (Supports TrustZone technology) 31 – (Legacy interrupts are not used) 0xF (default value) 0x3FF (default value) 0xF (default value) ppi_cx[0] – ppi_cx[5]: edge ppi_cx[6] – ppi_cx[10]: level ppi_cx[11]: edge ppi_cx[12]: level ppi_cx[13] – ppi_cx[14]: edge ppi_cx[15]: level Synchronized (for all PPI) Synchronized (for all SPI) 6-3 Exynos 4412_UM 6.3 Interrupt Source This section includes:  Interrupt source connection  GIC interrupt table 6.3.1 Interrupt Sources Connection Figure 6-1 illustrates the interrupt sources connection. ARM Core 6 Interrupt Controller nfiq_c0 nirq_c0 nfiq_c1 nirq_c1 nfiq_c2 nirq_c2 nfiq_c3 nirq_c3 GIC (PL390) Interrupt Source SPI[127:0] AXI IF for Distri. AXI IF for CPU IF Non-Combined Interrupt Core_SFR Interconnections Non-Combined ... Interrupt [127:32] ... Combined Interrupt [31:0] INT_COMBINER (INSTANCE1) ... Non-Combined Interrupt APB IF for INT_COMBINER ... Figure 6-1 Interrupt Sources Connection GIC interrupt sources are passed INT_COMBINER block that is combined interrupt sources for GIC. 6-4 Exynos 4412_UM 6 Interrupt Controller 6.3.2 GIC Interrupt Table Total 160 interrupts including Software Generated Interrupts (SGIs[15:0], ID[15:0]), Private Peripheral Interrupts (PPIs[15:0], ID[31:16]) and Shared Peripheral Interrupts (SPIs[127:0], ID[159:32]) are supported. For SPI, you can service a maximal 32  4 = 128 interrupt requests. Table 6-2 describes the GIC interrupt (SPI[127:]). SPI Port No 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 Table 6-2 GIC Interrupt Table (SPI[127:0]) ID Int_I_Combiner Interrupt Source 159 – G3D_IRQGP 158 – G3D_IRQPP3 157 – G3D_IRQPP2 156 – G3D_IRQPP1 155 – G3D_IRQPP0 154 – G3D_IRQGPMMU 153 – G3D_IRQPPMMU3 152 – G3D_IRQPPMMU2 151 – G3D_IRQPPMMU1 150 – G3D_IRQPPMMU0 149 – G3D_IRQPMU 148 – C2C_SSCM[1] 147 – TSI 146 – CEC 145 – SLIMBUS 144 – SSS 143 – GPS 142 – PMU 141 – KEYPAD IntG17_7 L2_IRQ IntG17_6 Reserved IntG17_5 SYSMMU_ISP_CX[1] IntG17_4 140 IntG17_3 SYSMMU_FIMC_FD[1] SYSMMU_FIMC_DRC[1] IntG17_2 SYSMMU_FIMC_ISP[1] IntG17_1 SYSMMU_FIMC_Lite1[1] IntG17_0 SYSMMU_FIMC_Lite0[1] IntG16_7 L3_IRQ 139 IntG16_6 Reserved IntG16_5 SYSMMU_ISP_CX[0] Source Block – – – – – – – – – – – – – – – – – – – MCT – – – – – MCT – – 6-5 Exynos 4412_UM SPI Port No 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 ID Int_I_Combiner Interrupt Source IntG16_4 SYSMMU_FIMC_FD[0] IntG16_3 SYSMMU_FIMC_DRC[0] IntG16_2 SYSMMU_FIMC_ISP[0] IntG16_1 SYSMMU_FIMC_Lite1[0] IntG16_0 SYSMMU_FIMC_Lite0[0] 138 – FIMC_lite1 137 – FIMC_lite0 136 – SPDIF 135 – PCM2 134 – PCM1 133 – PCM0 132 – AC97 131 – I2S2 130 – I2S1 129 – I2S0 128 – AUDIO_SS 127 – ISP[1] 126 – MFC 125 – HDMI_I2C 124 – HDMI 123 – MIXER 122 – ISP[0] 121 – G2D 120 – JPEG 119 – FIMC3 118 – FIMC2 117 – FIMC1 116 – FIMC0 115 – ROTATOR 114 – Reserved 113 – Reserved 112 – MIPI_CSI_2LANE 111 – MIPI_DSI_4LANE 110 – MIPI_CSI_4LANE 109 – SDMMC 108 – HSMMC3 107 – HSMMC2 6-6 6 Interrupt Controller Source Block – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Exynos 4412_UM 6 Interrupt Controller SPI Port No 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ID Int_I_Combiner Interrupt Source 106 – HSMMC1 105 – HSMMC0 104 – GPIO_C2C 103 – HSOTG 102 – UHOST 101 – G1_IRQ 100 – SPI2 99 – SPI1 98 – SPI0 97 – I2C7 96 – I2C6 95 – I2C5 94 – I2C4 93 – I2C3 92 – I2C2 91 – I2C1 90 – I2C0 89 – G0_IRQ 88 – Reserved 87 – UART3 86 – UART2 85 – UART1 84 – UART0 83 – NFC 82 – IEM_IEC 81 – IEM_APC IntG18_7 Reserved IntG18_6 CPU_nIRQOUT[2] IntG18_5 PARITYFAILSCU[2] IntG18_4 80 IntG18_3 PARITYFAIL2 nCTIIRQ[2] IntG18_2 PMUIRQ[2] IntG18_1 Reserved IntG18_0 L1_IRQ 79 – GPIO_LB 78 – GPIO_RT 77 – RTC_TIC Source Block – – – – USB HOST MCT – – – – – – – – – – – – – – – – – – – – – – Parity fails for SCU from CPU2 L1 parity fails for CPU2 F4Q CTI interrupt for CPU2 F4Q PMU interrupt from CPU2 – MCT – – – 6-7 Exynos 4412_UM 6 Interrupt Controller SPI Port No 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ID Int_I_Combiner Interrupt Source 76 – RTC_ALARM 75 – WDT IntG19_7 Reserved IntG19_6 CPU_nIRQOUT[3] IntG19_5 PARITYFAILSCU[3] IntG19_4 74 IntG19_3 PARITYFAIL3 nCTIIRQ[3] IntG19_2 PMUIRQ[3] IntG19_1 Reserved IntG19_0 L0_IRQ 73 – TIMER4 72 – TIMER3 71 – TIMER2 70 – TIMER1 69 – TIMER0 68 – PDMA1 67 – PDMA0 66 – MDMA 65 – C2C_SSCM[0] 64 – EINT16_31 63 – EINT[15] 62 – EINT[14] 61 – EINT[13] 60 – EINT[12] 59 – EINT[11] 58 – EINT[10] 57 – EINT[9] 56 – EINT[8] 55 – EINT[7] 54 – EINT[6] 53 – EINT[5] 52 – EINT[4] 51 – EINT[3] 50 – EINT[2] 49 – EINT[1] 48 – EINT[0] 47 IntG15_7 DECERRINTR Source Block – – – – Parity fails for SCU from CPU3 L1 parity fails for CPU3 F4Q CTI interrupt for CPU3 F4Q PMU interrupt from CPU3 – MCT – – – – – – – – – External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt F4D 6-8 Exynos 4412_UM 6 Interrupt Controller SPI Port No 14 13 12 11 10 ID Int_I_Combiner Interrupt Source IntG15_6 SLVERRINTR IntG15_5 ERRRDINTR IntG15_4 ERRRTINTR IntG15_3 ERRWDINTR IntG15_2 ERRWTINTR IntG15_1 ECNTRINTR IntG15_0 SCUEVABORT IntG14_6 CPU_nIRQOUT[1] IntG14_5 Reserved IntG14_4 Reserved 46 IntG14_3 Reserved IntG14_2 Reserved IntG14_1 Reserved IntG14_0 Reserved IntG13_5 CPU_nIRQOUT[0] IntG13_4 Reserved IntG13_3 45 IntG13_2 Reserved Reserved IntG13_1 Reserved IntG13_0 Reserved IntG12_7 G3 IntG12_6 G2 IntG12_5 G1 IntG12_4 44 IntG12_3 G0 Reserved IntG12_2 Reserved IntG12_1 MIPI_HSI IntG12_0 UART4 IntG11_3 LCD0[3] IntG11_2 43 IntG11_1 LCD0[2] LCD0[1] IntG11_0 LCD0[0] IntG10_7 DMC1_PPC_PEREV_M IntG10_6 DMC1_PPC_PEREV_A 42 IntG10_5 DMC0_PPC_PEREV_M IntG10_4 DMC0_PPC_PEREV_A IntG10_3 ADC Source Block F4D F4D F4D F4D F4D F4D F4D F4D – – – – – – F4D – – – – – MCT – – MIPI UART – – – – DMC1 DMC1 DMC0 DMC0 General ADC 6-9 Exynos 4412_UM 6 Interrupt Controller SPI Port No 9 8 7 6 5 ID Int_I_Combiner Interrupt Source IntG10_2 L2CACHE IntG10_1 RP_TIMER IntG10_0 GPIO_AUDIO IntG9_7 PPMU_ISP_X IntG9_6 PPMU_MFC_M1 IntG9_5 PPMU_MFC_M0 IntG9_4 41 IntG9_3 PPMU_3D PPMU_TV_M0 IntG9_2 PPMU_FILE_D_M0 IntG9_1 PPMU_ISP_MX IntG9_0 PPMU_LCD0 IntG8_7 PPMU_IMAGE_M0 IntG8_6 PPMU_CAMIF_M0 IntG8_5 PPMU_D_RIGHT_M0 IntG8_4 40 IntG8_3 PPMU_D_LEFT_M0 PPMU_ACP0_M0 IntG8_2 PPMU_XIU_R_S1 IntG8_1 PPMU_XIU_R IntG8_0 PPMU_XIU_L IntG7_7 Reserved IntG7_6 SYSMMU_MFC_M1[1] IntG7_5 SYSMMU_MFC_M0[1] IntG7_4 39 IntG7_3 SYSMMU_TV_M0[1] Reserved IntG7_2 SYSMMU_LCD0_M0[1] IntG7_1 SYSMMU_GPS[1] IntG7_0 SYSMMU_ROTATOR[1] IntG6_7 SYSMMU_2D[1] IntG6_6 SYSMMU_JPEG[1] IntG6_5 SYSMMU_FIMC3[1] IntG6_4 38 IntG6_3 SYSMMU_FIMC2[1] SYSMMU_FIMC1[1] IntG6_2 SYSMMU_FIMC0[1] IntG6_1 SYSMMU_SSS[1] IntG6_0 SYSMMU_MDMA[1] IntG5_7 37 IntG5_6 Reserved SYSMMU_MFC_M1[0] Source Block F4D – – PPMU for ISP X PPMU for MFC_M1 PPMU for MFC_M0 PPMU for 3D PPMU for TV_M0 PPMU for FILE_D_M0 PPMU for ISP MX PPMU for LCD0 PPMU for IMAGE_M0 PPMU for CAMIF_M0 PPMU for D_right_M0 PPMU for D_left_M0 PPMU for ACP0_M0 PPMU for XIU_R_S1 PPMU for XIU_R PPMU for XIU_L – System MMU for MFC_M1 System MMU for MFC_M0 System MMU for TV_M0 – System MMU for LCD0_M0 System MMU for GPS System MMU for Rotator System MMU for 2D System MMU for JPEG System MMU for FIMC3 System MMU for FIMC2 System MMU for FIMC1 System MMU for FIMC0 System MMU for SSS System MMU for MDMA – System MMU for MFC_M1 6-10 Exynos 4412_UM 6 Interrupt Controller SPI Port No 4 3 2 1 0 ID Int_I_Combiner Interrupt Source IntG5_5 SYSMMU_MFC_M0[0] IntG5_4 SYSMMU_TV_M0[0] IntG5_3 Reserved IntG5_2 SYSMMU_LCD0_M0[0] IntG5_1 SYSMMU_GPS[0] IntG5_0 SYSMMU_ROTATOR[0] IntG4_7 SYSMMU_2D[0] IntG4_6 SYSMMU_JPEG[0] IntG4_5 SYSMMU_FIMC3[0] IntG4_4 36 IntG4_3 SYSMMU_FIMC2[0] SYSMMU_FIMC1[0] IntG4_2 SYSMMU_FIMC0[0] IntG4_1 SYSMMU_SSS[0] IntG4_0 SYSMMU_MDMA[0] IntG3_6 nCTIIRQ_ISP IntG3_5 PMUIRQ_ISP IntG3_4 TMU 35 IntG3_3 nCTIIRQ[1] IntG3_2 PMUIRQ[1] IntG3_1 PARITYFAILSCU[1] IntG3_0 PARITYFAIL1 IntG2_6 PARRINTR IntG2_5 PARRDINTR IntG2_4 TMU 34 IntG2_3 nCTIIRQ[0] IntG2_2 PMUIRQ[0] IntG2_1 PARITYFAILSCU[0] IntG2_0 PARITYFAIL0 IntG1_3 TZASC1[1] IntG1_2 33 IntG1_1 TZASC1[0] TZASC0[1] IntG1_0 TZASC0[0] IntG0_3 MDNIE_LCD0[3] IntG0_2 32 IntG0_1 MDNIE_LCD0[2] MDNIE_LCD0[1] IntG0_0 MDNIE_LCD0[0] Source Block System MMU for MFC_M0 System MMU for TV_M0 – System MMU for LCD0_M0 System MMU for GPS System MMU for Rotator System MMU for 2D System MMU for JPEG System MMU for FIMC3 System MMU for FIMC2 System MMU for FIMC1 System MMU for FIMC0 System MMU for SSS System MMU for MDMA ISP CTI interrupt ISP PMU interrupt – F4D CTI interrupt for CPU1 F4D PMU interrupt from CPU1 Parity fails for SCU from CPU1 L1 parity fails for CPU1 Parity error on L2 tag RAM Parity error on L2 data RAM – F4D CTI interrupt for CPU0 F4D PMU interrupt from CPU0 Parity fails for SCU from CPU0 L1 parity fails for CPU0 – – – – – – – – 6-11 Exynos 4412_UM 6 Interrupt Controller Table 6-3 describes the GIC interrupt (PPI[15:0]). Table 6-3 GIC Interrupt Table (PPI[15:0]) PPI Port No ID 15 31 14 30 13 29 12 28 11 27 10 26 9 25 8 24 7 23 6 22 5 21 4 20 3 19 2 18 1 17 0 16 Interrupt Source Reserved Reserved Reserved L3_IRQ (for CPU3) or L2_IRQ (for CPU2) or L1_IRQ (for CPU1) or L0_IRQ (for CPU0) Reserved G3_IRQ (for CPU3) or G2_IRQ (for CPU2) or G1_IRQ (for CPU1) or G0_IRQ (for CPU0) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Source Block – – – MCT – MCT – – – – – – – – – – 6-12 Exynos 4412_UM 6.4 Functional Overview Please refer to the GIC PL390 technical reference manual. 6 Interrupt Controller 6-13 Exynos 4412_UM 6.5 Register Description 6.5.1 Register Map Summary  Base Address: 0x1048_0000 Register ICCICR_CPU0 ICCPMR_CPU0 ICCBPR_CPU0 ICCIAR_CPU0 ICCEOIR_CPU0 ICCRPR_CPU0 ICCHPIR_CPU0 ICCABPR_CPU0 INTEG_EN_C_CPU0 INTERRUPT_ OUT_CPU0 ICCIIDR ICCICR_CPU1 ICCPMR_CPU1 ICCBPR_CPU1 ICCIAR_CPU1 ICCEOIR_CPU1 ICCRPR_CPU1 ICCHPIR_CPU1 ICCABPR_CPU1 INTEG_C_EN_CPU1 INTERRUPT_ OUT_CPU1 ICCICR_CPU2 ICCPMR_CPU2 ICCBPR_CPU2 ICCIAR_CPU2 ICCEOIR_CPU2 ICCRPR_CPU2 ICCHPIR_CPU2 ICCABPR_CPU2 INTEG_C_EN_CPU2 INTERRUPT_ OUT_CPU2 Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0040 0x0044 0x00FC 0x4000 0x4004 0x4008 0x400C 0x4010 0x4014 0x4018 0x401C 0x4040 0x4044 0x8000 0x8004 0x8008 0x800C 0x8010 0x8014 0x8018 0x801C 0x8040 0x8044 Description CPU interface control register Interrupt priority mask register Binary point register Interrupt acknowledge register End of interrupt register Running priority register Highest pending interrupt register Aliased binary point register Integration test enable register Interrupt output register CPU interface identification register CPU interface control register Interrupt priority mask register Binary point register Interrupt acknowledge register End of interrupt register Running priority register Highest pending interrupt register Aliased binary point register Integration test enable register Interrupt output register CPU interface control register Interrupt priority mask register Binary point register Interrupt acknowledge register End of interrupt register Running priority register Highest pending interrupt register Aliased binary point register Integration test enable register Interrupt output register 6-14 6 Interrupt Controller Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_03FF Undefined 0x0000_00FF 0x0000_03FF 0x0000_0000 0x0000_0000 0x0000_0000 0x3901_043B 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_03FF Undefined 0x0000_00FF 0x0000_03FF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_03FF Undefined 0x0000_00FF 0x0000_03FF 0x0000_0000 0x0000_0000 0x0000_0000 Exynos 4412_UM Register ICCICR_CPU3 ICCPMR_CPU3 ICCBPR_CPU3 ICCIAR_CPU3 ICCEOIR_CPU3 ICCRPR_CPU3 ICCHPIR_CPU3 ICCABPR_CPU3 INTEG_C_EN_CPU3 INTERRUPT_ OUT_CPU3 Offset 0xC000 0xC004 0xC008 0xC00C 0xC010 0xC014 0xC018 0xC01C 0xC040 0xC044 Description CPU interface control register Interrupt priority mask register Binary point register Interrupt acknowledge register End of interrupt register Running priority register Highest pending interrupt register Aliased binary point register Integration test enable register Interrupt output register 6 Interrupt Controller Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_03FF Undefined 0x0000_00FF 0x0000_03FF 0x0000_0000 0x0000_0000 0x0000_0000 6-15 Exynos 4412_UM  Base Address: 0x1049_0000 Register ICDDCR ICDICTR ICDIIDR ICDISR0_CPU0 ICDISR1 ICDISR2 ICDISR3 ICDISR4 ICDISER0_CPU0 ICDISER1 ICDISER2 ICDISER3 ICDISER4 ICDICER0_CPU0 ICDICER1 ICDICER2 ICDICER3 ICDICER4 ICDISPR0_CPU0 ICDISPR1 ICDISPR2 ICDISPR3 ICDISPR4 ICDICPR0_CPU0 ICDICPR1 ICDICPR2 ICDICPR3 ICDICPR4 ICDABR0_CPU0 ICDABR1 ICDABR2 ICDABR3 ICDABR4 ICDIPR0_CPU0 ICDIPR1_CPU0 ICDIPR2_CPU0 Offset 0x0000 0x0004 0x0008 0x0080 0x0084 0x0088 0x008C 0x0090 0x0100 0x0104 0x0108 0x010C 0x0110 0x0180 0x0184 0x0188 0x018C 0x0190 0x0200 0x0204 0x0208 0x020C 0x0210 0x0280 0x0284 0x0288 0x028C 0x0290 0x0300 0x0304 0x0308 0x030C 0x0310 0x0400 0x0404 0x0408 Description Distributor control register Interrupt controller type register Distributor implementer identification register Interrupt security registers (SGI,PPI) Interrupt security registers (SPI[31:0]) Interrupt security registers (SPI[63:32]) Interrupt security registers (SPI[95:64]) Interrupt security registers (SPI[127:96]) Interrupt set-enable register (SGI,PPI) Interrupt set-enable register (SPI[31:0]) Interrupt set-enable register (SPI[63:32]) Interrupt set-enable register (SPI[95:64]) Interrupt set-enable register (SPI[127:96]) Interrupt clear-enable register (SGI,PPI) Interrupt clear-enable register (SPI[31:0]) Interrupt clear-enable register (SPI[63:32]) Interrupt clear-enable register (SPI[95:64]) Interrupt clear-enable register (SPI[127:96]) Interrupt pending-set register (SGI,PPI) Interrupt pending-set register (SPI[31:0]) Interrupt pending-set register (SPI[63:32]) Interrupt pending-set register (SPI[95:64]) Interrupt pending-set register (SPI[127:96]) Interrupt pending-clear register (SGI,PPI) Interrupt pending-clear register (SPI[31:0]) Interrupt pending-clear register (SPI[63:32]) Interrupt pending-clear register (SPI[95:64]) Interrupt pending-clear register(SPI[127:96]) Active bit register (SGI, PPI) Active bit register (SPI[31:0]) Active bit register (SPI[63:32]) Active bit register (SPI[95:64]) Active bit register (SPI[127:96]) Priority level register (SGI[3:0]) Priority level register (SGI[7:4]) Priority level register (SGI[11:8]) 6-16 6 Interrupt Controller Reset Value 0x0000_0000 0x0000_FC24 0x0000_043B 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Exynos 4412_UM Register ICDIPR3_CPU0 ICDIPR4_CPU0 ICDIPR5_CPU0 ICDIPR6_CPU0 ICDIPR7_CPU0 ICDIPR8 ICDIPR9 ICDIPR10 ICDIPR11 ICDIPR12 ICDIPR13 ICDIPR14 ICDIPR15 ICDIPR16 ICDIPR17 ICDIPR18 ICDIPR19 ICDIPR20 ICDIPR21 ICDIPR22 ICDIPR23 ICDIPR24 ICDIPR25 ICDIPR26 ICDIPR27 ICDIPR28 ICDIPR29 ICDIPR30 ICDIPR31 ICDIPR32 ICDIPR33 ICDIPR34 ICDIPR35 ICDIPR36 ICDIPR37 ICDIPR38 ICDIPR39 Offset 0x040C 0x0410 0x0414 0x0418 0x041C 0x0420 0x0424 0x0428 0x042C 0x0430 0x0434 0x0438 0x043C 0x0440 0x0444 0x0448 0x044C 0x0450 0x0454 0x0458 0x045C 0x0460 0x0464 0x0468 0x046C 0x0470 0x0474 0x0478 0x047C 0x0480 0x0484 0x0488 0x048C 0x0490 0x0494 0x0498 0x049C Description Priority level register (SGI[15:12]) Priority level register (PPI[3:0]) Priority level register (PPI[7:4]) Priority level register (PPI[11:8]) Priority level register (PPI[15:12]) Priority level register (SPI[3:0]) Priority level register (SPI[7:4]) Priority level register (SPI[11:8]) Priority level register (SPI[15:12]) Priority level register (SPI[19:16]) Priority level register (SPI[23:20]) Priority level register (SPI[27:24]) Priority level register (SPI[31:28]) Priority level register (SPI[35:32]) Priority level register (SPI[39:36]) Priority level register (SPI[43:40]) Priority level register (SPI[47:44]) Priority level register (SPI[51:48]) Priority level register (SPI[55:52]) Priority level register (SPI[59:56]) Priority level register (SPI[63:60]) Priority level register (SPI[67:64]) Priority level register (SPI[71:68]) Priority level register (SPI[75:72]) Priority level register (SPI[79:76]) Priority level register (SPI[83:80]) Priority level register (SPI[87:84]) Priority level register (SPI[91:98]) Priority level register (SPI[95:92]) Priority level register (SPI[99:96]) Priority level register (SPI[103:100]) Priority level register (SPI[107:104]) Priority level register (SPI[111:108]) Priority level register (SPI[115:112]) Priority level register (SPI[119:116]) Priority level register (SPI[123:120]) Priority level register (SPI[127:124]) 6-17 6 Interrupt Controller Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Exynos 4412_UM Register ICDIPTR0_CPU0 ICDIPTR1_CPU0 ICDIPTR2_CPU0 ICDIPTR3_CPU0 ICDIPTR4_CPU0 ICDIPTR5_CPU0 ICDIPTR6_CPU0 ICDIPTR7_CPU0 ICDIPTR8 ICDIPTR9 ICDIPTR10 ICDIPTR11 ICDIPTR12 ICDIPTR13 ICDIPTR14 ICDIPTR15 ICDIPTR16 ICDIPTR17 ICDIPTR18 ICDIPTR19 ICDIPTR20 ICDIPTR21 ICDIPTR22 ICDIPTR23 ICDIPTR24 ICDIPTR25 ICDIPTR26 ICDIPTR27 ICDIPTR28 ICDIPTR29 ICDIPTR30 ICDIPTR31 ICDIPTR32 ICDIPTR33 ICDIPTR34 ICDIPTR35 ICDIPTR36 Offset 0x0800 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0820 0x0824 0x0828 0x082C 0x0830 0x0834 0x0838 0x083C 0x0840 0x0844 0x0848 0x084C 0x0850 0x0854 0x0858 0x085C 0x0860 0x0864 0x0868 0x086C 0x0870 0x0874 0x0878 0x087C 0x0880 0x0884 0x0888 0x088C 0x0890 Description Processor targets register (SGI[3:0]) Processor targets register (SGI[7:4]) Processor targets register (SGI[11:8]) Processor targets register (SGI[15:12]) Processor targets register (PPI[3:0]) Processor targets register (PPI[7:4]) Processor targets register (PPI[11:8]) Processor targets register (PPI[15:12]) Processor targets register (SPI[3:0]) Processor targets register (SPI[7:4]) Processor targets register (SPI[11:8]) Processor targets register (SPI[15:12]) Processor targets register (SPI[19:16]) Processor targets register (SPI[23:20]) Processor targets register (SPI[27:24]) Processor targets register (SPI[31:28]) Processor targets register (SPI[35:32]) Processor targets register (SPI[39:36]) Processor targets register (SPI[43:40]) Processor targets register (SPI[47:44]) Processor targets register (SPI[51:48]) Processor targets register (SPI[55:52]) Processor targets register (SPI[59:56]) Processor targets register (SPI[63:60]) Processor targets register (SPI[67:64]) Processor targets register (SPI[71:68]) Processor targets register (SPI[75:72]) Processor targets register (SPI[79:76]) Processor targets register (SPI[83:80]) Processor targets register (SPI[87:84]) Processor targets register (SPI[91:98]) Processor targets register (SPI[95:92]) Processor targets register (SPI[99:96]) Processor targets register (SPI[103:100]) Processor targets register (SPI[107:104]) Processor targets register (SPI[111:108]) Processor targets register (SPI[115:112]) 6-18 6 Interrupt Controller Reset Value 0x0101_0101 0x0101_0101 0x0101_0101 0x0101_0101 0x0101_0101 0x0101_0101 0x0101_0101 0x0101_0101 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Exynos 4412_UM Register ICDIPTR37 ICDIPTR38 ICDIPTR39 ICDICFR0_CPU0 ICDICFR1_CPU0 ICDICFR2 ICDICFR3 ICDICFR4 ICDICFR5 ICDICFR6 ICDICFR7 ICDICFR8 ICDICFR9 PPI_STATUS_CPU0 SPI_STATUS0 SPI_STATUS1 SPI_STATUS2 SPI_STATUS3 ICDSGIR ICDISR0_CPU1 ICDISER0_CPU1 ICDICER0_CPU1 ICDISPR0_CPU1 ICDICPR0_CPU1 ICDABR0_CPU1 ICDIPR0_CPU1 ICDIPR1_CPU1 ICDIPR2_CPU1 ICDIPR3_CPU1 ICDIPR4_CPU1 ICDIPR5_CPU1 ICDIPR6_CPU1 ICDIPR7_CPU1 ICDIPTR0_CPU1 ICDIPTR1_CPU1 ICDIPTR2_CPU1 ICDIPTR3_CPU1 Offset 0x0894 0x0898 0x089C 0x0C00 0x0C04 0x0C08 0x0C0C 0x0C10 0x0C14 0x0C18 0x0C1C 0x0C20 0x0C24 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D10 0x0F00 0x4080 0x4100 0x4180 0x4200 0x4280 0x4300 0x4400 0x4404 0x4408 0x440C 0x4410 0x4414 0x4418 0x441C 0x4800 0x4804 0x4808 0x480C Description Processor targets register (SPI[119:116]) Processor targets register (SPI[123:120]) Processor targets register (SPI[127:124]) Interrupt configuration register (SGI[15:0]) Interrupt configuration register (PPI[15:0]) Interrupt configuration register (SPI[15:0]) Interrupt configuration register (SPI[31:16]) Interrupt configuration register (SPI[47:32]) Interrupt configuration register (SPI[63:48]) Interrupt configuration register (SPI[79:64]) Interrupt configuration register (SPI[95:80]) Interrupt configuration register (SPI[111:95]) Interrupt configuration register (SPI[127:112]) PPI status register SPI[31:0] status register SPI[63:32] status register SPI[95:64] status register SPI[127:96] status register Software generated interrupt register Interrupt security registers (SGI,PPI) Interrupt set-enable register (SGI,PPI) Interrupt clear-enable register (SGI,PPI) Interrupt pending-set register (SGI,PPI) Interrupt pending-clear register (SGI,PPI) Active status register (SGI, PPI) Priority level register (SGI[3:0]) Priority level register (SGI[7:4]) Priority level register (SGI[11:8]) Priority level register (SGI[15:12]) Priority level register (PPI[3:0]) Priority level register (PPI[7:4]) Priority level register (PPI[11:8]) Priority level register (PPI[15:12]) Processor targets register (SGI[3:0]) Processor targets register (SGI[7:4]) Processor targets register (SGI[11:8]) Processor targets register (SGI[15:12]) 6-19 6 Interrupt Controller Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0xAAAA_AAAA 0x7DD5_5FFF 0x5555_5555 0x5555_5555 0x5555_5555 0x5555_5555 0x5555_5555 0x5555_5555 0x5555_5555 0x5555_5555 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Undefined 0x0000_0000 0x0000_FFFF 0x0000_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 Exynos 4412_UM Register ICDIPTR4_CPU1 ICDIPTR5_CPU1 ICDIPTR6_CPU1 ICDIPTR7_CPU1 ICDICFR0_CPU1 ICDICFR1_CPU1 PPI_STATUS_CPU1 ICDISR0_CPU2 ICDISER0_CPU2 ICDICER0_CPU2 ICDISPR0_CPU2 ICDICPR0_CPU2 ICDABR0_CPU2 ICDIPR0_CPU2 ICDIPR1_CPU2 ICDIPR2_CPU2 ICDIPR3_CPU2 ICDIPR4_CPU2 ICDIPR5_CPU2 ICDIPR6_CPU2 ICDIPR7_CPU2 ICDIPTR0_CPU2 ICDIPTR1_CPU2 ICDIPTR2_CPU2 ICDIPTR3_CPU2 ICDIPTR4_CPU2 ICDIPTR5_CPU2 ICDIPTR6_CPU2 ICDIPTR7_CPU2 ICDICFR0_CPU2 ICDICFR1_CPU2 PPI_STATUS_CPU2 ICDISR0_CPU3 ICDISER0_CPU3 ICDICER0_CPU3 ICDISPR0_CPU3 ICDICPR0_CPU3 Offset 0x4810 0x4814 0x4818 0x481C 0x4C00 0x4C04 0x4D00 0x8080 0x8100 0x8180 0x8200 0x8280 0x8300 0x8400 0x8404 0x8408 0x840C 0x8410 0x8414 0x8418 0x841C 0x8800 0x8804 0x8808 0x880C 0x8810 0x8814 0x8818 0x881C 0x8C00 0x8C04 0x8D00 0xC080 0xC100 0xC180 0xC200 0xC280 Description Processor targets register (PPI[3:0]) Processor targets register (PPI[7:4]) Processor targets register (PPI[11:8]) Processor targets register (PPI[15:12]) Interrupt configuration register (SGI[15:0]) Interrupt configuration register (PPI[15:0]) PPI status register Interrupt security registers (SGI,PPI) Interrupt set-enable register (SGI,PPI) Interrupt clear-enable register (SGI,PPI) Interrupt pending-set register (SGI,PPI) Interrupt pending-clear register (SGI,PPI) Active status register (SGI, PPI) Priority level register (SGI[3:0]) Priority level register (SGI[7:4]) Priority level register (SGI[11:8]) Priority level register (SGI[15:12]) Priority level register (PPI[3:0]) Priority level register (PPI[7:4]) Priority level register (PPI[11:8]) Priority level register (PPI[15:12]) Processor targets register (SGI[3:0]) Processor targets register (SGI[7:4]) Processor targets register (SGI[11:8]) Processor targets register (SGI[15:12]) Processor targets register (PPI[3:0]) Processor targets register (PPI[7:4]) Processor targets register (PPI[11:8]) Processor targets register (PPI[15:12]) Interrupt configuration register (SGI[15:0]) Interrupt configuration register (PPI[15:0]) PPI status register Interrupt security registers (SGI,PPI) Interrupt set-enable register (SGI,PPI) Interrupt clear-enable register (SGI,PPI) Interrupt pending-set register (SGI,PPI) Interrupt pending-clear register (SGI,PPI) 6-20 6 Interrupt Controller Reset Value 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0xAAAA_AAAA 0x7DD5_5FFF 0x0000_0000 0x0000_0000 0x0000_FFFF 0x0000_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0xAAAA_AAAA 0x7DD5_5FFF 0x0000_0000 0x0000_0000 0x0000_FFFF 0x0000_FFFF 0x0000_0000 0x0000_0000 Exynos 4412_UM Register ICDABR0_CPU3 ICDIPR0_CPU3 ICDIPR1_CPU3 ICDIPR2_CPU3 ICDIPR3_CPU3 ICDIPR4_CPU3 ICDIPR5_CPU3 ICDIPR6_CPU3 ICDIPR7_CPU3 ICDIPTR0_CPU3 ICDIPTR1_CPU3 ICDIPTR2_CPU3 ICDIPTR3_CPU3 ICDIPTR4_CPU3 ICDIPTR5_CPU3 ICDIPTR6_CPU3 ICDIPTR7_CPU3 ICDICFR0_CPU3 ICDICFR1_CPU3 PPI_STATUS_CPU3 Offset 0xC300 0xC400 0xC404 0xC408 0xC40C 0xC410 0xC414 0xC418 0xC41C 0xC800 0xC804 0xC808 0xC80C 0xC810 0xC814 0xC818 0xC81C 0xCC00 0xCC04 0xCD00 Description Active status register (SGI, PPI) Priority level register (SGI[3:0]) Priority level register (SGI[7:4]) Priority level register (SGI[11:8]) Priority level register (SGI[15:12]) Priority level register (PPI[3:0]) Priority level register (PPI[7:4]) Priority level register (PPI[11:8]) Priority level register (PPI[15:12]) Processor targets register (SGI[3:0]) Processor targets register (SGI[7:4]) Processor targets register (SGI[11:8]) Processor targets register (SGI[15:12]) Processor targets register (PPI[3:0]) Processor targets register (PPI[7:4]) Processor targets register (PPI[11:8]) Processor targets register (PPI[15:12]) Interrupt configuration register (SGI[15:0]) Interrupt configuration register (PPI[15:0]) PPI status register 6 Interrupt Controller Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0x0202_0202 0xAAAA_AAAA 0x7DD5_5FFF 0x0000_0000 6-21 Exynos 4412_UM 7 Interrupt Combiner 7 Interrupt Combiner 7.1 Overview Interrupt controller in Exynos 4412 consists of:  PrimeCell generic interrupt controller (PL390)  Interrupt combiner A few interrupt sources are grouped in Exynos 4412. Interrupt combiner combines several interrupt sources as a group. Several interrupt requests in a group make a group interrupt request and a single request signal. As a result, the interrupt input sources of PrimeCell generic interrupt controller consists of the group interrupt requests from the interrupt combiner and uncombined interrupt sources. 7.2 Features The features of Interrupt Combiner are:  116 interrupt source inputs.  18 group interrupt outputs.  Enables or masks each interrupt source in a group.  Provides the status of interrupt source in a group before interrupt masking.  Provides the status of interrupt source in a group after interrupt masking.  Provides the status of group interrupt output after interrupt masking and combining 7-1 Exynos 4412_UM 7 Interrupt Combiner 7.3 Functional Description 7.3.1 Block Diagram There is a interrupt combiner in Exynos 4412. The interrupt combiner combines a few interrupts source into 18 group interrupt request outputs. The inputs of the GIC unit outside the ARM Core unit connect to the group interrupt request outputs. Figure 7-1 illustrates the block diagram of interrupt combiner. ARM Core nfiq_c0 nirq_c0 nfiq_c1 nirq_c1 nfiq_c2 nirq_c2 nfiq_c3 nirq_c3 ... GIC (PL390) Interrupt Source SPI[127:0] Non-Combined ... Interrupt [127:32] ... Combined Interrupt [31:0] INT_COMBINER (INSTANCE1) ... ... Non-Combined Interrupt Figure 7-1 Block Diagram of Interrupt Combiner 7-2 Exynos 4412_UM 7.4 Interrupt Sources This section includes:  Interrupt Combiner 7.4.1 Interrupt Combiner Table 7-1 describes the interrupt groups of interrupt combiner. Table 7-1 Interrupt Groups of Interrupt Combiner Combiner Group ID Combined Interrupt Source Name INTG0 Reserved INTG1 TZASC INTG2 PARITYFAIL0/ F4DCTI0/PMU0 INTG3 PARITYFAIL1/ F4DCTI1/PMU1 INTG4 SYSMMU[7:0] Bit Interrupt Source [3] Reserved [2] Reserved [1] Reserved [0] Reserved [3] TZASC1[1] [2] TZASC1[0] [1] TZASC0[1] [0] TZASC0[0] [6] PARRINTR [5] PARRDINTR [4] TMU [3] nCTIIRQ[0] [2] PMUIRQ[0] [1] PARITYFAILSCU[0] [0] PARITYFAIL0 [6] nCTIIRQ_ISP [5] PMUIRQ_ISP [4] TMU [3] nCTIIRQ[1] [2] PMUIR[1] [1] PARITYFAILSC[1] [0] PARITYFAIL1 [7] SYSMMU_2D[0] [6] SYSMMU_JPEG[0] [5] SYSMMU_FIMC3[0] [4] SYSMMU_FIMC2[0] [3] SYSMMU_FIMC1[0] [2] SYSMMU_FIMC0[0] 7 Interrupt Combiner Source Block Reserved TZASC CPU0 CPU1 System MMU 7-3 Exynos 4412_UM 7 Interrupt Combiner Combiner Group ID Combined Interrupt Source Name INTG5 SYSMMU[15:8] INTG6 SYSMMU[23:16] INTG7 SYSMMU[31:24] INTG8 PPMU [7:0] INTG9 PPMU [14:8] Bit Interrupt Source [1] SYSMMU_SSS[0] [0] SYSMMU_MDMA[0] [7] Reserved [6] SYSMMU_MFC_M1[0] [5] SYSMMU_MFC_M0[0] [4] SYSMMU_TV_M0[0] [3] Reserved [2] SYSMMU_LCD0_M0[0] [1] SYSMMU_GPS[0] [0] SYSMMU_ROTATOR[0] [7] SYSMMU_2D[1] [6] SYSMMU_JPEG[1] [5] SYSMMU_FIMC3[1] [4] SYSMMU_FIMC2[1] [3] SYSMMU_FIMC1[1] [2] SYSMMU_FIMC0[1] [1] SYSMMU_SSS[1] [0] SYSMMU_MDMA[1] [7] Reserved [6] SYSMMU_MFC_M1[1] [5] SYSMMU_MFC_M0[1] [4] SYSMMU_TV_M0[1] [3] Reserved [2] SYSMMU_LCD0_M0[1] [1] SYSMMU_GPS[1] [0] SYSMMU_ROTATOR[1] [7] PPMU_IMAGE_M0 [6] PPMU_CAMIF_M0 [5] PPMU_D_RIGHT_M0 [4] PPMU_D_LEFT_M0 [3] PPMU_ACP0_M0 [2] PPMU_XIU_R_S1 [1] PPMU_XIU_R [0] PPMU_XIU_L [6] PPMU_MFC_M1 [5] PPMU_MFC_M0 Source Block System MMU System MMU System MMU PPMU PPMU 7-4 Exynos 4412_UM Combiner Group ID Combined Interrupt Source Name INTG10 DMC1/DMC0/MIU/ L2CACHE INTG11 LCD0 INTG12 MCT/MIPI/UART4 INTG13 CPU INTG14 CPU Bit Interrupt Source [4] PPMU_3D [3] PPMU_TV_M0 [2] PPMU_FILE_D_M0 [1] PPMU_ISP_MX [0] PPMU_LCD0 [7] DMC1_PPC_PEREV_M [6] DMC1_PPC_PEREV_A [5] DMC0_PPC_PEREV_M [4] DMC0_PPC_PEREV_A [3] ADC [2] L2CACHE [1] RP_TIMER [0] GPIO_AUDIO [3] LCD0[3] [2] LCD0[2] [1] LCD0[1] [0] LCD0[0] [7] G3 [6] G2 [5] G1 [4] G0 [1] MIPI_HSI [0] UART4 [5] CPU_nIRQOUT[0] [4] Reserved [3] Reserved [2] Reserved [1] Reserved [0] Reserved [6] CPU_nIRQOUT[1] [5] Reserved [4] Reserved [3] Reserved [2] Reserved [1] Reserved [0] Reserved 7 Interrupt Combiner Source Block DMC1 DMC0 General ADC L2 Cache RP Audio_SS LCD0 MCT MIPI UART CPU CPU 7-5 Exynos 4412_UM 7 Interrupt Combiner Combiner Group ID Combined Interrupt Source Name INTG15 BUS_ERROR/ SCUEVABORT INTG16 ISP INTG17 ISP INTG18 PARITYFAIL2/ F4DCTI2/ PMU2 INTG19 PARITYFAIL3/ F4DCTI3/ PMU3 Bit Interrupt Source [7] DECERRINTR [6] SLVERRINTR [5] ERRRDINTR [4] ERRRTINTR [3] ERRWDINTR [2] ERRWTINTR [1] ECNTRINTR [0] SCUEVABORT [7] L3_IRQ [6] Reserved [5] SYSMMU_ISP_CX[0] [4] SYSMMU_FIMC_FD[0] [3] SYSMMU_FIMC_DRC[0] [2] SYSMMU_FIMC_ISP[0] [1] SYSMMU_FIMC_LITE0[0] [0] SYSMMU_FIMC_LITE0[0] [7] L2_IRQ [6] Reserved [5] SYSMMU_ISP_CX[1] [4] SYSMMU_FIMC_FD[1] [3] SYSMMU_FIMC_DRC[1] [2] SYSMMU_FIMC_ISP[1] [1] SYSMMU_FIMC_LITE0[1] [0] SYSMMU_FIMC_LITE0[1] [6] CPU_nIRQOUT[2] [5] PARITYFAILSCU[2] [4] PARITYFAIL2 [3] nCTIIRQ[2] [2] PMUIRQ[2] [1] Reserved [0] L1_IRQ [6] CPU_nIRQOUT[3] [5] PARITYFAILSCU[3] [4] PARITYFAIL3 [3] nCTIIRQ[3] [2] PMUIRQ[3] Source Block F4D ISP ISP CPU CPU 7-6 Exynos 4412_UM Combiner Group ID Combined Interrupt Source Name Bit Interrupt Source [1] Reserved [0] L0_IRQ 7 Interrupt Combiner Source Block 7-7 Exynos 4412_UM 7 Interrupt Combiner 7.5 Functional Description An interrupt enable bit controls an interrupt source in an interrupt group. IESRn and IECRn registers control the interrupt enable bits. IESRn register can toggle an interrupt bit to "1". If you write "1" to a bit position on IESRn, then it sets the corresponding bit on the interrupt enable bit to "1". However, IECRn register can toggle an interrupt enable bit to "0". If you write "1" to a bit position on IECRn, then it clears the corresponding bit on the interrupt enable bits to "0". This feature will make it easy to address resource sharing issues in a multi-processor system. There are several interrupt sources in an interrupt group. If an interrupt enable bit is "0", then it masks the corresponding interrupt. All the interrupt sources in an interrupt group, including the masked interrupt sources, are ORed to form a combined interrupt request signal. The interrupt combiner connects the combined group interrupt request output to an input of a GIC. You can show each interrupt source status before an interrupt-enable bit masks it by reading ISTRn register. You can show the combined group interrupt request output signal by reading CIPSR0 register. 7-8 Exynos 4412_UM 7.6 Register Description 7.6.1 Register Map Summary  Base Address: 0x1044_0000 Register Offset Interrupt Combiner IESR0 0x0000 IECR0 0x0004 ISTR0 0x0008 IMSR0 0x000C IESR1 0x0010 IECR1 0x0014 ISTR1 0x0018 IMSR1 0x001C IESR2 0x0020 IECR2 0x0024 ISTR2 0x0028 IMSR2 0x002C IESR3 0x0030 IECR3 0x0034 ISTR3 0x0038 IMSR3 0x003C IESR4 0x0040 IECR4 0x0044 ISTR4 0x0048 IMSR4 0x004C CIPSR0 0x0100 Description Interrupt enable set register for group 0 to 3 Interrupt enable clear register for group 0 to 3 Interrupt status register for group 0 to 3 Interrupt masked status register for group 0 to 3 Interrupt enable set register for group 4 to 7 Interrupt enable clear register for group 4 to 7 Interrupt status register for group 4 to 7 Interrupt masked status register for group 4 to 7 Interrupt enable set register for group 8 to 11 Interrupt enable clear register for group 8 to 11 Interrupt status register for group 8 to 11 Interrupt masked status register for group 8 to 11 Interrupt enable set register for group 12 to 15 Interrupt enable clear register for group 12 to 15 Interrupt masked status register for group 12 to 15 Interrupt status register for group 16 to 17 Interrupt enable set register for group 16 to 17 Interrupt enable clear register for group 16 to 17 Interrupt masked status register for group 16 to 17 Interrupt status register for group 16 to 17 Combined interrupt pending status0 7 Interrupt Combiner Reset Value 0x00000000 0x00000000 Undefined Undefined 0x00000000 0x00000000 Undefined Undefined 0x00000000 0x00000000 Undefined Undefined 0x00000000 0x00000000 Undefined Undefined 0x00000000 0x00000000 Undefined Undefined Undefined 7-9 Exynos 4412_UM 7 Interrupt Combiner 7.6.2 Interrupt Combiner 7.6.2.1 IESR0  Base Address: 0x1044_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_0000 Name RSVD nCTIIRQ_ISP PMUIRQ_ISP TMU nCTIIRQ[1] PMUIR[1] PARITYFAILSC[1] PARITYFAIL1 RSVD PARRINTR PARRDINTR TMU nCTIIRQ[0] PMUIRQ[0] PARITYFAILSCU[0] PARITYFAIL0 RSVD TZASC1[1] TZASC1[0] TZASC0[1] TZASC0[0] RSVD RSVD RSVD RSVD RSVD Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15:12] [11] [10] [9] [8] [7:4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW – RW RW RW RW RW RW RW – RW RW RW RW – RW RW RW RW Reserved Description Sets the corresponding interrupt enable bit to "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1" Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reserved Sets the corresponding interrupt enable bit to "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reserved Sets the corresponding interrupt enable bit to "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit 0 = Masks. 1 = Enables. Reserved Sets the corresponding interrupt enable bit to "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reset Value 0x0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 0 0x0 0 0 0 0 0x0 0 0 0 0 7-10 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.2 IECR0  Base Address: 0x1044_0000  Address = Base Address + 0x0004, Reset Value = 0x0000_0000 Name RSVD nCTIIRQ_ISP PMUIRQ_ISP TMU nCTIIRQ[1] PMUIR[1] PARITYFAILSC[1] PARITYFAIL1 RSVD PARRINTR PARRDINTR TMU nCTIIRQ[0] PMUIRQ[0] PARITYFAILSCU[0] PARITYFAIL0 RSVD TZASC1[1] TZASC1[0] TZASC0[1] TZASC0[0] RSVD RSVD RSVD RSVD RSVD Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15:12] [11] [10] [9] [8] [7:4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW – RW RW RW RW RW RW RW – RW RW RW RW – RW RW RW RW Reserved Description Clears the corresponding interrupt enable bit to "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. Write) 0 = Does not change the current setting. 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reserved Clears the corresponding interrupt enable bit to "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. Write) 0 = Does not change the current setting. 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reserved Clears the corresponding interrupt enable bit to "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. Write) 0 = Does not change the current setting. 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reserved Clears the corresponding interrupt enable bit to "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. Write) 0 = Does not change the current setting. 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reset Value 0x0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 0 0x0 0 0 0 0 0x0 0 0 0 0 7-11 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.3 ISTR0  Base Address: 0x1044_0000  Address = Base Address + 0x0008, Reset Value = Undefined Name RSVD nCTIIRQ_ISP PMUIRQ_ISP TMU nCTIIRQ[1] PMUIR[1] PARITYFAILSC[1] PARITYFAIL1 RSVD PARRINTR PARRDINTR TMU nCTIIRQ[0] PMUIRQ[0] PARITYFAILSCU[0] PARITYFAIL0 RSVD TZASC1[1] TZASC1[0] TZASC0[1] TZASC0[0] RSVD RSVD RSVD RSVD RSVD Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15:12] [11] [10] [9] [8] [7:4] [3] [2] [1] [0] Type – R R R R R R R – R R R R R R R – R R R R – R R R R Reserved Description Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Reserved Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Reserved Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Reserved Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Reset Value 0x0 – – – – – – – 0x0 – – – – – – – 0x0 – – – – 0x0 – – – – 7-12 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.4 IMSR0  Base Address: 0x1044_0000  Address = Base Address + 0x000C, Reset Value = Undefined Name RSVD nCTIIRQ_ISP PMUIRQ_ISP TMU nCTIIRQ[1] PMUIR[1] PARITYFAILSC[1] PARITYFAIL1 RSVD PARRINTR PARRDINTR TMU nCTIIRQ[0] PMUIRQ[0] PARITYFAILSCU[0] PARITYFAIL0 RSVD TZASC1[1] TZASC1[0] TZASC0[1] TZASC0[0] RSVD RSVD RSVD RSVD RSVD Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15:12] [11] [10] [9] [8] [7:4] [3] [2] [1] [0] Type – R R R R R R R – R R R R R R R – R R R R – R R R R Reserved Description Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Reserved Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Reserved Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Reserved Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Reset Value 0x0 – – – – – – – 0x0 – – – – – – – 0x0 – – – – 0x0 – – – – 7-13 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.5 IESR1  Base Address: 0x1044_0000  Address = Base Address + 0x0010, Reset Value = 0x0000_0000 Name RSVD SYSMMU_MFC_M1[1] SYSMMU_MFC_M0[1] SYSMMU_TV_M0[1] RSVD SYSMMU_LCD0_M0[1] SYSMMU_GPS[1] SYSMMU_ROTATOR[1] SYSMMU_2D[1] SYSMMU_JPEG[1] SYSMMU_FIMC3[1] SYSMMU_FIMC2[1] SYSMMU_FIMC1[1] SYSMMU_FIMC0[1] SYSMMU_SSS[1] SYSMMU_MDMA[1] RSVD SYSMMU_MFC_M1[0] SYSMMU_MFC_M0[0] SYSMMU_TV_M0[0] RSVD SYSMMU_LCD0_M0[0] SYSMMU_GPS[0] SYSMMU_ROTATOR[0] SYSMMU_2D[0] SYSMMU_JPEG[0] SYSMMU_FIMC3[0] SYSMMU_FIMC2[0] SYSMMU_FIMC1[0] SYSMMU_FIMC0[0] SYSMMU_SSS[0] SYSMMU_MDMA[0] Bit Type Description Reset Value [31] – 0 [30] RW Sets the corresponding interrupt enable bit to "1". If 0 [29] RW you set the interrupt enable bit, interrupt combiner serves the interrupt request. 0 [28] RW Write) 0 = Does not change the current setting. 0 [27] – 1 = Sets the interrupt enable bit to "1". 0 [26] RW Read) The current interrupt enable bit. 0 0 = Masks. [25] RW 1 = Enables. 0 [24] RW 0 [23] RW 0 [22] RW Sets the corresponding interrupt enable bit to "1". If 0 [21] RW you set the interrupt enable bit, interrupt combiner serves the interrupt request. 0 [20] RW Write) 0 = Does not change the current setting. 0 [19] RW 1 = Sets the interrupt enable bit to "1". 0 [18] RW Read) The current interrupt enable bit. 0 = Masks. 0 [17] RW 1 = Enables. 0 [16] RW 0 [15] – 0 [14] RW Sets the corresponding interrupt enable bit to "1". If 0 [13] RW you set the interrupt enable bit, interrupt combiner serves the interrupt request. 0 [12] RW Write) 0 = Does not change the current setting. 0 [11] – 1 = Sets the interrupt enable bit to "1". 0 [10] RW Read) The current interrupt enable bit. 0 = Masks. 0 [9] RW 1 = Enables. 0 [8] RW 0 [7] RW 0 [6] RW Sets the corresponding interrupt enable bit to "1". If 0 [5] RW you set the interrupt enable bit, interrupt combiner serves the interrupt request. 0 [4] RW Write) 0 = Does not change the current setting. 0 [3] RW 1 = Sets the interrupt enable bit to "1". 0 [2] RW Read) The current interrupt enable bit. 0 = Masks. 0 [1] RW 1 = Enables. 0 [0] RW 0 7-14 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.6 IECR1  Base Address: 0x1044_0000  Address = Base Address + 0x0014, Reset Value = 0x0000_0000 Name RSVD SYSMMU_MFC_M1[1] SYSMMU_MFC_M0[1] SYSMMU_TV_M0[1] RSVD SYSMMU_LCD0_M0[1] SYSMMU_GPS[1] SYSMMU_ROTATOR[1] SYSMMU_2D[1] SYSMMU_JPEG[1] SYSMMU_FIMC3[1] SYSMMU_FIMC2[1] SYSMMU_FIMC1[1] SYSMMU_FIMC0[1] SYSMMU_SSS[1] SYSMMU_MDMA[1] RSVD SYSMMU_MFC_M1[0] SYSMMU_MFC_M0[0] SYSMMU_TV_M0[0] RSVD SYSMMU_LCD0_M0[0] SYSMMU_GPS[0] SYSMMU_ROTATOR[0] SYSMMU_2D[0] SYSMMU_JPEG[0] SYSMMU_FIMC3[0] SYSMMU_FIMC2[0] SYSMMU_FIMC1[0] SYSMMU_FIMC0[0] SYSMMU_SSS[0] SYSMMU_MDMA[0] Bit Type Description Reset Value [31] – 0 [30] RW Clears the corresponding interrupt enable bit to "0". 0 [29] RW If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. 0 [28] RW Write) 0 = Does not change the current setting. 0 [27] – 1 = Clears the interrupt enable bit to "0". 0 [26] RW Read) The current interrupt enable bit. 0 0 = Masks. [25] RW 1 = Enables. 0 [24] RW 0 [23] RW 0 [22] RW Clears the corresponding interrupt enable bit to "0". 0 [21] RW If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. 0 [20] RW Write) 0 = Does not change the current setting. 0 [19] RW 1 = Clears the interrupt enable bit to "0". 0 [18] RW Read) The current interrupt enable bit. 0 0 = Masks. [17] RW 1 = Enables. 0 [16] RW 0 [15] – 0 [14] RW Clears the corresponding interrupt enable bit to "0". 0 [13] RW If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. 0 [12] RW Write) 0 = Does not change the current setting. 0 [11] – 1 = Clears the interrupt enable bit to "0". 0 [10] RW Read) The current interrupt enable bit. 0 0 = Masks. [9] RW 1 = Enables. 0 [8] RW 0 [7] RW 0 [6] RW Clears the corresponding interrupt enable bit to "0". 0 If you clear the interrupt enable bit, interrupt [5] RW combiner will mask the interrupt. 0 [4] RW Write) 0 = Does not change the current setting. 0 [3] RW 1 = Clears the interrupt enable bit to "0". 0 [2] RW Read) The current interrupt enable bit. 0 0 = Masks. [1] RW 1 = Enables. 0 [0] RW 0 7-15 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.7 ISTR1  Base Address: 0x1044_0000  Address = Base Address + 0x0018, Reset Value = Undefined Name RSVD SYSMMU_MFC_M1[1] SYSMMU_MFC_M0[1] SYSMMU_TV_M0[1] RSVD SYSMMU_LCD0_M0[1] SYSMMU_GPS[1] SYSMMU_ROTATOR[1] SYSMMU_2D[1] SYSMMU_JPEG[1] SYSMMU_FIMC3[1] SYSMMU_FIMC2[1] SYSMMU_FIMC1[1] SYSMMU_FIMC0[1] SYSMMU_SSS[1] SYSMMU_MDMA[1] RSVD SYSMMU_MFC_M1[0] SYSMMU_MFC_M0[0] SYSMMU_TV_M0[0] RSVD SYSMMU_LCD0_M0[0] SYSMMU_GPS[0] SYSMMU_ROTATOR[0] SYSMMU_2D[0] SYSMMU_JPEG[0] SYSMMU_FIMC3[0] SYSMMU_FIMC2[0] SYSMMU_FIMC1[0] SYSMMU_FIMC0[0] SYSMMU_SSS[0] SYSMMU_MDMA[0] Bit Type Description [31] – [30] R [29] R Interrupt pending status. [28] R The corresponding interrupt enable bit does not affect this pending status. [27] – 0 = The interrupt is not pending. [26] R 1 = The interrupt is pending. [25] R [24] R [23] R [22] R [21] R Interrupt pending status. [20] R The corresponding interrupt enable bit does not affect this pending status. [19] R 0 = The interrupt is not pending. [18] R 1 = The interrupt is pending. [17] R [16] R [15] – [14] R [13] R Interrupt pending status. [12] R The corresponding interrupt enable bit does not affect this pending status. [11] – 0 = The interrupt is not pending. [10] R 1 = The interrupt is pending. [9] R [8] R [7] R [6] R [5] R Interrupt pending status. [4] R The corresponding interrupt enable bit does not affect this pending status. [3] R 0 = The interrupt is not pending. [2] R 1 = The interrupt is pending. [1] R [0] R Reset Value – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 7-16 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.8 IMSR1  Base Address: 0x1044_0000  Address = Base Address + 0x001C, Reset Value = Undefined Name RSVD SYSMMU_MFC_M1[1] SYSMMU_MFC_M0[1] SYSMMU_TV_M0[1] RSVD SYSMMU_LCD0_M0[1] SYSMMU_GPS[1] SYSMMU_ROTATOR[1] SYSMMU_2D[1] SYSMMU_JPEG[1] SYSMMU_FIMC3[1] SYSMMU_FIMC2[1] SYSMMU_FIMC1[1] SYSMMU_FIMC0[1] SYSMMU_SSS[1] SYSMMU_MDMA[1] RSVD SYSMMU_MFC_M1[0] SYSMMU_MFC_M0[0] SYSMMU_TV_M0[0] RSVD SYSMMU_LCD0_M0[0] SYSMMU_GPS[0] SYSMMU_ROTATOR[0] SYSMMU_2D[0] SYSMMU_JPEG[0] SYSMMU_FIMC3[0] SYSMMU_FIMC2[0] SYSMMU_FIMC1[0] SYSMMU_FIMC0[0] SYSMMU_SSS[0] SYSMMU_MDMA[0] Bit Type Description [31] – [30] R [29] R Masked interrupt pending status. [28] R If the corresponding interrupt enable bit is "0", the IMSR bit reads out as "0". [27] – 0 = The interrupt is not pending. [26] R 1 = The interrupt is pending. [25] R [24] R [23] R [22] R [21] R Masked interrupt pending status. [20] R If the corresponding interrupt enable bit is "0", the IMSR bit reads out as "0". [19] R 0 = The interrupt is not pending. [18] R 1 = The interrupt is pending. [17] R [16] R [15] – [14] R [13] R Masked interrupt pending status. If the [12] R corresponding interrupt enable bit is "0", the IMSR bit reads out as "0". [11] – 0 = The interrupt is not pending. [10] R 1 = The interrupt is pending. [9] R [8] R [7] R [6] R [5] R Masked interrupt pending status. If the [4] R corresponding interrupt enable bit is "0", the IMSR bit reads out as "0". [3] R 0 = The interrupt is not pending. [2] R 1 = The interrupt is pending. [1] R [0] R Reset Value – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 7-17 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.9 IESR2  Base Address: 0x1044_0000  Address = Base Address + 0x0020, Reset Value = 0x0000_0000 Name RSVD LCD0[3] LCD0[2] LCD0[1] LCD0[0] DMC1_PPC_PEREV_M DMC1_PPC_PEREV_A DMC0_PPC_PEREV_M DMC0_PPC_PEREV_A ADC L2CACHE RP_TIMER GPIO_AUDIO RSVD PPMU_MFC_M1 PPMU_MFC_M0 PPMU_3D PPMU_TV_M0 PPMU_FILE_D_M0 PPMU_ISP_MX PPMU_LCD0 PPMU_IMAGE_M0 PPMU_CAMIF_M0 PPMU_D_RIGHT_M0 PPMU_D_LEFT_M0 PPMU_ACP0_M0 PPMU_XIU_R_S1 PPMU_XIU_R PPMU_XIU_L Bit [31:28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW RW RW RW – – RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Description Reserved Sets the corresponding interrupt enable bit to "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Set the corresponding interrupt enable bit to "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reserved Sets the corresponding interrupt enable bit to "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 =Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Sets the corresponding interrupt enable bit to "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reset Value 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7-18 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.10 IECR2  Base Address: 0x1044_0000  Address = Base Address + 0x0024, Reset Value = 0x0000_0000 Name RSVD LCD0[3] LCD0[2] LCD0[1] LCD0[0] DMC1_PPC_PEREV_M DMC1_PPC_PEREV_A DMC0_PPC_PEREV_M DMC0_PPC_PEREV_A ADC L2CACHE RP_TIMER GPIO_AUDIO RSVD PPMU_MFC_M1 PPMU_MFC_M0 PPMU_3D PPMU_TV_M0 PPMU_FILE_D_M0 PPMU_ISP_MX PPMU_LCD0 PPMU_IMAGE_M0 PPMU_CAMIF_M0 PPMU_D_RIGHT_M0 PPMU_D_LEFT_M0 PPMU_ACP0_M0 PPMU_XIU_R_S1 PPMU_XIU_R PPMU_XIU_L Bit [31:28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW RW RW RW RW – RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Description Reserved Clears the corresponding interrupt enable bit to "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. Write) 0 = Does not change the current setting. 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Clears the corresponding interrupt enable bit to "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. Write) 0 = Does not change the current setting. 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reserved Clears the corresponding interrupt enable bit to "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. Write) 0 = Does not change the current setting. 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Clears the corresponding interrupt enable bit to "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. Write) 0 = Does not change the current setting. 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reset Value 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7-19 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.11 ISTR2  Base Address: 0x1044_0000  Address = Base Address + 0x0028, Reset Value = Undefined Name RSVD LCD0[3] LCD0[2] LCD0[1] LCD0[0] DMC1_PPC_PEREV_M DMC1_PPC_PEREV_A DMC0_PPC_PEREV_M DMC0_PPC_PEREV_A ADC L2CACHE RP_TIMER GPIO_AUDIO RSVD PPMU_MFC_M1 PPMU_MFC_M0 PPMU_3D PPMU_TV_M0 PPMU_FILE_D_M0 PPMU_ISP_MX PPMU_LCD0 PPMU_IMAGE_M0 PPMU_CAMIF_M0 PPMU_D_RIGHT_M0 PPMU_D_LEFT_M0 PPMU_ACP0_M0 PPMU_XIU_R_S1 PPMU_XIU_R PPMU_XIU_L Bit [31:28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Type – R R R R R R R R R R R R – R R R R R R R R R R R R R R R Description Reserved Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Interrupts pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Reserved Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Reset Value 0x0 – – – – – – – – – – – 0 0 – – – – – – – – – – – – – – – 7-20 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.12 IMSR2  Base Address: 0x1044_0000  Address = Base Address + 0x002C, Reset Value = Undefined Name RSVD LCD0[3] LCD0[2] LCD0[1] LCD0[0] DMC1_PPC_PEREV_M DMC1_PPC_PEREV_A DMC0_PPC_PEREV_M DMC0_PPC_PEREV_A ADC L2CACHE RP_TIMER GPIO_AUDIO RSVD PPMU_MFC_M1 PPMU_MFC_M0 PPMU_3D PPMU_TV_M0 PPMU_FILE_D_M0 PPMU_ISP_MX PPMU_LCD0 PPMU_IMAGE_M0 PPMU_CAMIF_M0 PPMU_D_RIGHT_M0 PPMU_D_LEFT_M0 PPMU_ACP0_M0 PPMU_XIU_R_S1 PPMU_XIU_R PPMU_XIU_L Bit [31:28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Type – R R R R R R R R R R R R – R R R R R R R R R R R R R R R Description Reserved Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads out as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Reserved Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Reset Value 0x0 – – – – – – – – – – – 0 0 – – – – – – – – – – – – – – – 7-21 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.13 IESR3  Base Address: 0x1044_0000  Address = Base Address + 0x0030, Reset Value = 0x0000_0000 Name DECERRINTR SLVERRINTR ERRRDINTR ERRRTINTR ERRWDINTR ERRWTINTR ECNTRINTR SCUEVABORT RSVD CPU_nIRQOUT_1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD CPU_nIRQOUT_0 RSVD RSVD RSVD RSVD RSVD MCT_G3 MCT_G2 MCT_G1 MCT_G0 RSVD MIPI_HSI] UART4 Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15:14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3:2] [1] [0] Type RW RW RW RW RW RW RW RW – RW – – – – – – – RW – – – – – RW RW RW RW – RW RW Description Sets the corresponding interrupt enable bit to "1 If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Sets the corresponding interrupt enable bit to "1 If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Sets the corresponding interrupt enable bit to "1 If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Sets the corresponding interrupt enable bit to "1 If you set the interrupt enable bit, interrupt combiner serves the interrupt request. Write) 0 = Does not change the current setting. 1 = Sets the interrupt enable bit to "1". Read) The current interrupt enable bit. 0 = Masks. 1 = Enables. Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0x0 0 0 7-22 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.14 IECR3  Base Address: 0x1044_0000  Address = Base Address + 0x0034, Reset Value = 0x0000_0000 Name Bit Type Description DECERRINTR SLVERRINTR ERRRDINTR ERRRTINTR ERRWDINTR ERRWTINTR ECNTRINTR SCUEVABORT [31] RW [30] RW Clears the corresponding interrupt enable bit to "0". If [29] RW you clear the interrupt enable bit, interrupt combiner will mask the interrupt. [28] RW Write) 0 = Does not change the current setting. [27] RW 1 = Clears the interrupt enable bit to "0". [26] RW Read) The current interrupt enable bit. 0 = Masks. [25] RW 1 = Enables. [24] RW RSVD [23] CPU_nIRQOUT_1 [22] RSVD [21] RSVD [20] RSVD [19] RSVD [18] RSVD [17] RSVD [16] – RW Clears the corresponding interrupt enable bit to "0". If – you clear the interrupt enable bit, interrupt combiner will mask the interrupt. – Write) 0 = Does not change the current setting. – 1 = Clears the interrupt enable bit to "0". – Read) The current interrupt enable bit. 0 = Masks. – 1 = Enables. – RSVD [15:14] – Clears the corresponding interrupt enable bit to "0". If CPU_nIRQOUT_0 [13] RW you clear the interrupt enable bit, interrupt combiner will RSVD [12] – mask the interrupt. RSVD [11] – Write) 0 = Does not change the current setting. 1 = Clears the interrupt enable bit to "0". RSVD [10] – Read) The current interrupt enable bit. RSVD [9] – 0 = Masks. RSVD [8] – 1 = Enables. MCT_G3 MCT_G2 MCT_G1 MCT_G0 RSVD MIPI_HSI] UART4 LCD1[0] [7] RW [6] RW Clears the corresponding interrupt enable bit to "0". If you clear the interrupt enable bit, interrupt combiner will [5] RW mask the interrupt. [4] RW Write) 0 = Does not change the current setting. [3:2] RW 1 = Clears the interrupt enable bit to "0". [1] RW Read) The current interrupt enable bit. 0 = Masks. [0] RW 1 = Enables. [0] RW Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 0 7-23 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.15 ISTR3  Base Address: 0x1044_0000  Address = Base Address + 0x0038, Reset Value = Undefined Name DECERRINTR SLVERRINTR ERRRDINTR ERRRTINTR ERRWDINTR ERRWTINTR ECNTRINTR SCUEVABORT RSVD CPU_nIRQOUT_1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD CPU_nIRQOUT_0 RSVD RSVD RSVD RSVD RSVD MCT_G3 MCT_G2 MCT_G1 MCT_G0 RSVD MIPI_HSI] UART4 LCD1[0] Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15:14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3:2] [1] [0] [0] Type R R R R R R R R – R – – – – – – – R – – – – – R R R R – R R R Description Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Interrupt pending status. The corresponding interrupt enable bit does not affect this pending status. 0 = The interrupt is not pending. 1 = The interrupt is pending. Reset Value – – – – – – – – 0 – – – – – – – 00 – – – – – – 0x0 – – – – 7-24 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.16 IMSR3  Base Address: 0x1044_0000  Address = Base Address + 0x003C, Reset Value = Undefined Name DECERRINTR SLVERRINTR ERRRDINTR ERRRTINTR ERRWDINTR ERRWTINTR ECNTRINTR SCUEVABORT RSVD CPU_nIRQOUT_1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD CPU_nIRQOUT_0 RSVD RSVD RSVD RSVD RSVD MCT_G3 MCT_G2 MCT_G1 MCT_G0 RSVD MIPI_HSI] UART4 LCD1[0] Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15:14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3:2] [1] [0] [0] Type R R R R R R R R – R – – – – – – – R – – – – – R R R R R R R Description Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Masked interrupt pending status. If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". 0 = The interrupt is not pending. 1 = The interrupt is pending. Reset Value – – – – – – – – 0 – – – – – – – 00 – – – – – – 00 – – – 7-25 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.17 IESR4  Base Address: 0x1044_0000  Address = Base Address + 0x0040, Reset Value = 0x0000_0000 Name Bit Type Description RSVD CPU_nIRQOUT_3 PARITYFAILSCU3 PARITYFAIL3 CPU_nCTIIRQ_3 CPU_PMUIRQ_3 RSVD MCT_L0 [31] – [30] RW Sets the corresponding interrupt enable bit to [29] RW "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. [28] RW Write) 0 = Does not change the current setting. [27] RW 1 = Sets the interrupt enable bit to "1". [26] RW Read) The current interrupt enable bit. 0 = Masks. [25] RW 1 = Enables. [24] RW RSVD CPU_nIRQOUT_2 PARITYFAILSCU2 PARITYFAIL2 CPU_nCTIIRQ_2 CPU_PMUIRQ_2 RSVD MCT_L1 [23] – [22] RW Sets the corresponding interrupt enable bit to [21] RW "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. [20] RW Write) 0 = Does not change the current setting. [19] RW 1 = Sets the interrupt enable bit to "1". [18] RW Read) The current interrupt enable bit. 0 = Masks. [17] RW 1 = Enables. [16] RW MCT_L2 [15] RSVD [14] SYSMMU_ISP_CX[1] [13] SYSMMU_FIMC_FD[1] [12] SYSMMU_FIMC_DRC[1] [11] SYSMMU_FIMC_ISP[1] [10] SYSMMU_FIMC_LITE0[1] [9] SYSMMU_FIMC_LITE0[1] [8] RW – Sets the corresponding interrupt enable bit to RW "1". If you set the interrupt enable bit, interrupt combiner serves the interrupt request. RW Write) 0 = Does not change the current setting. RW 1 = Sets the interrupt enable bit to "1". RW Read) The current interrupt enable bit. 0 = Masks. RW 1 = Enables. RW MCT_L3 [7] RSVD [6] SYSMMU_ISP_CX[0] [5] SYSMMU_FIMC_FD[0] [4] SYSMMU_FIMC_DRC[0] [3] SYSMMU_FIMC_ISP[0] [2] SYSMMU_FIMC_LITE0[0] [1] SYSMMU_FIMC_LITE0[0] [0] RW – Sets the corresponding interrupt enable bit to "1". If you set the interrupt enable bit, interrupt RW combiner serves the interrupt request. RW Write) 0 = Does not change the current setting. RW 1 = Sets the interrupt enable bit to "1". RW Read) The current interrupt enable bit. 0 = Masks. RW 1 = Enables. RW Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7-26 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.18 IECR4  Base Address: 0x1044_0000  Address = Base Address + 0x0044, Reset Value = 0x0000_0000 Name Bit Type Description RSVD [31] – CPU_nIRQOUT_3 PARITYFAILSCU3 PARITYFAIL3 CPU_nCTIIRQ_3 CPU_PMUIRQ_3 RSVD [30] RW Clears the corresponding interrupt enable bit to [29] RW "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. [28] RW Write) 0 = Does not change the current setting. [27] RW 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. [26] RW 0 = Masks. [25] RW 1 = Enables. MCT_L0 [24] RW RSVD [23] – CPU_nIRQOUT_2 PARITYFAILSCU2 PARITYFAIL2 CPU_nCTIIRQ_2 CPU_PMUIRQ_2 RSVD [22] RW Clears the corresponding interrupt enable bit to [21] RW "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. [20] RW Write) 0 = Does not change the current setting. [19] RW 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. [18] RW 0 = Masks. [17] RW 1 = Enables. MCT_L1 [16] RW MCT_L2 [15] RW RSVD [14] SYSMMU_ISP_CX[1] [13] SYSMMU_FIMC_FD[1] [12] SYSMMU_FIMC_DRC[1] [11] SYSMMU_FIMC_ISP[1] [10] SYSMMU_FIMC_LITE0[1] [9] – Clears the corresponding interrupt enable bit to RW "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. RW Write) 0 = Does not change the current setting. RW 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. RW 0 = Masks. RW 1 = Enables. SYSMMU_FIMC_LITE0[1] [8] RW MCT_L3 [7] RW RSVD [6] SYSMMU_ISP_CX[0] [5] SYSMMU_FIMC_FD[0] [4] SYSMMU_FIMC_DRC[0] [3] SYSMMU_FIMC_ISP[0] [2] SYSMMU_FIMC_LITE0[0] [1] – Clears the corresponding interrupt enable bit to RW "0". If you clear the interrupt enable bit, interrupt combiner will mask the interrupt. RW Write) 0 = Does not change the current setting. RW 1 = Clears the interrupt enable bit to "0". Read) The current interrupt enable bit. RW 0 = Masks. RW 1 = Enables. SYSMMU_FIMC_LITE0[0] [0] RW Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7-27 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.19 ISTR4  Base Address: 0x1044_0000  Address = Base Address + 0x0048, Reset Value = Undefined Name Bit Type Description RSVD [31] – CPU_nIRQOUT_3 [30] R PARITYFAILSCU3 PARITYFAIL3 CPU_nCTIIRQ_3 CPU_PMUIRQ_3 [29] R Interrupt pending status. [28] R The corresponding interrupt enable bit does not affect this pending status. [27] R 0 = The interrupt is not pending. [26] R 1 = The interrupt is pending. RSVD [25] R MCT_L0 [24] R RSVD [23] – CPU_nIRQOUT_2 [22] R PARITYFAILSCU2 PARITYFAIL2 CPU_nCTIIRQ_2 CPU_PMUIRQ_2 [21] R Interrupt pending status. [20] R The corresponding interrupt enable bit does not affect this pending status. [19] R 0 = The interrupt is not pending. [18] R 1 = The interrupt is pending. RSVD [17] R MCT_L1 [16] R MCT_L2 [15] R RSVD [14] – SYSMMU_ISP_CX[1] [13] SYSMMU_FIMC_FD[1] [12] SYSMMU_FIMC_DRC[1] [11] SYSMMU_FIMC_ISP[1] [10] R Interrupt pending status. R The corresponding interrupt enable bit does not affect this pending status. R 0 = The interrupt is not pending. R 1 = The interrupt is pending. SYSMMU_FIMC_LITE0[1] [9] R SYSMMU_FIMC_LITE0[1] [8] R MCT_L3 [7] R RSVD [6] – SYSMMU_ISP_CX[0] [5] SYSMMU_FIMC_FD[0] [4] SYSMMU_FIMC_DRC[0] [3] SYSMMU_FIMC_ISP[0] [2] R Interrupt pending status. R The corresponding interrupt enable bit does not affect this pending status. R 0 = The interrupt is not pending. R 1 = The interrupt is pending. SYSMMU_FIMC_LITE0[0] [1] R SYSMMU_FIMC_LITE0[0] [0] R Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7-28 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.20 IMSR4  Base Address: 0x1044_0000  Address = Base Address + 0x004C, Reset Value = Undefined Name Bit Type Description RSVD [31] – CPU_nIRQOUT_3 [30] R PARITYFAILSCU3 PARITYFAIL3 CPU_nCTIIRQ_3 CPU_PMUIRQ_3 [29] R Masked interrupt pending status. [28] R If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". [27] R 0 = The interrupt is not pending. [26] R 1 = The interrupt is pending. RSVD [25] R MCT_L0 [24] R RSVD [23] – CPU_nIRQOUT_2 [22] R PARITYFAILSCU2 PARITYFAIL2 CPU_nCTIIRQ_2 CPU_PMUIRQ_2 [21] R Masked interrupt pending status. [20] R If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". [19] R 0 = The interrupt is not pending. [18] R 1 = The interrupt is pending. RSVD [17] R MCT_L1 [16] R MCT_L2 [15] R RSVD [14] – SYSMMU_ISP_CX[1] [13] SYSMMU_FIMC_FD[1] [12] SYSMMU_FIMC_DRC[1] [11] SYSMMU_FIMC_ISP[1] [10] R Masked interrupt pending status. R If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". R 0 = The interrupt is not pending. R 1 = The interrupt is pending. SYSMMU_FIMC_LITE0[1] [9] R SYSMMU_FIMC_LITE0[1] [8] R MCT_L3 [7] R RSVD [6] – SYSMMU_ISP_CX[0] [5] SYSMMU_FIMC_FD[0] [4] SYSMMU_FIMC_DRC[0] [3] SYSMMU_FIMC_ISP[0] [2] R Masked interrupt pending status. R If the corresponding interrupt enable bit is "0", the IMSR bit reads as "0". R 0 = The interrupt is not pending. R 1 = The interrupt is pending. SYSMMU_FIMC_LITE0[0] [1] R SYSMMU_FIMC_LITE0[0] [0] R Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7-29 Exynos 4412_UM 7 Interrupt Combiner 7.6.2.21 CIPSR0  Base Address: 0x1044_0000  Address = Base Address + 0x0100, Reset Value = Undefined Name INTG31 INTG30 INTG29 INTG28 INTG27 INTG26 INTG25 INTG24 INTG23 INTG22 INTG21 INTG20 INTG19 INTG18 INTG17 INTG16 INTG15 INTG14 INTG13 INTG12 INTG11 INTG10 INTG9 INTG8 INTG7 INTG6 INTG5 INTG4 INTG3 INTG2 INTG1 INTG0 Bit Type Description [31] – [30] – [29] – [28] – [27] – [26] – Reserved [25] – [24] – [23] – [22] – [21] – [20] – [19] R [18] R [17] R [16] R [15] R [14] R [13] R [12] R [11] R Combined interrupt pending status. [10] R 0 = The combined interrupt is not pending. [9] R 1 = The combined interrupt is pending. This means the [8] R corresponding interrupt request to the GIC is asserted. [7] R [6] R [5] R [4] R [3] R [2] R [1] R [0] R Reset Value – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 7-30 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) 8 Direct Memory Access Controller (DMAC) This chapter includes:  Overview of DMA Controller  Register description  Instruction 8.1 Overview The two Direct Memory Access (DMA) tops that Exynos 4412 supports:  Memory-to-Memory (M2M) transfer (DMA_mem)  Peripheral-to-memory transfer and vice-versa (DMA_peri) The DMA_mem consists of one PL330 (DMA) and some logics. DMA_peri consists of two PL330s (DMA0 and DMA1) and dma_map. Figure 8-1 illustrates the two DMA tops. IRQ to interrupt controller DMA_mem DMA (PL330) IRQ to interrupt controller DMA_peri DMA0 (PL330) IRQ to interrupt controller DMA1 (PL330) Conv erter Conv erter Conv erter Conv erter Conv erter Conv erter BREQ0[31:0] CLR0[31:0] BREQ1[31:0] dma_map (only wires and OR-gates) CLR1[31:0] REQ from IPs Figure 8-1 Two DMA Tops ACK to IPs The attributes that the DMA_mem DMA Controllers have:  DMA_mem accesses memory through the AXI_IMGX bus and is located in IMG block.  DMA_mem supports only the secured AXI transaction. 8-1 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) 8.2 Features Table 8-1 describes the features of DMA Controller. Refer to this table for DMA and for writing DMA assembly code. Key Features Supports data size Supports burst size Supports channel Table 8-1 Features of DMA Controller DMA_mem Up to double word (64-bit) Up to 16 burst 8 channels at the same time DMA_peri Up to word (32-bit) Up to 16 burst 16 channels at the same time Each DMA module has 32 interrupt sources. However, you should send only one interrupt to Interrupt Controller. Table 8-2 describes the DMA request mapping. Table 8-2 DMA Request Mapping Table Module Peri DMA1 No. 31 Reserved 30 Reserved 29 MIPI_HSI7 28 MIPI_HSI6 27 SPDIF 26 Siimbus0AUX_TX 25 Siimbus0AUX_RX 24 Siimbus5_RX 23 Siimbus5_RX 22 Siimbus3_TX 21 Siimbus3_RX 20 Slimbus1_TX 19 Slimbus1_RX 18 UART3_TX 17 UART3_RX 16 UART1_TX 15 UART1_RX 14 UART0_TX 13 UART0_RX 12 I2S1_TX 11 I2S1_RX 10 I2S0_TX 9 I2S0_RX 8-2 Exynos 4412_UM Module Peri DMA0 No. 8 I2S0S_TX 7 SPI1_TX 6 SPI1_RX 5 MIPI_HSI3 4 MIPI_HSI2 3 PCM1_TX 2 PCM1_RX 1 PCM0_TX 0 PCM0_RX 31 MIPI_HSI5 30 MIPI_HSI4 29 AC_PCMout 28 AC_PCMin 27 AC_MICin 26 SlimBUS4_TX 25 SlimBUS4_RX 24 SlimBUS2_TX 23 SlimBUS2_RX 22 SlimBUS0_TX 21 SlimBUS0_RX 20 UART4_TX 19 UART4_RX 18 UART2_TX 17 UART2_RX 16 UART0_TX 15 UART0_RX 14 I2S2_TX 13 I2S2_RX 12 I2S0_TX 11 I2S0_RX 10 I2S0S_TX 9 SPI2_TX 8 SPI2_RX 7 SPI0_TX 6 SPI0_RX 5 MIPI_HSI1 4 MIPI_HSI0 8-3 8 Direct Memory Access Controller (DMAC) Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) Module No. 3 PCM2_TX 2 PCM2_RX 1 PCM0_TX 0 PCM0_RX DMA_mem – – Caution: When you enable PDMA0 or PDMA1, verify the CLKGATE status. 8-4 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) 8.3 Register Description Most of the Special Function Registers (SFRs) are read-only. The main role of SFR is to verify the PL330 status. There are many SFRs for PL330. This section describes only the Exynos 4412-specific SFRs. Refer to Chapter 3, "PL330 TRM," for more information. 8.3.1 Register Map Summary  Base Address: 0x1284_0000 (MDMA) Register DS DPC RSVD INTEN ES INTSTATUS INTCLR FSM FSC FTM RSVD FTC0 FTC1 FTC2 FTC3 FTC4 FTC5 FTC6 FTC7 RSVD CS0 CS1 Offset 0x0000 0x0004 0x0008 to 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 to 0x00FC 0x0100 0x0108 Description Specifies the DMA status register. Refer to page 3-11 of "PL330 TRM" for more information. Specifies the DMA program counter register. Refer to page 3-13 of "PL330 TRM" for more information. Reserved Specifies the interrupt enable register. Refer to page 3-13 of "PL330 TRM" for more information. Specifies the event status register. Refer to page 3-14 of "PL330 TRM" for more information. Specifies the interrupt status register. Refer to page 3-16 of "PL330 TRM" for more information. Specifies the interrupt clear register. Refer to page 3-17 of "PL330 TRM" for more information. Specifies the fault status DMA manager register. Refer to page 3-18 of "PL330 TRM" for more information. Specifies the fault status DMA channel register. Refer to page 3-19 of "PL330 TRM" for more information. Specifies the fault type DMA manager register. Refer to page 3-20 of "PL330 TRM" for more information. Reserved Specifies the fault type for DMA channel 0. Specifies the fault type for DMA channel 1. Specifies the fault type for DMA channel 2. Specifies the fault type for DMA channel 3. Specifies the fault type for DMA channel 4. Specifies the fault type for DMA channel 5. Specifies the fault type for DMA channel 6. Specifies the fault type for DMA channel 7. Reserved Specifies the channel status for DMA channel 0. Specifies the channel status for DMA channel 1. Reset Value 0x200 0x0 Undefined 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Undefined 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Undefined 0x0 0x0 8-5 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) Register CS2 CS3 CS4 CS5 CS6 CS7 CPC0 CPC1 CPC2 CPC3 CPC4 CPC5 CPC6 CPC7 RSVD SA_0 SA_1 SA_2 SA_3 SA_4 SA_5 SA_6 SA_7 DA_0 DA_1 DA_2 DA_3 DA_4 DA_5 DA_6 DA_7 CC_0 CC_1 CC_2 CC_3 CC_4 Offset 0x0110 0x0118 0x0120 0x0128 0x0130 0x0138 0x0104 0x010C 0x0114 0x011C 0x0124 0x012C 0x0134 0x013C 0x0140 to 0x03FC 0x0400 0x0420 0x0440 0x0460 0x0480 0x04A0 0x04C0 0x04E0 0x0404 0x0424 0x0444 0x0464 0x0484 0x04A4 0x04C4 0x04E4 0x0408 0x0428 0x0448 0x0468 0x0488 Description Specifies the channel status for DMA channel 2. Specifies the channel status for DMA channel 3. Specifies the channel status for DMA channel 4. Specifies the channel status for DMA channel 5. Specifies the channel status for DMA channel 6. Specifies the channel status for DMA channel 7. Specifies the channel PC for DMA channel 0. Specifies the channel PC for DMA channel 1. Specifies the channel PC for DMA channel 2. Specifies the channel PC for DMA channel 3. Specifies the channel PC for DMA channel 4. Specifies the channel PC for DMA channel 5. Specifies the channel PC for DMA channel 6. Specifies the channel PC for DMA channel 7. Reserved Specifies the source address for DMA channel 0. Specifies the source address for DMA channel 1. Specifies the source address for DMA channel 2. Specifies the source address for DMA channel 3. Specifies the source address for DMA channel 4. Specifies the source address for DMA channel 5. Specifies the source address for DMA channel 6. Specifies the source address for DMA channel 7. Specifies the destination address for DMA channel 0. Specifies the destination address for DMA channel 1. Specifies the destination address for DMA channel 2. Specifies the destination address for DMA channel 3. Specifies the destination address for DMA channel 4. Specifies the destination address for DMA channel 5. Specifies the destination address for DMA channel 6. Specifies the destination address for DMA channel 7. Specifies the channel control for DMA channel 0. Specifies the channel control for DMA channel 1. Specifies the channel control for DMA channel 2. Specifies the channel control for DMA channel 3. Specifies the channel control for DMA channel 4. Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Undefined 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x00800200 0x00800200 0x00800200 0x00800200 0x00800200 8-6 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) Register CC_5 CC_6 CC_7 LC0_0 LC0_1 LC0_2 LC0_3 LC0_4 LC0_5 LC0_6 LC0_7 LC1_0 LC1_1 LC1_2 LC1_3 LC1_4 LC1_5 LC1_6 LC1_7 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD DBGSTATUS DBGCMD Offset 0x04A8 0x04C8 0x04E8 0x040C 0x042C 0x044C 0x046C 0x048C 0x04AC 0x04CC 0x04EC 0x0410 0x0430 0x0450 0x0470 0x0490 0x04B0 0x04D0 0x04F0 0x0414 to 0x041C 0x0434 to 0x043C 0x0454 to 0x045C 0x0474 to 0x047C 0x0494 to 0x049C 0x04B4 to 0x04BC 0x04D4 to 0x04DC 0x04F4 to 0x0CFC 0x0D00 0x0D04 Description Specifies the channel control for DMA channel 5. Specifies the channel control for DMA channel 6. Specifies the channel control for DMA channel 7. Specifies the loop counter 0 for DMA channel 0. Specifies the loop counter 0 for DMA channel 1. Specifies the loop counter 0 for DMA channel 2. Specifies the loop counter 0 for DMA channel 3. Specifies the loop counter 0 for DMA channel 4. Specifies the loop counter 0 for DMA channel 5. Specifies the loop counter 0 for DMA channel 6. Specifies the loop counter 0 for DMA channel 7. Specifies the loop counter 1 for DMA channel 0. Specifies the loop counter 1 for DMA channel 1. Specifies the loop counter 1 for DMA channel 2. Specifies the loop counter 1 for DMA channel 3. Specifies the loop counter 1 for DMA channel 4. Specifies the loop counter 1 for DMA channel 5. Specifies the loop counter 1 for DMA channel 6. Specifies the loop counter 1 for DMA channel 7. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Specifies the debug status register. Refer to page 3-37 of "PL330 TRM" for more information. Specifies the debug command register. Refer to page 3-37 of "PL330 TRM" for more information. Reset Value 0x00800200 0x00800200 0x00800200 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0x0 Undefined 8-7 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) Register DBGINST0 DBGINST1 CR0 CR1 CR2 CR3 CR4 CRDn periph_id_n pcell_id_n Offset 0x0D08 0x0D0C 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E14 0x0FE0 to 0x0FEC 0x0FF0 to 0x0FFC Description Specifies the debug instruction-0 register. Refer to page 338 of "PL330 TRM" for more information. Specifies the debug instruction-1 register. Refer to page 339 of "PL330 TRM" for more information. Specifies the configuration register 0. Refer to page 3-40 of "PL330 TRM" for more information. Specifies the configuration register 1. Refer to page 3-42 of "PL330 TRM" for more information. Specifies the configuration register 2. Refer to page 3-43 of "PL330 TRM" for more information. Specifies the configuration register 3. Refer to page 3-44 of "PL330 TRM" for more information. Specifies the configuration register 4. Refer to page 3-45 of "PL330 TRM" for more information. Specifies the configuration register Dn. Refer to page 3-46 of "PL330 TRM" for more information. Specifies the peripheral identification registers 0-3. Refer to page 3-48 of "PL330 TRM" for more information. Specifies the primecell identification registers 0-3. Refer to page 3-50 of "PL330 TRM" for more information. Reset Value Undefined Undefined 0x003E_0075 0x0000_0075 0x0 0x0 0x0000_0001 0x03F7_3733 Configuration- dependent Configuration- dependent 8-8 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC)  Base Address: 0x1268_0000, 0x1269_0000 (PDMA0/PDMA1) Register DS DPC RSVD INTEN ES INTSTATUS INTCLR FSM FSC FTM RSVD FTC0 FTC1 FTC2 FTC3 FTC4 FTC5 FTC6 FTC7 RSVD CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 Offset 0x0000 0x0004 0x0008 to 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 to 0x00FC 0x0100 0x0108 0x0110 0x0118 0x0120 0x0128 0x0130 0x0138 Description Specifies the DMA status register. Refer to page 3-11 of "PL330 TRM" for more information. Specifies the DMA program counter register. Refer to page 3-13 of "PL330 TRM" for more information. Reserved Specifies the interrupt enable register. Refer to page 3-13 of "PL330 TRM" for more information. Specifies the event status register. Refer to page 3-14 of "PL330 TRM" for more information. Specifies the interrupt status register. Refer to page 3-16 of "PL330 TRM" for more information. Specifies the interrupt clear register. Refer to page 3-17 of "PL330 TRM" for more information. Specifies the fault status DMA manager register. Refer to page 3-18 of "PL330 TRM" for more information. Specifies the fault status DMA channel register. Refer to page 3-19 of "PL330 TRM" for more information. Specifies the fault type DMA manager register. Refer to page 3-20 of "PL330 TRM" for more information. Reserved Specifies the fault type for DMA channel 0. Specifies the fault type for DMA channel 1. Specifies the fault type for DMA channel 2. Specifies the fault type for DMA channel 3. Specifies the fault type for DMA channel 4. Specifies the fault type for DMA channel 5. Specifies the fault type for DMA channel 6. Specifies the fault type for DMA channel 7. Reserved Specifies the channel status for DMA channel 0. Specifies the channel status for DMA channel 1. Specifies the channel status for DMA channel 2. Specifies the channel status for DMA channel 3. Specifies the channel status for DMA channel 4. Specifies the channel status for DMA channel 5. Specifies the channel status for DMA channel 6. Specifies the channel status for DMA channel 7. Reset Value 0x00000200 0x0 Undefined 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Undefined 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Undefined 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 8-9 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) Register CPC0 CPC1 CPC2 CPC3 CPC4 CPC5 CPC6 CPC7 RSVD SA_0 SA_1 SA_2 SA_3 SA_4 SA_5 SA_6 SA_7 DA_0 DA_1 DA_2 DA_3 DA_4 DA_5 DA_6 DA_7 CC_0 CC_1 CC_2 CC_3 CC_4 CC_5 CC_6 CC_7 LC0_0 LC0_1 LC0_2 Offset 0x0104 0x010C 0x0114 0x011C 0x0124 0x012C 0x0134 0x013C 0x0140 to 0x03FC 0x0400 0x0420 0x0440 0x0460 0x0480 0x04A0 0x04C0 0x04E0 0x0404 0x0424 0x0444 0x0464 0x0484 0x04A4 0x04C4 0x04E4 0x0408 0x0428 0x0448 0x0468 0x0488 0x04A8 0x04C8 0x04E8 0x040C 0x042C 0x044C Description Specifies the channel PC for DMA channel 0. Specifies the channel PC for DMA channel 1. Specifies the channel PC for DMA channel 2. Specifies the channel PC for DMA channel 3. Specifies the channel PC for DMA channel 4. Specifies the channel PC for DMA channel 5. Specifies the channel PC for DMA channel 6. Specifies the channel PC for DMA channel 7. Reserved Specifies the source address for DMA channel 0. Specifies the source address for DMA channel 1. Specifies the source address for DMA channel 2. Specifies the source address for DMA channel 3. Specifies the source address for DMA channel 4. Specifies the source address for DMA channel 5. Specifies the source address for DMA channel 6. Specifies the source address for DMA channel 7. Specifies the destination address for DMA channel 0. Specifies the destination address for DMA channel 1. Specifies the destination address for DMA channel 2. Specifies the destination address for DMA channel 3. Specifies the destination address for DMA channel 4. Specifies the destination address for DMA channel 5. Specifies the destination address for DMA channel 6. Specifies the destination address for DMA channel 7. Specifies the channel control for DMA channel 0. Specifies the channel control for DMA channel 1. Specifies the channel control for DMA channel 2. Specifies the channel control for DMA channel 3. Specifies the channel control for DMA channel 4. Specifies the channel control for DMA channel 5. Specifies the channel control for DMA channel 6. Specifies the channel control for DMA channel 7. Specifies the loop counter 0 for DMA channel 0. Specifies the loop counter 0 for DMA channel 1. Specifies the loop counter 0 for DMA channel 2. Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Undefined 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 8-10 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) Register LC0_3 LC0_4 LC0_5 LC0_6 LC0_7 LC1_0 LC1_1 LC1_2 LC1_3 LC1_4 LC1_5 LC1_6 LC1_7 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD DBGSTATUS DBGCMD DBGINST0 DBGINST1 CR0 CR1 Offset 0x046C 0x048C 0x04AC 0x04CC 0x04EC 0x0410 0x0430 0x0450 0x0470 0x0490 0x04B0 0x04D0 0x04F0 0x0414 to 0x041C 0x0434 to 0x043C 0x0454 to 0x045C 0x0474 to 0x047C 0x0494 to 0x049C 0x04B4 to 0x04BC 0x04D4 to 0x04DC 0x04F4 to 0x0CFC 0x0D00 0x0D04 0x0D08 0x0D0C 0x0E00 0x0E04 Description Specifies the loop counter 0 for DMA channel 3. Specifies the loop counter 0 for DMA channel 4. Specifies the loop counter 0 for DMA channel 5. Specifies the loop counter 0 for DMA channel 6. Specifies the loop counter 0 for DMA channel 7. Specifies the loop counter 1 for DMA channel 0. Specifies the loop counter 1 for DMA channel 1. Specifies the loop counter 1 for DMA channel 2. Specifies the loop counter 1 for DMA channel 3. Specifies the loop counter 1 for DMA channel 4. Specifies the loop counter 1 for DMA channel 5. Specifies the loop counter 1 for DMA channel 6. Specifies the loop counter 1 for DMA channel 7. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Specifies the debug status register on page 3-37 of "TRM". Specifies the debug command register. Refer to page 3-37 of "PL330 TRM" for more information. Specifies the debug instruction-0 register. Refer to page 338 of "PL330 TRM" for more information. Specifies the debug instruction-1 register. Refer to page 339 of "pl330 TRM" for more information. Specifies the configuration register 0. Refer to page 3-40 of "PL330 TRM" for more information. Specifies the configuration register 1. Refer to page 3-42 of "PL330 TRM" for more information. Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0x0 Undefined Undefined Undefined 0x003F_F075 0x0000_0074 8-11 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) Register CR2 CR3 CR4 CRDn periph_id_n pcell_id_n Offset 0x0E08 0x0E0C 0x0E10 0x0E14 0x0FE0 to 0x0FEC 0x0FF0 to 0x0FFC Description Specifies the configuration register 2. Refer to page 3-43 of "PL330 TRM" for more information. Specifies the configuration register 3. Refer to page 3-44 of "PL330 TRM" for more information. Specifies the configuration register 4. Refer to page 3-45 of "PL330 TRM" for more information. Specifies the configuration register Dn. Refer to page 3-46 of "PL330 TRM" for more information. Specifies the peripheral identification registers 0-3 Refer to page 3-48 of "PL330 TRM" for more information. Specifies the primecell identification registers 0-3. Refer to page 3-50 of "PL330 TRM" for more information. Reset Value 0x0000_0000 0x0 0xFFFF_FFFF 0x01F7_3732 Configuration- dependent Configuration- dependent NOTE: The SFR description shows only the restricted and fixed part of some SFR. PL330 TRM shows detailed information of other parts and other SFRs. 8-12 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) 8.3.1.1 CC CC includes:  Base Address: 0x1284_0000 (MDMA)  Base Address: 0x1268_0000, 0x1269_0000 (PDMA0/PDMA1)  Address = Base Address + 0x0408, Reset Value = 0x0080_0200 (CC_0)  Address = Base Address + 0x0428, Reset Value = 0x0080_0200 (CC_1)  Address = Base Address + 0x0448, Reset Value = 0x0080_0200 (CC_2)  Address = Base Address + 0x0468, Reset Value = 0x0080_0200 (CC_3)  Address = Base Address + 0x0488, Reset Value = 0x0080_0200 (CC_4)  Address = Base Address + 0x04A8, Reset Value = 0x0080_0200 (CC_5)  Address = Base Address + 0x04C8, Reset Value = 0x0080_0200 (CC_6)  Address = Base Address + 0x04E8, Reset Value = 0x0080_0200 (CC_7) 8-13 Exynos 4412_UM 8 Direct Memory Access Controller (DMAC) 8.4 Instruction Please refer to the PL330 TRM, "AMBA DMA Controller DMA-330 technical reference manua revision r1p0" from ARM® . 8.4.1.1 Security Scheme DMA_mem runs in both secure and non-secure modes, while DMA_peri runs in non-secure mode only. 8.4.1.2 Summary 1. You can configure the DMAC with up to eight DMA channels. Each channel supports single concurrent thread of DMA operation. Additionally, there is a single DMA manager thread to initialize the DMA channel thread. 2. Channel thread  Each channel thread can operate the DMA. Accordingly, write an assembly code. If you require a number of independent DMA channels, write a number of assembly codes for each channel.  Assemble and link the codes into one file and load this file into the memory. 8-14 Exynos 4412_UM 9 SROM Controller 9 SROM Controller 9.1 Overview Exynos 4412 SROM Controller (SROMC) supports:  External 8/16-bit NOR Flash/PROM/SRAM memory.  4-bank memory up to maximum 128 Kbyte per bank. 9.2 Features The features of SROMC are:  Supports SRAM, various ROMs, and NOR flash memory  Supports only 8 or 16-bit data bus  Address space: Up to 128 KB per bank  Supports 4-bank.  Fixed memory bank start address  External wait to extend the bus cycle  Supports byte and half-word access for external memory 9.3 Block Diagram Figure 9-1 illustrates the block diagram of SROMC introduction. AHB I /F for SROM SFR SROM DECODER AHB I /F for SROM MEM SFR CONTROL & STATE MACHINE SROM I /F SIGNAL GENERATON SROM MEM I /F DATA PATH Figure 9-1 Block Diagram of SROMC Introduction 9-1 Exynos 4412_UM 9.4 Functional Description SROMC supports SROM interface for Bank 0 to Bank 3. This section includes:  nWAIT Pin Operation  Programmable Access Cycle 9 SROM Controller 9.4.1 nWAIT Pin Operation When it enables nWAIT signal corresponding to each memory bank, the external nWAIT pin should prolong the duration of nOE while the memory bank is active. It verifies the nWAIT from tacc-1 and deasserts the nOE at the next clock after sampling nWAIT is high. The nWE signal has the similar relation with nOE signal. Figure 9-2 illustrates the SROMC nWAIT timing diagram. HCLK tRC ADDR nGCS nOE nWAIT DATA(R) Tacs Tcos Tacc=4 Delayed Sampling nWAIT Figure 9-2 SROMC nWAIT Timing Diagram 9-2 Exynos 4412_UM 9 SROM Controller 9.4.2 Programmable Access Cycle Figure 9-3 illustrates the SROMC read timing diagram. HCLK ADDR nGCS nOE DATA(R) Tacs ADDRESS 0 Tcos ADDRESS 1 Tcoh Tacc DATA 0 Tacp DATA 1 Tcah Tacs = 2-cycle Tcos = 2-cycle Tacc = 3-cycle Tacp = 2-cycle Tcoh = 2-cycle Tcah = 2-cycle Figure 9-3 SROMC Read Timing Diagram Figure 9-4 illustrates the SROMC write timing diagram. HCLK ADDR nGCS nWE DATA(W) Tacs ADDRESS Tcos DATA Tacc Tcoh Tcah Tacs= 2-cycle Tcos= 2-cycle Tacc= 3-cycle Tacp = don‟t care Tcoh = 2-cycle Tcah = 2-cycle Figure 9-4 SROMC Write Timing Diagram 9-3 Exynos 4412_UM 9 SROM Controller 9.5 I/O Description This section describes the I/O description of SROMC. Signal nGCS[3:0] ADDR[15:0] nOE nWE nWBE/nBE[1:0] DATA[15:0] nWAIT I/O Output Output Output Output Output In/Out Input Description Bank selection signal SROM address bus SROM output enable SROM write enable SROM byte write enable/byte enable SROM data bus SROM wait input Pad Xm0CSn_x Xm0ADDR_x Xm0OEn Xm0WEn Xm0BEn_x Xm0DATA_x Xm0WAITn Type muxed muxed muxed muxed muxed muxed muxed 9-4 Exynos 4412_UM 9.6 Register Description 9.6.1 Register Map Summary  Base Address: 0x1257_0000 Register SROM_BW SROM_BC0 SROM_BC1 SROM_BC2 SROM_BC3 Offset 0x0000 0x0004 0x0008 0x000C 0x0010 Description Specifies the SROM bus width and wait control Specifies the SROM bank 0 control register Specifies the SROM bank 1 control register Specifies the SROM bank 2 control register Specifies the SROM bank 3 control register 9 SROM Controller Reset Value 0x0000_0009 0x000F_0000 0x000F_0000 0x000F_0000 0x000F_0000 9-5 Exynos 4412_UM 9 SROM Controller 9.6.1.1 SROM_BW  Base Address: 0x1257_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_0009 Name RSVD Bit [31:16] ByteEnable3 [15] WaitEnable3 [14] AddrMode3 [13] DataWidth3 [12] ByteEnable2 [11] WaitEnable2 [10] AddrMode2 [9] DataWidth2 [8] ByteEnable1 [7] WaitEnable1 [6] Type – RW RW RW RW RW RW RW RW RW RW Description Reserved nWBE/nBE (for UB/LB) control for memory bank 3 0 = Does not use UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Uses UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]) Wait enable control for memory bank 3 0 = Disables WAIT 1 = Enables WAIT Select SROM ADDR base for memory bank 3 0 = SROM_ADDR is half-word base address. (SROM_ADDR[22:0]  HADDR[23:1]) 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0]  HADDR[22:0]) NOTE: When DataWidth3 is "0", SROM_ADDR is byte base address. (It ignores this bit.) Data bus width control for memory bank 3 0 = 8-bit 1 = 16-bit nWBE/nBE (for UB/LB) control for memory bank 2 0 = Does not use UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Uses UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]) Wait enable control for memory bank 2 0 = Disables WAIT 1 = Enables WAIT Select SROM ADDR Base for memory bank 2 0 = SROM_ADDR is half-word base address. (SROM_ADDR[22:0]  HADDR[23:1]) 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0]  HADDR[22:0]) NOTE: When DataWidth2 is "0", SROM_ADDR is byte base address. (It ignores this bit.) Data bus width control for memory bank 2 0 = 8-bit 1 = 16-bit nWBE/nBE (for UB/LB) control for memory bank 1 0 = Does not use UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Uses UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]) Wait enable control for memory bank 1 Reset Value 0 0 0 0 0 0 0 0 0 0 0 9-6 Exynos 4412_UM 9 SROM Controller Name Bit AddrMode1 [5] DataWidth1 [4] ByteEnable0 [3] WaitEnable0 [2] AddrMode0 [1] DataWidth0 [0] Type RW RW RW RW RW RW Description 0 = Disables WAIT 1 = Enables WAIT Select SROM ADDR base for memory bank 1 0 = SROM_ADDR is half-word base address. (SROM_ADDR[22:0]  HADDR[23:1]) 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0]  HADDR[22:0]) NOTE: When DataWidth1 is "0", SROM_ADDR is byte base address. (It ignores this bit.) Data bus width control for memory bank 1 0 = 8-bit 1 = 16-bit nWBE/nBE (for UB/LB) control for memory bank 0 0 = Does not use UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Uses UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]) Wait enable control for memory bank 0 0 = Disables WAIT 1 = Enables WAIT Select SROM ADDR base for memory bank 0 0 = SROM_ADDR is half-word base address. (SROM_ADDR[22:0]  HADDR[23:1]) 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0]  HADDR[22:0]) NOTE: When DataWidth0 is "0", SROM_ADDR is byte base address. (It ignores this bit.) Data bus width control for memory bank 0 0 = 8-bit 1 = 16-bit Reset Value 0 0 1 0 0 1 9-7 Exynos 4412_UM 9.6.1.2 SROM_BCn (n = 0 to 3)  Base Address: 0x1257_0000  Address = Base Address + 0x0004, Reset Value = 0x000F_0000 (SROM_BC0)  Address = Base Address + 0x0008, Reset Value = 0x000F_0000 (SROM_BC1)  Address = Base Address + 0x000C, Reset Value = 0x000F_0000 (SROM_BC2)  Address = Base Address + 0x0010, Reset Value = 0x000F_0000 (SROM_BC3) Name Tacs Tcos RSVD Tacc Tcoh Bit [31:28] [27:24] [23:21] [20:16] [15:12] Type RW RW – RW RW Description Address set-up before nGCS 0000 = 0 Clock 0001 = 1 Clocks 0010 = 2 Clocks 0011 = 3 Clocks …………. 1100 = 12 Clocks 1101 = 13 Clocks 1110 = 14 Clocks 1111 = 15 Clocks NOTE: More 1-2 cycles according to bus i/f status Chip selection set-up before nOE 0000 = 0 Clock 0001 = 1 Clocks 0010 = 2 Clocks 0011 = 3 Clocks …………. 1100 = 12 Clocks 1101 = 13 Clocks 1110 = 14 Clocks 1111 = 15 Clocks Reserved Access cycle 00000 = 1 Clock 00001 = 2 Clocks 00001 = 3 Clocks 00010 = 4 Clocks …………. 11100 = 29 Clocks 11101 = 30 Clocks 11110 = 31 Clocks 11111 = 32 Clocks Chip selection hold on nOE 0000 = 0 Clock 0001 = 1 Clocks 0010 = 2 Clocks 0011 = 3 Clocks …………. 1100 = 12 Clocks 1101 = 13 Clocks 9-8 9 SROM Controller Reset Value 0000 0000 000 01111 0000 Exynos 4412_UM Name Tcah Tacp RSVD PMC Bit [11:8] [7:4] [3:2] [1:0] Type RW RW – RW Description 1110 = 14 Clocks 1111 = 15 Clocks Address holding time after nGCSn 0000 = 0 Clock 0001 = 1 Clocks 0010 = 2 Clocks 0011 = 3 Clocks …………. 1100 = 12 Clocks 1101 = 13 Clocks 1110 = 14 Clocks 1111 = 15 Clocks NOTE: More 1-2 cycles according to bus i/f status Page mode access cycle at Page mode 0000 = 0 Clock 0001 = 1 Clocks 0010 = 2 Clocks 0011 = 3 Clocks …………. 1100 = 12 Clocks 1101 = 13 Clocks 1110 = 14 Clocks 1111 = 15 Clocks Reserved Page mode configuration 00 = Normal (1 Data) 01 = 4 Data 10 = Reserved 11 = Reserved 9 SROM Controller Reset Value 0000 0000 – 00 9-9 Exynos 4412_UM 10 NAND Flash Controller 10 NAND Flash Controller 10.1 Overview Due to the recent increase in the prices of NOR flash memory and the moderately priced DRAM, and NAND flash, customers prefer to execute boot code on NAND flash and execute the main code on DRAM. The boot code in Exynos 4412 can be executed on external NAND flash. It copies NAND flash data to DRAM. To validate the NAND flash data, Exynos 4412 includes hardware Error Correction Code (ECC). After the NAND flash content is copied to DRAM, main program will be executed on DRAM. 10.2 Features The features of NAND flash controller are:  Auto boot: The boot code is transferred to internal SRAM during reset. After the transfer, the boot code will be executed on the SRAM.  NAND flash memory interface: Supports 512 Bytes, 2 KB, 4 KB, and 8 KB pages.  Software mode: You can directly access NAND flash memory, for example, this feature can be used in read/erase/program NAND flash memory.  Interface: Supports 8-bit NAND flash memory interface bus.  Generates, detects, and indicates hardware ECC (software correction).  Supports both Single Level Cell (SLC) and Multi Level Cell (MLC) NAND flash memories.  ECC: Supports 1-/4-/8-/12-/16-bit ECC.  SFR interface: Supports byte/half word/word access to Data and ECC data registers, and Word access to other registers. 10-1 Exynos 4412_UM 10.3 Functional Description 10.3.1 Block Diagram Figure 10-1 illustrates the NAND Flash Controller block diagram. SYSTEMBUS AHB Slave /IF SFR ECC Gen. Control& State Machine 10 NAND Flash Controller NAND FLASH Interface nFCE CLE ALE nRE nWE R/nB I/O0 - I/O7 Figure 10-1 NAND Flash Controller Block Diagram 10-2 Exynos 4412_UM 10 NAND Flash Controller 10.3.2 NAND Flash Memory Timing Figure 10-2 illustrates the CLE and ALE timing (TACLS = 1, TWRPH0 = 0, TWRPH1 = 0). HCLK CLE/ALE nWE DATA TACLS TWRPH 0 TWRPH 1 COMMAND/ ADDRESS Figure 10-2 CLE and ALE Timing (TACLS = 1, TWRPH0 = 0, TWRPH1 = 0) Figure 10-3 illustrates the nWE and nRE timing (TWRPH0 = 0, TWRPH1 = 0). HCLK TWRPH0 TWRPH1 nWE/nRE DATA DATA Figure 10-3 nWE and nRE Timing (TWRPH0 = 0, TWRPH1 = 0) 10-3 Exynos 4412_UM 10 NAND Flash Controller 10.4 Software Mode Exynos 4412 supports only software mode access. Use this mode to access NAND flash memory. The NAND flash controller supports direct access to interface with the NAND flash memory.  Writing to the command register (NFCMMD) specifies the NAND flash memory command cycle  Writing to the address register (NFADDR) specifies the NAND flash memory address cycle  Writing to the data register (NFDATA) specifies write data to the NAND flash memory (Write cycle)  Reading from the data register (NFDATA) specifies read data from the NAND flash memory (Read cycle)  Reading main ECC registers (NFMECCD0/NFMECCD1) and Spare ECC registers (NFSECCD) specifies read data from the NAND flash memory NOTE: In the software mode, use polling or interrupt to verify the RnB status input pin. 10.4.1 Data Register Configuration 10.4.1.1 8-bit NAND Flash Memory Interface 1. Word Access Register NFDATA Endian Little Bit[31:24] 4th I/O[7:0] Bit[23:16] 3rd I/O[7:0] Bit[15:8] 2nd I/O[7:0] Bit[7:0] 1st I/O[7:0] 2. Half-word Access Register NFDATA Endian Little Bit[31:24] Invalid value Bit[23:16] Invalid value Bit[15:8] 2nd I/O[7:0] Bit[7:0] 1st I/O[7:0] 3. Byte Access Register NFDATA Endian Little Bit[31:24] Invalid value Bit[23:16] Invalid value Bit[15:8] Invalid value Bit[7:0] 1st I/O[7:0] 10-4 Exynos 4412_UM 10 NAND Flash Controller 10.4.2 1/4/8/12/16-bit ECC NAND flash controller supports 1-/4-/8-/12-/16-bit ECC. For 1-bit ECC, NAND flash controller includes ECC modules for main and spare (meta) data. Main data ECC module generates ECC parity code for 2048 bytes (maximum) data/message length, whereas spare (meta) data ECC module generates ECC parity code for 32 bytes (maximum). For 4-bit ECC, NAND flash controller includes an ECC module. It generates 512 or 24 bytes of ECC parity code. Set MsgLength (NFCONF[25]) to select 512 or 24 bytes message length. For 8-/12-/16-bit ECC, NAND flash controller includes ECC modules for each ECC. You can select data/message length for main and spare (meta) data length. Usually, the length of main data is 512 bytes and the length of spare (meta) data depends on user application. Since these ECC modules support variable length of main and spare (meta) data, you should set the ECC parity conversion codes to handle free page. Refer to 10.4.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC for more information on ECC parity conversion codes. Free page specifies an erased page. The value of erased page is "0xff". Therefore, set the ECC parity conversion codes to generate "0xff" ECC parity codes for all „0xff‟ data. This setting allows ECC module to detect errors on a free page. ECC parity codes are:  28-bit ECC Parity Code = 22-bit Line parity + 6-bit Column Parity  10-bit ECC Parity Code = 4-bit Line parity + 6-bit Column Parity Each 1-/4-/8-/12-/16-bit ECC module guarantees up to 1-/4-/8-/12-/16-bit errors, respectively. If the errors cross the number of guaranteed errors, it cannot guarantee the result. 10.4.3 2048 Byte 1-bit ECC Parity Code Assignment Table and 10.4.4 32 Byte 1-bit ECC Parity Code Assignment Table describes 1-bit ECC parity code assignment. 10-5 Exynos 4412_UM 10 NAND Flash Controller 10.4.3 2048 Byte 1-bit ECC Parity Code Assignment Table MECCn_0 MECCn_1 MECCn_2 MECCn_3 DATA7 – P64 – P1024 – P4 1 DATA6 – P64' – P1024' – P4‟ 1 DATA5 – P32 – P512 – P2 1 DATA4 – P32' – P512' – P2' 1 DATA3 – P16 – P256 – P1 – P8192 DATA2 – P16‟ – P256' – P1' – P8192‟ DATA1 – P8 – P128 – P2048 – P4096 DATA0 – P8' – P128' – P2048' – P4096' 10.4.4 32 Byte 1-bit ECC Parity Code Assignment Table SECCn_0 SECCn_1 DATA7 – P2 – P128 DATA6 – P2' – P128' DATA5 – P1 – P64 DATA4 – P1' – P64' DATA3 – P16 – P32 DATA2 – P16' – P32' DATA1 – P8 – P4 DATA0 – P8' – P4' 10.4.5 1-bit ECC Module Features The ECC Lock (MainECCLock and SpareECCLock) bit of the control register generates the 1-bit ECC. If ECCLock is low, the hardware ECC modules generate the ECC codes. 1-bit ECC Register Configuration The NAND Flash Memory interface table describes the configuration of 1-bit ECC value read from spare area of external NAND flash memory. The format of ECC read from memory is important to compare the ECC parity code that the hardware modules generate. NOTE: 4-bit/8-bit/12-bit/16-bit ECC decoding scheme is different compared to 1-bit ECC. NAND Flash Memory Interface Register NFMECCD0 NFMECCD1 NFSECCD Bit[31:24] Not used Not used Not used Bit[23:16] 2nd ECC 4th ECC 2nd ECC Bit[15:8] Not used Not used Not used Bit[7:0] 1st ECC 3rd ECC 1st ECC 10-6 Exynos 4412_UM 10 NAND Flash Controller 10.4.6 1-bit ECC Programming Guide 1. To use SLC ECC in software mode, reset the ECCType to "0" (enable SLC ECC). ECC module generates ECC parity code for all Read/Write data when MainECCLock (NFCON[7]) and SpareECCLock (NFCON[6]) are unlocked ("0"). You should reset ECC value. To reset ECC value, write the InitMECC (NFCONT[5]) and InitSECC (NFCON[4]) bit as "1" and clear the MainECCLock (NFCONT[7]) bit to "0" (Unlock) before Reading or Writing data. MainECCLock (NFCONT[7]) and SpareECCLock (NFCONT[6]) bits control whether it generates ECC parity code or not. 2. The ECC module generates ECC parity code on register NFMECC0/1 whenever it Reads or Writes data. 3. After you complete Reading or Writing one page (excluding spare area data), set the MainECCLock bit to "1" (Lock). It locks ECC parity code and the value of the ECC status register does not change. 4. To generate spare area ECC parity code, clear SpareECCLock (NFCONT[6]) bit as "0" (Unlock). 5. The spare area ECC module generates ECC parity code on register NFSECC whenever it Reads or Writes data. 6. After you complete Reading or Writing spare area, set the SpareECCLock bit to "1" (Lock). It locks ECC parity code and it does not change the value of the ECC status register. 7. From now on, you can use these values to record to the spare area or verify the bit error. 8. For example, to verify the bit error of main data area on page Read operation, you should move the ECC parity codes (stored in spare area) to NFMECCD0 and NFMECCD1 after it generates ECC codes for main data area. From this point, the NFECCERR0 and NFECCERR1 have the valid error status values. NOTE: NFSECCD is for ECC in the spare area. The main data area generates the spare area. (Usually, the user writes the ECC value generated from main data area to spare area. The value is similar to NFMECC0/1). 10-7 Exynos 4412_UM 10 NAND Flash Controller 10.4.7 4-bit ECC Programming Guide (ENCODING) 1. To use 4-bit ECC in software mode, set the MsgLength to 0 (512 byte message length) and the ECCType to "1" (enable 4-bit ECC). ECC module generates ECC parity code for 512 byte read data. Therefore, to reset ECC value write the InitMECC (NFCONT[5]) bit as "1" and clear the MainECCLock (NFCONT[7]) bit to "0" (Unlock) before reading data. MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not. 2. Whenever it writes data, the 4-bit ECC module generates ECC parity code internally. 3. After you complete writing 512 byte data (excluding spare area data) it updates the parity codes automatically to NFMECC0 and NFMECC1 registers. If you use 512 byte NAND Flash memory, you can program these values to spare area. However, if you use NAND Flash memory more than 512 byte page, you cannot program immediately. In this case, you have to copy these parity codes to other memory like DRAM. After writing all main data, you can write the copied ECC values to spare area. The parity codes have self-correctable information including parity code itself. 4. To generate spare area ECC parity code, set the MsgLength to "1" (24 byte message length) and the ECC Type to "1" (enable 4-bit ECC). ECC module generates ECC parity code for 24 byte write data. To reset ECC value write the InitMECC (NFCONT[5]) bit as "1" and clear the MainECCLock (NFCONT[7]) bit to "0" (unlock) before writing data. MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not. 5. Whenever it writes data, the 4-bit ECC module generates ECC parity code internally. 6. When you complete writing 24 byte meta or extra data, it automatically updates the parity codes to NFMECC0 and NFMECC1 registers. You can program these parity codes to spare area. The parity codes have self-correctable information including parity code itself. 10-8 Exynos 4412_UM 10 NAND Flash Controller 10.4.8 4-bit ECC Programming Guide (DECODING) 1. To use 4-bit ECC in software mode, set the MsgLength to "0" (512 byte message length) and the ECCType to "1" (enable 4-bit ECC). ECC module generates ECC parity code for 512 byte read data. Therefore, to reset ECC value, write the InitMECC (NFCONT[5]) bit as "1" and clear the MainECCLock (NFCONT[7]) bit to "0" (Unlock) before reading data. MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not. 2. Whenever data is read, the 4-bit ECC module generates ECC parity code internally. 3. After you complete reading 512 byte (excluding spare area data), you should read parity codes. MLC ECC module needs parity codes to detect whether error bits have occurred or not. Therefore, you should read ECC parity code immediately after reading 512 byte. After reading ECC parity code, 4-bit ECC engine starts searching for error internally. 4-bit ECC error searching engine requires minimum of 155 cycles to find any error. During this time, you can continue reading main data from external NAND flash memory. Use ECCDecDone (NFSTAT[6]) to verify whether ECC decoding is completed or not. 4. When ECCDecDone (NFSTAT[6]) is set to "1", NFECCERR0 indicates whether error bit exists or not. If any error exists, refer NFECCERR0/1 and NFMLCBITPT registers to fix. 5. If you have more main data to Read, repeat step 1. 6. To verify meta data error, set the MsgLength to 1 (24-byte message length) and the ECCType to "1" (Enable 4-bit ECC). ECC module generates ECC parity code for 24-byte read data. Therefore, you must reset ECC value by writing the InitSECC (NFCONT[4]) bit as "1" and clear the SpareECCLock (NFCONT[6]) bit to"0" (Unlock) before reading data. SpareECCLock (NFCONT[6]) bit controls whether ECC Parity code is generated or not. 7. Whenever data is read, the 4-bit ECC module generates ECC parity code internally. 8. After you complete reading 24 byte (excluding spare area data), you should read parity codes. 4-bit ECC module needs parity codes to detect whether error bits have occurred or not. Therefore, ensure to read ECC parity codes immediately after reading 24 byte. After ECC parity code is read, 4-bit ECC engine starts searching for error internally to verify whether ECC decoding is completed or not. 9. When ECCDecDone (NFSTAT[6]) is set ("1"), NFECCERR0 indicates whether error bit exists or not. If any error exists, you can fix it by referring to NFECCERR0/1 and NFMLCBITPT registers. 10-9 Exynos 4412_UM 10 NAND Flash Controller 10.4.9 8/12/16-bit ECC Programming Guide (ENCODING) 1. To use 8/12/16-bit ECC in software mode, set the MsgLength (NFECCCONF[25:16]) to 511 (512 byte message length) and the ECCType to "001/100/101" (enable 8/12/16-bit ECC, respectively). ECC module generates ECC parity code for 512 byte write data. Therefore, reset ECC value by writing the InitMECC (NFECCCONT[2]) bit as "1" before writing data and clear the MainECCLock (NFCONT[7]) bit to "0" (unlock) before writing data. 2. Whenever data is written, the corresponding 8/12/16-bit ECC module generates ECC parity code internally. 3. After you complete writing 512 byte data (excluding spare area data), the parity codes are automatically updated to the NFECCPRG0-NFECCPRGECC6 registers. If you use a NAND flash memory that contains 512 byte page, you can program these values to spare area. However, if you use a NAND flash memory more than 512 byte page, you cannot program immediately. In this case, you should copy these ECC parity codes to other memory like DRAM. After writing all main data, you can write the copied ECC values to spare area. The parity codes have self-correctable information including parity code itself. The following table describes the ECC parity size. ECC Type 8-bit ECC 12-bit ECC 16-bit ECC Size of ECC Parity Codes 13 byte 20 byte 26 byte 4. To generate spare area ECC parity code for meta data, the steps are similar (from 1-3), except setting the MsgLenght (NFECCCONF[25:16]) to the size that you prefer. When you set InitMECC (NFECCCONT[2]), all ECC parity codes generated for main data are cleared. Therefore, you should copy the ECC parity codes for main data. NOTE: You should set the ECC parity conversion codes to verify free page error. Refer to 10.4.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC for more information. 10-10 Exynos 4412_UM 10 NAND Flash Controller 10.4.10 8/12/16-bit ECC Programming Guide (DECODING) 1. To use 8/12/16-bit ECC in software mode, set the MsgLength (NFECCCONF[25:16] to 511 (512 byte message length) and the ECCType to "001/100/101" (enable 8/12/16-bit ECC, respectively). ECC module generates ECC parity code for 512 byte read data. Therefore, you should reset ECC value by writing the InitMECC (NFECCCONT[2]) bit as "1" and clear the MainECCLock (NFCONT[7]) bit to "0" (unlock) before read data. 2. Whenever data is read, the 8/12/16-bit ECC module generates ECC parity code internally. 3. After you complete reading 512 byte (excluding spare area data), ensure to read the corresponding parity codes. ECC module requires parity codes to detect whether error bits have occurred or not. Therefore, you should read ECC parity code immediately after reading 512 byte. After reading the ECC parity code, the 8/12/16-bit ECC engine searches for error internally. 8/12/16-bit ECC search engine requires minimum of 155 cycles to find any errors. DecodeDone (NFECCSTAT[24]) can be used to check whether ECC decoding is completed or not. 4. When DecodeDone (NFECCSTAT[24]) is set ("1"), ECCError (NFECCSECSTAT[4:0]) indicates whether error bit exists or not. If any error exists, you can fix it by referencing NFECCERL0 to NFECCERL7 and NFECCERP0 to NFECCERP3 registers. 5. If you have additional main data to Read, repeat the steps 1-4. 6. To verify spare area data (meta data) error, the sequences are similar (steps 1-4), except setting the MsgLenght (NFECCCONF[25:16]) to the size that you want. NOTE: You should set the ECC parity conversion codes to check free page error. Refer to 10.4.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC, for more information. 10-11 Exynos 4412_UM 10 NAND Flash Controller 10.4.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC The ECC parity conversion codes are there to fix errors, which occur when reading a free page. Free page means the erased page. The 8/12/16-bit ECC modules support variable message size for meta data stored in spare area. Generally, the size of main data (sector) is 512 byte and user should set the corresponding ECC parity conversion codes as the Table describes: ECC Type 8-bit ECC 12-bit ECC 16-bit ECC ECC Parity Conversion Codes Here, 13 byte ECC parity conversion codes Here, 20 byte ECC parity conversion codes Here, 26 byte ECC parity conversion codes Depending on the requirements of users, the message size for meta data stored spare area might differ. Therefore, you can change the size of meta data by changing MsgLength (NFECCCONF[25:16]) and change ECC parity conversion codes. Steps to determine ECC parity conversion codes according to the size of message length are: 1. Clear all ECC parity conversion registers (NFECCCONECC0 to NFECCCONECC6) as all zero. 2. Set all registers for page program. 3. Reset InitMECC (NFECCCONT[2] bit as "1". 4. Write "0xff" data as much as the size of meta data. 5. After you write data as MsgLength (NFECCCONF[25:16]), the EncodeDone (NFECCSTAT[25]) is set to "1". It generates the corresponding ECC parity codes. 6. Set ECC parity conversion registers as inverted values of ECC parity codes generated. To ensure ECC parity conversion codes work properly, repeat step 3-5. After you set ECC parity conversion codes, if the generated ECC parity codes are all "0xff", then it is working correctly. Constraints to support free page function are: 1. Free page check is for only data area (512 byte) 2. If there is an error during reading a page erased (free page), then free page engine indicates that the page is not free page. 3. To detect errors on free page, you should set corresponding conversion codes. 10-12 Exynos 4412_UM 10 NAND Flash Controller 10.4.12 Lock Scheme for Data Protection NFCON provides a lock scheme to protect data stored in external NAND flash memories from malicious program. For this scheme, the NFSBLK and NFEBLK registers are used to provide access control methods. Only the memory area between NFSBLK and NFEBLK is erasable and programmable. However, the read access is available to entire memory area. This lock scheme is only available when you enable LockTight (NFCONT[17]) and LOCK(NFCONT[16]). 1. Unlock Mode In unlock mode, user can access entire NAND flash memory; there are no constraints to access memory. 2. Soft Lock Mode In soft lock mode, you can access NAND block area between NFSBLK and NFEBLK. When you try to program or erase the locked area, an illegal access error occurs (NFSTAT [5] bit will be set). 3. Lock-Tight Mode In lock-tight mode, you can access NAND block area between NFSBLK and NFEBLK as soft lock mode. The difference is that you cannot change NFSBLK and NFEBLK registers. You cannot change LockTight (NFCONT[17]) bits also. When you try to program or erase the locked area, an illegal access error occurs (it sets NFSTAT[5] bit). The LockTight (NFCONT[17]) bit is only cleared when reset or wake up from sleep mode (It is impossible to clear it by software). Figure 10-4 illustrates the accessibility of NAND area. NFEBLK +1 NFEBLK NFSBLK NFSBLK -1 . NAND flash memory Locked area ( Read only ) Address High When NFSBLK = NFEBLK Prorammable/ Readable Area Locked area ( Read only ) NFSBLK NFEBLK Locked Area ( Read only ) Low when Lock- tight =1 or SoftLock =1 Figure 10-4 Accessibility of NAND Area NOTE: If the address of NFSBLK and NFEBLK are similar, then it does not allow the erase and program to all NAND memory. 10-13 Exynos 4412_UM 10 NAND Flash Controller 10.5 Programming Constraints NFCON has a constraint to access an external NAND flash memory. NFCON accesses NAND flash memory through External Bus Interface (EBI) which uses two different clocks source. The constraint occurs because EBI operates using OneNAND external interface clock and EBI interface between NFCON and EBI is handled as asynchronous interface so that a few clock latencies consume for bus handshaking. The clock of NFCON should be set lower than EBI internal operation clock. Refer to the EBI and Clock Management Unit (CMU) manual, for more information. 10.6 I/O Description Signal Xm0DATA[7:0] Xm0FRnB[3:0] Xm0FCLE Xm0FALE Xm0CSn[3:0] Xm0REn Xm0WEn I/O Input/Output Input Output Output Output Output Output Description Address/data bus Ready and busy Command latch enable Address latch enable Chip enable Read enable Write enable Pad Xm0DATA[7:0] Xm0FRnB[3:0] Xm0FCLE Xm0FALE Xm0CSn[3:0] Xm0OEn Xm0WEn Type muxed muxed muxed muxed muxed muxed muxed 10-14 Exynos 4412_UM 10 NAND Flash Controller 10.7 Register Description 10.7.1 Register Map Summary  Base Address: 0x0CE0_0000 Register 1/4-bit ECC Register NFCONF NFCONT NFCMMD NFADDR NFDATA NFMECCD0 NFMECCD1 NFSECCD NFSBLK NFEBLK NFSTAT NFECCERR0 NFECCERR1 NFMECC0 NFMECC1 Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 NFSECC NFMLCBITPT 0x003C 0x0040 Description Configuration register Control register Command register Address register Data register 1st and 2nd main ECC data register 3rd and 4th main ECC data register Spare ECC read register Programmable start block address register Programmable end block address register NAND status register ECC error status0 register ECC error status1 register Generated ECC status0 register Generated ECC status1 register Generated spare area ECC status register 4-bit ECC error bit pattern register Reset Value 0x0000_1000 0x00C1_00C6 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 0xF080_0F0D 0x0003_FFF2 0x0000_0000 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0x0000_0000 10-15 Exynos 4412_UM 10 NAND Flash Controller  Base Address: 0x0CE2_0000 Register Offset 8/12/16-bit ECC Register NFECCCONF 0000 NFECCCONT 0020 NFECCSTAT 0030 NFECCSECSTAT 0040 NFECCPRGECC0 0090 NFECCPRGECC1 0094 NFECCPRGECC2 0098 NFECCPRGECC3 009C NFECCPRGECC4 00A0 NFECCPRGECC5 00A4 NFECCPRGECC6 00A8 NFECCERL0 00C0 NFECCERL1 00C4 NFECCERL2 00C8 NFECCERL3 00CC NFECCERL4 00D0 NFECCERL5 00D4 NFECCERL6 00D8 NFECCERL7 00DC NFECCERP0 00F0 NFECCERP1 00F4 NFECCERP2 00F8 NFECCERP3 00FC NFECCCONECC0 0110 NFECCCONECC1 0114 NFECCCONECC2 0118 NFECCCONECC3 011C NFECCCONECC4 0120 NFECCCONECC5 0124 NFECCCONECC6 0128 Description ECC configuration register ECC control register ECC status register ECC sector status register ECC parity code0 register for page program ECC parity code1 register for page program ECC parity code2 register for page program ECC parity code3 register for page program ECC parity code4 register for page program ECC parity code5 register for page program ECC parity code6 register for page program ECC error byte location0 register ECC error byte location1 register ECC error byte location2 register ECC error byte location3 register ECC error byte location4 register ECC error byte location5 register ECC error byte location6 register ECC error byte location7 register ECC error bit pattern0 register ECC error bit pattern1 register ECC error bit pattern2 register ECC error bit pattern3 register ECC parity conversion code0 register ECC parity conversion code1 register ECC parity conversion code2 register ECC parity conversion code3 register ECC parity conversion code4 register ECC parity conversion code5 register ECC parity conversion code6 register Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 10-16 Exynos 4412_UM 10 NAND Flash Controller 10.7.2 NAND Flash Interface and 1/4-bit ECC Registers 10.7.2.1 NFCONF  Base Address: 0x0CE0_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_1000 Name RSVD MsgLength ECCType0 RSVD TACLS TWRPH0 TWRPH1 PageSize AddrCycle RSVD Bit [31:26] [25] [24:23] [22:16] [15:12] [11:8] [7:4] [3:2] [1] [0] Type – RW RW – RW RW RW RW RW – Description Reserved 0 = 512 byte message length 1 = 24 byte message length This bit indicates the type of ECC to use. 00 = 1-bit ECC 10 = 4-bit ECC 01 = 11 = Disables 1-bit and 4-bit ECC Reserved CLE and ALE duration setting value (0 – 15)  Duration = HCLK  TACLS TWRPH0 duration setting value (0 – 15)  Duration = HCLK  (TWRPH0 + 1) NOTE: You should add additional cycles about 10ns for page read because of additional signal delay on PCB pattern. TWRPH1 duration setting value (0 – 15)  Duration = HCLK  (TWRPH1 + 1) This bit indicates the page size of NAND flash memory 00 = 2048 byte 01 = 512 byte 10 = 4096 byte 11 = 2048 byte NOTE: Using 1-bit ECC it determines the message length. It does not determine the message length using MsgLength (NFCONF[25] field. NFCON does not consider the actual page size of external NAND. Software handles the page size. This bit indicates the number of address cycle of NAND flash memory. When Page Size is 512 Bytes: 0 = 3 Address cycle 1 = 4 Address cycle When page size is 2 K or 4 K: 0 = 4 Address cycle 1 = 5 Address cycle NOTE: It is only used for Lock scheme. Refer to section 10.4.12 Lock Scheme for Data Protection, for more information. Reserved Reset Value 0 0 0 0000000 0x1 0x0 0x0 0 0 0 10-17 Exynos 4412_UM 10 NAND Flash Controller 10.7.2.2 NFCONT  Base Address: 0x0CE0_0000  Address = Base Address + 0x0004, Reset Value = 0x00C1_00C6 Name RSVD Reg_nCE3 Reg_nCE2 RSVD MLCEccDirection LockTight LOCK RSVD EnbMLCEncInt EnbMLCDecInt RSVD EnbIllegalAccINT EnbRnBINT Bit [31:24] [23] [22] [21:19] [18] [17] [16] [15:14] [13] [12] [11] [10] [9] Type – RW RW – RW RW RW – RW RW – RW RW Description Reserved NAND flash memory nRCS[3] signal control 0 = Force nRCS[3] to low (Enables chip select) 1 = Force nRCS[3] to high (Disables chip select) NAND flash memory nRCS[2] signal control 0 = Force nRCS[2] to low (Enables chip select) 1 = Force nRCS[2] to high (Disables chip select) Reserved 4-bit, ECC encoding/decoding control 0 = Decoding 4-bit ECC. It is used for page read 1 = Encoding 4-bit ECC. It is used for page program Lock-tight configuration 0 = Disables lock-tight 1 = Enables lock-tight If this bit is set to 1, you cannot clear this bit. Refer to 10.4.12 Lock Scheme for Data Protection, for more information. Soft Lock configuration 0 = Disables lock 1 = Enables lock Software can modify soft lock area any time. Refer to 10.4.12 Lock Scheme for Data Protection, for more information. Reserved 4-bit ECC encoding completion interrupt control 0 = Disables interrupt 1 = Enables interrupt 4-bit ECC decoding completion interrupt control 0 = Disables interrupt 1 = Enables interrupt Reserved Illegal access interrupt control 0 = Disables interrupt 1 = Enables interrupt Illegal access interrupt occurs when CPU tries to program or erase locking area (the area setting in NFSBLK (0xB0E0_0020) to NFEBLK (0xB0E0_0024) – 1. RnB status input signal transition interrupt control 0 = Disables RnB interrupt Reset Value 0 1 1 0 0 0 1 00 0 0 0 0 0 10-18 Exynos 4412_UM 10 NAND Flash Controller Name RnB_TransMode MECCLock SECCLock InitMECC InitSECC HW_nCE Reg_nCE1 Reg_nCE0 MODE Bit Type Description 1 = Enables RnB interrupt Reset Value RnB transition detection configuration [8] RW 0 = Detects rising edge 0 1 = Detects falling edge Lock Main area ECC generation 0 = Unlocks Main area ECC [7] RW 1 = Locks Main area ECC 1 Main area ECC status register is NFMECC0/NFMECC1 (0xB0E0_0034/0xB0E0_0038), Lock Spare area ECC generation 0 = Unlocks Spare ECC [6] RW 1 = Locks Spare ECC 1 Spare area ECC status register is NFSECC (0xB0E0_003C) [5] RW 1 = Initializes main area ECC decoder/encoder (Writeonly) 0 [4] RW 1 = Initializes spare area ECC decoder/encoder (Writeonly) 0 [3] RW Reserved (HW_nCE) 0 [2] RW NAND flash memory nRCS[1] signal control 1 NAND flash memory nRCS[0] signal control 0 = Force nRCS[0] to low (enables chip select) 1 = Force nRCS[0] to high (disables chip select) [1] RW NOTE: The setting all nCE[3:0] zero cannot be allowed. 1 Only one nCE can be asserted to enable external NAND flash memory. The lower bit has more priority when user set all nCE[3:0] zeros. NAND flash controller operating mode [0] RW 0 = Disables NAND flash controller 0 1 = Enables NAND flash controller 10-19 Exynos 4412_UM 10 NAND Flash Controller 10.7.2.3 NFCMMD  Base Address: 0x0CE0_0000  Address = Base Address + 0x0008, Reset Value = 0x0000_0000 Name RSVD REG_CMMD Bit [31:8] [7:0] Type – RW Description Reserved NAND flash memory command value Reset Value 0x000000 0x00 10.7.2.4 NFADDR  Base Address: 0x0CE0_0000  Address = Base Address + 0x000C, Reset Value = 0x0000_0000 Name RSVD REG_ADDR Bit [31:8] [7:0] Type – RW Description Reserved NAND flash memory address value Reset Value 0x000000 0x00 10.7.2.5 NFDATA  Base Address: 0x0CE0_0000  Address = Base Address + 0x0010, Reset Value = 0x0000_0000 Name NFDATA Bit [31:0] Type RW Description NAND flash Read/program data value for I/O NOTE: Refer to 10.4.1 Data Register Configuration, for more information. Reset Value 0x00000000 10.7.2.6 NFMECCD  Base Address: 0x0CE0_0000  Address = Base Address + 0x0014, Reset Value = 0x0000_0000 Name RSVD ECCData1 (ECC1) RSVD ECCData0 (ECC0) Bit [31:24] [23:16] [15:8] [7:0] Type – RW – RW Description Reserved 2nd ECC NOTE: In software mode, read this register when you need to read 2nd ECC value from NAND flash memory Reserved 1st ECC. NOTE: In software mode, read this register when you need to read 1st ECC value from NAND flash memory. This register has the similar Read function as NFDATA. NOTE: It allows only word access. Reset Value 0x00 0x00 0x00 0x00 10-20 Exynos 4412_UM 10 NAND Flash Controller 10.7.2.7 NFMECCD1  Base Address: 0x0CE0_0000  Address = Base Address + 0x0018, Reset Value = 0x0000_0000 Name RSVD ECCData3 (ECC3) RSVD ECCData2 (ECC2) Bit [31:24] [23:16] [15:8] [7:0] Type – RW – RW Description Reserved 4th ECC. NOTE: In software mode, read this register when you need to read 4th ECC value from NAND flash memory Reserved 3rd ECC. NOTE: In software mode, read this register when you need to read 3rd ECC value from NAND flash memory. This register has the similar Read function as NFDATA. Reset Value 0x00 0x00 0x00 0x00 10.7.2.8 NFSECCD  Base Address: 0x0CE0_0000  Address = Base Address + 0x001C, Reset Value = 0xFFFF_FFFF Name RSVD SECCData1 RSVD SECCData0 Bit [31:24] [23:16] [15:8] [7:0] Type – RW – RW Description Reserved 2nd ECC. NOTE: In software mode, read this register when you need to read 2nd ECC value from NAND flash memory Reserved 1st ECC. NOTE: In software mode, read this register when you need to read 1st ECC value from NAND flash memory. This register has the similar Read function as NFDATA. NOTE: It allows only word access. Reset Value 0x00 0xFF 0x00 0xFF 10-21 Exynos 4412_UM 10 NAND Flash Controller 10.7.2.9 NFSBLK  Base Address: 0x0CE0_0000  Address = Base Address + 0x0020, Reset Value = 0x0000_0000 Name RSVD SBLK_ADDR2 SBLK_ADDR1 SBLK_ADDR0 Bit [31:24] [23:16] [15:8] [7:0] Type – RW RW RW Description Reserved The 3rd block address of the block erase operation The 2nd block address of the block erase operation The 1st block address of the block erase operation (Only bit[7:5] are valid). Reset Value 0x00 0x00 0x00 0x00 NOTE: Address of Advance Flash block starts from 3-address cycle. So block address register only requires 3-bytes. Refer to 10.4.12 Lock Scheme for Data Protection, for more information on lock scheme. 10.7.2.10 NFEBLK  Base Address: 0x0CE0_0000  Address = Base Address + 0x0024, Reset Value = 0x0000_0000 Name RSVD EBLK_ADDR2 EBLK_ADDR1 EBLK_ADDR0 Bit [31:24] [23:16] [15:8] [7:0] Type – RW RW RW Description Reserved The 3rd block address of the block erase operation The 2nd block address of the block erase operation The 1st block address of the block erase operation (Only bit[7:5] are valid) Reset Value 0x00 0x00 0x00 0x00 NOTE: Address of Advance Flash block starts from 3-address cycle. So block address register only requires 3-bytes. Refer to 10.4.12 Lock Scheme for Data Protection for more information on lock scheme. 10-22 Exynos 4412_UM 10 NAND Flash Controller 10.7.2.11 NFSTAT  Base Address: 0x0CE0_0000  Address = Base Address + 0x0028, Reset Value = 0xF080_0F0D Name Flash_RnB_GRP RnB_TransDetect_ GRP RSVD Flash_nCE[3:0] (Read-only) MLCEncodeDone MLCDecodeDone IllegalAccess RnB_TransDetect Flash_nCE[1] (Read-only) Flash_nCE[0] (Read-only) RSVD Bit [31:28] [27:24] [23:12] [11:8] [7] [6] [5] [4] [3] [2] [1] Type RW RW – RW RW RW RW RW RW RW – Description The status of RnB[3:0] input pin 0 = NAND flash memory busy 1 = NAND flash memory ready to operate When RnB[3:0] low to high transition occurs, this bit is set and an interrupt is issued if RnB_TransDetect_GRP is enabled. To clear this, write "1". 0 = RnB transition is not detected 1 = RnB transition is detected Transition configuration is set in RnB_TransMode(NFCONT[8]). Reserved The status of nCE[3:0] output pin When it completes 4-bit ECC encoding, this bit is set and it issues an interrupt if it enables MLCEncodeDone. The NFMLCECC0 and NFMLCECC1 have valid values. To clear this, write "1". 1 = It completes 4-bit ECC encoding When it completes 4-bit ECC decoding, this bit is set and it issues an interrupt if it enables MLCDecodeDone. The NFMLCBITPT, NFMLCL0, and NFMLCEL1 have valid values. To clear this, write "1". 1 = Completes 4-bit ECC decoding Once Soft Lock or Lock-tight is enabled and any illegal access (program, erase) to the memory takes place, then this bit is set. 0 = It does not detect illegal access 1 = It detects illegal access To clear this value, write 1 to this bit. When RnB[0] low to high transition occurs, this bit is set and an interrupt is issued if RnB_TransDetect is enabled. To clear this, write "1". 0 = It does not detect RnB transition 1 = It detects RnB transition Transition configuration is set in RnB_TransMode(NFCONT[8]). The status of nCE[1] output pin The status of nCE[0] output pin Reserved Reset Value 0xF – 0x800 0xF 0 0 0 0 1 1 0 10-23 Exynos 4412_UM 10 NAND Flash Controller Name Flash_RnB (Read-only) Bit Type Description The status of RnB[0] input pin [0] RW 0 = NAND flash memory busy 1 = NAND flash memory ready to operate Reset Value 1 10-24 Exynos 4412_UM 10 NAND Flash Controller 10.7.2.12 NFECCERR0  Base Address: 0x0CE0_0000  Address = Base Address + 0x002C, Reset Value = 0x0003_FFF2 When ECC Type is 1-bit ECC Name RSVD ECCSDataAddr ECCSBitAddr ECCDataAddr ECCBitAddr ECCSprErrNo ECCMainErrNo Bit [31:25] [24:21] [20:18] [17:7] [6:4] [3:2] [1:0] Type – R R R R R R Description Reserved In spare area, indicates which number data is error In spare area, indicates which bit is error In main data area, indicates which number data is error In main data area, indicates which bit is error Indicates whether spare area bit fail error occurred 00 = No Error 01 = 1-bit error (correctable) 10 = Multiple error 11 = ECC area error Indicates whether main data area bit fail error occurred 00 = No Error 01 = 1-bit error (Correctable) 10 = Multiple error 11 = ECC area error Reset Value 0x00 0x0 000 0x7FF 111 00 10 NOTE: The above values are valid only when both ECC register and ECC status register have valid value. When ECC Type is 4-bit ECC Name MLCECCBusy MLCECCReady MLCFreePage MLCECCError MLCErrLocation2 Bit [31] [30] [29] [28:26] [25:16] Type R R R R R Description Indicates the 4-bit ECC decoding engine is searching whether a error exists or not 0 = Idle 1 = Busy ECC Ready bit Indicates the page data read from NAND flash has all "FF" value. 4-bit ECC decoding result 000 = No error 001 = 1-bit error 010 = 2-bit error 011 = 3-bit error 100 = 4-bit error 101 = Uncorrectable 11x = Reserved Error byte location of 2nd bit error Reset Value 0 1 0 000 0x000 10-25 Exynos 4412_UM Name RSVD MLCErrLocation1 Bit [15:10] [9:0] Type – R Description Reserved Error byte location of 1st bit error NOTE: These values are updated when ECCDecodeDone (NFSTAT[6]) is set ("1"). 10 NAND Flash Controller Reset Value 0x00 0x000 10-26 Exynos 4412_UM 10.7.2.13 NFECCERR1  Base Address: 0x0CE0_0000  Address = Base Address + 0x0030, Reset Value = 0x0000_0000 When ECC Type is 4-bit ECC Name RSVD MLCErrLocation4 RSVD MLCErrLocation3 Bit [31:26] [25:16] [15:10] [9:0] Type – R – R Description Reserved Error byte location of 4th bit error Reserved Error byte location of 3rd bit error NOTE: These values are updated when ECCDecodeDone (NFSTAT[6]) is set ("1"). 10 NAND Flash Controller Reset Value 0x00 0x00 0x00 0x000 10.7.2.14 NFMECC0  Base Address: 0x0CE0_0000  Address = Base Address + 0x0034, Reset Value = 0xFFFF_FFFF When ECC Type is 1-bit ECC Name MECC3 MECC2 MECC1 MECC0 Bit [31:24] [23:16] [15:8] [7:0] Type R R R R ECC3 for data ECC2 for data ECC1 for data ECC0 for data Description Reset Value 0xFF 0xFF 0xFF 0xFF NOTE: The NAND flash controller generate NFMECC0/1 when read or write main area data while the MainECCLock (NFCONT[7]) bit is "0" (Unlock). When ECC Type is 4-bit ECC Name 4th Parity 3rd Parity 2nd Parity 1st Parity Bit [31:24] [23:16] [15:8] [7:0] Type R R R R Description 4th Check parity generated from main area (512 byte) 3rd Check parity generated from main area (512 byte) 2nd Check parity generated from main area (512 byte) 1st Check parity generated from main area (512 byte) Reset Value 0x00 0x00 0x00 0x00 NOTE: The NAND flash controller generates these ECC parity codes when write main area data while the MainECCLock (NFCON[7]) bit is "0" (unlock). 10-27 Exynos 4412_UM 10 NAND Flash Controller 10.7.2.15 NFMECC1  Base Address: 0x0CE0_0000  Address = Base Address + 0x0038, Reset Value = 0xFFFF_FFFF When ECC Type is 4-bit ECC Name RSVD 7th Parity 6th Parity 5th Parity Bit [31:24] [23:16] [15:8] [7:0] Type – R R R Description Reserved 7th Check parity generated from main area (512 byte) 6th Check parity generated from main area (512 byte) 5th Check parity generated from main area (512 byte) Reset Value 0x00 0x00 0x00 0x00 NOTE: The NAND flash controller generates these ECC parity codes when write main area data while the MainECCLock (NFCON[7]) bit is "0" (unlock). 10.7.2.16 NFSECC  Base Address: 0x0CE0_0000  Address = Base Address + 0x003C, Reset Value = 0xFFFF_FFFF Name RSVD SECC1 SECC0 Bit [31:16] [15:8] [7:0] Type – R R Description Reserved Spare area ECC1 Status Spare area ECC0 Status Reset Value 0xFFFF 0xFF 0xFF NOTE: The NAND flash controller generates NFSECC when Read or Write spare area data while the SpareECCLock (NFCONT[6]) bit is "0" (unlock). 10.7.2.17 NFMLCBITPT  Base Address: 0x0CE0_0000  Address = Base Address + 0x0040, Reset Value = 0x0000_0000 Name 4th Error bit pattern 3rd Error bit pattern 2nd Error bit pattern 1st Error bit pattern Bit [31:24] [23:16] [15:8] [7:0] Type R R R R Description 4th Error bit pattern 3rd Error bit pattern 2nd Error bit pattern 1st Error bit pattern Reset Value 0x00 0x00 0x00 0x00 10-28 Exynos 4412_UM 10 NAND Flash Controller 10.7.3 ECC Registers for 8, 12 and 16-bit ECC 10.7.3.1 NFECCCONF  Base Address: 0x0CE2_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_0000 Name RSVD RSVD MsgLength RSVD ECCType Bit [31] [28] [25:16] [15:4] [3:0] Type – – RW – RW Description Reserved Reserved The ECC message size For 512 byte message, you should set to 511. Reserved These bits indicate what type of ECC is used. 000 = Disables 8/12/16-bit ECC 001 = Reserved 010 = Reserved 011 = 8-bit ECC/512B 100 = 12-bit ECC 101 = 16-bit ECC/512B 110 = Reserved 111 = Reserved Reset Value 0 0 – 0 0x0 10.7.3.2 NFECCCONT  Base Address: 0x0CE2_0000  Address = Base Address + 0x0020, Reset Value = 0x0000_0000 Name RSVD EnbMLCEncInt EnbMLCDecInt EccDirection RSVD InitMECC RSVD ResetECC Bit [31:26] [25] [24] [16] [15:3] [2] [1] [0] Type – RW RW RW – RW – RW Description Reserved MLC ECC encoding completion interrupt control 0 = Disables interrupt 1 = Enables interrupt MLC ECC decoding completion interrupt control 0 = Disables interrupt 1 = Enables interrupt MLC ECC encoding/decoding control 0 = Decoding, used for page read 1 = Encoding, used for page program Reserved 1 = Initialize main area ECC decoder/encoder (Write-only) Reserved 1 = Reset ECC logic (Write-only) Reset Value 0x00 0 0 0 0x0 0 0 0 10-29 Exynos 4412_UM 10 NAND Flash Controller 10.7.3.3 NFECCSTAT  Base Address: 0x0CE2_0000  Address = Base Address + 0x0030, Reset Value = 0x0000_0000 Name ECCBusy RSVD EncodeDone DecodeDone RSVD FreePageStat RSVD Bit [31] [30] [25] [24] [23:9] [8] [7:0] Type R – RWX RWX – R – Description Indicates the 8-bit ECC decoding engine is searching whether a error exists or not 0 = Idle 1 = Busy Reserved When MLC ECC encoding is finished, this value set and issue interrupt if EncodeDone is enabled. The NFMLCECC0 and NFMLCECC1 have valid values. To clear this, write "1". 1 = It completes MLC ECC encoding When MLC ECC decoding is finished, this value set and issue interrupt if DecodeDone is enabled. The NFMLCBITPT, NFMLCL0, and NFMLCEL1 have valid values. To clear this, write "1". 1 = It completes MLC ECC decoding Reserved It indicates whether the sector is free page or not. Reserved Reset Value 0 1 0 0 0x0000 0 0x00 10.7.3.4 NFECCSECSTAT  Base Address: 0x0CE2_0000  Address = Base Address + 0x0040, Reset Value = 0x0000_0000 Name ValdErrorStat ECCErrorNo Bit [31:8] [4:0] Type R R Description Each bit indicates which ERL and ERP are valid. ECC decoding result when page read 00000 = No error 00001 = 1-bit error 00010 = 2-bit error 00011 = 3-bit error .... 01110 = 14-bit error 01111 = 15-bit error 10000 = 16-bit error NOTE: If it uses 8-bit ECC, the valid number of error is until 8. If the number exceeds the supported error number, it means that uncorrectable error occurs. Reset Value 0x0000_00 0x00 10-30 Exynos 4412_UM 10 NAND Flash Controller 10.7.3.5 NFECCPRGECCn (n = 0 to 6)  Base Address: 0x0CE2_0000  Address = Base Address + 0x0090, Reset Value = 0x0000_0000 (NFECCPRGECC0)  Address = Base Address + 0x0094, Reset Value = 0x0000_0000 (NFECCPRGECC1)  Address = Base Address + 0x0098, Reset Value = 0x0000_0000 (NFECCPRGECC2)  Address = Base Address + 0x009C, Reset Value = 0x0000_0000 (NFECCPRGECC3)  Address = Base Address + 0x00A0, Reset Value = 0x0000_0000 (NFECCPRGECC4)  Address = Base Address + 0x00A4, Reset Value = 0x0000_0000 (NFECCPRGECC5)  Address = Base Address + 0x00A8, Reset Value = 0x0000_0000 (NFECCPRGECC6) Name 4th Parity 3rd Parity 2nd Parity 1st Parity 8th Parity 7th Parity 6th Parity 5th Parity 12th Parity 11th Parity 10th Parity 9th Parity 16th Parity 15th Parity 14th Parity 13th Parity 20th Parity 19th Parity 18th Parity 17th Parity 24th Parity 23rd Parity 22th Parity 21th Parity RSVD 26th Parity 25th Parity Bit [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:16] [15:8] [7:0] Type R R R R R R R R R R R R R R R R R R R R R R R R – R R Description 4th check parity for page program from main area 3rd check parity for page program from main area 2nd check parity for page program from main area 1st check parity for page program from main area 8th check parity generated from main area 7th check parity generated from main area 6th check parity generated from main area 5th check parity generated from main area 12th check parity generated from main area 11th check parity generated from main area 10th check parity generated from main area 9th check parity generated from main area 16th check parity generated from main area 15th check parity generated from main area 14th check parity generated from main area 13th check parity generated from main area 20th check parity generated from main area 19th check parity generated from main area 18th check parity generated from main area 17th check parity generated from main area 24th check parity generated from main area 23rd check parity generated from main area 22th check parity generated from main area 21th check parity generated from main area Reserved 26th check parity generated from main area 25th check parity generated from main area Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 – 0x00 0x00 10-31 Exynos 4412_UM 10 NAND Flash Controller NOTE: The NAND flash controller generates these ECC parity codes when write main area data while the MainECCLock (NFCON[7]) bit is "0" (unlock). 10-32 Exynos 4412_UM 10 NAND Flash Controller 10.7.3.6 NFECCERLn (n = 0 to 7)  Base Address: 0x0CE2_0000  Address = Base Address + 0x00C0, Reset Value = 0x0000_0000 (NFECCERL0)  Address = Base Address + 0x00C4, Reset Value = 0x0000_0000 (NFECCERL1)  Address = Base Address + 0x00C8, Reset Value = 0x0000_0000 (NFECCERL2)  Address = Base Address + 0x00CC, Reset Value = 0x0000_0000 (NFECCERL3)  Address = Base Address + 0x00D0, Reset Value = 0x0000_0000 (NFECCERL4)  Address = Base Address + 0x00D4, Reset Value = 0x0000_0000 (NFECCERL5)  Address = Base Address + 0x00D8, Reset Value = 0x0000_0000 (NFECCERL6)  Address = Base Address + 0x00DC, Reset Value = 0x0000_0000 (NFECCERL7) Name RSVD ErrByteLoc2 RSVD ErrByteLoc1 RSVD ErrByteLoc4 RSVD ErrByteLoc3 RSVD ErrByteLoc6 RSVD ErrByteLoc5 RSVD ErrByteLoc8 RSVD ErrByteLoc7 RSVD ErrByteLoc10 RSVD ErrByteLoc9 RSVD ErrByteLoc12 RSVD ErrByteLoc11 RSVD ErrByteLoc14 Bit [31:26] [25:16] [15:10] [9:0] [31:26] [25:16] [15:10] [9:0] [31:26] [25:16] [15:10] [9:0] [31:26] [25:16] [15:10] [9:0] [31:26] [25:16] [15:10] [9:0] [31:26] [25:16] [15:10] [9:0] [31:26] [25:16] Type – R – R – R – R – R – R – R – R – R – R – R – R – R Description Reserved Error byte location of 2nd bit error Reserved Error byte location of 1st bit error Reserved Error byte location of 4th bit error Reserved Error byte location of 3rd bit error Reserved Error byte location of 6th bit error Reserved Error byte location of 5th bit error Reserved Error byte location of 8th bit error Reserved Error byte location of 7th bit error Reserved Error byte location of 10th bit error Reserved Error byte location of 9th bit error Reserved Error byte location of 12th bit error Reserved Error byte location of 11th bit error Reserved Error byte location of 14th bit error Reset Value 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 0x0 0x000 10-33 Exynos 4412_UM Name RSVD ErrByteLoc13 RSVD ErrByteLoc16 RSVD ErrByteLoc15 Bit [15:10] [9:0] [31:26] [25:16] [15:10] [9:0] Type – R – R – R Description Reserved Error byte location of 13th bit error Reserved Error byte location of 16th bit error Reserved Error byte location of 15th bit error NOTE: It updates these values when DecodeDone (NFECCSTAT[24]) is set ("1"). 10 NAND Flash Controller Reset Value 0x0 0x000 0x0 0x000 0x0 0x000 10-34 Exynos 4412_UM 10 NAND Flash Controller 10.7.3.7 NFECCERPn (n = 0 to 3)  Base Address: 0x0CE2_0000  Address = Base Address + 0x00F0, Reset Value = 0x0000_0000 (NFECCERP0)  Address = Base Address + 0x00F4, Reset Value = 0x0000_0000 (NFECCERP1)  Address = Base Address + 0x00F8, Reset Value = 0x0000_0000 (NFECCERP2)  Address = Base Address + 0x00FC, Reset Value = 0x0000_0000 (NFECCERP3) Name 4th ErrBitPattern 3rd ErrBitPattern 2nd ErrBitPattern 1st ErrBitPattern 8th ErrBitPattern 7th ErrBitPattern 6th ErrBitPattern 5th ErrBitPattern 12th ErrBitPattern 11th ErrBitPattern 10th ErrBitPattern 9th ErrBitPattern 16th ErrBitPattern 15th Error bit pattern 14th ErrBitPattern 13th ErrBitPattern Bit [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] Type R R R R R R R R R R R R R R R R Description 4th Error Bit Pattern 3rd Error bit pattern 2nd Error bit pattern 1st Error bit pattern 8th Error bit pattern 7th Error bit pattern 6th Error bit pattern 5th Error bit pattern 12th Error bit pattern 11th Error bit pattern 10th Error bit pattern 9th Error bit pattern 16th Error bit pattern 15th Error bit pattern 14th Error bit pattern 13th Error bit pattern NOTE: It updates these values when DecodeDone (NFECCSTAT[25]) is set ("1"). Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 10-35 Exynos 4412_UM 10 NAND Flash Controller 10.7.3.8 NFECCCONECCn (n = 0 to 6)  Base Address: 0x0CE2_0000  Address = Base Address + 0x0110, Reset Value = 0x0000_0000 (NFECCCONECC0)  Address = Base Address + 0x0114, Reset Value = 0x0000_0000 (NFECCCONECC1)  Address = Base Address + 0x0118, Reset Value = 0x0000_0000 (NFECCCONECC2)  Address = Base Address + 0x011C, Reset Value = 0x0000_0000 (NFECCCONECC3)  Address = Base Address + 0x0120, Reset Value = 0x0000_0000 (NFECCCONECC4)  Address = Base Address + 0x0124, Reset Value = 0x0000_0000 (NFECCCONECC5)  Address = Base Address + 0x0128, Reset Value = 0x0000_0000 (NFECCCONECC6) Name 4th Conversion Code 3rd Conversion Code 2nd Conversion Code 1st Conversion Code 8th Conversion Code 7th Conversion Code 6th Conversion Code 5th Conversion Code 12th Conversion Code 11th Conversion Code 10th Conversion Code 9th Conversion Code 16th Conversion Code 15th Conversion Code 14th Conversion Code 13th Conversion Code 20th Conversion Code 19th Conversion Code 18th Conversion Code 17th Conversion Code 24th Conversion Code 23th Conversion Code 22th Conversion Code 21th Conversion Code RSVD 26th Conversion Code 25th Conversion Code Bit [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:16] [15:8] [7:0] Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW – RW RW Description 4th ECC Parity Conversion Code 3rd ECC Parity conversion code 2nd ECC Parity conversion code 1st ECC Parity conversion code 8th ECC Parity conversion code 7th ECC Parity conversion code 6th ECC Parity conversion code 5th ECC Parity conversion code 12th ECC Parity conversion code 11th ECC Parity conversion code 10th ECC Parity conversion code 9th ECC Parity conversion code 16th ECC Parity conversion code 15th ECC Parity conversion code 14th ECC Parity conversion code 13th ECC Parity conversion code 20th ECC Parity conversion code 19th ECC Parity conversion code 18th ECC Parity conversion code 17th ECC Parity conversion code 24th ECC Parity conversion code 23th ECC Parity conversion code 22th ECC Parity conversion code 21th ECC Parity conversion code Reserved 26th ECC Parity conversion code 25th ECC Parity conversion code Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0000 0x00 0x00 10-36 Exynos 4412_UM 10 NAND Flash Controller NOTE: For more information about ECC parity conversion codes, refer to 10.4.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC. 10-37 Exynos 4412_UM 11 Pulse Width Modulation Timer 11 Pulse Width Modulation Timer 11.1 Overview Exynos 4412 has five 32-bit Pulse Width Modulation (PWM) timers. These timers generate internal interrupts for the ARM subsystem. Additionally, timers 0, 1, 2, and 3 include a PWM function that drives an external I/O signal. The PWM in timer 0 has an optional dead-zone generator capability to support a large current device. Timer 4 is an internal timer without output pins. The Timers use the APB-PCLK as source clock. Timers 0 and 1 share a programmable 8-bit prescaler that provides the first level of division for the PCLK. Timers 2, 3, and 4 share a different 8-bit prescaler. Each timer has its own private clock-divider that provides a second level of clock division (prescaler divided by 2, 4, 8, or 16). Each timer has its 32-bit down-counter; the timer clock drives this counter. The Timer Count Buffer registers (TCNTBn) loads initial value of the down-counter. If the down-counter reaches zero, it generates the timer interrupt request to inform the CPU that the timer operation is complete. If the timer down-counter reaches zero, the value of corresponding TCNTBn automatically reloads into the down-counter to start a next cycle. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of TCNTBn does not reload into the counter. The PWM function uses the value of the TCMPBn register. The timer control logic changes the output level if down-counter value matches the value of the compare register in timer control logic. Therefore, the compare register determines the turn-on time or turn-off time of a PWM output. Each timer is double-buffer structure with the TCNTBn and TCMPBn registers to allow the timer parameters to update in the middle of a cycle. The new values do not take effect until the current timer cycle completes. 11-1 Exynos 4412_UM Figure 11-1 illustrates the simple example of a PWM cycle. 1 2 3 11 Pulse Width Modulation Timer 4 TOUTn 50 109 110 5 Figure 11-1 Simple Example of a PWM Cycle Steps to use PWM as a pulse generator are: 5. Initialize the TCNTBn register with 159 (50 + 109) and TCMPBn with 109. 6. Start Timer: Set the start bit and manually update this bit to off. 7. The TCNTBn value of 159 is loaded into the down-counter, and then the output TOUTn is set to low. 8. If down-counter counts down the value from TCNTBn to value in the TCMPBn register 109, the output changes from low to high. 9. If the down-counter reaches 0, then it generates an interrupt request. 10. The down-counter automatically reloads TCNTBn. This restarts the cycle. 11-2 Exynos 4412_UM 11 Pulse Width Modulation Timer Figure 11-2 illustrates the clock generation scheme for individual PWM channels. PCLK 1/1 1/2 8BIT PRESCALER 1/4 0 1/8 1/16 TCMPB0 TCNTB0 6:1 Control MUX Logic 0 TCMPB1 TCNTB1 6:1 MUX Control Logic 1 TCMPB2 TCNTB2 6:1 MUX Control Logic 2 DeadZone Generator XpwmTOUT0 DeadZone XpwmTOUT1 DeadZone XpwmTOUT2 1/1 1/2 8BIT PRESCALER 1/4 1 1/8 1/16 TCMPB3 TCNTB3 6:1 MUX Control Logic 3 TCNTB4 6:1 MUX Control Logic 4 XpwmTOUT3 No pin Figure 11-2 PWM TIMER Clock Tree Diagram Each timer can generate level interrupts. 11-3 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.2 Features The features of PWM are:  Five 32-bit timers.  Two 8-bit Clock Prescalers providing first level of division for the PCLK. Five Clock Dividers and Multiplexers providing second level of division for the Prescaler clock.  Programmable Clock Select Logic for individual PWM Channels  Four Independent PWM Channels with Programmable Duty Control and Polarity  Static Configuration: It stops PWM.  Dynamic Configuration: PWM is running  Auto-Reload and One-Shot Pulse Mode  Dead Zone Generator on two PWM Outputs  Level Interrupt Generation The PWM has two operation modes. They are:  Auto-Reload Mode: In this mode, continuous PWM pulses are generated based on programmed duty cycle and polarity.  One-Shot Pulse Mode: In this mode, only one PWM pulse is generated based on programmed duty cycle and polarity. To control the functionality of PWM, 18 special function registers are provided. The PWM is an AMBA slave module which has programmable outputs and a clock input and the PWM connects to the Advanced Peripheral Bus (APB). These 18 special function registers within PWM are accessed via APB transactions. 11-4 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.3 PWM Operation PWM timer of Exynos 4412 can operate as a general timer and a pulse generator with TOUT signal. 11.3.1 Prescaler and Divider An 8-bit prescaler and 3-bit divider generates these output frequencies: Table 11-1 describes the minimum and maximum resolution based on prescaler and clock divider values. Table 11-1 Minimum and Maximum Resolution Based on Prescaler and Clock Divider Values 4-bit Divider Settings 1/1 (PCLK = 66 MHz) 1/2 (PCLK = 66 MHz) 1/4 (PCLK = 66 MHz) 1/8 (PCLK = 66 MHz) 1/16 PCLK = 66 MHz) Minimum Resolution (Prescaler Value = 1) 0.030 s (33.0 MHz) 0.061 s (16.5 MHz) 0.121 s (8.25 MHz) 0.242 s (4.13 MHz) 0.485 s (2.06 MHz) Maximum Resolution (Prescaler Value = 255) 3.879 s (257.8 kHz) 7.758 s (128.9 kHz) 15.515 s (64.5 kHz) 31.03 s (32.2 kHz) 62.061 s (16.1 kHz) Maximum Interval (TCNTBn = 4294967295) 16659.27s 33318.53s 66637.07s 133274.14s 266548.27s 11-5 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.3.2 Basic Timer Operation Figure 11-3 illustrates the timer operations. start bit=1 timer is started TCNTn=TCMPn auto-reload TCNTn=TCMPn timer is stopped. TCMPn 1 0 TCNTn 3 3 2 1 0 2 1 0 0 TCNTBn=3 TCMPBn=1 manual update=1 auto-reload=1 TCNTBn=2 TCMPBn=0 auto-reload=0 interrupt request interrupt request manual update=0 auto-reload=1 TOUTn command status Figure 11-3 Timer Operations The timer (except the timer channel 4) includes four registers. They are:  TCNTBn  TCNTn  TCMPBn  TCMPn If the timer reaches 0, then TCNTBn and TCMPBn registers are loaded into TCNTn and TCMPn. If TCNTn reaches 0, then the interrupt request occurs if it enables the interrupt (TCNTn and TCMPn are the names of the internal registers. It reads the TCNTn register from the TCNTOn register). To generate interrupt at intervals 3cycle of XpwmTOUTn, set TCNTBn, TCMPBn and TCON register as shown in Figure 11-3. 11-6 Exynos 4412_UM 11 Pulse Width Modulation Timer Steps to generate interrupt: 1. Set TCNTBn = 3 and TCMPBn = 1. 2. Set auto-reload = 1 and manual update = 1. If manual update bit is 1, then it loads TCNTBn and TCMPBn values to TCNTn and TCMPn. 3. Set TCNTBn = 2 and TCMPBn = 0 for the next operation. 4. Set auto-reload = 1 and manual update = 0. If you set manual update = 1 at this time, it changes TCNTn to 2 and it changes TCMP to 0. Therefore, it generates interrupt at interval two-cycle instead of three-cycle. You should set auto-reload = 1 automatically for the next operation. 5. Set start = 1 for starting the operation. Then TCNTn is down counting. If TCNTn is 0, it generates interrupt and if auto-reload is enable, it loads TCNTn 2 (TCNTBn value) and it loads TCMPn 0 (TCMPn value). 6. TCNTn is down counting before it stops. 11-7 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.3.3 Auto-Reload and Double Buffering PWM Timers includes a double buffering feature, which changes the reload value for the next timer operation without stopping the current timer operation. The timer value is written into TCNTBn (Timer Count Buffer register) and the current counter value of the timer is read from TCNTOn (Timer Count Observation register). If TCNTBn is read, the read value does not reflect the current state of the counter but the reload value for the next timer duration. Auto-reload is a copy function that a value of the TCNTBn is copied to the TCNTn when the TCNTn reaches 0. The value written to TCNTBn, is loaded to TCNTn if the TCNTn reaches to 0 and auto-reload is enabled. If the TCNTn is 0 and the auto-reload bit is 0, then TCNTn does not operate further. Figure 11-4 illustrates the example of double buffering feature. Write TCNTBn=100 Start TCNTBn=150 Write TCNTBn=200 auto_reload 150 100 100 200 interrupt If TCNT is 0, interrupt signal is generated and then load the next TCNTB Figure 11-4 Example of Double Buffering Feature 11-8 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.3.4 Timer Operation Example Figure 11-5 illustrates the example of a timer operation. 12 3 4 6 79 10 TOUTn 50 109 110 40 39 20 59 40 60 5 8 11 Figure 11-5 Example of a Timer Operation Steps to use PWM as a timer: 1. 1Enable the auto-reload feature. 2. Set the TCNTBn as 159 (50 + 109) and TCMPBn as 109. 3. Set the manual update bit On and set the manual update bit Off. 4. Set the inverter On/Off bit. The manual update bit sets TCNTn and TCMPn to the value of TCNTBn and TCMPBn. 5. Set TCNTBn and TCMPBn as 79 (40 + 39) and 39. 6. Start Timer: Set the start bit in TCON. 7. If TCNTn and TCMPn have the same value, then it changes the logic level of TOUTn from low to high 8. When TCNTn reaches 0, it generates interrupt request. 9. It automatically reloads TCNTn and TCMPn with TCNTBn and TCMPBn as (79 (40 + 39)) and 39. In the Interrupt Service Routine (ISR), the TCNTBn and TCMPBn are set as 79 (20 + 59) and 59. 10. If TCNTn and TCMPn have the same value, then it changes the logic level of TOUTn from low to high 11. When TCNTn reaches to 0, it generates interrupt request. 12. It automatically reloads TCNTn and TCMPn with TCNTBn, TCMPBn as (79 (20 + 59)) and 59. It disables the auto-reload and interrupt request to stop the timer in the ISR. 13. If TCNTn and TCMPn have similar value, then it changes the logic level of TOUTn from low to high. 14. Even if TCNTn reaches to 0, it does not generate interrupt request. 15. Because auto-reload is disabled, it does not reload TCNTn and stop the timer. 11-9 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.3.5 Initialize Timer (Setting Manual-Up Data and Inverter) You should define the starting value of the TCNTn, because an auto-reload operation of the timer occurs when the down counter reaches to "0" In this case, the starting value should be loaded by setting "1" to the manual update bit of TCON register. 1. Write the initial value into TCNTBn and TCMPBn. 2. Set the manual update bit and clear only manual update bit of the corresponding timer. NOTE: We recommend you to set the inverter On/Off bit (whether inverter is used or not). 3. Set the start bit of the corresponding timer to start the timer. 11.3.6 PWM Figure 11-6 illustrates the example of PWM. 60 50 40 30 30 Write TCMPBn=60 Write TCMPBn=40 Write TCMPBn=30 Write TCMPBn=50 Write TCMPBn=30 Write TCMPBn = next PWM Figure 11-6 Example of PWM Use TCMPBn to implement the PWM feature. TCNTBn determines PWM frequency. A As illustrated in Figure 11-6 TCMPBn determines a PWM value. For a higher PWM value, decrease the TCMPBn value. For a lower PWM value, increase the TCMPBn value. If you enable the output inverter, the increment/decrement can be disabled. Due to the double buffering feature, you should write a counter value for next PWM cycle into the TCMPBn register. 11-10 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.3.7 During Current ISR. (Interrupt Service Routine) Output Level Control Figure 11-7 illustrates the inverter On/Off. Inverter off Inverter on Initial State Period 1 Period 2 Timer stop Figure 11-7 Inverter On/Off Steps to maintain TOUT as high or low when inverter is turned Off: 1. Turn-Off the auto-reload bit. Then, TOUTn goes to high level and it stops the timer after TCNTn reaches to 0. This method is recommended. 2. Stop the timer by clearing the timer start/stop bit to 0. If TCNTn <= TCMPn, the output level is high. If TCNTn  TCMPn, the output level is low. 3. You can invert TOUTn signal by setting "1" to Inverter On/Off bit of TCON register. The inverter removes the additional circuit to adjust the output level. 11-11 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.3.8 Dead Zone Generator Dead Zone Generator feature inserts the time gap between a turn-off and turn-on of two different switching devices. This time gap prohibits the two switching devices turning On simultaneously even for a very short duration. TOUT_0 specifies the PWM output. nTOUT_0 specifies the inversion of the TOUT_0. If you enable the deadzone, the output wave-form of TOUT_0 and nTOUT_0 become TOUT_0_DZ and nTOUT_0_DZ. Dead-zone interval cannot turn on TOUT0_DZ and nTOUT_0_DZ simultaneously. For functional accuracy, it should set the dead zone length smaller than compare counter value. Figure 11-8 illustrates the waveform when it enables Dead Zone feature. TOUT0 nTOUT0 DEADZONE INTERVAL TOUT0_DZ nTOUT0_DZ Figure 11-8 Waveform when a Dead Zone Feature is Enabled 11-12 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.4 I/O Description Signal TOUT_0 TOUT_1 TOUT_2 TOUT_3 I/O Output Output Output Output Description PWMTIMER TOUT[0] PWMTIMER TOUT[1] PWMTIMER TOUT[2] PWMTIMER TOUT[3] Pad XpwmTOUT[0] XpwmTOUT[1] XpwmTOUT[2] XpwmTOUT[3] Type muxed muxed muxed muxed NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals. 11-13 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.5 Register Description 11.5.1 Register Map Summary  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP) Register TCFG0 TCFG1 TCON TCNTB0 TCMPB0 TCNTO0 TCNTB1 TCMPB1 TCNTO1 TCNTB2 TCMPB2 TCNTO2 TCNTB3 TCMPB3 TCNTO3 TCNTB4 TCNTO4 TINT_CSTAT Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 Description Specifies the timer configuration register 0 that configures the two 8-bit prescaler and dead-zone or dead zone length Specifies the timer configuration register 1 that controls five MUX select bit Specifies the timer control register Specifies the timer 0 count buffer register Specifies the timer 0 compare buffer register Specifies the timer 0 count observation register Specifies the timer 1 count buffer register Specifies the timer 1 compare buffer register Specifies the timer 1 count observation register Specifies the timer 2 count buffer register Specifies the timer 2 compare buffer register Specifies the timer 2 count observation register Specifies the timer 3 count buffer register Specifies the timer 3 compare buffer register Specifies the timer 3 count observation register Specifies the timer 4 count buffer register Specifies the timer 4 count observation register Specifies the timer interrupt control and status register Reset Value 0x0000_0101 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 11-14 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.5.1.1 TCFG0  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0000, Reset Value = 0x0000_0101 Name RSVD Dead zone length Prescaler 1 Prescaler 0 Bit [31:24] [23:16] [15:8] [7:0] Type – RW RW RW Description Reserved Bits Dead zone length Prescaler 1 value for Timer 2, 3, and 4 Prescaler 0 value for timer 0 and 1 Timer Input Clock Frequency = PCLK/({prescaler value + 1})/{divider value} {prescaler value} = 1 to 255 {divider value} = 1, 2, 4, 8, 16 Dead zone length = 0 to 254 NOTE: If deadzone length is set as "n", real Dead Zone length is "n + 1" (n = 0 to 254). Reset Value 0x00 0x00 0x01 0x01 11-15 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.5.1.2 TCFG1  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0004, Reset Value = 0x0000_0000 Name RSVD Divider MUX4 Divider MUX3 Divider MUX2 Divider MUX1 Divider MUX0 Bit [31:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type – RW RW RW RW RW Description Reserved Selects Mux input for PWM timer 4 0000 = 1/1 0001 = 1/2 0010 = 1/4 0011 = 1/8 0100 = 1/16 Selects Mux input for PWM timer 3 0000 = 1/1 0001 = 1/2 0010 = 1/4 0011 = 1/8 0100 = 1/16 Selects Mux input for PWM timer 2 0000 = 1/1 0001 = 1/2 0010 = 1/4 0011 = 1/8 0100 = 1/16 Selects Mux input for PWM timer 1 0000 = 1/1 0001 = 1/2 0010 = 1/4 0011 = 1/8 0100 = 1/16 Selects Mux input for PWM timer 0 0000 = 1/1 0001 = 1/2 0010 = 1/4 0011 = 1/8 0100 = 1/16 Reset Value 0x000 0x0 0x0 0x0 0x0 0x0 11-16 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.5.1.3 TCON  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0008, Reset Value = 0x0000_0000 Name RSVD Timer 4 auto reload on/off Timer 4 manual update Timer 4 start/stop Timer 3 auto reload on/off Timer 3 output inverter on/off Timer 3 manual update Timer 3 start/stop Timer 2 auto reload on/off Timer 2 output inverter on/off Timer 2 manual update Timer 2 start/stop Timer 1 auto reload on/off Timer 1 output inverter on/off Timer 1 manual update Timer 1 start/stop Reserved Dead zone enable/disable Timer 0 auto reload on/off Timer 0 output Bit [31:23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7:5] Type – RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW – Description Reserved Bits 0 = One-shot 1 = Interval mode (auto-reload) 0 = No operation 1 = Updates TCNTB4 0 = Stops Timer 4 1 = Starts Timer 4 0 = One-shot 1 = Interval mode(auto-reload) 0 = Inverter Off 1 = TOUT_3 inverter-on 0 = No operation 1 = Updates TCNTB3 0 = Stops Timer 3 1 = Starts Timer 3 0 = One-shot 1 = Interval mode (auto-reload) 0 = Inverter Off 1 = TOUT_2 inverter-on 0 = No operation 1 = Updates TCNTB2,TCMPB2 0 = Stops Timer 2 1 = Starts Timer 2 0 = One-shot 1 = Interval mode (auto-reload) 0 = Inverter Off 1 = TOUT_1 inverter-on 0 = No operation 1 = Updates TCNTB1 andTCMPB1 0 = Stops Timer 1 1 = Starts Timer 1 Reserved Bits [4] RW Enables/Disables Dead zone generator [3] RW 0 = One-shot 1 = Interval mode (auto-reload) [2] RW 0 = Inverter Off Reset Value 0x000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 11-17 Exynos 4412_UM 11 Pulse Width Modulation Timer Name inverter on/off Timer 0 manual update Timer 0 start/stop Bit Type Description 1 = TOUT_0 inverter-on [1] RW 0 = No operation 1 = Updates TCNTB0 andTCMPB0 [0] RW 0 = Stops Timer 0 1 = Starts Timer 0 Reset Value 0x0 0x0 11-18 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.5.1.4 TCNTB0  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x000C, Reset Value = 0x0000_0000 Name Timer 0 count buffer Bit [31:0] Type Description RW Timer 0 Count Buffer register 11.5.1.5 TCMPB0  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0010, Reset Value = 0x0000_0000 Name Timer 0 compare buffer Bit Type Description [31:0] RW Timer 0 Compare Buffer register 11.5.1.6 TCNTO0  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0014, Reset Value = 0x0000_0000 Name Timer 0 count observation Bit Type Description [31:0] R Timer 0 Count Observation register 11.5.1.7 TCNTB1  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0018, Reset Value = 0x0000_0000 Name Timer 1 count buffer Bit Type Description [31:0] RW Timer 1 Count Buffer register Reset Value 0x0000_0000 Reset Value 0x0000_0000 Reset Value 0x0000_0000 Reset Value 0x0000_0000 11-19 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.5.1.8 TCMPB1  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x001C, Reset Value = 0x0000_0000 Name Timer 1 compare buffer Bit [31:0] Type Description RW Timer 1 Compare Buffer register 11.5.1.9 TCNTO1  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0020, Reset Value = 0x0000_0000 Name Timer 1 count observation Bit Type Description [31:0] R Timer 1 Count Observation register 11.5.1.10 TCNTB2  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0024, Reset Value = 0x0000_0000 Name Timer 2 count buffer Bit Type Description [31:0] RW Timer 2 Count Buffer register 11.5.1.11 TCMPB2  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0028, Reset Value = 0x0000_0000 Name Timer 2 compare buffer Bit Type Description [31:0] RW Timer 2 Compare Buffer register Reset Value 0x0000_0000 Reset Value 0x0000_0000 Reset Value 0x0000_0000 Reset Value 0x0000_0000 11-20 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.5.1.12 TCNTO2  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x002C, Reset Value = 0x0000_0000 Name Timer 2 count observation Bit [31:0] Type Description R Timer 2 Count Observation register 11.5.1.13 TCNTB3  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0030, Reset Value = 0x0000_0000 Name Timer 3 count buffer Bit Type Description [31:0] RW Timer 3 Count Buffer register 11.5.1.14 TCMPB3  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0034, Reset Value = 0x0000_0000 Name Timer 3 compare buffer Bit Type Description [31:0] RW Timer 3 Compare Buffer register 11.5.1.15 TCNTO3  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0038, Reset Value = 0x0000_0000 Name Timer 3 count observation Bit Type Description [31:0] R Timer 3 Count Observation register Reset Value 0x0000_0000 Reset Value 0x0000_0000 Reset Value 0x0000_0000 Reset Value 0x0000_0000 11-21 Exynos 4412_UM 11.5.1.16 TCNTB4  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x003C, Reset Value = 0x0000_0000 Name Timer 4 count buffer Bit Type Description [31:0] RW Timer 4 Count Buffer register 11.5.1.17 TCNTO4  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0040, Reset Value = 0x0000_0000 Name Timer 4 count observation Bit Type Description [31:0] R Timer 4 Count Observation register 11 Pulse Width Modulation Timer Reset Value 0x0000_0000 Reset Value 0x0000_0000 11-22 Exynos 4412_UM 11 Pulse Width Modulation Timer 11.5.1.18 TINT_CSTAT  Base Address: 0x139D_0000 (PWM)  Base Address: 0x1216_0000 (PWM_ISP)  Address = Base Address + 0x0044, Reset Value = 0x0000_0000 Name RSVD Timer 4 interrupt status Timer 3 interrupt status Timer 2 interrupt status Timer 1 interrupt status Timer 0 interrupt status Timer 4 interrupt enable Timer 3 interrupt enable Timer 2 interrupt enable Timer 1 interrupt enable Timer 0 interrupt enable Bit [31:10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW RW RW Description Reserved Bits Timer 4 interrupt status bit. It clears by writing "1" on this bit. Timer 3 interrupt status bit. It clears by writing "1" on this bit. Timer 2 interrupt status bit. It clears by writing "1" on this bit. Timer 1 interrupt status bit. It clears by writing "1" on this bit. Timer 0 interrupt status bit. It clears by writing "1" on this bit. Enables timer 4 interrupt 0 = Disables Timer 4 interrupt 1 = Enables Timer 4 interrupt Enables timer 3 interrupt 0 = Disables Timer 3 interrupt 1 = Enables Timer 3 interrupt Enables timer 2 interrupt 0 = Disables Timer 2 interrupt 1 = Enables Timer 2 interrupt Enables timer 1 interrupt 0 = Disables Timer 1 interrupt 1 = Enables Timer 1 interrupt Enables timer 0 interrupt. 0 = Disables Timer 0 interrupt 1 = Enables Timer 0 interrupt Reset Value 0x00000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 11-23 Exynos 4412_UM 12 Watchdog Timer 12 Watchdog Timer 12.1 Overview Watchdog Timer (WDT) in Exynos 4412 is a timing device. You can use this device to resume the controller operation after malfunctioning due to noise and system errors. You can use WDT as a normal 16-bit interval timer to request interrupt service. WDT generates the reset signal. 12.2 Features The features of WDT are:  Supports normal interval timer mode with interrupt request.  Activates internal reset signal if the timer count value reaches 0 (time-out).  Supports level-triggered interrupt mechanism. 12-1 Exynos 4412_UM 12 Watchdog Timer 12.3 Functional Description This section includes:  WDT operation  WTDAT and WTCNT  WDT Start  Consideration of debugging environment 12.3.1 WDT Operation WDT uses PCLK as its source clock. The 8-bit Prescaler prescales the PCLK frequency to generate the corresponding WDT and it divides the resulting frequency again. PCLK 8-bit Prescaler WTCON[15:8] 1/16 1/32 1/64 1/128 MUX WTDAT WTCNT (Down Counter) Interrupt Reset Signal Generator RESET WTCON[4:3] WTCON[2] WTCON[0] Figure 12-1 Watchdog Timer Block Diagram Figure 12-1 illustrates the functional block diagram of WDT. The Watchdog Timer Control (WTCON) specifies the prescaler value and frequency division factor. Valid prescaler values range from 0 to (28 – 1). You can select the frequency division factor as: 16, 32, 64, or 128. Use this equation to calculate the WDT clock frequency and the duration of each timer clock cycle: t_watchdog = 1/(PCLK/(Prescaler value + 1)/Division_factor) 12-2 Exynos 4412_UM 12 Watchdog Timer 12.3.2 WTDAT and WTCNT After you enable the WDT, you cannot reload the value of the Watchdog Timer Data (WTDAT) register automatically into the Watchdog Timer Counter (WTCNT) register. Therefore, you must write an initial value to the WTCN register before WDT starts. 12.3.3 WDT Start To start WDT, set WTCON[0] and WTCON[5] as 1. 12.3.4 Consideration of Debugging Environment WDT should not operate if the Exynos 4412 is in debug mode that uses Embedded In Circuit Debugger (ICE). WDT determines whether CPU core is currently in the debug mode from the CPU core signal (DBGACK signal). After CPU core asserts the DBGACK signal, it does not activate the reset output of WDT as WDT expires. 12-3 Exynos 4412_UM 12.4 Register Description 12.4.1 Register Map Summary  Base Address: 0x1006_0000 Register WTCON WTDAT WTCNT WTCLRINT Offset 0x0000 0x0004 0x0008 0x000C Description Watchdog timer control register Watchdog timer data register Watchdog timer count register Watchdog timer interrupt clear register 12 Watchdog Timer Reset Value 0x0000_8021 0x0000_8000 0x0000_8000 Undefined 12-4 Exynos 4412_UM 12 Watchdog Timer 12.4.1.1 WTCON  Base Address: 0x1006_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_8021 Name RSVD Prescaler value RSVD WDT timer Clock select Interrupt generation RSVD Reset enable/disable Bit [31:16] [15:8] [7:6] [5] [4:3] [2] [1] [0] Type – RW – RW RW RW – RW Description Reserved Prescaler value. The valid range is from 0 to (28 – 1). Reserved These two bits should be 00 in normal operation. Enables or disables WDT bit. 0 = Disables WDT bit 1 = Enables WDT bit Determines the clock division factor. 00 = 16 01 = 32 10 = 64 11 = 128 Enables or disables interrupt bit. 0 = Disables interrupt bit 1 = Enables interrupt bit Reserved. This bit should be 0 in normal operation. Enables or disables WDT output bit for reset signal. 0 = Disables the reset function of the watchdog timer. 1 = Asserts reset signal of the Exynos 4412 at watchdog time-out. Reset Value 0 0x80 00 1 00 0 0 1 The WTCON register:  Allows you to enable/disable the watchdog timer  Selects the clock signal from four different sources  Enables/disables interrupts  Enables/disables the watchdog timer output You can use WDT to restart the Exynos 4412 to recover from malfunction. If you do not want to restart the controller, disable WDT. If you want to use the normal timer that WDT provides, enable the interrupt and disable the WDT. 12-5 Exynos 4412_UM 12 Watchdog Timer 12.4.1.2 WTDAT  Base Address: 0x1006_0000  Address = Base Address + 0x0004, Reset Value = 0x0000_8000 Name RSVD Count reload value Bit [31:16] [15:0] Type – RW Description Reserved WDT count value for reload. Reset Value 0 0x8000 The WTDAT register specifies the time-out duration. You cannot load the content of WTDAT into the timer counter at initial WDT operation. However, by using 0x8000 (initial value) drives the WDT counter first time-out. In this case, WDT counter logic reloads the value of WTDAT automatically into WTCNT. 12.4.1.3 WTCNT  Base Address: 0x1006_0000  Address = Base Address + 0x0008, Reset Value = 0x0000_8000 Name RSVD Count value Bit [31:16] [15:0] Type – RW Description Reserved The current count value of the WDT Reset Value 0 0x8000 The WTCNT register contains the current count values for the WDT during normal operation. WDT counter logic cannot automatically load the content of WTDAT register into the timer count register if it enables the WDT initially. Therefore, you should set the WTCNT register to an initial value before enabling it. 12.4.1.4 WTCLRINT  Base Address: 0x1006_0000  Address = Base Address + 0x000C, Reset Value = Undefined Name Bit Type Description Interrupt clear [31:0] RW Write any value to clear the interrupt Reset Value – You can use the WTCLRINT register to clear the interrupt. Interrupt service routine is responsible to clear the relevant interrupt after the interrupt service is complete. Writing any values on this register clears the interrupt. Reading on this register is not allowed. 12-6 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13 Universal Asynchronous Receiver and Transmitter 13.1 Overview A Universal Asynchronous Receiver and Transmitter (UART) in Exynos 4412 provide four independent channels with asynchronous and serial input/output (I/O) ports for general purpose (Ch0 to 3). It also provides a dedicated channel for communication with Global Positioning System (GPS) (Ch4). All the ports operate either in an interrupt-based or a DMA-based mode. UART generates either an interrupt or a DMA request to transfer data to and from CPU and UART. UART supports bit rates up to 4 Mbps. Each UART channel contains two First In First Outs (FIFOs) to receive and transmit data as in:  256 bytes in Ch0  64 bytes in Ch1 and Ch4  16 bytes in Ch2 and Ch3 UART includes:  Programmable Baud rates  Infrared (IR) transmitter/receiver  One or two stop bit insertion  5-bit, 6-bit, 7-bit, or 8-bit data width and parity checking As shown in Figure 13-1, each UART contains:  Baud-rate generator  Transmitter  Receiver  Control unit The Baud-rate generator uses SCLK_UART. The transmitter and the receiver contain FIFOs and data shifters. The data to be transmitted is written to Tx FIFO, and copied to the transmit shifter. The data is then shifted out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and copied to Rx FIFO from the shifter. 13-1 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.2 Features Features of UART are:  RxD0, TxD0, RxD1, TxD1, RxD2, TxD2, RxD3, and TxD3 with either DMA-based or interrupt-based operation  UART Ch 0, 1, 2, and 3 with IrDA 1.0  UART Ch 0 with 256 byte FIFO, Ch 1 and 4 with 64 byte FIFO, Ch 2 and 3 with 16 byte FIFO  UART Ch 0, 1, 2 with nRTS0, nCTS0, nRTS1, nCTS1, nCTS2, and nRTS2 for Auto Flow Control (AFC)  UART Ch 4 communicates with GPS and it supports AFC  UART supports handshakes transmit/receive. 13-0 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.3 UART Description This section includes UART operations such as:  Data transmission  Data reception  Interrupt generation  Baud-rate generation  Loop-back mode  Infrared modes  AFC Figure 13-1 illustrates the block diagram of UART. Peripheral BUS Transmitter Transmit Buffer Register Transmit FIFO Register (FIFO mode) Transmit Holding Register (Non-FIFO mode) Transmit Shifter TXDn Control Unit Buad-rate Generator Receiver Receive Shifter Clock Source RXDn Receive Buffer Register Receive Holding Register (Non-FIFO mode only) Receive FIFO Register (FIFO mode) In FIFO mode, all bytes of Buffer Register are used as FIFO register. In non-FIFO mode, only 1 byte of Buffer Register is used as Holding register. Figure 13-1 Block Diagram of UART 13-1 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.3.1 Data Transmission The data frame for transmission is programmable. It consists of these bits that are specified by the line control register (ULCONn):  A Start bit  Five to eight data bits  An optional parity bit  One to two stop bits The transmitter also produces a break condition that forces the serial output to logic 0 state for one-frame transmission time. This block transmits the break signals after it completely transmits the present transmission word. After the break signal transmission, the transmitter continuously transmits data to Tx FIFO (Tx holding register, in case of non-FIFO mode). 13.3.2 Data Reception The data frame for reception is also programmable. It consists of a start bit, five to eight data bits, an optional parity bit, and one to two stop bits in the line control register (ULCONn). The receiver detects these errors and each of these errors sets an error flag:  Overrun error: This error indicates that new data has overwritten the old data before the old data was read.  Parity error: This error indicates that the receiver has detected an unexpected parity condition.  Frame error: This error indicates that the received data does not have a valid stop bit.  Break condition: This indicates that the RxDn input is held in the logic 0 state for more than one-frame transmission time. Receive time-out condition occurs when the Rx FIFO is not empty in the FIFO mode and does not receive any data during the frame time specified in UCON. 13-2 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.3.3 AFC UART0 and UART1 in Exynos 4412 support AFC by using nRTS and nCTS signals. To connect UART to a Modem, disable the AFC bit in UMCONn register and control the signal of nRTS by using software. The UART4 supports AFC, but it is dedicated for communication with GPS. In AFC, the nRTS signal depends on the condition of the receiver, whereas the nCTS signals control the operation of transmitter. The transmitter of UART transfers the data to FIFO when nCTS signals are activated In AFC, nCTS signals means that other FIFO of UART is ready to receive data. Before the UART receives data, nRTS has to be activated when Rx FIFO has a spare more than 2-byte and has to be inactivated when its receive FIFO has a spare under 1-byte. In AFC, the nRTS signals means that its RX FIFO is ready to receive data). Figure 13-2 illustrates the UART AFC interface. Transmission case in UART A UART A UART B TxD nCTS RxD nRTS Reception case in UART A UART A UART B RxD nRTS TxD nCTS Figure 13-2 UART AFC Interface 13-3 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.3.4 Example of Non AFC (Controlling nRTS and nCTS by Software) This section includes:  Rx operation with FIFO  Tx operation with FIFO 13.3.4.1 Rx Operation with FIFO 1. Select the transmit mode (either interrupt or DMA mode). 2. Verify the value of Rx FIFO count in the UFSTATn register. When the value is less than 16, set the value of UMCONn[0] to "1" (activate nRTS). However, when the value equal to or larger than 16, set the value to "0" (inactivate nRTS). 3. Repeat the Step 2 to receive next data. 13.3.4.2 Tx Operation with FIFO 1. Select the transmit mode (either interrupt or DMA mode). 2. Verify the value of UMSTATn[0]. When the value is "1" (activate nCTS), Write data to Tx FIFO register. 3. Repeat the Step 2 to send next data. 13.3.5 Trigger Level of Tx/Rx FIFO and DMA Burst Size in DMA Mode DMA transaction starts when Tx/Rx data reaches the trigger level of Tx/Rx FIFO of UFCONn register in DMA mode. A single DMA transaction transfers a data whose size is specified as the DMA burst size of UCONn register. The DMA transactions are repeated until Tx/Rx FIFO count is less than the DMA burst size. Thus, DMA burst size should be less than or equal to the trigger level of Tx/Rx FIFO. In general ensure that the trigger level of Tx/Rx FIFO and DMA burst size matches. 13.3.6 RS-232C Interface To connect UART to the modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD, and nRI signals are required. You can control these signals with general I/O ports by using software as the AFC does not support the RS-232C interface. 13-4 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.3.7 Interrupt/DMA Request Generation Each UART in Exynos 4412 consists of seven status (Tx/Rx/Error) signals, namely:  Overrun error  Parity error  Frame error  Break condition  Receive buffer data ready  Transmit buffer empty  Transmit shifter empty The corresponding UART status register (UTRSTATn/UERSTATn) indicates these conditions. The overrun error, parity error, frame error, and break condition specify the receive error status. When you set receive-error-status-interrupt-enable bit to 1 in the control register (UCONn), the receive error status generates receive-error-status-interrupt. When a receive-error-status-interrupt-request is detected, you can identify the source of interrupt by reading the value of UERSTATn. When you set Receive mode in control register (UCONn) as interrupt request or polling mode, Rx interrupt is generated in this case. When you set Receive mode in control register (UCONn) as interrupt request or polling mode, Rx interrupt is generated in this case. When the receiver transfers data of the receive shifter to the receive FIFO register in FIFO mode, and the number of received data is greater than or equal to the trigger level of Rx FIFO. In non-FIFO mode, transferring the data of receive shifter to receive holding register causes Rx interrupt in the interrupt request and polling modes. When the transmitter transfers data from its transmit FIFO register to transmit shifter and the number of data left in transmit FIFO is less than or equal to the trigger level of Tx FIFO, Tx interrupt is generated This occurs when Transmit mode in control register is selected as Interrupt request or polling mode. In non-FIFO mode, transferring the data from transmit holding register to transmit shifter causes Tx interrupt in the interrupt request and polling mode. Remember that the Tx interrupt is always requested when the number of data in the transmit FIFO is smaller than the trigger level. This means that an interrupt is requested as soon as you enable the Tx interrupt, unless you fill the Tx buffer. Fill the Tx buffer first and then enable the Tx interrupt. The interrupt controllers of Exynos 4412 are of the level-triggered type. Set the interrupt type as "Level" when you program the UART control registers. When you select Receive and Transmit modes in control register as DMA request mode, DMAn request occurs instead of Rx or Tx interrupt in the above situation. 13-5 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter Table 13-1 describes the interrupts in connection with FIFO. Table 13-1 Interrupts in Connection with FIFO Type Rx interrupt Tx interrupt Error interrupt FIFO Mode Generated when Rx FIFO count is greater than or equal to the trigger level of received FIFO. Generated when the number of data in FIFO does not reach the trigger level of Rx FIFO and does not receive any data during the specified time (receive time out) in UCON. Generated when Tx FIFO count is less than or equal to the trigger level of transmit FIFO (trigger level of Tx FIFO). Generated if frame error, parity error, or break signal are detected. Generated if UART receives new data when Rx FIFO is full (overrun error). Non-FIFO Mode Generated by receive holding register whenever receive buffer becomes full. Generated by transmit holding register whenever transmit buffer becomes empty. Generated by all errors. However when another error occurs at the same time, only one interrupt is generated. 13-6 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.3.8 UART Error Status FIFO UART contains the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data among FIFO registers receives an error. An error interrupt is issued only when the data that contains an error is ready to read out. To clear the error status FIFO, you must read out URXHn with an error and UERSTATn. For example, assume that the UART Rx FIFO receives A, B, C, D, and E characters sequentially and the frame error occurs while receiving "B" and the parity error occurs while receiving "D". The actual UART receive error does not generate any error interrupt, since it does not read out the character received with an error. The error interrupt occurs if the character is read out. Time #0 #1 #2 #3 #4 #5 #6 Sequence Flow When no character is read out Receives A, B, C, D, and E After CPU reads out A After CPU reads out B After CPU reads out C After CPU reads out D After CPU reads out E Error Interrupt – – Frame error (in B) interrupt occurs. – Parity error (in D) interrupt occurs. – – Note – – "B" has to be read out. – "D" has to be read out. – – Figure 13-3 illustrates that UART receives the five characters including two errors. Rx FIFO 'E' 'D' 'C' 'B' 'A' URXHn Error Status FIFO break error parity error frame error UERSTATn Error Status Generator Unit Figure 13-3 UART Receives the Five Characters Including Two Errors 13-7 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.3.8.1 Infra-Red Mode The Exynos 4412 UART block supports both infra-red (IR) transmission and reception. You can select the IR mode by setting the IR-mode bit in the UART line control register (ULCONn). Figure 13-4 illustrates how to implement the IR mode. In IR transmit mode, the transmit pulse moves at the rate of 3/16, that is, normal serial transmit rate when the transmit data bit is set to 0. However, in IR receive mode, the receiver must detect the 3/16 pulsed period to recognize a 0 value Refer to frame timing diagrams shown in Figure 13-5 and Figure 13-7 for more information. Figure 13-4 illustrates IrDA function block diagram. TxD IRS UART Block RxD RE IrDA Tx Encoder 0 1 0 1 IrDA Rx Decoder TxD RxD Figure 13-4 IrDA Function Block Diagram Figure 13-5 illustrates the serial I/O frame timing diagram (Normal UART) Start Bit SIO Frame Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Figure 13-5 Serial I/O Frame Timing Diagram (Normal UART) 13-8 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter Figure 13-6 illustrates the infra-red transmit mode frame timing diagram. Start Bit IR Transmit Frame Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Bit Time Pulse Width = 3/16 Bit Frame Figure 13-6 Infra-Red Transmit Mode Frame Timing Diagram Figure 13-7 illustrates the infra-red receive mode frame timing diagram. Start Bit IR Receiv e Frame Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Figure 13-7 Infra-Red Receive Mode Frame Timing Diagram 13-9 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.4 UART Input Clock Description Figure 13-8 illustrates the input clock diagram for UART. System Controller XXTI XusbXTI SCLK_HDMI27M SCLK_USBPHY0 SCLK_USBPHY1 SCLK_HDMIPHY SCLKMPLL SCLKEPLL SCLKVPLL UART MUXUART0~4 DIVUART0~4 MOUTUART0~3 (1~16) SCLK UART UCLK Generator UCLK UBRDIVn UFRACVALn Figure 13-8 Input Clock Diagram for UART Exynos 4412 provides UART with a variety of clocks. Figure 13-8 illustrates that UART uses SCLK_UART clock, which is from clock controller. You can also select SCLK_UART from various clock sources. Refer to Chapter 7, Clock Controller, for more information. 13-10 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.5 I/O Description Signal UART_0_RXD UART_0_TXD UART_0_CTSn UART_0_RTSn UART_1_RXD UART_1_TXD UART_1_CTSn UART_1_RTSn UART_2_RXD UART_2_TXD UART_2_CTSn UART_2_RTSn UART_3_RXD UART_3_TXD I/O Input Output Input Output Input Output Input Output Input Output Input Output Input Output Description Receives data for UART0 Transmits data for UART0 Clears to send (active low) for UART0 Requests to send (active low) for UART0 Receives data for UART1 Transmits data for UART1 Clears to send (active low) for UART1 Requests to send (active low) for UART1 Receives data for UART2 Transmits data for UART2 Clears to send (active low) for UART2 Requests to send (active low) for UART2 Receives data for UART3 Transmits data for UART3 Pad XuRXD_0 XuTXD_0 XuCTSn_0 XuRTSn_0 XuRXD_1 XuTXD_1 XuCTSn_1 XuRTSn_1 XuRXD_2 XuTXD_2 XuCTSn_2 XuRTSn_2 XuRXD_3 XuTXD_3 Type muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed NOTE: 1. Type filed indicates whether the signal connects to the dedicated pad or muliplexed signal pad s. UART shares external pads with IrDA. To use these pads, set GPIO before the start of UART Refer to Chapter 6, GPIO, for more information. 2. UART4 has no I/O ports. It communicates with the internal GPS module. 13-11 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6 Register Description 13.6.1 Register Map Summary  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000 Register ULCONn UCONn UFCONn UMCONn UTRSTATn UERSTATn UFSTATn UMSTATn UTXHn URXHn UBRDIVn UFRACVALn UINTPn UINTSPn UINTMn Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 Description Specifies line control Specifies control Specifies FIFO control Specifies modem control Specifies Tx/Rx status Specifies Rx error status Specifies FIFO status Specifies modem status Specifies transmit buffer Specifies receive buffer Specifies baud rate divisor Specifies divisor fractional value Specifies interrupt pending Specifies interrupt source pending Specifies interrupt mask Reset Value 0x0000_0000 0x0000_3000 0x0000_0000 0x0000_0000 0x0000_0006 0x0000_0000 0x0000_0000 0x0000_0000 Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 13-12 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.1 ULCONn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_0000 Name RSVD Infrared Mode Bit [31:7] [6] Parity Mode [5:3] Number of Stop Bit [2] Word Length [1:0] Type – RW RW RW RW Description Reserved Determines whether to use the infra-red mode. 0 = Normal mode operation 1 = Infra-red Tx/Rx mode Specifies the type of parity that UART generates and checks during UART transmit and receive operation. 0xx = No parity 100 = Odd parity 101 = Even parity 110 = Parity forced/ checked as 1 111 = Parity forced/ checked as 0 Specifies how many stop bits UART uses to signal end-offrame signal. 0 = One stop bit per frame 1 = Two stop bit per frame Indicates the number of data bits UART transmits or receives per frame. 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits Reset Value 0 0 0 0 13-13 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.2 UCONn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0004, Reset Value = 0x0000_0000 Name RSVD RSVD Tx DMA Burst Size RSVD Rx DMA Burst Size Rx Timeout Interrupt Interval Rx Time-out with empty Rx FIFO (4) Bit [31:24] [23] [22:20] [19] [18:16] [15:12] [11] Type – WO RW WO RW RW R/W Description Reserved Reserved Tx DMA Burst Size It is the data transfer size of one DMA transaction. Tx DMA request triggers the DMA transaction. You must program the DMA program to transfer the same data size as this is the value for a single Tx DMA request. 000 = 1 byte (Single) 001 = 4 bytes 010 = 8 bytes 011 = 16 bytes 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved Reserved Rx DMA Burst Size It is the data transfer size of one DMA transaction. Rx DMA request triggers the DMA transaction. You must program the DMA program to transfer the same data size as this is the value for a single Rx DMA request. 000 = 1 byte (Single) 001 = 4 bytes 010 = 8 bytes 011 = 16 bytes 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved Rx Timeout Interrupt Interval Rx interrupt occurs if UART receives no data during 8  (N + 1) frame time. The default value of this field is 3. It means that the timeout interval is 32 frame time. Enables Rx time-out feature when Rx FIFO counter is 0. This bit is valid only when UCONn[7] is 1. 0 = Disables Rx time-out feature when Rx FIFO is empty. Reset Value 0 0 0 0 0 0x3 0 13-14 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter Name Rx Time-out DMA suspend enable Tx Interrupt Type Rx Interrupt Type Rx Time Out Enable Rx Error Status Interrupt Enable Loop-back Mode Send Break Signal Transmit Mode Receive Mode Bit Type Description 1 = Enables Rx time-out feature when Rx FIFO is empty. Reset Value Enables the suspension of Rx DMA FSM when Rx Time-out occurs. [10] R/W 0 0 = Disables suspension of Rx DMA FSM 1 = Enables suspension of Rx DMA FSM Interrupt request type. (2) 0 = Pulse (UART requests interrupt when the Tx buffer is empty in the non-FIFO mode or when it reaches the trigger [9] RW level of Tx FIFO in the FIFO mode.) 0 1 = Level (Interrupt is requested when Tx buffer is empty in the non-FIFO mode or when it reaches the trigger level of Tx FIFO in the FIFO mode.) Interrupt request type. (2) 0 = Pulse (UART requests interrupt when instant Rx buffer receives data in the non-FIFO mode or when it reaches the [8] RW trigger level of Rx FIFO in the FIFO mode.) 0 1 = Level (UART requests interrupt when Rx buffer receives data in the non-FIFO mode or when it reaches the trigger level of Rx FIFO in the FIFO mode.) Enables/disables Rx time-out interrupts when you enable UART FIFO. The interrupt is a receive interrupt. [7] RW 0 0 = Disables 1 = Enables Enables the UART to generate an interrupt upon an exception, such as a break, frame error, parity error, or [6] RW overrun error during a receive operation. 0 0 = Does not generate receive error status interrupt. 1 = Generates receive error status interrupt. To set this bit to 1 triggers the UART to enter the loop-back mode. This mode is for test purposes only. [5] RW 0 0 = Normal operation 1 = Loop-back mode To set this bit to 1 triggers UART to send a break during 1 frame time. This bit is automatically cleared after sending [4] RWX the break signal. 0 0 = Normal transmit 1 = Sends the break signal Determines which function is able to Write Tx data to the UART transmit buffer. [3:2] RW 00 = Disables 00 01 = Interrupt request or polling mode 10 = DMA mode 11 = Reserved Determines which function is able to Read data from UART [1:0] RW receive buffer. 00 00 = Disables 13-15 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter Name Bit Type Description 01 = Interrupt request or polling mode 10 = DMA mode 11 = Reserved Reset Value NOTE: 1. DIV_VAL = UBRDIVn + UFRACVAL/16. Refer to 13.6.1.11 UBRDIVn and 13.6.1.12 UFRACVALn for more information. 2. Exynos 4412 uses a level-triggered interrupt controller. Therefore, you must set these bits to 1 for every transfer. 3. If UART does not reach the trigger level of FIFO and does not receive data during the time specified at the "Rx Timeout Interrupt Interval" field in DMA receive mode with FIFO, UART generates the Rx interrupt (receive time out). Ensure to verify the FIFO status and read out the rest. 4. Both UCONn[11] and UCONn[7] should be set to 1 if you want to enable Rx time-out feature when Rx FIFO counter is set to 0. 13-16 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.3 UFCONn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0008, Reset Value = 0x0000_0000 Name RSVD Tx FIFO Trigger Level RSVD Rx FIFO Trigger Level Bit [31:11] [10:8] [7] [6:4] Type – RW – RW Description Reserved Determines the trigger level of Tx FIFO. When data count of Tx FIFO is less than or equal to the trigger level, Tx interrupt occurs. [Channel 0] 000 = 0 byte 001 = 32 bytes 010 = 64 bytes 011 = 96 bytes 100 = 128 bytes 101 = 160 bytes 110 = 192 bytes 111 = 224 bytes [Channel 1, 4] 000 = 0 byte 001 = 8 bytes 010 = 16 bytes 011 = 24 bytes 100 = 32 bytes 101 = 40 bytes 110 = 48 bytes 111 = 56 bytes [Channel 2, 3] 000 = 0 byte 001 = 2 bytes 010 = 4 bytes 011 = 6 bytes 100 = 8 bytes 101 = 10 bytes 110 = 12 bytes 111 = 14 bytes Reserved Determines the trigger level of Rx FIFO. When data count of Rx FIFO is more than or equal to the trigger level, Rx interrupt occurs. [Channel 0] 000 = 32 byte 001 = 64 bytes Reset Value 0 000 0 000 13-17 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter Name Bit Type Description 010 = 96 bytes 011 = 128 bytes 100 = 160 bytes 101 = 192 bytes 110 = 224 bytes 111 = 256 bytes [Channel 1, 4] 000 = 8 byte 001 = 16 bytes 010 = 24 bytes 011 = 32 bytes 100 = 40 bytes 101 = 48 bytes 110 = 56 bytes 111 = 64 bytes [Channel 2, 3] 000 = 2 byte 001 = 4 bytes 010 = 6 bytes 011 = 8 bytes 100 = 10 bytes 101 = 12 bytes 110 = 14 bytes 111 = 16 bytes RSVD [3] – Reserved Tx FIFO Reset Automatically clears after resetting FIFO [2] S 0 = Normal 1 = Tx FIFO reset Rx FIFO Reset Automatically clears after resetting FIFO [1] S 0 = Normal 1 = Rx FIFO reset FIFO Enable [0] RW 0 = Disables 1 = Enables Reset Value 0 0 0 0 NOTE: When UART does not reach the trigger level of FIFO, it does not receive data during the specified timeout interval in DMA receive mode with FIFO. It generates the Rx interrupt (receive time out). Ensure to verify the FIFO status and read out the rest. 13-18 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.4 UMCONn (n = 0, 1, 2, 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x000C, Reset Value = 0x0000_0000 Name RSVD RTS trigger Level Auto Flow Control (AFC) Modem Interrupt Enable RSVD Bit [31:8] [7:5] [4] [3] [2:1] Type – RW RW RW – Description Reserved Determines the trigger level of Rx FIFO to control nRTS signal. When it enables AFC bit and Rx FIFO have bytes that are greater than or equal to the trigger level, it deactivates nRTS signal. [Channel 0] 000 = 255 bytes 001 = 224 bytes 010 = 192 bytes 011 = 160 bytes 100 = 128 bytes 101 = 96 bytes 110 = 64 bytes 111 = 32 bytes [Channel 1, 4] 000 = 63 bytes 001 = 56 bytes 010 = 48 bytes 011 = 40 bytes 100 = 32 bytes 101 = 24 bytes 110 = 16 bytes 111 = 8 bytes [Channel 2] 000 = 15 bytes 001 = 14 bytes 010 = 12 bytes 011 = 10 bytes 100 = 8 bytes 101 = 6 bytes 110 = 4 bytes 111 = 2 bytes 0 = Disables 1 = Enables 0 = Disables 1 = Enables Reserved (These bits must be 0) Reset Value 0 0 0 0 0 13-19 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter Name Request to Send Bit Type Description Reset Value If AFC bit is enabled, this value will be ignored. In this case, the Exynos 4412 controls nRTS signals automatically. [0] RW If AFC bit is disabled, the software must control nRTS signal. 0 0 = "H" level (inactivate nRTS) 1 = "L" level (activate nRTS) NOTE: 1. UART 3 does not support AFC function because the Exynos 4412 has no nRTS3 and nCTS3. 2. In AFC mode, set the trigger level of Rx FIFO lower than the trigger level of RTS because transmitter stops data transfer when it deactivates the nRST signal. 13-20 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.5 UTRSTATn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0010, Reset Value = 0x0000_0000 Name RSVD RX FIFO count in RX time-out status TX DMA FSM State RX DMA FSM State RSVD RX Time-out status/Clear1 Bit [31:24] [23:16] [15:12] [11:8] [7:4] [3] Type – R R R – RWX Reserved Description Capture value of Rx FIFO counter when Rx time-out occurs Current State of Tx DMA FSM 0x0 = IDLE 0x1 = Burst Request 0x2 = Burst Acknowledgement 0x3 = Burst Next (intermediate state for next request) 0x4 = Single Request 0x5 = Single Acknowledgement 0x6 = Single Next (intermediate state for next request) 0x7 = Last Burst Request 0x8 = Last Burst Acknowledgement 0x9 = Last Single Request 0x10 = Last Single Acknowledgement Current State of Rx DMA FSM 0x0 = IDLE 0x1 = Burst Request 0x2 = Burst Acknowledgement 0x3 = Burst Next (intermediate state for next request) 0x4 = Single Request 0x5 = Single Acknowledgement 0x6 = Single Next (intermediate state for next request) 0x7 = Last Burst Request 0x8 = Last Burst Acknowledgement 0x9 = Last Single Request 0x10 = Last Single Acknowledgement Reserved RX Time-out status when read. 0 = Rx Time out did not occur 1 = Rx Time out. Clears Rx Time-out status when write. 0 = No operation 1 = Clears Rx Time-out status NOTE: When UCONn[10] is set to 1. writing 1 to this bit resumes Rx DMA FSM that was suspended when Rx time-out Reset Value 0 0x00 0x0 0x0 0 0 13-21 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter Name Bit Type Description Reset Value occurred. This bit is automatically set to 1 when the transmit buffer has Transmitter empty [2] no valid data to transmit, and the transmit shift is empty. R 0 = Not empty 1 1 = Transmitter ( includes transmit buffer and shifter) empty This bit is automatically set to 1 when transmit buffer is empty. 0 = Buffer is not empty 1 = Buffer is empty (in non-FIFO mode, it requests interrupt or Transmit buffer empty [1] R DMA). 1 In FIFO mode, it requests interrupt or DMA, when the trigger level of Tx FIFO is set to 00 (Empty). When UART uses FIFO, check for Tx FIFO Count bits and Tx FIFO Full bit in UFSTAT instead of this bit. It automatically sets this bit to 1 when receive buffer contains valid data, which is received over the RXDn port. Receive 0 = Buffer is empty buffer data [0] R 1 = Buffer has a received data 0 ready (In Non-FIFO mode, it requests interrupt or DMA ) When UART uses the FIFO, check for Rx FIFO Count bits and Rx FIFO Full bit in UFSTAT instead of this bit. 13-22 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.6 UERSTATn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0014, Reset Value = 0x0000_0000 Name RSVD Break Detect Frame Error Parity Error Overrun Error Bit [31:4] [3] [2] [1] [0] Type – R R R R Description Reserved It automatically sets this bit to 1 to indicate that a break signal has been received. 0 = No break signal is received 1 = Break signal is received (Interrupt is requested.) It automatically sets this bit to 1 when a frame error occurs during the receive operation. 0 = No frame error occurs during the receive operation 1 = Frame error occurs (Interrupt is requested.) during the receive operation It automatically sets this bit to 1 when a parity error occurs during the receive operation. 0 = No parity error occurs during receive the receive operation 1 = Parity error occurs (Interrupt is requested.) during the receive operation It automatically sets this bit to 1 automatically if an overrun error occurs during the receive operation. 0 = No overrun error occurs during the receive operation 1 = Overrun error occurs (Interrupt is requested.) during the receive operation Reset Value 0 0 0 0 0 NOTE: It clears these bits (UERSATn[3:0]) to 0 when UART error status is Read. 13-23 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.7 UFSTATn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0018, Reset Value = 0x0000_0000 Name RSVD Tx FIFO Full Tx FIFO Count RSVD Rx FIFO Error Rx FIFO Full Rx FIFO Count Bit [31:25] [24] [23:16] [15:10] [9] [8] [7:0] Type – R R – R R R Description Reserved It automatically sets this bit to 1 when the transmitted FIFO is full during transmit operation 0 = Not full 1 = Full Number of data in Tx FIFO NOTE: This field is set to 0 when Tx FIFO is full. Reserved This bit is set to 1 when Rx FIFO contains invalid data that results from frame error, parity error, or break signal. It automatically sets this bit to 1 when the received FIFO is full during receive operation 0 = Not full 1 = Full Number of data in Rx FIFO NOTE: This field is set to 0 when Rx FIFO is full. Reset Value 0 0 0 0 0 0 0 13-24 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.8 UMSTATn (n = 0, 1, 2, 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x001C, Reset Value = 0x0000_0000 Name RSVD Delta CTS RSVD Clear to Send Bit [31:5] [4] [3:1] [0] Type – R – R Description Reserved This bit indicates that the nCTS input to the Exynos 4412 has changed its state since the last time CPU read it. Refer to Figure 13-9 for more information. 0 = Has not changed 1 = Has changed NOTE: In UMSTAT4, reset value of this bit is undefined. It depends on the GPIO configuration of GPS. Reserved 0 = Does not activates CTS signal (nCTS pin is high) 1 = Activates CTS signal (nCTS pin is low) NOTE: In UMSTAT4, reset value of this bit is undefined. It depends on the GPIO configuration of GPS. Reset Value 0 0 0 Figure 13-9 illustrates the nCTS and delta Clear to Send (CTS) timing diagram. nCTS Delta CTS Read_UMSTAT Modem_interrupt Figure 13-9 nCTS and Delta CTS Timing Diagram 13-25 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.9 UTXHn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0020, Reset Value = 0x0000_0000 Name RSVD UTXHn Bit [31:8] [7:0] Type – RWX Description Reserved Transmits data for UARTn Reset Value – – 13.6.1.10 URXHn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0024, Reset Value = 0x0000_0000 Name RSVD URXHn Bit [31:8] [7:0] Type – R Description Reserved Receives data for UARTn Reset Value 0 0x00 NOTE: When an overrun error occurs, CPU must Read URXHn. If not, the next received data makes an overrun error, even though it clears the overrun bit of UERSTATn. 13.6.1.11 UBRDIVn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0028, Reset Value = 0x0000_0000 Name RSVD UBRDIVn Bit [31:16] [15:0] Type – RW Description Reserved Baud-rate division value NOTE: When UBRDIV value is set to 0, UFRACVAL value does not affect UART Baud rate. Reset Value 0 0x0000 13-26 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.12 UFRACVALn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x002C, Reset Value = 0x0000_0000 Name RSVD UFRACVALn Bit [31:4] [3:0] Type – RW Description Reserved Determines the fractional part of Baud-rate divisor. Reset Value 0 0x0 1. UART Baud-Rate Configuration You can use the value stored in the Baud-rate divisor (UBRDIVn) and divisor fractional value (UFRACVALn) to determine the serial Tx/Rx clock rate (Baud rate) as: DIV_VAL = UBRDIVn + UFRACVALn/16 or DIV_VAL = (SCLK_UART/(bps  16))  1 Where, the divisor should be from 1 to (216 – 1). By using UFRACVALn, you can generate the Baud rate more accurately. For example, if the Baud rate is 115200 bps and SCLK_UART is 40 MHz, UBRDIVn and UFRACVALn are: DIV_VAL = (40000000/(115200  16)) – 1 = 21.7 – 1 = 20.7 UBRDIVn = 20 (integer part of DIV_VAL) UFRACVALn/16 = 0.7 Therefore, UFRACVALn = 11 2. Baud-Rate Error Tolerance UART Frame error should be less than 1.87 % (3/160) tUPCLK = (UBRDIVn + 1 + UFRACVAL/16)  16  1Frame/SCLK_UART tUPCLK = Real UART Clock tEXTUARTCLK = 1Frame/baud-rate tEXTUARTCLK = Ideal UART Clock UART error = (tUPCLK  tEXTUARTCLK)/tEXTUARTCLK  100 % * 1Frame = start bit + data bit + parity bit + stop bit. 3. UART Clock and PCLK Relation There is a constraint on the ratio of clock frequencies for PCLK to UARTCLK. The frequency of UARTCLK must be no more than 5.5/3 times faster than the frequency of PCLK: FUARTCLK  5.5/3  FPCLK 13-27 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter FUARTCLK = baudrate  16 This allows sufficient time to Write the received data to the receive FIFO. 13-28 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.13 UINTPn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0030, Reset Value = 0x0000_0000 Name RSVD MODEM TXD ERROR RXD Bit [31:4] [3] [2] [1] [0] Type – S S S S Description Reserved Generates modem interrupt. Generates transmit interrupt. Generates error interrupt. Generates receive interrupt. Reset Value 0 0 0 0 0 Interrupt pending contains the information of the generated interrupts. If one of the 4 bits is logical high ("1"), each UART channel generates interrupt. NOTE: You must clear this in the interrupt service routine after clearing interrupt pending in Interrupt Controller (INTC). Clear specific bits of UINTP by writing 1's to the bits that you want to clear. 13.6.1.14 UINTSPn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0034, Reset Value = 0x0000_0000 Name RSVD MODEM TXD ERROR RXD Bit [31:4] [3] [2] [1] [0] Type – S S S S Description Reserved Generates modem interrupt. Generates transmit interrupt. Generates error interrupt. Generates receive interrupt. Reset Value 0 0 0 0 0 NOTE: Interrupt Source Pending contains the information of the generated interrupt regardless of the value of Interrupt Mask. 13-29 Exynos 4412_UM 13 Universal Asynchronous Receiver and Transmitter 13.6.1.15 UINTMn (n = 0 to 4)  Base Address: 0x1380_0000  Base Address: 0x1381_0000  Base Address: 0x1382_0000  Base Address: 0x1383_0000  Base Address: 0x1384_0000  Address = Base Address + 0x0038, Reset Value = 0x0000_0000 Name RSVD MODEM TXD ERROR RXD Bit [31:4] [3] [2] [1] [0] Type – RW RW RW RW Description Reserved Masks modem interrupt. Masks transmit interrupt. Masks error interrupt. Masks receive interrupt. Reset Value 0 0 0 0 0 Figure 13-10 illustrates the block diagram of UINTSP, UINTP, and UINTM. UART_INT(UART interrupt) UINTM UINTSP UINTP Figure 13-10 Block Diagram of UINTSP, UINTP, and UINTM Interrupt mask contains the information about masked interrupt sources. When a specific bit is set to 1, UART does not generate interrupt request signal to the Interrupt Controller even though it generates corresponding interrupt. NOTE: In such cases, the corresponding bit of UINTSPn is set to 1. When the mask bit is set to 0, CPU services the interrupt requests from the corresponding interrupt source. 13-30 Exynos 4412_UM 14 Inter-Integrated Circuit 14 Inter-Integrated Circuit 14.1 Overview The Exynos 4412 Reduced Instruction Set Computer (RISC) microprocessor supports four multi-master InterIntegrated Circuit (I2C) bus serial interfaces. To transmit information between bus masters and peripheral devices, which are connected to the I2C bus, a dedicated Serial Data Line (SDA) and Serial Clock Line (SCL) is used. Both SDA and SCL lines are bi-directional. In multi-master I2C-bus mode, multiple Exynos 4412 RISC microprocessors either receive or transmit serial data to or from slave devices. The master Exynos 4412 initiates and terminates a data transfer over the I2C bus. The I2C bus in the Exynos4412 uses a standard I2C bus arbitration procedure to realize multi-master and multi-slave transfer. To control multi-master I2C-bus operations, you must write values to these registers:  Multi-master I2C-bus control register – I2CCON  Multi-master I2C-bus control/status register – I2CSTAT  Multi-master I2C-bus Tx/Rx data shift register – I2CDS  Multi-master I2C-bus address register – I2CADD If the I2C-bus is idle, both SDA and SCL lines should be at High level. A High-to-Low transition of SDA initiates a Start condition. A Low-to-High transition of SDA initiates a Stop condition, while SCL remains steady at High level. The master device always generates Start and Stop conditions. Front 7 bits address value in the data byte is transferred through SDA line after the start condition has been initiated. This address value determines the slave device which the bus master device has selected. The 8th bit determines the direction of the transfer (Read or Write). Every data byte put on the SDA line should be 8 bits in total. There is no limit either to send or receive bytes during the bus transfer operation. I2C master and slave devices always send the data from the Most Significant Bit (MSB) first, and then acknowledge (ACK) bit immediately follows every byte. 14-1 Exynos 4412_UM 14 Inter-Integrated Circuit 14.2 Features Features of I2C bus interface are:  9 channels multi-master, Slave I2C bus interfaces (8 channels for general purpose, 1 channel dedicated for High Definition Multimedia Interface (HDMI))  7-bit addressing mode  Serial, 8-bit oriented, and bi-directional data transfer  Supports up to 100 kbit/s in the Standard mode  Supports up to 400 kbit/s in the Fast mode.  Supports master transmit, master receive, slave transmit, and slave receive operation  Supports interrupt or polling events 14.3 Functional Description 14.3.1 Block Diagram Figure 14-1 illustrates the block diagram of I2C bus. SCL PCLK I2C-Bus Control Logic I2 CCON I2 CSTAT 4-bit Prescaler Address Register Comparator Shift Register Shift Register (I2CDS) Data Bus Figure 14-1 I2C-Bus Block Diagram SDA 14-2 Exynos 4412_UM 14 Inter-Integrated Circuit 14.4 I2C-Bus Interface Operation The four operation modes of the Exynos 4412 I2C-bus interface are:  Master Transmitter Mode:  Master Receive Mode  Slave Transmitter Mode  Slave Receive Mode The functional relationships among these operating modes are described in these sections:  Start and Stop conditions  Data transfer format  ACK signal transmission  Read-Write operation  Bus arbitration procedures  Abort conditions  Configuring IIC-bus 14-3 Exynos 4412_UM 14 Inter-Integrated Circuit 14.4.1 Start and Stop Conditions When the I2C-bus interface is inactive, it is usually in Slave mode. Alternatively, the interface should be in Slave mode before detecting a Start condition on the SDA line (a Start condition is initiated with a High-to-Low transition of the SDA line, when the clock signal of SCL is High). When controller changes the interface state to mastermode, SDA line initiates data transfer and generates SCL signal. A Start condition transfers 1-byte serial data through SDA line, and a Stop condition terminates the data transfer. A Stop condition is a Low-to-High transition of the SDA line, while SCL is High. The master generates Start and Stop conditions. I2C bus goes into the busy state when a master or slave device generates a start condition. Alternatively, a Stop condition makes the I2C bus idle state. When a master initiates a Start condition, it should send a slave address to notify the slave device. 1 byte of address field includes a 7-bit address and 1-bit transfer direction indicator, which shows Write or Read. When bit 8 is 0, it indicates a Write operation (Transmit Operation); when bit 8 is 1, it indicates a request for data Read (Receive Operation). The master transmits Stop condition to complete the transfer operation. If the master wants to continue the data transmission to the bus, it should generate another Start condition and a slave address. In this manner, there can be various formats of the read-write operation. Figure 14-2 illustrates the Start and Stop condition. SDA SDA SCL SCL Start Condition Stop Condition Figure 14-2 Start and Stop Condition 14-4 Exynos 4412_UM 14 Inter-Integrated Circuit 14.4.2 Data Transfer Format Every byte placed on the SDA line should be 8 bits in length. There is no limit to transmit bytes per transfer. The first byte that follows a Start condition should have the address field. When the I2C-bus is operating in master mode, master transmits the address field. An ACK bit follows each byte. The I2C controller sends first the MSB of the data and address byte to the SDA line. Figure 14-3 illustrates the I2C-bus interface data format. Write Mode Format with 7-bit Addresses S Slave Address 7bits R/W A DATA(1Byte) AP "0" (W rite) Data Transferred (Data + Acknowledge ) Read Mode Format with 7-bit Addresses S Slave Address 7 bits R/W A DATA AP "1" (Read ) Data Transferred (Data + Acknowledge ) NOTES: 1. S: Start , rS: Repeat Start , P: Stop, A: Acknowledge 2. : From Master to Slave, : From Slave to Master Figure 14-3 I2C-Bus Interface Data Format Figure 14-4 illustrates the data transfer on the I2C-bus. SDA SCL S MSB Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver 1 2 7 8 9 Byte Complete, Interrupt within Receiver ACK 1 2 9 Clock Line Held Low by receiver and/or transmitter Figure 14-4 Data Transfer on the I2C-Bus 14-5 Exynos 4412_UM 14 Inter-Integrated Circuit 14.4.3 ACK Signal Transmission To complete a 1-byte transfer operation, the receiver sends an ACK bit to the transmitter. The ACK pulse appears at the ninth clock of the SCL line. The I2C master device generates eight clock cycles to transmit or receive 1 byte data. The master generates clock pulse that is required to transmit the ACK bit. When the transmitter receives ACK clock pulse, it sets the SDA line to High to release the SDA line. The receiver drives the SDA line Low during the ACK clock pulse to keep the SDA Low. This happens during the High period of the ninth SCL pulse. The software (I2CSTAT) enables or disables ACK bit transmit function. However, the ACK pulse on the ninth clock of SCL should complete the 1-byte data transfer operation. Figure 14-5 illustrates the acknowledgement on the I2C-bus. Clock to Output Data Output by Transmitter Data Output by Receiver SCL from Master S Start Condition 1 2 7 8 9 Clock Pulse for Acknowledgment Figure 14-5 Acknowledgement on the I2C-Bus 14-6 Exynos 4412_UM 14 Inter-Integrated Circuit 14.4.4 Read-Write Operation When the I2C controller transmits data in transmitter mode, the I2C-bus interface waits until I2C-bus Data Shift (I2CDS) register receives the new data. Before you write new data to the register, the SCL line is held Low. The I2C controller releases the SCL line after you write the data. Exynos 4412 holds the interrupt to identify the completion of current data transfer. After the CPU receives the interrupt request, it writes new data to the I2CDS register again. When the I2C controller receives data in receive mode, the I2C-bus interface waits until I2CDS register is Read. Before you read out the new data, the SCL line is held Low. The I2C controller releases the SCL line after you read the data. Exynos 4412 holds the interrupt to identify the completion of new data reception. After the CPU receives the interrupt request, it reads the data from the I2CDS register. 14.4.5 Bus Arbitration Procedures Arbitration occurs on the SDA line to prevent the conflict on the bus between two masters. If a master with a SDA High level detects other master with a SDA active Low level, it does not initiate a data transfer. This is because the current level on the bus is not corresponding to initiate a data transfer. The arbitration procedure extends until the SDA line turns High. When two or more masters assert the SDA line Low simultaneously, each master evaluates whether it has the mastership or not. For the purpose of evaluation, each master detects the address bits. While each master generates the Slave address, it detects the address bit on the SDA line. This is because the SDA line becomes Low instead of High. Let us assume that one master generates a Low as first address bit, while the other master is maintaining High. In such case, both masters detect Low on the bus. This is because the Low status is superior to the High status in power. When this happens, the Low (as the first bit of address) that generates master, gets the mastership while the High (as the first bit of address) that generates master, withdraws the mastership. When both masters generate Low as the first bit of address, there is arbitration for the second address bit again. This arbitration continues till the end of last address bit. 14.4.6 Abort Conditions When a Slave receiver cannot acknowledge the confirmation of the slave address, it holds the level of the SDA line High. In this case, the master generates a Stop condition and cancels the transfer. When a master receiver is involved in the aborted transfer, it signals the end of Slave transmit operation by canceling the generation of an ACK. This happens after the Master receives the last data byte from the Slave. The Slave transmitter releases the SDA to enable a master to generate a Stop condition. 14.4.7 Configuring I2C-Bus To control the frequency of SCL, you should write the 4-bit prescaler value in the I2CCON register. The I2C-bus interface address is stored in the I2C-bus address (I2CADD) register. By default, the I2C-bus interface address has an unknown value. 14-7 Exynos 4412_UM 14 Inter-Integrated Circuit 14.4.8 Flowcharts of Operations in Each Mode Before you execute any I2C Tx/Rx operations: 1. If required, Write own Slave address on I2CADD register. 2. Set I2CCON register: a) Enable interrupt. b) Define SCL period. 3. Set I2CSTAT to enable Serial Output. Figure 14-6 illustrates the operations for Master/Transmitter mode. START Master Tx mode has been configured. Write slave address to I2CDS. Write 0xF0 (M/T Start) to I2CSTAT. The data of the I2CDS is transmitted. After ACK period interrupt is pending. Stop? Y N Write new data transmitted to I2CDS. Clear pending bit to resume. The data of the I2CDS is shifted to SDA. Write 0xD0 (M/T Stop) to I2CSTAT. Clear pending bit. Wait until the stop condition takes effect. END Figure 14-6 Operations for Master/Transmitter Mode 14-8 Exynos 4412_UM Figure 14-7 illustrates the operations for Master/Receiver Mode. 14 Inter-Integrated Circuit START Master Rx mode has been configured. Write slave address to I2CDS. Write 0xB0 (M/R Start) to I2CSTAT. The data of the I2CDS (Slave address) is transmitted. After ACK period interrupt is pending. Y Stop ? N Read a new data from I2CDS. Clear pending bit to resume. SDA is shifted to I2CDS. Write 0x90 (M/R Stop) to I2CSTAT. Clear pending bit. Wait until the stop condition takes effect. END Figure 14-7 Operations for Master/Receiver Mode 14-9 Exynos 4412_UM Figure 14-8 illustrates the operations for Slave/Transmitter mode. START Slave Tx mode has been configured. I2C detects start signal. and, I2CDS receives data. I2C compares I2CADD and I2CDS (the received slave address). Matched ? N Y The I2C address match interrupt is generated. Write data to I2CDS. Clear pending bit to resume. Stop ? Y N The data of the I2CDS is shifted to SDA. Interrupt is pending. 14 Inter-Integrated Circuit END Figure 14-8 Operations for Slave/Transmitter Mode 14-10 Exynos 4412_UM Figure 14-9 illustrates the operations for Slave/Receiver Mode. START Slave Rx mode has been configured. I2C detects start signal. and, 12CDS receives data. I2C compares I2CADD and I2CDS (the received slave address). Matched ? N Y The I2C address match interrupt is generated. Read data from I2CDS. Clear pending bit to resume. Stop ? Y N SDA is shifted to I2CDS. Interrupt is pending. 14 Inter-Integrated Circuit END Figure 14-9 Operations for Slave/Receiver Mode 14-11 Exynos 4412_UM 14.5 I/O Description Signal I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA I2C3_SCL I2C3_SDA I2C4_SCL I2C4_SDA I2C5_SCL I2C5_SDA I2C6_SCL I2C6_SDA I2C7_SCL I2C7_SDA I/O Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Description I2C-bus interface0 serial clock line I2C-bus interface0 serial data line I2C-bus interface1 serial clock line I2C-bus interface1 serial data line I2C-bus interface2 serial clock line I2C-bus interface2 serial data line I2C-bus interface3 serial clock line I2C-bus interface3 serial data line I2C-bus interface4 serial clock line I2C-bus interface4 serial data line I2C-bus interface5 serial clock line I2C-bus interface5 serial data line I2C-bus interface6 serial clock line I2C-bus interface6 serial data line I2C-bus interface7 serial clock line I2C-bus interface7 serial data line NOTE: The I2C bus interface for the HDMI has no external I/O. 14 Inter-Integrated Circuit Pad XI2C0SCL XI2C0SDA XI2C1SCL XI2C1SDA XuRTSn_1 XuCTSn_1 XuRTSn_2 XuCTSn_2 XspiMOSI_0 XspiMISO_0 XspiMOSI_1 XspiMISO_1 Xi2s2SDO Xi2s2SDI XpwmTOUT_3 XpwmTOUT_2 Type muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed 14-12 Exynos 4412_UM 14 Inter-Integrated Circuit 14.6 Register Description 14.6.1 Register Map Summary  Base Address: 0x1386_0000  Base Address: 0x1387_0000  Base Address: 0x1388_0000  Base Address: 0x1389_0000  Base Address: 0x138A_0000  Base Address: 0x138B_0000  Base Address: 0x138C_0000  Base Address: 0x138D_0000  Base Address: 0x138E_0000 Register I2CCONn I2CSTATn I2CADDn Offset 0x0000 0x0004 0x0008 I2CDSn 0x000C I2CLCn 0x0010 Description Specifies the I2C-bus interface0 control register Specifies the I2C-bus interface0 control/status register Specifies the I2C-bus interface0 address register Specifies the I2C-bus interface0 transmit/receive data shift register Specifies the I2C-bus interface0 multi-master line control register Reset Value 0x0X 0x00 0xXX 0xXX 0x00 14-13 Exynos 4412_UM 14 Inter-Integrated Circuit 14.6.1.1 I2CCONn (n = 0 to 7)  Base Address: 0x1386_0000  Base Address: 0x1387_0000  Base Address: 0x1388_0000  Base Address: 0x1389_0000  Base Address: 0x138A_0000  Base Address: 0x138B_0000  Base Address: 0x138C_0000  Base Address: 0x138D_0000  Base Address: 0x138E_0000  Address = Base Address + 0x0000, Reset Value = 0x0X Name RSVD Acknowledge generation (1) Tx clock source selection Tx/Rx Interrupt (5) Interrupt pending flag (2), (3) Transmit clock value (4) Bit [31:8] [7] [6] [5] [4] [3:0] Type – RW RW RW S RW Description Reserved I2C-bus acknowledge enable bit 0 = Disables 1 = Enables In Tx mode, the I2CSDA is idle in the ACK time. In Rx mode, the I2CSDA is low in the ACK time. Source clock of I2C-bus transmit clock prescaler selection bit 0 = I2CCLK = fPCLK/16 1 = I2CCLK = fPCLK/512 I2C-bus Tx/Rx interrupt enable/ disable bit 0 = Disables 1 = Enables I2C-bus Tx/Rx interrupt pending flag You cannot write this bit to 1. If you read this bit as 1, the I2CSCL is tied to Low and the I2C is stopped. To resume the operation, write this bit as 0. 0 = 1) No interrupt is pending (If Read). 2) Clears pending condition and resumes the operation (If Write). 1 = 1) Interrupt is pending (If Read) 2) N/A (If Write) I2C-bus transmit clock prescaler 4-bit prescaler value determines the I2C-bus transmit clock frequency according to the formula given here: Tx clock = I2CCLK/(I2CCON[3:0] + 1). Reset Value 0 0 0 0 0 – NOTE: 1. While interfacing with EEPROM, the ACK generation is disabled before Reading the last data to generate the STOP condition in Rx mode. 14-14 Exynos 4412_UM 14 Inter-Integrated Circuit 2. An I2C-bus interrupt occurs when: (a) 1-byte Transmit or Receive operation is complete. Alternatively, the ACK period is finished. (b) A general call or a Slave address match occurs. (c) Bus arbitration fails. 3. To adjust the setup time of SDA before SCL rising edge, ensure to Write I2CDS before clearing the I2C interrupt pending bit. 4. I2CCON[6] determines I2CCLK. Tx clock can vary by SCL transition time. When I2CCON[6] = 0, I2CCON[3:0] = 0x0 or 0x1 is not available. 5. When I2CCON[5] = 0, I2CCON[4] does not operate correctly. Therefore, set I2CCON[5] = 1 even if you do not use the I2C interrupt. 14-15 Exynos 4412_UM 14 Inter-Integrated Circuit 14.6.1.2 I2CSTATn (n = 0 to 7)  Base Address: 0x1386_0000  Base Address: 0x1387_0000  Base Address: 0x1388_0000  Base Address: 0x1389_0000  Base Address: 0x138A_0000  Base Address: 0x138B_0000  Base Address: 0x138C_0000  Base Address: 0x138D_0000  Base Address: 0x138E_0000  Address = Base Address + 0x0004, Reset Value = 0x00 Name RSVD Mode selection Busy signal status/START STOP condition Serial output Arbitration status flag Address-as-slave status flag Address zero status flag Last-received bit status flag Bit [31:8] [7:6] [5] [4] [3] [2] [1] [0] Type – RWX S S R R R R Description Reserved I2C-bus Master/Slave Tx/Rx mode select bits 00 = Slave receive mode 01 = Slave transmit mode 10 = Master receive mode 11 = Master transmit mode I2C-bus busy signal status bit 0 = (Read) Not busy (If Read) (write) STOP signal generation 1 = (Read) Busy (If Read) (write) START signal generation. Transfers the data in I2CDS automatically just after the start signal. I2C-bus data output enable/ disable bit 0 = Disables Rx/Tx 1 = Enables Rx/Tx I2C-bus arbitration procedure status flag bit 0 = Bus arbitration successful 1 = Bus arbitration fails during serial I/O I2C-bus address-as-slave status flag bit 0 = Clears when it detects START/STOP condition 1 = Receives slave address that matches the address value in the I2CADD I2C-bus address zero status flag bit 0 = Clears when it detects START/ STOP condition 1 = Received slave address is 00000000b I2C-bus last-received bit status flag bit 0 = Last-received bit is set to 0 (receives ACK). 1 = Last-received bit is set to 1 (does not receive ACK). Reset Value 0 00 0 0 0 0 0 0 14-16 Exynos 4412_UM Samsung Confidential 14.6.1.3 I2CADDn (n = 0 to 7)  Base Address: 0x1386_0000  Base Address: 0x1387_0000  Base Address: 0x1388_0000  Base Address: 0x1389_0000  Base Address: 0x138A_0000  Base Address: 0x138B_0000  Base Address: 0x138C_0000  Base Address: 0x138D_0000  Base Address: 0x138E_0000  Address = Base Address + 0x0008, Reset Value = 0xXX Name RSVD Slave address Bit [31:8] [7:0] Type – RWX Description Reserved 7-bit slave address, latched from the I2C-bus. When serial output enable = 0 in the I2CSTAT, I2CADD is write-enabled. The I2CADD value is Read any time, regardless of the current serial output enable bit (I2CSTAT) setting. Slave address: [7:1] Not mapped: [0] Reset Value 0 – 14-17 Exynos 4412_UM Samsung Confidential 14.6.1.4 I2CDSn (n = 0 to 7)  Base Address: 0x1386_0000  Base Address: 0x1387_0000  Base Address: 0x1388_0000  Base Address: 0x1389_0000  Base Address: 0x138A_0000  Base Address: 0x138B_0000  Base Address: 0x138C_0000  Base Address: 0x138D_0000  Base Address: 0x138E_0000  Address = Base Address + 0x000C, Reset Value = 0xXX Name RSVD Data shift Bit [31:8] [7:0] Type – RWX Description Reserved 8-bit data shift register for I2C-bus Tx/Rx operation. When serial output enable = 1 in the I2CSTAT, I2CDS is write-enabled. The I2CDS value is Read any time, regardless of the current serial output enable bit (I2CSTAT) setting. Reset Value 0 – 14-18 Exynos 4412_UM Samsung Confidential 14.6.1.5 I2CLCn (n = 0 to 7)  Base Address: 0x1386_0000  Base Address: 0x1387_0000  Base Address: 0x1388_0000  Base Address: 0x1389_0000  Base Address: 0x138A_0000  Base Address: 0x138B_0000  Base Address: 0x138C_0000  Base Address: 0x138D_0000  Base Address: 0x138E_0000  Address = Base Address + 0x0010, Reset Value = 0x00 Name RSVD Filter enable SDA output delay Bit [31:27] [2] [1:0] Type – RW RW Description Reserved I2C-bus filter enable bit When SDA port is operating as input, set this bit to High. This filter prevents error caused by glitch between two PCLK clocks. 0 = Disables Filter 1 = Enables Filter I2C-bus SDA line delay length selection bits The I2C controller delays the SDA line by following clock cycle: 00 = 0 clock 01 = 5 clocks 10 = 10 clocks 11 = 15 clocks Reset Value 0 0 00 14-19 Exynos 4412_UM 15 Serial Peripheral Interface 15 Serial Peripheral Interface 15.1 Overview Serial Peripheral Interface (SPI) in Exynos 4412 transfers serial data by using various peripherals. SPI includes two 8, 16, and 32-bit shift registers to transmit and receive data. During an SPI transfer, it simultaneously transmits (shifts out serially) and receives (shifts in serially) data. SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface. 15.2 Features The features of SPI include:  Full duplex  8/16/32-bit shift register for Tx/Rx  Supports 8-bit/16-bit/32-bit bus interface  Supports the Motorola SPI protocol and National Semiconductor Microwire  Two independent 32-bits wide transmit and receive FIFOs: depth 64 in port 0 and depth 16 in port 1 and 2  Master-mode and Slave-mode  Receive-without-transmit operation  Tx/Rx maximum frequency at up to 50 MHz 15-1 Exynos 4412_UM 15 Serial Peripheral Interface 15.2.1 Operation of SPI The SPI transfers 1-bit serial data between Exynos 4412 and external device. The SPI in Exynos 4412 supports the CPU or DMA to transmit or receive FIFOs separately and to transfer data in both directions simultaneously. SPI has two channels, namely, Tx channel and Rx channel. Tx channel has the path from Tx FIFO to external device. Rx channel has the path from external device to Rx FIFO. CPU (or DMA) must write data on the register SPI_TX_DATA, to write data in FIFO. Data on the register are automatically moved to Tx FIFOs. To read data from Rx FIFOs, CPU (or DMA) must access the register SPI_RX_DATA and data are automatically sent to the SPI_RX_DATA register. CMU registers can control SPI operating frequency. Refer to "CMU" chapter for more information. 15.2.1.1 Operation Mode SPI has two modes, namely, master and slave mode. In master mode, SPICLK is generated and transmitted to external device. XspiCS#, which is the signal to select slave, indicates that the data is valid when XspiCS# is set to low level. XspiCS# must be set low before packets are transmitted or received. 15.2.1.2 FIFO Access The SPI supports CPU access and DMA access to FIFOs. Data size of CPU access and DMA access to FIFOs are selected either from 8-bit, 16-bit, or 32-bit data. When it selects 8-bit data size, then valid bits are from 0 to 7bit. User can define the trigger threshold to raise interrupt to CPU. The trigger level of each FIFO in port 0 is set by 4 bytes step from 0 to 252 bytes, and that of each FIFO in port 1 is set by 1 byte step from 0 to 63 bytes. TxDMAOn or RxDMAOn bit of SPI_MODE_CFG register must be set to use DMA access. DMA access supports only single transfer and 4-burst transfer. In Tx FIFO, DMA request signal is high until Tx FIFO is full. In Rx FIFO, DMA request signal is high if FIFO is not empty. 15.2.1.3 Trailing Bytes in the Rx FIFO When the number of samples in Rx FIFO is less than the threshold value in INT mode or DMA 4-burst mode and it does not receive any additional data, then the remaining bytes are called trailing bytes. To remove these bytes in Rx FIFO, it uses internal timer and interrupt signal. The value of internal timer is set up to 1024 clocks based on APB BUS clock. When timer value is zero, interrupt signal occurs and CPU can remove trailing bytes in FIFO. 15.2.1.4 Packet Number Control SPI controls the number of packets to be received in master mode. Set SFR (PACKET_CNT_REG) to receive any number of packets. SPI stops generating SPICLK if the number of packets is similar to PACKET_CNT_REG. The size of one packet depends on channel width. (One packet is one byte when you configure channel width as byte, and one packet is four bytes when you configure channel width as word.) It is mandatory to follow software or hardware reset before reloading this function. (Software reset can clear all registers except special function registers, but hardware reset clears all registers.) 15-2 Exynos 4412_UM 15 Serial Peripheral Interface 15.2.1.5 Chip Select Control Chip select XspiCS# is active low signal. In other words, a chip is selected when XspiCS# input is 0. You can control XspiCS# automatically or manually. No need to change. When you use manual control mode, you should clear AUTO_N_MANUAL (default value is 0). NSSOUT bit controls XspiCS# level. When you use auto control mode, AUTO_N_MANUAL must be set as 1. XspiCS toggled between packet and packet automatically. NCS_TIME_COUNT controls inactive period of XspiCS. NSSOUT is not available at this time. 15.2.1.6 High Speed Operation as Slave Exynos 4412 SPI supports Tx/Rx operations up to 50 MHz, but there is a limitation. When Exynos 4412 SPI works as a slave, it consumes large delay more than 15 ns in worst operating condition. Such a large delay can cause setup violation at SPI master device. To overcome the problem, Exynos 4412 SPI provides fast slave Tx mode by setting 1 to HIGH_SPEED bit of CH_CFG register. In that mode, it reduces MISO output delay by half cycle, so that the SPI master device has more setup margin. However, you can use the fast slave Tx mode only when CPHA = 0. 15.2.1.7 Feedback Clock Selection Under SPI protocol specification, SPI master should capture the input data launched by slave (MISO) with its internal SPICLK. When SPI runs at high operating frequency such as 50 MHz, it is difficult to capture the MISO input because the required arrival time of MISO is half cycle period in Exynos 4412. It is shorter than the arrival time of MISO that consists of SPICLK output delay of SPI master, MISO output delay of SPI slave, and MISO input delay of SPI master. To overcome the problem, Exynos 4412 SPI provides three feedback clocks that are phase-delayed clock of internal SPICLK. A selection of feedback clock depends on MISO output delay of SPI slave. To capture MISO data correctly, it selects the feedback clock that satisfies the following constraint: tSPIMIS(s) < tperiod/2 – tSPISOD * tSPIMIS(s): * tSPISOD: * tperiod: MISO input setup time of SPI master on a given feedback clock selection "s" MISO output delay of SPI slave SPICLK cycle period If multiple feedback clocks meet the constraint, then it should select the feedback clock with smallest phase delay. Because of a feedback clock with large phase delay, it may capture data of next cycle. For example of Exynos 4412, SPI CH1 with master configuration of 50 MHz operating frequency, 1.8 V external voltage and 15 pF load, if it assumes MISO output delay of SPI slave as 11 ns (tSPIMIS(s)  10 ns – 11 ns = – 1 ns), then it should use 270 degree phase-delayed feedback clock. If the operating clock frequency is 33 MHz and other conditions are similar to the previous example, it is better to use 180 degree phase-delayed feedback clock (tSPIMIS(s)  15 ns – 11 ns = 4 ns). 15-3 Exynos 4412_UM 15 Serial Peripheral Interface 15.2.1.8 SPI Transfer Format The Exynos 4412 supports four different formats for data transfer. Figure 15-1 illustrates four waveforms for SPICLK. Cycle SPICLK MOSI MISO CPOL = 0, CPHA = 0 (Format A) 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB *MSB *MSB : MSB of previous frame Cycle CPOL = 0, CPHA = 1 (Format B) 1 2 3 4 5 6 7 SPICLK MOSI MSB 6 5 4 3 2 1 MISO LSB* MSB 6 5 4 3 2 1 8 LSB LSB LSB* : LSB of next frame Cycle SPICLK MOSI MISO CPOL = 1, CPHA = 0 (Format A) 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB *MSB *MSB : MSB of previous frame Cycle CPOL = 1, CPHA = 1 (Format B) 1 2 3 4 5 6 7 SPICLK MOSI MSB 6 5 4 3 2 1 MISO LSB* MSB 6 5 4 3 2 1 8 LSB LSB LSB* : LSB of next frame Figure 15-1 SPI Transfer Format 15-4 Exynos 4412_UM 15 Serial Peripheral Interface 15.3 SPI Input Clock Description Figure 15-2 illustrates the input clock diagram for SPI. System Controller XXTI XusbXTI SCLK_HDMI27M SCLK_USBPHY0 SCLK_USBPHY1 SCLK_HDMIPHY SCLKMPLL SCLKEPLL SCLKVPLL MUXSPI0~2 MOUTSPI0~2 DIVSPI0~2 (1~16) DIVSPI0~2_PRE (1~256) SPI SCLK_SPI DIV ( Max 100MHz ) (2) SPI_CLK ( Max 50MHz ) Figure 15-2 Input Clock Diagram for SPI Exynos 4412 provides SPI with a variety of clocks. As illustrated in the Figure 28-8, the SPI uses SCLK_SPI clock, which is from clock controller. You can also select SCLK_SPI from various clock sources. To select SCLK_SPI, refer to Chapter 7 Clock Controller for more information. NOTE: SPI has an internal 2x clock divider. You should configure SCLK_SPI to have a double of the SPI operating clock frequency. 15-5 Exynos 4412_UM 15 Serial Peripheral Interface 15.4 IO Description The IO description table lists the external signals between the SPI and external device. The unused SPI ports are used as General Purpose I/O ports. Refer to "General Purpose I/O" chapter for more information. Signal SPI_0_CLK SPI_1_CLK SPI_2_CLK SPI_0_nSS SPI_1_nSS SPI_2_nSS SPI_0_MISO SPI_1_MISO SPI_2_MISO SPI_0_MOSI SPI_1_MOSI SPI_2_MOSI I/O In/Out In/Out In/Out In/Out Description XspiCLK is the serial clock used to control time of data transfer. Out: when used as master In: when used as slave Slave selection signal. All data Tx/Rx sequences are executed if XspiCS is low. Out: when used as master In: when used as slave This port is the input port in Master mode. You can use input mode to get data from slave output port. It transmits data to master through this port in slave mode. Out: when used as slave In: when used as master This port is the output port in Master mode. It uses this port to transfer data from master output port. It receives data from master through this port in slave mode. Out: when used as master In: when used as slave Pad Type XspiCLK_0 XspiCLK_1 Xi2s2CDCLK muxed XspiCSn_0 XspiCSn_1 Xi2s2LRCK muxed XspiMISO_0 XspiMISO_1 Xi2s2SDI muxed XspiMOSI_0 XspiMOSI_1 Xi2s2SDO muxed NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals. 15-6 Exynos 4412_UM 15 Serial Peripheral Interface 15.5 Register Description 15.5.1 Register Map Summary  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000 Register CH_CFGn MODE_CFGn CS_REGn SPI_INT_ENn SPI_STATUSn SPI_TX_DATAn SPI_RX_DATAn PACKET_CNT_REGn PENDING_CLR_REGn SWAP_CFGn FB_CLK_SELn Offset 0x0000 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C Description Specifies SPI configuration Specifies FIFO control Specifies slave selection control Specifies interrupt enable Specifies SPI status Specifies Tx data Specifies Rx data Specifies packet count Specifies interrupt pending clear Specifies swap configuration Specifies feedback clock selection Setting Sequence of Special Function Register Steps to set Special Function Register (nCS manual mode) are: 1. Set Transfer Type. (CPOL and CPHA set) 2. Set Feedback Clock Selection register. 3. Set SPI MODE_CFG register. 4. Set SPI INT_EN register. 5. Set PACKET_CNT_REG register if necessary. 6. Set Tx or Rx Channel on. 7. Set nSSout low to start Tx or Rx operation: a. Set nSSout Bit to low, then start Tx data writing. b. When auto chip selection bit is set, nSSout is controlled automatically. Reset Value 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 15-7 Exynos 4412_UM 15 Serial Peripheral Interface 15.5.1.1 CH_CFGn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x0000, Reset Value = 0x0 Name RSVD HIGH_SPEED_EN SW_RST SLAVE CPOL CPHA RX_CH_ON TX_CH_ON Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW Description Reserved Slave Tx output time control bit If this bit is enabled, slave Tx output time is reduced as much as half period of SPICLKout period. This bit is valid only in CPHA 0. 0 = Disables 1 = Enables Software Reset The following registers and bits are cleared by this bit. Rx/Tx FIFO data, SPI_STATUS register will be reset once in the initial time. And after that, if we want to reset the register again, we have to use SW_RST bit manually. 0 = Inactive 1 = Active Whether SPI Port is Master or Slave 0 = Master 1 = Slave Determines whether active high or active low clock 0 = Active high 1 = Active low Select one of the two fundamentally different transfer format 0 = Format A 1 = Format B SPI Rx Channel On 0 = Channel off 1 = Channel on SPI Tx Channel On 0 = Channel off 1 = Channel on NOTE: SPI controller should reset when: 1. Reconfiguration of SPI registers is done. 2. Error interrupt has occurred. Reset Value – 0 0 0 0 0 0 0 15-8 Exynos 4412_UM 15 Serial Peripheral Interface 15.5.1.2 MODE_CFGn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x0008, Reset Value = 0x0 Name RSVD CH_WIDTH TRAILING_CNT BUS_WIDTH RX_RDY_LVL TX_RDY_LVL RSVD RX_DMA_SW TX_DMA_SW DMA_TYPE Bit [31] [30:29] [28:19] [18:17] [16:11] [10:5] [4:3] [2] [1] [0] Type – RW RW RW RW RW – RW RW RW Description Reserved 00 = Byte 01 = Halfword 10 = Word 11 = Reserved Count value from writing the last data in Rx FIFO to flush trailing bytes in FIFO 00 = Byte 01 = Halfword 10 = Word 11 = Reserved Rx FIFO trigger level in INT mode. Port 0: Trigger level (bytes) = 4  N Port 1, 2: Trigger level (bytes) = N (N = value of RX_RDY_LVL field) Tx FIFO trigger level in INT mode. Port 0: Trigger level (bytes) = 4  N Port 1, 2: Trigger level (bytes) = N (N = value of TX_RDY_LVL field) Reserved Rx DMA mode enable/disable 0 = Disables DMA Mode 1 = Enables DMA Mode Tx DMA mode enable/disable 0 = Disables DMA Mode 1 = Enables DMA Mode DMA transfer type, single or 4 bursts. 0 = Single 1 = 4 burst DMA transfer size must be set as the same size in SPI DMA. NOTE: 1. CH_WIDTH is shift-register width. 2. BUS_WIDTH is SPI FIFO width, transfer data size should be aligned with BUS_WIDTH. For example, Tx/Rx data size must be aligned with 4 bytes if BUS_WIDTH is word. 3. CH_WIDTH must be smaller than BUS_WIDTH or similar to BUS_WIDTH. Reset Value – 0 0 0 0 0 – 0 0 0 15-9 Exynos 4412_UM 15 Serial Peripheral Interface 15.5.1.3 CS_REGn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x000C, Reset Value = 0x1 Name RSVD NCS_TIME_COUNT RSVD AUTO_N_MANUAL NSSOUT Bit [31:10] [9:4] [3:2] [1] [0] Type – RW – RW RW Description Reserved NSSOUT inactive time = ((nCS_time_count + 3)/2)  SPICLKout Reserved Chip select toggle manual or auto selection 0 = Manual 1 = Auto Slave selection signal (manual only) 0 = Active 1 = Inactive Reset Value – 0 – 0 1 When AUTO_N_MANUAL is set, then SPI controller controls NSSOUT and does not perform data transfer continuously. Unit data size depends on CH_WIDTH. Figure 15-3 illustrates auto chip select mode waveform. SPICLK MOSI MSB 6 5 4 3 2 1 LSB *MSB 6 5 4 3 2 1 *LSB MISO MSB 6 5 4 3 2 1 LSB *MSB 6 5 4 3 2 1 *LSB **MSB NSSOUT NCS_TIME_ COUNT Figure 15-3 Auto Chip Select Mode Waveform (CPOL = 0, CPHA = 0, CH_WIDTH = Byte) 15-10 Exynos 4412_UM 15 Serial Peripheral Interface 15.5.1.4 SPI_INT_ENn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x0010, Reset Value = 0x0 Name RSVD INT_EN_TRAILING INT_EN_RX_ OVERRUN INT_EN_RX_ UNDERRUN INT_EN_TX_ OVERRUN INT_EN_TX_ UNDERRUN INT_EN_RX_FIFO_ RDY INT_EN_TX_FIFO_ RDY Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW Description Reserved Interrupt Enable for trailing count to be 0 0 = Disables 1 = Enables Interrupt Enable for RxOverrun 0 = Disables 1 = Enables Interrupt Enable for RxUnderrun 0 = Disables 1 = Enables Interrupt Enable for TxOverrun 0 = Disables 1 = Enables Interrupt Enable for TxUnderrun. In slave mode, this bit must be clear first after turning on slave Tx path. 0 = Disables 1 = Enables Interrupt Enable for RxFifoRdy (INT mode) 0 = Disables 1 = Enables Interrupt Enable for TxFifoRdy (INT mode) 0 = Disables 1 = Enables Reset Value – 0 0 0 0 0 0 0 15-11 Exynos 4412_UM 15 Serial Peripheral Interface 15.5.1.5 SPI_STATUSn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x0014, Reset Value = 0x0 Name RSVD TX_DONE TRAILING_BYTE RX_FIFO_LVL TX_FIFO_LVL RX_OVERRUN RX_UNDERRUN TX_OVERRUN TX_UNDERRUN RX_FIFO_RDY TX_FIFO_RDY Bit [31:26] [25] [24] [23:15] [14:6] [5] [4] [3] [2] [1] [0] Type – R R R R R R R R R R Description Reserved Indication of transfer done in Shift register (master mode only) 0 = All case except below case 1 = If Tx FIFO and shift register are empty after transmission start Indication that trailing count is 0 Data level in Rx FIFO 0 to 256 bytes in port 0 0 to 64 bytes in port 1, 2 Data level in Tx FIFO 0 to 256 bytes in port 0 0 to 64 bytes in port 1, 2 Rx FIFO overrun error 0 = No error 1 = Overrun error Rx FIFO underrun error 0 = No error 1 = Underrun error Tx FIFO overrun error 0 = No error 1 = Overrun error Tx FIFO underrun error 0 = No error 1 = Underrun error NOTE: Tx FIFO underrun error will occur if Tx FIFO is empty in slave mode. 0 = Data in FIFO less than trigger level 1 = Data in FIFO more than trigger level 0 = Data in FIFO more than trigger level 1 = Data in FIFO less than trigger level Reset Value – 0 0 0 0 0 0 0 0 0 0 15-12 Exynos 4412_UM 15 Serial Peripheral Interface 15.5.1.6 SPI_TX_DATAn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x0018, Reset Value = 0x0 Name TX_DATA Bit [31:0] Type W Description This field contains the data to be transmitted over the SPI channel. Reset Value 0 15.5.1.7 SPI_RX_DATAn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x001C, Reset Value = 0x0 Name RX_DATA Bit [31:0] Type R Description This field contains the data to be received over the SPI channel. Reset Value 0 15.5.1.8 PACKET_CNT_REGn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x0020, Reset Value = 0x0 Name RSVD PACKET_CNT_EN COUNT_VALUE Bit [31:17] [16] [15:0] Type – RW RW Description Reserved Enable bit for packet count 0 = Disables 1 = Enables Packet count value Reset Value – 0 0 15-13 Exynos 4412_UM 15 Serial Peripheral Interface 15.5.1.9 PENDING_CLR_REGn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x0024, Reset Value = 0x0 Name RSVD TX_UNDERRUN_CLR TX_OVERRUN_CLR RX_UNDERRUN_CLR RX_OVERRUN_CLR TRAILING_CLR Bit [31:5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW Description Reserved Tx underrun pending clear bit 0 = Non-Clear 1 = Clears Tx overrun pending clear bit 0 = Non-Clear 1 = Clears Rx underrun pending clear bit 0 = Non-clear 1 = Clears Rx overrun pending clear bit 0 = Non-Clear 1 = Clears Trailing pending clear bit 0 = Non-Clear 1 = Clears NOTE: After error interrupt pending clear, SPI controller should be reset. Error interrupt list: Tx underrun, Tx overrun, Rx underrun, and Rx overrun. Reset Value – 0 0 0 0 0 15-14 Exynos 4412_UM 15 Serial Peripheral Interface 15.5.1.10 SWAP_CFGn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x0028, Reset Value = 0x0 Name RSVD RX_HWORD_SWAP RX_BYTE_SWAP RX_BIT_SWAP RX_SWAP_EN TX_HWORD_SWAP TX_BYTE_SWAP TX_BIT_SWAP TX_SWAP_EN Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW Reserved 0 = Off 1 = Swap 0 = Off 1 = Swap 0 = Off 1 = Swap Swap Enable 0 = Normal 1 = Swap 0 = Off 1 = Swap 0 = Off 1 = Swap 0 = Off 1 = Swap Swap Enable 0 = Normal 1 = Swap NOTE: Data size must be larger than swap size. Description Reset Value – 0 0 0 0 0 0 0 0 15-15 Exynos 4412_UM 15 Serial Peripheral Interface 15.5.1.11 FB_CLK_SELn (n = 0 to 2)  Base Address: 0x1392_0000  Base Address: 0x1393_0000  Base Address: 0x1394_0000  Address = Base Address + 0x002C, Reset Value = 0x0 Name RSVD FB_CLK_SEL Bit [31:2] [1:0] Type – RW Description Reserved In master mode, SPI uses a clock which is feedback from the SPICLK. The feedback clock is intended to capture safely the slave Tx signal. The slave Tx signal can lag if slave device is very far. There are four types of feedback clocks which experience different path delays. This register selects the feedback clock that you can use. Note that this register value is invalid when SPI operates in slave mode. 00 = SPICLK bypass (do not use feedback clock) 01 = A feedback clock with 90 degree phase lagging 10 = A feedback clock with 180 degree phase lagging 11 = A feedback clock with 270 degree phase lagging 90 degree phase lagging means 5 ns delay in 50 MHz operating frequency. Reset Value – 0x0 PAD Driving Strength PAD driving strength of SPI is controlled by setting drive strength control register in GPIO. SPI related SFR is GPBDRV (for SPI port 0 and 1) and GPCDRV (for SPI port 2). 15-16 Exynos 4412_UM 16 Display Controller 16 Display Controller 16.1 Overview Display controller consists of logic for transferring image data from a local bus of the camera interface controller or a video buffer located in system memory to an external LCD driver interface. The LCD driver interface supports three kinds of interfaces. They are RGB-interface, indirect-i80 interface, and YUV interface for write-back. The display controller uses up to five overlay image windows that support various color formats, 256 level alpha blending, color key, x-y position control, soft scrolling, and variable window size, among others. Display controller supports various color formats such as RGB (1 to 24 BPP) and YCbCr 4:4:4 (only local bus). You can program the display controller to support the different requirements on screen that associates with the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate. Display controller transfers the video data and generates the necessary control signals, such as, RGB_VSYNC, RGB_HSYNC, RGB_VCLK, RGB_VDEN, SYS_CS0, SYS_CS1, and SYS_WE. Additionally generating control signals, display controller contains data ports for video data (RGB_VD[23:0], and SYS_VD) Figure 16-1 illustrates the block diagram of display controller. FIFO I/F (8bit * 3) AXI Master I/F 24 24 Local I/F 24 (3-ch .) 64 ( ID : 1bit ) 64 ( ID : 2bit ) 256 x64 FIFO (5-ch .) AHB 32 Slave I/F ARBI TER + DMA PI XSC H ED (5-ch .) Blen der (5-ch . O v erl a y) Gam ma Color Gain H ue D itherin g FIMD 6. 0 VTIME _ RGB _ TV VTIME _i 80 CTRL SFRFILE YUV IF RGB I /F I80 I/ F 30 WB_ YUV 24 RGB_ VD 24 SYS_ VD Figure 16-1 Block Diagram of Display Controller 16-1 Exynos 4412_UM 16 Display Controller 16.2 Features The features of the display controller include: Video Output Interface Dual Output Mode PIP (OSD) function CSC (Internal) Source format Configurable Burst Length Palette Soft Scrolling Virtual Screen Transparent Overlay Color Key (Chroma Key) Partial Display RGB Interface (24-bit Parallel/8-bit Serial) Indirect i80 interface Write-Back interface Supports i80 and Write-Back Supports RGB and Write-Back Supports 8-BPP (bit per pixel) palletized color Supports 16-BPP non-palletized color Supports unpacked 18 BPP non-palletized color Supports unpacked 24 BPP non-palletized color Supports X,Y indexed position Supports 8-bit Alpha blending (Plane/Pixel) RGB to YCbCr (4:2:2) Window 0 Supports 1, 2, 4, or 8 BPP palletized color Supports 16, 18, or 24 BPP non-palletized color Supports RGB (8:8:8) local input from Local Bus (FIMC0) Window 1 Supports 1, 2, 4, or 8 BPP palletized color Supports 16, 18, or 24 BPP non-palletized color Supports RGB (8:8:8) local input from Local Bus (FIMC1) Window 2 Supports 1, 2, 4, or 8 BPP palletized color Supports 16, 18, or 24 BPP non-palletized color Supports RGB (8:8:8) local input from Local Bus (FIMC2) Window 3/4 Supports 1, 2, 4, or 8 BPP palletized color Supports 16, 18, or 24 BPP non-palletized color Programmable 4/8/16 Burst DMA Window 0/1/2/3/4 Supports 256  32 bits palette memory (5EA: One palette memory for each window) Horizontal = 1 Byte resolution Vertical = 1 pixel resolution Virtual image can have up to 16 MB image size. Each window can have its own virtual area. Supports transparent overlay Supports color key function Supports simultaneously color key and blending function Supports LCD partial display function through i80 interface 16-2 Exynos 4412_UM 16 Display Controller Image Enhancement Video Clock Source Maximum VCLK in RGB Interface Supports gamma control Supports hue control Supports color gain control SCLK_FIMD0 for display controller (from CMU module) Display Controller = 80 MHz 16-3 Exynos 4412_UM 16 Display Controller 16.3 Functional Description The functional description section describes the functionality of display controller. 16.3.1 Brief Description The display controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator. To configure the display controller, the VSFR has  121 programmable register sets  one gamma LUT register set (64 registers)  one i80 command register set (12 registers)  five 256  32 palette memories VDMA is a dedicated display DMA that transfers video data in frame memory to VPRCS. By using this special DMA, you can display video data on screen without CPU intervention. VPRCS receives video data from VDMA and sends it to display device (LCD) through data ports (RGB_VD, or SYS_VD), after changing the video data into a suitable data format, for example, 8-bit per pixel mode (8 BPP mode) or 16-bit per pixel mode (16 BPP mode). VTIME consists of programmable logic to support the variable requirement of interface timing and rates commonly found in different LCD drivers. The VTIME block generates RGB_VSYNC, RGB_HSYNC, RGB_VCLK, RGB_VDEN, VEN_VSYNC, VEN_HSYNC, VEN_FIELD, VEN_HREF, SYS_CS0, SYS_CS1, SYS_WE, and so on. Using the display controller data, you can select one of the above data paths by setting LCDBLK_CFG Register (0x1001_0210). For more information, refer to the "System Others" manual. 16-4 Exynos 4412_UM 16 Display Controller 16.3.2 Data Flow FIFO is in the VDMA. If FIFO is empty or partially empty, the VDMA requests data fetching from frame memory based on burst memory transfer mode. The data transfer rate determines the size of FIFO. The display controller contains five FIFOs (Three local FIFOs and two DMA FIFOs), since it needs to support the overlay window display mode. Use one FIFO for one screen display mode. VPRCS fetches data from FIFO. It contains the following functions for final image data: blending, image enhancing, and scheduling. It also supports the overlay function. This can overlay any image up to five window images, whose smaller or same size can be blended with the main window image having programmable alpha blending or color (chroma) key function. Figure 16-2 shows the data flow from system bus to output buffer. VDMA has five DMA channels (Ch0-Ch4) and three local input interfaces (CAMIF0, CAMIF1, and (CAMIF2 or CAMIF3)). The Color Space Conversion (CSC) block changes Hue (YCbCr, local input only) data to RGB data for blending operation. Also, the alpha values written in SFR determine the level of blending. Data from output buffer appears in the Video Data Port. NOTE: The performance of the all these local input interfaces is limited by the scale ratio of the input and output image resolution (TBD). 16-5 Exynos 4412_UM AXI 16 Display Controller CAMIF0 ( YUV/ RGB) YUV4:4:4 / RGB888 LIMITER CH 0 ( RGB) CAMIF1 ( YUV/ RGB) YUV4: 4:4 / RGB888 LIMITER CH 1 ( RGB) CAMIF2/ CAMIF3 ( YUV/ RGB) YUV4:4:4 / RGB888 LIMITER CH 2 ( RGB) CH 3 ( RGB) CH 4 ( RGB) CSC CSC CSC WIN0( RGB) RGB888 WIN1( RGB) RGB888 WIN2( RGB) RGB888 WIN3( RGB) RGB 888 WIN4 ( RGB) RGB888 Blending Color Keying RGB888 Blending Color Keying RGB888 Blending Color Keying RGB 888 Blending Color Keying RGB 888 Gamma( RGB) RGB 888 Color Gain( RGB) RGB 888 CSC Hue( YCbCr) CSC RGB 888 VE( RGB) RGB 888 Pixel Compen. (RGB) RGB 888 Dithering( RGB) RGB 888 RGBe RGB 888 RGBb Figure 16-2 Block Diagram of the Data Flow 16-6 Exynos 4412_UM 16 Display Controller 16.3.2.1 Interface The display controller supports three types of interfaces:  The first type is the conventional RGB interface, which uses RGB data, vertical/ horizontal sync, data valid signal, and data sync clock.  The second type is the indirect i80 Interface, which uses address, data, chip select, read/ write control, and register/ status indicating signal. The LCD driver using i80 Interface contains a frame buffer and can selfrefresh, so the display controller updates one still image by writing only one time to the LCD.  The third type is FIFO interface with CAMIFx selected FIMDxWB_DEST Bit Field on CAMERA_CONTROL Register in System Register for writeback. RGBe RGB 888 RGBb RGB 888 CSC YUV I/F RGB 888 RGB I / F RGB 888 i 80I/F RGB Inerface ( 24 / 8 bit) i 80 Inerface (8 / 9 / 16/ 18/ 24 bit) YUV4:4: 4 ( 30 bit) WriteBack to CAMIFx Figure 16-3 Block Diagram of the Interface 16-7 Exynos 4412_UM 16 Display Controller 16.3.3 Overview of the Color Data The overview of the color data section describes the RGB data format and 25 BPP display of display controller. 16.3.3.1 RGB Data Format The display controller requests the specified memory format of frame buffer. Figure 16-4 illustrates some examples of each display mode. 16.3.3.2 25 BPP Display (A888) Figure 16-4 illustrates the examples of each display mode. Figure 16-4 Memory Format of 25 BPP(A888) Display NOTE: 1. AEN: Specifies the transparency value selection bit. AEN = 0: Selects ALPHA0. AEN = 1: Selects ALPHA1. When it sets per-pixel blending, then this pixel blends with alpha value that AEN selects.. SFR selects the alpha value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B. For more information, refer to the section on "SFR". 2. D[23:16] = Red data, D[15:8] = Green data, and D[7:0] = Blue data. 16-8 Exynos 4412_UM 16.3.3.2.1 32BPP (8888) Mode Figure 16-5 illustrates the pixel data that contains alpha value. 16 Display Controller ( BYSWP=0 , HWSWP=0, WSWP= 0 ) D[63: 56] 000H ALPHA value 008H ALPHA value 010H ALPHA value … ( BYSWP=0 , HWSWP=0, WSWP= 1 ) D[63: 56] 000H ALPHA value 008H ALPHA value 010H … ALPHA value D[55: 32] P1 P3 P5 D[55: 32] P2 P4 P6 D[31:24] ALPHA value ALPHA value ALPHA value D[31:24] ALPHA value ALPHA value ALPHA value D[23: 0] P2 P4 P6 D[23: 0] P1 P3 P5 Figure 16-5 Memory Format of 32 BPP (8888) Display 16-9 Exynos 4412_UM 16.3.3.2.2 24 BPP Display (A887) Figure 16-6 illustrates the 24 BPP display. ( BSWP=0, HWSWP=0, WSWP=0 ) D[63:56] D[55] 000H Dummy Bit AEN 008H Dummy Bit AEN 010H Dummy Bit AEN … D[54:32] P1 P3 P5 ( BSWP=0, HWSWP=0, WSWP=1 ) D[63:56] D[55] 000H Dummy Bit AEN 008H Dummy Bit AEN 010H Dummy Bit AEN … D[54:32] P2 P4 P6 16 Display Controller D[31:24] Dummy Bit Dummy Bit Dummy Bit D[23] AEN AEN AEN D[22:0] P2 P4 P6 D[31:24] Dummy Bit Dummy Bit Dummy Bit D[23] AEN AEN AEN D[22:0] P1 P3 P5 P1 P2 P3 P4 P5 ...... LCD Panel Figure 16-6 Memory Format of 24 BPP (A887) Display NOTE: 1. AEN: Specifies the transparency value selection bit. AEN = 0: Selects ALPHA0. AEN = 1: Selects ALPHA1. When it sets per-pixel blending, then this pixel blends with alpha value that AEN selects. SFR selects the alpha value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B. For more information, refer to the section on "SFR". 2. D[22:15] = Red data, D[14:7] = Green data, and D[6:0] = Blue data. 16-10 Exynos 4412_UM 16.3.3.2.3 24 BPP Display (888) Figure 16-7 illustrates the 24 BPP display. ( BSWP=0, HWSWP=0, WSWP=0 ) D[63:56] 000H Dummy Bit 008H Dummy Bit 010H Dummy Bit … D[55:32] P1 P3 P5 ( BSWP=0, HWSWP=0, WSWP=1 ) D[63:56] 000H Dummy Bit 008H Dummy Bit 010H Dummy Bit … D[55:32] P2 P4 P6 D[31:24] Dummy Bit Dummy Bit Dummy Bit D[31:24] Dummy Bit Dummy Bit Dummy Bit P1 P2 P3 P4 P5 ...... LCD Panel 16 Display Controller D[23:0] P2 P4 P6 D[23:0] P1 P3 P5 Figure 16-7 Memory Format of 24 BPP (888) Display NOTE: D[23:16] = Red data, D[15:8] = Green data, and D[7:0] = Blue data. 16-11 Exynos 4412_UM 16.3.3.2.4 19 BPP Display (A666) Figure 16-8 illustrates the 19 BPP display. ( BSWP=0, HWSWP=0, WSWP=0 ) D[63:51] D[50] 000H Dummy Bit AEN 008H Dummy Bit AEN 010H Dummy Bit AEN … D[49:32] P1 P3 P5 ( BSWP=0, HWSWP=0, WSWP=1 ) D[63:51] D[50] 000H Dummy Bit AEN 008H Dummy Bit AEN 010H Dummy Bit AEN … D[49:32] P2 P4 P6 16 Display Controller D[31:19] Dummy Bit Dummy Bit Dummy Bit D[18] AEN AEN AEN D[17:0] P2 P4 P6 D[31:19] Dummy Bit Dummy Bit Dummy Bit D[18] AEN AEN AEN D[17:0] P1 P3 P5 P1 P2 P3 P4 P5 ...... LCD Panel Figure 16-8 Memory Format of 19 BPP (A666) Display NOTE: 1. AEN: Specifies the transparency value selection bit. AEN = 0: Selects ALPHA0. AEN = 1: Selects ALPHA1. When it sets per-pixel blending, then this pixel blends with alpha value that AEN selects.. SFR selects the alpha value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B. For more information, refer to the section on "SFR". 2. D[17:12] = Red data, D[11:6] = Green data, and D[5:0] = Blue data. 16-12 Exynos 4412_UM 16.3.3.2.5 18 BPP Display (666) Figure 16-9 illustrates the 18 BPP display. ( BSWP=0, HWSWP=0, WSWP=0 ) D[63:50] 000H Dummy Bit 008H Dummy Bit 010H Dummy Bit … D[49:32] P1 P3 P5 ( BSWP=0, HWSWP=0, WSWP=1 ) D[63:50] 000H Dummy Bit 008H Dummy Bit 010H Dummy Bit … D[49:32] P2 P4 P6 D[31:18] Dummy Bit Dummy Bit Dummy Bit D[31:18] Dummy Bit Dummy Bit Dummy Bit P1 P2 P3 P4 P5 ...... LCD Panel 16 Display Controller D[17:0] P2 P4 P6 D[17:0] P1 P3 P5 Figure 16-9 Memory Format of 18 BPP (666) Display NOTE: D[17:12] = Red data, D[11:6] = Green data, and D[5:0] = Blue data. 16-13 Exynos 4412_UM 16 Display Controller 16.3.3.2.6 16 BPP Display (A555) Figure 16-10 illustrates the 16 BPP display. ( BSWP=0, HWSWP=0, WSWP=0 ) D[63] D[62:48] 000H AEN1 P1 004H AEN5 P5 008H AEN9 P9 … D[47] AEN2 AEN6 AEN10 D[46:32] P2 P6 P10 D[31] AEN3 AEN7 AEN11 D[30:16] P3 P7 P11 D[15] AEN4 AEN8 AEN12 D[14:0] P4 P8 P12 ( BSWP=0, HWSWP=0, WSWP=1 ) D[63] D[62:48] 000H AEN3 P3 004H AEN7 P7 008H AEN11 P11 … D[47] AEN4 AEN8 AEN12 D[46:32] P4 P8 P12 D[31] AEN1 AEN5 AEN9 D[30:16] P1 P5 P9 D[15] AEN2 AEN6 AEN10 D[14:0] P2 P6 P10 ( BSWP=0, HWSWP=1, WSWP=0 ) D[63] D[62:48] 000H AEN4 P4 004H AEN8 P8 008H AEN12 P12 … D[47] AEN3 AEN7 AEN11 D[46:32] P3 P7 P11 D[31] AEN2 AEN6 AEN10 D[30:16] P2 P6 P10 D[15] AEN1 AEN5 AEN9 D[14:0] P1 P5 P9 Figure 16-10 Memory Format of 16 BPP (A555) Display NOTE: 1. AEN: Specifies the transparency value selection bit. AEN = 0: Selects ALPHA0. AEN = 1: Selects ALPHA1. When it sets per-pixel blending, then this pixel blends with alpha value that AEN selects. SFR selects the alpha value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B. For more information, refer to the section on "SFR". 2. D[14:10] = Red data, D[9:5] = Green data, and D[4:0] = Blue data. 16-14 Exynos 4412_UM 16.3.3.2.7 16 BPP Display (1555) Figure 16-11 illustrates the 16 BPP display. ( BSWP=0 , HWSWP=0 , WSWP= 0 ) D[63:48] 000H P1 008H P5 010H P9 … ( BSWP=0 , HWSWP=0 , WSWP= 1 ) D[63:48] 000H P3 008H P7 010H P11 … ( BSWP=0 , HWSWP=1 , WSWP= 0 ) D[63:48] 000H P4 008H P8 010H P12 … D[47:32] P2 P6 P10 D[47:32] P4 P8 P12 D[47:32] P3 P7 P11 P1 P2 P3 P4 P5 ...... D[31:16] P3 P7 P 11 D[31:16] P1 P5 P9 D[31:16] P2 P6 P 10 LCD Panel 16 Display Controller D[15:0] P4 P8 P12 D[15:0] P2 P6 P10 D[15:0] P1 P5 P9 Figure 16-11 Memory Format of 16 BPP (1555) Display NOTE: {D[14:10], D[15]} = Red data, {D[9:5], D15]} = Green data, and {D[4:0], D[15]} = Blue data. 16-15 Exynos 4412_UM 16.3.3.2.8 16 BPP Display (565) Figure 16-12 illustrates the 16 BPP display. ( BSWP=0, HWSWP=0, WSWP=0 ) D[63 :48] 000H P1 008H P5 010H P9 … ( BSWP=0, HWSWP=0, WSWP=1 ) D[63:48] 000H P3 008H P7 010H P11 … ( BSWP=0, HWSWP=1, WSWP=0 ) D[63:48] 000H P4 008H P8 010H P12 … D[ 47:32] P2 P6 P10 D[ 47:32] P4 P8 P12 D[ 47:32] P3 P7 P11 P1 P2 P3 P4 P5 ...... D[31 :16] P3 P7 P11 D[31:16] P1 P5 P9 D[31:16] P2 P6 P10 LCD Panel 16 Display Controller D[ 15: 0] P4 P8 P12 D[ 15: 0] P2 P6 P10 D[ 15: 0] P1 P5 P9 Figure 16-12 Memory Format of 16 BPP (565) Display NOTE: D[15:10] = Red data, D[10:5] = Green data, and D[4:0] = Blue data. 16-16 Exynos 4412_UM Figure 16-13 illustrates the 16 BPP (5:6:5) display types. 16 Display Controller A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I 12345 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:5:5+1 Format(Non-Palette) A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 12345 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 A[15] A[14] A[13] A[12]A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:6:5 Format(Non-Palette) Figure 16-13 16 BPP (5:6:5) Display Types 16-17 Exynos 4412_UM 16 Display Controller 16.3.3.2.9 13 BPP Display (A444) Figure 16-14 illustrates the13 BPP display. ( BYSWP=0 , HWSWP=0, WSWP= 0 ) D[63:61] D[60] D[ 59: 48] 000H Dummy AEN1 P1 004H Dummy AEN5 P5 008H Dummy AEN9 P9 … D[ 47:45] Dummy Dummy Dummy D[44] AEN2 AEN6 AEN10 D[43: 32] P2 P6 P10 D[31: 29] Dummy Dummy Dummy D[28] AEN3 AEN7 AEN11 D [27 :16] P3 P7 P11 D[15: 13] Dummy Dummy Dummy D[12] AEN4 AEN8 AEN12 D[ 11:0] P4 P8 P12 ( BYSWP=0 , HWSWP=1 , WSWP= 0 ) D[63:61] D[60] D[59: 48] 000H Dummy AEN4 P4 004H Dummy AEN8 P8 008H Dummy AEN12 P12 … D[47:45] D[44] Dummy AEN3 Dummy AEN7 Dummy AEN11 D[43: 32] P3 P7 P11 D[31: 29] Dummy Dummy Dummy D[ 28] AEN2 AEN6 AEN10 D[27: 16] P2 P6 P 10 D[ 15: 13] Dummy Dummy Dummy D[12] AEN1 AEN5 AEN9 D[ 11:0] P1 P5 P9 P1 P2 P3 P4 P5 ...... LCD Panel Figure 16-14 Memory Format of 13 BPP (A444) Display NOTE: 1. AEN: Specifies the transparency value selection bit. AEN = 0: Selects ALPHA0. AEN = 1: Selects ALPHA1. When it sets per-pixel blending, then this pixel blends with alpha value that AEN selects. 2. D[11:8] = Red data, D[7:4] = Green data, and D[3:0] = Blue data. 3. 16 BPP (4444) mode. (For more information, refer to the section on "SFR") Data has Alpha value. ( BYSWP=0, HWSWP=0, WSWP=0 ) D[63:60] D[59:48] D [47:44] 000H ALPHA1 P1 ALPHA2 004H ALPHA5 P5 ALPHA6 008H ALPHA9 P9 ALPHA10 … D[ 43:32] P2 P6 P10 D[ 31:28] ALPHA3 ALPHA7 ALPHA11 D[ 27:16 ] P3 P7 P11 D[ 15: 12] ALPHA4 ALPHA8 ALPHA12 D [11:0] P4 P8 P12 16-18 Exynos 4412_UM 16 Display Controller 16.3.3.2.10 8 BPP Display (A232) Figure 16-15 illustrates the 8 BPP display. ( BYSWP=0, HWSWP=0, WSWP=0 ) D[63] D[62:56] D[55] D[54:48] 000H AEN P1 AEN P2 008H 010H AEN P9 AEN P 10 AEN P17 AEN P 18 … D[47] D[46:40] AEN P3 AEN P11 AEN P19 D[39] D[38:32] AEN P4 AEN P 12 AEN P 20 D[31] AEN AEN AEN D[ 30:24] P5 P13 P21 D[23] D[22:16] AEN P6 AEN P14 AEN P22 D[15] AEN AEN AEN D[14:8] P7 P15 P23 D[ 7] AEN AEN AEN D[6:0] P8 P16 P24 ( BYSWP=1, HWSWP=0, WSWP=0 ) D[63] D[62:56] D[55] D[54:48] 000H AEN P8 AEN P7 008H AEN P16 AEN P 15 010H AEN P24 AEN P 23 … D[47] D[46:40] AEN P6 AEN P14 AEN P22 D[39] D[38:32] AEN P5 AEN P 13 AEN P 21 D[31] AEN AEN AEN D[ 30:24] P4 P12 P20 D[23] D[22:16] AEN P3 AEN P11 AEN P19 D[15] AEN AEN AEN D[14:8] P2 P10 P18 D[ 7] AEN AEN AEN D[6:0] P1 P9 P17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 ...... LCD Panel Figure 16-15 Memory Format of 8 BPP (A232) Display NOTE: 1. AEN: Specifies the transparency value selection bit. AEN = 0: Selects ALPHA0. AEN = 1: Selects ALPHA1. When it sets per-pixel blending, then this pixel blends with alpha value that AEN selects. SFR selects the alpha value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B. For more information, refer to the section on "SFR". 2. D[6:5] = Red data, D[4:2] = Green data, and D[1:0] = Blue data. 16-19 Exynos 4412_UM 16 Display Controller 16.3.3.2.11 8 BPP Display (Palette) Figure 16-16 illustrates the 8 BPP display. ( BYSWP=0, HWSWP=0, WSWP=0 ) D[63:56] D[55:48] D[47:40] 000H P1 P2 P3 008H P9 P 10 P11 010H … P17 P 18 P19 D[39: 32] P4 P12 P20 D[ 31:24] D[23:16] P5 P6 P13 P14 P21 P22 D[ 15:8] P7 P15 P23 D[7:0] P8 P16 P24 ( BYSWP=1, HWSWP=0, WSWP=0 ) D[63:56] D[55:48] D[47:40] D[39:32] D[ 31:24] D[23:16] 000H P8 P7 P6 P5 P4 P3 008H P16 P15 P14 P13 P12 P11 010H P24 P23 P22 P21 P20 P19 … D[ 15: 8] P2 P10 P18 D[7:0] P1 P9 P17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 ...... LCD Panel Figure 16-16 Memory Format of 8 BPP Display NOTE: AEN: Specifies the transparency value selection bit (with WPALCON: Palette output format). AEN = 0: Selects ALPHA0. AEN = 1: Selects ALPHA1. When it sets per-pixel blending, then this pixel blends with alpha value that AEN selects. SFR selects the alpha value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B. For more information, refer to the section on "SFR". 16-20 Exynos 4412_UM 16 Display Controller 16.3.3.2.12 4 BPP Display (Palette) Figure 16-17 illustrates the 4 BPP display. ( BYSWP=0, HWSWP=0, WSWP=0 ) D[63:60] D[59:56] D[55:52] 000H P1 P2 P3 008H P17 P 18 P19 … D[51: 48] P4 P20 D[ 47:44] P5 P21 D[43: 40] P6 P22 D[ 39: 36] P7 P23 D[ 35: 32] P8 P24 000H 008H … D[31:28] P9 P25 D[27:24] D[23:20] P 10 P11 P 26 P27 D[19: 16] P12 P28 D[ 15:12] P13 P29 D[11:8] P14 P30 D[7:4] P15 P31 D[3:0] P16 P32 ( BYSWP=1, HWSWP=0, WSWP=0 ) D[63:60] D[59:56] D[55:52] 000H P15 P 16 P13 008H … P31 P 32 P29 D[51: 48] P14 P30 D[ 47:44] P11 P27 D[43: 40] P12 P28 D[ 39: 36] P9 P25 D[ 35: 32] P10 P26 000H 008H … D[31:28] P7 P23 D[27:24] D[23:20] P8 P5 P 24 P21 D[19: 16] P6 P22 D[ 15:12] P3 P19 D[11:8] P4 P20 D[7:4] P1 P17 D[3:0] P2 P18 Figure 16-17 Memory Format of 4 BPP Display NOTE: AEN: Specifies the transparency value selection bit (with WPALCON: Palette output format) AEN = 0: Selects ALPHA0. AEN = 1: Selects ALPHA1. When it sets per-pixel blending, then this pixel blends with alpha value that AEN selects.. SFR selects the alpha value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B. For more information, refer to the section on "SFR". 16-21 Exynos 4412_UM 16 Display Controller 16.3.3.2.13 2 BPP Display (Palette) Figure 16-18 illustrates the 2 BPP display. ( BYSWP=0 , HWSWP=0 , WSWP= 0 ) D[63: 62] D[ 61:60] D[59:58] 000H P1 P2 P3 008H P 33 P34 P35 … D[57: 56] P4 P 36 D[ 55: 54] P5 P 37 D[ 53:52] P6 P38 D[51:50] P7 P39 D[49:48] P8 P40 000H 008H … D[47: 46] P9 P 41 D[ 45:44] P10 P42 D[43:42] P11 P43 D[41: 40] P 12 P 44 D[ 39: 38] P 13 P 45 D[ 37:36] P14 P46 D[35:34] P15 P47 D[33:32] P16 P48 000H 008H … D[31: 30] P 17 P 49 D[ 29:28] P18 P50 D[27:26] P19 P51 D[25: 24] P 20 P 52 D[ 23: 22] P 21 P 53 D[ 21:20] P22 P54 D[19:18] P23 P55 D[17:16] P24 P56 000H 008H … D[15: 14] P 25 P 57 D[ 13:12] P26 P58 D[11:10] P27 P59 D[9:8] P 28 P 60 D[7:6] P 29 P 61 D[5:4] P30 P62 D[3:2] P31 P63 D[1:0] P32 P64 Figure 16-18 Memory Format of 2 BPP Display NOTE: AEN: Specifies the transparency value selection bit (with WPALCON: Palette output format). AEN = 0: Selects ALPHA0. AEN = 1: Selects ALPHA1. When it sets per-pixel blending, then this pixel blends with alpha value that AEN selects. SFR selects the alpha value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B. For more information, refer to the section on "SFR". 16-22 Exynos 4412_UM 16 Display Controller 16.3.4 Palette Usage The Palette Usage section includes:  Palette Configuration and Format Control  Palette Read/Write 16.3.4.1 Palette Configuration and Format Control The display controller supports 256-color palette to select color mapping. You can select up to 256 colors from 32bit colors using these formats. 256 color palette consists of 256 (depth)  32-bit SPSRAM. Palette supports 8:8:8, 6:6:6, 5:6:5 (R: G: B), and other formats. For Example: See A:5:5:5 format, write palette, as illustrated in Figure 16-20. 1. Connect VD pin to TFT LCD panel (R (5) = VD[23:19], G (5) = VD[15:11], and B (5) = VD[7:3]). 2. AEN bit controls the blending function, enable or disable. 3. Set WPALCON (W1PAL, case window0) register to 0'b101. The 32-bit (8:8:8:8) format has an alpha value directly, without using alpha value register (ALPHA_0/1). Figure 16-19 illustrates the 32 BPP (8:8:8:8) palette data format. INDEX/ Bit Pos. 00 h 01 h …… FFh Number of VD 3 1 32 09 2 8 2 7 2 6 22 54 2 3 2 2 2 1 21 09 1 8 1 7 1 6 11 54 1 3 1 2 1 1 1 0 9 8 7 6 5 43 2 10 ALPHA R RR RR R RR G G G G G GG G B B B B B B B B 7 6 5 43 2 1 0 76 5 4 3 21 0 7 6 5 43 2 10 ALPHA R RR RR R RR G G G G G GG G B B B B B B B B 7 6 5 43 2 1 0 76 5 4 3 21 0 7 6 5 43 2 10 …… …… … …… …… …… ……………… ……… …………… … … …… ……… ALPHA R RR RR R RR G G G G G GG G B B B B B B B B 7 6 5 43 2 1 0 76 5 4 3 21 0 7 6 5 43 2 10 - - - - -- - - 2 3 2 2 21 1 2 1 09 8 1 1 11 7 6 54 111 321 1 0 9 8765 43 2 10 Figure 16-19 32 BPP (8:8:8:8) Palette Data Format 16-23 Exynos 4412_UM Figure 16-20 illustrates the 25 BPP (A: 8:8:8) palette data format. 16 Display Controller INDEX/ Bit Pos. 00 h 01 h …… FFh Number of VD 3 1 32 09 2 8 2 7 2 6 22 54 2 3 2 2 2 1 21 09 1 8 1 7 1 6 11 54 1 3 1 2 1 1 1 0 9 8 7 6 5 43 2 10 - - - - -- - A E N R 7 RR 65 RR 43 R 2 RR G 107 G 6 G 5 G 4 G 3 GG 21 G 0 BB 76 BB B B B B 5 43 2 10 - - - - -- - A E R 7 RR 65 RR 43 R 2 RR G 107 G 6 G 5 G 4 G 3 GG 21 G 0 BB 76 BB B B B B 5 43 2 10 N …… ……… …… ………… ………… …… ……… ……………… ……… ……… - - - - -- - A E N R 7 RR 65 RR 43 R 2 RR G 107 G 6 G 5 G 4 G 3 GG 21 G 0 BB 76 BB B B B B 5 43 2 10 - - - - -- - - 2 3 2 2 2 21 1 09 1 8 1 7 1 11 6 54 1 3 11 21 1 0 9 8 76 5 43 2 10 Figure 16-20 25 BPP (A: 8:8:8) Palette Data Format Figure 16-21 illustrates the 19 BPP (A: 6:6:6) palette data format. INDEX/ Bit Pos. 3 1 32 09 2 8 22 76 2 5 22 43 2 2 22 10 11 98 1 7 11 65 1 4 1 3 111 210 9 8 7 6 5 43 2 1 0 00 h 01 h …… FFh Number of VD - - - - - - - -- - -- - A E N R 5 R 4 RR 32 R 1 R 0 GG 54 GG 32 G 1 GB 05 B 4 B 3 B 2 B 1 B 0 - - - - - - - -- - -- - A E N R 5 R 4 RR 32 R 1 R 0 GG 54 GG 32 G 1 GB 05 B 4 B 3 B 2 B 1 B 0 ……… …… ……… ……… ………… … ……… ……… ……… ……… …… …… - - - - - - - -- - -- - A E N R 5 R 4 RR 32 R 1 R 0 GG 54 GG 32 G 1 GB 05 B 4 B 3 B 2 B 1 B 0 - - - - - - - -- - -- - - 2 3 2 2 2 1 21 09 111 854 1 3 11 21 1 0 7 65 4 32 Figure 16-21 19 BPP (A: 6:6:6) Palette Data Format 16-24 Exynos 4412_UM Figure 16-22 illustrates the 16 BPP (A: 5:5:5) palette data format 16 Display Controller INDEX / Bit Pos . 3322 1098 22 76 22 54 22 32 221 109 11 87 11 65 11 43 1 2 1 1 1 0 9 87 65 43 210 00 h 01 h …… FFh Number of VD - - - - - - - - - - - - - - - - A E N R 4 R 3 R 2 R 1 R 0 GG 43 G 2 G 1 GB 04 B 3 B 2 B 1 B 0 - - - - - - - - - - - - - - - - A E N R 4 R 3 R 2 R 1 R 0 GG 43 G 2 G 1 GB 04 B 3 B 2 B 1 B 0 … … … … … … … … … … … … … …… … … … … … … … … … … … … … … … … … - - - - - - - - - - - - - - - - A E N R 4 R 3 R 2 R 1 R 0 GG 43 G 2 G 1 GB 04 B 3 B 2 B 1 B 0 - - - - - - - - - - - - - - - - - 22 32 2211 1095 11 43 11 21 76 543 Figure 16-22 16 BPP (A: 5:5:5) Palette Data Format 16-25 Exynos 4412_UM 16 Display Controller 16.3.4.2 Palette Read/Write You should not access palette memory when the Vertical Status (VSTATUS) register has an ACTIVE status. You should check the VSTATUS to do Read/Write operation on the palette. 16.3.5 Window Blending This section includes:  Overview of Window Blending  Blending Diagram  Color-Key Function  Blending and Color-Key Function 16.3.5.1 Overview of Window Blending Window blending is the main function of VPRCS module. Display controller comprises of five window layers (win 0 to win 4). Example 16-1 Application The system uses win0 as OS window, full TV screen window, and so on. win1 as small (next channel) TV screen with win2 as menu. win3 as caption. win4 as channel information. win3 and win4 have color limitation while using color index with Color LUT. This feature enhances the system performance by reducing the data rate of total system. Example 16-2 Total Five Windows win0 (base): Local/YCbCr, RGB without palette) win1 (Overlay1): RGB with palette win2 (Overlay2): RGB with palette win3 (Caption): RGB (1/2/4) with 16-level Color LUT win4 (Cursor): RGB (1/2) with 4-level Color LUT Overlay Priority Win4  Win3  Win2  Win1  Win0 Color Key 24-bit RGB format should set the register value to color key register. 16-26 Exynos 4412_UM 16 Display Controller Example 16-3 Blending Equation Win01 (R,G,B) = Win0 (R,G,B)  b1 + Win1 (R,G,B)  a1 Win012 (R/G/B) = Win01 (R/G/B)  b2 + Win2 (R/G/B)  a2 Win0123 (R/G/B) = Win012 (R/G/B)  b3 + Win3 (R/G/B)  a3 WinOut (R/G/B) = Win0123 (R/G/B)  b4 + Win4 (R/G/B)  a4 , where, Win0 (R) = Window 0's Red data, Win0 (G) = Window 0's Green data, Win0 (B) = Window 0's Blue data, Win1 (R) = Window 1's Red data, ... b1 = Background's Data blending equation1 factor, a1 = Foreground's Data blending equation1 factor, b2 = Background's Data blending equation2 factor, a2 = Foreground's Data blending equation2 factor, AR (G,B)01 = AR (G,B)0  q1 + AR (G,B)1  p1 AR (G,B)012 = AR (G,B)01  q2 + AR (G,B)2  p2 AR (G,B)0123 = AR (G,B)012  q3 + AR (G,B)3  p3 , where, AR0 = Window 0's Red blending factor, AG0 = Window 0's Green blending factor, AB0 = Window 0's Blue blending factor, AR1 = Window 1's Red blending factor,... AR01 = Window01's Red blending factor (alpha value blending between AR0 and AR1), AG01 = Window01's Green blending factor (alpha value blending between AG0 and AG1), AB01 = Window01's Blue blending factor (alpha value blending between AB0 and AB1), AR012 = Window012's Red blending factor (alpha value blending between AR01 and AR2), ... q1 = Background's Alpha value blending equation1 factor, p1 = Foreground's Alpha value blending equation1 factor, q2 = Background's Alpha value blending equation2 factor, p2 = Foreground's Alpha value blending equation2 factor,… 16-27 Exynos 4412_UM Figure 16-23 illustrates the blending equation. 16 Display Controller alphaB B alphaA Blending alphaB’ A B’ = axA +bxB B’ alphaB’ = p x alphaA + q x alphaB a/b/p/ q = 0 or 1 or alphaA or 1- alphaA or alphaB or 1- alphaB or A or 1- A or B or 1- B or ALPHA0 ‘a’ is controlled by‘A_ FUNC’ @ BLENDEQ register ‘b’ “ by‘B_ FUNC’ @ BLENDEQ register ‘p’ “ by‘P_ FUNC’ @ BLENDEQ register ‘q’ “ by‘Q_ FUNC’ @ BLENDEQ register Figure 16-23 Blending Equation Example 16-4 Default Blending Equation B' = B  (1 - alphaA) + A  alphaA Alpha value blending> alphaB' = 0 (= alphaB  0 + alphaA  0) 16-28 Exynos 4412_UM 16 Display Controller 16.3.5.2 Blending Diagram The display controller can blend five layers for one pixel at the same time. ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B registers control the alpha value (blending factor), which you can implement for each window layer and color (R, G, B). The example below shows the R (Red) output using ALPHA_R value of each window. All windows have two kinds of alpha blending value: Alpha value that enables transparency (AEN value == 1) Alpha value that disables transparency (AEN value == 0) If you enable WINEN_F and BLD_PIX and disable ALPHA_SEL, then it selects the AR. The equation to select the AR is:  AR = (Pixel (R)'s AEN value == 1'b1) ? Reg (ALPHA1_R): Reg (ALPHA0_R);  AG = (Pixel (G)'s AEN value == 1'b1) ? Reg (ALPHA1_G): Reg (ALPHA0_G);  AB = (Pixel (B)'s AEN value == 1'b1) ? Reg (ALPHA1_B): Reg (ALPHA0_B); (where, BLD_ PIX == 1, ALPHA_SEL == 0) If you enable WINEN_F and disable BLD_PIX, then the ALPHA_SEL ALPHA0 controls the AR. AEN bit information is not used anymore. 16-29 Exynos 4412_UM Figure 16-24 illustrates the blending diagram. 16 Display Controller AR 0 Win 0(R) AR 1 Win 1(R) alphaB B alphaA A Blending 1 AR 1' Win 1'(R) AR 2 Win 2(R) AR 3 Win 3(R) AR 4 Win 4(R) Blending 2 AR 2' Win 2'(R) Blending 3 AR 3' Win 3'(R) Blending 4 OUTPUT (R) Figure 16-24 Blending Diagram Example 16-5 Window Blending Factor Decision Window n's blending factor decision (n = 0, 1, 2, 3, 4). For more information, refer to the section on "SFR". 16-30 Exynos 4412_UM Figure 16-25 illustrates the blending factor decision. ALPHA 0_R ALPHA 1_R DATA Palette AR decision ARn 16 Display Controller Keying AEN BLD_PIX ALPHA _SEL ALPHA _ MUL Figure 16-25 Blending Factor Decision NOTE: If you use DATA[15:12] (BPPMODE_F = b'1110, ARGB4444 format) to blend, then the alpha value is {DATA[15:12], DATA [15:12]} (4-bit  8-bit expanding). 16-31 Exynos 4412_UM 16 Display Controller 16.3.5.3 Color-Key Function The Color-Key function in display controller supports various effects for image mapping. For special functionality, the Color-Key register that specifies the color image of OSD layer is substituted by the background image-either as cursor image or preview image of the camera. Figure 16-26 illustrates the Color-Key function configurations. Window 3 OSD image180 x 100 Window 3 Window 1 BLEND ( ALPHA= 0 xFF ) Window 3 Window 1 Chroma- Key ( KEY_ BLEN ) (KEY_ ALPHA= 0xFF) Window 1 BG image320 x 240 Window 3 Window 1 BLEND ( ALPHA = 0 x7F) Window 1 BLEND ( ALPHA= 0 x 00 ) Window 3 Window 3 Window 1 Chroma- Key (KEY_BLEN) ( KEY_ ALPHA= 0 x7F) Window 1 Chroma- Key (KEY_BLEN ) (KEY_ ALPHA= 0x 00) Figure 16-26 Color-Key Function Configurations Window 3 Window 1 Chroma- Key ( not KEY_BLEN) 16-32 Exynos 4412_UM 16 Display Controller 16.3.5.4 Blending and Color-Key Function The display controller supports simultaneous blending function-with two transparency factors and Color-Key function in the same window. Figure 16-27 illustrates the blending and Color-Key function. Window 0 Window 1 Sub - menu Camera Mail Memo 08:23 Main Menu Alpha 1 (100%) Chroma-key SSuubb --mmeneunu Camera Mail Memo 08:23 Main Menu Alpha 0 (50%) Figure 16-27 Blending and Color-Key Function 16-33 Exynos 4412_UM Figure 16-28 illustrates the blending decision diagram. < Transparency factor Decision > Start KEY_ EN? Y N Color match Y N KEY_ BLEN? Y KEY_ ALPHA Ap N 0 Ap Y DATA[31: 24] Ap BLEN_ NEW N { DATA[ 27:24] , DATA[ 27:24]} Ap Only when‘ARGB’ BLD_ PIX = 1 Y N ALPHA_SEL Y N BPPMODE [3:2 ] = 00 N Palette Y ALPHA_SEL Y ALPHA_1 Ap N ALPHA_0 Ap WxPAL = 111 N Y AEN Y ALPHA_1 Ap N ALPHA_0 Ap DATA [31:24] Ap Ap BLEN_ NEW Ap [ 7:0] App { Ap[7:4], Ap[ 7:4]} App App Only valid @ ( BLD_ PIX= 1 &&ALPHA_ SEL=1 && ( BPPMODE == 1101 or 1110) ) ALPHA_MUL N Y App BLEN_ NEW N App * ( { ALPHA0 [7: 4], ALPHA 0[ 7: 4 ] }) Y App * ALPHA0 Transparency factor End 16 Display Controller < Blending Equation Decision > Start Y KEY_ EN? N Color match Y N KEY_ BLEN ? Y N a = alphaA b = 1- alphaA a = A_FUNC b = B_ FUNC DIRCON Y N Y a = 1 ( max) b =0 a=0 b = 1 ( max) End Data Formatter Data Formatter Transparency Factor Decision Transparency Factor Decision alphaB B alphaA A Blending &’ Chroma- keying alphaB’ B Equation Decision Figure 16-28 Blending Decision Diagram 16-34 Exynos 4412_UM 16.3.6 VTIME Controller Operation VTIME comprises of two blocks, namely:  VTIME_RGB_TV for RGB timing control  VTIME_i80 for indirect i80 interface timing control 16 Display Controller 16.3.6.1 RGB Interface Controller VTIME generates control signals such as RGB_VSYNC, RGB_HSYNC, RGB_VDEN, and RGB_VCLK signal for the RGB interface. You can use these control signals while configuring the VIDTCON0/1/ 2 registers in the VSFR register. You can program configurations of display control registers in the VSFR. Then, the VTIME module generates programmable control signals that support different types of display devices. The RGB_VSYNC signal causes the LCD line pointer to begin at the top of display. The configuration of both HOZVAL field and LINEVAL registers control pulse generation of RGB_VSYNC and RGB_HSYNC. Based on these equations, the size of the LCD panel determines HOZVAL and LINEVAL:  HOZVAL = (Horizontal display size) – 1  LINEVAL = (Vertical display size) – 1 The CLKVAL field in VIDCON0 register controls the rate of RGB_VCLK signal. RGB_VCLK (Hz) = SCLK_FIMDx/(CLKVAL + 1), where CLKVAL  1 where, SCLK_FIMDx (x = 0, 1) Table 16-1 describes the relationship of RGB_VCLK and CLKVAL. The minimum value of CLKVAL is 1.  RGB_VCLK (Hz) = SCLK_FIMDx/(CLKVAL + 1), where CLKVAL  1 where, SCLK_FIMDx (x = 0, 1) CLKVAL 2 3 : 63 Table 16-1 Relation 16 BPP between VCLK and CLKVAL (TFT, Frequency of Video Clock Source = 60 MHz) 60 MHz/X 60 MHz/3 60 MHz/4 : 60 MHz/64 VCLK 20.0 MHz 15.0 MHz : 937.5 kHz VSYNC, VBPD, VFPD, HSYNC, HBPD, HFPD, HOZVAL, and LINEVAL configure RGB_HSYNC and RGB_VSYNC signal. For more information, refer to RGB_VCLK (Hz) = SCLK_FIMDx/(CLKVAL + 1), where CLKVAL  1 where, SCLK_FIMDx (x = 0, 1) The frame rate is RGB_VSYNC signal frequency. The frame rate associates with the field of VSYNC, VBPD, VFPD, LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL registers. Most LCD drivers require their own adequate frame rate. 16-35 Exynos 4412_UM 16 Display Controller The equation to calculate frame rate is: Frame Rate = 1/[{(VSPW + 1) + (VBPD + 1) + (LIINEVAL + 1) + (VFPD + 1)}  {(HSPW + 1) + (HBPD + 1) + (HFPD + 1) + (HOZVAL + 1)}  {(CLKVAL + 1)/(Frequency of Clock source)}] 16-36 Exynos 4412_UM 16 Display Controller 16.3.6.2 i80 Interface Controller VTIME_I80 controls display controller for CPU style LCD Driver IC (LDI). The functions of interface controller are:  Generates I80 Interface Control Signals  CPU style LDI Command Control  Timing Control for VDMA and VDPRCS 16.3.6.3 Output Control Signal Generation VTIME_I80 generates SYS_CS0, SYS_CS1, SYS_WE, and SYS_RS control signals (for Timing Diagram, refer to RGB_VCLK (Hz) = SCLK_FIMDx/(CLKVAL + 1), where CLKVAL  1 where, SCLK_FIMDx (x = 0, 1). SYS_CS0, SYS_CS1, SYS_WE and SYS_RS timing parameters, LCD_CS_SETUP, LCD_WR_SETUP, LCD_WR_ACT, and LCD_WR_HOLD are set through I80IFCONA0 and I80IFCONA1 SFRs. 16.3.6.4 Partial Display Control Although partial display is the main feature of CPU style LDI, VTIME_I80 does not support this function in hardware logic. SFR setting (LINEVAL, HOZVAL, OSD_LeftTopX_F, OSD_LeftTopY_F, OSD_RightBotX_F, OSD_RightBotY_F, PAGEWIDTH, and OFFSIZE) implements partial display function. 16.3.6.5 LDI Command Control LDI receives both command and data. Command specifies an index for selecting the SFR in LDI. In control signal for command and data, only SYS_RS signal has a special function. Usually, SYS_RS has a polarity of „1' for issuing command and vice versa. Display controller has two kinds of command control:  Auto command  Normal command Auto command is issued automatically, that is, without software control and at a pre-defined rate (rate = 2, 4, 6, ... 30). If the rate is equal to 4, then it implies that auto commands are sent to LDI at the end of every four image frames. Normal command: The software control issues Normal command. 16-37 Exynos 4412_UM 16.3.6.6 Interrupt Completion of one frame generates Frame Done Interrupt. 16 Display Controller 16-38 Exynos 4412_UM 16 Display Controller 16.3.7 Virtual Display Display controller supports hardware horizontal or vertical scrolling. If the screen scrolls, then it changes the fields of LCDBASEU and LCDBASEL (Refer to Figure 16-29), but not the values of PAGEWIDTH and OFFSIZE. The size of video buffer in which you store the image should be larger than the LCD panel screen size. Figure 16-29 illustrates the example of scrolling in virtual display. OFFSIZE PAGEWIDTH OFFSIZE LCDBASEU This is the data of line 1 of v irtual screen. This is the data of line 1 of v irtual screen. This is the data of line 2 of v irtual screen. This is the data of line 2 of v irtual screen. This is the data of line 3 of v irtual screen. This is the data of line 3 of v irtual screen. This is the data of line 4 of v irtual screen. This is the data of line 4 of v irtual screen. LINEVAL + 1 This is the data of line 5 of v irtual screen. This is the data of line 5 of v irtual screen. This is the data of line 6 of v irtual screen. This is the data of line 6 of v irtual screen. This is the data of line 7 of v irtual screen. This is the data of line 7 of v irtual screen. This is the data of line 8 of v irtual screen. This is the data of line 8 of v irtual screen. This is the data of line 9 of v irtual screen. This is the data of line 9 of v irtual screen. This is the data of line 10 of v irtual screen. This is the data of line 10 of v irtual screen. View Port (The same size of LCD panel) This is the data of line 11 of v irtual screen. This is the data of line 11 of v irtual screen. Bef ore Scrolling . . . . . . LCDBASEL This is the data of line 1 of v irtual screen. This is the data of line 1 of v irtual screen. This is the data of line 2 of v irtual screen. This is the data of line 2 of v irtual screen. This is the data of line 3 of v irtual screen. This is the data of line 3 of v irtual screen. This is the data of line 4 of v irtual screen. This is the data of line 4 of v irtual screen. This is the data of line 5 of v irtual screen. This is the data of line 5 of v irtual screen. This is the data of line 6 of v irtual screen. This is the data of line 6 of v irtual screen. This is the data of line 7 of v irtual screen. This is the data of line 7 of v irtual screen. This is the data of line 8 of v irtual screen. This is the data of line 8 of v irtual screen. This is the data of line 9 of v irtual screen. This is the data of line 9 of v irtual screen. This is the data of line 10 of v irtual screen. This is the data of line 10 of v irtual screen. This is the data of line 11 of v irtual screen. This is the data of line 11 of v irtual screen. Af ter Scrolling Figure 16-29 Example of Scrolling in Virtual Display 16-39 Exynos 4412_UM 16 Display Controller 16.3.8 RGB Interface Specification RGB Interface Spec includes:  Signals  LCD RGB Interface Timing  Parallel Output  Serial 8-bit Output  Output Configuration Structure 16.3.8.1 Signals Table 16-2 describes the signals. Signal LCD_HSYNC LCD_VSYNC LCD_VCLK LCD_VDEN LCD_VD[0] LCD_VD[1] LCD_VD[2] LCD_VD[3] LCD_VD[4] LCD_VD[5] LCD_VD[6] LCD_VD[7] LCD_VD[8] LCD_VD[9] LCD_VD[10] LCD_VD[11] LCD_VD[12] LCD_VD[13] LCD_VD[14] LCD_VD[15] LCD_VD[16] LCD_VD[17] LCD_VD[18] Table 16-2 RGB Interface Signals of Display Controller In/Out Description O Horizontal Synchronization. Signal O Vertical Synchronization. Signal O LCD Video Clock O Data Enable O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output Display Controller PADs GPIO Control XvHSYNC GPF0CON[0] XvVSYNC GPF0CON[1] XvVCLK GPF0CON[3] XvVDEN GPF0CON[2] XvVD_0 GPF0CON[4] XvVD_1 GPF0CON[5] XvVD_2 GPF0CON[6] XvVD_3 GPF0CON[7] XvVD_4 GPF1CON[0] XvVD_5 GPF1CON[1] XvVD_6 GPF1CON[2] XvVD_7 GPF1CON[3] XvVD_8 GPF1CON[4] XvVD_9 GPF1CON[5] XvVD_10 GPF1CON[6] XvVD_11 GPF1CON[7] XvVD_12 GPF2CON[0] XvVD_13 GPF2CON[1] XvVD_14 GPF2CON[2] XvVD_15 GPF2CON[3] XvVD_16 GPF2CON[4] XvVD_17 GPF2CON[5] XvVD_18 GPF2CON[6] 16-40 Exynos 4412_UM 16 Display Controller Signal LCD_VD[19] LCD_VD[20] LCD_VD[21] LCD_VD[22] LCD_VD[23] In/Out Description O RGB data output O RGB data output O RGB data output O RGB data output O RGB data output Display Controller PADs GPIO Control XvVD_19 GPF2CON[7] XvVD_20 GPF3CON[0] XvVD_21 GPF3CON[1] XvVD_22 GPF3CON[2] XvVD_23 GPF3CON[3] While using RGB interface, the VT_LBLKx bit fields in LCDBLKC_CFG (0x1001_0210) register should be set to RGB Interface out (2'b00), even though you use DSI Video Mode. 16-41 Exynos 4412_UM 16.3.8.2 LCD RGB Interface Timing Figure 16-30 illustrates the LCD RGB interface timing. 16 Display Controller INT_FrSyn VSYNC HSYNC VDEN VBPD+1 VSPW+1 HSYNC VCLK VD VDEN HSPW+1 HBPD+1 1 FRAME LINEVAL+1 1 LINE HOZVAL+1 VFPD+1 HFPD+1 Figure 16-30 LCD RGB Interface Timing 16-42 Exynos 4412_UM 16 Display Controller 16.3.9 LCD Indirect i80 System Interface LCD Indirect i80 System Interface includes:  Signals  Indirect i80 System Interface Write Cycle Timing 16.3.9.1 Signals Table 16-3 describes the signals. Table 16-3 Signal SYS_VD[0] SYS_VD[1] SYS_VD[2] SYS_VD[3] SYS_VD[4] SYS_VD[5] SYS_VD[6] SYS_VD[7] SYS_VD[8] SYS_VD[9] SYS_VD[10] SYS_VD[11] SYS_VD[12] SYS_VD[13] SYS_VD[14] SYS_VD[15] SYS_VD[16] SYS_VD[17] SYS_CS0 SYS_CS1 SYS_WE SYS_OE SYS_RS/SYS_ADD[0] SYS_ST/SYS_ADD[1] LCD Indirect i80 System Interface Signals of Display Controller In/Out Description I/O Data bit[0] I/O Data bit[1] I/O Data bit[2] I/O Data bit[3] I/O Data bit[4] I/O Data bit[5] I/O Data bit[6] I/O Data bit[7] I/O Data bit[8] I/O Data bit[9] I/O Data bit[10] I/O Data bit[11] I/O Data bit[12] I/O Data bit[13] I/O Data bit[14] I/O Data bit[15] I/O Data bit[16] I/O Data bit[17] O Chip select for LCD0 O Chip select for LCD1 O Write enable O Output enable O Address Output[0] O Address Output[1] Display Controller PAD GPIO Control XvVD_0 GPF0CON[4] XvVD_1 GPF0CON[5] XvVD_2 GPF0CON[6] XvVD_3 GPF1CON[7] XvVD_4 GPF1CON[0] XvVD_5 GPF1CON[1] XvVD_6 GPF1CON[2] XvVD_7 GPF1CON[3] XvVD_8 GPF1CON[4] XvVD_9 GPF1CON[5] XvVD_10 GPF1CON[6] XvVD_11 GPF1CON[7] XvVD_12 GPF2CON[0] XvVD_13 GPF2CON[1] XvVD_14 GPF2CON[2] XvVD_15 GPF2CON[3] XvVD_16 GPF2CON[4] XvVD_17 GPF2CON[5] XvHSYNC GPF0CON[0] XvVSYNC GPF0CON[1] XvVCLK GPF0CON[3] XvSYS_OE GPF3CON[5] XvVDEN GPF0CON[2] – Internal Connection 16-43 Exynos 4412_UM 16 Display Controller NOTE: 1. SYS_ST/SYS_ADD[1] is valid in DSI Mode (VIDCON0 [30] = 1) SYS_ADD[1] = SYS_ST: 0 when VDOUT is from Frame SYS_ADD[1] = SYS_ST: 1 when VDOUT is from Command 2. While using RGB interface, set the VT_LBLKx bit fields in LCDBLKC_CFG (0x1001_0210) register to i80 interface out (2'b01), even though you use DSI Command Mode. 16-44 Exynos 4412_UM 16.3.9.2 Indirect i80 System Interface Write Cycle Timing Figure 16-31 illustrates the indirect i80 system interface write cycle timing. 16 Display Controller VCLK (Internal) SYS _ RS SYS _CSn SYS _ WE SYS _ VD LCD _CS _SETUP+1 LCD _WR_SETUP+1 LCD_WR_HOLD +1 LCD_WR_ACT +1 LCD _CS _ SETUP = 0, LCD _ WR _SETUP = 0, LCD _WR _ACT =0 , LCD _WR _ HOLD =0 Figure 16-31 Indirect i80 System Interface Write Cycle Timing 16-45 Exynos 4412_UM 16 Display Controller Table 16-4 describes the timing reference code (XY Definition). Table 16-4 Timing Reference Code (XY Definition) – VD[23] VD[22] VD[21] VD[20] VD[19] VD[18] VD[17] VD[16] VD[15] VD[14] VD[13] VD[12] VD[11] VD[10] VD[9] VD[8] VD[7] VD[6] VD[5] VD[4] VD[3] VD[2] VD[1] VD[0] 24 BPP (888) R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] Parallel RGB 18 BPP (666) R[5] R[4] R[3] R[2] R[1] R[0] – – G[5] G[4] G[3] G[2] G[1] G[0] – – B[5] B[4] B[3] B[2] B[1] B[0] – – 16 BPP (565) R[4] R[3] R[2] R[1] R[0] – – – G[5] G[4] G[3] G[2] G[1] G[0] – – B[4] B[3] B[2] B[1] B[0] – – – Serial RGB 24 BPP (888) 18 BPP (666) D[7] D[5] D[6] D[4] D[5] D[3] D[4] D[2] D[3] D[1] D[2] D[0] D[1] – D[0] – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 16-46 Exynos 4412_UM 16 Display Controller 16.4 I/O Description Table 16-5 describes the I/O. Table 16-5 I/O Signals of Display Controller Signal LCD_HSYNC LCD_VSYNC LCD_VCLK LCD_VDEN LCD_VD[23:0] SYS_VD[17:0] SYS_CS0 SYS_CS1 SYS_WE SYS_OE SYS_RS/ SYS_ADD[0] VSYNC_LDI LCD_FRM In/Out Out Out Out Out Out In/Out Out Out Out Out Out Out Out Description PAD for Display Controller Horizontal Synchronization. Signal XvHSYNC Vertical Synchronization. Signal XvVSYNC LCD Video Clock XvVCLK Data Enable XvVDEN RGB Data Output XvVD_23 to XvVD_0 Data to/from Display Controller from/to Display Module XvVD_17 to XvVD_0 Chip select for LCD0 XvHSYNC Chip select for LCD1 XvVSYNC Write Enable XvVCLK Output Enable XvSYS_OE Address Output SYS_ADD[0] is Register/State select XvVDEN VSYNC signal for Vsync Interface (2) XvVSYNC_LDI Frame Synchronization Signal for general use (3) XpwmTout_0 Type (1) Muxed Muxed Muxed Muxed Muxed Muxed Muxed Muxed Muxed Muxed Muxed Muxed Muxed NOTE: 1. Type field indicates type (or kind) of the pad whether it is dedicated to a signal or connected to multiplexed signals. 2. VSYNCEN register controls VSYNC_LD signal. 3. FRMEN control register controls LCD_FRM signal. 16-47 Exynos 4412_UM 16.5 Register Description Overview The registers you can use to configure display controller are: 1. VIDCON0: Configures video output format and displays enable/disable. 2. VIDCON1: Specifies RGB I/F control signal. 3. VIDCON2: Specifies output data format control. 4. VIDCON3: Specifies image enhancement control. 5. I80IFCONx: Specifies CPU interface control signal. 6. VIDTCONx: Configures video output timing and determines the size of display. 7. WINCONx: Specifies each window feature setting. 8. VIDOSDxA, VIDOSDxB: Specifies window position setting. 9. VIDOSDxC, D: Specifies On Screen Display (OSD) size setting. 10. VIDWxALPHA0/1: Specifies alpha value setting. 11. BLENDEQx: Specifies blending equation setting. 12. VIDWxxADDx: Specifies source image address setting. 13. WxKEYCONx: Specifies color key setting register. 14. WxKEYALPHA: Specifies color key alpha value setting. 15. WINxMAP: Specifies window color control. 16. GAMMALUT_xx: Specifies gamma value setting. 17. COLORGAINCON: Specifies color gain value setting. 18. HUExxx: Specifies Hue coefficient and offset value setting. 19. WPALCON: Specifies palette control register. 20. WxRTQOSCON: Specifies RTQoS control register. 21. WxPDATAxx: Specifies window palette data of each index. 22. SHDOWCON: Specifies shadow control register. 23. WxRTQOSCON: Specifies QoS control register. 16 Display Controller 16-48 Exynos 4412_UM 16 Display Controller 16.5.1 Register Map Summary  Base Address = 0x11C0_0000. Register Control Register VIDCON0 VIDCON1 VIDCON2 VIDCON3 VIDTCON0 VIDTCON1 VIDTCON2 VIDTCON3 WINCON0 WINCON1 WINCON2 WINCON3 WINCON4 SHADOWCON WINCHMAP2 VIDOSD0A VIDOSD0B VIDOSD0C VIDOSD1A VIDOSD1B VIDOSD1C VIDOSD1D VIDOSD2A VIDOSD2B VIDOSD2C VIDOSD2D VIDOSD3A VIDOSD3B VIDOSD3C VIDOSD4A VIDOSD4B VIDOSD4C VIDW00ADD0B0 Offset Description Reset Value 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x003C 0x0040 0x0044 0x0048 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x0080 0x0084 0x0088 0x00A0 Specifies video control 0 register. Specifies video control 1 register. Specifies video control 2 register. Specifies video control 3 register. Specifies video time control 0 register. Specifies video time control 1 register. Specifies video time control 2 register. Specifies video time control 3 register. Specifies window control 0 register. Specifies window control 1 register. Specifies window control 2 register. Specifies window control 3 register. Specifies window control 4 register. Specifies window shadow control register. Specifies window and channel mapping control register. Specifies video window 0's position control register. Specifies video window 0's position control register. Specifies video window 0's size control register. Specifies video window 1's position control register. Specifies video window 1's position control register Specifies video window 1's alpha control register. Specifies video window 1's size control register. Specifies video window 2's position control register. Specifies video window 2's position control register. Specifies video window 2's alpha control register. Specifies video window 2's size control register. Specifies video window 3's position control register. Specifies video window 3's position control register. Specifies video window 3's alpha control register. Specifies video window 4's position control register. Specifies video window 4's position control register. Specifies video window 4's alpha control register. Specifies window 0's buffer start address register, buffer 0. 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x7D51_7D51 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 16-49 Exynos 4412_UM 16 Display Controller Register VIDW00ADD0B1 VIDW00ADD0B2 VIDW01ADD0B0 VIDW01ADD0B1 VIDW01ADD0B2 VIDW02ADD0B0 VIDW02ADD0B1 VIDW02ADD0B2 VIDW03ADD0B0 VIDW03ADD0B1 VIDW03ADD0B2 VIDW04ADD0B0 VIDW04ADD0B1 VIDW04ADD0B2 VIDW00ADD1B0 VIDW00ADD1B1 VIDW00ADD1B2 VIDW01ADD1B0 VIDW01ADD1B1 VIDW01ADD1B2 VIDW02ADD1B0 VIDW02ADD1B1 VIDW02ADD1B2 VIDW03ADD1B0 VIDW03ADD1B1 VIDW03ADD1B2 VIDW04ADD1B0 VIDW04ADD1B1 VIDW04ADD1B2 VIDW00ADD2 VIDW01ADD2 VIDW02ADD2 VIDW03ADD2 VIDW04ADD2 VIDINTCON0 VIDINTCON1 W1KEYCON0 Offset 0x00A4 0x20A0 0x00A8 0x00AC 0x20A8 0x00B0 0x00B4 0x20B0 0x00B8 0x00BC 0x20B8 0x00C0 0x00C4 0x20C0 0x00D0 0x00D4 0x20D0 0x00D8 0x00DC 0x20D8 0x00E0 0x00E4 0x20E0 0x00E8 0x00EC 0x20E8 0x00F0 0x00F4 0x20F0 0x0100 0x0104 0x0108 0x010C 0x0110 0x0130 0x0134 0x0140 Description Specifies window 0's buffer start address register, buffer 1. Specifies window 0's buffer start address register, buffer 2. Specifies window 1's buffer start address register, buffer 0. Specifies window 1's buffer start address register, buffer 1. Specifies window 1's buffer start address register, buffer 2. Specifies window 2's buffer start address register, buffer 0. Specifies window 2's buffer start address register, buffer 1. Specifies window 2's buffer start address register, buffer 2. Specifies window 3's buffer start address register, buffer 0. Specifies window 3's buffer start address register, buffer 1. Specifies window 3's buffer start address register, buffer 2. Specifies window 4's buffer start address register, buffer 0. Specifies window 4's buffer start address register, buffer 1. Specifies window 4's buffer start address register, buffer 2. Specifies window 0's buffer end address register, buffer 0. Specifies window 0's buffer end address register, buffer 1. Specifies window 0's buffer end address register, buffer 2. Specifies window 1's buffer end address register, buffer 0. Specifies window 1's buffer end address register, buffer 1. Specifies window 1's buffer end address register, buffer 2. Specifies window 2's buffer end address register, buffer 0. Specifies window 2's buffer end address register, buffer 1. Specifies window 2's buffer end address register, buffer 2. Specifies window 3's buffer end address register, buffer 0. Specifies window 3's buffer end address register, buffer 1. Specifies window 3's buffer end address register, buffer 2. Specifies window 4's buffer end address register, buffer 0. Specifies window 4's buffer end address register, buffer 1. Specifies window 4's buffer end address register, buffer 2. Specifies window 0's buffer size register. Specifies window 1's buffer size register. Specifies window 2's buffer size register. Specifies window 3's buffer size register. Specifies window 4's buffer size register. Specifies video interrupt control register. Specifies video interrupt pending register. Specifies color key control register. Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 16-50 Exynos 4412_UM 16 Display Controller Register W1KEYCON1 W2KEYCON0 W2KEYCON1 W3KEYCON0 W3KEYCON1 W4KEYCON0 W4KEYCON1 W1KEYALPHA W2KEYALPHA W3KEYALPHA W4KEYALPHA DITHMODE WIN0MAP WIN1MAP WIN2MAP WIN3MAP WIN4MAP WPALCON_H WPALCON_L TRIGCON I80IFCONA0 I80IFCONA1 I80IFCONB0 I80IFCONB1 COLORGAINCON LDI_CMDCON0 LDI_CMDCON1 SIFCCON0 SIFCCON1 SIFCCON2 HUECOEF_CR_1 HUECOEF_CR_2 HUECOEF_CR_3 HUECOEF_CR_4 HUECOEF_CB_1 HUECOEF_CB_2 HUECOEF_CB_3 Offset 0x0144 0x0148 0x014C 0x0150 0x0154 0x0158 0x015C 0x0160 0x0164 0x0168 0x016C 0x0170 0x0180 0x0184 0x0188 0x018C 0x0190 0x019C 0x01A0 0x01A4 0x01B0 0x01B4 0x01B8 0x01BC 0x01C0 0x01D0 0x01D4 0x01E0 0x01E4 0x01E8 0x01EC 0x01F0 0x01F4 0x01F8 0x01FC 0x0200 0x0204 Description Specifies color key value (transparent value) register. Specifies color key control register. Specifies color key value (transparent value) register. Specifies color key control register. Specifies color key value (transparent value) register. Specifies color key control register. Specifies color key value (transparent value) register. Specifies color key alpha value register. Specifies color key alpha value register. Specifies color key alpha value register. Specifies color key alpha value register. Specifies dithering mode register. Specifies window 0's color control. Specifies window 1's color control. Specifies window 2's color control. Specifies window 3's color control. Specifies window 4's color control. Specifies window palette control register. Specifies window palette control register. Specifies i80/ RGB trigger control register. Specifies i80 interface control 0 for main LDI. Specifies i80 interface control 0 for sub LDI. Specifies i80 interface control 1 for main LDI. Specifies i80 interface control 1 for sub LDI. Specifies color gain control register. Specifies i80 interface LDI command control 0. Specifies i80 interface LDI command control 1. Specifies LCD i80 system interface command control 0. Specifies LCD i80 system interface command control 1. Specifies LCD i80 system interface command control 2. Specifies hue coefficient control register. Specifies hue coefficient control register. Specifies hue coefficient control register. Specifies hue coefficient control register. Specifies hue coefficient control register. Specifies hue coefficient control register. Specifies hue coefficient control register. Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x1004_0100 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x????_???? 0x0100_0100 0x0000_0000 0x0000_0000 0x0100_0100 0x0100_0100 0x0000_0000 0x0000_0000 16-51 Exynos 4412_UM 16 Display Controller Register Offset Description HUECOEF_CB_4 0x0208 Specifies hue coefficient control register. HUEOFFSET 0x020C Specifies hue offset control register. VIDW0ALPHA0 0x021C Specifies window 0's alpha value 0 register. VIDW0ALPHA1 0x0220 Specifies window 0's alpha value 1 register. VIDW1ALPHA0 0x0224 Specifies window 1's alpha value 0 register. VIDW1ALPHA1 0x0228 Specifies window 1's alpha value 1 register. VIDW2ALPHA0 0x022C Specifies window 2's alpha value 0 register. VIDW2ALPHA1 0x0230 Specifies window 2's alpha value 1 register. VIDW3ALPHA0 0x0234 Specifies window 3's alpha value 0 register. VIDW3ALPHA1 0x0238 Specifies window 3's alpha value 1 register. VIDW4ALPHA0 0x023C Specifies window 4's alpha value 0 register. VIDW4ALPHA1 0x0240 Specifies window 4's alpha value 1 register. BLENDEQ1 0x0244 Specifies window 1's blending equation control register. BLENDEQ2 0x0248 Specifies window 2's blending equation control register. BLENDEQ3 0x024C Specifies window 3's blending equation control register. BLENDEQ4 0x0250 Specifies window 4's blending equation control register. BLENDCON 0x0260 Specifies blending control register. W0RTQOSCON 0x0264 Specifies window 0's RTQOS control register. W1RTQOSCON 0x0268 Specifies window 1's RTQOS control register. W2RTQOSCON 0x026C Specifies window 2's RTQOS control register. W3RTQOSCON 0x0270 Specifies window 3's RTQOS control register. W4RTQOSCON 0x0274 Specifies window 4's RTQOS control register. LDI_CMD0 0x0280 Specifies i80 interface LDI command 0. LDI_CMD1 0x0284 Specifies i80 interface LDI command 1. LDI_CMD2 0x0288 Specifies i80 interface LDI command 2. LDI_CMD3 0x028C Specifies i80 interface LDI command 3. LDI_CMD4 0x0290 Specifies i80 interface LDI command 4. LDI_CMD5 0x0294 Specifies i80 interface LDI command 5. LDI_CMD6 0x0298 Specifies i80 interface LDI command 6. LDI_CMD7 0x029C Specifies i80 interface LDI command 7. LDI_CMD8 0x02A0 Specifies i80 interface LDI command 8. LDI_CMD9 0x02A4 Specifies i80 interface LDI command 9. LDI_CMD10 0x02A8 Specifies i80 interface LDI command 10. LDI_CMD11 0x02AC Specifies i80 interface LDI command 11. Gamma LUT Data for 64 Step Mode GAMMALUT_01_00 0x037C Specifies gamma LUT data of the index 0, 1. GAMMALUT_03_02 0x0380 Specifies gamma LUT data of the index 2, 3. Reset Value 0x0100_0100 0x0180_0080 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_00c2 0x0000_00c2 0x0000_00c2 0x0000_00c2 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0010_0000 0x0030_0020 16-52 Exynos 4412_UM 16 Display Controller Register Offset Description GAMMALUT_05_04 0x0384 Specifies gamma LUT data of the index 4, 5. GAMMALUT_07_06 0x0388 Specifies gamma LUT data of the index 6, 7. GAMMALUT_09_08 0x038C Specifies gamma LUT data of the index 8, 9. GAMMALUT_11_10 0x0390 Specifies gamma LUT data of the index 10, 11. GAMMALUT_13_12 0x0394 Specifies gamma LUT data of the index 12, 13. GAMMALUT_15_14 0x0398 Specifies gamma LUT data of the index 14, 15. GAMMALUT_17_16 0x039C Specifies gamma LUT data of the index 16, 17. GAMMALUT_19_18 0x03A0 Specifies gamma LUT data of the index 18, 19. GAMMALUT_21_20 0x03A4 Specifies gamma LUT data of the index 20, 21. GAMMALUT_23_22 0x03A8 Specifies gamma LUT data of the index 22, 23. GAMMALUT_25_24 0x03AC Specifies gamma LUT data of the index 24, 25. GAMMALUT_27_26 0x03B0 Specifies gamma LUT data of the index 26, 27. GAMMALUT_29_28 0x03B4 Specifies gamma LUT data of the index 28, 29. GAMMALUT_31_30 0x03B8 Specifies gamma LUT data of the index 30, 31. GAMMALUT_33_32 0x03BC Specifies gamma LUT data of the index 32, 33. GAMMALUT_35_34 0x03C0 Specifies gamma LUT data of the index 34, 35. GAMMALUT_37_36 0x03C4 Specifies gamma LUT data of the index 36, 37. GAMMALUT_39_38 0x03C8 Specifies gamma LUT data of the index 38, 39. GAMMALUT_41_40 0x03CC Specifies gamma LUT data of the index 40, 41. GAMMALUT_43_42 0x03D0 Specifies gamma LUT data of the index 42, 43. GAMMALUT_45_44 0x03D4 Specifies gamma LUT data of the index 44, 45. GAMMALUT_47_46 0x03D8 Specifies gamma LUT data of the index 46, 47. GAMMALUT_49_48 0x03DC Specifies gamma LUT data of the index 48, 49. GAMMALUT_51_50 0x03E0 Specifies gamma LUT data of the index 50, 51. GAMMALUT_53_52 0x03E4 Specifies gamma LUT data of the index 52, 53. GAMMALUT_55_54 0x03E8 Specifies gamma LUT data of the index 54, 55. GAMMALUT_57_56 0x03EC Specifies gamma LUT data of the index 56, 57. GAMMALUT_59_58 0x03F0 Specifies gamma LUT data of the index 58, 59. GAMMALUT_61_60 0x03F4 Specifies gamma LUT data of the index 60, 61. GAMMALUT_63_62 0x03F8 Specifies gamma LUT data of the index 62, 63. GAMMALUT_xx_64 0x03FC Specifies gamma LUT data of the index 64. Gamma LUT Data for 16 Step Mode GAMMALUT_R_1_0 0X037C Specifies gamma RED LUT data of the index 0, 1. GAMMALUT_R_3_2 0X0380 Specifies gamma RED data of the index 2, 3. GAMMALUT_R_5_4 0X0384 Specifies gamma RED data of the index 4, 5. GAMMALUT_R_7_6 0X0388 Specifies gamma RED data of the index 6, 7. GAMMALUT_R_9_8 0X038C Specifies gamma RED data of the index 8, 9. Reset Value 0x0050_0040 0x0070_0060 0x0090_0080 0x00B0_00A0 0x00D0_00C0 0x00F0_00E0 0x0110_0100 0x0130_0120 0x0150_0140 0x0170_0160 0x0190_0180 0x01B0_01A0 0x01F0_01C0 0x01F0_01E0 0x0210_0200 0x0230_0220 0x0250_0240 0x0270_0260 0x0290_0280 0x02B0_02A0 0x02D0_02C0 0x02F0_02E0 0x0310_0300 0x0330_0320 0x0350_0340 0x0370_0360 0x0390_0380 0x03B0_03A0 0x03D0_03C0 0x03F0_03E0 0x0000_0400 0X0010_0000 0X0030_0020 0X0050_0040 0X0070_0060 0X0090_0080 16-53 Exynos 4412_UM 16 Display Controller Register Offset GAMMALUT _R_11_10 0X0390 GAMMALUT _R_13_12 0X0394 GAMMALUT _R_15_14 0X0398 GAMMALUT_R_16 0X039C GAMMALUT_R_1_0 0X03A0 GAMMALUT_R_3_2 0X03A4 GAMMALUT_R_5_4 0X03A8 GAMMALUT_R_7_6 0X03AC GAMMALUT_R_9_8 0X03B0 GAMMALUT _R_11_10 0X03B4 GAMMALUT _R_13_12 0X03B8 GAMMALUT _R_15_14 0X03BC GAMMALUT_R_16 0X03C0 GAMMALUT_R_1_0 0X03C4 GAMMALUT_R_3_2 0X03C8 GAMMALUT_R_5_4 0X03CC GAMMALUT_R_7_6 0X03D0 GAMMALUT_R_9_8 0X03D4 GAMMALUT _R_11_10 0X03D8 GAMMALUT _R_13_12 0X03DC GAMMALUT _R_15_14 0X03E0 GAMMALUT _R_16 0X03E4 RSVD 0X03E8 RSVD 0X03EC RSVD 0X03F0 RSVD 0X03F4 RSVD 0X03F8 RSVD 0X03FC Shadow Windows Control Description Specifies gamma RED data of the index 10, 11. Specifies gamma RED data of the index 12, 13. Specifies gamma RED data of the index 14, 15. Specifies gamma RED data of the index 16. Specifies gamma GREEN LUT data of the index 0, 1. Specifies gamma GREEN data of the index 2, 3. Specifies gamma GREEN data of the index 4, 5. Specifies gamma GREEN data of the index 6, 7. Specifies gamma GREEN data of the index 8, 9. Specifies gamma GREEN data of the index 10, 11. Specifies gamma GREEN data of the index 12, 13. Specifies gamma GREEN data of the index 14, 15. Specifies gamma GREEN data of the index 16. Specifies gamma BLUE data of the index 0, 1. Specifies gamma BLUE data of the index 2, 3. Specifies gamma BLUE data of the index 4, 5. Specifies gamma BLUE data of the index 6, 7. Specifies gamma BLUE data of the index 8, 9. Specifies gamma BLUE data of the index 10, 11. Specifies gamma BLUE data of the index 12, 13. Specifies gamma BLUE data of the index 14, 15. Specifies gamma BLUE data of the index 16 Does not use. Does not use. Does not use. Does not use. Does not use. Does not use. Reset Value 0X00B0_00A0 0X00D0_00C0 0X00F0_00E0 0X0110_0100 0X0130_0120 0X0150_0140 0X0170_0160 0X0190_0180 0X01B0_01A0 0X01D0_01C0 0X01F0_01E0 0X0210_0200 0X0230_0220 0X0250_0240 0X0270_0260 0X0290_0280 0X02B0_02A0 0X02D0_02C0 0X02F0_02E0 0X0310_0300 0X0330_0320 0X0350_0340 0X0370_0360 0X0390_0380 0X03B0_03A0 0X03D0_03C0 0X03F0_03E0 0X0000_0400 16-54 Exynos 4412_UM 16 Display Controller Register SHD_VIDW00ADD0 SHD_VIDW01ADD0 SHD_VIDW02ADD0 SHD_VIDW03ADD0 SHD_VIDW04ADD0 SHD_VIDW00ADD1 SHD_VIDW01ADD1 SHD_VIDW02ADD1 SHD_VIDW03ADD1 SHD_VIDW04ADD1 SHD_VIDW00ADD2 SHD_VIDW01ADD2 SHD_VIDW02ADD2 SHD_VIDW03ADD2 SHD_VIDW04ADD2 Offset 0x40A0 0x40A8 0x40B0 0x40B8 0x40C0 0x40D0 0x40D8 0x40E0 0x40E8 0x40F0 0x4100 0x4104 0x4108 0x410C 0x4110 Description Specifies window 0's buffer start address register (shadow). Specifies window 1's buffer start address register (shadow). Specifies window 2's buffer start address register (shadow). Specifies window 3's buffer start address register (shadow). Specifies window 4's buffer start address register (shadow). Specifies window 0's buffer end address register (shadow) Specifies window 1's buffer end address register (shadow) Specifies window 2's buffer end address register (shadow). Specifies window 3's buffer end address register (shadow). Specifies window 4's buffer end address register (shadow). Specifies window 0's buffer size register (shadow). Specifies window 1's buffer size register (shadow). Specifies window 2's buffer size register (shadow). Specifies window 3's buffer size register (shadow). Specifies window 4's buffer size register (shadow). Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 16-55 Exynos 4412_UM 16 Display Controller 16.5.2 Palette Memory  Base Address = 0x11C0_0000 Register Win0 PalRam Win1 PalRam Win2 PalRam Win3 PalRam Win4 PalRam Start Address 0x2400 (0x0400) 0x2800 (0x0800) 0x2C00 0x3000 0x3400 End Address 0x27FC (0x07FC) 0x2BFC (0x0BFC) 0x2FFC 0x33FC 0x37FC Description Specifies 0 to 255 entry palette data. Specifies 0 to 255 entry palette data. Specifies 0 to 255 entry palette data. Specifies 0 to 255 entry palette data. Specifies 0 to 255 entry palette data. Reset Value Undefined Undefined Undefined Undefined Undefined 16-56 Exynos 4412_UM 16 Display Controller 16.5.3 Control Register 16.5.3.1 VIDCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x0000, Reset Value = 0x0000_0000 Name RSVD DSI_EN RSVD VIDOUT L1_DATA16 L0_DATA16 RSVD RGSPSEL Bit [31] [30] [29] [28:26] [25:23] [22:20] [19] [18] Type – RW – RW RW RW – RW Description Reserved NOTE: This bit should be set to 0. Enables MIPI DSI. 0 = Disables 1 = Enables (i80 24-bit data interface, SYS_ADD[1]) Reserve NOTE: This bit should be set to 0. Determines output format of Video Controller. 000 = RGB interface 001 = Reserved 010 = Indirect i80 interface for LDI0 011 = Indirect i80 interface for LDI1 100 = Write-Back interface and RGB interface 101 = Reserved 110 = WB Interface and i80 interface for LDI0 111 = WB Interface and i80 interface for LDI1 Selects output data format mode of indirect i80 interface (LDI1). (VIDOUT[1:0] == 2'b11) 000 = 16-bit mode (16 BPP) 001 = 16 + 2-bit mode (18 BPP) 010 = 9 + 9-bit mode (18 BPP) 011 = 16 + 8-bit mode (24 BPP) 100 = 18-bit mode (18 BPP) 101 = 8 + 8-bit mode (16 BPP) Selects output data format mode of indirect i80 interface (LDI0). (VIDOUT[1:0] == 2'b10) 000 = 16-bit mode (16 BPP) 001 = 16 + 2-bit mode (18 BPP) 010 = 9 + 9-bit mode (18 BPP) 011 = 16 + 8-bit mode (24 BPP) 100 = 18-bit mode (18 BPP) 101 = 8 + 8-bit mode (16 BPP) Reserved NOTE: This bit should be set to 0. Selects display mode (VIDOUT[1:0] == 2'b00). 0 = RGB parallel format 1 = RGB serial format Selects the display mode (VIDOUT[1:0] ! = 2'b00). Reset Value 0 0 0 000 000 000 0 0 16-57 Exynos 4412_UM 16 Display Controller Name PNRMODE CLKVALUP RSVD CLKVAL_F VCLKFREE RSVD ENVID ENVID_F Bit Type Description 0 = RGB parallel format Controls inverting RGB_ORDER (atVIDCON3). 0 = Normal: RGBORDER[2] atVIDCON3 [17] RW 1 = Invert: to RGBORDER[2] atVIDCON3 NOTE: You can use this bit for the previous version of FIMD. You do not have to use this bit if you use RGB_ORDER atVIDCON3 register. Selects CLKVAL_F update timing control. [16] RW 0 = Always 1 = Start of a frame (only once per frame) [15:14] – Reserved [13:6] Determines rates of VCLK and CLKVAL[7:0]. RW VCLK = FIMD  SCLK/(CLKVAL+1), where CLKVAL  1 NOTE: The maximum frequency of VCLK is 80 MHz. (80 MHz for Display Controller) Controls VCLK Free Run (only valid at RGB IF mode). [5] RW 0 = Normal mode (controls using ENVID) 1 = Free-run mode Reserved [4:2] – NOTE: This bit should be set to 0. Enables/disables video output and logic immediately. [1] RW 0 = Disables the video output and display control signal 1 = Enables the video output and display control signal Enables/disables video output and logic at current frame end. 0 = Disables the video output and display control signal [0] RW 1 = Enables the video output and display control signal If this bit is set to "on" and "off", then "H" is Read and enables the video controller until the end of current frame. (NOTE) NOTE: Display On: ENVID and ENVID_F are set to "1". Direct Off: ENVID and ENVID_F are set to "0" simultaneously. Per Frame Off: ENVID_F is set to "0" and ENVID is set to "1". Reset Value 00 0 0 0 0 0x0 0 0 Caution: 1 = If VIDCON0 is set for Per Frame Off in interlace mode, then the value of INTERLACE_F should be set to "0" in the same time. 2 = If display controller is off using direct off, then it is impossible to turn on the display controller without reset. 16-58 Exynos 4412_UM 16 Display Controller 16.5.3.2 VIDCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x0004, Reset Value = 0x0000_0000 Name LINECNT (read only) FSTATUS VSTATUS RSVD FIXVCLK RSVD IVCLK IHSYNC IVSYNC IVDEN RSVD Bit [26:16] [15] [14:13] [12:11] [10:9] [8] [7] [6] [5] [4] [3:0] Type RW RW RW – RW – RW RW RW RW RW Description Provides status of the line counter (Read only). Up count from 0 to LINEVAL. Specifies Field Status (Read only). 0 = ODD Field 1 = EVEN Field Specifies Vertical Status (Read only). 00 = VSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch Reserved Specifies VCLK hold scheme at data under-flow. 00 = VCLK hold 01 = VCLK running 11 = VCLK running and disables VDEN Reserved Controls polarity of the VCLK active edge. 0 = Fetches video data at VCLK falling edge 1 = Fetches video data at VCLK rising edge Specifies HSYNC pulse polarity. 0 = Normal 1 = Inverted Specifies VSYNC pulse polarity. 0 = Normal 1 = Inverted Specifies VDEN signal polarity. 0 = Normal 1 = Inverted Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0x0 16-59 Exynos 4412_UM 16 Display Controller 16.5.3.3 VIDCON2  Base Address = 0x11C0_0000  Address = Base Address + 0x0008, Reset Value = 0x0000_0000 Name RSVD RGB_SKIP_EN RSVD RGB_DUMMY _LOC RGB_DUMMY _EN RSVD RGB_ORDER_E RGB_ORDER_O Bit [31:28] [27] [26] [25] [24] [23:22] [21:19] [18:16] Type – RW – RW RW – RW RW Description Reserved Enables RGB skip mode. (Only where RGBSPSEL == 1'b0). 0 = Disables 1 = Enables Reserved Controls RGB dummy insertion location. (Only where RGBSPSEL == 1'b1 and RGB_DUMMY_EN == 1'b1) 0 = Last (fourth) position 1 = First position Enables RGB dummy insertion mode. (Only where RGBSPSEL == 1'b1) 0 = Disables 1 = Enables Reserved NOTE: This bit should be set to 0. Controls RGB interface output order. (Even line, line number 2, 4, 6, 8.), where, RGBSPSEL== 1'b0 000 = RGB 001 = GBR 010 = BRG 100 = BGR 101 = RBG 110 = GRB where, (RGBSPSEL == 1'b1) or (RGBSPSEL == 1'b0 and RGB_SKIP_EN = 1'b1) 000 = R  G  B 001 = G  B  R 010 = B  R  G 100 = B  G  R 101 = R  B  G 110 = G  R B NOTE: PNR0[0] atVIDCON0 should be set to 0, when you use RGB_ORDER_O[2:0] at VIDCON3 register. Controls RGB interface output order (Odd Line, line number 1, 3, 5, 7.), where, RGBSPSEL == 1'b0 000 = RGB 001 = GBR 010 = BRG 100 = BGR Reset Value 0 0 0 0 0 0 0 0 16-60 Exynos 4412_UM 16 Display Controller Name RSVD TVFORMATSEL RSVD OrgYCbCr YUVOrd RSVD WB_FRAME _SKIP Bit [15:14] [13:12] [11:9] [8] [7] [6:5] [4:0] Type – RW – RW RW – RW Description 101 = RBG 110 = GRB where, (RGBSPSEL == 1'b1) or (RGBSPSEL == 1'b0 and RGB_SKIP_EN = 1'b1) 000 = R  G B 001 = G  B R 010 = B  R  G 100 = B  G  R 101 = R  B  G 110 = G  R  B NOTE: PNR0[0] at VIDCON0 should be set to 0, when you use RGB_ORDER_E[2:0] at VIDCON3 register. Reserved NOTE: This bit should be set to 1. Specifies output format of YUV data. 00 = Reserved 01 = YUV422 1x = YUV444 Reserved Specifies order of YUV data. 0 = Y – CbCr 1 = CbCr – Y Specifies order of Chroma data. 0 = Cb – Cr 1 = Cr – Cb Reserved Controls WB frame skip rate. The maximum rate is up to 1:30 [only where (VIDOUT[2:0] == 3'b001 or 3'b100 TV encoder interface), (INTERLACE_F == 1'b0) and (TV422 or TVRGB output)]. 00000 = No skip = 1:1 00001 = Skip rate = 1:2 00010 = Skip rate = 1:3 … 11101 = Skip rate = 1: 0 1111x = Reserved Reset Value 0 0 0 0 0 0 0 16-61 Exynos 4412_UM 16 Display Controller 16.5.3.4 VIDCON3  Base Address = 0x11C0_0000  Address = Base Address + 0x000C, Reset Value = 0x0000_0000 Name RSVD RSVD CG_ON RSVD GM_ON GM_MODE HUE_CSC _F_Narrow HUE_CSC _F_EQ709 HUE_CSC _F_ON RSVD HUE_CSC _B_Narrow HUE_CSC _B_EQ709 HUE_CSC _B_ON HUE_ON RSVD PC_DIR Bit [31:21] [20:19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6:2] [1] Type – – RW – RW RW RW RW RW – RW RW RW RW – RW Description Reserved NOTE: This bit should be set to 0. Reserved Enables Control Color Gain. 0 = Disables (bypass) 1 = Enables Reserved Enables Control Gamma. 0 = Disables (bypass) 1 = Enables Gamma mode selection 0 = Applies 64 step identical value to all R, G, B data 1 = Applies 16 step independent value to each R, G, B data Controls HUE CSC_F Narrow/ Wide. 0 = Wide 1 = Narrow Controls HUE_CSC_F parameter. 0 = Equation. 601 1 = Equation. 709 Enables HUE_CSC_F. 0 = Disables 1 = Enables (when HUE_ON == 1'b1) Reserved. Controls HUE CSC_B Narrow/ Wide. 0 = Wide 1 = Narrow Controls HUE_CSC_B parameter. 0 = Equation 601 1 = Equation 709 Enables HUE_CSC_B. 0 = Disables 1 = Enables (when HUE_ON == 1'b1) Enables Control Hue. 0 = Disables (bypass) 1 = Enables Reserved NOTE: This bit should be set to 0. Controls Pixel Compensation direction. Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16-62 Exynos 4412_UM 16 Display Controller Name PC_ON Bit Type Description 0 = + 0.5 (positive) 1 = – 0.5 (negative) Enables Pixel Compensation. [3:0] RW 0 = Disables 1 = Enables NOTE: PC_ON == 1'b1 compensates the TV output data. Reset Value 0x0 16-63 Exynos 4412_UM 16 Display Controller 16.5.3.5 VIDTCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x0010, Reset Value = 0x0000_0000 Name VBPDE VBPD VFPD VSPW Bit [31:24] [23:16] [15:8] [7:0] Type RW RW RW RW Description Vertical back porch specifies the number of inactive lines at the start of a frame after vertical synchronization period. (only for even field of YVU interface) Vertical back porch specifies the number of inactive lines at the start of a frame after vertical synchronization period. Vertical front porch specifies the number of inactive lines at the end of a frame before vertical synchronization period. Vertical synchronization pulse width determines the highlevel width of VSYNC pulse by counting the number of inactive lines. Reset Value 0x00 0x00 0x00 0x00 16.5.3.6 VIDTCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x0014, Reset Value = 0x0000_0000 Name VFPDE HBPD HFPD HSPW Bit [31:24] [23:16] [15:8] [7:0] Type RW RW RW RW Description Vertical front porch specifies the number of inactive lines at the end of a frame before vertical synchronization period. (only for the even field of YVU interface). Horizontal back porch specifies the number of VCLK periods between the falling edge of HSYNC and start of active data. Horizontal front porch specifies the number of VCLK periods between the end of active data and rising edge of HSYNC. Horizontal synchronization pulse width determines the highlevel width of HSYNC pulse by counting the number of VCLK. Reset Value 0 0x00 0x00 0x00 16-64 Exynos 4412_UM 16 Display Controller 16.5.3.7 VIDTCON2  Base Address = 0x11C0_0000  Address = Base Address + 0x0018, Reset Value = 0x0000_0000 Name LINEVAL HOZVAL Bit [21:11] [10:0] Type RW RW Description Determines vertical size of display. In the Interlace mode, (LINEVAL + 1) should be even. Determines horizontal size of display. NOTE: HOZVAL = (Horizontal display size) – 1 and LINEVAL = (Vertical display size) – 1. Reset Value 0 0 16.5.3.8 VIDTCON3  Base Address = 0x11C0_0000  Address = Base Address + 0x001C, Reset Value = 0x0000_0000 Name VSYNCEN RSVD FRMEN INVFRM FRMVRATE RSVD FRMVFPD FRMVSPW Bit [31] [30] [29] [28] [27:24] [23:16] [15:8] [7:0] Type RW – RW RW RW RW RW RW Description Enables VSYNC Signal Output. 0 = Disables 1 = Enables VBPD (VFPD, VSPW) + 1  LINEVAL (when VSYNCEN = 1) Reserved NOTE: This bit should be set to 0. Enables FRM signal output. 0 = Disables 1 = Enables Controls polarity of FRM pulse. 0 = Active HIGH 1 = Active LOW Controls FRM issue rate (maximum rate up to 1:16). Reserved Specifies number of line between data active and FRM signal. Specifies number of line of FRM signal width. (FRMVFPD + 1) + (FRMVSPW + 1)  LINEVAL + 1 (in RGB) Reset Value 0 0 0 0 0x00 0x00 0x00 0x00 16-65 Exynos 4412_UM 16 Display Controller 16.5.3.9 WINCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x0020, Reset Value = 0x0000_0000 Name BUFSTATUS_H BUFSEL_H LIMIT_ON EQ709 nWide/Narrow TRGSTATUS RSVD ENLOCAL_F BUFSTATUS_L BUFSEL_L BUFAUTOEN BITSWP_F Bit [31] [30] [29] [28] [27:26] [25] [24:23] [22] [21] [20] [19] [18] Type RW RW RW RW RW RW – RW RW RW RW RW Description Specifies Buffer Status (read only). NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} 00 = Buffer set to 0 01 = Buffer set to 1 10 = Buffer set to 2 Selects Buffer set. NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} 00 = Buffer set to 0 01 = Buffer set to 1 10 = Buffer set to 2 (only available where BUF_MODE == 1'b1) Enables CSC source limiter (for clamping xvYCC source). 0 = Disables 1 = Enables (when local SRC data has xvYCC color space, InRGB = 1) Controls CSC parameter. 0 = Equation. 601 1 = Equation. 709 (when local SRC data has HD (709) color gamut) Chooses color space conversion equation from YCbCr to RGB according to input value range (2'00 for YCbCr w wide range and 2'11 for YCbCr narrow range) Wide Range: Y/Cb/Cr: 255-0 Narrow Range: Y:235-16, Cb/Cr:240-16 Specifies Trigger Status (read only). 0 = Does not issue trigger 1 = Issues trigger Reserved. Selects Data access method. 0 = Dedicated DMA 1 = Local Path Specifies Buffer Status (read only). NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} Selects Buffer set. NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} Specifies Double Buffer Auto control bit. 0 = Fixed by BUFSEL 1 = Auto Changed by Trigger Input Specifies Bit swap control bit. 0 = Disables swap Reset Value 0 0 0 0 00 0 00 0 0 0 0 0 16-66 Exynos 4412_UM 16 Display Controller Name BYTSWP_F HAWSWP_F WSWP_F BUF_MODE InRGB RSVD BURSTLEN RSVD BLD_PIX_F BPPMODE_F Bit [17] [16] [15] [14] [13] [12:11] [10:9] [8:7] [6] [5:2] Type RW RW RW RW RW – RW – RW RW Description 1 = Enables swap NOTE: It should be set to 0 when ENLOCAL is 1. Specifies Byte swaps control bit. 0 = Disables swap 1 = Enables swap NOTE: It should be set to 0 when ENLOCAL is 1. Specifies Half-Word swap control bit. 0 = Disables swap 1 = Enables swap NOTE: It should be set to 0 when ENLOCAL is 1. Specifies Word swap control bit. 0 = Disables swap 1 = Enables swap NOTE: It should be set to 0 when ENLOCAL is 1. Selects auto-buffering mode. 0 = Double 1 = Triple Specifies input color space of source image. (Only for "ENLOCAL" enable). 0 = RGB 1 = YCbCr Reserved NOTE: This bit should be set to 0. Selects DMA Burst Maximum Length. 00 = 16 word-burst 01 = 8 word-burst 10 = 4 word-burst Reserved NOTE: This bit should be set to 0. Selects blending category (In case of window0, this is required only for deciding window 0's blending factor.) 0 = Per plane blending 1 = Per pixel blending Selects Bits Per Pixel (BPP) mode for Window image. 0000 = 1 BPP 0001 = 2 BPP 0010 = 4 BPP 0011 = 8 BPP (palletized) 0100 = 8 BPP (non-palletized, A: 1-R:2-G:3-B:2) 0101 = 16 BPP (non-palletized, R:5-G:6-B:5) 0110 = 16 BPP (non-palletized, A:1-R:5-G:5-B:5) 0111 = 16 BPP (non-palletized, I :1-R:5-G:5-B:5) 1000 = Unpacked 18 BPP (non-palletized, R:6-G:6-B:6) 1001 = Unpacked 18 BPP (non-palletized, A:1-R:6-G:6B:5) Reset Value 0 0 0 0 0 0 0 0 0 0 16-67 Exynos 4412_UM 16 Display Controller Name ALPHA_SEL_F ENWIN_F Bit Type Description Reset Value 1010 = Unpacked 19 BPP (non-palletized, A:1-R:6-G:6B:6) 1011 = Unpacked 24 BPP (non-palletized R:8-G:8-B:8) 1100 = Unpacked 24 BPP (non-palletized A:1-R:8-G:8B:7) 1101 = Unpacked 25 BPP (non-palletized A:1-R:8-G:8B:8) 1110 = Unpacked 13 BPP (non-palletized A:1-R:4-G:4B:4) 1111 = Unpacked 15 BPP (non-palletized R:5-G:5-B:5) NOTE: 1. 1101 = Supports unpacked 32 BPP (non-palletized A:8R:8-G:8-B:8) for per pixel blending. 2. 1110 = Supports 16 BPP (non-palletized A:4-R:4-G:4B:4) for per pixel blending. (16 level blending) Selects Alpha value. When per plane blending case (BLD_PIX == 0): 0 = Uses ALPHA0_R/G/B values 1 = Uses ALPHA1_R/G/B values [1] RW When per pixel blending (BLD_PIX == 1): 0 0 = Selected by AEN (A value) 1 = Using DATA[31:24] data in word boundary (only when BPPMODE_F = 4'b1101) DATA[31:28], [15:12] data in word boundary (only when BPPMODE_F = 4'b1110) Enables/disables video output and logic immediately. [0] RW 0 = Disables the video output and video control signal 0 1 = Enables the video output and video control signal 16-68 Exynos 4412_UM 16 Display Controller 16.5.3.10 WINCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x0024, Reset Value = 0x0000_0000 Name BUFSTATUS_H BUFSEL_H LIMIT_ON EQ709 nWide/Narrow TRGSTATUS RSVD ENLOCAL_F BUFSTATUS_L BUFSEL_L Bit [31] [30] [29] [28] [27:26] [25] [24:23] [22] [21] [20] Type RW RW RW RW RW RW – RW RW RW Description Specifies Buffer Status (read only). 00 = Buffer set to 0 01 = Buffer set to 1 10 = Buffer set to 2 NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} Select Buffer set. 00 = Buffer set to 0 01 = Buffer set to 1 10 = Buffer set to 2 (only available when BUF_MODE == 1'b1) NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} Enables Control CSC source limiter (for clamping xvYCC source). 0 = Disables 1 = Enables (when local SRC data has xvYCC color space, InRGB = 1) Controls CSC parameter. 0 = Equation. 601 1 = Equation. 709 (when local SRC data has HD (709) color gamut) Chooses color space conversion equation from YCbCr to RGB based on input value range (2'00 for YCbCr wide range and 2'11 for YCbCr narrow range). Wide Range: Y/Cb/Cr: 255-0 Narrow Range: Y:235-16, Cb/Cr: 240-16 Specifies Window 0 Software Trigger Update Status (read only). 0 = Updates 1 = Does not update If the Software Trigger in window 1 occurs, then this bit is automatically set to "1". It clears this value only after updating the shadow register sets. Reserved NOTE: This bit should be set to 0. Selects Data access method. 0 = Dedicated DMA 1 = Local Path Specifies Buffer Status (Read only). NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} Selects Buffer set. Reset Value 0 0 0 0 00 0 0 0 0 0 16-69 Exynos 4412_UM 16 Display Controller Name BUFAUTOEN BITSWP_F BYTSWP_F HAWSWP_F WSWP_F BUF_MODE InRGB RSVD BURSTLEN RSVD ALPHA_MUL_F Bit [19] [18] [17] [16] [15] [14] [13] [12:11] [10:9] [8] [7] Type RW RW RW RW RW RW RW – RW – RW Description NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} Specifies Double Buffer Auto control bit. 0 = Fixed by BUFSEL 1 = Auto changed by Trigger Input Specifies Bit swap control bit. 0 = Disables swap 1 = Enables swap NOTE: Set it to 0 when ENLOCAL is 1. Specifies Byte swaps control bit. 0 = Disables swap 1 = Enables swap NOTE: Set it to 0 when ENLOCAL is 1. Specifies Half-Word swap control bit. 0 = Disables swap 1 = Enables swap NOTE: Set it to 0 when ENLOCAL is 1. Specifies Word swap control bit. 0 = Disables swap 1 = Enables swap NOTE: Set it to 0 when ENLOCAL is 1. Selects auto-buffering mode. 0 = Double 1 = Triple Indicates input color space of source image. (Only for "EnLcal" enable). 0 = RGB 1 = YCbCr Reserved NOTE: This bit should be set to 0. Specifies DMA's Burst Maximum Length selection. 00 = 16word-burst 01 = 8word-burst 10 = 4word-burst Reserved NOTE: This bit should be set to 0. Specifies Multiplied Alpha value mode. 0 = Disables multiplied mode 1 = Enables multiplied mode When ALPHA_MUL is 1, set BLD_PIX = 1, ALPHA_SEL = 1, and BPPMODE_F[5:2] = 4'b1101 or 4'b1110. NOTE: Alpha value = alpha_pixel (from data)  ALPHA0_R/G/B Reset Value 0 0 0 0 0 0 0 0 0 0 0 16-70 Exynos 4412_UM 16 Display Controller Name BLD_PIX_F BPPMODE_F ALPHA_SEL_F ENWIN_F Bit Type Description Reset Value Selects blending category. [6] RW 0 = Per plane blending 0 1 = Per pixel blending Selects Bits Per Pixel (BPP) mode in Window image. 0000 = 1 BPP 0001 = 2 BPP 0010 = 4 BPP 0011 = 8 BPP (palletized) 0100 = 8 BPP (non-palletized, A: 1-R:2-G:3-B:2) 0101 = 16 BPP (non-palletized, R:5-G:6-B:5) 0110 = 16 BPP (non-palletized, A:1-R:5-G:5-B:5) 0111 = 16 BPP (non-palletized, I :1-R:5-G:5-B:5) 1000 = Unpacked 18 BPP (non-palletized, R:6-G:6-B:6) 1001 = Unpacked 18 BPP (non-palletized, A:1-R:6-G:6- B:5) 1010 = Unpacked 19 BPP (non-palletized, A:1-R:6-G:6- [5:2] RW B:6) 0 1011 = Unpacked 24 BPP (non-palletized R:8-G:8-B:8) 1100 = Unpacked 24 BPP (non-palletized A:1-R:8-G:8- B:7) 1101 = Unpacked 25 BPP (non-palletized A:1-R:8-G:8- B:8) 1110 = Unpacked 13 BPP (non-palletized A:1-R:4-G:4- B:4) 1111 = Unpacked 15 BPP (non-palletized R:5-G:5-B:5) NOTE: 1. 1101 = Supports unpacked 32 BPP (non-palletized A:8- R:8-G:8-B:8) for per pixel blending. 2. 1110 = Supports 16 BPP (non-palletized A:4-R:4-G:4- B:4) for per pixel blending. (16 level blending) Selects Alpha value. When per plane blending case (BLD_PIX == 0) 0 = Using ALPHA0_R/G/B values 1 = Using ALPHA1_R/G/B values [1] RW When per pixel blending (BLD_PIX == 1) 0 0 = Selected by AEN (A value) 1 = Using DATA[31:24] data in word boundary (only when BPPMODE_F = 4'b1101) DATA[31:28], [15:12] data in word boundary (only when BPPMODE_F = 4'b1110) Enables/disables video output and logic immediately. [0] RW 0 = Disables the video output and video control signal 0 1 = Enables the video output and video control signal 16-71 Exynos 4412_UM 16 Display Controller 16.5.3.11 WINCON2  Base Address = 0x11C0_0000  Address = Base Address + 0x0028, Reset Value = 0x0000_0000 Name BUFSTATUS_H BUFSEL_H LIMIT_ON EQ709 nWide/Narrow RSVD LOCALSEL_F ENLOCAL_F BUFSTATUS_L BUFSEL_L BUFAUTOEN BITSWP_F Bit [31] [30] [29] [28] [27:26] [25:24] [23] [22] [21] [20] [19] [18] Type RW RW RW RW RW – RW RW RW RW RW RW Description Specifies Buffer Status (Read only). 00 = Buffer set to 0 01 = Buffer set to 1 10 = Buffer set to 2 NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} Selects Buffer set. 00 = Buffer set to 0 01 = Buffer set to 1 10 = Buffer set to 2 (only available when BUF_MODE == 1'b1) NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} Enables CSC source limiter (for clamping xvYCC source). 0 = Disables 1 = Enables (when local SRC data has xvYCC color space, InRGB = 1) Controls CSC parameter. 0 = Equation.601 1 = Equation 709 (when local SRC data has HD (709) color gamut) Chooses color space conversion equation from YCbCr to RGB based on the input value range (2'00 for YCbCr wide range and 2'11 for YCbCr narrow range). Wide Range: Y/Cb/Cr: 255-0 Narrow Range: Y: 235-16, Cb/Cr: 240-16 Reserved Selects local path source. 0 = CAMIF2 1 = CAMIF3 Selects Data access method. 0 = Dedicated DMA 1 = Local Path Specifies Buffer Status (read only). NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} Selects Buffer set. NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} Specifies Double Buffer Auto control bit. 0 = Fixed by BUFSEL 1 = Auto changed by Trigger Input Specifies the Bit swap control bit. 0 = Disables swap Reset Value 0 0 0 0 00 00 0 0 0 0 0 16-72 Exynos 4412_UM 16 Display Controller Name BYTSWP_F HAWSWP_F WSWP_F BUF_MODE InRGB RSVD BURSTLEN RSVD ALPHA_MUL_F BLD_PIX_F BPPMODE_F Bit [17] [16] [15] [14] [13] [12:11] [10:9] [8] [7] [6] [5:2] Type RW RW RW RW RW – RW – RW RW RW Description 1 = Enables swap NOTE: Set it to 0 when ENLOCAL is 1. Specifies Byte swaps control bit. 0 = Disables swap 1 = Enables swap NOTE: Set it to 0 when ENLOCAL is 1. Specifies Half-Word swap control bit. 0 = Disables swap 1 = Enables swap NOTE: Set it to 0 0 when ENLOCAL is 1. Specifies Word swap control bit. 0 = Disables swap 1 = Enables swap NOTE: Set it to 0 when ENLOCAL is 1. Selects auto-buffering mode. 0 = Double 1 = Triple Specifies input color space of source image (only for "EnLcal" enable). 0 = RGB 1 = YCbCr Reserved NOTE: This bit should be set to 0. Selects the DMA's Burst Maximum Length. 00 = 16 word-burst 01 = 8 word-burst 10 = 4 word-burst Reserved (should be 0). Specifies Multiplied Alpha value mode. 0 = Disables multiplied mode 1 = Enables multiplied mode When ALPHA_MUL is 1, set BLD_PIX = 1, ALPHA_SEL = 1, and BPPMODE_F[5:2] = 4'b1101 or 4'b1110. NOTE: Alpha value = alpha_pixel (from data)  ALPHA0_R/G/B Selects blending category. 0 = Per plane blending 1 = Per pixel blending Selects Bits Per Pixel (BPP) mode in Window image. 0000 = 1 BPP 0001 = 2 BPP 0010 = 4 BPP 0011 = 8 BPP (palletized) Reset Value 0 0 0 0 0 0 0 0 0 0 0 16-73 Exynos 4412_UM 16 Display Controller Name ALPHA_SEL_F ENWIN_F Bit Type Description Reset Value 0100 = 8 BPP (non-palletized, A: 1-R:2-G:3-B:2) 0101 = 16 BPP (non-palletized, R:5-G:6-B:5) 0110 = 16 BPP (non-palletized, A:1-R:5-G:5-B:5) 0111 = 16 BPP (non-palletized, I :1-R:5-G:5-B:5) 1000 = Unpacked 18 BPP (non-palletized, R:6-G:6-B:6 ) 1001 = Unpacked 18 BPP (non-palletized, A:1-R:6-G:6B:5) 1010 = Unpacked 19 BPP (non-palletized, A:1-R:6-G:6B:6) 1011 = Unpacked 24 BPP (non-palletized R:8-G:8-B:8) 1100 = Unpacked 24 BPP (non-palletized A:1-R:8-G:8B:7) 1101 = Unpacked 25 BPP (non-palletized A:1-R:8-G:8B:8) 1110 = Unpacked 13 BPP (non-palletized A:1-R:4-G:4B:4) 1111 = Unpacked 15 BPP (non-palletized R:5-G:5-B:5) NOTE: 1. 1101 = Supports unpacked 32 BPP (non-palletized A:8R:8-G:8-B:8) for per pixel blending. 2. 1110 = Supports 16 BPP (non-palletized A:4-R:4-G:4B:4) for per pixel blending. (16 level blending) Selects Alpha value. When Per plane blending case BLD_PIX == 0: 0 = Using ALPHA0_R/G/B values 1 = Using ALPHA1_R/G/B values [1] RW When Per pixel blending BLD_PIX == 1: 0 0 = Selected by AEN (A value) 1 = Using DATA[31:24] data in word boundary (only when BPPMODE_F = 4'b1101) DATA[31:28], [15:12] data in word boundary (only when BPPMODE_F = 4'b1110) Enables/disables the video output and logic immediately. [0] RW 0 = Disables the video output and video control signal 0 1 = Enables the video output and video control signal 16-74 Exynos 4412_UM 16 Display Controller 16.5.3.12 WINCON3  Base Address = 0x11C0_0000  Address = Base Address + 0x002C, Reset Value = 0x0000_0000 Name BUFSTATUS_H BUFSEL_H RSVD TRIGSTATUS RSVD BUFSTATUS_L BUFSEL_L BUFAUTOEN BITSWP_F BYTSWP_F HAWSWP_F WSWP_F BUF_MODE Bit [31] [30] [29:26] [25] [24:22] [21] [20] [19] [18] [17] [16] [15] [14] Type RW RW – RW – RW RW RW RW RW RW RW RW Description Specifies Buffer Status (read only). 00 = Buffer is set to 0 01 = Buffer is set to 1 10 = Buffer is set to 2 NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} Selects Buffer set 00 = Buffer is set to 0 01 = Buffer is set to 1 10 = Buffer is set to 2 (only available where BUF_MODE == 1'b1) NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} Reserved NOTE: This bit should be set to 0. Specifies Trigger Status (read only) 0 = No trigger is issued 1 = Trigger is issued Reserved NOTE: This bit should be set to 0. Specifies Buffer Status (read only). NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} Selects Buffer set. NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} Specifies Double Buffer Auto control bit. 0 = Fixed by BUFSEL 1 = Auto changed by Trigger Input Specifies Bit swap control bit. 0 = Disables swap 1 = Enables swap Specifies Byte swaps control bit. 0 = Disables swap 1 = Enables swap Specifies Half-Word swap control bit. 0 = Disables swap 1 = Enables swap Specifies Word swap control bit. 0 = Disables swap 1 = Enables swap Selects auto-buffering mode. 0 = Double Reset Value – – – – – – – – 0 0 0 0 16-75 Exynos 4412_UM 16 Display Controller Name RSVD BURSTLEN RSVD ALPHA_MUL_F BLD_PIX_F BPPMODE_F Bit [13:11] [10:9] [8] [7] [6] [5:2] Type – RW – RW RW RW 1 = Triple Description Reserved NOTE: This bit should be set to 0. Selects DMA Burst Maximum Length. 00 = 16 word- burst 01 = 8 word- burst 10 = 4 word- burst Reserved NOTE: This bit should be set to 0. Specifies Multiplied Alpha value mode. 0 = Disables multiplied mode 1 = Enables multiplied mode When ALPHA_MUL is 1, set BLD_PIX = 1, ALPHA_SEL = 1, and BPPMODE_F[5:2] = 4'b1101 or 4'b1110. NOTE. Alpha value = alpha_pixel (from data)  ALPHA0_R/G/B Selects blending category. 0 = Per plane blending 1 = Per pixel blending Selects Bits Per Pixel (BPP) mode in Window image. 0000 = 1 BPP 0001 = 2 BPP 0010 = 4 BPP 0011 = 8 BPP (palletized) 0100 = 8 BPP (non-palletized, A: 1-R:2-G:3-B:2) 0101 = 16 BPP (non-palletized, R:5-G:6-B:5) 0110 = 16 BPP (non-palletized, A:1-R:5-G:5-B:5) 0111 = 16 BPP (non-palletized, I :1-R:5-G:5-B:5) 1000 = Unpacked 18 BPP (non-palletized, R:6-G:6-B:6 ) 1001 = Unpacked 18 BPP (non-palletized, A:1-R:6-G:6B:5) 1010 = Unpacked 19 BPP (non-palletized, A:1-R:6-G:6B:6) 1011 = Unpacked 24 BPP (non-palletized R:8-G:8-B:8) 1100 = Unpacked 24 BPP (non-palletized A:1-R:8-G:8B:7) 1101 = Unpacked 25 BPP (non-palletized A:1-R:8-G:8B:8) 1110 = Unpacked 13 BPP (non-palletized A:1-R:4-G:4B:4) 1111 = Unpacked 15 BPP (non-palletized R:5-G:5-B:5) NOTE: 1. 1101 = Supports unpacked 32 BPP (non-palletized A:8R:8-G:8-B:8) for per pixel blending. 2. 1110 = Supports 16 BPP (non-palletized A:4-R:4-G:4B:4) for per pixel blending. (16 level blending) Reset Value 0 0 0 0 0 16-76 Exynos 4412_UM 16 Display Controller Name ALPHA_SEL_F ENWIN_F Bit Type Description Reset Value Selects Alpha value. When Per plane blending case BLD_PIX == 0: 0 = Uses ALPHA0_R/G/B values 1 = Uses ALPHA1_R/G/B values [1] RW When Per pixel blending BLD_PIX == 1: 0 0 = Selected by AEN (A value) 1 = Uses DATA[31:24] data in word boundary (only when BPPMODE_F = 4'b1101) DATA[31:28], [15:12] data in word boundary (only when BPPMODE_F = 4'b1110) Enables/disables video output and logic immediately. [0] RW 0 = Disables the video output and video control signal 0 1 = Enables the video output and video control signal 16-77 Exynos 4412_UM 16 Display Controller 16.5.3.13 WINCON4  Base Address = 0x11C0_0000  Address = Base Address + 0x0030, Reset Value = 0x0000_0000 Name BUFSTATUS_H BUFSEL_H RSVD TRIGSTATUS RSVD BUFSTATUS_L BUFSEL_L BUFAUTOEN BITSWP_F BYTSWP_F HAWSWP_F WSWP_F BUF_MODE Bit [31] [30] [29:26] [25] [24:22] [21] [20] [19] [18] [17] [16] [15] [14] Type RW RW – RW – RW RW RW RW RW RW RW RW Description Specifies Buffer Status (read only). 00 = Buffer is set to 0 01 = Buffer is set to 1 10 = Buffer is set to 2 NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} Selects Buffer set. 00 = Buffer is set to 0 01 = Buffer is set to 1 10 = Buffer is set to 2 (only available where BUF_MODE == 1'b1) NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} Reserved NOTE: This bit should be set to 0. Specifies Trigger Status (read only). 0 = Does not issue trigger 1 = Issues trigger Reserved NOTE: This bit should be set o 0. Specifies Buffer Status (read only). NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} Selects Buffer set. NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} Specifies Double Buffer Auto control bit. 0 = Fixed by BUFSEL 1 = Auto changed by Trigger Input Specifies Bit swap control bit. 0 = Disables swap 1 = Enables swap Specifies Byte swap control bit. 0 = Disables swap 1 = Enables swap Specifies Half-Word swap control bit. 0 = Disables swap 1 = Enables swap Specifies Word swap control bit. 0 = Disables swap 1 = Enables swap Selects auto-buffering mode. 0 = Double Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 16-78 Exynos 4412_UM 16 Display Controller Name RSVD BURSTLEN RSVD ALPHA_MUL_F BLD_PIX_F BPPMODE_F Bit [13:11] [10:9] [8] [7] [6] [5:2] Type – RW – RW RW RW 1 = Triple Description Reserved NOTE: This bit should be set to 0 Selects DMA Burst Maximum Length. 00 = 16 word-burst 01 = 8 word-burst 10 = 4 word-burst Reserved NOTE: This bit should be set to 0. Specifies Multiplied Alpha value mode. 0 = Disables multiplied mode 1 = Enables multiplied mode When ALPHA_MUL is 1, set BLD_PIX = 1, ALPHA_SEL = 1, and BPPMODE_F[5:2] = 4'b1101 or 4'b1110. NOTE: Alpha value = alpha_pixel (from data)  ALPHA0_R/G/B Selects blending category. 0 = Per plane blending 1 = Per pixel blending Selects Bits Per Pixel (BPP) mode in Window image. 0000 = 1 BPP 0001 = 2 BPP 0010 = 4 BPP 0011 = 8 BPP (palletized) 0100 = 8 BPP (non-palletized, A: 1-R:2-G:3-B:2) 0101 = 16 BPP (non-palletized, R:5-G:6-B:5) 0110 = 16 BPP (non-palletized, A:1-R:5-G:5-B:5) 0111 = 16 BPP (non-palletized, I :1-R:5-G:5-B:5) 1000 = Unpacked 18 BPP (non-palletized, R:6-G:6-B:6) 1001 = Unpacked 18 BPP (non-palletized, A:1-R:6-G:6B:5) 1010 = Unpacked 19 BPP (non-palletized, A:1-R:6-G:6B:6) 1011 = Unpacked 24 BPP (non-palletized, R:8-G:8-B:8) 1100 = Unpacked 24 BPP (non-palletized, A:1-R:8-G:8B:7) 1101 = Unpacked 25 BPP (non-palletized, A:1-R:8-G:8B:8) 1110 = Unpacked 13 BPP (non-palletized, A:1-R:4-G:4B:4) 1111 = Unpacked 15 BPP (non-palletized, R:5-G:5-B:5) NOTE: 1. 1101 = Support unpacked 32 BPP (non-palletized, A:8R:8-G:8-B:8) for per pixel blending. 2. 1110 = Support 16 BPP (non-palletized A:4-R:4-G:4B:4) for per pixel blending. (16 level blending) Reset Value 0 0 0 0 0 0 16-79 Exynos 4412_UM 16 Display Controller Name ALPHA_SEL_F ENWIN_F Bit Type Description Reset Value Selects Alpha value. When Per plane blending case BLD_PIX == 0 : 0 = Uses ALPHA0_R/G/B values 1 = Uses ALPHA1_R/G/B values [1] RW When Per pixel blending BLD_PIX == 1 : 0 0 = Selected by AEN (A value) 1 = Uses DATA[31:24] data in word boundary (only when BPPMODE_F = 4'b1101) DATA[31:28], [15:12] data in word boundary (only when BPPMODE_F = 4'b1110) Enables/disables video output and logic immediately. [0] RW 0 = Disables the video output and video control signal 0 1 = Enables the video output and video control signal 16-80 Exynos 4412_UM 16 Display Controller 16.5.3.14 SHADOWCON  Base Address = 0x11C0_0000  Address = Base Address + 0x0034, Reset Value = 0x0000_0000 Name RSVD W4_SHADOW _PROTECT W3_SHADOW _PROTECT W2_SHADOW _PROTECT W1_SHADOW _PROTECT W0_SHADOW _PROTECT RSVD C2_ENLOCAL_F C1_ENLOCAL_F C0_ENLOCAL_F C4_EN_F C3_EN_F C2_EN_F Bit [31:15] [14] [13] [12] [11] [10] [9:8] [7] [6] [5] [4] [3] [2] Type – RW RW RW RW RW – RW RW RW RW RW RW Description Reserved NOTE: This bit should be set to 0 Protects to update window 4's shadow register (xxx_F). 0 = Updates shadow register per frame 1 = Protects to update (updates shadow register at next frame after "SHADOW_PROTECT" turns to be 1'b0) Protects to update window 3's shadow register (xxx_F) 0 = Updates shadow register per frame 1 = Protects to update (updates shadow register at next frame after "SHADOW_PROTECT" turns to be 1'b0) Protects to update window 2's shadow register (xxx_F) 0 = Updates shadow register per frame 1 = Protects to update (updates shadow register at next frame after "SHADOW_PROTECT" turns to be 1'b0) Protects to update window 1's shadow register (xxx_F) 0 = Updates shadow register per frame 1 = Protects to update (update shadow register at next frame after "SHADOW_PROTECT" turns to be 1'b0) Protects to update window 0's shadow register (xxx_F) 0 = Updates shadow register per frame 1 = Protects to update (update shadow register at next frame after "SHADOW_PROTECT" turns to be 1'b0) Reserved Enables Channel 2 Local Path. 0 = Disables 1 = Enables Enables Channel 1 Local Path. 0 = Disables 1 = Enables Enables Channel 0 Local Path. 0 = Disables 1 = Enables Enables Channel 4. 0 = Disables 1 = Enables Enables Channel 3. 0 = Disables 1 = Enables Enables Channel 2. 0 = Disables Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 16-81 Exynos 4412_UM Name C1_EN_F C0_EN_F Bit Type Description 1 = Enables Enables Channel 1. [1] RW 0 = Disables 1 = Enables Enables Channel 0. [0] RW 0 = Disables 1 = Enables 16 Display Controller Reset Value 0 0 16-82 Exynos 4412_UM 16.5.3.15 WINCHMAP2  Base Address = 0x11C0_0000  Address = Base Address + 0x003C, Reset Value = 0x7D51_7D51 Name CH4FISEL CH3FISEL CH2FISEL CH1FISEL CH0FISEL W4FISEL W3FISEL Bit [30:28] [27:25] [24:22] [21:19] [18:16] [14:12] [11:9] Type RW RW RW RW RW RW RW Description Selects Channel 4's channel. 001 = Window 0 010 = Window 1 101 = Window 2 110 = Window 3 111 = Window 4 Selects Channel 3's channel. 001 = Window 0 010 = Window 1 101 = Window 2 110 = Window 3 111 = Window 4 Selects Channel 2's channel. 001 = Window 0 010 = Window 1 101 = Window 2 110 = Window 3 111 = Window 4 Selects Channel 1's channel. 001 = Window 0 010 = Window 1 101 = Window 2 110 = Window 3 111 = Window 4 Selects Channel 0's channel. 001 = Window 0 010 = Window 1 101 = Window 2 110 = Window 3 111 = Window 4 Selects Window 4's channel. 001 = Channel 0 010 = Channel 1 101 = Channel 2 110 = Channel 3 111 = Channel 4 Selects Window 3's channel. 001 = Channel 0 010 = Channel 1 101 = Channel 2 110 = Channel 3 111 = Channel 4 16-83 16 Display Controller Reset Value 111 110 101 010 001 111 110 Exynos 4412_UM Name W2FISEL W1FISEL W0FISEL Bit Type Description Selects Window 2's channel. 001 = Channel 0 [8:6] RW 010 = Channel 1 101 = Channel 2 110 = Channel 3 111 = Channel 4 Selects Window 1's channel. 001 = Channel 0 [5:3] RW 010 = Channel 1 101 = Channel 2 110 = Channel 3 111 = Channel 4 Selects Window 0's channel. 001 = Channel 0 [2:0] RW 010 = Channel 1 101 = Channel 2 110 = Channel 3 111 = Channel 4 16 Display Controller Reset Value 101 010 001 16-84 Exynos 4412_UM 16 Display Controller 16.5.3.16 VIDOSD0A  Base Address = 0x11C0_0000  Address = Base Address + 0x0040, Reset Value = 0x0000_0000 Name OSD_LeftTopX_F OSD_LeftTopY_F Bit [21:11] [10:0] Type RW RW Description Specifies the horizontal screen coordinate for left top pixel of OSD image. Specifies the vertical screen coordinate for left top pixel of OSD image. (For interlace TV output, this value should be set to half of the original screen y coordinate. The original screen y coordinate should be even.) Reset Value 0 0 16.5.3.17 VIDOSD0B  Base Address = 0x11C0_0000  Address = Base Address + 0x0044, Reset Value = 0x0000_0000 Name OSD_RightBotX_F OSD_RightBotY_F Bit [21:11] [10:0] Type RW RW Description Specifies horizontal screen coordinate for right bottom pixel of OSD image. Specifies vertical screen coordinate for right bottom pixel of OSD image. (For interlace TV output, this value should be set to half of the original screen y coordinate. The original screen y coordinate should be odd value.) NOTE: Registers should have word boundary X position. Therefore, 24 BPP mode should have X position by 1 pixel. (For example, X = 0, 1, 2, 3….) 16 BPP mode should have X position by 2 pixel. (For example, X = 0, 2, 4, 6….) 8 BPP mode should have X position by 4 pixel. (For example, X = 0, 4, 8, 12….) Reset Value 0 0 16.5.3.18 VIDOSD0C  Base Address = 0x11C0_0000  Address = Base Address + 0x0048, Reset Value = 0x0000_0000 Name RSVD OSDSIZE Bit [25:24] [23:0] Type – RW Description Reserved NOTE: This bit should be set to 0. Specifies the Window Size For example, Height  Width (number of word) Reset Value 0 0 16-85 Exynos 4412_UM 16 Display Controller 16.5.3.19 VIDOSD0C  Base Address = 0x11C0_0000  Address = Base Address + 0x0050, Reset Value = 0x0000_0000 Name OSD_LeftTopX_F OSD_LeftTopY_F Bit [21:11] [10:0] Type RW RW Description Specifies Horizontal screen coordinate for left top pixel of OSD image. Specifies Vertical screen coordinate for left top pixel of OSD image. (For interlace TV output, this value should be set to half of the original screen "y" coordinate. The original screen "y" coordinate should be even.) Reset Value 0 0 16.5.3.20 VIDOSD1B  Base Address = 0x11C0_0000  Address = Base Address + 0x0054, Reset Value = 0x0000_0000 Name OSD_RightBotX_F OSD_RightBotY_F Bit [21:11] [10:0] Type RW RW Description Specifies horizontal screen coordinate for right bottom pixel of OSD image. Specifies vertical screen coordinate for right bottom pixel of OSD image. (For interlace TV output, this value should be set to half of the original screen "y" coordinate. The original screen "y" coordinate should be odd value.) Reset Value 0 0 NOTE: Registers should have word boundary X position. Therefore, 24 BPP mode should have X position by 1 pixel. (For example, X = 0, 1, 2, 3….) 16 BPP mode should have X position by 2pixel. (For example, X = 0, 2, 4, 6….) 8 BPP mode should have X position by 4pixel. (For example, X = 0, 4, 8, 12….) 16-86 Exynos 4412_UM 16 Display Controller 16.5.3.21 VIDOSD1C  Base Address = 0x11C0_0000  Address = Base Address + 0x0058, Reset Value = 0x0000_0000 Name RSVD ALPHA0_R_H_F ALPHA0_G_H_F ALPHA0_B_H_F ALPHA1_R_H_F ALPHA1_G_H_F ALPHA1_B_H_F Bit [24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type – RW RW RW RW RW RW Description Reserved Specifies Red Alpha upper value (case AEN == 0) Specifies Green Alpha upper value (case AEN == 0) Specifies Blue Alpha upper value (case AEN == 0) Specifies Red Alpha upper value (case AEN == 1) Specifies Green Alpha upper value (case AEN == 1) Specifies Blue Alpha upper value (case AEN == 1) NOTE: For more information, refer to VIDW1ALPHA0, 1 register. Reset Value 0 0 0 0 0 0 0 16.5.3.22 VIDOSD1D  Base Address = 0x11C0_0000  Address = Base Address + 0x005C, Reset Value = 0x0000_0000 Name RSVD OSDSIZE Bit [25:24] [23:0] Type – RW Description Reserved NOTE: This bit should be set to 0. Specifies Window Size. For example, Height  Width (number of word) Reset Value 0 0 16.5.3.23 VIDOSD2A  Base Address = 0x11C0_0000  Address = Base Address + 0x0060, Reset Value = 0x0000_0000 Name OSD_LeftTopX_F OSD_LeftTopY_F Bit [21:11] [10:0] Type RW RW Description Specifies horizontal screen coordinate for left top pixel of OSD image. Specifies vertical screen coordinate for left top pixel of OSD image. For interlace TV output, this value should be set to half of the original screen "y" coordinate. The original screen "y" coordinate should be even value. Reset Value 0 0 16-87 Exynos 4412_UM 16 Display Controller 16.5.3.24 VIDOSD2B  Base Address = 0x11C0_0000  Address = Base Address + 0x0064, Reset Value = 0x0000_0000 Name OSD_RightBotX_F OSD_RightBotY_F Bit [21:11] [10:0] Type RW RW Description Specifies horizontal screen coordinate for right bottom pixel of OSD image. Specifies vertical screen coordinate for right bottom pixel of OSD image. (For interlace TV output, this value should be set to half of the original screen "y" coordinate. The original screen "y" coordinate should be odd value.) NOTE: Registers should have word boundary X position. Therefore, 24 BPP mode should have X position by 1 pixel. (For example, X = 0, 1, 2, 3….) 16 BPP mode should have X position by 2 pixel. (For example, X = 0, 2, 4, 6….) 8 BPP mode should have X position by 4 pixel. (For example, X = 0, 4, 8, 12….) Reset Value 0 0 16.5.3.25 VIDOSD2C  Base Address = 0x11C0_0000  Address = Base Address + 0x0068, Reset Value = 0x0000_0000 Name RSVD ALPHA0_R_H_F ALPHA0_G_H_F ALPHA0_B_H_F ALPHA1_R_H_F ALPHA1_G_H_F ALPHA1_B_H_F Bit [24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type – RW RW RW RW RW RW Description Reserved Specifies the Red Alpha upper value (case AEN == 0). Specifies the Green Alpha upper value (case AEN == 0). Specifies the Blue Alpha upper value (case AEN == 0). Specifies the Red Alpha upper value (case AEN == 1). Specifies the Green Alpha upper value (case AEN == 1). Specifies the Blue Alpha upper value (case AEN == 1). NOTE: For more information, refer to VIDW2ALPHA0, 1 register. Reset Value 0 0 0 0 0 0 0 16-88 Exynos 4412_UM 16 Display Controller 16.5.3.26 VIDOSD2D  Base Address = 0x11C0_0000  Address = Base Address + 0x006C, Reset Value = 0x0000_0000 Name RSVD OSDSIZE Bit [25:24] [23:0] Type – RW Description Reserved NOTE: This bit should be set to 0. Specifies Window Size For example, Height  Width(Number of Word) Reset Value 0 0 16.5.3.27 VIDOSD3A  Base Address = 0x11C0_0000  Address = Base Address + 0x0070, Reset Value = 0x0000_0000 Name OSD_LeftTopX_F OSD_LeftTopY_F Bit [21:11] [10:0] Type RW RW Description Specifies Horizontal screen coordinate for left top pixel of OSD image. Specifies Vertical screen coordinate for left top pixel of OSD image. For interlace TV output, this value should be set to half of the original screen "y" coordinate. The original screen "y" coordinate should be even value. Reset Value 0 0 16.5.3.28 VIDOSD3B  Base Address = 0x11C0_0000  Address = Base Address + 0x0074, Reset Value = 0x0000_0000 Name OSD_RightBotX_F OSD_RightBotY_F Bit [21:11] [10:0] Type RW RW Description Specifies Horizontal screen coordinate for right bottom pixel of OSD image. Specifies Vertical screen coordinate for right bottom pixel of OSD image. (For interlace TV output, this value should be set to half of the original screen "y" coordinate. The original screen "y" coordinate should be odd value.) Reset Value 0 0 NOTE: Registers should have word boundary X position. Therefore, 24 BPP mode should have X position by 1 pixel. (For example, X = 0, 1, 2, 3….) 16 BPP mode should have X position by 2 pixel. (For example, X = 0, 2, 4, 6….) 8 BPP mode should have X position by 4 pixel. (For example, X = 0, 4, 8, 12….) 16-89 Exynos 4412_UM 16 Display Controller 16.5.3.29 VIDOSD3C  Base Address = 0x11C0_0000  Address = Base Address + 0x0078, Reset Value = 0x0000_0000 Name RSVD ALPHA0_R_H_F ALPHA0_G_H_F ALPHA0_B_H_F ALPHA1_R_H_F ALPHA1_G_H_F ALPHA1_B_H_F Bit [24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type – RW RW RW RW RW RW Description Reserved Specifies the Red Alpha upper value (case AEN == 0). Specifies the Green Alpha upper value (case AEN == 0). Specifies the Blue Alpha upper value (case AEN == 0). Specifies the Red Alpha upper value (case AEN == 1). Specifies the Green Alpha upper value (case AEN == 1). Specifies the Blue Alpha upper value (case AEN == 1). Reset Value 0 0 0 0 0 0 0 NOTE: For more information, Refer to 16.5.3.76 VIDW3ALPHA0 16.5.3.77 VIDW3ALPHA1 register. 16.5.3.30 VIDOSD4A  Base Address = 0x11C0_0000  Address = Base Address + 0x0080, Reset Value = 0x0000_0000 Name OSD_LeftTopX_F OSD_LeftTopY_F Bit [21:11] [10:0] Type RW RW Description Specifies the Horizontal screen coordinate for left top pixel of OSD image. Specifies the Vertical screen coordinate for left top pixel of OSD image. For interlace TV output, this value should be set to half of the original screen "y" coordinate. The original screen "y" coordinate should be even value. Reset Value 0 0 16-90 Exynos 4412_UM 16 Display Controller 16.5.3.31 VIDOSD4B  Base Address = 0x11C0_0000  Address = Base Address + 0x0084, Reset Value = 0x0000_0000 Name OSD_RightBotX_F OSD_RightBotY_F Bit [21:11] [10:0] Type RW RW Description Specifies Horizontal screen coordinate for right bottom pixel of OSD image. Specifies Vertical screen coordinate for right bottom pixel of OSD image. For interlace TV output, this value should be set to half of the original screen "y" coordinate. The original screen "y" coordinate should be odd value. NOTE: Registers should have word boundary X position. Therefore, 24 BPP mode should have X position by1 pixel. (For example, X = 0, 1, 2, 3….) 16 BPP mode should have X position by 2 pixel. (For example, X = 0, 2, 4, 6….) 8 BPP mode should have X position by 4 pixel. (For example, X = 0, 4, 8, 12….) Reset Value 0 0 16.5.3.32 VIDOSD4C  Base Address = 0x11C0_0000  Address = Base Address + 0x0088, Reset Value = 0x0000_0000 Name RSVD ALPHA0_R_H_F ALPHA0_G_H_F ALPHA0_B_H_F ALPHA1_R_H_F ALPHA1_G_H_F ALPHA1_B_H_F Bit [24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Type – RW RW RW RW RW RW Description Reserved Specifies the Red Alpha upper value (case AEN == 0). Specifies the Green Alpha upper value (case AEN == 0). Specifies the Blue Alpha upper value (case AEN == 0). Specifies the Red Alpha upper value (case AEN == 1). Specifies the Green Alpha upper value (case AEN == 1). Specifies the Blue Alpha upper value (case AEN == 1). Reset Value 0 0 0 0 0 0 0 NOTE: For more information, Refer to 16.5.3.78 VIDW4ALPHA0 16.5.3.79 VIDW4ALPHA1 register 16-91 Exynos 4412_UM 16 Display Controller 16.5.3.33 VIDW0n (n = 00 to 04) ADD0Bn (n = 0 to 2)  Base Address = 0x11C0_0000  Address = Base Address + 0x00A0, Reset Value = 0x0000_0000 (VIDW00ADD0B0)  Address = Base Address + 0x00A4, Reset Value = 0x0000_0000 (VIDW00ADD0B1)  Address = Base Address + 0x20A0, Reset Value = 0x0000_0000 (VIDW00ADD0B2)  Address = Base Address + 0x00A8, Reset Value = 0x0000_0000 (VIDW01ADD0B0)  Address = Base Address + 0x00AC, Reset Value = 0x0000_0000 (VIDW01ADD0B1)  Address = Base Address + 0x20A8, Reset Value = 0x0000_0000 (VIDW01ADD0B2)  Address = Base Address + 0x00B0, Reset Value = 0x0000_0000 (VIDW02ADD0B0)  Address = Base Address + 0x00B4, Reset Value = 0x0000_0000 (VIDW02ADD0B1)  Address = Base Address + 0x20B0, Reset Value = 0x0000_0000 (VIDW02ADD0B2)  Address = Base Address + 0x00B8, Reset Value = 0x0000_0000 (VIDW03ADD0B0)  Address = Base Address + 0x00BC, Reset Value = 0x0000_0000 (VIDW03ADD0B1)  Address = Base Address + 0x20B8, Reset Value = 0x0000_0000 (VIDW03ADD0B2)  Address = Base Address + 0x00C0, Reset Value = 0x0000_0000 (VIDW04ADD0B0)  Address = Base Address + 0x00C4, Reset Value = 0x0000_0000 (VIDW04ADD0B1)  Address = Base Address + 0x20C0, Reset Value = 0x0000_0000 (VIDW04ADD0B2) Name VBASEU_F Bit [31:0] Type RW Description Specifies A[31:0] of the start address for video frame buffer. Reset Value 0 16-92 Exynos 4412_UM 16 Display Controller 16.5.3.34 VIDW0n (n = 00 to 04) ADD1Bn (n = 0 to 2)  Base Address = 0x11C0_0000  Address = Base Address + 0x00D0, Reset Value = 0x0000_0000 (VIDW00ADD1B0)  Address = Base Address + 0x00D4, Reset Value = 0x0000_0000 (VIDW00ADD1B1)  Address = Base Address + 0x20D0, Reset Value = 0x0000_0000 (VIDW00ADD1B2)  Address = Base Address + 0x00D8, Reset Value = 0x0000_0000 (VIDW01ADD1B0)  Address = Base Address + 0x00DC, Reset Value = 0x0000_0000 (VIDW01ADD1B1)  Address = Base Address + 0x20D8, Reset Value = 0x0000_0000 (VIDW01ADD1B2)  Address = Base Address + 0x00E0, Reset Value = 0x0000_0000 (VIDW02ADD1B0)  Address = Base Address + 0x00E4, Reset Value = 0x0000_0000 (VIDW02ADD1B1)  Address = Base Address + 0x20E0, Reset Value = 0x0000_0000 (VIDW02ADD1B2)  Address = Base Address + 0x00E8, Reset Value = 0x0000_0000 (VIDW03ADD1B0)  Address = Base Address + 0x00EC, Reset Value = 0x0000_0000 (VIDW03ADD1B1)  Address = Base Address + 0x20E8, Reset Value = 0x0000_0000 (VIDW03ADD1B2)  Address = Base Address + 0x00F0, Reset Value = 0x0000_0000 (VIDW04ADD1B0)  Address = Base Address + 0x00F4, Reset Value = 0x0000_0000 (VIDW04ADD1B1)  Address = Base Address + 0x20F0, Reset Value = 0x0000_0000 (VIDW04ADD1B2) Name VBASEL_F Bit [31:0] Type RW Description Specifies A[31:0] of the end address for video frame buffer. VBASEL = VBASEU + (PAGEWIDTH + OFFSIZE)  (LINEVAL + 1) Reset Value 0x0 16-93 Exynos 4412_UM 16 Display Controller 16.5.3.35 VIDW0nADD2 (n = 0 to 4)  Base Address = 0x11C0_0000  Address = Base Address + 0x0100, Reset Value = 0x0000_0000 (VIDW00ADD2)  Address = Base Address + 0x0104, Reset Value = 0x0000_0000 (VIDW01ADD2)  Address = Base Address + 0x0108, Reset Value = 0x0000_0000 (VIDW02ADD2)  Address = Base Address + 0x010C, Reset Value = 0x0000_0000 (VIDW03ADD2)  Address = Base Address + 0x0110, Reset Value = 0x0000_0000 (VIDW04ADD2) Name OFFSIZE_F PAGEWIDTH_F Bit [25:13] [12:0] Type RW RW Description Specifies virtual screen offset size (number of byte). This value defines the difference between address of last byte which displays on the previous video line and address of first byte which will display in the new video line. OFFSIZE_F should have value that is multiple of 4byte size or 0. Specifies virtual screen page width (number of byte). This value defines the width of view port in the frame. PAGEWIDTH should have bigger value than the burst size and you should align the size word boundary. Reset Value 0 0 NOTE: You should align the sum of PAGEWIDTH_F and OFFSIZE_F double-word (8 byte) boundary. 16-94 Exynos 4412_UM 16 Display Controller 16.5.3.36 VIDINTCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x0130, Reset Value = 0x0000_0000 Name RSVD FIFOINTERVAL SYSMAINCON SYSSUBCON I80IFDONE FRAMESEL0 FRAMESEL1 INTFRMEN FIFOSEL Bit [31:26] [25:20] [19] [18] [17] [16:15] [14:13] [12] [11:5] Type – RW RW RW RW RW RW RW RW Description Reserved Controls interval of the FIFO interrupt. Sends complete interrupt enable bit to Main LCD 0 = Disables Interrupt 1 = Enables Interrupt NOTE: This bit is valid if both INTEN and I80IFDONE are high. Sends complete interrupt enable bit to Sub LCD 0 = Disables Interrupt 1 = Enables Interrupt NOTE: This bit is valid l if both INTEN and I80IFDONE are high. Enables i80 Interface Interrupt (only for I80 Interface mode). 0 = Disables Interrupt1 = Enables Interrupt NOTE: This bit is valid if INTEN is high. Specifies Video Frame Interrupt 0 at start of: 00 = BACK Porch 01 = VSYNC 10 = ACTIVE 11 = FRONT Porch Specifies Video Frame Interrupt 1 at start of: 00 = None 01 = BACK Porch 10 = VSYNC 11 = FRONT Porch Specifies Video Frame Interrupt Enable Control Bit. 0 = Disables Video Frame Interrupt 1 = Enables Video Frame Interrupt NOTE: This bit is valid l when INTEN is high. Specifies FIFO Interrupt control bit. Each bit has a special significance: [11]Window 4 control 0 = Disables 1 = Enables [10]Window 3 control 0 = Disables 1 = Enables [9]Window 2 control 0 = Disables Reset Value 0 0 0 0 0 0 0 0 0 16-95 Exynos 4412_UM 16 Display Controller Name FIFOLEVEL INTFIFOEN INTEN Bit Type Description Reset Value 1 = Enables [8]Reserved [7]Reserved [6]Window 1 control 0 = Disables 1 = Enables [5]Window 0 control 0 = Disables 1 = Enables NOTE: This bit is valid l if both INTEN and INTFIFOEN are high. Selects Video FIFO Interrupt Level. 000 = 0 – 25 % [4:2] RW 001 = 0 – 50 % 0 010 = 0 – 75 % 011 = 0 % (empty) 100 = 100 % (full) Specifies Video FIFO Interrupt Enable Control Bit. [1] RW 0 = Disables video FIFO level interrupt 1 = Enables video FIFO level interrupt 0 NOTE: This bit is valid if INTEN is high. Specifies Video Interrupt Enable Control Bit. [0] RW 0 = Disables video interrupt 0 1 = Enables video interrupt NOTE: 1. If video frame interrupt occurs, then you can select maximum two points by setting FRAMESEL0 and FRAMESEL1. For example, in case of FRAMESEL0 = 00 and FRAMESEL1 = 11, it triggers video frame interrupt both at the start of back porch and front porch. 2. Interrupt controller has three interrupt sources related to display controller, namely, LCD[0], LCD[1], and LCD[2]. (For more information, refer to Chapter 9 interrupt controller"). LCD[0] specifies FIFO Level interrupt, LCD[1] specifies video frame synchronization interrupt and LCD[2] specifies i80 done interface interrupt. 16-96 Exynos 4412_UM 16 Display Controller 16.5.3.37 VIDINTCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x0134, Reset Value = 0x0000_0000 Name RSVD RSVD INTI80PEND INTFRMPEND INTFIFOPEND Bit [31:5] [4:3] [2] [1] [0] Type – – RW RW RW Description Reserved Reserved NOTE: This bit should be set to 0. Specifies i80 done interrupt. Writes "1" to clear this bit. 0 = Does not request interrupt 1 = i80 done status asserts the interrupt request Specifies frame synchronization interrupt. Writes "1" to clear this bit. 0 = Does not request interrupt 1 = Frame synchronization status asserts the interrupt request Specifies FIFO Level interrupt. Writes "1" to clear this bit. 0 = Does not request interrupt 1 = FIFO empty status asserts the interrupt request. Reset Value 0 0 0 0 0 16.5.3.38 W1KEYCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x0140, Reset Value = 0x0000_0000 Name KEYBLEN_F KEYEN_F DIRCON_F COMPKEY_F Bit [26] [25] [24] [23:0] Type RW RW RW RW Description Enables blending. 0 = Disables blending 1 = Enables blending using original alpha for non-key area and KEY_ALPHA for key area Enables/Disables Color Key (Chroma key). 0 = Disables color key 1 = Enables color key Controls color key (Chroma key) direction. 0 = If the pixel value matches foreground image with COLVAL, then it displays the pixel from background image (only in OSD area) 1 = If the pixel value matches background image with COLVAL, then it displays the pixel from foreground image (only in OSD area) Each bit corresponds to COLVAL [23:0]. If some position bit is set, then it disables the position bit of COLVAL. Reset Value 0 0 0 0 NOTE: Set BLD_PIX = 1, ALPHA_SEL = 0, A_FUNC = 0x2, and B_FUNC = 0x3 to enable alpha blending using color key. 16-97 Exynos 4412_UM 16 Display Controller 16.5.3.39 W1KEYCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x0144, Reset Value = 0x0000_0000 Name COLVAL_F Bit Type Description [23:0] RW Specifies color key value for transparent pixel effect. Reset Value 0 16.5.3.40 W2KEYCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x0148, Reset Value = 0x0000_0000 Name KEYBLEN_F KEYEN_F DIRCON_F Bit Type Description Enables blending. [26] RW 0 = Disables blending 1 = Enables blending using original alpha for non-key area and KEY_ALPHA for key area Enables color key (Chroma key). [25] RW 0 = Disables color key 1 = Enables color key Controls color key (Chroma key) direction. 0 = If the pixel value matches foreground image with COLVAL, then it displays the pixel from background image [24] RW (only in OSD area) 1 = If the pixel value matches background image with COLVAL, then it displays the pixel from foreground image (only in OSD area) COMPKEY_F [23:0] Each bit corresponds to COLVAL [23:0]. RW If some position bit is set, then it disables the position bit of COLVAL. Reset Value 0 0 0 0 NOTE: Set BLD_PIX = 1, ALPHA_SEL = 0, A_FUNC = 0x2, and B_FUNC = 0x3 to enable alpha blending using color key. 16.5.3.41 W2KEYCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x014C, Reset Value = 0x0000_0000 Name COLVAL_F Bit Type Description [23:0] RW Specifies color key value for transparent pixel effect. Reset Value 0 16-98 Exynos 4412_UM 16 Display Controller 16.5.3.42 W3KEYCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x0150, Reset Value = 0x0000_0000 Name KEYBLEN_F KEYEN_F DIRCON_F COMPKEY_F Bit [26] [25] [24] [23:0] Type RW RW RW RW Description Enables blending. 0 = Disables blending 1 = Enables blending using original alpha for non-key area and KEY_ALPHA for key area Enables Color Key (Chroma key). 0 = Disables color key 1 = Enables color key Controls Color key (Chroma key) direction. 0 = If the pixel value matches foreground image with COLVAL, then it displays the pixel from background image (only in OSD area) 1 = If the pixel value matches background image with COLVAL, then it displays the pixel from foreground image (only in OSD area) Each bit corresponds to COLVAL[23:0]. If some position bit is set, then it disables the position bit of COLVAL. Reset Value 0 0 0 0 NOTE: Set BLD_PIX = 1, ALPHA_SEL = 0, A_FUNC = 0x2, and B_FUNC = 0x3 to enable alpha blending using color key. 16.5.3.43 W3KEYCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x0154, Reset Value = 0x0000_0000 Name COLVAL_F Bit Type Description [23:0] RW Specifies color key value for transparent pixel effect. Reset Value 0 16-99 Exynos 4412_UM 16 Display Controller 16.5.3.44 W4KEYCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x0158, Reset Value = 0x0000_0000 Name KEYBLEN_F KEYEN_F DIRCON_F COMPKEY_F Bit [26] [25] [24] [23:0] Type RW RW RW RW Description Enables blending. 0 = Disables blending 1 = Enables blending using original alpha for non-key area and KEY_ALPHA for key area Enables color Key (Chroma key). 0 = Disables color key 1 = Enables color key Controls color key (Chroma key) direction. 0 = If the pixel value matches foreground image with COLVAL, then it displays the pixel from background image (only in OSD area) 1 = If the pixel value matches background image with COLVAL, then it displays the pixel from foreground image (only in OSD area) Each bit corresponds to COLVAL[23:0]. If some position bit is set, then it disables the COLVAL position bit. Reset Value 0 0 0 0 NOTE: Set BLD_PIX = 1, ALPHA_SEL = 0, A_FUNC = 0x2, and B_FUNC = 0x3 to enable alpha blending using color key. 16-100 Exynos 4412_UM 16 Display Controller 16.5.3.45 W4KEYCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x015C, Reset Value = 0x0000_0000 Name COLVAL_F Bit Type Description [23:0] RW Specifies color key value for transparent pixel effect. NOTE: Both COLVAL and COMPKEY use 24-bit color data in all BPP modes. At 24 BPP Mode: 24-bit color value is valid.  A. COLVAL  Red: COLVAL[23:17]  Green: COLVAL[15: 8]  Blue: COLVAL[7:0]  B. COMPKEY  Red: COMPKEY[23:17]  Green: COMPKEY[15: 8]  Blue: COMPKEY[7:0] At 16 BPP (5:6:5) mode: 16-bit color value is valid.  A. COLVAL  Red: COLVAL[23:19]  Green: COLVAL[15: 10]  Blue: COLVAL[7:3]  B. COMPKEY  Red: COMPKEY[23:19]  Green: COMPKEY[15: 10]  Blue: COMPKEY[7:3]  COMPKEY[18:16] should be 0x7.  COMPKEY[9: 8] should be 0x3.  COMPKEY[2:0] should be 0x7. NOTE: COMPKEY register should be set properly for each BPP mode. Reset Value 0 16-101 Exynos 4412_UM 16.5.3.46 W1KEYALPHA  Base Address = 0x11C0_0000  Address = Base Address + 0x0160, Reset Value = 0x0000_0000 Name RSVD KEYALPHA_R_F KEYALPHA_G_F KEYALPHA_B_F Bit [31:14] [23:0] [15:8] [7:0] Type – RW RW RW Description Reserved Specifies Key alpha R value. Specifies Key alpha G value. Specifies Key alpha B value. 16.5.3.47 W2KEYALPHA  Base Address = 0x11C0_0000  Address = Base Address + 0x0164, Reset Value = 0x0000_0000 Name RSVD KEYALPHA_R_F KEYALPHA_G_F KEYALPHA_B_F Bit [31:14] [23:0] [15:8] [7:0] Type – RW RW RW Description Reserved Specifies Key alpha R value. Specifies Key alpha G value. Specifies Key alpha B value. 16.5.3.48 W3KEYALPHA  Base Address = 0x11C0_0000  Address = Base Address + 0x0168, Reset Value = 0x0000_0000 Name RSVD KEYALPHA_R_F KEYALPHA_G_F KEYALPHA_B_F Bit [31:14] [23:0] [15:8] [7:0] Type – RW RW RW Description Reserved Specifies Key alpha R value. Specifies Key alpha G value. Specifies Key alpha B value. 16 Display Controller Reset Value 0 0 0 0 Reset Value 0 0 0 0 Reset Value 0 0 0 0 16-102 Exynos 4412_UM 16 Display Controller 16.5.3.49 W4KEYALPHA  Base Address = 0x11C0_0000  Address = Base Address + 0x016C, Reset Value = 0x0000_0000 Name RSVD KEYALPHA_R_F KEYALPHA_G_F KEYALPHA_B_F Bit [31:14] [23:0] [15:8] [7:0] Type – RW RW RW Description Reserved. Specifies Key alpha R value. Specifies Key alpha G value. Specifies Key alpha B value. Reset Value 0 0 0 0 16.5.3.50 DITHMODE  Base Address = 0x11C0_0000  Address = Base Address + 0x0170, Reset Value = 0x0000_0000 Name RSVD RDithPos GDithPos BDithPos DITHEN_F Bit Type Description [7] RW Does not use for normal access (writing not-zero values to these registers results in abnormal behavior.) Controls Red Dither bit. [6:5] RW 00 = 8-bit 01 = 6-bit 10 = 5-bit Controls Green Dither bit. [4:3] RW 00 = 8-bit 01 = 6-bit 10 = 5-bit Controls Blue Dither bit. [2:1] RW 00 = 8-bit 01 = 6-bit 10 = 5-bit Enables Dithering bit. [0] RW 0 = Disables dithering 1 = Enables dithering Reset Value 0 0 0 0 0 16-103 Exynos 4412_UM 16 Display Controller 16.5.3.51 WIN0MAP  Base Address = 0x11C0_0000  Address = Base Address + 0x0180, Reset Value = 0x0000_0000 Name MAPCOLEN_F MAPCOLOR Bit [24] [23:0] Type RW RW Description Specifies color mapping of window control bit. If it enables this bit, then Video DMA stops and MAPCOLOR appears on background image instead of original image. 0 = Disables 1 = Enables Specifies color value. Reset Value 0 0 16.5.3.52 WIN1MAP  Base Address = 0x11C0_0000  Address = Base Address + 0x0184, Reset Value = 0x0000_0000 Name MAPCOLEN_F MAPCOLOR Bit [24] [23:0] Type RW RW Description Specifies the color mapping of window control bit. If it enables this bit, then Video DMA stops and MAPCOLOR appears on background image instead of original image. 0 = Disables 1 = Enables Specifies the color value. Reset Value 0 0 16.5.3.53 WIN2MAP  Base Address = 0x11C0_0000  Address = Base Address + 0x0188, Reset Value = 0x0000_0000 Name MAPCOLEN_F MAPCOLOR Bit [24] [23:0] Type RW RW Description Specifies the color mapping of window control bit. If it enables this bit, then Video DMA stops and MAPCOLOR appears on background image instead of original image. 0 = Disables 1 = Enables Specifies color value. Reset Value 0 0 16-104 Exynos 4412_UM 16 Display Controller 16.5.3.54 WIN3MAP  Base Address = 0x11C0_0000  Address = Base Address + 0x0_018C, Reset Value = 0x0000_0000 Name MAPCOLEN_F MAPCOLOR Bit [24] [23:0] Type RW RW Description Specifies color mapping of window control bit. If it enables this bit, then Video DMA stops and MAPCOLOR appears on background image instead of original image. 0 = Disables 1 = Enables Specifies color value. 16.5.3.55 WIN4MAP  Base Address = 0x11C0_0000  Address = Base Address + 0x0190, Reset Value = 0x0000_0000 Name MAPCOLEN_F MAPCOLOR Bit [24] [23:0] Type RW RW Description Specifies color mapping of window control bit. If it enables this bit, then Video DMA stops and MAPCOLOR appears on background image instead of original image. 0 = Disables 1 = Enables Specifies color value. 16.5.3.56 WPALCON_H  Base Address = 0x11C0_0000  Address = Base Address + 0x019C, Reset Value = 0x0000_0000 Name RSVD W4PAL_H RSVD W3PAL_H RSVD W2PAL_H RSVD Bit [31:19] [18:17] [16:15] [14:13] [12:11] [10: 9] [ 8: 0] Type – RW RW RW RW RW RW Reserved W4PAL[2:1] Reserved W3PAL[2:1] Reserved W2PAL[2:1] Reserved Description Reset Value 0 0 Reset Value 0 0 Reset Value 0 0 0 0 0 0 0 16-105 Exynos 4412_UM 16.5.3.57 WPALCON_L  Base Address = 0x11C0_0000  Address = Base Address + 0x01A0, Reset Value = 0x0000_0000 Name RSVD PALUPDATEEN W4PAL_L W3PAL_L W2PAL_L W1PAL_L W0PAL_L Bit [31:23] [9] [8] [7] [6] [ 5: 3] [ 2: 0] Type – RW RW RW RW RW RW Description Reserved 0 = Normal Mode 1 = Enables (Palette Update) W4PAL[0] W3PAL[0] W2PAL[0] W1PAL[2:0] W0PAL[2:0] NOTE: 1. WPALCON = {WPALCON_H,WPALCON_L} Name Description PALUPDATEEN 0 = Normal Mode 1 = Enables (Palette Update) W4PAL[3:0] Specifies size of palette data format of Window 4. 000 = 16-bit (5:6:5) 001 = 16-bit (A:5:5:5) 010 = 18-bit (6:6:6) 011 = 18-bit (A:6:6:5) 100 = 19-bit (A:6:6:6) 101 = 24-bit (8:8:8) 110 = 25-bit (A:8:8:8) 111 = 32-bit (8:8:8:8) (A: 8-bit) W3PAL[2:0] Specifies size of palette data format of Window 3. 000 = 16-bit (5:6:5) 001 = 16-bit (A:5:5:5) 010 = 18-bit (6:6:6) 011 = 18-bit (A:6:6:5) 100 = 19-bit (A:6:6:6) 101 = 24-bit (8:8:8) 110 = 25-bit (A:8:8:8) 111 = 32-bit (8:8:8:8) (A: 8-bit) W2PAL[2:0] Specifies size of palette data format of Window 2. 000 = 16-bit (5:6:5) 001 = 16-bit (A:5:5:5) 010 = 18-bit (6:6:6) 011 = 18-bit (A:6:6:5) 100 = 19-bit (A:6:6:6) 101 = 24-bit (8:8:8) 110 = 25-bit (A:8:8:8) 111 = 32-bit (8:8:8:8) (A: 8-bit) 16-106 16 Display Controller Reset Value 0 0 0 0 0 0 0 Reset Value 0 0 0 0 Exynos 4412_UM Name W1PAL[2:0] W0PAL[2:0] Description Specifies size of palette data format of Window 1. 000 = 25-bit (A:8:8:8) 001 = 24-bit (8:8:8) 010 = 19-bit (A:6:6:6) 011 = 18-bit (A:6:6:5) 100 = 18-bit (6:6:6) 101 = 16-bit (A:5:5:5) 110 = 16-bit (5:6:5) 111 = 32-bit (8:8:8:8) (A: 8-bit) Specifies size of palette data format of Window 0. 000 = 25-bit (A:8:8:8) 001 = 24-bit (8:8:8) 010 = 19-bit (A:6:6:6) 011 = 18-bit (A:6:6:5) 100 = 18-bit (6:6:6) 101 = 16-bit (A:5:5:5) 110 = 16-bit (5:6:5) 111 = 32-bit (8:8:8:8) (A: 8-bit) 2. The bit map for W0/ W1 is different from W2/W3/W4. 16 Display Controller Reset Value 0 0 16-107 Exynos 4412_UM 16 Display Controller 16.5.3.58 TRIGCON  Base Address = 0x11C0_0000  Address = Base Address + 0x01A4, Reset Value = 0x0000_0000 Name RSVD SWTRGCMD _W4BUF TRGMODE _W4BUF RSVD SWTRGCMD _W3BUF TRGMODE _W3BUF RSVD SWTRGCMD _W2BUF TRGMODE _W2BUF RSVD SWTRGCMD _W1BUF TRGMODE _W1BUF RSVD SWTRGCMD _W0BUF TRGMODE_W0B UF RSVD SWFRSTATUS Bit [31:27] [26] [25] [24:22] [21] [20] [19:17] [16] [15] [14:12] [11] [10] [9:7] [6] [5] [4:3] [2] Type – RW RW – RW RW – RW RW – RW RW – RW RW – RW Description Reserved Specifies Window 4 double buffer trigger. 1 = Enables Software Trigger Command (write only) NOTE: Only when TRGMODE_W4BUF is set to "1" Specifies Window 4 double buffer trigger. 0 = Disables trigger 1 = Enables trigger Reserved Specifies Window 3 double buffer trigger. 1 = Enables Software Trigger Command (write only) NOTE: Only when TRGMODE_W3BUF is set to "1" Specifies Window 3 double buffer trigger. 0 = Disables trigger 1 = Enables trigger Reserved Specifies Window 2 double buffer trigger. 1 = Enables Software Trigger Command (write only) NOTE: Only when TRGMODE_W2BUF is set to "1" Specifies Window 2 double buffer trigger. 0 = Disables trigger 1 = Enables trigger Reserved Specifies Window 1 double buffer trigger. 1 = Enables Software Trigger Command (write only) NOTE: Only when TRGMODE_W1BUF is set to "1" Specifies Window 1 double buffer trigger. 0 = Disables trigger 1 = Enables trigger Reserved Specifies Window 0 double buffer trigger. 1 = Enables Software Trigger Command (write only) NOTE: Only when TRGMODE_W0BUF is set to "1" Specifies Window 0 double buffer trigger. 0 = Disables trigger 1 = Enables trigger Reserved Specifies Frame Done Status (read only; i80 start Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16-108 Exynos 4412_UM 16 Display Controller Name _I80 SWTRGCMD _I80 TRGMODE_I80 Bit Type Description trigger) 0 = Does not request 1 = Requests NOTE: 1. Clear Condition: Read or New Frame Start 2. Only when TRGMODE is set to "1" Enables i80 start trigger. [1] RW 1 = Software Triggering Command (write only) NOTE: Only when TRGMODE is set to "1" Enables i80 start trigger. [0] RW 0 = Disables i80 Software Trigger 1 = Enables i80 Software Trigger Reset Value 0 0 NOTE: Generates two continuous software trigger inputs in some video clocks (VCLK) recognizes as one. 16-109 Exynos 4412_UM 16 Display Controller 16.5.3.59 I80IFCONAn (n = 0 to 1)  Base Address = 0x11C0_0000  Address = Base Address + 0x01B0, Reset Value = 0x0000_0000 (I80IFCONA0)  Address = Base Address + 0x01B4, Reset Value = 0x0000_0000 (I80IFCONA1) Name RSVD LCD_CS_SETUP LCD_WR_SETUP LCD_WR_ACT LCD_WR_HOLD RSVD RSPOL RSVD I80IFEN Bit [22:20] [19:16] [15:12] [11:8] [7:4] [3] [2] [1] [0] Type – RW RW RW RW – RW – RW Description Reserved Specifies number of clock cycles for the active period of address signal enable to chip select enable. Specifies number of clock cycles for the active period of CS signal enable to write signal enable. Specifies number of clock cycles for the active period of chip select enable. Specifies number of clock cycles for the active period of chip select disable to write signal disable. Reserved Specifies polarity of RS Signal 0 = Low 1 = High Reserved Controls the LCD i80 interface. 0 = Disables 1 = Enables Reset Value 0 0 0 0 0 – 0 0 0 16-110 Exynos 4412_UM 16 Display Controller 16.5.3.60 I80IFCONBn (n = 0 to 1)  Base Address = 0x11C0_0000  Address = Base Address + 0x01B8, Reset Value = 0x0000_0000 (I80IFCONB0)  Address = Base Address + 0x01BC, Reset Value = 0x0000_0000 (I80IFCONB1) Name RSVD NORMAL_CMD_ST RSVD FRAME_SKIP RSVD AUTO_CMD_RATE Bit [11:10] [9] [8:7] [6:5] [4] [3:0] Type – RW – RW – RW Description Reserved 1 = Normal Command Start NOTE: Auto clears after sending out one set of commands Reserved Specifies i80 Interface Output Frame Decimation Factor. 00 = 1 (Does not Skip) 01 = 2 10 = 3 Reserved 0000 = Disables auto command (if you do not use any auto-command, then you should set AUTO_CMD_RATE as "0000".) 0001 = per 2 Frames 0010 = per 4 Frames 0011 = per 6 Frames … 1111 = per 30 Frames Reset Value 0 0 – 00 0 0000 16-111 Exynos 4412_UM 16 Display Controller 16.5.3.61 COLORGAINCON  Base Address = 0x11C0_0000  Address = Base Address + 0x01C0, Reset Value = 0x1004_0100 Name RSVD CG_RGAIN CG_GGAIN CG_BGAIN Bit [31:30] [29:20] [19:10] [9:0] Type – RW RW RW Description Reserved Specifies color gain value of R data (maximum 4, 8-bit resolution). 0h000 = 0 0h001 = 0.00390625 (1/256) 0h002 = 0.0078125 (2/256) … 0h0FF = 0.99609375 (255/256) 0h100 = 1.0 … 0x3FF = 3.99609375 (maximum) Specifies color gain value of G data (maximum 4, 8-bit resolution). 0h000 = 0 0h001 = 0.00390625 (1/256) 0h002 = 0.0078125 (2/256) … 0h0FF = 0.99609375 (255/256) 0h100 = 1.0 … 0x3FF = 3.99609375 (maximum) Specifies color gain value of B data (maximum 4, 8-bit resolution). 0h000 = 0 0h001 = 0.00390625 (1/256) 0h002 = 0.0078125 (2/256) … 0h0FF = 0.99609375 (255/256) 0h100 = 1.0 … 0x3FF = 3.99609375 (maximum) Reset Value 0 0x100 0x100 0x100 16-112 Exynos 4412_UM 16.5.3.62 LDI_CMDCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x01D0, Reset Value = 0x0000_0000 Name RSVD CMD11_EN CMD10_EN CMD9_EN CMD8_EN CMD7_EN CMD6_EN CMD5_EN CMD4_EN Bit [31:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] Type – RW RW RW RW RW RW RW RW Description Reserved Controls command 11 00 = Disables 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command Controls command 11 00 = Disables 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command Controls command 11 00 = Disables 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command Controls command 11 00 = Disables 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command Controls command 11 00 = Disables 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command Controls command 11 00 = Disables 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command Controls command 11 00 = Disables 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command Controls command 11 00 = Disables 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command 16-113 16 Display Controller Reset Value – 00 00 00 00 00 00 00 00 Exynos 4412_UM Name CMD3_EN CMD2_EN CMD1_EN CMD0_EN Bit Type Description Controls command 11 00 = Disables [7:6] RW 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command Controls command 11 00 = Disables [5:4] RW 01 = Enables Normal Command 10 = Enables Auto Command 11 = Normal and Auto Command Enable Controls command 11 00 = Disables [3:2] RW 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command Controls command 11 00 = Disables [1:0] RW 01 = Enables Normal Command 10 = Enables Auto Command 11 = Enables Normal and Auto Command 16 Display Controller Reset Value 00 00 00 00 16-114 Exynos 4412_UM 16.5.3.63 LDI_CMDCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x01D4, Reset Value = 0x0000_0000 Name RSVD CMD11_RS CMD10_RS CMD9_RS CMD8_RS CMD7_RS CMD6_RS CMD5_RS CMD4_RS CMD3_RS CMD2_RS CMD1_RS CMD0_RS Bit [31:10] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Type – RW RW RW RW RW RW RW RW RW RW RW RW Description Reserved. Controls Command 11 RS Controls Command 10 RS Controls Command 9 RS Controls Command 8 RS Controls Command 7 RS Controls Command 6 RS Controls Command 5 RS Controls Command 4 RS Controls Command 3 RS Controls Command 2 RS Controls Command 1 RS Controls Command 0 RS 16 Display Controller Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 16-115 Exynos 4412_UM 16 Display Controller 16.5.3.64 SIFCCON0  Base Address = 0x11C0_0000  Address = Base Address + 0x01E0, Reset Value = 0x0000_0000 Name Bit Type Description RSVD Reserved [7] – NOTE: This bit should be set to 0. SYS_ST_CON Controls LCD i80 System Interface ST Signal. [6] RW 0 = Low 1 = High SYS_RS_CON Controls LCD i80 System Interface RS Signal. [5] RW 0 = Low 1 = High SYS_nCS0_CON [4] Controls LCD i80 System Interface nCS0 (main) Signal. RW 0 = Disables (High) 1 = Enables (Low) SYS_nCS1_CON [3] Controls LCD i80 System Interface nCS1 (sub) Signal. RW 0 = Disables (High) 1 = Enables (Low) SYS_nOE_CON Controls LCD i80 System Interface nOE Signal. [2] RW 0 = Disables (High) 1 = Enables (Low) Controls LCD i80 System Interface nWE Signal. SYS_nWE_CON [1] RW 0 = Disables (High) 1 = Enables (Low) SCOMEN Enables LCD i80 System Interface Command Mode. [0] RW 0 = Disables (Normal Mode) 1 = Enables (Manual Command Mode) Reset Value 0 0 0 0 0 0 0 16.5.3.65 SIFCCON1  Base Address = 0x11C0_0000  Address = Base Address + 0x01E4, Reset Value = 0x0000_0000 Name SYS_WDATA Bit Type Description [23:0] RW Controls LCD i80 System Interface Write Data. Reset Value 0 16-116 Exynos 4412_UM 16 Display Controller 16.5.3.66 SIFCCON2  Base Address = 0x11C0_0000  Address = Base Address + 0x01E8, Reset Value = 0x????_???? Name SYS_RDATA Bit Type Description [23:0] R Controls LCD i80 System Interface Read Data. Reset Value 0 16.5.3.67 HUECOEF_CR_n (n = 1 to 4)  Base Address = 0x11C0_0000  Address = Base Address + 0x01EC, Reset Value = 0x0100_0100 (HUECOEF_CR_1)  Address = Base Address + 0x01F0, Reset Value = 0x0000_0000 (HUECOEF_CR_2)  Address = Base Address + 0x01F4, Reset Value = 0x0000_0000 (HUECOEF_CR_3)  Address = Base Address + 0x01F8, Reset Value = 0x0100_0100 (HUECOEF_CR_4) Name RSVD CRG0_x RSVD CRG1_x Bit [31:26] [25:16] [15:10] [9:0] Type – RW – RW Description Reserved Specifies Hue matrix coefficient 00 (when "cb + In_offset" is positive). (Signed) 0h000 = 0 0h001 = 0.00390625 (1/256) 0h002 = 0.0078125 (2/256) … 0h0FF = 0.99609375 (255/256) 0h100 = 1.0 (256/256) 0h300 = – 1.0 (– 256/256) 0h301 = – 0.99609375 (– 255/256) … 0h3FF = – 0.00390625 (– 1/256) 0h101 to 2FF = Reserved (do not use) Reserved Specifies Hue matrix coefficient 00 (when "cb + In_offset" is negative). (Signed) 0h000 = 0 0h001 = 0.00390625 (1/256) 0h002 = 0.0078125 (2/256) … 0h0FF = 0.99609375 (255/256) 0h100 = 1.0 (256/256) 0h300 = – 1.0 (– 256/256) 0h301 = – 0.99609375 (– 255/256) … 0h3FF = – 0.00390625 (– 1/256) 0h101 to 2FF =