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Data manual of TI J6 CPU (dual ARM Cortex-A15)

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EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 1.0 Texas Instruments Jacinto6 Ex and Jacinto6 Infotainment Families of Products Version G Data Manual TI Confidential — NDA Restrictions ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Literature Number: SPRS857G December 2012 – Revised November 2013 EARLY PRELIMINARY WARNING: EXPORT NOTICE Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorisation from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. This provision shall survive termination or expiration of this Agreement. According to our best knowledge of the state and end-use of this product or technology, and in compliance with the export control regulations of dual-use goods in force in the origin and exporting countries, this technology is classified as follows: US ECCN: 5E991 EU ECCN: EAR99 And may require export or re-export license for shipping it in compliance with the applicable regulations of certain countries. ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Contents 1 Introduction ...................................................................................................................... 17 1.1 Device Comparison ....................................................................................................... 18 1.2 Device Support Nomenclature ........................................................................................... 20 1.3 About This Manual ........................................................................................................ 20 1.4 Trademarks ................................................................................................................ 21 1.5 Community Resources .................................................................................................... 22 2 Terminal Description .......................................................................................................... 23 2.1 Terminal Assignment ...................................................................................................... 23 2.1.1 Unused balls connection requirements ...................................................................... 23 2.2 Ball Characteristics ........................................................................................................ 24 2.3 Multiplexing Characteristics .............................................................................................. 93 2.4 Signal Descriptions ...................................................................................................... 109 2.4.1 Video Input Ports (VIP) ....................................................................................... 109 2.4.2 Display Subsystem – Video Output Ports (DPI) .......................................................... 114 2.4.3 Display Subsystem – High-Definition Multimedia Interface (HDMI) .................................... 116 2.4.4 External Memory Interface (DDR2/DDR3/DDR3L SDRAM) ............................................. 116 2.4.5 General-Purpose Memory Controller (GPMC) ............................................................ 120 2.4.6 Timers .......................................................................................................... 122 2.4.7 Inter Integrated Circuit Interface (I2C) ...................................................................... 123 2.4.8 HDQ / 1-Wire Interface (HDQ1W) .......................................................................... 124 2.4.9 Universal Asynchronous Receiver Transmitter (UART) .................................................. 124 2.4.10 Multichannel Serial Port Interface (McSPI) ................................................................ 125 2.4.11 Quad Serial Port Interface (QSPI) .......................................................................... 126 2.4.12 Multicannel Audio Serial Port (McASP) .................................................................... 127 2.4.13 Universal Serial Bus (USB) .................................................................................. 129 2.4.14 SATA ............................................................................................................ 130 2.4.15 Peripheral Component Interconnect Express (PCIe) ..................................................... 131 2.4.16 Describes the Controller Area Network Interface (DCAN) ............................................... 131 2.4.17 Ethernet Interface (GMAC_SW) ............................................................................. 132 2.4.18 Media Local Bus (MLB) Interface ........................................................................... 133 2.4.19 eMMC/SD/SDIO ............................................................................................... 134 2.4.20 General-Purpose Interface (GPIO) ......................................................................... 135 2.4.21 Keyboard controller (KBD) ................................................................................... 140 2.4.22 Pulse Width Modulation (PWM) Interface .................................................................. 141 2.4.23 Audio Tracking Logic (ATL) .................................................................................. 142 2.4.24 Test Interfaces ................................................................................................. 142 2.4.24.1 Hardware Debug .................................................................................. 142 2.4.25 System and Miscellaneous .................................................................................. 143 2.4.25.1 Sysboot ............................................................................................ 143 2.4.25.2 Power, Reset and Clock Menager (PRCM) ................................................... 144 2.4.25.3 Real Time Clock (RTC) Interface ............................................................... 144 2.4.25.4 System Direct Memory Access (SDMA) ....................................................... 145 2.4.25.5 Interrupt Controllers (INTC) ..................................................................... 145 2.4.25.6 Obserabitily ........................................................................................ 145 2.4.26 Power Supplies ................................................................................................ 146 3 Electrical Characteristics .................................................................................................. 150 3.1 Absolute Maximum Ratings ............................................................................................ 150 3.2 Recommended Operating Conditions ................................................................................. 152 3.3 Operating Performance Points ......................................................................................... 156 3.3.1 Microprocessor Unit (MPU) Voltage And Clock Specifications ......................................... 156 3.3.2 Digital Signal Processor (DSP) and EVE Voltage And Clock Specifications .......................... 157 Copyright © 2012–2013, Texas Instruments Incorporated Contents 3 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 3.3.3 Image and Video Accelerator (IVA) Voltage And Clock Specifications ................................ 158 3.3.4 3D Graphic Accelerator (GPU) Voltage And Clock Specifications ..................................... 159 3.3.5 Core and Peripheral Voltage And Clock Specifications .................................................. 159 3.3.6 RTC Voltage And Clock Specifications .................................................................... 160 3.3.7 Maximum Supported Frequency ............................................................................ 160 3.4 DC Electrical Characteristics ........................................................................................... 180 3.4.1 LVCMOS DDR DC Electrical Characteristics ............................................................. 180 3.4.2 HDMIPHY DC Electrical Characteristics ................................................................... 183 3.4.3 Dual Voltage LVCMOS I2C DC Electrical Characteristics ............................................... 183 3.4.4 USB DC Electrical Characteristics .......................................................................... 185 3.4.4.1 USB2PHY DC Electrical Characteristics ...................................................... 185 3.4.4.2 USB3PHY DC Electrical Characteristics ...................................................... 185 3.4.5 MMC1 DC Electrical Characteristics ........................................................................ 186 3.4.6 Dual Voltage LVCMOS DC Electrical Characteristics .................................................... 186 3.4.7 SATAPHY DC Electrical Characteristics ................................................................... 187 3.4.8 PCIEPHY DC Electrical Characteristics .................................................................... 187 3.4.9 MLB DC Electrical Characteristics .......................................................................... 188 3.4.10 System DC Electrical Characteristics ...................................................................... 188 3.5 External Capacitors ...................................................................................................... 188 3.6 Power Sequencing ....................................................................................................... 188 4 Clock Specifications ........................................................................................................ 198 4.1 Input Clock Specifications .............................................................................................. 199 4.1.1 Input Clock Requirements ................................................................................... 199 4.1.2 System Oscillator OSC0 Input Clock ....................................................................... 200 4.1.2.1 OSC0 External Crystal ........................................................................... 200 4.1.2.2 OSC0 Input Clock ................................................................................ 201 4.1.3 Auxiliary Oscillator OSC1 Input Clock ...................................................................... 202 4.1.3.1 OSC1 External Crystal ........................................................................... 202 4.1.3.2 OSC1 Input Clock ................................................................................ 204 4.1.4 RTC Oscillator Input Clock ................................................................................... 205 4.1.4.1 RTC Oscillator External Crystal ................................................................ 205 4.1.4.2 RTC Oscillator Input Clock ...................................................................... 206 4.2 Output Clock Specifications ............................................................................................ 207 4.2.1 clkout[3:1] Output Clocks .................................................................................... 207 4.2.2 DPLLs, DLLs Specifications ................................................................................. 207 4.2.2.1 DPLL Characteristics ............................................................................. 208 4.2.2.2 DLL Characteristics .............................................................................. 212 4.2.2.3 DPLL and DLL Noise Isolation .................................................................. 212 4.2.3 Internal 32-kHz Oscillator .................................................................................... 212 5 Timing Requirements and Switching Characteristics ........................................................... 213 5.1 Timing Test Conditions .................................................................................................. 213 5.2 Interface Clock Specifications .......................................................................................... 213 5.2.1 Interface Clock Terminology ................................................................................. 213 5.2.2 Interface Clock Frequency ................................................................................... 213 5.2.3 Clock Jitter Specifications .................................................................................... 213 5.2.4 Clock Duty Cycle Error ....................................................................................... 214 5.3 Timing Parameters ....................................................................................................... 214 5.4 Video Input Ports (VIP) .................................................................................................. 215 5.5 Display Subsystem – Video Output Ports ............................................................................ 229 5.6 Display Subsystem – High-Definition Multimedia Interface (HDMI) ............................................... 234 5.7 External Memory Interface (EMIF) ..................................................................................... 234 5.8 General-Purpose Memory Controller (GPMC) ....................................................................... 234 5.8.1 GPMC/NOR Flash Interface Synchronous Timing ........................................................ 234 4 Contents Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 5.8.2 GPMC/NOR Flash Interface Asynchronous Timing ...................................................... 243 5.8.3 GPMC/NAND Flash Interface Asynchronous Timing ..................................................... 250 5.9 Timers ..................................................................................................................... 256 5.10 Inter-Integrated Circuit Interface (I2C) ................................................................................ 256 5.11 HDQ / 1-Wire Interface (HDQ1W) ..................................................................................... 259 5.11.1 HDQ / 1-Wire — HDQ Mode ................................................................................ 259 5.11.2 HDQ/1-Wire—1-Wire Mode .................................................................................. 260 5.12 Universal Asynchronous Receiver Transmitter (UART) ............................................................ 261 5.13 Multichannel Serial Port Interface (MCSPI) .......................................................................... 262 5.14 Quad Serial Port Interface (QSPI) ..................................................................................... 268 5.15 Multichannel Audio Serial Port (McASP) ............................................................................. 272 5.16 Universal Serial Bus (USB) ............................................................................................. 283 5.16.1 USB1 DRD PHY ............................................................................................... 283 5.16.2 USB2 PHY ..................................................................................................... 283 5.16.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode—1.8 V ............................. 283 5.17 Serial Advanced Technology Attachment (SATA) ................................................................... 284 5.18 Peripheral Component Interconnect Express (PCIe) ................................................................ 284 5.19 Controller Area Network Interface (DCAN) ........................................................................... 285 5.20 Ethernet Interface (GMAC_SW) ....................................................................................... 286 5.20.1 GMAC MII Timings ............................................................................................ 286 5.20.2 GMAC MDIO Interface Timings ............................................................................. 288 5.20.3 GMAC RMII Timings .......................................................................................... 289 5.20.4 GMAC RGMII Timings ........................................................................................ 290 5.21 Media Local Bus (MLB) interface ...................................................................................... 292 5.22 eMMC/SD/SDIO .......................................................................................................... 294 5.22.1 MMC1—SD Card Interface .................................................................................. 294 5.22.1.1 Default speed at 24 MHz, 4-bit data, SDR, half-cycle, 3.3 V ............................... 294 5.22.1.2 High speed at 48 MHz, 4-bit data, SDR, half-cycle, 3.3 V .................................. 296 5.22.1.3 SDR12 at 24 MHz, 4-bit data, half-cycle, 1.8 V .............................................. 297 5.22.1.4 SDR25 at 48 MHz, 4-bit data, half-cycle, 1.8 V .............................................. 298 5.22.1.5 UHS-I SDR50 at 96 MHz, 4-bit data, half-cycle, 1.8 V ...................................... 299 5.22.1.6 UHS-I SDR104 at 192 MHz, 4-bit data, half-cycle, 1.8 V ................................... 300 5.22.1.7 UHS-I DDR50 at 48 MHz, 4-bit data, 1.8 V ................................................... 301 5.22.2 MMC2 — eMMC .............................................................................................. 303 5.22.2.1 Standard JC64 SDR at 24 MHz, 8-bit data, half cycle, 1.8 V ............................... 303 5.22.2.2 High-speed JC64 SDR at 48 MHz, 8-bit data, half cycle, 3.3 V ............................ 304 5.22.2.3 High-speed HS200 JC64 SDR at 192 MHz, 8-bit data, half cycle, 1.8 V ................. 306 5.22.2.4 High-speed JC64 DDR at 48 MHz, 8-bit data, 1.8 V ........................................ 306 5.22.3 MMC3 and MMC4—SDIO/SD, 1.8 V ....................................................................... 308 5.22.3.1 MMC3 and MMC4, SDIO Standard Speed SDR12 Mode, 24 MHz, Half Cycle, 1.8 V .. 308 5.22.3.2 MMC3 and MMC4, SDIO High-Speed SDR25 Mode, 48 MHz, Half Cycle, 1.8 V ....... 309 5.22.3.3 MMC3 SDIO High-Speed UHS-I SDR50 Mode, 96 MHz, Half Cycle, 1.8 V .............. 311 5.22.3.4 MMC3 and MMC4, SD Default Speed, 1.8 V ................................................. 312 5.22.3.5 MMC3 and MMC4, SD High Speed, 1.8 V .................................................... 313 5.22.3.6 MMC3 and MMC4, SD SDR12 Mode, 1.8 V .................................................. 315 5.22.3.7 MMC3 and MMC4, SD SDR25 Mode, 1.8 V .................................................. 316 5.23 General-Purpose Interface (GPIO) .................................................................................... 318 5.24 Keyboard controller (KBD) .............................................................................................. 318 5.25 Pulse Width Modulation (PWM) Interface ............................................................................ 318 5.26 Audio Tracking Logic (ATL) ............................................................................................. 319 5.26.1 ATL Electrical Data/Timing ................................................................................... 319 5.27 System and Miscellaneous interfaces ................................................................................. 319 5.27.1 Reset Electrical Data/Timing ................................................................................ 319 Copyright © 2012–2013, Texas Instruments Incorporated Contents 5 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 5.28 Test Interfaces ............................................................................................................ 320 5.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG) ......................................................... 320 5.28.1.1 JTAG Electrical Data/Timing .................................................................... 320 5.28.1.2 Compact JTAG Interface (cJTAG) ............................................................. 322 5.28.2 Trace Port Interface Unit (TPIU) ............................................................................ 323 5.28.2.1 TPIU PLL DDR Mode ............................................................................ 323 6 Thermal Management ....................................................................................................... 324 6.1 Package Thermal Characteristics ...................................................................................... 324 7 Package Characteristics ................................................................................................... 325 7.1 Device Nomenclature .................................................................................................... 325 7.1.1 Standard Package Symbolization ........................................................................... 325 7.1.2 SAP Part Number ............................................................................................. 325 7.1.3 Device Naming Convention .................................................................................. 325 7.2 Mechanical Data ......................................................................................................... 327 8 PCB Guidelines ............................................................................................................... 328 8.1 Introduction ............................................................................................................... 328 8.1.1 Initial Requirements and Guidelines ........................................................................ 328 8.2 Power Optimizations ..................................................................................................... 329 8.2.1 Step 1: PCB Stack-up ........................................................................................ 329 8.2.2 Step 2: Physical Placement .................................................................................. 331 8.2.3 Step 3: Static Analysis ........................................................................................ 334 8.2.3.1 PDN Resistance and IR Drop ................................................................... 336 8.2.4 Step 4: Frequency Analysis .................................................................................. 336 8.2.5 System ESD Generic Guidelines ............................................................................ 339 8.2.5.1 System ESD Generic PCB Guideline .......................................................... 339 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity ................................. 340 8.2.6 EMI / EMC Issues Prevention ............................................................................... 340 8.2.6.1 Signal Bandwidth ................................................................................. 340 8.2.6.2 Signal Routing .................................................................................... 341 8.2.6.3 Ground Guidelines ............................................................................... 341 8.3 Core Power Domains .................................................................................................... 342 8.3.1 General Constraints ........................................................................................... 342 8.3.2 Voltage Decoupling ........................................................................................... 343 8.3.3 Static PDN Analysis .......................................................................................... 344 8.3.4 Dynamic PDN Analysis ....................................................................................... 344 8.3.5 Power Supply Mapping ....................................................................................... 345 8.3.6 DPLL Voltage Requirement .................................................................................. 345 8.3.7 Example PCB Design ......................................................................................... 346 8.3.7.1 Example Stack-up ................................................................................ 346 8.3.7.2 vdd_mpu Example Analysis ..................................................................... 346 8.4 Single-Ended Interfaces ................................................................................................. 352 8.4.1 General Routing Guidelines ................................................................................. 352 8.4.2 QSPI Board Design and Layout Guidelines ............................................................... 353 8.5 Differential Interfaces .................................................................................................... 354 8.5.1 General Routing Guidelines ................................................................................. 354 8.5.2 USB 2.0 Board Design and Layout Guidelines ............................................................ 355 8.5.2.1 Background ........................................................................................ 355 8.5.2.2 USB PHY Layout Guide ......................................................................... 355 8.5.2.3 Electrostatic Discharge (ESD) .................................................................. 362 8.5.2.4 References ........................................................................................ 364 8.5.3 USB 3.0 Board Design and Layout Guidelines ............................................................ 364 8.5.3.1 USB 3.0 interface introduction .................................................................. 364 8.5.3.2 USB 3.0 General routing rules .................................................................. 365 6 Contents Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com 8.6 8.7 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 8.5.4 HDMI Board Design and Layout Guidelines ............................................................... 366 8.5.4.1 HDMI Interface Schematic ...................................................................... 366 8.5.4.2 TMDS Routing .................................................................................... 367 8.5.4.3 TPDS115 .......................................................................................... 368 8.5.4.4 HDMI ESD Protection Device (Required) ..................................................... 368 8.5.4.5 PCB Stackup Specifications .................................................................... 368 8.5.4.6 Grounding ......................................................................................... 368 8.5.5 SATA Board Design and Layout Guidelines ............................................................... 368 8.5.5.1 SATA Interface Schematic ...................................................................... 369 8.5.5.2 Compatible SATA Components and Modes .................................................. 369 8.5.5.3 PCB Stackup Specifications .................................................................... 369 8.5.5.4 Routing Specifications ........................................................................... 370 8.5.6 PCIe Board Design and Layout Guidelines ................................................................ 370 8.5.6.1 PCIe Connections and Interface Compliance ................................................. 370 8.5.6.2 Non-standard PCIe connections ................................................................ 371 Clock Routing Guidelines ............................................................................................... 372 8.6.1 32-kHz Oscillator Routing .................................................................................... 372 8.6.2 Oscillator Ground Connection ............................................................................... 373 DDR2/DDR3 Board Design and Layout Guidelines ................................................................. 374 8.7.1 DDR2/DDR3 General Board Layout Guidelines .......................................................... 374 8.7.2 DDR3 Board Design and Layout Guidelines .............................................................. 374 8.7.2.1 Board Designs .................................................................................... 374 8.7.2.2 DDR3 EMIFs ...................................................................................... 375 8.7.2.3 DDR3 Device Combinations .................................................................... 375 8.7.2.4 DDR3 Interface Schematic ...................................................................... 375 8.7.2.5 Compatible JEDEC DDR3 Devices ............................................................ 379 8.7.2.6 PCB Stackup ...................................................................................... 379 8.7.2.7 Placement ......................................................................................... 380 8.7.2.8 DDR3 Keepout Region .......................................................................... 381 8.7.2.9 Bulk Bypass Capacitors ......................................................................... 382 8.7.2.10 High-Speed Bypass Capacitors ................................................................ 383 8.7.2.11 Net Classes ....................................................................................... 384 8.7.2.12 DDR3 Signal Termination ....................................................................... 384 8.7.2.13 VREFSSTL_DDR Routing ....................................................................... 384 8.7.2.14 VTT ................................................................................................. 384 8.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition .................................. 385 8.7.2.16 Data Topologies and Routing Definition ....................................................... 392 8.7.2.17 Routing Specification ............................................................................. 394 Copyright © 2012–2013, Texas Instruments Incorporated Contents 7 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com List of Figures 2-1 ABC S-PBGA-N760 Package (Bottom View)................................................................................. 23 3-1 Power-Up Sequencing ......................................................................................................... 189 3-2 Power-Down Sequencing ..................................................................................................... 191 3-3 RTC Mode Sequencing ........................................................................................................ 193 3-4 Power-Up Sequencing ......................................................................................................... 194 3-5 Power-Down Sequencing ..................................................................................................... 196 4-1 Clock Interface .................................................................................................................. 199 4-2 Crystal Implementation......................................................................................................... 200 4-3 1.8-V LVCMOS-Compatible Clock Input..................................................................................... 201 4-4 xi_osc0 Input Clock............................................................................................................. 202 4-5 Crystal Implementation......................................................................................................... 203 4-6 1.8-V LVCMOS-Compatible Clock Input..................................................................................... 204 4-7 xi_osc1 Input Clock............................................................................................................. 205 4-8 Crystal Implementation......................................................................................................... 205 4-9 LVCMOS-Compatible Clock Input ............................................................................................ 206 4-10 rtc_osc_xi_clkin32 Input Clock ................................................................................................ 207 4-11 clkoutx Output Clocks .......................................................................................................... 207 5-1 Cycle (or Period) Jitter ......................................................................................................... 213 5-2 Video Input Ports clock signal................................................................................................. 215 5-3 Video Input Ports timings ...................................................................................................... 215 5-4 DPI Video Output .............................................................................................................. 230 5-5 GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read - (GpmcFCLKDivider = 0) ....................................................................................................... 238 5-6 GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Single Read - (GpmcFCLKDivider = 0) ....................................................................................................... 239 5-7 GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits - (GpmcFCLKDivider = 0) ....................................................................................................... 240 5-8 GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits - (GpmcFCLKDivider = 0) ....................................................................................................... 241 5-9 GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits - (GpmcFCLKDivider = 0) ....................................................................................................... 242 5-10 GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits - (GpmcFCLKDivider = 0) ..... 243 5-11 GPMC / NOR Flash - Asynchronous Read - Single Word Timing ....................................................... 245 5-12 GPMC / NOR Flash - Asynchronous Read - 32-bit Timing ............................................................... 246 5-13 GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing .............................................. 247 5-14 GPMC / NOR Flash - Asynchronous Write - Single Word Timing........................................................ 248 5-15 GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing ......................................... 249 5-16 GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing ......................................... 250 5-17 GPMC / NAND Flash - Command Latch Cycle Timing .................................................................... 251 5-18 GPMC / NAND Flash - Address Latch Cycle Timing....................................................................... 252 5-19 GPMC / NAND Flash - Data Read Cycle Timing ........................................................................... 252 5-20 GPMC / NAND Flash - Data Write Cycle Timing ........................................................................... 253 5-21 I2C Receive Timing............................................................................................................. 257 5-22 I2C Transmit Timing ............................................................................................................ 259 5-23 HDQ Break and Break Recovery Timing — HDQ Interface Writing to Slave........................................... 259 5-24 Device HDQ Interface Bit Read Timing (Data).............................................................................. 259 5-25 Device HDQ Interface Bit Write Timing (Command / Address or Data) ................................................. 260 5-26 HDQ Communication Timing.................................................................................................. 260 8 List of Figures Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 5-27 1-Wire—Break (Reset) ......................................................................................................... 260 5-28 1-Wire—Read Bit (Data) ....................................................................................................... 261 5-29 1-Wire—Write Bit-One Timing (Command / Address or Data) ........................................................... 261 5-30 UART Timing .................................................................................................................... 262 5-31 McSPI - Master Mode Transmit............................................................................................... 265 5-32 McSPI - Master Mode Receive ............................................................................................... 265 5-33 McSPI - Slave Mode Transmit ............................................................................................... 267 5-34 McSPI - Slave Mode Receive ................................................................................................ 267 5-35 QSPI Read (PHA=1) ........................................................................................................... 270 5-36 QSPI Read (PHA=0) ........................................................................................................... 270 5-37 QSPI Write (PHA=1)............................................................................................................ 272 5-38 QSPI Write (PHA=0)............................................................................................................ 272 5-39 McASP Input Timing............................................................................................................ 275 5-40 McASP Output Timing ......................................................................................................... 278 5-41 HS USB3 and USB4 ULPI —SDR—Slave Mode—12-pin Mode—1.8 V................................................ 284 5-42 DCANx Timings ................................................................................................................. 286 5-43 Clock Timing (GMAC Receive) - MIIn operation............................................................................ 287 5-44 Clock Timing (GMAC Transmit) - MIIn operation........................................................................... 287 5-45 GMAC Receive Interface Timing MIIn operation ........................................................................... 288 5-46 GMAC Transmit Interface Timing MIIn operation........................................................................... 288 5-47 GMAC MDIO diagrams ........................................................................................................ 289 5-48 GMAC Receive Interface Timing RMIIn operation ......................................................................... 290 5-49 GMAC Transmit Interface Timing RMIIn Operation ........................................................................ 290 5-50 GMAC Receive Interface Timing, RGMIIn operation....................................................................... 291 5-51 GMAC Transmit Interface Timing RGMIIn operation....................................................................... 292 5-52 MLB_CLK Timing ............................................................................................................... 293 5-53 MMC/SD/SDIO in - Default Speed 3.3V Signaling - Receiver Mode .................................................... 295 5-54 MMC/SD/SDIO in - High Speed SDR12 - Transmiter Mode .............................................................. 296 5-55 MMC/SD/SDIO in - High Speed 3.3V Signaling - Receiver Mode ....................................................... 297 5-56 MMC/SD/SDIO in - High Speed 3.3V Signaling - Transmiter Mode ..................................................... 297 5-57 MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode ................................................................ 298 5-58 MMC/SD/SDIO in - High Speed SDR12 - Transmiter Mode .............................................................. 298 5-59 MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode ................................................................ 299 5-60 MMC/SD/SDIO in - High Speed SDR25 - Transmiter Mode .............................................................. 299 5-61 MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode ................................................................ 300 5-62 MMC/SD/SDIO in - High Speed SDR50 - Transmiter Mode .............................................................. 300 5-63 MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode............................................................... 301 5-64 MMC/SD/SDIO in - High Speed SDR104 - Transmiter Mode ............................................................ 301 5-65 SDMMC - High Speed SD - DDR - Data/Command Receive............................................................. 302 5-66 SDMMC - High Speed SD - DDR - Data/Command Transmit............................................................ 302 5-67 MMC/SD/SDIO in - Standard JC64 - Receiver Mode...................................................................... 304 5-68 MMC/SD/SDIO in - Standard JC64 - Transmiter Mode.................................................................... 304 5-69 MMC/SD/SDIO in - High Speed JC64 - Receiver Mode................................................................... 305 5-70 MMC/SD/SDIO in - High Speed JC64 - Transmiter Mode ................................................................ 306 5-71 eMMC in - HS200 SDR - Transmiter Mode ................................................................................. 306 5-72 eMMC in - HS200 - Receiver Mode .......................................................................................... 306 5-73 MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode ............................................................ 308 5-74 MMC/SD/SDIO in - High Speed DDR JC64 - Transmiter Mode.......................................................... 308 Copyright © 2012–2013, Texas Instruments Incorporated List of Figures 9 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 5-75 MMC/SD/SDIOj in - High Speed SDR12 - Receiver Mode................................................................ 309 5-76 MMC/SD/SDIOj in - High Speed SDR12 - Transmiter Mode ............................................................. 309 5-77 MMC/SD/SDIOj in - High Speed SDR25 - Receiver Mode................................................................ 311 5-78 MMC/SD/SDIOj in - High Speed SDR25 - Transmiter Mode ............................................................. 311 5-79 MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode................................................................ 312 5-80 MMC/SD/SDIOj in - High Speed SDR50 - Transmiter Mode ............................................................. 312 5-81 MMC/SD/SDIOj in - Default Speed 3.3V Signaling - Receiver Mode .................................................... 313 5-82 MMC/SD/SDIOj in - Default Speed 3.3V Signaling - Transmiter Mode.................................................. 313 5-83 MMC/SD/SDIOj in - High Speed 3.3V Signaling - Receiver Mode ....................................................... 315 5-84 MMC/SD/SDIOj in - High Speed 3.3V Signaling - Transmiter Mode..................................................... 315 5-85 MMC/SD/SDIOj in - SDR12 3.3V Signaling - Receiver Mode ............................................................ 316 5-86 MMC/SD/SDIOj in - SDR12 3.3V Signaling - Transmiter Mode .......................................................... 316 5-87 MMC/SD/SDIOj in - SDR25 3.3V Signaling - Receiver Mode ............................................................ 317 5-88 .MMC/SD/SDIOj in - SDR25 3.3V Signaling - Transmiter Mode ......................................................... 317 5-89 ATL_CLKOUTx Timing......................................................................................................... 319 5-90 JTAG Timing .................................................................................................................... 321 5-91 JTAG With RTCK Timing ...................................................................................................... 322 5-92 cJTAG Interface Timing—Normal Mode ..................................................................................... 323 5-93 TPIU—PLL DDR Transmit Mode ............................................................................................. 323 7-1 Printed Device Reference ..................................................................................................... 325 7-2 Mechanical Package ........................................................................................................... 327 8-1 Minimize Loop Inductance With Proper Layer Assignment ............................................................... 330 8-2 Layer PCB With High Density Interconnect (HDI) Vias .................................................................... 331 8-3 Layer PCB With Plated Through Holes (PTH) Vias ........................................................................ 331 8-4 Poor Via Assignment for PDN................................................................................................. 332 8-5 Improved Via Assignment for PDN ........................................................................................... 332 8-6 Via Starvation ................................................................................................................... 333 8-7 Improved Layout With More Transitional Vias .............................................................................. 333 8-8 Coplanar Shielding of Power Net Using Ground Guard-band ........................................................... 334 8-9 Depiction of Sheet Resistivity and Resistance.............................................................................. 334 8-10 Static IR Drop Budget for PCB Only ......................................................................................... 335 8-11 Pin-grouping concept: Lumped and Distributed Methodologies .......................................................... 336 8-12 Characteristics of a Real Capacitor With ESL and ESR................................................................... 337 8-13 Series Model Impedance Equation ........................................................................................... 337 8-14 Typical Impedance Profile of a Capacitor ................................................................................... 338 8-15 Capacitor Placement Geometry for Improved Mounting Inductance..................................................... 338 8-16 Placement Recommendation for an ESD External Protection............................................................ 339 8-17 Trace Examples................................................................................................................. 340 8-18 Field Lines of a Signal Above Ground ....................................................................................... 342 8-19 Guard Ring Routing ............................................................................................................ 342 8-20 PDN’s Target impedance ...................................................................................................... 343 8-21 vdd_mpu Simplified SCH Diagram ........................................................................................... 348 8-22 vdd_mpu routing [Top Layer].................................................................................................. 348 8-23 vdd_mpu routing [Internal Power Plane #2]................................................................................. 348 8-24 vdd_mpu routing and cap placements [Bottom Layer]..................................................................... 348 8-25 vdd_mpu Voltage/IR Drop [All Layers] ....................................................................................... 350 8-26 vdd_mpu Decoupling Cap Loop Inductances ............................................................................... 351 8-27 vdd_mpu Impedance vs Frequency .......................................................................................... 352 10 List of Figures Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 8-28 Ground Guard Illustration ...................................................................................................... 353 8-29 QSPI Interface High Level Schematic........................................................................................ 354 8-30 Suggested Array Capacitors and a Ferrite Bead to Minimize EMI ....................................................... 356 8-31 Four-Layer Board Stack-Up ................................................................................................... 357 8-32 USB Connector ................................................................................................................. 358 8-33 3W Spacing Rule ............................................................................................................... 359 8-34 Power Supply and Clock Connection to the USB PHY .................................................................... 359 8-35 USB PHY Connector and Cable Connector................................................................................. 360 8-36 Do Not Cross Plane Boundaries.............................................................................................. 361 8-37 Do Not Overlap Planes......................................................................................................... 361 8-38 Do Not Violate Image Planes ................................................................................................. 362 8-39 USB 3.0 Interface High Level Schematic .................................................................................... 365 8-40 HDMI Interface High Level Schematic ....................................................................................... 367 8-41 SATA Interface High Level Schematic ....................................................................................... 369 8-42 Slow Clock PCB Requirements ............................................................................................... 373 8-43 Grounding Scheme for Low-Frequency Clock .............................................................................. 373 8-44 Grounding Scheme for High-Frequency Clock ............................................................................. 374 8-45 DDR3 Memory Controller Clock Timing ..................................................................................... 375 8-46 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices....................................... 378 8-47 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices........................................ 378 8-48 Placement Specifications ...................................................................................................... 381 8-49 DDR3 Keepout Region......................................................................................................... 382 8-50 CK Topology for Four x8 DDR3 Devices .................................................................................... 385 8-51 ADDR_CTRL Topology for Four x8 DDR3 Devices........................................................................ 385 8-52 CK Routing for Four Single-Side DDR3 Devices ........................................................................... 386 8-53 ADDR_CTRL Routing for Four Single-Side DDR3 Devices............................................................... 386 8-54 CK Routing for Four Mirrored DDR3 Devices............................................................................... 387 8-55 ADDR_CTRL Routing for Four Mirrored DDR3 Devices .................................................................. 387 8-56 CK Topology for Two DDR3 Devices ........................................................................................ 388 8-57 ADDR_CTRL Topology for Two DDR3 Devices............................................................................ 388 8-58 CK Routing for Two Single-Side DDR3 Devices ........................................................................... 389 8-59 ADDR_CTRL Routing for Two Single-Side DDR3 Devices ............................................................... 389 8-60 CK Routing for Two Mirrored DDR3 Devices ............................................................................... 390 8-61 ADDR_CTRL Routing for Two Mirrored DDR3 Devices................................................................... 390 8-62 CK Topology for One DDR3 Device.......................................................................................... 391 8-63 ADDR_CTRL Topology for One DDR3 Device ............................................................................. 391 8-64 CK Routing for One DDR3 Device ........................................................................................... 392 8-65 ADDR_CTRL Routing for One DDR3 Device ............................................................................... 392 8-66 DQS Topology................................................................................................................... 393 8-67 DQ/DM Topology ............................................................................................................... 393 8-68 DQS Routing With Any Number of Allowed DDR3 Devices .............................................................. 394 8-69 DQ/DM Routing With Any Number of Allowed DDR3 Devices ........................................................... 394 8-70 CACLM for Four Address Loads on One Side of PCB .................................................................... 395 8-71 CACLM for Two Address Loads on One Side of PCB..................................................................... 396 8-72 DQLM for Any Number of Allowed DDR3 Devices......................................................................... 397 Copyright © 2012–2013, Texas Instruments Incorporated List of Figures 11 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com List of Tables 1-1 Device Comparison .............................................................................................................. 18 2-1 Unused balls specific connection requirements .............................................................................. 23 2-2 Ball Characteristics............................................................................................................... 27 2-3 Multiplexing Characteristics ..................................................................................................... 93 2-4 VIP Signal Descriptions ........................................................................................................ 109 2-5 DSS Signal Descriptions....................................................................................................... 114 2-6 HDMI Signal Descriptions ..................................................................................................... 116 2-7 DDR2/DDR3/DDR3L SDRAM Signal Descriptions......................................................................... 117 2-8 GPMC Signal Descriptions .................................................................................................... 120 2-9 Timers Signal Descriptions .................................................................................................... 123 2-10 I2C Signal Descriptions......................................................................................................... 123 2-11 HDQ / 1-Wire Signal Descriptions ............................................................................................ 124 2-12 UART Signal Descriptions ..................................................................................................... 124 2-13 SPI Signal Descriptions ........................................................................................................ 125 2-14 QSPI Signal Descriptions ...................................................................................................... 126 2-15 MCASP Signal Descriptions................................................................................................... 127 2-16 Universal Serial Bus Signal Descriptions .................................................................................... 129 2-17 SATA Signal Descriptions ..................................................................................................... 130 2-18 PCIe Signal Descriptions ...................................................................................................... 131 2-19 DCAN Signal Descriptions..................................................................................................... 131 2-20 GMAC Signal Descriptions .................................................................................................... 132 2-21 MLB Signal Descriptions....................................................................................................... 133 2-22 eMMC/SD/SDIO Signal Descriptions......................................................................................... 134 2-23 GPIOs Signal Descriptions .................................................................................................... 135 2-24 Keyboard Signal Descriptions................................................................................................. 141 2-25 PWM Signal Descriptions...................................................................................................... 141 2-26 ATL Signal Descriptions ....................................................................................................... 142 2-27 Debug Signal Descriptions .................................................................................................... 142 2-28 Sysboot Signal Descriptions................................................................................................... 143 2-29 PRCM Signal Descriptions .................................................................................................... 144 2-30 RTC Signal Descriptions....................................................................................................... 144 2-31 SDMA Signal Descriptions..................................................................................................... 145 2-32 INTC Signal Descriptions ...................................................................................................... 145 2-33 Observability Signal Descriptions............................................................................................. 145 2-34 Power Supply Signal Descriptions............................................................................................ 146 3-1 Absolute Maximum Rating Over Junction Temperature Range .......................................................... 150 3-2 Recommended Operating Conditions........................................................................................ 152 3-3 Power on Hour (POH) Limits .................................................................................................. 156 3-4 DRA75x / DRA74x Operating Points ......................................................................................... 156 3-5 MPU Voltage Domain ......................................................................................................... 157 3-6 MPU Clock AC Performances for DRA746/DRA756 devices............................................................. 157 3-7 MPU Clock AC Performances for DRA745 / DRA755 devices ........................................................... 157 3-8 MPU Clock AC Performances for DRA744 / DRA754 devices ........................................................... 157 3-9 DSPEVE Voltage Domain .................................................................................................... 157 3-10 DSPEVE Clocks AC Performances ......................................................................................... 158 3-11 IVA Voltage Domain ........................................................................................................... 158 3-12 IVA Clock AC Performances ................................................................................................. 158 12 List of Tables Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 3-13 GPU Voltage Domain .......................................................................................................... 159 3-14 GPU Clock AC Performances................................................................................................. 159 3-15 Device Core Voltage Domain ................................................................................................. 159 3-16 Core Clocks AC Performances for DRA746 / DRA756, DRA745 / DRA755 and DRA744 / DRA754 devices..... 160 3-17 RTC Voltage Domain........................................................................................................... 160 3-18 RTC Clock AC Performance .................................................................................................. 160 3-19 Maximum Supported Frequency.............................................................................................. 160 3-20 LVCMOS DDR DC Electrical Characteristics ............................................................................... 181 3-21 Dual Voltage LVCMOS I2C DC Electrical Characteristics ................................................................ 183 3-22 LVCMOS DC Electrical Characteristics...................................................................................... 186 3-23 Decoupling Capacitor Requirements......................................................................................... 188 4-1 Input Clock Requirements ..................................................................................................... 200 4-2 Crystal Electrical Characteristics ............................................................................................. 200 4-3 Oscillator Switching Characteristics—Crystal Mode ....................................................................... 201 4-4 OSC0 Input Clock Electrical Characteristics—Bypass Mode ............................................................. 202 4-5 OSC0 Input Clock Timing Requirements .................................................................................... 202 4-6 Crystal Electrical Characteristics ............................................................................................. 203 4-7 Oscillator Switching Characteristics—Crystal Mode ....................................................................... 203 4-8 OSC1 Input Clock Electrical Characteristics—Bypass Mode ............................................................. 204 4-9 OSC1 Input Clock Timing Requirements .................................................................................... 204 4-10 Crystal Electrical Characteristics ............................................................................................. 205 4-11 Oscillator Switching Characteristics—Crystal Mode ....................................................................... 206 4-12 RTC Oscillator Input Clock Electrical Characteristics—Bypass Mode ................................................... 206 4-13 clkout[3:1] Output Clock Electrical Characteristics ......................................................................... 207 4-14 DPLL Control Type ............................................................................................................. 208 4-15 DPLL Type A Characteristics ................................................................................................. 210 4-16 DPLL Type B Characteristics ................................................................................................. 211 4-17 DLL Characteristics............................................................................................................. 212 4-18 Internal 32-kHz Oscillator Characteristic..................................................................................... 212 5-1 Timing Parameters ............................................................................................................. 214 5-2 Timing Requirements for VIP ................................................................................................. 215 5-3 VIN2/3/4 IOSETs................................................................................................................ 216 5-4 Virtual Functions Mapping for VIP1-1a,1b,2a ............................................................................... 218 5-5 Virtual Functions Mapping for VIP1-2b ...................................................................................... 220 5-6 Virtual Functions Mapping for VIP2-3a,3b................................................................................... 221 5-7 Virtual Functions Mapping for VIP2-4a,4b................................................................................... 224 5-8 Virtual Functions Mapping for VIP3-5a,6a................................................................................... 228 5-9 DPI Video Output i (i = 1..3) Switching Characteristics .................................................................... 229 5-10 Virtual Functions Mapping for Video Output Port........................................................................... 230 5-11 GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 1 Load.................................... 234 5-12 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load ............................... 235 5-13 GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 5 Loads .................................. 235 5-14 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads.............................. 235 5-15 GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode ............................................. 243 5-16 GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode......................................... 244 5-17 GPMC/NAND Flash Interface Timing Requirements....................................................................... 250 5-18 GPMC/NAND Flash Interface Switching Characteristics .................................................................. 250 5-19 Virtual Functions Mapping for GPMC ........................................................................................ 254 Copyright © 2012–2013, Texas Instruments Incorporated List of Tables 13 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 5-20 Timing Requirements for I2C Input Timings ................................................................................ 257 5-21 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings ..................... 258 5-22 HDQ/1-Wire Timing Requirements—HDQ Mode ........................................................................... 259 5-23 HDQ / 1-Wire Switching Characteristics - HDQ Mode ..................................................................... 259 5-24 HDQ / 1-Wire Timing Requirements - 1-Wire Mode ....................................................................... 260 5-25 HDQ / 1-Wire Switching Characteristics - 1-Wire Mode ................................................................... 260 5-26 Timing Requirements for UART .............................................................................................. 261 5-27 Switching Characteristics Over Recommended Operating Conditions for UART ..................................... 261 5-28 Timing Requirements for SPI - Master Mode .............................................................................. 263 5-29 Timing Requirements for SPI - Slave Mode................................................................................. 265 5-30 SPI3/4 IOSETs .................................................................................................................. 267 5-31 Switching Characteristics for QSPI ........................................................................................... 268 5-32 Timing Requirements for QSPI ............................................................................................... 270 5-33 Virtual Functions Mapping for QSPI.......................................................................................... 272 5-34 Timing Requirements for McASP1 ........................................................................................... 273 5-35 Timing Requirements for McASP2 ........................................................................................... 273 5-36 Timing Requirements for McASP3/4/5/6/7/8 ............................................................................... 274 5-37 Switching Characteristics Over Recommended Operating Conditions for McASP1 ................................... 275 5-38 Switching Characteristics Over Recommended Operating Conditions for McASP2 .................................. 276 5-39 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8........................ 276 5-40 Virtual Functions Mapping for McASP1...................................................................................... 279 5-41 Virtual Functions Mapping for McASP2...................................................................................... 280 5-42 Virtual Functions Mapping for McASP3/4/5/6/7/8 .......................................................................... 281 5-43 Timing Requirements for ULPI SDR Slave Mode .......................................................................... 283 5-44 Switching Characteristics for ULPI SDR Slave Mode...................................................................... 284 5-45 Timing Requirements for DCANx Receive ................................................................................. 286 5-46 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit ........................ 286 5-47 Timing Requirements for miin_rxclk - MII Operation ...................................................................... 286 5-48 Timing Requirements for miin_txclk - MII Operation ...................................................................... 287 5-49 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s ........................................................... 287 5-50 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s .................................................................................................................................... 288 5-51 Timing Requirements for MDIO Input ........................................................................................ 288 5-52 Switching Characteristics Over Recommended Operating Conditions for MDIO Output ............................. 288 5-53 Timing Requirements for GMAC RMIIn Receive .......................................................................... 289 5-54 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s ........................................................................................................................... 290 5-55 Timing Requirements for rgmiin_rxc - RGMIIn Operation ................................................................ 290 5-56 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps ...................................... 291 5-57 Switching Characteristics Over Recommended Operating Conditions for transmit - RGMIIn operation for 10/100/1000 Mbit/s ............................................................................................................ 291 5-58 Switching Characteristics Over Recommended Operating Conditions for GMAC RGMIIn Transmit ............... 292 5-59 Timing Requirements for MLBCLK 3-Pin Option .......................................................................... 292 5-60 Timing Requirements for Receive Data for the MLB 3-Pin Option ....................................................... 293 5-61 Switching Characteristics Over Recommended Operating Conditions for MLB 3-Pin Option ........................ 293 5-62 Timing Requirements for MLBCLK 6-Pin Option .......................................................................... 293 5-63 Timing Requirements for Receive Data for the MLB 6-Pin Option ...................................................... 294 5-64 Switching Characteristics Over Recommended Operating Conditions for MLB 6-Pin Option ....................... 294 5-65 Timing Requirements for MMC1 - SD Card Default Speed Mode ....................................................... 294 14 List of Tables Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 5-66 5-67 5-68 5-69 5-70 5-71 5-72 5-73 5-74 5-75 5-76 5-77 5-78 5-79 5-80 5-81 5-82 5-83 5-84 5-85 5-86 5-87 5-88 5-89 5-90 5-91 5-92 5-93 5-94 5-95 5-96 5-97 5-98 5-99 5-100 5-101 5-102 5-103 5-104 5-105 5-106 5-107 5-108 5-109 7-1 8-1 8-2 8-3 Switching Characteristics for MMC1 - SD Card Default Speed Mode ................................................... 295 Timing Requirements for MMC1 - SD Card High Speed .................................................................. 296 Switching Characteristics for MMC1 - SD Card High Speed.............................................................. 296 Timing Requirements for MMC1 - SD Card SDR12 Mode ................................................................ 297 Switching Characteristics for MMC1 - SD Card SDR12 Mode ........................................................... 297 Timing Requirements for MMC1 - SD Card SDR25 Mode ................................................................ 298 Switching Characteristics for MMC1 - SD Card SDR25 Mode ........................................................... 298 Timing Requirements for MMC1 - SD Card SDR50 Mode ................................................................ 299 Switching Characteristics for MMC1 - SD Card SDR50 Mode ........................................................... 299 Switching Characteristics for MMC1 - SD Card SDR104 Mode .......................................................... 300 Timing Requirements for MMC1 - SD Card DDR50 Mode................................................................ 301 Switching Characteristics for MMC1 - SD Card DDR50 Mode ........................................................... 301 Virtual Functions Mapping for MMC1 ........................................................................................ 303 Timing Requirements for MMC2 - JC64 Standard SDR Mode ........................................................... 303 Switching Characteristics for MMC2 - JC64 Standard SDR Mode....................................................... 303 Timing Requirements for MMC2 - JC64 High Speed SDR Mode ........................................................ 304 Switching Characteristics for MMC2 - JC64 High Speed SDR Mode.................................................... 305 Switching Characteristics for MMC2 - JEDS84 HS200 Mode ............................................................ 306 Timing Requirements for MMC2 - JC64 High Speed DDR Mode ........................................................ 307 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode ................................................... 307 Timing Requirements for MMCj - SDIO Standard SDR12 Mode ......................................................... 308 Switching Characteristics for MMCj - SDIO Standard SDR12 Mode .................................................... 308 Timing Requirements for MMCj - SDIO High Speed SDR25 Mode...................................................... 310 Switching Characteristics for MMCj - SDIO High Speed SDR25 Mode ................................................. 310 Timing Requirements for MMCj - SDIO High Speed SDR50 Mode...................................................... 311 Switching Characteristics for MMCj - SDIO High Speed SDR50 Mode ................................................. 311 Timing Requirements for MMCj - SD Card Default Speed Mode ........................................................ 312 Switching Characteristics for MMCj - SD Card Default Speed Mode .................................................... 312 Timing Requirements for MMCj - SD Card High Speed Mode ........................................................... 313 Switching Characteristics for MMCj - SD Card High Speed Mode ....................................................... 314 Timing Requirements for MMCj - SD Card SDR12 Mode................................................................. 315 Switching Characteristics for MMCj - SD Card SDR12 Mode ............................................................ 315 Timing Requirements for MMCj - SD Card SDR25 Mode................................................................. 316 Switching Characteristics for MMCj - SD Card SDR25 Mode ............................................................ 316 MMC4 Slew mode reconfiguration ........................................................................................... 318 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx .......................... 319 Timing Requirements for Reset .............................................................................................. 320 Timing Requirements for IEEE 1149.1 JTAG .............................................................................. 320 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG ...................... 321 Timing Requirements for IEEE 1149.1 JTAG With RTCK ................................................................ 321 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK .............................................................................................. 321 Timing Requirements for IEEE 1149.7 cJTAG.............................................................................. 322 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.7 cJTAG ..................... 322 Switching Characteristics for TPIU ........................................................................................... 323 Nomenclature Description ..................................................................................................... 325 Commercial Applications Recommended Decoupling Capacitors Characteristics..................................... 343 Automotive Applications Recommended Decoupling Capacitors Characteristics ..................................... 344 Recommended PDN and Decoupling Characteristics .................................................................... 344 Copyright © 2012–2013, Texas Instruments Incorporated List of Tables 15 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 8-4 Power Supply Connections.................................................................................................... 345 8-5 Input Voltage Power Supplies for the DPLLs ............................................................................... 346 8-6 Example PCB vdd_mpu PI Analysis Summary ............................................................................. 347 8-7 PCB Etch Resistance Breakdown - From PMIC Source to Device Load ............................................... 348 8-8 PCB Etch Resistance Breakdown - From Power Inductor to Device Load ............................................. 349 8-9 PDN Effective Resistance - From PMIC Source to Device Load......................................................... 349 8-10 Rail - vdd_mpu .................................................................................................................. 350 8-11 USB1 Component Reference ................................................................................................. 365 8-12 USB1 Routing Specifications.................................................................................................. 366 8-13 HDMI Component Reference ................................................................................................. 367 8-14 TMDS Routing Specifications ................................................................................................. 368 8-15 HDMI PCB Stackup Specifications ........................................................................................... 368 8-16 SATA AC Coupling Capacitors Requirements .............................................................................. 369 8-17 SATA AC Coupling Capacitors Requirements .............................................................................. 369 8-18 SATA AC Coupling Capacitors Requirements .............................................................................. 369 8-19 SATA Routing Specifications.................................................................................................. 370 8-20 PCIe AC Coupling Capacitors Requirements ............................................................................... 371 8-21 PCIe AC Coupling Capacitors Requirements ............................................................................... 371 8-22 PCI-E Routing Specifications.................................................................................................. 372 8-23 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller ............... 374 8-24 Supported DDR3 Device Combinations ..................................................................................... 375 8-25 Compatible JEDEC DDR3 Devices (Per Interface) ........................................................................ 379 8-26 Six-Layer PCB Stackup Suggestion.......................................................................................... 379 8-27 PCB Stackup Specifications................................................................................................... 380 8-28 Placement Specifications ...................................................................................................... 381 8-29 Bulk Bypass Capacitors........................................................................................................ 383 8-30 High-Speed Bypass Capacitors............................................................................................... 383 8-31 Clock Net Class Definitions.................................................................................................... 384 8-32 Signal Net Class Definitions................................................................................................... 384 8-33 CK and ADDR_CTRL Routing Specification ................................................................................ 396 8-34 Data Routing Specification .................................................................................................... 397 ADVANCE INFORMATION 16 List of Tables Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com 1 Introduction SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Infotainment Applications Processor Silicon Revision 1.0 NOTE TO USERS: NOTE The content of this book is EARLY PRELIMINARY INFORMATION before silicon and is likely to be modified before release of the preliminary version of the Data Manual (DM). This Data Manual describes the electrical and mechanical specifications of the Device. It consists of the following sections: • A description of the device terminals: ball assignments, electrical characteristics, multiplexing modes, and signal descriptions (Section 2, Terminal Description) • A description of the required electrical characteristics: absolute maximum ratings, operating conditions, DC characteristics, voltage decoupling capacities, and device power-up and power-down sequences (Section 3, Electrical Characteristics) • The clock characteristics of the input and output clocks, PLL and DLL specifications (Section 4, Clock Specifications) • The timing requirements and switching characteristics (AC timings) of the interfaces (Section 5, Timing Requirements and Switching Characteristics) • The thermal management recommendations including the thermal resistance characteristics (Section 6, Thermal Management) • A description of the device nomenclature, and mechanical data (Section 7, Package Characteristics) • The Device PCB guidelines (Section 8, PCB Guidelines) 1 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 2012–2013, Texas Instruments Incorporated DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 1.1 Device Comparison Table 1-1 shows a comparison between devices, highlighting the differences. Table 1-1. Device Comparison Features Processors/ Accelerators ARM® Dual Cortex™-A15 Microprocessor Subsystem (MPU) C66x™ VLIW DSP BitBLT 2D Hardware Acceleration Engine (BB2D) Display Subsystem Embedded Vision Engine (EVE) ARM Dual Cortex-M4 Image Processing Unit (IPU) Image Video Accelarator (IVA) SGX544 Dual-Core 3D Graphics Processing Unit (GPU) VIP1 Video Input Port (VIP) VIP2 VIP3 Video Processing Engine (VPE) Program/Data Storage On-Chip Shared Memory (RAM) General-Purpose Memory Controller (GPMC) DDR2/DDR3 Memory Controller Dynamic Memory Manager (DMM) Radio Support Audio Tracking Logic (ATL) Viterbi Coprocessor (VCP) Peripherals MPU core 0 MPU core 1 DSP1 DSP2 VOUT1 VOUT2 VOUT3 HDMI EVE1 EVE2 IPU1 IPU2 vin1a vin1b vin2a vin2b vin3a vin3b vin4a vin4b vin5a vin6a OCMC_RAM1 OCMC_RAM2 OCMC_RAM3 EMIF1 EMIF2 VCP1 VCP2 DRA754 DRA75x DRA755 Device DRA756 DRA744 DRA74x DRA745 DRA746 1.0 GHz 1.0 GHz 1176 MHz 1176 MHz 700 MHz 700 MHz 1.5 GHz 1.5 GHz Yes Yes Yes Yes Yes 625 MHz 625 MHz 212.8 MHz 212.8 MHz 532 MHz 532 MHz Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1.0 GHz 1.0 GHz 1176 MHz 1176 MHz 700 MHz No 1.5 GHz 1.5 GHz Yes Yes Yes Yes Yes No No 212.8 MHz 212.8MHz 532 MHz 532 MHz No No Yes Yes Yes Yes Yes Yes No No Yes 512 KB 1MB 1MB Yes up to 2GB (optional with SECDED) up to 2GB Yes 512 KB No No Yes up to 2GB up to 2GB Yes Yes Yes Yes Yes Yes Yes 18 Introduction Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 1-1. Device Comparison (continued) Features Dual Controller Area Network Interface (DCAN) Enhanced DMA (EDMA) System DMA (DMA_SYSTEM) Ethernet Subsystem (Ethernet SS) General-Purpose IO (GPIO) Inter-Integrated Circuit Interface (I2C) System Mailbox Module Media Local Bus Subsystem (MLBSS) Multi-Channel Audio Serial Port (McASP) MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO) PCI Express 2.0 Port with Integrated PHY SATA Real-Time Clock Subsystem (RTCSS) Multichannel Serial Peripheral Interface (McSPI) HDQ1W Quad SPI (QSPI) Spinlock Module Keyboard Controller (KBD) Timers, General-Purpose Timer, Watchdog Pulse-Width Modulation Subsystem (PWMSS) Universal Asynchronous Receiver/Transmitter (UART) Universal Serial Bus (USB3.0) DCAN1 DCAN2 GMAC_SW[0] GMAC_SW[1] McASP1 McASP2 McASP3 McASP4 McASP5 McASP6 McASP7 McASP8 MMC1 MMC2 MMC3 MMC4 PCIe_SS1 PCIe_SS2 PWMSS1 PWMSS2 PWMSS3 USB1 (SuperSpeed, Dual-Role-Device [DRD]) Device DRA75x DRA74x DRA754 DRA755 DRA756 DRA744 DRA745 DRA746 Yes Yes Yes Yes Yes Yes Yes Yes MII, RMII, or RGMII MII, RMII, or RGMII MII, RMII, or RGMII MII, RMII, or RGMII Up to 252 Up to 252 5 5 13 13 Yes Yes 16 serializers 16 serializers 16 serializers 16 serializers 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers 1x UHSI 4b 1x UHSI 4b 1x eMMC v 4.5 8b 1x eMMC v 4.5 8b 1x SDIO 8b 1x SDIO 8b 1x SDIO 4b 1x SDIO 4b Yes Yes (Single-lane mode) Yes No Yes Yes Yes Yes 4 4 Yes Yes Yes Yes Yes Yes Yes Yes 16 16 Yes Yes Yes Yes Yes Yes Yes Yes 10 10 Yes Yes Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Introduction 19 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 1-1. Device Comparison (continued) Features DRA75x Device DRA74x DRA754 DRA755 DRA756 DRA744 DRA745 DRA746 USB2 (HighSpeed, Dual-Role-Device [DRD], with Yes Yes embedded HS PHY) Universal Serial Bus (USB2.0) USB3 (HighSpeed, OTG2.0, with Yes Yes ULPI) USB4 (HighSpeed, OTG2.0, with Yes ULPI) Yes(1) (1) USB4 will not be supported on some pin-compatible roadmap devices. USB3 will be mapped to these balls instead. Pin compatibility can be maintained in the future by either not using USB4, or via software change to use USB4 on this device, but USB3 on these balls in the future. 1.2 Device Support Nomenclature This device is currently in development. Experimental / Prototype devices are shipped against the following disclaimer: “This product is still in development and is intended for internal evaluation purposes.” Notwithstanding any provision to the contrary, for experimental/prototype devices, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability. 1.3 About This Manual FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Information About Cautions and Warnings This book may contain cautions and warnings. CAUTION This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. WARNING This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. 20 Introduction Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. 1.4 Trademarks TMS320DMC64x, C64x, ICECrusher, ICEPick and SmartReflex are trademarks of Texas Instruments Incorporated. PicoDLP is a registered trademark of Texas Instruments Incorporated. ARM, Jazelle, and Thumb are registered trademarks of ARM Limited. ETM, ETB, ARM9, CoreSight, ISA, Cortex, and Neon are trademarks of ARM Limited. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is licensed to Texas Instruments. HDQ is a trademark of Benchmarq. 1-Wire is a registered trademark of Dallas Semiconductor. Windows, WinMobile, and Direct3D are trademarks of Microsoft Corporation in the United States and other countries. USSE and POWERVR are trademarks or registered trademarks of Imagination Technologies Ltd. Mentor Graphics is a registered trademark of Mentor Graphics Corporation or its affiliated companies in the United States and other countries. OpenGL is a trademark of Silicon Graphics, Inc. OpenVG and OpenMAX are trademarks of Khronous Group, Inc. Arteris is a trademark of Arteris, Inc. RealVideo is a registered trademark of RealNetworks, Inc. SD is a registered trademark of Toshiba Corporation. eSD is a trademark of SD Association. MMC and eMMC are trademarks of MultiMediaCard Association. SonicsMX, Sonics3220 are trademarks or registered trademarks of Sonics, Inc. JTAG is a registered trademark of JTAG Technologies, Inc. Linux is a registered trademark of Linus Torvalds. On2 is a registered trademark of On2 Technologies. Symbian and all Symbian-based trademarks and logos are trademarks of Symbian Software Limited. Synopsys is a registered trademark of Synopsys, Inc. MIPI is registered trademarks of the Mobile Industry Processor Interface (MIPI) Alliance. Flex-OneNAND and OneNAND are trademarks of SAMSUNG Electronics, Corporation. Palm OS is a registered trademark of Palm Inc. PCI Express is a registered trademark of PCI-SIG. MediaLB is a trademark of Standard Microsystems Corporation. All other trademarks are the property of their respective owners. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Introduction 21 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 1.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. EARLY PRELIMINARY ADVANCE INFORMATION 22 Introduction Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com 2 Terminal Description SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 2.1 Terminal Assignment Figure 2-1 shows the ball locations for the 760 plastic ball grid array (PBGA) package and are used in conjunction with Table 2-2 through Table 2-34 to locate signal names and ball grid numbers. EARLY PRELIMINARY ADVANCE INFORMATION Figure 2-1. ABC S-PBGA-N760 Package (Bottom View) NOTE The following bottom balls are not connected: AF7 / AF10 / AF13 / AF16 / AF19 / AE4 / AE25 / AB26 / W3 / W26 / T3 / T26 / N3 / N26 / K3 / K26 / G3 / D4 / D25 / C10 / C13 / C16 / C19 / C22. These balls do not exist on the package. 2.1.1 Unused balls connection requirements This section describes the Unused/Reserved balls connection requirements. NOTE The following balls are reserved: A27 / K14 / Y5 / Y10 / B28 These balls must be left unconnected. NOTE All unused power supply balls must be supplied with the voltages specified in the Section 3.2, Recommended Operating Conditions, unless alternative tie-off options are included in Section 2.4, Signal Descriptions. Table 2-1. Unused balls specific connection requirements Balls AE15 / AC15 / AE14 / D20 / AD17 / AC17 / AC16 / AB16 E20 / D21 / E23 / C20 / C21 / AF14 Connection Requirements These balls must be connected to GND through an external pull resistor if unused These balls must be connect to the corresponding power supply through an external pull resistor if unused Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 23 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 2-1. Unused balls specific connection requirements (continued) Balls AB17 Connection Requirements These balls must be connected to F22 (porz) if unused NOTE All other unused signal balls with a Pad Configuration Register can be left unconnected with their internal pull-up or pull-down resistor enabled. EARLY PRELIMINARY ADVANCE INFORMATION NOTE All other unused signal balls without Pad Configuration Register can be left unconnected. 2.2 Ball Characteristics Table 2-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list describes the table column headers: 1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom. 2. BALL NAME: Mechanical name from package device (name is taken from muxmode 1). 3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 1). NOTE Table 2-2 does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 2.4, Signal Descriptions. NOTE In the Driver off mode, the buffer is configured in high-impedance. 4. 74x: This column shows if the functionality is applicable for DRA74x devices. Note that the ball characteristics table presents the functionality of DRA75x device. An empty box means "Yes". 5. MUXMODE: Multiplexing mode number: (a) MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily the default muxmode. NOTE The default mode is the mode at the release of the reset; also see the RESET REL. MUXMODE column. (b) MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used. 6. TYPE: Signal type and direction: – I = Input – O = Output – IO = Input or Output – D = Open drain – DS = Differential Signaling – A = Analog – PWR = Power 24 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 – GND = Ground – CAP = LDO Capacitor 7. BALL RESET STATE: The state of the terminal at power-on reset: – drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated). – drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated). – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor 8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal). – drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated). – drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated). – drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated). – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor NOTE For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see the Power Reset and Clock Management / PRCM Reset Management Functional Description section of the Device TRM. 9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal). 10. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply). 11. POWER: The voltage supply that powers the terminal IO buffers. 12. HYS: Indicates if the input buffer is with hysteresis: – Yes: With hysteresis – No: Without hysteresis An empty box means "Yes". NOTE For more information, see the hysteresis values in Section 3.4, DC Electrical Characteristics. 13. BUFFER TYPE: Drive strength of the associated output buffer. NOTE For programmable buffer strength: – The default value is given in Table 2-2. – A note describes all possible values according to the selected muxmode. 14. PULL UP / DOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. 15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers. – 0: Logic 0 driven on the peripheral's input signal port. – 1: Logic 1 driven on the peripheral's input signal port. – blank: Not Applicable. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 25 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com NOTE Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. (Hi Z mode is not an input signal.) NOTE When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided. CAUTION Peripherals exposed in Ball Characteristics Table and Multiplexing Characteristics Table represent functionality of a DRA75x device. Not all exposed peripherals are supported on DRA7xx devices. For peripherals supported on DRA7xx family of products please refer toTable 1-1, Device Comparison Table. NOTE Some of the DDR1 and DDR2 signals have an additional state change at the release of porz. The state that the signals change to at the release of porz is as follows: drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_ba[2:0], ddr1_a[15:0], ddr2_csn0, ddr2_ck, ddr2_nck, ddr2_casn, ddr2_rasn, ddr2_wen, ddr2_ba[2:0], ddr2_a[15:0]. OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0], ddr2_dqm[3:0], ddr2_dqs[3:0], ddr2_dqsn[3:0], ddr2_d[31:0]. ADVANCE INFORMATION 26 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com BALL NUMBER [1] BALL NAME [2] K9 cap_vbbldo_dspeve Y14 cap_vbbldo_gpu R20 cap_vbbldo_iva J16 cap_vbbldo_mpu L9 cap_vddram_core1 J19 cap_vddram_core2 Y15 cap_vddram_core3 P19 cap_vddram_core4 Y16 cap_vddram_core5 J10 cap_vddram_dspeve1 J9 cap_vddram_dspeve2 Y13 cap_vddram_gpu T20 cap_vddram_iva K16 cap_vddram_mpu1 K19 cap_vddram_mpu2 G19 dcan1_rx G20 dcan1_tx AD20 AC19 AD21 AD22 AC21 ddr1_a0 ddr1_a1 ddr1_a10 ddr1_a11 ddr1_a12 SIGNAL NAME [3] cap_vbbldo_dspeve cap_vbbldo_gpu cap_vbbldo_iva cap_vbbldo_mpu cap_vddram_core1 cap_vddram_core2 cap_vddram_core3 cap_vddram_core4 cap_vddram_core5 cap_vddram_dspeve1 cap_vddram_dspeve2 cap_vddram_gpu cap_vddram_iva cap_vddram_mpu1 cap_vddram_mpu2 dcan1_rx uart8_txd mmc2_sdwp sata1_led hdmi1_cec gpio1_15 Driver off dcan1_tx uart8_rxd mmc2_sdcd hdmi1_hpd gpio1_14 Driver off ddr1_a0 ddr1_a1 ddr1_a10 ddr1_a11 ddr1_a12 Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x Table 2-2. Ball Characteristics(1) SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 2 O Voltage LVCMOS 3 I 0 4 O 6 IO 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 2 I Voltage LVCMOS 1 3 I 1 6 I 14 IO 15 I 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR Submit Documentation Feedback Terminal Description 27 DRA75x, DRA74x TI Confidential — NDA Restrictions ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY BALL NUMBER [1] BALL NAME [2] AF18 AE17 AD18 AC20 AB19 AF21 AH22 AG23 AE21 AF22 AE22 AF17 AE18 AB18 AC18 AG24 AG22 AH23 AF25 AF26 AG27 AF28 AE26 ddr1_a13 ddr1_a14 ddr1_a15 ddr1_a2 ddr1_a3 ddr1_a4 ddr1_a5 ddr1_a6 ddr1_a7 ddr1_a8 ddr1_a9 ddr1_ba0 ddr1_ba1 ddr1_ba2 ddr1_casn ddr1_ck ddr1_cke ddr1_csn0 ddr1_d0 ddr1_d1 ddr1_d10 ddr1_d11 ddr1_d12 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] ddr1_a13 ddr1_a14 ddr1_a15 ddr1_a2 ddr1_a3 ddr1_a4 ddr1_a5 ddr1_a6 ddr1_a7 ddr1_a8 ddr1_a9 ddr1_ba0 ddr1_ba1 ddr1_ba2 ddr1_casn ddr1_ck ddr1_cke ddr1_csn0 ddr1_d0 ddr1_d1 ddr1_d10 ddr1_d11 ddr1_d12 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive clk (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 28 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 BALL NUMBER [1] BALL NAME [2] AC25 AC24 AD25 V20 W20 AB28 AC28 AG26 AC27 Y19 AB27 Y20 AA23 Y22 Y23 AA24 Y24 AA26 AH26 AA25 AA28 AF24 AE24 ddr1_d13 ddr1_d14 ddr1_d15 ddr1_d16 ddr1_d17 ddr1_d18 ddr1_d19 ddr1_d2 ddr1_d20 ddr1_d21 ddr1_d22 ddr1_d23 ddr1_d24 ddr1_d25 ddr1_d26 ddr1_d27 ddr1_d28 ddr1_d29 ddr1_d3 ddr1_d30 ddr1_d31 ddr1_d4 ddr1_d5 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] ddr1_d13 ddr1_d14 ddr1_d15 ddr1_d16 ddr1_d17 ddr1_d18 ddr1_d19 ddr1_d2 ddr1_d20 ddr1_d21 ddr1_d22 ddr1_d23 ddr1_d24 ddr1_d25 ddr1_d26 ddr1_d27 ddr1_d28 ddr1_d29 ddr1_d3 ddr1_d30 ddr1_d31 ddr1_d4 ddr1_d5 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 29 DRA75x, DRA74x TI Confidential — NDA Restrictions ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY BALL NUMBER [1] BALL NAME [2] AF23 AE23 AC23 AF27 AD23 AB23 AC26 AA27 V26 AH25 AE27 AD27 Y28 AG25 AE28 AD28 Y27 V28 V27 W22 V23 W19 W23 ddr1_d6 ddr1_d7 ddr1_d8 ddr1_d9 ddr1_dqm0 ddr1_dqm1 ddr1_dqm2 ddr1_dqm3 ddr1_dqm_ecc ddr1_dqs0 ddr1_dqs1 ddr1_dqs2 ddr1_dqs3 ddr1_dqsn0 ddr1_dqsn1 ddr1_dqsn2 ddr1_dqsn3 ddr1_dqsn_ecc ddr1_dqs_ecc ddr1_ecc_d0 ddr1_ecc_d1 ddr1_ecc_d2 ddr1_ecc_d3 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] ddr1_d6 ddr1_d7 ddr1_d8 ddr1_d9 ddr1_dqm0 ddr1_dqm1 ddr1_dqm2 ddr1_dqm3 ddr1_dqm_ecc ddr1_dqs0 ddr1_dqs1 ddr1_dqs2 ddr1_dqs3 ddr1_dqsn0 ddr1_dqsn1 ddr1_dqsn2 ddr1_dqsn3 ddr1_dqsn_ecc ddr1_dqs_ecc ddr1_ecc_d0 ddr1_ecc_d1 ddr1_ecc_d2 ddr1_ecc_d3 74x [4] No No No No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 30 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 BALL NUMBER [1] BALL NAME [2] Y25 V24 V25 Y26 AH24 AE20 AF20 AG21 Y18 AH21 R25 R26 N23 P26 N28 T22 R22 U22 R28 R27 P23 P22 P25 ddr1_ecc_d4 ddr1_ecc_d5 ddr1_ecc_d6 ddr1_ecc_d7 ddr1_nck ddr1_odt0 ddr1_rasn ddr1_rst ddr1_vref0 ddr1_wen ddr2_a0 ddr2_a1 ddr2_a10 ddr2_a11 ddr2_a12 ddr2_a13 ddr2_a14 ddr2_a15 ddr2_a2 ddr2_a3 ddr2_a4 ddr2_a5 ddr2_a6 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] ddr1_ecc_d4 ddr1_ecc_d5 ddr1_ecc_d6 ddr1_ecc_d7 ddr1_nck ddr1_odt0 ddr1_rasn ddr1_rst ddr1_vref0 ddr1_wen ddr2_a0 ddr2_a1 ddr2_a10 ddr2_a11 ddr2_a12 ddr2_a13 ddr2_a14 ddr2_a15 ddr2_a2 ddr2_a3 ddr2_a4 ddr2_a5 ddr2_a6 74x [4] No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive clk (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 power OFF OFF 1.35/1.5/1.8 vdds_ddr1 No LVCMOS NA DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 31 DRA75x, DRA74x TI Confidential — NDA Restrictions ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY BALL NUMBER [1] BALL NAME [2] N20 ddr2_a7 P27 ddr2_a8 N27 ddr2_a9 U23 ddr2_ba0 U27 ddr2_ba1 U26 ddr2_ba2 U28 ddr2_casn T28 ddr2_ck U24 ddr2_cke P24 ddr2_csn0 E26 ddr2_d0 G25 ddr2_d1 H24 ddr2_d10 H26 ddr2_d11 G26 ddr2_d12 J25 ddr2_d13 J26 ddr2_d14 J24 ddr2_d15 L22 ddr2_d16 K20 ddr2_d17 K21 ddr2_d18 L23 ddr2_d19 F25 ddr2_d2 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] ddr2_a7 ddr2_a8 ddr2_a9 ddr2_ba0 ddr2_ba1 ddr2_ba2 ddr2_casn ddr2_ck ddr2_cke ddr2_csn0 ddr2_d0 ddr2_d1 ddr2_d10 ddr2_d11 ddr2_d12 ddr2_d13 ddr2_d14 ddr2_d15 ddr2_d16 ddr2_d17 ddr2_d18 ddr2_d19 ddr2_d2 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive clk (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 32 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 BALL NUMBER [1] BALL NAME [2] L24 ddr2_d20 J23 ddr2_d21 K22 ddr2_d22 J20 ddr2_d23 L27 ddr2_d24 L26 ddr2_d25 L25 ddr2_d26 L28 ddr2_d27 M23 ddr2_d28 M24 ddr2_d29 F24 ddr2_d3 M25 ddr2_d30 M26 ddr2_d31 F26 ddr2_d4 F27 ddr2_d5 E27 ddr2_d6 E28 ddr2_d7 H23 ddr2_d8 H25 ddr2_d9 F28 ddr2_dqm0 G24 ddr2_dqm1 K23 ddr2_dqm2 M22 ddr2_dqm3 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] ddr2_d20 ddr2_d21 ddr2_d22 ddr2_d23 ddr2_d24 ddr2_d25 ddr2_d26 ddr2_d27 ddr2_d28 ddr2_d29 ddr2_d3 ddr2_d30 ddr2_d31 ddr2_d4 ddr2_d5 ddr2_d6 ddr2_d7 ddr2_d8 ddr2_d9 ddr2_dqm0 ddr2_dqm1 ddr2_dqm2 ddr2_dqm3 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 33 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] G28 ddr2_dqs0 H27 ddr2_dqs1 K27 ddr2_dqs2 M28 ddr2_dqs3 G27 ddr2_dqsn0 H28 ddr2_dqsn1 K28 ddr2_dqsn2 M27 ddr2_dqsn3 T27 ddr2_nck R23 ddr2_odt0 T23 ddr2_rasn R24 ddr2_rst N22 ddr2_vref0 U25 ddr2_wen G21 emu0 D24 emu1 AC5 gpio6_10 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] ddr2_dqs0 ddr2_dqs1 ddr2_dqs2 ddr2_dqs3 ddr2_dqsn0 ddr2_dqsn1 ddr2_dqsn2 ddr2_dqsn3 ddr2_nck ddr2_odt0 ddr2_rasn ddr2_rst ddr2_vref0 ddr2_wen emu0 gpio8_30 emu1 gpio8_31 gpio6_10 mdio_mclk i2c3_sda usb3_ulpi_d7 vin2b_hsync1 vin5a_clk0 ehrpwm2A gpio6_10 Driver off 74x [4] No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS Pux/PDy DDR 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS Pux/PDy DDR 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS Pux/PDy DDR 0 O PD drive clk (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 power OFF OFF 1.35/1.5/1.8 vdds_ddr2 No LVCMOS NA DDR 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 0 IO PU PU 0 14 IO 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0 IO PU PU 0 14 IO 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 O Voltage LVCMOS 1 2 IO 1 3 IO 0 4 I 9 I 0 10 O 14 IO 15 I 34 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] AB4 gpio6_11 E21 gpio6_14 F20 gpio6_15 F21 gpio6_16 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpio6_11 mdio_d i2c3_scl usb3_ulpi_d6 vin2b_vsync1 vin5a_de0 ehrpwm2B gpio6_11 Driver off gpio6_14 mcasp1_axr8 dcan2_tx uart10_rxd vout2_hsync vin4a_hsync0 i2c3_sda timer1 gpio6_14 Driver off gpio6_15 mcasp1_axr9 dcan2_rx uart10_txd vout2_vsync vin4a_vsync0 i2c3_scl timer2 gpio6_15 Driver off gpio6_16 mcasp1_axr10 vout2_fld vin4a_fld0 clkout1 timer3 gpio6_16 Driver off 74x [4] No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 IO 1 3 IO 0 4 I 9 I 0 10 O 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 IO Voltage LVCMOS 0 2 IO 1 3 I 1 6 O 8 I 0 9 IO 1 10 IO 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 IO Voltage LVCMOS 0 2 IO 1 3 O 6 O 8 I 0 9 IO 1 10 IO 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 IO Voltage LVCMOS 0 6 O 8 I 0 9 O 10 IO 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 35 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] R6 gpmc_a0 T9 gpmc_a1 N9 gpmc_a10 P9 gpmc_a11 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_a0 vin3a_d16 vout3_d16 vin4a_d0 vin4b_d0 i2c4_scl uart5_rxd gpio7_3 Driver off gpmc_a1 vin3a_d17 vout3_d17 vin4a_d1 vin4b_d1 i2c4_sda uart5_txd gpio7_4 Driver off gpmc_a10 vin3a_de0 vout3_de vin4b_clk1 timer10 spi4_d0 gpio2_0 Driver off gpmc_a11 vin3a_fld0 vout3_fld vin4a_fld0 vin4b_de1 timer9 spi4_cs0 gpio2_1 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 4 I 0 6 I 0 7 IO 1 8 I 1 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 4 I 0 6 I 0 7 IO 1 8 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 6 I 0 7 IO 8 IO 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 4 I 0 6 I 0 7 IO 8 IO 1 14 IO 15 I 36 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] P4 gpmc_a12 R3 gpmc_a13 T2 gpmc_a14 U2 gpmc_a15 U1 gpmc_a16 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_a12 vin4a_clk0 gpmc_a0 vin4b_fld1 timer8 spi4_cs1 dma_evt1 gpio2_2 Driver off gpmc_a13 qspi1_rtclk vin4a_hsync0 timer7 spi4_cs2 dma_evt2 gpio2_3 Driver off gpmc_a14 qspi1_d3 vin4a_vsync0 timer6 spi4_cs3 gpio2_4 Driver off gpmc_a15 qspi1_d2 vin4a_d8 timer5 gpio2_5 Driver off gpmc_a16 qspi1_d0 vin4a_d9 gpio2_6 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 4 I Voltage LVCMOS 0 5 1 6 I 0 7 IO 8 IO 1 9 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 I Voltage LVCMOS 0 4 I 0 7 IO 8 IO 1 9 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 I Voltage LVCMOS 0 4 I 0 7 IO 8 IO 1 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 I Voltage LVCMOS 0 4 I 0 7 IO 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 IO Voltage LVCMOS 0 4 I 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 37 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] P3 gpmc_a17 R2 gpmc_a18 K7 gpmc_a19 T6 gpmc_a2 M7 gpmc_a20 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_a17 qspi1_d1 vin4a_d10 gpio2_7 Driver off gpmc_a18 qspi1_sclk vin4a_d11 gpio2_8 Driver off gpmc_a19 mmc2_dat4 gpmc_a13 vin4a_d12 vin3b_d0 gpio2_9 Driver off gpmc_a2 vin3a_d18 vout3_d18 vin4a_d2 vin4b_d2 uart7_rxd uart5_ctsn gpio7_5 Driver off gpmc_a20 mmc2_dat5 gpmc_a14 vin4a_d13 vin3b_d1 gpio2_10 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 I Voltage LVCMOS 0 4 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 O Voltage LVCMOS 4 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 4 I 0 6 I 0 7 I 1 8 I 1 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I 38 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] J5 gpmc_a21 K6 gpmc_a22 J7 gpmc_a23 J4 gpmc_a24 J6 gpmc_a25 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_a21 mmc2_dat6 gpmc_a15 vin4a_d14 vin3b_d2 gpio2_11 Driver off gpmc_a22 mmc2_dat7 gpmc_a16 vin4a_d15 vin3b_d3 gpio2_12 Driver off gpmc_a23 mmc2_clk gpmc_a17 vin4a_fld0 vin3b_d4 gpio2_13 Driver off gpmc_a24 mmc2_dat0 gpmc_a18 vin4a_d8 vin3b_d5 gpio2_14 Driver off gpmc_a25 mmc2_dat1 gpmc_a19 vin4a_d9 vin3b_d6 gpio2_15 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 39 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] H4 gpmc_a26 H5 gpmc_a27 T7 gpmc_a3 P6 gpmc_a4 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_a26 mmc2_dat2 gpmc_a20 vin4a_d10 vin3b_d7 gpio2_16 Driver off gpmc_a27 mmc2_dat3 gpmc_a21 vin4a_d11 vin3b_hsync1 gpio2_17 Driver off gpmc_a3 qspi1_cs2 vin3a_d19 vout3_d19 vin4a_d3 vin4b_d3 uart7_txd uart5_rtsn gpio7_6 Driver off gpmc_a4 qspi1_cs3 vin3a_d20 vout3_d20 vin4a_d4 vin4b_d4 i2c5_scl uart6_rxd gpio1_26 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 O Voltage LVCMOS 1 2 I 0 3 O 4 I 0 6 I 0 7 O 8 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 O Voltage LVCMOS 1 2 I 0 3 O 4 I 0 6 I 0 7 IO 1 8 I 1 14 IO 15 I 40 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] R9 gpmc_a5 R5 gpmc_a6 P5 gpmc_a7 N7 gpmc_a8 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_a5 vin3a_d21 vout3_d21 vin4a_d5 vin4b_d5 i2c5_sda uart6_txd gpio1_27 Driver off gpmc_a6 vin3a_d22 vout3_d22 vin4a_d6 vin4b_d6 uart8_rxd uart6_ctsn gpio1_28 Driver off gpmc_a7 vin3a_d23 vout3_d23 vin4a_d7 vin4b_d7 uart8_txd uart6_rtsn gpio1_29 Driver off gpmc_a8 vin3a_hsync0 vout3_hsync vin4b_hsync1 timer12 spi4_sclk gpio1_30 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 4 I 0 6 I 0 7 IO 1 8 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 4 I 0 6 I 0 7 I 1 8 I 1 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 4 I 0 6 I 0 7 O 8 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 6 I 0 7 IO 8 IO 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 41 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] R4 gpmc_a9 M6 gpmc_ad0 M2 gpmc_ad1 J1 gpmc_ad10 J2 gpmc_ad11 H1 gpmc_ad12 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_a9 vin3a_vsync0 vout3_vsync vin4b_vsync1 timer11 spi4_d1 gpio1_31 Driver off gpmc_ad0 vin3a_d0 vout3_d0 gpio1_6 sysboot0 gpmc_ad1 vin3a_d1 vout3_d1 gpio1_7 sysboot1 gpmc_ad10 vin3a_d10 vout3_d10 gpio7_28 sysboot10 gpmc_ad11 vin3a_d11 vout3_d11 gpio7_29 sysboot11 gpmc_ad12 vin3a_d12 vout3_d12 gpio1_18 sysboot12 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 O 6 I 0 7 IO 8 IO 0 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 42 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] J3 gpmc_ad13 H2 gpmc_ad14 H3 gpmc_ad15 L5 gpmc_ad2 M1 gpmc_ad3 L6 gpmc_ad4 L4 gpmc_ad5 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_ad13 vin3a_d13 vout3_d13 gpio1_19 sysboot13 gpmc_ad14 vin3a_d14 vout3_d14 gpio1_20 sysboot14 gpmc_ad15 vin3a_d15 vout3_d15 gpio1_21 sysboot15 gpmc_ad2 vin3a_d2 vout3_d2 gpio1_8 sysboot2 gpmc_ad3 vin3a_d3 vout3_d3 gpio1_9 sysboot3 gpmc_ad4 vin3a_d4 vout3_d4 gpio1_10 sysboot4 gpmc_ad5 vin3a_d5 vout3_d5 gpio1_11 sysboot5 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 43 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] L3 gpmc_ad6 L2 gpmc_ad7 L1 gpmc_ad8 K2 gpmc_ad9 N1 gpmc_advn_ale Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_ad6 vin3a_d6 vout3_d6 gpio1_12 sysboot6 gpmc_ad7 vin3a_d7 vout3_d7 gpio1_13 sysboot7 gpmc_ad8 vin3a_d8 vout3_d8 gpio7_18 sysboot8 gpmc_ad9 vin3a_d9 vout3_d9 gpio7_19 sysboot9 gpmc_advn_ale gpmc_cs6 clkout2 gpmc_wait1 vin4a_vsync0 gpmc_a2 gpmc_a23 timer3 i2c3_sda dma_evt2 gpio2_23 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 2 I Voltage LVCMOS 0 3 O 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 O Voltage LVCMOS 2 O 3 I 1 4 I 0 5 1 6 O 7 IO 8 IO 1 9 I 0 14 IO 15 I 44 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] N6 gpmc_ben0 M4 gpmc_ben1 P7 gpmc_clk T1 gpmc_cs0 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_ben0 gpmc_cs4 vin1b_hsync1 vin3b_de1 timer2 dma_evt3 gpio2_26 Driver off gpmc_ben1 gpmc_cs5 vin1b_de1 vin3b_clk1 gpmc_a3 vin3b_fld1 timer1 dma_evt4 gpio2_27 Driver off gpmc_clk gpmc_cs7 clkout1 gpmc_wait1 vin4a_hsync0 vin4a_de0 vin3b_clk1 timer4 i2c3_scl dma_evt1 gpio2_22 Driver off gpmc_cs0 gpio2_19 Driver off 74x [4] No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 O Voltage LVCMOS 3 I 0 6 I 0 7 IO 9 I 0 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 I 0 7 IO 9 I 0 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 0 1 O Voltage LVCMOS 2 O 3 I 1 4 I 0 5 1 0 6 I 0 7 IO 8 IO 1 9 I 0 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 14 IO Voltage LVCMOS 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 45 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] H6 gpmc_cs1 P2 gpmc_cs2 P1 gpmc_cs3 M5 N2 M3 AG16 AH16 AG17 AH17 AG18 AH18 AG19 AH19 gpmc_oen_ren gpmc_wait0 gpmc_wen hdmi1_clockx hdmi1_clocky hdmi1_data0x hdmi1_data0y hdmi1_data1x hdmi1_data1y hdmi1_data2x hdmi1_data2y Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] gpmc_cs1 mmc2_cmd gpmc_a22 vin4a_de0 vin3b_vsync1 gpio2_18 Driver off gpmc_cs2 qspi1_cs0 gpio2_20 Driver off gpmc_cs3 qspi1_cs1 vin3a_clk0 vout3_clk gpmc_a1 gpio2_21 Driver off gpmc_oen_ren gpio2_24 Driver off gpmc_wait0 gpio2_28 Driver off gpmc_wen gpio2_25 Driver off hdmi1_clockx hdmi1_clocky hdmi1_data0x hdmi1_data0y hdmi1_data1x hdmi1_data1y hdmi1_data2x hdmi1_data2y 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PU PU 15 1.8/3.3 vddshv11 Yes Dual PU/PD 1 IO Voltage LVCMOS 1 2 O 4 I 0 6 I 0 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 O Voltage LVCMOS 1 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 O Voltage LVCMOS 1 2 I 0 3 O 5 1 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 14 IO Voltage LVCMOS 15 I 0 I PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 1 14 IO Voltage LVCMOS 15 I 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual PU/PD 14 IO Voltage LVCMOS 15 I 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy 46 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] C20 i2c1_scl C21 i2c1_sda F17 i2c2_scl C25 i2c2_sda AH15 AG15 B14 ljcb_clkn ljcb_clkp mcasp1_aclkr C14 mcasp1_aclkx G12 mcasp1_axr0 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] i2c1_scl i2c1_sda i2c2_scl hdmi1_ddc_sda Driver off i2c2_sda hdmi1_ddc_scl Driver off ljcb_clkn ljcb_clkp mcasp1_aclkr mcasp7_axr2 vout2_d0 vin4a_d0 i2c4_sda gpio5_0 Driver off mcasp1_aclkx vin6a_fld0 i2c3_sda gpio7_31 Driver off mcasp1_axr0 uart6_rxd vin6a_vsync0 i2c5_sda gpio5_2 Driver off 74x [4] No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO OFF OFF 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD 0 IO OFF OFF 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD 0 IO OFF OFF 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 15 I I2C 0 IO OFF OFF 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 15 I I2C 0 IO 1.8 vdda_pcie TBD LJCB TBD 0 IO 1.8 vdda_pcie TBD LJCB TBD 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 10 IO 1 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 7 I Voltage LVCMOS 0 10 IO 1 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 3 I Voltage LVCMOS 1 7 I 0 10 IO 1 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 47 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] F12 mcasp1_axr1 B13 mcasp1_axr10 A12 mcasp1_axr11 E14 mcasp1_axr12 A13 mcasp1_axr13 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mcasp1_axr1 uart6_txd vin6a_hsync0 i2c5_scl gpio5_3 Driver off mcasp1_axr10 mcasp6_aclkx mcasp6_aclkr spi3_d0 vin6a_d13 timer7 gpio5_12 Driver off mcasp1_axr11 mcasp6_fsx mcasp6_fsr spi3_cs0 vin6a_d12 timer8 gpio4_17 Driver off mcasp1_axr12 mcasp7_axr0 spi3_cs1 vin6a_d11 timer9 gpio4_18 Driver off mcasp1_axr13 mcasp7_axr1 vin6a_d10 timer10 gpio6_4 Driver off 74x [4] No No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 3 O Voltage LVCMOS 7 I 0 10 IO 1 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 2 IO 3 IO 0 7 I 0 10 IO 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 2 IO 3 IO 1 7 I 0 10 IO 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 3 IO 1 7 I 0 10 IO 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 7 I 0 10 IO 14 IO 15 I 48 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] G14 mcasp1_axr14 F14 mcasp1_axr15 G13 mcasp1_axr2 J11 mcasp1_axr3 E12 mcasp1_axr4 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mcasp1_axr14 mcasp7_aclkx mcasp7_aclkr vin6a_d9 timer11 gpio6_5 Driver off mcasp1_axr15 mcasp7_fsx mcasp7_fsr vin6a_d8 timer12 gpio6_6 Driver off mcasp1_axr2 mcasp6_axr2 uart6_ctsn vout2_d2 vin4a_d2 gpio5_4 Driver off mcasp1_axr3 mcasp6_axr3 uart6_rtsn vout2_d3 vin4a_d3 gpio5_5 Driver off mcasp1_axr4 mcasp4_axr2 vout2_d4 vin4a_d4 gpio5_6 Driver off 74x [4] No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 2 IO 7 I 0 10 IO 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 2 IO 7 I 0 10 IO 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 3 I 1 6 O 8 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 3 O 6 O 8 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 49 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] F13 mcasp1_axr5 C12 mcasp1_axr6 D12 mcasp1_axr7 B12 mcasp1_axr8 A11 mcasp1_axr9 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mcasp1_axr5 mcasp4_axr3 vout2_d5 vin4a_d5 gpio5_7 Driver off mcasp1_axr6 mcasp5_axr2 vout2_d6 vin4a_d6 gpio5_8 Driver off mcasp1_axr7 mcasp5_axr3 vout2_d7 vin4a_d7 timer4 gpio5_9 Driver off mcasp1_axr8 mcasp6_axr0 spi3_sclk vin6a_d15 timer5 gpio5_10 Driver off mcasp1_axr9 mcasp6_axr1 spi3_d1 vin6a_d14 timer6 gpio5_11 Driver off 74x [4] No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 10 IO 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 3 IO 0 7 I 0 10 IO 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 3 IO 0 7 I 0 10 IO 14 IO 15 I 50 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] J14 mcasp1_fsr D14 mcasp1_fsx E15 mcasp2_aclkr A19 mcasp2_aclkx B15 mcasp2_axr0 A15 mcasp2_axr1 C15 mcasp2_axr2 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mcasp1_fsr mcasp7_axr3 vout2_d1 vin4a_d1 i2c4_scl gpio5_1 Driver off mcasp1_fsx vin6a_de0 i2c3_scl gpio7_30 Driver off mcasp2_aclkr mcasp8_axr2 vout2_d8 vin4a_d8 Driver off mcasp2_aclkx vin6a_d7 Driver off mcasp2_axr0 vout2_d10 vin4a_d10 Driver off mcasp2_axr1 vout2_d11 vin4a_d11 Driver off mcasp2_axr2 mcasp3_axr2 vin6a_d5 gpio6_8 Driver off 74x [4] No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 10 IO 1 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 7 I Voltage LVCMOS 0 10 IO 1 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 7 I Voltage LVCMOS 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 6 O Voltage LVCMOS 8 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 6 O Voltage LVCMOS 8 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 7 I 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 51 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] A16 mcasp2_axr3 D15 mcasp2_axr4 B16 mcasp2_axr5 B17 mcasp2_axr6 A17 mcasp2_axr7 A20 mcasp2_fsr Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mcasp2_axr3 mcasp3_axr3 vin6a_d4 gpio6_9 Driver off mcasp2_axr4 mcasp8_axr0 vout2_d12 vin4a_d12 gpio1_4 Driver off mcasp2_axr5 mcasp8_axr1 vout2_d13 vin4a_d13 gpio6_7 Driver off mcasp2_axr6 mcasp8_aclkx mcasp8_aclkr vout2_d14 vin4a_d14 gpio2_29 Driver off mcasp2_axr7 mcasp8_fsx mcasp8_fsr vout2_d15 vin4a_d15 gpio1_5 Driver off mcasp2_fsr mcasp8_axr3 vout2_d9 vin4a_d9 Driver off 74x [4] No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 7 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 2 IO 6 O 8 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 2 IO 6 O 8 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 0 6 O 8 I 0 15 I 52 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] A18 mcasp2_fsx B18 mcasp3_aclkx B19 mcasp3_axr0 C17 mcasp3_axr1 F15 mcasp3_fsx TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mcasp2_fsx vin6a_d6 Driver off mcasp3_aclkx mcasp3_aclkr mcasp2_axr12 uart7_rxd vin6a_d3 gpio5_13 Driver off mcasp3_axr0 mcasp2_axr14 uart7_ctsn uart5_rxd vin6a_d1 Driver off mcasp3_axr1 mcasp2_axr15 uart7_rtsn uart5_txd vin6a_d0 vin5a_fld0 Driver off mcasp3_fsx mcasp3_fsr mcasp2_axr13 uart7_txd vin6a_d2 gpio5_14 Driver off 74x [4] No No No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 7 I Voltage LVCMOS 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 2 IO 0 3 I 1 7 I 0 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 2 IO Voltage LVCMOS 0 3 I 1 4 I 1 7 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 2 IO Voltage LVCMOS 0 3 O 4 O 7 I 0 9 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 2 IO 0 3 O 7 I 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 53 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] C18 mcasp4_aclkx G16 mcasp4_axr0 D17 mcasp4_axr1 A21 mcasp4_fsx Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mcasp4_aclkx mcasp4_aclkr spi3_sclk uart8_rxd i2c4_sda vout2_d16 vin4a_d16 vin5a_d15 Driver off mcasp4_axr0 spi3_d0 uart8_ctsn uart4_rxd vout2_d18 vin4a_d18 vin5a_d13 Driver off mcasp4_axr1 spi3_cs0 uart8_rtsn uart4_txd vout2_d19 vin4a_d19 vin5a_d12 Driver off mcasp4_fsx mcasp4_fsr spi3_d1 uart8_txd i2c4_scl vout2_d17 vin4a_d17 vin5a_d14 Driver off 74x [4] No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 2 IO 0 3 I 1 4 IO 1 6 O 8 I 0 9 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 2 IO Voltage LVCMOS 0 3 I 1 4 I 1 6 O 8 I 0 9 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 2 IO Voltage LVCMOS 1 3 O 4 O 6 O 8 I 0 9 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 2 IO 0 3 O 4 IO 1 6 O 8 I 0 9 I 0 15 I 54 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] AA3 mcasp5_aclkx AB3 mcasp5_axr0 AA4 mcasp5_axr1 AB9 mcasp5_fsx SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mcasp5_aclkx mcasp5_aclkr spi4_sclk uart9_rxd i2c5_sda mlb_clk vout2_d20 vin4a_d20 vin5a_d11 Driver off mcasp5_axr0 spi4_d0 uart9_ctsn uart3_rxd mlb_sig vout2_d22 vin4a_d22 vin5a_d9 Driver off mcasp5_axr1 spi4_cs0 uart9_rtsn uart3_txd mlb_dat vout2_d23 vin4a_d23 vin5a_d8 Driver off mcasp5_fsx mcasp5_fsr spi4_d1 uart9_txd i2c5_scl vout2_d21 vin4a_d21 vin5a_d10 Driver off 74x [4] No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 2 IO 0 3 I 1 4 IO 1 5 1 1 6 O 8 I 0 9 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual PU/PD 0 2 IO Voltage LVCMOS 0 3 I 1 4 I 1 5 1 1 6 O 8 I 0 9 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual PU/PD 0 2 IO Voltage LVCMOS 1 3 O 4 O 5 1 1 6 O 8 I 0 9 I 0 15 I 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual PU/PD 0 1 IO Voltage LVCMOS 2 IO 0 3 O 4 IO 1 6 O 8 I 0 9 I 0 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 55 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] U4 mdio_d V1 mdio_mclk AB2 mlbp_clk_n AB1 mlbp_clk_p AA2 mlbp_dat_n AA1 mlbp_dat_p AC2 mlbp_sig_n AC1 mlbp_sig_p W6 mmc1_clk Y6 mmc1_cmd AA6 mmc1_dat0 Y4 mmc1_dat1 AA5 mmc1_dat2 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mdio_d uart3_ctsn mii0_txer vin2a_d0 vin4b_d0 gpio5_16 Driver off mdio_mclk uart3_rtsn mii0_col vin2a_clk0 vin4b_clk1 gpio5_15 Driver off mlbp_clk_n mlbp_clk_p mlbp_dat_n mlbp_dat_p mlbp_sig_n mlbp_sig_p mmc1_clk gpio6_21 Driver off mmc1_cmd gpio6_22 Driver off mmc1_dat0 gpio6_23 Driver off mmc1_dat1 gpio6_24 Driver off mmc1_dat2 gpio6_25 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PU PU 15 1.8/3.3 vddshv9 Yes Dual PU/PD 1 1 I Voltage LVCMOS 1 3 O 0 4 I 0 5 1 0 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv9 Yes Dual PU/PD 1 1 O Voltage LVCMOS 3 I 0 4 I 5 1 0 14 IO 15 I 0 I 1.8 vdds_mlbp Yes MLB NA 0 I 1.8 vdds_mlbp Yes MLB NA 0 IO 1.8 vdds_mlbp TBD MLB TBD 0 IO 1.8 vdds_mlbp TBD MLB TBD 0 IO 1.8 vdds_mlbp TBD MLB TBD 0 IO 1.8 vdds_mlbp TBD MLB TBD 0 IO PD OFF 15 1.8/3.3 vddshv8 TBD MMC1 TBD 1 14 IO 15 I 0 IO PD OFF 15 1.8/3.3 vddshv8 TBD MMC1 TBD 1 14 IO 15 I 0 IO PD OFF 15 1.8/3.3 vddshv8 TBD MMC1 TBD 1 14 IO 15 I 0 IO PD OFF 15 1.8/3.3 vddshv8 TBD MMC1 TBD 1 14 IO 15 I 0 IO PD OFF 15 1.8/3.3 vddshv8 TBD MMC1 TBD 1 14 IO 15 I 56 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] Y3 mmc1_dat3 W7 mmc1_sdcd Y9 mmc1_sdwp AD4 mmc3_clk AC4 mmc3_cmd AC7 mmc3_dat0 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mmc1_dat3 gpio6_26 Driver off mmc1_sdcd uart6_rxd i2c4_sda gpio6_27 Driver off mmc1_sdwp uart6_txd i2c4_scl gpio6_28 Driver off mmc3_clk usb3_ulpi_d5 vin2b_d7 vin5a_d7 ehrpwm2_tripzone_input gpio6_29 Driver off mmc3_cmd spi3_sclk usb3_ulpi_d4 vin2b_d6 vin5a_d6 eCAP2_in_PWM2_out gpio6_30 Driver off mmc3_dat0 spi3_d1 uart5_rxd usb3_ulpi_d3 vin2b_d5 vin5a_d5 eQEP3A_in gpio6_31 Driver off 74x [4] No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD OFF 15 1.8/3.3 vddshv8 TBD MMC1 TBD 1 14 IO 15 I 0 I 3 I PU OFF 15 1.8/3.3 vddshv8 Yes Dual PU/PD 1 Voltage LVCMOS 1 4 IO 1 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv8 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 IO 1 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 3 IO Voltage LVCMOS 0 4 I 0 9 I 0 10 IO 0 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 0 3 IO 0 4 I 0 9 I 0 10 IO 0 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 0 2 I 1 3 IO 0 4 I 0 9 I 0 10 I 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 57 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] AC6 mmc3_dat1 AC9 mmc3_dat2 AC3 mmc3_dat3 AC8 mmc3_dat4 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mmc3_dat1 spi3_d0 uart5_txd usb3_ulpi_d2 vin2b_d4 vin5a_d4 eQEP3B_in gpio7_0 Driver off mmc3_dat2 spi3_cs0 uart5_ctsn usb3_ulpi_d1 vin2b_d3 vin5a_d3 eQEP3_index gpio7_1 Driver off mmc3_dat3 spi3_cs1 uart5_rtsn usb3_ulpi_d0 vin2b_d2 vin5a_d2 eQEP3_strobe gpio7_2 Driver off mmc3_dat4 spi4_sclk uart10_rxd usb3_ulpi_nxt vin2b_d1 vin5a_d1 ehrpwm3A gpio1_22 Driver off 74x [4] No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 0 2 O 3 IO 0 4 I 0 9 I 0 10 I 0 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 1 2 I 1 3 IO 0 4 I 0 9 I 0 10 IO 0 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 1 2 O 3 IO 0 4 I 0 9 I 0 10 IO 0 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 0 2 I 1 3 I 0 4 I 0 9 I 0 10 O 14 IO 15 I 58 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] AD6 mmc3_dat5 AB8 mmc3_dat6 AB5 mmc3_dat7 D21 Y11 AG13 AG11 AH13 AH11 AG14 AG12 nmi_dsp on_off pcie_rxn0 pcie_rxn1 pcie_rxp0 pcie_rxp1 pcie_txn0 pcie_txn1 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] mmc3_dat5 spi4_d1 uart10_txd usb3_ulpi_dir vin2b_d0 vin5a_d0 ehrpwm3B gpio1_23 Driver off mmc3_dat6 spi4_d0 uart10_ctsn usb3_ulpi_stp vin2b_de1 vin5a_hsync0 ehrpwm3_tripzone_input gpio1_24 Driver off mmc3_dat7 spi4_cs0 uart10_rtsn usb3_ulpi_clk vin2b_clk1 vin5a_vsync0 eCAP3_in_PWM3_out gpio1_25 Driver off nmi_dsp on_off pcie_rxn0 pcie_rxn1 pcie_rxp0 pcie_rxp1 pcie_txn0 pcie_txn1 74x [4] No No No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 0 2 O 3 I 0 4 I 0 9 I 0 10 O 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 0 2 I 1 3 O 4 I 9 I 0 10 IO 0 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual PU/PD 1 1 IO Voltage LVCMOS 1 2 O 3 I 0 4 I 9 I 0 10 IO 0 14 IO 15 I 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0 O PU drive 1 (OFF) 1.8/3.3 vddshv5 Yes RTC PU/PD 0 I 1.8 vdda_pcie0 0 I 1.8 vdda_pcie1 0 I 1.8 vdda_pcie0 0 I 1.8 vdda_pcie1 0 O 1.8 vdda_pcie0 0 O 1.8 vdda_pcie1 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 59 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] AH14 AH12 F22 E23 pcie_txp0 pcie_txp1 porz resetn U5 rgmii0_rxc V5 rgmii0_rxctl W2 rgmii0_rxd0 Y2 rgmii0_rxd1 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] pcie_txp0 pcie_txp1 porz resetn rgmii0_rxc rmii1_txen mii0_txclk vin2a_d5 vin4b_d5 usb4_ulpi_d2 gpio5_26 Driver off rgmii0_rxctl rmii1_txd1 mii0_txd3 vin2a_d6 vin4b_d6 usb4_ulpi_d3 gpio5_27 Driver off rgmii0_rxd0 rmii0_txd0 mii0_txd0 vin2a_fld0 vin4b_fld1 usb4_ulpi_d7 gpio5_31 Driver off rgmii0_rxd1 rmii0_txd1 mii0_txd1 vin2a_d9 usb4_ulpi_d6 gpio5_30 Driver off 74x [4] No No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O 1.8 vdda_pcie0 0 O 1.8 vdda_pcie1 0 I 1.8/3.3 vddshv3 TBD IHHV1833 TBD 0 I PU PU 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 0 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 0 6 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 0 2 O Voltage LVCMOS 3 O 4 I 0 5 1 0 6 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 0 1 O Voltage LVCMOS 3 O 4 I 5 1 0 6 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 0 1 O Voltage LVCMOS 3 O 4 I 0 6 IO 0 14 IO 15 I 60 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] V3 rgmii0_rxd2 V4 rgmii0_rxd3 W9 rgmii0_txc V9 rgmii0_txctl SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] rgmii0_rxd2 rmii0_txen mii0_txen vin2a_d8 usb4_ulpi_d5 gpio5_29 Driver off rgmii0_rxd3 rmii1_txd0 mii0_txd2 vin2a_d7 vin4b_d7 usb4_ulpi_d4 gpio5_28 Driver off rgmii0_txc uart3_ctsn rmii1_rxd1 mii0_rxd3 vin2a_d3 vin4b_d3 usb4_ulpi_clk spi3_d0 spi4_cs2 gpio5_20 Driver off rgmii0_txctl uart3_rtsn rmii1_rxd0 mii0_rxd2 vin2a_d4 vin4b_d4 usb4_ulpi_stp spi3_cs0 spi4_cs3 gpio5_21 Driver off 74x [4] No No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 0 1 O Voltage LVCMOS 3 O 4 I 0 6 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 0 2 O Voltage LVCMOS 3 O 4 I 0 5 1 0 6 IO 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 1 I Voltage LVCMOS 1 2 I 0 3 I 0 4 I 0 5 1 0 6 I 0 7 IO 0 8 IO 1 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 1 O Voltage LVCMOS 2 I 0 3 I 0 4 I 0 5 1 0 6 O 7 IO 1 8 IO 1 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 61 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] U6 rgmii0_txd0 V6 rgmii0_txd1 U7 rgmii0_txd2 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] rgmii0_txd0 rmii0_rxd0 mii0_rxd0 vin2a_d10 usb4_ulpi_d1 spi4_cs0 uart4_rtsn gpio5_25 Driver off rgmii0_txd1 rmii0_rxd1 mii0_rxd1 vin2a_vsync0 vin4b_vsync1 usb4_ulpi_d0 spi4_d0 uart4_ctsn gpio5_24 Driver off rgmii0_txd2 rmii0_rxer mii0_rxer vin2a_hsync0 vin4b_hsync1 usb4_ulpi_nxt spi4_d1 uart4_txd gpio5_23 Driver off 74x [4] No No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 1 I Voltage LVCMOS 0 3 I 0 4 I 0 6 IO 0 7 IO 1 8 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 1 I Voltage LVCMOS 0 3 I 0 4 I 5 1 0 6 IO 0 7 IO 0 8 IO 1 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 1 I Voltage LVCMOS 0 3 I 0 4 I 5 1 0 6 I 0 7 IO 0 8 O 14 IO 15 I 62 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] V7 rgmii0_txd3 U3 RMII_MHZ_50_CLK F23 E18 AF14 AE14 AD14 AB17 AH9 AG9 AG10 AH10 A24 A22 rstoutn rtck rtc_iso rtc_osc_xi_clkin32 rtc_osc_xo rtc_porz sata1_rxn0 sata1_rxp0 sata1_txn0 sata1_txp0 spi1_cs0 spi1_cs1 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] rgmii0_txd3 rmii0_crs mii0_crs vin2a_de0 vin4b_de1 usb4_ulpi_dir spi4_sclk uart4_rxd gpio5_22 Driver off RMII_MHZ_50_CLK vin2a_d11 gpio5_17 Driver off rstoutn rtck gpio8_29 rtc_iso rtc_osc_xi_clkin32 rtc_osc_xo rtc_porz sata1_rxn0 sata1_rxp0 sata1_txn0 sata1_txp0 spi1_cs0 gpio7_10 Driver off spi1_cs1 sata1_led spi2_cs1 gpio7_11 Driver off 74x [4] No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 1 I Voltage LVCMOS 0 3 I 0 4 I 5 1 0 6 I 0 7 IO 0 8 I 1 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 0 4 I Voltage LVCMOS 0 14 IO 15 I 0 O PD drive 1 (OFF) 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0 O PU drive clk 0 14 IO (OFF) 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0 I 1.8/3.3 vddshv5 TBD IHHV1833 TBD 0 I 1.8 vdda_rtc No RTC TBD 0 O 1.8 vdda_rtc No RTC TBD 0 I 1.8/3.3 vddshv5 TBD IHHV1833 TBD 0 I 1.8 vdda_sata TBD SATAPHY TBD 0 I 1.8 vdda_sata TBD SATAPHY TBD 0 O 1.8 vdda_sata TBD SATAPHY TBD 0 O 1.8 vdda_sata TBD SATAPHY TBD 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 14 IO Voltage LVCMOS 15 I 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 2 O Voltage LVCMOS 3 IO 1 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 63 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] B21 spi1_cs2 B20 spi1_cs3 B25 spi1_d0 F16 spi1_d1 A25 spi1_sclk B24 spi2_cs0 G17 spi2_d0 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] spi1_cs2 uart4_rxd mmc3_sdcd spi2_cs2 dcan2_tx mdio_mclk hdmi1_hpd gpio7_12 Driver off spi1_cs3 uart4_txd mmc3_sdwp spi2_cs3 dcan2_rx mdio_d hdmi1_cec gpio7_13 Driver off spi1_d0 gpio7_9 Driver off spi1_d1 gpio7_8 Driver off spi1_sclk gpio7_7 Driver off spi2_cs0 uart3_rtsn uart5_txd gpio7_17 Driver off spi2_d0 uart3_ctsn uart5_rxd gpio7_16 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 1 I Voltage LVCMOS 1 2 I 1 3 IO 1 4 IO 1 5 1 1 6 I 14 IO 15 I 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 1 O Voltage LVCMOS 2 I 0 3 IO 1 4 IO 1 5 1 1 6 IO 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 14 IO Voltage LVCMOS 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 14 IO Voltage LVCMOS 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 14 IO Voltage LVCMOS 15 I 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 1 O Voltage LVCMOS 2 O 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 I Voltage LVCMOS 1 2 I 1 14 IO 15 I 64 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] B22 spi2_d1 A26 spi2_sclk E20 tclk D23 tdi F19 tdo F18 tms D20 trstn E25 uart1_ctsn C27 uart1_rtsn B27 uart1_rxd C26 uart1_txd TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] spi2_d1 uart3_txd gpio7_15 Driver off spi2_sclk uart3_rxd gpio7_14 Driver off tclk tdi gpio8_27 tdo gpio8_28 tms trstn uart1_ctsn uart9_rxd mmc4_clk gpio7_24 Driver off uart1_rtsn uart9_txd mmc4_cmd gpio7_25 Driver off uart1_rxd mmc4_sdcd gpio7_22 Driver off uart1_txd mmc4_sdwp gpio7_23 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 O Voltage LVCMOS 14 IO 15 I 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 0 1 I Voltage LVCMOS 1 14 IO 15 I 0 I PU PU 0 1.8/3.3 vddshv3 TBD TCLK TBD 0 I 14 I PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0 O PU PU 0 14 IO 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0 IO OFF OFF 0 1.8/3.3 vddshv3 Yes Dual PU/PD Voltage LVCMOS 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0 I 2 I PU PU 15 1.8/3.3 vddshv4 Yes Dual PU/PD 1 Voltage LVCMOS 1 3 IO 1 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual PU/PD 2 O Voltage LVCMOS 3 IO 1 14 IO 15 I 0 I 3 I PU PU 15 1.8/3.3 vddshv4 Yes Dual PU/PD 1 Voltage LVCMOS 1 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual PU/PD 3 I Voltage LVCMOS 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 65 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] D27 uart2_ctsn C28 uart2_rtsn D28 uart2_rxd D26 uart2_txd Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] uart2_ctsn uart3_rxd mmc4_dat2 uart10_rxd uart1_dtrn gpio1_16 Driver off uart2_rtsn uart3_txd uart3_irtx mmc4_dat3 uart10_txd uart1_rin gpio1_17 Driver off uart3_ctsn uart3_rctx mmc4_dat0 uart2_rxd uart1_dcdn gpio7_26 Driver off uart2_txd uart3_rtsn uart3_sd mmc4_dat1 uart2_txd uart1_dsrn gpio7_27 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 2 I PU PU 15 1.8/3.3 vddshv4 Yes Dual PU/PD 1 Voltage LVCMOS 1 3 IO 1 4 I 1 5 1 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual PU/PD 1 O Voltage LVCMOS 2 O 3 IO 1 4 O 5 1 1 14 IO 15 I 1 I PU PU 15 1.8/3.3 vddshv4 Yes Dual PU/PD 1 2 O Voltage LVCMOS 3 IO 1 4 I 1 5 1 1 14 IO 15 I 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual PU/PD 1 O Voltage LVCMOS 2 O 3 IO 1 4 O 5 1 0 14 IO 15 I 66 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] V2 uart3_rxd Y1 uart3_txd AC12 AD12 AB10 usb1_dm usb1_dp usb1_drvvbus AF11 AE11 AC10 usb2_dm usb2_dp usb2_drvvbus AF12 AE12 AC11 AD11 usb_rxn0 usb_rxp0 usb_txn0 usb_txp0 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] uart3_rxd rmii1_crs mii0_rxdv vin2a_d1 vin4b_d1 spi3_sclk gpio5_18 Driver off uart3_txd rmii1_rxer mii0_rxclk vin2a_d2 vin4b_d2 spi3_d1 spi4_cs1 gpio5_19 Driver off usb1_dm usb1_dp usb1_drvvbus timer16 gpio6_12 Driver off usb2_dm usb2_dp usb2_drvvbus timer15 gpio6_13 Driver off usb_rxn0 usb_rxp0 usb_txn0 usb_txp0 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 2 I 3 I PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 1 Voltage LVCMOS 0 0 4 I 0 5 1 0 7 IO 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual PU/PD 2 I Voltage LVCMOS 0 3 I 0 4 I 0 5 1 0 7 IO 0 8 IO 1 14 IO 15 I 0 IO 3.3 vdda33v_us TBD USB3PHY TBD b1 0 IO 3.3 vdda33v_us TBD USB3PHY TBD b1 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 7 IO Voltage LVCMOS 14 IO 15 I 0 IO 3.3 vdda33v_us No USB2PHY TBD b2 0 IO 3.3 vdda33v_us No USB2PHY TBD b2 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 7 IO Voltage LVCMOS 14 IO 15 I 0 I 1.8 vdda_usb1 0 I 1.8 vdda_usb1 0 O 1.8 vdda_usb1 0 O 1.8 vdda_usb1 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 67 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] H13,H14,J17,J18,L vdd 7,L8,N10,N13,P11, P12,P13,R11,R16, R19,T13,T16,T19,U 13,U16,U8,U9,V16, V8 AA12 vdda33v_usb1 Y12 vdda33v_usb2 M14 vdda_abe_per P16 vdda_ddr N11 vdda_debug N12 vdda_dsp_eve P15 vdda_gmac_core R14 vdda_gpu Y17 vdda_hdmi R17 vdda_iva N16 vdda_mpu AD16,AE16 vdda_osc W14 vdda_pcie AA17 vdda_pcie0 AA16 vdda_pcie1 AB13 vdda_rtc V13 vdda_sata AA13 vdda_usb1 AB12 vdda_usb2 W12 vdda_usb3 P14 vdda_video G18,H17,M8,M9,N8 vdds18v ,P8,R8,T8,V21,V22, W17,W18 AA18,AA19,W21,Y vdds18v_ddr1 21 J21,J22,N21,P20,P vdds18v_ddr2 21 E3,E5,G4,G5,H8,H vddshv1 9 N4,N5,P10,R10,R7, vddshv10 T4,T5 J8,K8 vddshv11 B6,D10,E10,H10,H vddshv2 11 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vdd 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] power BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] vdda33v_usb1 vdda33v_usb2 vdda_abe_per vdda_ddr vdda_debug vdda_dsp_eve vdda_gmac_core vdda_gpu vdda_hdmi vdda_iva vdda_mpu vdda_osc vdda_pcie vdda_pcie0 vdda_pcie1 vdda_rtc vdda_sata vdda_usb1 vdda_usb2 vdda_usb3 vdda_video vdds18v vdds18v_ddr1 vdds18v_ddr2 vddshv1 vddshv10 vddshv11 vddshv2 power power power power power power power power power power power power power power power power power power power power power power power power power power power power 68 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] B23,D16,D22,E16, vddshv3 E22,G15,H15,H16, H18,H19 C24 vddshv4 V12 vddshv5 AD5,AD7,AE7,AF5 vddshv6 AB6,AB7 vddshv7 W8,Y8 vddshv8 U10,W4,W5 vddshv9 AA21,AA22,AB21,A vdds_ddr1 B22,AB24,AB25,AC 22,AD26,AG20,AG 28,AH27,W16,W27 E24,G22,G23,H20, vdds_ddr2 H21,H22,J27,L20,L 21,M20,M21,T24,T 25 AA7,Y7 vdds_mlbp J13,K10,K11,K12,K vdd_dspeve 13,L10,L11,L12,M1 0,M11,M12,M13 U11,U12,V10,V11, vdd_gpu V14,W10,W11,W13 U18,U19,V18,V19 vdd_iva K17,K18,L15,L16,L vdd_mpu 17,L18,L19,M15,M1 6,M17,M18,N17,N1 8,P17,P18,R18 AB15 vdd_rtc AG8 vin1a_clk0 AE8 vin1a_d0 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vddshv3 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] power BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] vddshv4 vddshv5 vddshv6 vddshv7 vddshv8 vddshv9 vdds_ddr1 power power power power power power power vdds_ddr2 power vdds_mlbp vdd_dspeve vdd_gpu vdd_iva vdd_mpu power power power power power vdd_rtc vin1a_clk0 vout3_d16 vout3_fld gpio2_30 Driver off vin1a_d0 vout3_d7 vout3_d23 uart8_rxd ehrpwm1A gpio3_4 Driver off power No 0 No 3 No 4 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage O LVCMOS O (7) 14 IO No 15 I No 0 No 3 No 4 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage O LVCMOS O No 5 1 1 No 10 O (7) 14 IO No 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 69 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] AD8 vin1a_d1 AG3 vin1a_d10 AG5 vin1a_d11 AF2 vin1a_d12 AF6 vin1a_d13 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin1a_d1 vout3_d6 vout3_d22 uart8_txd ehrpwm1B gpio3_5 Driver off vin1a_d10 vin1b_d5 vout3_d13 kbd_row4 gpio3_14 Driver off vin1a_d11 vin1b_d4 vout3_d12 gpmc_a23 kbd_row5 gpio3_15 Driver off vin1a_d12 vin1b_d3 usb3_ulpi_d7 vout3_d11 gpmc_a24 kbd_row6 gpio3_16 Driver off vin1a_d13 vin1b_d2 usb3_ulpi_d6 vout3_d10 gpmc_a25 kbd_row7 gpio3_17 Driver off 74x [4] No No No No No (7) No No No No No (7) No No No No No No (7) No No No No No No No (7) No No No No No No No (7) No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 5 1 10 O 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 4 O 9 I 0 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 4 O 5 1 9 I 0 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 2 IO 0 4 O 5 1 9 I 0 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 2 IO 0 4 O 5 1 9 I 0 14 IO 15 I 70 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] AF3 vin1a_d14 AF4 vin1a_d15 AF1 vin1a_d16 AE3 vin1a_d17 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin1a_d14 vin1b_d1 usb3_ulpi_d5 vout3_d9 gpmc_a26 kbd_row8 gpio3_18 Driver off vin1a_d15 vin1b_d0 usb3_ulpi_d4 vout3_d8 gpmc_a27 kbd_col0 gpio3_19 Driver off vin1a_d16 vin1b_d7 usb3_ulpi_d3 vout3_d7 vin3a_d0 kbd_col1 gpio3_20 Driver off vin1a_d17 vin1b_d6 usb3_ulpi_d2 vout3_d6 vin3a_d1 kbd_col2 gpio3_21 Driver off 74x [4] No No No No No No (7) No No No No No No No (7) No No No No No No No (7) No No No No No No No (7) No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 2 IO 0 4 O 5 1 9 I 0 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 2 IO 0 4 O 5 1 9 O 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 2 IO 0 4 O 6 I 0 9 O 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 2 IO 0 4 O 6 I 0 9 O 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 71 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] AE5 vin1a_d18 AE1 vin1a_d19 AG7 vin1a_d2 AE2 vin1a_d20 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin1a_d18 vin1b_d5 usb3_ulpi_d1 vout3_d5 vin3a_d2 kbd_col3 gpio3_22 Driver off vin1a_d19 vin1b_d4 usb3_ulpi_d0 vout3_d4 vin3a_d3 kbd_col4 gpio3_23 Driver off vin1a_d2 vout3_d5 vout3_d21 uart8_ctsn ehrpwm1_tripzone_input gpio3_6 Driver off vin1a_d20 vin1b_d3 usb3_ulpi_nxt vout3_d3 vin3a_d4 kbd_col5 gpio3_24 Driver off 74x [4] No No No No No No (7) No No No No No No No (7) No No No No No No (7) No No No No No No No (7) No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 2 IO 0 4 O 6 I 0 9 O 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 2 IO 0 4 O 6 I 0 9 O 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 5 1 1 10 IO 0 14 IO 15 I 0 I 1 I 2 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 0 4 O 6 I 0 9 O 14 IO 15 I 72 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] AE6 vin1a_d21 AD2 vin1a_d22 AD3 vin1a_d23 AH6 vin1a_d3 AH3 vin1a_d4 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin1a_d21 vin1b_d2 usb3_ulpi_dir vout3_d2 vin3a_d5 kbd_col6 gpio3_25 Driver off vin1a_d22 vin1b_d1 usb3_ulpi_stp vout3_d1 vin3a_d6 kbd_col7 gpio3_26 Driver off vin1a_d23 vin1b_d0 usb3_ulpi_clk vout3_d0 vin3a_d7 kbd_col8 gpio3_27 Driver off vin1a_d3 vout3_d4 vout3_d20 uart8_rtsn eCAP1_in_PWM1_out gpio3_7 Driver off vin1a_d4 vout3_d3 vout3_d19 ehrpwm1_synci gpio3_8 Driver off 74x [4] No No No No No No (7) No No No No No No No (7) No No No No No No No (7) No No No No No No (7) No No No No No (7) No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 1 I 2 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 0 4 O 6 I 0 9 O 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 2 O 4 O 6 I 0 9 O 14 IO 15 I 0 I 1 I 2 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 0 4 O 6 I 0 9 O 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 5 1 10 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 10 I 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 73 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] AH5 vin1a_d5 AG6 vin1a_d6 AH4 vin1a_d7 AG4 vin1a_d8 AG2 vin1a_d9 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin1a_d5 vout3_d2 vout3_d18 ehrpwm1_synco gpio3_9 Driver off vin1a_d6 vout3_d1 vout3_d17 eQEP2A_in gpio3_10 Driver off vin1a_d7 vout3_d0 vout3_d16 eQEP2B_in gpio3_11 Driver off vin1a_d8 vin1b_d7 vout3_d15 kbd_row2 eQEP2_index gpio3_12 Driver off vin1a_d9 vin1b_d6 vout3_d14 kbd_row3 eQEP2_strobe gpio3_13 Driver off 74x [4] No No No No (7) No No No No No (7) No No No No No (7) No No No No No No (7) No No No No No No (7) No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 10 O 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 10 I 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 10 I 0 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 4 O 9 I 0 10 IO 0 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 4 O 9 I 0 10 IO 0 14 IO 15 I 74 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] AD9 vin1a_de0 AF9 vin1a_fld0 AE9 vin1a_hsync0 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin1a_de0 vin1b_hsync1 vout3_d17 vout3_de uart7_rxd timer16 spi3_sclk kbd_row0 eQEP1A_in gpio3_0 Driver off vin1a_fld0 vin1b_vsync1 vout3_clk uart7_txd timer15 spi3_d1 kbd_row1 eQEP1B_in gpio3_1 Driver off vin1a_hsync0 vin1b_fld1 vout3_hsync uart7_ctsn timer14 spi3_d0 eQEP1_index gpio3_2 Driver off 74x [4] No No No No No No No No No (7) No No No No No No No No No (7) No No No No No No No No (7) No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 3 O 4 O 5 1 1 7 IO 8 IO 0 9 I 0 10 I 0 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 4 O 5 1 7 IO 8 IO 0 9 I 0 10 I 0 14 IO 15 I 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 4 O 5 1 1 7 IO 8 IO 0 10 IO 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 75 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] AF8 vin1a_vsync0 AH7 vin1b_clk1 E1 vin2a_clk0 F2 vin2a_d0 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin1a_vsync0 vin1b_de1 vout3_vsync uart7_rtsn timer13 spi3_cs0 eQEP1_strobe gpio3_3 Driver off vin1b_clk1 vin3a_clk0 gpio2_31 Driver off vin2a_clk0 vout2_fld emu5 kbd_row0 eQEP1A_in gpio3_28 Driver off vin2a_d0 vout2_d23 emu10 uart9_ctsn spi4_d0 kbd_row4 ehrpwm1B gpio4_1 Driver off 74x [4] No No No No No No No (7) No No No (7) No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 1 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 4 O 5 1 7 IO 8 IO 1 10 IO 0 14 IO 15 I 0 I 6 I PD PD 15 1.8/3.3 vddshv6 Yes Dual PU/PD 0 Voltage LVCMOS 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 4 O Voltage LVCMOS 5 1 9 I 0 10 I 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 7 I 1 8 IO 0 9 I 0 10 O 14 IO 15 I 76 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] F3 vin2a_d1 D3 vin2a_d10 F6 vin2a_d11 D5 vin2a_d12 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin2a_d1 vout2_d22 emu11 uart9_rtsn spi4_cs0 kbd_row5 ehrpwm1_tripzone_input gpio4_2 Driver off vin2a_d10 mdio_mclk vout2_d13 kbd_col7 ehrpwm2B gpio4_11 Driver off vin2a_d11 mdio_d vout2_d12 kbd_row7 ehrpwm2_tripzone_input gpio4_12 Driver off vin2a_d12 rgmii1_txc vout2_d11 mii1_rxclk kbd_col8 eCAP2_in_PWM2_out gpio4_13 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 7 O 8 IO 1 9 I 0 10 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 3 O Voltage LVCMOS 1 4 O 9 O 10 O 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 3 IO Voltage LVCMOS 1 4 O 9 I 0 10 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 8 I 0 9 O 10 IO 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 77 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] C2 vin2a_d13 C3 vin2a_d14 C4 vin2a_d15 B2 vin2a_d16 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin2a_d13 rgmii1_txctl vout2_d10 mii1_rxdv kbd_row8 eQEP3A_in gpio4_14 Driver off vin2a_d14 rgmii1_txd3 vout2_d9 mii1_txclk eQEP3B_in gpio4_15 Driver off vin2a_d15 rgmii1_txd2 vout2_d8 mii1_txd0 eQEP3_index gpio4_16 Driver off vin2a_d16 vin2b_d7 rgmii1_txd1 vout2_d7 vin3a_d8 mii1_txd1 eQEP3_strobe gpio4_24 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 8 I 0 9 I 0 10 I 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 8 I 0 10 I 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 3 O Voltage LVCMOS 4 O 8 O 10 IO 0 14 IO 15 I 0 I 2 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 Voltage LVCMOS 0 3 O 4 O 6 I 0 8 O 10 IO 0 14 IO 15 I 78 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] D6 vin2a_d17 C5 vin2a_d18 A3 vin2a_d19 D1 vin2a_d2 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin2a_d17 vin2b_d6 rgmii1_txd0 vout2_d6 vin3a_d9 mii1_txd2 ehrpwm3A gpio4_25 Driver off vin2a_d18 vin2b_d5 rgmii1_rxc vout2_d5 vin3a_d10 mii1_txd3 ehrpwm3B gpio4_26 Driver off vin2a_d19 vin2b_d4 rgmii1_rxctl vout2_d4 vin3a_d11 mii1_txer ehrpwm3_tripzone_input gpio4_27 Driver off vin2a_d2 vout2_d21 emu12 uart10_rxd kbd_row6 eCAP1_in_PWM1_out gpio4_3 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 2 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 Voltage LVCMOS 0 3 O 4 O 6 I 0 8 O 10 O 14 IO 15 I 0 I 2 I 3 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 Voltage LVCMOS 0 0 4 O 6 I 0 8 O 10 O 14 IO 15 I 0 I 2 I 3 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 Voltage LVCMOS 0 0 4 O 6 I 0 8 O 0 10 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 8 I 1 9 I 0 10 IO 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 79 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] B3 vin2a_d20 B4 vin2a_d21 B5 vin2a_d22 A4 vin2a_d23 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin2a_d20 vin2b_d3 rgmii1_rxd3 vout2_d3 vin3a_de0 vin3a_d12 mii1_rxer eCAP3_in_PWM3_out gpio4_28 Driver off vin2a_d21 vin2b_d2 rgmii1_rxd2 vout2_d2 vin3a_fld0 vin3a_d13 mii1_col gpio4_29 Driver off vin2a_d22 vin2b_d1 rgmii1_rxd1 vout2_d1 vin3a_hsync0 vin3a_d14 mii1_crs gpio4_30 Driver off vin2a_d23 vin2b_d0 rgmii1_rxd0 vout2_d0 vin3a_vsync0 vin3a_d15 mii1_txen gpio4_31 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 2 I 3 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 Voltage LVCMOS 0 0 4 O 5 1 0 6 I 0 8 I 0 10 IO 0 14 IO 15 I 0 I 2 I 3 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 Voltage LVCMOS 0 0 4 O 5 1 0 6 I 0 8 I 0 14 IO 15 I 0 I 2 I 3 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 Voltage LVCMOS 0 0 4 O 5 1 0 6 I 0 8 I 0 14 IO 15 I 0 I 2 I 3 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 Voltage LVCMOS 0 0 4 O 5 1 0 6 I 0 8 O 14 IO 15 I 80 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] E2 vin2a_d3 D2 vin2a_d4 F4 vin2a_d5 C1 vin2a_d6 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin2a_d3 vout2_d20 emu13 uart10_txd kbd_col0 ehrpwm1_synci gpio4_4 Driver off vin2a_d4 vout2_d19 emu14 uart10_ctsn kbd_col1 ehrpwm1_synco gpio4_5 Driver off vin2a_d5 vout2_d18 emu15 uart10_rtsn kbd_col2 eQEP2A_in gpio4_6 Driver off vin2a_d6 vout2_d17 emu16 mii1_rxd1 kbd_col3 eQEP2B_in gpio4_7 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 8 O 9 O 10 I 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 8 I 1 9 O 10 O 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 8 O 9 O 10 I 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 8 I 0 9 O 10 I 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 81 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] E4 vin2a_d7 F5 vin2a_d8 E6 vin2a_d9 G2 vin2a_de0 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin2a_d7 vout2_d16 emu17 mii1_rxd2 kbd_col4 eQEP2_index gpio4_8 Driver off vin2a_d8 vout2_d15 emu18 mii1_rxd3 kbd_col5 eQEP2_strobe gpio4_9 Driver off vin2a_d9 vout2_d14 emu19 mii1_rxd0 kbd_col6 ehrpwm2A gpio4_10 Driver off vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 vout2_de emu6 kbd_row1 eQEP1B_in gpio3_29 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 8 I 0 9 O 10 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 8 I 0 9 O 10 IO 0 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual PU/PD 0 4 O Voltage LVCMOS 5 1 8 I 0 9 O 10 O 14 IO 15 I 0 I 1 I 2 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 3 I 4 O 5 1 9 I 0 10 I 0 14 IO 15 I 82 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] H7 vin2a_fld0 G1 vin2a_hsync0 G6 vin2a_vsync0 D11 vout1_clk TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vin2a_fld0 vin2b_clk1 vout2_clk emu7 eQEP1_index gpio3_30 Driver off vin2a_hsync0 vin2b_hsync1 vout2_hsync emu8 uart9_rxd spi4_sclk kbd_row2 eQEP1_strobe gpio3_31 Driver off vin2a_vsync0 vin2b_vsync1 vout2_vsync emu9 uart9_txd spi4_d1 kbd_row3 ehrpwm1A gpio4_0 Driver off vout1_clk vin4a_fld0 vin3a_fld0 spi3_cs0 gpio4_19 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I 2 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 4 O 5 1 10 IO 0 14 IO 15 I 0 I 3 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 4 O 5 1 7 I 1 8 IO 0 9 I 0 10 IO 0 14 IO 15 I 0 I 3 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 4 O 5 1 7 O 8 IO 0 9 I 0 10 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 3 I Voltage LVCMOS 0 4 I 0 8 IO 1 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 83 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] F11 vout1_d0 G10 vout1_d1 D7 vout1_d10 D8 vout1_d11 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vout1_d0 uart5_rxd vin4a_d16 vin3a_d16 spi3_cs2 gpio8_0 Driver off vout1_d1 uart5_txd vin4a_d17 vin3a_d17 gpio8_1 Driver off vout1_d10 emu3 vin4a_d10 vin3a_d10 obs5 obs21 obs_irq2 gpio8_10 Driver off vout1_d11 emu10 vin4a_d11 vin3a_d11 obs6 obs22 obs_dmarq2 gpio8_11 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 I Voltage LVCMOS 1 3 I 0 4 I 0 8 IO 1 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 7 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 7 O 14 IO 15 I 84 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] A5 vout1_d12 C6 vout1_d13 C8 vout1_d14 C7 vout1_d15 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vout1_d12 emu11 vin4a_d12 vin3a_d12 obs7 obs23 gpio8_12 Driver off vout1_d13 emu12 vin4a_d13 vin3a_d13 obs8 obs24 gpio8_13 Driver off vout1_d14 emu13 vin4a_d14 vin3a_d14 obs9 obs25 gpio8_14 Driver off vout1_d15 emu14 vin4a_d15 vin3a_d15 obs10 obs26 gpio8_15 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 85 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] B7 vout1_d16 B8 vout1_d17 A7 vout1_d18 A8 vout1_d19 F10 vout1_d2 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vout1_d16 uart7_rxd vin4a_d0 vin3a_d0 gpio8_16 Driver off vout1_d17 uart7_txd vin4a_d1 vin3a_d1 gpio8_17 Driver off vout1_d18 emu4 vin4a_d2 vin3a_d2 obs11 obs27 gpio8_18 Driver off vout1_d19 emu15 vin4a_d3 vin3a_d3 obs12 obs28 gpio8_19 Driver off vout1_d2 emu2 vin4a_d18 vin3a_d18 obs0 obs16 obs_irq1 gpio8_2 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 I Voltage LVCMOS 1 3 I 0 4 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 7 O 14 IO 15 I 86 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] C9 vout1_d20 A9 vout1_d21 B9 vout1_d22 A10 vout1_d23 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vout1_d20 emu16 vin4a_d4 vin3a_d4 obs13 obs29 gpio8_20 Driver off vout1_d21 emu17 vin4a_d5 vin3a_d5 obs14 obs30 gpio8_21 Driver off vout1_d22 emu18 vin4a_d6 vin3a_d6 obs15 obs31 gpio8_22 Driver off vout1_d23 emu19 vin4a_d7 vin3a_d7 spi3_cs3 gpio8_23 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 8 IO 1 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 87 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] G11 vout1_d3 E9 vout1_d4 F9 vout1_d5 F8 vout1_d6 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vout1_d3 emu5 vin4a_d19 vin3a_d19 obs1 obs17 obs_dmarq1 gpio8_3 Driver off vout1_d4 emu6 vin4a_d20 vin3a_d20 obs2 obs18 gpio8_4 Driver off vout1_d5 emu7 vin4a_d21 vin3a_d21 obs3 obs19 gpio8_5 Driver off vout1_d6 emu8 vin4a_d22 vin3a_d22 obs4 obs20 gpio8_6 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 7 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 5 1 6 O 14 IO 15 I 88 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] E7 vout1_d7 E8 vout1_d8 D9 vout1_d9 B10 vout1_de B11 vout1_fld C11 vout1_hsync TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vout1_d7 emu9 vin4a_d23 vin3a_d23 gpio8_7 Driver off vout1_d8 uart6_rxd vin4a_d8 vin3a_d8 gpio8_8 Driver off vout1_d9 uart6_txd vin4a_d9 vin3a_d9 gpio8_9 Driver off vout1_de vin4a_de0 vin3a_de0 spi3_d1 gpio4_20 Driver off vout1_fld vin4a_clk0 vin3a_clk0 spi3_cs1 gpio4_21 Driver off vout1_hsync vin4a_hsync0 vin3a_hsync0 spi3_d0 gpio4_22 Driver off 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 I Voltage LVCMOS 1 3 I 0 4 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 2 O Voltage LVCMOS 3 I 0 4 I 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 3 I Voltage LVCMOS 0 4 I 0 8 IO 0 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 3 I Voltage LVCMOS 0 4 I 0 8 IO 1 14 IO 15 I 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 3 I Voltage LVCMOS 0 4 I 0 8 IO 0 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 89 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com BALL NUMBER [1] BALL NAME [2] E11 vout1_vsync A1,A14,A2,A23,A28 vss ,A6,AA10,AA14,AA 15,AA20,AA8,AA9, AB14,AB20,AD1,A D24,AG1,AH1,AH2, AH20,AH28,AH8,B 1,D13,D19,E13,E19 ,F1,F7,G7,G8,G9,H 12,J12,J15,J28,K1, K15,K24,K25,K4,K5 ,L13,L14,M19,N14, N15,N19,N24,N25, P28,R1,R12,R13,R 15,R21,T10,T11,T1 2,T14,T15,T17,T18, T21,U15,U17,U20, U21,V15,V17,W1,W 15,W24,W25,W28 AD19,AE19 vssa_hdmi AF15 vssa_osc0 AC14 vssa_osc1 AD13,AE13 vssa_pcie AE10 vssa_sata AA11,AB11 vssa_usb AD10 vssa_usb3 U14 vssa_video AD17 Wakeup0 AC17 Wakeup1 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] vout1_vsync vin4a_vsync0 vin3a_vsync0 spi3_sclk gpio4_23 Driver off vss 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual PU/PD 3 I Voltage LVCMOS 0 4 I 0 8 IO 0 14 IO 15 I ground vssa_hdmi vssa_osc0 vssa_osc1 vssa_pcie vssa_sata vssa_usb vssa_usb3 vssa_video Wakeup0 dcan1_rx gpio1_0 Driver off Wakeup1 dcan2_rx gpio1_1 Driver off ground ground ground ground ground ground ground ground 0 I OFF OFF 15 1.8/3.3 vddshv5 TBD IHHV1833 TBD 1 I 1 14 I 15 I 0 I OFF OFF 15 1.8/3.3 vddshv5 TBD IHHV1833 TBD 1 I 1 14 I 15 I 90 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER [1] BALL NAME [2] AB16 Wakeup2 AC16 Wakeup3 AE15 AC15 AD15 AC13 D18 xi_osc0 xi_osc1 xo_osc0 xo_osc1 xref_clk0 E17 xref_clk1 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-2. Ball Characteristics(1) (continued) SIGNAL NAME [3] Wakeup2 sys_nirq2 gpio1_2 Driver off Wakeup3 sys_nirq1 gpio1_3 Driver off xi_osc0 xi_osc1 xo_osc0 xo_osc1 xref_clk0 mcasp2_axr8 mcasp1_axr4 mcasp1_ahclkx mcasp5_ahclkx atl_clk0 vin6a_d0 hdq0 clkout2 timer13 gpio6_17 Driver off xref_clk1 mcasp2_axr9 mcasp1_axr5 mcasp2_ahclkx mcasp6_ahclkx atl_clk1 vin6a_clk0 timer14 gpio6_18 Driver off 74x [4] No No BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] 0 I OFF OFF 15 1.8/3.3 vddshv5 TBD IHHV1833 TBD 1 I 14 I 15 I 0 I OFF OFF 15 1.8/3.3 vddshv5 TBD IHHV1833 TBD 1 I 14 I 15 I 0 I 1.8 vdda_osc No LVCMOS No Analog 0 I 1.8 vdda_osc No LVCMOS No Analog 0 O 1.8 vdda_osc No LVCMOS No Analog 0 A 1.8 vdda_osc No LVCMOS No Analog 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 IO Voltage LVCMOS 0 2 IO 0 3 O 4 O 5 1 7 I 0 8 IO 1 9 O 10 IO 14 IO 15 I 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 IO Voltage LVCMOS 0 2 IO 0 3 O 4 O 5 1 7 I 0 10 IO 14 IO 15 I Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 91 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 2-2. Ball Characteristics(1) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4] BALL RESET REL. MUXMODE [5] BUFFER TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET I/O REL. VOLTAGE MUXMODE VALUE [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] B26 xref_clk2 xref_clk2 mcasp2_axr10 mcasp1_axr6 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 IO Voltage LVCMOS 0 2 IO 0 mcasp3_ahclkx 3 O mcasp7_ahclkx 4 O atl_clk2 5 1 vout2_clk 6 O vin4a_clk0 8 I 0 timer15 10 IO gpio6_19 14 IO Driver off 15 I C23 xref_clk3 xref_clk3 mcasp2_axr11 mcasp1_axr7 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual PU/PD 1 IO Voltage LVCMOS 0 2 IO 0 mcasp4_ahclkx 3 O mcasp8_ahclkx 4 O atl_clk3 5 1 vout2_de 6 O hdq0 7 IO 1 vin4a_de0 8 I 0 clkout3 9 O timer16 10 IO gpio6_20 14 IO Driver off 15 I (1) NA in this table stands for Not Applicable. (2) For more information on recommended operating conditions, see Table 3-2, Recommended Operating Conditions. (3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA. (4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the Device TRM. (5) IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V). (6) Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ. For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification. (7) This function will not be supported on some pin-compatibleroadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals. 92 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com 2.3 Multiplexing Characteristics Table 2-3 describes the device multiplexing (no characteristics are available in this table). SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 NOTE This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 2.4, Signal Descriptions. NOTE For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration section of the Device TRM. NOTE Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. (Hi Z mode is not an input signal.) NOTE When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided. Table 2-3. Multiplexing Characteristics ADDRESS REGISTER NAME BALL NUMBER 0 1 2 3 4 MUXMODE[15:0] SETTINGS 5 6 7 8 9 10 14 15 P25 ddr2_a6 Y23 ddr1_d26 Y19 ddr1_d21 AE15 xi_osc0 AH24 ddr1_nck D21 nmi_dsp AG15 ljcb_clkp AF24 ddr1_d4 U25 ddr2_wen F27 ddr2_d5 V25 ddr1_ecc_d6 M27 ddr2_dqsn3 G26 ddr2_d12 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 93 ADVANCE INFORMATION EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 ADDRESS REGISTER NAME Table 2-3. Multiplexing Characteristics (continued) BALL NUMBER 0 1 AG19 hdmi1_data2 x AF21 ddr1_a4 E27 ddr2_d6 F24 ddr2_d3 H26 ddr2_d11 W23 ddr1_ecc_d3 Y27 ddr1_dqsn3 AC24 ddr1_d14 J24 ddr2_d15 R26 ddr2_a1 G27 ddr2_dqsn0 AF28 ddr1_d11 AA23 ddr1_d24 AD18 ddr1_a15 H23 ddr2_d8 D28 uart3_ctsn AH16 hdmi1_clock y AC20 ddr1_a2 AA24 ddr1_d27 W19 ddr1_ecc_d2 L24 ddr2_d20 AG11 pcie_rxn1 AG21 ddr1_rst AE28 ddr1_dqsn1 AC11 usb_txn0 L22 ddr2_d16 U28 ddr2_casn K22 ddr2_d22 AG25 ddr1_dqsn0 W20 ddr1_d17 AF14 rtc_iso AA27 ddr1_dqm3 AF25 ddr1_d0 AF23 ddr1_d6 AG18 hdmi1_data1 x AG10 sata1_txn0 AF20 ddr1_rasn 2 uart3_rctx 3 4 mmc4_dat0 uart2_rxd MUXMODE[15:0] SETTINGS 5 6 7 uart1_dcdn 94 Terminal Description Submit Documentation Feedback www.ti.com 8 9 10 14 15 gpio7_26 Driver off Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com ADDRESS REGISTER NAME TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-3. Multiplexing Characteristics (continued) BALL MUXMODE[15:0] SETTINGS NUMBER 0 1 2 3 4 5 6 7 8 9 10 14 15 V26 ddr1_dqm_e cc V20 ddr1_d16 G25 ddr2_d1 AH13 pcie_rxp0 AC18 ddr1_casn AG9 sata1_rxp0 AH23 ddr1_csn0 AE11 usb2_dp R25 ddr2_a0 Y24 ddr1_d28 AH15 ljcb_clkn AD20 ddr1_a0 AA25 ddr1_d30 L23 ddr2_d19 AA1 mlbp_dat_p AD14 rtc_osc_xo J25 ddr2_d13 AC25 ddr1_d13 AB23 ddr1_dqm1 U22 ddr2_a15 T22 ddr2_a13 AH19 hdmi1_data2 y M26 ddr2_d31 AB27 ddr1_d22 AG14 pcie_txn0 Y28 ddr1_dqs3 J20 ddr2_d23 AB19 ddr1_a3 AH10 sata1_txp0 G28 ddr2_dqs0 AG24 ddr1_ck AE24 ddr1_d5 AC15 xi_osc1 AC21 ddr1_a12 K28 ddr2_dqsn2 AB1 mlbp_clk_p AF12 usb_rxn0 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 95 ADVANCE INFORMATION EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 ADDRESS REGISTER NAME Table 2-3. Multiplexing Characteristics (continued) BALL MUXMODE[15:0] SETTINGS NUMBER 0 1 2 3 4 5 6 7 L28 ddr2_d27 M24 ddr2_d29 AH9 sata1_rxn0 AC26 ddr1_dqm2 AA28 ddr1_d31 H28 ddr2_dqsn1 AD23 ddr1_dqm0 E26 ddr2_d0 AE27 ddr1_dqs1 AF27 ddr1_d9 V24 ddr1_ecc_d5 K23 ddr2_dqm2 K20 ddr2_d17 T28 ddr2_ck H24 ddr2_d10 AG27 ddr1_d10 R23 ddr2_odt0 U27 ddr2_ba1 AF22 ddr1_a8 AA2 mlbp_dat_n U23 ddr2_ba0 AH21 ddr1_wen AE21 ddr1_a7 AC12 usb1_dm AH12 pcie_txp1 Y20 ddr1_d23 AC27 ddr1_d20 AE23 ddr1_d7 T27 ddr2_nck AG22 ddr1_cke AD27 ddr1_dqs2 AH14 pcie_txp0 AH26 ddr1_d3 AD21 ddr1_a10 N28 ddr2_a12 Y25 ddr1_ecc_d4 AE17 ddr1_a14 AH18 hdmi1_data1 y 96 Terminal Description Submit Documentation Feedback www.ti.com 8 9 10 14 15 Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-3. Multiplexing Characteristics (continued) ADDRESS REGISTER NAME BALL NUMBER 0 1 2 3 4 MUXMODE[15:0] SETTINGS 5 6 7 8 9 10 14 15 AH22 ddr1_a5 J26 ddr2_d14 W22 ddr1_ecc_d0 V23 ddr1_ecc_d1 AE12 usb_rxp0 AE14 rtc_osc_xi_cl kin32 AH11 pcie_rxp1 AB2 mlbp_clk_n AG23 ddr1_a6 H27 ddr2_dqs1 AB18 ddr1_ba2 AG17 hdmi1_data0 x AF26 ddr1_d1 H25 ddr2_d9 M25 ddr2_d30 AD11 usb_txp0 AC1 mlbp_sig_p L27 ddr2_d24 V27 ddr1_dqs_ec c AF17 ddr1_ba0 AE26 ddr1_d12 G24 ddr2_dqm1 K27 ddr2_dqs2 AC19 ddr1_a1 AG13 pcie_rxn0 L26 ddr2_d25 AB28 ddr1_d18 N23 ddr2_a10 M22 ddr2_dqm3 U26 ddr2_ba2 Y26 ddr1_ecc_d7 P24 ddr2_csn0 R22 ddr2_a14 AD22 ddr1_a11 N20 ddr2_a7 M23 ddr2_d28 AD28 ddr1_dqsn2 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 97 ADVANCE INFORMATION EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 ADDRESS REGISTER NAME Table 2-3. Multiplexing Characteristics (continued) BALL MUXMODE[15:0] SETTINGS NUMBER 0 1 2 3 4 5 6 7 U24 ddr2_cke P22 ddr2_a5 AE18 ddr1_ba1 F26 ddr2_d4 AE20 ddr1_odt0 N22 ddr2_vref0 E28 ddr2_d7 F25 ddr2_d2 AF11 usb2_dm R24 ddr2_rst AD15 xo_osc0 R27 ddr2_a3 AE22 ddr1_a9 Y18 ddr1_vref0 AC13 xo_osc1 F28 ddr2_dqm0 J23 ddr2_d21 P26 ddr2_a11 M28 ddr2_dqs3 AC2 mlbp_sig_n AD12 usb1_dp Y22 ddr1_d25 T23 ddr2_rasn AH17 hdmi1_data0 y N27 ddr2_a9 P23 ddr2_a4 AG26 ddr1_d2 AH25 ddr1_dqs0 AG12 pcie_txn1 AF18 ddr1_a13 K21 ddr2_d18 AC28 ddr1_d19 V28 ddr1_dqsn_e cc P27 ddr2_a8 AC23 ddr1_d8 F22 porz L25 ddr2_d26 98 Terminal Description Submit Documentation Feedback www.ti.com 8 9 10 14 15 Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 ADDRESS REGISTER NAME 0x1400 0x1404 0x1408 0x140C 0x1410 0x1414 0x1418 0x141C 0x1420 0x1424 0x1428 0x142C 0x1430 0x1434 0x1438 0x143C 0x1440 0x1444 0x1448 0x144C 0x1450 0x1454 0x1458 0x145C 0x1460 0x1464 0x1468 0x146C 0x1470 0x1474 0x1478 CTRL_CORE_PAD_GPMC_AD0 CTRL_CORE_PAD_GPMC_AD1 CTRL_CORE_PAD_GPMC_AD2 CTRL_CORE_PAD_GPMC_AD3 CTRL_CORE_PAD_GPMC_AD4 CTRL_CORE_PAD_GPMC_AD5 CTRL_CORE_PAD_GPMC_AD6 CTRL_CORE_PAD_GPMC_AD7 CTRL_CORE_PAD_GPMC_AD8 CTRL_CORE_PAD_GPMC_AD9 CTRL_CORE_PAD_GPMC_AD10 CTRL_CORE_PAD_GPMC_AD11 CTRL_CORE_PAD_GPMC_AD12 CTRL_CORE_PAD_GPMC_AD13 CTRL_CORE_PAD_GPMC_AD14 CTRL_CORE_PAD_GPMC_AD15 CTRL_CORE_PAD_GPMC_A0 CTRL_CORE_PAD_GPMC_A1 CTRL_CORE_PAD_GPMC_A2 CTRL_CORE_PAD_GPMC_A3 CTRL_CORE_PAD_GPMC_A4 CTRL_CORE_PAD_GPMC_A5 CTRL_CORE_PAD_GPMC_A6 CTRL_CORE_PAD_GPMC_A7 CTRL_CORE_PAD_GPMC_A8 CTRL_CORE_PAD_GPMC_A9 CTRL_CORE_PAD_GPMC_A10 CTRL_CORE_PAD_GPMC_A11 CTRL_CORE_PAD_GPMC_A12 CTRL_CORE_PAD_GPMC_A13 CTRL_CORE_PAD_GPMC_A14 Table 2-3. Multiplexing Characteristics (continued) BALL NUMBER 0 1 AG16 hdmi1_clock x R28 ddr2_a2 AA26 ddr1_d29 AD25 ddr1_d15 M6 gpmc_ad0 M2 gpmc_ad1 L5 gpmc_ad2 M1 gpmc_ad3 L6 gpmc_ad4 L4 gpmc_ad5 L3 gpmc_ad6 L2 gpmc_ad7 L1 gpmc_ad8 K2 gpmc_ad9 J1 gpmc_ad10 J2 gpmc_ad11 H1 gpmc_ad12 J3 gpmc_ad13 H2 gpmc_ad14 H3 gpmc_ad15 R6 gpmc_a0 T9 gpmc_a1 T6 gpmc_a2 T7 gpmc_a3 qspi1_cs2 P6 gpmc_a4 qspi1_cs3 R9 gpmc_a5 R5 gpmc_a6 P5 gpmc_a7 N7 gpmc_a8 R4 gpmc_a9 N9 gpmc_a10 P9 gpmc_a11 P4 gpmc_a12 R3 gpmc_a13 qspi1_rtclk T2 gpmc_a14 qspi1_d3 MUXMODE[15:0] SETTINGS 2 3 4 5 6 7 vin3a_d0 vout3_d0 vin3a_d1 vout3_d1 vin3a_d2 vout3_d2 vin3a_d3 vout3_d3 vin3a_d4 vout3_d4 vin3a_d5 vout3_d5 vin3a_d6 vout3_d6 vin3a_d7 vout3_d7 vin3a_d8 vout3_d8 vin3a_d9 vout3_d9 vin3a_d10 vout3_d10 vin3a_d11 vout3_d11 vin3a_d12 vout3_d12 vin3a_d13 vout3_d13 vin3a_d14 vout3_d14 vin3a_d15 vout3_d15 vin3a_d16 vout3_d16 vin4a_d0 vin3a_d17 vout3_d17 vin4a_d1 vin3a_d18 vout3_d18 vin4a_d2 vin3a_d19 vout3_d19 vin4a_d3 vin3a_d20 vout3_d20 vin4a_d4 vin3a_d21 vout3_d21 vin4a_d5 vin3a_d22 vout3_d22 vin4a_d6 vin3a_d23 vout3_d23 vin4a_d7 vin3a_hsync vout3_hsync 0 vin3a_vsync vout3_vsync 0 vin3a_de0 vout3_de vin3a_fld0 vout3_fld vin4a_fld0 vin4a_clk0 gpmc_a0 vin4a_hsync 0 vin4a_vsync 0 vin4b_d0 i2c4_scl vin4b_d1 i2c4_sda vin4b_d2 uart7_rxd vin4b_d3 uart7_txd vin4b_d4 i2c5_scl vin4b_d5 i2c5_sda vin4b_d6 uart8_rxd vin4b_d7 uart8_txd vin4b_hsync timer12 1 vin4b_vsync timer11 1 vin4b_clk1 timer10 vin4b_de1 timer9 vin4b_fld1 timer8 timer7 timer6 8 9 uart5_rxd uart5_txd uart5_ctsn uart5_rtsn uart6_rxd uart6_txd uart6_ctsn uart6_rtsn spi4_sclk spi4_d1 spi4_d0 spi4_cs0 spi4_cs1 spi4_cs2 dma_evt1 dma_evt2 spi4_cs3 10 14 15 gpio1_6 gpio1_7 gpio1_8 gpio1_9 gpio1_10 gpio1_11 gpio1_12 gpio1_13 gpio7_18 gpio7_19 gpio7_28 gpio7_29 gpio1_18 gpio1_19 gpio1_20 gpio1_21 gpio7_3 gpio7_4 gpio7_5 gpio7_6 gpio1_26 gpio1_27 gpio1_28 gpio1_29 gpio1_30 sysboot0 sysboot1 sysboot2 sysboot3 sysboot4 sysboot5 sysboot6 sysboot7 sysboot8 sysboot9 sysboot10 sysboot11 sysboot12 sysboot13 sysboot14 sysboot15 Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off gpio1_31 Driver off gpio2_0 gpio2_1 gpio2_2 gpio2_3 Driver off Driver off Driver off Driver off gpio2_4 Driver off Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 99 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-3. Multiplexing Characteristics (continued) ADDRESS REGISTER NAME 0x147C 0x1480 0x1484 0x1488 0x148C 0x1490 0x1494 0x1498 0x149C 0x14A0 0x14A4 0x14A8 0x14AC CTRL_CORE_PAD_GPMC_A15 CTRL_CORE_PAD_GPMC_A16 CTRL_CORE_PAD_GPMC_A17 CTRL_CORE_PAD_GPMC_A18 CTRL_CORE_PAD_GPMC_A19 CTRL_CORE_PAD_GPMC_A20 CTRL_CORE_PAD_GPMC_A21 CTRL_CORE_PAD_GPMC_A22 CTRL_CORE_PAD_GPMC_A23 CTRL_CORE_PAD_GPMC_A24 CTRL_CORE_PAD_GPMC_A25 CTRL_CORE_PAD_GPMC_A26 CTRL_CORE_PAD_GPMC_A27 BALL NUMBER 0 U2 gpmc_a15 U1 gpmc_a16 P3 gpmc_a17 R2 gpmc_a18 K7 gpmc_a19 M7 gpmc_a20 J5 gpmc_a21 K6 gpmc_a22 J7 gpmc_a23 J4 gpmc_a24 J6 gpmc_a25 H4 gpmc_a26 H5 gpmc_a27 1 2 qspi1_d2 qspi1_d0 qspi1_d1 qspi1_sclk mmc2_dat4 gpmc_a13 mmc2_dat5 gpmc_a14 mmc2_dat6 gpmc_a15 mmc2_dat7 gpmc_a16 mmc2_clk gpmc_a17 mmc2_dat0 gpmc_a18 mmc2_dat1 gpmc_a19 mmc2_dat2 gpmc_a20 mmc2_dat3 gpmc_a21 0x14B0 CTRL_CORE_PAD_GPMC_CS1 H6 gpmc_cs1 mmc2_cmd gpmc_a22 0x14B4 CTRL_CORE_PAD_GPMC_CS0 T1 0x14B8 CTRL_CORE_PAD_GPMC_CS2 P2 0x14BC CTRL_CORE_PAD_GPMC_CS3 P1 0x14C0 CTRL_CORE_PAD_GPMC_CLK P7 gpmc_cs0 gpmc_cs2 gpmc_cs3 gpmc_clk qspi1_cs0 qspi1_cs1 gpmc_cs7 vin3a_clk0 clkout1 0x14C4 0x14C8 0x14CC 0x14D0 CTRL_CORE_PAD_GPMC_ADVN_AL N1 E CTRL_CORE_PAD_GPMC_OEN_REN M5 CTRL_CORE_PAD_GPMC_WEN M3 CTRL_CORE_PAD_GPMC_BEN0 N6 gpmc_advn_ gpmc_cs6 ale gpmc_oen_r en gpmc_wen gpmc_ben0 gpmc_cs4 clkout2 0x14D4 0x14D8 0x14DC 0x14E0 0x14E4 0x14E8 0x14EC 0x14F0 0x14F4 0x14F8 CTRL_CORE_PAD_GPMC_BEN1 CTRL_CORE_PAD_GPMC_WAIT0 CTRL_CORE_PAD_VIN1A_CLK0 CTRL_CORE_PAD_VIN1B_CLK1 CTRL_CORE_PAD_VIN1A_DE0 M4 N2 AG8 AH7 AD9 CTRL_CORE_PAD_VIN1A_FLD0 AF9 CTRL_CORE_PAD_VIN1A_HSYNC0 AE9 CTRL_CORE_PAD_VIN1A_VSYNC0 AF8 CTRL_CORE_PAD_VIN1A_D0 AE8 CTRL_CORE_PAD_VIN1A_D1 AD8 gpmc_ben1 gpmc_cs5 gpmc_wait0 vin1a_clk0 vin1b_clk1 vin1a_de0 vin1b_hsync 1 vin1a_fld0 vin1b_vsync 1 vin1a_hsync vin1b_fld1 0 vin1a_vsync vin1b_de1 0 vin1a_d0 vin1a_d1 3 4 vin4a_d8 vin4a_d9 vin4a_d10 vin4a_d11 vin4a_d12 vin4a_d13 vin4a_d14 vin4a_d15 vin4a_fld0 vin4a_d8 vin4a_d9 vin4a_d10 vin4a_d11 vin4a_de0 MUXMODE[15:0] SETTINGS 5 6 7 timer5 vin3b_d0 vin3b_d1 vin3b_d2 vin3b_d3 vin3b_d4 vin3b_d5 vin3b_d6 vin3b_d7 vin3b_hsync 1 vin3b_vsync 1 vout3_clk gpmc_a1 gpmc_wait1 vin4a_hsync vin4a_de0 0 gpmc_wait1 vin4a_vsync gpmc_a2 0 vin3b_clk1 gpmc_a23 timer4 timer3 vin1b_hsync 1 vin1b_de1 vin3b_clk1 gpmc_a3 vin3b_de1 timer2 vin3b_fld1 timer1 vout3_d16 vout3_fld vout3_d17 vout3_de uart7_rxd vin3a_clk0 timer16 vout3_clk uart7_txd timer15 vout3_hsync uart7_ctsn timer14 vout3_vsync uart7_rtsn timer13 vout3_d7 vout3_d6 vout3_d23 vout3_d22 uart8_rxd uart8_txd www.ti.com 8 9 10 14 15 gpio2_5 Driver off gpio2_6 Driver off gpio2_7 Driver off gpio2_8 Driver off gpio2_9 Driver off gpio2_10 Driver off gpio2_11 Driver off gpio2_12 Driver off gpio2_13 Driver off gpio2_14 Driver off gpio2_15 Driver off gpio2_16 Driver off gpio2_17 Driver off gpio2_18 Driver off i2c3_scl dma_evt1 gpio2_19 gpio2_20 gpio2_21 gpio2_22 Driver off Driver off Driver off Driver off i2c3_sda dma_evt2 gpio2_23 Driver off gpio2_24 Driver off dma_evt3 gpio2_25 gpio2_26 Driver off Driver off spi3_sclk dma_evt4 kbd_row0 gpio2_27 gpio2_28 gpio2_30 gpio2_31 eQEP1A_in gpio3_0 Driver off Driver off Driver off Driver off Driver off spi3_d1 kbd_row1 eQEP1B_in gpio3_1 Driver off spi3_d0 spi3_cs0 eQEP1_inde gpio3_2 x eQEP1_stro gpio3_3 be ehrpwm1A gpio3_4 ehrpwm1B gpio3_5 Driver off Driver off Driver off Driver off 100 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-3. Multiplexing Characteristics (continued) ADDRESS REGISTER NAME BALL NUMBER 0 1 2 3 4 MUXMODE[15:0] SETTINGS 5 6 7 8 9 0x14FC CTRL_CORE_PAD_VIN1A_D2 AG7 vin1a_d2 vout3_d5 vout3_d21 uart8_ctsn 0x1500 CTRL_CORE_PAD_VIN1A_D3 AH6 vin1a_d3 vout3_d4 vout3_d20 uart8_rtsn 0x1504 CTRL_CORE_PAD_VIN1A_D4 AH3 vin1a_d4 vout3_d3 vout3_d19 0x1508 CTRL_CORE_PAD_VIN1A_D5 AH5 vin1a_d5 vout3_d2 vout3_d18 0x150C 0x1510 0x1514 CTRL_CORE_PAD_VIN1A_D6 CTRL_CORE_PAD_VIN1A_D7 CTRL_CORE_PAD_VIN1A_D8 AG6 AH4 AG4 vin1a_d6 vin1a_d7 vin1a_d8 vin1b_d7 vout3_d1 vout3_d0 vout3_d17 vout3_d16 vout3_d15 kbd_row2 0x1518 CTRL_CORE_PAD_VIN1A_D9 AG2 vin1a_d9 vin1b_d6 vout3_d14 kbd_row3 0x151C 0x1520 0x1524 0x1528 0x152C 0x1530 0x1534 0x1538 0x153C 0x1540 0x1544 0x1548 0x154C 0x1550 0x1554 0x1558 0x155C CTRL_CORE_PAD_VIN1A_D10 CTRL_CORE_PAD_VIN1A_D11 CTRL_CORE_PAD_VIN1A_D12 CTRL_CORE_PAD_VIN1A_D13 CTRL_CORE_PAD_VIN1A_D14 CTRL_CORE_PAD_VIN1A_D15 CTRL_CORE_PAD_VIN1A_D16 CTRL_CORE_PAD_VIN1A_D17 CTRL_CORE_PAD_VIN1A_D18 CTRL_CORE_PAD_VIN1A_D19 CTRL_CORE_PAD_VIN1A_D20 CTRL_CORE_PAD_VIN1A_D21 CTRL_CORE_PAD_VIN1A_D22 CTRL_CORE_PAD_VIN1A_D23 CTRL_CORE_PAD_VIN2A_CLK0 CTRL_CORE_PAD_VIN2A_DE0 CTRL_CORE_PAD_VIN2A_FLD0 AG3 AG5 AF2 AF6 AF3 AF4 AF1 AE3 AE5 AE1 AE2 AE6 AD2 AD3 E1 G2 H7 vin1a_d10 vin1a_d11 vin1a_d12 vin1a_d13 vin1a_d14 vin1a_d15 vin1a_d16 vin1a_d17 vin1a_d18 vin1a_d19 vin1a_d20 vin1b_d5 vin1b_d4 vin1b_d3 vin1b_d2 vin1b_d1 vin1b_d0 vin1b_d7 vin1b_d6 vin1b_d5 vin1b_d4 vin1b_d3 vin1a_d21 vin1a_d22 vin1b_d2 vin1b_d1 vin1a_d23 vin1b_d0 vin2a_clk0 vin2a_de0 vin2a_fld0 vin2a_fld0 usb3_ulpi_d7 usb3_ulpi_d6 usb3_ulpi_d5 usb3_ulpi_d4 usb3_ulpi_d3 usb3_ulpi_d2 usb3_ulpi_d1 usb3_ulpi_d0 usb3_ulpi_nx t usb3_ulpi_dir usb3_ulpi_st p usb3_ulpi_cl k vin2b_fld1 vin2b_clk1 vin2b_de1 vout3_d13 vout3_d12 vout3_d11 vout3_d10 vout3_d9 vout3_d8 vout3_d7 vout3_d6 vout3_d5 vout3_d4 vout3_d3 vout3_d2 vout3_d1 vout3_d0 vout2_fld vout2_de vout2_clk gpmc_a23 gpmc_a24 gpmc_a25 gpmc_a26 gpmc_a27 emu5 emu6 emu7 vin3a_d0 vin3a_d1 vin3a_d2 vin3a_d3 vin3a_d4 vin3a_d5 vin3a_d6 vin3a_d7 kbd_row4 kbd_row5 kbd_row6 kbd_row7 kbd_row8 kbd_col0 kbd_col1 kbd_col2 kbd_col3 kbd_col4 kbd_col5 kbd_col6 kbd_col7 kbd_col8 kbd_row0 kbd_row1 0x1560 0x1564 0x1568 0x156C CTRL_CORE_PAD_VIN2A_HSYNC0 G1 CTRL_CORE_PAD_VIN2A_VSYNC0 G6 CTRL_CORE_PAD_VIN2A_D0 F2 CTRL_CORE_PAD_VIN2A_D1 F3 vin2a_hsync 0 vin2a_vsync 0 vin2a_d0 vin2a_d1 vin2b_hsync vout2_hsync emu8 1 vin2b_vsync vout2_vsync emu9 1 vout2_d23 emu10 vout2_d22 emu11 uart9_rxd spi4_sclk kbd_row2 uart9_txd spi4_d1 kbd_row3 uart9_ctsn uart9_rtsn spi4_d0 spi4_cs0 kbd_row4 kbd_row5 0x1570 CTRL_CORE_PAD_VIN2A_D2 D1 vin2a_d2 vout2_d21 emu12 uart10_rxd kbd_row6 10 14 ehrpwm1_tri gpio3_6 pzone_input eCAP1_in_P gpio3_7 WM1_out ehrpwm1_sy gpio3_8 nci ehrpwm1_sy gpio3_9 nco eQEP2A_in gpio3_10 eQEP2B_in gpio3_11 eQEP2_inde gpio3_12 x eQEP2_stro gpio3_13 be gpio3_14 gpio3_15 gpio3_16 gpio3_17 gpio3_18 gpio3_19 gpio3_20 gpio3_21 gpio3_22 gpio3_23 gpio3_24 gpio3_25 gpio3_26 gpio3_27 eQEP1A_in gpio3_28 eQEP1B_in gpio3_29 eQEP1_inde gpio3_30 x eQEP1_stro gpio3_31 be ehrpwm1A gpio4_0 ehrpwm1B gpio4_1 ehrpwm1_tri gpio4_2 pzone_input eCAP1_in_P gpio4_3 WM1_out 15 Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 101 DRA75x, DRA74x TI Confidential — NDA Restrictions ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY ADDRESS REGISTER NAME 0x1574 CTRL_CORE_PAD_VIN2A_D3 BALL NUMBER 0 E2 vin2a_d3 Table 2-3. Multiplexing Characteristics (continued) MUXMODE[15:0] SETTINGS 1 2 3 4 5 6 7 vout2_d20 emu13 8 9 uart10_txd kbd_col0 0x1578 CTRL_CORE_PAD_VIN2A_D4 D2 vin2a_d4 vout2_d19 emu14 uart10_ctsn kbd_col1 0x157C CTRL_CORE_PAD_VIN2A_D5 F4 0x1580 CTRL_CORE_PAD_VIN2A_D6 C1 0x1584 CTRL_CORE_PAD_VIN2A_D7 E4 vin2a_d5 vin2a_d6 vin2a_d7 vout2_d18 vout2_d17 vout2_d16 emu15 emu16 emu17 uart10_rtsn mii1_rxd1 mii1_rxd2 kbd_col2 kbd_col3 kbd_col4 0x1588 CTRL_CORE_PAD_VIN2A_D8 F5 vin2a_d8 vout2_d15 emu18 mii1_rxd3 kbd_col5 0x158C CTRL_CORE_PAD_VIN2A_D9 E6 0x1590 CTRL_CORE_PAD_VIN2A_D10 D3 0x1594 CTRL_CORE_PAD_VIN2A_D11 F6 vin2a_d9 vin2a_d10 vin2a_d11 mdio_mclk mdio_d vout2_d14 vout2_d13 vout2_d12 emu19 mii1_rxd0 kbd_col6 kbd_col7 kbd_row7 0x1598 CTRL_CORE_PAD_VIN2A_D12 D5 vin2a_d12 rgmii1_txc vout2_d11 mii1_rxclk kbd_col8 0x159C CTRL_CORE_PAD_VIN2A_D13 C2 0x15A0 CTRL_CORE_PAD_VIN2A_D14 C3 0x15A4 CTRL_CORE_PAD_VIN2A_D15 C4 vin2a_d13 vin2a_d14 vin2a_d15 rgmii1_txctl vout2_d10 rgmii1_txd3 vout2_d9 rgmii1_txd2 vout2_d8 mii1_rxdv mii1_txclk mii1_txd0 kbd_row8 0x15A8 CTRL_CORE_PAD_VIN2A_D16 B2 vin2a_d16 vin2b_d7 rgmii1_txd1 vout2_d7 vin3a_d8 mii1_txd1 0x15AC CTRL_CORE_PAD_VIN2A_D17 D6 0x15B0 CTRL_CORE_PAD_VIN2A_D18 C5 0x15B4 CTRL_CORE_PAD_VIN2A_D19 A3 vin2a_d17 vin2a_d18 vin2a_d19 vin2b_d6 vin2b_d5 vin2b_d4 rgmii1_txd0 vout2_d6 rgmii1_rxc vout2_d5 rgmii1_rxctl vout2_d4 vin3a_d9 vin3a_d10 vin3a_d11 mii1_txd2 mii1_txd3 mii1_txer 0x15B8 CTRL_CORE_PAD_VIN2A_D20 B3 vin2a_d20 vin2b_d3 rgmii1_rxd3 vout2_d3 vin3a_de0 vin3a_d12 mii1_rxer 0x15BC 0x15C0 0x15C4 0x15C8 0x15CC 0x15D0 0x15D4 0x15D8 0x15DC 0x15E0 0x15E4 0x15E8 CTRL_CORE_PAD_VIN2A_D21 B4 CTRL_CORE_PAD_VIN2A_D22 B5 CTRL_CORE_PAD_VIN2A_D23 A4 CTRL_CORE_PAD_VOUT1_CLK D11 CTRL_CORE_PAD_VOUT1_DE B10 CTRL_CORE_PAD_VOUT1_FLD B11 CTRL_CORE_PAD_VOUT1_HSYNC C11 CTRL_CORE_PAD_VOUT1_VSYNC E11 CTRL_CORE_PAD_VOUT1_D0 F11 CTRL_CORE_PAD_VOUT1_D1 G10 CTRL_CORE_PAD_VOUT1_D2 F10 CTRL_CORE_PAD_VOUT1_D3 G11 vin2a_d21 vin2a_d22 vin2a_d23 vout1_clk vout1_de vout1_fld vout1_hsync vout1_vsync vout1_d0 vout1_d1 vout1_d2 vout1_d3 vin2b_d2 vin2b_d1 vin2b_d0 uart5_rxd uart5_txd emu2 emu5 rgmii1_rxd2 vout2_d2 vin3a_fld0 vin3a_d13 rgmii1_rxd1 vout2_d1 vin3a_hsync vin3a_d14 0 rgmii1_rxd0 vout2_d0 vin3a_vsync vin3a_d15 0 vin4a_fld0 vin3a_fld0 vin4a_de0 vin3a_de0 vin4a_clk0 vin3a_clk0 vin4a_hsync vin3a_hsync 0 0 vin4a_vsync vin3a_vsync 0 0 vin4a_d16 vin3a_d16 vin4a_d17 vin3a_d17 vin4a_d18 vin3a_d18 obs0 obs16 vin4a_d19 vin3a_d19 obs1 obs17 mii1_col mii1_crs mii1_txen spi3_cs0 spi3_d1 spi3_cs1 spi3_d0 spi3_sclk spi3_cs2 obs_irq1 obs_dmarq1 10 14 ehrpwm1_sy gpio4_4 nci ehrpwm1_sy gpio4_5 nco eQEP2A_in gpio4_6 eQEP2B_in gpio4_7 eQEP2_inde gpio4_8 x eQEP2_stro gpio4_9 be ehrpwm2A gpio4_10 ehrpwm2B gpio4_11 ehrpwm2_tri gpio4_12 pzone_input eCAP2_in_P gpio4_13 WM2_out eQEP3A_in gpio4_14 eQEP3B_in gpio4_15 eQEP3_inde gpio4_16 x eQEP3_stro gpio4_24 be ehrpwm3A gpio4_25 ehrpwm3B gpio4_26 ehrpwm3_tri gpio4_27 pzone_input eCAP3_in_P gpio4_28 WM3_out gpio4_29 gpio4_30 gpio4_31 gpio4_19 gpio4_20 gpio4_21 gpio4_22 gpio4_23 gpio8_0 gpio8_1 gpio8_2 gpio8_3 15 Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off 102 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-3. Multiplexing Characteristics (continued) ADDRESS REGISTER NAME BALL NUMBER 0 1 2 3 4 MUXMODE[15:0] SETTINGS 5 6 7 8 9 0x15EC CTRL_CORE_PAD_VOUT1_D4 E9 vout1_d4 emu6 vin4a_d20 vin3a_d20 obs2 obs18 0x15F0 CTRL_CORE_PAD_VOUT1_D5 F9 vout1_d5 emu7 vin4a_d21 vin3a_d21 obs3 obs19 0x15F4 CTRL_CORE_PAD_VOUT1_D6 F8 vout1_d6 emu8 vin4a_d22 vin3a_d22 obs4 obs20 0x15F8 CTRL_CORE_PAD_VOUT1_D7 E7 vout1_d7 emu9 vin4a_d23 vin3a_d23 0x15FC CTRL_CORE_PAD_VOUT1_D8 E8 vout1_d8 uart6_rxd vin4a_d8 vin3a_d8 0x1600 CTRL_CORE_PAD_VOUT1_D9 D9 vout1_d9 uart6_txd vin4a_d9 vin3a_d9 0x1604 CTRL_CORE_PAD_VOUT1_D10 D7 vout1_d10 emu3 vin4a_d10 vin3a_d10 obs5 obs21 obs_irq2 0x1608 CTRL_CORE_PAD_VOUT1_D11 D8 vout1_d11 emu10 vin4a_d11 vin3a_d11 obs6 obs22 obs_dmarq2 0x160C CTRL_CORE_PAD_VOUT1_D12 A5 vout1_d12 emu11 vin4a_d12 vin3a_d12 obs7 obs23 0x1610 CTRL_CORE_PAD_VOUT1_D13 C6 vout1_d13 emu12 vin4a_d13 vin3a_d13 obs8 obs24 0x1614 CTRL_CORE_PAD_VOUT1_D14 C8 vout1_d14 emu13 vin4a_d14 vin3a_d14 obs9 obs25 0x1618 CTRL_CORE_PAD_VOUT1_D15 C7 vout1_d15 emu14 vin4a_d15 vin3a_d15 obs10 obs26 0x161C CTRL_CORE_PAD_VOUT1_D16 B7 vout1_d16 uart7_rxd vin4a_d0 vin3a_d0 0x1620 CTRL_CORE_PAD_VOUT1_D17 B8 vout1_d17 uart7_txd vin4a_d1 vin3a_d1 0x1624 CTRL_CORE_PAD_VOUT1_D18 A7 vout1_d18 emu4 vin4a_d2 vin3a_d2 obs11 obs27 0x1628 CTRL_CORE_PAD_VOUT1_D19 A8 vout1_d19 emu15 vin4a_d3 vin3a_d3 obs12 obs28 0x162C CTRL_CORE_PAD_VOUT1_D20 C9 vout1_d20 emu16 vin4a_d4 vin3a_d4 obs13 obs29 0x1630 CTRL_CORE_PAD_VOUT1_D21 A9 vout1_d21 emu17 vin4a_d5 vin3a_d5 obs14 obs30 0x1634 CTRL_CORE_PAD_VOUT1_D22 B9 vout1_d22 emu18 vin4a_d6 vin3a_d6 obs15 obs31 0x1638 CTRL_CORE_PAD_VOUT1_D23 A10 vout1_d23 emu19 vin4a_d7 vin3a_d7 spi3_cs3 0x163C CTRL_CORE_PAD_MDIO_MCLK V1 mdio_mclk uart3_rtsn mii0_col vin2a_clk0 vin4b_clk1 0x1640 CTRL_CORE_PAD_MDIO_D U4 mdio_d uart3_ctsn mii0_txer vin2a_d0 vin4b_d0 0x1644 CTRL_CORE_PAD_RMII_MHZ_50_CL U3 K RMII_MHZ_5 0_CLK vin2a_d11 0x1648 CTRL_CORE_PAD_UART3_RXD V2 uart3_rxd rmii1_crs mii0_rxdv vin2a_d1 vin4b_d1 spi3_sclk 0x164C CTRL_CORE_PAD_UART3_TXD Y1 uart3_txd rmii1_rxer mii0_rxclk vin2a_d2 vin4b_d2 spi3_d1 spi4_cs1 0x1650 CTRL_CORE_PAD_RGMII0_TXC W9 rgmii0_txc uart3_ctsn rmii1_rxd1 mii0_rxd3 vin2a_d3 vin4b_d3 usb4_ulpi_cl spi3_d0 k spi4_cs2 0x1654 CTRL_CORE_PAD_RGMII0_TXCTL V9 rgmii0_txctl uart3_rtsn rmii1_rxd0 mii0_rxd2 vin2a_d4 vin4b_d4 usb4_ulpi_st spi3_cs0 p spi4_cs3 0x1658 CTRL_CORE_PAD_RGMII0_TXD3 V7 rgmii0_txd3 rmii0_crs mii0_crs vin2a_de0 vin4b_de1 usb4_ulpi_dir spi4_sclk uart4_rxd 0x165C CTRL_CORE_PAD_RGMII0_TXD2 U7 rgmii0_txd2 rmii0_rxer mii0_rxer vin2a_hsync vin4b_hsync usb4_ulpi_nx spi4_d1 0 1 t uart4_txd 0x1660 CTRL_CORE_PAD_RGMII0_TXD1 V6 rgmii0_txd1 rmii0_rxd1 mii0_rxd1 vin2a_vsync vin4b_vsync usb4_ulpi_d0 spi4_d0 0 1 uart4_ctsn 0x1664 CTRL_CORE_PAD_RGMII0_TXD0 U6 rgmii0_txd0 rmii0_rxd0 mii0_rxd0 vin2a_d10 usb4_ulpi_d1 spi4_cs0 uart4_rtsn 0x1668 CTRL_CORE_PAD_RGMII0_RXC U5 rgmii0_rxc rmii1_txen mii0_txclk vin2a_d5 vin4b_d5 usb4_ulpi_d2 0x166C CTRL_CORE_PAD_RGMII0_RXCTL V5 rgmii0_rxctl rmii1_txd1 mii0_txd3 vin2a_d6 vin4b_d6 usb4_ulpi_d3 0x1670 CTRL_CORE_PAD_RGMII0_RXD3 V4 rgmii0_rxd3 rmii1_txd0 mii0_txd2 vin2a_d7 vin4b_d7 usb4_ulpi_d4 0x1674 CTRL_CORE_PAD_RGMII0_RXD2 V3 rgmii0_rxd2 rmii0_txen mii0_txen vin2a_d8 usb4_ulpi_d5 10 14 15 gpio8_4 Driver off gpio8_5 Driver off gpio8_6 Driver off gpio8_7 Driver off gpio8_8 Driver off gpio8_9 Driver off gpio8_10 Driver off gpio8_11 Driver off gpio8_12 Driver off gpio8_13 Driver off gpio8_14 Driver off gpio8_15 Driver off gpio8_16 Driver off gpio8_17 Driver off gpio8_18 Driver off gpio8_19 Driver off gpio8_20 Driver off gpio8_21 Driver off gpio8_22 Driver off gpio8_23 Driver off gpio5_15 Driver off gpio5_16 Driver off gpio5_17 Driver off gpio5_18 gpio5_19 gpio5_20 Driver off Driver off Driver off gpio5_21 Driver off gpio5_22 gpio5_23 Driver off Driver off gpio5_24 Driver off gpio5_25 gpio5_26 gpio5_27 gpio5_28 gpio5_29 Driver off Driver off Driver off Driver off Driver off Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 103 DRA75x, DRA74x TI Confidential — NDA Restrictions ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY Table 2-3. Multiplexing Characteristics (continued) ADDRESS REGISTER NAME BALL NUMBER 0 1 2 3 4 MUXMODE[15:0] SETTINGS 5 6 7 8 9 0x1678 CTRL_CORE_PAD_RGMII0_RXD1 Y2 rgmii0_rxd1 rmii0_txd1 mii0_txd1 vin2a_d9 usb4_ulpi_d6 0x167C CTRL_CORE_PAD_RGMII0_RXD0 W2 rgmii0_rxd0 rmii0_txd0 mii0_txd0 vin2a_fld0 vin4b_fld1 usb4_ulpi_d7 0x1680 CTRL_CORE_PAD_USB1_DRVVBUS AB10 usb1_drvvbu s timer16 0x1684 CTRL_CORE_PAD_USB2_DRVVBUS AC10 usb2_drvvbu s timer15 0x1688 CTRL_CORE_PAD_GPIO6_14 E21 gpio6_14 mcasp1_axr dcan2_tx 8 uart10_rxd vout2_hsync vin4a_hsync i2c3_sda 0 0x168C CTRL_CORE_PAD_GPIO6_15 F20 gpio6_15 mcasp1_axr dcan2_rx 9 uart10_txd vout2_vsync vin4a_vsync i2c3_scl 0 0x1690 CTRL_CORE_PAD_GPIO6_16 F21 gpio6_16 mcasp1_axr 10 vout2_fld vin4a_fld0 clkout1 0x1694 CTRL_CORE_PAD_XREF_CLK0 D18 xref_clk0 mcasp2_axr mcasp1_axr mcasp1_ahcl mcasp5_ahcl atl_clk0 8 4 kx kx vin6a_d0 hdq0 clkout2 0x1698 CTRL_CORE_PAD_XREF_CLK1 E17 xref_clk1 mcasp2_axr mcasp1_axr mcasp2_ahcl mcasp6_ahcl atl_clk1 9 5 kx kx vin6a_clk0 0x169C CTRL_CORE_PAD_XREF_CLK2 B26 xref_clk2 mcasp2_axr mcasp1_axr mcasp3_ahcl mcasp7_ahcl atl_clk2 10 6 kx kx vout2_clk vin4a_clk0 0x16A0 CTRL_CORE_PAD_XREF_CLK3 C23 xref_clk3 mcasp2_axr mcasp1_axr mcasp4_ahcl mcasp8_ahcl atl_clk3 11 7 kx kx vout2_de hdq0 vin4a_de0 clkout3 0x16A4 CTRL_CORE_PAD_MCASP1_ACLKX C14 mcasp1_aclk x vin6a_fld0 0x16A8 CTRL_CORE_PAD_MCASP1_FSX D14 mcasp1_fsx vin6a_de0 0x16AC CTRL_CORE_PAD_MCASP1_ACLKR B14 mcasp1_aclk mcasp7_axr r 2 vout2_d0 vin4a_d0 0x16B0 CTRL_CORE_PAD_MCASP1_FSR J14 mcasp1_fsr mcasp7_axr 3 vout2_d1 vin4a_d1 0x16B4 CTRL_CORE_PAD_MCASP1_AXR0 G12 mcasp1_axr 0 uart6_rxd vin6a_vsync 0 0x16B8 CTRL_CORE_PAD_MCASP1_AXR1 F12 mcasp1_axr 1 uart6_txd vin6a_hsync 0 0x16BC CTRL_CORE_PAD_MCASP1_AXR2 G13 mcasp1_axr mcasp6_axr 2 2 uart6_ctsn vout2_d2 vin4a_d2 0x16C0 CTRL_CORE_PAD_MCASP1_AXR3 J11 mcasp1_axr mcasp6_axr 3 3 uart6_rtsn vout2_d3 vin4a_d3 0x16C4 CTRL_CORE_PAD_MCASP1_AXR4 E12 mcasp1_axr mcasp4_axr 4 2 vout2_d4 vin4a_d4 0x16C8 CTRL_CORE_PAD_MCASP1_AXR5 F13 mcasp1_axr mcasp4_axr 5 3 vout2_d5 vin4a_d5 0x16CC CTRL_CORE_PAD_MCASP1_AXR6 C12 mcasp1_axr mcasp5_axr 6 2 vout2_d6 vin4a_d6 0x16D0 CTRL_CORE_PAD_MCASP1_AXR7 D12 mcasp1_axr mcasp5_axr 7 3 vout2_d7 vin4a_d7 0x16D4 CTRL_CORE_PAD_MCASP1_AXR8 B12 mcasp1_axr mcasp6_axr 8 0 spi3_sclk vin6a_d15 0x16D8 CTRL_CORE_PAD_MCASP1_AXR9 A11 mcasp1_axr mcasp6_axr 9 1 spi3_d1 vin6a_d14 10 timer1 timer2 timer3 timer13 timer14 timer15 timer16 i2c3_sda i2c3_scl i2c4_sda i2c4_scl i2c5_sda i2c5_scl timer4 timer5 timer6 14 gpio5_30 gpio5_31 gpio6_12 gpio6_13 gpio6_14 gpio6_15 gpio6_16 gpio6_17 gpio6_18 gpio6_19 gpio6_20 gpio7_31 gpio7_30 gpio5_0 gpio5_1 gpio5_2 gpio5_3 gpio5_4 gpio5_5 gpio5_6 gpio5_7 gpio5_8 gpio5_9 gpio5_10 gpio5_11 15 Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off 104 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-3. Multiplexing Characteristics (continued) ADDRESS REGISTER NAME BALL NUMBER 0 1 2 3 0x16DC CTRL_CORE_PAD_MCASP1_AXR10 B13 mcasp1_axr mcasp6_aclk mcasp6_aclk spi3_d0 10 x r 0x16E0 CTRL_CORE_PAD_MCASP1_AXR11 A12 mcasp1_axr mcasp6_fsx mcasp6_fsr spi3_cs0 11 0x16E4 CTRL_CORE_PAD_MCASP1_AXR12 E14 mcasp1_axr mcasp7_axr 12 0 spi3_cs1 0x16E8 CTRL_CORE_PAD_MCASP1_AXR13 A13 mcasp1_axr mcasp7_axr 13 1 0x16EC CTRL_CORE_PAD_MCASP1_AXR14 G14 mcasp1_axr mcasp7_aclk mcasp7_aclk 14 x r 0x16F0 CTRL_CORE_PAD_MCASP1_AXR15 F14 mcasp1_axr mcasp7_fsx mcasp7_fsr 15 0x16F4 CTRL_CORE_PAD_MCASP2_ACLKX A19 mcasp2_aclk x 0x16F8 CTRL_CORE_PAD_MCASP2_FSX A18 mcasp2_fsx 0x16FC CTRL_CORE_PAD_MCASP2_ACLKR E15 mcasp2_aclk mcasp8_axr r 2 0x1700 CTRL_CORE_PAD_MCASP2_FSR A20 mcasp2_fsr mcasp8_axr 3 0x1704 CTRL_CORE_PAD_MCASP2_AXR0 B15 mcasp2_axr 0 0x1708 CTRL_CORE_PAD_MCASP2_AXR1 A15 mcasp2_axr 1 0x170C CTRL_CORE_PAD_MCASP2_AXR2 C15 mcasp2_axr mcasp3_axr 2 2 0x1710 CTRL_CORE_PAD_MCASP2_AXR3 A16 mcasp2_axr mcasp3_axr 3 3 0x1714 CTRL_CORE_PAD_MCASP2_AXR4 D15 mcasp2_axr mcasp8_axr 4 0 0x1718 CTRL_CORE_PAD_MCASP2_AXR5 B16 mcasp2_axr mcasp8_axr 5 1 0x171C CTRL_CORE_PAD_MCASP2_AXR6 B17 mcasp2_axr mcasp8_aclk mcasp8_aclk 6 x r 0x1720 CTRL_CORE_PAD_MCASP2_AXR7 A17 mcasp2_axr mcasp8_fsx mcasp8_fsr 7 0x1724 CTRL_CORE_PAD_MCASP3_ACLKX B18 mcasp3_aclk mcasp3_aclk mcasp2_axr uart7_rxd x r 12 0x1728 CTRL_CORE_PAD_MCASP3_FSX F15 mcasp3_fsx mcasp3_fsr mcasp2_axr uart7_txd 13 0x172C CTRL_CORE_PAD_MCASP3_AXR0 B19 mcasp3_axr 0 mcasp2_axr uart7_ctsn 14 0x1730 CTRL_CORE_PAD_MCASP3_AXR1 C17 mcasp3_axr 1 mcasp2_axr uart7_rtsn 15 0x1734 CTRL_CORE_PAD_MCASP4_ACLKX C18 mcasp4_aclk mcasp4_aclk spi3_sclk x r uart8_rxd 0x1738 CTRL_CORE_PAD_MCASP4_FSX A21 mcasp4_fsx mcasp4_fsr spi3_d1 uart8_txd 4 uart5_rxd uart5_txd i2c4_sda i2c4_scl MUXMODE[15:0] SETTINGS 5 6 7 vin6a_d13 vin6a_d12 vin6a_d11 vin6a_d10 vin6a_d9 vin6a_d8 vin6a_d7 vout2_d8 vin6a_d6 vout2_d9 vout2_d10 vout2_d11 vin6a_d5 vin6a_d4 vout2_d12 vout2_d13 vout2_d14 vout2_d15 vin6a_d3 vin6a_d2 vin6a_d1 vin6a_d0 vout2_d16 vout2_d17 8 vin4a_d8 vin4a_d9 vin4a_d10 vin4a_d11 vin4a_d12 vin4a_d13 vin4a_d14 vin4a_d15 vin4a_d16 vin4a_d17 9 vin5a_fld0 vin5a_d15 vin5a_d14 10 timer7 timer8 timer9 timer10 timer11 timer12 14 gpio5_12 15 Driver off gpio4_17 Driver off gpio4_18 Driver off gpio6_4 Driver off gpio6_5 Driver off gpio6_6 Driver off Driver off Driver off Driver off Driver off Driver off Driver off gpio6_8 Driver off gpio6_9 Driver off gpio1_4 Driver off gpio6_7 Driver off gpio2_29 Driver off gpio1_5 Driver off gpio5_13 Driver off gpio5_14 Driver off Driver off Driver off Driver off Driver off Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 105 DRA75x, DRA74x TI Confidential — NDA Restrictions ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY Table 2-3. Multiplexing Characteristics (continued) ADDRESS REGISTER NAME BALL NUMBER 0 1 2 0x173C CTRL_CORE_PAD_MCASP4_AXR0 G16 mcasp4_axr 0 spi3_d0 0x1740 CTRL_CORE_PAD_MCASP4_AXR1 D17 mcasp4_axr 1 spi3_cs0 0x1744 CTRL_CORE_PAD_MCASP5_ACLKX AA3 mcasp5_aclk mcasp5_aclk spi4_sclk x r 0x1748 CTRL_CORE_PAD_MCASP5_FSX AB9 mcasp5_fsx mcasp5_fsr spi4_d1 0x174C CTRL_CORE_PAD_MCASP5_AXR0 AB3 mcasp5_axr 0 spi4_d0 0x1750 CTRL_CORE_PAD_MCASP5_AXR1 AA4 mcasp5_axr 1 spi4_cs0 0x1754 CTRL_CORE_PAD_MMC1_CLK W6 mmc1_clk 0x1758 CTRL_CORE_PAD_MMC1_CMD Y6 mmc1_cmd 0x175C CTRL_CORE_PAD_MMC1_DAT0 AA6 mmc1_dat0 0x1760 CTRL_CORE_PAD_MMC1_DAT1 Y4 mmc1_dat1 0x1764 CTRL_CORE_PAD_MMC1_DAT2 AA5 mmc1_dat2 0x1768 CTRL_CORE_PAD_MMC1_DAT3 Y3 mmc1_dat3 0x176C CTRL_CORE_PAD_MMC1_SDCD W7 mmc1_sdcd 0x1770 CTRL_CORE_PAD_MMC1_SDWP Y9 mmc1_sdwp 0x1774 CTRL_CORE_PAD_GPIO6_10 AC5 gpio6_10 mdio_mclk i2c3_sda 0x1778 CTRL_CORE_PAD_GPIO6_11 AB4 gpio6_11 mdio_d i2c3_scl 0x177C CTRL_CORE_PAD_MMC3_CLK AD4 mmc3_clk 3 uart8_ctsn 4 uart4_rxd MUXMODE[15:0] SETTINGS 5 6 7 vout2_d18 uart8_rtsn uart4_txd vout2_d19 uart9_rxd i2c5_sda mlb_clk vout2_d20 uart9_txd uart9_ctsn i2c5_scl uart3_rxd mlb_sig vout2_d21 vout2_d22 uart9_rtsn uart3_txd mlb_dat vout2_d23 uart6_rxd i2c4_sda uart6_txd i2c4_scl usb3_ulpi_d7 vin2b_hsync 1 usb3_ulpi_d6 vin2b_vsync 1 usb3_ulpi_d5 vin2b_d7 0x1780 CTRL_CORE_PAD_MMC3_CMD AC4 mmc3_cmd spi3_sclk usb3_ulpi_d4 vin2b_d6 0x1784 CTRL_CORE_PAD_MMC3_DAT0 AC7 0x1788 CTRL_CORE_PAD_MMC3_DAT1 AC6 0x178C CTRL_CORE_PAD_MMC3_DAT2 AC9 mmc3_dat0 spi3_d1 mmc3_dat1 spi3_d0 mmc3_dat2 spi3_cs0 uart5_rxd uart5_txd uart5_ctsn usb3_ulpi_d3 vin2b_d5 usb3_ulpi_d2 vin2b_d4 usb3_ulpi_d1 vin2b_d3 0x1790 CTRL_CORE_PAD_MMC3_DAT3 AC3 mmc3_dat3 spi3_cs1 uart5_rtsn usb3_ulpi_d0 vin2b_d2 0x1794 CTRL_CORE_PAD_MMC3_DAT4 AC8 0x1798 CTRL_CORE_PAD_MMC3_DAT5 AD6 0x179C CTRL_CORE_PAD_MMC3_DAT6 AB8 0x17A0 CTRL_CORE_PAD_MMC3_DAT7 AB5 0x17A4 CTRL_CORE_PAD_SPI1_SCLK A25 0x17A8 CTRL_CORE_PAD_SPI1_D1 F16 0x17AC CTRL_CORE_PAD_SPI1_D0 B25 0x17B0 CTRL_CORE_PAD_SPI1_CS0 A24 mmc3_dat4 spi4_sclk mmc3_dat5 spi4_d1 mmc3_dat6 spi4_d0 mmc3_dat7 spi4_cs0 spi1_sclk spi1_d1 spi1_d0 spi1_cs0 uart10_rxd usb3_ulpi_nx vin2b_d1 t uart10_txd usb3_ulpi_dir vin2b_d0 uart10_ctsn usb3_ulpi_st vin2b_de1 p uart10_rtsn usb3_ulpi_cl vin2b_clk1 k 8 9 10 vin4a_d18 vin5a_d13 14 15 Driver off vin4a_d19 vin5a_d12 Driver off vin4a_d20 vin5a_d11 Driver off vin4a_d21 vin4a_d22 vin5a_d10 vin5a_d9 Driver off Driver off vin4a_d23 vin5a_d8 Driver off vin5a_clk0 ehrpwm2A gpio6_21 gpio6_22 gpio6_23 gpio6_24 gpio6_25 gpio6_26 gpio6_27 gpio6_28 gpio6_10 Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off Driver off vin5a_de0 ehrpwm2B gpio6_11 Driver off vin5a_d7 vin5a_d6 vin5a_d5 vin5a_d4 vin5a_d3 vin5a_d2 vin5a_d1 ehrpwm2_tri gpio6_29 pzone_input eCAP2_in_P gpio6_30 WM2_out eQEP3A_in gpio6_31 eQEP3B_in gpio7_0 eQEP3_inde gpio7_1 x eQEP3_stro gpio7_2 be ehrpwm3A gpio1_22 Driver off Driver off Driver off Driver off Driver off Driver off Driver off vin5a_d0 ehrpwm3B gpio1_23 vin5a_hsync ehrpwm3_tri gpio1_24 0 pzone_input vin5a_vsync eCAP3_in_P gpio1_25 0 WM3_out gpio7_7 gpio7_8 gpio7_9 gpio7_10 Driver off Driver off Driver off Driver off Driver off Driver off Driver off 106 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-3. Multiplexing Characteristics (continued) ADDRESS REGISTER NAME BALL NUMBER 0 1 2 3 4 MUXMODE[15:0] SETTINGS 5 6 7 8 9 10 14 15 0x17B4 CTRL_CORE_PAD_SPI1_CS1 A22 spi1_cs1 sata1_led spi2_cs1 gpio7_11 Driver off 0x17B8 CTRL_CORE_PAD_SPI1_CS2 B21 spi1_cs2 uart4_rxd mmc3_sdcd spi2_cs2 dcan2_tx mdio_mclk hdmi1_hpd gpio7_12 Driver off 0x17BC CTRL_CORE_PAD_SPI1_CS3 B20 spi1_cs3 uart4_txd mmc3_sdwp spi2_cs3 dcan2_rx mdio_d hdmi1_cec gpio7_13 Driver off 0x17C0 CTRL_CORE_PAD_SPI2_SCLK A26 spi2_sclk uart3_rxd gpio7_14 Driver off 0x17C4 CTRL_CORE_PAD_SPI2_D1 B22 spi2_d1 uart3_txd gpio7_15 Driver off 0x17C8 CTRL_CORE_PAD_SPI2_D0 G17 spi2_d0 uart3_ctsn uart5_rxd gpio7_16 Driver off 0x17CC CTRL_CORE_PAD_SPI2_CS0 B24 spi2_cs0 uart3_rtsn uart5_txd gpio7_17 Driver off 0x17D0 CTRL_CORE_PAD_DCAN1_TX G20 dcan1_tx uart8_rxd mmc2_sdcd hdmi1_hpd gpio1_14 Driver off 0x17D4 CTRL_CORE_PAD_DCAN1_RX G19 dcan1_rx uart8_txd mmc2_sdwp sata1_led hdmi1_cec gpio1_15 Driver off 0x17E0 CTRL_CORE_PAD_UART1_RXD B27 uart1_rxd mmc4_sdcd gpio7_22 Driver off 0x17E4 CTRL_CORE_PAD_UART1_TXD C26 uart1_txd mmc4_sdwp gpio7_23 Driver off 0x17E8 CTRL_CORE_PAD_UART1_CTSN E25 uart1_ctsn uart9_rxd mmc4_clk gpio7_24 Driver off 0x17EC CTRL_CORE_PAD_UART1_RTSN C27 uart1_rtsn uart9_txd mmc4_cmd gpio7_25 Driver off 0x17F4 CTRL_CORE_PAD_UART2_TXD D26 uart2_txd uart3_rtsn uart3_sd mmc4_dat1 uart2_txd uart1_dsrn gpio7_27 Driver off 0x17F8 CTRL_CORE_PAD_UART2_CTSN D27 uart2_ctsn uart3_rxd mmc4_dat2 uart10_rxd uart1_dtrn gpio1_16 Driver off 0x17FC CTRL_CORE_PAD_UART2_RTSN C28 uart2_rtsn uart3_txd uart3_irtx mmc4_dat3 uart10_txd uart1_rin gpio1_17 Driver off 0x1800 CTRL_CORE_PAD_I2C1_SDA C21 i2c1_sda 0x1804 CTRL_CORE_PAD_I2C1_SCL C20 i2c1_scl 0x1808 CTRL_CORE_PAD_I2C2_SDA C25 i2c2_sda hdmi1_ddc_s cl Driver off 0x180C CTRL_CORE_PAD_I2C2_SCL F17 i2c2_scl hdmi1_ddc_s da Driver off 0x1818 CTRL_CORE_PAD_WAKEUP0 AD17 Wakeup0 dcan1_rx gpio1_0 Driver off 0x181C CTRL_CORE_PAD_WAKEUP1 AC17 Wakeup1 dcan2_rx gpio1_1 Driver off 0x1820 CTRL_CORE_PAD_WAKEUP2 AB16 Wakeup2 sys_nirq2 gpio1_2 Driver off 0x1824 CTRL_CORE_PAD_WAKEUP3 AC16 Wakeup3 sys_nirq1 gpio1_3 Driver off 0x1828 CTRL_CORE_PAD_ON_OFF Y11 on_off 0x182C CTRL_CORE_PAD_RTC_PORZ AB17 rtc_porz 0x1830 CTRL_CORE_PAD_TMS F18 tms 0x1834 CTRL_CORE_PAD_TDI D23 tdi gpio8_27 0x1838 CTRL_CORE_PAD_TDO F19 tdo gpio8_28 0x183C CTRL_CORE_PAD_TCLK E20 tclk 0x1840 CTRL_CORE_PAD_TRSTN D20 trstn 0x1844 CTRL_CORE_PAD_RTCK E18 rtck gpio8_29 0x1848 CTRL_CORE_PAD_EMU0 G21 emu0 gpio8_30 0x184C CTRL_CORE_PAD_EMU1 D24 emu1 gpio8_31 0x185C CTRL_CORE_PAD_RESETN E23 resetn 0x1864 CTRL_CORE_PAD_RSTOUTN F23 rstoutn Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 107 DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 1. NA in table stands for Not Applicable. TI Confidential — NDA Restrictions www.ti.com EARLY PRELIMINARY ADVANCE INFORMATION 108 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 2.4 Signal Descriptions Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options. 1. SIGNAL NAME: The name of the signal passing through the pin. NOTE The subsystem multiplexing signals are not described in Table 2-2 and Table 2-3. 2. DESCRIPTION: Description of the signal 3. TYPE: Signal direction and type: – I = Input – O = Output – IO = Input or output – D = Open Drain – DS = Differential – A = Analog – PWR = Power – GND = Ground 4. BALL: Associated ball(s) bottom 2.4.1 Video Input Ports (VIP) NOTE For more information, see the Control Module / Control Module Register Manual section of the device TRM. Table 2-4. VIP Signal Descriptions SIGNAL NAME Video Input 1 vin1a_clk0 vin1a_de0 vin1a_fld0 vin1a_hsync0 vin1a_vsync0 vin1a_d0 vin1a_d1 vin1a_d2 vin1a_d3 vin1a_d4 vin1a_d5 vin1a_d6 vin1a_d7 vin1a_d8 vin1a_d9 vin1a_d10 vin1a_d11 vin1a_d12 vin1a_d13 DESCRIPTION Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video capture. Input data is sampled on the CLK0 edge. Video Input 1 Data Enable input (1) Video Input 1 Port A Field ID input (1) Video Input 1 Port A Horizontal Sync input (1) Video Input 1 Port A Vertical Sync input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TYPE BALL I AG8 I AD9 I AF9 I AE9 I AF8 I AE8 I AD8 I AG7 I AH6 I AH3 I AH5 I AG6 I AH4 I AG4 I AG2 I AG3 I AG5 I AF2 I AF6 Terminal Description 109 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME vin1a_d14 vin1a_d15 vin1a_d16 vin1a_d17 vin1a_d18 vin1a_d19 vin1a_d20 vin1a_d21 vin1a_d22 vin1a_d23 vin1b_hsync1 vin1b_vsync1 vin1b_fld1 vin1b_de1 vin1b_clk1 vin1b_d0 vin1b_d1 vin1b_d2 vin1b_d3 vin1b_d4 vin1b_d5 vin1b_d6 vin1b_d7 Video Input 2 vin2a_clk0 vin2a_de0 vin2a_fld0 vin2a_hsync0 vin2a_vsync0 vin2a_d0 vin2a_d1 vin2a_d2 vin2a_d3 vin2a_d4 vin2a_d5 vin2a_d6 vin2a_d7 vin2a_d8 vin2a_d9 vin2a_d10 vin2a_d11 vin2a_d12 vin2a_d13 vin2a_d14 vin2a_d15 vin2a_d16 vin2a_d17 Table 2-4. VIP Signal Descriptions (continued) DESCRIPTION Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port A Data input (1) Video Input 1 Port B Horizontal Sync input (1) Video Input 1 Port B Vertical Sync input (1) Video Input 1 Port B Field ID input (1) Video Input 1 Port B Data Enable input(1) Video Input 1 Port B Clock input (1) Video Input 1 Port B Data input (1) Video Input 1 Port B Data input (1) Video Input 1 Port B Data input (1) Video Input 1 Port B Data input (1) Video Input 1 Port B Data input (1) Video Input 1 Port B Data input (1) Video Input 1 Port B Data input (1) Video Input 1 Port B Data input (1) Video Input 1 Port A Clock input. Video Input 1 Port A Data Enable input Video Input 1 Port A Field ID input Video Input 1 Port A Horizontal Sync input Video Input 1 Port A Vertical Sync input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input www.ti.com TYPE I I I I I I I I I I I I I I I I I I I I I I I BALL AF3 AF4 AF1 AE3 AE5 AE1 AE2 AE6 AD2 AD3 N6 / AD9 AF9 AE9 AF8 / M4 AH7 AF4 / AD3 AF3 / AD2 AF6 / AE6 AF2 / AE2 AG5 / AE1 AG3 / AE5 AG2 / AE3 AG4 / AF1 I E1 / V1 I G2 / V7 I H7 / G2 / W2 IO G1 / U7 IO G6 / V6 I F2 / U4 I F3 / V2 I D1 / Y1 I E2 / W9 I D2 / V9 I F4 / U5 I C1 / V5 I E4 / V4 I F5 / V3 I E6 / Y2 I D3 / U6 I F6 / U3 I D5 I C2 I C3 I C4 I B2 I D6 110 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME vin2a_d18 vin2a_d19 vin2a_d20 vin2a_d21 vin2a_d22 vin2a_d23 vin2b_clk1 vin2b_de1 vin2b_fld1 vin2b_hsync1 vin2b_vsync1 vin2b_d0 vin2b_d1 vin2b_d2 vin2b_d3 vin2b_d4 vin2b_d5 vin2b_d6 vin2b_d7 Video Input 3 vin3a_clk0 vin3a_de0 vin3a_fld0 vin3a_hsync0 vin3a_vsync0 vin3a_d0 vin3a_d1 vin3a_d2 vin3a_d3 vin3a_d4 vin3a_d5 vin3a_d6 vin3a_d7 vin3a_d8 vin3a_d9 vin3a_d10 vin3a_d11 vin3a_d12 vin3a_d13 vin3a_d14 vin3a_d15 vin3a_d16 vin3a_d17 vin3a_d18 vin3a_d19 vin3a_d20 vin3a_d21 Table 2-4. VIP Signal Descriptions (continued) DESCRIPTION Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 2 Port A Data input Video Input 1 Port B Clock input Video Input 1 Port B Data Enable input Video Input 1 Port B Field ID input Video Input 1 Port B Horizontal Sync input Video Input 1 Port B Vertical Sync input Video Input 2 Port B Data input Video Input 2 Port B Data input Video Input 2 Port B Data input Video Input 2 Port B Data input Video Input 2 Port B Data input Video Input 2 Port B Data input Video Input 2 Port B Data input Video Input 2 Port B Data input Video Input 3 Port A Clock input Video Input 3 Port A Data Enable input Video Input 3 Port A Field ID input Video Input 3 Port A Horizontal Sync input Video Input 3 Port A Vertical Sync input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port A Data input TYPE I I I I I I I I I I I I I I I I I I I BALL C5 A3 B3 B4 B5 A4 AB5 / H7 AB8 / G2 G2 AC5 / G1 AB4 / G6 AD6 / A4 AC8 / B5 AC3 / B4 AC9 / B3 AC6 / A3 AC7 / C5 AC4 / D6 AD4 / B2 I B11 / AH7 / P1 I N9 / B3 / B10 I P9 / B4 / D11 I N7 / B5 / C11 I R4 / A4 / E11 I M6 / AF1 / B7 I M2 / AE3 / B8 I L5 / AE5 / A7 I M1 / AE1 / A8 I L6 / AE2 / C9 I L4 / AE6 / A9 I L3 / AD2 / B9 I L2 / AD3 / A10 I L1 / B2 / E8 I K2 / D6 / D9 I J1 / C5 / D7 I J2 / A3 / D8 I H1 / B3 / A5 I J3 / B4 / C6 I H2 / B5 / C8 I H3 / A4 / C7 I R6 / F11 I T9 / G10 I T6 / F10 I T7 / G11 I P6 / E9 I R9 / F9 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 111 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME vin3a_d22 vin3a_d23 vin3b_clk1 vin3b_de1 vin3b_fld1 vin3b_hsync1 vin3b_vsync1 vin3b_d0 vin3b_d1 vin3b_d2 vin3b_d3 vin3b_d4 vin3b_d5 vin3b_d6 vin3b_d7 Video Input 4 vin4a_clk0 vin4a_de0 vin4a_fld0 vin4a_hsync0 vin4a_vsync0 vin4a_d0 vin4a_d1 vin4a_d2 vin4a_d3 vin4a_d4 vin4a_d5 vin4a_d6 vin4a_d7 vin4a_d8 vin4a_d9 vin4a_d10 vin4a_d11 vin4a_d12 vin4a_d13 vin4a_d14 vin4a_d15 vin4a_d16 vin4a_d17 vin4a_d18 vin4a_d19 vin4a_d20 vin4a_d21 vin4a_d22 vin4a_d23 vin4b_clk1 vin4b_de1 Table 2-4. VIP Signal Descriptions (continued) DESCRIPTION Video Input 3 Port A Data input Video Input 3 Port A Data input Video Input 3 Port B Clock input Video Input 3 Port B Data Enable input Video Input 3 Port A Field ID input Video Input 3 Port A Horizontal Sync input Video Input 3 Port A Vertical Sync input Video Input 3 Port B Data input Video Input 3 Port B Data input Video Input 3 Port B Data input Video Input 3 Port B Data input Video Input 3 Port B Data input Video Input 3 Port B Data input Video Input 3 Port B Data input Video Input 3 Port B Data input Video Input 4 Port A Clock input Video Input 4 Port A Data Enable input Video Input 4 Port A Field ID input Video Input 4 Port A Horizontal Sync input Video Input 4 Port A Vertical Sync input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port A Data input Video Input 4 Port B Clock input Video Input 4 Port B Data Enable input www.ti.com TYPE I I I I I I I I I I I I I I I BALL R5 / F8 P5 / E7 P7 / M4 N6 M4 H5 H6 K7 M7 J5 K6 J7 J4 J6 H4 I P4 / B26 / B11 I H6 / C23 / B10 / P7 I J7 / F21 / P9 / D11 I R3 / E21 / C11 / P7 I T2 / F20 / E11 / N1 I R6 / B7 / B14 I T9 / B8 / J14 I T6 / A7 / G13 I T7 / A8 / J11 I P6 / C9 / E12 I R9 / A9 / F13 I R5 / B9 / C12 I P5 / A10 / D12 I E8 / U2 / E15 / J4 I D9 / U1 / A20 / J6 I D7 / P3 / B15 / H4 I D8 / R2 / A15 / H5 I A5 / K7 / D15 I C6 / M7 / B16 I C8 / J5 / B17 I C7 / K6 / A17 I C18 / F11 I A21 / G10 I G16 / F10 I D17 / G11 I AA3 / E9 I AB9 / F9 I AB3 / F8 I AA4 / E7 I N9 / V1 I P9 / V7 112 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME vin4b_fld1 vin4b_hsync1 vin4b_vsync1 vin4b_d0 vin4b_d1 vin4b_d2 vin4b_d3 vin4b_d4 vin4b_d5 vin4b_d6 vin4b_d7 Video Input 5 vin5a_clk0 vin5a_de0 vin5a_fld0 vin5a_hsync0 vin5a_vsync0 vin5a_d0 vin5a_d1 vin5a_d2 vin5a_d3 vin5a_d4 vin5a_d5 vin5a_d6 vin5a_d7 vin5a_d8 vin5a_d9 vin5a_d10 vin5a_d11 vin5a_d12 vin5a_d13 vin5a_d14 vin5a_d15 Video Input 6 vin6a_clk0 vin6a_de0 vin6a_fld0 vin6a_hsync0 vin6a_vsync0 vin6a_d0 vin6a_d1 vin6a_d2 vin6a_d3 vin6a_d4 vin6a_d5 vin6a_d6 vin6a_d7 Table 2-4. VIP Signal Descriptions (continued) DESCRIPTION Video Input 4 Port B Field ID input Video Input 4 Port B Horizontal Sync input Video Input 4 Port B Vertical Sync input Video Input 4 Port B Data input Video Input 4 Port B Data input Video Input 4 Port B Data input Video Input 4 Port B Data input Video Input 4 Port B Data input Video Input 4 Port B Data input Video Input 4 Port B Data input Video Input 4 Port B Data input Video Input 5 Port A Clock input (2) Video Input 5 Port A Data Enable input (2) Video Input 5 Port A Field ID input (2) Video Input 5 Port A Horizontal Sync input (2) Video Input 5 Port A Vertical Sync input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 5 Port A Data input (2) Video Input 6 Port A Clock input (2) Video Input 6 Port B Data Enable input(2) Video Input 6 Port A Field ID input (2) Video Input 6 Port A Horizontal Sync input (2) Video Input 6 Port A Vertical Sync input (2) Video Input 6 Port A Data input (2) Video Input 6 Port A Data input (2) Video Input 6 Port A Data input (2) Video Input 6 Port A Data input (2) Video Input 6 Port A Data input (2) Video Input 6 Port A Data input (2) Video Input 6 Port A Data input (2) Video Input 6 Port A Data input (2) TYPE I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I BALL P4 / W2 N7 / U7 R4 / V6 R6 / U4 T9 / V2 T6 / Y1 T7 / W9 P6 / V9 R9 / U5 R5 / V5 P5 / V4 AC5 AB4 C17 AB8 AB5 AD6 AC8 AC3 AC9 AC6 AC7 AC4 AD4 AA4 AB3 AB9 AA3 D17 G16 A21 C18 E17 D14 C14 F12 G12 C17 / D18 B19 F15 B18 A16 C15 A18 A19 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 113 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 2-4. VIP Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL vin6a_d8 Video Input 6 Port A Data input (2) I F14 vin6a_d9 Video Input 6 Port A Data input (2) I G14 vin6a_d10 Video Input 6 Port A Data input (2) I A13 vin6a_d11 Video Input 6 Port A Data input (2) I E14 vin6a_d12 Video Input 6 Port A Data input (2) I A12 vin6a_d13 Video Input 6 Port A Data input (2) I B13 vin6a_d14 Video Input 6 Port A Data input (2) I A11 vin6a_d15 Video Input 6 Port A Data input (2) I B12 (1) The VIP1 interface (Video Input 1a and Video Input 1b in Table 2-4 ) signal sets are NOT supported in the DRA74x device. For more details on the device differentiation, refer to the Table 1-1, Device Comparison in the Section 1, Introduction. (2) The VIP3 interface (Video Input 5 and Video Input 6 in Table 2-4 ) signal sets are NOT supported in the DRA74x device. For more details on the device differentiation, refer to the Table 1-1, Device Comparison in the Section 1, Introduction. 2.4.2 Display Subsystem – Video Output Ports (DPI) Table 2-5. DSS Signal Descriptions SIGNAL NAME DESCRIPTION DPI Video Output 1 vout1_clk Video Output 1 Clock output vout1_de Video Output 1 Data Enable output vout1_fld Video Output 1 Field ID output.This signal is not used for embedded sync modes. vout1_hsync Video Output 1 Horizontal Sync output.This signal is not used for embedded sync modes. vout1_vsync Video Output 1 Vertical Sync output.This signal is not used for embedded sync modes. vout1_d0 Video Output 1 Data output vout1_d1 Video Output 1 Data output vout1_d2 Video Output 1 Data output vout1_d3 Video Output 1 Data output vout1_d4 Video Output 1 Data output vout1_d5 Video Output 1 Data output vout1_d6 Video Output 1 Data output vout1_d7 Video Output 1 Data output vout1_d8 Video Output 1 Data output vout1_d9 Video Output 1 Data output vout1_d10 Video Output 1 Data output vout1_d11 Video Output 1 Data output vout1_d12 Video Output 1 Data output vout1_d13 Video Output 1 Data output vout1_d14 Video Output 1 Data output vout1_d15 Video Output 1 Data output vout1_d16 Video Output 1 Data output vout1_d17 Video Output 1 Data output vout1_d18 Video Output 1 Data output vout1_d19 Video Output 1 Data output vout1_d20 Video Output 1 Data output vout1_d21 Video Output 1 Data output vout1_d22 Video Output 1 Data output vout1_d23 Video Output 1 Data output TYPE O O O O O O O O O O O O O O O O O O O O O O O O O O O O O BALL D11 B10 B11 C11 E11 F11 G10 F10 G11 E9 F9 F8 E7 E8 D9 D7 D8 A5 C6 C8 C7 B7 B8 A7 A8 C9 A9 B9 A10 114 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-5. DSS Signal Descriptions (continued) SIGNAL NAME DESCRIPTION DPI Video Output 2 vout2_clk Video Output 2 Clock output vout2_de Video Output 2 Data Enable output vout2_fld Video Output 2 Field ID output.This signal is not used for embedded sync modes. vout2_hsync Video Output 2 Horizontal Sync output.This signal is not used for embedded sync modes. vout2_vsync Video Output 2 Vertical Sync output.This signal is not used for embedded sync modes. vout2_d0 Video Output 2 Data output vout2_d1 Video Output 2 Data output vout2_d2 Video Output 2 Data output vout2_d3 Video Output 2 Data output vout2_d4 Video Output 2 Data output vout2_d5 Video Output 2 Data output vout2_d6 Video Output 2 Data output vout2_d7 Video Output 2 Data output vout2_d8 Video Output 2 Data output vout2_d9 Video Output 2 Data output vout2_d10 Video Output 2 Data output vout2_d11 Video Output 2 Data output vout2_d12 Video Output 2 Data output vout2_d13 Video Output 2 Data output vout2_d14 Video Output 2 Data output vout2_d15 Video Output 2 Data output vout2_d16 Video Output 2 Data output vout2_d17 Video Output 2 Data output vout2_d18 Video Output 2 Data output vout2_d19 Video Output 2 Data output vout2_d20 Video Output 2 Data output vout2_d21 Video Output 2 Data output vout2_d22 Video Output 2 Data output vout2_d23 Video Output 2 Data output DPI Video Output 3 vout3_clk Video Output 3 Clock output vout3_de Video Output 3 Data Enable output vout3_fld Video Output 3 Field ID output.This signal is not used for embedded sync modes. vout3_hsync Video Output 3 Horizontal Sync output.This signal is not used for embedded sync modes. vout3_vsync Video Output 3 Vertical Sync output.This signal is not used for embedded sync modes. vout3_d0 Video Output 3 Data output vout3_d1 Video Output 3 Data output vout3_d2 Video Output 3 Data output vout3_d3 Video Output 3 Data output vout3_d4 Video Output 3 Data output vout3_d5 Video Output 3 Data output vout3_d6 Video Output 3 Data output vout3_d7 Video Output 3 Data output vout3_d8 Video Output 3 Data output vout3_d9 Video Output 3 Data output TYPE O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O BALL H7 / B26 G2 / C23 E1 / F21 G1 / E21 G6 / F20 A4 / B14 B5 / J14 B4 / G13 B3 / J11 A3 / E12 C5 / F13 D6 / C12 B2 / D12 C4 / E15 C3 / A20 C2 / B15 D5 / A15 F6 / D15 D3 / B16 E6 / B17 F5 / A17 E4 / C18 C1 / A21 F4 / G16 D2 / D17 E2 / AA3 D1 / AB9 F3 / AB3 F2 / AA4 P1 / AF9 N9 / AD9 P9 / AG8 N7 / AE9 R4 / AF8 M6/ AH4/ AD3 M2/ AG6/ AD2 L5/ AH5/ AE6 M1/ AH3/ AE2 L6/ AH6/ AE1 L4/ AG7/ AE5 L3/ AD8/ AE3 L2/ AE8/ AF1 L1 / AF4 K2 / AF3 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 115 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME vout3_d10 vout3_d11 vout3_d12 vout3_d13 vout3_d14 vout3_d15 vout3_d16 vout3_d17 vout3_d18 vout3_d19 vout3_d20 vout3_d21 vout3_d22 vout3_d23 Table 2-5. DSS Signal Descriptions (continued) DESCRIPTION Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output Video Output 3 Data output 2.4.3 Display Subsystem – High-Definition Multimedia Interface (HDMI) www.ti.com TYPE O O O O O O O O O O O O O O BALL J1 / AF6 J2 / AF2 H1 / AG5 J3 / AG3 H2 / AG2 H3 / AG4 R6/ AG8/ AH4 T9/ AD9/ AG6 T6 / AH5 T7 / AH3 P6 / AH6 R9 / AG7 R5 / AD8 P5 / AE8 NOTE For more information, see the Display Subsystem / Display Subsystem Overview of the device TRM. Table 2-6. HDMI Signal Descriptions SIGNAL NAME hdmi1_cec hdmi1_hpd hdmi1_ddc_scl hdmi1_ddc_sda hdmi1_clockx hdmi1_clocky hdmi1_data2x hdmi1_data2y hdmi1_data1x hdmi1_data1y hdmi1_data0x hdmi1_data0y DESCRIPTION HDMI consumer electronic control HDMI display hot plug detect HDMI display data channel clock HDMI display data channel data HDMI clock differential positive or negative HDMI clock differential positive or negative HDMI data 2 differential positive or negative HDMI data 2 differential positive or negative HDMI data 1 differential positive or negative HDMI data 1 differential positive or negative HDMI data 0 differential positive or negative HDMI data 0 differential positive or negative 2.4.4 External Memory Interface (DDR2/DDR3/DDR3L SDRAM) TYPE IOD I IOD IOD ODS ODS ODS ODS ODS ODS ODS ODS BALL B20/ G19 B21/ G20 C25 F17 AG16 AH16 AG19 AH19 AG18 AH18 AG17 AH17 NOTE For more information, see the Memory Subsystem / EMIF Controller section of the device TRM. 116 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 NOTE The index numbers 1 and 2 which are part of the EMIF1 and EMIF2 signal prefixes (ddr1_* and ddr2_*) listed in Table 2-7, DDR2/DDR3/DDR3L SDRAM Signal Descriptions, column "DDR2/DDR3/DDR3L Signal Descriptions" not to be confused with DDR1 and DDR2 types of SDRAM memories. EARLY PRELIMINARY ADVANCE INFORMATION Table 2-7. DDR2/DDR3/DDR3L SDRAM Signal Descriptions SIGNAL NAME DESCRIPTION DDR2/DDR3/DDR3L SDRAM Channel 1 ddr1_csn0 EMIF1 Chip Select 0 ddr1_cke EMIF1 Clock Enable ddr1_ck EMIF1 Clock ddr1_nck EMIF1 Negative Clock ddr1_odt0 EMIF1 On-Die Termination for Chip Select 0 ddr1_casn EMIF1 Column Address Strobe output ddr1_rasn EMIF1 Row Address Strobe output ddr1_wen EMIF1 Write Enable ddr1_rst EMIF1 Reset output (DDR3-SDRAM only) ddr1_ba0 EMIF1 Bank Address outputs ddr1_ba1 EMIF1 Bank Address outputs ddr1_ba2 EMIF1 Bank Address outputs ddr1_a0 EMIF1 Address Bus ddr1_a1 EMIF1 Address Bus ddr1_a2 EMIF1 Address Bus ddr1_a3 EMIF1 Address Bus ddr1_a4 EMIF1 Address Bus ddr1_a5 EMIF1 Address Bus ddr1_a6 EMIF1 Address Bus ddr1_a7 EMIF1 Address Bus ddr1_a8 EMIF1 Address Bus ddr1_a9 EMIF1 Address Bus ddr1_a10 EMIF1 Address Bus ddr1_a11 EMIF1 Address Bus ddr1_a12 EMIF1 Address Bus ddr1_a13 EMIF1 Address Bus ddr1_a14 EMIF1 Address Bus ddr1_a15 EMIF1 Address Bus ddr1_d0 EMIF1 Data Bus ddr1_d1 EMIF1 Data Bus ddr1_d2 EMIF1 Data Bus ddr1_d3 EMIF1 Data Bus ddr1_d4 EMIF1 Data Bus ddr1_d5 EMIF1 Data Bus ddr1_d6 EMIF1 Data Bus ddr1_d7 EMIF1 Data Bus ddr1_d8 EMIF1 Data Bus ddr1_d9 EMIF1 Data Bus ddr1_d10 EMIF1 Data Bus TYPE O O O O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BALL AH23 AG22 AG24 AH24 AE20 AC18 AF20 AH21 AG21 AF17 AE18 AB18 AD20 AC19 AC20 AB19 AF21 AH22 AG23 AE21 AF22 AE22 AD21 AD22 AC21 AF18 AE17 AD18 AF25 AF26 AG26 AH26 AF24 AE24 AF23 AE23 AC23 AF27 AG27 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 117 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 2-7. DDR2/DDR3/DDR3L SDRAM Signal Descriptions (continued) SIGNAL NAME ddr1_d11 ddr1_d12 ddr1_d13 ddr1_d14 ddr1_d15 ddr1_d16 ddr1_d17 ddr1_d18 ddr1_d19 ddr1_d20 ddr1_d21 ddr1_d22 ddr1_d23 ddr1_d24 ddr1_d25 ddr1_d26 ddr1_d27 ddr1_d28 ddr1_d29 ddr1_d30 ddr1_d31 ddr1_ecc_d0 ddr1_ecc_d1 ddr1_ecc_d2 ddr1_ecc_d3 ddr1_ecc_d4 ddr1_ecc_d5 ddr1_ecc_d6 ddr1_ecc_d7 ddr1_dqm0 ddr1_dqm1 ddr1_dqm2 ddr1_dqm3 ddr1_dqm_ecc ddr1_dqs0 ddr1_dqsn0 ddr1_dqs1 ddr1_dqsn1 ddr1_dqs2 ddr1_dqsn2 ddr1_dqs3 ddr1_dqsn3 ddr1_dqs_ecc ddr1_dqsn_ecc DESCRIPTION EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 Data Bus EMIF1 ECC Data Bus (1) EMIF1 ECC Data Bus (1) EMIF1 ECC Data Bus (1) EMIF1 ECC Data Bus (1) EMIF1 ECC Data Bus (1) EMIF1 ECC Data Bus (1) EMIF1 ECC Data Bus (1) EMIF1 ECC Data Bus (1) EMIF1 Data Mask outputs EMIF1 Data Mask outputs EMIF1 Data Mask outputs EMIF1 Data Mask outputs EMIF1 ECC Data Mask outputs Data strobe 0 input/outputs for byte 0 of the 32-bit data bus. These signals are outputs to the EMIF1 memory when writing and inputs when reading. Data strobe 0 invert Data strobe 1 input/outputs for byte 1 of the 32-bit data bus. These signals are outputs to the EMIF1 memory when writing and inputs when reading. Data strobe 1 invert Data strobe 2 input/outputs for byte 2 of the 32-bit data bus. These signals are outputs to the EMIF1 memory when writing and inputs when reading. Data strobe 2 invert Data strobe 3 input/outputs for byte 3 of the 32-bit data bus. These signals are outputs to the EMIF1 memory when writing and inputs when reading. Data strobe 3 invert EMIF1 ECC Data strobe input/output. These signals are outputs to the EMIF1 memory when writing and inputs when reading. EMIF1 ECC Complementary Data strobe TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BALL AF28 AE26 AC25 AC24 AD25 V20 W20 AB28 AC28 AC27 Y19 AB27 Y20 AA23 Y22 Y23 AA24 Y24 AA26 AA25 AA28 W22 V23 W19 W23 Y25 V24 V25 Y26 AD23 AB23 AC26 AA27 V26 AH25 AG25 AE27 AE28 AD27 AD28 Y28 Y27 V27 V28 118 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-7. DDR2/DDR3/DDR3L SDRAM Signal Descriptions (continued) SIGNAL NAME DESCRIPTION ddr1_vref0 Reference Power Supply EMIF1 DDR2/DDR3/DDR3L SDRAM Channel 2 ddr2_csn0 EMIF2 Chip Select 0 ddr2_cke EMIF2 Clock Enable ddr2_ck EMIF2 Clock ddr2_nck EMIF2 Negative Clock ddr2_odt0 EMIF2 On-Die Termination for Chip Select 0 ddr2_casn EMIF2 Column Address Strobe output ddr2_rasn EMIF2 Row Address Strobe output ddr2_wen EMIF2 Write Enable ddr2_rst EMIF2 Reset output (DDR3-SDRAM only) ddr2_ba0 EMIF2 Bank Address outputs ddr2_ba1 EMIF2 Bank Address outputs ddr2_ba2 EMIF2 Bank Address outputs ddr2_a0 EMIF2 Address Bus ddr2_a1 EMIF2 Address Bus ddr2_a2 EMIF2 Address Bus ddr2_a3 EMIF2 Address Bus ddr2_a4 EMIF2 Address Bus ddr2_a5 EMIF2 Address Bus ddr2_a6 EMIF2 Address Bus ddr2_a7 EMIF2 Address Bus ddr2_a8 EMIF2 Address Bus ddr2_a9 EMIF2 Address Bus ddr2_a10 EMIF2 Address Bus ddr2_a11 EMIF2 Address Bus ddr2_a12 EMIF2 Address Bus ddr2_a13 EMIF2 Address Bus ddr2_a14 EMIF2 Address Bus ddr2_a15 EMIF2 Address Bus ddr2_d0 EMIF2 Data Bus ddr2_d1 EMIF2 Data Bus ddr2_d2 EMIF2 Data Bus ddr2_d3 EMIF2 Data Bus ddr2_d4 EMIF2 Data Bus ddr2_d5 EMIF2 Data Bus ddr2_d6 EMIF2 Data Bus ddr2_d7 EMIF2 Data Bus ddr2_d8 EMIF2 Data Bus ddr2_d9 EMIF2 Data Bus ddr2_d10 EMIF2 Data Bus ddr2_d11 EMIF2 Data Bus ddr2_d12 EMIF2 Data Bus ddr2_d13 EMIF2 Data Bus ddr2_d14 EMIF2 Data Bus ddr2_d15 EMIF2 Data Bus ddr2_d16 EMIF2 Data Bus TYPE A O O O O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BALL Y18 P24 U24 T28 T27 R23 U28 T23 U25 R24 U23 U27 U26 R25 R26 R28 R27 P23 P22 P25 N20 P27 N27 N23 P26 N28 T22 R22 U22 E26 G25 F25 F24 F26 F27 E27 E28 H23 H25 H24 H26 G26 J25 J26 J24 L22 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 119 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 2-7. DDR2/DDR3/DDR3L SDRAM Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL ddr2_d17 EMIF2 Data Bus I/O K20 ddr2_d18 EMIF2 Data Bus I/O K21 ddr2_d19 EMIF2 Data Bus I/O L23 ddr2_d20 EMIF2 Data Bus I/O L24 ddr2_d21 EMIF2 Data Bus I/O J23 ddr2_d22 EMIF2 Data Bus I/O K22 ddr2_d23 EMIF2 Data Bus I/O J20 ddr2_d24 EMIF2 Data Bus I/O L27 ddr2_d25 EMIF2 Data Bus I/O L26 ddr2_d26 EMIF2 Data Bus I/O L25 ddr2_d27 EMIF2 Data Bus I/O L28 ddr2_d28 EMIF2 Data Bus I/O M23 ddr2_d29 EMIF2 Data Bus I/O M24 ddr2_d30 EMIF2 Data Bus I/O M25 ddr2_d31 EMIF2 Data Bus I/O M26 ddr2_dqm0 EMIF2 Data Mask outputs O F28 ddr2_dqm1 EMIF2 Data Mask outputs O G24 ddr2_dqm2 EMIF2 Data Mask outputs O K23 ddr2_dqm3 EMIF2 Data Mask outputs O M22 ddr2_dqs0 Data strobe 0 input/outputs for byte 0 of the 32-bit data bus. These signals are outputs I/O G28 to the EMIF2 memory when writing and inputs when reading. ddr2_dqsn0 Data strobe 0 invert I/O G27 ddr2_dqs1 Data strobe 1 input/outputs for byte 1 of the 32-bit data bus. These signals are outputs I/O H27 to the EMIF2 memory when writing and inputs when reading. ddr2_dqsn1 Data strobe 1 invert I/O H28 ddr2_dqs2 Data strobe 2 input/outputs for byte 2 of the 32-bit data bus. These signals are outputs I/O K27 to the EMIF2 memory when writing and inputs when reading. ddr2_dqsn2 Data strobe 2 invert I/O K28 ddr2_dqs3 Data strobe 3 input/outputs for byte 3 of the 32-bit data bus. These signals are outputs I/O M28 to the EMIF2 memory when writing and inputs when reading. ddr2_dqsn3 Data strobe 3 invert I/O M27 ddr2_vref0 Reference Power Supply EMIF2 A N22 (1) The ECC module (EMIF1 ECC Data Bus in Table 2-4 ) signal sets are NOT supported in the DRA74x device. For more details on the device differentiation, refer to the Table 1-1, Device Comparison in the Section 1, Introduction. 2.4.5 General-Purpose Memory Controller (GPMC) NOTE For more information, see the Memory Subsystem / General-Purpose Memory Controller section of the device TRM. SIGNAL NAME gpmc_ad0 gpmc_ad1 gpmc_ad2 Table 2-8. GPMC Signal Descriptions DESCRIPTION GPMC Data 0 in A/D non-multiplexed mode and additinaly Address 1 in A/D multiplexed mode GPMC Data 1 in A/D non-multiplexed mode and additinaly Address 2 in A/D multiplexed mode GPMC Data 2 in A/D non-multiplexed mode and additinaly Address 3 in A/D multiplexed mode TYPE I/O I/O I/O BALL M6 M2 L5 120 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SIGNAL NAME gpmc_ad3 gpmc_ad4 gpmc_ad5 gpmc_ad6 gpmc_ad7 gpmc_ad8 gpmc_ad9 gpmc_ad10 gpmc_ad11 gpmc_ad12 gpmc_ad13 gpmc_ad14 gpmc_ad15 gpmc_a0 gpmc_a1 gpmc_a2 gpmc_a3 gpmc_a4 gpmc_a5 gpmc_a6 gpmc_a7 gpmc_a8 gpmc_a9 gpmc_a10 gpmc_a11 gpmc_a12 gpmc_a13 gpmc_a14 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-8. GPMC Signal Descriptions (continued) DESCRIPTION GPMC Data 3 in A/D non-multiplexed mode and additinaly Address 4 in A/D multiplexed mode GPMC Data 4 in A/D non-multiplexed mode and additinaly Address 5 in A/D multiplexed mode GPMC Data 5 in A/D non-multiplexed mode and additinaly Address 6 in A/D multiplexed mode GPMC Data 6 in A/D non-multiplexed mode and additinaly Address 7 in A/D multiplexed mode GPMC Data 7 in A/D non-multiplexed mode and additinaly Address 8 in A/D multiplexed mode GPMC Data 8 in A/D non-multiplexed mode and additinaly Address 9 in A/D multiplexed mode GPMC Data 9 in A/D non-multiplexed mode and additinaly Address 10 in A/D multiplexed mode GPMC Data 10 in A/D non-multiplexed mode and additinaly Address 11 in A/D multiplexed mode GPMC Data 11 in A/D non-multiplexed mode and additinaly Address 12 in A/D multiplexed mode GPMC Data 12 in A/D non-multiplexed mode and additinaly Address 13 in A/D multiplexed mode GPMC Data 13 in A/D non-multiplexed mode and additinaly Address 14 in A/D multiplexed mode GPMC Data 14 in A/D non-multiplexed mode and additinaly Address 15 in A/D multiplexed mode GPMC Data 15 in A/D non-multiplexed mode and additinaly Address 16 in A/D multiplexed mode GPMC Address 0. Only used to effectively address 8-bit data nonmultiplexed memories GPMC address 1 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 2 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 3 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 4 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 5 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 6 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 7 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 8 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 9 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 10 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 11 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 12 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 13 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 14 in A/D non-multiplexed mode and unused in A/D multiplexed mode TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O BALL M1 L6 L4 L3 L2 L1 K2 J1 J2 H1 J3 H2 H3 R6 / P4 T9 / P1 T6 / N1 T7 / M4 P6 R9 R5 P5 N7 R4 N9 P9 P4 R3 / K7 T2 / M7 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 121 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME gpmc_a15 gpmc_a16 gpmc_a17 gpmc_a18 gpmc_a19 gpmc_a20 gpmc_a21 gpmc_a22 gpmc_a23 gpmc_a24 gpmc_a25 gpmc_a26 gpmc_a27 gpmc_cs0 gpmc_cs1 gpmc_cs2 gpmc_cs3 gpmc_cs4 gpmc_cs5 gpmc_cs6 gpmc_cs7 gpmc_clk gpmc_advn_ale gpmc_oen_ren gpmc_wen gpmc_ben0 gpmc_ben1 gpmc_wait0 gpmc_wait1 Table 2-8. GPMC Signal Descriptions (continued) DESCRIPTION GPMC address 15 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC address 16 in A/D non-multiplexed mode and Address 17 in A/D multiplexed mode GPMC address 17 in A/D non-multiplexed mode and Address 18 in A/D multiplexed mode GPMC address 18 in A/D non-multiplexed mode and Address 19 in A/D multiplexed mode GPMC address 19 in A/D non-multiplexed mode and Address 20 in A/D multiplexed mode GPMC address 20 in A/D non-multiplexed mode and Address 21 in A/D multiplexed mode GPMC address 21 in A/D non-multiplexed mode and Address 22 in A/D multiplexed mode GPMC address 22 in A/D non-multiplexed mode and Address 23 in A/D multiplexed mode GPMC address 23 in A/D non-multiplexed mode and Address 24 in A/D multiplexed mode GPMC address 24 in A/D non-multiplexed mode and Address 25 in A/D multiplexed mode GPMC address 25 in A/D non-multiplexed mode and Address 26 in A/D multiplexed mode GPMC address 26 in A/D non-multiplexed mode and Address 27 in A/D multiplexed mode GPMC address 27 in A/D non-multiplexed mode and unused in A/D multiplexed mode GPMC Chip Select 0 (active low) GPMC Chip Select 1 (active low) GPMC Chip Select 2 (active low) GPMC Chip Select 3 (active low) GPMC Chip Select 4 (active low) GPMC Chip Select 5 (active low) GPMC Chip Select 6 (active low) GPMC Chip Select 7 (active low) GPMC Clock output GPMC address valid active low or address latch enable GPMC output enable active low or read enable GPMC write enable active low GPMC lower-byte enable active low GPMC upper-byte enable active low GPMC external indication of wait 0 GPMC external indication of wait 1 TYPE O O O O O O O O O O O O O O O O O O O O O I/O O O O O O I I 2.4.6 Timers NOTE For more information, see the Timers section of the device TRM. www.ti.com BALL U2 / J5 U1 / K6 P3 / J7 R2 / J4 K7 / J6 M7 / H4 J5 / H5 K6 / H6 J7/ AG5/ N1 J4 / AF2 J6 / AF6 H4 / AF3 H5 / AF4 T1 H6 P2 P1 N6 M4 N1 P7 P7 N1 M5 M3 N6 M4 N2 P7 / N1 122 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-9. Timers Signal Descriptions SIGNAL NAME timer1 timer2 timer3 timer4 timer5 timer6 timer7 timer8 timer9 timer10 timer11 timer12 timer13 timer14 timer15 timer16 DESCRIPTION PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input PWM output/event trigger input TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BALL M4 / E21 N6 / F20 N1 / F21 P7 / D12 U2 / B12 T2 / A11 R3 / B13 P4 / A12 P9 / E14 N9 / A13 R4 / G14 N7 / F14 D18 / AF8 E17 / AE9 B26/ AF9/ AC10 C23/ AD9/ AB10 2.4.7 Inter Integrated Circuit Interface (I2C) NOTE For more information, see the Serial Communication Interface / Multimaster High-Speed I2C Controller / HS I2C Environment / HS I2C in I2C Mode section of the device TRM. NOTE I2C1 and I2C2 do NOT support HS-mode. SIGNAL NAME DESCRIPTION Inter-Integrated Circuit Interface (I2C1) i2c1_scl I2C1 Clock I/O i2c1_sda I2C1 Data I/O Inter-Integrated Circuit Interface (I2C2) i2c2_scl I2C2 Clock I/O i2c2_sda I2C2 Data I/O Inter-Integrated Circuit Interface (I2C3) i2c3_scl I2C3 Clock I/O i2c3_sda I2C3 Data I/O Inter-Integrated Circuit Interface (I2C4) i2c4_scl I2C4 Clock I/O i2c4_sda I2C4] Data I/O Inter-Integrated Circuit Interface (I2C5) i2c5_scl I2C5 Clock I/O i2c5_sda I2C5 Data I/O Table 2-10. I2C Signal Descriptions TYPE BALL IOD C20 IOD C21 IOD F17 IOD C25 IOD P7/ D14/ AB4/ F20 IOD N1/ C14/ AC5/ E21 IOD R6/ J14/ A21/ Y9 IOD T9/ B14/ C18/ W7 IOD AB9/ P6/ F12 IOD AA3/ R9/ G12 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 123 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 2.4.8 HDQ / 1-Wire Interface (HDQ1W) www.ti.com NOTE For more information, see the Serial Communication Interface / HDQ/1-Wire section of the device TRM. Table 2-11. HDQ / 1-Wire Signal Descriptions SIGNAL NAME hdq0 DESCRIPTION HDQ or 1-wire protocol single interface pin 2.4.9 Universal Asynchronous Receiver Transmitter (UART) TYPE IOD BALL D18/ C23 NOTE For more information about UART booting, see the Initialization / Device Initialization by ROM Code / Perypheral Booting / Initialization Phase for UART Boot section of the device TRM. Table 2-12. UART Signal Descriptions SIGNAL NAME DESCRIPTION Universal Asynchronous Receiver/Transmitter (UART1) uart1_dcdn UART1 Data Carrier Detect active low uart1_dsrn UART1 Data Set Ready Active Low uart1_dtrn UART1 Data Terminal Ready Active Low uart1_rin UART1 Ring Indicator Input uart1_rxd UART1 Receive Data Input. uart1_txd UART1 Transmit Data Output. uart1_ctsn UART1 clear to send active low uart1_rtsn UART1 request to send active low Universal Asynchronous Receiver/Transmitter (UART2) uart2_rxd UART2 Receive Data Input. uart2_txd UART2 Transmit Data Output. uart2_ctsn UART2 clear to send active low uart2_rtsn UART2 request to send active low Universal Asynchronous Receiver/Transmitter (UART3)/IrDA uart3_rxd UART3 Receive Data Input for both normal UART mode and IrDA mode uart3_txd UART3 Transmit Data Output uart3_ctsn UART3 clear to send active low uart3_rtsn UART3 request to send active low uart3_rctx Remote control data output uart3_sd Infrared transceiver configure/shutdown uart3_irtx Infrared data output Universal Asynchronous Receiver/Transmitter (UART4) uart4_rxd UART4 Receive Data Input. uart4_txd UART4 Transmit Data Output uart4_ctsn UART4 clear to send active low uart4_rtsn UART4 request to send active low Universal Asynchronous Receiver/Transmitter (UART5) TYPE BALL I D28 I D26 O D27 I C28 I B27 O C26 I E25 O C27 I D28 O D26 I D27 O C28 I V2/ AB3/ A26 / D27 O Y1/ AA4/ B22/ C28 I U4/ W9/ G17/ D28 O V1/ V9/ D28/ B24 O D28 O D26 O C28 I V7/ G16/ B21 O U7/ D17/ B20 I V6 O U6 124 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME uart5_rxd Table 2-12. UART Signal Descriptions (continued) DESCRIPTION UART5 Receive Data Input uart5_txd UART5 Transmit Data Output uart5_ctsn UART5 clear to send active low uart5_rtsn UART5 request to send active low Universal Asynchronous Receiver/Transmitter (UART6) uart6_rxd UART6 Receive Data Input uart6_txd UART6 Transmit Data Output uart6_ctsn UART6 clear to send active low uart6_rtsn UART6 request to send active low Universal Asynchronous Receiver/Transmitter (UART7) uart7_rxd UART7 Receive Data Input uart7_txd UART7 Transmit Data Output uart7_ctsn UART7 clear to send active low uart7_rtsn UART7 request to send active low Universal Asynchronous Receiver/Transmitter (UART8) uart8_rxd UART8 Receive Data Input uart8_txd UART8 Transmit Data Output uart8_ctsn UART8 clear to send active low uart8_rtsn UART8 request to send active low Universal Asynchronous Receiver/Transmitter (UART9) uart9_rxd UART9 Receive Data Input uart9_txd UART9 Transmit Data Output uart9_ctsn UART9 clear to send active low uart9_rtsn UART9 request to send active low Universal Asynchronous Receiver/Transmitter (UART10) uart10_rxd UART10 Receive Data Input uart10_txd UART10 Transmit Data Output uart10_ctsn UART10 clear to send active low uart10_rtsn UART10 request to send active low TYPE I O I O BALL R6/ F11/ B19/ AC7/ G17 T9/ G10/ C17/ AC6/ B24 T6 / AC9 T7 / AC3 I P6/ E8/ G12/ W7 O R9/ D9/ F12/ Y9 I R5 / G13 O P5 / J11 I T6/ AD9/ B7/ B18 O T7/ AF9/ B8/ F15 I AE9 / B19 O AF8 / C17 I AE8/ R5/ C18/ G20 O AD8/ P5/ A21/ G19 I AG7 / G16 O AH6 / D17 I G1/ AA3/ E25 O G6/ AB9/ C27 I F2 / AB3 O F3/ AA4 I D1/ E21/ AC8/ D27 O E2/ F20/ AD6/ C28 I D2 / AB8 O F4 / AB5 2.4.10 Multichannel Serial Port Interface (McSPI) NOTE For more information, see the Serial Communication Interface / Multichannel Serial Port Interface (MCSPI) section of the device TRM. Table 2-13. SPI Signal Descriptions SIGNAL NAME DESCRIPTION Serial Peripheral Interface 1 spi1_sclk SPI Clock I/O spi1_d1 SPI Data I/O.Can be configured as either MISO or MOSI. spi1_d0 SPI Data I/O.Can be configured as either MISO or MOSI. spi1_cs0 SPI Chip Select I/O spi1_cs1 SPI Chip Select I/O spi1_cs2 SPI Chip Select I/O Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TYPE BALL I/O A25 I/O F16 I/O B25 I/O A24 I/O A22 I/O B21 Terminal Description 125 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-13. SPI Signal Descriptions (continued) SIGNAL NAME DESCRIPTION spi1_cs3 SPI Chip Select I/O Serial Peripheral Interface 2 spi2_sclk SPI Clock I/O spi2_d1 SPI Data I/O.Can be configured as either MISO or MOSI. spi2_d0 SPI Data I/O.Can be configured as either MISO or MOSI. spi2_cs0 SPI Chip Select I/O spi2_cs1 SPI Chip Select I/O spi2_cs2 SPI Chip Select I/O spi2_cs3 SPI Chip Select I/O Serial Peripheral Interface 3 spi3_sclk SPI Clock I/O spi3_d1 SPI Data I/O.Can be configured as either MISO or MOSI. spi3_d0 SPI Data I/O.Can be configured as either MISO or MOSI. spi3_cs0 SPI Chip Select I/O spi3_cs1 SPI Chip Select I/O spi3_cs2 SPI Chip Select I/O spi3_cs3 SPI Chip Select I/O Serial Peripheral Interface 4 spi4_sclk SPI Clock I/O spi4_d1 SPI Data I/O.Can be configured as either MISO or MOSI. spi4_d0 SPI Data I/O.Can be configured as either MISO or MOSI. spi4_cs0 SPI Chip Select I/O spi4_cs1 spi4_cs2 spi4_cs3 SPI Chip Select I/O SPI Chip Select I/O SPI Chip Select I/O 2.4.11 Quad Serial Port Interface (QSPI) www.ti.com TYPE I/O BALL B20 I/O A26 I/O B22 I/O G17 I/O B24 I/O A22 I/O B21 I/O B20 IO AD9/ V2/ B12/ E11/ AC4/ C18 IO AF9/ Y1/ B10/ A11/ A21/ AC7 IO AE9/ W9/ C11/ B13/ AC6/ G16 IO AF8/ V9/ D11/ A12/ AC9/ D17 IO B11/ AC3/ E14 IO F11 IO A10 IO N7/ G1/ AA3/ V7/ AC8 IO R4/ G6/ AB9/ U7/ AD6 IO N9/ F2/ AB3/ V6/ AB8 IO P9/ F3/ AA4/ U6/ AB5 IO P4 / Y1 IO R3 / W9 IO T2 / V9 NOTE For more information about UART booting, see the Initialization / Device Initialization by ROM Code / Memory Booting / SPI/QSPI Flash Devices section of the device TRM. SIGNAL NAME qspi1_sclk qspi1_rtclk qspi1_d0 qspi1_d1 qspi1_d2 Table 2-14. QSPI Signal Descriptions DESCRIPTION QSPI1 Serial Clock Output QSPI1 Return Clock Input.Must be connected from QSPI1_SCLK on PCB. Refer to PCB Guidelines for QSPI1 QSPI1 Data[0].This pin is output data for all commands/writes and for dual read and quad read modes it becomes input data pin during read phase. QSPI1 Data[1].Input read data in all modes. QSPI1 Data[2].This pin is used only in quad read mode as input data pin during read phase TYPE O I IO I I BALL R2 R3 U1 P3 U2 126 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SIGNAL NAME qspi1_d3 qspi1_cs0 qspi1_cs1 qspi1_cs2 qspi1_cs3 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-14. QSPI Signal Descriptions (continued) DESCRIPTION QSPI1 Data[3].This pin is used only in quad read mode as input data pin during read phase QSPI1 Chip Select[0].This pin is Used for QSPI1 boot modes. QSPI1 Chip Select[1] QSPI1 Chip Select[2] QSPI1 Chip Select[3] TYPE I O O O O BALL T2 P2 P1 T7 P6 2.4.12 Multicannel Audio Serial Port (McASP) NOTE For more information, see the Serial Communication Interface / Multichannel Audio Serial Port (MCASP) section of the device TRM. Table 2-15. MCASP Signal Descriptions SIGNAL NAME DESCRIPTION Multichannel Audio Serial Port 1 mcasp1_axr0 MCASP1 Transmit/Receive Data I/Os mcasp1_axr1 MCASP1 Transmit/Receive Data I/Os mcasp1_axr2 MCASP1 Transmit/Receive Data I/Os mcasp1_axr3 MCASP1 Transmit/Receive Data I/Os mcasp1_axr4 MCASP1 Transmit/Receive Data I/Os mcasp1_axr5 MCASP1 Transmit/Receive Data I/Os mcasp1_axr6 MCASP1 Transmit/Receive Data I/Os mcasp1_axr7 MCASP1 Transmit/Receive Data I/Os mcasp1_axr8 MCASP1 Transmit/Receive Data I/Os mcasp1_axr9 MCASP1 Transmit/Receive Data I/Os mcasp1_axr10 MCASP1 Transmit/Receive Data I/Os mcasp1_axr11 MCASP1 Transmit/Receive Data I/Os mcasp1_axr12 MCASP1 Transmit/Receive Data I/Os mcasp1_axr13 MCASP1 Transmit/Receive Data I/Os mcasp1_axr14 MCASP1 Transmit/Receive Data I/Os mcasp1_axr15 MCASP1 Transmit/Receive Data I/Os mcasp1_fsx MCASP1 Transmit Frame Sync I/O mcasp1_aclkr MCASP1 Receive Bit Clock I/O mcasp1_fsr MCASP1 Receive Frame Sync I/O mcasp1_ahclkx MCASP1 Transmit High-Frequency Master Clock I/O mcasp1_aclkx MCASP1 Transmit Bit Clock I/O Multichannel Audio Serial Port 2 mcasp2_axr0 MCASP2 Transmit/Receive Data I/Os mcasp2_axr1 MCASP2 Transmit/Receive Data I/Os mcasp2_axr2 MCASP2 Transmit/Receive Data I/Os mcasp2_axr3 MCASP2 Transmit/Receive Data I/Os mcasp2_axr4 MCASP2 Transmit/Receive Data I/Os mcasp2_axr5 MCASP2 Transmit/Receive Data I/Os mcasp2_axr6 MCASP2 Transmit/Receive Data I/Os mcasp2_axr7 MCASP2 Transmit/Receive Data I/Os mcasp2_axr8 MCASP2 Transmit/Receive Data I/Os Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TYPE BALL I/O G12 I/O F12 I/O G13 I/O J11 I/O D18/ E12 I/O E17 / F13 I/O B26 / C12 I/O C23 / D12 I/O E21 / B12 I/O F20/ A11 I/O F21 / B13 I/O A12 I/O E14 I/O A13 I/O G14 I/O F14 I/O D14 I/O B14 I/O J14 O D18 I/O C14 I/O B15 I/O A15 I/O C15 I/O A16 I/O D15 I/O B16 I/O B17 I/O A17 I/O D18 Terminal Description 127 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-15. MCASP Signal Descriptions (continued) SIGNAL NAME DESCRIPTION mcasp2_axr9 MCASP2 Transmit/Receive Data I/Os mcasp2_axr10 MCASP2 Transmit/Receive Data I/Os mcasp2_axr11 MCASP2 Transmit/Receive Data I/Os mcasp2_axr12 MCASP2 Transmit/Receive Data I/Os mcasp2_axr13 MCASP2 Transmit/Receive Data I/Os mcasp2_axr14 MCASP2 Transmit/Receive Data I/Os mcasp2_axr15 MCASP2 Transmit/Receive Data I/Os mcasp2_fsx MCASP2 Transmit Frame Sync I/O mcasp2_aclkr MCASP2 Receive Bit Clock I/O mcasp2_fsr MCASP2 Receive Frame Sync I/O mcasp2_ahclkx MCASP2 Transmit High-Frequency Master Clock I/O mcasp2_aclkx MCASP2 Transmit Bit Clock I/O Multichannel Audio Serial Port 3 mcasp3_axr0 MCASP3 Transmit/Receive Data I/Os mcasp3_axr1 MCASP3 Transmit/Receive Data I/Os mcasp3_axr2 MCASP3 Transmit/Receive Data I/Os mcasp3_axr3 MCASP3 Transmit/Receive Data I/Os mcasp3_fsx MCASP3 Transmit Frame Sync I/O mcasp3_ahclkx MCASP3 Transmit High-Frequency Master Clock I/O mcasp3_aclkx MCASP3 Transmit Bit Clock I/O mcasp3_aclkr MCASP3 Receive Bit Clock I/O mcasp3_fsr MCASP3 Receive Frame Sync I/O Multichannel Audio Serial Port 4 mcasp4_axr0 MCASP4 Transmit/Receive Data I/Os mcasp4_axr1 MCASP4 Transmit/Receive Data I/Os mcasp4_axr2 MCASP4 Transmit/Receive Data I/Os mcasp4_axr3 MCASP4 Transmit/Receive Data I/Os mcasp4_fsx MCASP4 Transmit Frame Sync I/O mcasp4_ahclkx MCASP4 Transmit High-Frequency Master Clock I/O mcasp4_aclkx MCASP4 Transmit Bit Clock I/O mcasp4_aclkr MCASP4 Receive Bit Clock I/O mcasp4_fsr MCASP4 Receive Frame Sync I/O Multichannel Audio Serial Port 5 mcasp5_axr0 MCASP5 Transmit/Receive Data I/Os mcasp5_axr1 MCASP5 Transmit/Receive Data I/Os mcasp5_axr2 MCASP5 Transmit/Receive Data I/Os mcasp5_axr3 MCASP5 Transmit/Receive Data I/Os mcasp5_fsx MCASP5 Transmit Frame Sync I/O mcasp5_ahclkx MCASP5 Transmit High-Frequency Master Clock I/O mcasp5_aclkx MCASP5 Transmit Bit Clock I/O mcasp5_aclkr MCASP5 Receive Bit Clock I/O mcasp5_fsr MCASP5 Receive Frame Sync I/O Multichannel Audio Serial Port 6 mcasp6_axr0 MCASP6 Transmit/Receive Data I/Os mcasp6_axr1 MCASP6 Transmit/Receive Data I/Os mcasp6_axr2 MCASP6 Transmit/Receive Data I/Os mcasp6_axr3 MCASP6 Transmit/Receive Data I/Os TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O www.ti.com BALL E17 B26 C23 B18 F15 B19 C17 A18 E15 A20 E17 A19 B19 C17 C15 A16 F15 B26 B18 B18 F15 G16 D17 E12 F13 A21 C23 C18 C18 A21 AB3 AA4 C12 D12 AB9 D18 AA3 AA3 AB9 B12 A11 G13 J11 128 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-15. MCASP Signal Descriptions (continued) SIGNAL NAME DESCRIPTION mcasp6_ahclkx MCASP6 Transmit High-Frequency Master Clock I/O mcasp6_aclkx MCASP6 Transmit Bit Clock I/O mcasp6_fsx MCASP6 Transmit Frame Sync I/O mcasp6_aclkr MCASP6 Receive Bit Clock I/O mcasp6_fsr MCASP6 Receive Frame Sync I/O Multichannel Audio Serial Port 7 mcasp7_axr0 MCASP7 Transmit/Receive Data I/Os mcasp7_axr1 MCASP7 Transmit/Receive Data I/Os mcasp7_axr2 MCASP7 Transmit/Receive Data I/Os mcasp7_axr3 MCASP7 Transmit/Receive Data I/Os mcasp7_ahclkx MCASP7 Transmit High-Frequency Master Clock I/O mcasp7_aclkx MCASP7 Transmit Bit Clock I/O mcasp7_fsx MCASP7 Transmit Frame Sync I/O mcasp7_aclkr MCASP7 Receive Bit Clock I/O mcasp7_fsr MCASP7 Receive Frame Sync I/O Multichannel Audio Serial Port 8 mcasp8_axr0 MCASP8 Transmit/Receive Data I/Os mcasp8_axr1 MCASP8 Transmit/Receive Data I/Os mcasp8_axr2 MCASP8 Transmit/Receive Data I/Os mcasp8_axr3 MCASP8 Transmit/Receive Data I/Os mcasp8_ahclkx MCASP8 Transmit High-Frequency Master Clock I/O mcasp8_aclkx MCASP8 Transmit Bit Clock I/O mcasp8_fsx MCASP7 Transmit Frame Sync I/O mcasp8_aclkr MCASP8 Receive Bit Clock I/O mcasp8_fsr MCASP8 Receive Frame Sync I/O TYPE O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O BALL E17 B13 A12 B13 A12 E14 A13 B14 J14 B26 G14 F14 G14 F14 D15 B16 E15 A20 C23 B17 A17 B17 A17 2.4.13 Universal Serial Bus (USB) NOTE For more information, see: Serial Communication Interface / SuperSpeed USB DRD Subsystem section of the device TRM. Table 2-16. Universal Serial Bus Signal Descriptions SIGNAL NAME DESCRIPTION Universal Serial Bus 1 usb1_dp USB1 USB2.0 differential signal pair (positive) usb1_dm USB1 USB2.0 differential signal pair (negative) usb1_drvvbus USB1 Drive VBUS signal usb_rxn0 USB1 USB3.0 receiver negative lane usb_rxp0 USB1 USB3.0 receiver positive lane usb_txn0 USB1 USB3.0 transmitter negative lane usb_txp0 USB1 USB3.0 transmitter positive lane Universal Serial Bus 2 usb2_dp USB2 USB2.0 differential signal pair (positive) usb2_dm USB2 USB2.0 differential signal pair (negative) usb2_drvvbus USB2 Drive VBUS signal TYPE I/O I/O O I I O O I/O I/O O BALL AD12 AC12 AB10 AF12 AE12 AC11 AD11 AE11 AF11 AC10 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 129 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 2-16. Universal Serial Bus Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL Universal Serial Bus 3 usb3_ulpi_d0 USB3 - ULPI 8-bit data bus I/O AC3 / AE1 usb3_ulpi_d1 USB3 - ULPI 8-bit data bus I/O AC9 / AE5 usb3_ulpi_d2 USB3 - ULPI 8-bit data bus I/O AC6 / AE3 usb3_ulpi_d3 USB3 - ULPI 8-bit data bus I/O AC7 / AF1 usb3_ulpi_d4 USB3 - ULPI 8-bit data bus I/O AC4 / AF4 usb3_ulpi_d5 USB3 - ULPI 8-bit data bus I/O AD4 / AF3 usb3_ulpi_d6 USB3 - ULPI 8-bit data bus I/O AB4 / AF6 usb3_ulpi_d7 USB3 - ULPI 8-bit data bus I/O AC5 / AF2 usb3_ulpi_nxt USB3 - ULPI next I AC8 / AE2 usb3_ulpi_dir USB3 - ULPI bus direction I AD6 / AE6 usb3_ulpi_stp USB3 - ULPI stop O AB8 / AD2 usb3_ulpi_clk USB3 - ULPI functional clock I AB5 / AD3 Universal Serial Bus 4 usb4_ulpi_d0 USB4 - ULPI 8-bit data bus (1) I/O V6 usb4_ulpi_d1 USB4 - ULPI 8-bit data bus (1) I/O U6 usb4_ulpi_d2 USB4 - ULPI 8-bit data bus (1) I/O U5 usb4_ulpi_d3 USB4 - ULPI 8-bit data bus (1) I/O V5 usb4_ulpi_d4 USB4 - ULPI 8-bit data bus (1) I/O V4 usb4_ulpi_d5 USB4 - ULPI 8-bit data bus (1) I/O V3 usb4_ulpi_d6 USB4 - ULPI 8-bit data bus (1) I/O Y2 usb4_ulpi_d7 USB4 - ULPI 8-bit data bus (1) I/O W2 usb4_ulpi_nxt USB4 - ULPI next (1) I U7 usb4_ulpi_dir USB4 - ULPI bus direction (1) I V7 usb4_ulpi_stp USB4 - ULPI stop (1) O V9 usb4_ulpi_clk USB4 - ULPI functional clock (1) I W9 (1) USB4 will not be supported on some pin-compatible roadmap devices. USB3 will be mapped to these balls instead. Pin compatibility can be maintained in the future by either not using USB4, or via software change to use USB4 on this device, but USB3 on these balls in the future. 2.4.14 SATA NOTE For more information, see the Serial Communication Interfaces / SATA section of the device TRM. SIGNAL NAME sata1_rxn0 sata1_rxp0 sata1_txn0 sata1_txp0 sata1_led Table 2-17. SATA Signal Descriptions DESCRIPTION SATA differential negative receiver lane 0 SATA differential positive receiver lane 0 SATA differential negative transmitter lane 0 SATA differential positive transmitter lane 0 SATA channel activity indicator TYPE IOS IOS ODS ODS O BALL AH9 AG9 AG10 AH10 A22 / G19 130 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 2.4.15 Peripheral Component Interconnect Express (PCIe) NOTE For more information, see the Serial Communication Interfaces / PCIe Controllers and the Shared PHY Component Subsystems / PCIe Shared PHY Susbsytem sections of the device TRM. NOTE In the DRA74x device, the PCIe_SS2 controller is NOT available, and the PCIe_SS1 controller supports only a single lane. The PCIe2_PHY interface signal set (pcie_rxn1/rxp1, pcie_txn1/txp1 in Table 2-18) is NOT supported in the DRA74x device. For more details on the device differentiation, refer to the Table 1-1, Device Comparison in the Section 1, Introduction. Table 2-18. PCIe Signal Descriptions SIGNAL NAME DESCRIPTION pcie_rxn0 PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only. pcie_rxp0 PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only. pcie_txn0 PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only. pcie_txp0 PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only. pcie_rxn1(1) PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) pcie_rxp1(1) PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) pcie_txn1(1) PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) pcie_txp1(1) PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) ljcb_clkp PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair (negative) ljcb_clkn PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair (positive) (1) This is not applicable for DRA74x devices. TYPE IOS IOS ODS ODS IOS IOS ODS ODS IODS IODS 2.4.16 Describes the Controller Area Network Interface (DCAN) BALL AG13 AH13 AG14 AH14 AG11 AH11 AG12 AH12 AG15 AH15 NOTE For more information, see the Serial Communication Interface / DCAN section of the device TRM. SIGNAL NAME DCAN 1 dcan1_tx dcan1_rx DCAN 2 dcan2_tx dcan2_rx DESCRIPTION Table 2-19. DCAN Signal Descriptions DCAN1 transmit data pin DCAN1 receive data pin DCAN2 transmit data pin DCAN2 receive data pin TYPE BALL I/O G20 I/O G19 / AD17 I/O E21/ B21 I/O F20/ AC17/ B20 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 131 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 2.4.17 Ethernet Interface (GMAC_SW) www.ti.com NOTE For more information, see the Serial Communication Interfaces / Ethernet Controller section of the device TRM. EARLY PRELIMINARY ADVANCE INFORMATION Table 2-20. GMAC Signal Descriptions SIGNAL NAME rgmii0_txc rgmii0_txctl rgmii0_txd3 rgmii0_txd2 rgmii0_txd1 rgmii0_txd0 rgmii0_rxc rgmii0_rxctl rgmii0_rxd3 rgmii0_rxd2 rgmii0_rxd1 rgmii0_rxd0 rgmii1_txc rgmii1_txctl rgmii1_txd3 rgmii1_txd2 rgmii1_txd1 rgmii1_txd0 rgmii1_rxc rgmii1_rxctl rgmii1_rxd3 rgmii1_rxd2 rgmii1_rxd1 rgmii1_rxd0 mii1_rxd1 mii1_rxd2 mii1_rxd3 mii1_rxd0 mii1_rxclk mii1_rxdv mii1_txclk mii1_txd0 mii1_txd1 mii1_txd2 mii1_txd3 mii1_txer mii1_rxer mii1_col mii1_crs mii1_txen mii0_rxd1 DESCRIPTION RGMII0 Transmit Clock RGMII0 Transmit Enable RGMII0 Transmit Data RGMII0 Transmit Data RGMII0 Transmit Data RGMII0 Transmit Data RGMII0 Receive Clock RGMII0 Receive Control RGMII0 Receive Data RGMII0 Receive Data RGMII0 Receive Data RGMII0 Receive Data RGMII1 Transmit Clock RGMII1 Transmit Enable RGMII1 Transmit Data RGMII1 Transmit Data RGMII1 Transmit Data RGMII1 Transmit Data RGMII1 Receive Clock RGMII1 Receive Control RGMII1Receive Data RGMII1 Receive Data RGMII1 Receive Data RGMII1 Receive Data MII1 Receive Data MII1 Receive Data MII1 Receive Data MII1 Receive Data MII1 Receive Clock MII1 Receive Data Valid input MII1 Transmit Clock MII1 Transmit Data MII1 Transmit Data MII1 Transmit Data MII1 Transmit Data MII1 Transmit Error MII1 Receive Data Error input MII1 Collision Detect (Sense) input MII1 Carrier Sense input MII1 Transmit Data Enable Output MII0 Receive Data TYPE O O O O O O I I I I I I O O O O O O I I I I I I I I I I I I I O O O O I I I I O I BALL W9 V9 V7 U7 V6 U6 U5 V5 V4 V3 Y2 W2 D5 C2 C3 C4 B2 D6 C5 A3 B3 B4 B5 A4 C1 E4 F5 E6 D5 C2 C3 C4 B2 D6 C5 A3 B3 B4 B5 A4 V6 132 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME mii0_rxd2 mii0_rxd3 mii0_rxd0 mii0_rxclk mii0_rxdv mii0_txclk mii0_txd0 mii0_txd1 mii0_txd2 mii0_txd3 mii0_txer mii0_rxer mii0_col mii0_crs mii0_txen rmii1_crs rmii1_rxer rmii1_rxd1 rmii1_rxd0 rmii1_txen rmii1_txd1 rmii1_txd0 rmii0_crs rmii0_rxer rmii0_rxd1 rmii0_rxd0 rmii0_txen rmii0_txd1 rmii0_txd0 mdio_mclk mdio_d Table 2-20. GMAC Signal Descriptions (continued) DESCRIPTION MII0 Receive Data MII0 Receive Data MII0 Receive Data MII0 Receive Clock MII0 Receive Data Valid input MII0 Transmit Clock MII0 Transmit Data MII0 Transmit Data MII0 Transmit Data MII0 Transmit Data MII0 Transmit Error MII0 Receive Data Error input MII0 Collision Detect (Sense) input MII0 Carrier Sense input MII0 Transmit Data Enable Output RMII1 Carrier Sense input RMII1 Receive Data Error input RMII1 Receive Data RMII1 Receive Data RMII1 Transmit Data Enable output RMII1 Transmit Data RMII1 Transmit Data RMII0 Carrier Sense input RMII0 Receive Data Error input RMII0 Receive Data RMII0 Receive Data RMII0 Transmit Data Enable output RMII0 Transmit Data RMII0 Transmit Data Management Data Serial Clock output Management Data I/O TYPE I I I I I I O O O O I I I I O I I I I O O O I I I I O O O IO IO BALL V9 W9 U6 Y1 V2 U5 W2 Y2 V4 V5 U4 U7 V1 V7 V3 V2 Y1 W9 V9 U5 V5 V4 V7 U7 V6 U6 V3 Y2 W2 AC5 / V1 / B21 / D3 AB4 / U4 / B20 / F6 2.4.18 Media Local Bus (MLB) Interface NOTE For more information, see the Serial Communication Interface / Media Local Bus (MLB) section of the device TRM. SIGNAL NAME mlb_sig mlb_dat mlb_clk mlbp_sig_p mlbp_sig_n Table 2-21. MLB Signal Descriptions DESCRIPTION Media Local Bus Subsystem (MLBSS) signal input and output Media Local Bus Subsystem (MLBSS) data input and output Media Local Bus Subsystem (MLBSS) clock input Media Local Bus Subsystem (MLBSS) signal input and output differential pair (positive) Media Local Bus Subsystem (MLBSS) signal input and output differential pair (negative) Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TYPE IO IO I IODS IODS BALL AB3 AA4 AA3 AC1 AC2 Terminal Description 133 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME mlbp_dat_p mlbp_dat_n mlbp_clk_p mlbp_clk_n Table 2-21. MLB Signal Descriptions (continued) DESCRIPTION Media Local Bus Subsystem (MLBSS) data input and output differential pair (positive) Media Local Bus Subsystem (MLBSS) data input and output differential pair (negative) Media Local Bus Subsystem (MLBSS) clock input differential pair (positive) Media Local Bus Subsystem (MLBSS) clock input differential pair (negative) 2.4.19 eMMC/SD/SDIO TYPE IODS IODS IOS IOS NOTE For more information, see the HS MMC/SDIO section of the device TRM. www.ti.com BALL AA1 AA2 AB1 AB2 ADVANCE INFORMATION Table 2-22. eMMC/SD/SDIO Signal Descriptions SIGNAL NAME Multi Media Card 1 mmc1_clk mmc1_cmd mmc1_sdcd mmc1_sdwp mmc1_dat0 mmc1_dat1 mmc1_dat2 mmc1_dat3 Multi Media Card 2 mmc2_clk mmc2_cmd mmc2_sdcd mmc2_sdwp mmc2_dat0 mmc2_dat1 mmc2_dat2 mmc2_dat3 mmc2_dat4 mmc2_dat5 mmc2_dat6 mmc2_dat7 Multi Media Card 3 mmc3_clk mmc3_cmd mmc3_sdcd mmc3_sdwp mmc3_dat0 mmc3_dat1 mmc3_dat2 mmc3_dat3 mmc3_dat4 mmc3_dat5 DESCRIPTION MMC1 clock MMC1 command MMC1 Card Detect MMC1 Write Protect MMC1 data bit 0 MMC1 data bit 1 MMC1 data bit 2 MMC1 data bit 3 MMC2 clock MMC2 command MMC2 Card Detect MMC2 Write Protect MMC2 data bit 0 MMC2 data bit 1 MMC2 data bit 2 MMC2 data bit 3 MMC2 data bit 4 MMC2 data bit 5 MMC2 data bit 6 MMC2 data bit 7 MMC3 clock MMC3 command MMC3 Card Detect MMC3 Write Protect MMC3 data bit 0 MMC3 data bit 1 MMC3 data bit 2 MMC3 data bit 3 MMC3 data bit 4 MMC3 data bit 5 TYPE O I/O I I I/O I/O I/O I/O O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O O I/O I I I/O I/O I/O I/O I/O I/O BALL W6 Y6 W7 Y9 AA6 Y4 AA5 Y3 J7 H6 G20 G19 J4 J6 H4 H5 K7 M7 J5 K6 AD4 AC4 B21 B20 AC7 AC6 AC9 AC3 AC8 AD6 134 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME mmc3_dat6 mmc3_dat7 Multi Media Card 4 mmc4_sdcd mmc4_sdwp mmc4_clk mmc4_cmd mmc4_dat0 mmc4_dat1 mmc4_dat2 mmc4_dat3 Table 2-22. eMMC/SD/SDIO Signal Descriptions (continued) DESCRIPTION MMC3 data bit 6 MMC3 data bit 7 TYPE I/O I/O MMC4 Card Detect I MMC4 Write Protect I MMC4 clock O MMC4 command I/O MMC4 data bit 0 I/O MMC4 data bit 1 I/O MMC4 data bit 2 I/O MMC4 data bit 3 I/O BALL AB8 AB5 B27 C26 E25 C27 D28 D26 D27 C28 2.4.20 General-Purpose Interface (GPIO) NOTE For more information, see the General-Purpose Interface section of the device TRM. Table 2-23. GPIOs Signal Descriptions SIGNAL NAME GPIO 1 gpio1_0 gpio1_1 gpio1_2 gpio1_3 gpio1_4 gpio1_5 gpio1_6 gpio1_7 gpio1_8 gpio1_9 gpio1_10 gpio1_11 gpio1_12 gpio1_13 gpio1_14 gpio1_15 gpio1_16 gpio1_17 gpio1_18 gpio1_19 gpio1_20 gpio1_21 gpio1_22 gpio1_23 gpio1_24 gpio1_25 DESCRIPTION General-Purpose Input General-Purpose Input General-Purpose Input General-Purpose Input General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) TYPE I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BALL AD17 AC17 AB16 AC16 D15 A17 M6 M2 L5 M1 L6 L4 L3 L2 G20 G19 D27 C28 H1 J3 H2 H3 AC8 AD6 AB8 AB5 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 135 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME gpio1_26 gpio1_27 gpio1_28 gpio1_29 gpio1_30 gpio1_31 GPIO 2 gpio2_0 gpio2_1 gpio2_2 gpio2_3 gpio2_4 gpio2_5 gpio2_6 gpio2_7 gpio2_8 gpio2_9 gpio2_10 gpio2_11 gpio2_12 gpio2_13 gpio2_14 gpio2_15 gpio2_16 gpio2_17 gpio2_18 gpio2_19 gpio2_20 gpio2_21 gpio2_22 gpio2_23 gpio2_24 gpio2_25 gpio2_26 gpio2_27 gpio2_28 gpio2_29 gpio2_30 gpio2_31 GPIO 3 gpio3_0 gpio3_1 gpio3_2 gpio3_3 gpio3_4 gpio3_5 gpio3_6 Table 2-23. GPIOs Signal Descriptions (continued) DESCRIPTION General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O www.ti.com BALL P6 R9 R5 P5 N7 R4 N9 P9 P4 R3 T2 U2 U1 P3 R2 K7 M7 J5 K6 J7 J4 J6 H4 H5 H6 T1 P2 P1 P7 N1 M5 M3 N6 M4 N2 B17 AG8 AH7 AD9 AF9 AE9 AF8 AE8 AD8 AG7 136 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME gpio3_7 gpio3_8 gpio3_9 gpio3_10 gpio3_11 gpio3_12 gpio3_13 gpio3_14 gpio3_15 gpio3_16 gpio3_17 gpio3_18 gpio3_19 gpio3_20 gpio3_21 gpio3_22 gpio3_23 gpio3_24 gpio3_25 gpio3_26 gpio3_27 gpio3_28 gpio3_29 gpio3_30 gpio3_31 GPIO 4 gpio4_0 gpio4_1 gpio4_2 gpio4_3 gpio4_4 gpio4_5 gpio4_6 gpio4_7 gpio4_8 gpio4_9 gpio4_10 gpio4_11 gpio4_12 gpio4_13 gpio4_14 gpio4_15 gpio4_16 gpio4_17 gpio4_18 gpio4_19 gpio4_20 Table 2-23. GPIOs Signal Descriptions (continued) DESCRIPTION General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BALL AH6 AH3 AH5 AG6 AH4 AG4 AG2 AG3 AG5 AF2 AF6 AF3 AF4 AF1 AE3 AE5 AE1 AE2 AE6 AD2 AD3 E1 G2 H7 G1 G6 F2 F3 D1 E2 D2 F4 C1 E4 F5 E6 D3 F6 D5 C2 C3 C4 A12 E14 D11 B10 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 137 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME gpio4_21 gpio4_22 gpio4_23 gpio4_24 gpio4_25 gpio4_26 gpio4_27 gpio4_28 gpio4_29 gpio4_30 gpio4_31 GPIO 5 gpio5_0 gpio5_1 gpio5_2 gpio5_3 gpio5_4 gpio5_5 gpio5_6 gpio5_7 gpio5_8 gpio5_9 gpio5_10 gpio5_11 gpio5_12 gpio5_13 gpio5_14 gpio5_15 gpio5_16 gpio5_17 gpio5_18 gpio5_19 gpio5_20 gpio5_21 gpio5_22 gpio5_23 gpio5_24 gpio5_25 gpio5_26 gpio5_27 gpio5_28 gpio5_29 gpio5_30 gpio5_31 GPIO 6 gpio6_4 gpio6_5 Table 2-23. GPIOs Signal Descriptions (continued) DESCRIPTION General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O www.ti.com BALL B11 C11 E11 B2 D6 C5 A3 B3 B4 B5 A4 B14 J14 G12 F12 G13 J11 E12 F13 C12 D12 B12 A11 B13 B18 F15 V1 U4 U3 V2 Y1 W9 V9 V7 U7 V6 U6 U5 V5 V4 V3 Y2 W2 A13 G14 138 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME gpio6_6 gpio6_7 gpio6_8 gpio6_9 gpio6_10 gpio6_11 gpio6_12 gpio6_13 gpio6_14 gpio6_15 gpio6_16 gpio6_17 gpio6_18 gpio6_19 gpio6_20 gpio6_21 gpio6_22 gpio6_23 gpio6_24 gpio6_25 gpio6_26 gpio6_27 gpio6_28 gpio6_29 gpio6_30 gpio6_31 GPIO 7 gpio7_0 gpio7_1 gpio7_2 gpio7_3 gpio7_4 gpio7_5 gpio7_6 gpio7_7 gpio7_8 gpio7_9 gpio7_10 gpio7_11 gpio7_12 gpio7_13 gpio7_14 gpio7_15 gpio7_16 gpio7_17 gpio7_18 gpio7_19 Table 2-23. GPIOs Signal Descriptions (continued) DESCRIPTION General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BALL F14 B16 C15 A16 AC5 AB4 AB10 AC10 E21 F20 F21 D18 E17 B26 C23 W6 Y6 AA6 Y4 AA5 Y3 W7 Y9 AD4 AC4 AC7 AC6 AC9 AC3 R6 T9 T6 T7 A25 F16 B25 A24 A22 B21 B20 A26 B22 G17 B24 L1 K2 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 139 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME gpio7_22 gpio7_23 gpio7_24 gpio7_25 gpio7_26 gpio7_27 gpio7_28 gpio7_29 gpio7_30 gpio7_31 GPIO 8 gpio8_0 gpio8_1 gpio8_2 gpio8_3 gpio8_4 gpio8_5 gpio8_6 gpio8_7 gpio8_8 gpio8_9 gpio8_10 gpio8_11 gpio8_12 gpio8_13 gpio8_14 gpio8_15 gpio8_16 gpio8_17 gpio8_18 gpio8_19 gpio8_20 gpio8_21 gpio8_22 gpio8_23 gpio8_27 gpio8_28 gpio8_29 gpio8_30 gpio8_31 Table 2-23. GPIOs Signal Descriptions (continued) DESCRIPTION General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) General-Purpose Input/Output (I/O) TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O 2.4.21 Keyboard controller (KBD) NOTE For more information, see Keyboard Controller section of the device TRM. www.ti.com BALL B27 C26 E25 C27 D28 D26 J1 J2 D14 C14 F11 G10 F10 G11 E9 F9 F8 E7 E8 D9 D7 D8 A5 C6 C8 C7 B7 B8 A7 A8 C9 A9 B9 A10 D23 F19 E18 G21 D24 140 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-24. Keyboard Signal Descriptions SIGNAL NAME kbd_row0 kbd_row1 kbd_row2 kbd_row3 kbd_row4 kbd_row5 kbd_row6 kbd_row7 kbd_row8 kbd_col0 kbd_col1 kbd_col2 kbd_col3 kbd_col4 kbd_col5 kbd_col6 kbd_col7 kbd_col8 DESCRIPTION Keypad row 0 Keypad row 1 Keypad row 2 Keypad row 3 Keypad row 4 Keypad row 5 Keypad row 6 Keypad row 7 Keypad row 8 Keypad column 0 Keypad column 1 Keypad column 2 Keypad column 3 Keypad column 4 Keypad column 5 Keypad column 6 Keypad column 7 Keypad column 8 TYPE I I I I I I I I I O O O O O O O O O BALL AD9/ E1 AF9/ G2 AG4/ G1 AG2/ G6 AG3/ F2 AG5/ F3 AF2/ D1 AF6/ F6 AF3/ C2 AF4/ E2 AF1/ D2 AE3/ F4 AE5/ C1 AE1/ E4 AE2/ F5 AE6/ E6 AD2/ D3 AD3/ D5 2.4.22 Pulse Width Modulation (PWM) Interface NOTE For more information, see the Pulse-Width Modulation (PWM) SS section of the device TRM. Table 2-25. PWM Signal Descriptions SIGNAL NAME DESCRIPTION PWMSS1 eQEP1A_in EQEP1 Quadrature Input A eQEP1B_in EQEP1 Quadrature Input B eQEP1_index EQEP1 Index Input eQEP1_strobe EQEP1 Strobe Input ehrpwm1A EHRPWM1 Output A ehrpwm1B EHRPWM1 Output B ehrpwm1_tripzone_in EHRPWM1 Trip Zone Input put eCAP1_in_PWM1_out ECAP1 Capture Iniput / PWM Output ehrpwm1_synci EHRPWM1 Sync Input ehrpwm1_synco EHRPWM0 Sync Output PWMSS2 eQEP2A_in EQEP2 Quadrature Input A eQEP2B_in EQEP2 Quadrature Input B eQEP2_index EQEP2 Index Input eQEP2_strobe EQEP2 Strobe Input ehrpwm2A EHRPWM2 Output A ehrpwm2B EHRPWM2 Output B ehrpwm2_tripzone_in EHRPWM2 Trip Zone Input put Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TYPE BALL I E1 / AD9 I G2 / AF9 IO AE9 / H7 IO G1 / AF8 O AE8 / G6 O AD8 / F2 IO AG7 / F3 IO AH6 / D1 I AH3 / E2 O AH5 / D2 I AG6 / F4 I AH4 / C1 IO AG4 / E4 IO AG2 / F5 O AC5 / E6 O AB4 / D3 IO AD4 / F6 Terminal Description 141 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-25. PWM Signal Descriptions (continued) SIGNAL NAME DESCRIPTION eCAP2_in_PWM2_out ECAP2 Capture Iniput / PWM Output eQEP3A_in EQEP3 Quadrature Input A eQEP3B_in EQEP3 Quadrature Input B eQEP3_index EQEP3 Index Input eQEP3_strobe EQEP3 Strobe Input ehrpwm3A EHRPWM3 Output A ehrpwm3B EHRPWM3 Output B ehrpwm3_tripzone_in EHRPWM3 Trip Zone Input put eCAP3_in_PWM3_out ECAP3 Capture Iniput / PWM Output PWMSS3 2.4.23 Audio Tracking Logic (ATL) TYPE IO I I IO IO O O IO IO NOTE For more information, see the Audio Tracking Logic (ATL) section of the device TRM. www.ti.com BALL AC4 / D5 AC7 / C2 AC6 / C3 AC9 / C4 AC3 / B2 AC8 / D6 AD6 / C5 AB8 / A3 AB5 / B3 ADVANCE INFORMATION Table 2-26. ATL Signal Descriptions SIGNAL NAME DESCRIPTION atl_clk0 Audio Tracking Logic Clock 0 output atl_clk1 Audio Tracking Logic Clock 1 output atl_clk2 Audio Tracking Logic Clock 2 output atl_clk3 Audio Tracking Logic Clock 3 output 2.4.24 Test Interfaces 2.4.24.1 Hardware Debug TYPE O O O O BALL D18 E17 B26 C23 NOTE For more information, see the On-Chip Debug Support / Debug Ports section of the device TRM. Table 2-27. Debug Signal Descriptions SIGNAL NAME tms tdi tdo tclk trstn rtck emu0 emu1 emu2 emu3 emu4 DESCRIPTION JTAG test port mode select input.For proper operation do not oppose the IPU on this ball. JTAG test data input JTAG test port data output JTAG test clock input JTAG test reset JTAG return clock output Emulator pin 0 Emulator pin 1 Emulator pin 2 Emulator pin 3 Emulator pin 4 TYPE IO I O I I O IO IO O O O BALL F18 D23 F19 E20 D20 E18 G21 D24 F10 D7 A7 142 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SIGNAL NAME emu5 emu6 emu7 emu8 emu9 emu10 emu11 emu12 emu13 emu14 emu15 emu16 emu17 emu18 emu19 Table 2-27. Debug Signal Descriptions (continued) DESCRIPTION Emulator pin 5 Emulator pin 6 Emulator pin 7 Emulator pin 8 Emulator pin 9 Emulator pin 10 Emulator pin 11 Emulator pin 12 Emulator pin 13 Emulator pin 14 Emulator pin 15 Emulator pin 16 Emulator pin 17 Emulator pin 18 Emulator pin 19 TYPE O O O O O O O O O O O O O O O BALL E1 / G11 G2 / E9 H7 / F9 G1 / F8 G6 / E7 F2 / D8 F3 / A5 D1 / C6 E2 / C8 D2 / C7 F4 / A8 C1 / C9 E4 / A9 F5 / B9 E6 / A10 2.4.25 System and Miscellaneous 2.4.25.1 Sysboot NOTE For more information, see the Initialization (ROM Code) section of the device TRM. Table 2-28. Sysboot Signal Descriptions SIGNAL NAME sysboot0 sysboot1 sysboot2 sysboot3 sysboot4 sysboot5 sysboot6 sysboot7 sysboot8 sysboot9 sysboot10 sysboot11 sysboot12 DESCRIPTION Boot Mode Configuration 0. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 1. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 2. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 3. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 4. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 5. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 6. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 7. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 8. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 9. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 10. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 11. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 12. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TYPE I I I I I I I I I I I I I BALL M6 M2 L5 M1 L6 L4 L3 L2 L1 K2 J1 J2 H1 Terminal Description 143 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-28. Sysboot Signal Descriptions (continued) SIGNAL NAME sysboot13 sysboot14 sysboot15 DESCRIPTION Boot Mode Configuration 13. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 14. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. Boot Mode Configuration 15. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. TYPE I I I 2.4.25.2 Power, Reset and Clock Menager (PRCM) NOTE For more information, see PRCM section of the device TRM. www.ti.com BALL J3 H2 H3 ADVANCE INFORMATION Table 2-29. PRCM Signal Descriptions SIGNAL NAME DESCRIPTION clkout1 Device Clock output 1. Can be used as a system clock for other devices. clkout2 Device Clock output 2. Can be used as a system clock for other devices. clkout3 Device Clock output 3. Can be used as a system clock for other devices. rstoutn Reset out (Active low).This pin asserts low in response to any global reset condition on the device. resetn Device Reset Input porz Power on Reset (active low).This pin must be asserted low until all device supplies are valid (see reset sequence/requirements) xref_clk0 External Reference Clock 0. For Audio and other Peripherals. xref_clk1 External Reference Clock 1. For Audio and other Peripherals. xref_clk2 External Reference Clock 2. For Audio and other Peripherals. xref_clk3 External Reference Clock 3. For Audio and other Peripherals. xi_osc0 System Oscillator OSC0 Crystal input / LVCMOS clock input.Functions as the input connection to a crystal when the internal oscillator OSC0 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used. xo_osc0 System Oscillator OSC0 Crystal output xi_osc1 Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.Functions as the input connection to a crystal when the internal oscillator OSC1 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used xo_osc1 Auxiliary Oscillator OSC1 Crystal output RMII_MHZ_50_C RMII Reference Clock (50MHz).This pin is an input when external reference is used LK or output when internal reference is used. TYPE O O O O I I I I I I I O I O I/O 2.4.25.3 Real Time Clock (RTC) Interface NOTE For more information, see the Real Time Clock (RTC) SS section of the device TRM. BALL F21 / P7 D18 / N1 C23 F23 E23 F22 D18 E17 B26 C23 AE15 AD15 AC15 AC13 U3 Table 2-30. RTC Signal Descriptions SIGNAL NAME Wakeup0 Wakeup1 Wakeup2 Wakeup3 rtc_porz DESCRIPTION RTC External Wakeup Input 0 RTC External Wakeup Input 1 RTC External Wakeup Input 2 RTC External Wakeup Input 3 RTC Power Domain Power-On Reset Input TYPE I I I I I BALL AD17 AC17 AB16 AC16 AB17 144 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-30. RTC Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL rtc_osc_xi_clkin3 RTC Oscillator Input. Crystal connection to internal RTC oscillator. Functions as an I 2 RTC clock input when an external oscillator is used. AE14 rtc_osc_xo RTC Oscillator Output O AD14 (1)rtc_iso RTC domain isolation signal. I AF14 on_off RTC Power Enable output pin O Y11 (1) This signal must be kept 0 if device power supplies are not valid during RTC mode and 1 during normal operation. This can typically be achieved by connecting rtc_iso to the same signal driving porz (not rtc_porz) 2.4.25.4 System Direct Memory Access (SDMA) NOTE For more information, see the DMA Controllers / System DMA section of the device TRM. Table 2-31. SDMA Signal Descriptions SIGNAL NAME dma_evt1 dma_evt2 dma_evt3 dma_evt4 DESCRIPTION System DMA Event Input 1 System DMA Event Input 2 System DMA Event Input 3 System DMA Event Input 4 2.4.25.5 Interrupt Controllers (INTC) TYPE I I I I NOTE For more information, see the Interrupt Controllers section of the device TRM. BALL P7 / P4 N1 / R3 N6 M4 Table 2-32. INTC Signal Descriptions SIGNAL NAME nmi_dsp sys_nirq2 sys_nirq1 DESCRIPTION Non maskable interrupt input.This pin can be optionally routed to the DSP NMI input or as generic input to the ARM cores. External interrupt event to any device INTC External interrupt event to any device INTC 2.4.25.6 Obserabitily TYPE I I I NOTE For more information, see the Control Module section of the device TRM. BALL D21 AB16 AC16 Table 2-33. Observability Signal Descriptions SIGNAL NAME DESCRIPTION obs0 Observation Output 0 obs1 Observation Output 1 obs2 Observation Output 2 obs3 Observation Output 3 obs4 Observation Output 4 obs5 Observation Output 5 obs6 Observation Output 6 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TYPE O O O O O O O BALL F10 G11 E9 F9 F8 D7 D8 Terminal Description 145 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-33. Observability Signal Descriptions (continued) SIGNAL NAME DESCRIPTION obs7 Observation Output 7 obs8 Observation Output 8 obs9 Observation Output 9 obs10 Observation Output 10 obs11 Observation Output 11 obs12 Observation Output 12 obs13 Observation Output 13 obs14 Observation Output 14 obs15 Observation Output 15 obs16 Observation Output 16 obs17 Observation Output 17 obs18 Observation Output 18 obs19 Observation Output 19 obs20 Observation Output 20 obs21 Observation Output 21 obs22 Observation Output 22 obs23 Observation Output 23 obs24 Observation Output 24 obs25 Observation Output 25 obs26 Observation Output 26 obs27 Observation Output 27 obs28 Observation Output 28 obs29 Observation Output 29 obs30 Observation Output 30 obs31 Observation Output 31 obs_dmarq1 DMA Request External Observation Output 1 obs_dmarq2 DMA Request External Observation Output 2 obs_irq1 IRQ External Observation Output 1 obs_irq2 IRQ External Observation Output 2 TYPE O O O O O O O O O O O O O O O O O O O O O O O O O O O O O 2.4.26 Power Supplies www.ti.com BALL A5 C6 C8 C7 A7 A8 C9 A9 B9 F10 G11 E9 F9 F8 D7 D8 A5 C6 C8 C7 A7 A8 C9 A9 B9 G11 D8 F10 D7 NOTE For more information, see Power, Reset and Clock Management / PRCM Subsystem Environment / External Voltage Inputs section of the device TRM. SIGNAL NAME vdd Table 2-34. Power Supply Signal Descriptions DESCRIPTION Core voltage domain supply TYPE PWR BALL H13/ H14/ J17/ J18/ L7/ L8/ N10/ N13/ P11/ P12/ P13/ R11/ R16/ R19/ T13/ T16/ T19/ U8/ U9/ U13/ U16/ V8/ V16 146 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SIGNAL NAME vss vdd_dspeve vdd_iva vdd_gpu vdd_mpu vdd_rtc vdda_usb1 vssa_usb vdda_usb2 vdda33v_usb1 vdda33v_usb2 vdda_abe_per vdda_ddr vdda_debug vdda_dsp_eve vdda_gmac_core vdda_gpu vdda_hdmi vssa_hdmi vdda_iva vdda_pcie vssa_pcie vdda_pcie0 vdda_pcie1 vdda_sata vssa_sata SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-34. Power Supply Signal Descriptions (continued) DESCRIPTION Ground TYPE GND DSP-EVE voltage domain supply IVA voltage domain supply GPU voltage domain supply MPU voltage domain supply PWR PWR PWR PWR RTC voltage domain supply DPLL_USB and HS USB1 1.8V analog power supply HS USB1 and HS USB2 analog ground HS USB2 1.8V analog power supply HS USB1 3.3V analog power supply. If USB1 is not used, this pin can alternatively be connected to VSS if the following requirements are met: - The usb1_dm/usb1_dp pins are left unconnected - The USB1 PHY is kept powered down HS USB2 3.3V analog power supply. If USB2 is not used, this pin can alternatively be connected to VSS if the following requirements are met: - The usb2_dm/usb2_dp pins are left unconnected - The USB2 PHY is kept powered down DPLL_ABE, DPLL_PER, and PER HSDIVIDER analog power supply DPLL_DDR and DDR HSDIVIDER analog power supply DPLL_DEBUG analog power supply DPLL_DSP and DPLL_EVE analog power supply DPLL_CORE and CORE HSDIVIDER analog power supply DPLL_GPU analog power supply PLL_HDMI and HDMI analog power supply DPLL_HDMI and HDMI PHY analog ground DPLL_IVA analog power supply DPLL_PCIe_REF and PCIe analog power supply PCIe analog ground PCIe ch0 RX/TX analog power supply PCIe ch1 RX/TX analog power supply DPLL_SATA and SATA RX/TX analog power supply SATA analog ground PWR PWR GND PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR GND PWR PWR GND PWR PWR PWR GND BALL A1/ A2/ A6/ A14/ A23/ A28/ B1/ D13/ D19/ E13/ E19/ F1/ F7/ G7/ G8/ G9/ H12/ J12/ J15/ J28/ K1/ K4/ K5/ K15/ K24/ K25/ L13/ L14/ M19/ N14/ N15/ N19/ N24/ N25/ P28/ R1/ R12/ R13/ R15/ R21/ T10/ T11/ T12/ T14/ T15/ T17/ T18/ T21/ U15/ U17/ U20/ U21/ V15/ V17/ W1/ W15/ W24/ W25/ W28/ AA8/ AA9/ AA10/ AA14/ AA15/ AA20/ AB14/ AB20/ AD1/ AD24/ AG1/ AH1/ AH2/ AH8/ AH20/ AH28 J13/ K10/ K11/ K12/ K13/ L10/ L11/ L12/ M10/ M11/ M12/ M13 U18/ U19/ V18/ V19 U11/ U12/ V10/ V11/ V14/ W10/ W11/ W13 K17/ K18/ L15/ L16/ L17/ L18/ L19/ M15/ M16/ M17/ M18/ N17/ N18/ P17/ P18/ R18 AB15 AA13 AB11/ AA11 AB12 AA12 Y12 M14 P16 N11 N12 P15 R14 Y17 AE19 / AD19 R17 W14 AE13 / AD13 AA17 AA16 V13 AE10 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 147 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com SIGNAL NAME vdda_usb3 vssa_usb3 vdda_video vssa_video vdds_mlbp vdda_mpu vdda_osc vssa_osc0 vssa_osc1 vdda_rtc vdds18v vdds18v_ddr1 vdds18v_ddr2 vdds_ddr2 vdds_ddr1 Table 2-34. Power Supply Signal Descriptions (continued) DESCRIPTION DPLL_USB_OTG_SS and USB3.0 RX/TX analog power supply DPLL_USB and USB3.0 RX/TX analog ground DPLL_VIDEO1 and DPLL_VIDEO2 analog power supply DPLL_VIDEO1 and DPLL_VIDEO2 analog ground MLBP IO power supply DPLL_MPU analog power supply HFOSC analog power supply OSC0 analog ground OSC1 analog ground RTC bias and RTC LFOSC analog power supply 1.8V power supply TYPE PWR GND PWR GND PWR PWR PWR GND GND PWR PWR DDR1 bias power supply DDR2 bias power supply DDR2 power supply (1.8V for DDR2 mode / 1.5V for DDR3 mode / 1.35V DDR3L mode) PWR PWR PWR DDR1 power supply (1.8V for DDR2 mode / 1.5V for DDR3 mode / 1.35V DDR3L mode) PWR vddshv5 vddshv1 vddshv10 vddshv11 vddshv2 vddshv3 Dual Voltage (1.8V or 3.3V) power supply for the RTC Power Group pins Dual Voltage (1.8V or 3.3V) power supply for the VIN2 Power Group pins Dual Voltage (1.8V or 3.3V) power supply for the GPMC Power Group pins Dual Voltage (1.8V or 3.3V) power supply for the MMC2 Power Group pins Dual Voltage (1.8V or 3.3V) power supply for the VOUT Power Group pins Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power Group pins vddshv4 vddshv6 vddshv7 vddshv8 vddshv9 (1)cap_vddram_dspeve2 (1)cap_vddram_dspeve1 (1)cap_vbbldo_mpu (1)cap_vddram_core2 Dual Voltage (1.8V or 3.3V) power supply for the MMC4 Power Group pins Dual Voltage (1.8V or 3.3V) power supply for the VIN1 Power Group pins Dual Voltage (1.8V or 3.3V) power supply for the WIFI Power Group pins Dual Voltage (1.8V or 3.3V) power supply for the MMC1 Power Group pins Dual Voltage (1.8V or 3.3V) power supply for the RGMII Power Group pins External capacitor connection for the DSP-EVE SRAM array ldo2 output External capacitor connection for the DSP-EVE SRAM array ldo1 output External capacitor connection for the MPU vbb ldo output External capacitor connection for the Core SRAM array ldo2 output PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR CAP CAP CAP CAP BALL W12 AD10 P14 U14 AA7 / Y7 N16 AE16 / AD16 AF15 AC14 AB13 W17/ W18/ V21/ V22/ T8/ R8/ P8/ N8/ M8/ M9/ H17/ G18 AA18/ AA19/ Y21/ W21 P20/ P21/ N21/ J21/ J22 T24/ T25/ M20/ M21/ L20/ L21/ J27/ H20/ H21/ H22/ G22/ G23/ E24 AH27/ AG20/ AG28/ AD26/ AC22/ AB21/ AB22/ AB24/ AB25/ AA21/ AA22/ W16/ W27 V12 H8/ H9/ G4/ G5/ E3/ E5 T4/ T5/ R7/ R10/ P10/ N4/ N5 K8/ J8 H10/ H11/ E10/ D10/ B6 H15/ H16/ H18/ H19/ G15/ E16/ E22/ D16/ D22/ B23 C24 AF5/ AE7/ AD5/ AD7 AB6 / AB7 Y8 / W8 W4/ W5/ U10 J9 J10 J16 J19 148 Terminal Description Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 2-34. Power Supply Signal Descriptions (continued) SIGNAL NAME (1)cap_vbbldo_dspeve (1)cap_vddram_mpu1 (1)cap_vddram_mpu2 (1)cap_vddram_core1 (1)cap_vddram_core4 (1)cap_vbbldo_iva (1)cap_vddram_iva (1)cap_vddram_gpu (1)cap_vbbldo_gpu (1)cap_vddram_core3 (1)cap_vddram_core5 DESCRIPTION External capacitor connection for the DSP-EVE vbb ldo output External capacitor connection for the MPU SRAM array ldo1 output External capacitor connection for the MPU SRAM array ldo2 output External capacitor connection for the Core SRAM array ldo1 output External capacitor connection for the Core SRAM array ldo4 output External capacitor connection for the IVA vbb ldo output External capacitor connection for the IVA SRAM array ldo output External capacitor connection for the GPU SRAM array ldo output External capacitor connection for the GPU vbb ldo output External capacitor connection for the Core SRAM array ldo3 output External capacitor connection for the Core SRAM array ldo5 output TYPE CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP (1) This pin must always be connected via a 1-uF capacitor to vss. BALL K9 K16 K19 L9 P19 R20 T20 Y13 Y14 Y15 Y16 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Terminal Description 149 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 3 Electrical Characteristics www.ti.com NOTE For more information, see Power, Reset and Clock Management / PRCM Subsystem Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements section of the Device TRM. EARLY PRELIMINARY ADVANCE INFORMATION NOTE The index numbers 1 and 2 which is part of the EMIF1 and EMIF2 signal prefixes (ddr1_* and ddr2_*) listed in Section 2.4.4, DDR2/DDR3/DDR3L SDRAM Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 and DDR2 types of SDRAM memories. 3.1 Absolute Maximum Ratings Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Section 3.2, Recommended Operating Conditions, is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 3-1. Absolute Maximum Rating Over Junction Temperature Range vdd vdd_mpu vdd_gpu vdd_dspeve vdd_iva vdd_rtc vdda_usb1 vdda_usb2 vdda33v_usb1 vdda33v_usb2 vdda_abe_per vdda_ddr vdda_debug vdda_dsp_eve vdda_gmac_core vdda_gpu vdda_hdmi vdda_iva vdda_pcie vdda_pcie0 vdda_pcie1 vdda_sata vdda_usb3 vdda_video PARAMETER(2) Core voltage domain supply MPU power supply GPU voltage domain supply DSP-EVE voltage domain supply IVA voltage domain supply RTC voltage domain supply DPLL_USB and HS USB1 1.8V analog power supply HS USB2 1.8V analog power supply HS USB1 3.3V analog power supply. If USB1 is not used, this pin can alternatively be connected to VSS if the following requirements are met: - The usb1_dm / usb1_dp pins are left unconnected - The USB1 PHY is kept powered down HS USB2 3.3V analog power supply. If USB2 is not used, this pin can alternatively be connected to VSS if the following requirements are met: - The usb2_dm/usb2_dp pins are left unconnected - The USB2 PHY is kept powered down DPLL_ABE, DPLL_PER, and PER HSDIVIDER analog power supply DPLL_DDR and DDR HSDIVIDER analog power supply DPLL_DEBUG analog power supply DPLL_DSP and DPLL_EVE analog power supply DPLL_CORE and CORE HSDIVIDER analog power supply DPLL_GPU analog power supply PLL_HDMI and HDMI analog power supply DPLL_IVA analog power supply DPLL_PCIe_REF and PCIe analog power supply PCIe ch0 RX/TX analog power supply PCIe ch1 RX/TX analog power supply DPLL_SATA and SATA RX/TX analog power supply DPLL_USB_OTG_SS and USB3.0 RX/TX analog power supply DPLL_VIDEO1 and DPLL_VIDEO2 analog power supply MIN TBD TBD TBD TBD TBD TBD TBD TBD TBD MAX TBD TBD TBD TBD TBD TBD TBD TBD TBD UNIT V V V V V V V V V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V TBD TBD V 150 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 3-1. Absolute Maximum Rating Over Junction Temperature Range (continued) PARAMETER(2) MIN MAX UNIT vdds_mlbp MLBP IO power supply TBD TBD V vdda_mpu DPLL_MPU analog power supply TBD TBD V vdda_osc HFOSC analog power supply TBD TBD V vdda_rtc RTC bias and RTC LFOSC analog power supply TBD TBD V vdds18v 1.8V power supply TBD TBD V vdds18v_ddr1 DDR1 bias power supply TBD TBD V vdds18v_ddr2 DDR2 bias power supply TBD TBD V vdds_ddr2 DDR2 power supply (1.8V for DDR2 mode/ 1.5V for DDR3 mode / 1.35V DDR3L mode) TBD TBD V vdds_ddr1 DDR1 power supply (1.8V for DDR2 mode/ 1.5V for DDR3 mode / 1.35V DDR3L mode) TBD TBD V vddshv5 Dual Voltage (1.8V or 3.3V) power supply for the RTC Power Group pins TBD TBD V vddshv1 Dual Voltage (1.8V or 3.3V) power supply for the VIN2 Power Group pins TBD TBD V vddshv10 Dual Voltage (1.8V or 3.3V) power supply for the GPMC Power Group pins TBD TBD V vddshv11 Dual Voltage (1.8V or 3.3V) power supply for the MMC2 Power Group pins TBD TBD V vddshv2 Dual Voltage (1.8V or 3.3V) power supply for the VOUT Power Group pins TBD TBD V vddshv3 Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power Group TBD TBD V pins vddshv4 Dual Voltage (1.8V or 3.3V) power supply for the MMC4 Power Group pins TBD TBD V vddshv6 Dual Voltage (1.8V or 3.3V) power supply for the VIN1 Power Group pins TBD TBD V vddshv7 Dual Voltage (1.8V or 3.3V) power supply for the WIFI Power Group pins TBD TBD V vddshv8 Dual Voltage (1.8V or 3.3V) power supply for the MMC1 Power Group pins TBD TBD V vddshv9 Dual Voltage (1.8V or 3.3V) power supply for the RGMII Power Group pins TBD TBD V ddr1_vref0 DDR1 vref supply TBD TBD V ddr2_vref0 DDR2 vref supply TBD TBD V TJ VESD Absolute junction temperature range ESD stress voltage(1) Automotive HBM (Human Body Model) CDM (Charged Device Model) -40 125 °C TBD V TBD II/OI Iclamp TSTG Current-pulse injection on each I/O pin Clamp current for an input or output Storage temperature range after soldered onto PC Board TBD TBD mA TBD TBD mA TBD TBD °C (1) Electrostatic discharge (ESD) to measure device sensitivity or immunity to damage caused by electrostatic discharges into the device. (2) See I/Os supplied by this power pin in Table 2-2 Ball Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 151 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 3.2 Recommended Operating Conditions The device is used under the recommended operating conditions described in Table 3-2. www.ti.com NOTE Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. Table 3-2. Recommended Operating Conditions PARAMETER DESCRIPTION Input Power Supply Voltage Range vdd Core voltage domain supply Maximum noise (peak-peak) f < 10 MHz f ≥ 10 MHz vdd_mpu Supply voltage range for MPU domain Maximum noise (peak-peak) f < 10 MHz f ≥ 10 MHz vdd_gpu GPU voltage domain supply Maximum noise (peak-peak) f < 10 MHz f ≥ 10 MHz vdd_dspeve DSP-EVE voltage domain supply Maximum noise (peak-peak) f < 10 MHz f ≥ 10 MHz vdd_iva IVA voltage domain supply Maximum noise (peak-peak) f < 10 MHz f ≥ 10 MHz vdd_rtc RTC voltage domain supply Maximum noise (peak-peak) f < 10 MHz f ≥ 10 MHz vdda_usb1 DPLL_USB and HS USB1 1.8V analog power supply Maximum noise (peak-peak) vdda_usb2 HS USB2 1.8V analog power supply Maximum noise (peak-peak) vdda33v_usb1 HS USB1 3.3V analog power supply.If USB1 is not used, this pin can alternatively be connected to VSS if the following requirements are met: - The usb1_dm/usb1_dp pins are left unconnected - The USB1 PHY is kept powered down Maximum noise (peak-peak) vdda33v_usb2 HS USB2 3.3V analog power supply. If USB2 is not used, this pin can alternatively be connected to VSS if the following requirements are met: - The usb2_dm/usb2_dp pins are left unconnected - The USB2 PHY is kept powered down Maximum noise (peak-peak) vdda_abe_per DPLL_ABE, DPLL_PER, and PER HSDIVIDER analog power supply Maximum noise (peak-peak) MIN 1.71 1.71 3.135 3.135 1.71 NOM See Section 3.3 TBD TBD See Section 3.3 TBD TBD See Section 3.3 TBD TBD See Section 3.3 TBD TBD See Section 3.3 TBD TBD See Section 3.3 TBD TBD 1.80 TBD 1.80 TBD 3.3 TBD 3.3 TBD 1.80 TBD MAX 1.89 1.89 3.465 3.465 1.89 UNIT V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax 152 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com PARAMETER vdda_ddr vdda_debug vdda_dsp_eve vdda_gmac_core vdda_gpu vdda_hdmi vdda_iva vdda_pcie vdda_pcie0 vdda_pcie1 vdda_sata vdda_usb3 vdda_video vdds_mlbp vdda_mpu vdda_osc vdda_rtc vdds18v vdds18v_ddr1 vdds18v_ddr2 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 3-2. Recommended Operating Conditions (continued) DESCRIPTION MIN DPLL_DDR and DDR HSDIVIDER analog 1.71 power supply Maximum noise (peak-peak) DPLL_DEBUG analog power supply 1.71 Maximum noise (peak-peak) DPLL_DSP and DPLL_EVE analog power 1.71 supply Maximum noise (peak-peak) DPLL_CORE and CORE HSDIVIDER 1.71 analog power supply Maximum noise (peak-peak) DPLL_GPU analog power supply 1.71 Maximum noise (peak-peak) PLL_HDMI and HDMI analog power supply 1.71 Maximum noise (peak-peak) DPLL_IVA analog power supply 1.71 Maximum noise (peak-peak) DPLL_PCIe_REF and PCIe analog power 1.71 supply Maximum noise (peak-peak) PCIe ch0 RX/TX analog power supply 1.71 Maximum noise (peak-peak) PCIe ch1 RX/TX analog power supply 1.71 Maximum noise (peak-peak) DPLL_SATA and SATA RX/TX analog 1.71 power supply Maximum noise (peak-peak) DPLL_USB_OTG_SS and USB3.0 RX/TX 1.71 analog power supply Maximum noise (peak-peak) DPLL_VIDEO1 and DPLL_VIDEO2 analog 1.71 power supply Maximum noise (peak-peak) MLBP IO power supply 1.71 Maximum noise (peak-peak) DPLL_MPU analog power supply 1.71 Maximum noise (peak-peak) HFOSC analog power supply 1.71 Maximum noise (peak-peak) RTC bias and RTC LFOSC analog power 1.71 supply Maximum noise (peak-peak) 1.8V power supply 1.71 Maximum noise (peak-peak) DDR1 bias power supply 1.71 Maximum noise (peak-peak) DDR2 bias power supply 1.71 Maximum noise (peak-peak) NOM 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD 1.80 TBD MAX 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 1.89 UNIT V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 153 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com PARAMETER vdds_ddr1 vdds_ddr2 vddshv5 vddshv1 vddshv10 vddshv11 vddshv2 vddshv3 vddshv4 vddshv6 Table 3-2. Recommended Operating Conditions (continued) DESCRIPTION DDR1 power supply (1.8V for DDR2 mode / 1.5V for DDR3 mode / 1.35V DDR3L mode) 1.35-V Mode 1.5-V Mode 1.8-V Mode Maximum noise (peak-peak) 1.35-V Mode 1.5-V Mode 1.8-V Mode DDR2 power supply (1.8V for DDR2 mode/ 1.5V for DDR3 mode / 1.35V DDR3L mode) 1.35-V Mode 1.5-V Mode 1.8-V Mode Maximum noise (peak-peak) 1.35-V Mode 1.5-V Mode 1.8-V Mode Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the RTC Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the VIN2 Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the GPMC Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the MMC2 Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the VOUT Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power Group pins 1.8-V Mode 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the MMC4 Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the VIN1 Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode MIN 1.28 1.43 1.71 1.28 1.43 1.71 1.71 3.135 1.71 3.135 1.71 3.135 1.71 3.135 1.71 3.135 1.71 3.135 1.71 3.135 1.71 3.135 NOM 1.35 1.50 1.80 TBD 1.35 1.50 1.80 TBD 1.80 3.30 TBD 1.80 3.30 TBD 1.80 3.30 TBD 1.80 3.30 TBD 1.80 3.30 TBD 1.80 3.30 TBD 1.80 3.30 TBD 1.80 3.30 TBD MAX 1.42 1.57 1.89 1.42 1.57 1.89 1.89 3.465 1.89 3.465 1.89 3.465 1.89 3.465 1.89 3.465 1.89 3.465 1.89 3.465 1.89 3.465 UNIT V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax V mVPPmax 154 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 3-2. Recommended Operating Conditions (continued) PARAMETER DESCRIPTION vddshv7 Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the WIFI Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode vddshv8 Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the MMC1 Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode vddshv9 Dual Voltage (1.8V or 3.3V) 1.8-V Mode power supply for the RGMII Power Group pins 3.3-V Mode Maximum noise (peak-peak) 1.8-V Mode 3.3-V Mode vss Ground supply vssa_hdmi DPLL_HDMI and HDMI PHY analog ground vssa_pcie PCIe analog ground vssa_usb HS USB1 and HS USB2 analog ground vssa_usb3 DPLL_USB and USB3.0 RX/TX analog ground vssa_video DPLL_VIDEO1 and DPLL_VIDEO2 analog ground vssa_osc0 OSC0 analog ground vssa_osc1 OSC1 analog ground TJ(1) Operating junction temperature range Automotive Output Power Supply Voltage Range ddr1_vref0 Reference Power Supply DDR1 ddr2_vref0 Reference Power Supply DDR2 (1) Refer to Power on Hours table Table 3-3 for limitations. MIN 1.71 3.135 1.71 3.135 1.71 3.135 -40 NOM 1.80 3.30 TBD 1.80 3.30 TBD 1.80 3.30 TBD 0 0 0 0 0 0 0 0 0.5*vdds_ddr1 0.5*vdds_ddr2 MAX 1.89 3.465 1.89 3.465 1.89 3.465 125 UNIT V mVPPmax V mVPPmax V mVPPmax V V V V V V V V °C V V Power on Hour (POH) Limits • The information in the section below is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products. • POH is a functional of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH to achieve the same reliability performance. For assessment of alternate use cases, contact your local TI representative. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 155 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 3-3. Power on Hour (POH) Limits IP Duty Cycle Voltage Domain Voltage (V) (max) Frequency (MHz) (max) Tj(°C) POH ARM 70% 30% vdd_mpu vdd_mpu OPP_HIGH Retention 1500 0 Automotive Profile(1) 20000 40% 60% vdd_mpu vdd_mpu OPP_HIGH OPP_HIGH 1500 1000 Automotive Profile(1) 20000 55% 45% vdd_mpu vdd_mpu OPP_HIGH OPP_NOM 1500 1000 Automotive Profile(1) 20000 100% vdd_mpu OPP_HIGH 1176 Automotive Profile(1) 20000 100% vdd_mpu OPP_NOM 1000 Automotive Profile(1) 20000 Others(2) 100% All All Support OPPs TBD TBD (1) Automotive profile is defined as 20000 power on hours with junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C, 10%@125°C. (2) Others covers all other IP's voltage and temperature combinations that are not specified in the table, and are constrained by other sections of this data manual. 3.3 Operating Performance Points This section describes the operating conditions of the device. This section also contains the description of each OPP (operating performance point) for processor clocks and device core clocks. CAUTION The OPP voltage and frequency values may change following the silicon characterization result. Table 3-4 describes the supported operating performance points (OPP) for DRA75x/DRA74x devices. Table 3-4. DRA75x / DRA74x Operating Points OPP_NOM VD_MPU √ VD_DSPEVE √ VD_IVA √ VD_GPU √ VD_CORE √ VD_RTC √ (1) Supported only on DRA746/DRA756 devices. OPP_OD √ √ √ √ OPP_HIGH √(1) √ √(1) NOTE All points supported at TBD temperature junction. 3.3.1 Microprocessor Unit (MPU) Voltage And Clock Specifications Table 3-5 shows the recommended MPU voltage domain. 156 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 3-5. MPU Voltage Domain (1) DOMAIN CONDITION OPP_NOM OPP_OD OPP_HIGH MIN (3) NOM (2) MAX (3) MIN (3) NOM (2) MAX (3) MIN (3) NOM (2) MAX (3) VD_MPU BOOT (Before 1.023 1.06 1.11 (V) AVS is enabled) (5) Not Applicable Not Applicable After AVS is enabled NOM – 0.85 to 3.5% 1.06 (4) NOM + 5% NOM – 3.5% 0.95 to 1.16 (4) NOM + 5% NOM – 3.5% 1.05 to 1.25 (4) NOM + 5% (1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with the ability to modify the voltage to comply with future recommendations. (2) In a typical implementation, the power supply should target the NOM voltage and ensure that the MIN and MAX voltages are guaranteed at the device ball. (3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc. (4) The power supply should be adjustable over this entire range to enable required AVS operation. For AVS Class 0 operation, the devicedependent AVS Voltage can be read from the STD_FUSE_OPP Registers in the Control Module Section of the TRM. (5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power. Table 3-6 describes the standard processor clock speed characteristics vs VD_MPU for DRA746 / DRA756 devices. Table 3-6. MPU Clock AC Performances for DRA746/DRA756 devices DESCRIPTION MPU_CLK OPP_NOM Max Freq (MHz) 1000 OPP_OD Max Freq (MHz) 1176 OPP_HIGH Max Freq (MHz) 1500 Table 3-7 describes the standard processor clock speed characteristics vs VD_MPU for DRA745 / DRA755 devices. Table 3-7. MPU Clock AC Performances for DRA745 / DRA755 devices DESCRIPTION MPU_CLK OPP_NOM Max Freq (MHz) 1000 OPP_OD Max Freq (MHz) 1176 Table 3-8 describes the standard processor clock speed characteristics vs VD_MPU for DRA744 / DRA754 devices. Table 3-8. MPU Clock AC Performances for DRA744 / DRA754 devices DESCRIPTION MPU_CLK OPP_NOM Max Freq (MHz) 1000 OPP_OD Max Freq (MHz) 1000 3.3.2 Digital Signal Processor (DSP) and EVE Voltage And Clock Specifications Table 3-9 shows the recommended DSPEVE voltage domain. Table 3-9. DSPEVE Voltage Domain (1) DOMAIN VD_DSPEVE (V) CONDITION BOOT (Before AVS is enabled) (5) MIN (3) 1.02 After AVS is enabled NOM – 3.5% OPP_NOM NOM (2) 1.06 0.85 to 1.06 (4) MAX (3) 1.11 NOM + 5% MIN (3) OPP_OD NOM (2) Not Applicable NOM – 3.5% 0.94 to 1.15 (4) MAX (3) NOM + 5% Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 157 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com (1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with the ability to modify the voltage to comply with future recommendations. (2) In a typical implementation, the power supply should target the NOM voltage and ensure that the MIN and MAX voltages are guaranteed at the device ball. (3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc. (4) The power supply should be adjustable over this entire range to enable required AVS operation. For AVS Class 0 operation, the devicedependent AVS Voltage can be read from the STD_FUSE_OPP Registers in the Control Module Section of the TRM. (5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power. Table 3-10 describes the standard processor clocks speed characteristics vs VD_DSPEVE Table 3-10. DSPEVE Clocks AC Performances DESCRIPTION DSP_CLK EVE_FCLK OPP_NOM Max Freq. (MHz) 600 535 OPP_OD Max Freq. (MHz) 700 625 3.3.3 Image and Video Accelerator (IVA) Voltage And Clock Specifications Table 3-11 shows the recommended IVA voltage domain. Table 3-11. IVA Voltage Domain (1) DOMAIN CONDITION OPP_NOM MIN (3) NOM (2) MAX (3) MIN (3) OPP_OD NOM (2) MAX (3) OPP_HIGH MIN (3) NOM (2) MAX (3) VD_IVA (V) BOOT (Before AVS is enabled) (5) After AVS is enabled 1.02 NOM – 3.5% 1.06 0.85 to 1.06 (4) 1.11 NOM + 5% Not Applicable NOM – 3.5% 0.94 to 1.15 (4) NOM + 5% Not Applicable NOM – 3.5% 1.05 to 1.25 (4) NOM + 5% (1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with the ability to modify the voltage to comply with future recommendations. (2) In a typical implementation, the power supply should target the NOM voltage and ensure that the MIN and MAX voltages are guaranteed at the device ball. (3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc. (4) The power supply should be adjustable over this entire range to enable required AVS operation. For AVS Class 0 operation, the devicedependent AVS Voltage can be read from the STD_FUSE_OPP Registers in the Control Module Section of the TRM. (5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power. Table 3-12 describes the standard processor clock speed characteristics vs VD_IVA. Table 3-12. IVA Clock AC Performances DESCRIPTION IVA_GCLK OPP_NOM Max Freq. (MHz) 388.3 OPP_OD Max Freq. (MHz) 430 OPP_HIGH Max Freq. (MHz) 532 158 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 3.3.4 3D Graphic Accelerator (GPU) Voltage And Clock Specifications Table 3-13 shows the recommended GPU voltage domain. Table 3-13. GPU Voltage Domain (1) DOMAIN CONDITION OPP_NOM MIN (3) NOM (2) MAX (3) OPP_OD MIN (3) NOM (2) MAX (3) OPP_HIGH MIN (3) NOM (2) MAX (3) VD_GPU (V) BOOT (Before AVS is enabled) (5) After AVS is enabled 1.02 NOM – 3.5% 1.06 0.85 to 1.06 (4) 1.11 NOM + 5% Not Applicable NOM – 3.5% 0.94 to 1.15 (4) NOM + 5% Not Applicable NOM – 3.5% 1.05 to 1.25 (4) NOM + 5% (1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with the ability to modify the voltage to comply with future recommendations. (2) In a typical implementation, the power supply should target the NOM voltage and ensure that the MIN and MAX voltages are guaranteed at the device ball. (3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc. (4) The power supply should be adjustable over this entire range to enable required AVS operation. For AVS Class 0 operation, the devicedependent AVS Voltage can be read from the STD_FUSE_OPP Registers in the Control Module Section of the TRM. (5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power. Table 3-14 shows the 3D graphic accelerator (GPU) clock speed characteristics vs VD_GPU. Table 3-14. GPU Clock AC Performances DESCRIPTION OPP_NOM Max Freq. (MHz) GPU_CLK 425.6 (1) Supported only on DRA746 / DRA756 devices. OPP_OD Max Freq. (MHz) 500 OPP_HIGH(1) Max Freq. (MHz) 532(1) 3.3.5 Core and Peripheral Voltage And Clock Specifications Table 3-15 shows the recommended devices core voltage domain. Table 3-15. Device Core Voltage Domain (1) DOMAIN CONDITION MIN (3) OPP_NOM NOM (2) MAX (3) VD_CORE (V) BOOT (Before AVS is enabled) (5) After AVS is enabled 0.99 NOM – 3.5% 1.03 0.85 to 1.03 (4) 1.08 NOM + 5% (1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with the ability to modify the voltage to comply with future recommendations. (2) In a typical implementation, the power supply should target the NOM voltage and ensure that the MIN and MAX voltages are guaranteed at the device ball. (3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc. (4) The power supply should be adjustable over this entire range to enable required AVS operation. For AVS Class 0 operation, the devicedependent AVS Voltage can be read from the STD_FUSE_OPP Registers in the Control Module Section of the TRM. (5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power. Table 3-16 shows the core clocks speed characteristics vs VD_CORE for DRA746 / DRA756, DRA745 / DRA755 and DRA744 / DRA754 devices. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 159 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 3-16. Core Clocks AC Performances for DRA746 / DRA756, DRA745 / DRA755 and DRA744 / DRA754 devices IPU_CLK L3_CLK DDR2 DDR3 DDR3L DESCRIPTION OPP_NOM Max Freq. (MHz) 212.8 266 DDR800 DDR1066 DDR1066 3.3.6 RTC Voltage And Clock Specifications Table 3-17 shows the recommended RTC voltage domain. Table 3-17. RTC Voltage Domain(1) DOMAIN OPP_NOM MIN (3) NOM(2) MAX(3) VD_RTC (V)(4) 0.84 0.88 to 1.03 1.08 (1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with the ability to modify the voltage to comply with future recommendations. (2) In a typical implementation, the power supply should target the NOM voltage and ensure that the MIN and MAX voltages are guaranteed at the device ball. (3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc. (4) VD_RTC can optionally be tied to to VD_CORE and operate at the VD_CORE AVS voltages Table 3-18 shows the RTCSS clock speed characteristics vs VD_RTC. Table 3-18. RTC Clock AC Performance RTC_FCLK DESCRIPTION OPP_NOM Max Freq. (MHz) 0.034 3.3.7 Maximum Supported Frequency Device modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM. Table 3-19 lists the clock source options for each module on this device, along with the maximum frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table. Table 3-19. Maximum Supported Frequency Instance Name AES1 AES2 Module Input Clock Name AES1_L3_CLK AES2_L3_CLK Clock Type Int Int Max. Clock Allowed (MHz) 266 266 PRCM Clock Name L4SEC_L3_GICLK L4SEC_L3_GICLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK CORE_X2_CLK PLL / OSC / Source Name DPLL_CORE DPLL_CORE 160 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Instance Name ATL Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name ATL_ICLK_L3 ATLPCLK Clock Type Int Func Max. Clock Allowed (MHz) 266 266 PRCM Clock Name ATL_L3_GICLK ATL_GFCLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK CORE_X2_CLK PER_ABE_X1_GF CLK FUNC_32K_CLK BB2D COUNTER_32K BB2D_FCLK BB2D_ICLK COUNTER_32K_F CLK COUNTER_32K_IC LK CTRL_MODULE_B L3INSTR_TS_GCL ANDGAP K CTRL_MODULE_C L4CFG_L4_GICLK ORE CTRL_MODULE_ WKUPAON_GICLK WKUP DCAN1 DCAN1_FCLK DCAN1_ICLK DCAN2 DES3DES DLL DLL_AGING DCAN2_FCLK DCAN2_ICLK DES_CLK_L3 EMIF_DLL_FCLK FCLK DMA_CRYPTO DMM DPLL_DEBUG DSP1 DMA_CRYPTO_FC LK DMA_CRYPTO_IC LK DMM_CLK SYSCLK DSP1_FICLK DSP2 DSP2_FICLK Func Int Func Int Int Int Int Func Int Func Int Int Func Int Int & Func Int Int Int Int & Func Int & Func 354.6 266 0.032 BB2D_GFCLK DSS_L3_GICLK FUNC_32K_CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK BB2D_GFCLK CORE_X2_CLK SYS_32K 38.4 WKUPAON_GICLK SYS_CLK1 DPLL_ABE_X2_CL K 4.8 L3INSTR_TS_GCLK SYS_CLK1 DPLL_ABE_X2_CL K 133 L4CFG_L4_GICLK CORE_X2_CLK 38.4 38.4 266 38.4 266 266 EMIF_DLL_FC LK TBD 266 WKUPAON_GICLK DCAN1_SYS_CLK WKUPAON_GICLK DCAN2_SYS_CLK L4PER2_L3_GICLK L4SEC_L3_GICLK EMIF_DLL_GCLK L3INSTR_DLL_AGING _GCLK L4SEC_L3_GICLK SYS_CLK1 DPLL_ABE_X2_CL K SYS_CLK1 SYS_CLK2 SYS_CLK1 DPLL_ABE_X2_CL K SYS_CLK1 CORE_X2_CLK CORE_X2_CLK EMIF_DLL_GCLK SYS_CLK1 DPLL_ABE_X2_CL K CORE_X2_CLK 133 L4SEC_L4_GICLK CORE_X2_CLK 266 38.4 DSP_CLK EMIF_L3_GICLK EMU_SYS_CLK DSP1_GFCLK CORE_X2_CLK SYS_CLK1 DSP_GFCLK DSP_CLK DSP2_GFCLK DSP_GFCLK PLL / OSC / Source Name DPLL_CORE DPLL_CORE DPLL_ABE OSC1 RTC Oscillator DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE DPLL_CORE RTC Oscillator OSC1 DPLL_ABE OSC1 DPLL_ABE DPLL_CORE OSC1 DPLL_ABE OSC1 OSC2 OSC1 DPLL_ABE OSC1 DPLL_CORE DPLL_CORE DPLL_DDR OSC1 DPLL_ABE DPLL_CORE DPLL_CORE DPLL_CORE OSC1 DPLL_DSP DPLL_DSP Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 161 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 3-19. Maximum Supported Frequency (continued) Module Instance Name Input Clock Name DSS DSS_HDMI_CEC_ CLK DSS_HDMI_PHY_ CLK DSS_CLK HDMI_CLKINP DSS_L3_ICLK VIDEO1_CLKINP VIDEO2_CLKINP DPLL_DSI1_A_CL K1 DPLL_DSI1_B_CL K1 DPLL_DSI1_C_CL K1 DSS DISPC DPLL_HDMI_CLK1 LCD1_CLK LCD2_CLK LCD3_CLK F_CLK EFUSE_CTRL_CU ST ocp_clk sys_clk ELM EMIF_OCP_FW EMIF_PHY1 EMIF_PHY2 ELM_ICLK L3_CLK EMIF_PHY1_FCLK EMIF_PHY2_FCLK Clock Type Func Func Func Func Int Func Func Func Func Func Func Func Func Func Func Int Func Int Int Func Func Max. Clock Allowed (MHz) 0.032 PRCM Clock Name HDMI_CEC_GFCLK Clock Sources PLL / OSC / Source Clock Name SYS_32K 48 HDMI_PHY_GFCLK FUNC_192M_CLK 192 38.4 266 38.4 38.4 209.3 209.3 209.3 185.6 TBD TBD TBD TBD 133 38.4 266 266 DDR DDR DSS_GFCLK DSS_CLK HDMI_DPLL_CLK SYS_CLK1 SYS_CLK2 DSS_L3_GICLK CORE_X2_CLK VIDEO1_DPLL_CLK SYS_CLK1 SYS_CLK2 VIDEO2_DPLL_CLK SYS_CLK1 SYS_CLK2 N/A HDMI_CLK VIDEO1_CLKOUT1 N/A VIDEO1_CLKOUT3 VIDEO2_CLKOUT3 HDMI_CLK DPLL_ABE_X2_CL K N/A HDMI_CLK VIDEO1_CLKOUT3 VIDEO2_CLKOUT1 N/A HDMI_CLK N/A DPLL_DSI1_A_CL K1 DSS_CLK N/A DPLL_DSI1_B_CL K1 DSS_CLK N/A DPLL_DSI1_C_CL K1 DSS_CLK N/A DPLL_DSI1_A_CL K1 DPLL_DSI1_B_CL K1 DPLL_DSI1_C_CL K1 DSS_CLK DPLL_HDMI_CLK1 CUSTEFUSE_L4_GICL CORE_X2_CLK K CUSTEFUSE_SYS_GF CLK SYS_CLK1 L4PER_L3_GICLK CORE_X2_CLK EMIF_L3_GICLK CORE_X2_CLK EMIF_PHY_GCLK EMIF_PHY_GCLK EMIF_PHY_GCLK EMIF_PHY_GCLK PLL / OSC / Source Name RTC Oscillator DPLL_PER DPLL_PER OSC1 OSC2 DPLL_CORE OSC1 OSC2 OSC1 OSC2 DPLL_HDMI DPLL_VIDEO1 DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_ABE DPLL_HDMI DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI See DSS data in the rows above DPLL_CORE OSC1 DPLL_CORE DPLL_CORE DPLL_DDR DPLL_DDR 162 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Instance Name EMIF1 EMIF2 EVE1 EVE2 FPKA GMAC_SW GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name EMIF1_ICLK EMIF2_ICLK EVE1_FCLK EVE2_FCLK PKA_CLK CPTS_RFT_CLK MAIN_CLK MHZ_250_CLK MHZ_5_CLK MHZ_50_CLK RMII1_MHZ_50_CL K RMII2_MHZ_50_CL K GPIO1_ICLK GPIO1_DBCLK Clock Type Int Int Func Func Int & Func Func Int Func Func Func Func Func Int Func Max. Clock Allowed (MHz) 266 266 EVE_FCLK EVE_FCLK 266 PRCM Clock Name EMIF_L3_GICLK EMIF_L3_GICLK EVE1_GFCLK EVE2_GFCLK L4SEC_L3_GICLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK CORE_X2_CLK EVE_GFCLK EVE_GFCLK CORE_X2_CLK 266 125 250 5 50 50 50 38.4 0.032 GMAC_RFT_CLK PER_ABE_X1_GF CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK CORE_X2_CLK GMAC_MAIN_CLK GMAC_250M_CLK GMII_250MHZ_CLK GMII_250MHZ_CL K RGMII_5MHZ_CLK GMAC_RMII_HS_C LK RMII_50MHZ_CLK GMAC_RMII_HS_C LK RMII_50MHZ_CLK GMAC_RMII_HS_C LK RMII_50MHZ_CLK GMAC_RMII_HS_C LK WKUPAON_GICLK SYS_CLK1 DPLL_ABE_X2_CL K WKUPAON_SYS_GFC WKUPAON_32K_G LK FCLK GPIO2_ICLK GPIO2_DBCLK Int Func 266 0.032 L4PER_L3_GICLK GPIO_GFCLK CORE_X2_CLK FUNC_32K_CLK GPIO3_ICLK GPIO3_DBCLK Int Func 266 0.032 L4PER_L3_GICLK GPIO_GFCLK CORE_X2_CLK FUNC_32K_CLK GPIO4_ICLK GPIO4_DBCLK PIDBCLK GPIO5_ICLK GPIO5_DBCLK PIDBCLK GPIO6_ICLK GPIO6_DBCLK PIDBCLK Int Func Func Int Func Func Int Func Func 266 0.032 0.032 266 0.032 0.032 266 0.032 0.032 L4PER_L3_GICLK GPIO_GFCLK GPIO_GFCLK L4PER_L3_GICLK GPIO_GFCLK GPIO_GFCLK L4PER_L3_GICLK GPIO_GFCLK GPIO_GFCLK CORE_X2_CLK FUNC_32K_CLK CORE_X2_CLK FUNC_32K_CLK CORE_X2_CLK FUNC_32K_CLK PLL / OSC / Source Name DPLL_CORE DPLL_CORE DPLL_DSP DPLL_EVE DPLL_DSP DPLL_EVE DPLL_CORE DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE DPLL_GMAC DPLL_GMAC DPLL_GMAC DPLL_GMAC DPLL_GMAC DPLL_GMAC OSC1 DPLL_ABE OSC1 RTC Oscillator DPLL_CORE OSC1 RTC Oscillator DPLL_CORE OSC1 RTC Oscillator DPLL_CORE OSC1 RTC Oscillator DPLL_CORE OSC1 RTC Oscillator DPLL_CORE OSC1 RTC Oscillator Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 163 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 3-19. Maximum Supported Frequency (continued) Module Instance Name Input Clock Name GPIO7 GPIO8 GPMC GPU GPIO7_ICLK GPIO7_DBCLK PIDBCLK GPIO8_ICLK GPIO8_DBCLK PIDBCLK GPMC_FCLK GPU_FCLK1 GPU_FCLK2 HDMI PHY HDQ1W GPU_ICLK DSS_HDMI_PHY_ CLK HDQ1W_ICLK I2C1 I2C2 I2C3 I2C4 I2C5 IEEE1500_2_OCP HDQ1W_FCLK I2C1_ICLK I2C1_FCLK I2C2_ICLK I2C2_FCLK I2C3_ICLK I2C3_FCLK I2C4_ICLK I2C4_FCLK I2C5_ICLK I2C5_FCLK PI_L3CLK IPU1 IPU1_GFCLK IPU2 IVA KBD L3_INSTR L3_MAIN IPU2_GFCLK IVA_GCLK KBD_FCLK PICLKKBD KBD_ICLK PICLKOCP L3_CLK L3_CLK1 L3_CLK2 Clock Type Int Func Func Int Func Func Int Func Func Int Func Int & Func Func Int Func Int Func Int Func Int Func Int Func Int & Func Int & Func Int & Func Int Func Func Int Int Int Int Int Max. Clock Allowed (MHz) 266 0.032 0.032 266 0.032 0.032 266 GPU_CLK GPU_CLK 266 38.4 PRCM Clock Name L4PER_L3_GICLK GPIO_GFCLK GPIO_GFCLK L4PER_L3_GICLK GPIO_GFCLK GPIO_GFCLK L3MAIN1_L3_GICLK GPU_CORE_GCLK GPU_HYD_GCLK GPU_L3_GICLK HDMI_PHY_GFCLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK FUNC_32K_CLK CORE_X2_CLK FUNC_32K_CLK CORE_X2_CLK CORE_GPU_CLK PER_GPU_CLK GPU_GCLK CORE_GPU_CLK PER_GPU_CLK GPU_GCLK CORE_X2_CLK FUNC_192M_CLK 266 L4PER_L3_GICLK CORE_X2_CLK 12 PER_12M_GFCLK FUNC_192M_CLK 266 L4PER_L3_GICLK CORE_X2_CLK 96 PER_96M_GFCLK FUNC_192M_CLK 266 L4PER_L3_GICLK CORE_X2_CLK 96 PER_96M_GFCLK FUNC_192M_CLK 266 L4PER_L3_GICLK CORE_X2_CLK 96 PER_96M_GFCLK FUNC_192M_CLK 266 L4PER_L3_GICLK CORE_X2_CLK 96 PER_96M_GFCLK FUNC_192M_CLK 266 IPU_L3_GICLK CORE_X2_CLK 96 IPU_96M_GFCLK FUNC_192M_CLK 266 L3INIT_L3_GICLK CORE_X2_CLK IPU_CLK IPU_CLK IVA_GCLK 0.032 0.032 38.4 38.4 L3_CLK L3_CLK L3_CLK IPU1_GFCLK DPLL_ABE_X2_CL K CORE_IPU_ISS_B OOST_CLK IPU2_GFCLK CORE_IPU_ISS_B OOST_CLK IVA_GCLK IVA_GFCLK WKUPAON_SYS_GFC WKUPAON_32K_G LK FCLK WKUPAON_SYS_GFC LK WKUPAON_GICLK SYS_CLK1 WKUPAON_GICLK DPLL_ABE_X2_CL K L3INSTR_L3_GICLK CORE_X2_CLK L3MAIN1_L3_GICLK CORE_X2_CLK L3INSTR_L3_GICLK CORE_X2_CLK PLL / OSC / Source Name DPLL_CORE OSC1 RTC Oscillator DPLL_CORE OSC1 RTC Oscillator DPLL_CORE DPLL_CORE DPLL_PER DPLL_GPU DPLL_CORE DPLL_PER DPLL_GPU DPLL_CORE DPLL_PER DPLL_CORE DPLL_PER DPLL_CORE DPLL_PER DPLL_CORE DPLL_PER DPLL_CORE DPLL_PER DPLL_CORE DPLL_PER DPLL_CORE DPLL_PER DPLL_CORE DPLL_ABE DPLL_CORE DPLL_CORE DPLL_IVA OSC1 RTC Oscillator OSC1 DPLL_ABE DPLL_CORE DPLL_CORE DPLL_CORE 164 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Instance Name L4_CFG L4_PER1 L4_PER2 L4_PER3 L4_WKUP MAILBOX1 MAILBOX2 MAILBOX3 MAILBOX4 MAILBOX5 MAILBOX6 MAILBOX7 MAILBOX8 MAILBOX9 MAILBOX10 MAILBOX11 MAILBOX12 MAILBOX13 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name L4_CFG_CLK L4_PER1_CLK L4_PER2_CLK L4_PER3_CLK L4_WKUP_CLK MAILBOX1_FLCK MAILBOX2_FLCK MAILBOX3_FLCK MAILBOX4_FLCK MAILBOX5_FLCK MAILBOX6_FLCK MAILBOX7_FLCK MAILBOX8_FLCK MAILBOX9_FLCK MAILBOX10_FLCK MAILBOX11_FLCK MAILBOX12_FLCK MAILBOX13_FLCK Clock Type Int Int Int Int Int Int Int Int Int Int Int Int Int Int Int Int Int Int Max. Clock Allowed (MHz) 133 133 133 133 38.4 266 266 266 266 266 266 266 266 266 266 266 266 266 PRCM Clock Name L4CFG_L3_GICLK L4PER_L3_GICLK L4PER2_L3_GICLK L4PER3_L3_GICLK WKUPAON_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK L4CFG_L3_GICLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK SYS_CLK1 DPLL_ABE_X2_CL K CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK PLL / OSC / Source Name DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE OSC1 DPLL_ABE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 165 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Instance Name MCASP1 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name MCASP1_AHCLKR MCASP1_AHCLKX MCASP1_FCLK MCASP1_ICLK Clock Type Func Func Func Int Clock Sources Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name 100 MCASP1_AHCLKR DPLL_ABE_X2_CL K SYS_CLK1 FUNC_96M_AON_ CLK ATLCLK0 ATLCLK1 ATLCLK2 ATLCLK3 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 MLB_CLK MLBP_CLK 100 MCASP1_AHCLKX DPLL_ABE_X2_CL K SYS_CLK1 FUNC_96M_AON_ CLK ATLCLK0 ATLCLK1 ATLCLK2 ATLCLK3 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 MLB_CLK MLBP_CLK 192 MCASP1_AUX_GFCLK PER_ABE_X1_GF CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 IPU_L3_GICLK CORE_X2_CLK PLL / OSC / Source Name DPLL_ABE OSC1 DPLL_PER Module ATL Module ATL Module ATL Module ATL OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 Module MLB Module MLB DPLL_ABE OSC1 DPLL_PER Module ATL Module ATL Module ATL Module ATL OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 Module MLB Module MLB DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE 166 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Instance Name MCASP2 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name MCASP2_AHCLKR MCASP2_AHCLKX MCASP2_FCLK MCASP2_ICLK Clock Type Func Func Func Int Clock Sources Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name 100 MCASP2_AHCLKR DPLL_ABE_X2_CL K SYS_CLK1 FUNC_96M_AON_ CLK ATL_CLK3 ATL_CLK2 ATL_CLK1 ATL_CLK0 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 MLB_CLK MLBP_CLK 100 MCASP2_AHCLKX DPLL_ABE_X2_CL K SYS_CLK1 FUNC_96M_AON_ CLK ATL_CLK3 ATL_CLK2 ATL_CLK1 ATL_CLK0 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 MLB_CLK MLBP_CLK 192 MCASP2_AUX_GFCLK PER_ABE_X1_GF CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L4PER2_L3_GICLK CORE_X2_CLK PLL / OSC / Source Name DPLL_ABE OSC1 DPLL_PER Module ATL Module ATL Module ATL Module ATL OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 Module MLB Module MLB DPLL_ABE OSC1 DPLL_PER Module ATL Module ATL Module ATL Module ATL OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 Module MLB Module MLB DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 167 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Instance Name MCASP3 MCASP4 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name MCASP3_AHCLKX MCASP3_FCLK MCASP3_ICLK MCASP4_AHCLKX MCASP4_FCLK MCASP4_ICLK Clock Type Func Func Int Func Func Int Clock Sources Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name 100 MCASP3_AHCLKX DPLL_ABE_X2_CL K SYS_CLK1 FUNC_96M_AON_ CLK ATL_CLK3 ATL_CLK2 ATL_CLK1 ATL_CLK0 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 MLB_CLK MLBP_CLK 192 MCASP3_AUX_GFCLK PER_ABE_X1_GF CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L4PER2_L3_GICLK CORE_X2_CLK 100 MCASP4_AHCLKX DPLL_ABE_X2_CL K SYS_CLK1 FUNC_96M_AON_ CLK ATL_CLK3 ATL_CLK2 ATL_CLK1 ATL_CLK0 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 MLB_CLK MLBP_CLK 192 MCASP4_AUX_GFCLK PER_ABE_X1_GF CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L4PER2_L3_GICLK CORE_X2_CLK PLL / OSC / Source Name DPLL_ABE OSC1 DPLL_PER Module ATL Module ATL Module ATL Module ATL OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 Module MLB Module MLB DPLL_ABE DPLL_ABE DPLL_VIDEO2 DPLL_HDMI DPLL_CORE DPLL_ABE OSC1 DPLL_PER Module ATL Module ATL Module ATL Module ATL OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 Module MLB Module MLB DPLL_ABE DPLL_ABE DPLL_VIDEO2 DPLL_HDMI DPLL_CORE 168 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Instance Name MCASP5 MCASP6 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name MCASP5_AHCLKX MCASP5_FCLK MCASP5_ICLK MCASP6_AHCLKX MCASP6_FCLK MCASP6_ICLK Clock Type Func Func Int Func Func Int Clock Sources Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name 100 MCASP5_AHCLKX DPLL_ABE_X2_CL K SYS_CLK1 FUNC_96M_AON_ CLK ATL_CLK3 ATL_CLK2 ATL_CLK1 ATL_CLK0 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 MLB_CLK MLBP_CLK 192 MCASP5_AUX_GFCLK PER_ABE_X1_GF CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L4PER2_L3_GICLK CORE_X2_CLK 100 MCASP6_AHCLKX DPLL_ABE_X2_CL K FUNC_96M_AON_ CLK ATL_CLK3 ATL_CLK2 ATL_CLK1 ATL_CLK0 MLB_CLK MLBP_CLK SYS_CLK1 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 192 MCASP6_AUX_GFCLK PER_ABE_X1_GF CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L4PER2_L3_GICLK CORE_X2_CLK PLL / OSC / Source Name DPLL_ABE OSC1 DPLL_PER Module ATL Module ATL Module ATL Module ATL OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 Module MLB Module MLB DPLL_ABE DPLL_ABE DPLL_VIDEO2 DPLL_HDMI DPLL_CORE DPLL_ABE DPLL_PER Module ATL Module ATL Module ATL Module ATL Module MLB Module MLB OSC1 OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_ABE DPLL_VIDEO2 DPLL_HDMI DPLL_CORE Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 169 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Instance Name MCASP7 MCASP8 MCSPI1 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name MCASP7_AHCLKX MCASP7_FCLK MCASP7_ICLK MCASP8_AHCLKX MCASP8_FCLK MCASP8_ICLK SPI1_ICLK SPI1_FCLK Clock Type Func Func Int Func Func Int Int Func Clock Sources Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name 100 MCASP7_AHCLKX DPLL_ABE_X2_CL K SYS_CLK1 FUNC_96M_AON_ CLK ATL_CLK3 ATL_CLK2 ATL_CLK1 ATL_CLK0 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 MLB_CLK MLBP_CLK 192 MCASP7_AUX_GFCLK PER_ABE_X1_GF CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L4PER2_L3_GICLK CORE_X2_CLK 100 MCASP8_AHCLKX DPLL_ABE_X2_CL K SYS_CLK1 FUNC_96M_AON_ CLK ATL_CLK3 ATL_CLK2 ATL_CLK1 ATL_CLK0 SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 MLB_CLK MLBP_CLK 192 MCASP8_AUX_GFCLK PER_ABE_X1_GF CLK VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L4PER2_L3_GICLK CORE_X2_CLK 266 L4PER_L3_GICLK CORE_X2_CLK 48 PER_48M_GFCLK PER_48M_GFCLK PLL / OSC / Source Name DPLL_ABE OSC1 DPLL_PER Module ATL Module ATL Module ATL Module ATL OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 Module MLB Module MLB DPLL_ABE DPLL_ABE DPLL_VIDEO2 DPLL_HDMI DPLL_CORE DPLL_ABE OSC1 DPLL_PER Module ATL Module ATL Module ATL Module ATL OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 Module MLB Module MLB DPLL_ABE DPLL_ABE DPLL_VIDEO2 DPLL_HDMI DPLL_CORE DPLL_CORE DPLL_PER 170 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Instance Name MCSPI2 MCSPI3 MCSPI4 MLB_SS MMC1 MMC2 MMC3 MMC4 MMU_EDMA MMU_PCIESS MPU MPU_EMU_DBG OCMC_RAM1 OCMC_RAM2 OCMC_RAM3 OCMC_ROM OCP_WP_NOC OCP2SCP1 OCP2SCP2 OCP2SCP3 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name SPI2_ICLK SPI2_FCLK SPI3_ICLK SPI3_FCLK SPI4_ICLK SPI4_FCLK MLB_L3_ICLK MLB_L4_ICLK MLB_FCLK MMC1_CLK_32K MMC1_FCLK MMC1_ICLK1 MMC1_ICLK2 MMC2_CLK_32K MMC2_FCLK MMC2_ICLK1 MMC2_ICLK2 MMC3_ICLK MMC3_CLK_32K MMC3_FCLK MMC4_ICLK MMC4_CLK_32K MMC4_FCLK MMU1_CLK MMU2_CLK MPU_CLK FCLK OCMC1_L3_CLK OCMC2_L3_CLK OCMC3_L3_CLK OCMC_L3_CLK PICLKOCPL3 L4CFG1_ADAPTE R_CLKIN L4CFG2_ADAPTE R_CLKIN L4CFG3_ADAPTE R_CLKIN Clock Type Int Func Int Func Int Func Int Int Func Func Func Int Int Func Func Int Int Int Func Func Int Func Func Int Int Int & Func Int Int Int Int Int Int Int Int Int Max. Clock Allowed (MHz) 266 48 266 48 266 48 266 133 266 0.032 192 128 266 133 0.032 192 128 266 133 266 0.032 48 192 266 0.032 48 192 266 266 MPU_CLK PRCM Clock Name L4PER_L3_GICLK PER_48M_GFCLK L4PER_L3_GICLK PER_48M_GFCLK L4PER_L3_GICLK PER_48M_GFCLK MLB_SHB_L3_GICLK MLB_SPB_L4_GICLK MLB_SYS_L3_GFCLK L3INIT_32K_GFCLK MMC1_GFCLK L3INIT_L3_GICLK L3INIT_L4_GICLK L3INIT_32K_GFCLK MMC2_GFCLK L3INIT_L3_GICLK L3INIT_L4_GICLK L4PER_L3_GICLK L4PER_32K_GFCLK MMC3_GFCLK L4PER_L3_GICLK L4PER_32K_GFCLK MMC4_GFCLK L3MAIN1_L3_GICLK L3MAIN1_L3_GICLK MPU_GCLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK PER_48M_GFCLK CORE_X2_CLK PER_48M_GFCLK CORE_X2_CLK PER_48M_GFCLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK FUNC_32K_CLK FUNC_192M_CLK FUNC_256M_CLK CORE_X2_CLK CORE_X2_CLK FUNC_32K_CLK FUNC_192M_CLK FUNC_256M_CLK CORE_X2_CLK CORE_X2_CLK CORE_X2_CLK FUNC_32K_CLK FUNC_192M_CLK CORE_X2_CLK FUNC_32K_CLK FUNC_192M_CLK CORE_X2_CLK CORE_X2_CLK MPU_GCLK 38.4 EMU_SYS_CLK SYS_CLK1 MPU_GCLK 266 L3MAIN1_L3_GICLK CORE_X2_CLK 266 L3MAIN1_L3_GICLK CORE_X2_CLK 266 L3MAIN1_L3_GICLK CORE_X2_CLK 266 L3MAIN1_L3_GICLK CORE_X2_CLK 266 L3INSTR_L3_GICLK CORE_X2_CLK 133 L3INIT_L4_GICLK CORE_X2_CLK 133 L4CFG_L4_GICLK CORE_X2_CLK 133 L3INIT_L4_GICLK CORE_X2_CLK PLL / OSC / Source Name DPLL_CORE DPLL_PER DPLL_CORE DPLL_PER DPLL_CORE DPLL_PER DPLL_CORE DPLL_CORE DPLL_CORE OSC1 DPLL_PER DPLL_PER DPLL_CORE DPLL_CORE OSC1 DPLL_PER DPLL_PER DPLL_CORE DPLL_CORE DPLL_CORE OSC1 DPLL_PER DPLL_CORE OSC1 DPLL_PER DPLL_CORE DPLL_CORE DPLL_MPU OSC1 DPLL_MPU DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 171 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 3-19. Maximum Supported Frequency (continued) Module Instance Name Input Clock Name PCIESS1 PCIESS2 PRCM_MPU PCIE1_PHY_WKU P_CLK PCIe_SS1_FICLK PCIEPHY_CLK PCIEPHY_CLK_DI V PCIE1_REF_CLKI N PCIE1_PWR_CLK PCIE2_PHY_WKU P_CLK PCIe_SS2_FICLK PCIEPHY_CLK PCIEPHY_CLK_DI V PCIE2_REF_CLKI N PCIE2_PWR_CLK 32K_CLK SYS_CLK PWMSS1 PWMSS2 PWMSS3 QSPI PWMSS1_GICLK PWMSS2_GICLK PWMSS3_GICLK QSPI_ICLK QSPI_FCLK RNG RTC_SS SAR_ROM SATA SDMA RNG_ICLK RTC_ICLK RTC_FCLK PRCM_ROM_CLO CK SATA_FICLK SATA_PMALIVE_F CLK REF_CLK SDMA_FCLK SHA2MD51 SHA2MD52 SL2 SMARTREFLEX_C ORE SHAM_1_CLK SHAM_2_CLK IVA_GCLK MCLK SYSCLK Clock Type Func Int Func Func Func Func Func Func Func Func Func Func Func Func Int & Func Int & Func Int & Func Int Func Int Int Func Int Int Func Func Int & Func Int Int Int Int Func Max. Clock Allowed (MHz) 0.032 PRCM Clock Name PCIE_32K_GFCLK Clock Sources PLL / OSC / Source Clock Name FUNC_32K_CLK 266 2500 1250 34.3 38.4 0.032 PCIE_L3_GICLK CORE_X2_CLK PCIE_PHY_GCLK PCIE_PHY_GCLK PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G CLK PCIE_REF_GFCLK CORE_USB_OTG_ SS_LFPS_TX_CLK PCIE_SYS_GFCLK SYS_CLK1 PCIE_32K_GFCLK FUNC_32K_CLK 266 2500 1250 34.3 38.4 0.032 38.4 266 PCIE_L3_GICLK CORE_X2_CLK PCIE_PHY_GCLK PCIE_PHY_GCLK PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G CLK PCIE_REF_GFCLK CORE_USB_OTG_ SS_LFPS_TX_CLK PCIE_SYS_GFCLK SYS_CLK1 FUNC_32K_CLK SYS_32K WKUPAON_ICLK SYS_CLK1 DPLL_ABE_X2_CL K L4PER2_L3_GICLK CORE_X2_CLK 266 L4PER2_L3_GICLK CORE_X2_CLK 266 L4PER2_L3_GICLK CORE_X2_CLK 266 128 266 133 RTC_FCLK 266 L4PER2_L3_GICLK QSPI_GFCLK L4SEC_L3_GICLK RTC_L4_GICLK RTC_AUX_CLK L4CFG_L3_GICLK CORE_X2_CLK FUNC_256M_CLK PER_QSPI_CLK CORE_X2_CLK CORE_X2_CLK FUNC_32K_CLK CORE_X2_CLK 266 L3INIT_L3_GICLK CORE_X2_CLK 48 L3INIT_48M_GFCLK FUNC_192M_CLK 38 SATA_REF_GFCLK SYS_CLK1 266 DMA_L3_GICLK CORE_X2_CLK 266 266 IVA_GCLK 133 38.4 L4SEC_L3_GICLK L4SEC_L3_GICLK IVA_GCLK COREAON_L4_GICLK WKUPAON_ICLK CORE_X2_CLK CORE_X2_CLK IVA_GFCLK CORE_X2_CLK SYS_CLK1 DPLL_ABE_X2_CL K PLL / OSC / Source Name RTC Oscillator DPLL_CORE APLL_PCIE APLL_PCIE DPLL_CORE OSC1 RTC Oscillator DPLL_CORE APLL_PCIE APLL_PCIE DPLL_CORE OSC1 RTC Oscillator OSC1 DPLL_ABE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE DPLL_CORE RTC Oscillator DPLL_CORE DPLL_CORE DPLL_PER OSC1 DPLL_CORE DPLL_CORE DPLL_CORE DPLL_IVA DPLL_CORE OSC1 DPLL_ABE 172 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 3-19. Maximum Supported Frequency (continued) Module Instance Name Input Clock Name SMARTREFLEX_D SPEVE MCLK SYSCLK SMARTREFLEX_G PU MCLK SYSCLK SMARTREFLEX_IV AHD MCLK SYSCLK SMARTREFLEX_M PU MCLK SYSCLK SPINLOCK TIMER1 SPINLOCK_ICLK TIMER1_ICLK TIMER1_FCLK Clock Type Int Func Int Func Int Func Int Func Int Int Func Max. Clock Allowed (MHz) 133 38.4 133 38.4 133 38.4 133 38.4 266 38.4 100 PRCM Clock Name COREAON_L4_GICLK WKUPAON_ICLK COREAON_L4_GICLK WKUPAON_ICLK COREAON_L4_GICLK WKUPAON_ICLK COREAON_L4_GICLK WKUPAON_ICLK L4CFG_L3_GICLK WKUPAON_GICLK TIMER1_GFCLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK SYS_CLK1 DPLL_ABE_X2_CL K CORE_X2_CLK SYS_CLK1 DPLL_ABE_X2_CL K CORE_X2_CLK SYS_CLK1 DPLL_ABE_X2_CL K CORE_X2_CLK SYS_CLK1 DPLL_ABE_X2_CL K CORE_X2_CLK SYS_CLK1 DPLL_ABE_X2_CL K SYS_CLK1 FUNC_32K_CLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK TIMER2 TIMER2_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK TIMER2_FCLK Func 100 TIMER2_GFCLK SYS_CLK1 FUNC_32K_CLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK PLL / OSC / Source Name DPLL_CORE OSC1 DPLL_ABE DPLL_CORE OSC1 DPLL_ABE DPLL_CORE OSC1 DPLL_ABE DPLL_CORE OSC1 DPLL_ABE DPLL_CORE OSC1 DPLL_ABE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 173 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Instance Name TIMER3 TIMER4 TIMER5 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name TIMER3_ICLK TIMER3_FCLK Clock Type Int Func Max. Clock Allowed (MHz) 266 100 PRCM Clock Name L4PER_L3_GICLK TIMER3_GFCLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK SYS_CLK1 FUNC_32K_CLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK TIMER4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK TIMER4_FCLK Func 100 TIMER4_GFCLK SYS_CLK1 FUNC_32K_CLK TIMER5_ICLK Int 266 TIMER5_FCLK Func 100 IPU_L3_GICLK TIMER5_GFCLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK CORE_X2_CLK SYS_CLK1 FUNC_32K_CLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK CLKOUTMUX[0] PLL / OSC / Source Name DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI CLKOUTMUX[0] 174 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Instance Name TIMER6 TIMER7 TIMER8 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name TIMER6_ICLK TIMER6_FCLK Clock Type Int Func Max. Clock Allowed (MHz) 266 100 PRCM Clock Name IPU_L3_GICLK TIMER6_GFCLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK SYS_CLK1 FUNC_32K_CLK TIMER7_ICLK Int 266 TIMER7_FCLK Func 100 IPU_L3_GICLK TIMER7_GFCLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK CLKOUTMUX[0] CORE_X2_CLK SYS_CLK1 FUNC_32K_CLK TIMER8_ICLK Int 266 TIMER8_FCLK Func 100 IPU_L3_GICLK TIMER8_GFCLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK CLKOUTMUX[0] CORE_X2_CLK SYS_CLK1 FUNC_32K_CLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK CLKOUTMUX[0] PLL / OSC / Source Name DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI CLKOUTMUX[0] DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI CLKOUTMUX[0] DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI CLKOUTMUX[0] Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 175 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Instance Name TIMER9 TIMER10 TIMER11 TIMER12 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name TIMER9_ICLK TIMER9_FCLK Clock Type Int Func Max. Clock Allowed (MHz) 266 100 PRCM Clock Name L4PER_L3_GICLK TIMER9_GFCLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK SYS_CLK1 FUNC_32K_CLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK TIMER10_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK TIMER10_FCLK Func 100 TIMER10_GFCLK SYS_CLK1 FUNC_32K_CLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK TIMER11_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK TIMER11_FCLK Func 100 TIMER11_GFCLK SYS_CLK1 FUNC_32K_CLK TIMER12_ICLK Int TIMER12_FCLK Func 38.4 0.032 WKUPAON_GICLK OSC_32K_CLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK SYS_CLK1 DPLL_ABE_X2_CL K RC_CLK PLL / OSC / Source Name DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI OSC1 DPLL_ABE RC oscillator 176 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Instance Name TIMER13 TIMER14 TIMER15 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name TIMER13_ICLK TIMER13_FCLK Clock Type Int Func Max. Clock Allowed (MHz) 266 100 PRCM Clock Name L4PER3_L3_GICLK TIMER13_GFCLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK SYS_CLK1 FUNC_32K_CLK TIMER14_ICLK TIMER14_FCLK Int Func SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L4PER3_L3_GICLK CORE_X2_CLK 100 TIMER14_GFCLK SYS_CLK1 FUNC_32K_CLK TIMER15_ICLK TIMER15_FCLK Int Func SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L4PER3_L3_GICLK CORE_X2_CLK 100 TIMER15_GFCLK SYS_CLK1 FUNC_32K_CLK SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK PLL / OSC / Source Name DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 177 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Instance Name TIMER16 TPCC TPTC1 TPTC2 UART1 UART2 UART3 UART4 UART5 UART6 UART7 UART8 UART9 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name TIMER16_ICLK TIMER16_FCLK Clock Type Int Func Max. Clock Allowed (MHz) 266 100 PRCM Clock Name L4PER3_L3_GICLK TIMER16_GFCLK Clock Sources PLL / OSC / Source Clock Name CORE_X2_CLK SYS_CLK1 FUNC_32K_CLK TPCC_GCLK TPTC0_GCLK TPTC1_GCLK UART1_FCLK Int Int Int Func SYS_CLK2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE_X2_CL K VIDEO1_CLK VIDEO2_CLK HDMI_CLK 266 L3MAIN1_L3_GICLK CORE_X2_CLK 266 L3MAIN1_L3_GICLK CORE_X2_CLK 266 L3MAIN1_L3_GICLK CORE_X2_CLK 48 UART1_GFCLK FUNC_192M_CLK UART1_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK UART2_FCLK Func 48 UART2_GFCLK FUNC_192M_CLK UART2_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK UART3_FCLK Func 48 UART3_GFCLK FUNC_192M_CLK UART3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK UART4_FCLK Func 48 UART4_GFCLK FUNC_192M_CLK UART4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK UART5_FCLK Func 48 UART5_GFCLK FUNC_192M_CLK UART5_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK UART6_FCLK Func 48 UART6_GFCLK FUNC_192M_CLK UART6_ICLK Int 266 UART7_FCLK Func 48 IPU_L3_GICLK UART7_GFCLK CORE_X2_CLK FUNC_192M_CLK UART7_ICLK UART8_FCLK Int Func 266 L4PER2_L3_GICLK CORE_X2_CLK 48 UART8_GFCLK FUNC_192M_CLK UART8_ICLK UART9_FCLK Int Func 266 L4PER2_L3_GICLK CORE_X2_CLK 48 UART9_GFCLK FUNC_192M_CLK UART9_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK PLL / OSC / Source Name DPLL_CORE OSC1 OSC1 RTC Oscillator OSC2 XREF_CLK0 XREF_CLK1 XREF_CLK2 XREF_CLK3 DPLL_ABE DPLL_VIDEO1 DPLL_VIDEO2 DPLL_HDMI DPLL_CORE DPLL_CORE DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE DPLL_PER DPLL_PER DPLL_CORE 178 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Instance Name UART10 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name UART10_FCLK Clock Type Func Max. Clock Allowed (MHz) 48 PRCM Clock Name UART10_GFCLK Clock Sources PLL / OSC / Source Clock Name FUNC_192M_CLK UART10_ICLK Int USB1 USB1_MICLK USB3PHY_REF_C LK USB2PHY1_TREF _CLK USB2PHY1_REF_ CLK USB2 USB2_MICLK USB2PHY2_TREF _CLK USB2PHY2_REF_ CLK USB3 USB3_MICLK USB3PHY_PWRS_ CLK USB4 USB4_MICLK DPLL_USBSS_RE F_CLK USB_PHY1_CORE USB2PHY1_WKUP _CLK USB_PHY2_CORE USB2PHY2_WKUP _CLK USB_PHY3_CORE USB3PHY_WKUP_ CLK VCP1 VCP1_CLK VCP2 VCP2_CLK VIP1 L3_CLK_PROC_CL K Int Func Func Func Int Func Func Int Func Int Func Func Func Func Int Int Int & Func VIP2 L3_CLK_PROC_CL Int & K Func VIP3 L3_CLK_PROC_CL Int & K Func VPE L3_CLK_PROC_CL Int & K Func WD_TIMER1 PIOCPCLK Int PITIMERCLK Func 38.4 266 34.3 38.4 960 266 38.4 960 266 38.4 266 38.4 0.032 0.032 0.032 266 266 266 266 266 300 38.4 0.032 WKUPAON_GICLK SYS_CLK1 DPLL_ABE_X2_CL K L3INIT_L3_GICLK CORE_X2_CLK USB_LFPS_TX_GFCL CORE_USB_OTG_ K SS_LFPS_TX_CLK USB_OTG_SS_REF_C LK SYS_CLK1 L3INIT_960M_GFCLK L3INIT_960_GFCL K L3INIT_L3_GICLK CORE_X2_CLK USB_OTG_SS_REF_C LK SYS_CLK1 L3INIT_960M_GFCLK L3INIT_960_GFCL K L3INIT_L3_GICLK CORE_X2_CLK USB_OTG_SS_REF_C LK SYS_CLK1 L3INIT_L3_GICLK CORE_X2_CLK USB_OTG_SS_REF_C LK SYS_CLK1 COREAON_32K_GFCL K SYS_32K COREAON_32K_GFCL K SYS_32K COREAON_32K_GFCL K SYS_32K L3MAIN1_L3_GICLK CORE_X2_CLK L3MAIN1_L3_GICLK CORE_X2_CLK VIP1_GCLK CORE_X2_CLK CORE_ISS_MAIN_ CLK VIP2_GCLK CORE_X2_CLK CORE_ISS_MAIN_ CLK VIP3_GCLK CORE_X2_CLK CORE_ISS_MAIN_ CLK VPE_GCLK CORE_ISS_MAIN_ CLK VIDEO1_CLKOUT4 WKUPAON_GICLK SYS_CLK1 DPLL_ABE_X2_CL K OSC_32K_CLK RC_CLK PLL / OSC / Source Name DPLL_PER DPLL_PER OSC1 DPLL_ABE DPLL_CORE DPLL_CORE OSC1 DPLL_USB DPLL_CORE OSC1 DPLL_USB DPLL_CORE OSC1 DPLL_CORE OSC1 RTC Oscillator RTC Oscillator RTC Oscillator DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_CORE DPLL_VIDEO1 OSC1 DPLL_ABE RC oscillator Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 179 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Instance Name WD_TIMER2 Table 3-19. Maximum Supported Frequency (continued) Module Input Clock Name WD_TIMER2_ICLK WD_TIMER2_FCL K Clock Type Int Func Clock Sources Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name 38.4 WKUPAON_GICLK SYS_CLK1 DPLL_ABE_X2_CL K 0.032 WKUPAON_SYS_GFC WKUPAON_32K_G LK FCLK PLL / OSC / Source Name OSC1 DPLL_ABE RTC Oscillator 3.4 DC Electrical Characteristics NOTE The data specified in Section 3.4.1 through Section 3.4.10 are subject to change. NOTE The interfaces or signals described in Section 3.4.1 through Section 3.4.10 correspond to the interfaces or signals available in multiplexing mode 0 (Function 1). All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions). 3.4.1 LVCMOS DDR DC Electrical Characteristics Table 3-20 summarizes the DC electrical characteristics for LVCMOS DDR Buffers. NOTE For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control Module of the Device TRM. ADVANCE INFORMATION 180 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 3-20. LVCMOS DDR DC Electrical Characteristics PARAMETER MIN NOM MAX UNIT Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[0], ddr1_cke, ddr1_odt[0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc, ddr2_d[31:0], ddr2_a[15:0], ddr2_dqm[3:0], ddr2_ba[2:0], ddr2_csn[0], ddr2_cke, ddr2_odt[0], ddr2_casn, ddr2_rasn, ddr2_wen, ddr2_rst; Balls: AA28 / AA25 / AA26 / Y24 / AA24 / Y23 / Y22 / AA23 / Y20 / AB27 / Y19 / AC27 / AC28 / AB28 / W20 / V20 / AD25 / AC24 / AC25 / AE26 / AF28 / AG27 / AF27 / AC23 / AE23 / AF23 / AE24 / AF24 / AH26 / AG26 / AF26 / AF25 / AD18 / AE17 / AF18 / AC21 / AD22 / AD21 / AE22 / AF22 / AE21 / AE21 / AH22 / AF21 / AB19 / AC20 / AC19 / AD20 / AA27 / AC26 / AB23 / AD23 / AB18 / AE18 / AF17 / AH23 / AG22 / AE20 / AC18 / AF20 / AH21 / AG21 / Y26 / V25 / V24 / Y25 / W23 / W19 / V23 / W22 / V26 / M26 / M25 / M24 / M23 / L28 / L25 / L26 / L27 / J20 / K22 / J23 / L24 / L23 / K21 / K20 / L22 / J24 / J26 / J25 / G26 / H26 / H24 / H25 / H23 / E28 / E27 / F27 / F26 / F24 / F25 / G25 / E26 / U22 / R22 / T22 / N28 / P26 / N23 / N27 / P27 / N20 / P25 / P22 / P23 / R27 / R28 / R26 / R25 / M22 / K23 / G24 / F28 / U26 / U27 / U23 / P24 / U24 / R23 / U28 / T23 / U25 / R24; Driver Mode VOH High-level output threshold (IOH = 0.1 mA) 0.9*VDDS V VOL Low-level output threshold (IOL = 0.1 mA) 0.1*VDDS V CPAD Pad capacitance (including package capacitance) 3 pF ZO Output impedance (drive l[2:0] = 000 80 Ω strength) (Imp80) l[2:0] = 001 60 (Imp60) l[2:0] = 010 48 (Imp48) l[2:0] = 011 40 (Imp40) l[2:0] = 100 34 (Imp34) tOT Output transition time (rise time sr[2:0] = 000 ns tR or fall time tF, evaluated (Fastest) between 10% and 90% of VPAD) for drive strength = 40 Ω and CLOAD = 5 pF sr[2:0] = 001 (Faster) sr[2:0] = 010 (Fast) sr[2:0] = 011 (Slow) sr[2:0] = 100 (Slower) sr[2:0] = 101 (Slowest-1) sr[2:0] = 110 (Slowest-2) sr[2:0] = 111 (Slowest-3) Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L DDR2 VREF+0.1 VREF+0.125 VDDS+0.2 V VDDS+0.3 VIL Low-level input threshold DDR3/DDR3L -0.2 DDR2 -0.3 VREF-0.1 V VREF-0.125 VCM Input common-mode voltage VREF -10%vdds VREF+ V 10%vdds CPAD Pad capacitance (including package capacitance) pF Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr2_dqs[3:0], ddr2_dqsn[3:0], ddr2_ck, ddr2_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc Bottom Balls: Y28 / AD27 / AE27 / AH25 / Y27 / AD28 / AE28 / AG25 / AG24 / AH24 / M28 / K27 / H27 / G28 / M27 / K28 / H28 / G27 / T28 / T27 / V27 / V28 Driver Mode VOH High-level output threshold (IOH = 0.1 mA) VOL Low-level output threshold (IOL = 0.1 mA) 0.9*VDDS V 0.1*VDDS V Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 181 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 3-20. LVCMOS DDR DC Electrical Characteristics (continued) PARAMETER MIN CPAD ZO Pad capacitance (including package capacitance) Output impedance (drive strength) l[2:0] = 000 (Imp80) l[2:0] = 001 (Imp60) l[2:0] = 010 (Imp48) l[2:0] = 011 (Imp40) l[2:0] = 100 (Imp34) tOT Output transition time (rise time sr[2:0] = 000 tR or fall time tF, evaluated (Fastest) between 10% and 90% of VPAD) for drive strength = 40 Ω and CLOAD = 5 pF sr[2:0] = 001 (Faster) sr[2:0] = 010 (Fast) sr[2:0] = 011 (Slow) sr[2:0] = 100 (Slower) sr[2:0] = 101 (Slowest-1) sr[2:0] = 110 (Slowest-2) sr[2:0] = 111 (Slowest-3) Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L DDR2 VREF+0.1 VREF+0.125 VIL Low-level input threshold DDR3/DDR3L -0.2 DDR2 -0.3 VCM Input common-mode voltage VREF 10%vdds CPAD Pad capacitance (including package capacitance) Differential Receiver Mode VSWING Input voltage swing DDR3/DDR3L 0.2 DDR2 0.25 VCM Input common-mode voltage VREF 10%vdds CPAD Pad capacitance (including package capacitance) Signal Names in MUXMODE 1 (VREF Signals): ddr1_vref0, ddr2_vref0 Bottom Balls: Y18 / N22 VREF Reference internal generation dc voltage level vref_tap[1:0] = 00, 2-µA current load vref_tap[1:0] = 01, 4-µA current load vref_tap[1:0] = 10, 8-µA current load vref_tap[1:0] = 11, 32-µA current load NOM 80 60 48 40 34 0.5*VDDS 0.5*VDDS 0.5*VDDS 0.5*VDDS MAX 3 VDDS+0.2 VDDS+0.3 VREF-0.1 VREF-0.125 VREF+ 10%vdds vdds+0.4 vdds+0.6 VREF+ 10%vdds UNIT pF Ω ns V V V pF V pF V 182 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 3-20. LVCMOS DDR DC Electrical Characteristics (continued) CCAP PARAMETER Decoupling capacitor MIN ccap[1:0] = 00 ccap[1:0] = 01 ccap[1:0] = 10 ccap[1:0] = 11 NOM TBD TBD TBD TBD MAX UNIT 1. VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1 or vdds_ddr2). For more information on the power supply name and the corresponding ball, see Table 2-2, POWER [11] column. 2. VREF in this table stands for corresponding Reference Power Supply (i.e. ddr1_vref0 or ddr2_vref0). For more information on the power supply name and the corresponding ball, see Table 2-2, POWER [11] column. 3.4.2 HDMIPHY DC Electrical Characteristics NOTE For more information on HDMI, please contact your TI representative. 3.4.3 Dual Voltage LVCMOS I2C DC Electrical Characteristics Table 3-21 summarizes the DC electrical characteristics for Dual Voltage LVCMOS I2C Buffers. NOTE For more information on the I/O cell configurations , see the Control Module section of the Device TRM. Table 3-21. Dual Voltage LVCMOS I2C DC Electrical Characteristics PARAMETER MIN Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda; Balls: F17 / C20 / C21 / C25 I2C Standard Mode – 1.8 V VIH Input high-level threshold VIL Input low-level threshold Vhys Hysteresis II Input current at each I/O pin with an input voltage between 0.1*VDDS to 0.9*VDDS 0.7*VDDS 0.1*VDDS CI VOL3 Input capacitance Output low-level threshold opendrain at 3-mA sink current IOLmin Low-level output current 3 @VOL=0.2*VDDS tOF Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF to 400 pF I2C Fast Mode – 1.8 V VIH Input high-level threshold VIL Input low-level threshold Vhys Hysteresis II Input current at each I/O pin with an input voltage between 0.1*VDDS to 0.9*VDDS 0.7*VDDS 0.1*VDDS NOM MAX 0.3*VDDS 12 10 0.2*VDDS 250 0.3*VDDS 12 UNIT V V V µA pF V mA ns V V V µA Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 183 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 3-21. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued) PARAMETER CI VOL3 Input capacitance Output low-level threshold opendrain at 3-mA sink current IOLmin Low-level output current @VOL=0.2*VDDS tOF Output fall time from VIHmin to VILmax with a bus capacitance CB from 10 pF to 400 pF I2C Standard Mode – 3.3 V VIH Input high-level threshold VIL Input low-level threshold Vhys Hysteresis II Input current at each I/O pin with an input voltage between 0.1*VDDS to 0.9*VDDS CI VOL3 Input capacitance Output low-level threshold opendrain at 3-mA sink current IOLmin Low-level output current @VOL=0.4V IOLmin Low-level output current @VOL=0.6V for full drive load (400pF/400KHz) tOF Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF to 400 pF I2C Fast Mode – 3.3 V VIH Input high-level threshold VIL Input low-level threshold Vhys Hysteresis II Input current at each I/O pin with an input voltage between 0.1*VDDS to 0.9*VDDSS CI VOL3 Input capacitance Output low-level threshold opendrain at 3-mA sink current IOLmin Low-level output current @VOL=0.4V IOLmin Low-level output current @VOL=0.6V for full drive load (400pF/400KHz) tOF Output fall time from VIHmin to VILmax with a bus capacitance CB from 10 pF to 200 pF (Proper External Resistor Value should be used as per I2C spec) Output fall time from VIHmin to VILmax with a bus capacitance CB from 300 pF to 400 pF (Proper External Resistor Value should be used as per I2C spec) MIN 3 20+0.1*Cb NOM MAX 10 0.2*VDDS 250 0.7*VDDS 0.05*VDDS 3 6 0.3*VDDS 80 10 0.4 250 0.7*VDDS 0.05*VDDS 3 6 20+0.1*Cb 0.3*VDDS 80 10 0.4 250 40 290 www.ti.com UNIT pF V mA ns V V V µA pF V mA mA ns V V V µA pF V mA mA ns 184 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 1. VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the corresponding ball, see Table 2-2, POWER [11] column. 3.4.4 USB DC Electrical Characteristics 3.4.4.1 USB2PHY DC Electrical Characteristics NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. 3.4.4.2 USB3PHY DC Electrical Characteristics NOTE The USB3 RX PHY module is compliant with the receiver electrical parameters specified in the Universal Serial Bus 3.0 Specification, Revision 1.0, November 12, 2008. NOTE The USB3 TX PHY module is compliant with the transmitter electrical parameters and LFPS electrical parameters specified in the Universal Serial Bus 3.0 Specification, Revision 1.0, November 12, 2008. NOTE For more information regarding the USB3 pin name (or ball name) and corresponding signal name, see Section 2.4.13, USB Signal Descriptions. NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 185 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 3.4.5 MMC1 DC Electrical Characteristics NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. 3.4.6 Dual Voltage LVCMOS DC Electrical Characteristics Table 3-22 summarizes the DC electrical characteristics for Dual Voltage LVCMOS Buffers. Table 3-22. LVCMOS DC Electrical Characteristics PARAMETER 1.8-V Mode VIH VIL VHYS VOH VOL IDRIVE IIN CPAD ZO tOT 3.3-V Mode VIH VIL VHYS VOH VOL IDRIVE IIN CPAD ZO tOT Input high-level threshold Input low-level threshold Input hysteresis voltage Output high-level threshold (IOH = 2 mA) Output low-level threshold (IOL = 2 mA) Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V Input current at each I/O pin Pad capacitance (including package capacitance) Output impedance (drive strength) Output transition time (tR or tF evaluated between 10% and 90% of VPAD) for drive strength = 40 Ω and CLOAD = 10 pF SC1 = 0 (Fast) SC1 = 1 (Slow) Input high-level threshold Input low-level threshold Input hysteresis voltage Output high-level threshold (IOH =100UA) Output low-level threshold (IOL = 100UA) Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V Input current at each I/O pin Pad capacitance (including package capacitance) Output impedance (drive strength) Output transition time (tR or tF evaluated between 10% and 90% of VPAD) for drive strength = 40 Ω and CLOAD = 10 pF SC1 = 0 (Fast) SC1 = 1 (Slow) MIN 0.65*VDDS 100 VDDS-0.45 6mA 2 200 VDDS-0.2 6mA NOM 40 40 MAX 0.35*VDDS 0.45 12 0.8 0.2 65 www.ti.com UNIT V V mV V V mA uA pF Ω ns V V mV V V mA uA pF Ω ns 186 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 1. VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 2-2, POWER [11] column. 3.4.7 SATAPHY DC Electrical Characteristics NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. NOTE For more information regarding the SATA PHY pin name (or ball name) and corresponding signal name, see Section 2.4.14, SATA Signal Descriptions. 3.4.8 PCIEPHY DC Electrical Characteristics NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 187 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 3.4.9 MLB DC Electrical Characteristics NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. www.ti.com 3.4.10 System DC Electrical Characteristics NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. 3.5 External Capacitors This section describes the device decoupling capacitor requirements per supply rail. Table 3-23 describes the device Decoupling Capacitor Requirements. Table 3-23. Decoupling Capacitor Requirements Supply Rail vdd_mpu vdd_dspeve vdd vdd_gpu vdd_iva Other 0.001uF 0 0 0 0 0 TBD 0.01uF 0 0 0 0 0 TBD 0.1uF 12 8 6 6 5 TBD Number of Required Decoupling Capacitors 0.22uF 0.47uF 1uF 2.2uF 2 2 3 1 1 1 2 1 1 1 1 1 1 1 1 1 0 1 0 0 TBD TBD TBD TBD 4.7uF 1 1 1 1 1 TBD 10uF 0 1 0 0 0 TBD 22uF 1 0 0 0 0 TBD 3.6 Power Sequencing This section describes the power-up and power-down sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the Section 2.2, Ball Characteristics of the Section 2, Terminal Description to determine which power supplies are applicable. Figure 3-1 and Figure 3-2, describes the device Power Sequencing when RTC-mode is used. 188 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com vdda_rtc(3) vdds18v, vdds_mlbp, vdds18v_ddr1, vdds18v_ddr2 vdda_abe_per, vdda_ddr, vdda_debug, vdda_dsp_eve, vdda_gmac_core, vdda_gpu, vdda_iva, vdda_video, vdda_mpu, vdda_osc vdd_rtc(3) vdds_ddr2, vdds_ddr1, ddr1_vref0, ddr2_vref0 vdd vdd_mpu vdd_iva vdd_gpu vdd_dspeve vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_pcie1, vdda_sata, vdda_usb3 vddshv5(3) vddshv1, vddshv2, vddshv3, vddshv4, vddshv6, vddshv7, vddshv9, vddshv10, vddshv11 vdda33v_usb1, vdda33v_usb2 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Note 4 Note 5 Note 6 vddshv8 porz xi_osc0 Note 7 Note 9 Note 10 SPRS85v_ELCH_01 Figure 3-1. Power-Up Sequencing 1. Grey shaded areas are windows where it is valid to ramp the voltage rail. 2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note. 3. If RTC-mode is used then VDDA_RTC, VDD_RTC and VDDSHV5 must be individually powered with Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 189 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com separate power supplies and cannot be combined with other rails. 4. VDD must ramp before or at the same time as VDD_MPU, VDD_GPU, VDD_DSPEVE and VDD_IVA. 5. VDD_MPU, VDD_GPU, VDD_DSPEVE, VDD_IVA can be ramped at the same time or can be staggered. 6. If VDDSHV[1-7,9-11] (not including VDDSHV8) are used as 1.8V only, then these rails can be combined with VDDS18V. 7. VDDSHV8 is separated out to show support for dual voltage. If single voltage is used then VDDSHV8 can be combined with other VDDSHV* rails but VDDSHV8 must ramp after VDD. 8. VDDS and VDDA rails must not be combined together. 9. PORZ and RTC_PORZ can be de-asserted high 4096 SYS_CLKIN1 cycles after all supplies are ramped and stable. 10. If external oscillator is used to provide clock input to XI_OSC0, then this clock can turn on as long as the voltage supplies for the IOs are fully ramped. The external oscillator input to XI_OSC0 must be stable 5ms after PORZ is released. ADVANCE INFORMATION 190 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 EARLY PRELIMINARY ADVANCE INFORMATION porz vddshv8 vdda33v_usb1, vdda33v_usb2 vddshv1, vddshv2, vddshv3, vddshv4, vddshv6, vddshv7, vddshv9, vddshv10, vddshv11 vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_pcie1, vdda_sata, vdda_usb3 vddshv5(4) Note 5 Note 6 Note 8 Note 7 vdd_dspeve vdd_gpu vdd_iva vdd_mpu vdd vdds_ddr2, vdds_ddr1, ddr1_vref0, ddr2_vref0 vdda_abe_per, vdda_ddr, vdda_debug, vdda_dsp_eve, vdda_gmac_core, vdda_gpu, vdda_iva, vdda_video, vdda_mpu, vdda_osc vdd_rtc(4) vdds18v, vdds_mlbp, vdds18v_ddr1, vdds18v_ddr2 vdda_rtc(4) xi_osc0 Figure 3-2. Power-Down Sequencing SPRS85v_ELCH_02 1. XI_OSC0 can be turned off anytime after PORZ assertion and must be turned off before VDDA_OSC voltage rail is shutdown. 2. Grey shaded areas are windows where it is valid to ramp the voltage rail. 3. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 191 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 4. If RTC-mode is supported then VDDA_RTC, VDD_RTC and VDDSHV5 must be individually powered with separate power supplies and cannot be combined with other rails. 5. VDD_MPU, VDD_GPU, VDD_DSPEVE, VDD_IVA can be ramped at the same time or can be staggered. 6. VDD must ramp after or at the same time as VDD_MPU, VDD_GPU, VDD_DSPEVE and VDD_IVA. 7. If VDDSHV[1-7,9-11] (not including VDDSHV8) are used as 1.8V only, then these rails can be combined with VDDS18V 8. VDDSHV8 is separated out to show support for dual voltage. If single voltage is used then VDDSHV8 can be combined with other VDDSHV* rails but VDDSHV8 must ramp before VDD. Figure 3-3 describes the RTC-mode Power Sequencing. EARLY PRELIMINARY ADVANCE INFORMATION 192 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com vdds18v, vdds_mlbp, vdds18v_ddr1, vdds18v_ddr2 vdda_rtc vdda_abe_per, vdda_ddr, vdda_debug, vdda_dsp_eve, vdda_gmac_core, vdda_gpu, vdda_iva, vdda_video, vdda_mpu, vdda_osc vdd_rtc vdds_ddr2, vdds_ddr1, ddr1_vref0, ddr2_vref0 vdd vdd_mpu vdd_iva vdd_gpu TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Note 4 Note 3 Note 5 Note 4 R T C M O D E vdd_dspeve vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_pcie1, vdda_sata, vdda_usb3 vddshv5 vddshv1, vddshv2, vddshv3, vddshv4, vddshv6, vddshv7, vddshv9, vddshv10, vddshv11 Note 6 Note 6 vdda33v_usb1, vdda33v_usb2 vddshv8 Note 7 Note 7 SPRS85v_ELCH_03 Figure 3-3. RTC Mode Sequencing 1. Grey shaded areas are windows where it is valid to ramp the voltage rail. 2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note. 3. VDD must ramp down after or at the same time as VDD_MPU, VDD_GPU, VDD_DSPEVE and VDD_IVA. 4. VDD_MPU, VDD_GPU, VDD_DSPEVE, VDD_IVA can be ramped at the same time or can be Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 193 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com staggered. 5. VDD must ramp up before or at the same time as VDD_MPU, VDD_GPU, VDD_DSPEVE and VDD_IVA. 6. If VDDSHV[1-7,9-11] (not including VDDSHV8) are used as 1.8V only, then these rails can be combined with VDDS18V. 7. VDDSHV8 is separated out to show support for dual voltage. If single voltage is used then VDDSHV8 can be combined with other VDDSHV* rails but VDDSHV8 must ramp down before VDD and must ramp up after VDD. Figure 3-4 and Figure 3-5, describe the device Power Sequencing when RTC-mode is NOT used. Note 4 Note 5 ADVANCE INFORMATION vdda_abe_per, vdda_ddr, vdda_debug, vdda_dsp_eve, vdda_gmac_core, vdda_gpu, vdda_iva, vdda_video, vdda_mpu, vdda_osc vdds_ddr2, vdds_ddr1, ddr1_vref0, ddr2_vref0 vdd, vdd_rtc(3) vdd_mpu vdd_iva vdd_gpu vdd_dspeve vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_pcie1, vdda_sata, vdda_usb3 Note 6 vdda33v_usb1, vdda33v_usb2 vddshv8 porz Note 7 Note 9 Note 10 xi_osc0 Figure 3-4. Power-Up Sequencing SPRS85v_ELCH_04 1. Grey shaded areas are windows where it is valid to ramp the voltage rail. 2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note. 194 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 3. If RTC-mode is not used then the following combinations are approved: - VDDA_RTC can be combined with VDDS18V - VDD_RTC can be combined with VDD - VDDSHV5 can be combined with other 1.8V or 3.3V VDDSHV* rails If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements. 4. VDD must ramp before or at the same time as VDD_MPU, VDD_GPU, VDD_DSPEVE and VDD_IVA. 5. VDD_MPU, VDD_GPU, VDD_DSPEVE, VDD_IVA can be ramped at the same time or can be staggered. 6. If VDDSHV[1-7,9-11] (not including VDDSHV8) are used as 1.8V only, then these rails can be combined with VDDS18V 7. VDDSHV8 is separated out to show support for dual voltage. If single voltage is used then VDDSHV8 can be combined with other VDDSHV* rails but VDDSHV8 must ramp after VDD. 8. VDDS and VDDA rails must not be combined together, with the one exception of VDDA_RTC when RTC-mode is not supported. 9. PORZ and RTC_PORZ can be de-asserted high 4096 SYS_CLKIN1 cycles after all supplies are ramped and stable. 10. If external oscillator is used to provide clock input to XI_OSC0, then this clock can turn on as long as the voltage supplies for the IOs are fully ramped. The external oscillator input to XI_OSC0 must be stable 5ms after PORZ is released. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 195 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Note 5 Note 6 porz vddshv8 Note 8 vdda33v_usb1, vdda33v_usb2 Note 7 vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_pcie1, vdda_sata, vdda_usb3 vdd_dspeve vdd_gpu vdd_iva vdd_mpu vdd, vdd_rtc(4) vdds_ddr2, vdds_ddr1, ddr1_vref0, ddr2_vref0 vdda_abe_per, vdda_ddr, vdda_debug, vdda_dsp_eve, vdda_gmac_core, vdda_gpu, vdda_iva, vdda_video, vdda_mpu, vdda_osc www.ti.com ADVANCE INFORMATION xi_osc0 Figure 3-5. Power-Down Sequencing SPRS85v_ELCH_05 1. Grey shaded areas are windows where it is valid to ramp the voltage rail. 2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note. 3. XI_OSC0 can be turned off anytime after PORZ assertion and must be turned off before VDDA_OSC voltage rail is shutdown. 4. If RTC-mode is not used then the following combinations are approved: - VDDA_RTC can be combined with VDDS18V - VDD_RTC can be combined with VDD - VDDSHV5 can be combined with other 1.8V or 3.3V VDDSHV* rails If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements. 5. VDD_MPU, VDD_GPU, VDD_DSPEVE, VDD_IVA can be ramped at the same time or can be staggered. 196 Electrical Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 6. VDD must ramp after or at the same time as VDD_MPU, VDD_GPU, VDD_DSPEVE and VDD_IVA 7. If VDDSHV[1-7,9-11] (not including VDDSHV8) are used as 1.8V only, then these rails can be combined with VDDS18V 8. VDDSHV8 is separated out to show support for dual voltage. If single voltage is used then VDDSHV8 can be combined with other VDDSHV* rails but VDDSHV8 must ramp before VDD EARLY PRELIMINARY ADVANCE INFORMATION Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Electrical Characteristics 197 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 4 Clock Specifications www.ti.com NOTE For more information, see Power Reset and Clock Management / PRCM Environment / External Clock Signal and Power Reset / PRCM Functional Description / PRCM Clock Manager Functional Description section of the Device TRM. The device operation requires the following clocks: • The 32 kHz frequency is used for low frequency operation. It supplies the wake-up domain for operation in lowest power mode. This is an optional clock and will be supplied by on chip divider + mux (FUNC_32_CLK) incase it is not available on external pin. • The system clocks, SYS_CLKIN1(Mandatory) and SYS_CLKIN2(Optional) are the main clock sources of the device. They supply the reference clock to the DPLLs as well as functional clock to several modules. The Device also embeds an internal free-running 32-kHz oscillator that is always active as long as the the wake-up (WKUP) domain is supplied. Figure 4-1 shows the external input clock sources and the output clocks to peripherals. ADVANCE INFORMATION 198 Clock Specifications Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com DEVICE rtc_osc_xi_clkin32 rtc_osc_xo rstoutn resetn porz xi_osc0 xo_osc0 xi_osc1 xo_osc1 clkout1 clkout2 clkout3 xref_clk0 xref_clk1 xref_clk2 xref_clk3 sysboot[15:0] TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 From quartz (32 kHz) or from CMOS square clock source (32 kHz). To quartz (from oscillator output). Warm reset output. Device reset input. Power ON Reset. From quartz (19.2, 20, 26 or 27 MHz) or from CMOS square clock source (12, 16.8, 19.2, 20, 26, 27 or 38.4 MHz). To quartz (from oscillator output). From quartz (range from 19.2 to 32 MHz) or from CMOS square clock source(range from 12 to 38.4 MHz). To quartz (from oscillator output). Output clkout[3:1] clocks come from: • Either the input system clock and alternate clock (xi_osc0 or xi_osc1) • Or a CORE clock (from CORE output) • Or a 192-MHz clock (from PER DPLL output). External Reference Clock [3:0]. For Audio and other Peripherals Boot Mode Configuration Figure 4-1. Clock Interface 4.1 Input Clock Specifications 4.1.1 Input Clock Requirements • The source of the internal system clock (SYS_CLK1) could be either: – A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock case). – A crystal oscillator clock managed by xi_osc0 and xo_osc0. • The source of the internal system clock (SYS_CLK2) could be either: – A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock case). – A crystal oscillator clock managed by xi_osc1 and xo_osc1. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Clock Specifications 199 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com • The source of the internal system clock (SYS_32K) could be either: – A CMOS clock that enters on the rtc_osc_xi_clkin32 ball and supports external LVCMOS clock generators – A crystal oscillator clock managed by rtc_osc_xi_clkin32 and rtc_osc_xo. Table 4-1 illustrates the requirements to supply an input clock to the device. Table 4-1. Input Clock Requirements PAD rtc_osc_xi_clkin32 rtc_osc_xo xi_osc0 xo_osc0 xi_osc1 xo_osc1 CLOCK FREQUENCY 32.768 kHz 19.2, 20, 26, 27 MHz Crystal clock 12, 16.8, 19.2, 20, 26, 27 or External 38.4 MHz Clock Range from 19.2 to 32 MHz Crystal clock Range from 12 to 38.4 MHz External Clock STABILITY TBD TBD TBD TBD DUTY CYCLE - TBD NA TBD TBD TBD NA TBD JITTER - TBD NA NA TRANSITION TBD TBD NA TBD NA TBD 4.1.2 System Oscillator OSC0 Input Clock SYS_CLKIN1 is received directly from oscillator OSC0. For more information about SYS_CLKIN1 see Device TRM, Chapter: Power, Reset, and Clock Management. 4.1.2.1 OSC0 External Crystal An external crystal is connected to the device pins. Figure 4-2 describes the crystal implementation. ADVANCE INFORMATION Device xi_osc0 xo_osc0 vssa_osc0 Crystal Rd (Optional) Cf1 Cf2 Figure 4-2. Crystal Implementation NOTE vssa_osc0, Cf1 and Cf2 should NOT be connected to board ground (VSS) The crystal must be in the fundamental mode of operation and parallel resonant. Table 4-2 summarizes the required electrical constraints. Table 4-2. Crystal Electrical Characteristics NAME fp Cf1 Cf2 ESR(Cf1,Cf2) DESCRIPTION Parallel resonance crystal frequency Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2 Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2 Crystal ESR 200 Clock Specifications Submit Documentation Feedback MIN TYP MAX 19.2, 20, 26, 27 12 24 12 24 50 UNIT MHz pF pF Ω Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 4-2. Crystal Electrical Characteristics (continued) NAME CO LM CM DL DESCRIPTION MIN Crystal shunt capacitance ESR=30 Ω ESR=40 Ω ESR=50 Ω Crystal motional inductance for fp = 12 MHz Crystal motional capacitance 19.2MHz≤fp≤27MHz 19.2MHz≤fp≤27MHz 19.2MHz≤fp≤25MHz 25MHz 1, the minimum frequency on these clocks will further scale down by factor of M2. (2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1. (3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down by factor of M3. (4) The maximum frequency on CLKOUTHIF is assuming M3 = 1. (5) Relock time assumes typical operating conditions, 10°C maximum temperature drift. (6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM. ADVANCE INFORMATION 210 Clock Specifications Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 4-16. DPLL Type B Characteristics NAME finput finternal fCLKINPULOW fCLKLDOOUT fCLKOUT fCLKDCOLDO tJ tlock DESCRIPTION CLKINP input clock frequency REFCLK internal reference clock frequency CLKINPULOW bypass input clock frequency CLKOUTLDO output clock frequency CLKOUT output clock frequency Internal oscillator (DCO) output clock frequency CLKOUTLDO period jitter CLKOUT period jitter CLKDCOLDO period jitter Frequency lock time plock trelock-L prelock-L Phase lock time Relock time—Frequency lock(3) (LP relock time from bypass) Relock time—Phase lock(3) (LP relock time from bypass) MIN 0.62 0.62 0.001 20(1)(5) 20(1)(5) 750(5) 1250(5) –2.5% TYP MAX 60 2.5 600 2500(2)(5) 1450(2)(5) 1500(5) 2500(5) 2.5% 350 × REFCLKs 500 × REFCLKs 9 + 30 × REFCLKs 9 + 125 × REFCLKs UNIT MHz MHz MHz MHz MHz MHz MHz COMMENTS FINP [1 / (N + 1)] × FINP Bypass mode: fCLKOUT = fCLKINPULOW / (M1 + 1) If ulowclken = 1(4) M / (N + 1)] × FINP × [1 / M2] (in locked condition) [M / (N + 1)] × FINP × [1 / M2] (in locked condition) [M / (N + 1)] × FINP (in locked condition) The period jitter at the output clocks is ± 2.5% peak to peak µs µs µs µs (1) The minimum frequency on CLKOUT is assuming M2 = 1. For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2. (2) The maximum frequency on CLKOUT is assuming M2 = 1. (3) Relock time assumes typical operating conditions, 10°C maximum temperature drift. (4) Bypass mode: fCLKOUT = FINP if ULOWCLKEN = 0. For more information, see the Device TRM. (5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Clock Specifications 211 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 4.2.2.2 DLL Characteristics Table 4-17 summarizes the DLL characteristics and assumes testing over recommended operating conditions. Table 4-17. DLL Characteristics NAME DESCRIPTION MIN TYP MAX UNIT finput tlock trelock Input clock frequency (EMIF_DLL_FCLK) Lock time Relock time (a change of the DLL frequency implies that DLL must relock) 266 TBD TBD MHz cycles cycles (1) See the operating condition addendum for values. OPP voltage values may change following the silicon characterization result. 4.2.2.3 DPLL and DLL Noise Isolation NOTE For more information on DPLL and DLL decoupling capacitor requirements, see the External Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA Power Domain section. 4.2.3 Internal 32-kHz Oscillator An internal 32-kHz oscillator is implemented in the wake-up domain. Table 4-18 gives the internal 32-kHz oscillator characteristics. NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. Table 4-18. Internal 32-kHz Oscillator Characteristic PARAMETER Internal 32-kHz oscillator frequency MIN TBD TYP 32.768 MAX TBD UNIT kHz ADVANCE INFORMATION 212 Clock Specifications Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 5 Timing Requirements and Switching Characteristics 5.1 Timing Test Conditions All timing requirements and switching characteristics are valid over the recommended operating conditions unless otherwise specified. 5.2 Interface Clock Specifications 5.2.1 Interface Clock Terminology The interface clock is used at the system level to sequence the data and/or to control transfers accordingly with the interface protocol. 5.2.2 Interface Clock Frequency The two interface clock characteristics are: • The maximum clock frequency • The maximum operating frequency The interface clock frequency documented in this document is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. This frequency defines the maximum limit supported by the Device IC and does not take into account any system consideration (PCB, peripherals). The system designer will have to consider these system considerations and the Device IC timing characteristics as well to define properly the maximum operating frequency that corresponds to the maximum frequency supported to transfer the data on this interface. 5.2.3 Clock Jitter Specifications Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this document is the time difference between the typical cycle period and the actual cycle period affected by noise sources on the clock. The cycle (or period) jitter terminology will be used to identify this type of jitter. tn–1 tn tn+1 Figure 5-1. Cycle (or Period) Jitter TIMING_01 Jitter values are defined as follows: • Ideal clock period = tp • Maximum Cycle/Period Jitter = Max (|ti – tp|), with i = n – 1, n, n + 1, … • Minimum Cycle/Period Jitter = Min (|ti – tp|) • Jitter Standard Deviation (or RMS Jitter) = Standard Deviation (|ti – tp|) Unless otherwise specified, the jitter probability density can be approximated by a Gaussian function and peak-to-peak jitter is defined over a ±7 sigma distribution of this function. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 213 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 5.2.4 Clock Duty Cycle Error The maximum duty cycle error is the difference between the absolute value of the maximum high-level pulse duration or the maximum low-level pulse duration and the typical pulse duration value: • Maximum pulse duration = typical pulse duration + maximum duty cycle error • Minimum pulse duration = typical pulse duration – maximum duty cycle error In this document, the clock duty cycle can be documented as maximum pulse duration or as maximum duty cycle error. In this case, you can consider: • Maximum duty cycle error = maximum [(maximum pulse duration – typical pulse duration) or (typical pulse duration – minimum pulse duration)] 5.3 Timing Parameters The timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other related terminologies have been abbreviated as follows: Table 5-1. Timing Parameters SYMBOL c d dis en h su START t v w X F H L R V IV AE FE LE Z SUBSCRIPTS PARAMETER Cycle time (period) Delay time Disable time Enable time Hold time Setup time Start bit Transition time Valid time Pulse duration (width) Unknown, changing, or don't care level Fall time High Low Rise time Valid Invalid Active Edge First Edge Last Edge High impedance 214 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 5.4 Video Input Ports (VIP) The Device includes 3 Video Input Ports (VIP) Table 5-2, Figure 5-2 and Figure 5-3 Presents timings and switching characteristics of the VIPs CAUTION The IO timings provided in this section are applicable for all combinations of signals for vin1, vin5 and vin6. However, the timings are only valid for vin2, vin3, and vin4 if signals within a single IOSET are used. The IOSETs are defined in the Table 5-3. Table 5-2. Timing Requirements for VIP (1)(2) NO. PARAMETER DESCRIPTION V1 tc(CLK) Cycle time, vinx_clki(3)(5) V2 tw(CLKH) Pulse duration, vinx_clki high(3)(5) V3 tw(CLKL) Pulse duration, vinx_clki low(3)(5) V4 tsu(CTL/DATA-CLK) Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3)(4)(5) V6 th(CLK-CTL/DATA) Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid from vinx_clki transition(3)(4)(5) (1) For maximum frequency of 165 MHZ (2) P = vinx_clki period. (3) x in vinx = 1a, 1b, 2a, 2b, 3a, 3b, 4a, 4b, 5a and 6a. (4) n in dn = 0 to 7 when x = 1b, 2b, 3b and 4b; n = 0 to 15 when x = 5a and 6a; n = 0 to 23 when x = 1a, 2a, 3a and 4a; (5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1. MIN 6.06 (1) 0.45*P (2) 0.45*P (2) 3.11 -0.05 V2 V1 vinx_clki MAX UNIT ns ns ns ns ns V3 Figure 5-2. Video Input Ports clock signal SPRS8xx_VIP_01 vinx_clki (positive-edge clocking) vinx_clki (negative-edge clocking) vinx_d[23:0]/sig V5 V4 Figure 5-3. Video Input Ports timings SPRS8xx_VIP_02 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 215 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com In Table 5-3 are presented the specific groupings of signals (IOSET) for use with vin2, vin3, and vin4. Table 5-3. VIN2/3/4 IOSETs Signals IOSET1 BALL MUX vin*a_d0 F2 0 vin*a_d1 F3 0 vin*a_d2 D1 0 vin*a_d3 E2 0 vin*a_d4 D2 0 vin*a_d5 F4 0 vin*a_d6 C1 0 vin*a_d7 E4 0 vin*a_d8 F5 0 vin*a_d9 E6 0 vin*a_d10 D3 0 vin*a_d11 F6 0 vin*a_d12 D5 0 vin*a_d13 C2 0 vin*a_d14 C3 0 vin*a_d15 C4 0 vin*a_d16 B2 0 vin*a_d17 D6 0 vin*a_d18 C5 0 vin*a_d19 A3 0 vin*a_d20 B3 0 vin*a_d21 B4 0 vin*a_d22 B5 0 vin*a_d23 A4 0 vin*a_hsync0 G1 0 vin*a_vsync0 G6 0 vin*a_de0 G2 0 vin*a_fld0 H7 0 VIN2 IOSET2 BALL MUX F2 0 F3 0 D1 0 E2 0 D2 0 F4 0 C1 0 E4 0 F5 0 E6 0 D3 0 F6 0 D5 0 C2 0 C3 0 C4 0 B2 0 D6 0 C5 0 A3 0 B3 0 B4 0 B5 0 A4 0 G1 0 G6 0 - - G2 1 IOSET3 BALL MUX U4 4 V2 4 Y1 4 W9 4 V9 4 U5 4 V5 4 V4 4 V3 4 Y2 4 U6 4 U3 4 - - - - - - - - - - - - - - - - - - - - - - - - U7 4 V6 4 V7 4 W2 4 IOSET1 BALL MUX M6 2 M2 2 L5 2 M1 2 L6 2 L4 2 L3 2 L2 2 L1 2 K2 2 J1 2 J2 2 H1 2 J3 2 H2 2 H3 2 R6 2 T9 2 T6 2 T7 2 P6 2 R9 2 R5 2 P5 2 N7 2 R4 2 N9 2 P9 2 VIN3 IOSET2 IOSET3 BALL MUX BALL MUX VIN*a AF1 6 AF1 6 AE3 6 AE3 6 AE5 6 AE5 6 AE1 6 AE1 6 AE2 6 AE2 6 AE6 6 AE6 6 AD2 6 AD2 6 AD3 6 AD3 6 B2 6 B2 6 D6 6 D6 6 C5 6 C5 6 A3 6 A3 6 B3 6 - - B4 6 - - B5 6 - - A4 6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N7 2 B5 5 R4 2 A4 5 N9 2 B3 5 P9 2 B4 5 IOSET4 IOSET1 BALL MUX BALL MUX B7 4 R6 4 B8 4 T9 4 A7 4 T6 4 A8 4 T7 4 C9 4 P6 4 A9 4 R9 4 B9 4 R5 4 A10 4 P5 4 E8 4 U2 4 D9 4 U1 4 D7 4 P3 4 D8 4 R2 4 A5 4 K7 4 C6 4 M7 4 C8 4 J5 4 C7 4 K6 4 F11 4 - - G10 4 - - F10 4 - - G11 4 - - E9 4 - - F9 4 - - F8 4 - - E7 4 - - C11 4 R3/ P7 4 / 4 E11 4 T2/ N1 4 / 4 B10 4 H6/ P7 4 / 5 D11 4 P9/ J7 4 / 4 VIN4 IOSET2 BALL MUX B7 3 B8 3 A7 3 A8 3 C9 3 A9 3 B9 3 A10 3 E8 3 D9 3 D7 3 D8 3 A5 3 C6 3 C8 3 C7 3 F11 3 G10 3 F10 3 G11 3 E9 3 F9 3 F8 3 E7 3 C11 3 E11 3 B10 3 D11 3 IOSET3 BALL MUX B14 8 J14 8 G13 8 J11 8 E12 8 F13 8 C12 8 D12 8 E15 8 A20 8 B15 8 A15 8 D15 8 B16 8 B17 8 A17 8 - - - - - - - - - - - - - - - - E21 8 F20 8 C23 8 F21 8 216 Timing Requirements and Switching Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Signals vin*a_clk0 IOSET1 BALL MUX E1 0 vin*b_clk1 H7 2 vin*b_de1 - - vin*b_fld1 G2 2 vin*b_d0 A4 2 vin*b_d1 B5 2 vin*b_d2 B4 2 vin*b_d3 B3 2 vin*b_d4 A3 2 vin*b_d5 C5 2 vin*b_d6 D6 2 vin*b_d7 B2 2 vin*b_hsync1 G1 3 vin*b_vsync1 G6 3 VIN2 IOSET2 BALL MUX E1 0 H7 2 G2 3 - - A4 2 B5 2 B4 2 B3 2 A3 2 C5 2 D6 2 B2 2 G1 3 G6 3 IOSET3 BALL MUX V1 4 AB5 4 AB8 4 - - AD6 4 AC8 4 AC3 4 AC9 4 AC6 4 AC7 4 AC4 4 AD4 4 AC5 4 AB4 4 Table 5-3. VIN2/3/4 IOSETs (continued) IOSET1 BALL MUX P1 2 P7 6 N6 6 M4 6 K7 6 M7 6 J5 6 K6 6 J7 6 J4 6 J6 6 H4 6 H5 6 H6 6 VIN3 IOSET2 IOSET3 BALL MUX BALL MUX AH7 6 AH7 6 VIN*b M4 4 - - N6 6 - - - - - - K7 6 - - M7 6 - - J5 6 - - K6 6 - - J7 6 - - J4 6 - - J6 6 - - H4 6 - - H5 6 - - H6 6 - - IOSET4 BALL MUX B11 4 - - - - - - - - - - - - - - - - - - - - - - - - - - IOSET1 BALL MUX P4 4 N9 6 P9 6 P4 6 R6 6 T9 6 T6 6 T7 6 P6 6 R9 6 R5 6 P5 6 N7 6 R4 6 VIN4 IOSET2 BALL MUX B11 3 V1 5 V7 5 W2 5 U4 5 V2 5 Y1 5 W9 5 V9 5 U5 5 V5 5 V4 5 U7 5 V6 5 IOSET3 BALL MUX B26 8 - - - - - - - - - - - - - - - - - - - - - - - - - - Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Timing Requirements and Switching Characteristics 217 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY ADVANCE INFORMATION NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 2-3 and described in Device TRM, Chapter 18 - Control Module. The IO timings in data manual for VIN1A, VIN1B and VIN2A Fall-edge Capture Mode are guarantee if VIP1_VIRTUAL1 virtual mode is configured. Table 5-4 present the values for DELAYMODE bitfield. Table 5-4. Virtual Functions Mapping for VIP1-1a,1b,2a BALL BALL NAME Delay Mode Value MUXMODE[15:0] NUMBER VIP1_VIRTUAL1 0 1 3 4 N6 gpmc_ben0 15 vin1b_hsync1 M4 gpmc_ben1 15 vin1b_de1 AG8 vin1a_clk0 15 vin1a_clk0 AH7 vin1b_clk1 15 vin1b_clk1 AD9 vin1a_de0 15 vin1a_de0 vin1b_hsync1 AF9 vin1a_fld0 15 vin1a_fld0 vin1b_vsync1 AE9 vin1a_hsync0 15 vin1a_hsync0 vin1b_fld1 AF8 vin1a_vsync0 15 vin1a_vsync0 vin1b_de1 AE8 vin1a_d0 15 vin1a_d0 AD8 vin1a_d1 15 vin1a_d1 AG7 vin1a_d2 15 vin1a_d2 AH6 vin1a_d3 14 vin1a_d3 AH3 vin1a_d4 15 vin1a_d4 AH5 vin1a_d5 14 vin1a_d5 AG6 vin1a_d6 14 vin1a_d6 AH4 vin1a_d7 14 vin1a_d7 AG4 vin1a_d8 15 vin1a_d8 vin1b_d7 AG2 vin1a_d9 15 vin1a_d9 vin1b_d6 AG3 vin1a_d10 15 vin1a_d10 vin1b_d5 AG5 vin1a_d11 14 vin1a_d11 vin1b_d4 AF2 vin1a_d12 14 vin1a_d12 vin1b_d3 AF6 vin1a_d13 15 vin1a_d13 vin1b_d2 AF3 vin1a_d14 14 vin1a_d14 vin1b_d1 AF4 vin1a_d15 14 vin1a_d15 vin1b_d0 AF1 vin1a_d16 14 vin1a_d16 vin1b_d7 AE3 vin1a_d17 14 vin1a_d17 vin1b_d6 AE5 vin1a_d18 14 vin1a_d18 vin1b_d5 AE1 vin1a_d19 14 vin1a_d19 vin1b_d4 AE2 vin1a_d20 14 vin1a_d20 vin1b_d3 AE6 vin1a_d21 14 vin1a_d21 vin1b_d2 AD2 vin1a_d22 14 vin1a_d22 vin1b_d1 AD3 vin1a_d23 14 vin1a_d23 vin1b_d0 E1 vin2a_clk0 15 vin2a_clk0 G2 vin2a_de0 14 vin2a_de0 vin2a_fld0 H7 vin2a_fld0 14 vin2a_fld0 218 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 BALL NUMBER G1 G6 F2 F3 D1 E2 D2 F4 C1 E4 F5 E6 D3 F6 D5 C2 C3 C4 B2 D6 C5 A3 B3 B4 B5 A4 V1 U4 U3 V2 Y1 W9 V9 V7 U7 V6 U6 U5 V5 V4 V3 Y2 W2 Table 5-4. Virtual Functions Mapping for VIP1-1a,1b,2a (continued) BALL NAME vin2a_hsync0 vin2a_vsync0 vin2a_d0 vin2a_d1 vin2a_d2 vin2a_d3 vin2a_d4 vin2a_d5 vin2a_d6 vin2a_d7 vin2a_d8 vin2a_d9 vin2a_d10 vin2a_d11 vin2a_d12 vin2a_d13 vin2a_d14 vin2a_d15 vin2a_d16 vin2a_d17 vin2a_d18 vin2a_d19 vin2a_d20 vin2a_d21 vin2a_d22 vin2a_d23 mdio_mclk mdio_d RMII_MHZ_50_C LK uart3_rxd uart3_txd rgmii0_txc rgmii0_txctl rgmii0_txd3 rgmii0_txd2 rgmii0_txd1 rgmii0_txd0 rgmii0_rxc rgmii0_rxctl rgmii0_rxd3 rgmii0_rxd2 rgmii0_rxd1 rgmii0_rxd0 Delay Mode Value VIP1_VIRTUAL1 14 14 15 15 15 14 14 14 14 14 14 14 14 14 14 14 15 14 9 9 9 9 9 10 10 10 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 0 vin2a_hsync0 vin2a_vsync0 vin2a_d0 vin2a_d1 vin2a_d2 vin2a_d3 vin2a_d4 vin2a_d5 vin2a_d6 vin2a_d7 vin2a_d8 vin2a_d9 vin2a_d10 vin2a_d11 vin2a_d12 vin2a_d13 vin2a_d14 vin2a_d15 vin2a_d16 vin2a_d17 vin2a_d18 vin2a_d19 vin2a_d20 vin2a_d21 vin2a_d22 vin2a_d23 MUXMODE[15:0] 1 3 4 vin2a_clk0 vin2a_d0 vin2a_d11 vin2a_d1 vin2a_d2 vin2a_d3 vin2a_d4 vin2a_de0 vin2a_hsync0 vin2a_vsync0 vin2a_d10 vin2a_d5 vin2a_d6 vin2a_d7 vin2a_d8 vin2a_d9 vin2a_fld0 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 219 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com The IO timings in data manual for VIN2B Fall-edge Capture Mode are guarantee if VIP1_2B_VIRTUAL1 virtual mode is configured. Table 5-5 present the values for DELAYMODE bitfield. Table 5-5. Virtual Functions Mapping for VIP1-2b BALL NUMBER G2 H7 G1 G6 B2 D6 C5 A3 B3 B4 B5 A4 AC5 AB4 AD4 AC4 AC7 AC6 AC9 AC3 AC8 AD6 AB8 AB5 BALL NAME vin2a_de0 vin2a_fld0 vin2a_hsync0 vin2a_vsync0 vin2a_d16 vin2a_d17 vin2a_d18 vin2a_d19 vin2a_d20 vin2a_d21 vin2a_d22 vin2a_d23 gpio6_10 gpio6_11 mmc3_clk mmc3_cmd mmc3_dat0 mmc3_dat1 mmc3_dat2 mmc3_dat3 mmc3_dat4 mmc3_dat5 mmc3_dat6 mmc3_dat7 Delay Mode Value VIP1_2B_VIRTUAL1 15 15 15 15 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 2 vin2b_fld1 vin2b_clk1 vin2b_d7 vin2b_d6 vin2b_d5 vin2b_d4 vin2b_d3 vin2b_d2 vin2b_d1 vin2b_d0 MUXMODE[15:0] 3 4 vin2b_de1 vin2b_hsync1 vin2b_vsync1 vin2b_hsync1 vin2b_vsync1 vin2b_d7 vin2b_d6 vin2b_d5 vin2b_d4 vin2b_d3 vin2b_d2 vin2b_d1 vin2b_d0 vin2b_de1 vin2b_clk1 ADVANCE INFORMATION 220 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 The IO timings in data manual for VIN3B with gpmc_ben1 signal working as clock are guarantee if VIP2_VIRTUAL1 virtual mode is configured. The IO timings in data manual for VIN3A, 3B Fall-Edge Capture Mode are guarantee if VIP2_VIRTUAL2 virtual mode is configured. The IO timings in data manual for VIN3B with gpmc_ben1 signal working as clock in Fall-Edge Capture Mode are guarantee if VIP2_VIRTUAL3 virtual mode is configured. Table 5-6 present the values for DELAYMODE bitfield. Table 5-6. Virtual Functions Mapping for VIP2-3a,3b BALL BALL NAME Delay Mode Value MUXMODE[15:0] NUMBER VIP2_3x_VIRTUAL1 VIP2_3x_VIRTUAL2 VIP2_3x_VIRTUAL3 2 4 5 6 M6 gpmc_ad0 N/A 13 N/A vin3a_d0 M2 gpmc_ad1 N/A 13 N/A vin3a_d1 L5 gpmc_ad2 N/A 13 N/A vin3a_d2 M1 gpmc_ad3 N/A 13 N/A vin3a_d3 L6 gpmc_ad4 N/A 13 N/A vin3a_d4 L4 gpmc_ad5 N/A 13 N/A vin3a_d5 L3 gpmc_ad6 N/A 13 N/A vin3a_d6 L2 gpmc_ad7 N/A 13 N/A vin3a_d7 L1 gpmc_ad8 N/A 13 N/A vin3a_d8 K2 gpmc_ad9 N/A 13 N/A vin3a_d9 J1 gpmc_ad10 N/A 13 N/A vin3a_d10 J2 gpmc_ad11 N/A 13 N/A vin3a_d11 H1 gpmc_ad12 N/A 13 N/A vin3a_d12 J3 gpmc_ad13 N/A 13 N/A vin3a_d13 H2 gpmc_ad14 N/A 13 N/A vin3a_d14 H3 gpmc_ad15 N/A 13 N/A vin3a_d15 R6 gpmc_a0 N/A 13 N/A vin3a_d16 T9 gpmc_a1 N/A 13 N/A vin3a_d17 T6 gpmc_a2 N/A 13 N/A vin3a_d18 T7 gpmc_a3 N/A 13 N/A vin3a_d19 P6 gpmc_a4 N/A 13 N/A vin3a_d20 R9 gpmc_a5 N/A 13 N/A vin3a_d21 R5 gpmc_a6 N/A 13 N/A vin3a_d22 P5 gpmc_a7 N/A 13 N/A vin3a_d23 N7 gpmc_a8 N/A 14 N/A vin3a_hsync0 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Timing Requirements and Switching Characteristics 221 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 BALL NUMBER R4 N9 P9 K7 M7 J5 K6 J7 J4 J6 H4 H5 H6 P1 P7 N6 M4 AH7 AF1 AE3 AE5 AE1 AE2 AE6 AD2 AD3 B2 D6 C5 A3 B3 B4 BALL NAME gpmc_a9 gpmc_a10 gpmc_a11 gpmc_a19 gpmc_a20 gpmc_a21 gpmc_a22 gpmc_a23 gpmc_a24 gpmc_a25 gpmc_a26 gpmc_a27 gpmc_cs1 gpmc_cs3 gpmc_clk gpmc_ben0 gpmc_ben1 vin1b_clk1 vin1a_d16 vin1a_d17 vin1a_d18 vin1a_d19 vin1a_d20 vin1a_d21 vin1a_d22 vin1a_d23 vin2a_d16 vin2a_d17 vin2a_d18 vin2a_d19 vin2a_d20 vin2a_d21 Table 5-6. Virtual Functions Mapping for VIP2-3a,3b (continued) VIP2_3x_VIRTUAL1 N/A N/A N/A 14 14 14 14 14 14 14 14 14 14 N/A N/A 14 14 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Delay Mode Value VIP2_3x_VIRTUAL2 14 14 13 13 13 13 13 13 13 13 13 13 13 15 13 13 13 14 9 9 9 9 9 9 9 9 5 5 5 5 1 9 VIP2_3x_VIRTUAL3 N/A N/A N/A 12 12 12 12 12 12 12 12 12 12 N/A N/A 12 12 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 2 vin3a_vsync0 vin3a_de0 vin3a_fld0 vin3a_clk0 MUXMODE[15:0] 4 5 vin3b_clk1 vin3a_de0 vin3a_fld0 www.ti.com 6 vin3b_d0 vin3b_d1 vin3b_d2 vin3b_d3 vin3b_d4 vin3b_d5 vin3b_d6 vin3b_d7 vin3b_hsync1 vin3b_vsync1 vin3b_clk1 vin3b_de1 vin3b_fld1 vin3a_clk0 vin3a_d0 vin3a_d1 vin3a_d2 vin3a_d3 vin3a_d4 vin3a_d5 vin3a_d6 vin3a_d7 vin3a_d8 vin3a_d9 vin3a_d10 vin3a_d11 vin3a_d12 vin3a_d13 222 Timing Requirements and Switching Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com BALL NUMBER B5 A4 D11 B10 B11 C11 E11 F11 G10 F10 G11 E9 F9 F8 E7 E8 D9 D7 D8 A5 C6 C8 C7 B7 B8 A7 A8 C9 A9 B9 A10 BALL NAME vin2a_d22 vin2a_d23 vout1_clk vout1_de vout1_fld vout1_hsync vout1_vsync vout1_d0 vout1_d1 vout1_d2 vout1_d3 vout1_d4 vout1_d5 vout1_d6 vout1_d7 vout1_d8 vout1_d9 vout1_d10 vout1_d11 vout1_d12 vout1_d13 vout1_d14 vout1_d15 vout1_d16 vout1_d17 vout1_d18 vout1_d19 vout1_d20 vout1_d21 vout1_d22 vout1_d23 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-6. Virtual Functions Mapping for VIP2-3a,3b (continued) Delay Mode Value MUXMODE[15:0] VIP2_3x_VIRTUAL1 VIP2_3x_VIRTUAL2 VIP2_3x_VIRTUAL3 2 4 5 N/A 9 N/A vin3a_hsync0 N/A 9 N/A vin3a_vsync0 N/A 14 N/A vin3a_fld0 N/A 14 N/A vin3a_de0 N/A 14 N/A vin3a_clk0 N/A 14 N/A vin3a_hsync0 N/A 14 N/A vin3a_vsync0 N/A 11 N/A vin3a_d16 N/A 11 N/A vin3a_d17 N/A 11 N/A vin3a_d18 N/A 11 N/A vin3a_d19 N/A 14 N/A vin3a_d20 N/A 11 N/A vin3a_d21 N/A 14 N/A vin3a_d22 N/A 11 N/A vin3a_d23 N/A 11 N/A vin3a_d8 N/A 11 N/A vin3a_d9 N/A 14 N/A vin3a_d10 N/A 11 N/A vin3a_d11 N/A 11 N/A vin3a_d12 N/A 11 N/A vin3a_d13 N/A 11 N/A vin3a_d14 N/A 11 N/A vin3a_d15 N/A 9 N/A vin3a_d0 N/A 9 N/A vin3a_d1 N/A 9 N/A vin3a_d2 N/A 14 N/A vin3a_d3 N/A 9 N/A vin3a_d4 N/A 14 N/A vin3a_d5 N/A 9 N/A vin3a_d6 N/A 9 N/A vin3a_d7 6 vin3a_d14 vin3a_d15 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Timing Requirements and Switching Characteristics 223 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 1. NA in this table stands for Not Applicable. The IO timings in data manual for VIN4A and VIN4B Fall-Edge Capture Mode are guarantee if VIP2_4A_VIRTUAL1 and VIP2_4B_VIRTUAL1 virtual mode is configured. Table 5-7 present the values for DELAYMODE bitfield. Table 5-7. Virtual Functions Mapping for VIP2-4a,4b BALL BALL NAME Delay Mode Value MUXMODE[15:0] NUMBER VIP2_4A_VIRTUAL2 VIP2_4B_VIRTUAL2 3 4 5 6 8 R6 gpmc_a0 N/A 14 vin4b_d0 T9 gpmc_a1 N/A 14 vin4b_d1 T6 gpmc_a2 N/A 14 vin4b_d2 T7 gpmc_a3 N/A 14 vin4b_d3 P6 gpmc_a4 N/A 14 vin4b_d4 R9 gpmc_a5 N/A 14 vin4b_d5 R5 gpmc_a6 N/A 14 vin4b_d6 P5 gpmc_a7 N/A 14 vin4b_d7 N7 gpmc_a8 N/A 15 vin4b_hsync1 R4 gpmc_a9 N/A 15 vin4b_vsync1 N9 gpmc_a10 N/A 15 vin4b_clk1 P9 gpmc_a11 N/A 14 vin4b_de1 P4 gpmc_a12 N/A 14 vin4b_fld1 R6 gpmc_a0 15 N/A vin4a_d0 T9 gpmc_a1 15 N/A vin4a_d1 T6 gpmc_a2 15 N/A vin4a_d2 T7 gpmc_a3 15 N/A vin4a_d3 P6 gpmc_a4 15 N/A vin4a_d4 R9 gpmc_a5 15 N/A vin4a_d5 R5 gpmc_a6 15 N/A vin4a_d6 P5 gpmc_a7 15 N/A vin4a_d7 P9 gpmc_a11 15 N/A vin4a_fld0 P4 gpmc_a12 15 N/A vin4a_clk0 R3 gpmc_a13 13 N/A vin4a_hsync0 T2 gpmc_a14 13 N/A vin4a_vsync0 U2 gpmc_a15 13 N/A vin4a_d8 224 Timing Requirements and Switching Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com BALL NUMBER U1 P3 R2 K7 M7 J5 K6 J7 J4 J6 H4 H5 H6 P7 N1 D11 B10 B11 C11 E11 F11 G10 F10 G11 E9 F9 F8 E7 E8 D9 D7 D8 BALL NAME gpmc_a16 gpmc_a17 gpmc_a18 gpmc_a19 gpmc_a20 gpmc_a21 gpmc_a22 gpmc_a23 gpmc_a24 gpmc_a25 gpmc_a26 gpmc_a27 gpmc_cs1 gpmc_clk gpmc_advn_ale vout1_clk vout1_de vout1_fld vout1_hsync vout1_vsync vout1_d0 vout1_d1 vout1_d2 vout1_d3 vout1_d4 vout1_d5 vout1_d6 vout1_d7 vout1_d8 vout1_d9 vout1_d10 vout1_d11 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-7. Virtual Functions Mapping for VIP2-4a,4b (continued) Delay Mode Value MUXMODE[15:0] VIP2_4A_VIRTUAL2 VIP2_4B_VIRTUAL2 3 4 5 6 8 13 N/A vin4a_d9 13 N/A vin4a_d10 15 N/A vin4a_d11 15 N/A vin4a_d12 15 N/A vin4a_d13 15 N/A vin4a_d14 15 N/A vin4a_d15 15 N/A vin4a_fld0 15 N/A vin4a_d8 15 N/A vin4a_d9 15 N/A vin4a_d10 15 N/A vin4a_d11 15 N/A vin4a_de0 14 N/A vin4a_hsync0 vin4a_de0 14 N/A vin4a_vsync0 15 N/A vin4a_fld0 15 N/A vin4a_de0 15 N/A vin4a_clk0 15 N/A vin4a_hsync0 15 N/A vin4a_vsync0 14 N/A vin4a_d16 14 N/A vin4a_d17 14 N/A vin4a_d18 14 N/A vin4a_d19 15 N/A vin4a_d20 14 N/A vin4a_d21 15 N/A vin4a_d22 14 N/A vin4a_d23 14 N/A vin4a_d8 14 N/A vin4a_d9 15 N/A vin4a_d10 14 N/A vin4a_d11 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Timing Requirements and Switching Characteristics 225 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-7. Virtual Functions Mapping for VIP2-4a,4b (continued) BALL NUMBER A5 C6 C8 C7 B7 B8 A7 A8 C9 A9 B9 A10 V1 U4 V2 Y1 W9 V9 V7 U7 V6 U5 V5 V4 W2 E21 F20 F21 B26 C23 B14 J14 BALL NAME vout1_d12 vout1_d13 vout1_d14 vout1_d15 vout1_d16 vout1_d17 vout1_d18 vout1_d19 vout1_d20 vout1_d21 vout1_d22 vout1_d23 mdio_mclk mdio_d uart3_rxd uart3_txd rgmii0_txc rgmii0_txctl rgmii0_txd3 rgmii0_txd2 rgmii0_txd1 rgmii0_rxc rgmii0_rxctl rgmii0_rxd3 rgmii0_rxd0 gpio6_14 gpio6_15 gpio6_16 xref_clk2 xref_clk3 mcasp1_aclkr mcasp1_fsr Delay Mode Value VIP2_4A_VIRTUAL2 VIP2_4B_VIRTUAL2 14 N/A 14 N/A 14 N/A 14 N/A 14 N/A 14 N/A 14 N/A 15 N/A 14 N/A 15 N/A 14 N/A 14 N/A N/A 10 N/A 10 N/A 10 N/A 10 N/A 10 N/A 10 N/A 10 N/A 10 N/A 10 N/A 10 N/A 10 N/A 10 N/A 10 13 N/A 13 N/A 13 N/A 9 N/A 9 N/A 13 N/A 13 N/A 3 vin4a_d12 vin4a_d13 vin4a_d14 vin4a_d15 vin4a_d0 vin4a_d1 vin4a_d2 vin4a_d3 vin4a_d4 vin4a_d5 vin4a_d6 vin4a_d7 MUXMODE[15:0] 4 5 6 vin4b_clk1 vin4b_d0 vin4b_d1 vin4b_d2 vin4b_d3 vin4b_d4 vin4b_de1 vin4b_hsync1 vin4b_vsync1 vin4b_d5 vin4b_d6 vin4b_d7 vin4b_fld1 www.ti.com 8 vin4a_hsync0 vin4a_vsync0 vin4a_fld0 vin4a_clk0 vin4a_de0 vin4a_d0 vin4a_d1 226 Timing Requirements and Switching Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-7. Virtual Functions Mapping for VIP2-4a,4b (continued) BALL BALL NAME Delay Mode Value NUMBER VIP2_4A_VIRTUAL2 VIP2_4B_VIRTUAL2 3 G13 mcasp1_axr2 12 N/A J11 mcasp1_axr3 12 N/A E12 mcasp1_axr4 12 N/A F13 mcasp1_axr5 12 N/A C12 mcasp1_axr6 12 N/A D12 mcasp1_axr7 12 N/A E15 mcasp2_aclkr 12 N/A A20 mcasp2_fsr 12 N/A B15 mcasp2_axr0 11 N/A A15 mcasp2_axr1 11 N/A D15 mcasp2_axr4 10 N/A B16 mcasp2_axr5 10 N/A B17 mcasp2_axr6 10 N/A A17 mcasp2_axr7 10 N/A C18 mcasp4_aclkx 14 N/A A21 mcasp4_fsx 14 N/A G16 mcasp4_axr0 14 N/A D17 mcasp4_axr1 11 N/A AA3 mcasp5_aclkx 11 N/A AB9 mcasp5_fsx 11 N/A AB3 mcasp5_axr0 10 N/A AA4 mcasp5_axr1 10 N/A 1. NA in this table stands for Not Applicable. MUXMODE[15:0] 4 5 6 8 vin4a_d2 vin4a_d3 vin4a_d4 vin4a_d5 vin4a_d6 vin4a_d7 vin4a_d8 vin4a_d9 vin4a_d10 vin4a_d11 vin4a_d12 vin4a_d13 vin4a_d14 vin4a_d15 vin4a_d16 vin4a_d17 vin4a_d18 vin4a_d19 vin4a_d20 vin4a_d21 vin4a_d22 vin4a_d23 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Timing Requirements and Switching Characteristics 227 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com The IO timings in data manual for VIN5A and VIN6A Fall-Edge Capture Mode are guarantee if VIP3_VIRTUAL1 virtual mode is configured. Table 5-8 present the values for DELAYMODE bitfield. Table 5-8. Virtual Functions Mapping for VIP3-5a,6a BALL NUMBER D18 E17 C14 D14 G12 F12 B12 A11 B13 A12 E14 A13 G14 F14 A19 A18 C15 A16 B18 F15 B19 C17 C18 A21 G16 D17 AA3 AB9 AB3 AA4 AC5 AB4 AD4 AC4 AC7 AC6 AC9 AC3 AC8 AD6 AB8 AB5 BALL NAME xref_clk0 xref_clk1 mcasp1_aclkx mcasp1_fsx mcasp1_axr0 mcasp1_axr1 mcasp1_axr8 mcasp1_axr9 mcasp1_axr10 mcasp1_axr11 mcasp1_axr12 mcasp1_axr13 mcasp1_axr14 mcasp1_axr15 mcasp2_aclkx mcasp2_fsx mcasp2_axr2 mcasp2_axr3 mcasp3_aclkx mcasp3_fsx mcasp3_axr0 mcasp3_axr1 mcasp4_aclkx mcasp4_fsx mcasp4_axr0 mcasp4_axr1 mcasp5_aclkx mcasp5_fsx mcasp5_axr0 mcasp5_axr1 gpio6_10 gpio6_11 mmc3_clk mmc3_cmd mmc3_dat0 mmc3_dat1 mmc3_dat2 mmc3_dat3 mmc3_dat4 mmc3_dat5 mmc3_dat6 mmc3_dat7 Delay Mode Value VIP3_VIRTUAL1 5 5 9 13 9 9 8 8 8 8 8 8 8 8 6 6 5 5 6 5 5 4 13 13 13 10 10 10 7 7 8 8 8 8 8 8 8 8 8 8 8 8 MUXMODE[15:0] 7 9 vin6a_d0 vin6a_clk0 vin6a_fld0 vin6a_de0 vin6a_vsync0 vin6a_hsync0 vin6a_d15 vin6a_d14 vin6a_d13 vin6a_d12 vin6a_d11 vin6a_d10 vin6a_d9 vin6a_d8 vin6a_d7 vin6a_d6 vin6a_d5 vin6a_d4 vin6a_d3 vin6a_d2 vin6a_d1 vin6a_d0 vin5a_fld0 vin5a_d15 vin5a_d14 vin5a_d13 vin5a_d12 vin5a_d11 vin5a_d10 vin5a_d9 vin5a_d8 vin5a_clk0 vin5a_de0 vin5a_d7 vin5a_d6 vin5a_d5 vin5a_d4 vin5a_d3 vin5a_d2 vin5a_d1 vin5a_d0 vin5a_hsync0 vin5a_vsync0 228 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 5.5 Display Subsystem – Video Output Ports Three Display Port interfaces(DPI) channels are available in DSS named DPI Video Output 1, DPI Video Output 2 and DPI Video Output 3. NOTE The DPI Video Output i (i = 1 to 3) interface is also referred to as VOUTi. Every VOUT interface consists of: • 24-bit data bus (data[23:0]) • Horizontal synchronization signal (HSYNC) • Vertical synchronization signal (VSYNC) • Data enable (DE) • Field ID (FID) • Pixel clock (CLK) NOTE For more information, see the Display Subsystem chapter of the Device TRM. Table 5-9 and Figure 5-4 assumes testing over the recommended operating conditions and electrical characteristic conditions. Table 5-9. DPI Video Output i (i = 1..3) Switching Characteristics(1) NO. D1 D2 D3 D4 D5 D6 PARAMETER tc(clk) tw(clkL) tw(clkH) tt(clk) td(clk-ctlV) td(clk-dV) DESCRIPTION Cycle time, output pixel clock vouti_clk Pulse duration, output pixel clock vouti_clk low Pulse duration, output pixel clock vouti_clk high Transistion time, output pixel clock vouti_clk (10%-90%) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid MIN 6.06 P*0.45 (1) P*0.45 (1) TBD -1.39 -1.39 MAX TBD 1.15 1.15 UNIT ns ns ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 229 Submit Documentation Feedback DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 (1) P = output vouti_clk period in ns. D2 D1 D3 D4 vouti_clk D6 vouti_vsync www.ti.com EARLY PRELIMINARY D6 vouti_hsync vouti_d[23:0] vouti_de D5 data_1 data_2 D6 data_n ADVANCE INFORMATION vouti_fld D6 odd even Figure 5-4. DPI Video Output(1) (2)(3) SWPS049-018 (1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock. (2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM. (3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM. NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 2-3 and described in Device TRM, Chapter 18 - Control Module. The IO timings in data manual for Clock Fall mode of VOUT (fall-edge capture) are guarantee if DSS_VIRTUAL1 virtual mode is configured. Table 5-10 present the values for DELAYMODE bitfield. Table 5-10. Virtual Functions Mapping for Video Output Port BALL BALL NAME Delay Mode Value MUXMODE[15:0] NUMBER DSS_VIRTUAL1 0 3 4 6 M6 gpmc_ad0 14 vout3_d0 M2 gpmc_ad1 14 vout3_d1 L5 gpmc_ad2 14 vout3_d2 M1 gpmc_ad3 14 vout3_d3 L6 gpmc_ad4 14 vout3_d4 L4 gpmc_ad5 14 vout3_d5 L3 gpmc_ad6 14 vout3_d6 L2 gpmc_ad7 14 vout3_d7 L1 gpmc_ad8 14 vout3_d8 230 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER K2 J1 J2 H1 J3 H2 H3 R6 T9 T6 T7 P6 R9 R5 P5 N7 R4 N9 P9 P1 AG8 AD9 AE9 AF8 AE8 AD8 AG7 AH6 AH3 AH5 AG6 AH4 AG4 AG2 AG3 AG5 AF2 AF6 AF3 AF4 AF1 AE3 AE5 AE1 AE2 AE6 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-10. Virtual Functions Mapping for Video Output Port (continued) BALL NAME Delay Mode Value MUXMODE[15:0] DSS_VIRTUAL1 0 3 4 6 gpmc_ad9 14 vout3_d9 gpmc_ad10 14 vout3_d10 gpmc_ad11 14 vout3_d11 gpmc_ad12 14 vout3_d12 gpmc_ad13 14 vout3_d13 gpmc_ad14 14 vout3_d14 gpmc_ad15 14 vout3_d15 gpmc_a0 15 vout3_d16 gpmc_a1 15 vout3_d17 gpmc_a2 15 vout3_d18 gpmc_a3 15 vout3_d19 gpmc_a4 15 vout3_d20 gpmc_a5 15 vout3_d21 gpmc_a6 15 vout3_d22 gpmc_a7 15 vout3_d23 gpmc_a8 15 vout3_hsync gpmc_a9 15 vout3_vsync gpmc_a10 15 vout3_de gpmc_a11 15 vout3_fld gpmc_cs3 15 vout3_clk vin1a_clk0 15 vout3_d16 vout3_fld vin1a_de0 15 vout3_d17 vout3_de vin1a_hsync0 15 vout3_hsync vin1a_vsync0 15 vout3_vsync vin1a_d0 15 vout3_d7 vout3_d23 vin1a_d1 15 vout3_d6 vout3_d22 vin1a_d2 15 vout3_d5 vout3_d21 vin1a_d3 15 vout3_d4 vout3_d20 vin1a_d4 15 vout3_d3 vout3_d19 vin1a_d5 15 vout3_d2 vout3_d18 vin1a_d6 15 vout3_d1 vout3_d17 vin1a_d7 15 vout3_d0 vout3_d16 vin1a_d8 15 vout3_d15 vin1a_d9 15 vout3_d14 vin1a_d10 15 vout3_d13 vin1a_d11 15 vout3_d12 vin1a_d12 15 vout3_d11 vin1a_d13 15 vout3_d10 vin1a_d14 15 vout3_d9 vin1a_d15 15 vout3_d8 vin1a_d16 15 vout3_d7 vin1a_d17 15 vout3_d6 vin1a_d18 15 vout3_d5 vin1a_d19 15 vout3_d4 vin1a_d20 15 vout3_d3 vin1a_d21 15 vout3_d2 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 231 Submit Documentation Feedback DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 BALL NUMBER AD2 AD3 E1 G2 H7 G1 G6 F2 F3 D1 E2 D2 F4 C1 E4 F5 E6 D3 F6 D5 C2 C3 C4 B2 D6 C5 A3 B3 B4 B5 A4 D11 B10 B11 C11 E11 F11 G10 F10 G11 E9 F9 F8 E7 E8 D9 Table 5-10. Virtual Functions Mapping for Video Output Port (continued) BALL NAME vin1a_d22 vin1a_d23 vin2a_clk0 vin2a_de0 vin2a_fld0 vin2a_hsync0 vin2a_vsync0 vin2a_d0 vin2a_d1 vin2a_d2 vin2a_d3 vin2a_d4 vin2a_d5 vin2a_d6 vin2a_d7 vin2a_d8 vin2a_d9 vin2a_d10 vin2a_d11 vin2a_d12 vin2a_d13 vin2a_d14 vin2a_d15 vin2a_d16 vin2a_d17 vin2a_d18 vin2a_d19 vin2a_d20 vin2a_d21 vin2a_d22 vin2a_d23 vout1_clk vout1_de vout1_fld vout1_hsync vout1_vsync vout1_d0 vout1_d1 vout1_d2 vout1_d3 vout1_d4 vout1_d5 vout1_d6 vout1_d7 vout1_d8 vout1_d9 Delay Mode Value DSS_VIRTUAL1 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 0 vout1_clk vout1_de vout1_fld vout1_hsync vout1_vsync vout1_d0 vout1_d1 vout1_d2 vout1_d3 vout1_d4 vout1_d5 vout1_d6 vout1_d7 vout1_d8 vout1_d9 MUXMODE[15:0] 3 4 vout3_d1 vout3_d0 vout2_fld vout2_de vout2_clk vout2_hsync vout2_vsync vout2_d23 vout2_d22 vout2_d21 vout2_d20 vout2_d19 vout2_d18 vout2_d17 vout2_d16 vout2_d15 vout2_d14 vout2_d13 vout2_d12 vout2_d11 vout2_d10 vout2_d9 vout2_d8 vout2_d7 vout2_d6 vout2_d5 vout2_d4 vout2_d3 vout2_d2 vout2_d1 vout2_d0 www.ti.com 6 232 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com BALL NUMBER D7 D8 A5 C6 C8 C7 B7 B8 A7 A8 C9 A9 B9 A10 E21 F20 F21 B26 C23 B14 J14 G13 J11 E12 F13 C12 D12 E15 A20 B15 A15 D15 B16 B17 A17 C18 A21 G16 D17 AA3 AB9 AB3 AA4 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-10. Virtual Functions Mapping for Video Output Port (continued) BALL NAME vout1_d10 vout1_d11 vout1_d12 vout1_d13 vout1_d14 vout1_d15 vout1_d16 vout1_d17 vout1_d18 vout1_d19 vout1_d20 vout1_d21 vout1_d22 vout1_d23 gpio6_14 gpio6_15 gpio6_16 xref_clk2 xref_clk3 mcasp1_aclkr mcasp1_fsr mcasp1_axr2 mcasp1_axr3 mcasp1_axr4 mcasp1_axr5 mcasp1_axr6 mcasp1_axr7 mcasp2_aclkr mcasp2_fsr mcasp2_axr0 mcasp2_axr1 mcasp2_axr4 mcasp2_axr5 mcasp2_axr6 mcasp2_axr7 mcasp4_aclkx mcasp4_fsx mcasp4_axr0 mcasp4_axr1 mcasp5_aclkx mcasp5_fsx mcasp5_axr0 mcasp5_axr1 Delay Mode Value DSS_VIRTUAL1 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 0 vout1_d10 vout1_d11 vout1_d12 vout1_d13 vout1_d14 vout1_d15 vout1_d16 vout1_d17 vout1_d18 vout1_d19 vout1_d20 vout1_d21 vout1_d22 vout1_d23 MUXMODE[15:0] 3 4 6 vout2_hsync vout2_vsync vout2_fld vout2_clk vout2_de vout2_d0 vout2_d1 vout2_d2 vout2_d3 vout2_d4 vout2_d5 vout2_d6 vout2_d7 vout2_d8 vout2_d9 vout2_d10 vout2_d11 vout2_d12 vout2_d13 vout2_d14 vout2_d15 vout2_d16 vout2_d17 vout2_d18 vout2_d19 vout2_d20 vout2_d21 vout2_d22 vout2_d23 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 233 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 5.6 Display Subsystem – High-Definition Multimedia Interface (HDMI) The High-Definition Multimedia Interface is provided for transmitting digital television audiovisual signals from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other video displays. The HDMI interface is aligned with the HDMI TMDS single stream standard v1.4 3D (720p @60Hz to 1080p @24Hz) and the HDMI v1.3 (1080p @60Hz): 3 data channels, plus 1 clock channel is supported (differential). NOTE For more information, see the High-Definition Multimedia Interface chapter of the device TRM 5.7 External Memory Interface (EMIF) The device has a dedicated interface to DDR3 and DDR2 SDRAM. It supports JEDEC standard compliant DDR2 and DDR3 SDRAM devices with the following features: • 16-bit or 32-bit data path to external SDRAM memory • Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 2Gb and 4Gb devices • One interface with associated DDR2/DDR3 PHYs NOTE For more information, see the EMIF Controller section of the Device TRM. 5.8 General-Purpose Memory Controller (GPMC) The GPMC is the unified memory controller that interfaces external memory devices such as: • Asynchronous SRAM-like memories and ASIC devices • Asynchronous page mode and synchronous burst NOR flash • NAND flash NOTE For more information, see the General-Purpose Memory Controller section of the Device TRM. 5.8.1 GPMC/NOR Flash Interface Synchronous Timing Table 5-11 and Table 5-12, Table 5-13 and Table 5-14 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-5, Figure 5-6, Figure 5-7, Figure 58, Figure 5-9 and Figure 5-10). Table 5-11. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 1 Load NO. F12 F13 F21 F22 PARAMETER tsu(DV-CLKH) th(CLKH-DV) tsu(WAITV-CLKH) th(CLKH-WAITV) DESCRIPTION Setup time, read gpmc_ad[15:0] valid before gpmc_clk high Hold time, read gpmc_ad[15:0] valid after gpmc_clk high Setup time, gpmc_wait[1:0] valid before gpmc_clk high Hold Time, gpmc_wait[1:0] valid after gpmc_clk high MIN MAX UNIT 1.9 ns 1 ns 1.9 ns 1 ns NOTE Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see the Device TRM. 234 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-12. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load NO. PARAMETER DESCRIPTION F0 tc(CLK) Cycle time, output clock gpmc_clk period F1 tw(CLKH) Typical Pulse duration, output clock gpmc_clk high F1 tw(CLKL) Typical Pulse duration, output clock gpmc_clk low tdc(CLK) Duty cycle error, output clock gpmc_clk tj(CLK) Jitter standard deviation , output clock gpmc_clk tr(CLK) Rise time, output clock gpmc_clk tf(CLK) Fall time, output clock gpmc_clk tr(DO) Rise time, output data gpmc_ad[15:0] tf(DO) Fall time, output data gpmc_ad[15:0] F2 td(CLKH-nCSV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition F3 td(CLKH-nCSIV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid F4 td(ADDV-CLK) Delay time, gpmc_a address bus valid to gpmc_clk first edge F5 td(CLKH-ADDIV) Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid F6 td(nBEV-CLK) Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge F7 td(CLKL-nBEIV) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid F8 td(CLKL-nADV) Delay time, gpmc_clk rising edge to gpmc_advn_ale transition F9 td(CLKH-nADVIV) Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid F10 td(CLKL-nOE) Delay time, gpmc_clk rising edge to gpmc_oen_ren transition F11 td(CLKL-nOEIV) Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid F14 td(CLKL-nWE) Delay time, gpmc_clk rising edge to gpmc_wen transition F15 td(CLKL-Data) Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition F17 F18 F19 F20 td(CLKH-nBE) tw(nCSV) tw(nBEV) tw(nADVV) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition Pulse duration, gpmc_cs[7:0] low Pulse duration, gpmc_ben[1:0] low Pulse duration, gpmc_advn_ale low MIN MAX UNIT 11.3 ns 0.5P(11) 0.5P(13) ns 0.5P(13) 0.5P(13) ns TBD TBD ps TBD ps TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns F-0.8(6) F+3.1(6) ns E-0.8(5) E+3.1(5) ns B-3.1(2) B-0.8(2) ns -0.8 ns B-3.8(2) B+1.1(2) ns D-0.4(4) D+1.1(4) ns G-0.8(7) G+3.1(7) ns D-0.8(4) D+3.1(4) ns H-0.8(8) H+2.1(8) ns E-0.8(5) E+2.1(5) ns I-0.8(9) I+3.1(9) ns J-1.1(10) J+3.92(1 ns 0) J-1.1(10) J+3.8(10) ns A(1) ns C(3) ns K(12) ns Table 5-13. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 5 Loads NO. F12 F13 F21 F22 PARAMETER tsu(DV-CLKH) th(CLKH-DV) tsu(WAITV-CLKH) th(CLKH-WAITV) DESCRIPTION Setup time, read gpmc_ad[15:0] valid before gpmc_clk high Hold time, read gpmc_ad[15:0] valid after gpmc_clk high Setup time, gpmc_wait[1:0] valid before gpmc_clk high Hold Time, gpmc_wait[1:0] valid after gpmc_clk high MIN MAX UNIT 2.5 ns 1.9 ns 2.5 ns 1.9 ns Table 5-14. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads NO. PARAMETER DESCRIPTION F0 tc(CLK) F1 tw(CLKH) F1 tw(CLKL) tdc(CLK) tj(CLK) tr(CLK) tf(CLK) tr(DO) tf(DO) Cycle time, output clock gpmc_clk period Typical Pulse duration, output clock gpmc_clk high Typical Pulse duration, output clock gpmc_clk low Duty cycle error, output clock gpmc_clk Jitter standard deviation , output clock gpmc_clk Rise time, output clock gpmc_clk Fall time, output clock gpmc_clk Rise time, output data gpmc_ad[15:0] Fall time, output data gpmc_ad[15:0] MIN 15.04 0.5P(11) 0.5P(11) TBD TBD TBD TBD TBD MAX UNIT ns 0.5P(11) ns 0.5P(11) ns TBD ps TBD ps TBD ns TBD ns TBD ns TBD ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 235 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-14. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads (continued) NO. PARAMETER DESCRIPTION MIN MAX UNIT F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F14 F15 F17 F18 F19 F20 td(CLKH-nCSV) td(CLKH-nCSIV) td(ADDV-CLK) td(CLKH-ADDIV) td(nBEV-CLK) td(CLKL-nBEIV) td(CLKL-nADV) td(CLKH-nADVIV) td(CLKL-nOE) td(CLKH-nOEIV) td(CLKH-nWE) td(CLKL-Data) td(CLKL-nBE) tw(nCSV) tw(nBEV) tw(nADVV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid Delay time, gpmc_clk rising edge to gpmc_advn_ale transition Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid Delay time, gpmc_clk rising edge to gpmc_noe transition Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid Delay time, gpmc_clk rising edge to gpmc_wen transition Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition Pulse duration, gpmc_cs[7:0] low Pulse duration, gpmc_ben[1:0] low Pulse duration, gpmc_advn_ale low F+0.7(6) E+0.7(5) B-6.1(2) 0.7 B-4.9(2) D-0.4(4) G+0.7(7) D+0.7(4) H+0.7(8) E+0.7(5) I+0.7(9) J-0.4(10) J-0.4(10) A(1) C(3) K(12) F+6.1(6) ns E+6.1(5) ns B-0.7(2) ns ns B+0.4(2) ns D+4.9(4) ns G+6.1(7) ns D+6.1(4) ns H+5.1(8) ns E+5.1(5) ns I+6.1(9) ns J+4.9(10) ns J+4.9(10) ns ns ns ns (1) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period with n the page burst access number. (2) B = ClkActivationTime * GPMC_FCLK (3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For Burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n the page burst access number. (4) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK (5) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK (6) For nCS falling edge (CS activated): Case GpmcFCLKDivider = 0: – F = 0.5 × CSExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1: – F = 0.5 × CSExtraDelay × GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even) – F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: – F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3) – F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3) – F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3) (7) For ADV falling edge (ADV activated): Case GpmcFCLKDivider = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3) 236 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 For ADV rising edge (ADV deactivated) in Reading mode: Case GpmcFCLKDivider = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Writing mode: Case GpmcFCLKDivider = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3) (8) For OE falling edge (OE activated) / IO DIR rising edge (IN direction): Case GpmcFCLKDivider = 0: – H = 0.5 × OEExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1: – H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: – H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3) For OE rising edge (OE deactivated): Case GpmcFCLKDivider = 0: – H = 0.5 × OEExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1: – H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: – H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3) (9) For WE falling edge (WE activated): Case GpmcFCLKDivider = 0: – I = 0.5 × WEExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1: – I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: – I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3) For WE rising edge (WE deactivated): Case GpmcFCLKDivider = 0: – I = 0.5 × WEExtraDelay × GPMC_FCLK Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 237 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Case GpmcFCLKDivider = 1: – I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: – I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3) (10) J = GPMC_FCLK period (11) P = gpmc_clk period (12) For read: K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK (13) The gpmc_clk output clock maximum and minimum frequency programmable in I/F module by setting the GPMC_CONFIG1_CSx configuration register bit fields GpmcFCLKDivider. (14) The jitter probability density can be approximated by a Gaussian function gpmc_clk gpmc_ncsi gpmc_a[25:16] gpmc_nbe1 gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_ad[15:0] F1 F0 F1 F2 F18 F4 Address (MSB) F6 F19 F6 F19 F8 F8 F20 F4 F5 Address (LSB) F3 F7 F7 F9 F10 F11 F13 F12 D0 F22 F21 gpmc_waitj gpmc_io_dir OUT F23 F24 IN OUT Figure 5-5. GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read (GpmcFCLKDivider = 0)(1)(2) GPMC_01 (1) In gpmc_ncsi, i = 0 to 7. (2) In gpmc_waitj, j = 0 to 1. 238 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com gpmc_clk gpmc_ncsi gpmc_a[25:16] gpmc_nbe1 gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_ad[15:0] SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 F1 F0 F1 F2 F3 F18 F4 Address F6 F7 F19 F6 F7 F19 F8 F8 F20 F9 F10 F11 F13 F12 D0 F22 F21 gpmc_wait gpmc_io_dir OUT F23 F24 IN OUT GPMC_02 Figure 5-6. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Single Read (GpmcFCLKDivider = 0)(1)(2)(3) (1) In gpmc_ncsi, i = 0 to 7. (2) In gpmc_waitj, j = 0 to 1. (3) Nonmultiplexed NOR interface can be used only with a limited address range corresponding to 10 address bits. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 239 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 gpmc_clk F2 gpmc_ncsi F1 F0 F1 F18 www.ti.com F3 gpmc_a[25:16] gpmc_nbe1 gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_ad[15:0] F4 Address (MSB) F7 F6 F19 Valid F7 F6 F19 Valid F8 F8 F20 F9 F10 F11 F4 Address (LSB) F12 F5 F13 F12 D0 D1 D2 D3 gpmc_waitj F22 F21 gpmc_io_dir OUT F23 F24 IN OUT GPMC_03 Figure 5-7. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits (GpmcFCLKDivider = 0)(1)(2) (1) In gpmc_ncsi, i= 0 to 7. (2) In gpmc_waitj, j = 0 to 1. ADVANCE INFORMATION 240 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com gpmc_clk F2 gpmc_ncsi SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 F1 F0 F1 F3 F18 gpmc_a[25:16] gpmc_nbe1 gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_ad[15:0] F4 Address F7 F6 F19 Valid F7 F6 F19 Valid F8 F8 F20 F9 F10 F11 F12 F13 D0 D1 D2 F12 D3 gpmc_waitj F22 F21 gpmc_io_dir OUT F23 F24 IN OUT GPMC_04 Figure 5-8. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits (GpmcFCLKDivider = 0)(1)(2)(3) (1) In gpmc_ncsi, i = 0 to 7. (2) In gpmc_waitj, j = 0 to 1. (3) Nonmultiplexed NOR interface can be used only with a limited address range corresponding to 10 address bits. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 241 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 gpmc_clk F2 F1 F1 F0 gpmc_ncsi gpmc_a[25:16] F4 Address (MSB) F6 gpmc_nbe1 F6 gpmc_nbe0_cle gpmc_nadv_ale gpmc_nwe F8 F8 F20 F14 F14 gpmc_ad[15:0] gpmc_waitj Address (LSB) F22 www.ti.com F3 F18 F17 F17 F17 F17 F17 F17 F9 F15 F15 F15 D0 D1 D2 D3 F21 gpmc_io_dir OUT GPMC_05 Figure 5-9. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits (GpmcFCLKDivider = 0)(1)(2) (1) In “gpmc_ncsi”, i = 0 to 7. (2) In “gpmc_waitj”, j = 0 to 1. ADVANCE INFORMATION 242 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com gpmc_clk gpmc_ncsi gpmc_a[25:16] gpmc_nbe1 gpmc_nbe0_cle gpmc_nadv_ale gpmc_nwe gpmc_ad[15:0] gpmc_waitj F1 F1 F0 F2 F4 Address F6 F6 F8 F8 F20 F14 F14 D0 F22 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 F3 F18 F17 F17 F17 F17 F17 F17 F9 F15 F15 F15 D1 D2 D3 F21 gpmc_io_dir OUT GPMC_06 Figure 5-10. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits (GpmcFCLKDivider = 0)(1)(2)(3) (1) In “gpmc_ncsi”, i = 1 to 7. (2) In “gpmc_waitj”, j = 0 to 1. (3) Non Multiplexed NOR interface can be used only with a limited address range corresponding to 10 address bits. 5.8.2 GPMC/NOR Flash Interface Asynchronous Timing Table 5-15 and Table 5-16 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-11, Figure 5-12, Figure 5-13, Figure 5-14, Figure 5-15 and Figure 5-16). Table 5-15. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode NO. PARAMETER DESCRIPTION MIN FA5 FA20 tacc(DAT) tacc1-pgmode(DAT) Data Maximum Access Time (GPMC_FCLK cycles) Page Mode Successive Data Maximum Access Time (GPMC_FCLK cycles) FA21 tacc2-pgmode(DAT) Page Mode First Data Maximum Access Time (GPMC_FCLK cycles) tsu(DV-OEH) Setup time. read gpmc_ad[15:0] valid before gpmc_noe high 1.9 th(OEH-DV) Hold time, read gpmc_ad[15:0] valid after gpmc_noe high 1 MAX H(1) P(2) H(1) UNIT cycles cycles cycles ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 243 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com (1) H = Access Time * (TimeParaGranularity + 1) (2) P = PageBurstAccessTime * (TimeParaGranularity + 1) Table 5-16. GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT tr(DO) tf(DO) FA0 tw(nBEV) FA1 tw(nCSV) FA3 td(nCSV-nADVIV) FA4 td(nCSV-nOEIV) FA9 td(AV-nCSV) FA10 td(nBEV-nCSV) FA12 td(nCSV-nADVV) FA13 td(nCSV-nOEV) FA16 tw(AIV) FA18 td(nCSV-nOEIV) FA20 tw(AV) FA25 td(nCSV-nWEV) FA27 td(nCSV-nWEIV) FA28 td(nWEV-DV) FA29 td(DV-nCSV) FA37 td(nOEV-AIV) Rising time, gpmc_ad[15:0] output data Fallling time, gpmc_ad[15:0] output data Pulse duration, gpmc_ben[1:0] valid time Pulse duration, gpmc_cs[7:0] low Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read) Delay time, address bus valid to gpmc_cs[7:0] valid Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid Pulse duration, address invalid between 2 successive R/W accesses Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read) Pulse duration, address valid : 2nd, 3rd and 4th accesses Delay time, gpmc_cs[7:0] valid to gpmc_wen valid Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid Delay time, gpmc_ wen valid to data bus valid Delay time, data bus valid to gpmc_cs[7:0] valid Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed address bus phase end TBD TBD B - 2(3) C - 2(4) J - 2(5) J - 2(5) K - 2(6) L - 2(7) G(8) I - 2(9) D(10) E - 2(11) F - 2(12) J - 0.2(5) TBD ns TBD ns N ns A ns B + 4(3) ns C + 4(4) ns J + 4(5) ns J + 4(5) ns K + 4(6) ns L + 4(7) ns ns I + 4(9) ns ns E + 4(11) ns F + 4(12) ns 2 ns J + 2.0(5) ns 2 ns (1) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK (2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period with n the page burst access number. (3) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK (4) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLKFor single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK (5) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK (6) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK (7) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK (8) G = Cycle2CycleDelay * GPMC_FCLK * (TimeParaGranularity + 1) (9) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK (10) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK (11) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK (12) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK 244 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com GPMC_FCLK gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 FA5 FA1 FA9 FA10 FA10 FA3 FA12 Valid Address FA0 Valid FA0 Valid FA4 FA13 Data IN 0 Data IN 0 gpmc_waitx gpmc_io_dir FA15 FA14 OUT IN Figure 5-11. GPMC / NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3) OUT GPMC_07 (1) In gpmc_ncsx, x = 0 to 7. In gpmc_waitx, x = 0 to 1. (2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. (3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 245 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 GPMC_FCLK www.ti.com gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 FA5 FA1 FA9 FA10 FA10 Address 0 FA0 Valid FA0 Valid FA16 FA9 FA10 FA10 FA5 FA1 Address 1 FA0 Valid FA0 Valid gpmc_nadv_ale gpmc_noe gpmc_d[15:0] FA3 FA12 FA4 FA13 FA3 FA12 FA4 FA13 Data Upper gpmc_waitx FA14 FA15 FA14 FA15 gpmc_io_dir OUT IN OUT IN GPMC_08 Figure 5-12. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing(1)(2)(3) (1) In “gpmc_ncsx”, x = 0 to 7. In “gpmc_waitx”, x = 0 to 1. (2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock edge. FA5 value should be stored inside AccessTime register bits field (3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally ADVANCE INFORMATION 246 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com GPMC_FCLK SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] FA21 FA9 FA10 Add0 FA10 FA12 FA13 FA20 FA1 FA20 FA20 Add1 Add2 Add3 FA0 Add4 FA0 FA18 D0 D1 D2 D3 D3 gpmc_waitx FA15 FA14 gpmc_io_dir OUT IN OUT GPMC_09 Figure 5-13. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4) (1) In “gpmc_ncsx”, x = 0 to 7. In “gpmc_waitx”, x = 0 to 1 (2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled by active functional clock edge. FA21 calculation is detailled in a separated application note (ref …) and should be stored inside AccessTime register bits field. (3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field. (4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 247 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 gpmc_fclk www.ti.com gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] FA9 FA10 FA10 FA3 FA12 FA29 FA25 FA1 Valid Address FA0 FA0 FA27 Data OUT gpmc_waitx gpmc_io_dir OUT Figure 5-14. GPMC / NOR Flash - Asynchronous Write - Single Word Timing(1) (1) In “gpmc_ncsx”, x = 0 to 7. In “gpmc_waitx”, x = 0 to 1. GPMC_10 ADVANCE INFORMATION 248 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com GPMC_FCLK SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 gpmc_clk gpmc_ncsx gpmc_a[26:17] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_a[16.1]_d[15:0] FA9 FA10 FA10 FA3 FA12 FA13 FA29 Address (LSB) FA1 FA5 Address (MSB) FA0 Valid FA0 Valid FA4 FA37 Data IN Data IN FA15 FA14 gpmc_io_dir OUT IN OUT gpmc_waitx GPMC_11 Figure 5-15. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3) (1) In “gpmc_ncsx”, x = 0 to 7. In “gpmc_waitx”, x = 0 to 1 (2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock edge. FA5 value should be stored inside AccessTime register bits field. (3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 249 Submit Documentation Feedback DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 gpmc_fclk www.ti.com EARLY PRELIMINARY gpmc_clk gpmc_ncsx gpmc_a[26:17] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_a[16.1]_d[15:0] FA9 FA10 FA10 FA3 FA12 FA25 FA29 Valid Address (LSB) FA1 Address (MSB) FA0 FA0 FA27 FA28 Data OUT ADVANCE INFORMATION gpmc_waitx gpmc_io_dir OUT GPMC_12 Figure 5-16. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1) (1) In “gpmc_ncsx”, x = 0 to 7. In “gpmc_waitx”, x = 0 to 1. 5.8.3 GPMC/NAND Flash Interface Asynchronous Timing Table 5-17 and Table 5-18 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see , Figure 5-18, Figure 5-19 and Figure 5-20). Table 5-17. GPMC/NAND Flash Interface Timing Requirements(1) NO. PARAMETER DESCRIPTION MIN GNF12 tACC(DAT) tsu(DV-OEH) Data maximum access time (GPMC_FCLK Cycles) Setup time, read gpmc_ad[15:0] valid before 1.9 gpmc_noe high th(OEH-DV) Hold time, read gpmc_ad[15:0] valid after gpmc_noe 1 high (1) J = AccessTime * (TimeParaGranularity + 1) MAX J(1) UNIT cycles ns ns Table 5-18. GPMC/NAND Flash Interface Switching Characteristics NO. GNF0 GNF1 PARAMETER tr(DO) tf(DO) tw(nWEV) td(nCSV-nWEV) DESCRIPTION Rising time, gpmc_ad[15:0] output data Fallling time, gpmc_ad[15:0] output data Pulse duration, gpmc_wen valid time Delay time, gpmc_cs[7:0] valid to gpmc_wen valid MIN TBD TBD B - 2(2) MAX TBD TBD A(1) B + 4(2) UNIT ns ns ns ns 250 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-18. GPMC/NAND Flash Interface Switching Characteristics (continued) NO. PARAMETER DESCRIPTION MIN MAX UNIT GNF2 GNF3 GNF4 GNF5 GNF6 GNF7 GNF8 GNF9 GNF10 GNF13 GNF14 GNF15 td(CLEH-nWEV) td(nWEV-DV) td(nWEIV-DIV) td(nWEIV-CLEIV) td(nWEIV-nCSIV) td(ALEH-nWEV) td(nWEIV-ALEIV) tc(nWE) td(nCSV-nOEV) tw(nOEV) tc(nOE) td(nOEIV-nCSIV) Delay time, gpmc_ben[1:0] high to gpmc_wen valid Delay time, gpmc_ad[15:0] valid to gpmc_wen valid Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid Delay time, gpmc_advn_ale high to gpmc_wen valid Delay time, gpmc_wen invalid to gpmc_advn_ale invalid Cycle time, write cycle time Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid Pulse duration, gpmc_oen_ren valid time Cycle time, read cycle time Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid C - 2(3) C + 4(3) ns D - 2(4) D + 4(4) ns E - 2(5) E + 4(5) ns F - 2(6) F + 4(6) ns G - 2(7) G + 4(7) ns C - 2(3) C + 4(3) ns F - 2(6) F + 4(6) ns H(8) ns I - 2(9) I + 4(9) ns K(10) ns L(11) ns M - 2(12) M + 4(12) ns (1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK (2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK (3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK (4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK (5) E = (WrCycleTime – WEOffTime * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK (6) F = (ADVWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay ) * GPMC_FCLK (7) G = (CSWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay ) * GPMC_FCLK (8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK (9) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK (10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK (11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK (12) M = (CSRdOffTime – OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay ) * GPMC_FCLK GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle GNF1 GNF2 GNF6 GNF5 gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16.1]_d[15:0] GNF0 GNF3 Command GNF4 Figure 5-17. GPMC / NAND Flash - Command Latch Cycle Timing(1) (1) In gpmc_ncsx, x = 0 to 7. GPMC_13 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 251 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 GPMC_FCLK gpmc_ncsx GNF1 GNF6 www.ti.com gpmc_nbe0_cle gpmc_nadv_ale GNF7 GNF8 gpmc_noe gpmc_nwe gpmc_a[16.1]_d[15:0] GNF0 GNF9 GNF3 Address GNF4 Figure 5-18. GPMC / NAND Flash - Address Latch Cycle Timing(1) (1) In gpmc_ncsx, x = 0 to 7. GPMC_FCLK GPMC_14 GNF12 gpmc_ncsx GNF10 GNF15 gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_a[16.1]_d[15:0] GNF13 GNF14 DATA gpmc_waitx Figure 5-19. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3) GPMC_15 (1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field. (2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. (3) In gpmc_ncsx, x = 0 to 7. In gpmc_waitx, x = 0 to 1. 252 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com GPMC_FCLK gpmc_ncsx GNF1 SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 GNF6 gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16.1]_d[15:0] GNF9 GNF0 GNF3 DATA GNF4 Figure 5-20. GPMC / NAND Flash - Data Write Cycle Timing(1) (1) In gpmc_ncsx, x = 0 to 7. GPMC_16 NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 2-3 and described in Device TRM, Chapter 18 - Control Module. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 253 Submit Documentation Feedback DRA75x, DRA74x TI Confidential — NDA Restrictions ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY The IO timings in data manual for GPMC 5L (5 load) application @66MHz are guarantee if GPMC_VIRTUAL1 virtual mode is configured. Table 5-19 present the values for DELAYMODE bitfield. Table 5-19. Virtual Functions Mapping for GPMC BALL BALL NAME Delay Mode Value NUMBER GPMC_VIRTUAL1 0 1 M6 gpmc_ad0 TBD gpmc_ad0 M2 gpmc_ad1 TBD gpmc_ad1 L5 gpmc_ad2 TBD gpmc_ad2 M1 gpmc_ad3 TBD gpmc_ad3 L6 gpmc_ad4 TBD gpmc_ad4 L4 gpmc_ad5 TBD gpmc_ad5 L3 gpmc_ad6 TBD gpmc_ad6 L2 gpmc_ad7 TBD gpmc_ad7 L1 gpmc_ad8 TBD gpmc_ad8 K2 gpmc_ad9 TBD gpmc_ad9 J1 gpmc_ad10 TBD gpmc_ad10 J2 gpmc_ad11 TBD gpmc_ad11 H1 gpmc_ad12 TBD gpmc_ad12 J3 gpmc_ad13 TBD gpmc_ad13 H2 gpmc_ad14 TBD gpmc_ad14 H3 gpmc_ad15 TBD gpmc_ad15 R6 gpmc_a0 14 gpmc_a0 T9 gpmc_a1 14 gpmc_a1 T6 gpmc_a2 14 gpmc_a2 T7 gpmc_a3 14 gpmc_a3 P6 gpmc_a4 14 gpmc_a4 R9 gpmc_a5 14 gpmc_a5 R5 gpmc_a6 14 gpmc_a6 P5 gpmc_a7 14 gpmc_a7 N7 gpmc_a8 14 gpmc_a8 R4 gpmc_a9 14 gpmc_a9 N9 gpmc_a10 14 gpmc_a10 P9 gpmc_a11 14 gpmc_a11 P4 gpmc_a12 15 gpmc_a12 MUXMODE[15:0] 2 3 5 6 gpmc_a0 254 Timing Requirements and Switching Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com BALL NUMBER R3 T2 U2 U1 P3 R2 K7 M7 J5 K6 J7 J4 J6 H4 H5 H6 T1 P2 P1 P7 N1 M5 M3 N6 M4 N2 AG5 AF2 AF6 AF3 AF4 BALL NAME gpmc_a13 gpmc_a14 gpmc_a15 gpmc_a16 gpmc_a17 gpmc_a18 gpmc_a19 gpmc_a20 gpmc_a21 gpmc_a22 gpmc_a23 gpmc_a24 gpmc_a25 gpmc_a26 gpmc_a27 gpmc_cs1 gpmc_cs0 gpmc_cs2 gpmc_cs3 gpmc_clk gpmc_advn_ale gpmc_oen_ren gpmc_wen gpmc_ben0 gpmc_ben1 gpmc_wait0 vin1a_d11 vin1a_d12 vin1a_d13 vin1a_d14 vin1a_d15 TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-19. Virtual Functions Mapping for GPMC (continued) Delay Mode Value GPMC_VIRTUAL1 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 14 15 15 15 15 15 15 15 14 14 14 14 14 0 gpmc_a13 gpmc_a14 gpmc_a15 gpmc_a16 gpmc_a17 gpmc_a18 gpmc_a19 gpmc_a20 gpmc_a21 gpmc_a22 gpmc_a23 gpmc_a24 gpmc_a25 gpmc_a26 gpmc_a27 gpmc_cs1 gpmc_cs0 gpmc_cs2 gpmc_cs3 gpmc_clk gpmc_advn_ale gpmc_oen_ren gpmc_wen gpmc_ben0 gpmc_ben1 gpmc_wait0 1 gpmc_cs7 gpmc_cs6 gpmc_cs4 gpmc_cs5 MUXMODE[15:0] 2 3 gpmc_a13 gpmc_a14 gpmc_a15 gpmc_a16 gpmc_a17 gpmc_a18 gpmc_a19 gpmc_a20 gpmc_a21 gpmc_a22 gpmc_wait1 gpmc_wait1 5 gpmc_a1 gpmc_a2 gpmc_a3 gpmc_a23 gpmc_a24 gpmc_a25 gpmc_a26 gpmc_a27 6 gpmc_a23 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Timing Requirements and Switching Characteristics 255 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY ADVANCE INFORMATION 5.9 Timers The device has 16 general-purpose (GP) timers (TIMER1 - TIMER16), two watchdog timers, and a 32-kHz synchronized timer (COUNTER_32K) that have the following features: • Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM) signal • Interrupts generated on overflow, compare, and capture • Free-running 32-bit upward counter • Supported modes: – Compare and capture modes – Auto-reload mode – Start-stop mode • On-the-fly read/write register (while counting) The device has two system watchdog timer (WD_TIMER1 and WD_TIMER2) that have the following features: • Free-running 32-bit upward counter • On-the-fly read/write register (while counting) • Reset upon occurrence of a timer overflow condition The device includes one instance of the 32-bit watchdog timer: WD_TIMER2, also called the MPU watchdog timer. The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop. NOTE For additional information on the Timer Module, see the Device TRM. 5.10 Inter-Integrated Circuit Interface (I2C) The device includes 5 inter-integrated circuit (I2C) modules which provide an interface to other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through the I2C module. NOTE Note that, on I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is not supported NOTE Inter-integrated circuit i ( i=1 to 5) module is also referred to as I2Ci NOTE For more information, see the Multimaster High-Speed I2C Controller section of the Device TRM. Table 5-20 and Figure 5-21 assumes testing over the recommended operating conditions and electrical characteristic conditions below. 256 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-20. Timing Requirements for I2C Input Timings(1) NO. PARAMETER DESCRIPTION STANDARD MODE MIN MAX FAST MODE MIN MAX UNIT 1 tc(SCL) Cycle time, SCL 10 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 2.5 µs 0.6 µs 3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs 4 tw(SCLL) 5 tw(SCLH) 6 tsu(SDAV-SCLH) 7 th(SCLL-SDAV) 8 tw(SDAH) Pulse duration, SCL low Pulse duration, SCL high Setup time, SDA valid before SCL high Hold time, SDA valid after SCL low Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs 4 0.6 µs 250 100(2) ns 0(3) 3.45(4) 0(3) 0.9(4) µs 4.7 1.3 µs 9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb (5) 300(3) ns 10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (5) 300(3) ns 11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (5) 300(3) ns 12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (5) 300(3) ns 13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs 14 tw(SP) 15 Cb (5) Pulse duration, spike (must be suppressed) Capacitive load for each bus line 0 50 ns 400 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. (2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. I2Ci_SDA I2Ci_SCL 11 8 4 10 1 7 3 6 5 12 3 2 9 14 13 Stop Start Repeated Start Stop Figure 5-21. I2C Receive Timing Table 5-21 and Figure 5-22 assumes testing over the recommended operating conditions and electrical characteristic conditions below. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 257 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-21. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2) NO. PARAMETER DESCRIPTION STANDARD MODE MIN MAX FAST MODE MIN MAX UNIT 16 tc(SCL) Cycle time, SCL 10 17 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 2.5 µs 0.6 µs 18 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs 19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 20 tw(SCLH) Pulse duration, SCL high 4 0.6 21 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 22 th(SCLL-SDAV) Hold time, SDA valid after SCL low (for I2C bus devices) 0 3.45 0 µs µs ns 0.9 µs 23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs 24 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb (1) (3) 300(3) ns 25 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (1) (3) 300(3) ns 26 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (1) (3) 300(3) ns 27 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (1) (3) 300(3) ns 28 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs 29 Cp Capacitance for each I2C pin 10 10 pF (1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. (2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details. (3) These timings apply only to I2C1 and I2C2. I2C3, I2C4, and I2C5 use standard LVCMOS buffers to emulate open-drain buffers and their rise/fall times should be referenced in the device IBIS model. NOTE I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic-1. I2Ci_SDA I2Ci_SCL 26 23 19 25 21 20 16 18 27 22 18 17 Stop Start Repeated Start Figure 5-22. I2C Transmit Timing 24 28 Stop 258 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 5.11 HDQ / 1-Wire Interface (HDQ1W) The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to communicate between the master and the slave. The protocols employ an asynchronous return to one mechanism where, after any command, the line is pulled high. NOTE For more information, see the HDQ / 1-Wire section of the Device TRM. 5.11.1 HDQ / 1-Wire — HDQ Mode Table 5-22 and Table 5-23 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-23, Figure 5-24, Figure 5-25 and Figure 5-26). Table 5-22. HDQ/1-Wire Timing Requirements—HDQ Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 tCYCH 2 tHW1 3 tHW0 4 tRSPS Read bit window timing Read one data valid after HDQ low Read zero data hold after HDQ low Response time from HDQ slave device(1) 190 250 µs 32(2) 66(2) µs 70(2) 145(2) µs 190 320 µs (1) Defined by software. (2) If the HDQ slave device drives a logic-low state after tHW0 maximum, it can be interpreted as a break pulse. For more information see "HDQ / 1-Wire Switching Characteristics - HDQ Mode" and the HDQ/1-Wire chapter of the TRM. Table 5-23. HDQ / 1-Wire Switching Characteristics - HDQ Mode NO. PARAMETER DESCRIPTION 5 tB 6 tBR 7 tCYCD 8 tDW1 9 tDW0 Break timing Break recovery time Write bit windows timing Write one data valid after HDQ low Write zero data hold after HDQ low MIN MAX UNIT 190 µs 40 µs 190 µs 0.5 50 µs 86 145 µs HDQ tB tBR Figure 5-23. HDQ Break and Break Recovery Timing — HDQ Interface Writing to Slave HDQ tHW1 tHW0 tCYCH Figure 5-24. Device HDQ Interface Bit Read Timing (Data) HDQ tDW1 tDW0 tCYCD Figure 5-25. Device HDQ Interface Bit Write Timing (Command / Address or Data) Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 259 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 HDQ Command_byte_written 0_(LSB) Break 1 6 tRSPS 7_(MSB) Data_byte_received 1 0_(LSB) 6 Figure 5-26. HDQ Communication Timing www.ti.com 5.11.2 HDQ/1-Wire—1-Wire Mode Table 5-24 and Table 5-25 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-27, Figure 5-28 and Figure 5-29). Table 5-24. HDQ / 1-Wire Timing Requirements - 1-Wire Mode NO. PARAMETER DESCRIPTION 10 tPDH 11 tPDL 12 tRDV 13 tREL Presence pulse delay high Presence pulse delay low Read data valid time Read data release time MIN 15 60 tLOWR 0 MAX 60 240 15 45 UNIT µs µs µs µs Table 5-25. HDQ / 1-Wire Switching Characteristics - 1-Wire Mode NO. PARAMETER DESCRIPTION MIN 14 tRSTL Reset time low 480 15 tRSTH Reset time high 480 16 tSLOT Bit cycle time 60 17 tLOW1 Write bit-one time 1 18 tLOW0 Write bit-zero time(2) 60 19 tREC Recovery time 1 20 tLOWR Read bit strobe time(1) 1 (1) tLOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window. (2) tLOW0 must be less than tSLOT. MAX 960 120 15 120 15 UNIT µs µs µs µs µs µs µs 1-WIRE tRTSL tPDH tRSTH tPDL 1-WIRE Figure 5-27. 1-Wire—Break (Reset) tLOWR tRDV_and_tREL tSLOT_and_tREC Figure 5-28. 1-Wire—Read Bit (Data) 260 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 1-WIRE TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 tLOW1 tLOW0 tSLOT_and_tREC EARLY PRELIMINARY ADVANCE INFORMATION Figure 5-29. 1-Wire—Write Bit-One Timing (Command / Address or Data) 5.12 Universal Asynchronous Receiver Transmitter (UART) The UART performs serial-to-parallel conversions on data received from a peripheral device and parallelto-serial conversion on data received from the CPU. There are 10 UART modules in the device. Only one UART supports IrDA features. Each UART can be used for configuration and data exchange with a number of external peripheral devices or interprocessor communication between devices The UARTi (where i = 1 to 10) include the following features: • 16C750 compatibility • 64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter • Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed functional clock of 48 MHz or 192 MHz • Break character detection and generation • Configurable data format: – Data bit: 5, 6, 7, or 8 bits – Parity bit: Even, odd, none – Stop-bit: 1, 1.5, 2 bit(s) • Flow control: Hardware (RTS/CTS) or software (XON/XOFF) • Only UART1 module has extended modem control signals (CD, RI, DTS, DSR) • Only UART3 supports IrDA NOTE For more information, see the UART section of the Device TRM. Table 5-26, Table 5-27 and Figure 5-30 assumes testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-26. Timing Requirements for UART NO. PARAMETER DESCRIPTION 4 tw(RX) 5 tw(CTS) td(RTS-TX) td(CTS-TX) Pulse width, receive data bit, 15/30/100pF high or low Pulse width, receive start bit, 15/30/100pF high or low Delay time, transmit start bit to transmit data Delay time, receive start bit to transmit data (1) U = UART baud time = 1/programmed baud rate (2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz). MIN 0.96U(1) 0.96U(1) P(2) P(2) MAX 1.05U(1) 1.05U(1) UNIT ns ns ns ns Table 5-27. Switching Characteristics Over Recommended Operating Conditions for UART NO. PARAMETER f(baud) DESCRIPTION 15 pF Maximum programmable baud rate 30 pF 100 pF MIN MAX UNIT 12 0.23 MHz 0.115 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 261 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-27. Switching Characteristics Over Recommended Operating Conditions for UART (continued) NO. PARAMETER DESCRIPTION 2 tw(TX) 3 tw(RTS) Pulse width, transmit data bit, 15/30/100 pF high or low Pulse width, transmit start bit, 15/30/100 pF high or low (1) U = UART baud time = 1/programmed baud rate MIN U - 2(1) U - 2(1) MAX U + 2(1) U + 2(1) UNIT ns ns UARTi_TXD 3 2 Start Bit Data Bits UARTi_RXD 5 4 Start Bit Data Bits Figure 5-30. UART Timing 5.13 Multichannel Serial Port Interface (MCSPI) The MCSPI is a master/slave synchronous serial bus. There are four separate MCSPI modules (SPI1, SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip selects) and are able to work as both master and slave. The MCSPI modules include the following main features: • Serial clock with programmable frequency, polarity, and phase for each channel • Wide selection of SPI word lengths, ranging from 4 to 32 bits • Up to four master channels, or single channel in slave mode • Master multichannel mode: – Full duplex/half duplex – Transmit-only/receive-only/transmit-and-receive modes – Flexible input/output (I/O) port controls per channel – Programmable clock granularity – SPI configuration per channel. This means, clock definition, polarity enabling and word width • Power management through wake-up capabilities • Programmable timing control between chip select and external clock generation • Built-in FIFO available for a single channel. • Each SPI module supports multiply chipselect pins spim_cs[i], whete i = 1 to 4. NOTE For more information, see the Serial Communication Interface section of the device TRM. NOTE The MCSPIm module (m = 1 to 4) is also referred to as SPIm. 262 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 CAUTION The IO timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are only valid for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETS are defined in the Table 5-30. EARLY PRELIMINARY ADVANCE INFORMATION Table 5-28, Figure 5-31 and Figure 5-32 Presents Timing Requirements for McSPI - Master Mode. Table 5-28. Timing Requirements for SPI - Master Mode (1) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT Fast Mode SM1 tc(SPICLK) Cycle time, spi_sclk (1) (2) 20.8 (3) ns SM2 tw(SPICLKL) Typical Pulse duration, spi_sclk low (1) TBD ns SM3 tw(SPICLKH) Typical Pulse duration, spi_sclk high (1) TBD ns SM4 tsu(MISO-SPICLK) Setup time, spi_d[x] valid before spi_sclk active edge (1) 2.29 ns SM5 th(SPICLK-MISO) Hold time, spi_d[x] valid after spi_sclk active edge (1) 2.67 ns SM6 td(SPICLK-SIMO) Delay time, spi_sclk active edge to spi_d[x] transition (1) -3.57 3.57 ns SM7 td(CS-SIMO) Delay time, spi_cs[x] active edge to spi_d[x] transition 3.57 ns SM8 td(CS-SPICLK) Delay time, spi_cs[x] active to spi_sclk first edge (1) MASTER B-4.2 (5) ns _PHA0 (4) MASTER A-4.2 (6) ns _PHA1 (4) SM9 td(SPICLK-CS) Delay time, spi_sclk last edge to spi_cs[x] inactive (1) MASTER A-4.2 (6) ns _PHA0 (4) MASTER B-4.2 (5) ns _PHA1 (4) Slow Mode SM1 tc(SPICLK) Cycle time, spi_sclk (1) (2) 41.7 (7) ns SM2 tw(SPICLKL) Typical Pulse duration, spi_sclk low (1) TBD ns SM3 tw(SPICLKH) Typical Pulse duration, spi_sclk high (1) TBD ns SM4 tsu(MISO-SPICLK) Setup time, spi_d[x] valid before spi_sclk active edge (1) 3.02 ns SM5 th(SPICLK-MISO) Hold time, spi_d[x] valid after spi_sclk active edge (1) 2.76 ns SM6 td(SPICLK-SIMO) Delay time, spi_sclk active edge to spi_d[x] transition (1) -4.62 4.62 ns SM7 td(CS-SIMO) Delay time, spi_cs[x] active edge to spi_d[x] transition 4.62 ns SM8 td(CS-SPICLK) Delay time, spi_cs[x] active to spi_sclk first edge (1) MASTER B-2.54 ns _PHA0 (5) (4) MASTER A-2.54 ns _PHA1 (6) (4) SM9 td(SPICLK-CS) Delay time, spi_sclk last edge to spi_cs[x] inactive (1) MASTER A-2.54 ns _PHA0 (6) (4) MASTER B-2.54 ns _PHA1 (5) (4) (1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data. (2) Related to the SPI_CLK maximum frequency. (3) Maximum frequency = 48 MHz (4) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 263 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com (5) B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2. (6) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. (7) Maximum frequency = 24 MHz spim_cs(OUT) PHA=0 EPOL=1 spim_sclk(OUT) POL=0 spim_sclk(OUT) POL=1 SM8 SM1 SM2 SM3 SM3 SM1 SM2 SM9 spim_d(OUT) SM7 Bit n-1 SM6 Bit n-2 SM6 Bit n-3 Bit n-4 Bit 0 spim_cs(OUT) PHA=1 EPOL=1 spim_sclk(OUT) POL=0 spim_sclk(OUT) POL=1 spim_d(OUT) SM8 SM2 SM1 SM3 SM1 SM3 SM2 SM9 SM6 SM6 SM6 SM6 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0 Figure 5-31. McSPI - Master Mode Transmit ADVANCE INFORMATION 264 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com spim_cs(OUT) PHA=0 EPOL=1 spim_sclk(OUT) POL=0 POL=1 spim_sclk(OUT) spim_d(IN) TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 SM8 SM1 SM2 SM3 SM3 SM1 SM2 SM4 Bit n-1 SM5 SM4 Bit n-2 SM5 Bit n-3 Bit n-4 Bit 0 SM9 spim_cs(OUT) PHA=1 EPOL=1 spim_sclk(OUT) POL=0 SM8 POL=1 spim_sclk(OUT) SM2 SM1 SM3 SM1 SM3 SM2 SM9 spim_d(IN) SM5 SM4 Bit n-1 SM4 SM5 Bit n-2 Bit n-3 Bit 1 Bit 0 Figure 5-32. McSPI - Master Mode Receive Table 5-29, Figure 5-33 and Figure 5-34 Presents Timing Requirements for McSPI - Slave Mode. Table 5-29. Timing Requirements for SPI - Slave Mode NO. SM1 SM2 SM3 SM4 SM5 SM6 PARAMETER tc(SPICLK) tw(SPICLKL) tw(SPICLKH) tsu(SIMO-SPICLK) th(SPICLK-SIMO) td(SPICLK-SOMI) SM7 SM8 td(CS-SOMI) tsu(CS-SPICLK) DESCRIPTION Cycle time, spi_sclk(1)(2) Typical Pulse duration, spi_sclk low(1) Typical Pulse duration, spi_sclk high(1) Setup time, spi_d[x] valid before spi_sclk active edge(1) Hold time, spi_d[x] valid after spi_sclk active edge(1) Delay time, spi_sclk active edge to mcspi_somi transition(1) Delay time, spi_cs[x] active edge to mcspi_somi transition(4) Setup time, spi_cs[x] valid before spi_sclk first edge(1) MODE (3) SPI1/2/3 SPI4 MIN 62.5 TBD TBD 12.92 12.92 2 -4 12.92 MAX 26.1 17.12 20.95 UNIT ns ns ns ns ns ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 265 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-29. Timing Requirements for SPI - Slave Mode (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SM9 th(SPICLK-CS) Hold time, spi_cs[x] valid after spi_sclk last edge(1) 12.92 ns (1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data. (2) Related to the input maximum frequency supported by the SPI module. (3) Maximum frequency = 16 MHz (4) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register. PHA=0 EPOL=1 spim_cs(IN) SS2 SS1 SS8 SS3 SS9 spim_sclk(IN) POL=0 SS2 SS1 spim_sclk(IN) POL=1 SS3 spim_d(OUT) SS7 Bit n-1 SS6 Bit n-2 SS6 Bit n-3 Bit n-4 Bit 0 PHA=1 EPOL=1 spim_cs(IN) SS2 SS1 SS8 SS3 SS9 spim_sclk(IN) POL=0 SS3 SS1 spim_sclk(IN) POL=1 SS2 spim_d(OUT) SS6 SS6 Bit n-1 Bit n-2 SS6 Bit n-3 SS6 Bit 1 Bit 0 Figure 5-33. McSPI - Slave Mode Transmit 266 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 EARLY PRELIMINARY ADVANCE INFORMATION spim_cs(IN) PHA=0 EPOL=1 spim_sclk(IN) POL=0 POL=1 spim_sclk(IN) spim_d(IN) spim_cs(IN) PHA=1 EPOL=1 spim_sclk(IN) POL=0 spim_sclk(IN) POL=1 SS2 SS1 SS8 SS3 SS9 SS2 SS1 SS3 SS5 SS4 Bit n-1 SS4 SS5 Bit n-2 Bit n-3 Bit n-4 Bit 0 SS2 SS1 SS8 SS3 SS9 SS3 SS1 SS2 spim_d(IN) SS4 SS5 SS4 SS5 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0 Figure 5-34. McSPI - Slave Mode Receive In Table 5-30 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4. Table 5-30. SPI3/4 IOSETs Signal spi3_sclk spi3_d1 spi3_d0 spi3_cs0 spi3_cs1 spi3_cs2 spi3_cs3 spi4_sclk IOSET1 BALL MUX AD9 8 AF9 8 AE9 8 AF8 8 - - - - - - N7 8 IOSET2 BALL MUX E11 8 B10 8 C11 8 D11 8 B11 8 F11 8 A10 8 G1 8 IOSET3 BALL MUX SPI3 V2 7 Y1 7 W9 7 V9 7 - - - - - - SPI4 V7 7 IOSET4 BALL MUX B12 3 A11 3 B13 3 A12 3 E14 3 - - - - AA3 2 IOSET5 BALL MUX C18 2 A21 2 G16 2 D17 2 - - - - - - AC8 1 IOSET6 BALL MUX AC4 1 AC7 1 AC6 1 AC9 1 AC3 1 - - - - - - Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 267 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Signal spi4_d1 spi4_d0 spi4_cs0 spi4_cs1 spi4_cs2 spi4_cs3 IOSET1 BALL MUX R4 8 N9 8 P9 8 P4 8 R3 8 T2 8 Table 5-30. SPI3/4 IOSETs (continued) IOSET2 BALL MUX G6 8 F2 8 F3 8 - - - - - - IOSET3 BALL MUX U7 7 V6 7 U6 7 Y1 8 W9 8 V9 8 IOSET4 BALL MUX AB9 2 AB3 2 AA4 2 - - - - - - IOSET5 BALL MUX AD6 1 AB8 1 AB5 1 - - - - - - IOSET6 BALL MUX - - - - - - - - - - - - 5.14 Quad Serial Port Interface (QSPI) The Quad SPI (QSPI) module is a kind of SPI module that allows single, dual or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. It works as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories. General SPI features: • Programmable clock divider • Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2) • 4 external chip select signals • Support for 3-, 4- or 6-pin SPI interface • Programmable CS_N to DOUT delay from 0 to 3 DCLKs • Programmable signal polarities • Programmable active clock edge • Software controllable interface allowing for any type of SPI transfer NOTE For more information, see the Quad Serial Port Interface section of the Device TRM. Table 5-31 and Table 5-32 Present Timing and Switching Characteristics for Quad SPI Interface. Table 5-31. Switching Characteristics for QSPI No Q1 PARAMETER DESCRIPTION tc(SCLK) Cycle time, sclk Q2 tw(SCLKL) Pulse duration, sclk low Q3 tw(SCLKH) Pulse duration, sclk high Q4 td(CS-SCLK) Delay time, cs active edge to sclk transition, CS3:0 Mode Default Mode (1) QSPI1_VIRTUAL1 Timing Diagram (1) QSPI1_VIRTUAL2 Timing Diagram (1) Default Mode (1) QSPI1_VIRTUAL1 Timing Diagram (1) QSPI1_VIRTUAL2 Timing Diagram (1) MIN MAX 13.5 12.8 12.6 0.48*P (2) 0.48*P (2) –M*P-2.45 (2) (3) -M*P-1.2 (2) (3) -M*P-1.45 (2) (3) –M*P+1.45 (2) (3) -M*P+2.2 (2) (3) -M*P+2.45 (2) (3) UNIT ns ns ns ns ns ns ns ns 268 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-31. Switching Characteristics for QSPI (continued) No PARAMETER DESCRIPTION Mode Q5 td(SCLK-CS) Delay time, sclk transition to cs inactive edge, Default Mode (1) CS3:0 QSPI1_VIRTUAL1 Timing Diagram (1) QSPI1_VIRTUAL2 Timing Diagram (1) Q6 td(SCLK-D1) Delay time, sclk active edge to d[1] transition Default Mode (1) QSPI1_VIRTUAL1 Timing Diagram (1) QSPI1_VIRTUAL2 Timing Diagram (1) Q7 tena(CS-D1LZ) Enable time, cs active edge to d[1] driven (lo-z) Q8 tdis(CS-D1Z) Disable time, cs active edge to d[1] tri-stated (hi-z) Q9 td(SCLKF-D1F) Delay time, sclk first active edge to d[1] first PHA=0 Only transition (1) Maximum frequency 66MHz. Final max frequency TBD until silicon characterization. (2) P = SCLK period. (3) M - Programmable per chip select. MIN M*P-2.45 (2) (3) M*P-1.2 (2) (3) M*P-1.45 (2) (3) -2.45 -1.2 -1.45 5 5 -1-P(2) MAX M*P+1.45 (2) (3) M*P+2.2 (2) (3) M*P+2.45 (2) (3) 1.45 2.2 2.45 5 5 1-P(2) PHA=1 cs Q5 UNIT ns ns ns ns ns ns ns ns ns Q4 POL=1 sclk Q1 Q3 Q2 POL=1 rtclk d[0] d[3:1] Q7 Q6 Q6 Command Command Bit n-1 Bit n-2 Q12 Q13 Read Data Bit 1 Q12 Q13 Read Data Bit 1 Q12 Q13 Read Data Bit 0 Q12 Q13 Read Data Bit 0 Figure 5-35. QSPI Read (PHA=1) SPRS85v_TIMING_OSPI1_01 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 269 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 PHA=0 cs Q4 POL=0 sclk Q1 Q2 Q3 www.ti.com Q5 POL=0 rtclk Q7 d[0] d[3:1] Q9 Q6 Command Command Bit n-1 Bit n-2 Q12 Q13 Read Data Bit 1 Q12 Q13 Read Data Bit 1 Q12 Q13 Read Data Bit 0 Q12 Q13 Read Data Bit 0 Figure 5-36. QSPI Read (PHA=0) SPRS85v_TIMING_OSPI1_02 Table 5-32. Timing Requirements for QSPI No Q12 PARAMETER DESCRIPTION tsu(D-RTCLK) Setup time, d[3:0] valid before active rtclk edge Mode Default Timing Mode, POL=0, PHA=0 Default Timing Mode, POL=1, PHA=1 QSPI1_VIRTUAL1, Timing Mode, POL=0, PHA=0 QSPI1_VIRTUAL1, Timing Mode, POL=1, PHA=1 QSPI1_VIRTUAL2, Timing Mode, POL=0, PHA=0 QSPI1_VIRTUAL2, Timing Mode, POL=1, PHA=1 MIN TBD TBD TBD TBD TBD TBD MAX UNIT ns ns ns ns ns ns 270 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-32. Timing Requirements for QSPI (continued) No PARAMETER DESCRIPTION Mode Q13 th(RTCLK-D) Hold time, d[3:0] valid after active rtclk edge Default Timing Mode, POL=0, PHA=0 Default Timing Mode, POL=1, PHA=1 QSPI1_VIRTUAL1, Timing Mode, POL=0, PHA=0 QSPI1_VIRTUAL1, Timing Mode, POL=1, PHA=1 QSPI1_VIRTUAL2, Timing Mode, POL=0, PHA=0 QSPI1_VIRTUAL2, Timing Mode, POL=1, PHA=1 (1) Maximum frequency 66MHz. Final max frequency TBD until silicon characterization. MIN TBD TBD TBD TBD TBD TBD PHA=1 cs Q5 MAX UNIT ns ns ns ns ns ns Q4 POL=1 sclk Q1 Q3 Q2 Q7 Q6 Q6 Command Command Q6 Write Data Q8 Write Data d[0] Bit n-1 Bit n-2 Bit 1 Bit 0 d[3:1] Figure 5-37. QSPI Write (PHA=1) SPRS85v_TIMING_OSPI1_03 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 271 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com PHA=0 cs Q5 Q4 POL=0 sclk Q1 Q2 Q3 Q9 Q6 Q6 Q8 Q7 Command Command Write Data Write Data d[0] Bit n-1 Bit n-2 Bit 1 Bit 0 ADVANCE INFORMATION d[3:1] Figure 5-38. QSPI Write (PHA=0) SPRS85v_TIMING_OSPI1_04 NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 2-3 and described in Device TRM, Chapter 18 - Control Module. The IO timings in data manual for QSPI1_VIRTUAL1 and QSPI1_VIRTUAL2 are guaranteed if QSPI1_VIRTUAL1 and QSPI1_VIRTUAL2 virtual mode is configured. Table 5-33 present the values for DELAYMODE bitfield. Table 5-33. Virtual Functions Mapping for QSPI BALL NUMBER T7 P6 R3 T2 U2 U1 P3 R2 P2 P1 BALL NAME gpmc_a3 gpmc_a4 gpmc_a13 gpmc_a14 gpmc_a15 gpmc_a16 gpmc_a17 gpmc_a18 gpmc_cs2 gpmc_cs3 Delay Mode Value QSPI1_VIRTUAL1 QSPI1_VIRTUAL2 13 12 13 12 15 14 15 14 15 14 TBD TBD 15 14 14 13 14 13 13 12 MUXMODE[15:0] 1 qspi1_cs2 qspi1_cs3 qspi1_rtclk qspi1_d3 qspi1_d2 qspi1_d1 qspi1_d0 qspi1_sclk qspi1_cs0 qspi1_cs1 5.15 Multichannel Audio Serial Port (McASP) The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT). 272 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 The device have integrated 8 McASP modules (McASP1-McASP8) with : • McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain • McASP3 through McASP8 modules supporting 4 channels with independent TX/RX clock/sync domain • The McASP1 is instantiated in IPU power domain • McASP2 through McASP8 are part of the L4_PER2 peripheral power domain EARLY PRELIMINARY ADVANCE INFORMATION NOTE For more information, see the Serial Communication Interface section of the Device TRM. Table 5-34, Table 5-35, Table 5-36 and Figure 5-39 Presents Timing Requirements for McASP1 to 8. Table 5-34. Timing Requirements for McASP1(1) NO. 1 2 3 4 5 PARAMETER tc(AHCLKRX) tw(AHCLKRX) tc(ACLKRX) tw(ACLKRX) tsu(AFSRX-ACLK) DESCRIPTION Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low Cycle time, ACLKR/X Pulse duration, ACLKR/X high or low Setup time, AFSR/X input valid before ACLKR/X 6 th(ACLK-AFSRX) Hold time, AFSR/X input valid after ACLKR/X 7 tsu(AXR-ACLK) Setup time, AXR input valid before ACLKR/X 8 th(ACLK-AXR) Hold time, AXR input valid after ACLKR/X (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in nano seconds. (3) R = ACLKR/X period in ns. MODE ACLKR/X int ACLKR/X ext in ACLKR/X ext out ACLKR/X int ACLKR/X ext in ACLKR/X ext out ACLKR/X int ACLKR/X ext in ACLKR/X ext out ACLKR/X int ACLKR/X ext in ACLKR/X ext out MIN 20 TBD 20 TBD 19.4 4 4 -1 0.4 0.4 19.4 11.5 11.5 -1 -1 -1 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NO. 1 2 3 4 5 Table 5-35. Timing Requirements for McASP2(1) PARAMETER DESCRIPTION tc(AHCLKRX) tw(AHCLKRX) tc(ACLKRX) Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low Cycle time, ACLKR/X tw(ACLKRX) Pulse duration, ACLKR/X high or low tsu(AFSRX-ACLK) Setup time, AFSR/X input valid before ACLKR/X MODE Any Other Conditions ACLKx, AFSX, and AXR are all inputs Any Other Conditions ACLKx, AFSX, and AXR are all inputs ACLKR/X int ACLKR/X ext in ACLKR/X ext out MIN 20 TBD 20 12.5 TBD TBD 18.5 2 2 MAX UNIT ns ns ns ns ns ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 273 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-35. Timing Requirements for McASP2(1) (continued) NO. 6 PARAMETER DESCRIPTION th(ACLK-AFSRX) Hold time, AFSR/X input valid after ACLKR/X 7 tsu(AXR-ACLK) Setup time, AXR input valid before ACLKR/X 8 th(ACLK-AXR) Hold time, AXR input valid after ACLKR/X (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in nano seconds. (3) R = ACLKR/X period in ns. MODE ACLKR/X int ACLKR/X ext in ACLKR/X ext out ACLKR/X int ACLKR/X ext in ACLKR/X ext out ACLKR/X int ACLKR/X ext in ACLKR/X ext out MIN -1 2 2 18.5 2 2 -1 2 2 Table 5-36. Timing Requirements for McASP3/4/5/6/7/8(1) NO. 1 2 3 4 5 PARAMETER tc(AHCLKRX) tw(AHCLKRX) tc(ACLKRX) tw(ACLKRX) tsu(AFSRX-ACLK) DESCRIPTION Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low Cycle time, ACLKR/X Pulse duration, ACLKR/X high or low Setup time, AFSR/X input valid before ACLKR/X 6 th(ACLK-AFSRX) Hold time, AFSR/X input valid after ACLKR/X 7 tsu(AXR-ACLK) Setup time, AXR input valid before ACLK/X 8 th(ACLK-AXR) Hold time, AXR input valid after ACLK/X (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in nano seconds. (3) R = ACLKR/X period in ns. MODE ACLKR/X int ACLKR/X ext in ACLKR/X ext out ACLKR/X int ACLKR/X ext in ACLKR/X ext out ACLKR/X int (ASYNC=0) ACLKR/X ext in ACLKR/X ext out ACLKR/X int (ASYNC=0) ACLKR/X ext in ACLKR/X ext out MIN 20 TBD 20 TBD 18.2 4 4 -1 0.4 0.4 18.2 11.5 11.5 -1 -1 -1 www.ti.com MAX UNIT ns ns ns ns ns ns ns ns ns MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 274 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 2 1 2 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) AFSR/X (Bit Width, 0 Bit Delay) 4 3 4 6 5 AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). Figure 5-39. McASP Input Timing Table 5-37, Table 5-38, Table 5-39 and Figure 5-40 Presents Switching Characteristics Over Recommended Operating Conditions for McASP1 to 8. Table 5-37. Switching Characteristics Over Recommended Operating Conditions for McASP1(1) NO. 9 10 11 12 13 PARAMETER tc(AHCLKRX) tw(AHCLKRX) tc(ACLKRX) tw(ACLKRX) td(ACLK-AFSXR) DESCRIPTION MODE Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low Cycle time, ACLKR/X Pulse duration, ACLKR/X high or low Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int ACLKR/X ext in ACLKR/X ext out MIN 20 TBD 20 TBD 0 2 2 MAX 6 23.1 23.1 UNIT ns ns ns ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 275 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-37. Switching Characteristics Over Recommended Operating Conditions for McASP1(1) (continued) NO. 14 PARAMETER td(ACLK-AXR) DESCRIPTION Delay time, ACLKR/X transmit edge to AXR output valid 15 tdis(ACLK-AXR) Disable time, ACLKR/X transmit edge to AXR output high impedance; Not Tested (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in ns. (3) R = ACLKR/X period in ns. MODE ACLKR/X int ACLKR/X ext in ACLKR/X ext out ACLKR/X int ACLKR/X ext in ACLKR/X ext out MIN 0 2 2 0 2 2 MAX 6 23.1 23.1 6 23.1 23.1 UNIT ns ns ns ns ns ns Table 5-38. Switching Characteristics Over Recommended Operating Conditions for McASP2 (1) NO. PARAMETER DESCRIPTION MODE 9 tc(AHCLKRX) Cycle time, AHCLKR/X 10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 11 tc(ACLKRX) Cycle time, ACLKR/X 12 tw(ACLKRX) Pulse duration, ACLKR/X high or low 13 td(ACLK-AFSXR) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int ACLKR/X ext in ACLKR/X ext out 14 td(ACLK-AXR) Delay time, ACLKR/X transmit edge to AXR output valid ACLKR/X int ACLKR/X ext in ACLKR/X ext out 15 tdis(ACLK-AXR) Disable time, ACLKR/X transmit edge to AXR output high ACLKR/X int impedance; Not Tested ACLKR/X ext in ACLKR/X ext out (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in ns. (3) R = ACLKR/X period in ns. MIN 20 TBD 20 TBD 0 2 2 0 2 2 0 2 2 MAX 6 22.2 22.2 6 22.2 22.2 6 22.2 22.2 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns Table 5-39. Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8(1) NO. 9 10 11 12 PARAMETER tc(AHCLKRX) tw(AHCLKRX) tc(ACLKRX) tw(ACLKRX) DESCRIPTION Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low Cycle time, ACLKR/X Pulse duration, ACLKR/X high or low MODE MIN 20 TBD 20 TBD MAX UNIT ns ns ns ns 276 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-39. Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8(1) (continued) NO. PARAMETER DESCRIPTION MODE 13 td(ACLK-AFSXR) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int ACLKR/X ext in ACLKR/X ext out 14 td(ACLK-AXR) Delay time, ACLKR/X transmit edge to AXR output valid ACLKR/X int ACLKR/X ext in ACLKR/X ext out 15 tdis(ACLK-AXR) Disable time, ACLKR/X transmit edge to AXR output high ACLKR/X int impedance; Not Tested ACLKR/X ext in ACLKR/X ext out (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in ns. (3) R = ACLKR/X period in ns. MIN 0 2 2 0 2 2 0 2 2 MAX 6 23.1 23.1 6 23.1 23.1 6 23.1 23.1 UNIT ns ns ns ns ns ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 277 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 9 AHCLKR/X (Falling Edge Polarity) 10 10 AHCLKR/X (Rising Edge Polarity) 11 ACLKR/X (CLKRP = CLKXP = 1)(A) 12 12 ACLKR/X (CLKRP = CLKXP = 0)(B) 13 13 AFSR/X (Bit Width, 0 Bit Delay) 13 13 AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) 13 AFSR/X (Slot Width, 0 Bit Delay) 13 13 AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 14 15 AXR[n] (Data Out/Transmit) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). Figure 5-40. McASP Output Timing NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 2-3 and described in Device TRM, Chapter 18 - Control Module. 278 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 The IO timings in data manual for McASP1 Asynchronous Trasmit are guarantee if MCASP1_VIRTUAL1_ASYNC_TX virtual mode is configured. The IO timings in data manual for McASP1 Synchronous Receive are guarantee if MCASP1_VIRTUAL2_SYNC_RX virtual mode is configured. The IO timings in data manual for McASP1 Async Receive are guarantee if MCASP1_VIRTUAL3_ASYNC_RX virtual mode is configured. Table 5-40 present the values for DELAYMODE bitfield. Table 5-40. Virtual Functions Mapping for McASP1 BALL NUMBER E21 F20 F21 D18 E17 B26 C23 C14 D14 B14 J14 G12 F12 G13 J11 E12 F13 C12 D12 B12 A11 B13 A12 E14 A13 BALL NAME gpio6_14 gpio6_15 gpio6_16 xref_clk0 xref_clk1 xref_clk2 xref_clk3 mcasp1_aclkx mcasp1_fsx mcasp1_aclkr mcasp1_fsr mcasp1_axr0 mcasp1_axr1 mcasp1_axr2 mcasp1_axr3 mcasp1_axr4 mcasp1_axr5 mcasp1_axr6 mcasp1_axr7 mcasp1_axr8 mcasp1_axr9 mcasp1_axr10 mcasp1_axr11 mcasp1_axr12 mcasp1_axr13 MCASP1_VIRTUAL1_A SYNC_TX TBD TBD TBD 15 15 TBD TBD 15 15 14 14 15 15 TBD TBD TBD TBD TBD TBD 15 15 15 15 15 15 Delay Mode Value MCASP1_VIRTUAL2_S YNC_RX 15 15 15 15 15 15 15 15 15 N/A N/A 15 15 15 15 15 15 15 15 15 15 15 15 15 15 MCASP1_VIRTUAL3_A SYNC_RX 14 14 14 14 14 14 14 14 14 15 15 14 14 14 14 14 14 14 14 14 14 14 14 14 14 0 mcasp1_aclkx mcasp1_fsx mcasp1_aclkr mcasp1_fsr mcasp1_axr0 mcasp1_axr1 mcasp1_axr2 mcasp1_axr3 mcasp1_axr4 mcasp1_axr5 mcasp1_axr6 mcasp1_axr7 mcasp1_axr8 mcasp1_axr9 mcasp1_axr10 mcasp1_axr11 mcasp1_axr12 mcasp1_axr13 MUXMODE[15:0] 1 2 mcasp1_axr8 mcasp1_axr9 mcasp1_axr10 mcasp1_axr4 mcasp1_axr5 mcasp1_axr6 mcasp1_axr7 3 mcasp1_ahclkx Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Timing Requirements and Switching Characteristics 279 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-40. Virtual Functions Mapping for McASP1 (continued) BALL BALL NAME Delay Mode Value MUXMODE[15:0] NUMBER MCASP1_VIRTUAL1_A MCASP1_VIRTUAL2_S MCASP1_VIRTUAL3_A 0 1 2 3 SYNC_TX YNC_RX SYNC_RX G14 mcasp1_axr14 15 15 14 mcasp1_axr14 F14 mcasp1_axr15 15 15 14 mcasp1_axr15 1. NA in this table stands for Not Applicable. The IO timings in data manual for McASP2 80MHz Async Receive are guarantee if MCASP2_VIRTUAL1_ASYNC_RX_80M virtual mode is configured. The IO timings in data manual for McASP2 Async Receive are guarantee if MCASP2_VIRTUAL2_ASYNC_RX virtual mode is configured. The IO timings in data manual for McASP2 Async Transmit are guarantee if MCASP2_VIRTUAL3_ASYNC_TX virtual mode is configured. The IO timings in data manual for McASP2 Synchronous Receive are guarantee if MCASP2_VIRTUAL4_SYNC_RX virtual mode is configured. The IO timings in data manual for McASP2 80MHz Synchrounous Receive are guarantee if MCASP2_VIRTUAL5_SYNC_RX_80M virtual mode is configured. Table 5-41 present the values for DELAYMODE bitfield. Table 5-41. Virtual Functions Mapping for McASP2 BALL NUM BALL NAME D18 xref_clk0 E17 xref_clk1 B26 xref_clk2 C23 xref_clk3 A19 mcasp2_aclkx A18 mcasp2_fsx E15 mcasp2_aclkr A20 mcasp2_fsr B15 mcasp2_axr0 A15 mcasp2_axr1 C15 mcasp2_axr2 MCASP2_ VIRTUAL1 _ ASYNC_R X_80M 10 10 13 13 15 15 15 15 15 15 15 Delay Mode Value MCASP2_ VIRTUAL2 _ ASYNC_R X MCASP2_ VIRTUAL3 _ ASYNC_TX MCASP2_ VIRTUAL4 _ SYNC_RX 9 14 8 9 14 8 12 TBD 11 12 TBD 11 14 15 10 14 15 10 14 14 N/A 14 14 N/A 14 TBD 13 14 TBD 13 14 15 10 MCASP2_ VIRTUAL5 _ SYNC_RX_ 80M 6 6 10 10 9 9 N/A N/A 12 12 9 0 mcasp2_aclkx mcasp2_fsx mcasp2_aclkr mcasp2_fsr mcasp2_axr0 mcasp2_axr1 mcasp2_axr2 MUXMODE[15:0] 1 2 mcasp2_axr8 mcasp2_axr9 mcasp2_axr10 mcasp2_axr11 3 mcasp2_ahclkx 280 Timing Requirements and Switching Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-41. Virtual Functions Mapping for McASP2 (continued) BALL NUM BALL NAME Delay Mode Value MCASP2_ VIRTUAL1 _ ASYNC_R X_80M MCASP2_ VIRTUAL2 _ ASYNC_R X MCASP2_ VIRTUAL3 _ ASYNC_TX MCASP2_ VIRTUAL4 _ SYNC_RX MCASP2_ VIRTUAL5 _ SYNC_RX_ 80M A16 mcasp2_axr3 15 14 15 10 9 D15 mcasp2_axr4 15 14 TBD 13 12 B16 mcasp2_axr5 15 14 TBD 13 12 B17 mcasp2_axr6 15 14 TBD 13 12 A17 mcasp2_axr7 15 14 TBD 13 12 B18 mcasp3_aclkx 15 14 15 10 9 F15 mcasp3_fsx 15 14 15 10 9 B19 mcasp3_axr0 15 14 15 10 9 C17 mcasp3_axr1 15 14 15 10 8 1. NA in this table stands for Not Applicable. 0 mcasp2_axr3 mcasp2_axr4 mcasp2_axr5 mcasp2_axr6 mcasp2_axr7 MUXMODE[15:0] 1 2 3 mcasp2_axr12 mcasp2_axr13 mcasp2_axr14 mcasp2_axr15 The IO timings in data manual for McASP[8:3] Synchronous Receive mode are guarantee if virtual mode is configured. Table 5-42 present the values for DELAYMODE bitfield. Table 5-42. Virtual Functions Mapping for McASP3/4/5/6/7/8 BALL NUMBER BALL NAME Delay Mode Value MUXMODE[15:0] 0 1 2 MCASP3_VIRTUAL2_SYNC_RX C15 mcasp2_axr2 8 mcasp3_axr2 A16 mcasp2_axr3 8 mcasp3_axr3 B18 mcasp3_aclkx 8 mcasp3_aclkx mcasp3_aclkr F15 mcasp3_fsx 8 mcasp3_fsx mcasp3_fsr B19 mcasp3_axr0 8 mcasp3_axr0 C17 mcasp3_axr1 6 mcasp3_axr1 MCASP4_VIRTUAL1_SYNC_RX E12 mcasp1_axr4 13 mcasp4_axr2 F13 mcasp1_axr5 13 mcasp4_axr3 C18 mcasp4_aclkx 15 mcasp4_aclkx mcasp4_aclkr A21 mcasp4_fsx 15 mcasp4_fsx mcasp4_fsr Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Timing Requirements and Switching Characteristics 281 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 BALL NUMBER G16 D17 C12 D12 AA3 AB9 AB3 AA4 G13 J11 B12 A11 B13 A12 B14 J14 E14 A13 G14 F14 E15 A20 D15 B16 B17 A17 Table 5-42. Virtual Functions Mapping for McASP3/4/5/6/7/8 (continued) BALL NAME mcasp4_axr0 mcasp4_axr1 mcasp1_axr6 mcasp1_axr7 mcasp5_aclkx mcasp5_fsx mcasp5_axr0 mcasp5_axr1 mcasp1_axr2 mcasp1_axr3 mcasp1_axr8 mcasp1_axr9 mcasp1_axr10 mcasp1_axr11 mcasp1_aclkr mcasp1_fsr mcasp1_axr12 mcasp1_axr13 mcasp1_axr14 mcasp1_axr15 mcasp2_aclkr mcasp2_fsr mcasp2_axr4 mcasp2_axr5 mcasp2_axr6 mcasp2_axr7 Delay Mode Value 0 15 mcasp4_axr0 15 mcasp4_axr1 MCASP5_VIRTUAL1_SYNC_RX 13 13 15 mcasp5_aclkx 15 mcasp5_fsx 15 mcasp5_axr0 15 mcasp5_axr1 MCASP6_VIRTUAL1_SYNC_RX 13 13 10 10 10 10 MCASP7_VIRTUAL2_SYNC_RX 14 14 10 10 10 10 MCASP8_VIRTUAL1_SYNC_RX 13 13 11 11 11 11 MUXMODE[15:0] 1 mcasp5_axr2 mcasp5_axr3 mcasp5_aclkr mcasp5_fsr mcasp6_axr2 mcasp6_axr3 mcasp6_axr0 mcasp6_axr1 mcasp6_aclkx mcasp6_fsx mcasp7_axr2 mcasp7_axr3 mcasp7_axr0 mcasp7_axr1 mcasp7_aclkx mcasp7_fsx mcasp8_axr2 mcasp8_axr3 mcasp8_axr0 mcasp8_axr1 mcasp8_aclkx mcasp8_fsx www.ti.com 2 mcasp6_aclkr mcasp6_fsr mcasp7_aclkr mcasp7_fsr mcasp8_aclkr mcasp8_fsr 282 Timing Requirements and Switching Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 EARLY PRELIMINARY ADVANCE INFORMATION 5.16 Universal Serial Bus (USB) SuperSpeed USB DRD Subsystem has four instances in the device providing the following functions: • USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0) PHY and HS/FS (USB2.0) PHY. • USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY. • USB3: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS PHYs. • USB4: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS PHYs. NOTE For more information, see the SuperSpeed USB DRD section of the Device TRM. 5.16.1 USB1 DRD PHY The USB1 DRD interface supports the following applications: • USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum data rate of 480 Mbps. • USB3.0 Super-Speed PHY port (1.8 V): this asynchronous differential super-speed interface is compliant with the USB3.0 RX/TX PHY standard (USB3.0 standard v1.0) for a maximum data bit rate of 5Gbps. 5.16.2 USB2 PHY The USB2 interface supports the following applications: • USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum data rate of 480 Mbps. 5.16.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode—1.8 V TheUSB3 and USB4 DRD interfaces support the following application: • USB ULPI port (1.8 V): this synchronous interface is compliant with the USB2.0 ULPI SDR standard (UTMI+ v1.22), for alternative off-chip USB2.0 PHY interface; that is, with external transceiver with a maximum frequency of 60 MHz (synchronous slave mode, SDR, 12-pin, 8-data-bit). NOTE The Universal Serial Bus k ULPI modules are also refered as USBk where k = 3, 4. Table 5-43, Table 5-44 and Figure 5-41 assumes testing over the recommended operating conditions and electrical characteristic conditions. Table 5-43. Timing Requirements for ULPI SDR Slave Mode NO. US1 US2 US3 PARAMETER tc(clk) tw(clkH) tw(clkL) tj(clk) DESCRIPTION Cycle time, usb_ulpi_clk period Pulse duration, usb_ulpi_clk high Pulse duration, usb_ulpi_clk low Jitter standard deviation, usb_ulpi_clk MIN 16.66 TBD TBD MAX TBD UNIT ns ns ns ps Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 283 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-43. Timing Requirements for ULPI SDR Slave Mode (continued) NO. US5 US6 US7 US8 PARAMETER tsu(ctrlV-clkH) th(clkH-ctrlV) tsu(dV-clkH) th(clkH-dV) DESCRIPTION Setup time, usb_ulpi_dir/usb_ulpi_nxt valid before usb_ulpi_clk rising edge Hold time, usb_ulpi_dir/usb_ulpi_nxt valid after usb_ulpi_clk rising edge Setup time, usb_ulpi_d[7:0] valid before usb_ulpi_clk rising edge Hold time, usb_ulpi_d[7:0] valid after usb_ulpi_clk rising edge MIN 6.73 -0.41 6.73 -0.41 MAX www.ti.com UNIT ns ns ns ns Table 5-44. Switching Characteristics for ULPI SDR Slave Mode NO. US4 US9 PARAMETER td(clkH-stpV) tR(stp) tF(stp) td(clkL-doV) tR(d) tF(d) DESCRIPTION Delay time, usb_ulpi_clk rising edge high to output usb_ulpi_stp valid Rising time, usb_ulpi_stp Falling time, usb_ulpi_stp Delay time, usb_ulpi_clk rising edge high to output usb_ulpi_d[7:0] valid Rising time, usb_ulpi_d[7:0] Falling time, usb_ulpi_d[7:0] MIN 0.44 0.44 MAX 8.35 TBD TBD 8.35 TBD TBD UNIT ns ns ns ns ns ns usbk_ulpi_clk usbk_ulpi_stp usbk_ulpi_dir_&_nxt usbk_ulpi_d[7:0] US1 US2 US3 US4 US4 US7 Data_IN US9 US8 US6 US5 US9 Data_OUT Figure 5-41. HS USB3 and USB4 ULPI —SDR—Slave Mode—12-pin Mode—1.8 V ADVANCE INFORMATION 5.17 Serial Advanced Technology Attachment (SATA) The SATA RX/TX PHY interface is compliant with the SATA standard v2.6 for a maximum data rate: • Gen2i, Gen2m, Gen2x: 3Gbps. • Gen1i, Gen1m, Gen1x: 1.5Gbps. NOTE For more information, see the SATA Controller section of the Device TRM. 5.18 Peripheral Component Interconnect Express (PCIe) The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane) (Single Lane and Flexible dual lane configuration). The device PCIe supports the following features: 284 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 • 16-bit operation @250 MHz on PIPE interface (per 16-bit lane) • Supports 2 ports x 1 lane or 1 port x 2 lanes configuration • Single virtual channel (VC0), single traffic class (TC0) • Single function in end-point mode • Automatic width and speed negotiation • Max payload: 128 byte outbound, 256 byte inbound • Automatic credit management • ECRC generation and checking • Configurable BAR filtering • Legacy interrupt reception (RC) and generation (EP) • MSI generation and reception • PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions) • All PCI Device Power Management D-states with the exception of D3cold / L2 state The PCIe peripheral on the device conforms to the PCI Express Base standard 3.0 version 3.0. and PCI local bus specification version 3.0. NOTE For more information, see the PCIe Controller section of the Device TRM. 5.19 Controller Area Network Interface (DCAN) The device provides two DCAN interfaces for supporting distributed realtime control with a high level of security. The DCAN interfaces implement the following features: • Supports CAN protocol version 2.0 part A, B • Bit rates up to 1 MBit/s • 64 message objects • Individual identifier mask for each message object • Programmable FIFO mode for message objects • Programmable loop-back modes for self-test operation • Suspend mode for debug support • Software module reset • Automatic bus on after Bus-Off state by a programmable 32-bit timer • Direct access to Message RAM during test mode • CAN Rx/Tx pins are configurable as general-purpose IO pins • Two interrupt lines (plus additional parity-error interrupts line) • RAM initialization • DMA support NOTE For more information, see the DCAN section of the Device TRM. NOTE The Controller Area Network Interface x (x = 1 to 2) is also referred to as DCANx. Table 5-45, Table 5-46 and Figure 5-42 Presents timing and switching characteristics for DCANx Interface. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 285 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-45. Timing Requirements for DCANx Receive(1) NO. PARAMETER DESCRIPTION f(baud) Maximum programmable baud rate 1 tw(DCANRX) Pulse duration, receive data bit (DCANx_RX) (1) H = period of baud rate, 1/programmed baud rate. MIN H-2 NOM MAX 1 H+2 UNIT Mbps ns Table 5-46. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit (1) NO. PARAMETER DESCRIPTION f(baud) Maximum programmable baud rate 2 tw(DCANTX) Pulse duration, transmit data bit (DCANx_TX) (1) H = period of baud rate, 1/programmed baud rate. MIN H-2 MAX 1 H+2 UNIT Mbps ns 1 DCANx_RX DCANx_TX 2 Figure 5-42. DCANx Timings 5.20 Ethernet Interface (GMAC_SW) The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication and can be configured as an ethernet switch. It provides the Gigabit Media Independent Interface (G/MII) in MII mode, Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY) management. NOTE For more information, see the Ethernet Subsystem section of the Device TRM. ADVANCE INFORMATION NOTE The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as MIIn, RMIIn and RGMIIn Table 5-47 and Figure 5-43 Presents timing requirements for MIIn in receive operation. 5.20.1 GMAC MII Timings Table 5-47. Timing Requirements for miin_rxclk - MII Operation NO. PARAMETER DESCRIPTION 1 tc(RX_CLK) Cycle time, miin_rxclk 2 tw(RX_CLKH) Pulse duration, miin_rxclk high 3 tw(RX_CLKL) Pulse duration, miin_rxclk low SPEED 10 Mbps 100 Mbps 10 Mbps 100 Mbps 10 Mbps 100 Mbps MIN 399.96 39.996 140 14 140 14 MAX 400.04 40.004 260 26 260 26 UNIT ns ns ns ns ns ns 286 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-47. Timing Requirements for miin_rxclk - MII Operation (continued) NO. PARAMETER DESCRIPTION 4 tt(RX_CLK) Transition time, miin_rxclk SPEED 10 Mbps 100 Mbps MIN TBD TBD MAX TBD TBD UNIT ns ns miin_rxclk 1 2 4 3 4 Figure 5-43. Clock Timing (GMAC Receive) - MIIn operation Table 5-48 and Figure 5-44 Presents timing requirements for MIIn in transmit operation. Table 5-48. Timing Requirements for miin_txclk - MII Operation NO. PARAMETER DESCRIPTION 1 tc(TX_CLK) Cycle time, miin_txclk 2 tw(TX_CLKH) Pulse duration, miin_txclk high 3 tw(TX_CLKL) Pulse duration, miin_txclk low 4 tt(TX_CLK) Transition time, miin_txclk SPEED 10 Mbps 100 Mbps 10 Mbps 100 Mbps 10 Mbps 100 Mbps 10 Mbps 100 Mbps MIN 399.96 39.996 140 14 140 14 TBD TBD MAX 400.04 40.004 260 26 260 26 TBD TBD UNIT ns ns ns ns ns ns ns ns 1 2 4 3 miin_txclk 4 Figure 5-44. Clock Timing (GMAC Transmit) - MIIn operation Table 5-49 and Figure 5-45 Presents timing requirements for GMAC MIIn Receive 10/100Mbit/s. Table 5-49. Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s NO. 1 2 PARAMETER tsu(RXD-RX_CLK) tsu(RX_DV-RX_CLK) tsu(RX_ER-RX_CLK) th(RX_CLK-RXD) th(RX_CLK-RX_DV) th(RX_CLK-RX_ER) DESCRIPTION Setup time, receive selected signals valid before miin_rxclk Hold time, receive selected signals valid after miin_rxclk MIN MAX 8 8 UNIT ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 287 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 1 2 www.ti.com miin_rxclk (Input) miin_rxd3−miin_rxd0, miin_rxdv, miin_rxer (Inputs) Figure 5-45. GMAC Receive Interface Timing MIIn operation Table 5-50 and Figure 5-46 Presents timing requirements for GMAC MIIn Transmit 10/100Mbit/s. Table 5-50. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s NO. 1 PARAMETER td(TX_CLK-TXD) td(TX_CLK-TX_EN) DESCRIPTION Delay time, miin_txclk to transmit selected signals valid MIN MAX UNIT 0 25 ns 1 miin_txclk (input) miin_txd3 − miin_txd0, miin_txen (outputs) Figure 5-46. GMAC Transmit Interface Timing MIIn operation 5.20.2 GMAC MDIO Interface Timings Table 5-51, Table 5-51 and Figure 5-47 Presents timing requirements for MDIO. Table 5-51. Timing Requirements for MDIO Input No PARAMETER MDIO1 MDIO2 MDIO3 MDIO4 MDIO5 tc(MDC) tw(MDCH) tw(MDCL) tsu(MDIO-MDC) th(MDIO_MDC) DESCRIPTION Cycle time, MDC Pulse Duration, MDC High Pulse Duration, MDC Low Setup time, MDIO valid before MDC High Hold time, MDIO valid from MDC High MIN MAX UNIT 400 ns 160 ns 160 ns 90 ns 0 ns Table 5-52. Switching Characteristics Over Recommended Operating Conditions for MDIO Output NO PARAMETER MDIO6 tt(MDC) MDIO7 td(MDC-MDIO) DESCRIPTION Transition time, MDC Delay time, MDC High to MDIO valid MIN MAX UNIT 5 ns 10 390 ns 288 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 EARLY PRELIMINARY ADVANCE INFORMATION MDCLK MDIO (input) 1 MDIO2 MDIO3 MDIO6 MDIO4 MDIO5 MDIO6 MDIO (output) MDIO7 Figure 5-47. GMAC MDIO diagrams 5.20.3 GMAC RMII Timings The main reference clock REF_CLK (RMII_50MHZ_CLK) of RMII interface is internally supplied from PRCM. The source of this clock could be either externally sourced from the RMII_MHZ_50_CLK pin of the device or internally generated from DPLL_GMAC output clock GMAC_RMII_HS_CLK. Please see the PRCM chapter of the device TRM for full details about RMII reference clock. Table 5-53 and Figure 5-48 Presents timing requirements for GMAC RMIIn Receive. Table 5-53. Timing Requirements for GMAC RMIIn Receive NO. PARAMETER RMII1 RMII2 RMII3 RMII4 RMII5 RMII6 tc(REF_CLK) tw(REF_CLKH) tw(REF_CLKL) ttt(REF_CLK) tsu(RXD-REF_CLK) tsu(CRS_DV-REF_CLK) tsu(RX_ER-REF_CLK) th(REF_CLK-RXD) th(REF_CLK-CRS_DV) th(REF_CLK-RX_ER) DESCRIPTION Cycle time, REF_CLK Pulse duration, REF_CLK high Pulse duration, REF_CLK low Transistion time, REF_CLK Setup time, receive selected signals valid before REF_CLK Hold time, receive selected signals valid after REF_CLK MIN 20 7 7 TBD 4 2 MAX 13 13 TBD UNIT ns ns ns ns ns ns REF_CLK (PRCM) RMII4 RMII3 RMII1 RMII2 RMII5 RMII6 rmiin_rxd1−rmiin_rxd0, rmiin_crs, rmin_rxer (inputs) Figure 5-48. GMAC Receive Interface Timing RMIIn operation SPRS8xx_GMAC_RMIIRX_05 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 289 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-54 and Figure 5-49 Presents switching characteristics for GMAC RMIIn Transmit 10/100Mbit/s. Table 5-54. Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s NO. RMII7 RMII8 RMII9 RMII10 RMII11 PARAMETER tc(REF_CLK) tw(REF_CLKH) tw(REF_CLKL) ttt(REF_CLK) td(REF_CLK-TXD) tdd(REF_CLK-TXEN) td(REF_CLK-TXD) tdd(REF_CLK-TXEN) DESCRIPTION Cycle time, REF_CLK Pulse duration, REF_CLK high Pulse duration, REF_CLK low Transistion time, REF_CLK Delay time, REF_CLK high to selected transmit signals valid RMIIn RMII0 RMII1 MIN 20 7 7 TBD 2 2 MAX 13 13 TBD 13.5 UNIT ns ns ns ns ns 13.8 ns REF_CLK (PRCM) RMII7 RMII8 RMII11 RMII9 RMII10 rmiin_txd1−rmiin_txd0, rmiin_txen (Outputs) Figure 5-49. GMAC Transmit Interface Timing RMIIn Operation SPRS8xx_GMAC_RMIITX_06 5.20.4 GMAC RGMII Timings Table 5-55, Table 5-56 and Figure 5-50 Presents timing requirements for receive RGMIIn operation. Table 5-55. Timing Requirements for rgmiin_rxc - RGMIIn Operation NO. PARAMETER DESCRIPTION 1 tc(RXC) Cycle time, rgmiin_rxc 2 tw(RXCH) Pulse duration, rgmiin_rxc high 3 tw(RXCL) Pulse duration, rgmiin_rxc low 4 tt(RXC) Transition time, rgmiin_rxc SPEED 10 Mbps 100 Mbps 1000 Mbps 10 Mbps 100 Mbps 1000 Mbps 10 Mbps 100 Mbps 1000 Mbps 10 Mbps 100 Mbps 1000 Mbps MIN 360 36 7.2 160 16 3.6 160 16 3.6 TBD TBD TBD MAX 440 44 8.8 240 24 4.4 240 24 4.4 TBD TBD TBD UNIT ns ns ns ns ns ns ns ns ns ns ns ns 290 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-56. Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps NO. PARAMETER DESCRIPTION MIN MAX 5 tsu(RXD-RXCH) 6 th(RXCH-RXD) Setup time, receive selected signals valid before rgmiin_rxc high/low 1 Hold time, receive selected signals valid after rgmiin_rxc high/low 1 (1) For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl. UNIT ns ns rgmiin_rxc(A) rgmiin_rxd[3:0](B) 1 2 3 4 4 5 1st Half-byte 2nd Half-byte 6 RGRXD[3:0] RGRXD[7:4] rgmiin_rxctl(B) RXDV RXERR A. rgmiin_rxc must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc. Figure 5-50. GMAC Receive Interface Timing, RGMIIn operation Table 5-57, Table 5-58 and Figure 5-51 Presents switching characteristics for transmit - RGMIIn for 10/100/1000Mbit/s. Table 5-57. Switching Characteristics Over Recommended Operating Conditions for transmit - RGMIIn operation for 10/100/1000 Mbit/s NO. PARAMETER DESCRIPTION 1 tc(TXC) Cycle time, rgmiin_txc 2 tw(TXCH) Pulse duration, rgmiin_txc high 3 tw(TXCL) Pulse duration, rgmiin_txc low 4 tt(TXC) Transition time, rgmiin_txc SPEED MIN MAX UNIT 10 Mbps 360 440 ns 100 Mbps 36 44 ns 1000 Mbps 7.2 8.8 ns 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns 10 Mbps 0.75 ns 100 Mbps 0.75 ns 1000 Mbps 0.75 ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 291 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-58. Switching Characteristics Over Recommended Operating Conditions for GMAC RGMIIn Transmit NO. PARAMETER DESCRIPTION 5 tsu(TXD-TXCH) Setup time, transmit selected signals valid before rgmiin_txc high/low 6 th(TXCH-TXD) Hold time, transmit selected signals valid after rgmiin_txc high/low (1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl. MODE Internal delay enabled Internal delay enabled MIN MAX UNIT 1.2 ns 1.2 ns rgmiin_txc(A) [internal delay enabled] 1 4 2 3 4 5 rgmiin_txd[3:0](B) 1st Half-byte 2nd Half-byte 6 rgmiin_txctl(B) TXEN TXERR A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled. B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc. Figure 5-51. GMAC Transmit Interface Timing RGMIIn operation 5.21 Media Local Bus (MLB) interface The MLBSS allows connection to a MOST (Media Oriented Systems Transport) network controller for transport of media and control data between multimedia nodes. The MLBSS supports the following features: • 3 pin mode compliant to MediaLB Physical Layer Specification v4.0 • 6 pin mode (3 differential pairs) compliant to MediaLB Physical Layer Specification v4.0 • Supports 256/512/1024Fs in 3 pin mode and 2048Fs in 6 pin mode • Supports all types of transfer (Sync, Isoc, Async/Packet, Control) over 64 logical channels • 16KB buffering for synchronous /isochronous/control/packet data in the subsystem NOTE For more information, see the Media Local Bus (MLB) section of the Device TRM. Table 5-59 and Figure 5-52 Present Timing Requirements for MLKCLK 3-Pin Option. Table 5-59. Timing Requirements for MLBCLK 3-Pin Option (1) NO. 1 2 3 PARAMETER tc(MLBCLK) tw(MLBCLK) tw(MLBCLK) DESCRIPTION Cycle time, MLB_CLK Pulse duration, MLB_CLK high Pulse duration, MLB_CLK low MODE MIN 512FS 39 1024FS 19.5 512FS 14 1024FS 9.3 512FS 14 1024FS 6.1 MAX UNIT ns ns ns ns ns ns 292 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-59. Timing Requirements for MLBCLK 3-Pin Option (1) (continued) NO. PARAMETER DESCRIPTION MODE MIN 4 tt(MLBCLK) Transition time, MLB_CLK high 512FS 1024FS 4 ttf(MLBCLK) Transition time, MLB_CLK low 512FS 1024FS (1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. MAX 3 1 3 1 UNIT ns ns ns ns 2 1 4 MLB_CLK 3 4 Figure 5-52. MLB_CLK Timing Table 5-60 and Table 5-61 Present Timing Requirements and Switching Characteristics for MLB 3-Pin Option. Table 5-60. Timing Requirements for Receive Data for the MLB 3-Pin Option NO. PARAMETER DESCRIPTION MODE 5 tsu(MLBDAT-MLBCLKL) Setup time, MLB_DAT/MLB_SIG input valid before MLB_CLK 512FS low 1024FS 6 th(MLBCLKL-MLBDAT) Hold time, MLB_DAT/MLB_SIG input valid after MLB_CLK 512FS low 1024FS MIN MAX UNIT 1 ns 1 ns 4 ns 2 ns Table 5-61. Switching Characteristics Over Recommended Operating Conditions for MLB 3-Pin Option NO. PARAMETER DESCRIPTION 7 td(MLBCLKH-MLBDATV) Delay time, MLBCLKH rising to MLB_DAT/MLB_SIG valid 8 tdis(MLBCLKL- MLBDATZ) Disable time, MLBCLKH falling to MLB_DAT/MLB_SIG Hi-Z MODE 512FS 1024FS 512FS 1024FS MIN MAX UNIT 0 10 ns 0 7 ns 0 14 ns 0 6.1 ns Table 5-62 and Figure 5-52 Present Timing Requirements for MLKCLK 6-Pin Option. Table 5-62. Timing Requirements for MLBCLK 6-Pin Option (1) NO. 1 2 3 4 4 PARAMETER tc(MLBCLKx) tw(MLBCLKx) tw(MLBCLKx) tt(MLBCLKx) ttf(MLBCLKx) DESCRIPTION Cycle time, MLB_CLKP/N Pulse duration, MLB_CLKP/N high Pulse duration, MLB_CLKP/N low Transition time, MLB_CLKP/N high Transition time, MLB_CLKP/N low MODE 2048FS 2048FS 2048FS 2048FS 2048FS MIN MAX UNIT 10 ns 4.5 ns 4.5 ns 1 ns 1 ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 293 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com (1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. Table 5-63 and Table 5-64 Present Timing Requirements and Switching Characteristics for MLB 6-Pin Option. Table 5-63. Timing Requirements for Receive Data for the MLB 6-Pin Option (1) NO. PARAMETER DESCRIPTION 5 tsu(DATx-CLKxH) Setup time, MLBP_DATx/MLBP_SIGx input valid before MLBP_CLKx rising 6 th(CLKxH-DATx) Hold time, MLBP_DATx/MLBP_SIGx input valid after MLBP_CLKx rising (1) MLBP_SIGx/MLBP_DATx is valid at the receiver input for at least TBD. MODE 2048FS 2048FS MIN MAX UNIT 1 ns 0.5 ns Table 5-64. Switching Characteristics Over Recommended Operating Conditions for MLB 6-Pin Option (1) NO. PARAMETER DESCRIPTION MODE MIN 7 td(CLKxH-DATxV) Delay time, MLBPCLKxH rising to MLB_DATx/MLB_SIGx valid 2048FS 0.5 8 tdis(CLKPH-DATPZ) Disable time, MLBPCLKxH rising to MLBP_DATx/MLBP_SIGx 2048FS 0.5 Hi-Z (1) MLBP_SIGx/MLBP_DATx is valid at the receiver input for at least TBD. MAX 7 7 UNIT ns ns 5.22 eMMC/SD/SDIO The Device includes the following external memory interfaces 4 MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO) NOTE The eMMC/SD/SDIOi (i = 1 to 4) controller is also referred to as MMCi. ADVANCE INFORMATION 5.22.1 MMC1—SD Card Interface MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card applications: • Default speed at 24 MHz, 4-bit data, SDR, half-cycle, 3.3 V • High speed at 48 MHz, 4-bit data, SDR, half-cycle, 3.3 V • SDR12 at 24 MHz, 4-bit data, half-cycle, 1.8 V • SDR25 at 48 MHz, 4-bit data, half-cycle, 1.8 V • UHS-I SDR50 at 96 MHz, 4-bit data, half-cycle, 1.8 V • UHS-I SDR104 at 192 MHz, 4-bit data, half-cycle, 1.8 V • UHS-I DDR50 at 48 MHz, 4-bit data, 1.8 V NOTE For more information, see the eMMC/SD/SDIO chapter of the Device TRM. 5.22.1.1 Default speed at 24 MHz, 4-bit data, SDR, half-cycle, 3.3 V Table 5-65 and Table 5-66 Presents Timing requirements and Switching characteristics for MMC1 Default Speed in receiver and transmiter mode.(see Figure 5-53 and Figure 5-54) Table 5-65. Timing Requirements for MMC1 - SD Card Default Speed Mode NO. PARAMETER DSSD5 tsu(dV-clkH) DESCRIPTION Setup time, mmc1_cmd valid before mmc1_clk rising clock edge MIN MAX UNIT 2.1 ns 294 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-65. Timing Requirements for MMC1 - SD Card Default Speed Mode (continued) NO. DSSD6 DSSD7 DSSD8 PARAMETER th(clkH-dV) tsu(dV-clkH) th(clkH-dV) DESCRIPTION Hold time, mmc1_cmd valid after mmc1_clk rising clock edge Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge MIN 19.1 2.1 19.1 MAX UNIT ns ns ns Table 5-66. Switching Characteristics for MMC1 - SD Card Default Speed Mode NO. PARAMETER DESCRIPTION DSSD0 DSSD1 DSSD2 DSSD3 DSSD4 fop(clk) tw(clkH) tw(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) tR(do) tF(do) td(clkL-doV) tR(do) tF(do) Operating frequency, mmc1_clk Pulse duration, mmc1_clk high Pulse duration, mmc1_clk low Jitter standard deviation (1), mmc1_clk Rising time, mmc1_clk Falling time, mmc1_clk Delay time, mmc1_clk falling clock edge to mmc1_cmd transition Rising time, mmc1_cmd Falling time, mmc1_cmd Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition Rising time, mmc1_dat[3:0] Falling time, mmc1_dat[3:0] (1) This number is a typical value MIN TBD TBD TBD –11.1 –11.1 MAX 24 TBD TBD TBD 11.1 TBD TBD 11.1 TBD TBD UNIT MHz ns ns ns ns ns ns ns ns ns ns ns DSSD2 DSSD1 DSSD0 mmc1_clk DSSD6 mmc1_cmd DSSD5 DSSD8 mmc1_dat[3:0] DSSD7 MMC1_01 Figure 5-53. MMC/SD/SDIO in - Default Speed 3.3V Signaling - Receiver Mode mmcx_clk mmcx_cmd mmcx_dat[3:0] DSSD2 DSSD1 DSSD0 DSSD3 DSSD4 Figure 5-54. MMC/SD/SDIO in - High Speed SDR12 - Transmiter Mode MMC1_02 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 295 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 5.22.1.2 High speed at 48 MHz, 4-bit data, SDR, half-cycle, 3.3 V Table 5-67 and Table 5-68 Presents Timing requirements and Switching characteristics for MMC1 - High Speed in receiver and transmiter mode.(see Figure 5-55 and Figure 5-56) Table 5-67. Timing Requirements for MMC1 - SD Card High Speed NO. PARAMETER DESCRIPTION MIN MAX UNIT HSSD3 tsu(dV-clkH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 4.6 ns HSSD4 th(clkH-dV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 2.1 ns HSSD7 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 4.6 ns HSSD8 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge 2.1 ns Table 5-68. Switching Characteristics for MMC1 - SD Card High Speed NO. PARAMETER DESCRIPTION HSSD1 HSSD2H HSSD2L HSSD5 HSSD6 fop(clk) tw(clkH) tw(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) tR(do) tF(do) td(clkL-doV) tR(do) tF(do) Operating frequency, mmc1_clk Pulse duration, mmc1_clk high Pulse duration, mmc1_clk low Jitter standard deviation (1), mmc1_clk Rising time, mmc1_clk Falling time, mmc1_clk Delay time, mmc1_clk falling clock edge to mmc1_cmd transition Rising time, mmc1_cmd Falling time, mmc1_cmd Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition Rising time, mmc1_dat[3:0] Falling time, mmc1_dat[3:0] (1) This number is a typical value MIN TBD TBD TBD –5.7 –5.7 MAX 48 TBD TBD TBD 1.3 TBD TBD 1.3 TBD TBD UNIT MHz ns ns ns ns ns ns ns ns ns ns ns mmc1_clk mmc1_cmd mmc1_dat[3:0] HSSD1 HSSD2L HSSD3 HSSD7 HSSD2H HSSD4 HSSD8 Figure 5-55. MMC/SD/SDIO in - High Speed 3.3V Signaling - Receiver Mode MMC1_03 296 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 mmc1_clk HSSD1 HSSD2H HSSD2L mmc1_cmd mmc1_dat[3:0] HSSD5 HSSD6 HSSD5 HSSD6 MMC1_04 Figure 5-56. MMC/SD/SDIO in - High Speed 3.3V Signaling - Transmiter Mode 5.22.1.3 SDR12 at 24 MHz, 4-bit data, half-cycle, 1.8 V Table 5-69 and Table 5-70 Presents Timing requirements and Switching characteristics for MMC1 SDR12 in receiver and transmiter mode.(see Figure 5-57 and Figure 5-58) Table 5-69. Timing Requirements for MMC1 - SD Card SDR12 Mode NO. SDR125 SDR126 SDR127 SDR128 PARAMETER tsu(dV-clkH) th(clkH-dV) tsu(dV-clkH) th(clkH-dV) DESCRIPTION Setup time, mmc1_cmd valid before mmc1_clk rising clock edge Hold time, mmc1_cmd valid after mmc1_clk rising clock edge Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge MIN 2.2 19.1 2.2 19.1 MAX UNIT ns ns ns ns Table 5-70. Switching Characteristics for MMC1 - SD Card SDR12 Mode NO. SDR120 SDR121 SDR122 SDR123 SDR124 PARAMETER fop(clk) tw(clkH) tw(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) tR(do) tF(do) td(clkL-doV) tR(do) tF(do) DESCRIPTION Operating frequency, mmc1_clk Pulse duration, mmc1_clk high Pulse duration, mmc1_clk low Jitter standard deviation (1), mmc1_clk Rising time, mmc1_clk Falling time, mmc1_clk Delay time, mmc1_clk falling clock edge to mmc1_cmd transition Rising time, mmc1_cmd Falling time, mmc1_cmd Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition Rising time, mmc1_dat[3:0] Falling time, mmc1_dat[3:0] MIN TBD TBD TBD –14.1 –14.1 MAX 24 TBD TBD TBD 10.1 TBD TBD 10.1 TBD TBD UNIT MHz ns ns ns ns ns ns ns ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 297 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com (1) This number is a typical value SDR122 SDR121 SDR120 mmc1_clk SDR126 SDR125 mmc1_cmd SDR128 SDR127 mmc1_dat[3:0] MMC1_05 Figure 5-57. MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode ADVANCE INFORMATION mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR122 SDR121 SDR120 SDR123 SDR124 Figure 5-58. MMC/SD/SDIO in - High Speed SDR12 - Transmiter Mode MMC1_06 5.22.1.4 SDR25 at 48 MHz, 4-bit data, half-cycle, 1.8 V Table 5-71 and Table 5-72 Presents Timing requirements and Switching characteristics for MMC1 SDR25 in receiver and transmiter mode.(see Figure 5-59 and Figure 5-60) Table 5-71. Timing Requirements for MMC1 - SD Card SDR25 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR253 tsu(dV-clkH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 4.6 ns SDR254 th(clkH-dV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 2.1 ns SDR257 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 4.6 ns SDR258 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge 2.1 ns Table 5-72. Switching Characteristics for MMC1 - SD Card SDR25 Mode NO. PARAMETER SDR251 SDR252H SDR252L fop(clk) tw(clkH) tw(clkL) tj(clk) tR(clk) tF(clk) DESCRIPTION Operating frequency, mmc1_clk Pulse duration, mmc1_clk high Pulse duration, mmc1_clk low Jitter standard deviation, mmc1_clk Rising time (1), mmc1_clk Falling time, mmc1_clk MIN TBD TBD TBD MAX 48 TBD TBD TBD UNIT MHz ns ns ns ns ns 298 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-72. Switching Characteristics for MMC1 - SD Card SDR25 Mode (continued) NO. PARAMETER SDR255 td(clkL-doV) tR(do) tF(do) SDR256 td(clkL-doV) tR(do) tF(do) (1) This number is a typical value DESCRIPTION Delay time, mmc1_clk falling clock edge to mmc1_cmd transition Rising time, mmc1_cmd Falling time, mmc1_cmd Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition Rising time, mmc1_dat[3:0] Falling time, mmc1_dat[3:0] MIN –6.1 –6.1 MAX 2 TBD TBD 2 TBD TBD UNIT ns ns ns ns ns ns mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR251 SDR252L SDR253 SDR257 SDR252H SDR254 SDR258 Figure 5-59. MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode MMC1_07 mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR251 SDR252H SDR252L HSSDR255 SDR256 SDR255 SDR256 Figure 5-60. MMC/SD/SDIO in - High Speed SDR25 - Transmiter Mode MMC1_08 5.22.1.5 UHS-I SDR50 at 96 MHz, 4-bit data, half-cycle, 1.8 V Table 5-73 and Table 5-74 Presents Timing requirements and Switching characteristics for MMC1 SDR50 in receiver and transmiter mode.(see Figure 5-61 and Figure 5-62) Table 5-73. Timing Requirements for MMC1 - SD Card SDR50 Mode NO. SDR503 SDR504 SDR507 PARAMETER tsu(dV-clkH) th(clkH-dV) tsu(dV-clkH) SDR508 th(clkH-dV) DESCRIPTION MIN Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 0.9 Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 1.3 Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock 0.9 edge Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge 1.3 MAX UNIT ns ns ns ns Table 5-74. Switching Characteristics for MMC1 - SD Card SDR50 Mode NO. SDR501 SDR502H PARAMETER fop(clk) tw(clkH) DESCRIPTION Operating frequency, mmc1_clk Pulse duration, mmc1_clk high MIN TBD MAX 96 UNIT MHz ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 299 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-74. Switching Characteristics for MMC1 - SD Card SDR50 Mode (continued) NO. SDR502L SDR505 SDR506 PARAMETER tw(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) tR(do) tF(do) td(clkL-doV) tR(do) tF(do) (1) This number is a typical value DESCRIPTION Pulse duration, mmc1_clk low Jitter standard deviation (1), mmc1_clk Rising time, mmc1_clk Falling time, mmc1_clk Delay time, mmc1_clk falling clock edge to mmc1_cmd transition Rising time, mmc1_cmd Falling time, mmc1_cmd Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition Rising time, mmc1_dat[3:0] Falling time, mmc1_dat[3:0] MIN TBD TBD –2.9 –2.9 MAX TBD TBD TBD 0.87 TBD TBD 0.6 TBD TBD UNIT ns ps ps ps ns ps ps ns ps ps mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR501 SDR502L SDR503 SDR507 SDR502H SDR504 SDR508 Figure 5-61. MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode MMC1_09 ADVANCE INFORMATION mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR501 SDR502H SDR502L SDR505 SDR506 SDR505 SDR506 Figure 5-62. MMC/SD/SDIO in - High Speed SDR50 - Transmiter Mode MMC1_10 5.22.1.6 UHS-I SDR104 at 192 MHz, 4-bit data, half-cycle, 1.8 V Table 5-75 Presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver and transmiter mode.(see Figure 5-63 and Figure 5-64) Table 5-75. Switching Characteristics for MMC1 - SD Card SDR104 Mode NO. SDR1041 SDR1042H SDR1042L PARAMETER fop(clk) tw(clkH) tw(clkL) tj(clk) tR(clk) tF(clk) DESCRIPTION Operating frequency, mmc1_clk Pulse duration, mmc1_clk high Pulse duration, mmc1_clk low Jitter standard deviation (1), mmc1_clk Rising time, mmc1_clk Falling time, mmc1_clk MIN TBD TBD TBD MAX 192 TBD TBD TBD UNIT MHz ns ns ps ps ps 300 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-75. Switching Characteristics for MMC1 - SD Card SDR104 Mode (continued) NO. SDR1045 PARAMETER td(clkL-doV) SDR1046 tR(do) tF(do) td(clkL-doV) tR(do) tF(do) (1) This number is a typical value DESCRIPTION Delay time, mmc1_clk falling clock edge to mmc1_cmd transition Rising time, mmc1_cmd Falling time, mmc1_cmd Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition Rising time, mmc1_dat[3:0] Falling time, mmc1_dat[3:0] MIN MAX –1 –0.1 TBD TBD –1 –0.1 TBD TBD UNIT ns ps ps ns ps ps mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR1041 SDR1042L SDR1043 SDR1047 SDR1042H SDR1044 SDR1048 Figure 5-63. MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode MMC1_11 mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR1041 SDR1042H SDR1042L SDR1045 SDR1046 SDR1045 SDR1046 Figure 5-64. MMC/SD/SDIO in - High Speed SDR104 - Transmiter Mode MMC1_12 5.22.1.7 UHS-I DDR50 at 48 MHz, 4-bit data, 1.8 V Table 5-76 and Table 5-77 Presents Timing requirements and Switching characteristics for MMC1 DDR50 in receiver and transmiter mode.(see Figure 5-65 and Figure 5-66) Table 5-76. Timing Requirements for MMC1 - SD Card DDR50 Mode NO. DDR505 DDR506 DDR507 DDR508 PARAMETER tsu(dV-clkH) th(clkH-dV) tsu(dV-clkH) th(clkH-dV) DESCRIPTION Setup time, mmc1_cmd valid before mmc1_clk transition Hold time, mmc1_cmd valid after mmc1_clk transition Setup time, mmc1_dat[3:0] valid before mmc1_clk transition Hold time, mmc1_dat[3:0] valid after mmc1_clk transition MIN MAX UNIT 5 ns 1 ns 1.15 ns 1.25 ns Table 5-77. Switching Characteristics for MMC1 - SD Card DDR50 Mode NO. PARAMETER DDR500 fop(clk) DESCRIPTION Operating frequency, mmc1_clk MIN MAX UNIT 48 MHz Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 301 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-77. Switching Characteristics for MMC1 - SD Card DDR50 Mode (continued) NO. PARAMETER DDR501 tw(clkH) DDR502 tw(clkL) tj(clk) tR(clk) tF(clk) DDR503 td(clkL-doV) tR(do) tF(do) DDR504 td(clkL-doV) tR(do) tF(do) (1) This number is a typical value DESCRIPTION Pulse duration, mmc1_clk high Pulse duration, mmc1_clk low Jitter standard deviation, (1) mmc1_clk Rising time, mmc1_clk Falling time, mmc1_clk Delay time, mmc1_clk transition to mmc1_cmd transition Rising time, mmc1_cmd Falling time, mmc1_cmd Delay time, mmc1_clk transition to mmc1_dat[3:0] transition Rising time, mmc1_dat[3:0] Falling time, mmc1_dat[3:0] MIN TBD TBD 1.1 1.1 MAX TBD TBD TBD 14.1 TBD TBD 6.3 TBD TBD UNIT ns ns ps ps ps ns ps ps ns ps ps mmc1_clk mmc1_cmd mmc1_dat[3:0] DDR501 DDR507 DDR508 DDR500 DDR502 DDR505 DDR507 DDR508 DDR506 MMC1_13 Figure 5-65. SDMMC - High Speed SD - DDR - Data/Command Receive ADVANCE INFORMATION mmc1_clk mmc1_cmd mmc1_dat[3:0] DDR501 DDR500 DDR502 DDR503(max) DDR504(max) DDR504(min) DDR504(max) DDR504(min) Figure 5-66. SDMMC - High Speed SD - DDR - Data/Command Transmit DDR503(min) MMC1_14 NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 2-3 and described in Device TRM, Chapter 18 - Control Module. The IO timings in data manual for MMC-HS mode @48MHz are guarantee if MMC1_VIRTUAL1 virtual mode is configured. The IO timings in data manual for MMC-SDR50 mode @96MHz are guarantee if MMC1_VIRTUAL2 virtual mode is configured. 302 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 The IO timings in data manual for MMC-DDR50 @48MHz are guarantee if MMC1_VIRTUAL3 virtual mode is configured. The IO timings in data manual for MMC SDR-104 @192MHz are guarantee if MMC1_VIRTUAL4 virtual mode is configured. Table 5-78 present the values for DELAYMODE bitfield. Table 5-78. Virtual Functions Mapping for MMC1 BALL NUMBER W6 Y6 AA6 Y4 AA5 Y3 BALL NAME Delay Mode Value mmc1_clk mmc1_cmd mmc1_dat0 mmc1_dat1 mmc1_dat2 mmc1_dat3 MMC1_VIRTUAL1 15 15 15 15 15 15 MMC1_VIRTUAL1 14 14 14 14 14 14 MMC1_VIRTUAL1 13 13 13 13 13 13 MMC1_VIRTUAL1 12 12 12 12 12 12 MUXMODE[15:0] 0 mmc1_clk mmc1_cmd mmc1_dat0 mmc1_dat1 mmc1_dat2 mmc1_dat3 5.22.2 MMC2 — eMMC MMC2 interface is compliant with the JC64 eMMC Standard v4.5 and it supports the following eMMC applications: • Standard JC64 SDR at 24 MHz, 8-bit data, half cycle, 1.8 V • High-speed JC64 SDR at 48 MHz, 8-bit data, half cycle, 3.3 V • High-speed JC64 DDR at 48 MHz, 8-bit data, 1.8 V • High-speed HS200 JC64 SDR at 192 MHz, 8-bit data, half cycle, 1.8 V NOTE For more information, see the eMMC/SD/SDIO chapter of the Device TRM. 5.22.2.1 Standard JC64 SDR at 24 MHz, 8-bit data, half cycle, 1.8 V Table 5-79 and Table 5-80 Presents Timing requirements and Switching characteristics for MMC2 Standart SDR in receiver and transmiter mode.(see Figure 5-67 and Figure 5-68) Table 5-79. Timing Requirements for MMC2 - JC64 Standard SDR Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SSDR5 tsu(dV-clkH) Setup time, emmc_cmd valid before emmc_clk rising edge 2.9 ns SSDR6 th(clkH-dV) Hold time, emmc_cmd valid after emmc_clk rising edge 1.7 ns SSDR7 tsu(dV-clkH) Setup time, emmc_data[7:0] valid before emmc_clk rising 2.9 ns edge SSDR8 th(clkH-dV) Hold time, emmc_data[7:0] valid after emmc_clk rising edge 1.7 ns Table 5-80. Switching Characteristics for MMC2 - JC64 Standard SDR Mode NO. SSDR1 SSDR2H SSDR2L PARAMETER fop(clk) tW(clkH) tW(clkL) tj(clk) tR(clk) DESCRIPTION Operating frequency, mmc2_clk Pulse duration, mmc2_clk high Pulse duration, mmc2_clk low Jitter standard deviation (1), mmc2_clk Rising time, mmc2_clk MIN TBD TBD TBD MAX 24 TBD TBD UNIT MHz ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 303 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-80. Switching Characteristics for MMC2 - JC64 Standard SDR Mode (continued) NO. SSDR3 PARAMETER tF(clk) td(clkL-doV) SSDR4 tR(do) tF(do) td(clkL-doV) tR(do) tF(do) (1) This number is a typical value DESCRIPTION Falling time, mmc2_clk Delay time, mmc2_clk falling clock edge to mmc2_cmd transition Rising time, mmc2_cmd Falling time, mmc2_cmd Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition Rising time, mmc2_dat[7:0] Falling time, mmc2_dat[7:0] MIN –14.4 –14.4 MAX TBD 14.4 TBD TBD 14.4 TBD TBD UNIT ns ns ns ns ns ns ns SSDR2 mmc2_clk SSDR5 mmc2_cmd SSDR7 mmc2_dat[7:0] SSDR2 SSDR1 SSDR6 SSDR8 Figure 5-67. MMC/SD/SDIO in - Standard JC64 - Receiver Mode MMC2_01 ADVANCE INFORMATION SSDR2 mmc2_clk mmc2_cmd mmc2_dat[7:0] SSDR2 SSDR1 SSDR3 SSDR4 Figure 5-68. MMC/SD/SDIO in - Standard JC64 - Transmiter Mode MMC2_02 5.22.2.2 High-speed JC64 SDR at 48 MHz, 8-bit data, half cycle, 3.3 V Table 5-81 and Table 5-82 Presents Timing requirements and Switching characteristics for MMC2 - High speed SDR in receiver and transmiter mode.(see Figure 5-69 and Figure 5-70) Table 5-81. Timing Requirements for MMC2 - JC64 High Speed SDR Mode NO. PARAMETER DESCRIPTION MIN JC643 tsu(dV-clkH) Setup time, mmc2_cmd valid before mmc2_clk rising clock 5.8 edge JC644 th(clkH-dV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 1.9 MAX UNIT ns ns 304 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 NO. JC647 JC648 Table 5-81. Timing Requirements for MMC2 - JC64 High Speed SDR Mode (continued) PARAMETER tsu(dV-clkH) th(clkH-dV) DESCRIPTION MIN Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock 5.8 edge Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock 1.9 edge MAX UNIT ns ns Table 5-82. Switching Characteristics for MMC2 - JC64 High Speed SDR Mode NO. JC641 JC642H JC642L JC645 PARAMETER fop(clk) tW(clkH) tW(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) JC646 tR(do) tF(do) td(clkL-doV) tR(do) tF(do) (1) This number is a typical value DESCRIPTION Operating frequency, mmc2_clk Pulse duration, mmc2_clk high Pulse duration, mmc2_clk low Jitter standard deviation (1), mmc2_clk Rising time, mmc2_clk Falling time, mmc2_clk Delay time, mmc2_clk falling clock edge to mmc2_cmd transition Rising time, mmc2_cmd Falling time, mmc2_cmd Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition Rising time, mmc2_dat[7:0] Falling time, mmc2_dat[7:0] MIN TBD TBD TBD –6.6 –6.6 MAX 48 TBD TBD TBD 6.6 TBD TBD 6.6 TBD TBD UNIT MHz ns ns ps ps ps ns ps ps ns ps ps mmc2_clk mmc2_cmd mmc2_dat[3:0] JC641 JC642L JC643 JC647 JC642H JC644 JC648 Figure 5-69. MMC/SD/SDIO in - High Speed JC64 - Receiver Mode MMC2_03 mmc2_clk mmc2_cmd mmc2_dat[3:0] JC645 JC646 JC641 JC642L JC642H JC645 JC646 Figure 5-70. MMC/SD/SDIO in - High Speed JC64 - Transmiter Mode MMC2_04 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 305 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 5.22.2.3 High-speed HS200 JC64 SDR at 192 MHz, 8-bit data, half cycle, 1.8 V Table 5-83 Present Timing requirements and Switching characteristics for MMC2 - HS200 in receiver and transmiter mode.(see Figure 5-71 and Figure 5-72) Table 5-83. Switching Characteristics for MMC2 - JEDS84 HS200 Mode NO. HS2001 HS2002H HS2002L HS2005 PARAMETER fop(clk) tW(clkH) tW(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) HS2006 tR(do) tF(do) td(clkL-doV) tR(do) tF(do) (1) This number is a typical value DESCRIPTION Operating frequency, mmc2_clk Pulse duration, mmc2_clk high Pulse duration, mmc2_clk low Jitter standard deviation (1), mmc2_clk Rising time, mmc2_clk Falling time, mmc2_clk Delay time, mmc2_clk falling clock edge to mmc2_cmd transition Rising time, mmc2_cmd Falling time, mmc2_cmd Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition Rising time, mmc2_dat[7:0] Falling time, mmc2_dat[7:0] MIN TBD TBD TBD –1.2 –1.2 MAX 192 TBD TBD TBD 0.4 TBD TBD 0.4 TBD TBD UNIT MHz ns ns ps ps ps ns ps ps ns ps ps mmc2_clk mmc2_cmd mmc2_dat[3:0] HS2001 HS2002L HS2005 HS2006 HS2002H HS2005 HS2006 Figure 5-71. eMMC in - HS200 SDR - Transmiter Mode MMC2_05 ADVANCE INFORMATION mmc2_clk mmc2_cmd mmc2_dat[3:0] HS2001 HS2002L HS2003 HS2007 HS2002H HS2004 HS2008 Figure 5-72. eMMC in - HS200 - Receiver Mode MMC2_06 5.22.2.4 High-speed JC64 DDR at 48 MHz, 8-bit data, 1.8 V Table 5-84 and Table 5-85 Presents Timing requirements and Switching characteristics for MMC2 - High speed DDR in receiver and transmiter mode.(see Figure 5-73 and Figure 5-74) 306 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-84. Timing Requirements for MMC2 - JC64 High Speed DDR Mode NO. PARAMETER DESCRIPTION MIN DDR3 tsu(dV-clkH) Setup time, mmc2_cmd valid before mmc2_clk rising clock 5.9 edge DDR4 DDR7 th(clkH-dV) tsu(dV-clkH) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 1.9 Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock 2.3 edge DDR8 th(clkH-dV) Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock 0.4 edge MAX UNIT ns ns ns ns Table 5-85. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode NO. DDR1 DDR2H DDR2L DDR5 PARAMETER fop(clk) tW(clkH) tW(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) DDR6 tR(do) tF(do) td(clkL-doV) tR(do) tF(do) (1) This number is a typical value DESCRIPTION Operating frequency, mmc2_clk Pulse duration, mmc2_clk high Pulse duration, mmc2_clk low Jitter standard deviation (1), mmc2_clk Rising time, mmc2_clk Falling time, mmc2_clk Delay time, mmc2_clk falling clock edge to mmc2_cmd transition Rising time, mmc2_cmd Falling time, mmc2_cmd Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition Rising time, mmc2_dat[7:0] Falling time, mmc2_dat[7:0] MIN TBD TBD 3.5 3.0 MAX 48 TBD TBD TBD 16.9 TBD TBD 7.1 TBD TBD UNIT MHz ns ns ps ps ps ns ps ps ns ps ps mmc2_clk mmc2_cmd mmc2_dat[3:0] DDR1 DDR2L DDR3 DDR2H DDR4 DDR8 DDR7 DDR8 DDR7 DDR8 DDR7 DDR7 Figure 5-73. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode MMC2_07 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 307 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com mmc2_clk mmc2_cmd mmc2_dat[3:0] DDR1 DDR5 DDR5 DDR2 DDR2 DDR5 DDR5 DDR6 DDR6 DDR6 DDReMMC6 DDReMMC6 DDR6 Figure 5-74. MMC/SD/SDIO in - High Speed DDR JC64 - Transmiter Mode MMC2_08 5.22.3 MMC3 and MMC4—SDIO/SD, 1.8 V MMC3 and MMC4 interfaces are compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic SDIO devices, it supports the following applications: • SDIO Standard speed at 24 MHz (SDR12 mode of the SD Standard v3.01), 4-bit data, SDR, half cycle, 1.8 V • SDIO High speed at 48 MHz (SDR25 mode of the SD Standard v3.01), 4-bit data, SDR, half cycle, 1.8 V NOTE The eMMC/SD/SDIOj (j = 3 to 4) controller is also referred to as MMCj. ADVANCE INFORMATION NOTE For more information, see the MMC/SDIO chapter of the Device TRM. 5.22.3.1 MMC3 and MMC4, SDIO Standard Speed SDR12 Mode, 24 MHz, Half Cycle, 1.8 V Table 5-86 and Table 5-87 Presents Timing requirements and Switching characteristics for MMC3 and MMC4 - SDIO Standard SDR12 in receiver and transmiter mode.(see Figure 5-75 and Figure 5-76) Table 5-86. Timing Requirements for MMCj - SDIO Standard SDR12 Mode NO. PARAMETER SDR125 tsu(dV-clkH) SDR126 SDR127 th(clkH-dV) tsu(dV-clkH) SDR128 th(clkH-dV) (1) j in mmcj = 3 or 4 (2) i in [i:0] = 3 DESCRIPTION MIN Setup time, mmcj_cmd valid before mmcj_clk rising clock 2.5 edge Hold time, mmcj_cmd valid after mmcj_clk rising clock edge 16 Setup time, mmcj_dat[i:0] valid before mmcj_clk rising clock 2.5 edge Hold time, mmcj_dat[i:0] valid after mmcj_clk rising clock edge 16 MAX UNIT ns ns ns ns Table 5-87. Switching Characteristics for MMCj - SDIO Standard SDR12 Mode NO. PARAMETER SDR120 fop(clk) DESCRIPTION Operating frequency, mmcj_clk MIN MAX UNIT 24 MHz 308 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-87. Switching Characteristics for MMCj - SDIO Standard SDR12 Mode (continued) NO. SDR121 SDR122 SDR123 PARAMETER tW(clkH) tW(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) SDR124 tR(do) tF(do) td(clkL-doV) tR(do) tF(do) (1) This number is a typical value (2) j in mmcj = 3 or 4 (3) i in [i:0] = 3 DESCRIPTION Pulse duration,, mmcj_clk high Pulse duration,, mmcj_clk low Jitter standard deviation, mmcj_clk (1) Rising time, mmcj_clk Falling time, mmcj_clk Delay time, mmcj_clk falling clock edge to mmcj_cmd transition Rising time, mmcj_cmd Falling time, mmcj_cmd Delay time, mmcj_clk falling clock edge to mmcj_dat[i:0] transition Rising time, mmcj_dat[i:0] Falling time, mmcj_dat[i:0] MIN TBD TBD TBD –13.9 –13.9 MAX TBD TBD TBD 9.9 TBD TBD 9.9 TBD TBD UNIT ns ns ns ns ns ns ns ns ns ns ns SDR122 SDR121 SDR120 mmcj_clk mmcj_cmd mmcj_dat[3:0] SDR126 SDR125 SDR128 SDR127 MMC3/4_01 Figure 5-75. MMC/SD/SDIOj in - High Speed SDR12 - Receiver Mode SDR122 SDR121 SDR120 mmcj_clk SDR123 mmcj_cmd SDR124 mmcj_dat[3:0] MMC3/4_02 Figure 5-76. MMC/SD/SDIOj in - High Speed SDR12 - Transmiter Mode 5.22.3.2 MMC3 and MMC4, SDIO High-Speed SDR25 Mode, 48 MHz, Half Cycle, 1.8 V Table 5-88 and Table 5-89 Presents Timing requirements and Switching characteristics for MMC3 and MMC4 - SDIO High speed SDR25 in receiver and transmiter mode.(see Figure 5-77 and Figure 5-78) Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 309 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-88. Timing Requirements for MMCj - SDIO High Speed SDR25 Mode www.ti.com NO. PARAMETER SDR253 tsu(dV-clkH) SDR254 SDR257 th(clkH-dV) tsu(dV-clkH) SDR258 th(clkH-dV) (1) j in mmcj = 3 or 4 (2) i in [i:0] = 3 DESCRIPTION MIN Setup time, mmcj_cmd valid before mmcj_clk rising clock 4.9 edge Hold time, mmcj_cmd valid after mmcj_clk rising clock edge 2 Setup time, mmcj_dat[i:0] valid before mmcj_clk rising clock 4.9 edge Hold time, mmcj_dat[i:0] valid after mmcj_clk rising clock edge 2 MAX Table 5-89. Switching Characteristics for MMCj - SDIO High Speed SDR25 Mode UNIT ns ns ns ns NO. PARAMETER SDR251 SDR252H SDR252L SDR255 fop(clk) tW(clkH) tW(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) SDR256 tR(do) tF(do) td(clkL-doV) tR(do) tF(do) (1) This number is a typical value (2) j in mmcj = 3 or 4 (3) i in [i:0] = 3 DESCRIPTION Operating frequency, mmcj_clk Pulse duration,, mmcj_clk high Pulse duration,, mmcj_clk low Jitter standard deviation, mmcj_clk (1) Rising time, mmcj_clk Falling time, mmcj_clk Delay time, mmcj_clk falling clock edge to mmcj_cmd transition Rising time, mmcj_cmd Falling time, mmcj_cmd Delay time, mmcj_clk falling clock edge to mmcj_dat[i:0] transition Rising time, mmcj_dat[i:0] Falling time, mmcj_dat[i:0] MIN TBD TBD TBD –5.3 –5.3 MAX 48 TBD TBD TBD 1.3 TBD TBD 1.3 TBD TBD UNIT MHz ns ns ns ns ns ns ns ns ns ns ns SDR251 SDR252L SDR252H mmcj_clk SDR253 SDR254 mmcj_cmd SDR257 SDR258 mmcj_dat[3:0] MMC3/4_03 Figure 5-77. MMC/SD/SDIOj in - High Speed SDR25 - Receiver Mode 310 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 mmcxj_clk mmcj_cmd mmcj_dat[3:0] SDR251 SDR252H SDR252L SDR255 SDR255 SDR256 SDR256 MMC3/4_04 Figure 5-78. MMC/SD/SDIOj in - High Speed SDR25 - Transmiter Mode 5.22.3.3 MMC3 SDIO High-Speed UHS-I SDR50 Mode, 96 MHz, Half Cycle, 1.8 V Table 5-90 and Table 5-91 Presents Timing requirements and Switching characteristics for MMC3 and MMC4 - SDIO High speed SDR50 in receiver and transmiter mode.(see Figure 5-79 and Figure 5-80) Table 5-90. Timing Requirements for MMCj - SDIO High Speed SDR50 Mode NO. PARAMETER SDR503 tsu(dV-clkH) SDR504 th(clkH-dV) SDR507 tsu(dV-clkH) SDR508 th(clkH-dV) (1) j in mmcj = 3 (2) i in [i:0] = 3 DESCRIPTION MIN Setup time, mmcj_cmd valid before mmcj_clk rising clock edge 1.5 Hold time, mmcj_cmd valid after mmcj_clk rising clock edge 1.1 Setup time, mmcj_dat[i:0] valid before mmcj_clk rising clock edge 1.5 Hold time, mmcj_dat[i:0] valid after mmcj_clk rising clock edge 1.1 MAX UNIT ns ns ns ns Table 5-91. Switching Characteristics for MMCj - SDIO High Speed SDR50 Mode NO. SDR501 SDR502H SDR502L SDR505 SDR506 PARAMETER fop(clk) tW(clkH) tW(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) tR(do) tF(do) td(clkL-doV) tR(do) tF(do) DESCRIPTION Operating frequency, mmcj_clk Pulse duration,, mmcj_clk high Pulse duration,, mmcj_clk low Jitter standard deviation, mmcj_clk (2) Rising time, mmcj_clk Falling time, mmcj_clk Delay time, mmcj_clk falling clock edge to mmcj_cmd transition Rising time, mmcj_cmd Falling time, mmcj_cmd Delay time, mmcj_clk falling clock edge to mmcj_dat[i:0] transition Rising time, mmcj_dat[i:0] Falling time, mmcj_dat[i:0] MIN TBD TBD TBD –3.0 –3.0 MAX 96 TBD TBD TBD 0.8 TBD TBD 0.8 TBD TBD UNIT MHz ns ns ns ns ns ns ns ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 311 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com (1) P = output mmcj_clk period in ns (2) This number is a typical value (3) j in mmcj = 3 (4) i in [i:0] = 3 SDR501 SDR502L SDR502H mmcj_clk mmcj_cmd SDR503 SDR507 SDR504 SDR508 mmcj_dat[3:0] MMC3/4_05 Figure 5-79. MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode ADVANCE INFORMATION mmcj_clk mmcj_cmd mmcj_dat[3:0] SDR501 SDR502H SDR502L SDR505 SDR505 SDR506 SDR506 MMC3/4_06 Figure 5-80. MMC/SD/SDIOj in - High Speed SDR50 - Transmiter Mode 5.22.3.4 MMC3 and MMC4, SD Default Speed, 1.8 V Table 5-86 and Table 5-87 Presents Timing requirements and Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmiter mode.(see Figure 5-81 and Figure 5-82) Table 5-92. Timing Requirements for MMCj - SD Card Default Speed Mode NO. PARAMETER DESCRIPTION MIN DS5 tsu(dV-clkH) Setup time, mmcj_cmd valid before mmcj_clk rising clock 2.5 edge DS6 DS7 th(clkH-dV) tsu(dV-clkH) Hold time, mmcj_cmd valid after mmcj_clk rising clock edge 16 Setup time, mmcj_dat[i:0] valid before mmcj_clk rising clock 2.5 edge DS8 th(clkH-dV) Hold time, mmcj_dat[i:0] valid after mmcj_clk rising clock edge 16 (1) j in mmcj = 3 or 4 (2) i in [i:0] = 7 for MMC3 and i in [i:0] = 3 for MMC4 MAX UNIT ns ns ns ns Table 5-93. Switching Characteristics for MMCj - SD Card Default Speed Mode NO. DS0 DS1 DS2 PARAMETER fop(clk) tW(clkH) tW(clkL) tj(clk) tR(clk) DESCRIPTION Operating frequency, mmcj_clk Pulse duration,, mmcj_clk high Pulse duration,, mmcj_clk low Jitter standard deviation, mmcj_clk (1) Rising time, mmcj_clk MIN TBD TBD TBD MAX 24 TBD TBD UNIT MHz ns ns ns ns 312 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-93. Switching Characteristics for MMCj - SD Card Default Speed Mode (continued) NO. PARAMETER DESCRIPTION DS3 tF(clk) td(clkL-doV) Falling time, mmcj_clk Delay time, mmcj_clk falling clock edge to mmcj_cmd transition DS4 tR(do) tF(do) td(clkL-doV) Rising time, mmcj_cmd Falling time, mmcj_cmd Delay time, mmcj_clk falling clock edge to mmcj_dat[i:0] transition tR(do) tF(do) Rising time, mmcj_dat[i:0] Falling time, mmcj_dat[i:0] (1) This number is a typical value (2) j in mmcj = 3 or 4 (3) i in [i:0] = 7 for MMC3 and i in [i:0] = 3 for MMC4 MIN –11.1 –11.1 MAX TBD 11.1 TBD TBD 11.1 TBD TBD UNIT ns ns ns ns ns ns ns DS2 DS1 DS0 mmcj_clk DS6 mmcj_cmd mmcj_dat[3:0] DS5 DS8 DS7 MMC3/4_07 Figure 5-81. MMC/SD/SDIOj in - Default Speed 3.3V Signaling - Receiver Mode DS2 DS1 DS0 mmcj_clk DS3 mmcj_cmd DS4 mmcj_dat[3:0] MMC3/4_08 Figure 5-82. MMC/SD/SDIOj in - Default Speed 3.3V Signaling - Transmiter Mode 5.22.3.5 MMC3 and MMC4, SD High Speed, 1.8 V Table 5-86 and Table 5-87 Presents Timing requirements and Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmiter mode.(see Figure 5-83 and Figure 5-84) Table 5-94. Timing Requirements for MMCj - SD Card High Speed Mode NO. HS3 PARAMETER tsu(dV-clkH) DESCRIPTION Setup time, mmcj_cmd valid before mmcj_clk rising clock edge MIN MAX UNIT 4.6 ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 313 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-94. Timing Requirements for MMCj - SD Card High Speed Mode (continued) NO. PARAMETER DESCRIPTION MIN HS4 HS7 th(clkH-dV) tsu(dV-clkH) Hold time, mmcj_cmd valid after mmcj_clk rising clock edge 2.1 Setup time, mmcj_dat[i:0] valid before mmcj_clk rising clock 4.6 edge HS8 th(clkH-dV) Hold time, mmcj_dat[i:0] valid after mmcj_clk rising clock edge 2.1 1. j in mmcj = 3 or 4 2. i in [i:0] = 7 for MMC3 and i in [i:0] = 3 for MMC4 MAX UNIT ns ns ns Table 5-95. Switching Characteristics for MMCj - SD Card High Speed Mode NO. PARAMETER DESCRIPTION HS1 HS2H HS2L HS5 fop(clk) tW(clkH) tW(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) Operating frequency, mmcj_clk Pulse duration, mmcj_clk high Pulse duration, mmcj_clk low Jitter standard deviation, mmcj_clk (1) Rising time, mmcj_clk Falling time, mmcj_clk Delay time, mmcj_clk falling clock edge to mmcj_cmd transition HS6 tR(do) tF(do) td(clkL-doV) Rising time, mmcj_cmd Falling time, mmcj_cmd Delay time, mmcj_clk falling clock edge to mmcj_dat[i:0] transition tR(do) tF(do) Rising time, mmcj_dat[i:0] Falling time, mmcj_dat[i:0] (1) This number is a typical value (2) j in mmcj = 3 or 4 (3) i in [i:0] = 7 for MMC3 and i in [i:0] = 3 for MMC4 MIN TBD TBD TBD –5.7 –5.7 MAX 48 TBD TBD TBD 1.3 TBD TBD 1.3 TBD TBD UNIT MHz ns ns ns ns ns ns ns ns ns ns ns HS1 HS2L HS2H mmcj_clk HS3 HS4 mmcj_cmd HS7 HS8 mmcj_dat[3:0] MMC3/4_09 Figure 5-83. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Receiver Mode 314 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 HS1 HS2H HS2L mmcj_clk HS5 HS5 mmcj_cmd HS6 HS6 mmcj_dat[3:0] MMC3/4_10 Figure 5-84. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Transmiter Mode 5.22.3.6 MMC3 and MMC4, SD SDR12 Mode, 1.8 V Table 5-86 and Table 5-87 Presents Timing requirements and Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmiter mode.(see Figure 5-85 and Figure 5-86) Table 5-96. Timing Requirements for MMCj - SD Card SDR12 Mode NO. PARAMETER DESCRIPTION SDR125 tsu(dV-clkH) Setup time, mmcj_cmd valid before mmcj_clk rising clock edge SDR126 SDR127 th(clkH-dV) tsu(dV-clkH) Hold time, mmcj_cmd valid after mmcj_clk rising clock edge Setup time, mmcj_dat[i:0] valid before mmcj_clk rising clock edge SDR128 th(clkH-dV) Hold time, mmcj_dat[i:0] valid after mmcj_clk rising clock edge (1) j in mmcj = 3 or 4 (2) i in [i:0] = 7 for MMC3 and i in [i:0] = 3 for MMC4 MIN 2.2 19.1 2.2 19.1 MAX UNIT ns ns ns ns Table 5-97. Switching Characteristics for MMCj - SD Card SDR12 Mode NO. PARAMETER SDR120 SDR121 SSDR122 SDR125 fop(clk) tW(clkH) tW(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) SDR126 tR(do) tF(do) td(clkL-doV) tR(do) tF(do) DESCRIPTION Operating frequency, mmcj_clk Pulse duration,, mmcj_clk high Pulse duration,, mmcj_clk low Jitter standard deviation, mmcj_clk (1) Rising time, mmcj_clk Falling time, mmcj_clk Delay time, mmcj_clk falling clock edge to mmcj_cmd transition Rising time, mmcj_cmd Falling time, mmcj_cmd Delay time, mmcj_clk falling clock edge to mmcj_dat[i:0] transition Rising time, mmcj_dat[i:0] Falling time, mmcj_dat[i:0] MIN TBD TBD -65 –14.1 –14.1 MAX 24 65 2750 2750 10.1 2750 2750 10.1 2750 2750 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 315 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com (1) This number is a typical value (2) j in mmcj = 3 or 4 (3) i in [i:0] = 7 for MMC3 and i in [i:0] = 3 for MMC4 SDR122 SDR121 SDR120 mmcj_clk SDR126 mmcj_cmd SDR125 SDR128 mmcj_dat[3:0] SDR127 MMC3/4_11 Figure 5-85. MMC/SD/SDIOj in - SDR12 3.3V Signaling - Receiver Mode ADVANCE INFORMATION SDR122 SDR121 SDR120 mmcj_clk SDR123 mmcj_cmd SDR124 mmcj_dat[3:0] MMC3/4_12 Figure 5-86. MMC/SD/SDIOj in - SDR12 3.3V Signaling - Transmiter Mode 5.22.3.7 MMC3 and MMC4, SD SDR25 Mode, 1.8 V Table 5-86 and Table 5-87 Presents Timing requirements and Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmiter mode.(see Figure 5-87 and Figure 5-88) Table 5-98. Timing Requirements for MMCj - SD Card SDR25 Mode NO. PARAMETER DESCRIPTION MIN SDR255 tsu(dV-clkH) Setup time, mmcj_cmd valid before mmcj_clk rising clock 4.6 edge SDR256 SDR257 th(clkH-dV) tsu(dV-clkH) Hold time, mmcj_cmd valid after mmcj_clk rising clock edge 2.1 Setup time, mmcj_dat[i:0] valid before mmcj_clk rising clock 4.6 edge SDR258 th(clkH-dV) Hold time, mmcj_dat[i:0] valid after mmcj_clk rising clock edge 2.1 (1) j in mmcj = 3 or 4 (2) i in [i:0] = 7 for MMC3 and i in [i:0] = 3 for MMC4 MAX UNIT ns ns ns ns Table 5-99. Switching Characteristics for MMCj - SD Card SDR25 Mode NO. PARAMETER SDR251 top(clk) SDR252H tW(clkH) DESCRIPTION Operating frequency, mmcj_clk Pulse duration, mmcj_clk high 316 Timing Requirements and Switching Characteristics Submit Documentation Feedback MIN TBD MAX 48 UNIT MHz ns Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-99. Switching Characteristics for MMCj - SD Card SDR25 Mode (continued) NO. PARAMETER DESCRIPTION SDR252L SDR255 tW(clkL) tj(clk) tR(clk) tF(clk) td(clkL-doV) Pulse duration, mmcj_clk low Jitter standard deviation, mmcj_clk (1) Rising time, mmcj_clk Falling time, mmcj_clk Delay time, mmcj_clk falling clock edge to mmcj_cmd transition SDR256 tR(do) tF(do) td(clkL-doV) Rising time, mmcj_cmd Falling time, mmcj_cmd Delay time, mmcj_clk falling clock edge to mmcj_dat[i:0] transition tR(do) tF(do) Rising time, mmcj_dat[i:0] Falling time, mmcj_dat[i:0] (1) This number is a typical value (2) j in mmcj = 3 or 4 (3) i in [i:0] = 7 for MMC3 and i in [i:0] = 3 for MMC4 MIN TBD TBD –6.1 –6.1 MAX TBD TBD TBD 2 TBD TBD 2 TBD TBD UNIT ns ns ns ns ns ns ns ns ns ns mmcj_clk mmcj_cmd mmcj_dat[3:0] SDR251 SDR252L SDR253 SDR257 SDR252H SDR254 SDR258 MMC3/4_13 Figure 5-87. MMC/SD/SDIOj in - SDR25 3.3V Signaling - Receiver Mode mmcj_clk SDR251 SDR252H SDR252L mmcj_cmd mmcj_dat[3:0] SDR255 SDR256 SDR255 SDR256 MMC3/4_14 Figure 5-88. .MMC/SD/SDIOj in - SDR25 3.3V Signaling - Transmiter Mode In cases of some pins for MMC4, the IO timings can only be guaranteed if the slew mode is reconfigured to fast mode. To configure fast slew mode the user must clear SLEWCONTROL bit for each corresponding pad control register. This can be configured at the same time pinmux is configured in the same pad control registers. Table 5-100 present the MMC4 pins that require reconfiguration of the slew mode. The pad control register are described in Device TRM, Chapter 18 - Control Module. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 317 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-100. MMC4 Slew mode reconfiguration BALL NUMBER E25 C27 D28 D26 D27 C28 BALL NAME uart1_ctsn uart1_rtsn uart2_rxd uart2_txd uart2_ctsn uart2_rtsn MUXMODE 3 mmc4_clk mmc4_cmd mmc4_dat0 mmc4_dat1 mmc4_dat2 mmc4_dat3 REGISTER NAME CTRL_CORE_PAD_UART1_CTSN CTRL_CORE_PAD_UART1_RTSN CTRL_CORE_PAD_UART2_RXD CTRL_CORE_PAD_UART2_TXD CTRL_CORE_PAD_UART2_CTSN CTRL_CORE_PAD_UART2_RTSN www.ti.com 5.23 General-Purpose Interface (GPIO) The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities; thus, the generalpurpose interface supports up to 256 (8 × 32) pins. These pins can be configured for the following applications: • Data input (capture)/output (drive) • Keyboard interface with a debounce cell • Interrupt generation in active mode upon the detection of external events. Detected events are processed by two parallel independent interrupt-generation submodules to support biprocessor operations • Wake-up request generation in idle mode upon the detection of external events NOTE For more information, see the General-Purpose Interface chapter of the Device TRM. ADVANCE INFORMATION NOTE The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi. 5.24 Keyboard controller (KBD) NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. NOTE For more information, see the Keyboard Controller chapter of the Device TRM. 5.25 Pulse Width Modulation (PWM) Interface NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. 318 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 NOTE For more information, see the Pulse-Width Modulation Subsystem chapter of the Device TRM. 5.26 Audio Tracking Logic (ATL) The device contains four ATL modules that can be used for asynchronous sample rate conversion of audio. The ATL calculates the error between two time bases, such as audio syncs, and optionally generates an averaged clock using cycle stealing via software. NOTE For more detailed information on the ATL peripheral, see the Audio Tracking Logic (ATL) chapter of the device-specific Technical Reference Manual. NOTE Audio Tracking Logic x (x= 1 to 4) module is also referred to as ATLx. 5.26.1 ATL Electrical Data/Timing Table 5-101 and Figure 5-89 Presents switching characteristics for ATL Table 5-101. Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx NO. PARAMETER DESCRIPTION 1 tc(ATLCLKOUT) 2 tw(ATLCLKOUTL) 3 tw(ATLCLKOUTH) Cycle time, ATL_CLKOUTx Pulse Duration, ATL_CLKOUTx low Pulse Duration, ATL_CLKOUTx high (1) P = ATL_CLKOUTx period. M = internal ATL PCLK period. MIN 20 0.45*P - M(1) 0.45*P - M(1) MAX UNIT ns ns ns 1 2 atl_clkx 3 ATL_01 Figure 5-89. ATL_CLKOUTx Timing 5.27 System and Miscellaneous interfaces The Device includes the following System and Miscellaneous interfaces: • Sysboot Interface • System DMA Interface • Interrupt Controlers (INTC) Interface • Observability Signal (OBS) Interface • Reset Electrical Data/Timing 5.27.1 Reset Electrical Data/Timing Table 5-102 lists the reset timings of the device. Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 319 Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 5-102. Timing Requirements for Reset PARAMETER DESCRIPTION MIN tw(resetn) tsu(sysboot) th(sysboot) tw(rtc_porz) Pulse duration, porz low or resetn low Setup time, sysboot[15:0] pins valid before porz high or resetn high Hold time, sysboot[15:0] pins valid after porz high or resetn high Pulse duration, rtc_porz low after vdda_rtc, vddshv5, and vdd_rtc stable 12P (1)(2) 2P (2) 15P (2) 1 (3) (1) The SYS_CLK1 source must be stable and at a valid frequency prior to meeting the tw(resetn) requirement. (2) P = 1/(SYS_CLK1/610) frequency in ns. (3) The SYS_32K source must be stable and at a valid frequency prior to meeting the tw(rtc_porz) requirement. 5.28 Test Interfaces The Device includes the following Test interfaces: • IEEE 1149.1 Standard-Test-Access Port (JTAG) • Compact JTAG Interface (cJTAG) • Trace Port Interface Unit (TPIU) • Advanced Event Triggering Interface (AET) MAX UNIT ns ns ns ms 5.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG) The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture) interface is used for BSDL testing and emulation of the device. The TRST pin only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. For maximum reliability, the device includes an internal Pull-down (IPD) on the TRST pin to ensure that TRST is always asserted upon power up and the device's internal emulation logic is always properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a Pull-up resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary-scan operations. The main JTAG features include: • 32KB embedded trace buffer (ETB) • 5-pin system trace interface for debug • Supports Advanced Event Triggering (AET) • All processors can be emulated via JTAG ports • All functions on EMU pins of the device: – EMU[1:0] - cross-triggering, boot mode (WIR), STM trace – EMU[4:2] - STM trace only (single direction) 5.28.1.1 JTAG Electrical Data/Timing Table 5-103, Table 5-104 and Figure 5-90 assumes testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-103. Timing Requirements for IEEE 1149.1 JTAG NO. 1 1a 1b 3 PARAMETER tc(TCK) tw(TCKH) tw(TCKL) tsu(TDI-TCK) tsu(TMS-TCK) DESCRIPTION Cycle time, TCK Pulse duration, TCK high (40% of tc) Pulse duration, TCK low (40% of tc) Input setup time, TDI valid to TCK high Input setup time, TMS valid to TCK high MIN 62.29 24.92 24.92 6.23 6.23 MAX UNIT ns ns ns ns ns 320 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 5-103. Timing Requirements for IEEE 1149.1 JTAG (continued) NO. 4 PARAMETER th(TCK-TDI) th(TCK-TMS) DESCRIPTION Input hold time, TDI valid from TCK high Input hold time, TMS valid from TCK high MIN 31.15 31.15 MAX UNIT ns ns Table 5-104. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG NO. 2 PARAMETER td(TCKL-TDOV) DESCRIPTION Delay time, TCK low to TDO valid MIN MAX UNIT 0 27.5 ns TCK 1 1a 1b 2 TDO 3 TDI/TMS 4 Figure 5-90. JTAG Timing JTAG_01 Table 5-105, Table 5-106 and Figure 5-91 assumes testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-105. Timing Requirements for IEEE 1149.1 JTAG With RTCK NO. 1 1a 1b 3 4 PARAMETER tc(TCK) tw(TCKH) tw(TCKL) tsu(TDI-TCK) tsu(TMS-TCK) th(TCK-TDI) th(TCK-TMS) DESCRIPTION Cycle time, TCK Pulse duration, TCK high (40% of tc) Pulse duration, TCK low (40% of tc) Input setup time, TDI valid to TCK high Input setup time, TMS valid to TCK high Input hold time, TDI valid from TCK high Input hold time, TMS valid from TCK high MIN 62.29 24.92 24.92 6.23 6.23 31.15 31.15 MAX UNIT ns ns ns ns ns ns ns Table 5-106. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK NO. PARAMETER 5 td(TCK-RTCK) 6 tc(RTCK) 7 tw(RTCKH) 8 tw(RTCKL) DESCRIPTION Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is the only tap selected--when the arm is in the scan chain the delay time is a function of the ARM functional clock). Cycle time, RTCK Pulse duration, RTCK high (40% of tc) Pulse duration, RTCK low (40% of tc) MIN 0 62.29 24.92 24.92 MAX 24 UNIT ns ns ns ns Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 321 Submit Documentation Feedback DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY ADVANCE INFORMATION TCK RTCK 5 6 7 8 Figure 5-91. JTAG With RTCK Timing JTAG_02 5.28.1.2 Compact JTAG Interface (cJTAG) The cJTAG module is a component which can run a 2-pin communication protocol on top of an IEEE 1149.1 JTAG Test Access Port (TAP). The cJTAG logic serializes the IEEE 1149.1 transactions, using a variety of compression formats, to reduce the number of pins needed to implement a JTAG debug and boundary scan port. Table 5-107, Table 5-108 and Figure 5-92 assumes testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-107. Timing Requirements for IEEE 1149.7 cJTAG NO. CJ1 CJ1a CJ1b CJ9a CJ10a C9b CJ10b PARAMETER tc(tck) tw(tckH) tw(tckL) tsu(TMSC-TCKre) tsu(TMSC-TCKfe) th(TCKre-TMSC) th(TCKfe-TMSC) DESCRIPTION Cycle time, TCK Pulse duration, TCK high (40% of tc) Pulse duration, TCK low(40% of tc) input setup time, TMSC valid to TCK high (RE timing selected) input setup time, TMSC valid to TCK low (FE timing selected) input hold time, TMSC valid from TCK high (RE timing selected) input hold time, TMSC valid from TCK low (FE timing selected) MIN 62.29 24.92 24.92 12.46 12.46 0 0 MAX UNIT ns ns ns ns ns ns ns Table 5-108. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.7 cJTAG NO. CJ11 CJ13 CJ12 CJ2 PARAMETER td(TCKL-TMSCV) td(TCKH-TMSCZ) td(TMSCV-KPRV) td(TCKL-TDOV) DESCRIPTION Delay time, input clock jtag_tck low to output mode select jtag_tms_tmsc valid Delay time, TCK high to TMSC HiZ Delay time, TMSC valid to Keeper Valid Delay time, TCK low to TDO valid MIN MAX UNIT 0 12.45 ns 0 18.68 ns 0 12.45 ns 0 29.14 ns jtag_tck jtag_tms_tmsc(IN) jtag_tms_tmsc(OUT) CJ1 CJ1b CJ1a CJ9a CJ9b CJ10a CJ2 CJ11 CJ10b CJ13 JTAG_03 Figure 5-92. cJTAG Interface Timing—Normal Mode 322 Timing Requirements and Switching Characteristics Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 5.28.2 Trace Port Interface Unit (TPIU) 5.28.2.1 TPIU PLL DDR Mode Table 5-109 and Figure 5-93 assumes testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-109. Switching Characteristics for TPIU NO. PARAMETER DESCRIPTION TPIU1 TPIU2 TPIU3 TPIU4 tc(clk) tw(clkH) tw(clkL) tj(clk) tR(clk) tF(clk) td(clk-ctlV) Cycle time, TRACECLK period Typical Pulse duration, TRACECLK high Typical Pulse duration, TRACECLK low Jitter standard deviation, TRACECLK Rising time, TRACECLK Falling time, TRACECLK Skew time, TRACECLK transition to TRACECTL transition TPIU5 td(clk-dataV) Skew time, TRACECLK transition to TRACEDATA[17:0] transition tr(ctl/data) Rising time, TRACECTL and TRACEDATA[17:0] tf(ctl/data) Falling time, TRACECTL and TRACEDATA[17:0] (1) P = TRACECLK period in ns (2) The listed pulse duration is a typical value MIN 5.56 0.5*P-0.278(1) 0.5*P-0.278(1) MAX TBD TBD TBD 0.96 0.96 TBD TBD UNIT ns ns ns ps ns ns ns ns ns ns TRACECLK TRACECTL TRACEDATA[X:0] TPIU4 TPIU1 TPIU2 TPIU3 TPIU5 TPIU5 Figure 5-93. TPIU—PLL DDR Transmit Mode(1) (1) In d[X:0], X is equal to 15 or 17. TPIU4 TPIU_01 Copyright © 2012–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 323 Submit Documentation Feedback EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 6 Thermal Management For reliability and operability concerns, the maximum junction temperature of the Device has to be at or below the TJ value identified in Table 3-2, Recommended Operating Conditions. Depending on the thermal mechanical design (Automotive Vision Applications, etc) and worst case thermal applications, the junction temperature might be exposed to higher values than those specified above. Therefore, it is recommended to perform thermal simulations at device level (Automotive Vision Applications, etc) with the power worst use case. 6.1 Package Thermal Characteristics NOTE TO USERS: NOTE The content of this section is UNDER DEVELOPMENT! For more information, see the corresponding chapter of the Device TRM. ADVANCE INFORMATION 324 Thermal Management Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com 7 Package Characteristics 7.1 Device Nomenclature 7.1.1 Standard Package Symbolization SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 EARLY PRELIMINARY ADVANCE INFORMATION PIN ONE INDICATOR JACINTOTM aBBBBBBrzYyPPPQ1 YMLLLL S 842 PPP G1 O Figure 7-1. Printed Device Reference SWPS857_PACK_01 7.1.2 SAP Part Number The actual part number used in the system follows this syntax : • SAP part number in Tray: aBBBBBBrFzYyPPPQ1 • SAP part number in Tape and Reel: aBBBBBBrFzYyPPPRQ1 7.1.3 Device Naming Convention Table 7-1. Nomenclature Description FIELD PARAMETER a BBBBBB r F FIELD DESCRIPTION Device evolution stage(1) Base production part number Device revision Fabrication flow code(2) VALUE X P BLANK DRA744 DRA745 DRA746 DRA754 DRA755 DRA756 BLANK A A B C DESCRIPTION Prototype Preproduction (production test flow, no reliability data) Production J6 Low Tier J6 Mid Tier J6 High Tier J6EX Low Tier J6EX Mid Tier J6EX High Tier ES 1.0 ES 2.0 It is for planning use only (not written on the package) It is for planning use only (not written on the package) It is for planning use only (not written on the package) Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Package Characteristics 325 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 7-1. Nomenclature Description (continued) FIELD PARAMETER FIELD DESCRIPTION VALUE DESCRIPTION z Device Speed P High speed grade L Overdrive speed grade J Nominal speed grade OTHER Alternate speed grade Yy Device type G General purpose (Prototype and Production) E Emulation (E) devices D High security prototype devices with TI Development keys (D) H High security (HS) production devices Yn Letter followed by number indicates legacy HS customer key PPP Package designator ABC ABC S-PBGA-N760 (23mm x 23mm) Package R Tape/Reel BLANK Tray R Tape/Reel Q1 Automotive Designator BLANK not meeting automotive qualification Q1 meeting Q100 equal requirements, with exceptions as specified in DM. YM Lot Trace Code (LTC): Y = Year, M = Month LLLL Lot Trace Code (LTC): Assembly lot number S Lot Trace Code (LTC): Assembly site code O Pin one designator G1 ECAT—Green package designator (1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices. Nonqualified / production devices are shipped against the following disclaimer: “This product is still in development and is intended for internal evaluation purposes.” Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of fitness for a specific purpose, of this device. (2) The fabrication flow code will include the silicon fabrication site and / or assembly site and / or test site. NOTE BLANK in the symbol or part number is collapsed so there are no gaps between characters. ADVANCE INFORMATION 326 Package Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com 7.2 Mechanical Data TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 EARLY PRELIMINARY ADVANCE INFORMATION Figure 7-2. Mechanical Package Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Package Characteristics 327 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 8 PCB Guidelines www.ti.com 8.1 Introduction This chapter is intended to communicate, guide and illustrate a PCB design strategy resulting in a PCB that can support TI’s latest Application Processor. This Processor is a high-performance processor designed for automotive Infotainment and Advanced Driver Assistance Systems based on enhanced OMAP™ architecture integrated on a 28-nm CMOS process technology. These guidelines first focus on designing a robust Power Delivery Network (PDN) which is essential to achieve the desirable high performance processing available on Device. The general principles and stepby-step approach for implementing good power integrity (PI) with specific requirements will be described for the key Device power domains. TI strongly believes that simulating a PCB’s proposed PDN is required for first pass PCB design success. Key Device processor high-current power domains need to be evaluated for Power Rail IR Drop, Decoupling Capacitor Loop-Inductance and Power Rail Target Impedance. Only then can a PCB’s PDN performance be truly accessed by comparing these model PI parameters vs. TI’s recommended values. Ultimately for any high-volume product, TI recommends conducting a “Processor PDN Validation” test on prototype PCBs across processor “split lots” to verify PDN robustness meets desired performance goals for each customer’s worst-case scenario. Please contact your TI representative to receive guidance on PDN PI modeling and validation testing. Likewise, the methodology and requirements needed to route Device high-speed, differential interfaces (i.e. USB2.0, USB3.0, HDMI, PCI, SATA), single-ended interfaces (i.e. DDR2/DDR3, QSPI) and general purpose interfaces using LVCMOS drivers that meet timing requirements while minimizing signal integrity (SI) distortions on the PCB’s signaling traces. Signal trace lengths and flight times are aligned with FR-4 standard specification for PCBs. Several different PCB layout stack-up examples have been presented to illustrate a typical number of layers, signal assignments and controlled impedance requirements. Different Device interface signals demand more or less complexity for routing and controlled impedance stack-ups. Optimizing the PCB’s PDN stack-up needs with all of these different types of signal interfaces will ultimately determine the final layer count and layer assignments in each customer’s PCB design. This guideline must be used as a supplement in complement to TI’s Application Processor, Power Management IC (PMIC) and Audio Companion components along with other TI component technical documentation (i.e. Technical Reference Manual, Data Manual, Data Sheets, Silicon Errata, Pin-Out Spreadsheet, Application Notes, etc.). NOTE Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of fitness for a specific purpose, for customer boards. The data described in this appendix are intended as guidelines only. ADVANCE INFORMATION NOTE These PCB guidelines are in a draft maturity and consequently, are subject to change depending on design verification testing conducted during IC development and validation. Note also that any references to Application Processor’s ballout or pin muxing are subject to change following the processor’s ballout maturity. 8.1.1 Initial Requirements and Guidelines Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to be between 35 Ω and 65 Ω to minimize the overshoot or undershoot on far-end loads. 328 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Characteristic impedance for differential interfaces must be routed as differential traces on the same layer. The trace width and spacing must be chosen to yield the recommended differential impedance. For more information see Section 8.5.1. The PDN must be optimized for low trace resistance and low trace inductance for all high-current power nets from PMIC to the device. An external interface using a connector must be protected following the IEC61000-4-2 level 4 system ESD. 8.2 Power Optimizations This section describes the necessary steps for designing a robust Power Distribution Network (PDN): • Section 8.2.1, Step 1: PCB Stack-up • Section 8.2.2, Step 2: Physical Placement • Section 8.2.3, Step 3: Static Analysis • Section 8.2.4, Step 4: Frequency Analysis 8.2.1 Step 1: PCB Stack-up The PCB stack-up (layer assignment) is an important factor in determining the optimal performance of the power distribution system. An optimized PCB stack-up for higher power integrity performance can be achieved by following these recommendations: • Power and ground plane pairs must be closely coupled together. The capacitance formed between the planes can decouple the power supply at high frequencies. Whenever possible, the power and ground planes must be solid to provide continuous return path for return current. • Use a thin dielectric between the power and ground plane pair. Capacitance is inversely proportional to the separation of the plane pair. Minimizing the separation distance (the dielectric thickness) maximizes the capacitance. • Optimize the power and ground plane pair carrying high current supplies to key component power domains as close as possible to the same surface where these components are placed (see Figure 81). This will help to minimize “loop inductance” encountered between supply decoupling capacitors and component supply inputs and between power and ground plane pairs. NOTE 1-2oz for planes per total thickness and layer count is preferred! NOTE PCB thermal spreading can help to reduce Processor junction temperatures and is more effective when using heavier Cu weights on the outer Gnd plane layers. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 329 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Trace Capacitor Via 3 DIE Package www.ti.com Power/Ground Ground/Power 1 2 Note: 1. BGA via pair loop inductance 2. Power/Ground net spreading inductance 3. Capacitor trace inductance Loop inductance SPRABP6-001 Figure 8-1. Minimize Loop Inductance With Proper Layer Assignment The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a significant impact on the parasitic inductances of power current path as shown in Figure 8-1. For this reason, it is recommended to consider layer order in the early stages of the PCB PDN design cycle, putting high-priority supplies in the top half of the stackup (assuming high load and priority components are mounted on the top-side of PCB) and low-priority supplies in the bottom half of the stackup as shown in the examples below (vias have parasitic inductances which impact the bottom layers more, so it is advised to put the sensitive and high-priority power supplies on the top/same layers). Two PCB stack-ups with layer assignments and via types that can enable an optimize PDN are shown in Figure 8-2 and Figure 8-3. TOP/SIGNAL1 GROUND POWER SIGNAL2 Figure 8-2. Layer PCB With High Density Interconnect (HDI) Vias SIGNAL3 POWER GROUND BOTTOM/SIGNAL4 SPRABP6-002 330 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 TOP/SIGNAL1 POWER GROUND SIGNAL2 SIGNAL3 Figure 8-3. Layer PCB With Plated Through Holes (PTH) Vias GROUND POWER BOTTOM/SIGNAL4 SPRABP6-003 8.2.2 Step 2: Physical Placement A critical step in designing an optimized PDN is that proper care must be taken to making sure that the initial floor planning of the PCB layout is done with good power integrity design guidelines in mind. The following points are important for optimizing a PCB’s PDN: • Minimizing the physical distance between power sources and key high load components is the first step toward optimization. Placing source and load components on the same side of the PCB is desirable. This will minimize via inductance impact for high current loads and steps • External trace routing between components must be as wide as possible. The wider the traces, the lower the DC resistance and consequently the lower the static IR drop. • Whenever possible for the internal layers (routing and plane), wide traces and copper area fills are preferred for PDN layout. The routing of power nets in plane provide for more interplane capacitance and improved high frequency performance of the PDN. • Whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling capacitors, power inductors and current sensing resistors). Do not share vias among multiple capacitors for connecting power supply and ground planes. • Placement of vias must be as close as possible or even within a component’s solder pad if the PCB technology you are using provides this capability. Figure 8-4 shows an example of acceptable width for power net routing but with poor via placement. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 331 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Figure 8-4. Poor Via Assignment for PDN SWPS040-211 Figure 8-5 shows an improved power net routing with better via assignment and placement, respectively. ADVANCE INFORMATION Figure 8-5. Improved Via Assignment for PDN SWPS040-212 • To avoid any “ampacity” issue – maximum current-carrying capacity of each transitional via should be evaluated to determine the appropriate number of vias required to connect components. Figure 8-6 and Figure 8-7 show examples of “via starvation” on a power net transitioning from top routing layer to internal layers and the improved layout, respectively. Adding vias to bring the “via-topad” ratio to 1:1 will improve PDN performance. 332 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 EARLY PRELIMINARY ADVANCE INFORMATION One via for 5 capacitor pads is NOT good practice Figure 8-6. Via Starvation SWPS040-213 Added vias SWPS040-214 Figure 8-7. Improved Layout With More Transitional Vias • For noise sensitive power supplies (i.e. Phase Lock-Loops, analog signals like audio and video), a Gnd shield can be used to isolate coplanar supplies that may have high step currents or high frequency switching transitions from coupling into low-noise supplies. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 333 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 vdd_mpu www.ti.com EARLY PRELIMINARY ADVANCE INFORMATION vss vdd PCB_PO_8 Figure 8-8. Coplanar Shielding of Power Net Using Ground Guard-band 8.2.3 Step 3: Static Analysis Delivering reliable power to circuits is always of critical importance because voltage drops (also known as IR drops) can happen at every level within an electronic system, on-chip, within a package, and across the board. Robust system performance can only be ensured by understanding how the system elements will perform under typical stressful Use Cases. Therefore, it is a good practice to perform a Static or DC Analysis. Static or DC analysis and design methodology results in a PDN design that minimizes voltage or IR drops across power and ground planes, traces and vias. This ensures the application processor’s internal transistors will be operating within their specified voltage ranges for proper functionality. The amount of IR drop that will be encounter is based upon amount power drawn for a desired Use Case and PCB trace (widths, geometry and number of parallel traces) and via (size, type and number) characteristics. Components that are distant from their power source are particularly susceptible to IR drop. Designs that rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively impact system performance. Early assessments a PDN’s static (DC) performance helps to determine basic power distribution parameters such as best system input power point, optimal PCB layer stackup, and copper area needed for load currents. The resistance Rs of a plane conductor for a unit length and unit width is called the surface resistivity (ohms per square). L t W 1r Rs = = σ×t t l R = Rs × w SWPS040-178 Figure 8-9. Depiction of Sheet Resistivity and Resistance Ohm’s Law (V = I × R) relates conduction current to voltage drop. At DC, the relation coefficient is a constant and represents the resistance of the conductor. Even current carrying conductors will dissipate power at high currents even though their resistance may be very small. Both voltage drop and power dissipation are proportional to the resistance of the conductor. Figure 8-10 shows a PCB-level static IR drop budget defined between the power management device (PMIC) pins and the application processor’s balls when the PMIC is supplying power. 334 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 • It is highly recommended to physically place the PMIC as close as possible to the processor and on the same side. The orientation of the PMIC vs. processor should be aligned to minimize distance for the highest current rail. PCB Static IR drop and Effective Resistance Source Component Load Component BGA pad on PCB Figure 8-10. Static IR Drop Budget for PCB Only PCB_PO_10 The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR or dc analysis/design methodology consists of designing the PDN such that the voltage drop (under dc operating conditions) across power and ground pads of the transistors of the application processor device is within a specified value of the nominal voltage for proper functionality of the device. A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal voltage. For a 1.35-V supply, this would be ≤20 mV. To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration violations of current-carrying vias, and “Swiss-cheese” effects via placement has on power rails. It is recommended to perform the following analyses: • Lumped resistance/IR drop analysis • Distributed resistance/IR drop analysis NOTE The PMIC companion device supporting Processor has been designed with voltage sensing feedback loop capabilities that enable a remote sense of the SMPS output voltage at the point of use. The NOTE above means the SMPS feedback signals and returns must be routed across PCB and connected to the Device input power ball for which a particular SMPS is supplying power. This feedback loop provides compensation for some of the voltage drop encountered across the PDN within limits. As such, the effective resistance of the PDN within this loop should be determined in order to optimize voltage compensation loop performance. The resistance of two PDN segments are of interest: one from the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the entire PDN route from SMPS output pin/ball to the Processor input power. In the following sections each methodology is described in detail and an example has been provided of analysis flow that can be used by the PCB designer to validate compliance to the requirements on their PCB PDN design. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 335 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 8.2.3.1 PDN Resistance and IR Drop Lumped methodology consists of grouping all of the power pins on both the PMIC (voltage source) and processor (current sink) devices. Then the PMIC source is set to an expected Use Case voltage level and the processor load has its Use Case current sink value set as well. Now the lumped/effective resistance for the power rail trace/plane routes can be determine based upon the actual layout’s power rail etch wide, shape, length, via count and placement Figure 8-11 illustrates the pin-grouping/lumped concept. The lumped methodology consists of importing the PCB layout database (from Cadence Allegro tool or any other layout design tool) into the static IR drop modeling and simulation tool of preference for the PCB designer. This is followed by applying the correct PCB stack-up information (thickness, material properties) of the PCB dielectric and metallization layers. The material properties of dielectric consist of permittivity (Dk) and loss tangent (Df). For the conductor layers, the correct conductivity needs to be programmed into the simulation tool. This is followed by pin-grouping of the power and ground nets, and applying appropriate voltage/current sources. The current and voltage information can be obtained from the power and voltage specifications of the device under different operating conditions / Use Cases. Grouped Power/Ground pins to create 1 equivalent resistive branch Sources Multiport net Branch Port/Pin Sources Sinks Sinks SWPS040-179 Figure 8-11. Pin-grouping concept: Lumped and Distributed Methodologies ADVANCE INFORMATION 8.2.4 Step 4: Frequency Analysis Delivering low noise voltage sources are very important to allowing a system to operate at the lowest possible Operational Performance Point (OPP) for any one Use Case. An OPP is a combination of the supply voltage level and clocking rate for key internal processor domains. A SCH and PCB designed to provide low noise voltage supplies will then enable the processor to enter optimal OPPs for each Use Case that in turn will minimize power dissipation and junction temperatures on-die. Therefore, it is a good engineering practice to perform a Frequency Analysis over the key power domains. Frequency analysis and design methodology results in a PDN design that minimizes transient noise voltages at the processor’s input power balls. This allows the processor’s internal transistors to operate near the minimum specified operating supply voltage levels. To accomplish this one must evaluate how a voltage supply will change due to impedance variations over frequency. This analysis will focus on the decoupling capacitor network (VDD_xxx and VSS/Gnd rails) at the load. Sufficient capacitance with a distribution of self-resonant points will provide for an overall lower impedance vs frequency response for each power domain. Decoupling components that are distant from their load’s input power are susceptible to encountering spreading loop inductance from the PCB design. Early analysis of each key power domain’s frequency response helps to determine basic decoupling capacitor placement, optimal footprint, layer assignment, and types needed for minimizing supply voltage noise/fluctuations due to switching and load current transients. NOTE Evaluation of loop inductance values for decoupling capacitors placed ~300mils closer to the load’s input power balls has shown an 18% reduction in loop inductance due to reduced distance. 336 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 • Decoupling capacitors must be carefully placed in order to minimize loop inductance impact on supply voltage transients. A real capacitor has characteristics not only of capacitance but also inductance and resistance. Figure 8-12 shows the parasitic model of a real capacitor. A real capacitor must be treated as an RLC circuit with effective series resistance (ESR) and effective series inductance (ESL). C ESL ESR SWPS040-175 Figure 8-12. Characteristics of a Real Capacitor With ESL and ESR The magnitude of the impedance of this series model is given as: Z= ESR2 +ωæçè EωSELSL - 1 ωC ö2 ÷ø where : w = 2π¦ SWPS040-e002 Figure 8-13. Series Model Impedance Equation Figure 8-14 shows the resonant frequency response of a typical capacitor with a self-resonant frequency of 55 MHz. The impedance of the capacitor is a combination of its series resistance and reactive capacitance and inductance as shown in the equation above. 1.0e+01 S-Parameter Magnitude Job: GCM155R71E153KA55_15NF; 1.0e+00 1.0e–01 1.0e–02 XC=1/ωC XL=ωL 1.0e–03 1.0e–04 1.00e–002 1.00e+000 Resonant frequency (55 MHz) (minimum) 1.00e+002 1.00e+004 Frequency (MHz) 1.00e+006 Figure 8-14. Typical Impedance Profile of a Capacitor Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 1.00e+008 SWPS040-176 PCB Guidelines 337 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Because a capacitor has series inductance and resistance that impacts its effectiveness, it is important that the following recommendations are adopted in placing capacitors on the PDN. Wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and resistance. This was shown earlier in Figure 8-1. The capacitor mounting inductance and resistance values include the inductance and resistance of the pads, trace, and vias. Whenever possible, use footprints that have the lowest inductance configuration as shown in Figure 8-15 The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing. Further improvements can be made to the mounting by placing vias to the side of capacitor lands or doubling the number of vias as shown in Figure 8-15. If the PCB manufacturing processes allow it and if cost-effective, via-in-pad (VIP) geometries are strongly recommended. In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z is due to PCB thickness (as shown in Figure 8-2). From left to right the capacitor footprint types shown are known as: • 2-via, Skinny End Exit (2vSEE) • 2-via, Wide End Exit (2vWEE) • 2-via, Wide Side Exit (2vWSE) • 4-via, Wide Side Exit (4vWSE) • 2-via, In-Pad (2vIP) Via Pad Via-in-pad ADVANCE INFORMATION Trace Mounting geometry for reduced inductance SWPS040-177 Figure 8-15. Capacitor Placement Geometry for Improved Mounting Inductance NOTE Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case) vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was used in place of 2vSEE. 338 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY ConnectorPRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Frequency analysis for the MPU power domain has yielded the vdd_mpu Impedance vs Frequency response shown in Section 8.3.7.2, vdd_mpu Example Analysis. As the example shows the overall MPU PDN Reff meets the maximum recommended PDN resistance of 10mΩ. 8.2.5 System ESD Generic Guidelines 8.2.5.1 System ESD Generic PCB Guideline Protection devices must be placed close to the ESD source which means close to the connector. This allows the device to subtract the energy associated with an ESD strike before it reaches the internal circuitry of the application board. To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the lowresistive, low-inductive path from the signal to the ground is granted and not increasing the impedance between signal and ground. For ESD protection array being railed to a power supply when no decoupling capacitor is available in close vicinity, consider using a decoupling capacitor (≥ 0.1 µF) tight to the VCC pin of the ESD protection. A positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse. Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and GND in Figure 8-16) from connector to external protection because the interconnect may see between 15A to 30-A current in a short period of time during the ESD event. Bypass capacitor 0.1 mf (minimum) Stub inductance Signal VCC Protected circuit Interconnection inductance Stub inductance vcc Minimize such inductance by optimizing layout Ground inductance Stub inductance External protection VCC Signal ESD strike Keep distance between protected circuit and external protection Keep external protection closed by connector SPRABP6-004 Figure 8-16. Placement Recommendation for an ESD External Protection NOTE To ensure normal behavior of the ESD protection (unwanted leakage), it is better to ground the ESD protection to the board ground rather than any local ground (example isolated shield or audio ground). Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 339 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity • Avoid running critical signal traces (clocks, resets, interrupts, control signals, and so forth) near PCB edges. • Add high frequency filtering: Decoupling capacitors close to the receivers rather than close to the drivers to minimize ESD coupling. • Put a ground (guard) ring around the entire periphery of the PCB to act as a lightning rod. • Connect the guard ring to the PCB ground plane to provide a low impedance path for ESD-coupled current on the ring. • Fill unused portions of the PCB with ground plane. • Minimize circuit loops between power and ground by using multilayer PCB with dedicated power and ground planes. • Shield long line length (strip lines) to minimize radiated ESD. • Avoid running traces over split ground planes. It is better to use a bridge connecting the two planes in one area. BAD BETTER ADVANCE INFORMATION Figure 8-17. Trace Examples SWPS040-220 • Always route signal traces and their associated ground returns as close to one another as possible to minimize the loop area enclosed by current flow: – At high frequencies current follows the path of least inductance. – At low frequencies current flows through the path of least resistance. 8.2.6 EMI / EMC Issues Prevention All high-speed digital integrated circuits can be sources of unwanted radiation, which can affect nearby sensitive circuitry and cause the final product to have radiated emissions levels above the limits allowed by the EMC regulations if some preventative steps are not taken. Likewise, analog and digital circuits can be susceptible to interference from the outside world and picked up by the circuitry interconnections. To minimize the potential for EMI/EMC issues, the following guidelines are recommended to be followed. 8.2.6.1 Signal Bandwidth To evaluate the frequency of a digital signal, an estimated rule of thumb is to consider its bandwidth fBW with respect to its rise time, tR: fBW ≈ 0.35 / tR This frequency actually corresponds to the break point in the signal spectrum, where the harmonics start to decay at 40 dB per decade instead of 20 dB per decade. 340 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 8.2.6.2 Signal Routing 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding Keep radio frequency (RF) sensitive circuitry (like GPS receivers, GSM/WCDMA, Bluetooth/WLAN transceivers, frequency modulation (FM) radio) away from high-speed ICs (the device, power and audio manager, chargers, memories, and so forth) and ideally on the opposite side of the PCB. For improved protection it is recommended to place these emission sources in a shield can. If the shield can have a removable lid (two-piece shield), ensure there is low contact impedance between the fence and the lid. Leave some space between the lid and the components under it to limit the high-frequency currents induced in the lid. Limit the shield size to put any potential shield resonances above the frequencies of interest; see Figure 8-14, Typical Impedance Profile of a Capacitor. 8.2.6.2.2 Signal Routing—Outer Layer Routing In case there is a need to use the outer layers for routing outside of shielded areas, it is recommended to route only static signals and ensure that these static signals do not carry any high-frequency components (due to parasitic coupling with other signals). In case of long traces, make provision for a bypass capacitor near the signal source. Routing of high-frequency clock signals on outer layers, even for a short distance, is discouraged, because their emissions energy is concentrated at the discrete harmonics and can become significant even with poor radiators. Coplanar shielding of traces on outer layers (placing ground near the sides of a track along its length) is effective only if the distance between the trace sides and the ground is smaller that the trace height above the ground reference plane. For modern multilayer PCBs this is often not possible, so coplanar shielding will not be effective. Do not route high-frequency traces near the periphery of the PCB, as the lack of a ground reference near the trace edges can increase EMI: see Section 8.2.6.3, Ground Guidelines. 8.2.6.3 Ground Guidelines 8.2.6.3.1 PCB Outer Layers Ideally the areas on the top and bottom layers of the PCB that are not enclosed by a shield should be filled with ground after the routing is completed and connected with an adequate number of vias to the ground on the inner ground planes. 8.2.6.3.2 Metallic Frames Ensure that all metallic parts are well connected to the PCB ground (like LCD screens metallic frames, antennas reference planes, connector cages, flex cables grounds, and so forth). If using flex PCB ribbon cables to bring high-frequency signals off the PCB, ensure they are adequately shielded (coaxial cables or flex ribbons with a solid reference ground). 8.2.6.3.3 Connectors For high-frequency signals going to connectors choose a fully shielded connector, if possible (for example, SD card connectors). For signals going to external connectors or which are routed over long distances, it is recommended to reduce their bandwidth by using low-pass filters (resistor, capacitor (RC) combinations or lossy ferrite inductors). These filters will help to prevent emissions from the board and can also improve the immunity from external disturbances. 8.2.6.3.4 Guard Ring on PCB Edges The major advantage of a multilayer PCB with ground-plane is the ground return path below each and every signal or power trace. As shown in Figure 8-18 the field lines of the signal return to PCB ground as long as an infinite ground is available. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 341 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Traces near the PCB-edges do not have this infinite ground and therefore may radiate more than the others. Thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in the vicinity of PCB edges, or, if not avoidable, must be accompanied by a guard ring on the PCB edge. EARLY PRELIMINARY ADVANCE INFORMATION SWPS040-199 Figure 8-18. Field Lines of a Signal Above Ground Signal Power Ground Signal SWPS040-200 Figure 8-19. Guard Ring Routing The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on the borders of all layers (including power layer) must be applied as shown in Figure 8-19. As these traces must have the same (HF–) potential as the ground plane they must be connected to the ground plane at least every 10 mm. 8.2.6.3.5 Analog and Digital Ground For the optimum solution, the AGND and the DGND planes must be connected together at the power supply source in a same point. This ensures that both planes are at the same potential, while the transfer of noise from the digital to the analog domain is minimized. 8.3 Core Power Domains 8.3.1 General Constraints • Max PCB static/DC voltage drop (IRd) budget between PMIC’s power inductor/filter capacitor node and Processor input (including ground return losses) is 1.5% of supply voltage. • Max Total Effective Resistance (Reff) budget for key power rails only (not including Gnd plane) from PMIC’s outputs to Processor is 10 - 50mΩ depending upon maximum load currents. • Max PCB dynamic/AC peak-to-peak ripple voltage budget between PMIC and Processor including ground return is 5% of nominal supply voltage. • Max PCB Loop Inductance (LL) budget between Processor’s power inputs and local bulk and high frequency decoupling capacitors (including ground return) ranges from 0.5 – 2.5nH depending upon maximum transient load currents. 342 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 • Max PCB Impedance vs Frequency budget between Processor’s power inputs and PMIC’s output power (including ground return) is determined by using the Frequency Domain Target Impedance Method in order to determine the frequency range (from DC to Fmax) for which PDN’s impedance value remains below a “target impedance” (Zt). The Zt value is determined by: EARLY PRELIMINARY ADVANCE INFORMATION Voltage Rail x %Ripple ZTarget = 0.5 x I max transient PCB_CPD_8 Figure 8-20. PDN’s Target impedance Fmax is the frequency point after which adding a reasonable number of decoupling capacitors does not reduce the power rail impedance below the desired target impedance (Zt). This is due to the dominance of the PCB’s parasitic planar spreading and internal package inductances. • PMIC SMPS output capacitor values: – 22uF max output power filter capacitor located close to the PMIC and power inductor – 22uF max bulk decoupling capacitance located close to Processor’s input power balls – SMPS sense feedback and sense return balls should be routed to connect to Processor’s input power (VDD_xxx) and ground (VSS) balls 8.3.2 Voltage Decoupling Recommended power supply decoupling capacitors main characteristics for commercial products whose ambient temperature is not to exceed +85C are shown in table below: Table 8-1. Commercial Applications Recommended Decoupling Capacitors Characteristics(1)(2)(3) Value Voltage [V] Package Stability Dielectric Capacitanc Temp Range Temp e [°C] Sensitivity Tolerance [%] REFERENCE 22µF 6,3 0603 Class 2 X5R - / + 20% -55 to + 85 - / + 15 GRM188R60J226M EA0L 10µF 4,0 0402 Class 2 X5R - / + 20% -55 to + 85 - / + 15 GRM155R60G106M E44 4.7µF 6,3 0402 Class 2 X5R - / + 20% -55 to + 85 - / + 15 GRM155R60J475M E95 2.2µF 6,3 0402 Class 2 X5R - / + 20% -55 to + 85 - / + 15 GRM155R60J225M E95 1µF 6,3 0201 Class 2 X5R - / + 20% -55 to + 85 - / + 15 GRM033R60J105M EA2 470nF 6,3 0201 Class 2 X5R - / + 20% -55 to + 85 - / + 15 GRM033R60G474M E90 220nF 6,3 0201 Class 2 X5R - / + 20% -55 to + 85 - / + 15 GRM033R60J224M E90 100nF 6,3 0201 Class 2 X5R - / + 20% -55 to + 85 - / + 15 GRM033R60J104M E19 (1) Minimum value for each PCB capacitor: 100 nF. (2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range. (3) In comparison with the EIA Class 1 dielectrics, Class 2 dielectric capacitors tend to have severe temperature drift, high dependence of capacitance on applied voltage, high voltage coefficient of dissipation factor, high frequency coefficient of dissipation, and problems with aging due to gradual change of crystal structure. Aging causes gradual exponential loss of capacitance and decrease of dissipation factor. Recommended power supply decoupling capacitors main characteristics for automotive products are shown in table below: Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 343 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 8-2. Automotive Applications Recommended Decoupling Capacitors Characteristics (1)(2) Value Voltage [V] Package Stability Dielectric Capacitanc Temp Temp e Range [°C] Sensitivity Tolerance [%] REFERENCE 22µF 6,3 1206 Class 2 X7R - / + 20% -55 to + 125 - / + 15 GCM31CR70J226M E23 10µF 6,3 0805 Class 2 X7R - / + 20% -55 to + 125 - / + 15 GCM21BR70J106M E22 4.7µF 10 0805 Class 2 X7R - / + 20% -55 to + 125 - / + 15 GCM21BC71A475M A73 2.2µF 6,3 0603 Class 2 X7R - / + 20% -55 to + 125 - / + 15 GCM188R70J225M E22 1µF 16 0603 Class 2 X7R - / + 20% -55 to + 125 - / + 15 GCM188R71C105M A64 470nF 16 0603 Class 2 X7R - / + 20% -55 to + 125 - / + 15 GCM188R71C474M A55 220nF 25 0603 Class 2 X7R - / + 20% -55 to + 125 - / + 15 GCM188L81C224M A37 100nF 16 0402 Class 2 X7R - / + 20% -55 to + 125 - / + 15 GCM155R71C104M A55 (1) Minimum value for each PCB capacitor: 100 nF. (2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range. 8.3.3 Static PDN Analysis Effective Resistance (Reff) quantifies the PCB’s power net routing resistance with values given for different segments: • Power Inductor to Processor = PCB trace resistance only between power inductor’s output and Processor power balls. • Total = all PCB trace resistance back to PMIC’s output balls and including any series elements (i.e. current sensing resistor) 8.3.4 Dynamic PDN Analysis Loop Inductance (LL) shows a range of PCB’s inherent inductance between Processor supply decoupling capacitors and Processor ground connections (ESL NOT included). Impedance value at a given frequency is based on the allowing 5% p-p ripple noise on a supply from DC up to a given frequency of interest Table 8-3. Recommended PDN and Decoupling Characteristics (1)(2)(3)(4)(5) PDN Analysis: Static Supply vdd_mpu vdda_dsp_eve vdd vdd_gpu vdd_iva vdds_ddr1 vdds_ddr2 Max Reff (7) [mΩ] 10 13 27 18 48 10 10 Dec. Cap. Max LL(8) (6) [nH] 2 2.5 2 2.5 2 2.5 2.5 Dynamic Number of Recommended Decoupling Capacitors per Supply Impedance [mΩ] Frequency of Interest [MHz] 100 nF(6) 220 nF 470 nF 1μF 2.2 μF 4.7 μF 10 μF 22 μF 57 20 12 2 2 3 1 1 1 54 20 8 1 1 2 1 1 1 87 50 6 1 1 1 1 1 207 50 6 1 1 1 1 1 800 100 5 1 1 200 100 8 4 2 2 1 200 100 8 4 2 2 1 344 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 (1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Electrical Characteristics chapter. (2) ESL must be as low as possible and must not exceed 0.5 nH. (3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency) based on the Recommended Operating Conditions table of the Electrical Characteristics chapter. (4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor power balls. (5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls. (6) High-frequency (30 to 70MHz) PCB decoupling capacitors (7) Maximum Reff from SMPS to Processor. (8) Maximum Loop Inductance for decoupling capacitor. NOTE For power IC which can support more than 10uF close to processor, a bulk capacitor of at least 22uF is strongly recommended for VDD_MPU power domains. 8.3.5 Power Supply Mapping TPS659039 is the Power Management IC (PMIC) that should be used for the Device designs. TI recommends use of this PMIC for the following reasons: • TI has validated its use with the Device • Board level margins including transient response and output accuracy are analyzed and optimized for the entire system • Support for power sequencing requirements (refer to Section 3.6 Power Sequencing) • Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software Deviations from using this PMIC will require additional analysis, validation, and software development. Table 8-4 illustrates the approved and validated power supply connections to the Device for the SMPS outputs of the TPS659039 PMIC. Table 8-4. Power Supply Connections SMPS Valid Combination 1: Reference Platform Valid Combination 2: MPU Centric Valid Combination 3: DSPEVE Centric SMPS1/2/3(1) vdd_mpu vdd_mpu vdd_mpu, vdd_gpu, vdd_iva SMPS3(1) Free (DDR Memory) Free (DDR Memory) Free (DDR Memory) SMPS4/5 vdd_dspeve vdd_dspeve, vdd_gpu, vdd_iva vdd_dspeve SMPS6 vdd_gpu vdd vdd SMPS7 vdd Free Free SMPS8 vdd_iva Free Free SMPS9 vdds18v vdds18v vdds18v (1) SMPS1/2/3 can be used in dual phase (SMPS1/2) as long as it is guaranteed that the MPU OPP does not operate above OPP_HIGH. This in turn will free up SMPS3 for other usage such as supplying DDR Memory. 8.3.6 DPLL Voltage Requirement The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The TPS659039 PMIC LDOLN output is specifically designed to meet this low noise requirement. NOTE For more information about Input Voltage Sources, see Section 4.2.2 DPLLs, DLLs Specifications Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 345 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 8-4 present the voltage inputs that supply the DPLLs. Table 8-5. Input Voltage Power Supplies for the DPLLs POWER SUPPLY vdda_abe_per vdda_ddr vdda_debug vdda_dsp_eve vdda_gmac_core vdda_gpu vdda_iva vdda_video vdda_mpu vdda_osc DPLLs DPLL_PER, DPLL_ABE and PER HSDIVIDER analog power supply DPLL_DDR and DDR HSDIVIDER analog power supply DPLL_DEBUG analog power supply DPLL_DSP and DPLL_EVE analog power supply DPLL_CORE and HSDIVIDER analog power supply DPLL_GPU analog power supply DPLL_IVA analog power supply DPLL_VIDEO1 and DPLL_VIDEO2 analog power supply DPLL_MPU analog power supply not DPLL input but is required to be supplied by low noise input voltage 8.3.7 Example PCB Design The following sections describe an example PCB design and its resulting PDN performance for the vdd_mpu key processor power domain. 8.3.7.1 Example Stack-up Layer Assignments: • Layer Top: Signal and Segmented Power Plane – Processor and PMIC components placed on Top-side • Layer 2: Gnd Plane1 • Layer 3: Signals • Layer n: Power Plane1 • Layer n+1: Power Plane 2 • Layer n+2: Signal • Layer n+3: Gnd Plane2 • Layer Bottom: Signal and Segmented Power Planes – Decoupling caps, etc. Via Technology: Through-hole Copper Weight: • ½ oz for all signal and plane layers other thanGnd Plane1 and Gnd Plane2 set to 2oz for improved thermal heat spreading • Total PCB Thickness 0.080inches 8.3.7.2 vdd_mpu Example Analysis Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not exceed 10mΩ. Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and decoupling capacitances should not exceed 2.0nH (ESL NOT included ) Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS output power balls should not exceed 57mΩ at 20MHz. 346 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 8-6. Example PCB vdd_mpu PI Analysis Summary Parameter Processor OPP Clocking Rate Voltage Level Max Current Draw Max Effective Resistance: Power Inductor Segment Total Reff Max Loop Inductance Impedance Target Recommendation High 1.5 GHz 1.22V 5.12 A 10mΩ 2.0nH 57mΩ F<20Mhz Example PCB 1.22V 5.12 A 9.0mΩ 1.0 – 1.4nH 57mΩ F<20Mhz Figure 8-21, Figure 8-22, Figure 8-23, and Figure 8-24 show a PCB layout example and the resulting PI analysis results. U45 PMIC SMPS (3000mA) SMPS1_SW (E11, E12, E13) SMPS2 (3000mA) SMPS1_SW (E11, E12, E13) SMPS3 (3000mA) SMPS1_SW (E11, E12, E13) SW1 L17 1.0uH, 4.5A, 1616 IHLP-1616ABER1R0M11 PCB – Top-side SMPS_1_2_3 SW2 C410 22uF, 4V, 0603 GRM188R60G226MEA0L PCB – Bottom-side L15 1.0uH, 4.5A, 1616 IHLP-1616ABER1R0M11 PCB – Top-side SW3 C378 22uF, 4V, 0603 GRM188R60G226MEA0L PCB – Bottom-side L13x 1.0uH, 4.5A, 1616 IHLP-1616ABER1R0M11 PCB – Top-side C350 22uF, 4V, 0603 GRM188R60G226MEA0L PCB – Bottom-side R181 0.001ohm, 1%, 4W, 2725 CSS2725FT1L00 PCB – Top-side 6A U52 vdd_mpu C365, 366, 368, 369, 370, 384, 385, 387, 389, 391, 392, 396 0.1uF, 6.3V, X5R, 0201 GRM033R60J104KE19D PCB – Bottom-side C92, 96 0.22uF, 6.3V, X5R, 0201 ECJ-ZEB0J224M PCB – Top-side Device SoC vdd_mpu (N18, K18, L19 N17, M17, L17 M18, L18, P18 K17, L15, L16 M15, M16, P17 R18) C93, 94 0.47uF, 4V, X5R, 0201 AMK063BJ474MP-F PCB – Top-side PS_EVM_3V3 U39 INA226 A0 VIN+ A1 VIN- PM I2C Addr: 100 0001 C91, 95, 367 1.0uF, 6.3V, X5R, 0201 GRM033R60J105MEA2D PCB – 2 Top-side & 1 Bottom C359 2.2uF, 6.3V, X5R, 0402 C1005X5R0J225M PCB – Bottom-side C360 4.7uF, 6.3V, X5R, 0402 GRM155R60J475ME8 7D PCB – Bottom-side C356 22uF, 4V, X5R, 0603 GRM188R60G226ME A0L PCB – Bottom-side Figure 8-21. vdd_mpu Simplified SCH Diagram Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 347 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Device (U52) vdd_mpu “Ball-Field” 4 of 22 Decoupling Caps (C96, 385, 387, 389; 0201) www.ti.com Sense Resistor (R181; 2725) PMIC (U45) Power Inductors (L13, 15 & 17; 1616) Top -side segmented planes (vdd_mpu = Green) Multiple vias connecting power segments on different layers Figure 8-22. vdd_mpu routing [Top Layer] EARLY PRELIMINARY ADVANCE INFORMATION Interior Power Plane #2, Layer 9 of 16 (vdd_mpu = Green) Figure 8-23. vdd_mpu routing [Internal Power Plane #2] Larger Value Decoupling Caps (2.2uF C359, 4.7uF C360 & 22uF C356; 0402 & 0603) Bulk Caps underneath power inductors (C410, C378, C350; 0603) Remaining 15 of 22 Decoupling Caps (C96, 385, 387, 389; 0201) Figure 8-24. vdd_mpu routing and cap placements [Bottom Layer] PCB_CPD_4 Net[from] SW1 SW2 SW3 SW1 SW2 SW3 vdd_mpu vdd_mpu Table 8-7. PCB Etch Resistance Breakdown - From PMIC Source to Device Load Component [from]: Net[to] Component [to]: L17 L15 L13 L17 L15 L13 R181 R181 SW1 SW2 SW3 SMPS_1_2_3 SMPS_1_2_3 SMPS_1_2_3 vdd_mpu vdd_mpu U45 U45 U45 R181 R181 R181 U52 U52 Etch Resistance (Ω) 0,001038 0,000898 0,000861 0,000696 0,000541 0,000526 0,006311 0,006311 % of Total Etch Resistance 13% 12% 11% 9% 7% 7% 78% 81% 348 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 8-7. PCB Etch Resistance Breakdown - From PMIC Source to Device Load (continued) Net[from] vdd_mpu Component [from]: Net[to] Component [to]: Etch Resistance (Ω) R181 vdd_mpu U52 Total Etch Resistance from SW1 = Total Etch Resistance from SW2 = Total Etch Resistance from SW3 = Max Value = 0,006311 0,008045 0,00775 0,007698 0,008045 % of Total Etch Resistance 82% 100% 100% 100% Net[from] SMPS_1_2_3 SMPS_1_2_3 SMPS_1_2_3 vdd_mpu vdd_mpu vdd_mpu Table 8-8. PCB Etch Resistance Breakdown - From Power Inductor to Device Load Component [from]: Net[to] Component [to]: Etch Resistance (Ω) L17 L15 L13 R181 R181 R181 SMPS_1_2_3 R181 SMPS_1_2_3 R181 SMPS_1_2_3 R181 vdd_mpu U52 vdd_mpu U52 vdd_mpu U52 Total Etch Resistance = Total Etch Resistance = Total Etch Resistance = Max Value = 0,000696 0,000541 0,000526 0,006311 0,006311 0,006311 0,007007 0,006852 0,006837 0,007007 % of Total Etch Resistance 10% 8% 8% 90% 92% 92% 100% 100% 100% Table 8-9. PDN Effective Resistance - From PMIC Source to Device Load PDN Elements Etch Inductor Sense Resistor Max PDN Effectiv Resistance from Source PDN Effective Resistance (Ω) 0,008045 0 0,001 0,009045 % of Total Etch Resistance 89% 0% 11% 100% IR Drop: vdd_mpu (PCB RevJan14, Sentinel PSI) • Source Conditions: 1.22V @ 5,12A • Recommended Reff < 10mΩ • Reff = Total Trace Resistance + Sence Resistor = 8,04mΩ + 1mΩ = 9,04mΩ • Voltage / IR Drop: 1,22 - 1,179 = 52,6 mV Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 349 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY ADVANCE INFORMATION Figure 8-25. vdd_mpu Voltage/IR Drop [All Layers] PCB_CPD_5 Dynamic analysis of this PCB design for the MPU power domain determined the vdd_mpu decoupling capacitor loop inductance and impedance vs frequency analysis shown below. As you can see, the loop inductance values ranged from 1.0 to 1.4nH and were less than maximum 2.0nH recommended. NOTE Comparing loop inductances for capacitors at different distances from the processor’s input power balls shows an 18% reduction for caps placed closer. This was derived by averaging the inductances for the 3 caps with distances over 800mils (Avg LL = 1.33nH) vs the 3 caps with distances less than 600mils (Avg LL = 1.096nH). Cap Ref Model Port Loop Inductacne Des # [nH] C356 1 1,4 C359 2 1,26 C360 3 1,33 C365 4 1,14 C366 5 1,13 C367 6 1,07 C368 7 1,12 C369 8 1,06 C370 9 1,12 C384 10 1,04 C385 11 1,07 C387 12 1,16 C389 13 1,18 C391 14 1,14 C392 15 1,18 C396 16 1,11 Table 8-10. Rail - vdd_mpu Footprint Types 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE PCB Side Bottom Bottom Bottom Bottom Bottom Bottom Bottom Bottom Bottom Bottom Top Top Top Bottom Bottom Bottom Distance to Ball-Field [mils] 897 855 850 817 755 758 811 690 680 686 686 755 693 693 542 745 Value [μF] 22 2,2 4,7 0,1 0,1 1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 Size 0603 0402 0402 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 350 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Cap Ref Model Port Des # C91 17 C92 18 C93 19 C94 20 C95 21 C96 22 Table 8-10. Rail - vdd_mpu (continued) Loop Inductacne [nH] 1,1 1,09 1,01 1,13 1,04 1,08 Footprint Types 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE 4vWSE PCB Side Bottom Bottom Bottom Bottom Bottom Top Distance to Ball-Field [mils] 515 622 504 604 612 612 Value [μF] 1 0,22 0,47 0,47 1 0,22 Size 0201 0201 0201 0201 0201 0201 Loop Inductance range: 1,01 - 1,40 nH PCB_CPD_6 Figure 8-26. vdd_mpu Decoupling Cap Loop Inductances Figure 8-27 shows vdd_mpu Impedance vs Frequency characteristics. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 351 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com EARLY PRELIMINARY ADVANCE INFORMATION 310mΩ @ 100MHz 30mΩ @ 10MHz 160mΩ @ 50MHz 56,6mΩ @ 20MHz Figure 8-27. vdd_mpu Impedance vs Frequency PCB_CPD_7 8.4 Single-Ended Interfaces 8.4.1 General Routing Guidelines The following paragraphs detail the routing guidelines that must be observed when routing the various functional LVCMOS interfaces. • Line spacing: – For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the crosstalk between switching signals between the different lines. On the PCB, this is not achievable everywhere (for example, when breaking signals out from the device package), but it is recommended to follow this rule as much as possible. When violating this guideline, minimize the length of the traces running parallel to each other (see Figure 8-28). W 352 PCB Guidelines D+ S = 2 W = 200 µm SWPS040-185 Figure 8-28. Ground Guard Illustration Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 • Length matching (unless otherwise specified): – For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length difference between the longest and the shortest lines) must be less than 25 mm. – For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length difference between the longest and the shortest lines) must be less than 2.5 mm. • Characteristic impedance – Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to be between 35-Ω and 65-Ω. • Multiple peripheral support – For interfaces where multiple peripherals have to be supported in the star topology, the length of each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify signal integrity based on simulations including actual PCB extraction. 8.4.2 QSPI Board Design and Layout Guidelines The following section details the routing guidelines that must be observed when routing the QSPI interfaces. • The qspi1_sclk output signal must be looped back into the qspi1_rtclk input. • The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must be approximately equal to the signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D). • The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be approximately equal to the signal propagation delay of the control and data signals between the QSPI device and the SoC device (E to F, or F to E). • The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip) • 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-29. • Propagation delays and matching: – A to C = C to D = E to F. – Matching skew: < 60pS – A to B < 450pS – B to C = as small as possible (<60pS) Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 353 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 A R1 0 Ω* qspi1_sclk D Locate both R2 resistors close together near the QSPI device B C R2 10 Ω R2 10 Ω QSPI device clock input www.ti.com EARLY PRELIMINARY ADVANCE INFORMATION qspi1_rtclk E F qspi1_d[x], qspi1_cs[y] QSPI deice IOx, CS# PCB_QSPI_1 Figure 8-29. QSPI Interface High Level Schematic NOTE *0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for finetuning if needed. 8.5 Differential Interfaces 8.5.1 General Routing Guidelines To maximize signal integrity, proper routing techniques for differential signals are important for high-speed designs. The following general routing guidelines describe the routing guidelines for differential lanes and differential signals. • As much as possible, no other high-frequency signals must be routed in close proximity to the differential pair. • Must be routed as differential traces on the same layer. The trace width and spacing must be chosen to yield the differential impedance value recommended. • Minimize external components on differential lanes (like external ESD, probe points). • Through-hole pins are not recommended. • Differential lanes mustn’t cross image planes (ground planes). • No sharp bend on differential lanes. • Number of vias on the differential pairs must be minimized, and identical on each line of the differential pair. In case of multiple differential lanes in the same interface, all lines should have the same number of vias. • Shielded routing is to be promoted as much as possible (for instance, signals must be routed on internal layers that are inside power and/or ground planes). 354 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 8.5.2 USB 2.0 Board Design and Layout Guidelines This section discusses schematic guidelines when designing a universal serial bus (USB) system. 8.5.2.1 Background Clock frequencies generate the main source of energy in a USB design. The USB differential DP/DM pairs operate in high-speed mode at 480 Mbps. System clocks can operate at 12 MHz, 48 MHz, and 60 MHz. The USB cable can behave as a monopole antenna; take care to prevent RF currents from coupling onto the cable. When designing a USB board, the signals of most interest are: • Device interface signals: Clocks and other signal/data lines that run between devices on the PCB. • Power going into and out of the cable: The USB connector socket pin 1 (VBUS ) may be heavily filtered and need only pass low frequency signals of less than ~100 KHz. The USB socket pin 4 (analog ground) must be able to return the current during data transmission, and must be filtered sparingly. • Differential twisted pair signals going out on cable, DP and DM: Depending upon the data transfer rate, these device terminals can have signals with fundamental frequencies of 240 MHz (high speed), 6 MHz (full speed), and 750 kHz (low speed). • External crystal circuit (device terminals XI and X0): 12 MHz, 19.2 MHz, 24 MHz, and 48 MHz fundamental. When using an external crystal as a reference clock, a 24 MHz and higher crystal is highly recommended. 8.5.2.2 USB PHY Layout Guide The following sections describe in detail the specific guidelines for USB PHY Layout. 8.5.2.2.1 General Routing and Placement Use the following routing and placement guidelines when laying out a new design for the USB physical layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI) problems on a four-or-more layer evaluation module (EVM). • Place the USB PHY and major components on the un-routed board first. For more details, see Section 8.5.2.2.2.3. • Route the high-speed clock and high-speed USB differential signals with minimum trace lengths. • Route the high-speed USB signals on the plane closest to the ground plane, whenever possible. • Route the high-speed USB signals using a minimum of vias and corners. This reduces signal reflections and impedance changes. • When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance discontinuities. • Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices or IC’s that use or duplicate clock signals. • Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then the stub should be less than 200 mils. • Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing over anti-etch, commonly found with plane splits. 8.5.2.2.2 Specific Guidelines for USB PHY Layout The following sections describe in detail the specific guidelines for USB PHY Layout. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 355 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 8.5.2.2.2.1 Analog, PLL, and Digital Power Supply Filtering To minimize EMI emissions, add decoupling capacitors with a ferrite bead at power supply terminals for the analog, phase-locked loop (PLL), and digital portions of the chip. Place this array as close to the chip as possible to minimize the inductance of the line and noise contributions to the system. An analog and digital supply example is shown in Figure 8-30. In case of multiple power supply pins with the same function, tie them up to a single low-impedance point in the board and then add the decoupling capacitors, in addition to the ferrite bead. This array of caps and ferrite bead improve EMI and jitter performance. Take both EMI and jitter into account before altering the configuration. Analog Power Supply Ferrite Bead Digital Power Supply 0.1 µF 0.01 µF 0.001 µF Ferrite Bead 0.1 µF 0.01 µF 0.001 µF 10 µF 10 µF SoC Board Figure 8-30. Suggested Array Capacitors and a Ferrite Bead to Minimize EMI ADVANCE INFORMATION 356 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Consider the recommendations listed below to achieve proper ESD/EMI performance: • Use a 0.01 μF cap on each cable power VBUS line to chassis GND close to the USB connector pin. • Use a 0.01 μF cap on each cable ground line to chassis GND next to the USB connector pin. • If voltage regulators are used, place a 0.01 μF cap on both input and output. This is to increase the immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet. 8.5.2.2.2.2 Analog, Digital, and PLL Partitioning If separate power planes are used, they must be tied together at one point through a low-impedance bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail close to the device. The analog ground, digital ground, and PLL ground must be tied together to the lowimpedance circuit board ground plane. 8.5.2.2.2.3 Board Stackup Because of the high frequencies associated with the USB, a printed circuit board with at least four layers is recommended; two signal layers separated by a ground and power layer as shown in Figure 8-31. Signal 1 GND Plane Power Plane Signal 2 Figure 8-31. Four-Layer Board Stack-Up The majority of signal traces should run on a single layer, preferably SIGNAL1. Immediately next to this layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies. 8.5.2.2.2.4 Cable Connector Socket Short the cable connector sockets directly to a small chassis ground plane (GND strap) that exists immediately underneath the connector sockets. This shorts EMI (and ESD) directly to the chassis ground before it gets onto the USB cable. This etch plane should be as large as possible, but all the conductors coming off connector pins 1 through 6 must have the board signal GND plane run under. If needed, scoop out the chassis GND strap etch to allow for the signal ground to extend under the connector pins. Note that the etches coming from pins 1 and 4 (VBUS power and GND) should be wide and via-ed to their respective planes as soon as possible, respecting the filtering that may be in place between the connector pin and the plane. See Figure 8-32 for a schematic example. Place a ferrite in series with the cable shield pins near the USB connector socket to keep EMI from getting onto the cable shield. The ferrite bead between the cable shield and ground may be valued between 10 Ω and 50 Ω at 100 MHz; it should be resistive to approximately 1 GHz. To keep EMI from getting onto the cable bus power wire (a very large antenna) a ferrite may be placed in series with cable bus power, VBUS, near the USB connector pin 1. The ferrite bead between connector pin 1 and bus power may be valued between 47 Ω and approximately 1000 Ω at 100 MHz. It should continue being resistive out to approximately 1 GHz, as shown in Figure 8-32. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 357 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 VBUS Ferrite Bead U2 U1 5 SHIELD_GND 4 GND 3 DP 2 DM 1 +5 V 6 SHIELD_GND USB Socket Ferrite Bead www.ti.com Figure 8-32. USB Connector 8.5.2.2.2.5 Clock Routings To address the system clock emissions between devices, place a ~10 to 130 Ω resistor in series with the clock signal. Use a trial and error method of looking at the shape of the clock waveform on a high-speed oscilloscope and of tuning the value of the resistance to minimize waveform distortion. The value on this resistor should be as small as possible to get the desired effect. Place the resistor close to the device generating the clock signal. If an external crystal is used, follow the guidelines detailed in the Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122). When routing the clock traces from one device to another, try to use the 3W spacing rule. The distance from the center of the clock trace to the center of any adjacent signal trace should be at least three times the width of the clock trace. Many clocks, including slow frequency clocks, can have fast rise and fall times. Using the 3W rule cuts down on crosstalk between traces. In general, leave space between each of the traces running parallel between the devices. Avoid using right angles when routing traces to minimize the routing distance and impedance discontinuities. For further protection from crosstalk, run guard traces beside the clock signals (GND pin to GND pin), if possible. This lessens clock signal coupling, as shown in Figure 8-33. 3W 3W ADVANCE INFORMATION Trace W Figure 8-33. 3W Spacing Rule 358 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 8.5.2.2.2.6 Crystals/Oscillator Keep the crystal and its load capacitors close to the USB PHY pins, XI and XO (see Figure 8-34). Note that frequencies from power sources or large capacitors can cause modulations within the clock and should not be placed near the crystal. In these instances, errors such as dropped packets occur. A placeholder for a resistor, in parallel with the crystal, can be incorporated in the design to assist oscillator startup. Power is proportional to the current squared. The current is I = C*dv/dt, since dv/dt is a function of the PHY, current is proportional to the capacitive load. Cutting the load to 1/2 decreases the current by 1/2 and the power to 1/4 of the original value. For more details on crystal selection, see the Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122). 0.1 µF X1 Power Pins 0.001 µF XTAL X0 USB PHY Figure 8-34. Power Supply and Clock Connection to the USB PHY 8.5.2.2.2.7 DP/DM Trace Place the USB PHY as close as possible to the USB 2.0 connector. The signal swing during high-speed operation on the DP/DM lines is relatively small (400 mV ± 10%), so any differential noise picked up on the twisted pair can affect the received signal. When the DP/DM traces do not have any shielding, the traces tend to behave like an antenna and picks up noise generated by the surrounding components in the environment. To minimize the effect of this behavior: • DP/DM traces should always be matched lengths and must be no more than 4 inches in length; otherwise, the eye opening may be degraded (see Figure 8-35). • Route DP/DM traces close together for noise rejection on differential signals, parallel to each other and within two mils in length of each other (start the measurement at the chip package boundary, not to the balls or pins). • A high-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic impedance of 90 Ω ±15%. In layout, the impedance of DP and DM should each be 45 Ω ± 10%. • DP/DM traces should not have any extra components to maintain signal integrity. For example, traces cannot be routed to two USB connectors. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 359 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Minimize This Distance USB PHY D+ Connector D- VBUS GND D+ D- www.ti.com Cable Connector Figure 8-35. USB PHY Connector and Cable Connector 8.5.2.2.2.8 DP/DM Vias When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended. 8.5.2.2.2.9 Image Planes An image plane is a layer of copper (voltage plane or ground plane), physically adjacent to a signal routing plane. Use of image planes provides a low impedance, shortest possible return path for RF currents. For a USB board, the best image plane is the ground plane because it can be used for both analog and digital circuits. • Do not route traces so they cross from one plane to the other. This can cause a broken RF return path resulting in an EMI radiating loop as shown in Figure 8-36. This is important for higher frequency or repetitive signals. Therefore, on a multi-layer board, it is best to run all clock signals on the signal plane above a solid ground plane. • Avoid crossing the image power or ground plane boundaries with high-speed clock signal traces immediately above or below the separated planes. This also holds true for the twisted pair signals (DP, DM). Any unused area of the top and bottom signal layers of the PCB can be filled with copper that is connected to the ground plane through vias. 360 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 EARLY PRELIMINARY ADVANCE INFORMATION Don't Do Figure 8-36. Do Not Cross Plane Boundaries • Do not overlap planes that do not reference each other. For example, do not overlap a digital power plane with an analog power plane as this produces a capacitance between the overlapping areas that could pass RF emissions from one plane to the other, as shown in Figure 8-37. Analog Power Plane Unwanted Capacitance Digital Power Plane Figure 8-37. Do Not Overlap Planes • Avoid image plane violations. Traces that route over a slot in an image plane results in a possible RF return loop, as shown in Figure 8-38. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 361 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com RF Return Current RF Return Current EARLY PRELIMINARY ADVANCE INFORMATION Slot in Image Plane Slot in Image Plane Bad Better Figure 8-38. Do Not Violate Image Planes 8.5.2.2.2.10 JTAG Interface For test and debug of the USB PHY only, an IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture (JTAG) and Serial Test and Configuration Interface (STCI) may be available on the System-on-Chip (SoC). If available, keep the USB PHY JTAG interface less than six inches; keeping this distance short reduces noise coupling from other devices and signal loss due to resistance. 8.5.2.2.2.11 Power Regulators Switching power regulators are a source of noise and can cause noise coupling if placed close to sensitive areas on a circuit board. Therefore, the switching power regulator should be kept away from the DP/DM signals, the external clock crystal (or clock oscillator), and the USB PHY. 8.5.2.3 Electrostatic Discharge (ESD) International Electronic Commission (IEC) 61000-4-xx is a set of about 25 testing specifications from the IEC. IEC ESD Stressing is done both un-powered and with power applied, and with the device functioning. There must be no physical damage, and the device must keep working normally after the conclusion of the stressing. Typically, equipment has to pass IEC stressing at 8 kV contact and 15 kV air discharge, or higher. To market products/systems in the European community, all products/systems must be CE compliant and have the CE Mark. To obtain the CE Mark, all products/systems need to go through and pass IEC standard requirements; for ESD, it is 61000-4-2. 61000-4-2 requires that the products/systems pass contact discharge at 8 kV and air discharge at 15 kV. When performing an IEC ESD Stressing, only pins accessible to the outside world need to pass the test. The system into which the integrated circuit (IC) is placed makes a difference in how well the IC does. For example: • Cable between the zap point and the IC attenuate the high frequencies in the waveform. • Series inductance on the PCB board attenuates the high frequencies. • Unless the capacitor’s ground connection is inductive, capacitance to ground shunts away high frequencies. 8.5.2.3.1 IEC ESD Stressing Test The following sections describe in detail the IEC ESD Stressing Test modes and test types. 8.5.2.3.1.1 Test Mode The IEC ESD Stressing test is done through two modes: contact discharge mode and air discharge mode. 362 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 For the contact discharge test mode, the preferred way is direct contact applied to the conductive surfaces of the equipment under test (EUT). In the case of the USB system, the conductive surface is the outer casing of the USB connector. The electrode of the ESD generator is held in contact with the EUT or a coupling plane prior to discharge. The arc formation is created under controlled conditions, inside a relay, resulting in repeatable waveforms; however, this arc does not accurately recreate the characteristic unique to the arc of an actual ESD event. 8.5.2.3.1.2 Air Discharge Mode The air discharge usually applies to a non-conductive surface of the EUT. Instead of a direct contact with the EUT, the charged electrode of the ESD generator is brought close to the EUT, and a spark in the air to the EUT actuates the discharge. Compared to the contact discharge mode, the air discharge is more realistic to the actual ESD occurrence. However, due to the variations of the arc length, it may not be able to produce repeatable waveform. 8.5.2.3.1.3 Test Type The IEC ESD Stressing test has two test types: direct discharge and indirect discharge. Direct discharge is applies directly to the surface or the structure of the EUT. It includes both contact discharge and air discharge modes. Indirect discharge applies to a coupling plane in the vicinity of the EUT. The indirect discharge is used to simulate personal discharge to objects which are adjacent to the EUT. It includes contact discharge mode only. 8.5.2.3.2 TI Component Level IEC ESD Test TI Component Level IEC ESD Test tests only the IC terminals that are exposed in system level applications. It can be used to determine the robustness of on-chip protection and the latch-up immunity. The IC can only pass the TI Component Level IEC ESD test when there is no latch-up and IC is fully functional after the test. 8.5.2.3.3 Construction of a Custom USB Connector A standard USB connector, either type A or type B, provides good ESD protection. However, if a custom USB connector is desired, the following guidelines should be observed to ensure good ESD protection. • There should be an easily accessible shield plate next to the connector for air-discharge mode purpose. • Tie the outer shield of the connector to GND. When a cable is inserted into the connector, the shield of the cable should first make contact with the outer shield. • If the connector includes power and GND, the lead of power and GND need to be longer than the leads of signal. • The connector needs to have a key to ensure proper insertion of the cable. • See the standard USB connector for reference. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 363 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 8.5.2.3.4 ESD Protection System Design Consideration ESD protection system design consideration is covered in Section 8.5.2.2 of this document. The following are additional considerations for ESD protection in a system. • Metallic shielding for both ESD and EMI • Chassis GND isolation from the board GND • Air gap designed on board to absorb ESD energy • Clamping diodes to absorb ESD energy • Capacitors to divert ESD energy • The use of external ESD components on the DP/DM lines may affect signal quality and are not recommended. 8.5.2.4 References • USB 2.0 Specification, Intel, 2000, http://www.usb.org/developers/docs/ • High Speed USB Platform Design Guidelines, http://www.intel.com/technology/usb/download/usb2dg_R1_0.pdf Intel, • Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122) 2000, 8.5.3 USB 3.0 Board Design and Layout Guidelines This section provides the timing specification for the USB3.0 (USB1 in the device) interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to ensure the USB3.0 interface requirements are met. 8.5.3.1 USB 3.0 interface introduction The USB 3.0 have two unidirectional differential pairs: TXp/TXn pair and RXp/RXn pair. AC coupling caps are needed on the board for TX traces. Figure 8-39 present high level schematic diagram for USB 3.0 interface. ADVANCE INFORMATION 364 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com USB2 VBUS usb2_dp usb2_dm TI Confidential — NDA Restrictions DRA75x, DRA74x Choke SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Close to USB connector VCC 10kΩ VBUS usb2_dp usb2_dm ESD2 VBUS usb2_dp usb2_dm GND USB2.0 Connector 0Ω ADVANCE INFORMATION EARLY PRELIMINARY DEVICE VBUS usb1_dp usb1_dm USB1 VCC 10kΩ Choke VBUS usb1_dp usb1_dm ESD2 VBUS usb1_dp usb1_dm GND USB3.0 Connector 0Ω usb_txp0 C usb_txn0 C usb_rxp0 usb_rxn0 Choke Choke usb_txp0 usb_txn0 usb_rxp0 usb_rxn0 ESD1 ESD1 usb_txp0 usb_txn0 usb_rxp0 usb_rxn0 Figure 8-39. USB 3.0 Interface High Level Schematic PCB_USB1_1 NOTE ESD components should be on a PCB layer next to a system GND plane layer to achive the lowest inductance GND via. INTERFACE USB3 PHY Table 8-11. USB1 Component Reference DEVICE ESD1 ESD2 SUPPLIER TI TI Choke TDK / Murata C - PART NUMBER TPD2EUSB30DRT-Q1 TPD4S014-Q1 ACM2012H-900-2P-T001 (TDK), or DLW21SN121HQ2 or DLW21SN670HQ2 (Murata) 100nF 8.5.3.2 USB 3.0 General routing rules Some general routing guidelines regarding USB 3.0: • Avoid crossing splits reference planes. • Shorter trace length is preferred. • Minimize the via usage and layer transition • Keep large spacing between TX and RX pairs or route on different layers • Intra-lane delay mismatch between DP and DM less than 5ps Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 365 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com • Distance between common mode choke (CMF) and ESD protection device should be as short as possible • Distance between ESD protection device and USB connector should be as short as possible. Table 8-12 present routing specification for USB1 in the device. Table 8-12. USB1 Routing Specifications PARAMETER MIN device to USB3 connector trace length Number of stubs allowed on TX/RX traces TX/RX pair differential impedance 80 Number of vias on each TX/RX trace TYP MAX UNIT 7000 Mils 0 Stubs 90 100 Ω 2 3 Vias 8.5.4 HDMI Board Design and Layout Guidelines This section provides the timing specification for the HDMI interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to ensure the HDMI interface requirements are met. 8.5.4.1 HDMI Interface Schematic The HDMI bus is separated into three main sections (HDMI Ethernet and the optional Audio Return Channel are not specifically supported by this chip): 1. Transition Minimized Differential Signaling (TMDS) high speed digital video interface 2. Display Data Channel (I2C bus for configuration and status exchange between two devices) 3. Consumer Electronics Control (optional) for remote control of connected devices. The DDC and CEC are low speed interfaces, so nothing special is required for PCB layout of these signals. Their connection is shown in the below diagram. The TMDS channels are high speed differential pairs and therefore require the most care in layout. Specifications for TMDS layout are below. Figure 8-40 shows the HDMI interface schematic. ADVANCE INFORMATION 366 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Close to HDMI connector Micro-HDMI EARLY PRELIMINA ConnectorRY ADVANCE INFORMATION hdmi1_data2x hdmi1_data2y hdmi1_data1x hdmi1_data1y DEVICE hdmi1_clockx hdmi1_clocky hdmi1_data0x hdmi1_data0y Choke Choke Choke Choke ESD2 hdmi1_data2x hdmi1_data2y hdmi1_data1x hdmi1_data1y ESD2 hdmi1_clockx hdmi1_clocky hdmi1_data0x hdmi1_data0y hdmi1_cec hdmi1_hpd hdmi1_ddc_scl hdmi1_ddc_sda ESD1 hdmi1_cec hdmi1_hpd hdmi1_ddc_scl hdmi1_ddc_sda Figure 8-40. HDMI Interface High Level Schematic PCB_HDMI_1 INTERFACE HDMI Table 8-13. HDMI Component Reference DEVICE ESD1 ESD2 Choke SUPPLIER TI TI Murata PART NUMBER TPD5S115 TPD4E05U06RVZ DLW21SN900HQ2 8.5.4.2 TMDS Routing The TMDS signals are high speed differential pairs. Care must be taken in the PCB layout of these signals to ensure good signal integrity. The TMDS differential signal traces must be routed to achieve 100 Ohms (+/- 10%) differential impedance and 60 ohms (+/-10%) single ended impedance. Single ended impedance control is required because differential signals can’t be closely coupled on PCBs and therefore single ended impedance becomes important. These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as close to 60 ohms impedance traces as possible. For best accuracy, work with your PCB fabricator to ensure this impedance is met. In general, closely coupled differential signal traces are not an advantage on PCBs. When differential signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing variations affect impedance dramatically, so tight impedance control can be more problematic to maintain in production. Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing make obstacle avoidance easier, and trace width variations don’t affect impedance as much, therefore it’s easier to maintain accurate impedance over the length of the signal. The wider traces also show reduced skin effect and therefore often result in better signal integrity. Table 8-14 shows the routing specifications for the TMDS signals. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 367 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 8-14. TMDS Routing Specifications PARAMETER DSP to HDMI header trace length Number of stubs allowed on TMDS traces TX/RX pair differential impedance TX/RX single-ended impedance Number of vias on each TMDS trace TMDS differential pair to any other trace spacing (1) Vias must be used in pairs with the distance minimized. (2) DS = differential spacing of the SATA traces. MIN TYP 90 100 54 60 2×DS(2) MAX 7000 0 110 66 2 UNIT inches stubs Ω Ω Vias(1) 8.5.4.3 TPDS115 The TPD5S115 is an integrated HDMI companion chip solution. The device provides a regulated 5 V output (5VOUT) for sourcing the HDMI power line. The TPD5S115 exceeds the IEC61000-4-2 (Level 4) ESD protection level. 8.5.4.4 HDMI ESD Protection Device (Required) Interfaces that connect to a cable such as HDMI generally require more ESD protection than can be built into the processor’s outputs. Therefore this HDMI interface requires the use of an ESD protection chip to provide adequate ESD. When selecting an ESD protection chip, choose the lowest capacitance ESD protection available to minimize signal degradation. In no case should be ESD protection circuit capacitance be more than 5pF. TI manufactures these devices that provide ESD protection for HDMI signals such as the TPDxE05U06. For more information see the www.ti.com website. 8.5.4.5 PCB Stackup Specifications Table 8-15 shows the stackup and feature sizes required for HDMI. Table 8-15. HDMI PCB Stackup Specifications PARAMETER MIN TYP MAX UNIT PCB Routing/Plane Layers 4 6 - Layers Signal Routing Layers 2 3 - Layers Number of ground plane cuts allowed within HDMI routing region - - 0 Cuts Number of layers between HDMI routing region and reference ground plane - - 0 Layers PCB Trace width 4 Mils PCB BGA escape via pad size 18 Mils PCB BGA escape via hole size 10 Mils 8.5.4.6 Grounding Each TMDS channel has its own shield pin and they should be grounded to provide a return current path for the TMDS signal. 8.5.5 SATA Board Design and Layout Guidelines The device provides two SATA ports. This section provides the timing specification for the SATA interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to ensure the SATA interface requirements are met. 368 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 A standard 100 MHz differential clock source input to the xx pins must be used for SATA operation. 8.5.5.1 SATA Interface Schematic Figure 8-41 shows the data portion of the SATA interface schematic. EARLY PRELIMINARY ADVANCE INFORMATION DEVICE SATA Interface sata1_rxn0 C sata1_rxp0 C sata1_txn0l C sata1_txp0 C SATA Connector PCB_SATA_1 Figure 8-41. SATA Interface High Level Schematic NOTE AC coupling capacitors (C) are required on the receive data pair. Table 8-16 shows the requirements for these capacitors. Table 8-16. SATA AC Coupling Capacitors Requirements PARAMETER MIN TYP MAX UNIT PCIe AC coupling capacitor value TBD 100 TBD nF PCIe AC coupling capacitor package size 0402 0603 EIA(1)(2) (1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor. (2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side. 8.5.5.2 Compatible SATA Components and Modes Table x-1 shows the compatible SATA components and supported modes. Note that the only supported configuration is an internal cable from the processor host to the SATA device. Table 8-17. SATA AC Coupling Capacitors Requirements PARAMETER Transfer Rates eSATA xSATA Backplane Internal Cable MIN MAX UNIT SUPPORTED 1.5 3 Gbps - - - YES - - - NO - - - NO - - - YES 8.5.5.3 PCB Stackup Specifications Table 8-18 shows the stackup and feature sizes required for these types of SATA connections. Table 8-18. SATA AC Coupling Capacitors Requirements PARAMETER MIN TYP MAX UNIT PCB Routing/Plane Layers 4 6 - Layers Signal Routing Layers 2 3 - Layers Number of ground plane cuts allowed within SATA routing region - - 0 Cuts Number of layers between SATA routing area and reference plane - - 0 Layers Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 369 DRA75x, DRA74x TI Confidential — NDA Restrictions EARLY PRELIMINARY ADVANCE INFORMATION SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 8-18. SATA AC Coupling Capacitors Requirements (continued) PARAMETER PCB Routing clearance PCB Trace width PCB BGA escape via pad size PCB BGA escape via hole size DSP Device BGA pad size (1)(2) (1) Non-solder mask defined pad (2) Per IPC-7351A BGA pad size guideline MIN TYP MAX 4 4 20 10 0.4 UNIT Mils Mils Mils Mils mm 8.5.5.4 Routing Specifications The SATA data signal traces must be routed to achieve 100 Ohms (+/-20%) differential impedance and 60 ohms (+/-15%) single ended impedance. The signal ended impedance is required because differential signals can’t be closely coupled on PCBs and therefore single ended impedance becomes important. 60 ohms is chosen for the single ended impedance to minimize problems caused by too low an impedance. These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as close to 100 ohms differential and 60 ohms single ended impedance traces as possible. For best accuracy, work with your PCB fabricator to ensure this impedance is met. Table 8-19 shows the routing specifications for the SATA data signals. Table 8-19. SATA Routing Specifications PARAMETER PCIe signal trace length Number of stubs allowed on PCIe traces(2) TX/RX pair differential impedance TX/RX single-ended impedance Number of vias on each SATA trace SATA differential pair to any other trace spacing (1) Beyond this, signal integrity may suffer. (2) Inline pads may be used for probing. (3) Vias must be used in pairs with the distance minimized. (4) DS = differential spacing of the SATA traces. MIN TYP 80 100 51 60 2×DS(4) MAX 10(1) 0 120 69 3 UNIT inches stubs Ω Ω Vias(3) 8.5.6 PCIe Board Design and Layout Guidelines The PCIe interface on the device provides support for a 5.0 Gbps lane with polarity inversion. A standard 100 MHz PCIe differential clock source must be used for PCIe operation. 8.5.6.1 PCIe Connections and Interface Compliance The PCIe interface on the device is compliant with the PCIe revision 2.0 specification. Please refer to the PCIe specifications for all connections that are described in it. Those recommendations are more descriptive and exhaustive than what is possible here. The use of PCIe compatible bridges and switches is allowed for interfacing with more than one other processor or PCIe device. 8.5.6.1.1 Coupling Capacitors AC coupling capacitors are required on the transmit data pair. Table 8-20 shows the requirements for these capacitors. 370 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated TI Confidential — NDA Restrictions DRA75x, DRA74x EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 8-20. PCIe AC Coupling Capacitors Requirements PARAMETER MIN TYP MAX UNIT PCIe AC coupling capacitor value TBD 100 TBD nF PCIe AC coupling capacitor package size 0402 0603 EIA(1)(2) (1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor. (2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side. 8.5.6.1.2 Polarity Inversion The PCIe specification requires polarity inversion support. This means for layout purposes, polarity is unimportant since each signal can change its polarity on die inside the chip. This means polarity within a lane is unimportant for layout. 8.5.6.2 Non-standard PCIe connections The following sections contain suggestions for any PCIe connection that is NOT described in the official PCIe specification, such as an on-board Device to Device or Device to other PCIe compliant processor connection. 8.5.6.2.1 PCB Stackup Specifications Table 8-21 shows the stackup and feature sizes required for these types of PCIe connections. Table 8-21. PCIe AC Coupling Capacitors Requirements PARAMETER MIN TYP PCB Routing/Plane Layers 4 6 Signal Routing Layers 2 3 Number of ground plane cuts allowed within PCIe routing region - - Number of layers between PCIe routing area and reference plane (1) - - PCB Routing clearance 4 PCB Trace width (4) 4 PCB BGA escape via pad size 20 PCB BGA escape via hole size 10 DSP Device BGA pad size (2)(3) 0.4 (1) A reference plane may be a ground plane or the power plane referencing the PCIe signals.. (2) Non-solder mask defined pad (3) Per IPC-7351A BGA pad size guideline (4) In breakout area MAX 0 0 UNIT Layers Layers Cuts Layers Mils Mils Mils Mils mm 8.5.6.2.2 Routing Specifications 8.5.6.2.2.1 Impedance The PCIe data signal traces must be routed to achieve 100-Ω (±20%) differential impedance and 60-Ω (±15%) single-ended impedance. The single-ended impedance is required because differential signals are extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important. These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0 document, available from PCI-SIG (www.pcisig.com). These impedances are impacted by trace width, trace spacing, distance between signals and referencing planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal pairs result in as close to 100-Ω differential impedance and 60-Ω single-ended impedance as possible. For best accuracy, work with your PCB fabricator to ensure this impedance is met. See Table 8-22 below. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 371 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 8.5.6.2.2.2 Differential Coupling In general, closely coupled differential signal traces are not an advantage on PCBs. When differential signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing variations affect impedance dramatically, so tight impedance control can be more problematic to maintain in production. For PCBs with very tight space limitations (which are usually small) this can work, but for most PCBs, the loosely coupled option is probably best. Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing make obstacle avoidance easier (since each trace is not so fixed in position relative to the other), and trace width variations don’t affect impedance as much, therefore it’s easier to maintain an accurate impedance over the length of the signal. For longer routes, the wider traces also show reduced skin effect and therefore often result in better signal integrity with a larger eye diagram opening. Table 8-22 shows the routing specifications for the PCIe data signals. Table 8-22. PCI-E Routing Specifications PARAMETER PCIe signal trace length Differential pair trace matching Number of stubs allowed on PCIe traces(3) TX/RX pair differential impedance TX/RX single-ended impedance Pad size of vias on PCIe trace Hole size of vias on PCIe trace Number of vias on each PCIe trace PCIe differential pair to any other trace spacing (1) Beyond this, signal integrity may suffer. (2) For example, RXP0 within 5 Mils of RXN0. (3) Inline pads may be used for probing. (4) 35-Mil antipad maximum recommended. (5) Vias must be used in pairs with the distance minimized. (6) DS = differential spacing of the PCIe traces. MIN TYP 80 100 51 60 2×DS(6) MAX 10(1) 5(2) 0 120 69 25(4) 14 3 UNIT inches Mils stubs Ω Ω Mils Mils Vias(5) 8.5.6.2.2.3 Pair Length Matching Each signal in the differential pair should be matched to within 5 mils of its matching differential signal. Length matching should be done as close to the mismatch as possible. 8.6 Clock Routing Guidelines 8.6.1 32-kHz Oscillator Routing When designing the printed-circuit board: • Keep the crystal as close as possible to the crystal pins X1 and X2. • Keep the trace lengths short and small to reduce capacitor loading and prevent unwanted noise pickup. • Place a guard ring around the crystal and tie the ring to ground to help isolate the crystal from unwanted noise pickup. • Keep all signals out from beneath the crystal and the X1 and X2 pins to prevent noise coupling. 372 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated ADVANCE INFORMATION Crystal EARLY PRELIMINARY TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 • Finally, an additional local ground plane on an adjacent PCB layer can be added under the crystal to shield it from unwanted pickup from traces on other layers of the board. This plane must be isolated from the regular PCB ground plane and tied to the GND pin of the RTC. The plane must not be any larger than the perimeter of the guard ring. Make sure that this ground plane does not contribute to significant capacitance (a few pF) between the signal line and ground on the connections that run from X1 and X2 to the crystal. IC Cap X Via to GND 1 X 2 Cap Local ground plane SWPS040-196 Figure 8-42. Slow Clock PCB Requirements 8.6.2 Oscillator Ground Connection Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in the ground plane causes a voltage drop in the ground. Figure 8-43 shows the grounding scheme for slow (low frequency) clock generated from the internal oscillator. Device rtc_osc_xi_clkin32 rtc_osc_xo Crystal Rd (Optional) Cf1 Cf2 SPRS85v_PCB_CLK_OSC_2 Figure 8-43. Grounding Scheme for Low-Frequency Clock Figure 8-44 shows the grounding scheme for high-frequency clock. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 373 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Device xi_oscj xo_oscj vssa_oscj Crystal Rd (Optional) (1) j in *_osc = 0 or 1 Cf1 Cf2 SPRS85v_PCB_CLK_OSC_3 Figure 8-44. Grounding Scheme for High-Frequency Clock 8.7 DDR2/DDR3 Board Design and Layout Guidelines 8.7.1 DDR2/DDR3 General Board Layout Guidelines To help ensure good signaling performance, consider the following board design guidelines: • Avoid crossing splits in the power plane. • Minimize Vref noise. • Use the widest trace that is practical between decoupling capacitors and memory module. • Maintain a single reference (either ground or Vdd). • Minimize ISI by keeping impedances matched. • Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities. • Utilize proper low-pass filtering on the Vref pins. • Keep the stub length as short as possible. • Add additional spacing for on-clock and strobe nets to eliminate crosstalk. • Maintain a common ground reference for all bypass and decoupling capacitors. • Take into account the differences in propagation delays between microstrip and stripline nets when evaluating timing constraints. 8.7.2 DDR3 Board Design and Layout Guidelines 8.7.2.1 Board Designs TI only supports board designs utilizing DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-23 and Figure 8-45. Table 8-23. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller NO. 1 tc(DDR_CLK) PARAMETER Cycle time, DDR_CLK -1G MIN 1.875 MAX 2.5(1) UNIT ns 374 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 (1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and operating frequency (see the DDR3 memory device data sheet). 1 DDR_CLK Figure 8-45. DDR3 Memory Controller Clock Timing 8.7.2.1.1 DDR3 versus DDR2 This specification only covers device PCB designs that utilize DDR3 memory. Designs using DDR2 memory should use the PCB design specifications for DDR2 memory . While similar, the two memory systems have different requirements. It is currently not possible to design one PCB that covers both DDR2 and DDR3. 8.7.2.2 DDR3 EMIFs The processor contains two separate DDR3 EMIFs. This specification covers one of these EMIFs (DDR[0]) and, thus, needs to be implemented twice, once for each EMIF. The PCB layout generally turns out to be a semi-mirror with DDR[1] being a flipped version of DDR[0]; the only exception being the DDR3 devices themselves are not flipped unless mounted on opposite sides of the PCB. Requirements are identical between the two EMIFs. 8.7.2.3 DDR3 Device Combinations Since there are several possible combinations of device counts and single- or dual-side mounting, Table 8-24 summarizes the supported device configurations. Table 8-24. Supported DDR3 Device Combinations(1) NUMBER OF DDR3 DEVICES DDR3 DEVICE WIDTH (BITS) MIRRORED? DDR3 EMIF WIDTH (BITS) 1 16 N 16 2 8 Y(2) 16 2 16 N 32 2 16 Y(2) 32 3 16 N 32 4 8 N 32 4 8 Y(3) 32 5 8 N 32 (1) This table is per EMIF. (2) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of the board. (3) This is two mirrored pairs of DDR3 devices. 8.7.2.4 DDR3 Interface Schematic 8.7.2.4.1 32-Bit DDR3 Interface The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR devices look like two 8-bit devices. Figure 8-46 and Figure 8-47 show the schematic connections for 32-bit interfaces using x16 devices. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 375 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 8.7.2.4.2 16-Bit DDR3 Interface Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-46 and Figure 8-47); only the high-word DDR memories are removed and the unused DQS inputs are tied off. The processor DDR[x]_DQS[2] and DDR[x]_DQS[3] pins should be pulled to the DDR supply via 1-kΩ resistors. Similarly, the DDR[x]_DQS[2] and DDR[x]_DQS[3] pins should be pulled to ground via 1-kΩ resistors. When not using a DDR interface, the proper method of handling the unused pins is to tie off the DDR[x]_DQS[n] pins to the corresponding DVDD_DDR[x] supply via a 1-kΩ resistor and pulling the DDR[x]_DQS[n] pins to ground via a 1k-Ω resistor. This needs to be done for each byte not used. Although these signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection against external electrical noise causing activity on the signals. ADVANCE INFORMATION 376 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com 32-bit DDR3 EMIF TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 DDR[x]_ODT[1] NC DDR[x]_CS[1] NC DDR[x]_D[31] 8 DDR[x]_D[24] DDR[x]_DQM[3] DDR[x]_DQS[3] DDR[x]_DQS[3] DDR[x]_D[23] 8 DDR[x]_D[16] DDR[x]_DQM[2] DDR[x]_DQS[2] DDR[x]_DQS[2] DDR[x]_D[15] 8 DDR[x]_D[8] DDR[x]_DQM[1] DDR[x]_DQS[1] DDR[x]_DQS[1] DDR[x]_D[7] 8 DDR[x]_D[0] DDR[x]_DQM[0] DDR[x]_DQS[0] DDR[x]_DQS[0] DDR[x]_CLK DDR[x]_CLK DDR[x]_ODT[0] DDR[x]_CS[0] DDR[x]_BA[0] DDR[x]_BA[1] DDR[x]_BA[2] DDR[x]_A[0] 15 DDR[x]_A[14] DDR[x]_CAS DDR[x]_RAS DDR[x]_WE DDR[x]_CKE DDR[x]_RST VREFSSTL_DDR[x] 0.1 µF 16-Bit DDR3 Devices DQ15 DQ8 UDM UDQS UDQS DQ7 DQ15 D08 LDM LDQS LDQS DQ8 UDM UDQS UDQS DQ7 DQ0 LDM LDQS LDQS CK CK ODT CS BA0 BA1 BA2 A0 CK CK ODT CS BA0 BA1 BA2 A0 A14 CAS RAS WE CKE RST ZQ ZQ VREFDQ VREFCA 0.1 µF A14 CAS RAS WE CKE RST ZQ VREFDQ VREFCA 0.1 µF Zo 0.1 µF DDR_1V5 Zo DDR_VTT Zo Zo DDR_VREF ZQ Zo Termination is required. See terminator comments. ZQ Value determined according to the DDR memory device data sheet. Figure 8-46. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 377 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 32-bit DDR3 EMIF www.ti.com DDR[x]_ODT[1] NC DDR[x]_CS[1] NC DDR[x]_D[31] 8 DDR[x]_D[24] DDR[x]_DQM[3] DDR[x]_DQS[3] DDR[x]_DQS[3] DDR[x]_D[23] 8 DDR[x]_D[16] DDR[x]_DQM[2] DDR[x]_DQS[2] DDR[x]_DQS[2] DDR[x]_D[15] 8 DDR[x]_D[8] DDR[x]_DQM[1] DDR[x]_DQS[1] DDR[x]_DQS[1] DDR[x]_D[7] 8 DDR[x]_D[0] DDR[x]_DQM[0] DDR[x]_DQS[0] DDR[x]_DQS[0] DDR[x]_CLK DDR[x]_CLK DDR[x]_ODT[0] DDR[x]_CS[0] DDR[x]_BA[0] DDR[x]_BA[1] DDR[x]_BA[2] DDR[x]_A[0] 15 DDR[x]_A[14] DDR[x]_CAS DDR[x]_RAS DDR[x]_WE DDR[x]_CKE DDR[x]_RST VREFSSTL_DDR[x] 0.1 µF 8-Bit DDR3 Devices DQ7 DQ7 DQ0 DM/TQS NC TDQS DQS DQS DQ0 DM/TQS NC TDQS DQS DQS CK CK ODT CS BA0 BA1 BA2 A0 CK CK ODT CS BA0 BA1 BA2 A0 A14 CAS RAS WE CKE RST ZQ ZQ VREFDQ VREFCA 0.1 µF A14 CAS RAS WE CKE RST ZQ VREFDQ ZQ VREFCA 0.1 µF 8-Bit DDR3 Devices DQ7 DQ7 DQ0 DM/TQS NC TDQS DQS DQS DQ0 DM/TQS NC TDQS DQS DQS CK CK ODT CS BA0 BA1 BA2 A0 A14 CAS RAS WE CKE RST ZQ ZQ VREFDQ VREFCA 0.1 µF CK CK ODT CS BA0 BA1 BA2 A0 A14 CAS RAS WE CKE RST ZQ VREFDQ VREFCA 0.1 µF Zo 0.1 µF DDR_1V5 Zo DDR_VTT Zo Zo DDR_VREF ZQ Zo Termination is required. See terminator comments. ZQ Value determined according to the DDR memory device data sheet. Figure 8-47. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices 378 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 8.7.2.5 Compatible JEDEC DDR3 Devices Table 8-25 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface. Generally, the DDR3 interface is compatible with DDR3-1066 devices in the x8 or x16 widths. Table 8-25. Compatible JEDEC DDR3 Devices (Per Interface) N PARAMETER CONDITION O. MIN MAX UNIT 1 JEDEC DDR3 device speed grade(1) DDR clock rate = 400MHz DDR3-800 DDR3-1600 400MHz< DDR clock rate ≤ 533MHz DDR3-1066 DDR3-1600 2 JEDEC DDR3 device bit width x8 x16 Bits 3 JEDEC DDR3 device count(2) 2 4 Devices (1) Refer to Table 8-23 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of supported DDR clock rates. (2) For valid DDR3 device configurations and device counts, see Section 8.7.2.4, Figure 8-46, and Figure 8-47. 8.7.2.6 PCB Stackup The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in Table 8-26. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in Table 8-27. LAYER 1 2 3 4 5 6 Table 8-26. Six-Layer PCB Stackup Suggestion TYPE Signal Plane Plane Plane Plane Signal DESCRIPTION Top routing mostly vertical Ground Split power plane Split power plane or Internal routing Ground Bottom routing mostly horizontal Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 379 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 8-27. PCB Stackup Specifications NO. PARAMETER MIN TYP MAX UNIT PS1 PCB routing/plane layers 6 PS2 Signal routing layers 3 PS3 Full ground reference layers under DDR3 routing region(1) 1 PS4 Full 1.5-V power reference layers under the DDR3 routing region(1) 1 PS5 Number of reference plane cuts allowed within DDR routing region(2) 0 PS6 Number of layers between DDR3 routing layer and reference plane(3) 0 PS7 PCB routing feature size 4 Mils PS8 PCB trace width, w 4 Mils PS9 Single-ended impedance, Zo 50 75 Ω PS10 Impedance control(5) Z-5 Z Z+5 Ω (1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer return current as the trace routes switch routing layers. (2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and EMI radiation. (3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop. (4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available for power routing. An 18-mil pad is required for minimum layer count escape. (5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9. 8.7.2.7 Placement Figure 8-48 shows the required placement for the processor as well as the DDR3 devices. The dimensions for this figure are defined in Table 8-28. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3 devices are omitted from the placement. ADVANCE INFORMATION 380 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 x3 EARLY PRELIMINARY ADVANCE INFORMATION x2 x1 y2 y1 y2 DDR3 Controller y2 y2 y2 PCB_DDR3_3 Figure 8-48. Placement Specifications Table 8-28. Placement Specifications PARAMET MIN ER X1 X2 X3 Y1 Y2 MAX 500 600 600 1800 600 UNIT Mils Mils Mils Mils Mils 8.7.2.8 DDR3 Keepout Region The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout region is defined for this purpose and is shown in Figure 8-49. The size of this region varies with the placement and DDR routing. Additional clearances required for the keepout region are shown in Table 828. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region. Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the two signals from the DDR3 controller should be separated from each other by the specification in Table 828, item 5. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 381 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com DDR3 Keepout Region DDR3 Controller Figure 8-49. DDR3 Keepout Region PCB_DDR3_4 8.7.2.9 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. Table 8-29 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk bypass capacitance may be needed for other circuitry. ADVANCE INFORMATION 382 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Table 8-29. Bulk Bypass Capacitors NO. PARAMETER MIN MAX UNIT 1 DDR_1V5 bulk bypass capacitor count(1) 6 Devices 2 DDR_1V5 bulk bypass total capacitance 140 μF (1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the highspeed (HS) bypass capacitors and DDR3 signal routing. 8.7.2.10 High-Speed Bypass Capacitors High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power, and processor/DDR ground connections. Table 8-30 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to: 1. Fit as many HS bypass capacitors as possible. 2. Minimize the distance from the bypass cap to the pins/balls being bypassed. 3. Use the smallest physical sized capacitors possible with the highest capacitance readily available. 4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest hole size via possible. 5. Minimize via sharing. Note the limites on via sharing shown in Table 8-30. Table 8-30. High-Speed Bypass Capacitors NO. PARAMETER MIN TYP MAX UNIT 1 HS bypass capacitor package size(1) 0201 0402 10 Mils 2 Distance, HS bypass capacitor to processor being bypassed(2)(3)(4) 400 Mils 3 processor DDR_1V5 HS bypass capacitor count 70 Devices 4 processor DDR_1V5 HS bypass capacitor total capacitance 5 μF 5 Number of connection vias for each device power/ground ball(5) Vias 6 Trace length from device power/ground ball to connection via(2) 35 70 Mils 7 Distance, HS bypass capacitor to DDR device being bypassed(6) 150 Mils 8 DDR3 device HS bypass capacitor count(7) 12 Devices 9 DDR3 device HS bypass capacitor total capacitance(7) 0.85 μF 10 Number of connection vias for each HS capacitor(8)(9) 2 Vias 11 Trace length from bypass capacitor connect to connection via(2)(9) 35 100 Mils 12 Number of connection vias for each DDR3 device power/ground ball(10) 1 Vias 13 Trace length from DDR3 device power/ground ball to connection via(2)(8) 35 60 Mils (1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor. (2) Closer/shorter is better. (3) Measured from the nearest processor power/ground ball to the center of the capacitor package. (4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls, between the DDR interfaces on the package. (5) See the Via Channel™ escape for the processor package. (6) Measured from the DDR3 device power/ground ball to the center of the capacitor package. (7) Per DDR3 device. (8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board. (9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils. (10) Up to a total of two pairs of DDR power/ground balls may share a via. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 383 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com 8.7.2.10.1 Return Current Bypass Capacitors Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals hopping from one signal layer to another. The bypass capacitor here provides a path for the return current to hop planes along with the signal. As many of these return current bypass capacitors should be used as possible. Since these are returns for signal current, the signal via size may be used for these capacitors. 8.7.2.11 Net Classes Table 8-31 lists the clock net classes for the DDR3 interface. Table 8-32 lists the signal net classes, and associated clock net classes, for signals in the DDR3 interface. These net classes are used for the termination and routing rules that follow. Table 8-31. Clock Net Class Definitions CLOCK NET CLASS processor PIN NAMES CK DDR[x]_CLK/DDR[x]_CLK DQS0 DDR[x]_DQS[0]/DDR[x]_DQS[0] DQS1 DDR[x]_DQS[1]/DDR[x]_DQS[1] DQS2(1) DDR[x]_DQS[2]/DDR[x]_DQS[2] DQS3(1) DDR[x]_DQS[3]/DDR[x]_DQS[3] (1) Only used on 32-bit wide DDR3 memory systems. Table 8-32. Signal Net Class Definitions CLOCK NET CLASS ADDR_CTRL ASSOCIATED CLOCK NET CLASS CK DQ0 DQS0 DQ1 DQS1 DQ2(1) DQS2 DQ3(1) DQS3 (1) Only used on 32-bit wide DDR3 memory systems. processor PIN NAMES DDR[x]_BA[2:0], DDR[x]_A[14:0], DDR[x]_CS[x], DDR[x]_CAS, DDR[x]_RAS, DDR[x]_WE, DDR[x]_CKE, DDR[x]_ODT[x] DDR[x]_D[7:0], DDR[x]_DQM[0] DDR[x]_D[15:8], DDR[x]_DQM[1] DDR[x]_D[23:16], DDR[x]_DQM[2] DDR[x]_D[31:24], DDR[x]_DQM[3] 8.7.2.12 DDR3 Signal Termination Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in the routing rules in the following sections. 8.7.2.13 VREFSSTL_DDR Routing VREFSSTL_DDR (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the DDR3 1.5-V and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing congestion. 8.7.2.14 VTT Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is expected to source and sink current, specifically the termination current for the ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power sub-plane. VTT should be bypassed near the terminator resistors. 384 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated ADVANCE INFORMATION AS+ EARLY PRELIMINARY AS- TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 8.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew between them. CK is a bit more complicated because it runs at a higher transition rate and is differential. The following subsections show the topology and routing for various DDR3 configurations for CK and ADDR_CTRL. The figures in the following subsections define the terms for the routing specification detailed in Table 8-33. 8.7.2.15.1 Four DDR3 Devices Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB. 8.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices Figure 8-50 shows the topology of the CK net classes and Figure 8-51 shows the topology for the corresponding ADDR_CTRL net classes. DDR Differential CK Input Buffers +– +– +– +– AS- AS+ AS- AS+ AS- AS+ Processor + Differential Clock Output Buffer – Clock Parallel Terminator Rcp DDR_1V5 A1 A2 A3 A4 A3 AT Cac Rcp 0.1 µF A1 A2 A3 A4 A3 AT Routed as Differential Pair Figure 8-50. CK Topology for Four x8 DDR3 Devices DDR Address and Control Input Buffers AS AS AS AS Processor Address and Control Output Buffer A1 A2 A3 A4 A3 Figure 8-51. ADDR_CTRL Topology for Four x8 DDR3 Devices Address and Control Terminator Rtt AT Vtt 8.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices Figure 8-52 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-53 shows the corresponding ADDR_CTRL routing. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 385 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com A1 NARY A1 AS+ AS- DDR_1V5 Rcp Cac A2 A3 A4 A3 AT A2 A3 A4 A3 AT Rcp 0.1 µF = Figure 8-52. CK Routing for Four Single-Side DDR3 Devices A1 EARLY PRELIMI AS ADVANCE INFORMATION Rtt A2 A3 A4 A3 AT Vtt = Figure 8-53. ADDR_CTRL Routing for Four Single-Side DDR3 Devices To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of increased routing and assembly complexity. Figure 8-54 and Figure 8-55 show the routing for CK and ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration. 386 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 A1 NARY A1 AS+ AS- DDR_1V5 Rcp Cac A2 A3 A4 A3 AT A2 A3 A4 A3 AT Rcp 0.1 µF = Figure 8-54. CK Routing for Four Mirrored DDR3 Devices ADVANCE INFORMATION A1 EARLY PRELIMI AS Rtt A2 A3 A4 A3 AT Vtt = Figure 8-55. ADDR_CTRL Routing for Four Mirrored DDR3 Devices 8.7.2.15.2 Two DDR3 Devices Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB. 8.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices Figure 8-56 shows the topology of the CK net classes and Figure 8-57 shows the topology for the corresponding ADDR_CTRL net classes. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 387 AS+ EARLY PRELIMINARY AS- DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 DDR Differential CK Input Buffers www.ti.com +– +– AS- AS+ Processor + Differential Clock Output Buffer – Clock Parallel Terminator Rcp DDR_1V5 A1 A2 A3 AT Cac Rcp 0.1 µF A1 A2 A3 AT Routed as Differential Pair Figure 8-56. CK Topology for Two DDR3 Devices DDR Address and Control Input Buffers AS AS Processor Address and Control Output Buffer Address and Control Terminator Rtt A1 A2 A3 AT Vtt Figure 8-57. ADDR_CTRL Topology for Two DDR3 Devices 8.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices Figure 8-58 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-59 shows the corresponding ADDR_CTRL routing. ADVANCE INFORMATION 388 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 A1 NARY A1 AS+ AS- DDR_1V5 A2 A3 A2 A3 = Rcp AT AT Rcp Cac 0.1 µF Figure 8-58. CK Routing for Two Single-Side DDR3 Devices ADVANCE INFORMATION A1 EARLY PRELIMI AS Rtt A2 A3 AT Vtt = Figure 8-59. ADDR_CTRL Routing for Two Single-Side DDR3 Devices To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. Figure 8-60 and Figure 8-61 show the routing for CK and ADDR_CTRL, respectively, for two DDR3 devices mirrored in a single-pair configuration. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 389 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com A1 NARY A1 AS+ AS- DDR_1V5 Rcp Cac A2 A3 AT A2 A3 AT Rcp 0.1 µF = Figure 8-60. CK Routing for Two Mirrored DDR3 Devices A1 EARLY PRELIMI AS ADVANCE INFORMATION Rtt A2 A3 AT Vtt = Figure 8-61. ADDR_CTRL Routing for Two Mirrored DDR3 Devices 8.7.2.15.3 One DDR3 Device A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as one bank (CS), 16 bits wide. 8.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device Figure 8-62 shows the topology of the CK net classes and Figure 8-63 shows the topology for the corresponding ADDR_CTRL net classes. 390 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated AS+ PRELIMINARY ASAS www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 DDR Differential CK Input Buffer +– Processor + Differential Clock Output Buffer – Clock Parallel Terminator Rcp DDR_1V5 A1 A2 AT Cac Rcp 0.1 µF A1 A2 AT Routed as Differential Pair Figure 8-62. CK Topology for One DDR3 Device DDR Address and Control Input Buffers Processor Address and Control Output Buffer Address and Control Terminator Rtt A1 A2 AT Vtt Figure 8-63. ADDR_CTRL Topology for One DDR3 Device 8.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device Figure 8-64 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-65 shows the corresponding ADDR_CTRL routing. ADVANCE INFORMATION EARLY Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 391 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com A1 NARY A1 AS+ AS- DDR_1V5 Rcp Cac A2 AT A2 AT Rcp 0.1 µF = Figure 8-64. CK Routing for One DDR3 Device A1 EARLY PRELIMI AS ADVANCE INFORMATION Rtt A2 AT Vtt = Figure 8-65. ADDR_CTRL Routing for One DDR3 Device 8.7.2.16 Data Topologies and Routing Definition No matter the number of DDR3 devices used, the data line topology is always point to point, so its definition is simple. Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure there are nearby ground vias to allow the return currents to transition between reference planes if both reference planes are ground or DVDD_DDR. Ensure there are nearby bypass capacitors to allow the return currents to transition between reference planes if one of the reference planes is ground. The goal is to minimize the size of the return current loops. 8.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-66 and Figure 8-67 show these topologies. 392 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Processor DQS IO Buffer DQSn+ DQSn- Routed Differentially n = 0, 1, 2, 3 Figure 8-66. DQS Topology DDR DQS IO Buffer Processor DQ and DM Dn IO Buffer n = 0, 1, 2, 3 Figure 8-67. DQ/DM Topology DDR DQ and DM IO Buffer 8.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices Figure 8-68 and Figure 8-69 show the DQS and DQ/DM routing. DQSn+ DQSn- Routed Differentially DQS n = 0, 1, 2, 3 Figure 8-68. DQS Routing With Any Number of Allowed DDR3 Devices Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 393 EARLY PRELIMINARY DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 DQ and DM Dn www.ti.com n = 0, 1, 2, 3 Figure 8-69. DQ/DM Routing With Any Number of Allowed DDR3 Devices 8.7.2.17 Routing Specification 8.7.2.17.1 CK and ADDR_CTRL Routing Specification Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. A metric to establish this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the length between the points when connecting them only with horizontal or vertical segments. A reasonable trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address Control Longest Manhattan distance. Given the clock and address pin locations on the processor and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 8-70 and Figure 8-71 show this distance for four loads and two loads, respectively. It is from this distance that the specifications on the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specifications are contained in Table 8-33. ADVANCE INFORMATION 394 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated ADVANCE INFORMATION A1 PRELIM AISNARY www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 A8(A) CACLMX CACLMY A8(A) A8(A) A8(A) A8(A) Rtt A2 A3 A4 A3 AT Vtt = A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control. The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this length calculation. Non-included lengths are grayed out in the figure. Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils. The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8. Figure 8-70. CACLM for Four Address Loads on One Side of PCB EARLY A1 AS A8(A) CACLMX CACLMY A8(A) A8(A) Rtt A2 A3 AT Vtt = A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control. The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this length calculation. Non-included lengths are grayed out in the figure. Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils. The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8. Figure 8-71. CACLM for Two Address Loads on One Side of PCB Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 395 EARLY PRELIMINARY ADVANCE INFORMATION DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com Table 8-33. CK and ADDR_CTRL Routing Specification(1)(2) NO. PARAMETER MIN TYP MAX UNIT 1 A1+A2 length 2500 mils 2 A1+A2 skew 25 mils 3 A3 length 660 mils 4 A3 skew(3) 25 mils 5 A3 skew(4) 125 mils 6 A4 length 660 mils 7 A4 skew 25 mils 8 AS length 100 mils 9 AS skew 100 mils 10 AS+/AS- length 70 mils 11 AS+/AS- skew 5 mils 12 AT length(5) 500 mils 13 AT skew(6) 100 mils 14 AT skew(7) 5 mils 15 CK/ADDR_CTRL nominal trace length(8) CACLM-50 CACLM CACLM+50 mils 16 Center-to-center CK to other DDR3 trace spacing(9) 4w 17 Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10) 4w 18 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(9) 3w 19 CK center-to-center spacing(11) 20 CK spacing to other net(9) 4w 21 Rcp(13) Zo-1 Zo Zo+1 Ω 22 Rtt(13)(14) Zo-5 Zo Zo+5 Ω (1) The use of vias should be minimized. (2) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump between the DDR_1V5 plane and the ground plane when the net class switches layers at a via. (3) Non-mirrored configuration (all DDR3 memories on same side of PCB). (4) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom). (5) While this length can be increased for convenience, its length should be minimized. (6) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required. (7) CK net class only. (8) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 8.7.2.17.1, Figure 8- 70, and Figure 8-71. (9) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length. (10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing. (11) CK spacing set to ensure proper differential impedance. (12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo. (13) Source termination (series resistor at driver) is specifically not allowed. (14) Termination values should be uniform across the net class. 8.7.2.17.2 DQS and DQ Routing Specification Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL, a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1. 396 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated www.ti.com TI Confidential — NDA Restrictions DRA75x, DRA74x SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 NOTE It is not required, nor is it recommended, to match the lengths across all bytes. Length matching is only required within each byte. Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 8-72 shows this distance for four loads. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-34. EARLY PRELIMINARY ADVANCE INFORMATION DQLMY3 DQLMY2 DQLMX0 DB0 DQ[0:7]/DM0/DQS0 DB1 DQ[8:15]/DM1/DQS1 DQLMX1 DB2 DQ[16:23]/DM2/DQS2 DQLMX2 DB3 DQ[23:31]/DM3/DQS3 DQLMY1 DQLMX3 DQLMY0 3 2 1 0 DB0 - DB3 represent data bytes 0 - 3. There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the byte; therefore: DQLM0 = DQLMX0 + DQLMY0 DQLM1 = DQLMX1 + DQLMY1 DQLM2 = DQLMX2 + DQLMY2 DQLM3 = DQLMX3 + DQLMY3 Figure 8-72. DQLM for Any Number of Allowed DDR3 Devices Table 8-34. Data Routing Specification(1) NO. PARAMETER MIN TYP MAX 1 DB0 nominal length(2)(3) DQLM0 2 DB1 nominal length(2)(4) DQLM1 3 DB2 nominal length(2)(5) DQLM2 4 DB3 nominal length(2)(6) DQLM3 5 DBn skew(7) 25 6 DQSn+ to DQSn- skew 5 7 DQSn to DBn skew(7)(8) 25 8 Center-to-center DBn to other DDR3 trace spacing(10) 4 9 Center-to-center DBn to other DBn trace spacing(11) 3 10 DQSn center-to-center spacing(12) 11 DQSn center-to-center spacing to other net 4 (1) External termination disallowed. Data termination should use built-in ODT functionality. (2) DQLMn is the longest Manhattan distance of a byte. r definition, see Section 8.7.2.17.2 and Figure 8-72. (3) DQLM0 is the longest Manhattan length for the net classes of Byte 0. (4) DQLM1 is the longest Manhattan length for the net classes of Byte 1. (5) DQLM2 is the longest Manhattan length for the net classes of Byte 2. (6) DQLM3 is the longest Manhattan length for the net classes of Byte 3. (7) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended. UNIT mils mils mils mils mils mils mils w(9) w(9) w(9) Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 397 DRA75x, DRA74x TI Confidential — NDA Restrictions SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 www.ti.com (8) Each DQS pair is length matched to its associated byte. (9) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length. (10) Other DDR3 trace spacing means other DDR3 net classes not within the byte. (11) This applies to spacing within the net classes of a byte. (12) DQS pair spacing is set to ensure proper differential impedance. (13) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo. EARLY PRELIMINARY ADVANCE INFORMATION 398 PCB Guidelines Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EARLY PRELIMINARY ADVANCE INFORMATION TI Confidential — NDA Restrictions DRA75x, DRA74x www.ti.com SPRS857G – DECEMBER 2012 – REVISED NOVEMBER 2013 Revision History The following table summarizes the device Data Manual versions. Version Literature Number Date Notes A SPRS857 December 2012 See (1) A2 SPRS857 December 2012 See (2) B SPRS857 March 2013 See (3) C SPRS857 April 2013 See (4) D SPRS857 May 2013 See (5) E SPRS857 July 2013 See (6) F SPRS857 September 2013 See (7) G SPRS857 November 2013 See (8) (1) DRA75x/DRA74x Infotainment Applications Processor Silicon Revision 1.0 Data Manual - version A - DRAFT Book release. (2) DRA75x/DRA74x Infotainment Applications Processor Silicon Revision 1.0 Data Manual - version A2 - DRAFT Book release. Version A2 fixes a problem with the vin1a_xxx and vin1b_clk pins on the DRA74x device, and with gpio6 muxing (3) DRA75x/DRA74x Infotainment Applications Processor Silicon Revision 1.0 Data Manual - version B - Early Preliminary Book release. (4) DRA75x/DRA74x Infotainment Applications Processor Silicon Revision 1.0 Data Manual - version C - Early Preliminary Book release. In this version are updated the following chapters : Chapter 2 - Terminal Descriptions, Chapter 3 - Electrical Characteristics, and Chapter 5 - Timing Requirements and Switching Characteristics. (5) DRA75x/DRA74x Infotainment Applications Processor Silicon Revision 1.0 Data Manual - version D - Early Preliminary Book release. In this version are updated the following chapters : Chapter 2 - Terminal Descriptions, Chapter 5 - Timing Requirements and Switching Characteristics and include new Chapter 8 - PCB Guidelines. (6) DRA75x/DRA74x Infotainment Applications Processor Silicon Revision 1.0 Data Manual - version E - Early Preliminary Book release. In this version are updated the following chapters : Chapter 1 Introduction, Chapter 2 - Terminal Descriptions, Chapter 3 - Electrical Characteristics, Chapter 4 - Clock Specifications, and Chapter 5 - Timing Requirements and Switching Characteristics. (7) DRA75x/DRA74x Infotainment Applications Processor Silicon Revision 1.0 Data Manual - version F - Early Preliminary Book release. In this version are updated the following chapters : Chapter 1 Introduction, Chapter 2 - Terminal Descriptions, Chapter 3 - Electrical Characteristics, Chapter 4 - Clock Specifications, Chapter 5 - Timing Requirements and Switching Characteristics and Chapter 8 - PCB Guidelines. Populate information in Chapter 7 - Package Characteristics. (8) DRA75x/DRA74x Infotainment Applications Processor Silicon Revision 1.0 Data Manual - version G - Early Preliminary Book release. In this version are updated the following chapters : Chapter 1 Introduction, Chapter 2 - Terminal Descriptions, Chapter 3 - Electrical Characteristics, Chapter 4 - Clock Specifications, Chapter 5 - Timing Requirements and Switching Characteristics and Chapter 8 - PCB Guidelines. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback PCB Guidelines 399 IMPORTANT NOTICE EARLY PRELIMINARY ADVANCE INFORMATION Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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