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《mipi协议》高清完整英文版

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MIPI联盟,即移动产业处理器接口(Mobile Industry Processor Interface 简称MIPI)联盟。MIPI(移动产业处理器接口)是MIPI联盟发起的为移动应用处理器制定的开放标准和一个规范。

mipi协议汇总,d-phy

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MIPI Alliance Test Program DPHY Physical Layer Conformance Test Suite Version 100 Technical Document MIPI Confidential NOTICE This is a living document Contents are subject to change in subsequent releases as incremental refinementsimprovements are made and supplemental material is added To check for the latest version always refer to the MIPI Alliance Testing Page Last Updated September 16 2010 MIPI Alliance T......

MIPI Alliance Test Program D-PHY Physical Layer Conformance Test Suite Version 1.00 Technical Document MIPI Confidential NOTICE: This is a living document. Contents are subject to change in subsequent releases, as incremental refinements/improvements are made, and supplemental material is added. To check for the latest version, always refer to the MIPI Alliance Testing Page Last Updated September 16, 2010 MIPI Alliance Test Program InterOperability Laboratory University of New Hampshire 121 Technology Drive, Suite 2 Durham, NH 03824 Phone: (603) 862-3749 The University of New Hampshire InterOperability Laboratory TABLE OF CONTENTS TABLE OF CONTENTS....................................................................................................... 2 MODIFICATION RECORD............................................................................................... 5 ACKNOWLEDGMENTS................................................................................................... 12 INTRODUCTION ................................................................................................................. 13 REFERENCES ....................................................................................................................... 15 SECTION 1: TX TIMERS AND SIGNALING ................................ 16 GROUP 1: DATA LANE LP-TX SIGNALING REQUIREMENTS......................................................................17 Test 1.1.1 – Data Lane LP-TX Thevenin Output High Level Voltage (VOH)......................................................18 Test 1.1.2 – Data Lane LP-TX Thevenin Output Low Level Voltage (VOL).......................................................20 Test 1.1.3 – Data Lane LP-TX 15%-85% Rise Time (TRLP)................................................................................21 Test 1.1.4 – Data Lane LP-TX 15%-85% Fall Time (TFLP).................................................................................24 Test 1.1.5 – Data Lane LP-TX Slew Rate vs. CLOAD (δV/δtSR)............................................................................25 Test 1.1.6 – Data Lane LP-TX Pulse Width of Exclusive-OR Clock (TLP-PULSE-TX)............................................31 Test 1.1.7 – Data Lane LP-TX Period of Exclusive-OR Clock (TLP-PER-TX) ........................................................33 GROUP 2: CLOCK LANE LP-TX SIGNALING REQUIREMENTS ..................................................................35 Test 1.2.1 – Clock Lane LP-TX Thevenin Output High Level Voltage (VOH)....................................................36 Test 1.2.2 – Clock Lane LP-TX Thevenin Output Low Level Voltage (VOL).....................................................37 Test 1.2.3 – Clock Lane LP-TX 15%-85% Rise Time (TRLP)..............................................................................38 Test 1.2.4 – Clock Lane LP-TX 15%-85% Fall Time (TFLP)...............................................................................39 Test 1.2.5 – Clock Lane LP-TX Slew Rate vs. CLOAD (δV/δtSR)..........................................................................40 GROUP 3: DATA LANE HS-TX SIGNALING REQUIREMENTS .....................................................................42 Test 1.3.1 – Data Lane HS Entry: Data Lane TLPX Value....................................................................................43 Test 1.3.2 – Data Lane HS Entry: THS-PREPARE Value...........................................................................................44 Test 1.3.3 – Data Lane HS Entry: THS-PREPARE + THS-ZERO Value.........................................................................45 Test 1.3.4 – Data Lane HS-TX Differential Voltages (VOD(0), VOD(1)).................................................................46 Test 1.3.5 – Data Lane HS-TX Differential Voltage Mismatch (∆VOD) .............................................................50 Test 1.3.6 – Data Lane HS-TX Single-Ended Output High Voltages (VOHHS(DP), VOHHS(DN))..............................51 Test 1.3.7 – Data Lane HS-TX Static Common-Mode Voltages (VCMTX(1), VCMTX(0)) ........................................54 Test 1.3.8 – Data Lane HS-TX Static Common-Mode Voltage Mismatch (∆VCMTX(1,0))....................................56 Test 1.3.9 – Data Lane HS-TX Dynamic Common-Level Variations Between 50-450MHz (∆VCMTX(LF)) ........57 Test 1.3.10 – Data Lane HS-TX Dynamic Common-Level Variations Above 450MHz (∆VCMTX(HF))...............59 Test 1.3.11 – Data Lane HS-TX 20%-80% Rise Time (tR) .................................................................................60 Test 1.3.12 – Data Lane HS-TX 80%-20% Fall Time (tF)...................................................................................63 Test 1.3.13 – Data Lane HS Exit: THS-TRAIL Value ..............................................................................................65 Test 1.3.14 – Data Lane HS Exit: 30%-85% Post-EoT Rise Time (TREOT) .........................................................67 Test 1.3.15 – Data Lane HS Exit: TEOT Value .....................................................................................................68 Test 1.3.16 – Data Lane HS Exit: THS-EXIT Value ................................................................................................69 GROUP 4: CLOCK LANE HS-TX SIGNALING REQUIREMENTS..................................................................71 Test 1.4.1 – Clock Lane HS Entry: TLPX Value ...................................................................................................72 Test 1.4.2 – Clock Lane HS Entry: TCLK-PREPARE Value.......................................................................................73 Test 1.4.3 – Clock Lane HS Entry: TCLK-PREPARE+TCLK-ZERO Value .....................................................................74 Test 1.4.4 – Clock Lane HS-TX Differential Voltages (VOD(0), VOD(1))...............................................................75 Test 1.4.5 – Clock Lane HS-TX Differential Voltage Mismatch (∆VOD) ...........................................................78 Test 1.4.6 – Clock Lane HS-TX Single-Ended Output High Voltages (VOHHS(DP), VOHHS(DN))............................79 Test 1.4.7 – Clock Lane HS-TX Static Common-Mode Voltages (VCMTX(1), VCMTX(0)) ......................................81 Test 1.4.8 – Clock Lane HS-TX Static Common-Mode Voltage Mismatch (∆VCMTX(1,0))..................................82 Test 1.4.9 – Clock Lane HS-TX Dynamic Common-Level Variations Between 50-450MHz (∆VCMTX(LF)).......83 Test 1.4.10 – Clock Lane HS-TX Dynamic Common-Level Variations Above 450MHz (∆VCMTX(HF)).............84 Test 1.4.11 – Clock Lane HS-TX 20%-80% Rise Time (tR) ...............................................................................85 MIPI Alliance Test Program MIPI Confidential 2 D-PHY Physical Layer Conformance Test Suite v1.00 MIPI Confidential The University of New Hampshire InterOperability Laboratory Test 1.4.12 – Clock Lane HS-TX 80%-20% Fall Time (tF).................................................................................87 Test 1.4.13 – Clock Lane HS Exit: TCLK-TRAIL Value...........................................................................................89 Test 1.4.14 – Clock Lane HS Exit: 30%-85% Post-EoT Rise Time (TREOT) .......................................................91 Test 1.4.15 – Clock Lane HS Exit: TEOT Value ...................................................................................................92 Test 1.4.16 – Clock Lane HS Exit: THS-EXIT Value ..............................................................................................93 Test 1.4.17 – Clock Lane HS Clock Instantaneous (UIINST)................................................................................95 GROUP 5: HS-TX CLOCK-TO-DATA LANE TIMING REQUIREMENTS .......................................................97 Test 1.5.1 – HS Entry: TCLK-PRE Value.................................................................................................................98 Test 1.5.2 – HS Exit: TCLK-POST Value ...............................................................................................................100 Test 1.5.3 – HS Clock Rising Edge Alignment to First Payload Bit .................................................................102 Test 1.5.4 – Data-to-Clock Skew (TSKEW[TX]) ....................................................................................................104 GROUP 6: LP-TX INIT, ULPS, AND BTA REQUIREMENTS..........................................................................106 Test 1.6.1 – INIT: LP-TX Initialization Period (TINIT,MASTER) ...........................................................................107 Test 1.6.2 – ULPS Entry: Verification of Clock Lane LP-TX ULPS support...................................................109 Test 1.6.3 – ULPS Exit: Transmitted TWAKEUP Interval.....................................................................................110 Test 1.6.4 – BTA: TX-Side TTA-GO Interval Value ............................................................................................111 Test 1.6.5 – BTA: RX-Side TTA-SURE Interval Value .........................................................................................113 Test 1.6.6 – BTA: RX-Side TTA-GET Interval Value...........................................................................................115 SECTION 2: RX TIMERS AND ELECTRICAL TOLERANCES ............................................................................................................117 GROUP 1: LP-RX VOLTAGE AND TIMING REQUIREMENTS .....................................................................118 Test 2.1.1 – LP-RX Logic 1 Input Voltage (VIH) ..............................................................................................119 Test 2.1.2 – LP-RX Logic 0 Input Voltage, Non-ULP State (VIL) ....................................................................121 Test 2.1.3 – LP-RX Logic 0 Input Voltage, ULP State (VIL-ULPS) .....................................................................123 Test 2.1.4 – LP-RX Input Hysteresis (VHYST)....................................................................................................125 Test 2.1.5 – LP-RX Minimum Pulse Width Response (TMIN-RX).......................................................................128 Test 2.1.6 – LP-RX Input Pulse Rejection (eSPIKE) ............................................................................................130 Test 2.1.7 – LP-RX Interference Tolerance (VINT and fINT)...............................................................................134 Test 2.1.8 – LP-CD Logic Contention Thresholds (VIHCD and VILCD)...............................................................136 GROUP 2: LP-RX BEHAVIORAL REQUIREMENTS.......................................................................................138 Test 2.2.1 – LP-RX Initialization period (TINIT) ................................................................................................139 Test 2.2.2 – ULPS Exit: LP-RX TWAKEUP Timer Value.....................................................................................141 Test 2.2.3 – Clock Lane LP-RX Invalid/Aborted ULPS Entry..........................................................................142 Test 2.2.4 – Data Lane LP-RX Invalid/Aborted Escape Mode Entry................................................................144 Test 2.2.5 – Data Lane LP-RX Invalid/Aborted Escape Mode Command ........................................................146 Test 2.2.6 – Data Lane LP-RX Escape Mode Invalid Exit (INFORMATIVE) .................................................148 Test 2.2.7 – Data Lane LP-RX Escape Mode, Ignoring of Post-Trigger-Command Extra Bits ........................150 Test 2.2.8 – Data Lane LP-RX Escape Mode Unsupported/Unassigned Commands........................................152 GROUP 3: HS-RX VOLTAGE AND SETUP/HOLD REQUIREMENTS...........................................................154 Test 2.3.1 – HS-RX Common Mode Voltage Tolerance (VCMRX(DC))................................................................155 Test 2.3.2 – HS-RX Differential Input High Threshold (VIDTH)........................................................................157 Test 2.3.3 – HS-RX Differential Input Low Threshold (VIDTL).........................................................................159 Test 2.3.4 – HS-RX Single-Ended Input High Voltage (VIHHS) ........................................................................160 Test 2.3.5 – HS-RX Single-Ended Input Low Voltage (VILHS) .........................................................................162 Test 2.3.6 – HS-RX Common-Mode Interference 50MHz - 450MHz (∆VCMRX(LF)).........................................164 Test 2.3.7 – HS-RX Common-Mode Interference Beyond 450MHz (∆VCMRX(HF))...........................................166 Test 2.3.8 – HS-RX Setup/Hold and Jitter Tolerance........................................................................................167 GROUP 4: HS-RX TIMER REQUIREMENTS...................................................................................................171 Test 2.4.1 – Data Lane HS-RX TD-TERM-EN Value..............................................................................................172 Test 2.4.2 – Data Lane HS-RX THS-PREPARE + THS-ZERO Tolerance.....................................................................174 Test 2.4.3 – Data Lane HS-RX THS-SETTLE Value...............................................................................................176 Test 2.4.4 – Data Lane HS-RX THS-TRAIL Tolerance..........................................................................................178 Test 2.4.5 – Data Lane HS-RX THS-SKIP Value ..................................................................................................180 Test 2.4.6 – Clock Lane HS-RX TCLK-TERM-EN Value.........................................................................................182 MIPI Alliance Test Program MIPI Confidential 3 D-PHY Physical Layer Conformance Test Suite v1.00 MIPI Confidential The University of New Hampshire InterOperability Laboratory Test 2.4.7 – Clock Lane HS-RX TCLK-PREPARE + TCLK-ZERO Tolerance...............................................................183 Test 2.4.8 – Clock Lane HS-RX TCLK-SETTLE Value...........................................................................................185 Test 2.4.9 – Clock Lane HS-RX TCLK-TRAIL Tolerance ......................................................................................187 Test 2.4.10 – Clock Lane HS-RX TCLK-MISS Value............................................................................................189 Test 2.4.11 – Clock Lane HS-RX TCLK-PRE and TCLK-POST Tolerance.................................................................191 SECTION 3: INTERFACE IMPEDANCE AND S- PARAMETERS........................................................................................................... 193 GROUP 1: HS-TX S-PARAMETERS..................................................................................................................194 Test 3.1.1 – HS-TX Differential Return Loss (SDD22) ....................................................................................195 Test 3.1.2 – HS-TX Common-Mode Return Loss (SCC22)..............................................................................198 Test 3.1.3 – HS-TX Mode Conversion Limits (SDC22) ...................................................................................200 Test 3.1.4 – HS-TX Single-Ended Output Impedance (ZOS) .............................................................................202 Test 3.1.5 – HS-TX Single-Ended Output Impedance Mismatch (∆ZOS)..........................................................204 GROUP 2: HS-RX S-PARAMETERS .................................................................................................................205 Test 3.2.1 – HS-RX Differential Return Loss (SDD11)....................................................................................206 Test 3.2.2 – HS-RX Common-Mode Return Loss (SCC11)..............................................................................208 Test 3.2.3 – HS-RX Mode Conversion Limits (SDC11) ...................................................................................210 Test 3.2.4 – HS-RX DC Differential Input Impedance (ZID).............................................................................212 GROUP 3: LP-TX/RX IMPEDANCE REQUIREMENTS ..................................................................................214 Test 3.3.1 – LP-TX Output Impedance (ZOLP)...................................................................................................215 Test 3.3.2 – LP-RX Input Leakage Current (ILEAK) ...........................................................................................217 APPENDICES .............................................................................................................. 219 APPENDIX A – RESOURCE REQUIREMENTS (DUT AND TEST EQUIPMENT) ............................................................220 APPENDIX B – TEST SETUPS..................................................................................................................................223 APPENDIX C – GENERIC RECEIVER TEST SEQUENCE TEMPLATE ...........................................................................229 APPENDIX D – REFERENCE HS TEST PATTERN FOR RX BER VERIFICATION AND INTEROPERABILITY TESTING....232 APPENDIX E – LOGIC ANALYZER TRIGGER SETUP FOR FRAME ERROR COUNTING (INFORMATIVE).......................238 APPENDIX F – STATISTICAL METHODOLOGY FOR BIT ERROR RATE (BER) VERIFICATION ....................................241 APPENDIX G – RX TEST OBSERVABLES FOR DUT DEVICE TYPES.........................................................................246 APPENDIX H – STANDARDIZED SOFTWARE INTERFACE FOR TEST AUTOMATION ...................................................250 APPENDIX I – VENDOR DUT PRE-TEST CHECKLIST..............................................................................................252 MIPI Alliance Test Program MIPI Confidential 4 D-PHY Physical Layer Conformance Test Suite v1.00 MIPI Confidential 2010 Sep 16 (v1.00) Final incremental update. First v1.0 release. Andy Baldman: The University of New Hampshire InterOperability Laboratory MODIFICATION RECORD Entire document: Removed ‘NEW’ and ‘Prev.’ indicators from titles of all tests whose test numbers have not changed since the previous revision. SECTION 1: (TX TESTS): Section 1, Group 1 Title Page: Added paragraph to Overview stating that this Group is typically only performed for Master DUTs. Section 1, Group 2 Title Page: Added paragraph to Overview stating that this Group is N/A for Slave DUTs. Section 1, Groups 3+4+5 Title Pages: Added statement to Overview stating that Group is N/A for Slave DUTs. Section 1, Group 6 Title Page: Added paragraph to Overview stating applicability for each test in the group. All 1.1.x Tests: Changed all Procedures to specify using ULPS Entry sequence. Test 1.1.6+1.1.7: Fixed major typo/goof-up where maximum trip-level threshold was previously incorrectly calculated/stated in 1.1.6 as “880+50=850mV”, instead of 930mV. All references to the 850mV trip level in 1.1.6 and 1.1.7 have been corrected to 930mV. Also, added comments to Possible Problems regarding glitches caused by noise on the input waveforms. Test 1.1.6: Added clarification that a ‘pulse’ is defined as rising edge to falling edge. Tests 1.1.5+1.2.5: Modified methodology so final slew rate results are now averaged over all measured edges (as opposed to reporting the peak measured values as the final result.) Also, changed 1.1.5 Discussion to use a horizontally centered sliding window. Also cleaned up and expanded 1.1.5 Discussion to more clearly describe the separate measurements that are performed for the rising and falling edges. Cleaned up and synchronized both Procedure sections to more clearly show the 2 falling edge and 3 rising edge measurements. Added informative provision to repeat all measurements with the CLOAD board removed, to get a sense of the DUT PCB’s CLOAD contribution. Tests 1.2.1/2/4/5: Modified Discussion and Procedure sections to specify using the Clock ULPS Entry sequence for all measurements (and prohibit using HS Entry.) Tests 1.2.3: Modified procedure to specify using Clock ULPS Exit sequence. Test 1.3.4: Added a paragraph to Possible Problems explaining that averaging should be performed starting with the end of the burst (and worked backwards), rather than from the front of the burst. Test 1.3.5: Added note to Possible Problems pointing to Possible Problems of Test 1.3.4. Tests 1.3.6+1.4.6: Changed Data/Clock VOHHS methodologies to use the same reference pulse-based approach as 1.3.4/1.4.4 (Data/Clock VOD). Tests 1.3.7+1.4.7: Added specification that measurements be performed over at least 5K UIs each. Tests 1.3.11+1.3.12: Updated figures with better looking versions. Test 1.3.13: Added new observable result to verify that the THS-TRAIL state is actually inverted. Test 1.4.1: Improved wording/language of Possible Problems section. Test 1.4.4+1.4.11: Changed minimum averaging factor from 5000 to 128, to be consistent with respective Data Lane pulse-based tests. (Note: This change also applies to Test 1.4.12, however the test description didn’t need to be modified, as it just references 1.4.11.) Test 1.4.4: Updated figures with better looking versions. Added note to Possible Problems pointing to Possible Problems of Test 1.3.4. Test 1.4.5: Added note to Possible Problems pointing to Possible Problems of Test 1.3.4. Test 1.4.6: Added note to Possible Problems pointing to Possible Problems of Test 1.3.4. Test 1.4.11: Updated figure with better looking version. Added note to Possible Problems pointing to Possible Problems of Test 1.3.4. Test 1.4.12: Added figure showing example measurement. Added note to Possible Problems pointing to Possible Problems of Test 1.3.4. Test 1.4.13: Added new observable result to verify that the TCLK-TRAIL state is actually HS-0. Also added note to Possible Problems pointing to Possible Problems of Test 1.4.1. Test 1.4.14: Replaced missing Possible Problems section, and added a note pointing to Possible Problems of Test 1.4.1. Test 1.4.15: Added note pointing to Possible Problems of Test 1.4.1. Test 1.4.16: Added note to Discussion stating that test is N/A for continuous-clocking DUTs. Test 1.4.17: Changed minimum population size from 10K to 5K UIs. Test 1.5.3: Removed comment from Discussion about using a persistence capture to observe multiple bursts, and added a new figure showing an example measurement. Test 1.6.1: Added paragraph to discussion stating that this test may be N/A for some DUT types. Test 1.6.3: Added paragraph to discussion stating that this test may be N/A for some DUT types. (Continued on next page…) MIPI Alliance Test Program MIPI Confidential 5 D-PHY Physical Layer Conformance Test Suite v1.00 MIPI Confidential
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