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东芝闪存芯片

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标签: 东芝闪存芯片

1984年,东芝开发出一种全新的半导体存储器——闪存,由此引领整个行业跨入了一个新的时代。

在几年后的1987年,东芝又成功开发出NAND闪存。目前NAND闪存被广泛应用于众多存储卡和电子设备中。NAND闪存市场发展迅速,闪存也逐渐成为国际标准的存储设备。东芝作为闪存世界的缔造者,凭借其雄厚的技术实力和值得信赖的品质,正在创造“便携移动影音数据的新纪元”。

TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 TOSHIBA NAND memory Toggle DDR1.0 Technical Data Sheet Rev. 0.3 2012 – 04 – 10 TOSHIBA Semiconductor & Storage Products Memory Division TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 0 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C 1. INTRODUCTION TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 1.1. General Description Toggle DDR is a NAND interface for high performance applications which support data read and write operations using bidirectional DQS. Toggle DDR NAND has implemented ’Double Data Rate’ without a clock. It is compatible with functions and command which have been supported in conventional type NAND(i.e. SDR NAND) while providing high data transfer rate based on the high-speed Toggle DDR Interface and saving power with separated DQ voltage. For applications that require high capacity and high performance NAND, Toggle DDR NAND is the most appropriate. Toggle DDR1.0 NAND supports the interface speed of up to 100 MHz, which is faster than the data transfer rate offered by SDR NAND. Toggle DDR NAND transfers data at high speed using DQS signal that behaves as a clock, and DQS shall be used only when data is transferred for optimal power consumption. This device supports both SDR interface and Toggle DDR interface. When starting, the device is activated in SDR mode. The interface mode can be changed into Toggle DDR interface utilizing specific command issued by the Host. 1.2. Definitions and Abbreviations SDR Acronym for single data rate. DDR Acronym for double data rate. Address The address is comprised of a column address with 2 cycles and a row address with 3 cycles. The row address identifies the page, block and LUN to be accessed. The column address identifies the byte within a page to access. The least significant bit of the column address shall always be zero. Column The byte location within the page register. Row Refer to the block and page to be accessed. Page The smallest addressable unit for the Read and the Program operations. Block Consists of multiple pages and is the smallest addressable unit for the Erase operation. Plane The unit that consists of a number of blocks. There are one or more Planes per LUN. Page register Register used to transfer data to and from the Flash Array. Cache register Register used to transfer data to and from the Host. Defect area The defect area is where factory defects are marked by the manufacturer. Refer to the section 3.2 Device The packaged NAND unit. A device may contain more than a target. TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 1 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 LUN (Logical Unit Number) The minimum unit that can independently execute commands and report status. There are one or more LUNs per CE . Target An independent NAND Flash component with its own CE signal. SR[x] (Status Read) SR refers to the status register contained within a particular LUN. SR[x] refers to bit x in the status register for the associated LUN. Refer to section 5.13 for the definition of bit meanings within the status register. TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 2 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 1.3. Features Organization Table 1 Product Organization Parameter Part number (TOPER: 0~70℃) Part number (TOPER: -40~85℃) Device capacity Page size Block size Plane size Plane per one LUN LUN per one target Target per one device Number of valid blocks per a device (min) Number of valid blocks per a device (max) TC58TEG6DCJ TC58TEG6DCJTA00 TC58TEG6DCJTAI0 17664×256×2092×8 bits 17664 Bytes (4M + 320 K) Bytes 9459990528Bytes 1 Planes 1 LUNs 1 target 2018 2092 TH58TEG7DCJ TH58TEG7DCJTA20 TH58TEG7DCJTAK0 17664×256×2092×8×2 bits 17664 Bytes (4M + 320 K) Bytes 9459990528 Bytes 1 Planes 1 LUNs 2 targets TH58TEG8DCJ TH58TEG8DCJTA20 TH58TEG8DCJTAK0 17664×256×2092×8×4 bits 17664 Bytes (4M + 320 K) Bytes 9459990528Bytes 1 Planes 2LUNs 2 targets 4036 8072 4184 8368 • Modes Basic Operation Page Read Operation (with Random Data Output), Data Out After Status Read, Sequential Cache Read Operation, Random Cache Read Operation, Page Program Operation (with Random Data Input), Cache Program Operation, Block Erase Operation, Copy-Back Program Operation (with Random Data Input), Set Feature Operation, Get Feature Operation, Read ID Operation, Read Status Operation, Reset Operation, Reset LUN Operation Extend Operation Page Copy (2) Operation, Device Identification Table Read Operation, Read Status Enhanced Operation, Read LUN #0 Status Operation Interleaving Operation Interleaving Page Program, Interleaving Page Read, Interleaving Block Erase, Interleaving Read to Page Program, Interleaving Copy-Back Program, Table 2 Supported Operation Modes Operation Mode TC58TEG6DCJ TH58TEG7DCJ Basic Operation Supported Supported Extend Operation Supported Supported Interleaving Operation Not supported Not supported NOTE : Read LUN #1 Status Operation is supported only if the Target has more than 2 LUNs. TH58TEG8DCJ Supported Supported Supported • Mode control Serial input/output Command control • Power supply VCC = 2.7 V to 3.6 V VCCQ = 2.7 V to 3.6 V / 1.7 V to 1.95V TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 3 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 • Access time Cell array to register 100 µs max (TENTATIVE) 50 µs typ. Data Transfer rate 100MHz • Program/Erase time Auto Page Program Auto Block Erase 1700 µs/page typ. 5 ms/block typ. • Operating current Read TBD mA max. (per 1 chip) Program (avg.) Erase (avg.) Standby TBD mA max. (per 1 chip) TBD mA max. (per 1 chip) TBD µA max. (per 1 chip) • Package (Weight: TBD g typ.) • Reliability Refer to APPLICATION NOTES AND COMMENTS. 1.4. Diagram Legend Diagrams in the Toggle DDR1.0 datasheet use the following legend: Command This legend shows the command data. Refer to the Table 32 for more information about the command data. Address C1 C2 R1 R2 R3 This legend shows the Address data. The addresses are comprised of 2 cycles column address and 3 cycles row address. C1: Column address 1 C2: Column address 2 R1: Row address 1 R2: Row address 2 R3: Row address 3 W-Data This legend shows Host writing data (data input) to the device. R-Data This legend shows Host reading data (data output) from the device. SR[x] This legend shows Host reading the status register within a particular LUN. TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 4 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C 2. PHYSICAL INTERFACE 2.1. Pin Descriptions TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 Table 3 Pin Descriptions SDR Toggle DDR1.0 Pin Function DATA INPUTS/OUTPUTS DQ[7:0] DQ[7:0] The DQ pins are used to input command, address and data and to output data during read operations. The DQ pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, CLE CLE commands are latched into the command register through the DQ ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE ALE ALE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE CE CE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. READ ENABLE The RE input is the serial data-out control, and when active, drives the data onto the DQ bus. Data is RE RE valid after tDQSRE of rising edge & falling edge of RE , which also increments the internal column address counter by each one. WRITE ENABLE WE WE The WE input controls writes to the DQ port. Commands, addresses are latched on the rising edge of the WE pulse. WRITE PROTECT WP WP The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. READY/BUSY OUTPUT R/ B R/ B The R/ B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. DATA STROBE - DQS Output with read data, input with write data. Edge-aligned with read data, centered in write data. POWER Vcc Vcc VCC is the power supply for device. VccQ VccQ DQ POWER The VccQ is the power supply for input and/or output signals. Vss Vss GROUND VssQ VssQ DQ GROUND The VssQ is the power supply ground No connection NC NC NCs are not internally connected. They can be driven or left unconnected. Not use NU NU Nus must be left unconnected. NOTE: 1) Connect all Vcc and Vss pins of each device to common power supply outputs. 2) Do not leave all Vcc, VccQ, Vss and VssQ disconnected. TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 5 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 2.2. PIN ASSIGNMENT (TOP VIEW) SDR SDR/Toggle only DDR1.0 Vcc Vcc 1 Vss Vss 2 NC NC 3 NC NC 4 NC NC 5 RY / BY 1 RY / BY 1 6 RY / BY 0 RY / BY 0 7 RE RE 8 CE 0 CE 0 9 CE 1 CE 1 10 NC NC 11 VCC VSS NC VCC 12 VSS 13 NC 14 NC NC 15 CLE CLE 16 ALE ALE 17 WE WE 18 WP WP 19 NC NC 20 NC NC 21 NC NC 22 Vss Vss 23 Vcc Vcc 24 NOTE: The Pin assignment supports 2CE/2RB. Tx58TEGxDCJ SDR/Toggle SDR DDR1.0 only 48 Vss Vss 47 NC NC 46 VssQ NU or VssQ 45 VccQ NU or VccQ 44 DQ7 DQ7 43 DQ6 DQ6 42 DQ5 DQ5 41 DQ4 DQ4 40 VssQ NU or VssQ 39 VccQ NU or VccQ 38 VccQ VccQ 37 VCC 36 VSS 35 DQS VCC VSS NU 34 VccQ VccQ 33 VssQ NU or VssQ 32 DQ3 DQ3 31 DQ2 DQ2 30 DQ1 DQ1 29 DQ0 DQ0 28 VccQ NU or VccQ 27 VssQ NU or VssQ 26 NC NC 25 Vss Vss TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 6 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C 2.3. BLOCK DIAGRAM TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 VCCQ VSSQ VCC VSS DQ0 to DQ7 DQS CE CLE ALE WE RE WP DQS RY / BY I/O Control circuit Status register Address register Command register Logic control Control circuit Column buffer Column decoder Data register Sense amp Memory cell array Row address buffer decoder Row address decoder RY / BY HV generator Figure 1. Block Diagram (TC58TEG6DCJ) TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 7 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C DQ0 to DQ7 DQS CE 0 CLE ALE WE RE WP DQS RY / BY 0 CE 1 RY / BY 1 TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 I/O Control circuit (Chip A) Status register Address register Command register Logic control Control circuit VCCQ VSSQ VCC VSS Column buffer Column decoder Data register Sense amp Memory cell array Row address buffer decoder Row address decoder RY / BY I/O Control circuit HV generator Status register Address register Command register Logic control Control circuit Column buffer Column decoder Data register Sense amp Memory cell array Row address buffer decoder Row address decoder RY / BY HV generator (Chip B) Figure 2. Block Diagram (TH58TEG7DCJ) VCCQ VSSQ VCC VSS TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 8 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C DQ0 to DQ7 DQS CE 0 CLE ALE WE RE WP DQS RY / BY 0 CE 1 RY / BY 1 TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 I/O Control circuit (Chip A,B) Status register Address register Command register Logic control Control circuit VCCQ VSSQ VCC VSS Column buffer Column decoder Data register Sense amp Memory cell array Row address buffer decoder Row address decoder RY / BY I/O Control circuit HV generator Status register Address register Command register Logic control Control circuit Column buffer Column decoder Data register Sense amp Memory cell array Row address buffer decoder Row address decoder RY / BY HV generator (Chip C,D) Figure 3. Block Diagram (TH58TEG8DCJ) VCCQ VSSQ VCC VSS TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 9 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 2.4. Independent Data Buses There may be two independent 8-bit data buses in some packages, with two, four or eight CE signals. If the device supports two independent data buses, then CE 1, CE 3, CE 5, and CE 7 (if connected) shall use the second data bus. CE 0, CE 2 CE 4, and CE 6 shall always use the first data bus pins. Note that all CE s may use the first data bus and the first set of control signals ( RE 0, CLE0, ALE0, WE 0, and WP 0) if the device does not support independent data buses. Table 4 defines the control signal to CE signal mapping when there are two independent x8 data buses. Table 4 Dual Channel(x8) Data Bus Signal to CE mapping Signal Name R/ B 0 R/ B 1 R/ B 2 R/ B 3 RE 0 RE 1 CLE0 CLE1 ALE0 ALE1 WE 0 WE 1 WP 0 WP 1 DQS0 DQS1 CE CE 0, CE 4 CE 1, CE 5 CE 2, CE 6 CE 3, CE 7 CE 0, CE 2, CE 4, CE 6 CE 1, CE 3, CE 5, CE 7 CE 0, CE 2, CE 4, CE 6 CE 1, CE 3, CE 5, CE 7 CE 0, CE 2, CE 4, CE 6 CE 1, CE 3, CE 5, CE 7 CE 0, CE 2, CE 4, CE 6 CE 1, CE 3, CE 5, CE 7 CE 0, CE 2, CE 4, CE 6 CE 1, CE 3, CE 5, CE 7 CE 0, CE 2, CE 4, CE 6 CE 1, CE 3, CE 5, CE 7 Implementations may tie the data lines and control signals ( RE , CLE, ALE, WE , WP , and DQS) together for the two independent 8-bit data buses externally to the device. 2.5. Absolute Maximum DC Rating Stresses greater than those listing in Table 5 may cause permanent damage to the device. This is a stress rating only. Operation beyond the operating conditions specified in Table 6 is not recommended. Extended exposure beyond these conditions may affect device reliability. Table 5 Absolute Maximum Rating Parameter Voltage on any pin relative to VSS VIN VI/O Symbol VCC VccQ(3.3V) VccQ(1.8V) VccQ(3.3V) VccQ(1.8V) Rating Unit -0.6 to +4.6 -0.6 to +4.6 -0.2 to +2.4 V -0.6 to +4.6 -0.2 to +2.4 TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 10 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 2.6. Operating Temperature Condition Table 6 Operating Temperature Condition Symbol Parameter Part Number Rating Unit Operating Temperature Range for Commercial TC58TEG6DCJTA00 0~70 Operating Temperature Range for Industrial TC58TEG6DCJTAI0 -40~+85 TOPER Operating Temperature Range for Commercial TH58TEG7DCJTA20 0~70 ℃ Operating Temperature Range for Industrial TH58TEG7DCJTAK0 -40~+85 Operating Temperature Range for Commercial TH58TEG8DCJTA20 0~70 Operating Temperature Range for Industrial TH58TEG8DCJTAK0 -40~+85 TSOLDER Soldering Temperature (10 s) 260 TSTG Storage Temperature -55~+150 NOTE: 1) Operating Temperature (TOPER) is the case surface temperature on the center/top side of the NAND. 2) Operating Temperature Range specifies the temperatures where all NAND specifications will be supported. During operation, the NAND case temperature must be maintained between the range specified in the table under all operating conditions. 2.7. Recommended Operating Conditions Table 7 Recommended Operating Condition Parameter Symbol Min Typ. Max Unit Supply Voltage VCC 2.7 3.3 3.6 V Ground Voltage VSS 0 0 0 V Supply Voltage for 1.8V I/O signaling VccQ 1.7 1.8 1.95 V Supply Voltage for 3.3V I/O signaling VccQ 2.7 3.3 3.6 V Ground Voltage for I/O signaling VssQ 0 0 0 V VccQ and Vcc may be distinct and unique voltages. The device shall support one of the following VccQ/Vcc combinations, Vcc = 3.3V, VccQ = 3.3V Vcc = 3.3V, VccQ = 1.8V All parameters, timing modes and other characteristics are related to the supported voltage combination. 2.8. Valid Blocks Table 8 Valid Blocks Number of Valid Blocks per a device TC58TEG6DCJ TH58TEG7DCJ Min 2018 4036 Max 2092 4184 NOTE: 1) The device occasionally contains unusable blocks. 2) The first block (Block 0) is guaranteed to be a valid block at the time of shipment. 3) The specification for the minimum number of valid blocks is applicable over the device lifetime. 4) The number of valid blocks includes extended blocks. TH58TEG8DCJ 8072 8368 TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 11 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C 7. Package Dimensions TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 12 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission. • Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. • Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document. Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact (“Unintended Use”). Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for Unintended Use unless specifically permitted in this document. • Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part. • Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. • The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. • ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. • Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. • Product is subject to foreign exchange and foreign trade control laws. • Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 13 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 TENTATIVE 2012-04-10C
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