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Preliminary TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide Literature Number: SPRUGE5B December 2008 – Revised December 2009 Preliminary 2 SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preface ....................................................................................................................................... 6 1 Analog-to-Digital Converter (ADC) ......................................................................................... 8 1.1 Features .................................................................................................................. 8 1.2 Block Diagram ........................................................................................................... 9 1.3 SOC Principle of Operation ............................................................................................ 9 1.4 ADC Conversion Priority .............................................................................................. 12 1.5 Simultaneous Sampling Mode ....................................................................................... 15 1.6 EOC and Interrupt Operation ......................................................................................... 15 1.7 Power Up Sequence .................................................................................................. 16 1.8 ADC Calibration ........................................................................................................ 16 1.9 Internal/External Reference Voltage Selection ..................................................................... 18 1.10 ADC Registers ......................................................................................................... 19 1.11 ADC Timings ........................................................................................................... 35 1.12 Internal Temperature Sensor ......................................................................................... 38 2 Comparator Block ............................................................................................................. 40 2.1 Features ................................................................................................................. 40 2.2 2.2 Block Diagram ..................................................................................................... 40 2.3 Comparator Function .................................................................................................. 41 2.4 DAC Reference ........................................................................................................ 41 2.5 Initialization ............................................................................................................. 41 2.6 Digital Domain Manipulation .......................................................................................... 41 2.7 Comparator Registers ................................................................................................. 43 Appendix A Revision History ...................................................................................................... 45 SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Table of Contents 3 Preliminary www.ti.com List of Figures 1 ADC Block Diagram ........................................................................................................ 9 2 SOC Block Diagram....................................................................................................... 10 3 ADCINx Input Model ...................................................................................................... 12 4 Round Robin Priority Example........................................................................................... 13 5 High Priority Example ..................................................................................................... 14 6 Interrupt Structure ......................................................................................................... 16 7 ADC Control Register 1 (ADCCTL1) (Address Offset 00h) .......................................................... 19 8 ADC Interrupt Flag Register (ADCINTFLG) (Address Offset 04h).................................................. 21 9 ADC Interrupt Flag Clear Register (ADCINTFLGCLR) (Address Offset 05h) ..................................... 22 10 ADC Interrupt Overflow Register (ADCINTOVF) (Address Offset 06h) ............................................ 22 11 ADC Interrupt Overflow Clear Register (ADCINTOVFCLR) (Address Offset 07h) ............................... 23 12 Interrupt Select 1 And 2 Register (INTSEL1N2) (Address Offset 08h)............................................. 23 13 Interrupt Select 3 And 4 Register (INTSEL3N4) (Address Offset 09h)............................................. 23 14 Interrupt Select 5 And 6 Register (INTSEL5N6) (Address Offset 0Ah) ............................................ 23 15 Interrupt Select 7 And 8 Register (INTSEL7N8) (Address Offset 0Bh) ............................................ 24 16 Interrupt Select 9 And 10 Register (INTSEL9N10) (Address Offset 0Ch) ......................................... 24 17 ADC Start of Conversion Priority Control Register (SOCPRICTL).................................................. 25 18 ADC Sample Mode Register (ADCSAMPLEMODE) (Address Offset 12h)........................................ 27 19 ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1) (Address Offset 14h) ...................... 28 20 ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2) (Address Offset 15h) ...................... 29 21 ADC SOC Flag 1 Register (ADCSOCFLG1) (Address Offset 18h)................................................. 29 22 ADC SOC Force 1 Register (ADCSOCFRC1) (Address Offset 1Ah) .............................................. 29 23 ADC SOC Overflow 1 Register (ADCSOCOVF1) (Address Offset 1Ch)........................................... 30 24 ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1) (Address Offset 1Eh) .............................. 30 25 ADC SOC0 - SOC15 Control Registers (ADCSOCxCTL) (Address Offset 20h - 2Fh) .......................... 31 26 ADC Reference/Gain Trim Register (ADCREFTRIM) (Address Offset 40h) ...................................... 33 27 ADC Offset Trim Register (ADCOFFTRIM) (Address Offset 41h) .................................................. 33 28 ADC Revision Register (ADCREV) (Address Offset 4Fh) ........................................................... 34 29 ADC RESULT0 - RESULT15 Registers (ADCRESULTx) (PF1 Block Address Offset 00h - 0Fh).............. 34 30 Timing Example For Sequential Mode / Late Interrupt Pulse........................................................ 35 31 Timing Example For Sequential Mode / Early Interrupt Pulse....................................................... 36 32 Timing Example For Simultaneous Mode / Late Interrupt Pulse .................................................... 37 33 Timing Example For Simultaneous Mode / Early Interrupt Pulse ................................................... 38 34 Temperature Sensor Transfer Function ............................................................................... 39 35 Comparator Block Diagram .............................................................................................. 40 36 Comparator................................................................................................................. 41 37 Comparator Control (COMPCTL) Register ............................................................................ 43 38 Compare Output Status (COMPSTS) Register........................................................................ 44 39 DAC Value (DACVAL) Register ......................................................................................... 44 4 List of Figures SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 List of Tables Sample timings with different values of ACQPS ...................................................................... 11 ADC Configuration & Control Registers (AdcRegs and AdcResult): ............................................... 19 ADC Control Register 1 (ADCCTL1) Field Descriptions ............................................................. 20 ADC Interrupt Flag Register (ADCINTFLG) Field Descriptions ..................................................... 21 ADC Interrupt Flag Clear Register (ADCINTFLGCLR) Field Descriptions......................................... 22 ADC Interrupt Overflow Register (ADCINTOVF) Field Descriptions................................................ 22 ADC Interrupt Overflow Clear Register (ADCINTOVFCLR) Field Descriptions ................................... 23 INTSELxNy Register Field Descriptions................................................................................ 24 SOCPRICTL Register Field Descriptions .............................................................................. 25 ADC Sample Mode Register (ADCSAMPLEMODE) Field Descriptions ........................................... 27 ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1) Register Field Descriptions............... 28 ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2) Field Descriptions.......................... 29 ADC SOC Flag 1 Register (ADCSOCFLG1) Field Descriptions .................................................... 29 ADC SOC Force 1 Register (ADCSOCFRC1) Field Descriptions .................................................. 30 ADC SOC Overflow 1 Register (ADCSOCOVF1) Field Descriptions .............................................. 30 ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1) Field Descriptions .................................. 30 ADC SOC0 - SOC15 Control Registers (ADCSOCxCTL) Register Field Descriptions .......................... 31 ADC Reference/Gain Trim Register (ADCREFTRIM) Field Descriptions .......................................... 33 ADC Offset Trim Register (ADCOFFTRIM) Field Descriptions...................................................... 33 ADC Revision Register (ADCREV) Field Descriptions ............................................................... 34 ADC RESULT0 - ADCRESULT15 Registers (ADCRESULTx) Field Descriptions................................ 34 Comparator Truth Table .................................................................................................. 41 Comparator Module Registers .......................................................................................... 43 COMPCTL Register Field Descriptions................................................................................. 43 Compare Output Status (COMPSTS) Register Field Descriptions ................................................. 44 DAC Value (DACVAL) Register Field Descriptions ................................................................... 44 Changes in this Document ............................................................................................... 45 SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated List of Tables 5 Preliminary Preface SPRUGE5B – December 2008 – Revised December 2009 Read This First Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h or with a leading 0x. For example, the following number is 40 hexadecimal (decimal 64): 40h or 0x40. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties. – Reserved bits in a register figure designate a bit that is used for future device expansion. Related Documents From Texas Instruments The following documents are available for download from the Texas Instruments website, www.ti.com. SPRS523 — TMS320F28020, TMS320F28021, TMS320F28022, TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the 2802x devices. SPRZ292 — TMS320F28020, TMS320F28021, TMS320F28022, TMS320F28023, TMS320F28026, TMS320F28027 Piccolo MCU Silicon Errata describes known advisories on silicon and provides workarounds. SPRS584 — TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo Microcontrollers Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the 2803x devices. SPRZ295 — TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo MCU Silicon Errata describes known advisories on silicon and provides workarounds. CPU User's Guides— SPRU430 — TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. Peripheral Guides— SPRUFN3 — TMS320x2802x Piccolo System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 2802x microcontrollers (MCUs). SPRUGL8 — TMS320x2803x Piccolo System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 2803x microcontrollers (MCUs). SPRU566 — TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRUGO0 — TMS320x2803x Piccolo Boot ROM Reference Guide describes the purpose and features of the bootloader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory. 6 Preface SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Related Documents From Texas Instruments SPRUFN6 — TMS320x2802x Piccolo Boot ROM Reference Guide describes the purpose and features of the bootloader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory. SPRUGE6 — TMS320x2803x Piccolo Control Law Accelerator (CLA) Reference Guide describes the operation of the Control Law Accelerator (CLA). SPRUGE2 — TMS320x2803x Piccolo Local Interconnect Network (LIN) Module Reference Guide describes the operation of the Local Interconnect Network (LIN) Module. SPRUFK8 — TMS320x2803x Piccolo Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide describes the operation of the Enhanced Quadrature Encoder Pulse (eQEP) module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and position control systems. It includes the module description on registers. SPRUGL7 — TMS320x2803x Piccolo Enhanced Controller Area Network (eCAN) Reference Guide describes the operation of the Enhanced Controller Area Network (eCAN) which uses established protocol to communicate serially with other controllers in electrically noisy environments. SPRUGE5 — TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC. SPRUGE9 — TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion. SPRUGE8 — TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM) describes the operation of the high-resolution extension to the pulse width modulator (HRPWM). SPRUGH1 — TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference Guide describes how to use the SCI. SPRUFZ8 — TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module Reference Guide describes the enhanced capture module. It includes the module description and registers. SPRUG71 — TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guide describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. SPRUFZ9 — TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) Reference Guide describes the features and operation of the inter-integrated circuit (I2C) module. Tools Guides— SPRU513 — TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. SPRU514 — TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. SPRU608 — TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core. SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Read This First 7 Preliminary Reference Guide SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator The ADC module described in this reference guide is a Type 3 ADC and exists on the Piccolo™ family of devices. The Comparator function described in this reference guide is a Type 0 Comparator. See the TMS320C28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with modules of the same type, to determine the differences between the types, and for a list of device-specific differences within a type. 1 Analog-to-Digital Converter (ADC) The ADC module described in this reference guide is a 12-bit recyclic ADC; part SAR, part pipelined. The analog circuits of this converter, referred to as the "core" in this document, include the front-end analog multiplexers (MUXs), sample-and-hold (S/H) circuits, the conversion core, voltage regulators, and other analog supporting circuits. Digital circuits, referred to as the "wrapper" in this document, include programmable conversions, result registers, interface to analog circuits, interface to device peripheral bus, and interface to other on-chip modules. 1.1 Features The core of the ADC contains a single 12-bit converter fed by two sample and hold circuits. The sample and hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16 analog input channels. See the device datasheet for the specific number of channels available. The converter can be configured to run with an internal bandgap reference to create true-voltage based conversions or with a pair of external voltage references (VREFHI/LO) to create ratiometric based conversions. Contrary to previous ADC types, this ADC is not sequencer based. It is easy for the user to create a series of conversions from a single trigger. However, the basic principle of operation is centered around the configurations of individual conversions, called SOC’s, or Start-Of-Conversions. Functions of the ADC module include: • 12-bit ADC core with built-in dual sample-and-hold (S/H) • Simultaneous sampling or sequential sampling modes • Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric • Runs at full system clock, no prescaling required • Up to 16-channel, multiplexed inputs • 16 SOC’s, configurable for trigger, sample window, and channel • 16 result registers (individually addressable) to store conversion values • Multiple trigger sources – S/W - software immediate start – ePWM 1-7 – GPIO XINT2 – CPU Timers 0/1/2 – ADCINT1/2 • 9 flexible PIE interrupts, can configure interrupt request after any conversion 8 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com 1.2 Block Diagram Figure 1 shows the block diagram of the ADC module. Figure 1. ADC Block Diagram Reference Voltage Generator Bandgap Reference Circuit Int Gain Trim Analog-to-Digital Converter (ADC) VREFHI VREFLO Ext Gain Trim 10 ADCCTL1.ADCREFSEL ADCINA 0 ADCINA 1 ADCINA 2 ADCINA 3 ADCINA 4 ADCINA 5 TEMP SENSOR ADCINA 6 ADCINA 7 Input Circuit 0 1 2 3 4 0 5 1 6 7 S/H-A CHSEL[2:0] ADCINB 0 0 ADCINB 1 1 ADCINB 2 2 ADCINB 3 3 ADCINB 4 4 ADCINB 5 0 5 VREFLO 1 6 ADCINB 6 7 ADCINB 7 S/H-B ADCCTL1.VREFLOCONV ADCCTL1.TEMPCONV CHSEL[3] Converter Result RESULT Registers CHSEL SOC ACQPS SOC ADC Sample Generation Logic EOCx ADC Interrupt Logic ADCINT1-9 SOC0 – SOC15 Configurations ADCINT1 ADCINT2 SW, ePWM, Timer, GPIO SOCx Signals SOCx Triggers 1.3 SOC Principle of Operation Contrary to previous ADC types, this ADC is not sequencer based. Instead, it is SOC based. The term SOC is configuration set defining the single conversion of a single channel. In that set there are three configurations: the trigger source that starts the conversion, the channel to convert, and the acquisition (sample) window size. Each SOC is independently configured and can have any combination of the trigger, channel, and sample window size available. Multiple SOC’s can be configured for the same trigger, channel, and/or acquisition window as desired. This provides a very flexible means of configurating conversions ranging from individual samples of different channels with different triggers, to oversampling the same channel using a single trigger, to creating your own series of conversions of different channels all from a single trigger. The trigger source for SOCx is configured by a combination of the TRIGSEL field in the ADCSOCxCTL register and the appropriate bits in the ADCINTSOCSEL1 or ADCINTSOCSEL2 register. Software can also force an SOC event with the ADCSOCFRC1 register. The channel and sample window size for SOCx are configured with the CHSEL and ACQPS fields of the ADCSOCxCTL register. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 9 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com Figure 2. SOC Block Diagram SOC15 ADCSOC15CTL.ACQPS ADCSOC2CTL.ACQPS ADCSOC1CTL.ACQPS ADCSOC0CTL.ACQPS SOC2 SOC1 SOC0 ADCSOC0CTL.ACQPS ACQPS SOC CHSEL ADCSOC15CTL.CHSEL ADCSOC2CTL.CHSEL ADCSOC1CTL.CHSEL ADCSOC0CTL.CHSEL ADCSOCFLG1.SOC15 ADCSOCFLG1.SOC2 ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC0 ADC Sample Generation Logic ADCSOC0CTL.TRIGSEL ADCSOC0CTL.CHSEL 0 1 2 SOCOVF 12 Set Latch 0 Clear Start of SOC0 1 2 3 ADCINTSOCSEL1.SOC0 ADCTRIG1 ADCTRIG2 ADCTRIG12 ADCSOCFRC1.SOC0 ADCINT1 ADCINT2 undefined For example, to configure a single conversion on channel ADCINA1 to occur when the ePWM3 timer reaches its period match you must first setup ePWM3 to output an SOCA or SOCB signal on a period match. See the TMS320x2802x Piccolo Enhanced Pulse Width Modulator Module User's Guide (SPRUGE9) on how to do this. In this case, we’ll use SOCA. Then, setup one of the SOC’s using its ADCSOCxCTL register. It makes no difference which SOC we choose, so we’ll use SOC0. The fastest allowable sample window for the ADC is 7 cycles. Choosing the fastest time for the sample window, channel ADCINA1 for the channel to convert, and ePWM3 for the SOC0 trigger, we’ll set the ACQPS field to 6, the CHSEL field to 1, and the TRIGSEL field to 9, respectively. The resulting value written into the register will be: ADCSOC0CTL = 4846h; // (ACQPS=6, CHSEL=1, TRIGSEL=9) When configured as such, a single conversion of ADCINA1 will be started on an ePWM3 SOCA event with the resulting value stored in the ADCRESULT0 register. If instead ADCINA1 needed to be oversampled by 3X, then SOC1, SOC2, and SOC3 could all be given the same configuration as SOC0. ADCSOC1CTL = 4846h; ADCSOC2CTL = 4846h; ADCSOC3CTL = 4846h; // (ACQPS=6, CHSEL=1, TRIGSEL=9) // (ACQPS=6, CHSEL=1, TRIGSEL=9) // (ACQPS=6, CHSEL=1, TRIGSEL=9) When configured as such, four conversions of ADCINA1 will be started in series on an ePWM3 SOCA event with the resulting values stored in the ADCRESULT0 – ADCRESULT3 registers. Another application may require 3 different signals to be sampled from the same trigger. This can be done by simply changing the CHSEL field for SOC0-SOC2 while leaving the TRIGSEL field unchanged. 10 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) ADCSOC0CTL = 4846h; ADCSOC1CTL = 4886h; ADCSOC2CTL = 48C6h; // (ACQPS=6, CHSEL=1, TRIGSEL=9) // (ACQPS=6, CHSEL=2, TRIGSEL=9) // (ACQPS=6, CHSEL=3, TRIGSEL=9) When configured this way, three conversions will be started in series on an ePWM3 SOCA event. The result of the conversion on channel ADCINA1 will show up in ADCRESULT0. The result of the conversion on channel ADCINA2 will show up in ADCRESULT1. The result of the conversion on channel ADCINA3 will show up in ADCRESULT2. The channel converted and the trigger have no bearing on where the result of the conversion shows up. The RESULT register is associated with the SOC. NOTE: These examples are incomplete. Clocks must be enabled via the PCLKCR0 register and the ADC must be powered to work correctly. For a description of the PCLKCR0 register see the TMS320F2802x Piccolo System Control and Interrupts Reference Guide (SPRUFN3). For the power up sequence of the ADC, see Section 1.7 . 1.3.1 ADC Acquisition (Sample and Hold) Window External drivers vary in their ability to drive an analog signal quickly and effectively. Some circuits require longer times to properly transfer the charge into the sampling capacitor of an ADC. To address this, the ADC supports control over the sample window length for each individual SOC configuration. Each ADCSOCxCTL register has a 6-bit field, ACQPS, that determines the sample and hold (S/H) window size. The value written to this field is one less than the number of cycles desired for the sampling window for that SOC. Thus, a value of 15 in this field will give 16 clock cycles of sample time. The minimum number of sample cycles allowed is 7 (ACQPS=6). The total sampling time is found by adding the sample window size to the conversion time of the ADC, 13 ADC clocks. Examples of various sample times are shown below in Table 1. Table 1. Sample timings with different values of ACQPS ADC Clock ACQPS Sample Window Conversion Time (13 cycles) Total Time to Process Analog Voltage(1) 60MHz 6 116.67ns 216.67ns 333.34ns 60MHz 8 150.00ns 216.67ns 366.67ns 60MHz 10 183.33ns 216.67ns 400.00ns 60MHz 14 250.00ns 216.67ns 466.67ns 60MHz 25 433.33ns 216.67ns 650.00ns 40MHz 6 175 325ns 500.00ns 40MHz 25 625 325ns 950.00ns (1) The total times are for a single conversion and do not include pipelining effects that increase the average speed over time. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 11 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com As shown in Figure 3 , the ADCIN pins can be modeled as an RC circuit. With VREFLO connected to ground, a voltage swing from 0 to 3.3v on ADCIN yields a typical RC time constant of 2ns. Figure 3. ADCINx Input Model RS ADCIN Ron 3.4 kΩ Switch Source Signal ac Cp 5 pF Typical Values of the Input Circuit Components: Switch Resistance (Ron): 3.4 kΩ Sampling Capacitor (Ch): 1.6 pF Parasitic Capacitance (Cp): 5 pF Source Resistance (RS): 50 Ω Ch 1.6 pF 28x DSP 1.3.2 Trigger Operation Each SOC can be configured to start on one of many input triggers. Multiple SOC’s can be configured for the same channel if desired. Following is a list of the available input triggers: • Software • CPU Timers 0/1/2 interrupts • XINT2 SOC • ePWM1-7 SOCA and SOCB See the ADCSOCxCTL Register Bit Definitions for the configuration details of these triggers. Additionally ADCINT1 and ADCINT2 can be fed back to trigger another conversion. This configuration is controlled in the ADCINTSOCSEL1/2 registers. This mode is useful if a continuous stream of conversions is desired. See section 1.6 for information on the ADC interrupt signals. 1.3.3 Channel Selection Each SOC can be configured to convert any of the available ADCIN input channels. When an SOC is configured for sequential sampling mode, the four bit CHSEL field of the ADCSOCxCTL register defines which channel to convert. When an SOC is configured for simultaneous sampling mode, the most significant bit of the CHSEL field is dropped and the lower three bits determine which pair of channels are converted. ADCINA0 is shared with VREFHI, and therefore cannot be used as a variable input source when using external reference voltage mode. See Section 1.9 for details on this mode. 1.4 ADC Conversion Priority When multiple SOC flags are set at the same time, one of two forms of priority determines the order in which they are converted. The default priority method is round robin. In this scheme, no SOC has an inherent higher priority than another. Priority depends on the round robin pointer (RRPOINTER). The RRPOINTER reflected in the ADCSOCPRIORITYCTL register points to the last SOC converted. The highest priority SOC is given to the next value greater than the RRPOINTER value, wrapping around back to SOC0 after SOC15. At reset the value is 32 since 0 indicates a conversion has already occurred. When RRPOINTER equals 32 the highest priority is given to SOC0. The RRPOINTER is reset by a device reset, when the ADCCTL1.RESET bit is set, or when the SOCPRICTL register is written. 12 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com An example of the round robin priority method is given in Figure 4 . Analog-to-Digital Converter (ADC) Figure 4. Round Robin Priority Example A After reset, SOC0 is highest priority SOC ; SOC7 receives trigger ; SOC7 configured channel is converted immediately . A SOC SOC 0 SOC 15 1 SOC SOC 14 2 B RRPOINTER changes to point to SOC 7; SOC 13 SOC 3 SOC8 is now highest priority SOC . C SOC2 & SOC12 triggers rcvd . simultaneously ; SOC12 is first on round robin wheel ; SOC12 configured channel is converted while SOC2 stays pending . SOC 12 SOC 11 RRPOINTER (default = 32) SOC 4 SOC 5 D RRPOINTER changes to point to SOC 12; SOC2 configured channel is now converted . E RRPOINTER changes to point to SOC 2; SOC3 is now highest priority SOC . SOC 10 SOC 9 SOC 8 SOC 7 SOC 6 B SOC 15 SOC 14 SOC 13 SOC 0 SOC 1 SOC 2 SOC 3 SOC 12 RRPOINTER (value = 7) SOC 4 SOC 11 SOC 10 SOC 9 SOC 8 SOC 5 SOC 7 SOC 6 C SOC 15 SOC 14 SOC 13 SOC 0 SOC 1 SOC 2 SOC 3 SOC 12 RRPOINTER (value = 7) SOC 4 SOC 11 SOC 10 SOC 9 SOC 8 SOC 5 SOC 7 SOC 6 D SOC 15 SOC 14 SOC 13 SOC 0 SOC 1 SOC 2 SOC 3 E SOC 15 SOC 14 SOC 13 SOC 0 SOC 1 SOC 2 SOC 3 SOC 12 RRPOINTER (value = 12) SOC 4 SOC 12 RRPOINTER (value = 2) SOC 4 SOC 11 SOC 10 SOC 9 SOC 8 SOC 5 SOC 7 SOC 6 SOC 11 SOC 10 SOC 9 SOC 8 SOC 5 SOC 7 SOC 6 The SOCPRIORITY field in the ADCSOCPRIORITYCTL register can be used to assign high priority from a single to all of the SOC’s. When configured as high priority, an SOC will interrupt the round robin wheel after any current conversion completes and insert itself in as the next conversion. After its conversion completes, the round robin wheel will continue where it was interrupted. If two high priority SOC’s are triggered at the same time, the SOC with the lower number will take precedence. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 13 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com High priority mode is assigned first to SOC0, then in increasing numerical order. The value written in the SOCPRIORITY field defines the first SOC that is not high priority. In other words, if a value of 4 is written into SOCPRIORITY, then SOC0, SOC1, SOC2, and SOC3 are defined as high priority, with SOC0 the highest. An example using high priority SOC’s is given in Figure 5 . Figure 5. High Priority Example Example when SOCPRIORITY = 4 A After reset, SOC4 is 1st on round robin wheel ; SOC7 receives trigger ; SOC7 configured channel is converted immediately . B RRPOINTER changes to point to SOC 7; SOC8 is now 1st on round robin wheel . C SOC2 & SOC12 triggers rcvd . simultaneously ; SOC2 interrupts round robin wheel and SOC 2 configured channel is converted while SOC 12 stays pending . D RRPOINTER stays pointing to 7; SOC12 configured channel is now converted . E RRPOINTER changes to point to SOC 12; SOC13 is now 1st on round robin wheel . A High Priority SOC 0 SOC 1 SOC 2 SOC 3 SOC 14 SOC 13 SOC 12 SOC 15 SOC 4 SOC 5 SOC 6 RRPOINTER (default = 32) SOC 7 SOC 8 SOC 11 SOC 10 SOC 9 B High Priority SOC 0 SOC 1 SOC 2 SOC 3 SOC 14 SOC 13 SOC 12 SOC 15 SOC 4 SOC 5 RRPOINTER (value = 7) SOC 6 SOC 7 SOC 8 SOC 11 SOC 10 SOC 9 C High Priority SOC 0 SOC 1 SOC 2 SOC 3 SOC 14 SOC 13 SOC 12 SOC 15 SOC 4 SOC 5 SOC 6 RRPOINTER (value = 7) SOC 7 SOC 8 SOC 11 SOC 10 SOC 9 D High Priority SOC 0 SOC 1 SOC 2 SOC 3 SOC 14 SOC 13 SOC 12 SOC 15 SOC 4 SOC 5 RRPOINTER (value = 7) SOC 6 SOC 7 SOC 8 SOC 11 SOC 10 SOC 9 E High Priority SOC 0 SOC 1 SOC 2 SOC 3 SOC 14 SOC 13 SOC 12 SOC 15 SOC 4 SOC 5 SOC 6 RRPOINTER (value = 12) SOC 7 SOC 8 SOC 11 SOC 10 SOC 9 14 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) 1.5 Simultaneous Sampling Mode In some applications it is important to keep the delay between the sampling of two signals minimal. The ADC contains dual sample and hold circuits to allow two different channels to be sampled simultaneously. Simultaneous sampling mode is configured for a pair of SOCx's with the ADCSAMPLEMODE register. The even numbered SOCx and the following odd numbered SOCx (i.e., SOC0 and SOC1) are coupled together with one enable bit (SIMULEN0, in this case). The coupling behavior is as follows: • Either SOCx’s trigger will start a pair of conversions. • The pair of channels converted will consist of the A-channel and the B-channel corresponding to the value of the CHSEL field of the triggered SOCx. The valid values in this mode are 0-7. • Both channels will be sampled simultaneously. • The A channel will always convert first. • The even EOCx pulse will be generated based off of the A-channel conversion, the odd EOCx pulse will be generated off of the B-channel conversion. See Section 1.6 for an explanation of the EOCx signals. • The result of the A-channel conversion is placed in the even ADCRESULTx register and the result of the B-channel conversion is written to the odd ADCRESULTx register. For example, if the ADCSAMPLEMODE.SIMULEN0 bit is set, and SOC0 is configured as follows: CHSEL = 2 (ADCINA2/ADCINB2 pair) TRIGSEL = 5 (ADCTRIG5 = ePWM1.ADCSOCA) When the ePWM1 sends out an ADCSOCA trigger, both ADCINA2 and ADCINB2 will be sampled simultaneously (assuming priority). Immediately after, the ADCINA2 channel will be converted and its value will be stored in the ADCRESULT0 register. Depending on the ADCCTL1.INTPULSEPOS setting, the EOC0 pulse will either occur when the conversion of ADCINA2 begins or completes. Then the ADCINB2 channel will be converted and its value will be stored in the ADCRESULT1 register. Depending on the ADCCTL1.INTPULSEPOS setting, the EOC1 pulse will either occur when the conversion of ADCINB2 begins or completes. Typically in an application it is expected that only the even SOCx of the pair will be used. However, it is possible to use the odd SOCx instead, or even both. In the latter case, both SOCx triggers will start a conversion. Therefore, caution is urged as both SOCx's will store their results to the same ADCRESULTx registers, possibly overwriting each other. The rules of priority for the SOCx’s remain the same as in sequential sampling mode. Section 1.11 shows the timing of simultaneous sampling mode. 1.6 EOC and Interrupt Operation Just as there are 16 independent SOCx configuration sets, there are 16 EOCx pulses. In sequential sampling mode, the EOCx is associated directly with the SOCx. In simultaneous sampling mode, the even and the following odd EOCx pair are associated with the even and the following odd SOCx pair, as described in Section 1.5. Depending on the ADCCTL1.INTPULSEPOS setting, the EOCx pulse will occur either at the beginning of a conversion or the end. See section 1.11 for exact timings on the EOCx pulses. The ADC contains 9 interrupts that can be flagged and/or passed on to the PIE. Each of these interrupts can be configured to accept any of the available EOCx signals as its source. The configuration of which EOCx is the source is done in the INTSELxNy registers. Additionally, the ADCINT1 and ADCINT2 signals can be configured to generate an SOCx trigger. This is beneficial to creating a continuous stream of conversions. Figure 6 shows a block diagram of the interrupt structure of the ADC. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 15 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) Figure 6. Interrupt Structure INT9 ININTIN3TT21 www.ti.com EOC EOC15:EOC0 ADC Sample Generation Logic INTSEL1N2.INT1SEL INTSEL1N2.INT1E 0 1 2 1 0 15 ADCINTFLGCLR.ADCINT1 INTSEL1N2.INT1CONT Set Latch Clear 1 0 INTOVF ADCINTFLG.ADCINT1 ADCINT1 to PIE 1.7 Power Up Sequence The ADC resets to the ADC off state. Before writing to any of the ADC registers the ADCENCLK bit in the PCLKCR0 register must be set. For a description of the PCLKCR0 register see the TMS320F2802x Piccolo System Control Reference Guide (SPRUFN3). When powering up the ADC, use the following sequence: 1. If an external reference is desired, enable this mode using bit 3 (ADCREFSEL) in the ADCCTL1 register. 2. Power up the reference, bandgap, and analog circuits together by setting bits 7-5 (ADCPWDN, ADCBGPWD, ADCREFPWD) in the ADCCTL1 register. Intermediary states are not currently supported. 3. Enable the ADC by setting bit 14 (ADCENABLE) of the ADCCTL1 register. 4. Before performing the first conversion, a delay of 1 millisecond after step 2 is required. Alternatively, steps 1 through 3 can be performed simultaneously. When powering down the ADC, all three bits in step 2 can be cleared simultaneously. The ADC power levels must be controlled via software and they are independent of the state of the device power modes. NOTE: This type ADC requires a 1ms delay after all of the circuits are powered up. This differs from the previous type ADC's. 1.8 ADC Calibration Inherent in any converter is a zero offset error and a full scale gain error. The ADC is factory calibrated at 25-degrees Celsius to correct both of these while allowing the user to modify the offset correction for any application environmental effects, such as the ambient temperature. Except under certain emulation conditions, or unless a modification from the factory settings is desired, the user is not required to perform any specific action. The ADC will be properly calibrated during the device boot process. 16 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) 1.8.1 Factory Settings and Calibration Function During the fabrication and test process Texas Instruments calibrates several ADC settings along with a couple of internal oscillator settings. These settings are embedded into the TI reserved OTP memory as part of a C-callable function named Device_cal(). Called during the startup boot procedure in the Boot ROM this function writes the factory settings into their respective active registers. Until this occurs, the ADC and the internal oscillators will not adhere to their specified parameters. If the boot process is skipped during emulation, the user must ensure the trim settings are written to their respective registers to ensure the ADC and the internal oscillators meet the specifications in the datasheet. This can be done either by calling this function manually or in the application itself, or by a direct write via CCS. A gel function is provided as part of the C2802x C/C++ Header Files and Peripheral Examples (SPRC823) to accomplish this. For more information on the Device_cal() function refer to the TMS320x2802x Boot ROM Reference Guide (SPRUFN6). Texas Instruments cannot guarantee the parameters specified in the datasheet if a value other than the factory settings contained in the TI reserved OTP memory is written into the ADC trim registers. 1.8.2 ADC Zero Offset Calibration Zero offset error is defined as the resultant digital value that occurs when converting a voltage at VREFLO. This base error affects all conversions of the ADC and together with the full scale gain and linearity specifications, determine the DC accuracy of a converter. The zero offset error can be positive, meaning that a positive digital value is output when VREFLO is presented, or negative, meaning that a voltage higher than a one step above VREFLO still reads as a digital zero value. To correct this error, the two's complement of the error is written into the ADCOFFTRIM register. The value contained in this register will be applied before the results are available in the ADC result registers. This operation is fully contained within the ADC core, so the timing for the results will not be affected and the full dynamic range of the ADC will be maintained for any trim value. Calling the Device_cal() function writes the ADCOFFTRIM register with the factory calibrated offset error correction, but the user can modify the ADCOFFTRIM register to compensate for additional offset error induced by the application environment. This can be done without sacrificing an ADC channel by using the VREFLOCONV bit in the ADCCTRL1 register. Use the following procedure to re-calibrate the ADC offset: 1. Set ADCOFFTRIM to 80 (50h). This adds an artificial offset to account for negative offset that may reside in the ADC core. 2. Set ADCCTL1.VREFLOCONV to 1. This internally connects VREFLO to input channel B5. See the ADCCTL1 register description for more details. 3. Perform multiple conversions on B5 (i.e. sample VREFLO) and take an average to account for board noise. See Section 1.3 on how to setup and initiate the ADC to sample B5. 4. Set ADCOFFTRIM to 80 (50h) minus the average obtained in step 3. This removes the artificial offset from step 1 and creates a two's compliment of the offset error. 5. Set ADCCTL1.VREFLOCONV to 0. This connects B5 back to the external ADCINB5 input pin. NOTE: The "AdcOffsetSelfCal()" function located in DSP2802x(3x)_Adc.c in the common header files performs t hese steps. 1.8.3 ADC Full Scale Gain Calibration Gain error occurs as an incremental error as the voltage input is increased. Full scale gain error occurs at the maximum input voltage. As in offset error, gain error can be positive or negative. A positive full scale gain error means that the full scale digital result is reached before the maximum voltage is input. A negative full scale error implies that the full digital result will never be achieved. The calibration function Device_cal() writes a factory trim value to correct the ADC full scale gain error into the ADCREFTRIM register. This register should not be modified after the Device_cal() function is called. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 17 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com 1.8.4 ADC Bias Current Calibration To further increase the accuracy of the ADC, the calibration function Device_cal() also writes a factory trim value to an ADC register for the ADC bias currents. This register should not be modified after the Device_cal() function is called. 1.9 Internal/External Reference Voltage Selection 1.9.1 Internal Reference Voltage The ADC can operate in two different reference modes, selected by the ADCCTL1.ADCREFSEL bit. By default the internal bandgap is chosen to generate the reference voltage for the ADC. This will convert the voltage presented according to a fixed scale 0 to 3.3v range. The equation governing conversions in this mode is: Digital Value = 0 when Input ≤ 0v Digital Value = 4096 [(Input – VREFLO)/3.3v] when 0v < Input < 3.3v Digital Value = 4095, when Input ≥ 3.3v *All fractional values are truncated **VREFLO must be tied to ground in this mode. This is done internally on some devices. 1.9.2 External Reference Voltage To convert the voltage presented as a ratiometric signal, the external VREFHI/VREFLO pins should be chosen to generate the reference voltage. In contrast with the fixed 0 to 3.3v input range of the internal bandgap mode, the ratiometric mode has an input range from VREFLO to VREFHI. Converted values will scale to this range. For instance, if VREFLO is set to 0.5v and VREFHI is 3.0v, a voltage of 1.75v will be converted to the digital result of 2048. See the device datasheet for the allowable ranges of VREFLO and VREFHI. On some devices VREFLO is tied to ground internally, and hence limited to 0v. The equation governing the conversions in this mode is: Digital Value = 0 Digital Value = 4096 [(Input – VREFLO)/(VREFHI – VREFLO)] Digital Value = 4095, *All fractional values are truncated when Input ≤ VREFLO when VREFLO < Input < VREFHI when Input ≥ VREFHI 18 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) 1.10 ADC Registers This section contains the ADC registers and bit definitions with the registers grouped by function. All of the ADC registers are located in Peripheral Frame 2 except the ADCRESULTx registers, which are found in Peripheral Frame 0. See the device datasheet for specific addresses. Table 2. ADC Configuration & Control Registers (AdcRegs and AdcResult): Register Name Address Offset Size Description (x16) ADCCTL1 0x00 1 Control 1 Register(1) ADCINTFLG 0x04 1 Interrupt Flag Register ADCINTFLGCLR 0x05 1 Interrupt Flag Clear Register ADCINTOVF 0x06 1 Interrupt Overflow Register ADCINTOVFCLR 0x07 1 Interrupt Overflow Clear Register INTSEL1N2 0x08 1 Interrupt 1 and 2 Selection Register(1) INTSEL3N4 0x09 1 Interrupt 3 and 4 Selection Register(1) INTSEL5N6 0x0A 1 Interrupt 5 and 6 Selection Register(1) INTSEL7N8 0x0B 1 Interrupt 7 and 8 Selection Register(1) INTSEL9N10 0x0C 1 Interrupt 9 Selection Register (reserved Interrupt 10 Selection)(1) SOCPRICTL 0x10 1 SOC Priority Control Register(1) ADCSAMPLEMODE 0x12 1 Sampling Mode Register(1) ADCINTSOCSEL1 0x14 1 Interrupt SOC Selection 1 Register (for 8 channels)(1) ADCINTSOCSEL2 0x15 1 Interrupt SOC Selection 2 Register (for 8 channels)(1) ADCSOCFLG1 0x18 1 SOC Flag 1 Register (for 16 channels) ADCSOCFRC1 0x1A 1 SOC Force 1 Register (for 16 channels) ADCSOCOVF1 0x1C 1 SOC Overflow 1 Register (for 16 channels) ADCSOCOVFCLR1 0x1E 1 SOC Overflow Clear 1 Register (for 16 channels) ADCSOC0CTL - ADCSOC15CTL 0x20 - 0x2F 1 SOC0 Control Register to SOC15 Control Register(1) ADCREFTRIM 0x40 1 Reference Trim Register(1) ADCOFFTRIM 0x41 1 Offset Trim Register(1) ADCREV – reserved 0x4F 1 Revision Register ADCRESULT0 - ADCRESULT15 0x00 - 0x0F(2) 1 ADC Result 0 Register to ADC Result 15 Register (1) This register is EALLOW protected. (2) The base address of the ADCRESULT registers differs from the base address of the other ADC registers. In the header files, the ADCRESULT registers are found in the AdcResult register file, not AdcRegs. 1.10.1 ADC Control Register 1 (ADCCTL1) NOTE: The following ADC Control Register is EALLOW protected. 15 RESET R-0/W-1 Figure 7. ADC Control Register 1 (ADCCTL1) (Address Offset 00h) 14 13 12 ADCENABLE ADCBSY ADCBSYCHN R/W-0 R-0 R-0 7 6 5 4 3 2 1 ADCPWN ADCBGPWD ADCREFPWD Reserved ADCREFSEL INTPULSEPOS VREFLO CONV R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; R-0/W-1 = always read as 0, write 1 to set; -n = value after reset 8 0 TEMPCONV R/W-0 SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 19 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) Table 3. ADC Control Register 1 (ADCCTL1) Field Descriptions www.ti.com Bit Field 15 RESET 14 ADCENABLE 13 ADCBSY 12-8 ADCBSYCHN Value Description ADC module software reset. This bit causes a master reset on the entire ADC module. All register bits and state machines are reset to the initial state as occurs when the device reset pin is pulled low (or after a power-on reset). This is a one-time-effect bit, meaning this bit is self-cleared immediately after it is set to 1. Read of this bit always returns a 0. Also, the reset of ADC has a latency of two clock cycles (that is, other ADC control register bits should not be modified until two clock cycles after the instruction that resets the ADC. 0 no effect 1 Resets entire ADC module (bit is then set back to 0 by ADC logic) Note: The ADC module is reset during a system reset. If an ADC module reset is desired at any other time, you can do so by writing a 1 to this bit. After two clock cycles, you can then write the appropriate values to the ADCCTL1 register bits. Assembly code: MOV ADCCTL1, #1xxxxxxxxxxxxxxxb ; Resets the ADC (RESET = 1) NOP ; Delay two cycles NOP MOV ADCCTL1, #0xxxxxxxxxxxxxxxb ; Set to user-desired value Note: The second MOV is not required if the default configuration is sufficient. ADC Enable 0 ADC disabled (does not power down ADC) 1 ADC Enabled. Musts set before an ADC conversion (recommend that it be set directly after setting ADC power-up bits ADC Busy Set when ADC SOC is generated, cleared per below. Used by the ADC state machine to determine if ADC is avaliable to sample. Sequential Mode: Cleared 4 ADC clocks after negative edge of S/H pulse Simultaneous Mode: Cleared 14 ADC clocks after negative edge of S/H pulse 0 ADC is available to sample next channel 1 ADC is busy and cannot sample another channel Set when ADC SOC for current channel is generated When ADCBSY = 0: holds the value of the last converted channel When ADCBSY = 1: reflects channel currently being processed 00h ADCINA0 is currently processing or was last channel converted 01h ADCINA1 is currently processing or was last channel converted 02h ADCINA2 is currently processing or was last channel converted 03h ADCINA3 is currently processing or was last channel converted 04h ADCINA4 is currently processing or was last channel converted 05h ADCINA5 is currently processing or was last channel converted 06h ADCINA6 is currently processing or was last channel converted 07h ADCINA7 is currently processing or was last channel converted 08h ADCINB0 is currently processing or was last channel converted 09h ADCINB1 is currently processing or was last channel converted 0Ah ADCINB2 is currently processing or was last channel converted 0Bh ADCINB3 is currently processing or was last channel converted 0Ch ADCINB4 is currently processing or was last channel converted 0Dh ADCINB5 is currently processing or was last channel converted 0Eh ADCINB6 is currently processing or was last channel converted 0Fh ADCINB7 is currently processing or was last channel converted 1xh Invalid value 20 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) Table 3. ADC Control Register 1 (ADCCTL1) Field Descriptions (continued) Bit Field 7 ADCPWDN 6 ADCBGPWD 5 ADCREFPWD 4 Reserved 3 ADCREFSEL 2 INTPULSEPOS 1 VREFLOCONV 0 TEMPCONV Value Description ADC power down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core except the bandgap and reference circuitry 0 All analog circuitry inside the core except the bandgap and referencce circuitry is powered down 1 The analog circuitry inside the core is powered up Bandgap circuit power down (active low) 0 Bandgap circuitry is powered down 1 Bandgap buffer's curcuitry inside core is powered up Reference buffers circuit power down (active low) 0 Reference buffers circuitry is powered down 1 Reference buffers circuitry inside the core is powered up 0 Reads return a zero; Writes have no effect. Internal/external reference select 0 Internal Bandgap used for reference generation 1 External VREFHI/VREFLO pins used for reference generation. On some devices the VREFHI pin is shared with ADCINA0. In this case ADCINA0 will not be available for conversions in this mode. On some devices the VREFLO pin is shared with VSSA. In this case the VREFLO voltage cannot be varied. INT Pulse Generation control 0 INT pulse generation occurs when ADC begins conversion (neg edge of sample pulse od the sampled signal) 1 INT pulse generation occurs 1 cycle prior to ADC result latching into its result register VREFLO Convert. When enabled, internally connects VREFLO to the ADC channel B5 and disconnects the ADCINB5 pin from the ADC. Whether the pin ADCINB5 exists on the device does not affect this function. Any external circuitry on the ADCINB5 pin is unaffected by this mode. 0 ADCINB5 is passed to the ADC module as normal, VREFLO connection to ADCINB5 is disabled 1 VREFLO internally connected to the ADC for sampling Temperature sensor convert. When enabled internally connects the internal temperature sensor to ADC channel A5 and disconnects the ADCINA5 pin from the ADC. Whether the pin ADCINA5 exists on the device does not affect this function. Any external circuitry on the ADCINA5 pin is uneffected by this mode 0 ADCINA5 is passed to the ADC module as normal, internal temperature sensor connection to ADCINA5 is disabled. 1 Temperature sensor is internally connected to the ADC for sampling 1.10.2 ADC Interrupt Registers Figure 8. ADC Interrupt Flag Register (ADCINTFLG) (Address Offset 04h) 15 9 Reserved R-0 7 6 5 4 ADCINT8 ADCINT7 ADCINT6 ADCINT5 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 3 ADCINT4 R-0 2 ADCINT3 R-0 1 ADCINT2 R-0 8 ADCINT9 R-0 0 ADCINT1 R-0 Bit Field 15-9 Reserved Table 4. ADC Interrupt Flag Register (ADCINTFLG) Field Descriptions Value Description 0 Reads return a zero; Writes have no effect. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 21 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com Table 4. ADC Interrupt Flag Register (ADCINTFLG) Field Descriptions (continued) Bit Field 8-0 ADCINTx (x = 9 to 1) Value 0 1 Description ADC Interrupt Flag Bits: Reading this bit indicates if an ADCINT pulse was generated No ADC interrupt pulse generated ADC Interrupt pulse generated If the ADC interrupt is placed in continuous mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Figure 9. ADC Interrupt Flag Clear Register (ADCINTFLGCLR) (Address Offset 05h) 15 9 8 Reserved ADCINT9 R-0 R/W-0 7 6 5 4 ADCINT8 ADCINT7 ADCINT6 ADCINT5 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 3 ADCINT4 R/W-0 2 ADCINT3 R/W-0 1 ADCINT2 R/W-0 0 ADCINT1 R/W-0 Table 5. ADC Interrupt Flag Clear Register (ADCINTFLGCLR) Field Descriptions Bit 15-9 8-0 Field Reserved ADCINTx (x = 9 to 1) Value 0 0 1 Description Reads return a zero; Writes have no effect. ADC interrupt Flag Clear Bit No action. Clears respective flag bit in the ADCINTFLG register. If software tries to set this bit on the same clock cycle that hardware tries to set the flag bit in the ADCINTFLG register, then hardware has priority and the ADCINTFLG bit will be set. In this case the overflow bit in the ADCINTOVF register will not be affected regardless of whether the ADCINTFLG bit was previously set or not. Figure 10. ADC Interrupt Overflow Register (ADCINTOVF) (Address Offset 06h) 15 9 8 Reserved ADCINT9 R-0 R-0 7 6 5 4 ADCINT8 ADCINT7 ADCINT6 ADCINT5 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 3 ADCINT4 R-0 2 ADCINT3 R-0 1 ADCINT2 R-0 0 ADCINT1 R-0 Table 6. ADC Interrupt Overflow Register (ADCINTOVF) Field Descriptions Bit 15-9 8-0 Field Reserved ADCINTx (x = 9 to 1) Value 0 0 1 Description Reserved ADC Interrupt Overflow Bits. Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. No ADC interrupt overflow event detected. ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. 22 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) Figure 11. ADC Interrupt Overflow Clear Register (ADCINTOVFCLR) (Address Offset 07h) 15 9 8 Reserved ADCINT9 R-0 R-0/W-1 7 6 5 4 3 2 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 R-0/W-1 R-0/W-1 R-0/W-1 R-0/W-1 R-0/W-1 R-0/W-1 LEGEND: R/W = Read/Write; R = Read only; R-0/W-1 =always read 0, write 1 to set; -n = value after reset 1 ADCINT2 R-0/W-1 0 ADCINT1 R-0/W-1 Table 7. ADC Interrupt Overflow Clear Register (ADCINTOVFCLR) Field Descriptions Bit 15-9 8-0 Field Reserved ADCINTx (x = 9 to 1) Value 0 0 1 Description Reads return a zero; Writes have no effect. ADC Interrupt Overflow Clear Bits. No action. Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. NOTE: The following Interrupt Select Registers are EALLOW protected. 15 Reserved R-0 Figure 12. Interrupt Select 1 And 2 Register (INTSEL1N2) (Address Offset 08h) 14 13 12 8 INT2CONT INT2E INT2SEL R/W-0 R/W-0 R/W-0 7 6 5 4 0 Reserved INT1CONT INT1E INT1SEL R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 15 Reserved R-0 Figure 13. Interrupt Select 3 And 4 Register (INTSEL3N4) (Address Offset 09h) 14 13 12 8 INT4CONT INT4E INT4SEL R/W-0 R/W-0 R/W-0 7 6 5 4 0 Reserved INT3CONT INT3E INT3SEL R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 15 Reserved R-0 Figure 14. Interrupt Select 5 And 6 Register (INTSEL5N6) (Address Offset 0Ah) 14 13 12 8 INT6CONT INT6E INT6SEL R/W-0 R/W-0 R/W-0 7 6 5 4 0 Reserved INT5CONT INT5E INT5SEL R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 23 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com 15 Reserved R-0 Figure 15. Interrupt Select 7 And 8 Register (INTSEL7N8) (Address Offset 0Bh) 14 13 12 8 INT8CONT INT8E INT8SEL R/W-0 R/W-0 R/W-0 7 6 5 4 0 Reserved INT7CONT INT7E INT7SEL R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 16. Interrupt Select 9 And 10 Register (INTSEL9N10) (Address Offset 0Ch) 15 8 Reserved R-0 7 6 5 4 0 Reserved INT9CONT INT9E INT9SEL R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Bit Field 15 Reserved 14 INTyCONT 13 INTyE 12-8 INTySEL 7 Reserved Table 8. INTSELxNy Register Field Descriptions Value 0 0 1 0 1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 1xh 0 Description Reserved ADCINTy Continuous Mode Enable No further ADCINTy pulses are generated until ADCINTy flag (in ADCINTFLG register) is cleared by user. ADCINTy pulses are generated whenever an EOC pulse is generated irrespective if the flag bit is cleared or not. ADCINTy Interrupt Enable ADCINTy is disabled. ADCINTy is enabled. ADCINTy EOC Source Select EOC0 is trigger for ADCINTy EOC1 is trigger for ADCINTy EOC2 is trigger for ADCINTy EOC3 is trigger for ADCINTy EOC4 is trigger for ADCINTy EOC5 is trigger for ADCINTy EOC6 is trigger for ADCINTy EOC7 is trigger for ADCINTy EOC8 is trigger for ADCINTy EOC9 is trigger for ADCINTy EOC10 is trigger for ADCINTy EOC11 is trigger for ADCINTy EOC12 is trigger for ADCINTy EOC13 is trigger for ADCINTy EOC14 is trigger for ADCINTy EOC15 is trigger for ADCINTy Invalid value. Reads return a zero; Writes have no effect. 24 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Bit Field 6 INTxCONT 5 INTxE 4-0 INTxSEL Analog-to-Digital Converter (ADC) Table 8. INTSELxNy Register Field Descriptions (continued) Value 0 1 0 1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch .0Dh 0Eh 0Fh 1xh Description ADCINTx Continuous Mode Enable. No further ADCINTx pulses are generated until ADCINTx flag (in ADCINTFLG register) is cleared by user. ADCINTx pulses are generated whenever an EOC pulse is generated irrespective if the flag bit is cleared or not. ADCINTx Interrupt Enable ADCINTx is disabled. ADCINTx is enabled . ADCINTx EOC Source Select EOC0 is trigger for ADCINTx EOC1 is trigger for ADCINTx EOC2 is trigger for IADCNTx EOC3 is trigger for ADCINTx EOC4 is trigger for ADCINTx EOC5 is trigger for ADCINTx EOC6 is trigger for ADCINTx EOC7 is trigger for ADCINTx EOC8 is trigger for ADCINTx EOC9 is trigger for ADCINTx EOC10 is trigger for ADCINTx EOC11 is trigger for ADCINTx EOC12 is trigger for ADCINTx EOC13 is trigger for ADCINTx EOC14 is trigger for ADCINTx EOC15 is trigger for ADCINTx Invalid value. 1.10.3 ADC Priority Register NOTE: The following SOC Priority Control Register is EALLOW protected. Figure 17. ADC Start of Conversion Priority Control Register (SOCPRICTL) 15 11 10 5 4 0 Reserved RRPOINTER SOCPRIORITY R-0 R-20h R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Bit Field 15-11 Reserved Table 9. SOCPRICTL Register Field Descriptions Value Description Reads return a zero; Writes have no effect. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 25 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com Bit 10-5 4-0 Field RRPOINTER SOCPRIORITY Table 9. SOCPRICTL Register Field Descriptions (continued) Value 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 1xh 20h Others 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h Others Description Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. SOC0 was last round robin SOC to convert. SOC1 is highest round robin priority. SOC1 was last round robin SOC to convert. SOC2 is highest round robin priority. SOC2 was last round robin SOC to convert. SOC3 is highest round robin priority. SOC3 was last round robin SOC to convert. SOC4 is highest round robin priority. SOC4 was last round robin SOC to convert. SOC5 is highest round robin priority. SOC5 was last round robin SOC to convert. SOC6 is highest round robin priority. SOC6 was last round robin SOC to convert. SOC7 is highest round robin priority. SOC7 was last round robin SOC to convert. SOC8 is highest round robin priority. SOC8 was last round robin SOC to convert. SOC9 is highest round robin priority. SOC9 was last round robin SOC to convert. SOC10 is highest round robin priority. SOC10 was last round robin SOC to convert. SOC11 is highest round robin priority. SOC11 was last round robin SOC to convert. SOC12 is highest round robin priority. SOC12 was last round robin SOC to convert. SOC13 is highest round robin priority. SOC13 was last round robin SOC to convert. SOC14 is highest round robin priority. SOC14 was last round robin SOC to convert. SOC15 is highest round robin priority. SOC15 was last round robin SOC to convert. SOC0 is highest round robin priority. Invalid value Reset value to indicate no SOC has been converted. SOC0 is highest round robin priority. Set to this value when the device is reset, when the ADCCTL1.RESET bit is set, or when the SOCPRICTL register is written. In the latter case, if a conversion is currently in progress, it will complete and then the new priority will take effect. Invalid selection. SOC Priority. Determines the cutoff point for priority mode and round robin arbitration for SOCx SOC priority is handled in round robin mode for all channels. SOC0 is high priority, rest of channels are in round robin mode. SOC0-SOC1 are high priority, SOC2-SOC15 are in round robin mode. SOC0-SOC2 are high priority, SOC3-SOC15 are in round robin mode. SOC0-SOC3 are high priority, SOC4-SOC15 are in round robin mode. SOC0-SOC4 are high priority, SOC5-SOC15 are in round robin mode. SOC0-SOC5 are high priority, SOC6-SOC15 are in round robin mode. SOC0-SOC6 are high priority, SOC7-SOC15 are in round robin mode. SOC0-SOC7 are high priority, SOC8-SOC15 are in round robin mode. SOC0-SOC8 are high priority, SOC9-SOC15 are in round robin mode. SOC0-SOC9 are high priority, SOC10-SOC15 are in round robin mode. SOC0-SOC10 are high priority, SOC11-SOC15 are in round robin mode. SOC0-SOC11 are high priority, SOC12-SOC15 are in round robin mode. SOC0-SOC12 are high priority, SOC13-SOC15 are in round robin mode. SOC0-SOC13 are high priority, SOC14-SOC15 are in round robin mode. SOC0-SOC14 are high priority, SOC15 is in round robin mode. All SOCs are in high priority mode, arbitrated by SOC number Invalid selection. 26 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com 1.10.4 ADC SOC Registers Analog-to-Digital Converter (ADC) NOTE: The following ADC Sample Mode Register is EALLOW protected. Figure 18. ADC Sample Mode Register (ADCSAMPLEMODE) (Address Offset 12h) 15 8 Reserved R-0 7 6 5 4 SIMULEN14 SIMULEN12 SIMULEN10 SIMULEN8 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 3 SIMULEN6 R/W-0 2 SIMULEN4 R/W-0 1 SIMULEN2 R/W-0 0 SIMULEN0 R/W-0 Table 10. ADC Sample Mode Register (ADCSAMPLEMODE) Field Descriptions Bit Field 15:8 Reserved 7 SIMULEN14 6 SIMULEN12 5 SIMULEN10 4 SIMULEN8 Value 0 0 1 0 1 0 1 0 1 Description Reserved Simultaneous sampling enable for SOC14/SOC15. Couples SOC14 and SOC15 in simultaneous sampling mode. See section 1.5 for details. This bit should not be set when the ADC is actively converting SOC14 or SOC15. Single sample mode set for SOC14 and SOC15. All bits of CHSEL field define channel to be converted. EOC14 associated with SOC14. EOC15 associated with SOC15. SOC14’s result placed in ADCRESULT14 register. SOC15’s result placed in ADCRESULT15. Simultaneous sample for SOC14 and SOC15. Lowest three bits of CHSEL field define the pair of channels to be converted. EOC14 and EOC15 associated with SOC14 and SOC15 pair. SOC14’s and SOC15’s results will be placed in ADCRESULT14 and ADCRESULT15 registers, respectively. Simultaneous sampling enable for SOC12/SOC13. Couples SOC12 and SOC13 in simultaneous sampling mode. See section 1.5 for details. This bit should not be set when the ADC is actively converting SOC12 or SOC13. Single sample mode set for SOC12 and SOC13. All bits of CHSEL field define channel to be converted. EOC12 associated with SOC12. EOC13 associated with SOC13. SOC12’s result placed in ADCRESULT12 register. SOC13’s result placed in ADCRESULT13. Simultaneous sample for SOC12 and SOC13. Lowest three bits of CHSEL field define the pair of channels to be converted. EOC12 and EOC13 associated with SOC12 and SOC13 pair. SOC12’s and SOC13’s results will be placed in ADCRESULT12 and ADCRESULT13 registers, respectively. Simultaneous sampling enable for SOC10/SOC11. Couples SOC10 and SOC11 in simultaneous sampling mode. See section 1.5 for details. This bit should not be set when the ADC is actively converting SOC10 or SOC11. Single sample mode set for SOC10 and SOC11. All bits of CHSEL field define channel to be converted. EOC10 associated with SOC10. EOC11 associated with SOC11. SOC10’s result placed in ADCRESULT10 register. SOC11’s result placed in ADCRESULT11. Simultaneous sample for SOC10 and SOC11. Lowest three bits of CHSEL field define the pair of channels to be converted. EOC10 and EOC11 associated with SOC10 and SOC11 pair. SOC10’s and SOC11’s results will be placed in ADCRESULT10 and ADCRESULT11 registers, respectively. Simultaneous sampling enable for SOC8/SOC9. Couples SOC8 and SOC9 in simultaneous sampling mode. See section 1.5 for details. This bit should not be set when the ADC is actively converting SOC8 or SOC9. Single sample mode set for SOC8 and SOC9. All bits of CHSEL field define channel to be converted. EOC8 associated with SOC8. EOC9 associated with SOC9. SOC8’s result placed in ADCRESULT8 register. SOC9’s result placed in ADCRESULT9. Simultaneous sample for SOC8 and SOC9. Lowest three bits of CHSEL field define the pair of channels to be converted. EOC8 and EOC9 associated with SOC8 and SOC9 pair. SOC8’s and SOC9’s results will be placed in ADCRESULT8 and ADCRESULT9 registers, respectively. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 27 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com Table 10. ADC Sample Mode Register (ADCSAMPLEMODE) Field Descriptions (continued) Bit Field 3 SIMULEN6 2 SIMULEN4 1 SIMULEN2 0 SIMULEN0 Value 0 1 0 1 0 1 0 1 Description Simultaneous sampling enable for SOC6/SOC7. Couples SOC6 and SOC7 in simultaneous sampling mode. See section 1.5 for details. This bit should not be set when the ADC is actively converting SOC6 or SOC7. Single sample mode set for SOC6 and SOC7. All bits of CHSEL field define channel to be converted. EOC6 associated with SOC6. EOC7 associated with SOC7. SOC6’s result placed in ADCRESULT6 register. SOC7’s result placed in ADCRESULT7. Simultaneous sample for SOC6 and SOC7. Lowest three bits of CHSEL field define the pair of channels to be converted. EOC6 and EOC7 associated with SOC6 and SOC7 pair. SOC6’s and SOC7’s results will be placed in ADCRESULT6 and ADCRESULT7 registers, respectively. Simultaneous sampling enable for SOC4/SOC5. Couples SOC4 and SOC5 in simultaneous sampling mode. See section 1.5 for details. This bit should not be set when the ADC is actively converting SOC4 or SOC5. Single sample mode set for SOC4 and SOC5. All bits of CHSEL field define channel to be converted. EOC4 associated with SOC4. EOC5 associated with SOC5. SOC4’s result placed in ADCRESULT4 register. SOC5’s result placed in ADCRESULT5. Simultaneous sample for SOC4 and SOC5. Lowest three bits of CHSEL field define the pair of channels to be converted. EOC4 and EOC5 associated with SOC4 and SOC5 pair. SOC4’s and SOC5’s results will be placed in ADCRESULT4 and ADCRESULT5 registers, respectively. Simultaneous sampling enable for SOC2/SOC3. Couples SOC2 and SOC3 in simultaneous sampling mode. See section 1.5 for details. This bit should not be set when the ADC is actively converting SOC2 or SOC3. Single sample mode set for SOC2 and SOC3. All bits of CHSEL field define channel to be converted. EOC2 associated with SOC2. EOC3 associated with SOC3. SOC2’s result placed in ADCRESULT2 register. SOC3’s result placed in ADCRESULT3. Simultaneous sample for SOC2 and SOC3. Lowest three bits of CHSEL field define the pair of channels to be converted. EOC2 and EOC3 associated with SOC2 and SOC3 pair. SOC2’s and SOC3’s results will be placed in ADCRESULT2 and ADCRESULT3 registers, respectively. Simultaneous sampling enable for SOC0/SOC1. Couples SOC0 and SOC1 in simultaneous sampling mode. See section 1.5 for details. This bit should not be set when the ADC is actively converting SOC0 or SOC1. Single sample mode set for SOC0 and SOC1. All bits of CHSEL field define channel to be converted. EOC0 associated with SOC0. EOC1 associated with SOC1. SOC0’s result placed in ADCRESULT0 register. SOC1’s result placed in ADCRESULT1. Simultaneous sample for SOC0 and SOC1. Lowest three bits of CHSEL field define the pair of channels to be converted. EOC0 and EOC1 associated with SOC0 and SOC1 pair. SOC0’s and SOC1’s results will be placed in ADCRESULT0 and ADCRESULT1 registers, respectively. NOTE: The following ADC Interrupt SOC Select Registers are EALLOW protected. Figure 19. ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1) (Address Offset 14h) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOC7 SOC6 SOC5 SOC4 SOC3 SOC2 SOC1 SOC0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11. ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1) Register Field Descriptions Bit 15--0 Field SOCx (x = 7 to 0) Value 00 01 10 11 Description SOCx ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOCx. This field overrides the TRIGSEL field in the ADCSOCxCTL register. No ADCINT will trigger SOCx. TRIGSEL field determines SOCx trigger. ADCINT1 will trigger SOCx. TRIGSEL field is ignored. ADCINT2 will trigger SOCx. TRIGSEL field is ignored. Invalid selection. 28 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) Figure 20. ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2) (Address Offset 15h) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOC15 SOC14 SOC13 SOC12 SOC11 SOC10 SOC9 SOC8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 12. ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2) Field Descriptions Bit 15-0 Field SOCx (x = 15 to 8) Value 00 01 10 11 Description SOCx ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOCx. This field overrides the TRIGSEL field in the ADCSOCxCTL register. No ADCINT will trigger SOCx. TRIGSEL field determines SOCx trigger. ADCINT1 will trigger SOCx. TRIGSEL field is ignored. ADCINT2 will trigger SOCx. TRIGSEL field is ignored. Invalid selection. 15 SOC15 R-0 Figure 21. ADC SOC Flag 1 Register (ADCSOCFLG1) (Address Offset 18h) 14 13 12 11 10 9 SOC14 SOC13 SOC12 SOC11 SOC10 SOC9 R-0 R-0 R-0 R-0 R-0 R-0 7 6 5 4 SOC7 SOC6 SOC5 SOC4 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 3 SOC3 R-0 2 SOC2 R-0 1 SOC1 R-0 8 SOC8 R-0 0 SOC0 R-0 Table 13. ADC SOC Flag 1 Register (ADCSOCFLG1) Field Descriptions Bit 15-0 Field SOCx (x = 15 to 0) Value 0 1 Description SOCx Start of Conversion Flag. Indicates the state of individual SOC conversions. No sample pending for SOCx. Trigger has been received and sample is pending for SOCx. The bit will be automatically cleared when the respective SOCx conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. 15 SOC15 R/W-0 Figure 22. ADC SOC Force 1 Register (ADCSOCFRC1) (Address Offset 1Ah) 14 13 12 11 10 9 SOC14 SOC13 SOC12 SOC11 SOC10 SOC9 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 SOC7 SOC6 SOC5 SOC4 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 3 SOC3 R/W-0 2 SOC2 R/W-0 1 SOC1 R/W-0 8 SOC8 R/W-0 0 SOC0 R/W-0 SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 29 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) Table 14. ADC SOC Force 1 Register (ADCSOCFRC1) Field Descriptions www.ti.com Bit 15-0 Field SOCx (x = 15 to 0) Value 0 1 Description SOCx Force Start of Conversion Flag. Writing a 1 will force to 1 the respective SOCx flag bit in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. No action. Force SOCx flag bit to 1. This will cause a conversion to start once priority is given to SOCx. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOCx bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. 15 SOC15 R-0 Figure 23. ADC SOC Overflow 1 Register (ADCSOCOVF1) (Address Offset 1Ch) 14 13 12 11 10 9 8 SOC14 SOC13 SOC12 SOC11 SOC10 SOC9 SOC8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7 6 5 4 SOC7 SOC6 SOC5 SOC4 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 3 SOC3 R-0 2 SOC2 R-0 1 SOC1 R-0 0 SOC0 R-0 Table 15. ADC SOC Overflow 1 Register (ADCSOCOVF1) Field Descriptions Bit 15-0 Field SOCx (x = 15 to 0) Value 0 1 Description SOCx Start of Conversion Overflow Flag. Indicates an SOCx event was generated while an existing SOCx event was already pending. No SOCx event overflow SOCx event overflow An overflow condition does not stop SOCx events from being processed. It simply is an indication that a trigger was missed Figure 24. ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1) (Address Offset 1Eh) 15 14 13 12 11 10 9 8 SOC15 SOC14 SOC13 SOC12 SOC11 SOC10 SOC9 SOC8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 SOC7 SOC6 SOC5 SOC4 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 3 SOC3 R/W-0 2 SOC2 R/W-0 1 SOC1 R/W-0 0 SOC0 R/W-0 Table 16. ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1) Field Descriptions Bit 15-0 Field SOCx (x = 15 to 0) Value 0 1 Description SOCx Clear Start of Conversion Overflow Flag. Writing a 1 will clear the respective SOCx overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. No action. Clear SOCx overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set. 30 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) NOTE: The following ADC SOC0 - SOC15 Control Registers are EALLOW protected. Figure 25. ADC SOC0 - SOC15 Control Registers (ADCSOCxCTL) (Address Offset 20h - 2Fh) 15 11 10 9 6 5 0 TRIGSEL Reserved CHSEL ACQPS R/W-0 R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17. ADC SOC0 - SOC15 Control Registers (ADCSOCxCTL) Register Field Descriptions Bit Field 15-11 TRIGSEL 10 Reserved Value 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h Others Description SOCx Trigger Source Select. Configures which trigger will set the respective SOCx flag in the ADCSOCFLG1 register to intiate a conversion to start once priority is given to SOCx. This setting can be overridden by the respective SOCx field in the ADCINTSOCSEL1 or ADCINTSOCSEL2 register. ADCTRIG0 - Software only. ADCTRIG1 - CPU Timer 0, TINT0n ADCTRIG2 - CPU Timer 1, TINT1n ADCTRIG3 - CPU Timer 2, TINT2n ADCTRIG4 – XINT2, XINT2SOC ADCTRIG5 – ePWM1, ADCSOCA ADCTRIG6 – ePWM1, ADCSOCB ADCTRIG7 – ePWM2, ADCSOCA ADCTRIG8 – ePWM2, ADCSOCB ADCTRIG9 – ePWM3, ADCSOCA ADCTRIG10 – ePWM3, ADCSOCB ADCTRIG11 – ePWM4, ADCSOCA ADCTRIG12 – ePWM4, ADCSOCB ADCTRIG13 – ePWM5, ADCSOCA ADCTRIG14 – ePWM5, ADCSOCB ADCTRIG15 – ePWM6, ADCSOCA ADCTRIG16 – ePWM6, ADCSOCB ADCTRIG17 - ePWM7, ADCSOCA ADCTRIG18 - ePWM7, ADCSOCB Invalid selection. Reads return a zero; Writes have no effect. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 31 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com Table 17. ADC SOC0 - SOC15 Control Registers (ADCSOCxCTL) Register Field Descriptions (continued) Bit Field 9-6 CHSEL Value 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh Description SOCx Channel Select. Selects the channel to be converted when SOCx is received by the ADC. Sequential Sampling Mode (SIMULENx = 0): ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 Simultaneous Sampling Mode (SIMULENx = 1): ADCINA0/ADCINB0 pair ADCINA1/ADCINB1 pair ADCINA2/ADCINB2 pair ADCINA3/ADCINB3 pair ADCINA4/ADCINB4 pair ADCINA5/ADCINB5 pair ADCINA6/ADCINB6 pair ADCINA7/ADCINB7 pair Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. 32 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) Table 17. ADC SOC0 - SOC15 Control Registers (ADCSOCxCTL) Register Field Descriptions (continued) Bit Field Value Description 5-0 ACQPS SOCx Acquisition Prescale. Controls the sample and hold window for SOCx. Minimum value allowed is 6. 00h Invalid selection. 01h Invalid selection. 02h Invalid selection. 03h Invalid selection. 04h Invalid selection. 05h Invalid selection. 06h Sample window is 7 cycles long (6 + 1 clock cycles). 07h Sample window is 8 cycles long (7 + 1 clock cycles). 08h Sample window is 9 cycles long (8 + 1 clock cycles). 09h Sample window is 10 cycles long (9 + 1 clock cycles). ... ... 3Fh Sample window is 64 cycles long (63 + 1 clock cycles). Other invalid selections: 10h, 11h, 12h, 13h, 14h, 1Dh, 1Eh, 1Fh, 20h, 21h, 2Ah, 2Bh, 2Ch, 2Dh, 2Eh, 37h, 38h, 39h, 3Ah, 3Bh 1.10.5 ADC Calibration Registers NOTE: The following ADC Calibration Registers are EALLOW protected. Figure 26. ADC Reference/Gain Trim Register (ADCREFTRIM) (Address Offset 40h) 15 13 12 8 7 4 3 0 Reserved EXTREF_FINE_TRIM BG_COARSE_TRIM BG_FINE_TRIM R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18. ADC Reference/Gain Trim Register (ADCREFTRIM) Field Descriptions Bit 15-13 12-8 Field Reserved EXTREF_FINE_TRIM 7-4 BG_COARSE_TRIM 3-0 BG_FINE_TRIM Value Description Reads return a zero; Writes have no effect. ADC External reference Fine Trim. These bits should not be modified after device boot code loads them with the factory trim setting. ADC Internal Bandgap Fine Trim. These bits should not be modified after device boot code loads them with the factory trim setting. ADC Internal Bandgap Coarse Trim. A maximum value of 30 is supported. These bits should not be modified after device boot code loads them with the factory trim setting. Figure 27. ADC Offset Trim Register (ADCOFFTRIM) (Address Offset 41h) 15 9 8 0 Reserved OFFTRIM R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Bit Field 15-9 Reserved Table 19. ADC Offset Trim Register (ADCOFFTRIM) Field Descriptions Value Description Reads return a zero; Writes have no effect. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 33 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com Table 19. ADC Offset Trim Register (ADCOFFTRIM) Field Descriptions (continued) Bit Field 8-0 OFFTRIM Value Description ADC Offset Trim. 2's complement of ADC offset. Range is -256 to +255. These bits are loaded by device boot code with a factory trim setting. Modification of this default setting can be made to correct any board induced offset. 1.10.6 ADC Revision Register Figure 28. ADC Revision Register (ADCREV) (Address Offset 4Fh) 15 8 REV R-x 7 0 TYPE R-3h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Bit Field 15-8 REV 7-0 TYPE Table 20. ADC Revision Register (ADCREV) Field Descriptions Value 3 Description ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h. ADC Type. Always set to 3 for this type ADC 1.10.7 ADC Result Registers The ADC Result Registers are found in Peripheral Frame 0 (PF0). In the header files, the ADCRESULTx registers are located in the AdcResult register file, not AdcRegs. Figure 29. ADC RESULT0 - RESULT15 Registers (ADCRESULTx) (PF1 Block Address Offset 00h 0Fh) 15 12 11 0 Reserved RESULT R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 21. ADC RESULT0 - ADCRESULT15 Registers (ADCRESULTx) Field Descriptions Bit 15-12 11-0 Field Reserved RESULT Value Description Reads return a zero; Writes have no effect. 12-bit right-justified ADC result Sequential Sampling Mode (SIMULENx = 0): After the ADC completes a conversion of an SOCx, the digital result is placed in the corresponding ADCRESULTx register. For example, if SOC4 is configured to sample ADCINA1, the completed result of that conversion will be placed in ADCRESULT4. Simultaneous Sampling Mode (SIMULENx = 1): After the ADC completes a conversion of a channel pair, the digital results are found in the corresponding ADCRESULTx and ADCRESULTx+1 registers (assuming x is even). For example, for SOC4, the completed results of those conversions will be placed in ADCRESULT4 and ADCRESULT5. See 1.11 for timings of when this register is written. 34 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) 1.11 ADC Timings Figure 30. Timing Example For Sequential Mode / Late Interrupt Pulse Analog Input ADCCLK SOC0 Sample Window 02 9 SOC1 Sample Window 15 22 24 SOC2 Sample Window 37 ADCCTL 1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core ADCRESULT 0 ADCRESULT 1 SOC0 SOC1 2 ADCCLKs SOC2 Result 0 Latched EOC0 Pulse EOC1 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 13 ADC Clocks 6 Minimum ADCCLKs 7 ADCCLKs 1 ADCCLK Conversion 1 13 ADC Clocks SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 35 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) Figure 31. Timing Example For Sequential Mode / Early Interrupt Pulse Analog Input ADCCLK SOC0 Sample Window 02 9 SOC1 Sample Window 15 22 24 SOC2 Sample Window 37 ADCCTL 1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core ADCRESULT 0 SOC0 SOC1 SOC2 Result 0 Latched ADCRESULT 1 EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 13 ADC Clocks 6 Minimum ADCCLKs 7 ADCCLKs 2 ADCCLKs Conversion 1 13 ADC Clocks www.ti.com 36 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Analog-to-Digital Converter (ADC) Figure 32. Timing Example For Simultaneous Mode / Late Interrupt Pulse Analog Input A Analog Input B ADCCLK SOC0 Sample A Window SOC0 Sample B Window 02 9 SOC2 Sample A Window SOC2 Sample B Window 22 24 37 50 ADCCTL 1 .INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B) ADCRESULT 0 2 ADCCLKs Result 0 (A) Latched ADCRESULT 1 Result 0 (B) Latched ADCRESULT 2 EOC0 Pulse EOC1 Pulse 1 ADCCLK EOC2 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks 19 ADCCLKs Conversion 0 (B) 13 ADC Clocks Minimum 7 ADCCLKs 2 ADCCLKs Conversion 1 (A) 13 ADC Clocks SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 37 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Analog-to-Digital Converter (ADC) www.ti.com Figure 33. Timing Example For Simultaneous Mode / Early Interrupt Pulse Analog Input A Analog Input B ADCCLK SOC0 Sample A Window SOC0 Sample B Window 02 9 SOC2 Sample A Window SOC2 Sample B Window 22 24 37 50 ADCCTL 1 .INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B) ADCRESULT 0 2 ADCCLKs Result 0 (A) Latched ADCRESULT 1 Result 0 (B) Latched ADCRESULT 2 EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks 19 ADCCLKs Conversion 0 (B) 13 ADC Clocks Minimum 7 ADCCLKs 2 ADCCLKs Conversion 1 (A) 13 ADC Clocks 1.12 Internal Temperature Sensor The internal temperature sensor measures the junction temperature of the device. The sensor output can be sampled with the ADC on channel A5 using a switch controlled by the ADCCTL1.TEMPCONV bit. The switch allows A5 to be used both as an external ADC input pin and the temperature sensor access point. When sampling the temperature sensor, the external circuitry on ADCINA5 has no affect on the sample. Refer to Section 1.10.1 for information about switching between the external ADCINA5 input pin and the internal temperature sensor. 1.12.1 Transfer Function The temperature sensor output and the resulting ADC values increase with increasing junction temperature. The offset is defined as the 0 ºC LSB crossing as illustrated in Figure 34. This information can be used to convert the ADC sensor sample into a temperature unit. The transfer function to determine a temperature is defined as: Temperature = (sensor - Offset) * Slope 38 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated www.ti.com Preliminary Analog-to-Digital Converter (ADC) Figure 34. Temperature Sensor Transfer Function Temperature Slope (°C/LSB) Offset (0°C LSB value) LSB Refer to the electrical characteristics section in TMS320F28020, TMS320F28021, TMS320F28022, TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers Data Manual (SPRS523) for the slope and offset, or use the stored slope and offset calibrated per device in the factory which can be extract by a function at the following locations. For F2802x: • 0x3D7E80 - Slope (ºC / LSB, fixed-point Q15 format) • 0x3D7E83 - Offset (0 ºC LSB value) For F2803x: • 0x3D7E82 - Slope (ºC / LSB, fixed-point Q15 format) • 0x3D7E85 - Offset (0 ºC LSB value) The values listed are assuming a 3.3v full scale range. Using the internal reference mode automatically achieves this fixed range, but if using the external mode, the temperature sensor values must be adjusted accordingly to the external reference voltages. Example The header files include an example project to easily sample the temperature sensor and convert the result into two different temperature units. There are threee steps to using the temperature sensor: 1. Configure the ADC to sample the temperature sensor 2. Sample the temperature sensor 3. Convert the result into a temperature unit, such as ºC. Here is an example of these steps: // Configure the ADC to sample the temperature sensor EALLOW; AdcRegs.ADCCTL1.bit.TEMPCONV = 1; //Connect A5 - temp sensor AdcRegs.ADCSOC0CTL.bit.CHSEL = 5; //Set SOC0 to sample A5 AdcRegs.ADCSOC1CTL.bit.CHSEL = 5; //Set SOC1 to sample A5 AdcRegs.ADCSOC0CTL.bit.ACQPS = 6; //Set SOC0 ACQPS to 7 ADCCLK AdcRegs.ADCSOC1CTL.bit.ACQPS = 6; //Set SOC1 ACQPS to 7 ADCCLK AdcRegs.INTSEL1N2.bit.INT1SEL = 1; //Connect ADCINT1 to EOC1 AdcRegs.INTSEL1N2.bit.INT1E = 1; //Enable ADCINT1 EDIS; // Sample the temperature sensor AdcRegs.ADCSOCFRC1.all = 0x03; //Sample temp sensor SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 39 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Comparator Block while(AdcRegs.ADCINTFLG.bit.ADCINT1 == 0){} //Wait for ADCINT1 AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //Clear ADCINT1 sensorSample = AdcResult.ADCRESULT1; //Get temp sensor sample result //Convert raw temperature sensor output to a temperature (i.e. degC) DegreesC = (sensorSample - TempSensorOffset) * TempSensorSlope; For the F2802x, call the below factory stored slope and offset get functions: //Slope of temperature sensor (deg. C / ADC code, fixed pt Q15 format) #define getTempSlope() (*(int (*)(void))0x3D7E80)() //ADC code corresponding to temperature sensor output at 0-degreesC #define getTempOffset() (*(int (*)(void))0x3D7E83)() For the F2803x, call the below factory stored slope and offset get functions: //Slope of temperature sensor (deg. C / ADC code, fixed pt Q15 format) #define getTempSlope() (*(int (*)(void))0x3D7E82)() //ADC code corresponding to temperature sensor output at 0-degreesC #define getTempOffset() (*(int (*)(void))0x3D7E85)() www.ti.com 2 Comparator Block The comparator module described in this reference guide is a true analog voltage comparator in the VDDA domain. The analog portion of the block include the comparator, its inputs and outputs, and the internal DAC reference. The digital circuits, referred to as the wrapper in this document, include the DAC controls, interface to other on-chip logic, output qualification block, and the control signals. 2.1 Features The comparator block can accommodate two external analog inputs or one external analog input using the internal DAC reference for the other input. The output of the comparator can be passed asynchronously or qualified and synchronized to the system clock period. The comparator output is routed to both the ePWM Trip Zone modules, as well as the GPIO output multiplexer. 2.2 2.2 Block Diagram Figure 35. Comparator Block Diagram CMPDACEN Input Pin A Input Pin B 1 VDDA VSSA 10-bit DAC 0 COMPx COMPSOURCE DACVAL [9:0] SYNCSEL 0 1 SYSCLK CMPINV Sync / Qualification 0 ETPWM COMPxTRIP & GPIO Mux 1 QUALSEL [4:0] COMPSTS 40 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Comparator Block 2.3 Comparator Function The comparator in each comparator block is an analog comparator module, and as such its output is asynchronous to the system clock. The truth table for the comparator is shown in Table 22. Figure 36. Comparator A Comparator B Output Voltages Voltage A > Voltage B Voltage B > Voltage A Table 22. Comparator Truth Table Output 1 0 There is no definition for the condition Voltage A = Voltage B since there is hysteresis in the response of the comparator output. Refer to the device datasheet for the value of this hysteresis. This also limits the sensitivity of the comparator output to noise on the input voltages. The output state of the comparator, after qualification, is reflected by the COMPSTS bit in the COMPSTS register. Since this bit is part of the wrapper, clocks must be enabled to the comparator block for the COMPSTS bit to actively show the comparator state. 2.4 DAC Reference Each comparator block contains a 10-bit voltage DAC reference that can used to supply the inverting input (B side input) of the comparator. The voltage output of the DAC is controlled by the DACVAL bit field in the DACVAL register. The output of the DAC is given by the equation: V = DACVAL * (VDDA-VSSA) 1023 Since the DAC is also in the analog domain it does not require a clock to maintain its voltage output. A clock is required, however, to modify the digital inputs that control the DAC. 2.5 Initialization There are 2 steps that must be performed prior to using the comparator block: 1. Enable the Band Gap inside the ADC by writing a 1 to the ADCBGPWD bit inside ADCTRL1. 2. Enable the comparator block by writing a 1 to the COMPDACEN bit in the COMPCTL register. 2.6 Digital Domain Manipulation At the output of the comparator there are two more functional blocks that can be used to influence the behavior of the comparator output. They are: 1. Inverter circuit: Controlled by the CMPINV bit in the COMPCTL register; will apply a logical NOT to the output of the comparator. This function is asynchronous, while its control requires a clock present in order to change its value. SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 41 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Comparator Block www.ti.com 2. Qualification block: Controlled by the QUALSEL bit field in the COMPCTL register, and gated by the SYNCSEL bit in the COMPCTL register. This block can be used as a simple filter to only pass the output of the comparator once it is synchronized to the system clock. and qualified by the number of system clocks defined in QUALSEL bit field. 42 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Comparator Block 2.7 Comparator Registers F280x2x devices have two comparators COMP1 and COMP2. Table 23 lists the registers for these modules. Name COMP1 COMP2 Address Range 6400h – 641Fh 6420h – 642Fh Size(x16) 1 1 Description Comparator Comparator Table 23. Comparator Module Registers Name Address Range(base) COMPCTL 0x0000 0000 Reserved 0x0000 0001 COMPSTS 0x0000 0002 Reserved 0x0000 0003 Reserved 0x0000 0004 Reserved 0x0000 0005 DACVAL 0x0000 0006 Reserved 0x0000 0007 0x0000 001F (1) This register is EALLOW protected. Size(x16) 1 1 1 1 1 1 1 25 Description comparator control(1) Reserved compare output status Reserved Reserved Reserved 10-bit DAC Value Reserved 2.7.1 Comparator Control (COMPCTL) Register Figure 37. Comparator Control (COMPCTL) Register 15 9 Reserved R-0 7 3 QUALSEL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 2 CMPINV R/W-0 1 COMPSOURCE R/W-0 8 SYNCSEL R/W-0 0 COMPDACE R/W-0 Bit 15-9 8 Field Reserved SYNCSEL 7-3 QUALSEL 2 CMPINV Table 24. COMPCTL Register Field Descriptions Value 0 1 0h 1h 2h ... Fh 0 1 Description Reads return a 0; Writes have no effect. Synchronization select for output of the comparator before being passed to ETPWM/GPIO blocks Asynchronous version of Comparator output is passed Synchronous version of comparator output is passed Qualification Period for synchronized output of the comparator Synchronized value of comparator is passed through Input to the block must be consistent for 2 consecutive clocks before output of Qual block can change Input to the block must be consistent for 3 consecutive clocks before output of Qual block can change ... Input to the block must be consistent for 16 consecutive clocks before output of Qual block can change Invert select for Comparator Output of comparator is passed Inverted output of comparator is passed SPRUGE5B – December 2008 – Revised December 2009 Analog-to-Digital Converter and Comparator 43 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary Comparator Block Table 24. COMPCTL Register Field Descriptions (continued) Bit Field 1 COMPSOURCE 0 COMPDACE Value 0 1 0 1 Description Source select for comparator inverting input Inverting input of comparator connected to internal DAC Inverting input connected to external pin Comparator/DAC Enable Comparator/DAC logic is powered down. Comparator/DAC logic is powered up. www.ti.com 2.7.2 Compare Output Status (COMPSTS) Register Figure 38. Compare Output Status (COMPSTS) Register 15 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 1 0 COMPSTS R-0 Table 25. Compare Output Status (COMPSTS) Register Field Descriptions Bit 15-1 0 Field Reserved COMPSTS Value Description Reads return zero and writes have no effect. Logical latched value of the comparator 2.7.3 DAC Value (DACVAL) Register Figure 39. DAC Value (DACVAL) Register 15 10 9 0 Reserved DACVAL R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Bit 15-10 9-0 Field Reserved DACVAL Table 26. DAC Value (DACVAL) Register Field Descriptions Value Description Reads return zero and writes have no effect. 0-3FFh DAC Value bits, scales the output of the DAC from 0 – 1023. 44 Analog-to-Digital Converter and Comparator SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Preliminary www.ti.com Appendix A Revision History This document has been revised to include the following technical change(s) Location Table 3 Table 24 Table 27. Changes in this Document Additions/Deletions/Modificatons Reversed the description for the 0 and 1 values for the ADCBSY register For QUALSEL field, Fh value, changed "15 consecutive clocks" to "16 consecutive clocks" SPRUGE5B – December 2008 – Revised December 2009 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Revision History 45 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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