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em4095 芯片资料

EM MICROELECTRONIC - MARIN SA EM4095 Read/Write analog front end for 125kHz RFID Basestation Description The EM4095 (previously named P4095) chip is a CMOS integrated transceiver circuit intended for use in an RFID basestation to perform the following functions: - antenna driving with carrier frequency - AM modulation of the field for writable transponder - AM demodulation of the antenna signal modulation induced by the transponder communicate with a microprocessor via simple interface. Features Integrated PLL system to achieve self adaptive carrier frequency to antenna resonant frequency No external quartz required 100 to 150 kHz carrier frequency range Direct antenna driving using bridge drivers Data transmission by OOK (100% Amplitude Modulation) using bridge driver Typical Operating Configuration Read Only Mode LA +5V CRES CDV1 +5V CDV2 RDY/CLK 1 2 16 15 CDC2 CFCAP 3 14 4 EPM44009955 13 5 12 6 11 SHD DEMOD_OUT MOD CAGND µP 7 10 CDEC 8 9 Data transmission by Amplitude Modulation with externally adjustable modulation index using single ended driver Multiple transponder protocol compatibility (Ex: EM400X, EM4050, EM4150, EM4070, EM4170, EM4069….) Sleep mode 1µA USB compatible power supply range 40 to +85°C temperature range Small outline plastic package SO16 Applications Car immobiliser Hand held reader Low cost reader Pin Assignment VSS RDY/CLK ANT1 DVDD DVSS ANT2 VDD DEMOD_IN SO16 DC2 FCAP SHD DEMOD_OUT MOD AGND CDEC_IN CDEC_OUT Fig. 1 Read/Write Mode LA +5V CRES CDV1 +5V CDV2 RDY/CLK 1 2 16 15 CDC2 CFCAP 3 14 4 EPM440095 13 5 12 6 11 SHD DEMOD_OUT MOD CAGND µP 7 10 CDEC 8 9 Fig. 3 Fig. 2 Copyright  2002, EM Microelectronic-Marin SA 1 System principle Transponder Coil1 Read Only and R/W Chip Coil2 Signal on Transceiver coil UPLINK Signal on Transponder coil RF Carrier Data EM4095 Transceiver R/W configuration RDY/CLK LA +5V CRES CDV1 +5V CDV2 1 2 16 15 CDC2 CFCAP 3 14 4EM4095 13 5 12 6 11 SHD DEMOD_OUT MOD CAGND µP 7 10 CDEC 8 9 Signal on Transponder coil DOWNLINK Signal on Transceiver coil RF Carrier Data Fig. 4 Copyright  2002, EM Microelectronic-Marin SA 2 Absolute Maximum Ratings Parameter Storage temperature Maximum voltage at VDD Minimum voltage at VDD Max. voltage other pads Min. voltage other pads Max. junction temperature Electrostatic discharge max. to MIL-STD-883C method 3015 against VSS Electrostatic discharge max. to MIL-STD-883C method 3015 (only for pins ANT1 and ANT2) against VSS Maximum Input/Output current on all pads except VDD, VSS, DVDD, DVSS, ANT1, ANT2, RDY/CLK Maximum AC peak current on ANT1 and ANT2 pads 100 kHz duty cycle 50% Symbol TSTO VDDmax VDDmin VMAX VMIN TJMAX Conditions -55 to +150°C VSS+6V VSS -0.3V VDD +0.3V VSS -0.3V +125°C VESD 4000V VESD_ANT 10000V IIMAX IOMAX IANTmax 10mA 300mA Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. EM4095 Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Symb Min Typ Max Units Operating junction TJ -40 temperature +110 °C Supply voltage VDD 4.1 5 5.5 V Antenna circuit resonant frequency FRES 100 125 150 kHz AC peak current on ANT1 & ANT2 pads IANT 250 mA CFCAP CDEC CDC2 CAGND Package thermal resistor SO16 Rth j-a * 10 * * 100 * * 6.80 * 100 220 69 70 71 nF nF nF nF °C/W * ±10% tolerance capacitors should be used ** According to 1S2P JEDEC test board Due to antenna driver current the internal junction temperature is higher than ambient temperature. Please calculate ambient temperature range from max. antenna current and package Thermal Resistor. It is the user's responsibility to guarantee that TJ remains below 110°C. Supply voltage (VDD and DVDD pads) must be blocked by a 100nF capacitor (to VSS) as close as possible to the chip Copyright  2002, EM Microelectronic-Marin SA 3 EM4095 Electrical and Switching Characteristics: Parameters specified below are valid only in case the device is used according to Operating Conditions defined on previous page. VSS=DVSS=0V, VDD =DVDD = 5V, Tj = -40 to 110°C, unless otherwise specified Parameter Symbol Test Conditions Min Typ Max Units Supply current in sleep mode Supply current excluding drivers current IDDsleep IDDon 1 2 µA 5 7 mA AGND level VAGND Note 1 2.35 2.5 2.65 V Logic signals SHD, MOD, DEMOD_OUT Input logic high Input logic low Output logic high Output logic low MOD pull down resistor SHD pull up resistor PLL VIH VIL VOH VOL RPD RPU ISOURCE=1mA ISINK=1mA 0.2VDD 0.8VDD 0.8VDD V 0.2VDD V 0.9VDD V 0.1VDD V 20 50 90 kΩ 20 50 90 kΩ Antenna capture frequency range Antenna locking frequency range Drivers FANT_C FANT_L 100 150 kHz 100 150 kHz ANT drivers output resistance RDY/CLK driver output resistance AM demodulation RAD IANT=100mA RCL IRDY/CLK=10mA 3 9 Ω 12 36 Ω DEMOD_IN common mode range VCM VSS + 0.5 VDD - 0.5 V DEMOD_IN input sensitivity Vsense Note 2 0.85 2 mVpp Note 1: AGND is a EM4095 internal reference point. Any external connection except specified capacitor to VSS may lead to device malfunction. Note 2: Modulating signal 2Khz square wave on 125 kHz carrier, total signal inside VCM Vsense Copyright  2002, EM Microelectronic-Marin SA 4 EM4095 Timing Characteristics: Parameters specified below are valid only in case the device is used according to Operating Conditions defined on previous page. VSS=DVSS=0V, VDD=DVDD = 5V Parameter Symbol Test Conditions Typ Max Units Set-up time after a sleep period Tset 25 35 ms Time from full power to modulation state Tmdon antenna circuit specifications: Q=15,FRES=125Khz 50 µs modulation index: 100% AM demodulation: Delay time from input to output Tpd Modulating signal 2Khz square wave 10mVpp 40 100 µs Recovery time of reception after antenna modulation Trec Note 1 400 500 µs Note 1: RF period is time of one period transmitted on ANT outputs (at 125 kHz 8µs). Trec after antenna modulation receiver chain is ready to demodulate. The condition is of course that the amplitude on antenna has already reached its steady state by that time (this depends on Q of antenna). See also Application Notes. Block Diagram VDD VSS SHD AGND FCAP MOD to all blocks to all blocks to all blocks BIAS & AGND BIAS & AGND to all blocks LOCK LOOP FILTER VCO & SEQUENCER SYNCHRO HOLD SHORT DETECTION & READY ANTENNA DRIVERS RDY/CLK DVDD ANT1 ANT2 DVSS DMOD_IN SAMPLER FILTER COMPARATOR DMOD_OUT CDEC_OUT CDEC_IN DC2 Fig. 5 Copyright  2002, EM Microelectronic-Marin SA 5 Functional Description General The EM4095 is intended to be used with an attached antenna circuit and a microcontroller. Few external components are needed to achieve DC and RF filtering, current sensing and power supply decoupling. A stabilised power supply has to be provided. Please refer to EM4095 Application Notes for advice. Device operation is controlled by logic inputs SHD and MOD. When SHD is high EM4095 is in sleep mode, current consumption is minimised. At power up the input SHD has to be high to enable correct initialisation. When SHD is low the circuit is enabled to emit RF field, it starts to demodulate any amplitude modulation (AM) signal seen on the antenna. This digital signal coming from the AM demodulation block is provided through DEMOD_OUT pin to the microcontroller for decoding and processing. High level on MOD pin forces in tri-state the main antenna drivers synchronously with the RF carrier. While MOD is high the VCO and AM demodulation chain are kept in state before the MOD went high. This ensures fast recovery after MOD is released. The switching ON of VCO and AM demodulation is delayed by 41 RF clocks after falling edge on MOD. In this way the VCO and AM demodulation operating points are not perturbed by startup of antenna resonant circuit. Analog Blocks The circuit performs the two functions of an RFID basestation, namely: transmission and reception. Transmission involves antenna driving and AM modulation of the RF field. The antenna drivers deliver a current into the external antenna to generate the magnetic field. Reception involves the AM demodulation of the antenna signal modulation induced by the transponder. This is achieved by sensing the absorption modulation applied by the tag (transponder). Transmission Referring to the block diagram, transmission is achieved by a Phase Locked Loop (PLL) and the antenna drivers. EM4095 Drivers The antenna drivers supply the reader basestation antenna with the appropriate energy. They deliver current at the resonant frequency which is typically 125 kHz. Current delivered by drivers depends on Q of external resonant circuit. It is strongly recommended that design of antenna circuit is done in a way that maximum peak current of 250 mA is never exceeded (see Typical Operating Configuration for antenna current calculation). Another limiting factor for antenna current is Thermal Convection of package. Maximum peak current should be designed in a way that internal junction temperature does not exceed maximum junction temperature at maximum application ambient temperature. 100% modulation (field stop) is done by switching OFF the drivers. The ANT drivers are protected against antenna DC short circuit to the power supplies. When a short circuit has been detected the RDY/CLK pin is pulled low while the main driver is forced in tri-state. The circuit can be restarted by activating the SHD pin. Phase locked loop The PLL is composed of the loop filter, the Voltage Controlled Oscillator (VCO), and the phase comparator blocks. By using an external capacitive divider, pin DEMOD_IN gets information about the actual high voltage signal on antenna. Phase of this signal is compared with the signal driving antenna drivers. Therefore the PLL is able to lock the carrier frequency to the resonant frequency of the antenna. Depending on the antenna type the resonant frequency of the system can be anywhere in the range from 100 kHz to 150 kHz. Wherever the resonant frequency is in this range it will be maintained by the Phase Lock Loop. Reception The demodulation input signal for the reception block is the voltage sensed on the antenna. DEMOD_IN pin is also used as input to Reception chain. The signal level on the DEMOD_IN input must be lower than VDD-0.5V and higher than VSS+0.5V. The input level is adjusted by the use of an external capacitive divider. Additional capacitance of divider must be compensated by accordingly smaller resonant capacitor. The AM demodulation scheme is based on the "AM Synchronous Demodulation" technique. The reception chain is composed of sample and hold, DC offset cancellation, bandpass filter and comparator. DC voltage of signal on DEMOD_IN is set to AGND by internal resistor. The AM signal is sampled, the sampling is synchronised by a clock from VCO. Any DC component is removed from this signal by the CDEC capacitor. Further filtering to remove the remaining carrier signal, high and low frequency noise is made by second order highpass filter and CDC2. The amplified and filtered receive signal is fed to asynchronous comparator. Comparator output is buffered on output pin DEMOD_OUT. Copyright  2002, EM Microelectronic-Marin SA 6 Signal RDY/CLK This signal provides the external microprocessor with clock signal which is synchronous with the signal on ANT1 and with information about EM4095 internal state. Clock signal synchronous with ANT1 indicates that PLL is in lock and that Reception chain operation point is set. When SHD is high RDY/CLK pin is forced low. After high to low transition on SHD the PLL starts-up, and the reception chain is switched on. After time TSET the PLL is locked and reception chain operation point has been established. At this moment the same signal which is being transmitted to ANT1 is also put to RDY/CLK pin indicating to microprocessor that it can start observing signal on DEMOD_OUT and giving at the same time reference clock signal. Clock on RDY/CLK pin is continuous, it is also present during time the ANT drivers are OFF due to high level on MOD pin. During the time TSET from high to low transition on SHD pin RDY/CLK pin is pulled down by 100 kΩ pull down resistor. The reason for this is in additional functionality of RDY/CLK pin in case of AM modulation with index which is lower then 100%. In that case it is used as auxiliary driver which maintains lower amplitude on coil during modulation. (see also Typical Operating Configuration) Remark: Please refer to AN4095 for external components calculation and limits. Typical Operating Configuration Read Only Mode LA +5V CRES CDV1 +5V CDV2 RDY/CLK 1 2 16 15 CDC2 CFCAP 3 14 4 EPM44009955 13 5 12 6 11 SHD DEMOD_OUT MOD CAGND µP 7 10 CDEC 8 9 Fig. 6 Read/Write mode (Low Q factor antenna) LA +5V CRES CDV1 +5V CDV2 RDY/CLK 1 2 16 15 CDC2 CFCAP 3 14 4 EPM44009955 13 5 12 6 11 SHD DEMOD_OUT MOD CAGND µP 7 10 CDEC 8 9 Fig. 7 Copyright  2002, EM Microelectronic-Marin SA EM4095 Read/Write mode (High Q factor antenna) RSER LA +5V CRES CDV1 +5V CDV2 RDY/CLK 1 2 16 15 CDC2 CFCAP 3 4 5 6 14 EPM44009955 13 12 11 SHD DEMOD_OUT MOD CAGND µP 7 10 CDEC 8 9 Read/Write mode (AM modulation) Fig. 8 RAM LA +5V CRES CDV1 +5V CDV2 RDY/CLK 1 2 16 15 CDC2 CFCAP 3 4 5 6 14 EPM44009955 13 12 11 SHD DEMOD_OUT MOD CAGND µP 7 10 CDEC 8 9 Fig. 9 Figure 6 presents EM4095 used in Read Only mode. Pin MOD is not used. It is recommended to connect it to VSS. Figure 7 presents typical R/W configuration for OOK communication protocol reader to transponder (eg. EM4150). It is recommended to be used with low Q factor antennas (up to 15). When the antenna quality is high using configuration of figure 6 or 7 the voltage on antenna can arrive in the range of few hundred volts and antenna peak current may exceed its maximum value. In such a case the capacitive divider ratio has to be high thus limiting the sensitivity. For such case it is better to reduce antenna circuit quality by adding serial resistor. In this way the antenna current is lower and thus power dissipation of IC is reduced with practically the same performance (Fig. 8). In the case AM modulation communication protocol reader to transponder (eg. EM4069) is needed a single ended configuration has to be used (figure 9). When pin MOD is pulled high driver on ANT1 is put in three state, driver RDY/CLK continues driving thus maintaining lower antenna current. Modulation index is adjusted by resitor RAM. As mentioned above RDY/CLK signal becomes active only after the demodulation chain operating point is set. Before it is pulled down by high impedance pull down resistor (100 kΩ) in order not to load ANT1 output. In the case of AM modulation configuration the total antenna current change at the moment RDY/CLK pin becomes active, so external microprocessor has to wait another TSET before it can start observing DEMOD_OUT. 7 Read Only mode with external peak detector LA +5V CRES CDV1 +5V CDV2 RDY/CLK 1 2 16 15 CDC2 CFCAP 3 4 5 6 14 EPM44009955 13 12 11 SHD DEMOD_OUT MOD CAGND µP 7 10 CDEC 8 9 D1 C1 R1 Read/Write mode with external peak detector Fig. 10 LA +5V CRES CDV1 +5V CDV2 RDY/CLK 1 2 16 15 CDC2 CFCAP 3 14 4 EPM4400955 13 5 12 6 11 SHD DEMOD_OUT MOD CAGND µP 7 10 CDEC 8 9 D1 C1 R1 Fig. 11 EM4095 As mentioned above for high Q antennas the voltage on antenna is high and read sensitivity is limited by demodulator sensitivity due to capacitive divider. Read sensitivity (and thus reading range) can be increased by using external envelope detector circuit. Input is taken on antenna high voltage side output is directly fed to CDEC_IN pin. However, the capacitor divider is still needed for PLL locking. Such configuration is shown in figure 5, the envelope detector is formed by three components: D1, R1 and C1. The configuration presented in figure 9 may also be used for read write applications but it has a drawback in the case fast recovery of reading is needed after communication reader to transponder is finished. The reason is in fact that DC voltage after diode D1 is lost during modulation and it takes very long time before it is established again. Figure 10 presents a solution to that problem. A high voltage NMOS transistor blocks the discharge path during modulation, so operating point is preserved. The signal controlling NMOS gate has to be put low synchronously with signal MOD, but it can be put high only after the amplitude on antenna has recovered after modulation. PCB Layout Refer to "EM4095 Application Note" (App. Note 404) Copyright  2002, EM Microelectronic-Marin SA 8 EM4095 Pin Description SOIC 16 package Pin Name Description 1 VSS 2 RDY/CLK Negative power supply (substrate) Ready flag and clock output, driver for AM modulation 3 ANT1 4 DVDD 5 DVSS 6 ANT2 Antenna driver Positive power supply for antenna drivers Negative power supply for antenna drivers Antenna driver 7 VDD 8 DEMOD_IN Positive power supply Antenna sensing voltage 9 CDEC_OUT DC blocking capacitor connection « out » 10 CDEC_IN DC blocking capacitor connection « in » 11 AGND 12 MOD Analog ground A High level voltage modulates the antenna 13 DEMOD_OUT Digital signal representing the AM seen on the antenna 14 SHD A High level voltage forces the circuit into sleep mode 15 FCAP PLL Loop filter capacitor 16 DC2 DC decoupling capacitor GND: reference ground PWR: power supply IPD: input with internal pull down IPU: input with internal pull up ANA: O: Type GND O O PWR GND O PWR ANA ANA ANA ANA IPD O IPU ANA ANA analog signal output Package and Ordering Information Dimensions of SOIC 16 Package (table in millimeters) Symbol A A1 B C D E H L Common Dimensions (mm) Min Nom Max 1.55 1.63 1.73 0.127 0.15 0.25 0.35 0.41 0.49 0.19 0.20 0.25 9.80 9.93 9.98 3.81 3.94 3.99 5.84 5.99 6.20 0.41 0.64 0.89 Fig. 12 Ordering Information Please make sure to give the complete part number when ordering. The EM4095 is available in the following package: Part Number Package Delivery Form EM4095HMSO16A SOIC 16 package stick Product Support Check our Web Site under Products/RF Identification section. Questions can be sent to Copyright  2002, EM Microelectronic-Marin SA 9 EM4095 Appendix Equations Antenna resonant frequency f0: f0 = 2π 1 LAC0 (1) Where C0 is resonant capacitor composed of CRES, CDV1 and CDV2: C0 = CRES + CDV 1∗CDV 2 CDV 1 + CDV 2 (2) Usually antenna coil is specified by its inductance (LA) and Q factor (QA). Serial resistance of antenna is defined by following equation: R ANT = 2πf 0 LA QA (3) The equations which follow are valid for bridge configuration as defined on Figures 1, 2 and 3. For figures 1 and 2 RSER has to be considered 0. The AC current amplitude at resonant frequency is defined as follows: Peak to peak voltage on antenna is defined by following equation: V ANTpp = I ANT πf 0 C 0 (6) To ensure correct operation of the AM demodulation chain, the AC peak to peak voltage on DEMOD_IN pin (VDMOD_INpp) has to be inside common mode range. Once peak to peak voltage on antenna is known the capacitor divider division factor can be calculated: VDMOD _ INpp = VANTpp C DV1 CDV1 + CDV 2 (7) Power dissipation is composed of power dissipated on ANT drivers and internal power consumption: ( ) P = 2 ⋅ I RMS 2 ⋅ RAD + I DDon VDD − VSS (7) Temperature increase of die due to power dissipation is: ∆T = P ⋅ RTh (8) Where RTh is Package thermal resistor. I ANT = 4 π R ANT Vdd − Vss + RSER + 2RAD (4) RMS antenna current (important for power dissipation calculation): I RMS = I ANT 2 (5) EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. © EM Microelectronic-Marin SA, 07/02, Rev. Ê/490 Copyright  2002, EM Microelectronic-Marin SA 10




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