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Power Sequence Timing Analysis

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     Power Sequence Timing Analysis EA Test Report Revision: 1.02 11/28/14 Miraculix Revision History: Revision Date Description 1.00 06/13/14 Initial release Author:Brena lin System Configuration / EA Information Table: Description: Comments Motherboard PWB Revision: Miraculix MB REV:1.02 PCB Vendor: WUS ALLEGRO Board File: 7t-miraculix.102-0827 .brd BOM: 69F1N3M0132D BIOS Revision: D01 09/10/2014 CPU: Intel(R) Core(TM) i5-4258U CPU @ 2.40GHZ Clock Generator / Clock Buffer: Apacer DDR3 1600MHZ 8GB DIMM1 / DIMM2 AC ADAPTER MODEL:PA-1900-32 Power Supply: LITEON Model:PA-1900-32 Rev:X01 Expansion Card(s): Software Utility: Oscilloscope: DPO7104C Probe: DPO1500*4 Other: Owner: Lucy Liu Date Start: 11/28/2014 Date Finish: 12/05/2014 Pass / Fail: 9Pass/3Fail/2NA Comments: Measurement Signals summary/Failure & Marginal EA Characterization: No. Signal name Pass/Fail Problem Description Note Power sequencing and RTC Reset signal Timing Intel Lynx Point Platform 1 G3 w/RTC Loss to S4/S5 Timings Pass 2 S5/S3/M3 to S0 Timing Pass 3 S5/Moff to S5/M3 Timings Pass 4 S0 to S5 Timings Pass 5 S3/S4/S5 to Deep Sx to G3 w/RTC Loss Timing Diargam NA Not support deep sleep 6 Power Sequence and reset signal timing Fail T252&T258 fail Open 7 AC Timing Pass CPU 8 Power Sequence Timing Diagram (Haswell Bridge) Fail Tcpu14 fail Open Reset Timing 9 THERMTRIP# Power Down Sequence Pass Other Battery AC adapter Desktop 10 Measure BATT when RSMRST at power down Pass Mini PCIE card Power Sequence 11 Power Up NA Has no G3 state 12 Power Management States Pass 13 Power Down Pass PLT_RST#_BUF_S has a glitch STDP 9320 Power rails sequence 14 STDP 9320 Power rails sequence Fail +3.3V has a glitth Open Test scope Test Equipments 1.1 Please use any digital oscilloscope with >=1GHz bandwidth and >=20GS/s sampling rate. 1.2 Please use any active single-ended with >=1GHz BW and input impedance >=1MOhm. Configuration of System Under Test 1.3 All the related system components should be installed. For example, mini-card should be installed in slot 1 when we test mini-card slot 1. 1.4 Please use the system components of this project if they are available. If there is no dedicate system component for the project, please use the high-end components that the system can support. 1.5 Please install the operating system and driver, Test Procedure 1.6 Please measure the signal at the receiver side in order to reduce the reflection. Please remark the net name and measurement location of each signal under test. The signal wire and the ground wire should be very short (<5mm) in order to get the proper waveform. 1.7 Please run the stress utility to make sure that the captured waveform is in worst case. For example, please transfer the large file via Ethernet when we measure the signal related to the Ethernet port. 1.8 Please set the time scale and voltage scale so that we can read the test result from the waveform directly.  For example, please set the time scale to small scale for rise time measurement, and the rise time should take about 2 horizontal divisions of the screen. For example, the offset should be set to high level and the ring down should take about 2 vertical divisions so that we may trigger the waveform easily. For example, the waveform should take about 8 vertical divisions so that we may read the high level and low level easily. 1.9 Please set the sample rate to >1GS/s except we need to capture a long period (>=1s) of waveform. For example, we should set the sample rate to >1GS/s so that we may check if there is any non-monotony at the rising edge or falling edge. 1.10 Please save the screenshot and make sure that the test result is easily read and easily printed. For example, please save the waveform in “ink saving mode”, and please change the color of channel 1 from color of channel 1 from yellow to brown for easier read. (Display -> Colors -> Record View Palette “User” -> Hue “160 degrees”) Reference Documents 1.11 Please refer to the datasheet and design guide of each chipset. Power Sequence Intel Lynix Point 1.1.1 G3 w/RTC Loss to S4/S5 Timings #1: Refer to 503118_503118_Lynx_Point_LP_EDS_Rev_2p2_Final in detail. Refer to 486708_486708_LPT_EDS_Rev2_0 Intel 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH) External Design Specification (EDS) Revision 2.0 February 2013 in detail. #3. This timing is a nominal value counted using RTC clock. If RTC clock isn’t already stable at the rising edge of RSMRST#, this timing could be shorter or longer than the specified value. #4. Platforms not supporting Deep Sx will typically have SLP_SUS# left as no connect.Hence DPWROK high and RSMRST# deassertion to SUSCLK toggling would be t202+t202a=100 ms minimum. #5. Platforms supporting Deep Sx will have SLP_SUS# deassert prior to RSMRST#. Platforms not supporting Deep Sx will have RSMRST# deassert prior to SLP_SUS# #6. The VccDSW3_3 supplies must never be active while the VccRTC supply is inactive. #7:Measured from VCCRTC-10% to RTCRST# reaching 0.55*VCCRTC. VCCRTC is defined as the final settling voltage that the rail ramps. #8:VCCHSIO cannot take the full 65us max ramp time due to the dilters on VCCUSB3PLL and VCCSATA3PLL. Based on the existing recommended filter capacitors for the PLLs, VCCSHIO Rails will need to ramp within ~22us VccRTC active to RTCRST# deassertion t200 Without Deep Sleep Note Specification >9ms #7 Measured Result 12.36ms Result: Pass Fail CH1:+VCC_RTC(4894.90 2036.60) CH2:RTC_RST#(4062.00 1930.00) Without Deep Sleep RTCRST# deassertion to DPWROK high t200a Without Deep Sleep Note Specification >1us Measured Result 208ms Result: Pass Fail CH1:RTC_RST#(4062.00 1930.00) CH2:PCH_DPROK(4702.00 2123.00) Without Deep Sleep VccDSW3_3 active to DPWROK high t200b Without Deep Sleep Note Specification >10ms Measured Result 19.08ms Result: Pass Fail CH1:+VCCDSW(4876.00 1998.00) CH2:PCH_DPROK(4702.00 2123.00) Without Deep Sleep VccDSW3_3 active to VccSus3_3 active t200c Without Deep Sleep Note Specification >= 0ms Measured Result 0ms Result: Pass Fail CH1: +VCCDSW(4876.00 1998.00) CH2:+3VSUS_VCCPUSB(4369.00 2496.00) Without Deep Sleep VccSUS active to RSMRST# deassertion t201 Without Deep Sleep Note Specification >10ms #2 Measured Result 19.08ms Result: Pass Fail CH1: +3VSUS_VCCPUSB(4369.00 2496.00) CH2:PM_RSMRST_R(4731.00 2157.00) Without Deep Sleep DPWROK high to SLP_SUS# deassertion t202 Without Deep Sleep Note Specification >95ms #3,#4,#8 Measured Result NA Result: Pass Fail CH2:PCH_DPROK(4702.00 2123.00) CH3:SLP_SUS#_R_EC (4675.00 1562.00) With Deep sleep Without Deep Sleep RSMRST# and SLP_SUS# deassertion to SUSCLK togglinf t202a Without Deep Sleep Note Specification >5ms #4,#5 Measured Result 167.72ms Result: Pass Fail CH1: PM_RSMRST_R(4731.00 2157.00) CH2:SUS_CLK (5083.00 1658.00) Without Deep Sleep VccRTC active to VccDSW3_3 active t225 Without Deep Sleep Note Specification >0ms #2,#6 Measured Result 898.025us Result: Pass Fail CH1:+VCCDSW(4876.00 1998.00) CH2:+VCC_RTC(4894.90 2036.60) Without Deep: 1.1.2 S5/S3/M3 to S0 Timing #1: Refer to 503118_503118_Lynx_Point_LP_EDS_Rev_2p2_Final in detail. #2. VccSus supplies include VccSus3_3 and VccSusHDA(if VCCHDA is on suspend well). Also includes DcpSus for mobile platforms that power DcpSus externally. #3. Dependency on SLP_S4# and SLP_A# stretching #4. Dependency on SLP_S3# and SLP_A# stretching #5. PCI/PCIe2.0 specification requires that power rails associcated with PCI/PCIe (typically the 3.3 V, 5 V, and 1 V core well rails) have been valid for 100 ms prior to PLTRST# de-assertion. System designers must ensure the requirement is met on the platforms. #6. Ensure PWROK is a solid logic '1' before proceeding with the boot sequence. Note: If PWROK drops after t206 it will be considered a power failure. #7. Timing is dependant on whether 25 MHz crystal is stable by the time PWROK is high. #8. Vcc includes VCC1_05,VCCCLK,VCCHSIO,VCCUSB3PLL,VCCSATA3PLL,VCCAPLL,VCCACLKPLL, VCCTS1_5,VCCSDIO,VCC3_3 and VccASW (if Intel® ME only powered in S0). #9. A Power rail is considered to be inactive when the rail is at its nominal voltage minus 5% or less. #10. Board design may meet (t231 AND t232 AND t234 AND t235) OR (t238). #11. The definition of rail falling for this timing requirement is as follows:1)VCCDSW3_3 and VCCSUS3_3 is 2.9V; 2) VCCASW and DCPSUS*(in external suspend VR mode) is 0.92V; 3)VCC is 0.99V #12. Timing enabled through soft strap. If T205b is not enabled, the platform is responsible for controlling the assertion timing of PCH_PWROK and SYS_PWROK in such a way that it satisfies the PCIe timing requirement of power stable to reset de-assertion. However, mini-PCIe devices require only 1ms (refer PCI Express® Mini Card Electromechanical Specification Revision 1.21). #13:Requirment applies to power failure and surprise power down scenario. As long as the board follows the recommended power-well control signals(that is,SLP_S3#, SLP_A# and SLP_SUS#), the PCH guarantees proper isolation during the normal graceful power down events. #14:Ensure respective PWROK signals(PCH_PEROK,APWROK and RSMRST#) toggle appropriately during normal power state transiton(for example S0->SX->S0,S0->DEEP SX->S0,etc.) even if the supply voltage does not drop below the specified value. Use of the stretch registers can be used to achieve this. #15.Timing does not apply after Deep Sx exit when Intel ME has configuared SLP_S5# and/or SLP_S4# to rise with SLP_A#. SLP_S5# high to SLP_S4# high t203 Note Specification >30us #3,#15 Measured Result NA Result: Pass Fail CH2: SLP_S5# CH3:SLP_S4# SLP_S4# high to SLP_S3# high t204 Note Specification >30us #4 Measured Result 43.2us Result: Pass Fail CH2:PM_SUSC# (5877.00 615.00) CH3:PM_SUSB# (6003.66 687.23) Vcc active to PWROK high (S5-S0/S3-S0) t205a(s5-s0) t205a(s3-s0) Note Specification >5ms >5ms #5,#8 Measured Result 109.2ms 104.2ms Result: Pass Fail CH1: N19050076(5225.00 2128.00) CH2:+1.05VS(5420.00 2157.12) CH3:+1.05VS_AUSB3PLL(5780.00 2390.51) CH4: PM_PCH_PWROK_R (4929.00 1526.00) S5-S0: S3-S0: CH1:+1.05VS_ASATA3PLL(5605.00 2122.00) CH2:+1.05VS_APLLOPI(4590.00 2329.00) CH3:+1.05VS_AXCK_LCPLL(5605.00 2295.00) CH4:PM_PCH_PWROK_R (4929.00 1526.00) S5-S0: S3-S0: CH1:+1.5VS(5323.00 2125.00) CH2:+3VS_+1.8VS_SDIO(5374.70 1692.80) CH3: +3VS(5300.00 1593.00) CH4:PM_PCH_PWROK_R (4929.00 1526.00) S5-S0: S3-S0: CH1:+1.05VM_VCCASW(4551.00 2457.00) CH4:PM_PCH_PWROK_R (4929.00 1526.00) S5-S0: S3-S0: PCH_PWROK high to PLTRST# de-assertion (S5-S0/S3-S0) t205b t205b Note Specification >1ms S5-S0 >1ms S3-S0 #12 Measured Result 56.201ms 61.201ms Result: Pass Fail CH1:PLT_RST#(5041.00 1626.00) CH2:PM_PCH_PWROK_R (4929.00 1526.00) S5-S0: S3-S0: PCH_PWROK deglitch time(S5-S0/S3-S0) t206 S5-S0 t206 S5-S0 Note Specification >1ms >1ms #5 Measured Result NA NA Result: Pass Fail CH2:PM_PCH_PWROK_R (4929.00 1526.00) CH3: VccASW active to APWROK high t207 Note Specification >1ms Measured Result 109.15ms Result: Pass Fail CH2:+1.05VM_VCCASW(4551.00 2457.00) CH4:PM_APWROK_R(4990.00 1526.00) PCH_PWROK high to PCH clock outputs stable(S5-S0/S3-S0) t208 S5-S0 t208 S3-S0 Note Specification >1ms >1ms #7 Measured Result 50.68ms 50.74ms Result: Pass Fail CH1:PM_PCH_PWROK_R (4929.00 1526.00) CH4:CLK_PCIE_WLAN_PCH (765.00 1773.00) S5-S0: S3-S0: PCH clock output stable to PROCPWRGD High (S5-S0/S3-S0) t209 S5-S0 t209 S3-S0 Note Specification >1ms >1ms Measured Result 2.06ms 1.88ms Result: Pass Fail CH1:H_CPUPWRGD_R (5535.00 3488.00) CH4:CLK_PCIE_WLAN_PCH (765.00 1773.00) S5-S0: S3-S0: PROPWRGD and SYS_PWROK high to SUS_STAT# deassertion(S5-S0/S3-S0) t210 S5-S0 t210 S3-S0 Note Specification >1ms >1ms Measured Result NA NA Result: Pass Fail SUS_STAT# deassertion to PLTRST# deassertion t211 S5-S0 t211 S3-S0 Note Specification >60us >60us Measured Result NA NA Result: Pass Fail #A: This is for design that supports M3, If ME is only on in S0, Intel expect VccASW to be shared with Vcc Vcc includes VccIO, Vcc, Vcc3_3, VccADAC1_5, VccADACBG3_3, V_PROC_IO, VccCLK, VccCLK3_3, VccVRM, and VccASW (if Intel® ME only powered in S0). VccASW active to Vcc active t229 Note Specification >0ms #A Measured Result NA Result: Pass Fail APWROK high to PCH_PWROK high t230 Note Specification >=0ms Measured Result 0ms Result: Pass Fail CH1:PM_APWROK_R(4990.00 1526.00) CH2:PM_PCH_PWROK_R (4929.00 1526.00) APWROK falling to VccASW falling t232 Note Specification >40ns #10,#11,#13,#14 Measured Result 90us Result: Pass Fail CH1:PM_APWROK_R(4990.00 1526.00 CH2:+1.05VM_VCCASW(4551.00 2457.00) SLP_S3# assertion to Vcc rail falling t233 Note Specification >5us #8,#9 Measured Result 10.4ms Result: Pass Fail CH1: N19050076(5225.00 2128.00) CH2:+1.05VS(5420.00 2157.12) CH3:+1.05VS_AUSB3PLL(5780.00 2390.51) CH4: PM_SUSB# (6003.66 687.23) CH1:+1.05VS_ASATA3PLL(5605.00 2122.00) CH2:+1.05VS_APLLOPI(4590.00 2329.00) CH3:+1.05VS_AXCK_LCPLL(5605.00 2295.00) CH4: PM_SUSB# (6003.66 687.23) CH1:+1.5VS(5323.00 2125.00) CH2:+3VS_+1.8VS_SDIO(5369.00 1690.00) CH3: +3VS(5300.00 1593.00) CH4: PM_SUSB# (6003.66 687.23) CH2:+1.05VM_VCCASW(4551.00 2457.00) CH1: PM_SUSB# (6003.66 687.23) 1.1.3 S5/Moff to S5 /M3 Timings #1: Refer to 503118_503118_Lynx_Point_LP_EDS_Rev_2p2_Final in detail. #2. APWROK high to SPI Soft Strap Read is an internal PCH timing. The timing cannot be measured externally and included here for general power sequencing reference. #3. Requires SPI messaging to be completed. VccASW stable to APWROK high t207 Note Specification >1ms Measured Result 108.75ms Result: Pass Fail CH1:+1.05VM_VCCASW(4551.00 2457.00) CH2:PM_APWROK_R(4990.00 1526.00) APWROK high to SPI Soft-Start Reads t212 Note Specification >500us #2 Measured Result 578.4us Result: Pass Fail CH1:PM_APWROK_R(4990.00 1526.00) CH2:SPI1_CLK(4975.00 1077.00) CH4:SPI1_SI(5025.00 1077.00) APWROK high to CL_RST1# deasserted t213 Note Specification >500us #3 Measured Result NA For mobile Result: Pass Fail CH1:PM_APWROK_R(4990.00 1526.00) CH2:CL_RST#(846.65 1406.49) 1.1.4 S0 to S5 Timings #1: Refer to 503118_503118_Lynx_Point_LP_EDS_Rev_2p2_Final in detail. DMI message and all PCI Express ports and DMI in L2/L3 state to SUS_STAT# active t214 Note Specification >60us Measured Result NA Result: Pass Fail SUS_STAT# active to PLT_RST# active t215 Note Specification >210us Measured Result NA Result: Pass Fail PLTRST# active to PROCPWRGD inactive t217 Note Specification >30us Measured Result 36.04us Result: Pass Fail CH1:PLT_RST#(5041.00 1626.00) CH2:H_CPUPWRGD_R (5535.00 3488.00) PROCPWRGD inactive to clocks invalid t218 Note Specification >10us Measured Result 31.6us Result: Pass Fail CH1:H_CPUPWRGD_R (5535.00 3488.00) CH2:CLK_PCIE_WLAN_PCH (765.00 1773.00) Clocks invalid to SLP_S3# assertion t219 Note Specification >1us Measured Result 58us Result: Pass Fail CH1:PM_SUSB# (6003.66 687.23) CH2:CLK_PCIE_WLAN_PCH (765.00 1773.00) SLP_S3# low to SLP_S4# low t220 Note Specification >30us Measured Result 97.5us Result: Pass Fail CH1:PM_SUSB# (6003.66 687.23) CH2:PM_SUSC# (5877.00 615.00) SLP_S4# low to SLP_S5# low t221 Note Specification >30us Measured Result NA Result: Pass Fail SLP_S3# active to PCH_PWROK deasserted t222 Note Specification >0 Measured Result 10.4ms Result: Pass Fail CH3:PM_SUSB# (6003.66 687.23) CH2:PM_PCH_PWROK_R (4929.00 1526.00) S3/S4/S5 to Deep Sx to G3 w/RTC Loss Timing Diargam #1: Refer to 503118_503118_Lynx_Point_LP_EDS_Rev_2p2_Final in detail. #2. VccSus supplies include VccSus3_3 and VccSusHDA(if VCCHDA is on suspend well). Also includes DcpSus for mobile platforms that power DcpSus externally. #3. Board design may meet (t231 AND t232 AND t234 AND t235) OR (t238). #4. The definition of rail falling for this timing requirement is as follows:1)VCCDSW3_3 and VCCSUS3_3 is 2.9V; 2) VCCASW and DCPSUS*(in external suspend VR mode) is 0.92V; 3)VCC is 0.99V #5.Requirment applies to power failure and surprise power down scenario. As long as the board follows the recommended power-well control signals(that is,SLP_S3#, SLP_A# and SLP_SUS#), the PCH guarantees proper isolation during the normal graceful power down events. #6. Ensure respective PWROK signals(PCH_PEROK,APWROK and RSMRST#) toggle appropriately during normal power state transiton(for example S0->SX->S0,S0->DEEP SX->S0,etc.) even if the supply voltage does not drop below the specified value. Use of the stretch registers can be used to achieve this. DPWROK falling to VccDSW3_3 rail falling(with deep) t234 Note Specification >40ns #3,#4,#5,#6 Measured Result NA Result: Pass Fail RSMRST# assertion to VccSUS rail falling(with deep) t235 Note Specification >40ns #2,#3,#4,#5,#6 Measured Result NA Result: Pass Fail RTCRST# deassertion to VccRTC rail falling(with deep) t236 Note Specification >0ms Measured Result NA Result: Pass Fail Power Sequence and reset signal timing #1: Refer to 503118_503118_Lynx_Point_LP_EDS_Rev_2p2_Final in detail. #2. VccSus supplies include VccSus3_3 and VccSusHDA. Also includes DcpSus for mobile platforms that power DcpSus externally. #3. Dependency on SLP_S4# and SLP_A# stretching #4. Dependency on SLP_S3# and SLP_A# stretching #5. Vcc includes VCC1_05,VCCCLK,VCCHSIO,VCCUSB3PLL,VCCSATA3PLL,VCCAPLL,VCCACLKPLL, VCCTS1_5,VCCSDIO,VCC3_3 and VccASW (if Intel® ME only powered in S0). #6. Board design may meet (t231 AND t232 AND t234 AND t235) OR (t238). #7. The definition of rail falling for this timing requirement is as follows:1)VCCDSW3_3 and VCCSUS3_3 is 2.9V; 2) VCCASW and DCPSUS*(in external suspend VR mode) is 0.92V; 3)VCC is 0.99V #8. RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.9 V #9. The 50 μs should be measured from Vih to Vil (2 V to 0.78 V). #10. DPWROK falling edge must transition to 0.8V or less before VccDSW3_3 drops to 2.9V #11. This is an internal timing showing when the signals (SLP_S5#, SLP_S4#, SLP_S3#, SUS_STAT#, PLTRST# and PCIRST#) are valid after VccSus rail is Active. #12. Programmable via PM_CFG.PWR_CYC_DUR Default is 4-5 seconds. #13:Requirment applies to power failure and surprise power down scenario. As long as the board follows the recommended power-well control signals(that is,SLP_S3#, SLP_A# and SLP_SUS#), the PCH guarantees proper isolation during the normal graceful power down events. #14:Ensure respective PWROK signals(PCH_PEROK,APWROK and RSMRST#) toggle appropriately during normal power state transiton(for example S0->SX->S0,S0->DEEP SX->S0,etc.) even if the supply voltage does not drop below the specified value. Use of the stretch registers can be used to achieve this. #15. Full Icc load must be support by then end of t258. #16. “Active” is defined as VCCmin and is 1.05v-5%. #17. VCCHSIO cannot take the full 65us max ramp time due to the filters on VCCUSB3PLL and VCCSATA3PLL. Base on the existing recommended filter capacitors for the PLLs, VCCHSIO rails will need to ramp within ~22us VccSUS active to VccASW active t227 Note Specification >0ms #2 Measured Result AC Power on Result: Pass Fail CH2:+3VSUS_VCCPUSB(4369.00 2496.00) CH4:+1.05VM_VCCASW(4551.00 2457.00) SLP_LAN# (or LANPHYPC) rising to Intel LAN Phy power high and stable t237 Note Specification <20ms Measured Result NA Result: Pass Fail VccSus supplies active to Vcc supplies active t241 Note Specification >0ms #2,#5 Measured Result AC Power on Result: Pass Fail CH1:+3VSUS_VCCPUSB(4369.00 2496.00) CH2:+3VSUS_VCCPUSB(4369.00 2496.00) CH3: +1.05VM_VCCASW(4551.00 2457.00) CH4:+VCCDSW(4876.00 1998.00) CH1:+3VSUS_VCCPUSB(4369.00 2496.00) CH2: N19050076(5225.00 2128.00) CH3:+1.05VS(5420.00 2159.00) CH4:+1.05VS_AUSB3PLL(5780.00 2390.51) CH1:+3VSUS_VCCPUSB(4369.00 2496.00) CH2:+1.05VS_ASATA3PLL(5605.00 2122.00) CH3:+1.05VS_APLLOPI(4590.00 2329.00) CH4:+1.05VS_AXCK_LCPLL(5605.00 2295.00) CH1:+3VSUS_VCCPUSB(4369.00 2496.00) CH2:+1.5VS(5323.00 2125.00) CH3:+3VS_+1.8VS_SDIO(5369.00 1690.00) CH4:+3VS(5300.00 1593.00) HDA_RST# active low pulse width t242 Note Specification >1us Measured Result 192.801us Result: Pass Fail CH1:HDA_BCLK_R_CODEC/I2S_BCLK(6755.00 -522.00) CH2:N24952770(6657.36 -566.89) VccSus active to SLP_S5#,SLP_S4#,SLP_S3#,SUS_STAT#,PLTRST# and PCIRST# valid t244 Note Specification <50ns #11 Measured Result AC Power on Result: Pass Fail CH1:+3VSUS_VCCPUSB(4369.00 2496.00)CH2: PM_SUSC# (5877.00 615.00) CH3:PM_SUSB# (6003.66 687.23) CH4:PLT_RST#(5041.00 1626.00) S4 Wake Event to SLP_S4# inactive(S4 wake) t246 Note Specification See note below #3 Measured Result 220.201us Result: Pass Fail CH2: PM_SUSC# (5877.00 615.00) CH1:PM_PWRBTN# (3846.20 1928.00) S3 Wake Event to SLP_S3# inactive(S3 wake) t247 Note Specification See note below #4 Measured Result 209.701us Result: Pass Fail CH2:PM_SUSB# (6003.66 687.23) CH1:PM_PWRBTN#(3846.20 1928.00) RSMRST# deassertion to APWROK assertion t251 Note Specification >0ms Measured Result AC Power on Result: Pass Fail CH2:PM_RSMRST_R(4731.00 2157.00) CH3:PM_APWROK_R(4990.00 1526.00) THRMTRIP# active to SLP_S3#, SLP_S4#, SLP_S5# active t252 Note Specification <175ns Measured Result 14.4ms Result: Pass Fail CH1: PM_THRMTRIP#(5613.00 3260.00) CH2: PM_SUSC# (5877.00 615.00) CH3:PM_SUSB# (6003.66 687.23) RSMRST# rising edge transition from 20% to 80% t253 Note Specification <50us Measured Result 23.78ns Result: Pass Fail CH2:PM_RSMRST_R(4731.00 2157.00) DPWROK rising edge transition from 20% to 80%(with deep) t255 Note Specification <50us Measured Result NA Result: Pass Fail DPWROK falling edge transition(with deep) t256 Note Specification >0us (DPWROK fall to VccDSW3_3) <50us DPWROK falling time #9,#13 Measured Result NA NA Result: Pass Fail Power-cycle duration for a global reset other than G3 or Deep Sx, Also the duration of a host reset with power-cycle t257 Note Specification >4-5sec Measured Result NA Result: Pass Fail HSIOPC assertion to VCCHSIO,VCCUSB3PLL and VCCSATA3PLL active. t258 Note Specification <65us Measured Result 488.4us Result: Pass Fail CH1: HSIO_PWR_CNTL(5055.00 1508.00)CH2: N19050076(5225.00 2128.00)CH3:+1.05VS_AUSB3PLL(5780.00 2390.51) CH4:+1.05VS_ASATA3PLL(5605.00 2122.00) AC Timing #0: Refer to Shark Bay Mobile and Ultrabook™ Platform Power Sequence Specification December 2012 Revision 1.3 in detail Refer to Haswell U/Y Platform Design Guide For use with Haswell U/Y Processor October 2013 Revision 2.3 in detail Refer to 503118_503118_Lynx_Point_LP_EDS_Rev_2p2_Final in detail. #1:VCCSus3_3 must be powered up before VCCSUS(DCPSUS), or not more than 0.7V below VCCSUS(DCPSUS) while the two rails ramp up. VCCSus3_3 must be powered down after VCCSUS1.05(DCPSUS), or not more than 0.7V below VCCSUS(DCPSUS) while the two rails ramp down. VCCSus3_3 active to VCCSUS Note Specification Figure 6-35 Measured Result Ac Power On #1 Result: Pass Fail CH2:+3VSUS_VCCPUSB(4369.00 2496.00) CH3:+1.05A_VCCUSB3SUS() VCCSUS1.05 falling to VCCSus3_3 falling Note Specification Figure 6-35 Measured Result Ac Power On #1 Result: Pass Fail CH2:+3VSUS_VCCPUSB(4369.00 2496.00) CH3:+1.05A_VCCUSB3SUS() #2:VCC3_3/ VCCADACBG3_3 may power up before VCC, but VCC must ramp up to 0.6V within 25ms of VCC3_3/VCCADACBG3_3 ramping to 2.6 V. See timing diagram for measurement points VCC may power down before VCC3_3/VCCADACBG3_3,but the VCC3_3/VCCADACBG3_3 must ramp down to 2.6-V within 35-ms assuming a linear ramp. VCC powers up before VCCCORE, VCCCORE may power up before VCC, but VCC must ramp up to 0.6-V within 25 ms of VCC VCCCORE ramping to 1.35 V. VCC powers down after VCCCORE, VCC may power down before VCCCORE, but VCCCORE must ramp downto 1.35 V within 35 ms assuming a linear ramp. VCC3_3/VCCADACBG3_3 powers up before VCC Note Specification <=25ms Figure 6-36 Measured Result 460us #2 Result: Pass Fail CH1: +3VS(5300.00 1593.00) CH2:+1.05VS(5420.00 2159.00) VCC power down before VCC3_3/VCCADACBG3_3 Note Specification <=35ms Figure 6-36 Measured Result 100us #2 Result: Pass Fail CH1: +3VS(5300.00 1593.00) CH2:+1.05VS(5420.00 2159.00) VCCCORE power up before VCC power up v Note Specification <=25ms Figure 6-37 Measured Result 620us #2 Result: Pass Fail CH1:+1.5VS(5323.00 2125.00) CH2:+1.05VS(5420.00 2159.00) VCC power down before VCCCORE power down Note Specification <=35ms Figure 6-37 Measured Result -60us #2 Result: Pass Fail CH1:+1.5VS(5323.00 2125.00) CH2:+1.05VS(5420.00 2159.00) VCCDSW3_3 ramps up before VBUS reaches 1.05 V Note Specification Figure 6-34 Measured Result Ac Power On Result: Pass Fail CH2:+VCCDSW(4876.00 1998.00) CH3:+5V_U2U_GPS(693.00 5623.00) VccDSW3_3 active to DPWROK active Note Specification >10ms Measured Result 18.98ms Result: Pass Fail CH1:PCH_DPROK(4702.00 2123.00) CH2: +VCCDSW(4876.00 1998.00) VCCHSIO rising slew rate Note Specification <0.7V/us Measured Result 0.0034V/us Result: Pass Fail CH2: N19050076(5225.00 2128.00) Sata and PCIe IREF/RCOMP, VCCUSB3PLL, VCCSATA3PLL slew rate Note Specification <0.1V/us Measured Result 0.0035V/us Result: Pass Fail CH2:+1.05VS_ASATA3PLL(5605.00 2122.00) CH3:+1.05VS_AUSB3PLL(5780.00 2390.51) CPU (Desktop)Power Sequence Timing Diagram(Haswell) #1: 453513_453513_VR12.5_PMW_spec_1.5 in detail. 486711_486711_ Haswell Desktop and Denlow-WS Platform Design Guide For Use with Haswell Processor and Haswell Platform Controller Hub (PCH) Revision 2.2 May 2014 in detail. 453513_453513_VR12.5_PMW_spec_1.5 in detail. Refer to Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family External Design Specification (EDS) – Volume 1 of 2 Supporting 4th Generation Intel® Core™ processor based on Mobile U-Processor and Y-Processor Lines Supporting Mobile Intel® Pentium® Processor and Mobile Intel® Celeron® Processor Families April 2014 in detail. TA TB TC TD TE Specification <5ms <1ms <100us 0~1us <500ns Measured Result 868us 116us 8us NA NA Result: Pass Fail TA: CH1:+VCORE(5275.00 3125.43) CH2:CPU_VRON_PWR(6490.00 4043.00) TB: CH1:+VCORE(5275.00 3125.43) TC: CH1:+VCORE(5275.00 3125.43) CH2:CPU_VR_READY_R(5525.00 3607.00) T1:VCCST and VDDQ must both be within voltage spec before VCCST_PWRGD asserts. VCCST_PWRGD should assert a minimum of 1ms after both VCCST and VDDQ have both ramped T2:VCCST and VDDQ ordering has the following restrictions a. If VCCST ramps before VDDQ, then VDDQ must complete ramping within 25ms b. If VDDQ ramps before VCCST, there is no limit on timing between these rails T3:VDDQ must ramp before VCCIN ,VCCST must complete it’s ramp at least 1us before VCCIN starts to ramp T1 T2 T3: Specification >=1ms <=25ms >=1us Measured Result 1.16ms 4.63ms 2.03ms Result: Pass Fail T1: CH3:+1.05VS_VCCST(5335.00 3522.00) CH2:+1P35V_DUAL(4666.38 2850.00) CH1:+1.05VS_PWRGD_S_R(5700.00 3623.00) T2: CH1:+1P35V_DUAL(4666.38 2850.00) CH2:+1.05VS_VCCST(5335.00 3522.00) T3: CH1:+1.05VS_VCCST(5335.00 3522.00) CH2:+1P35V_DUAL(4666.38 2850.00) CH4:+VCORE(5275.00 3125.43) VccST active to PCH_PWROK high (S5-S0/S3-S0) t205a Note Specification >1ms Measured Result 108.651ms Result: Pass Fail CH1:+1.05VS_VCCST(5335.00 3522.00) CH2:PM_PCH_PWROK_R(4929.00 1526.00) S5-S0 S3-S0 3V active to PCH CORE (1.05V) or VCCST Note Specification <25ms Measured Result 484us Result: Pass Fail CH1:+1.05VS_VCCST(5335.00 3522.00) CH2:+3VS(5300.00 1593.00) VCCADAC/VCCTS active to PCH CORE (1.05V) or VCCST Note Specification <25ms Measured Result 677us Result: Pass Fail CH1:+1.05VS_VCCST(5335.00 3522.00) CH2:+1.5VS(5323.00 2125.00) VR_EN to CPU PWRGOOD assertion Note Specification >=5ms Measured Result 178.4ms Result: Pass Fail CH1:CPU_VRON_PWR(6490.00 4043.00) CH2:H_CPUPWRGD_R(5535.00 3488.00) #0Shark Bay Mobile and Ultrabook™ Platform Power Sequence Specification December 2012 Revision 1.3 in detail. #1. Unless otherwise noted, all specifications in this table apply to all processor frequencies #2. No edge rate requirement, but edge must be monotonic. #3. VCCST_PWRGD must accurately reflect the state of VCCST and must not glitch when VCCST or VDDQ power is applied. Additionally, VCCST_PWRGD must track to the state of PCH_PWROK on the platform. If PCH_PWROK de-asserts during S0 --> Sx transitions, then VCCST_PWRGD must also de-assert. #4. CPU’s PWRGOOD is not required externally on the platform, but is available for monitoring. #5. 10 BCLK cycles and 10 24M clock cycles VCCST ramped and stable to VCCST_PWRGD assertion Tcpu00 Note Specification >1ms Measured Result 1.156ms CH1: +1.05VS_VCCST(5335.00 3522.00) CH2:+1.05VS_PWRGD_S_R(5700.00 3623.00) VDDQ ramped and stable to VCCST_PWRGD assertion Tcpu01 Note Specification >1ms Measured Result 5.82ms CH2:+1.05VS_PWRGD_S_R(5700.00 3623.00) CH4:+1P35V_DUAL(4666.38 2850.00) VCCST ramping & stable before VDDQ stable Tcpu02a Note Specification <25ms Measured Result 4.68ms CH1: +1.05VS_VCCST(5335.00 3522.00) CH4:+1P35V_DUAL(4666.38 2850.00) VDDQ ramping & stable before VCCST stable Tcpu02b Note Specification Measured Result NA CH3:+1P35V_DUAL(4666.38 2850.00) CH1: +1.05VS_VCCST(5335.00 3522.00) VDDQ ramping & stable before VCCIN ramps Tcpu03 Note Specification >100ns Measured Result 6.67ms CH4:+1P35V_DUAL(4666.38 2850.00) CH2:+VCORE(5275.00 3125.43) VCCST ramping & stable before VCCIN ramps Tcpu04 Note Specification >100ns Measured Result 2.02ms CH2:+VCORE(5275.00 3125.43) CH1: +1.05VS_VCCST(5335.00 3522.00) VCCST_PWRGD assertion to VR_EN assertion Tcpu05 Note Specification <100ns Measured Result -401ns CH1:+1.05VS_PWRGD_S_R(5700.00 3623.00) CH2:CPU_VRON_PWR(6490.00 4043.00) BCLK / 24MHz Clks stable to PWRGOOD Tcpu06 Note Specification >10clks Measured Result 76us CH1:XTAL_24M_IN(5929.66 2369.23) CH2:H_CPUPWRGD_R(5535.00 3488.00) VR_EN asserted until VCCIN ramped to Vboot Tcpu07 Note Specification <2.5ms Measured Result 867.5us CH1:CPU_VRON_PWR(6490.00 4043.00) CH2:+VCORE(5275.00 3125.43) PWRGOOD assertion to PLTRST# de-assertion Tcpu12 Note Specification >1ms Measured Result 9ms CH1:PLT_RST#(5041.00 1626.00) CH2:H_CPUPWRGD_R(5535.00 3488.00) DDR_PG_CTL assertion to DDR VTT supplied ramped and stable Tcpu13 Note Specification <35us Measured Result 4.3us CH1: DDR_PG_CTRL(3880.00 3532.00) CH2: +0.675V(3975.00 4615.00) VCCST_PWRGD deassertion to VCCST rail dropping 5% from nominal value Tcpu14 Note Specification <40ns Measured Result 240us CH1: +1.05VS_VCCST(5335.00 3522.00) CH2:+1.05VS_PWRGD_S_R(5700.00 3623.00) ALL_SYS_PWRGD high to PLTRST# de-assertion Tcpu15 Note Specification 5ms Measured Result 163.6ms Result: Pass Fail CH4:PLT_RST#(5041.00 1626.00) CH3:ALL_SYSTEM_PWRGD_R(5478.66 482.23) 5. Reset Timing THERMTRIP# Power Down Sequence THERMTRIP# Assertion until Vcc removal Skew Note Specification <0.5s Measured Result 7.14ms Result: Pass Fail CH1:PM_THRMTRIP# (5613.00 3260.00) CH2:+VCORE(5275.00 3125.43) 6. Other #1: Refer to 486708_486708 Lynx Point Platform Controller Hub (PCH) External Design Specification (EDS) Revision 1.5 October 2012 in detail Measure BATT when RSMRST at power down Voltage Drop Note Specification 2~3.6V BATT 3.132~3.348V Result: Pass Fail CH1:+VCC_RTC(4894.90 2036.60) CH2: PM_RSMRST_R(4731.00 2157.00) Mini Card(WLAN) Power Sequence #1. Refer to PCI Express® Mini Card Electromechanical Specification Revision 1.2 #2. CLKREQ# is asserted in response to PERST# assertion. On power up, CLKREQ# must be asserted by a PCI Express device within a delay (TPVCRL) from the power rails achieving specified operating limits and PERST# assertion. This delay is to allow adequate time for the power to 5 stabilize on the card and certain system functions to start prior to the card starting up. CLKREQ# may not be de-asserted while PERST# is asserted. Power Up Power Valid to PERST# Input inactive TPVPGL Note Specification >1ms #3 Measured Result Result: Pass Fail CH1: MINI1_PLTRST# CH2: MINI1_3P3AUX CH3: +1P5V_PE1 REFCLK stable before PERST# inactive TPERST#-CLK Note Specification >100us #3 Measured Result Result: Pass Fail CH1: MINI1_PLTRST# CH2: CK_100M_MINI1 PCIE Power Sequence #1. Refer to PCI-E Electromechanical Spec. Rev:1.0a #2. Any supplied power is stable when it meets the requirements specified for that power supply. #3. A supplied reference clock is stable when it meets the requirements specified for the reference clock. The PERST# signal is asserted and de-asserted asynchronously with respect to the supplied reference clock. #4. The PERST# signal must be asserted within TFAIL of any supplied power going out of specification. #5. Measured from WAKE# assertion/de-assertion to valid input level at the system PM controller. Since WAKE# is an open-drain signal, the rise time is dependent on the total capacitance on the platform and the system board pull-up resistor. It is the responsibility of the system designer to meet the rise time specification. Power Up(G3-S0) Power stable to PERST# inactive Tpvperl Note Specification >100ms #2 Measured Result NA wlan Result: Pass Fail 100us #3 Measured Result wlan Result: Pass Fail CH3: PLT_RST#_BUF_S(222.18 799.81) CH2: CLK_PCIE_WLAN_PCH(2304.25 6027.00) Power Management States(S0 to S3/S4 to S0) PERST# active to Power not stable S0-S3 S0-S4 Note Specification #2 Measured Result NA NA wlan Result: Pass Fail CH2: +3V_WLAN(545.00 1350.00) CH3:PLT_RST#_BUF_S(222.18 799.81) S0-S3: S0-S4: PERST# active to REFCLK and JTAG inactive S0-S3 S0-S4 Note Specification #3 Measured Result 800ns -1.2us wlan Result: Pass Fail CH1: CLK_PCIE_WLAN_PCH (765.00 1773.00) CH3: PLT_RST#_BUF_S(222.18 799.81) S0-S3: S0-S4: PERST# active time Tperst(S0-S3-S0) Tperst(S0-S4-S0) Note Specification >100us >100us #5 Measured Result 7.704ms 7.914ms wlan Result: Pass Fail CH3:PLT_RST#_BUF_S(222.18 799.81) S0-S3-S0: S0-S4-S0: Power Down PERST# active to Power not stable Note Specification #2 Measured Result NA wlan Result: Pass Fail CH2: +3V_WLAN(545.00 1350.00) CH3:PLT_RST#_BUF_S(222.18 799.81) PERST# active to REFCLK and JTAG inactive Note Specification #3 Measured Result 6.5us wlan Result: Pass Fail CH1: PLT_RST#_BUF_S(222.18 799.81) CH3: CLK_PCIE_WLAN_PCH (765.00 1773.00) Power level invalid to PERST# active Tfail Note Specification <500ns #4 Measured Result 100us wlan Result: Pass Fail CH1: +3V_WLAN(545.00 1350.00) CH3:PLT_RST#_BUF_S(222.18 799.81) STDP9320 Power rails sequence #1: Refer to STDP9320, STDP9310, STDP9210 STDP7320, STDP7310Athena — Premium high resolution multimedia monitor controller with 3D video in detail. #1;T1:The 3.3 V LPM rail must be energized at the same time or earlier than the 3.3 V main rail. There is no maximum limit to this sequence. #2:T2:The 1.2 V LPM rail must be energized within a maximum of 70 ms of the 3.3 V LPM rail coming up. This ensures that the LPM digital core is powered when the LPM reset cell is still asserting reset. The only minimum limit on the 1.2 V LPM rail is that it must not be powered up before the 3.3 V LPM rail (i.e. the 1.2 V LPM rail must not exceed the 3.3 V LPM rail by within one diode drop). #3:T3:VDD2V5_LPM_SAFEMEM must not be powered before VDD1V2_LPM_DIG. This is a SAFEMEM power sequencing requirement. #4:T4:The 1.2 V main rail must be energized within a maximum of 70 ms of the 3.3 V main rail coming up. This ensures the mission digital core is powered when the mission reset cell is still asserting reset. The only minimum limit on the 1.2 V main rail is that it must not be powered up before the 3.3V main rail (i.e. the 1.2 V main rail must not exceed the 3.3V main rail by within one diode drop). #5:T5:There is no power sequencing requirement between VDD3V3_DIG and mission rails other than VDD1V2_DIG. 3.3 V LPM rail active to 3.3 V main rail Note Specification >0ms #1 Measured Result 19.23ms Result: Pass Fail CH2: +3.3V_LPM (1649.02 2354.40) CH1: +3.3V (439.00 3752.00) 1.2 V LPM rail active to 3.3 V LPM active Note Specification 0ms~70ms #2 Measured Result 9.22ms Result: Pass Fail CH2: +3.3V_LPM(1644.00 2358.00) CH3:+1.2V_LPM(1047.50 2171.38) VDD1V2_LPM_DIG power up before VDD2V5_LPM_SAFEMEM Note Specification #3 Measured Result 4.8ms Result: Pass Fail CH3:+1.2V_LPM (1047.50 2171.38) CH2: +2V5_LPM(825.00 2230.12) VDD2V5_LPM_SAFEMEM power down before VDD1V2_LPM_DIG Note Specification #3 Measured Result 0ms Result: Pass Fail CH2:+1.2V_LPM (1047.50 2171.38) CH3: +2V5_LPM(825.00 2230.12) 3.3 V main rail power up before 1.2 V main rail power up Note Specification <70ms #4 Measured Result 23.8ms Result: Pass Fail CH2: +3.3V (439.00 3752.00) CH1: +1.2V(917.00 4279.00)

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