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P1020 QorIQ Integrated Processor Reference Manual Supports: P1020 and P1011 Document Number: P1020RM Rev. 6, 01/2013 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 2 Freescale Semiconductor, Inc. Section number Contents Title Page Chapter 1 Overview 1.1 Overview.......................................................................................................................................................................61 1.1.1 Block diagram............................................................................................................................................61 1.1.2 Critical performance parameters................................................................................................................62 1.1.3 Chip-level features.....................................................................................................................................62 1.2 P1020 Application examples........................................................................................................................................64 1.2.1 Dual-core device application.....................................................................................................................64 1.2.2 High-performance communication system ...............................................................................................65 1.2.3 RAID controller application ......................................................................................................................66 1.2.4 SMB gateway application .........................................................................................................................67 1.2.5 WLAN access point application ...............................................................................................................68 1.3 Architecture overview...................................................................................................................................................69 1.3.1 e500v2 cores and memory unit..................................................................................................................69 1.3.2 e500 coherency module (ECM) and address map.....................................................................................70 1.3.3 Integrated security engine (SEC 3.3.2)......................................................................................................70 1.3.4 Enhanced three-speed Ethernet controllers................................................................................................71 1.3.5 Universal serial bus (USB) 2.0 controllers................................................................................................72 1.3.6 Enhanced secure digital host controller.....................................................................................................73 1.3.7 Serial peripheral interface (SPI).................................................................................................................73 1.3.8 DDR SDRAM controller...........................................................................................................................74 1.3.9 High-speed I/O interfaces..........................................................................................................................74 1.3.9.1 PCI Express interfaces...........................................................................................................75 1.3.9.2 SGMII....................................................................................................................................75 1.3.9.3 High-speed interface multiplexing.........................................................................................75 1.3.10 Programmable interrupt controller (PIC)...................................................................................................76 1.3.11 Time division multiplexing (TDM) interface ...........................................................................................76 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 3 Section number Title Page 1.3.12 DMA, I2C, DUART, and enhanced local bus controller...........................................................................76 1.3.13 Device boot locations.................................................................................................................................77 1.3.14 Boot sequencer...........................................................................................................................................77 1.3.15 System performance monitor.....................................................................................................................78 Chapter 2 Memory Map 2.1 Overview.......................................................................................................................................................................79 2.2 Configuration, control, and status registers..................................................................................................................80 2.2.1 Accessing CCSR memory from the local processor..................................................................................81 2.2.2 Accessing CCSR memory from external masters......................................................................................81 2.2.3 Organization of CCSR space.....................................................................................................................82 2.2.3.1 General utilities registers.......................................................................................................82 2.2.3.1.1 General utilities register organization.............................................................83 2.2.3.2 Programmable interrupt controller registers..........................................................................84 2.2.4 Device-specific utilities registers...............................................................................................................85 2.2.5 CCSR address map.....................................................................................................................................86 2.3 Local access windows...................................................................................................................................................88 2.3.1 Precedence of local access windows .........................................................................................................89 2.3.2 Configuring local access windows.............................................................................................................89 2.3.3 Distinguishing local access windows from other mapping functions........................................................90 2.3.4 Illegal interaction between local access windows and DDR chip selects..................................................90 2.3.5 Local address map example.......................................................................................................................90 2.4 Local Access Window Registers..................................................................................................................................91 2.4.1 Local access window n base address register (LAW_LAWBARn)..........................................................93 2.4.2 Local access window n attribute register (LAW_LAWARn)....................................................................93 2.5 Address translation and mapping units.........................................................................................................................95 2.5.1 Address translation ....................................................................................................................................95 2.5.2 Outbound ATMUs.....................................................................................................................................96 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 4 Freescale Semiconductor, Inc. Section number Title Page 2.5.3 Inbound ATMUs........................................................................................................................................96 2.5.3.1 Illegal interaction between inbound ATMUs and LAWs......................................................97 Chapter 3 Signal Descriptions 3.1 General overview..........................................................................................................................................................99 3.2 Signals overview...........................................................................................................................................................99 3.3 Configuration signals sampled at reset.........................................................................................................................109 3.4 Output Signal States During Reset...............................................................................................................................111 Chapter 4 Reset, Clocking, and Initialization 4.1 Overview.......................................................................................................................................................................115 4.2 Reset external signal descriptions.................................................................................................................................115 4.2.1 System control signals...............................................................................................................................116 4.2.2 Clock signals..............................................................................................................................................117 4.3 Accessing configuration, control, and status registers..................................................................................................118 4.3.1 Updating CCSRBAR.................................................................................................................................118 4.3.2 Accessing alternate configuration space....................................................................................................119 4.3.3 Boot page translation.................................................................................................................................120 4.3.4 Boot sequencer...........................................................................................................................................120 4.4 Reset Memory Map/Register Definition.......................................................................................................................120 4.4.1 Configuration, control, and status registers base address register (reset_CCSRBAR)..............................121 4.4.2 Alternate configuration base address register (reset_ALTCBAR)............................................................122 4.4.3 Alternate configuration attribute register (reset_ALTCAR)......................................................................122 4.4.4 Boot page translation register (reset_BPTR).............................................................................................123 4.5 Functional description...................................................................................................................................................123 4.5.1 Reset operations.........................................................................................................................................123 4.5.1.1 Soft reset................................................................................................................................124 4.5.1.2 Hard reset...............................................................................................................................124 4.5.2 Power-on reset sequence............................................................................................................................124 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 5 Section number Title Page 4.5.3 4.5.4 Power-on reset configuration.....................................................................................................................126 4.5.3.1 System PLL ratio...................................................................................................................127 4.5.3.2 DDR PLL ratio.......................................................................................................................128 4.5.3.3 e500 core PLL ratios..............................................................................................................128 4.5.3.4 Boot ROM location................................................................................................................129 4.5.3.5 Host/agent configuration........................................................................................................130 4.5.3.6 I/O port selection....................................................................................................................131 4.5.3.7 CPU boot configuration.........................................................................................................132 4.5.3.8 Boot sequencer configuration................................................................................................133 4.5.3.9 DDR SDRAM type................................................................................................................134 4.5.3.10 SerDes reference clock configuration....................................................................................134 4.5.3.11 eTSECn configuration............................................................................................................135 4.5.3.11.1 eTSEC3 SGMII mode.....................................................................................135 4.5.3.11.2 eTSEC1 width.................................................................................................136 4.5.3.11.3 eTSEC1 protocol.............................................................................................136 4.5.3.11.4 eTSEC3 protocol.............................................................................................137 4.5.3.12 Memory debug configuration.................................................................................................138 4.5.3.13 DDR debug configuration......................................................................................................138 4.5.3.14 General-purpose POR configuration......................................................................................139 4.5.3.15 Engineering use POR configuration......................................................................................139 4.5.3.16 eLBC ECC enable configuration...........................................................................................139 4.5.3.17 System speed..........................................................................................................................140 4.5.3.18 Platform speed........................................................................................................................140 4.5.3.19 Core 0 speed...........................................................................................................................141 4.5.3.20 Core 1 speed...........................................................................................................................141 4.5.3.21 DDR speed.............................................................................................................................142 4.5.3.22 eSDHC card-detect polarity select.........................................................................................142 Voltage selection configuration.................................................................................................................143 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 6 Freescale Semiconductor, Inc. Section number Title Page 4.5.5 Clocking.....................................................................................................................................................144 4.5.5.1 System clock and DDR controller complex clock.................................................................144 4.5.5.2 PCI Express clock..................................................................................................................146 4.5.5.2.1 Minimum frequency requirements..................................................................147 4.5.5.3 SGMII clocks.........................................................................................................................147 4.5.5.4 Ethernet clocks.......................................................................................................................147 4.5.5.5 Real time clock.......................................................................................................................148 4.6 Initialization/applications information..........................................................................................................................149 4.6.1 eSDHC boot...............................................................................................................................................149 4.6.1.1 eSDHC boot overview...........................................................................................................150 4.6.1.2 eSDHC boot features.............................................................................................................151 4.6.1.3 SD/MMC card data structure.................................................................................................151 4.6.1.3.1 SD/MMC configuration words section...........................................................153 4.6.1.3.2 Notes on compatibility with FAT12/FAT16/FAT32 filesystems...................155 4.6.1.4 eSDHC controller initial configuration..................................................................................156 4.6.1.5 eSDHC controller boot sequence...........................................................................................157 4.6.1.6 eSDHC boot error handling...................................................................................................157 4.6.2 eSPI boot ROM..........................................................................................................................................159 4.6.2.1 eSPI boot overview................................................................................................................159 4.6.2.2 Features..................................................................................................................................160 4.6.2.3 EEPROM data structure.........................................................................................................161 4.6.2.3.1 EEPROM configuration words section...........................................................162 4.6.2.4 eSPI controller configuration.................................................................................................164 4.6.3 Default e500 addressing during system boot.............................................................................................166 Chapter 5 e500 Core Integration Details 5.1 Overview.......................................................................................................................................................................169 5.2 e500 core block diagram...............................................................................................................................................170 5.3 e500 core integration and the core complex bus (CCB)...............................................................................................172 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 7 Section number Title Page 5.4 Summary of core integration details.............................................................................................................................174 5.4.1 Processor version register (PVR) and system version register (SVR).......................................................176 Chapter 6 L2 Look-Aside Cache/SRAM 6.1 Introduction...................................................................................................................................................................177 6.2 L2 cache overview........................................................................................................................................................177 6.2.1 L2 cache and SRAM features....................................................................................................................178 6.3 L2 cache and SRAM organization................................................................................................................................180 6.3.1 Accessing the on-chip array as an L2 cache..............................................................................................181 6.3.2 Accessing the on-chip array as an SRAM.................................................................................................182 6.3.3 Connection of the on-chip memory to the system.....................................................................................184 6.4 L2 cache external write registers..................................................................................................................................185 6.5 L2 memory-mapped SRAM registers...........................................................................................................................186 6.6 L2 error registers...........................................................................................................................................................186 6.7 L2_Cache memory map/register definition..................................................................................................................187 6.7.1 L2 control register (L2_Cache_L2CTL)....................................................................................................188 6.7.2 L2 cache way allocation for processors (L2_Cache_L2CWAP)...............................................................193 6.7.3 L2 cache external write address register n (L2_Cache_L2CEWARn)......................................................195 6.7.4 L2 cache external write address register extended address n (L2_Cache_L2CEWAREAn)....................195 6.7.5 L2 cache external write control register n (L2_Cache_L2CEWCRn).......................................................196 6.7.6 L2 memory-mapped SRAM base address register n (L2_Cache_L2SRBARn)........................................197 6.7.7 L2 memory-mapped SRAM base address register extended address n (L2_Cache_L2SRBAREAn)......198 6.7.8 L2 error injection mask high register (L2_Cache_L2ERRINJHI).............................................................199 6.7.9 L2 error injection mask low register (L2_Cache_L2ERRINJLO).............................................................200 6.7.10 L2 error injection tag/ECC control register (L2_Cache_L2ERRINJCTL)................................................200 6.7.11 L2 error data high capture register (L2_Cache_L2CAPTDATAHI).........................................................201 6.7.12 L2 error data low capture register (L2_Cache_L2CAPTDATALO).........................................................202 6.7.13 L2 error syndrome register (L2_Cache_L2CAPTECC)............................................................................202 6.7.14 L2 error detect register (L2_Cache_L2ERRDET).....................................................................................204 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 8 Freescale Semiconductor, Inc. Section number Title Page 6.7.15 L2 error disable register (L2_Cache_L2ERRDIS)....................................................................................206 6.7.16 L2 error interrupt enable register (L2_Cache_L2ERRINTEN).................................................................208 6.7.17 L2 error attributes capture register (L2_Cache_L2ERRATTR)................................................................210 6.7.18 L2 error address capture register low (L2_Cache_L2ERRADDRL).........................................................212 6.7.19 L2 error address capture register high (L2_Cache_L2ERRADDRH).......................................................212 6.7.20 L2 error control register (L2_Cache_L2ERRCTL)...................................................................................213 6.8 External writes to the L2 cache (cache stashing)..........................................................................................................213 6.8.1 Stash-only cache regions............................................................................................................................214 6.9 L2 cache timing.............................................................................................................................................................214 6.10 L2 cache and SRAM coherency...................................................................................................................................216 6.10.1 L2 cache coherency rules ..........................................................................................................................216 6.10.2 Memory-mapped SRAM coherency rules.................................................................................................218 6.11 L2 cache locking...........................................................................................................................................................218 6.11.1 Locking the entire L2 cache.......................................................................................................................218 6.11.2 Locking programmed memory ranges.......................................................................................................219 6.11.3 Locking selected lines................................................................................................................................219 6.11.4 Clearing locks on selected lines.................................................................................................................220 6.11.5 Flash clearing of instruction and data locks...............................................................................................220 6.11.6 Locks with stale data..................................................................................................................................220 6.12 PLRU L2 replacement policy.......................................................................................................................................221 6.12.1 PLRU bit update considerations................................................................................................................221 6.12.2 Allocation of lines......................................................................................................................................222 6.13 L2 cache operation........................................................................................................................................................223 6.13.1 Initialization...............................................................................................................................................223 6.13.1.1 L2 cache initialization............................................................................................................223 6.13.1.2 Memory-mapped SRAM initialization..................................................................................224 6.13.2 Flash invalidation of the L2 cache.............................................................................................................224 6.13.3 Managing errors.........................................................................................................................................225 6.13.3.1 ECC errors .............................................................................................................................225 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 9 Section number Title Page 6.13.3.2 Tag parity errors ....................................................................................................................225 6.13.4 L2 cache states ..........................................................................................................................................225 6.13.5 L2 state transitions.....................................................................................................................................226 6.14 Error checking and correcting (ECC)...........................................................................................................................231 Chapter 7 e500 Coherency Module 7.1 Introduction...................................................................................................................................................................233 7.1.1 Overview....................................................................................................................................................234 7.1.2 Features......................................................................................................................................................234 7.2 ECM memory map/register definition..........................................................................................................................235 7.2.1 ECM CCB address configuration register (ECM_EEBACR)...................................................................236 7.2.2 ECM CCB port configuration register (ECM_EEBPCR)..........................................................................237 7.2.3 ECM IP Block Revision Register 1 (ECM_EIPBRR1).............................................................................239 7.2.4 ECM IP Block Revision Register 2 (ECM_EIPBRR2).............................................................................239 7.2.5 ECM error detect register (ECM_EEDR)..................................................................................................240 7.2.6 ECM error enable register (ECM_EEER).................................................................................................241 7.2.7 ECM error attributes capture register (ECM_EEATR).............................................................................242 7.2.8 ECM error low address capture register (ECM_EELADR)......................................................................244 7.2.9 ECM error high address capture register (ECM_EEHADR).....................................................................244 7.3 Functional description...................................................................................................................................................245 7.3.1 I/O arbiter...................................................................................................................................................245 7.3.2 CCB arbiter................................................................................................................................................245 7.3.3 Transaction queue .....................................................................................................................................246 7.3.4 Global data multiplexor.............................................................................................................................246 7.3.5 CCB interface.............................................................................................................................................246 7.4 Initialization/application information...........................................................................................................................247 Chapter 8 DDR Memory Controllers 8.1 Introduction...................................................................................................................................................................249 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 10 Freescale Semiconductor, Inc. Section number Title Page 8.2 Features.........................................................................................................................................................................250 8.2.1 Modes of operation....................................................................................................................................251 8.3 External signal descriptions..........................................................................................................................................251 8.3.1 Signals overview........................................................................................................................................251 8.3.2 Detailed signal descriptions.......................................................................................................................253 8.3.2.1 Memory interface signals.......................................................................................................253 8.3.2.2 Clock interface signals...........................................................................................................257 8.4 DDR memory map/register definition..........................................................................................................................258 8.4.1 Chip select n memory bounds (DDR_CSn_BNDS)..................................................................................260 8.4.2 Chip select n configuration (DDR_CSn_CONFIG)..................................................................................261 8.4.3 Chip select n configuration 2 (DDR_CSn_CONFIG_2)...........................................................................263 8.4.4 DDR SDRAM timing configuration 3 (DDR_TIMING_CFG_3).............................................................264 8.4.5 DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0).............................................................266 8.4.6 DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1).............................................................269 8.4.7 DDR SDRAM timing configuration 2 (DDR_TIMING_CFG_2).............................................................273 8.4.8 DDR SDRAM control configuration (DDR_DDR_SDRAM_CFG).........................................................277 8.4.9 DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2)..................................................280 8.4.10 DDR SDRAM mode configuration (DDR_DDR_SDRAM_MODE).......................................................283 8.4.11 DDR SDRAM mode configuration 2 (DDR_DDR_SDRAM_MODE_2)................................................284 8.4.12 DDR SDRAM mode control (DDR_DDR_SDRAM_MD_CNTL)..........................................................284 8.4.13 DDR SDRAM interval configuration (DDR_DDR_SDRAM_INTERVAL)...........................................288 8.4.14 DDR SDRAM data initialization (DDR_DDR_DATA_INIT).................................................................288 8.4.15 DDR SDRAM clock control (DDR_DDR_SDRAM_CLK_CNTL).........................................................289 8.4.16 DDR training initialization address (DDR_DDR_INIT_ADDR)..............................................................290 8.4.17 DDR training initialization extended address (DDR_DDR_INIT_EXT_ADDR)....................................291 8.4.18 DDR SDRAM timing configuration 4 (DDR_TIMING_CFG_4).............................................................292 8.4.19 DDR SDRAM timing configuration 5 (DDR_TIMING_CFG_5).............................................................295 8.4.20 DDR ZQ calibration control (DDR_DDR_ZQ_CNTL)............................................................................297 8.4.21 DDR write leveling control (DDR_DDR_WRLVL_CNTL).....................................................................299 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 11 Section number Title Page 8.4.22 DDR Self Refresh Counter (DDR_DDR_SR_CNTR)..............................................................................302 8.4.23 DDR Register Control Words 1 (DDR_DDR_SDRAM_RCW_1)...........................................................303 8.4.24 DDR Register Control Words 2 (DDR_DDR_SDRAM_RCW_2)...........................................................304 8.4.25 DDR write leveling control 2 (DDR_DDR_WRLVL_CNTL_2)..............................................................305 8.4.26 DDR write leveling control 3 (DDR_DDR_WRLVL_CNTL_3)..............................................................307 8.4.27 DDR Debug Status Register 1 (DDR_DDRDSR_1).................................................................................310 8.4.28 DDR Debug Status Register 2 (DDR_DDRDSR_2).................................................................................311 8.4.29 DDR Control Driver Register 1 (DDR_DDRCDR_1)..............................................................................311 8.4.30 DDR Control Driver Register 2 (DDR_DDRCDR_2)..............................................................................315 8.4.31 DDR IP block revision 1 (DDR_DDR_IP_REV1)....................................................................................316 8.4.32 DDR IP block revision 2 (DDR_DDR_IP_REV2)....................................................................................316 8.4.33 Memory data path error injection mask high (DDR_DATA_ERR_INJECT_HI)....................................317 8.4.34 Memory data path error injection mask low (DDR_DATA_ERR_INJECT_LO)....................................317 8.4.35 Memory data path error injection mask ECC (DDR_ERR_INJECT).......................................................318 8.4.36 Memory data path read capture high (DDR_CAPTURE_DATA_HI)......................................................319 8.4.37 Memory data path read capture low (DDR_CAPTURE_DATA_LO)......................................................319 8.4.38 Memory data path read capture ECC (DDR_CAPTURE_ECC)...............................................................320 8.4.39 Memory error detect (DDR_ERR_DETECT)...........................................................................................321 8.4.40 Memory error disable (DDR_ERR_DISABLE)........................................................................................323 8.4.41 Memory error interrupt enable (DDR_ERR_INT_EN).............................................................................325 8.4.42 Memory error attributes capture (DDR_CAPTURE_ATTRIBUTES)......................................................327 8.4.43 Memory error address capture (DDR_CAPTURE_ADDRESS)...............................................................329 8.4.44 Memory error extended address capture (DDR_CAPTURE_EXT_ADDRESS)......................................329 8.4.45 Single-Bit ECC memory error management (DDR_ERR_SBE)...............................................................330 8.5 Functional description...................................................................................................................................................330 8.5.1 DDR SDRAM interface operation.............................................................................................................336 8.5.1.1 Supported DDR SDRAM organizations................................................................................336 8.5.2 DDR SDRAM address multiplexing..........................................................................................................338 8.5.3 JEDEC standard DDR SDRAM interface commands...............................................................................347 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 12 Freescale Semiconductor, Inc. Section number Title Page 8.5.4 DDR SDRAM interface timing..................................................................................................................349 8.5.5 DDR SDRAM registered DIMM mode.....................................................................................................352 8.5.6 DDR SDRAM write timing adjustments...................................................................................................353 8.5.7 DDR SDRAM refresh................................................................................................................................354 8.5.7.1 DDR SDRAM refresh timing................................................................................................355 8.5.7.2 DDR SDRAM refresh and power-saving modes...................................................................356 8.5.7.2.1 Self-refresh in sleep mode..............................................................................357 8.5.8 DDR data beat ordering.............................................................................................................................358 8.5.9 Page mode and logical bank retention.......................................................................................................359 8.5.10 Error checking and correcting (ECC)........................................................................................................360 8.5.11 Error management......................................................................................................................................361 8.6 Initialization/application information...........................................................................................................................362 8.6.1 Programming differences between memory types.....................................................................................366 8.6.2 DDR SDRAM initialization sequence.......................................................................................................371 8.7 Using Forced Self-Refresh Mode to Implement a Battery-Backed RAM System.......................................................371 8.7.1 Hardware Based Self-Refresh Scheme......................................................................................................372 8.7.2 Software Based Self-Refresh Scheme........................................................................................................372 8.7.3 Bypassing Re-initialization During Battery-Backed Operation ................................................................372 Chapter 9 Programmable Interrupt Controller (PIC) 9.1 Introduction...................................................................................................................................................................375 9.1.1 Overview....................................................................................................................................................375 9.1.2 The PIC in multiple-processor implementations.......................................................................................378 9.1.3 Interrupts to the e500 processor core.........................................................................................................378 9.1.4 Modes of operation....................................................................................................................................379 9.1.4.1 Mixed mode (GCR[M] = 1)...................................................................................................379 9.1.4.2 Pass-through mode (GCR[M] = 0).........................................................................................379 9.1.5 Interrupt sources.........................................................................................................................................380 9.1.5.1 Interrupt routing-mixed mode................................................................................................381 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 13 Section number Title Page 9.1.5.2 Interrupt destinations..............................................................................................................381 9.1.5.3 Internal interrupt sources.......................................................................................................382 9.2 PIC external signal descriptions....................................................................................................................................383 9.2.1 Signal overview..........................................................................................................................................384 9.2.2 Detailed signal descriptions.......................................................................................................................384 9.3 PIC memory map/register definition............................................................................................................................385 9.3.1 Block revision register 1 (PIC_BRR1)......................................................................................................395 9.3.2 Block revision register 2 (PIC_BRR2)......................................................................................................396 9.3.3 Interprocessor n dispatch register (PIC_IPIDRn)......................................................................................397 9.3.4 Current task priority register (PIC_CTPR)................................................................................................397 9.3.5 Who am I register (PIC_WHOAMI).........................................................................................................398 9.3.6 Interrupt acknowledge register (PIC_IACK).............................................................................................399 9.3.7 End of interrupt register (PIC_EOI)...........................................................................................................400 9.3.8 Feature reporting register (PIC_FRR)........................................................................................................400 9.3.9 Global configuration register (PIC_GCR).................................................................................................402 9.3.10 Vendor identification register (PIC_VIR)..................................................................................................403 9.3.11 Processor core initialization register (PIC_PIR)........................................................................................403 9.3.12 Interprocessor interrupt n vector/priority register (PIC_IPIVPRn)...........................................................404 9.3.13 Spurious vector register (PIC_SVR)..........................................................................................................405 9.3.14 Timer frequency reporting register group X (PIC_TFRRn)......................................................................405 9.3.15 Global timer n current count register group A (PIC_GTCCRAn).............................................................406 9.3.16 Global timer n base count register group A (PIC_GTBCRAn).................................................................407 9.3.17 Global timer n vector/priority register group A (PIC_GTVPRAn)...........................................................408 9.3.18 Global timer n destination register group A (PIC_GTDRAn)...................................................................409 9.3.19 Timer control register group n (PIC_TCRn)..............................................................................................409 9.3.20 External interrupt summary register (PIC_ERQSR)..................................................................................412 9.3.21 IRQ_OUT_B summary register 0 (PIC_IRQSR0)....................................................................................412 9.3.22 IRQ_OUT_B summary register 1 (PIC_IRQSR1)....................................................................................413 9.3.23 IRQ_OUT_B summary register 2 (PIC_IRQSR2)....................................................................................413 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 14 Freescale Semiconductor, Inc. Section number Title Page 9.3.24 9.3.25 9.3.26 9.3.27 9.3.28 9.3.29 9.3.30 9.3.31 9.3.32 9.3.33 9.3.34 9.3.35 9.3.36 9.3.37 9.3.38 9.3.39 9.3.40 9.3.41 9.3.42 9.3.43 9.3.44 9.3.45 9.3.46 9.3.47 9.3.48 9.3.49 9.3.50 9.3.51 9.3.52 Critical interrupt summary register 0 (PIC_CISR0)..................................................................................414 Critical interrupt summary register 1 (PIC_CISR1)..................................................................................414 Critical interrupt summary register 2 (PIC_CISR2)..................................................................................415 Performance monitor n mask register 0 (PIC_PMnMR0).........................................................................415 Performance monitor n mask register 1 (PIC_PMnMR1).........................................................................416 Performance monitor n mask register 2 (PIC_PMnMR2).........................................................................416 Message register n (PIC_MSGRn)............................................................................................................417 Message enable register (PIC_MER).........................................................................................................417 Message status register (PIC_MSR)..........................................................................................................418 Shared message signaled interrupt register n (PIC_MSIRn).....................................................................418 Shared message signaled interrupt status register (PIC_MSISR)..............................................................419 Shared message signaled interrupt index register (PIC_MSIIR)...............................................................420 Global timer n current count register group B (PIC_GTCCRBn).............................................................421 Global timer n base count register group B (PIC_GTBCRBn).................................................................422 Global timer n vector/priority register group B (PIC_GTVPRBn)............................................................423 Global timer n destination register group B (PIC_GTDRBn)...................................................................424 Message register n (PIC_MSGRan)...........................................................................................................424 Message enable register (PIC_MERa).......................................................................................................425 Message status register (PIC_MSRa)........................................................................................................426 External interrupt n (IRQn) vector/priority register (PIC_EIVPRn).........................................................426 External interrupt n (IRQn) destination register (PIC_EIDRn).................................................................428 Internal interrupt n vector/priority register (PIC_IIVPRn)........................................................................429 Internal interrupt n destination register (PIC_IIDRn)................................................................................430 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPRn)...................................................431 Messaging interrupt n (MSGn) destination register (PIC_MIDRn)..........................................................432 Shared message signaled interrupt vector/priority register n (PIC_MSIVPRn)........................................433 Shared message signaled interrupt destination register n (PIC_MSIDRn)................................................434 Processor core 0 interprocessor n dispatch register (PIC_IPIDR_CPU0n)...............................................435 Processor core current task priority register 0 Processor core (PIC_CTPR_CPU0).................................435 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 15 Section number Title Page 9.3.53 Processor core 0 who am I register (PIC_WHOAMI_CPU0)...................................................................436 9.3.54 Processor core 0 interrupt acknowledge register (PIC_IACK_CPU0)......................................................437 9.3.55 Processor core 0 end of interrupt register (PIC_EOI_CPU0)....................................................................438 9.3.56 Processor core 1 interprocessor n dispatch register (PIC_IPIDR_CPU1n)...............................................439 9.3.57 Processor core 1 current task priority register (PIC_CTPR_CPU1)..........................................................439 9.3.58 Processor core 1 who am I register (PIC_WHOAMI_CPU1)...................................................................440 9.3.59 Processor core 1 interrupt acknowledge register (PIC_IACK_CPU1)......................................................441 9.3.60 Processor core 1 end of interrupt register (PIC_EOI_CPU1)....................................................................442 9.4 Functional description...................................................................................................................................................442 9.4.1 Programming model considerations...........................................................................................................442 9.4.1.1 Global registers......................................................................................................................442 9.4.1.2 Global timer registers.............................................................................................................443 9.4.1.3 IRQ_OUT_B and critical interrupt summary registers..........................................................443 9.4.1.4 Performance monitor mask registers (PMMRs)....................................................................444 9.4.1.5 Message registers...................................................................................................................444 9.4.1.6 Shared message signaled registers.........................................................................................444 9.4.1.7 Interrupt source configuration registers.................................................................................444 9.4.1.8 Per-CPU (private access) registers.........................................................................................446 9.4.2 Flow of interrupt control............................................................................................................................448 9.4.2.1 Interrupts routed to cint or IRQ_OUT_B...............................................................................448 9.4.2.2 Interrupts routed to int............................................................................................................449 9.4.2.2.1 Interrupt source priority..................................................................................451 9.4.2.2.2 Interrupt acknowledge....................................................................................451 9.4.2.2.3 Spurious vector generation.............................................................................452 9.4.2.2.4 Nesting of interrupts.......................................................................................452 9.4.3 Interprocessor interrupts............................................................................................................................453 9.4.4 Message interrupts.....................................................................................................................................453 9.4.5 Shared message signaled interrupts...........................................................................................................453 9.4.6 PCI Express INTx/IRQn sharing...............................................................................................................454 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 16 Freescale Semiconductor, Inc. Section number Title Page 9.4.7 Global timers..............................................................................................................................................455 9.4.8 Resets.........................................................................................................................................................455 9.4.9 Resetting the PIC.......................................................................................................................................456 9.4.9.1 Processor core initialization...................................................................................................456 9.5 Initialization/application information...........................................................................................................................456 9.5.1 Programming guidelines............................................................................................................................456 9.5.1.1 PIC registers...........................................................................................................................457 9.5.1.2 Changing interrupt source configuration...............................................................................458 Chapter 10 I2C Interfaces 10.1 Overview.......................................................................................................................................................................459 10.2 Introduction to I2C........................................................................................................................................................459 10.2.1 What is the I2C module?............................................................................................................................459 10.2.2 I2C module block diagram.........................................................................................................................460 10.2.3 Features .....................................................................................................................................................460 10.2.4 Advantages of the I2C bus.........................................................................................................................461 10.2.5 Modes of operation....................................................................................................................................461 10.2.6 I2C-specific conditions..............................................................................................................................461 10.3 I2C external signal descriptions....................................................................................................................................462 10.3.1 Signal overview..........................................................................................................................................462 10.3.2 Detailed signal descriptions.......................................................................................................................462 10.4 I2C memory map/register definition.............................................................................................................................463 10.4.1 I2C address register (I2Cx_I2CADR)........................................................................................................464 10.4.2 I2C frequency divider register (I2Cx_I2CFDR)........................................................................................465 10.4.3 I2C control register (I2Cx_I2CCR)............................................................................................................467 10.4.4 I2C status register (I2Cx_I2CSR)..............................................................................................................468 10.4.5 I2C data register (I2Cx_I2CDR)................................................................................................................469 10.4.6 I2C digital filter sampling rate register (I2Cx_I2CDFSRR)......................................................................470 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 17 Section number Title Page 10.5 Functional description...................................................................................................................................................470 10.5.1 Transaction protocol..................................................................................................................................470 10.5.1.1 START condition...................................................................................................................471 10.5.1.2 Slave address transmission.....................................................................................................471 10.5.1.3 Repeated START condition...................................................................................................472 10.5.1.4 STOP condition......................................................................................................................473 10.5.1.5 Protocol implementation details.............................................................................................473 10.5.1.5.1 Transaction monitoring-implementation details.............................................473 10.5.1.5.2 Control transfer-implementation details.........................................................473 10.5.1.6 Address compare-implementation details..............................................................................474 10.5.2 Arbitration procedure.................................................................................................................................475 10.5.2.1 Arbitration control..................................................................................................................475 10.5.3 Handshaking...............................................................................................................................................476 10.5.4 Clock control..............................................................................................................................................476 10.5.4.1 Clock synchronization............................................................................................................476 10.5.4.2 Input synchronization and digital filter..................................................................................477 10.5.4.2.1 Input signal synchronization...........................................................................477 10.5.4.2.2 Filtering of SCL and SDA lines......................................................................477 10.5.4.3 Clock stretching.....................................................................................................................477 10.5.5 Boot sequencer mode.................................................................................................................................478 10.5.5.1 EEPROM calling address.......................................................................................................479 10.5.5.2 EEPROM data format............................................................................................................479 10.6 Initialization/application information...........................................................................................................................482 10.6.1 Initialization sequence................................................................................................................................482 10.6.2 Generation of START................................................................................................................................483 10.6.3 Post-transfer software response.................................................................................................................483 10.6.4 Generation of STOP...................................................................................................................................484 10.6.5 Generation of repeated START.................................................................................................................484 10.6.6 Generation of SCL when SDA low............................................................................................................484 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 18 Freescale Semiconductor, Inc. Section number Title Page 10.6.7 Slave mode interrupt service routine.........................................................................................................485 10.6.7.1 Slave transmitter and received acknowledge.........................................................................485 10.6.7.2 Loss of arbitration and forcing of slave mode.......................................................................485 10.6.8 Interrupt service routine flowchart.............................................................................................................486 Chapter 11 DUART 11.1 Introduction...................................................................................................................................................................489 11.1.1 Overview....................................................................................................................................................489 11.1.1.1 Features..................................................................................................................................490 11.1.1.2 Modes of operation................................................................................................................491 11.2 DUART external signal descriptions............................................................................................................................491 11.3 DUART memory map/register definition.....................................................................................................................492 11.3.1 Receiver Buffer Registers (DUART_URBRn)..........................................................................................493 11.3.2 Transmitter Holding Registers (DUART_UTHRn)...................................................................................494 11.3.3 Divisor Least Significant Byte Registers (DUART_UDLBn)...................................................................495 11.3.4 Divisor Most Significant Byte Registers (DUART_UDMBn)..................................................................496 11.3.5 Interrupt Enable Register (DUART_UIERn)............................................................................................497 11.3.6 Interrupt ID Registers (DUART_UIIRn)...................................................................................................497 11.3.7 FIFO Control Registers (DUART_UFCRn)..............................................................................................499 11.3.8 Alternate Function Registers (DUART_UAFRn)......................................................................................500 11.3.9 Line Control Registers (DUART_ULCRn)...............................................................................................501 11.3.10 Modem Control Registers (DUART_UMCRn).........................................................................................503 11.3.11 Line Status Registers (DUART_ULSRn)..................................................................................................503 11.3.12 Modem Status Registers (DUART_UMSRn)............................................................................................505 11.3.13 Scratch Registers (DUART_USCRn)........................................................................................................505 11.3.14 DMA Status Registers (DUART_UDSRn)................................................................................................506 11.4 Functional description...................................................................................................................................................507 11.4.1 Serial interface...........................................................................................................................................508 11.4.1.1 START bit..............................................................................................................................508 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 19 Section number Title Page 11.4.1.2 Data transfer...........................................................................................................................509 11.4.1.3 Parity bit.................................................................................................................................509 11.4.1.4 STOP bit.................................................................................................................................509 11.4.2 Baud-rate generator logic...........................................................................................................................509 11.4.3 Local loopback mode.................................................................................................................................510 11.4.4 Errors..........................................................................................................................................................510 11.4.4.1 Framing error.........................................................................................................................511 11.4.4.2 Parity error.............................................................................................................................511 11.4.4.3 Overrun error..........................................................................................................................511 11.4.5 FIFO mode.................................................................................................................................................511 11.4.5.1 FIFO interrupts.......................................................................................................................512 11.4.5.2 DMA mode select..................................................................................................................512 11.4.5.3 Interrupt control logic............................................................................................................513 11.5 DUART initialization/application information.............................................................................................................513 Chapter 12 Enhanced local bus controller (eLBC) 12.1 eLBC introduction........................................................................................................................................................515 12.1.1 Overview....................................................................................................................................................516 12.1.2 Features......................................................................................................................................................517 12.1.3 Modes of operation....................................................................................................................................518 12.1.3.1 eLBC bus clock and clock ratios............................................................................................518 12.1.3.2 Source ID debug mode...........................................................................................................519 12.2 eLBC external signal descriptions................................................................................................................................519 12.3 Enhanced Local Bus Controller (eLBC) Memory Map................................................................................................522 12.3.1 Base register 0 (eLBC_BR0).....................................................................................................................526 12.3.2 Options register 0 layout for GPCM Mode (eLBC_ORg0).......................................................................528 12.3.3 Options register 0 layout for FCM Mode (eLBC_ORf0)..........................................................................531 12.3.4 Options register 0 layout for UPM Mode (eLBC_ORu0)..........................................................................535 12.3.5 Base register n (eLBC_BRn).....................................................................................................................539 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 20 Freescale Semiconductor, Inc. Section number Title Page 12.3.6 Options register n layout for GPCM Mode (eLBC_ORgn).......................................................................540 12.3.7 Options register n layout for FCM Mode (eLBC_ORfn)..........................................................................544 12.3.8 Options register n layout for UPM Mode (eLBC_ORun)..........................................................................548 12.3.9 UPM address register (eLBC_MAR).........................................................................................................550 12.3.10 UPMn mode register (eLBC_MnMR).......................................................................................................551 12.3.11 Memory refresh timer prescaler register (eLBC_MRTPR).......................................................................554 12.3.12 UPM data register (eLBC_MDRu)............................................................................................................554 12.3.13 FCM data register (eLBC_MDRf).............................................................................................................555 12.3.14 Special operation initiation register (eLBC_LSOR)..................................................................................555 12.3.15 UPM refresh timer (eLBC_LURT)............................................................................................................556 12.3.16 Transfer error status register (eLBC_LTESR)...........................................................................................557 12.3.17 Transfer error disable register (eLBC_LTEDR)........................................................................................559 12.3.18 Transfer error interrupt register (eLBC_LTEIR).......................................................................................560 12.3.19 Transfer error attributes register (eLBC_LTEATR)..................................................................................561 12.3.20 Transfer error address register (eLBC_LTEAR).......................................................................................562 12.3.21 Transfer error ECC register (eLBC_LTECCR).........................................................................................563 12.3.22 Configuration register (eLBC_LBCR).......................................................................................................564 12.3.23 Clock ratio register (eLBC_LCRR)...........................................................................................................566 12.3.24 Flash mode register (eLBC_FMR)............................................................................................................567 12.3.25 Flash instruction register (eLBC_FIR)......................................................................................................569 12.3.26 Flash command register (eLBC_FCR)......................................................................................................571 12.3.27 Flash block address register (eLBC_FBAR).............................................................................................571 12.3.28 Flash page address register [Large Page Device (ORx[PGS] = 1)] (eLBC_FPARl).................................572 12.3.29 Flash page address register [Small Page Device (ORx[PGS] = 0)] (eLBC_FPARs)................................573 12.3.30 Flash byte count register (eLBC_FBCR)...................................................................................................574 12.3.31 Flash ECC block n registers (eLBC_FECCn)............................................................................................575 12.4 eLBC functional description.........................................................................................................................................575 12.4.1 Basic architecture.......................................................................................................................................577 12.4.1.1 Address and address space checking.....................................................................................577 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 21 Section number Title Page 12.4.2 12.4.3 12.4.1.2 External address latch enable signal (LALE)........................................................................577 12.4.1.3 Data transfer acknowledge (TA)............................................................................................579 12.4.1.4 Data buffer control (LBCTL).................................................................................................580 12.4.1.5 Parity generation and checking (LDP)...................................................................................581 12.4.1.6 Bus monitor............................................................................................................................581 12.4.1.7 PLL Bypass mode..................................................................................................................582 General-purpose chip-select machine (GPCM).........................................................................................582 12.4.2.1 GPCM read signal timing......................................................................................................583 12.4.2.2 GPCM write signal timing.....................................................................................................585 12.4.2.3 Chip-select assertion timing...................................................................................................587 12.4.2.3.1 Programmable wait state configuration..........................................................587 12.4.2.3.2 Chip-select and write enable negation timing.................................................588 12.4.2.3.3 Relaxed timing................................................................................................589 12.4.2.3.4 Output enable (LOE_B) timing......................................................................593 12.4.2.3.5 Extended hold time on read accesses-GPCM.................................................593 12.4.2.4 External access termination (LGTA_B)................................................................................594 12.4.2.5 GPCM boot chip-select operation..........................................................................................595 Flash control machine (FCM)....................................................................................................................596 12.4.3.1 FCM buffer RAM .................................................................................................................598 12.4.3.1.1 Buffer layout and page mapping for small-page NAND flash devices .........599 12.4.3.1.2 Buffer layout and page mapping for large-page NAND flash devices ..........600 12.4.3.1.3 Error correcting codes and the spare region ..................................................601 12.4.3.2 Programming FCM................................................................................................................603 12.4.3.2.1 FCM command instructions ...........................................................................604 12.4.3.2.2 FCM no-operation instruction ........................................................................605 12.4.3.2.3 FCM address instructions ..............................................................................605 12.4.3.2.4 FCM data read instructions ............................................................................606 12.4.3.2.5 FCM data write instructions ...........................................................................606 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 22 Freescale Semiconductor, Inc. Section number Title Page 12.4.4 12.4.3.3 FCM signal timing.................................................................................................................607 12.4.3.3.1 FCM chip-select timing .................................................................................607 12.4.3.3.2 FCM command, address, and write data timing ............................................607 12.4.3.3.3 FCM ready/busy timing .................................................................................609 12.4.3.3.4 FCM read data timing ....................................................................................610 12.4.3.3.5 FCM extended read hold timing ....................................................................611 12.4.3.4 FCM boot chip-select operation ............................................................................................612 12.4.3.4.1 FCM bank 0 reset initialization ......................................................................613 12.4.3.4.2 Boot block loading into the FCM buffer RAM .............................................613 User-programmable machines (UPMs).....................................................................................................615 12.4.4.1 UPM requests.........................................................................................................................616 12.4.4.1.1 Memory access requests.................................................................................617 12.4.4.1.2 UPM refresh timer requests............................................................................618 12.4.4.1.3 Software requests-RUN command.................................................................618 12.4.4.1.4 Exception requests..........................................................................................619 12.4.4.2 Programming the UPMs.........................................................................................................619 12.4.4.2.1 UPM programming example (two sequential writes to the RAM array)........620 12.4.4.2.2 UPM programming example (two sequential reads from the RAM array)....621 12.4.4.3 UPM signal timing.................................................................................................................622 12.4.4.4 RAM array.............................................................................................................................622 12.4.4.4.1 RAM words.....................................................................................................623 12.4.4.4.2 Chip-select signal timing (CSTn)...................................................................627 12.4.4.4.3 Byte select signal timing (BSTn)....................................................................628 12.4.4.4.4 General-purpose signals (GnTn, GOn)...........................................................629 12.4.4.4.5 Loop control (LOOP)......................................................................................629 12.4.4.4.6 Repeat execution of current RAM word (REDO)..........................................630 12.4.4.4.7 Address multiplexing (AMX).........................................................................630 12.4.4.4.8 Data valid and data sample control (UTA).....................................................632 12.4.4.4.9 LGPL[0:5] signal negation (LAST)................................................................633 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 23 Section number Title Page 12.4.4.4.10 Wait mechanism (WAEN)..............................................................................633 12.4.4.5 Extended hold time on read accesses-UPM...........................................................................635 12.5 eLBC initialization/application information.................................................................................................................635 12.5.1 Interfacing to peripherals in different address modes................................................................................635 12.5.1.1 Non-multiplexed address and data buses...............................................................................635 12.5.1.2 Multiplexed address and data to save maximum pins in 8- to 16-bit addressing..................636 12.5.1.3 Peripheral hierarchy on the local bus for high bus speeds.....................................................636 12.5.1.4 GPCM timings.......................................................................................................................637 12.5.2 Bus turnaround...........................................................................................................................................638 12.5.2.1 Address phase after previous read.........................................................................................639 12.5.2.2 Read data phase after address phase......................................................................................639 12.5.2.3 Read-modify-write cycle for parity protected memory banks...............................................639 12.5.2.4 UPM cycles with additional address phases..........................................................................640 12.5.3 Interface to different port-size devices.......................................................................................................640 12.5.4 Command sequence examples for NAND flash EEPROM.......................................................................641 12.5.4.1 NAND flash soft reset command sequence example.............................................................641 12.5.4.2 NAND flash read status command sequence example..........................................................642 12.5.4.3 NAND flash read identification command sequence example..............................................643 12.5.4.4 NAND flash page read command sequence example............................................................643 12.5.4.5 NAND flash block erase command sequence example.........................................................644 12.5.4.6 NAND flash program command sequence example..............................................................645 12.5.5 Interfacing to fast-page mode DRAM using UPM....................................................................................646 12.5.6 Interfacing to ZBT SRAM using UPM......................................................................................................655 Chapter 13 DMA Controller 13.1 DMA overview.............................................................................................................................................................659 13.1.1 DMA features summary.............................................................................................................................660 13.1.2 DMA modes of operation..........................................................................................................................660 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 24 Freescale Semiconductor, Inc. Section number Title Page 13.2 DMA external signal description..................................................................................................................................663 13.2.1 Signal overview..........................................................................................................................................663 13.2.2 DMA signal descriptions...........................................................................................................................664 13.3 DMA controller memory map......................................................................................................................................664 13.3.1 DMA mode register (DMA_MRn)............................................................................................................668 13.3.2 DMA status register (DMA_SRn).............................................................................................................672 13.3.3 DMA current link descriptor extended address register (DMA_ECLNDARn).........................................673 13.3.4 DMA current link descriptor address register (DMA_CLNDARn)..........................................................674 13.3.5 DMA source attributes register (DMA_SATRn).......................................................................................676 13.3.6 DMA source address register (DMA_SARn)............................................................................................677 13.3.7 DMA destination attributes register (DMA_DATRn)...............................................................................677 13.3.8 DMA destination address register (DMA_DARn)....................................................................................678 13.3.9 DMA byte count register (DMA_BCRn)...................................................................................................679 13.3.10 DMA extended next link descriptor address register (DMA_ENLNDARn).............................................679 13.3.11 DMA next link descriptor address register (DMA_NLNDARn)...............................................................680 13.3.12 DMA extended current list descriptor address register (DMA_ECLSDARn)...........................................681 13.3.13 DMA current list descriptor address register (DMA_CLSDARn)............................................................682 13.3.14 DMA extended next list descriptor address register (DMA_ENLSDARn)...............................................683 13.3.15 DMA next list descriptor address register (DMA_NLSDARn).................................................................683 13.3.16 DMA source stride register (DMA_SSRn)................................................................................................684 13.3.17 DMA destination stride register (DMA_DSRn)........................................................................................685 13.3.18 DMA general status register (DMA_DGSR).............................................................................................686 13.4 DMA functional description.........................................................................................................................................689 13.4.1 DMA channel operation.............................................................................................................................689 13.4.1.1 Source/destination transaction size calculations....................................................................690 13.4.1.2 Basic DMA mode transfer.....................................................................................................692 13.4.1.2.1 Basic direct mode............................................................................................692 13.4.1.2.2 Basic, direct, single-write start mode..............................................................692 13.4.1.2.3 Basic chaining mode.......................................................................................693 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 25 Section number Title Page 13.4.1.2.4 Basic chaining, single-write start mode..........................................................694 13.4.1.3 Extended DMA mode transfer...............................................................................................695 13.4.1.3.1 Extended direct mode ....................................................................................695 13.4.1.3.2 Extended direct, single-write start mode........................................................695 13.4.1.3.3 Extended chaining mode.................................................................................695 13.4.1.3.4 Extended chaining, single-write start mode....................................................696 13.4.1.4 External control mode transfer...............................................................................................697 13.4.1.5 Channel continue mode for cascading transfer chains...........................................................698 13.4.1.5.1 Basic mode......................................................................................................699 13.4.1.5.2 Extended mode................................................................................................699 13.4.1.6 Channel abort.........................................................................................................................699 13.4.1.7 Bandwidth control..................................................................................................................699 13.4.1.8 Channel state..........................................................................................................................700 13.4.1.9 Illustration of stride size and stride distance..........................................................................700 13.4.2 DMA transfer interfaces.............................................................................................................................701 13.4.3 DMA errors................................................................................................................................................701 13.4.4 DMA descriptors........................................................................................................................................702 13.4.5 DMA controller limitations and restrictions..............................................................................................705 13.5 DMA system considerations.........................................................................................................................................706 13.5.1 Unusual DMA scenarios............................................................................................................................707 13.5.1.1 DMA to core..........................................................................................................................707 13.5.1.2 DMA to configuration, control, and status registers (CCSR)................................................707 13.5.1.3 DMA to I2C...........................................................................................................................708 13.5.1.4 DMA to DUART...................................................................................................................708 Chapter 14 PCI Express Interface Controller 14.1 Introduction...................................................................................................................................................................709 14.1.1 Outbound transactions................................................................................................................................711 14.1.2 Inbound transactions..................................................................................................................................712 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 26 Freescale Semiconductor, Inc. Section number Title Page 14.2 PCI Express features summary.....................................................................................................................................713 14.3 PCI Express modes of operation...................................................................................................................................713 14.3.1 Root complex/endpoint modes...................................................................................................................714 14.3.2 Link width..................................................................................................................................................714 14.4 PCI Express signal descriptions....................................................................................................................................714 14.5 Memory map/register overview....................................................................................................................................715 14.6 PCI Express memory-mapped registers........................................................................................................................716 14.6.1 PCI Express configuration address register (PEXx_PEX_CONFIG_ADDR)..........................................721 14.6.2 PCI Express configuration data register (PEXx_PEX_CONFIG_DATA)................................................722 14.6.3 PCI Express outbound completion timeout register (PEXx_PEX_OTB_CPL_TOR)...............................722 14.6.4 PCI Express configuration retry timeout register (PEXx_PEX_CONF_RTY_TOR)...............................723 14.6.5 PCI Express configuration register (PEXx_PEX_CONFIG).....................................................................724 14.6.6 PCI Express PME & message detect register (PEXx_PEX_PME_MES_DR)..........................................725 14.6.7 PCI Express PME & message disable register (PEXx_PEX_PME_MES_DISR)....................................728 14.6.8 PCI Express PME & message interrupt enable register (PEXx_PEX_PME_MES_IER).........................730 14.6.9 PCI Express power management command register (PEXx_PEX_PMCR)..............................................732 14.6.10 IP block revision register 1 (PEXx_PEX_IP_BLK_REV1)......................................................................733 14.6.11 IP block revision register 2 (PEXx_PEX_IP_BLK_REV2)......................................................................733 14.6.12 PCI Express outbound translation address register n (PEXx_PEXOTARn).............................................734 14.6.13 PCI Express outbound translation extended address register n (PEXx_PEXOTEARn)...........................734 14.6.14 PCI Express outbound window attributes register n (PEXx_PEXOWAR0).............................................736 14.6.15 PCI Express outbound window base address register n (PEXx_PEXOWBARn).....................................738 14.6.16 PCI Express outbound window attributes register n (PEXx_PEXOWARn).............................................739 14.6.17 PCI Express outbound window attributes register 3 (PEXx_PEXOWAR3).............................................742 14.6.18 PCI Express outbound window attributes register 4 (PEXx_PEXOWAR4).............................................744 14.6.19 PCI Express inbound translation address register n (PEXx_PEXITARn).................................................746 14.6.20 PCI Express inbound window base address register n (PEXx_PEXIWBARn).........................................747 14.6.21 PCI Express inbound window base extended address register n (PEXx_PEXIWBEARn).......................748 14.6.22 PCI Express inbound window attributes register n (PEXx_PEXIWARn).................................................749 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 27 Section number Title Page 14.6.23 PCI Express error detect register (PEXx_PEX_ERR_DR)........................................................................752 14.6.24 PCI Express error interrupt enable register (PEXx_PEX_ERR_EN)........................................................755 14.6.25 PCI Express error disable register (PEXx_PEX_ERR_DISR)..................................................................758 14.6.26 PCI Express error capture status register (PEXx_PEX_ERR_CAP_STAT).............................................760 14.6.27 PCI Express error capture register n (PEXx_PEX_ERR_CAP_Rn).........................................................761 14.7 PCI Express configuration-space registers...................................................................................................................762 14.7.1 PCI compatible configuration headers.......................................................................................................762 14.8 Type 0 configuration header registers...........................................................................................................................763 14.8.1 PCI Express Vendor ID Register (Vendor_ID_Register)..........................................................................765 14.8.2 PCI Express Device ID Register (Device_ID_Register)...........................................................................765 14.8.3 PCI Express Command Register (Command_Register)............................................................................766 14.8.4 PCI Express Status Register (Status_Register)..........................................................................................768 14.8.5 PCI Express Revision ID Register (Revision_ID_Register)......................................................................769 14.8.6 PCI Express Class Code Register (Class_Code_Register)........................................................................769 14.8.7 PCI Express Cache Line Size Register (Cache_Line_Size_Register).......................................................770 14.8.8 PCI Express Latency Timer Register (Latency_Timer_Register).............................................................771 14.8.9 PCI Express Header Type Register (Header_Type_Register)...................................................................771 14.8.10 PCI Express Base Address Register 0 (PEXCSRBAR).............................................................................772 14.8.11 PCI Express Base Address Register 1 (BAR1)..........................................................................................773 14.8.12 PCI Express Base Address Register 2,4 (BARn).......................................................................................774 14.8.13 PCI Express Base Address Register 3,5 (BARn).......................................................................................776 14.8.14 PCI Express Subsystem Vendor ID Register (Subsystem_Vendor_ID_Register)....................................776 14.8.15 PCI Express Subsystem ID Register (Subsystem_ID_Register)...............................................................777 14.8.16 Capabilities Pointer Register (Capabilities_Pointer_Register)..................................................................778 14.8.17 PCI Express Interrupt Line Register (Interrupt_Line_Register)................................................................778 14.8.18 PCI Express Interrupt Pin Register (Interrupt_Pin_Register)....................................................................779 14.8.19 PCI Express Minimum Grant Register (Minimum_Grant_Register)........................................................779 14.8.20 PCI Express Maximum Latency Register (Maximum_Latency_Register)...............................................780 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 28 Freescale Semiconductor, Inc. Section number Title Page 14.9 Type 1 configuration header registers...........................................................................................................................780 14.9.1 PCI Express Base Address Register 0 (PEXCSRBAR).............................................................................781 14.9.2 PCI Express Primary Bus Number Register (Primary_Bus_Number_Register).......................................783 14.9.3 PCI Express Secondary Bus Number Register (Secondary_Bus_Number_Register)...............................783 14.9.4 PCI Express Subordinate Bus Number Register (Subordinate_Bus_Number_Register)..........................783 14.9.5 PCI Express I/O Base Register (IO_Base_Register).................................................................................784 14.9.6 PCI Express I/O Limit Register (IO_Limit_Register)...............................................................................784 14.9.7 PCI Express Secondary Status Register (Secondary_Status_Register).....................................................785 14.9.8 PCI Express Memory Base Register (Memory_Base_Register)...............................................................786 14.9.9 PCI Express Memory Limit Register (Memory_Limit_Register).............................................................786 14.9.10 PCI Express Prefetchable Memory Base Register (Prefetchable_Memory_Base_Register)....................787 14.9.11 PCI Express Prefetchable Memory Limit Register (Prefetchable_Memory_Limit_Register)..................787 14.9.12 PCI Express Prefetchable Base Upper 32 Bits Register (Prefetchable_Base_Upper_32_Bits_Register). 788 14.9.13 PCI Express Prefetchable Limit Upper 32 Bits Register (Prefetchable_Limit_Upper_32_Bits_Register)........................................................................................788 14.9.14 PCI Express I/O Base Upper 16 Bits Register (IO_Base_Upper_16_Bits_Register)...............................789 14.9.15 PCI Express I/O Limit Upper 16 Bits Register (IO_Limit_Upper_16_Bits_Register).............................789 14.9.16 Capabilities Pointer Register (Capabilities_Pointer_Register)..................................................................790 14.9.17 PCI Express Interrupt Line Register (Interrupt_Line_Register)................................................................790 14.9.18 PCI Express Interrupt Pin Register (Interrupt_Pin_Register)....................................................................791 14.9.19 PCI Express Bridge Control Register (Bridge_Control_Register)............................................................791 14.10 PCI compatible device-specific configuration space....................................................................................................792 14.10.1 PCI Express Power Management Capability ID Register (Power_Management_Capability_ID_Register)........................................................................................794 14.10.2 PCI Express Power Management Capabilities Register (Power_Management_Capabilities_Register)...794 14.10.3 PCI Express Power Management Status and Control Register (Power_Management_Status_and_Control_Register)...............................................................................795 14.10.4 PCI Express Power Management Data Register (Power_Management_Data_Register)..........................796 14.10.5 PCI Express Capability ID Register (Capability_ID_Register).................................................................796 14.10.6 PCI Express Capabilities Register (Capabilities_Register).......................................................................797 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 29 Section number Title Page 14.10.7 PCI Express Device Capabilities Register (Device_Capabilities_Register)..............................................798 14.10.8 PCI Express Device Control Register (Device_Control_Register)...........................................................799 14.10.9 PCI Express Device Status Register (Device_Status_Register)................................................................800 14.10.10 PCI Express Link Capabilities Register (Link_Capabilities_Register).....................................................801 14.10.11 PCI Express Link Control Register (Link_Control_Register)...................................................................802 14.10.12 PCI Express Link Status Register (Link_Status_Register)........................................................................803 14.10.13 PCI Express Slot Capabilities Register (Slot_Capabilities_Register).......................................................804 14.10.14 PCI Express Slot Control Register (Slot_Control_Register).....................................................................805 14.10.15 PCI Express Slot Status Register (Slot_Status_Register)..........................................................................807 14.10.16 PCI Express Root Control Register (Root_Control_Register)..................................................................808 14.10.17 PCI Express Root Status Register (Root_Status_Register).......................................................................809 14.10.18 PCI Express MSI Message Capability ID Register (MSI_Message_Capability_ID_Register)................810 14.10.19 PCI Express MSI Message Control Register (MSI_Message_Control_Register).....................................810 14.10.20 PCI Express MSI Message Address Register (MSI_Message_Address_Register)...................................811 14.10.21 PCI Express MSI Message Upper Address Register (MSI_Message_Upper_Address_Register)............811 14.10.22 PCI Express MSI Message Data Register (MSI_Message_Data_Register)..............................................812 14.11 PCI Express extended configuration space...................................................................................................................812 14.11.1 PCI Express Advanced Error Reporting Capability ID Register (Advanced_Error_Reporting_Capability_ID_Register)............................................................................814 14.11.2 PCI Express Uncorrectable Error Status Register (Uncorrectable_Error_Status_Register)......................814 14.11.3 PCI Express Uncorrectable Error Mask Register (Uncorrectable_Error_Mask_Register)........................816 14.11.4 PCI Express Uncorrectable Error Severity Register (Uncorrectable_Error_Severity_Register)...............817 14.11.5 PCI Express Correctable Error Status Register (Correctable_Error_Status_Register)..............................818 14.11.6 PCI Express Correctable Error Mask Register (Correctable_Error_Mask_Register)................................819 14.11.7 PCI Express Advanced Error Capabilities and Control Register (Advanced_Error_Capabilities_and_Control_Register)............................................................................821 14.11.8 PCI Express Header Log Register 1 (Header_Log_Register_DWORD1)................................................822 14.11.9 PCI Express Header Log Register 2 (Header_Log_Register_DWORD2)................................................822 14.11.10 PCI Express Header Log Register 3 (Header_Log_Register_DWORD3)................................................823 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 30 Freescale Semiconductor, Inc. Section number Title Page 14.11.11 PCI Express Header Log Register 4 (Header_Log_Register_DWORD4)................................................824 14.11.12 PCI Express Root Error Command Register (Root_Error_Command_Register)......................................825 14.11.13 PCI Express Root Error Status Register (Root_Error_Status_Register)...................................................826 14.11.14 PCI Express Correctable Error Source ID Register (Correctable_Error_Source_ID_Register)................827 14.11.15 PCI Express Error Source ID Register (Error_Source_ID_Register)........................................................827 14.11.16 LTSSM State Status Register (LTSSM_State_Status_Register)...............................................................828 14.11.17 PCI Express Controller Core Clock Ratio Register (Controller_Core_Clock_Ratio_Register)................829 14.11.18 PCI Express Power Management Timer Register (Power_Management_Timer_Register)......................830 14.11.19 PCI Express PME Time-Out Register (PME_Time_Out_Register)..........................................................831 14.11.20 PCI Express Subsystem Vendor ID Update Register (Subsystem_Vendor_ID_Update_Register)..........831 14.11.21 Configuration Ready Register (Configuration_Ready_Register)..............................................................832 14.11.22 Flow Control Update Timeout Register (Flow_Control_Update_Timeout_Register)..............................833 14.11.23 Secondary Status Interrupt Mask Register (Secondary_Status_Interrupt_Mask_Register)......................834 14.12 Functional description...................................................................................................................................................835 14.12.1 Architecture................................................................................................................................................836 14.12.1.1 PCI Express transactions........................................................................................................836 14.12.1.2 Byte ordering..........................................................................................................................837 14.12.1.2.1 Address invariance..........................................................................................838 14.12.1.2.2 Byte order for configuration transactions.......................................................839 14.12.1.3 Lane reversal..........................................................................................................................840 14.12.1.4 Transaction ordering rules.....................................................................................................841 14.12.1.5 PCI Express outbound ATMUs.............................................................................................842 14.12.1.6 PCI Express inbound ATMUs...............................................................................................843 14.12.1.6.1 EP inbound ATMU implementation...............................................................843 14.12.1.6.2 RC inbound ATMU implementation..............................................................844 14.12.1.7 Memory space addressing......................................................................................................844 14.12.1.8 I/O space addressing..............................................................................................................845 14.12.1.9 Configuration space addressing.............................................................................................845 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 31 Section number Title Page 14.12.2 14.12.3 14.12.4 14.12.5 14.12.1.10 PCI Express configuration space access................................................................................846 14.12.1.10.1 RC configuration register access....................................................................846 14.12.1.10.1.1 PCI Express configuration access register mechanism........847 14.12.1.10.1.2 Outbound ATMU configuration mechanism (RC-only)......847 14.12.1.10.2 EP configuration register access.....................................................................848 14.12.1.11 Serialization of configuration and I/O writes.........................................................................848 14.12.1.12 Messages................................................................................................................................849 14.12.1.12.1 Outbound ATMU message generation...........................................................849 14.12.1.12.2 Inbound messages...........................................................................................850 14.12.1.13 Error handling........................................................................................................................852 14.12.1.13.1 PCI Express error logging and signaling........................................................853 14.12.1.13.2 PCI Express controller internal interrupt sources...........................................854 14.12.1.13.3 Error conditions .............................................................................................855 14.12.1.13.4 Error capture registers.....................................................................................858 14.12.1.13.4.1 Error capture registers (outbound error)...............................858 14.12.1.13.4.2 Error capture registers (inbound error).................................859 Interrupts....................................................................................................................................................862 14.12.2.1 EP interrupt generation..........................................................................................................862 14.12.2.1.1 Hardware INTx message generation...............................................................862 14.12.2.1.2 Hardware MSI generation...............................................................................863 14.12.2.1.3 Software INTx message generation................................................................863 14.12.2.1.4 Software MSI generation................................................................................863 14.12.2.2 RC handling of INTx message and MSI interrupts................................................................864 14.12.2.2.1 INTx message handling..................................................................................864 14.12.2.2.2 MSI handling..................................................................................................864 Initial credit advertisement.........................................................................................................................864 Power management....................................................................................................................................865 14.12.4.1 L2/L3 ready link state............................................................................................................866 Hot reset.....................................................................................................................................................866 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 32 Freescale Semiconductor, Inc. Section number Title Page 14.12.6 Link down..................................................................................................................................................866 14.13 Initialization/application information...........................................................................................................................867 14.13.1 EP Boot mode and inbound configuration transactions.............................................................................867 14.13.2 Automatic link retraining during initialization..........................................................................................868 14.13.3 Configuration accesses and inbound writes to CCSR space......................................................................868 Chapter 15 Enhanced Three-Speed Ethernet Controllers 15.1 Overview.......................................................................................................................................................................871 15.2 Features.........................................................................................................................................................................872 15.3 Modes of operation.......................................................................................................................................................874 15.4 eTSEC external signals description..............................................................................................................................876 15.4.1 Detailed signal descriptions.......................................................................................................................879 15.5 eTSEC memory map/register definition.......................................................................................................................883 15.5.1 Top-level module memory map.................................................................................................................883 15.5.2 Controller ID register * (eTSECx_TSEC_ID)...........................................................................................913 15.5.3 Controller ID register * (eTSECx_TSEC_ID2).........................................................................................914 15.5.4 Group Interrupt event register (eTSECx_IEVENTGn).............................................................................915 15.5.5 Group Interrupt mask register (eTSECx_IMASKGn)...............................................................................921 15.5.6 Error disabled register (eTSECx_EDIS)....................................................................................................923 15.5.7 Group Error mapping register (eTSECx_EMAPG)...................................................................................925 15.5.8 Ethernet control register (eTSECx_ECNTRL)..........................................................................................927 15.5.9 Pause time value register (eTSECx_PTV).................................................................................................931 15.5.10 DMA control register (eTSECx_DMACTRL)..........................................................................................932 15.5.11 TBI PHY address register (eTSECx_TBIPA)............................................................................................934 15.5.12 Transmit control register (eTSECx_TCTRL)............................................................................................934 15.5.13 Transmit status register (eTSECx_TSTATn).............................................................................................938 15.5.14 Default VLAN control word * (eTSECx_DFVLAN)................................................................................942 15.5.15 Transmit interrupt coalescing register (eTSECx_TXIC)...........................................................................943 15.5.16 Transmit queue control register * (eTSECx_TQUEUE)...........................................................................944 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 33 Section number Title Page 15.5.17 15.5.18 15.5.19 15.5.20 15.5.21 15.5.22 15.5.23 15.5.24 15.5.25 15.5.26 15.5.27 15.5.28 15.5.29 15.5.30 15.5.31 15.5.32 15.5.33 15.5.34 15.5.35 15.5.36 15.5.37 15.5.38 15.5.39 15.5.40 15.5.41 15.5.42 15.5.43 15.5.44 15.5.45 TxBD Rings 0-3 round-robin weightings * (eTSECx_TR03WT).............................................................945 TxBD Rings 4-7 round-robin weightings * (eTSECx_TR47WT).............................................................946 Tx data buffer pointer high bits * (eTSECx_TBDBPH)............................................................................947 TxBD pointer for ring n (eTSECx_TBPTRn)............................................................................................948 TxBD base address high bits * (eTSECx_TBASEH)................................................................................948 TxBD base address of ring n (eTSECx_TBASEn)....................................................................................949 Tx time stamp identification tag [set n] * (eTSECx_TMR_TXTSn_ID)..................................................949 Tx time stamp high [set n] * (eTSECx_TMR_TXTSn_H)........................................................................950 Tx time stamp low [set n] * (eTSECx_TMR_TXTSn_L).........................................................................950 Receive control register (eTSECx_RCTRL)..............................................................................................951 Receive status register (eTSECx_RSTATn)..............................................................................................954 Receive interrupt coalescing register (eTSECx_RXIC).............................................................................957 Receive queue control register * (eTSECx_RQUEUE).............................................................................958 Ring mapping register n * (eTSECx_RIRn)..............................................................................................960 Receive bit field extract control register * (eTSECx_RBIFX)..................................................................961 Receive queue filing table address register * (eTSECx_RQFAR)............................................................963 Receive queue filer table control register * (eTSECx_RQFCR)...............................................................964 Receive queue filing table property register * (eTSECx_RQFPR)............................................................966 Maximum receive buffer length register (eTSECx_MRBLR)...................................................................970 Receive packet wakeup timer register (eTSECx_RPWT).........................................................................971 Rx data buffer pointer high bits * (eTSECx_RBDBPH)...........................................................................972 RxBD pointer for ring n (eTSECx_RBPTRn)...........................................................................................972 RxBD base address high bits * (eTSECx_RBASEH)................................................................................973 RxBD base address of ring n (eTSECx_RBASEn)....................................................................................974 Rx timer time stamp register high * (eTSECx_TMR_RXTS_H)..............................................................974 Rx timer time stamp register low * (eTSECx_TMR_RXTS_L)................................................................975 MAC configuration register 1 (eTSECx_MACCFG1)..............................................................................976 MAC configuration register 2 (eTSECx_MACCFG2)..............................................................................978 Interpacket/interframe gap register (eTSECx_IPGIFG)............................................................................980 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 34 Freescale Semiconductor, Inc. Section number Title Page 15.5.46 15.5.47 15.5.48 15.5.49 15.5.50 15.5.51 15.5.52 15.5.53 15.5.54 15.5.55 15.5.56 15.5.57 15.5.58 15.5.59 15.5.60 15.5.61 15.5.62 15.5.63 15.5.64 15.5.65 15.5.66 15.5.67 15.5.68 15.5.69 15.5.70 15.5.71 15.5.72 15.5.73 15.5.74 Half-duplex control (eTSECx_HAFDUP).................................................................................................982 Maximum frame length (eTSECx_MAXFRM).........................................................................................983 Interface status (eTSECx_IFSTAT)...........................................................................................................983 MAC station address register 1 (eTSECx_MACSTNADDR1).................................................................985 MAC station address register 2 (eTSECx_MACSTNADDR2).................................................................985 MAC exact match address n, part 1 * (eTSECx_MACnADDR1).............................................................986 MAC exact match address n, part 2 * (eTSECx_MACnADDR2).............................................................987 Transmit and receive 64-byte frame counter (eTSECx_TR64).................................................................988 Transmit and receive 65- to 127-byte frame counter (eTSECx_TR127)...................................................988 Transmit and receive 128- to 255-byte frame counter (eTSECx_TR255).................................................989 Transmit and receive 256- to 511-byte frame counter (eTSECx_TR511).................................................989 Transmit and receive 512- to 1023-byte frame counter (eTSECx_TR1K)................................................990 Transmit and receive 1024- to 1518-byte frame counter (eTSECx_TRMAX)..........................................990 Transmit and receive 1519- to 1522-byte good VLAN frame count (eTSECx_TRMGV)........................991 Receive byte counter (eTSECx_RBYT)....................................................................................................991 Receive packet counter (eTSECx_RPKT).................................................................................................992 Receive FCS error counter (eTSECx_RFCS)............................................................................................992 Receive multicast packet counter (eTSECx_RMCA)................................................................................993 Receive broadcast packet counter (eTSECx_RBCA)................................................................................993 Receive control frame packet counter (eTSECx_RXCF)..........................................................................994 Receive PAUSE frame packet counter (eTSECx_RXPF).........................................................................994 Receive unknown OP code counter (eTSECx_RXUO).............................................................................995 Receive alignment error counter (eTSECx_RALN)..................................................................................995 Receive frame length error counter (eTSECx_RFLR)...............................................................................996 Receive code error counter (eTSECx_RCDE)...........................................................................................996 Receive carrier sense error counter (eTSECx_RCSE)...............................................................................997 Receive undersize packet counter (eTSECx_RUND)................................................................................997 Receive oversize packet counter (eTSECx_ROVR)..................................................................................998 Receive fragments counter (eTSECx_RFRG)...........................................................................................998 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 35 Section number Title Page 15.5.75 Receive jabber counter (eTSECx_RJBR)..................................................................................................999 15.5.76 Receive drop counter (eTSECx_RDRP)....................................................................................................999 15.5.77 Transmit byte counter (eTSECx_TBYT)...................................................................................................1000 15.5.78 Transmit packet counter (eTSECx_TPKT)................................................................................................1000 15.5.79 Transmit multicast packet counter (eTSECx_TMCA)...............................................................................1001 15.5.80 Transmit broadcast packet counter (eTSECx_TBCA)...............................................................................1001 15.5.81 Transmit PAUSE control frame counter (eTSECx_TXPF).......................................................................1002 15.5.82 Transmit deferral packet counter (eTSECx_TDFR)..................................................................................1002 15.5.83 Transmit excessive deferral packet counter (eTSECx_TEDF)..................................................................1003 15.5.84 Transmit single collision packet counter (eTSECx_TSCL).......................................................................1003 15.5.85 Transmit multiple collision packet counter (eTSECx_TMCL)..................................................................1004 15.5.86 Transmit late collision packet counter (eTSECx_TLCL)..........................................................................1004 15.5.87 Transmit excessive collision packet counter (eTSECx_TXCL)................................................................1005 15.5.88 Transmit total collision counter (eTSECx_TNCL)....................................................................................1005 15.5.89 Transmit drop frame counter (eTSECx_TDRP)........................................................................................1006 15.5.90 Transmit jabber frame counter (eTSECx_TJBR).......................................................................................1006 15.5.91 Transmit FCS error counter (eTSECx_TFCS)...........................................................................................1007 15.5.92 Transmit control frame counter (eTSECx_TXCF)....................................................................................1007 15.5.93 Transmit oversize frame counter (eTSECx_TOVR)..................................................................................1008 15.5.94 Transmit undersize frame counter (eTSECx_TUND)................................................................................1008 15.5.95 Transmit fragments frame counter (eTSECx_TFRG)................................................................................1009 15.5.96 Carry register one (eTSECx_CAR1)..........................................................................................................1010 15.5.97 Carry register two (eTSECx_CAR2).........................................................................................................1012 15.5.98 Carry register one mask register (eTSECx_CAM1)..................................................................................1014 15.5.99 Carry register two mask register (eTSECx_CAM2)..................................................................................1016 15.5.100 Receive filer rejected packet counter * (eTSECx_RREJ)..........................................................................1017 15.5.101 Individual/group address register n (eTSECx_IGADDRn).......................................................................1018 15.5.102 Group address register n (eTSECx_GADDRn).........................................................................................1019 15.5.103 Attribute register (eTSECx_ATTR)...........................................................................................................1019 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 36 Freescale Semiconductor, Inc. Section number Title Page 15.5.104 Attribute extract length and extract index register * (eTSECx_ATTRELI)..............................................1021 15.5.105 Receive Queue Parameters register n * (eTSECx_RQPRMn)...................................................................1022 15.5.106 Last Free RxBD pointer for ring n * (eTSECx_RFBPTRn)......................................................................1023 15.5.107 Interrupt steering register group n (eTSECx_ISRGn)................................................................................1023 15.5.108 Ring n Rx interrupt coalescing (eTSECx_RXICn)....................................................................................1026 15.5.109 Ring n Tx interrupt coalescing (eTSECx_TXICn)....................................................................................1028 15.6 eTSEC IEEE 1588 PTP memory map/register definition.............................................................................................1029 15.6.1 Timer control register * (eTSEC1x_TMR_CTRL)....................................................................................1030 15.6.2 Time stamp event register * (eTSEC1x_TMR_TEVENT)........................................................................1034 15.6.3 Timer event mask register * (eTSEC1x_TMR_TEMASK).......................................................................1035 15.6.4 Time stamp event register * (eTSEC1x_TMR_PEVENT)........................................................................1036 15.6.5 Timer event mask register * (eTSEC1x_TMR_PEMASK).......................................................................1037 15.6.6 Time stamp status register * (eTSEC1x_TMR_STAT).............................................................................1038 15.6.7 Timer counter high register * (eTSEC1x_TMR_CNT_H)........................................................................1039 15.6.8 Timer counter low register * (eTSEC1x_TMR_CNT_L)..........................................................................1040 15.6.9 Timer drift compensation addend register * (eTSEC1x_TMR_ADD)......................................................1041 15.6.10 Timer accumulator register * (eTSEC1x_TMR_ACC).............................................................................1042 15.6.11 Timer prescale * (eTSEC1x_TMR_PRSC)...............................................................................................1042 15.6.12 Timer offset high * (eTSEC1x_TMROFF_H)...........................................................................................1043 15.6.13 Timer offset low * (eTSEC1x_TMROFF_L)............................................................................................1043 15.6.14 Timer alarm n high register * (eTSEC1x_TMR_ALARMn_H)................................................................1044 15.6.15 Timer alarm n low register * (eTSEC1x_TMR_ALARMn_L).................................................................1045 15.6.16 Timer fixed period interval n * (eTSEC1x_TMR_FIPERn)......................................................................1045 15.6.17 Time stamp of general purpose external trigger * (eTSEC1x_TMR_ETTSn_H).....................................1047 15.6.18 Time stamp of general purpose external trigger * (eTSEC1x_TMR_ETTSn_L)......................................1047 15.7 MDIO memory map/register definition........................................................................................................................1048 15.7.1 MDIO Interrupt event register (eTSECx1_MDIO_IEVENTM)................................................................1049 15.7.2 MDIO Interrupt mask register (eTSECx1_MDIO_IMASKM).................................................................1051 15.7.3 MDIO Error mapping register (eTSECx1_MDIO_EMAPM)...................................................................1052 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 37 Section number Title Page 15.7.4 MII management configuration register (eTSECx1_MDIO_MIIMCFG).................................................1052 15.7.5 MII management command register (eTSECx1_MDIO_MIIMCOM)......................................................1054 15.7.6 MII management address register (eTSECx1_MDIO_MIIMADD)..........................................................1055 15.7.7 MII management control register (eTSECx1_MDIO_MIIMCON)...........................................................1056 15.7.8 MII management status register (eTSECx1_MDIO_MIIMSTAT)...........................................................1056 15.7.9 MII management indicator register (eTSECx1_MDIO_MIIMIND).........................................................1057 15.8 TBI memory map/register definition............................................................................................................................1057 15.8.1 Control (TBI_MII_Register_Set_CR).......................................................................................................1059 15.8.2 Status (TBI_MII_Register_Set_SR)..........................................................................................................1060 15.8.3 AN Advertisement Register for 1000Base-X auto-negotiation (TBI_MII_Register_Set_ANA)..............1061 15.8.4 AN Advertisement Register for SGMII auto-negotiation (TBI_MII_Register_Set_ANA_SGMII).........1063 15.8.5 AN Link Partner Base Page Ability Register for 1000Base-X auto-negotiation (TBI_MII_Register_Set_ANLPBPA)........................................................................................................1064 15.8.6 AN Link Partner Base Page Ability Register for SGMII auto-negotiation (TBI_MII_Register_Set_ANLPBPA_SGMII)..........................................................................................1065 15.8.7 AN expansion (TBI_MII_Register_Set_ANEX).......................................................................................1066 15.8.8 AN next page transmit (TBI_MII_Register_Set_ANNPT).......................................................................1067 15.8.9 AN link partner ability next page (TBI_MII_Register_Set_ANLPANP).................................................1068 15.8.10 Extended status (TBI_MII_Register_Set_EXST)......................................................................................1069 15.8.11 Jitter diagnostics (TBI_MII_Register_Set_JD).........................................................................................1070 15.8.12 TBI control (TBI_MII_Register_Set_TBICON).......................................................................................1071 15.9 Functional description...................................................................................................................................................1072 15.9.1 Programming model considerations ..........................................................................................................1072 15.9.1.1 MAC functionality.................................................................................................................1073 15.9.1.1.1 Configuring the MAC ....................................................................................1073 15.9.1.1.2 Controlling CSMA/CD ..................................................................................1074 15.9.1.1.3 Handling packet collisions .............................................................................1074 15.9.1.1.4 Controlling packet flow .................................................................................1075 15.9.1.1.5 Controlling PHY links ...................................................................................1076 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 38 Freescale Semiconductor, Inc. Section number Title Page 15.9.2 15.9.3 15.9.1.2 MIB registers .........................................................................................................................1076 15.9.1.3 Hash function registers ..........................................................................................................1077 15.9.1.4 Lossless flow control configuration registers........................................................................1078 15.9.1.5 Hardware assist for IEEE1588 compliant timestamping.......................................................1078 15.9.1.6 Interrupt steering and coalescing registers ............................................................................1078 15.9.1.7 Ten-bit interface (TBI)...........................................................................................................1079 Connecting to physical interfaces on Ethernet...........................................................................................1079 15.9.2.1 Media-independent interface (MII)........................................................................................1080 15.9.2.2 Reduced media-independent interface (RMII).......................................................................1081 15.9.2.3 Reduced gigabit media-independent interface (RGMII)........................................................1081 15.9.2.4 Serial gigabit media-independent interface (SGMII).............................................................1082 15.9.2.5 SGMII interface.....................................................................................................................1083 Gigabit Ethernet controller channel operation...........................................................................................1083 15.9.3.1 Initialization sequence............................................................................................................1084 15.9.3.1.1 Hardware controlled initialization..................................................................1084 15.9.3.1.2 User initialization............................................................................................1084 15.9.3.2 Soft reset and reconfiguring procedure..................................................................................1085 15.9.3.2.1 Timer soft reset and reconfiguring procedure.................................................1086 15.9.3.3 Gigabit Ethernet frame transmission......................................................................................1087 15.9.3.4 Gigabit Ethernet frame reception...........................................................................................1089 15.9.3.5 Ethernet preamble customization...........................................................................................1091 15.9.3.5.1 User-defined preamble transmission...............................................................1091 15.9.3.5.2 User-visible preamble reception ....................................................................1092 15.9.3.6 RMON support.......................................................................................................................1093 15.9.3.7 Frame recognition..................................................................................................................1093 15.9.3.7.1 Destination address recognition and frame filtering ......................................1093 15.9.3.7.2 Hash table algorithm ......................................................................................1095 15.9.3.8 Magic Packet mode................................................................................................................1097 15.9.3.9 Flow control ..........................................................................................................................1097 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 39 Section number Title Page 15.9.4 15.9.5 15.9.3.10 Grouping of rings...................................................................................................................1098 15.9.3.11 Interrupt handling...................................................................................................................1099 15.9.3.11.1 Interrupt coalescing.........................................................................................1100 15.9.3.11.2 Interrupt coalescing by frame count threshold ...............................................1101 15.9.3.11.3 Interrupt coalescing by timer threshold .........................................................1101 15.9.3.12 Interframe gap time................................................................................................................1102 15.9.3.13 Internal and external loop back .............................................................................................1103 15.9.3.14 Error-handling procedure ......................................................................................................1103 TCP/IP offload...........................................................................................................................................1106 15.9.4.1 Frame control blocks..............................................................................................................1107 15.9.4.2 Transmit path off-load and Tx PTP packet parsing ..............................................................1107 15.9.4.3 Receive path offload .............................................................................................................1109 Quality of service (QoS) provision............................................................................................................1112 15.9.5.1 Receive parser........................................................................................................................1112 15.9.5.2 Receive queue filer ................................................................................................................1114 15.9.5.2.1 Filing rules .....................................................................................................1114 15.9.5.2.2 Comparing properties with bit masks.............................................................1116 15.9.5.2.3 Special-case rules............................................................................................1117 15.9.5.2.4 Filer hash engine.............................................................................................1117 15.9.5.2.5 Ring index mapping logic...............................................................................1119 15.9.5.2.6 Hash function..................................................................................................1119 15.9.5.2.7 Filer interrupt events.......................................................................................1120 15.9.5.2.8 Setting up the receive queue filer table...........................................................1121 15.9.5.2.9 Filer example-802.1p priority filing ..............................................................1121 15.9.5.2.10 Filer example-IP diff-serv code points filing .................................................1122 15.9.5.2.11 Filer example-TCP and UDP port filing ........................................................1123 15.9.5.2.12 Filer example-hash on AND chain (2-tuple)..................................................1124 15.9.5.2.13 Filer example-hash on AND chain (3-tuple)..................................................1124 15.9.5.2.14 Filer example-hash on AND chain (5-tuple)..................................................1125 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 40 Freescale Semiconductor, Inc. Section number Title Page 15.9.5.2.15 Filer example-hash on cluster rules................................................................1126 15.9.5.2.16 Filer example-hash on compound rule............................................................1126 15.9.5.2.17 Filer example-interrupt from deep sleep.........................................................1127 15.9.5.3 Transmission scheduling........................................................................................................1129 15.9.5.3.1 Priority-based queuing (PBQ) ........................................................................1130 15.9.5.3.2 Modified weighted round-robin queuing (MWRR) .......................................1130 15.9.6 Lossless flow control.................................................................................................................................1132 15.9.6.1 Back pressure determination through free buffers.................................................................1132 15.9.6.2 Software use of hardware-initiated back pressure.................................................................1135 15.9.6.2.1 Initialization ...................................................................................................1135 15.9.6.2.2 Operation.........................................................................................................1135 15.9.7 Hardware assist for IEEE Std. 1588 compliant timestamping ..................................................................1136 15.9.7.1 Features..................................................................................................................................1136 15.9.7.2 Timer logic overview.............................................................................................................1137 15.9.7.3 Time stamp insertion on the received packets.......................................................................1139 15.9.7.3.1 Time stamp point............................................................................................1139 15.9.7.4 PTP packet parsing.................................................................................................................1139 15.9.7.4.1 General purpose filer rule...............................................................................1141 15.9.7.5 Time stamp insertion on transmit packets..............................................................................1141 15.9.7.5.1 Interrupts.........................................................................................................1141 15.9.7.5.2 Error condition................................................................................................1142 15.9.7.6 Tx PTP packet parsing...........................................................................................................1143 15.9.8 Buffer descriptors.......................................................................................................................................1145 15.9.8.1 Data buffer descriptors...........................................................................................................1145 15.9.8.2 Transmit data buffer descriptors (TxBD) ..............................................................................1147 15.9.8.3 Receive buffer descriptors (RxBD) .......................................................................................1150 15.10 Initialization/application information...........................................................................................................................1152 15.10.1 Interface mode configuration.....................................................................................................................1153 15.10.1.1 MII interface mode.................................................................................................................1153 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 41 Section number Title Page 15.10.1.2 RMII interface mode..............................................................................................................1156 15.10.1.3 RGMII interface mode...........................................................................................................1161 15.10.1.4 SGMII interface support........................................................................................................1165 15.10.2 Multigroup mode initialization..................................................................................................................1169 Chapter 16 Enhanced secure digital host controller (eSDHC) 16.1 eSDHC overview..........................................................................................................................................................1171 16.2 eSDHC features summary.............................................................................................................................................1173 16.2.1 Data transfer modes...................................................................................................................................1174 16.3 eSDHC external signal description...............................................................................................................................1174 16.4 Enhanced Secure Digital Host Controller (eSDHC) Memory Map..............................................................................1175 16.4.1 DMA system address (eSDHC_DSADDR)...............................................................................................1177 16.4.2 Block attributes (eSDHC_BLKATTR)......................................................................................................1177 16.4.3 Command argument (eSDHC_CMDARG)...............................................................................................1178 16.4.4 Command transfer type (eSDHC_XFERTYP)..........................................................................................1179 16.4.5 Command response n (eSDHC_CMDRSPn).............................................................................................1182 16.4.6 Data buffer access port (eSDHC_DATPORT)..........................................................................................1183 16.4.7 Present state (eSDHC_PRSSTAT)............................................................................................................1184 16.4.8 Protocol control (eSDHC_PROCTL)........................................................................................................1189 16.4.9 System control (eSDHC_SYSCTL)...........................................................................................................1192 16.4.10 Interrupt status (eSDHC_IRQSTAT).........................................................................................................1195 16.4.11 Interrupt status enable (eSDHC_IRQSTATEN)........................................................................................1199 16.4.12 Interrupt signal enable (eSDHC_IRQSIGEN)...........................................................................................1202 16.4.13 Auto CMD12 status (eSDHC_AUTOC12ERR)........................................................................................1204 16.4.14 Host controller capabilities (eSDHC_HOSTCAPBLT)............................................................................1208 16.4.15 Watermark level (eSDHC_WML).............................................................................................................1210 16.4.16 Force event (eSDHC_FEVT).....................................................................................................................1211 16.4.17 Host controller version (eSDHC_HOSTVER)..........................................................................................1213 16.4.18 DMA control register (eSDHC_DCR).......................................................................................................1214 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 42 Freescale Semiconductor, Inc. Section number Title Page 16.5 eSDHC functional description......................................................................................................................................1215 16.5.1 Data buffer.................................................................................................................................................1215 16.5.1.1 Write operation sequence.......................................................................................................1216 16.5.1.2 Read operation sequence........................................................................................................1217 16.5.1.3 Data buffer size......................................................................................................................1217 16.5.2 DMA CCB interface..................................................................................................................................1218 16.5.2.1 Internal DMA request............................................................................................................1218 16.5.2.2 DMA burst length..................................................................................................................1219 16.5.2.3 CCB Master interface.............................................................................................................1219 16.5.3 SD protocol unit.........................................................................................................................................1220 16.5.3.1 SD transceiver........................................................................................................................1220 16.5.3.2 SD clock and monitor............................................................................................................1220 16.5.3.3 Command agent.....................................................................................................................1221 16.5.3.4 Data agent..............................................................................................................................1221 16.5.4 Clock and reset manager............................................................................................................................1222 16.5.5 Clock generator..........................................................................................................................................1222 16.5.6 Card insertion and removal detection........................................................................................................1222 16.5.7 Power management and wake-up events...................................................................................................1223 16.5.7.1 Setting wake-up events..........................................................................................................1223 16.6 Initialization/application information...........................................................................................................................1224 16.6.1 Command send and response receive basic operation...............................................................................1224 16.6.2 Card identification mode............................................................................................................................1225 16.6.2.1 Card detect.............................................................................................................................1225 16.6.2.2 Reset.......................................................................................................................................1226 16.6.2.3 Voltage validation..................................................................................................................1227 16.6.2.4 Card registry...........................................................................................................................1228 16.6.3 Card access.................................................................................................................................................1230 16.6.3.1 Block write.............................................................................................................................1230 16.6.3.1.1 Normal write...................................................................................................1230 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 43 Section number Title Page 16.6.3.1.2 Write with pause.............................................................................................1231 16.6.3.2 Block read..............................................................................................................................1232 16.6.3.2.1 Normal read....................................................................................................1232 16.6.3.2.2 Read with pause..............................................................................................1233 16.6.3.3 Transfer error.........................................................................................................................1234 16.6.3.3.1 CRC error........................................................................................................1234 16.6.3.3.2 Internal DMA error.........................................................................................1234 16.6.3.3.3 Auto CMD12 error..........................................................................................1235 16.6.3.4 Card interrupt.........................................................................................................................1235 16.6.4 Switch function..........................................................................................................................................1235 16.6.4.1 Query, enable and disable SD high speed mode....................................................................1236 16.6.4.2 Query, enable and disable MMC high speed mode...............................................................1236 16.6.4.3 Set MMC bus width...............................................................................................................1237 16.6.5 Commands for MMC/SD...........................................................................................................................1237 16.6.6 Software restrictions..................................................................................................................................1243 Chapter 17 Universal Serial Bus Interface 17.1 Introduction...................................................................................................................................................................1245 17.1.1 Overview....................................................................................................................................................1246 17.1.2 Features......................................................................................................................................................1246 17.1.3 Modes of operation....................................................................................................................................1247 17.2 USB external signals.....................................................................................................................................................1247 17.2.1 ULPI interface............................................................................................................................................1247 17.2.2 PHY clocks................................................................................................................................................1248 17.3 USB memory map/register definition...........................................................................................................................1249 17.3.1 Identification register (USBx_ID)..............................................................................................................1253 17.3.2 Capability register length (USBx_CAPLENGTH)....................................................................................1254 17.3.3 Host controller interface version number (USBx_HCIVERSION)...........................................................1254 17.3.4 Host controller structural parameters (USBx_HCSPARAMS).................................................................1255 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 44 Freescale Semiconductor, Inc. Section number Title Page 17.3.5 17.3.6 17.3.7 17.3.8 17.3.9 17.3.10 17.3.11 17.3.12 17.3.13 17.3.14 17.3.15 17.3.16 17.3.17 17.3.18 17.3.19 17.3.20 17.3.21 17.3.22 17.3.23 17.3.24 17.3.25 17.3.26 17.3.27 17.3.28 17.3.29 17.3.30 17.3.31 17.3.32 17.3.33 Host controller capability parameters (USBx_HCCPARAMS)................................................................1256 Device controller interface version number (USBx_DCIVERSION).......................................................1258 Device controller capability parameters (USBx_DCCPARAMS).............................................................1259 USB command (USBx_USBCMD)...........................................................................................................1259 USB status (USBx_USBSTS)....................................................................................................................1264 USB interrupt enable (USBx_USBINTR).................................................................................................1268 USB frame index (USBx_FRINDEX).......................................................................................................1270 Periodic frame list base address [host mode] (USBx_PERIODICLISTBASE)........................................1271 USB device address [device mode] (USBx_DEVICEADDR)..................................................................1272 Next asynchronous list addr [host mode] (USBx_ASYNCLISTADDR)..................................................1272 Address at endpoint list [device mode] (USBx_ENDPOINTLISTADDR)...............................................1273 Master interface data burst size (USBx_BURSTSIZE).............................................................................1274 Transmit FIFO tuning controls (USBx_TXFILLTUNING)......................................................................1274 ULPI register access (USBx_ULPI_VIEWPORT)....................................................................................1276 Configured flag register (USBx_CONFIGFLAG).....................................................................................1279 Port status/control (USBx_PORTSC)........................................................................................................1279 USB device mode (USBx_USBMODE)....................................................................................................1286 Endpoint setup status (USBx_ENDPTSETUPSTAT)...............................................................................1287 Endpoint initialization (USBx_ENDPOINTPRIME)................................................................................1288 Endpoint flush (USBx_ENDPTFLUSH)...................................................................................................1289 Endpoint status (USBx_ENDPTSTATUS)................................................................................................1289 Endpoint complete (USBx_ENDPTCOMPLETE)....................................................................................1290 Endpoint control 0 (USBx_ENDPTCTRL0).............................................................................................1292 Endpoint control n (USBx_ENDPTCTRLn).............................................................................................1294 Snoop n (USBx_SNOOPn)........................................................................................................................1296 Age count threshold (USBx_AGE_CNT_THRESH)................................................................................1297 Priority control (USBx_PRI_CTRL).........................................................................................................1299 System interface control (USBx_SI_CTRL)..............................................................................................1300 Control (USBx_CONTROL).....................................................................................................................1301 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 45 Section number Title Page 17.4 Functional description...................................................................................................................................................1302 17.4.1 System interface.........................................................................................................................................1302 17.4.2 DMA engine...............................................................................................................................................1302 17.4.3 FIFO RAM controller................................................................................................................................1303 17.4.4 PHY interface.............................................................................................................................................1303 17.5 Host data structures.......................................................................................................................................................1303 17.5.1 Periodic frame list......................................................................................................................................1304 17.5.2 Asynchronous list queue head pointer.......................................................................................................1306 17.5.3 Isochronous (high-speed) transfer descriptor (iTD)...................................................................................1306 17.5.3.1 Next link pointer-iTD.............................................................................................................1307 17.5.3.2 iTD transaction status and control list....................................................................................1308 17.5.3.3 iTD buffer page pointer list (plus).........................................................................................1309 17.5.4 Split transaction isochronous transfer descriptor (siTD)...........................................................................1311 17.5.4.1 Next link pointer-siTD...........................................................................................................1311 17.5.4.2 siTD endpoint capabilities/characteristics.............................................................................1312 17.5.4.3 siTD transfer state..................................................................................................................1313 17.5.4.4 siTD buffer pointer list (plus)................................................................................................1314 17.5.4.5 siTD back link pointer............................................................................................................1315 17.5.5 Queue element transfer descriptor (qTD)..................................................................................................1315 17.5.5.1 Next qTD pointer...................................................................................................................1316 17.5.5.2 Alternate next qTD pointer....................................................................................................1317 17.5.5.3 qTD token..............................................................................................................................1317 17.5.5.4 qTD buffer page pointer list...................................................................................................1320 17.5.6 Queue head.................................................................................................................................................1321 17.5.6.1 Queue head horizontal link pointer........................................................................................1321 17.5.6.2 Endpoint capabilities/characteristics .....................................................................................1322 17.5.6.3 Transfer overlay.....................................................................................................................1324 17.5.7 Periodic frame span traversal node (FSTN)...............................................................................................1326 17.5.7.1 FSTN normal path pointer.....................................................................................................1326 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 46 Freescale Semiconductor, Inc. Section number Title Page 17.5.7.2 FSTN back path link pointer..................................................................................................1327 17.6 Host operations.............................................................................................................................................................1327 17.6.1 Host controller initialization......................................................................................................................1327 17.6.2 Power port..................................................................................................................................................1329 17.6.3 Reporting over-current...............................................................................................................................1329 17.6.4 Suspend/resume ........................................................................................................................................1329 17.6.4.1 Port suspend/resume..............................................................................................................1330 17.6.5 Schedule traversal rules.............................................................................................................................1332 17.6.6 Periodic schedule frame boundaries vs. bus frame boundaries..................................................................1334 17.6.7 Periodic schedule.......................................................................................................................................1336 17.6.8 Managing isochronous transfers using iTDs..............................................................................................1337 17.6.8.1 Host controller operational model for iTDs...........................................................................1338 17.6.8.2 Software operational model for iTDs.....................................................................................1340 17.6.8.2.1 Periodic scheduling threshold.........................................................................1342 17.6.9 Asynchronous schedule..............................................................................................................................1343 17.6.9.1 Adding queue heads to asynchronous schedule.....................................................................1345 17.6.9.2 Removing queue heads from asynchronous schedule............................................................1345 17.6.9.3 Empty asynchronous schedule detection ..............................................................................1348 17.6.9.4 Asynchronous schedule traversal: Start event.......................................................................1349 17.6.9.5 Reclamation status bit (USBSTS Register)...........................................................................1349 17.6.10 Managing control/bulk/interrupt transfers via queue heads.......................................................................1350 17.6.10.1 Buffer pointer list use for data streaming with qTDs ............................................................1351 17.6.10.2 Adding interrupt queue heads to the periodic schedule ........................................................1353 17.6.10.3 Managing transfer complete interrupts from queue heads ....................................................1353 17.6.11 Ping control................................................................................................................................................1354 17.6.12 Split transactions........................................................................................................................................1355 17.6.12.1 Split transactions for asynchronous transfers ........................................................................1356 17.6.12.1.1 Asynchronous-do-start-split............................................................................1356 17.6.12.1.2 Asynchronous-do-complete-split ...................................................................1357 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 47 Section number Title Page 17.6.13 17.6.14 17.6.12.2 Split transaction interrupt ......................................................................................................1358 17.6.12.2.1 Split transaction scheduling mechanisms for interrupt ..................................1359 17.6.12.2.2 Host controller operational model for FSTNs ...............................................1362 17.6.12.2.3 Software operational model for FSTNs..........................................................1365 17.6.12.2.4 Tracking split transaction progress for interrupt transfers .............................1366 17.6.12.2.5 Split transaction execution state machine for interrupt ..................................1367 17.6.12.2.6 Periodic interrupt-do-start-split ......................................................................1368 17.6.12.2.7 Periodic interrupt-do-complete-split ..............................................................1369 17.6.12.2.8 Managing the QH[FrameTag] field ...............................................................1373 17.6.12.2.9 Rebalancing the periodic schedule .................................................................1374 17.6.12.3 Split transaction isochronous ................................................................................................1375 17.6.12.3.1 Split transaction scheduling mechanisms for isochronous ............................1375 17.6.12.3.2 Tracking split transaction progress for isochronous transfers .......................1380 17.6.12.3.3 Split transaction execution state machine for isochronous ............................1382 17.6.12.3.4 Periodic isochronous-do-start-split ................................................................1383 17.6.12.3.5 Periodic isochronous-do complete split..........................................................1385 17.6.12.3.6 Complete-split for scheduling boundary cases 2a, 2b....................................1388 17.6.12.3.7 Split transaction for isochronous-processing example...................................1390 Port test modes...........................................................................................................................................1392 Interrupts....................................................................................................................................................1392 17.6.14.1 Transfer/transaction based interrupts.....................................................................................1394 17.6.14.1.1 Transaction error.............................................................................................1394 17.6.14.1.2 Serial bus babble.............................................................................................1394 17.6.14.1.3 Data buffer error ............................................................................................1395 17.6.14.1.4 USB interrupt (interrupt on completion (IOC))..............................................1396 17.6.14.1.5 Short packet....................................................................................................1396 17.6.14.2 Host controller event interrupts..............................................................................................1396 17.6.14.2.1 Port change events..........................................................................................1397 17.6.14.2.2 Frame list rollover...........................................................................................1397 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 48 Freescale Semiconductor, Inc. Section number Title Page 17.6.14.2.3 Interrupt on async advance.............................................................................1397 17.6.14.2.4 Host system error............................................................................................1397 17.7 Device data structures...................................................................................................................................................1398 17.7.1 Endpoint queue head..................................................................................................................................1399 17.7.1.1 Endpoint capabilities/characteristics .....................................................................................1400 17.7.1.2 Transfer overlay ....................................................................................................................1401 17.7.1.3 Current dTD pointer...............................................................................................................1401 17.7.1.4 Setup buffer............................................................................................................................1402 17.7.2 Endpoint transfer descriptor (dTD)............................................................................................................1402 17.8 Device operational model.............................................................................................................................................1404 17.8.1 Device controller initialization...................................................................................................................1405 17.8.2 Port state and control..................................................................................................................................1406 17.8.2.1 Bus reset.................................................................................................................................1408 17.8.2.2 Suspend/resume ....................................................................................................................1409 17.8.2.2.1 Suspend description........................................................................................1409 17.8.2.2.2 Suspend operational model.............................................................................1410 17.8.2.2.3 Resume............................................................................................................1410 17.8.3 Managing endpoints...................................................................................................................................1410 17.8.3.1 Endpoint initialization............................................................................................................1411 17.8.3.1.1 Stalling............................................................................................................1412 17.8.3.2 Data toggle.............................................................................................................................1412 17.8.3.2.1 Data toggle reset.............................................................................................1413 17.8.3.2.2 Data toggle inhibit...........................................................................................1413 17.8.3.3 Device operational model for packet transfers.......................................................................1413 17.8.3.3.1 Priming transmit endpoints.............................................................................1414 17.8.3.3.2 Priming receive endpoints...............................................................................1414 17.8.3.4 Interrupt/bulk endpoint operational model............................................................................1414 17.8.3.4.1 Interrupt/bulk endpoint bus response matrix..................................................1416 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 49 Section number Title Page 17.8.3.5 Control endpoint operation model.........................................................................................1417 17.8.3.5.1 Setup phase.....................................................................................................1417 17.8.3.5.2 Data phase.......................................................................................................1418 17.8.3.5.3 Status phase.....................................................................................................1418 17.8.3.5.4 Control endpoint bus response matrix............................................................1419 17.8.3.6 Isochronous endpoint operational model...............................................................................1419 17.8.3.6.1 Isochronous pipe synchronization...................................................................1421 17.8.3.6.2 Isochronous endpoint bus response matrix.....................................................1421 17.8.4 Managing queue heads...............................................................................................................................1422 17.8.4.1 Queue head initialization.......................................................................................................1422 17.8.4.2 Operational model for setup transfers....................................................................................1423 17.8.5 Managing transfers with transfer descriptors.............................................................................................1424 17.8.5.1 Software link pointers............................................................................................................1424 17.8.5.2 Building a transfer descriptor.................................................................................................1425 17.8.5.3 Executing a transfer descriptor..............................................................................................1425 17.8.5.4 Transfer completion...............................................................................................................1426 17.8.5.5 Flushing/depriming an endpoint............................................................................................1427 17.8.5.6 Device error matrix................................................................................................................1427 17.8.6 Servicing interrupts....................................................................................................................................1428 17.8.6.1 High-frequency interrupts......................................................................................................1428 17.8.6.2 Low-frequency interrupts.......................................................................................................1428 17.8.6.3 Error interrupts.......................................................................................................................1429 17.9 Deviations from the EHCI specifications.....................................................................................................................1429 17.9.1 Embedded transaction translator function..................................................................................................1430 17.9.1.1 Capability registers................................................................................................................1430 17.9.1.2 Operational registers..............................................................................................................1430 17.9.1.3 Discovery ..............................................................................................................................1430 17.9.1.4 Data structures........................................................................................................................1431 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 50 Freescale Semiconductor, Inc. Section number Title Page 17.9.1.5 Operational model..................................................................................................................1432 17.9.1.5.1 Microframe pipeline........................................................................................1432 17.9.1.5.2 Split state machines.........................................................................................1433 17.9.1.5.3 Asynchronous transaction scheduling and buffer management......................1433 17.9.1.5.4 Periodic transaction scheduling and buffer management...............................1434 17.9.1.5.5 Multiple transaction translators.......................................................................1434 17.9.2 Device operation........................................................................................................................................1434 17.9.3 Non-zero fields the register file.................................................................................................................1434 17.9.4 SOF interrupt..............................................................................................................................................1435 17.9.5 Embedded design.......................................................................................................................................1435 17.9.5.1 Frame adjust register..............................................................................................................1435 17.9.6 Miscellaneous variations from EHCI.........................................................................................................1435 17.9.6.1 Discovery...............................................................................................................................1436 17.9.6.1.1 Port reset.........................................................................................................1436 17.9.6.1.2 Port speed detection........................................................................................1436 Chapter 18 Enhanced Serial Peripheral Interface 18.1 Introduction...................................................................................................................................................................1437 18.1.1 Features......................................................................................................................................................1438 18.1.2 eSPI transmission and reception process...................................................................................................1439 18.1.3 Modes of operation....................................................................................................................................1439 18.2 External signal descriptions..........................................................................................................................................1440 18.2.1 Overview....................................................................................................................................................1440 18.2.2 ESPI detailed signal descriptions ..............................................................................................................1441 18.3 Enhanced serial peripheral interface (eSPI) memory map...........................................................................................1442 18.3.1 eSPI mode register (ESPI_SPMODE).......................................................................................................1443 18.3.2 eSPI event register (ESPI_SPIE)...............................................................................................................1445 18.3.3 eSPI mask register (ESPI_SPIM)..............................................................................................................1447 18.3.4 eSPI command register (ESPI_SPCOM)...................................................................................................1449 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 51 Section number Title Page 18.3.5 eSPI transmit FIFO access register (ESPI_SPITF)....................................................................................1451 18.3.6 eSPI receive FIFO access register (ESPI_SPIRF).....................................................................................1453 18.3.7 eSPI CS0 mode register (ESPI_SPMODE0).............................................................................................1454 18.3.8 eSPI CS1 mode register (ESPI_SPMODE1).............................................................................................1456 18.3.9 eSPI CS2 mode register (ESPI_SPMODE2).............................................................................................1458 18.3.10 eSPI CS3 mode register (ESPI_SPMODE3).............................................................................................1460 18.4 eSPI transfer formats.....................................................................................................................................................1461 18.5 CI and CP values for various eSPI devices...................................................................................................................1462 18.6 eSPI programming examples........................................................................................................................................1463 18.6.1 24-bit address example...............................................................................................................................1463 18.6.2 16-bit address example...............................................................................................................................1463 Chapter 19 Time Division Multiplexing (TDM) 19.1 Introduction...................................................................................................................................................................1465 19.1.1 TDM features.............................................................................................................................................1465 19.2 TDM signal descriptions...............................................................................................................................................1466 19.2.1 TDM signals overview...............................................................................................................................1466 19.2.2 TDM external signals descriptions............................................................................................................1466 19.3 TDM overview..............................................................................................................................................................1467 19.3.1 TDM basics................................................................................................................................................1468 19.3.2 Common signals for the TDM modules.....................................................................................................1470 19.4 TDM programming model............................................................................................................................................1471 19.4.1 SB interface................................................................................................................................................1471 19.5 TDM_SB memory map/register definition...................................................................................................................1472 19.5.1 TDM general interface register (TDM_SB_TDMGIR).............................................................................1473 19.5.2 TDM receive interface register (TDM_SB_TDMRIR).............................................................................1475 19.5.3 TDM transmit interface register (TDM_SB_TDMTIR)............................................................................1477 19.5.4 TDM receive frame parameters (TDM_SB_TDMRFP)............................................................................1480 19.5.5 TDM transmit frame parameters (TDM_SB_TDMTFP)...........................................................................1482 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 52 Freescale Semiconductor, Inc. Section number Title Page 19.5.6 TDM receive channel enable registers (TDM_SB_TDMRCENn)............................................................1483 19.5.7 TDM transmit channel enable registers (TDM_SB_TDMTCENn)..........................................................1484 19.5.8 TDM transmit channel mask registers (TDM_SB_TDMTCMAn)...........................................................1485 19.5.9 TDM receive control register (TDM_SB_TDMRCR)...............................................................................1485 19.5.10 TDM transmit control register (TDM_SB_TDMTCR).............................................................................1486 19.5.11 TDM receive interrupt enable register (TDM_SB_TDMRIER)................................................................1487 19.5.12 TDM transmit interrupt enable register (TDM_SB_TDMTIER)..............................................................1488 19.5.13 TDM receive event register (TDM_SB_TDMRER).................................................................................1490 19.5.14 TDM transmit event register (TDM_SB_TDMTER)................................................................................1492 19.5.15 TDM receive status register (TDM_SB_TDMRSR).................................................................................1494 19.5.16 TDM transmit status register (TDM_SB_TDMTSR)................................................................................1495 19.6 AHB interface...............................................................................................................................................................1495 19.7 TDM_AHB memory map/register definition...............................................................................................................1496 19.7.1 TDM receive data registers (TDM_AHB_TDMRDREG).........................................................................1497 19.7.2 TDM transmit data registers (TDM_AHB_TDMTDREG).......................................................................1498 19.8 Clocks and reset............................................................................................................................................................1498 19.8.1 TDM clock and frame sync generation......................................................................................................1499 19.8.2 Reset...........................................................................................................................................................1500 19.9 TDM configurations......................................................................................................................................................1501 19.9.1 Typical configurations...............................................................................................................................1501 19.10 TDM detailed operation................................................................................................................................................1502 19.10.1 Serial interface...........................................................................................................................................1503 19.10.1.1 Sync out configuration...........................................................................................................1503 19.10.1.2 Sync in configuration.............................................................................................................1503 19.10.1.3 Serial interface synchronization.............................................................................................1507 19.10.1.4 Reverse data order..................................................................................................................1509 19.10.2 Receiver and transmitter independent or shared operation........................................................................1510 19.10.3 TDM multichannel (network) mode..........................................................................................................1512 19.10.3.1 Operation using Tx channel mask register.............................................................................1512 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 53 Section number Title Page 19.10.3.2 Operation using Rx channel enable register..........................................................................1514 19.10.4 Data structures............................................................................................................................................1515 19.10.5 FIFO configuration....................................................................................................................................1516 19.10.6 DMA configuration....................................................................................................................................1517 19.10.6.1 Setting up the TDM for correct operation with the DMA.....................................................1518 19.11 Software programming.................................................................................................................................................1518 19.11.1 Software programming sequence...............................................................................................................1518 19.11.1.1 Initialization-shared operation starting on the same frame....................................................1519 19.11.1.2 Initialization-non-shared operation........................................................................................1519 19.11.1.3 Dynamic channel configuration while TDM operating-shared.............................................1520 19.11.1.4 Dynamic channel configuration while TDM operating-non-shared......................................1521 19.11.1.5 Configuring the TDM for I2S operation................................................................................1522 19.11.1.6 TDM power down..................................................................................................................1522 19.11.1.7 Synchronization errors...........................................................................................................1522 19.11.2 Interrupts....................................................................................................................................................1523 19.11.2.1 Receiver normal and receiver error interrupts.......................................................................1523 19.11.2.2 Transmit normal and transmit error TDMRDREG................................................................1523 19.12 DMA controller (DMAC).............................................................................................................................................1523 19.12.1 Overview....................................................................................................................................................1524 19.12.1.1 DMAC features......................................................................................................................1525 19.12.2 TDM_DMAC memory map/register definition.........................................................................................1525 19.122.1 DMA Control Register (TDM_DMAC_DMACR)................................................................1527 19.122.2 DMA Error Status Register (TDM_DMAC_DMAES).........................................................1530 19.122.3 DMA enable request register (TDM_DMAC_DMAERQ)...................................................1533 19.122.4 DMA enable error interrupt register (TDM_DMAC_DMAEEI)..........................................1534 19.122.5 DMA set enable request (TDM_DMAC_DMASERQ).........................................................1535 19.122.6 DMA clear enable request (TDM_DMAC_DMACERQ).....................................................1536 19.122.7 DMA Set Enable Error Interrupt (TDM_DMAC_DMASEEI).............................................1537 19.122.8 DMA Clear Enable Error Interrupt (TDM_DMAC_DMACEEI).........................................1538 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 54 Freescale Semiconductor, Inc. Section number Title Page 19.12.3 19.12.4 19.12.5 19.12.6 19.122.9 DMA Clear Interrupt Request (TDM_DMAC_DMACINT).................................................1539 19.122.10 DMA Clear Error (TDM_DMAC_DMACERR)...................................................................1540 19.122.11 DMA Set START Bit (TDM_DMAC_DMASSRT).............................................................1541 19.122.12 DMA Clear DONE Status Bit (TDM_DMAC_DMACDNE)...............................................1542 19.122.13 DMA interrupt request register (TDM_DMAC_DMAINT).................................................1542 19.122.14 DMA error register (TDM_DMAC_DMAERR)...................................................................1543 19.122.15 DMA hardware request status register (TDM_DMAC_DMAHRS).....................................1544 19.122.16 DMA general purpose output register (TDM_DMAC_DMAGPOR)...................................1545 19.122.17 DMA Channel n Priority Register (TDM_DMAC_DCHPRIn)............................................1546 19.122.18 Transfer Control Descriptor Word 0 (TDM_DMAC_TCDW0)............................................1547 19.122.19 Transfer Control Descriptor Word 1 (TDM_DMAC_TCDW1)............................................1548 19.122.20 Transfer Control Descriptor Word 2 (TDM_DMAC_TCDW2)............................................1549 19.122.21 Transfer Control Descriptor Word 3 (TDM_DMAC_TCDW3)............................................1551 19.122.22 Transfer Control Descriptor Word 4 (TDM_DMAC_TCDW4)............................................1551 19.122.23 Transfer Control Descriptor Word 5 (TDM_DMAC_TCDW5)............................................1552 19.122.24 Transfer Control Descriptor Word 6 (TDM_DMAC_TCDW6)............................................1553 19.122.25 Transfer Control Descriptor Word 7 (TDM_DMAC_TCDW7)............................................1554 Functional description................................................................................................................................1556 19.12.3.1 DMA microarchitecture.........................................................................................................1556 19.12.3.2 DMA basic data flow.............................................................................................................1557 Initialization/application information........................................................................................................1560 19.12.4.1 DMA initialization.................................................................................................................1560 19.12.4.2 DMA programming errors.....................................................................................................1561 DMA transfer.............................................................................................................................................1562 19.12.5.1 Single request.........................................................................................................................1562 19.12.5.2 Multiple requests....................................................................................................................1563 TCD status..................................................................................................................................................1565 19.12.6.1 Minor loop complete..............................................................................................................1565 19.12.6.2 Active channel TCD reads.....................................................................................................1566 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 55 Section number Title Page 19.12.7 Hardware request release timing................................................................................................................1566 Chapter 20 General-Purpose I/O (GPIO) Module 20.1 Introduction...................................................................................................................................................................1569 20.1.1 Overview....................................................................................................................................................1569 20.1.2 Features......................................................................................................................................................1570 20.2 External signal description............................................................................................................................................1570 20.2.1 Signals overview........................................................................................................................................1570 20.3 GPIO memory map/register definition.........................................................................................................................1570 20.3.1 GPIO direction register (GPIO_GPDIR)...................................................................................................1571 20.3.2 GPIO open drain register (GPIO_GPODR)...............................................................................................1572 20.3.3 GPIO data register (GPIO_GPDAT).........................................................................................................1572 20.3.4 GPIO interrupt event register (GPIO_GPIER)..........................................................................................1573 20.3.5 GPIO interrupt mask register (GPIO_GPIMR).........................................................................................1573 20.3.6 GPIO external interrupt control register (GPIO_GPICR)..........................................................................1574 Chapter 21 Device Performance Monitor 21.1 Introduction...................................................................................................................................................................1575 21.1.1 Overview....................................................................................................................................................1576 21.1.2 Features......................................................................................................................................................1577 21.2 Signal descriptions........................................................................................................................................................1578 21.3 PERFMON Memory Map/Register Definition.............................................................................................................1578 21.3.1 Performance monitor global control register (PERFMON_PMGC0).......................................................1580 21.3.2 Performance monitor local control register A0 (PERFMON_PMLCA0).................................................1581 21.3.3 Performance monitor local control register B0 (PERFMON_PMLCB0)..................................................1582 21.3.4 Performance monitor counter 0 lower (PERFMON_PMC0_upper).........................................................1583 21.3.5 Performance monitor counter 0 upper (PERFMON_PMC0_lower).........................................................1584 21.3.6 Performance monitor local control register An (PERFMON_PMLCAn).................................................1585 21.3.7 Performance monitor local control register Bn (PERFMON_PMLCBn)..................................................1586 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 56 Freescale Semiconductor, Inc. Section number Title Page 21.3.8 Performance monitor counter n (PERFMON_PMCn)...............................................................................1587 21.4 Functional description...................................................................................................................................................1588 21.4.1 Performance monitor interrupt...................................................................................................................1588 21.4.2 Event counting...........................................................................................................................................1588 21.4.3 Threshold events........................................................................................................................................1589 21.4.4 Chaining.....................................................................................................................................................1590 21.4.5 Triggering...................................................................................................................................................1591 21.4.6 Burstiness counting....................................................................................................................................1591 21.4.7 Performance monitor events......................................................................................................................1594 21.4.8 Performance monitor examples.................................................................................................................1603 21.5 Initialization/application information...........................................................................................................................1604 Chapter 22 Global Utilities 22.1 Introduction...................................................................................................................................................................1607 22.2 Overview.......................................................................................................................................................................1607 22.3 Global utilities features.................................................................................................................................................1607 22.3.1 Power management and block disables.....................................................................................................1607 22.3.2 Accessing current POR configuration settings..........................................................................................1608 22.3.3 Clock control..............................................................................................................................................1608 22.4 Global utilities external signal description...................................................................................................................1608 22.4.1 Signals overview........................................................................................................................................1608 22.4.2 Detailed signal descriptions.......................................................................................................................1608 22.5 GUTS Memory Map/Register Definition.....................................................................................................................1610 22.5.1 POR PLL ratio status register (GUTS_PORPLLSR)................................................................................1612 22.5.2 POR boot mode status register (GUTS_PORBMSR)................................................................................1615 22.5.3 POR device status register (GUTS_PORDEVSR)....................................................................................1617 22.5.4 POR debug mode status register (GUTS_PORDBGMSR).......................................................................1620 22.5.5 POR device status register 2 (GUTS_PORDEVSR2)...............................................................................1622 22.5.6 General-purpose POR configuration register (GUTS_GPPORCR)..........................................................1624 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 57 Section number Title Page 22.5.7 Alternate function signal multiplex control (GUTS_PMUXCR)..............................................................1625 22.5.8 Device disable register (GUTS_DEVDISR)..............................................................................................1626 22.5.9 Power management control and status register (GUTS_POWMGTCSR)................................................1630 22.5.10 Power management clock disable register (GUTS_PMCDR)...................................................................1633 22.5.11 Machine check summary register (GUTS_MCPSUMR)...........................................................................1634 22.5.12 Reset request status and control register (GUTS_RSTRSCR)..................................................................1637 22.5.13 Exception reset control register (GUTS_ECTRSTCR).............................................................................1638 22.5.14 Automatic reset status register (GUTS_AUTORSTSR)............................................................................1640 22.5.15 Processor version register (GUTS_PVR)..................................................................................................1642 22.5.16 System version register (GUTS_SVR)......................................................................................................1642 22.5.17 Reset control register (GUTS_RSTCR).....................................................................................................1643 22.5.18 I/O voltage select status register (GUTS_IOVSELSR).............................................................................1644 22.5.19 DDR clock disable register (GUTS_DDRCLKDR)..................................................................................1645 22.5.20 Clock out control register (GUTS_CLKOCR)..........................................................................................1646 22.5.21 ECM control register (GUTS_ECMCR)....................................................................................................1647 22.5.22 SRDS Control Register 0 (GUTS_SRDSCR0)..........................................................................................1648 22.5.23 SRDS Control Register 1 (GUTS_SRDSCR1)..........................................................................................1650 22.5.24 SRDS Control Register 2 (GUTS_SRDSCR2)..........................................................................................1651 22.5.25 SRDS Control Register 3 (GUTS_SRDSCR3)..........................................................................................1653 22.5.26 SRDS Control Register 4 (GUTS_SRDSCR4)..........................................................................................1656 22.6 Functional description...................................................................................................................................................1657 22.6.1 Power management....................................................................................................................................1657 22.6.1.1 Relationship between both cores and device power management states...............................1658 22.6.1.2 CKSTP_IN0/1_B is not power management.........................................................................1659 22.6.1.3 Dynamic power management ................................................................................................1659 22.6.1.4 Shutting down unused blocks................................................................................................1659 22.6.1.5 Software-controlled power-down states.................................................................................1660 22.6.1.5.1 Doze mode......................................................................................................1660 22.6.1.5.2 Nap mode........................................................................................................1660 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 58 Freescale Semiconductor, Inc. Section number Title Page 22.6.1.5.3 Sleep mode......................................................................................................1661 22.6.1.6 Power management control fields..........................................................................................1661 22.6.1.7 Power-down sequence coordination......................................................................................1662 22.6.1.8 Interrupts and power management.........................................................................................1663 22.6.1.8.1 Interrupts and power management controlled by MSR[WE].........................1664 22.6.1.8.2 Interrupts and power management controlled by POWMGTCSR.................1664 22.6.1.9 Snooping in power down modes............................................................................................1665 22.6.1.10 Software considerations for power management...................................................................1665 22.6.1.11 Requirements for reaching and recovering from sleep state..................................................1665 Chapter 23 Debug Features and Watchpoint Facility 23.1 Introduction...................................................................................................................................................................1667 23.1.1 Overview....................................................................................................................................................1667 23.1.2 Features......................................................................................................................................................1669 23.1.3 Modes of operation....................................................................................................................................1669 23.1.3.1 Memory debug mode (eLBC and DDR)................................................................................1670 23.1.3.2 DDR SDRAM interface debug mode....................................................................................1670 23.1.3.3 Watchpoint monitor modes....................................................................................................1671 23.1.3.4 Trace buffer modes................................................................................................................1671 23.2 Debug external signal description.................................................................................................................................1671 23.2.1 Signals overview........................................................................................................................................1672 23.2.2 Detailed signal descriptions.......................................................................................................................1673 23.2.2.1 Debug signals-details.............................................................................................................1673 23.2.2.2 Watchpoint monitor trigger signals-details............................................................................1674 23.2.2.3 JTAG test signals-details.......................................................................................................1675 23.3 Debug Memory Map/Register Definition.....................................................................................................................1676 23.3.1 Watchpoint monitor control register 0 (debug_WMCR0).........................................................................1677 23.3.2 Watchpoint monitor control register 1 (debug_WMCR1).........................................................................1679 23.3.3 Watchpoint monitor address register (debug_WMAR).............................................................................1680 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 59 Section number Title Page 23.3.4 Watchpoint monitor address mask register (debug_WMAMR)................................................................1680 23.3.5 Watchpoint monitor transaction mask register (debug_WMTMR)...........................................................1681 23.3.6 Watchpoint monitor status register (debug_WMSR).................................................................................1682 23.3.7 Trace buffer control register 0 (debug_TBCR0)........................................................................................1683 23.3.8 Trace buffer control register 1 (debug_TBCR1)........................................................................................1685 23.3.9 Trace buffer address register (debug_TBAR)............................................................................................1686 23.3.10 Trace buffer address mask register (debug_TBAMR)...............................................................................1686 23.3.11 Trace buffer transaction mask register (debug_TBTMR)..........................................................................1687 23.3.12 Trace buffer status register (debug_TBSR)...............................................................................................1688 23.3.13 Trace buffer access control register (debug_TBACR)...............................................................................1689 23.3.14 Trace buffer access data high register (debug_TBADHR)........................................................................1689 23.3.15 Trace buffer access data register (debug_TBADR)...................................................................................1690 23.3.16 Programmed context ID register (debug_PCIDR).....................................................................................1690 23.3.17 Current context ID register (debug_CCIDR).............................................................................................1691 23.3.18 Trigger output source register (debug_TOSR)..........................................................................................1691 23.4 Functional description...................................................................................................................................................1692 23.4.1 Source and target ID..................................................................................................................................1692 23.4.2 DDR SDRAM interface debug..................................................................................................................1694 23.4.2.1 Debug information on debug pins..........................................................................................1694 23.4.2.2 Debug information on ECC pins............................................................................................1694 23.4.3 Local bus interface debug..........................................................................................................................1695 23.4.4 Watchpoint monitor...................................................................................................................................1695 23.4.4.1 Watchpoint monitor performance monitor events.................................................................1696 23.4.5 Trace buffer................................................................................................................................................1696 23.4.5.1 Traced data formats (as a function of TBCR1[IFSEL])........................................................1697 23.5 Initialization .................................................................................................................................................................1698 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 60 Freescale Semiconductor, Inc. Chapter 1 Overview The chip combines dual Power Architecture® e500v2 processor cores with system logic required for networking, wireless infrastructure, and telecommunications applications. 1.1 Overview This document provides an overview of features and functionality of the QorIQ P1020 integrated processor. The P1020 combines dual Power Architecture™ e500v2 processor cores with system logic required for networking, wireless infrastructure, and telecommunications applications. The P1020 offers an excellent combination of protocol and interface support including dual high-performance CPU cores, a large L2 cache, a DDR2/DDR3 memory controller, three enhanced three-speed Ethernet controllers, two USB 2.0 interfaces (USB1 and USB2), and two PCI Express controllers. The device also supports the IEEE 1588™ precision time protocol for network synchronization over Ethernet. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 61 Overview 1.1.1 Block diagram The figure below shows the major functional units within the P1020 . Figure 1-1. P1020/P1011 block diagram 1.1.2 Critical performance parameters The critical performance parameters are as follows: • e500v2 core frequency of up to 800 MHz • 45-nm SOI process technology • 32-bit DDR2/DDR3 SDRAM memory controller with ECC support • Supply voltage for core/platform: 1.0 V • Operating junction temperature (Tj) range: 0-125°C and -40-125°C (industrial specification) • 31 x 31 mm 689-pin WB-TePBGA II (wire bond temperature-enhanced plastic BGA) 1.1.3 Chip-level features Key features include: P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 62 Freescale Semiconductor, Inc. Chapter 1 Overview • Dual (P1020) or single (P1011) high-performance Power Architecture e500v2 cores • 36-bit physical addressing • Double-precision floating-point support • 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache for each core • 533 MHz to 800 MHz core clock frequency • 256-Kbyte L2 cache with ECC, also configurable as SRAM and stashing memory • Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs) • TCP/IP acceleration and classification capabilities • IEEE 1588 support • Lossless flow control • MII, RMII, RGMII and SGMII support • High-speed interfaces (not all available simultaneously): • Four SerDes lanes running at 2.5 GHz (multiplexed across controllers) • Up to two PCI express interfaces (two x1 or one x1/x2/x4) • Two SGMII interfaces • Two high-speed USB controllers (USB 2.0) • Host and device support • Enhanced host controller interface (EHCI) • ULPI interface to PHY • One dedicated USB interface, one multiplexed with the local bus • Enhanced secure digital host controller (SD/MMC) • Serial peripheral interface • Integrated security engine (SEC 3.3.2) • Crypto algorithm support includes 3DES, AES, MD5/SHA, RSA/ECC, and FIPS deterministic RNG • Single pass encryption/message authentication for common security protocols (IPsec, SSL, SRTP, and WiMax) • XOR acceleration • 16-/32-bit DDR2/DDR3 SDRAM memory controller with ECC support • Programmable interrupt controller (PIC) compliant with Open-PIC standard • Four-channel DMA controller • DUART, timers and two I2C controllers • Enhanced local bus controller (eLBC) • TDM interface supporting up to 128 channels • 16 general-purpose I/O signals These features are described in greater detail in subsequent sections. NOTE This device is also available without a security engine. All specifications other than those relating to security apply to the non-security version exactly as described in this document. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 63 P1020 Application examples 1.2 P1020 Application examples The following section provides block diagrams of different applications. The P1020 is a very flexible device and can be configured to meet many system application needs. Both cores can operate in a symmetric multiprocessing mode to achieve higher performance, or they can run independent operating systems, each performing separate tasks. This flexibility enables application developers to assign distinct processing resources to distinct tasks that need guaranteed performance. For example, one core can manage a data plane and the other a control plane. The value proposition of a dual-core device is further enhanced by a high degree of peripheral integration of system controllers such as DDR. A device with faster internal buses can entirely replace the system controller where a discrete processor without integration was used previously. 1.2.1 Dual-core device application There are two main ways to map operating systems to the two cores: • Symmetric multiprocessing • Cooperative asymmetric multiprocessing • Two copies of the same OS that are non-SMP enabled • Two separate operating systems The figure below shows how to use an integrated dual-core device. A line card uses an ASIC or network processing unit (NPU) for the data path. The ASIC/NPU manages user interfaces on the faceplate on the left as well as the interface to the backplane on the right. The dual-core device is responsible for the control plane. The two cores can operate in an SMP configuration, or two separate operating systems can be used for separate control plane tasks. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 64 Freescale Semiconductor, Inc. Chapter 1 Overview Figure 1-2. Integrated dual core device application The lower line card shows that the eTSEC interfaces are attached to faceplate connectors and the PCI Express block is connected to the backplane switch fabric. The CPUs handle both the control and data plane in a variety of configurations. Two popular alternatives split functionality directionally (one core per direction) or split functionality vertically (one core handling the data plane, one core handling the control plane). At the right of the switch fabric is an example service card, which is easily added to a system to add new features without replacing all the line cards with upgraded ASICs. One service card supports a new feature set in a centralized scheme, receiving traffic from all line cards, so the high performance of a dual-core device is required. The PCI Express port connects to the fabric, and the eTSECs implement a management interface. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 65 P1020 Application examples 1.2.2 High-performance communication system The figure below shows this device as part of a high-end network card used in a system area network that is enabled by PCI Express. Figure 1-3. High-performance communication system P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 66 Freescale Semiconductor, Inc. 1.2.3 RAID controller application Chapter 1 Overview The figure below shows the device in a redundant array of independent disks (RAID) controller application. Figure 1-4. RAID controller application using P1020 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 67 P1020 Application examples 1.2.4 SMB gateway application The figure below shows a multiservice router or business gateway targeting small-tomedium business customer premise equipment. The solution enables complete secure data, voice, and wireless communications services in a single easy-to-manage platform. Figure 1-5. SMB multiservice gateway example P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 68 Freescale Semiconductor, Inc. 1.2.5 WLAN access point application Chapter 1 Overview The figure below shows a high performance WLAN access point application where the CPU provided the complete data and control path processing needs for multiple MAC/ radio interfaces. This device is ideally suited for this application with its high performance system interfaces and best-in-class performance per watt. Figure 1-6. WLAN access point example 1.3 Architecture overview This section contains a high-level view of the device architecture. 1.3.1 e500v2 cores and memory unit This device contains two high-performance 32-bit e500v2 cores that implement Power Architecture technology. In addition to 36-bit physical addressing, this version of the e500 core includes: • SPE double-precision floating-point instruction set using 64-bit operands • SPE embedded vector and scalar single-precision floating-point instruction set using 32- or 64-bit operands • 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 69 Architecture overview The device also contains 256 Kbytes of L2 cache/SRAM, as follows: • Eight-way set-associative cache organization with 32-byte cache lines • Flexible configuration (can be configured as part cache, part SRAM) • External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). • SRAM features include the following: • I/O devices access SRAM regions by marking transactions as snoopable (global). • Regions can reside at any aligned location in the memory map. • Byte-accessible ECC uses read-modify-write transaction accesses for smaller- than-cache-line accesses. 1.3.2 e500 coherency module (ECM) and address map The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus between the e500v2 cores and the integrated L2 cache in order to maintain coherency across local cacheable memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be routed or dispatched to target modules on the device. This device supports a flexible 36-bit physical address map. Conceptually, the address map consists of local space and external address space. The local address map is supported by twelve local access windows that define mapping within the local 36-bit (64-Gbyte) address space. The device can be made part of a larger system address space through the mapping of translation windows. This functionality is included in the address translation and mapping units (ATMUs). Both inbound and outbound translation windows are provided. The ATMUs allows the device to be part of larger address maps such as that of PCI Express. 1.3.3 Integrated security engine (SEC 3.3.2) The SEC is a modular and scalable security core optimized to process all the algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, IEEE 802.11i®, IEEE 802.16® (WiMAX), and IEEE 802.1AE® Std. (MACSec). Although it is not a protocol processor, the SEC is designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of the data. The version of the SEC used in this device is specifically capable of performing single-pass security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 70 Freescale Semiconductor, Inc. SEC features include the following: Chapter 1 Overview • Compatible with code written for the Freescale MPC8548E, MPC8555E, and MPC8541E devices • XOR engine for parity checking in RAID storage applications • Four crypto channels, each supporting multi-command descriptor chains • Cryptographic execution units: • PKEU-public key execution unit • DEU-data encryption standard execution unit • AESU-advanced encryption standard unit • MDEU-message digest execution unit • CRCU-cyclical redundancy check unit • RNGU-random number generator For more information, see Security Engine (SEC) 3.3.2 Engineering Bulletin (EB748). 1.3.4 Enhanced three-speed Ethernet controllers This device has three on-chip enhanced three-speed Ethernet controllers (eTSECs). The eTSECs incorporate a media access control (MAC) sublayer that supports 10- and 100Mbps and 1-Gbps Ethernet/802.3 networks with MII, RMII, SGMII and RGMII physical interfaces. The eTSECs support programmable CRC generation and checking, RMON statistics, and jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache to speed classification or other frame processing. They are designed to comply with IEEE Std. 802.3™, 802.3u, 802.3x, 802.3z, 802.3ac, and 802.3ab. The buffer descriptors are based on the MPC8540 three-speed Ethernet controller programming model. Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with minimal change. Some of the key features of these controllers include: • Flexible configuration for multiple PHY interface configurations. The table below lists available configurations. Table 1-1. eTSEC configuration options1 • MII • RMII • RGMII eTSEC1 • SGMII eTSEC2 • RMII • RGMII • SGMII eTSEC3 1. The parallel interfaces must use the same voltage. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 71 Architecture overview • TCP/IP acceleration and QoS features: • IP v4 and IP v6 header recognition on receive • IP v4 header checksum verification and generation • TCP and UDP checksum verification and generation • Per-packet configurable acceleration • Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS stacks, and ESP/AH IP-security headers • Transmission from up to eight physical queues • Reception to up to eight physical queues • Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex): • IEEE Std. 802.3 full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE frame generation and recognition) • IEEE Std. 802.1 virtual local area network (VLAN) tags and priority • VLAN insertion and deletion • Per-frame VLAN control word or default VLAN for each eTSEC • Extracted VLAN control word passed to software separately • Programmable Ethernet preamble insertion and extraction of up to 7 bytes • MAC address recognition • Ability to force allocation of header information and buffer descriptors into L2 cache • Interrupt virtualization • Each ring mappable to one of two separate groups for interrupt and BD management; each group associated by software with a CPU. • Separate address spaces per group and for MDIO • Interrupt coalescing controls per ring in multi-group mode • Modified Weighted Round-Robin Queuing (MWRR) • Advanced hashing logic 1.3.5 Universal serial bus (USB) 2.0 controllers The two USB 2.0 controllers (USB1 and USB2) provide point-to-point connectivity complying with the Universal Serial Bus Revision 2.0 Specification. The USB controllers can be configured to operate as a stand-alone host, stand-alone device, or both host and device functions operating simultaneously. The host and device functions are both configured to support the following types of USB transfers: • Bulk • Control • Interrupt • Isochronous P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 72 Freescale Semiconductor, Inc. Other controller features are as follows: Chapter 1 Overview • Supports USB dual-role operation and can be configured as host or device • Supports operation as a stand-alone USB device • Supports one upstream facing port • Supports six programmable USB endpoints • Supports operation as a stand-alone USB host controller • Supports USB root hub with one downstream-facing port • Enhanced host controller interface (EHCI) compatible • Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations • Supports external PHY with UTMI+ low-pin interface (ULPI) 1.3.6 Enhanced secure digital host controller The enhanced secure digital host controller (eSDHC) provides an interface between the host system and SD/MMC cards. The eSDHC acts as a bridge, passing host bus transactions to SD/MMC cards by sending commands and performing data accesses to or from the cards. It handles SD/MMC protocols at the transmission level. Booting from onchip ROM is supported through the eSDHC, as described in eSDHC boot. The eSDHC includes the following features: • SD bus clock frequency up to 50 MHz • Supports 1-/4-bit SD mode, 1-/4-bit MMC modes • Up to 200 Mbps data transfer for SD/MMC cards using 4 parallel data lines • Supports single- and multi-block read and write • Supports write protection switch for write operations • Supports synchronous and asynchronous abort • Supports pause during the data transfer at a block gap • Supports Auto CMD12 for multi-block transfer • Host can initiate non-data transfer commands while the data transfer is in progress • Embodies a fully configurable 128 x 32-bit FIFO for read/write data • Supports internal DMA capabilities 1.3.7 Serial peripheral interface (SPI) The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC family devices, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 73 Architecture overview The SPI is a full-duplex, synchronous, character-oriented channel that supports a fourwire interface (receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an independent baud-rate generator, and a control unit. This device also has the ability to boot from an SPI serial flash device. The SPI receiver and transmitter each have a FIFO of 32 bytes to support more efficient transfers to and from SPI devices. The SPI interface supports RapidS for Atmel devices as well as Winbond devices dual read commands; in this mode the SPI uses two bits in parallel for reads. 1.3.8 DDR SDRAM controller This device supports DDR2 and DDR3 SDRAM. The memory interface controls main memory accesses and provides for a maximum of 8 Gbytes of main memory. The device supports a variety of SDRAM configurations. SDRAM banks can be built using directly-attached memory devices. Sixteen multiplexed address signals provide for device densities from 32 Mbits to 4 Gbits. Two chip select signals support up to two banks of memory. The device supports bank sizes from 32 Mbytes to 4 Gbytes. Five data masks (MDM[0:3], MDM8) are used to provide byte selection for memory bank writes. The device can be configured to retain the currently active SDRAM page for pipelined burst accesses. Page mode support of up to 32 simultaneously open pages can dramatically reduce access latencies for page hits. Depending on the memory system design and timing parameters, using page mode can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active page. Using ECC, the device detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble. The device can invoke a level of system power management by asserting the MCKE SDRAM signal on-the-fly to put the memory into a low-power sleep mode. The device offers both hardware and software options to support battery-backed main memory. In addition, the DDR controller offers an initialization bypass feature which system designers may use to prevent re-initialization of main memory during system power-on following abnormal shutdown. 1.3.9 High-speed I/O interfaces This device supports the SGMII and PCI Express high-speed I/O interface standards. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 74 Freescale Semiconductor, Inc. Chapter 1 Overview 1.3.9.1 PCI Express interfaces This device supports two PCI Express interfaces that are compatible with the PCI Express Base Specification Revision 1.0a. They are configurable at boot time to act as either root complex or endpoint. The physical layer of the PCI Express interface operates at a transmission rate of 2.5 Gbaud (data rate of 2.0 Gbps) per lane. The theoretical unidirectional peak bandwidth is 2 Gbps per lane. Receive and transmit ports operate independently, resulting in an aggregate theoretical bandwidth of 4 Gbps per lane. Other features of the PCI Express interface include: • Supports two PCI Express interfaces with up to x4 link width • Both 32- and 64-bit addressing and 256-byte maximum payload size • Full 64-bit decode with 36-bit wide windows 1.3.9.2 SGMII The serial gigabit media independent interface (SGMII) is a high-speed interface linking the Ethernet controller with an Ethernet PHY. SGMII uses differential signaling for electrical robustness. Only four signals are required: receive data and its inverse, and send data and its inverse. No clock signals are required. 1.3.9.3 High-speed interface multiplexing The table below shows the supported high-speed interface configurations. The desired configuration must be selected at power-on reset. Table 1-2. Supported high-speed interface combinations Lanes 0 1 2 PEX1: x1 off off PEX1: x4 PEX1: x1 PEX2: x1 SGMII2 PEX1: x2 SGMII2 3 off SGMII3 SGMII3 Gbaud Lane0/Lane1 Lane2/Lane3 2.5 - 2.5 2.5 1.25 2.5 1.25 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 75 Architecture overview 1.3.10 Programmable interrupt controller (PIC) The PIC implements the logic and programming structures of the OpenPIC architecture, providing for external interrupts (with fully nested interrupt delivery), message interrupts, internal-logic driven interrupts, and global high-resolution timers. Up to 16 programmable interrupt priority levels are supported. The PIC can be bypassed to allow use of an external interrupt controller. 1.3.11 Time division multiplexing (TDM) interface The TDM interface supports the following features: • Independent receive and transmit with dedicated data, clock, and frame sync line • Separate or shared RCK and TCK whose source can be either internal or external • Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses • Up to 128 time slots, where each slot can be programmed to be active or inactive • 8- or 16-bit word widths • The TDM transmitter sync signal (TFS), transmitter clock signal (TCK), and receiver clock signal (RCK) can be configured as either input or output • Frame sync and data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock • Frame sync can be programmed as active low or active high • MSB or LSB first support 1.3.12 DMA, I2C, DUART, and enhanced local bus controller This device provides an integrated four-channel DMA controller, which can transfer data between any of its I/O or memory ports or between two devices or locations on the same port. The DMA controller can be used as follows: • To chain (both extended and direct) through local memory-mapped chain descriptors. • To handle misaligned transfers as well as stride transfers and complex transaction chaining. • To specify local attributes such as snoop and L2 write stashing. There are two I2C controllers. These synchronous, multimaster buses can be connected to additional devices for expansion and system development. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 76 Freescale Semiconductor, Inc. Chapter 1 Overview The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550 programming models. Both the transmitter and receiver support 16-byte FIFOs. The enhanced local bus controller (eLBC) port allows connection with a wide variety of external memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be programmed separately to access different types of devices. The general-purpose chip select machine (GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The user programmable machine (UPM) can be programmed to interface to synchronous devices or custom ASIC interfaces. The NAND Flash control machine (FCM) further extends interface options. Each chip select can be configured so that the associated chip interface can be controlled by the GPCM, UPM, or FCM controller. All may exist in the same system. The local bus controller supports the following features: • Multiplexed 26-bit address and data bus operating up to 83 MHz • Eight chip selects support eight external slaves • Up to eight-beat burst transfers • 16- and 8-bit port sizes controlled by on-chip memory controller • Three protocol engines available on a per-chip-select basis • Parity support • Default boot ROM chip select with configurable bus width (8 or 16 bits) • Supports zero-bus-turnaround (ZBT) RAM • FCM supports NAND Flash, GPCM supports NOR Flash 1.3.13 Device boot locations This device may be configured to boot using one of the following interfaces: • DDR2/DDR3 memory controller • Any PCI Express interface • Enhanced local bus interface (using the GPCM or FCM) • SPI Flash • SD/MMC Flash 1.3.14 Boot sequencer This device provides a boot sequencer that uses the I2C1 interface to access an external serial ROM and loads the data into the device's configuration registers. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 77 Architecture overview The boot sequencer is enabled by a configuration pin sampled at the negation of the devices's hardware reset signal. If enabled, the boot sequencer holds the processor cores in reset until the boot sequence is complete. If the boot sequencer is not enabled, the processor cores exit reset and fetches boot code in default configurations. 1.3.15 System performance monitor The performance monitor facility supports eight 32-bit counters that can count up to 512 counter-specific events. It supports duration and quantity threshold counting and a burstiness feature that permits counting of burst events with a programmable time between bursts. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 78 Freescale Semiconductor, Inc. Chapter 2 Memory Map This chapter describes the mechanisms that define the device memory map-the local access windows (LAWs), the address translation and mapping units (ATMUs), and the configuration, control, and status registers (CCSRs). 2.1 Overview This chapter describes the mechanisms that define the device memory map-the local access windows (LAWs), the address translation and mapping units (ATMUs), and the configuration, control, and status registers (CCSRs). There are several address domains within the device, including the following: • Logical, virtual, and physical (real) address spaces within the e500 core • Internal local address space • Internal configuration, control, and status register (CCSR) address space • External memory, I/O, and configuration address spaces of the PCI Express link The MMU in the e500 core handles translation of logical (effective) addresses into virtual addresses and ultimately to the physical addresses for the local address space. The local address map refers to the physical 36-bit address space seen by the e500 core as it accesses memory and I/O space. The DMA engines also see this same local address map. All memory controlled by the DDR and local bus controllers exists in this address map, as do all memory-mapped configuration, control, and status registers (CCSRs). The local address map is defined by a set of twelve local access windows (LAWs). Each of these windows maps a region of the local address space to a specified target interface, such as the DDR controller, enhanced local bus controller, PCI Express controller, or other targets. The internal configuration, control, and status registers (CCSRs) for all the functional blocks are located in the local memory space at a specific CCSR window. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 79 Configuration, control, and status registers If the target mapping performed by the local access windows directs the transaction to one of the external interfaces (as an outbound read or write), the transaction is then mapped into that interface's external address space by address translation and mapping unit (ATMU) windows associated with the external interface. Outbound ATMUs perform the mapping from the local 36-bit address space to the address space of external interface; inbound ATMU windows perform the address translation from the external address space to the local address space. 2.2 Configuration, control, and status registers All of the memory-mapped configuration, control, and status registers (CCSRs) in this device are contained within a 1-Mbyte address region. To allow for flexibility, the CCSR block is relocatable in the local address space. The local address map location of the CCSR block is controlled by the configuration, control, and status base address register (CCSRBAR); see Configuration, control, and status registers base address register (reset_CCSRBAR). The default address for CCSRBAR is 0x0_FF70_0000 (or 4 Gbytes - 9 Mbytes). No address translation is performed for CCSR space, so there is no associated translation address register. The CCSR window is always enabled with a fixed size of 1 Mbyte; no other attributes are attached, so there is no associated window attribute register. NOTE The CCSR window must not overlap a LAW that maps to the DDR controller. Otherwise, undefined behavior occurs. An example of a top-level memory map with the default location of the configuration, control, and status registers is shown in the figure below. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 80 Freescale Semiconductor, Inc. Chapter 2 Memory Map Figure 2-1. CCSR space 2.2.1 Accessing CCSR memory from the local processor When the local e500 core is used to configure CCSR space, the CCSR memory space should typically be marked as cache-inhibited and guarded. In addition, many configuration registers affect accesses to other memory regions; therefore writes to these registers must be guaranteed to have taken effect before accesses are made to the associated memory regions. To guarantee that the results of any sequence of writes to configuration registers are in effect, the final configuration register write should be chased by a read of the same register, and that should be followed by a SYNC instruction. Then accesses can safely be made to memory regions affected by the configuration register write. 2.2.2 Accessing CCSR memory from external masters In addition to being accessible by the e500 processor, the CCSRs are accessible from the external PCI Express interface. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 81 Configuration, control, and status registers This allows external masters on the I/O ports to configure the device. External masters do not need to know the location of the CCSR memory in the local address map. Rather, they access the CCSR region of the local memory map through a window defined by a register in the interface's programming model that is accessible to the external master from its external memory map. The PCI Express base address for accessing the local CCSR memory is selectable through the PCI Express configuration and status register base address register (PEXCSRBAR), at offset 0x10. An external PCI Express master sets this register by performing a PCI Express configuration cycle to this device. Subsequent memory accesses by a PCI Express master to the PCI Express address range indicated by PEXCSRBAR are translated to the local CCSR address indicated by the current setting of CCSRBAR. 2.2.3 Organization of CCSR space As shown in Figure 2-1, the CCSR space is divided into the following groups-general utilities, programmable interrupt controller (PIC), and device-specific utilities registers. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 82 Freescale Semiconductor, Inc. 2.2.3.1 General utilities registers Chapter 2 Memory Map The general utilities registers are the functional block-specific registers that occupy the first 256 Kbytes of CCSR space. Each functional block is allocated a 4-Kbyte address range for its registers within the general utilities space. The figure below shows the layout of the general utilities registers. Figure 2-2. General utilities register map within CCSR space P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 83 Configuration, control, and status registers 2.2.3.1.1 General utilities register organization The figure below shows the typical organization of registers inside the 4-Kbyte register space allocated to an individual functional block. Starting at the block base address, the first 3 Kbytes are available for general registers. If the functional block has associated ATMUs, the next 512 bytes are dedicated to address translation and mapping registers. If a functional block has error management registers, they are typically placed starting at offset 0xE00 from the block base address, and any debug registers are typically placed in the final 256 bytes of the block's register space starting at offset 0xF00. Figure 2-3. General utility register block NOTE Refer to detailed register descriptions for each functional block for exact locations, sizes, and access requirements. 2.2.3.2 Programmable interrupt controller registers The programmable interrupt controller (PIC) follows the OpenPIC programming model which requires a larger register address space than the 4 Kbytes allocated to other blocks within the general utilities space. For this reason, the PIC is allocated the second 256 Kbytes of CCSR space, beginning at offset 0x4_0000 from CCSRBAR. The layout of the PIC register space is shown in the figure below. Note that the PIC registers should only be accessed with 32-bit accesses. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 84 Freescale Semiconductor, Inc. Chapter 2 Memory Map Figure 2-4. PIC register map within CCSR space 2.2.4 Device-specific utilities registers The device-specific utilities registers control functions that are not particular to a functional unit but to the device as a whole; they occupy the highest 256 Kbytes of CCSR space. The device-specific utilities registers consist of power management, performance monitors, and device-wide debug utilities. The figure below shows the layout of the device-specific utilities registers. Note that the device-specific registers are accessible with 32-bit accesses only. Transactions of a size other than 32-bits are considered programming errors and the operation is undefined. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 85 Configuration, control, and status registers Figure 2-5. P1020 Device-specific register map within CCSR space 2.2.5 CCSR address map The full register address of any CCSR is comprised of the CCSR window base address, specified in CCSRBAR (default address 0x0_FF70_0000), plus the functional block base address, plus the specific register's offset within that block. The table below shows the location of the functional block base addresses for the entire CCSR space. Cross-references are provided to the CCSR maps for each individual block. Table 2-1. CCSR block base address map Block Base Address (Hex) Block General Utilities (0x0_0000-0x3_FFFF) 0x0_0000- 0x0_0FFF Local configuration control Local access window 0x0_1000- 0x0_1FFF ECM (e500 coherency module) CCSR Map ECM memory map/ - register definition Local Access Window Registers ECM memory map/ - register definition Table continues on the next page... Comments P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 86 Freescale Semiconductor, Inc. Chapter 2 Memory Map Table 2-1. CCSR block base address map (continued) Block Base Address (Hex) Block CCSR Map Comments 0x0_2000- 0x0_2FFF DDR memory controller 0x0_3000- 0x0_3FFF I2C controllers DDR memory map/ register definition I2C memory map/ register definition - I2C controller 1: 0x0_3000 I2C controller 2: 0x0_3100 0x0_4000- 0x0_4FFF DUART DUART memory map/ UART 0: 0x0_4500 register definition UART 1: 0x0_4600 0x0_5000- 0x0_5FFF Enhanced local bus controller Enhanced Local Bus - (eLBC) Controller (eLBC) Memory Map 0x0_6000- 0x0_6FFF Reserved - - 0x0_7000- 0x0_7FFF Enhanced serial peripheral Enhanced serial - interface (eSPI) peripheral interface (eSPI) memory map 0x0_8000- 0x0_8FFF Reserved - - 0x0_9000- 0x0_9FFF PCI Express controller 2 PCI Express memory- mapped registers 0x0_A000- 0x0_AFFF PCI Express controller 1 PCI Express memory- mapped registers 0x0_B000- 0x0_EFFF Reserved - - 0x0_F000- 0x0_FFFF GPIO GPIO memory map/ register definition 0x1_0000- 0x1_5FFF Reserved - - 0x1_6000- 0x1_61FF TDM TDM_SB memory map/ TDM configuration (0x1_6000-0x1_60FF) register definition TDM data (0x1_6100-0x1_617F) TDM_AHB memory map/register definition 0x1_6200- 0x1_FFFF Reserved - - 0x2_0000- 0x2_0FFF L2 Cache L2_Cache memory - map/register definition 0x2_1000- 0x2_1FFF DMA controller DMA controller memory DMA 0: 0x2_1100 map DMA 1: 0x2_1180 DMA 2: 0x2_1200 DMA 3: 0x2_1280 General Status: 0x2_1300 0x2_2000-0x2_3FFF USB controllers (dual role) USB memory map/ register definition USB 1: 0x2_2000 USB 2: 0x2_3000 0x2_4000- 0x2_6FFF eTSEC MDIO eTSEC memory map/ register definition eTSEC 1 MDIO: 0x2_4000 eTSEC 2 MDIO: 0x2_5000 eTSEC 3 MDIO: 0x2_6000 0x2_7000- 0x2_BFFF Reserved - - 0x2_C000- 0x2_DFFF TDM DMA controller (DMAC) TDM_DMAC memory map/register definition Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 87 Local access windows Table 2-1. CCSR block base address map (continued) Block Base Address (Hex) Block CCSR Map Comments 0x2_E000- 0x2_EFFF eSDHC Enhanced Secure - Digital Host Controller (eSDHC) Memory Map 0x2_F000- 0x2_FFFF Reserved - - 0x3_0000- 0x3_FFFF Security Engine (SEC) See Security Engine (SEC) 3.3.2 Engineering Bulletin (EB748) Programmable Interrupt Controller (PIC) (0x4_0000-0x7_FFFF) 0x4_0000- 0x7_FFFF PIC PIC memory map/ register definition Global registers: 0x4_0000 Interrupt source registers: 0x5_0000 Processor (per-CPU) registers: 0x6_0000 eTSEC (0xB_0000-0xB_6FFF) 0xB_0000- 0xB_2FFF eTSEC group 0 eTSEC memory map/ register definition eTSEC 1 group 0: 0xB_0000 eTSEC 2 group 0: 0xB_1000 eTSEC 3 group 0: 0xB_2000 0xB_3000- 0xB_3FFF Reserved - - 0xB_4000- 0xB_6FFF eTSEC group 1 eTSEC memory map/ register definition eTSEC 1 group 1: 0xB_4000 eTSEC 2 group 1: 0xB_5000 eTSEC 3 group 1: 0xB_6000 Device-Specific Utilities (0xE_0000-0xF_FFFF) 0xE_0000- 0xE_0FFF Global utilities GUTS Memory Map/ Register Definition 0xE_1000- 0xE_1FFF Performance monitor PERFMON Memory Map/Register Definition 0xE_2000- 0xE_2FFF Debug/Watchpoint monitor and trace buffer Debug Memory Map/ Register Definition 0xE_3000- 0xE_30FF SerDes control GUTS Memory Map/ Register Definition 0xE_3100- 0xE_FFFF Reserved - - 0xF_0000- 0xF_FFFF Internal boot ROM 1 - - 1. Even though it is allocated 64 Kbytes in the memory space, only 8 Kbytes of internal boot ROM is physically implemented. This is located at the upper 8 Kbytes of the allocated 64 Kbyte address space, from CCSR offset 0xF_E000 to 0xF_FFFF. 2.3 Local access windows The local address map is defined by a set of twelve local access windows (LAWs). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 88 Freescale Semiconductor, Inc. Chapter 2 Memory Map Each of these windows maps a programmable 4-Kbyte to 32-Gbyte region of the local 36-bit address space to a specified target interface, such as the DDR controller, local bus controller, PCI Express controllers, or other targets. This allows the internal interconnections of the device to route a transaction from its source to the proper target. Each LAW is defined by a base address register which specifies the starting address for the window, and an attribute register which specifies whether the mapping is enabled, the size of the window, and the target interface for that window. Note that the LAWs do not perform any address translation, and therefore, there are no corresponding translation address registers. The local access window registers exist as part of the local access block in the general utilities registers in CCSR space. With the exception of configuration space (mapped by CCSRBAR) and the default boot ROM space, all addresses used by the system must be mapped by an LAW. This includes addresses that are mapped by inbound ATMU windows. Thus, target mappings of the local access windows and the inbound ATMU windows must be consistent. 2.3.1 Precedence of local access windows If two or more LAWs overlap, the lower numbered window takes precedence. For instance, consider two LAWs, set up as shown in the table below. Table 2-2. Overlapping local access windows LAW 1 2 Base Address 0x0_7FF0_0000 0x0_0000_0000 Size 1 Mbyte 2 Gbytes Target Interface 0b00100 (local bus controller-LBC) 0b01111 (DDR controller) In this case, LAW 1 governs the mapping of the 1-Mbyte region from 0x0_7FF0_0000 to 0x0_7FFF_FFF, even though the window described in LAW 2 also encompasses that memory region. 2.3.2 Configuring local access windows Once a local access window is enabled, it should not be modified while any device in the system may be using the window. Neither should a new window be used until the effect of the write to the window is visible to all blocks that use the window. This can be guaranteed by completing a read of the last LAW configuration register before enabling any other devices to use the window. For example, if LAWs 0-3 are being configured in order during the initialization process, P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 89 Local access windows the last write (to LAWAR3) should be followed by a read of LAWAR3 before any devices try to use any of these windows. If the configuration is being performed by the e500 core, the read of LAWAR3 should be followed by an isync instruction. 2.3.3 Distinguishing local access windows from other mapping functions It is important to distinguish between the mapping function performed by the LAWs and the additional mapping functions that occur at the target interfaces. The LAWs define how a transaction is routed through the device's internal interconnects from the transaction's source to its target. After the transaction has arrived at its target interface, that interface controller may perform additional mapping. For instance, the DDR controller has chip select registers that map a memory request to a particular external device. Similarly, the local bus controller has base registers that perform a similar function. The PCI Express interface has an outbound address translation and mapping unit (ATMU) that maps the local address into an external address space. These other mapping functions are configured by programming the CCSRs of the individual interfaces. Note that there is no need to have a one-to-one correspondence between LAWs and chip select regions or outbound ATMU windows. A single LAW can be further decoded to any number of chip selects or to any number of outbound ATMU windows at the target interface. 2.3.4 Illegal interaction between local access windows and DDR chip selects If a local access window maps an address to an interface other than the DDR controller, there should not be a valid chip select configured for the same address in the DDR controller. Because DDR chip select boundaries are defined by a beginning and ending address, it is easy to define them so that they do not overlap with LAWs that map to other interfaces. 2.3.5 Local address map example The figure below shows what a typical local address map might look like. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 90 Freescale Semiconductor, Inc. Chapter 2 Memory Map Figure 2-6. Local address map example The table below shows the corresponding set of LAW settings for the example shown in the figure above. Table 2-3. Local access window settings example Window 0 1 2 3 4 5-9 Base Address 0x0_0000_0000 0x0_8000_0000 0x0_A000_0000 0x0_B000_0000 0x0_C000_0000 Unused Size 2 Gbytes 1 Mbyte 256 Mbytes 256 Mbytes 256 Mbytes Target Interface DDR controller Enhanced local bus controller (eLBC)-FCM PCI Express 1 PCI Express 2 Enhanced local bus controller (eLBC)-DSP TRGT 0b01111 0b00100 0b00010 0b00001 0b00100 In this example, it is not necessary to use a LAW to specify the location of the boot ROM. See Boot page translation, for more information. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 91 Local Access Window Registers 2.4 Local Access Window Registers The local access window registers are accessed by reading and writing to an address comprised of the base address (specified in the CCSRBAR), plus the block base address, plus the offset of the specific register to be accessed. For the LAWs, the block base address is 0x0_0000. Note that all LAW registers should only be accessed a word (4-bytes) at a time. The table below shows the memory map for the LAW registers. LAW memory map Offset address (hex) C08 C10 C28 C30 C48 C50 C68 C70 C88 C90 CA8 CB0 CC8 CD0 CE8 CF0 D08 D10 D28 D30 Register name Width (in bits) Access Reset value Local access window n base address register (LAW_LAWBAR0) 32 Local access window n attribute register (LAW_LAWAR0) 32 Local access window n base address register (LAW_LAWBAR1) 32 Local access window n attribute register (LAW_LAWAR1) 32 Local access window n base address register (LAW_LAWBAR2) 32 Local access window n attribute register (LAW_LAWAR2) 32 Local access window n base address register (LAW_LAWBAR3) 32 Local access window n attribute register (LAW_LAWAR3) 32 Local access window n base address register (LAW_LAWBAR4) 32 Local access window n attribute register (LAW_LAWAR4) 32 Local access window n base address register (LAW_LAWBAR5) 32 Local access window n attribute register (LAW_LAWAR5) 32 Local access window n base address register (LAW_LAWBAR6) 32 Local access window n attribute register (LAW_LAWAR6) 32 Local access window n base address register (LAW_LAWBAR7) 32 Local access window n attribute register (LAW_LAWAR7) 32 Local access window n base address register (LAW_LAWBAR8) 32 Local access window n attribute register (LAW_LAWAR8) 32 Local access window n base address register (LAW_LAWBAR9) 32 Local access window n attribute register (LAW_LAWAR9) 32 Table continues on the next page... R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h Section/ page 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 92 Freescale Semiconductor, Inc. Offset address (hex) D48 D50 D68 D70 LAW memory map (continued) Chapter 2 Memory Map Register name Local access window n base address register (LAW_LAWBAR10) Local access window n attribute register (LAW_LAWAR10) Local access window n base address register (LAW_LAWBAR11) Local access window n attribute register (LAW_LAWAR11) Width (in bits) Access Reset value 32 R/W 0000_0000h 32 R/W 0000_0000h 32 R/W 0000_0000h 32 R/W 0000_0000h Section/ page 2.4.1/93 2.4.2/93 2.4.1/93 2.4.2/93 2.4.1 Local access window n base address register (LAW_LAWBARn) The LAWBARn registers define the 24 high-order address bits that fixes the location of each window in the local address space. Note that the minimum size of any LAW is 4 Kbytes, so the 12 lowest-order bits of the base address cannot be specified. The figure below shows the bit fields of the LAWBARn registers. Address: 0h base + C08h offset + (32d × i), where i=0d to 11d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved BASE_ADDR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAW_LAWBARn field descriptions Field 0–7 - 8–31 BASE_ADDR Description This field is reserved. Reserved Identifies the 24 most-significant address bits of the base of local access window n. The specified base address must be aligned to the window size, as defined by LAWARn[SIZE]. 2.4.2 Local access window n attribute register (LAW_LAWARn) The LAWARn registers are used to enable specific local access windows, define their size and specify the target interface. The figure below shows the bit fields of the LAWARn registers. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 93 Local Access Window Registers The target interface for each LAW is specified using the encodings shown in the table below. Note that configuration registers are mapped by the windows defined by CCSRBAR. The CCSR mapping supersedes local access window mappings, so configuration registers do not appear as a target for local access windows. Table 2-7. Target Interface Encodings TRGT 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Target Interface Reserved PCI Express 2 PCI Express 1 Reserved Enhanced local bus (eLBC) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DDR memory controller TRGT 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Target Interface Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Address: 0h base + C10h offset + (32d × i), where i=0d to 11d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W EN Reserved TRGT Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0 EN 1–6 - 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved SIZE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAW_LAWARn field descriptions Enabled Description 0 The local access window n (and all other LAWARn and LAWBARn fields) are disabled. 1 The local access window n is enabled and other LAWARn and LAWBARn fields combine to identify an address range for this window. This field is reserved. Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 94 Freescale Semiconductor, Inc. Field 7–11 TRGT 12–25 - 26–31 SIZE LAW_LAWARn field descriptions (continued) Chapter 2 Memory Map Description Identifies the target interface when a transaction hits in the address range defined by this window. The encodings for TRGT are defined in Table 2-7. This field is reserved. Reserved Identifies the size of the window from the starting address. Window size is 2(SIZE+1) bytes. Example settings: 000000-001010 001011 001100 001101 100010 100011-111111 Reserved 4 Kbytes 8 Kbytes 16 Kbytes 32 Gbytes Reserved 2.5 Address translation and mapping units To facilitate flexibility in defining the address maps for external interfaces such as PCI Express, the device provides address translation and mapping units (ATMUs). The following types of translation and mapping operations are performed by the ATMUs: • Translating the local 36-bit address to an external address space • Translating external addresses to the local 36-bit address space • Assigning attributes to transactions • Mapping a local address to a target interface Outbound address translation and mapping refers to the translation of addresses from the local 36-bit address space to the external address space and attributes of a particular I/O interface. Inbound address translation and mapping refers to the translation of an address from the external address space of an I/O interface to the local address space understood by the internal interfaces of this device. It also refers to the mapping of transactions to a particular target interface and the assignment of transaction attributes. Note that in mapping the transaction to the target interface, an inbound ATMU window performs a function similar to the local access windows. The target mappings created by an inbound ATMU must be consistent with those of the LAWs. That is, if an inbound ATMU maps a transaction to a given local address and a given target, a LAW must also map that same local address to the same target. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 95 Address translation and mapping units 2.5.1 Address translation All of the configuration registers that define an ATMU window's translation and mapping functions follow the same general register format, summarized in the table below. Table 2-43. Format of ATMU window definitions Register Translation address (TAR) Base address (BAR) Window attributes (WAR) Function High-order address bits defining location of the window in the target address space High-order address bits defining location of the window in the initiator address space Window enable, window size, target interface, and transaction attributes The size of the windows must be a power-of-two. To perform a translation or mapping function, the address of the transaction is compared with the base address register of each window. The number of bits used in the comparison is dictated by each window's size attribute. When an address hits a window, if address translation is being performed, the new translated address is created by concatenating the window offset to the translation address. Again, the windows size attribute dictates how many bits are translated. 2.5.2 Outbound ATMUs If the target mapping performed by the local access windows directs the transaction to one of the external interfaces (as an outbound read or write), the transaction is then mapped into that interface's external address space by outbound ATMUs associated with the external interface. The outbound ATMUs perform the mapping from the local 36-bit address space to the address space of PCI Express, which may be much larger than the local space. The outbound ATMUs also map attributes such as transaction type and priority level. The PCI Express controller has four outbound ATMU windows plus a default window. If a transaction's address does not hit any of the four outbound ATMU windows, the translation attributes defined by the default window are used. The default window is always enabled. The PCI Express outbound ATMUs include extended translation address registers so that up to 64 bits of external address space can be supported. See PCI Express outbound ATMUs for a detailed description of the PCI Express outbound ATMU windows. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 96 Freescale Semiconductor, Inc. 2.5.3 Inbound ATMUs Chapter 2 Memory Map The inbound ATMUs perform the address translation from external address spaces to the local address space, attach attributes and transaction types to the transaction, and also map the transaction to its target interface. The PCI Express controller has three general inbound ATMU windows plus a default. See PCI Express inbound ATMUs for a detailed description of the PCI-Express inbound ATMU windows. 2.5.3.1 Illegal interaction between inbound ATMUs and LAWs Since both local access windows and inbound ATMUs map transactions to a target interface, it is essential that they not contradict one another. For example, it is considered a programming error to have an inbound ATMU map a transaction to the DDR memory controller (target interface 0b0_1111) if the resulting translated local address is mapped to the PCI Express interface (target interface 0b0_0000) by a local access window. Such programming errors may result in unpredictable system deadlocks. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 97 Address translation and mapping units P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 98 Freescale Semiconductor, Inc. Chapter 3 Signal Descriptions This chapter describes the external signals. 3.1 General overview This chapter describes the external signals. It is organized into the following sections: • Overview of signals and cross-references for signals that serve multiple functions, including two lists: one by functional block and one alphabetical • List of reset configuration signals • List of output signal states at reset NOTE A bar over a signal name indicates that the signal is active low, such as IRQ_OUT_B (interrupt output). Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as IRQ (interrupt input), are referred to as asserted when they are high and negated when they are low. Internal signals are shown throughout this document as lower case and in italics. For example, sys_logic_clk is an internal signal. These are discussed only as necessary for understanding the external functionality of the device. 3.2 Signals overview The signals are grouped as follows: P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 99 Signals overview • DDR memory interface signals • SerDes/PCI Express/SGMII interface signals • Enhanced three-speed Ethernet Controller (eTSEC) interface signals • Enhanced local bus interface signals • eSDHC interface signals • SPI interface signals • USB interface signals • DMA interface signals • PIC interface signals • DUART interface signals • I2C interface signals • TDM interface signals • System control, general-purpose input/output, power management, and debug signals • Test, JTAG, configuration, and clock signals The figures below illustrate the external signals of the device, showing how the signals are grouped. Refer to the P1020 QorIQ Integrated Processor Hardware Specifications for a pinout diagram showing pin numbers and a listing of all the electrical and mechanical specifications. Note that these figures show multiplexed signals multiple times. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 100 Freescale Semiconductor, Inc. DDR SerDes, PCl Express, SGMII eTSEC1, eTSEC2, eTSEC3 eTSEC1 Chapter 3 Signal Descriptions MDQ[0:31] 32 MECC[0:7] 8 MAPAR_ERR_B 1 1 3 1 MAPAR_OUT MDM[0:3], MDM[8] MDQS[0:3], MDQS8 1 5 1 1 MDQS_B[0:3], MDQS8_B 5 1 MBA[0:2] 5 3 MA[0:15] 4 1 MWE_B MRAS_B 16 1 MCAS_B 1 1 1 MCS_B[0:1] 1 1 MCKE[0:1] MCK[0:3], MCK_B[0:3] 2 2 8 MODT[0:1] 8 1 MDIC[0:1] 2 2 1 1 SD_TX[3:0] SD_TX_B[3:0] SD_RX[3:0] 4 4 SD_RX_B[3:0] 4 1 1 1 SD_REF_CLK SD_REF_CLK_B SD_PLL_TPD SD_PLL_TPA SD_IMP_CAL_TX SD_IMP_CAL_RX 4 1 1 1 1 2 1 1 1 1 1 P1020 1 2 3 TSEC_1588_CLK_IN TSEC_1588_TRIG_IN1 1 1 1 TSEC_1588_TRIG_IN2 TSEC_1588_ALARM_OUT1/cfg_srds_refclk 1 1 1 1 1 TSEC_1588_ALARM_OUT2/cfg_sgmii3 TSEC_1588_CLK_OUT/cfg_ddr_pll0 1 1 1 1 TSEC_1588_PULSE_OUT1/cfg_ddr_pll1 1 2 TSEC_1588_PULSE_OUT2/cfg_ddr_pll2 1 1 EC_GTX_CLK125 1 8 1 TSEC3_TXD3/cfg_tsec1_prtcl1 1 TSEC3_TXD[2:0]/cfg_rom_loc[0:2] 1 3 TSEC1_TXD[3:1]/cfg_io_ports[0:2] 1 1 TSEC1_TXD0/cfg_tsec1_prtcl0 3 1 TSEC1_TX_EN TSEC1_TX_ER/cfg_rom_loc3 1 1 TSEC1_TX_CLK/TSEC1_GTX_CLK125 1 TSEC1_CRS/TSEC3_RX_DV 1 TSEC1_COL/TSEC3_RX_CLK 1 TSEC1_RXD[3:0] 4 TSEC1_RX_DV 1 1 1 1 1 1 1 1 TSEC1_RX_ER 1 1 1 TSEC1_RX_CLK 1 TSEC1_GTX_CLK 1 1 1 4 TSEC3_TXD3/cfg_tsec1_prtcl1 TSEC3_TXD[2:0]/cfg_rom_loc[0:2] TSEC3_TX_EN/cfg_sdhc_cd_pol_sel TSEC3_RX_ER TSEC3_TX_CLK TSEC3_GTX_CLK TSEC3_RXD[3:0] TSEC3_RX_DV/TSEC1_CRS TSEC3_RX_CLK/TSEC1_COL EC_MDC/cfg_tsec_reduce EC_MDIO LAD[0:7]/USB2_D[7:0]/cfg_gpinput[0:7] LAD8/USB2_NXT/cfg_gpinput8 LAD9/USB2_DIR/cfg_gpinput9 LAD10/USB2_STP/cfg_gpinput10 LAD11/USB2_PWRFAULT/cfg_gpinput11 LAD12/USB2_CLK/cfg_gpinput12 LAD13/USB2_PCTL0/cfg_gpinput13 LAD14/USB2_PCTL1/cfg_gpinput14 LAD15/cfg_gpinput15 LDP[0:1] LA16/cfg_cpu1_boot LA17 LA[18:19]/cfg_host-agt[1:2] LA[20:22]/cfg_eng_use[0:2] LA23/cfg_plat_speed LA24/cfg_core0_speed LA25/cfg_core1_speed LA26/cfg_ddr_speed LA27/cfg_cpu0_boot LA28/cfg_sys_speed LA[29:30]/cfg_sys_pll[0:1] LA31/cfg_sys_pll2 LCS_B[0:7] LWE0_B/LFWE_B/LBS0_B/cfg_core1_pll0 LWE1_B/LBS1_B/cfg_host_agt0 LBCTL/cfg_core0_pll0 LALE/cfg_core0_pll1 LGPL0/LFCLE LGPL1/LFALE LGPL2/LOE_B/LFRE_B/cfg_core0_pll2 LGPL3/LFWP_B/cfg_boot_seq0 LGPL4/LGTA_B/LFRB_B/LUPWAIT LGPL5/cfg_boot_seq1 LCLK0 LCLK1 SPI_MOSI SPI_MISO SPI_CLK SPI_CS_B[0:3]/SDHC_DAT[4:7] eTSEC3 Ethernet Mgmnt eLBC SPI Figure 3-1. P1020 signal groupings (1/3) P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 101 Signals overview eSDHC USB1, USB2 DMA PIC PIC/ GPIO GPIO Power Mgmnt SDHC_CMD 1 SDHC_DAT[0:3] 1 1 4 SDHC_DAT[4:7]/SPI_CS_B[0:3] 4 SDHC_CD_B/GPIO8 1 1 1 SDHC_WP/GPIO9 1 1 SDHC_CLK 1 1 1 USB1_D[7:0] 1 8 USB1_NXT 1 1 USB1_DIR 1 USB1_STP 1 1 USB1_PCTL0/GPIO10 1 1 USB1_PCTL1/GPIO11 1 1 USB1_PWRFAULT USB1_CLK 1 1 1 1 1 USB2_D[7:0]/LAD[0:7]/cfg_gpinput[0:7] USB2_NXT/LAD8/cfg_gpinput8 8 USB2_DIR/LAD9/cfg_gpinput9 1 USB2_STP/LAD10/cfg_gpinput10 1 1 1 1 1 USB2_PWRFAULT/LAD11/cfg_gpinput11 1 1 USB2_CLK/LAD12/gpinput12 1 1 USB2_PCTL0/LAD13/gpinput13 1 1 USB2_PCTL1/LAD14/gpinput14 2 1 2 DMA_DREQ0_B DMA_DACK0_B DMA_DDONE0_B 1 1 1 P1020 1 1 1 MCP_B[0:1] UDE_B[0:1] 2 1 IRQ_OUT_B 2 1 IRQ[0:5] 1 1 IRQ6/TDM_RX_CLK 6 1 1 1 IRQ7/GPIO0/TDM_TX_DATA 1 1 IRQ8/GPIO1/TDM_TFS 1 1 IRQ9/GPIO2/TDM_TX_CLK 1 1 IRQ10/GPIO3/TDM_RFS 1 1 IRQ11/GPIO4/TDM_RX_DATA 1 1 GPIO[5:7] 3 1 GPIO8/SDHC_CD_B 1 GPIO9/SDHC_WP 1 1 GPIO10/USB1_PCTL0 1 GPIO11/USB1_PCTL1 1 1 GPIO[12:15] 1 1 4 1 ASLEEP CLK_OUT 1 1 1 2 2 UART_SOUT0/cfg_eng_use[3] UART_SOUT1/cfg_core1_pll1 UART_SIN0 UART_SIN1 UART_CTS0_B UART_CTS1_B UART_RTS0_B/cfg_tsec3_prtcl0 UART_RTS1_B/cfg_tsec3_prtcl1 IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL TDM_RX_CLK/IRQ6 TDM_TX_DATA/GPIO0/IRQ7 TDM_TFS/GPIO1/IRQ8 TDM_TX_CLK/GPIO2/IRQ9 TDM_RFS/GPIO3/IRQ10 TDM_RX_DATA/GPIO4/IRQ11 HRESET_B HRESET_REQ_B SRESET_B CKSTP_IN_B[0:1] CKSTP_OUT_B[0:1] TRIG_IN TRIG_OUT READY_P1/cfg_core1_pll2 MSRCID0/LB MSRCID0/PLL_PER_OUT0 /cfg_elbc_ecc MSRCID1/LB MSRCID1/PLL_PER_OUT1 MSRCID2/LB_MSRCID2/PLL_PER_OUT2 MSRCID3/LB_MSRCID3/PLL_PER_OUT3 MSRCID4/LB_MSRCID4/PLL_UP_DN/ cfg_eng_use[6] MDVAL/LB_MDVAL/PLL_PER_VALID SYSCLK RTC DDRCLK SCAN_MODE_B TEST_SEL_B TCK TDI TDO TMS TRST_B LVDD_VSEL BVDD_VSEL[0:1] CVDD_VSEL[0:1] Dual UART I2C TDM System Control Debug Clock Test JTAG IO VSEL Figure 3-2. P1020 signal groupings (2/3) (continued) P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 102 Freescale Semiconductor, Inc. Config Chapter 3 Signal Descriptions cfg_srds_refclk/TSEC_1588_ALARM_OUT1 cfg_sgmii3/TSEC_1588_ALARM_OUT2 cfg_ddr_pll0/TSEC_1588_CLK_OUT cfg_ddr_pll1/TSEC_1588_PULSE_OUT1 cfg_ddr_pll2/TSEC_1588_PULSE_OUT2 cfg_tsec_reduce/EC_MDC cfg_tsec1_prtcl1/TSEC3_TXD3 cfg_rom_loc[0:2]/TSEC3_TXD[2:0] cfg_io_ports[0:2]/TSEC1_TXD[3:1] cfg_tsec1_prtcl0/TSEC1_TXD0 cfg_rom_loc3/TSEC1_TX_ER cfg_tsec1_prtcl1/TSEC3_TXD3 cfg_rom_loc[0:2]/TSEC3_TXD[2:0] cfg_gpinput[0:7]/LAD[0:7]/USB2_D[7:0] cfg_gpinput8/LAD8/USB2_NXT cfg_gpinput9/LAD9/USB2_DIR cfg_gpinput10/LAD10/USB2_STP cfg_gpinput11/LAD11/USB2_PWRFAULT cfg_gpinput12/LAD12/USB2_CLK cfg_gpinput13/LAD13/USB2_PCTL0 cfg_gpinput14/LAD14/USB2_PCTL1 cfg_core1_pll1/UART_SOUT1 cfg_tsec3_prtcl0/UART_RTS0_B cfg_tsec3_prtcl1/UART_RTS1_B cfg_mem_debug cfg_ddr_debug cfg_io_ports3 cfg_dram_type 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 3 1 1 2 1 1 1 1 P1020 1 3 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 cfg_gpinput[0:7]/USB2_D[7:0]/LAD[0:7] cfg_gpinput8/USB2_NXT/LAD8 cfg_gpinput9/USB2_DIR/LAD9 cfg_gpinput10/USB2_STP/LAD10 cfg_gpinput11/USB2_PWRFAULT/LAD11 cfg_gpinput12/USB2_CLK/LAD12 cfg_gpinput13/USB2_PCTL0/LAD13 cfg_gpinput14/USB2_PCTL1/LAD14 cfg_gpinput15/LAD15 cfg_cpu1_boot/LA16 cfg_host_agt[1:2]/LA[18:19] cfg_plat_speed/LA23 cfg_core0_speed/LA24 cfg_core1_speed/LA25 cfg_ddr_speed/LA26 cfg_cpu0_boot/LA27 cfg_sys_speed/LA28 cfg_sys_pll[0:1]/LA[29:30] cfg_sys_pll2/LA31 cfg_core1_pll0/LWE0_B/LFWE_B/LBS0_B cfg_host_agt0/LWE1_B/LBS1_B cfg_core0_pll0/LBCTL cfg_core0_pll1/LALE cfg_core0_pll2/LFRE_B/LOE_B/LGPL2_B cfg_boot_seq0/LFWP_B/LGPL3 cfg_boot_seq1/LGPL5 cfg_core1_pll2/READY_P1 cfg_elbc_ecc/ PLL_PER_OUT0/LB_MSRCID0/MSRCID0 Config Figure 3-3. P1020 signal groupings (3/3) (continued) Note that individual chapters of this document provide details for each signal, describing each signal's behavior when the signal is asserted or negated and when the signal is an input or an output. The following table provide summary of signals grouped by function. This table details the signal name, interface, alternate functions, number of signals, and whether the signal is an input, output, or bidirectional. The direction of the multiplexed signals applies for the primary signal function listed in the left-most column of the table for that row (and does not apply for the state of the reset configuration signals). Table 3-1. Signal reference by functional block Name Description DDR Controller (See DDR external signal descriptions for more details) Alternate Function(s) No. of I/O Signals Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 103 Signals overview Table 3-1. Signal reference by functional block (continued) Name Description Alternate Function(s) MDQ[0:31] DDR data - MECC[0:7] DDR error correcting code - MAPAR_ERR_B Address parity error - MAPAR_OUT Address parity out - MDM[0:3], MDM[8] DDR data mask - MDQS[0:3], MDQS8 DDR data strobe - MDQS_B[0:3], MDQS8_B DDR data strobe (complement) - MBA[0:2] DDR bank select - MA[0:15] DDR address - MWE_B DDR write enable - MRAS_B DDR row address strobe - MCAS_B DDR column address strobe - MCS_B[0:1] DDR chip select - MCKE[0:1] DDR clock enable - MCK[0:3], MCK_B[0:3] DDR differential clocks (2 pairs/DIMM) - MODT[0:1] DRAM on-die termination - MDIC[0:1] Driver impedance calibration - SerDes (See PCI Express signal descriptions for more details) SD_TX[3:0] Transmit data - SD_TX_B[3:0] Transmit data (complement) - SD_RX[3:0] Receive data - SD_RX_B[3:0] Receive data (complement) - SD_REF_CLK PLL reference clock - SD_REF_CLK_B PLL reference clock (complement) - IEEE 1588 (See eTSEC external signals description for more details) TSEC_1588_ CLK_IN 1588 clock-in - TSEC_1588_ TRIG_IN1 1588 trigger-in 1 - TSEC_1588_ TRIG_IN2 1588 trigger-in 2 - TSEC_1588_ ALARM_OUT1 1588 timer alarm-out 1 cfg_srds_refclk TSEC_1588_ ALARM_OUT2 1588 timer alarm-out 2 cfg_sgmii3 TSEC_1588_ CLK_OUT 1588 clock-out cfg_ddr_pll0 TSEC_1588_ PULSE_OUT1 1588 timer pulse-out 1 cfg_ddr_pll1 TSEC_1588_ PULSE_OUT2 1588 timer pulse-out 2 cfg_ddr_pll2 Ethernet Controller MI (See eTSEC external signals description for more details) EC_GTX_CLK125 Gigabit reference clock - EC_MDC Ethernet management data clock cfg_tsec_reduce No. of I/O Signals 32 I/O 8 I/O 1 I 1 O 5 O 5 I/O 5 I/O 3 O 16 O 1 O 1 O 1 O 2 O 2 O 8 O 2 O 2 I/O 4 O 4 O 4 I 4 I 1 I 1 I 1 I 1 I 1 I 1 O 1 O 1 O 1 O 1 O 1 I 1 O Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 104 Freescale Semiconductor, Inc. Chapter 3 Signal Descriptions Table 3-1. Signal reference by functional block (continued) Name Description Alternate Function(s) No. of I/O Signals EC_MDIO Ethernet management data in/out - 1 I/O eTSEC Controller 1 (See eTSEC external signals description for more details) TSEC1_TXD[3:1] eTSEC1 transmit data 3-1 cfg_io_ports[0:2] 3 O TSEC1_TXD0 eTSEC1 transmit data 0 cfg_tsec1_prtcl0 1 O TSEC1_TX_EN eTSEC1 transmit enable - 1 O TSEC1_TX_ER eTSEC1 transmit error cfg_rom_loc3 1 O TSEC1_TX_CLK eTSEC1 transmit clock in TSEC1_GTX_CLK125 1 I TSEC1_CRS eTSEC1 carrier sense TSEC3_RX_DV 1 I/O TSEC1_COL eTSEC1 collision detect TSEC3_RX_CLK 1 I TSEC1_RXD[3:0] eTSEC1 receive data 3-0 - 4 I TSEC1_RX_DV eTSEC1 receive data valid - 1 I TSEC1_RX_ER eTSEC1 receiver error - 1 I TSEC1_RX_CLK eTSEC1 receive clock - 1 I TSEC1_GTX_CLK125 eTSEC1 Gigabit reference clock TSEC1_TX_CLK 1 I TSEC1_GTX_CLK eTSEC1 transmit clock out - 1 O eTSEC Controller 3 (See eTSEC external signals description for more details) TSEC3_TXD3 eTSEC3 transmit data 3 cfg_tsec1_prtcl1 1 O TSEC3_TXD[2:0] eTSEC3 transmit data 2-0 cfg_rom_loc[0:2] 3 O TSEC3_TX_EN eTSEC3 transmit enable cfg_sdhc_cd_pol_sel 1 O TSEC3_RX_ER eTSEC3 receive error - 1 I/O TSEC3_TX_CLK eTSEC3 transmit clock in - 1 I TSEC3_GTX_CLK eTSEC3 transmit clock out - 1 O TSEC3_RXD[3:0] eTSEC3 receive data 3-0 - 4 I TSEC3_RX_DV eTSEC3 receive data valid TSEC1_CRS 1 I/O TSEC3_RX_CLK eTSEC3 receive clock TSEC1_COL 1 I Enhanced Local Bus Controller (See eLBC external signal descriptions for more details) LAD[0:7] Local bus address/data 0-7 USB2_D[7:0]/ cfg_gpinput[0:7] 8 I/O LAD8 Local bus address/data 8 USB2_NXT/ cfg_gpinput8 1 I/O LAD9 Local bus address/data 9 USB2_DIR/ cfg_gpinput9 1 I/O LAD10 Local bus address/data 10 USB2_STP/ cfg_gpinput10 1 I/O LAD11 Local bus address/data 11 USB2_PWRFAULT/ cfg_gpinput11 1 I/O LAD12 Local bus address/data 12 USB2_CLK/ cfg_gpinput12 1 I/O LAD13 Local bus address/data 13 USB2_PCTL0/ cfg_gpinput13 1 I/O LAD14 Local bus address/data 14 USB2_PCTL1/ cfg_gpinput14 1 I/O LAD15 Local bus address/data 15 cfg_gpinput15 1 I/O LDP[0:1] Local bus data parity - 2 I/O LA16 Local bus burst address 16 cfg_cpu1_boot 1 I/O LA17 Local bus burst address 17 - 1 I/O Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 105 Signals overview Table 3-1. Signal reference by functional block (continued) Name Description Alternate Function(s) LA[18:19] Local bus burst address 18-19 LA[20:22] Local bus burst address 20-22 LA23 Local bus burst address 23 LA24 Local bus burst address 24 LA25 Local bus burst address 25 LA26 Local bus burst address 26 LA27 Local bus burst address 27 LA28 Local bus burst address 28 LA[29:30] Local bus port address 29-30 LA31 Local bus port address 31 LCS_B[0:7] Local bus chip select 0-7 LWE0_B/LFWE_B/LBS0_B Local bus write enable 0 / write enable / byte lane select 1 LWE1_B/LBS1_B Local bus write enable1 / bye lane select 1 LBCTL Local bus data buffer control LALE Local bus address latch enable LGPL0/ LFCLE Local bus UPM general purpose line 0 / flash command latch enable LGPL1/ LFALE Local bus GP line 1 / flash address latch enable LGPL2/LOE_B/LFRE_B Local bus GP line 2 / output enable / flash read enable LGPL3/LFWP_B Local bus GP line 3 / flash write protect LGPL4/LGTA_B/LFRB_B/ Local bus GP line 4 / transaction LUPWAIT termination / flash ready-busy / wait LGPL5 Local bus GP line 5 address LCLK0 Local bus clock 0 LCLK1 Local bus clock 1 eSDHC (See eSDHC external signal description for more details) SDHC_CMD CMD line connect to card SDHC_DAT[0:3] Data line 0-3 SDHC_DAT[4:7] Data line 4-7 SDHC_CD_B eSDHC card detection SDHC_WP eSDHC card write protect SDHC_CLK Clock for MMC/SD card eSPI (See eSDHC external signal description for more details) SPI_MOSI SPI master-out slave-in SPI_MISO SPI master-in slave-out SPI_CLK SPI clock SPI_CS_B[0:3] SPI slave select 0-3 cfg_host_agt[1:2] cfg_eng_use[0:2] cfg_plat_speed cfg_core0_speed cfg_core1_speed cfg_ddr_speed cfg_cpu0_boot cfg_sys_speed cfg_sys_pll[0:1] cfg_sys_pll2 cfg_core1_pll0 cfg_host_agt0 cfg_core0_pll0 cfg_core0_pll1 - - cfg_core0_pll2 cfg_boot_seq0 - cfg_boot_seq1 - SPI_CS_B[0:3] GPIO8 GPIO9 - SDHC_DAT[4:7] No. of I/O Signals 2 I/O 3 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 2 I/O 1 I/O 8 O 1 O 1 I/O 1 I/O 1 O 1 I/O 1 I/O 1 O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 4 I/O 4 I/O 1 I/O 1 I/O 1 O 1 I/O 1 I 1 O 4 I/O Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 106 Freescale Semiconductor, Inc. Chapter 3 Signal Descriptions Table 3-1. Signal reference by functional block (continued) Name Description Alternate Function(s) USB (See USB external signals for more details) USB1_D[7:0] USB1 data bus - USB1_NXT USB1 next data - USB1_DIR USB1 direction of data bus - USB1_STP USB1 end of a transfer on the bus - USB1_PCTL0 USB1 port control 0 GPIO10 USB1_PCTL1 USB1 port control1 GPIO11 USB1_PWRFAULT USB1 VBus power fault - USB1_CLK USB1 PHY clock - USB2_D[7:0] USB2 data bus LAD[0:7]/ cfg_gpinput[0:7] USB2_NXT USB2 next data LAD8/cfg_gpinput8 USB2_DIR USB2 direction of data bus LAD9/cfg_gpinput9 USB2_STP USB2 end of a transfer on the bus LAD10/cfg_gpinput10 USB2_PWRFAULT USB2 VBus power fault LAD11/cfg_gpinput11 USB2_CLK USB2 PHY clock LAD12/cfg_gpinput12 USB2_PCTL0 USB2 port control 0 LAD13/cfg_gpinput13 USB2_PCTL1 USB2 port control 1 LAD14/cfg_gpinput14 DMA (See DMA external signal description for more details) DMA_DREQ0_B DMA request 0 - DMA_DACK0_B DMA acknowledge 0 - DMA_DDONE0_B DMA done 0 - PIC (See PIC external signal descriptions and GPIO signal descriptions for more details) MCP_B[0:1] Machine check processor - UDE_B[0:1] Unconditional debug event - IRQ_OUT_B Interrupt output - IRQ[0:5] External interrupt 0-5 - IRQ6 External interrupt 6 TDM_RX_CLK IRQ7/GPIO0 External interrupt 7/General-purpose I/O signal 0 TDM_TX_DATA IRQ8/GPIO1 External interrupt 8/General-purpose I/O signal 1 TDM_TFS IRQ9/GPIO2 External interrupt 9/General-purpose I/O signal 2 TDM_TX_CLK IRQ10/GPIO3 External interrupt 10/General-purpose I/O TDM_RFS signal 3 IRQ11/GPIO4 External interrupt 11/General-purpose I/O TDM_RX_DATA signal 4 GPIO (See GPIO signal descriptions for more details) GPIO[5:7] General-purpose I/O signal 5-7 - GPIO8 General-purpose I/O signal 8 SDHC_CD_B No. of I/O Signals 8 I/O 1 I 1 I 1 O 1 I/O 1 I/O 1 I 1 I 8 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I 1 O 1 O 2 I 2 I 1 O 6 I 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 3 I/O 1 I/O Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 107 Signals overview Table 3-1. Signal reference by functional block (continued) Name Description Alternate Function(s) No. of I/O Signals GPIO9 General-purpose I/O signal 9 SDHC_WP 1 I/O GPIO10 General-purpose I/O signal 10 USB1_PCTL0 1 I/O GPIO11 General-purpose I/O signal 11 USB1_PCTL1 1 I/O GPIO[12:15] General-purpose I/O signal 12-15 - 4 I/O DUART (See DUART external signal descriptions for more details) UART_SOUT0 UART0 serial data out cfg_eng_use[3] 1 O UART_SOUT1 UART1 serial data out cfg_core1_pll1 1 I/O UART_SIN0 UART0 serial data in - 1 I UART_SIN1 UART1 serial data in - 1 I/O UART_CTS0_B UART0 clear to send - 1 I UART_CTS1_B UART1 clear to send - 1 I/O UART_RTS0_B UART0 ready to send cfg_tsec3_prtcl0 1 O UART_RTS1_B UART1 ready to send cfg_tsec3_prtcl1 1 O I2C (See I2C external signal descriptions for more details) IIC1_SDA I2C1 serial data - 1 I/O IIC1_SCL I2C1 serial clock - 1 I/O IIC2_SDA I2C2 serial data - 1 I/O IIC2_SCL I2C2 serial clock - 1 I/O TDM (See TDM external signals descriptions for more details) TDM_RX_CLK TDM receive clock IRQ6 1 I/O TDM_TX_DATA TDM transmit data GPIO0/IRQ7 1 I/O TDM_TFS TDM transmit frame sync GPIO1/IRQ8 1 I/O TDM_TX_CLK TDM transmit clock GPIO2/IRQ9 1 I/O TDM_RFS TDM receive frame sync GPIO3/IRQ10 1 I/O TDM_RX_DATA TDM receive data GPIO4/IRQ11 1 I/O QUICC Engine (See Table 1, , Table 2 for more details) System Control (See Reset external signal descriptions and Global utilities external signal description for more details) HRESET_B Hard reset - 1 I HRESET_REQ_B Hard reset request - 1 O SRESET_B Soft reset - 1 I CKSTP_IN_B[0:1] Checkstop in - 2 I CKSTP_OUT_B[0:1] Checkstop out - 2 O Debug (See Debug external signal description for more details) TRIG_IN Watchpoint trigger in - 1 I TRIG_OUT Watchpoint trigger out - 1 O READY_P1 Processor 1 ready cfg_core1_pll2 1 O MSRCID0 Memory debug source ID 0 cfg_elbc_ecc 1 I/O MSRCID1 Memory debug source ID 1 - 1 I/O MSRCID2 Memory debug source ID 2 - 1 I/O Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 108 Freescale Semiconductor, Inc. Chapter 3 Signal Descriptions Table 3-1. Signal reference by functional block (continued) Name Description Alternate Function(s) MSRCID3 Memory debug source ID 3 - MSRCID4 Memory debug source ID 4 cfg_eng_use[6] MDVAL Memory debug data valid - CFG_MEM_ DEBUG Memory debug configuration - CFG_DDR_ DEBUG DDR debug configuration - CFG_IO_PORTS3 I/O port configuration - CFG_DRAM_TYPE DDR DRAM type configuration - Power Management (See Global utilities external signal description for more details) ASLEEP Asleep - CLK_OUT Clock out - Clocking (See Reset external signal descriptions for more details) SYSCLK System clock - RTC Real time clock - DDRCLK DDR clock - Test and JTAG (See Debug external signal description for more details) SCAN_MODE_B Test select - TEST_SEL_B Test select - TCK Test clock - TDI Test data in - TDO Test data out - TMS Test mode select - TRST_B Test reset - IO VSEL (See Reset external signal descriptions for more details) LVDD_VSEL LVDD voltage select - BVDD_VSEL[0:1] BVDD voltage select - CVDD_VSEL[0:1] CVDD voltage select - Analog (See eTSEC external signals description for more details) SD_PLL_TPD PLL test point digital - SD_PLL_TPA PLL test point analog - SD_IMP_CAL_TX Transmitter impedance calibration - SD_IMP_CAL_RX Receiver impedance calibration - No. of I/O Signals 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I 1 O 1 O 1 O 1 I 1 I 1 I 1 I 1 I 1 I 1 I 1 O 1 I 1 I 1 I 2 I 2 I 1 O 1 O 1 I 1 I 3.3 Configuration signals sampled at reset The signals that serve alternate functions as configuration input signals during system reset are summarized in the table below. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 109 Configuration signals sampled at reset The detailed interpretation of their voltage levels during reset is described in the "Reset" chapter. Note that throughout this document, the reset configuration signals are described as being sampled at the negation of HRESET_B. However, there is a setup and hold time for these signals relative to the rising edge of HRESET_B, as described in the P1020 QorIQ Integrated Processor Hardware Specifications. Note that the PLL configuration signals have different setup and hold time requirements than the other reset configuration signals. The reset configuration signals are multiplexed with other functional signals. The values on these signals during reset are interpreted to be logic one or zero, regardless of whether the functional signal name is defined as active-low. Most of the reset configuration signals have internal pull-up resistors so that if the signals are not driven, the default value is high (a one), as shown in the table. Some signals do not have pull-up resistors and must be driven high or low during the reset period. For details about all the signals that require external pull-up resistors, see the P1020 QorIQ Integrated Processor Hardware Specifications. Note that the multiplexing of various signals on the device is controlled by the PMUXCR register described in the "Global Utilities" chapter. Table 3-2. Reset configuration signals Functional Interface Debug DUART eLBC Functional Signal Name READY_P1 MSRCID0 MSRCID4 UART_SOUT1 UART_RTS0_B UART_RTS1_B UART_SOUT0 LGPL3/LFWP_B LGPL5 LBCTL LALE LGPL2/LOE_B/LFRE_B LA16 LA[18:19] LA23 LA24 LA25 LA26 LA27 LA28 Reset Configuration Name Default cfg_core1_pll2 Must be driven cfg_elbc_ecc 1 cfg_eng_use6 1 cfg_core1_pll1 Must be driven cfg_tsec3_prtcl0 1 cfg_tsec3_prtcl1 1 cfg_eng_use3 1 cfg_boot_seq0 1 cfg_boot_seq1 1 cfg_core0_pll0 Must be driven cfg_core0_pll1 Must be driven cfg_core0_pll2 Must be driven cfg_cpu1_boot 1 cfg_host_agt[1:2] 11 cfg_plat_speed 1 cfg_core0_speed 1 cfg_core1_speed 1 cfg_ddr_speed 1 cfg_cpu0_boot 1 cfg_sys_speed 1 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 110 Freescale Semiconductor, Inc. Chapter 3 Signal Descriptions Table 3-2. Reset configuration signals (continued) Functional Interface Ethernet Management IEEE 1588 eTSEC1 eTSEC3 Configuration-only Functional Signal Name LA[29:31] LAD[0:15] LWE0_B/LFWE_B/LBS0_B LWE1_B/LBS1_B LA[20:22] EC_MDC TSEC_1588_CLK_OUT TSEC_1588_PULSE_OUT1 TSEC_1588_PULSE_OUT2 TSEC_1588_ALARM_OUT1 TSEC_1588_ALARM_OUT2 TSEC1_TXD[3:1] TSEC1_TX_ER TSEC1_TXD0 TSEC3_TXD3 TSEC3_TXD[2:0] TSEC3_TX_EN CFG_MEM_DEBUG CFG_DDR_DEBUG CFG_DRAM_TYPE CFG_IO_PORTS3 Reset Configuration Name Default cfg_sys_pll[0:2] Must be driven cfg_gpinput[0:15] All ones cfg_core1_pll0 Must be driven cfg_host_agt0 1 cfg_eng_use[0:2] 111 cfg_tsec_reduce 1 cfg_ddr_pll0 Must be driven cfg_ddr_pll1 Must be driven cfg_ddr_pll2 Must be driven cfg_srds_refclk 1 cfg_sgmii3 1 cfg_io_ports[0:2] 111 cfg_rom_loc3 1 cfg_tsec1_prtcl0 1 cfg_tsec1_prtcl1 1 cfg_rom_loc[0:2] 111 cfg_sdhc_cd_pol_sel 1 cfg_mem_debug 1 cfg_ddr_debug 1 cfg_dram_type 1 cfg_io_ports3 1 3.4 Output Signal States During Reset When a system reset is recognized (HRESET_B is asserted), the chip aborts all current internal and external transactions and releases all bidirectional I/O signals to a highimpedance state. See Reset, Clocking, and Initialization for a complete description of the reset functionality. During reset, the chip ignores most input signals (except for the reset configuration signals) and drives most of the output-only signals to an inactive state. Table 3-3. Output Signal States During Reset DDR Controller Interface MA[0:15] Signal Table continues on the next page... State During Reset High-Z P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 111 Output Signal States During Reset Table 3-3. Output Signal States During Reset (continued) Interface DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller DDR Controller eLBC eLBC eLBC eLBC eLBC eLBC eLBC eLBC eLBC eLBC eLBC eLBC SPI SPI SPI DUART DUART DMA DMA IEEE 1588 IEEE 1588 IEEE 1588 Ethernet Management Signal MBA[0:2] MCS_B[0:1] MCKE[0:1] MCK[0:3] MCK_B[0:3] MODT[0:1] MDIC[0:1] MDM[0:3], MDM[8] MDQ[0:31] MDQS[0:3], MDQS[8] MDQS_B[0:3], MDQS_B[8] MECC[0:7] MAPAR_OUT MWE_B MRAS_B MCAS_B LA[16:31] LAD[0:15] LCLK[0:1] LCS_B[0:7] LDP[0:1] LWE_B[0:1] LBCTL LALE LGPL[0:1] LGPL[2:3] LGPL[4] LGPL[5] SPI_MOSI SPI_CLK SPI_CS_B[0:3] UART_SOUT[0:1] UART_RTS_B[0:1] DMA_DACK0_B DMA_DDONE0_B TSEC_1588_ ALARM_OUT[1:2] TSEC_1588_ CLK_OUT TSEC_1588_ PULSE_OUT[1:2] EC_MDC State During Reset High-Z High-Z Driven Low Driven Low Driven High Driven Low High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z POR Weak Pullup POR Weak Pullup Driven Low Driven High High-Z POR Weak Pullup POR Weak Pullup POR Weak Pullup Driven High POR Weak Pullup High-Z POR Weak Pullup High-Z High-Z Driven High POR Weak Pullup POR Weak Pullup POR Weak Pullup POR Weak Pullup POR Weak Pullup POR Weak Pullup POR Weak Pullup POR Weak Pullup Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 112 Freescale Semiconductor, Inc. Chapter 3 Signal Descriptions Table 3-3. Output Signal States During Reset (continued) Interface Ethernet Management Ethernet Controller 1 Ethernet Controller 1 Ethernet Controller 1 Ethernet Controller 1 Ethernet Controller 3 Ethernet Controller 3 I2C I2C I2C I2C eSDHC eSDHC eSDHC PIC USB USB GPIO System Control System Control Debug Debug Debug Debug Debug Debug Debug Power Management Power Management JTAG Signal EC_MDIO TSEC1_TXD[3:0] TSEC1_TX_EN TSEC1_TX_ER TSEC1_GTX_CLK TSEC3_GTX_CLK TSEC3_TX_EN IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL SDHC_CMD SDHC_DAT[0:3] SDHC_CLK IRQ_OUT_B USB_STP USB_D[7:0] GPIO[0:15] HRESET_REQ_B CKSTP_OUT_B[0:1] READY_P1 TRIG_OUT MDVAL MSRCID[0:4] CFG_DRAM_TYPE CFG_MEM_DEBUG CFG_DDR_DEBUG CLK_OUT ASLEEP TDO State During Reset High-Z POR Weak Pullup Driven Low POR Weak Pullup Driven Low High-Z POR Weak Pullup High-Z High-Z High-Z High-Z High-Z High-Z Driven Low High-Z Driven High High-Z High-Z POR Weak Pullup High-Z POR Weak Pullup POR Weak Pullup POR Weak Pullup POR Weak Pullup POR Weak Pullup POR Weak Pullup POR Weak Pullup High-Z POR Weak Pullup High-Z P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 113 Output Signal States During Reset P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 114 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization This chapter describes the reset, clocking, and some overall initialization of the device, including a definition of the reset configuration signals and the options they select. 4.1 Overview This chapter describes the reset, clocking, and some overall initialization of the device, including a definition of the reset configuration signals and the options they select. Additionally, the configuration, control, and status registers are described. Note that other chapters in this book may describe specific aspects of initialization for individual blocks. The reset, clocking, and control signals provide many options for the operation of the device. Additionally, many modes are selected with reset configuration signals during a hard reset (assertion of HRESET_B). 4.2 Reset external signal descriptions The table below summarizes the external signals described in this chapter. Table 4-2 and Table 4-3 have detailed signal descriptions, and Table 4-1 contains references to additional sections that contain more information. Table 4-1. Signal summary Signal I/O Description References HRESET_B I Hard reset input. Causes a power-on reset (POR) sequence. Hard reset HRESET_REQ_B O Hard reset request output. An internal block requests that HRESET_B be asserted. Hard reset SRESET_B I Soft reset input. Causes mcp assertion to the core Soft reset READY_P0/ TRIG_OUT O The device has completed the reset operation, and e500 core 0 is not in a power- Power-on reset down (nap, doze, or sleep) or debug state. sequence Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 115 Reset external signal descriptions Table 4-1. Signal summary (continued) Signal I/O Description References READY_P1 O The device has completed the reset operation, and e500 core 1 is not in a power- Power-on reset down (nap, doze, or sleep) or debug state. sequence SYSCLK I Primary clock input to the device System clock and DDR controller complex clock RTC I Real time clock input Real time clock SD_REF_CLK/ I SerDes high-speed interface reference clock SD_REF_CLK_B PCI Express clock DDRCLK I Reference clock for DDR controller, when running in asynchronous mode System clock and DDR controller complex clock The following sections describe the reset and clock signals in detail. 4.2.1 System control signals The table below describes some of the device's system control signals. Power-on reset configuration, describes the signals that also function as reset configuration signals. Note that the CKSTP_IN_B and CKSTP_OUT_B signals are described in Global Utilities. Signal HRESET_B Table 4-2. System control signals-detailed signal descriptions I/O Description I Hard reset. Causes the device to abort all current internal and external transactions and set all registers to their default values. HRESET_B may be asserted completely asynchronously with respect to all other signals. State Asserted/Negated-See Signal Descriptions and Power-on reset configuration, for more Meaning information on the interpretation of other signals during reset. Timing Assertion/Negation-The P1020 QorIQ Integrated Processor Hardware Specifications gives specific timing information for this signal and the reset configuration signals. HRESET_REQ_ O B Hard reset request. Indicates to the board (system in which the device is embedded) that a condition requiring the assertion of HRESET_B has been detected. State Asserted-A watchdog timer, a boot sequencer failure (see Boot sequencer mode), or an Meaning eLBC ECC error (see Reset request status and control register (GUTS_RSTRSCR) has triggered a request for hard reset. Timing Negated-Indicates no reset request. Assertion/Negation-May occur any time, synchronous to the core complex bus clock. Once asserted, HRESET_REQ_B does not negate until HRESET_B is asserted. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 116 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization Table 4-2. System control signals-detailed signal descriptions (continued) Signal SRESET_B READY_P0/ TRIG_OUT READY_P1 I/O Description I Soft reset. Causes a machine check interrupt to the e500 core. Note that if the e500 core is not configured to process machine check interrupts, the assertion of SRESET_B causes a core checkstop. SRESET_B need not be asserted during a hard reset . State Asserted-Asserting SRESET_B causes a machine check interrupt (edge sensitive) to the Meaning e500 core. SRESET_B has no effect while HRESET_B is asserted. However, the POR sequence is paused if SRESET_B is asserted during POR. Timing Assertion-May occur at any time, asynchronous to any clock. Negation-Must be asserted for at least two CCB_clk cycles. O Ready processor 0. Multiplexed with TRIG_OUT and QUIESCE_B. See Debug Features and Watchpoint Facility for more information on TOSR and TRIG_OUT. State Asserted-Indicates that the device has completed the reset operation, and e500 core 0 is Meaning not in a power-down state (nap, doze, or sleep) when TOSR[SEL] equals 0b000. See Power-on reset sequence, for more information. Timing Assertion/Negation-Initial assertion of READY_P0 after reset is synchronous with SYSCLK. Subsequent assertion/negation due to power down modes occurs asynchronously. O Ready processor 1. State Asserted-Indicates that the device has completed the reset operation, and e500 core 1 is Meaning not in a power-down state (nap, doze, or sleep). Timing Assertion/Negation-Initial assertion of READY_P1 after reset is synchronous with SYSCLK. Subsequent assertion/negation due to power down modes occurs asynchronously. 4.2.2 Clock signals The table below describes the overall clock signals. Note that some clock signals are specific to blocks within the device, and although some of their functionality is described in Clocking, they are defined in detail in their respective chapters. Note that there is also a CLK_OUT signal; the signal driven on the CLK_OUT pin is selectable and described in Clock out control register (GUTS_CLKOCR). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 117 Accessing configuration, control, and status registers Table 4-3. Clock signals-detailed signal descriptions Signal SYSCLK RTC DDRCLK I/ Description O I System clock (SYSCLK). SYSCLK is the primary clock input to the device. It is the clock source for the e500 core and for all devices and interfaces that operate synchronously with the core. It is multiplied up with a phased-lock loop (PLL) to create the core complex bus (CCB) clock (also called the platform clock), which is used by virtually all of the synchronous system logic, including the L2 cache, the DDR SDRAM and local bus memory controllers, and other internal blocks such as the DMA and interrupt controllers. The CCB clock, in turn, feeds the PLL in the e500 core and the PLL that creates the local bus memory clocks. Timing Assertion/Negation-See the P1020 QorIQ Integrated Processor Hardware Specifications for specific timing information for this signal. I Real time clock. May be used (optionally) to clock the time base of the e500 core. The RTC timing specifications are given in the P1020 QorIQ Integrated Processor Hardware Specifications, but the maximum frequency should be less than one-quarter of the CCB frequency. See Real time clock. This signal can also be used (optionally) to clock the global timers in the programmable interrupt controller (PIC). Timing Assertion/Negation-See the P1020 QorIQ Integrated Processor Hardware Specifications for specific timing information for this signal. I DDR controller complex clock. DDRCLK is the clock source for the DDR memory controller complex except in the case where synchronous mode of operation is selected (see DDR PLL ratio). This clock input is multiplied up with a phased-lock loop (PLL) to create the DDR controller complex clock. The DDR memory controller complex clock is the DDR data rate on the external interface unless the given controller is configured to run in half speed. Timing Assertion/Negation-See the P1020 QorIQ Integrated Processor Hardware Specifications for specific timing information for this signal. 4.3 Accessing configuration, control, and status registers The configuration, control, and status registers are memory mapped. The set of configuration, control, and status registers occupies a 1-Mbyte region of memory. Their location is programmable using the CCSR base address register (CCSRBAR). The default base address for the configuration, control, and status registers is 0x0_FF70_0000 (CCSRBAR = 0x000F_F700). CCSRBAR itself is part of the local access block of CCSR memory, which begins at offset 0x0 from CCSRBAR. Because CCSRBAR is at offset 0x0 from the beginning of the local access registers, CCSRBAR always points to itself. The contents of CCSRBAR are broadcast internally in the P1020 to all functional units that need to be able to identify or create configuration transactions. 4.3.1 Updating CCSRBAR Updates to CCSRBAR that relocate the entire 1-Mbyte region of configuration, control, and status registers require special treatment. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 118 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization The effect of the update must be guaranteed to be visible by the mapping logic before an access to the new location is seen. To make sure this happens, these guidelines should be followed: • CCSRBAR should be updated during initial configuration of the device when only one host or controller has access to the device. • If the boot sequencer is being used to initialize, it is recommended that the boot sequencer set CCSRBAR to its desired final location. • If an external host on PCI Express is configuring the device, it should set CCSRBAR to the desired final location before the e500 core is released to boot. • If the e500 core is initializing the device, it should set CCSRBAR to the desired final location before enabling other I/O devices to access the device. • When the e500 core is writing to CCSRBAR, it should use the following sequence: • Read the current value of CCSRBAR using a load word instruction followed by an isync. This forces all accesses to configuration space to complete. • Write the new value to CCSRBAR. • Perform a load of an address that does not access configuration space or the onchip SRAM, but has an address mapping already in effect (for example, boot ROM). Follow this load with an isync. • Read the contents of CCSRBAR from its new location, followed by another isync. 4.3.2 Accessing alternate configuration space An alternate configuration space can be accessed by configuring the ALTCBAR and ALTCAR registers. These are intended to be used with the boot sequencer to allow the boot sequencer to access an alternate 1-Mbyte region of configuration space. By loading the proper boot sequencer command in the serial ROM, the base address in the ALTCBAR can be combined with the 20 bits of address offset supplied from the serial ROM to generate a 36-bit address that is mapped to the target specified in ALTCAR. Thus, by configuring these registers, the boot sequencer has access to the entire memory map, one 1-Mbyte block at a time. See Boot sequencer mode, for more information. NOTE The enable bit in the ALTCAR register should be cleared either by the boot sequencer or by the boot code that executes after the boot sequencer has completed its configuration operations. This prevents problems with incorrect mappings if subsequent configuration of the local access windows uses a different target mapping for the address specified in ALTCBAR. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 119 Reset Memory Map/Register Definition 4.3.3 Boot page translation When each e500 core comes out of reset, its MMU has one 4-Kbyte page defined at 0x0_FFFF_Fnnn. Each core begins execution with the instruction at effective address 0x0_FFFF_FFFC. To get this instruction, the core's first instruction fetch is a burst read of boot code from effective address 0x0_FFFF_FFE0. For systems in which the boot code resides at a different address, the device provides boot page translation capability. Boot page translation is controlled by the boot page translation register (BPTR). Note that boot page translation affects transactions initiated by each of the two e500 cores in the same manner. The boot sequencer can enable boot page translation, or the boot page translation can be set up by an external host when the device is configured to be in boot holdoff mode. If translation is to be performed to a page outside the default boot ROM address range defined in the device (8 Mbytes at 0x0_FF80_0000 to 0x0_FFFF_FFFF as defined in Boot ROM location), the external host or boot sequencer must then also set up a local access window to define the routing of the boot code fetch to the target interface that contains the boot code, because the BPTR defines only the address translation, not the target interface window. See Local address map example, and Boot sequencer mode, for more information. 4.3.4 Boot sequencer The boot sequencer is a DMA engine that accesses a serial ROM on the I2C interface and writes data to CCSR memory or the memory space pointed to by the alternate configuration base address register (ALTCBAR). See Accessing alternate configuration space. The boot sequencer is enabled by reset configuration pins as described in Boot sequencer configuration. If the boot sequencer is enabled, the e500 core is held in reset until the boot sequencer has completed its operation. For more details, see Boot sequencer mode, in the I2C chapter. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 120 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization 4.4 Reset Memory Map/Register Definition This section describes the configuration and control registers that control access to the configuration space and to the boot code as well as guidelines for accessing these regions. It also contains a brief description of the boot sequencer which may be used to initialize configuration registers or memory before the CPU is released to boot. reset memory map Offset address (hex) 0 8 10 20 Register name Configuration, control, and status registers base address register (reset_CCSRBAR) Alternate configuration base address register (reset_ALTCBAR) Alternate configuration attribute register (reset_ALTCAR) Boot page translation register (reset_BPTR) Width (in bits) Access Reset value Section/ page 32 R/W 000F_F700h 4.4.1/121 32 R/W 0000_0000h 4.4.2/122 32 R/W 0000_0000h 4.4.3/122 32 R/W 0000_0000h 4.4.4/123 4.4.1 Configuration, control, and status registers base address register (reset_CCSRBAR) Address: 0h base + 0h offset = 0h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W - BASE_ADDR - Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 reset_CCSRBAR field descriptions Field 0–7 - 8–23 BASE_ADDR 24–31 - Write reserved, read = 0. Description Identifies the 16 most-significant address bits of the window used for configuration accesses. The base address is aligned on a 1-Mbyte boundary. Write reserved, read = 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 121 Reset Memory Map/Register Definition 4.4.2 Alternate configuration base address register (reset_ALTCBAR) Address: 0h base + 8h offset = 8h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W - BASE_ADDR - Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset_ALTCBAR field descriptions Field 0–7 - 8–23 BASE_ADDR 24–31 - Write reserved, read = 0 Description Identifies the 16 most significant address bits of an alternate window used for configuration accesses. Write reserved, read = 0 4.4.3 Alternate configuration attribute register (reset_ALTCAR) Address: 0h base + 10h offset = 10h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W EN - TRGT_ID - Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W - Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Field 0 EN 1–7 - 8–11 TRGT_ID reset_ALTCAR field descriptions Description Enable for a second configuration window. Like CCSRBAR, it has a fixed size of 1 Mbyte. 0 Second configuration window is disabled. 1 Second configuration window is enabled. Write reserved, read = 0 Identifies the device ID to target when a transaction hits in the 1-Mbyte address range defined by the second configuration window. 0000 0001 0010 Reserved PCI Express interface 2 PCI Express interface 1 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 122 Freescale Semiconductor, Inc. Field 12–31 - Chapter 4 Reset, Clocking, and Initialization reset_ALTCAR field descriptions (continued) Description 0011 0100 0101-1110 1111 Reserved Local bus controller Reserved Local memory -DDR SDRAM and on-chip SRAM Write reserved, read = 0 4.4.4 Boot page translation register (reset_BPTR) Address: 0h base + 20h offset = 20h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W EN - BOOT_PAGE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W BOOT_PAGE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset_BPTR field descriptions Field 0 EN 1–7 - 8–31 BOOT_PAGE Boot page translation enable Description 0 Boot page is not translated. 1 Boot page is translated as defined in the BPTR[BOOT_PAGE] parameter. Write reserved, read = 0 Translation for boot page. If enabled, the high order 24 bits of accesses to 0x0_FFFF_Fnnn are replaced with this value. 4.5 Functional description This section describes the various ways to reset the device, the POR configurations, and the clocking on the device. 4.5.1 Reset operations This device has reset input signals for hard and soft reset operation. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 123 Functional description 4.5.1.1 Soft reset Assertion of SRESET_B causes a machine check interrupt to both e500 cores. When this occurs, the soft reset flag is recorded in the machine check summary register in the global utilities block so that software can identify the machine check as a soft reset condition. See the PowerPC e500 Core Complex Reference Manual for more information on the machine check interrupt and Machine check summary register (GUTS_MCPSUMR), for more information on the setting of the soft reset flag. Note that if SRESET_B is asserted before a given e500 core is configured to handle a machine check interrupt, a checkstop condition occurs for that particular core, which causes CKSTP_OUT0_B or CKSTP_OUT1_B to assert. 4.5.1.2 Hard reset This device can be completely reset by the assertion of the HRESET_B input. The assertion of this signal by external logic is the equivalent of a POR and causes the sequence of events described in Power-on reset sequence. Refer to the P1020 QorIQ Integrated Processor Hardware Specifications for the timing requirements for HRESET_B assertion and negation. The hard reset request output signal (HRESET_REQ_B) indicates to external logic that a hard reset is being requested by hardware or software. Hardware causes this signal to assert for a boot sequencer failure (see Boot sequencer mode, and EEPROM data format), for a local bus non-correctable ECC error during NAND Flash boot process (see Boot block loading into the FCM buffer RAM ), or when either e500 watchdog timer is configured to cause a hard reset request when it expires (See Timer control register group n (PIC_TCRn) ; TCR[WRC] field). Software may request a hard reset by setting a bit in a global utilities register; see Reset control register (GUTS_RSTCR). 4.5.2 Power-on reset sequence The POR sequence for the device is as follows: 1. Power is applied to meet the specifications in the P1020 QorIQ Integrated Processor Hardware Specifications. 2. The system asserts HRESET_B and TRST_B, causing all registers to be initialized to their default states and most I/O drivers to be three-stated (some clock, clock enabled, and system control signals are active). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 124 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization 3. The system applies a stable SYSCLK signal and stable PLL configuration inputs, and the device PLL begins locking to SYSCLK. 4. The e500 PLL configuration inputs are applied, allowing the e500 PLLs to begin locking to the device clock (the CCB clock). 5. The CCB clock is cycled for approximately 100 μs to lock the e500 PLLs. 6. The device enables I/O drivers. 7. The internal hard resets to the e500 cores are negated and soft resets are negated to the PLLs and other remaining I/O blocks. The PLLs begin to lock. 8. When PLL locking is completed, the enhanced local bus FCM is released provided NAND flash is configured as the boot device, as described in Boot ROM location. Once the FCM finishes loading the pages from the NAND Flash device, the boot sequencer, if enabled, is allowed to progress, causing it to load configuration data from serial ROMs on the I2C1 interface, as described in Boot sequencer configuration. 9. When the local bus FCM and boot sequencer complete, the PCI Express interfaces begin training and are released to accept external requests, and the boot vectors fetched by the e500 cores are allowed to proceed unless processor booting is further held off by POR configuration inputs as described in Boot sequencer configuration. The device is now in its ready state. 10. The ASLEEP signal negates synchronized to a rising edge of SYSCLK, indicating the ready state of the system. The ready state for the e500 core is also indicated by the assertion of READY_P0/TRIG_OUT if TOSR[SEL] = 000. In this case, READY is asserted with the same rising edge of SYSCLK, to indicate that the e500 core has reached its ready state, allows external system monitors to know basic device status, for example, exactly when the e500 core emerges from reset, or if it is in a lowpower mode. The figure below shows a timing diagram of the POR sequence. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 125 Functional description SYSCLK HRESET_B TRST_B SRESET_B PLL Config (POR Config) CCB_CLOCK Core_Clock POR Config ASLEEP READY_P0 Max 5 Clocks Min 4 Clocks 25 μSec Min. Reset Assertion Time 100 μSec Min. System PLL 100 μSec Boot Sequence Core PLL if enabled These signals can have any values These signals can be driven till the required values Figure 4-5. Power-on reset sequence 4.5.3 Power-on reset configuration Various device functions are initialized by sampling certain signals during the assertion of HRESET_B. The values of all these signals are sampled into registers while HRESET_B is asserted. These inputs are to be pulled high or low by external resistors. During HRESET_B, all other signal drivers connected to these signals must be in the high-impedance state. Most POR configuration signals have internal pull-up resistors so that if the desired setting is high, there is no need for a pull-up resistor on the board. Other POR configuration signals do not use pull-ups and therefore must be pulled high or low. Refer to the P1020 QorIQ Integrated Processor Hardware Specifications for proper resistor values to be used for pulling POR configuration signals high or low. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 126 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization This section describes the functions and modes configured by POR configuration signals. Note that many reset configuration settings are accessible to software through the following read-only memory-mapped registers described in GUTS Memory Map/ Register Definition • POR PLL status register (PORPLLSR) • POR boot mode status register (PORBMSR) • POR device status register (PORDEVSR) • POR device status register 2 (PORDEVSR2) • POR debug mode status register (PORDBGMSR) • General-purpose POR configuration register (GPPORCR)-Reports the value on LAD[0:15] during POR (can be used to external system configuration) NOTE In the following tables, the binary value 0b0 represents a signal pulled down to GND and a value of 0b1 represents a signal pulled up to VDD, regardless of the sense of the functional signal name on the signal. 4.5.3.1 System PLL ratio The system PLL inputs establish the clock ratio between the SYSCLK input and the platform clock used by this device. The platform clock, also called the CCB clock, drives the L2 cache, the DDR SDRAM data rate, and the e500 core complex bus (CCB). There is no default value for this PLL ratio; these signals must be pulled to the desired values. See Minimum frequency requirements, for optimal selection of this ratio with regard to available high-speed interface widths and frequencies. Note that the values latched on these signals during POR are accessible in the PORPLLSR (POR PLL status register), as described in POR PLL ratio status register (GUTS_PORPLLSR). The system PLL inputs are shown in the table below. Table 4-8. CCB clock PLL ratio Functional signals Reset configuration name LA[29:31] No Default cfg_sys_pll[0:2] Value (Binary) 000 001 010 other CCB Clock : SYSCLK Ratio 4:1 5:1 6:1 Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 127 Functional description 4.5.3.2 DDR PLL ratio The DDR PLL inputs, shown in the table below, establish the clock ratio between the DDRCLK input and the DDR complex clock. The DDR complex clock drives the DDR data rate, which is twice the rate at which commands are issued on the DDR interface. This DDR complex clock domain is asynchronous to the platform clock or CCB clock domain, and is sourced from a separate PLL than the rest of the platform, unless the DDR PLL encoding for synchronous mode operation is selected. When synchronous mode is selected, the DDR complex is driven by the CCB clock, which becomes the DDR data rate. There is no default value for this PLL ratio; these signals must be pulled to the desired values. Note that the encoded values latched on these signals during power-on reset-and not the actual values on the pins-are accessible in PORPLLSR (POR PLL status register), as described in POR PLL ratio status register (GUTS_PORPLLSR). Table 4-9. DDR complex clock PLL ratio Functional signals TSEC_1588_CLK_OUT, TSEC_1588_PULSE_OUT1, TSEC_1588_PULSE_OUT2 No Default Reset configuration name cfg_ddr_pll[0:2] Value (Binary) 000 001 010 011 100 101 110 111 DDR complex : DDRCLK ratio 3:1 4:1 6:1 8:1 10 : 1 Reserved Reserved Synchronous mode 4.5.3.3 e500 core PLL ratios Table 4-10 and Table 4-11 describe the e500 core clock PLL inputs that program the core PLLs and establish the ratio between the e500 core clocks and the e500 core complex bus (CCB) clock. There are no default values for these PLL ratios; these signals must be P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 128 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization pulled to the desired values. Note that the values latched on these signals during POR are accessible through the memory-mapped PORPLLSR, as described in POR PLL ratio status register (GUTS_PORPLLSR), and also in the e500 core HID1 register. Table 4-10. e500 core0 clock PLL ratios Functional signals Reset configuration name Value (binary) e500 core:CCB clock ratio LBCTL, LALE, LGPL2/LOE_B/LFRE_B cfg_core0_pll[0:2] 000 Reserved No Default 001 Reserved 010 1:1 011 3 : 2 (1.5 : 1) 100 2:1 101 5 : 2 (2.5:1) 110 3:1 111 Reserved Table 4-11. e500 core1 clock PLL ratios Functional signals LWE0_B, UART_SOUT1, READY_P1 No Default Reset configuration name Value (Binary) e500 core:CCB clock ratio cfg_core1_pll[0:2] 000 Reserved 001 Reserved 010 1:1 011 3 : 2 (1.5 : 1) 100 2:1 101 5 : 2 (2.5:1) 110 3:1 111 Reserved 4.5.3.4 Boot ROM location This device defines the default boot ROM address range to be 8 Mbytes at address 0x0_FF80_0000 to 0x0_FFFF_FFFF. However, which peripheral interface handles these boot ROM accesses can be selected at power on. The boot ROM location inputs, shown in the table below, select the physical location of boot ROM. Accesses to the boot vector and the default boot ROM region of the local address map are directed to the interface specified by these inputs. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 129 Functional description Functional Signals TSEC3_TXD[2:0], TSEC1_TX_ER Default (1111) Table 4-12. Boot ROM location Reset Configuration Name Value (Binary) cfg_rom_loc[0:3] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Meaning PCI Express 1 PCI Express 2 Reserved Reserved DDR controller Reserved On-chip boot ROM-SPI configuration On-chip boot ROM-eSDHC configuration Local bus FCM-8-bit NAND flash small page Reserved Local bus FCM-8-bit NAND flash large page Reserved Reserved Local bus GPCM-8-bit ROM Local bus GPCM-16-bit ROM Local bus GPCM-16-bit ROM (default) Note that the values latched on these signals during POR are accessible through the memory-mapped PORBMSR (POR boot mode status register) described in POR boot mode status register (GUTS_PORBMSR). See Local address map example, for an example memory map that relies on the default boot ROM values. Also, see Boot page translation register (reset_BPTR), for information on translation of the boot page. 4.5.3.5 Host/agent configuration The host/agent reset configuration inputs, shown in the table below, configure the device to act as a host or as an agent of a master on another interface. If the device is an agent on the PCI Express interfaces, then it is disabled from mastering transactions on that interface until the external host enables it to do so. The external host does this by setting the control registers of the device interfaces appropriately. See details in the PCI Express programming model described in PCI Express Interface Controller. Note that the values latched on these signals during POR are accessible through the memory-mapped PORBMSR (POR boot mode status register) described in POR boot mode status register (GUTS_PORBMSR). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 130 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization Table 4-13. Host/agent configuration Functional signals Reset configuration name Value Meaning (Binary) LWE1_B, LA[18:19] cfg_host_agt[0:2] 000 Device acts as an agent on all its PCI Express interfaces. Default (111) 001 Device acts as an agent on PCI Express 1 and acts as a host on PCI Express 2. 010 Device acts as a host on PCI Express 1 and acts as an agent on PCI Express 2. 011-110 Reserved 111 Device acts as the host processor/root complex for all PCI Express interfaces (default). 4.5.3.6 I/O port selection This device can be configured with different I/O ports active. The table below shows the configuration of I/O ports and bit rates (and required reference clocks) that are possible for the PCI Express interfaces. Note that the POR configuration input cfg_sgmii3, in combination with cfg_io_ports[0:3], determines whether Serdes lane 2 and 3 are used by eTSEC2 and eTSEC3 respectively in SGMII mode. Also note that when PCI-Express operation is required, the Serdes reference clock must be 100MHz. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 131 Functional description Table 4-14. I/O port selection Functional signal Reset configuration name Value Meaning (Binary) TSEC1_TXD[3:1], CFG_IO_PORTS3 Default (1111) cfg_io_ports[0:3] 0000 0001 PCI Express 1 (x1) (2.5Gbps) → SerDes lane 0 SerDes lanes 1-3 powered down. SerDes lanes 0-3 powered down. 0010-0101 Reserved 0110 PCI Express 1 (x4) (2.5 Gbps) → SerDes lanes 0-3 0111-1101 Reserved 11101 PCI Express 1 (x1) (2.5 Gbps) → SerDes lane 0 PCI Express 2 (x1) (2.5 Gbps) → SerDes lane 1 SGMII eTSEC2 (x1) (1.25Gbps) → SerDes lane 2 SGMII eTSEC3 (x1) (1.25Gbps) → SerDes lane 32 1111 PCI Express 1 (x2) (2.5 Gbps) → SerDes lanes 0-1 SGMII eTSEC2 (x1) (1.25Gbps) → SerDes lane 2 SGMII eTSEC3 (x1) (1.25Gbps) → SerDes lane 3 2 (default) 1. If the SERDES PLL does not lock, the value of PORDEVSR[IO_SEL] will be 0001 2. Port cfg_sgmii3 must also be logic 0 in addition for eTSEC3 to operate in SGMII mode. 4.5.3.7 CPU boot configuration The CPU boot configuration input, shown in the table below, specifies the boot configuration mode. If cfg_cpu0_boot (LA27) is sampled low at reset, e500 core 0 is prevented from fetching boot code until configuration by an external master is complete. Similarly, cfg_cpu1_boot (LA16) can be used to gate off e500 core 1 from fetching boot code. The external master frees the core 0 and/or core 1 to boot by setting EEBPCR[CPU0_EN] and/or EEBPCR[CPU1_EN] in the ECM CCB port configuration register (EEBPCR). See ECM CCB port configuration register (ECM_EEBPCR), for more information. Note that the value latched on these signals during POR are accessible through the memory-mapped PORBMSR (POR boot mode status register) described in POR boot mode status register (GUTS_PORBMSR). Note also that the values latched on these signals during POR affect all of the PCI Express interfaces' configuration ready mode settings. See Type 0 configuration header registers. When the specific PCI Express module is configured for agent mode and both P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 132 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization cores are configured to be in boot holdoff, the associated configuration register PEX_CFG_READY[CFG_READY] will have a reset value of 1, which indicates a configuration complete status to the transaction layer. Table 4-15. CPU boot configuration Functional signal Reset configuration name Value Meaning (Binary) LA27, LA16 Default (11) cfg_cpu0_boot, cfg_cpu1_boot 00 CPU boot holdoff mode for both cores. The e500 cores are prevented from booting until configured by an external master. 01 e500 core 1 is allowed to boot without waiting for configuration by an external master, while e500 core 0 is prevented from booting until configured by an external master or the other core. 10 e500 core 0 is allowed to boot without waiting for configuration by an external master, while e500 core 1 is prevented from booting until configured by an external master or the other core. 11 Both e500 cores are allowed to boot without waiting for configuration by an external master (default). 4.5.3.8 Boot sequencer configuration The boot sequencer configuration options, shown in the table below, allow the boot sequencer to load configuration data from the serial ROM located on the I2C1 port before the host tries to configure the device. These options also specify normal or extended I2C addressing modes. See Boot sequencer mode, for more information on the boot sequencer. Note that the values latched on these signals during POR are accessible through the memory-mapped PORBMSR (POR boot mode status register) described in POR boot mode status register (GUTS_PORBMSR). Table 4-16. Boot sequencer configuration Functional Signal LGPL3/LFWP_B, LGPL5 Default (11) Reset Configuration Name cfg_boot_seq[0:1] Value (Binary) Meaning 00 Reserved 01 Normal I2C addressing mode is used. Boot sequencer is enabled and loads configuration information from a ROM on the I2C1 interface. A valid ROM must be present. 10 Extended I2C addressing mode is used. Boot sequencer is enabled and loads configuration information from a ROM on the I2C1 interface. A valid ROM must be present. 11 Boot sequencer is disabled. No I2C ROM is accessed (default). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 133 Functional description NOTE When the boot sequencer is enabled, the processor core will be held in reset and thus prevented from fetching boot code until the boot sequencer has completed its task, regardless of the state of the CPU boot configuration signal described in CPU boot configuration. 4.5.3.9 DDR SDRAM type DDR3 requires a different voltage level from DDR2. The table below describes the configuration of the DDR SDRAM type. Table 4-17. DDR SDRAM type Functional signal CFG_DRAM_TYPE Default (1) Reset configuration name Value Meaning (Binary) cfg_dram_type 0 DDR2 1.8 V, CKE low at reset 1 DDR3 1.5 V, CKE low at reset (default) 4.5.3.10 SerDes reference clock configuration As shown in the table below, two options are available for the frequency of the input SerDes reference clock-either a 100-MHz or 125-MHz LVDS differential clock. This one clock is applied to an internal PLL whose output creates the clocks used by all four SerDes lanes. The result is always a 1.25-Gbaud transmission/receive rate on each SGMII lane and a 2.5-Gbaud rate on each PCI Express lane. For any SerDes configuration with PCI Express active, a 100 MHz reference clock must be supplied. Note that the value latched on this signal during POR is accessible through the memorymapped PORDEVSR2 (POR device status 2 register) described in POR device status register 2 (GUTS_PORDEVSR2). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 134 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization Table 4-18. SerDes reference clock configuration Functional signal TSEC_1588_ALARM_OUT1 Default (1) Reset configuration name Value Meaning (Binary ) cfg_srds_refclk 0 SerDes expects a 125 MHz reference clock frequency. 1 SerDes expects a 100 MHz reference clock frequency (default). 4.5.3.11 eTSECn configuration The possible configurations for eTSECn are shown in Table 4-19 and Table 4-20. The values latched on these signals during POR are accessible through the memorymapped PORDEVSR (POR device status register) described in POR device status register (GUTS_PORDEVSR). Note that eTSEC1 is MII, RMII, and RGMII, eTSEC2 is SGMII only, and eTSEC3 is RMII, RGMII, and SGMII. The table below shows the eTSEC1 POR configuration summary. Table 4-19. eTSEC1 POR configuration summary eTSEC1 configuration cfg_tsec_reduce MII 1 01 RMII 0 01 RGMII 0 10 cfg_tsec1_prtcl Table 4-20 shows the eTSEC3 POR configuration summary. Table 4-20. eTSEC3 POR configuration summary SGMII RMII RGMII eTSEC3 configuration cfg_sgmii3 cfg_tsec_reduce 0 - 1 0 1 0 cfg_tsec3_prtcl 01 10 NOTE eTSEC2 is in SGMII mode only. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 135 Functional description 4.5.3.11.1 eTSEC3 SGMII mode The eTSEC3 SGMII mode input, shown in Table 4-21, selects SGMII mode versus parallel mode for enhanced three-speed Ethernet controller (eTSEC) interface 3. If eTSEC3 is configured to run in SGMII mode, none of the parallel mode configuration inputs are pertinent for configuring eTSEC3's interface. When operating in SGMII mode, the parallel interface pins normally used for eTSEC3 interface are not used, but rather the corresponding SGMII Serdes lane is used. Note that the value latched on this signal during POR is accessible through the memorymapped PORDEVSR (POR device status register) described in POR device status register (GUTS_PORDEVSR). Table 4-21. eTSEC3 SGMII mode configuration Functional signal Reset configuration name Value (Binary ) Meaning TSEC_1588_ALARM_OUT2 cfg_sgmii3 Default (1) 0 eTSEC3 Ethernet interface operates in SGMII mode and uses SGMII SerDes lane 3 pins. 1 eTSEC3 Ethernet interface operates in standard parallel interface mode and uses the TSEC3_* pins (default). 4.5.3.11.2 eTSEC1 width The eTSEC width input, shown in Table 4-22, selects standard versus reduced width for three-speed Ethernet controller interfaces operating in parallel mode. The value latched on this signal during POR is accessible through the memory-mapped PORDEVSR (POR device status register) described in POR device status register (GUTS_PORDEVSR). Table 4-22. eTSEC1 width configuration Functional signals EC_MDC Default (1) Reset configuration name cfg_tsec_reduce Value Meaning (Binary ) 0 eTSEC1 Ethernet interface operates in reduced pin mode (either RGMII or RMII mode). 1 eTSEC1 Ethernet interface operates in standard width MII mode (default). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 136 Freescale Semiconductor, Inc. 4.5.3.11.3 eTSEC1 protocol Chapter 4 Reset, Clocking, and Initialization The eTSEC1 protocol inputs, shown in the table below, select the protocol (MII) used by the eTSEC1 controller when operating in parallel mode. Note that the value latched on these signals during POR is accessible through the memory-mapped PORDEVSR (POR device status register) described in POR device status register (GUTS_PORDEVSR). Table 4-23. eTSEC1 protocol configuration Functional signals TSEC1_TXD0, TSEC3_TXD3 Default (11) Reset configuration name Value (Binary) Meaning cfg_tsec1_prtcl[0:1] 00 Reserved 01 The eTSEC1 controller operates using the MII protocol (or RMII if configured in reduced mode as described in eTSEC1 width). 10 The eTSEC1 controller operates using the RGMII protocol if configured in reduced mode as described in eTSEC1 width. 11 Reserved 4.5.3.11.4 eTSEC3 protocol The eTSEC3 protocol inputs, shown in the table below, select the protocol (RMII or RGMII) used by the eTSEC3 controller when operating in parallel mode. This input only affects operation of eTSEC3 if it is not configured to operate in SGMII mode. The value latched on these signals during POR is accessible through the memory-mapped PORDEVSR (POR device status register) described in POR device status register (GUTS_PORDEVSR). Note that parallel mode operation for eTSEC3 is only available when eTSEC1 is configured for reduced-mode width. Table 4-24. eTSEC3 protocol configuration Functional signals UART_RTS0_B, UART_RTS1_B Default (11) Reset configuration name Value (Binary) Meaning cfg_tsec3_prtcl[0:1] 00 Reserved. 01 The eTSEC3 controller operates using the RMII protocol if not configured to operate in SGMII mode. 10 The eTSEC3 controller operates using the RGMII protocol if not configured to operate in SGMII mode. 11 Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 137 Functional description 4.5.3.12 Memory debug configuration The memory debug configuration input, shown in the table below, selects which debug outputs (DDR or LBC memory controller) are driven onto the MSRCID and MDVAL debug signals. Note that the value latched on this signal during POR is accessible through the memorymapped PORDBGMSR (POR debug mode register) described in POR debug mode status register (GUTS_PORDBGMSR). Table 4-25. Memory debug configuration Functional signal CFG_MEM_DEBUG Default (1) Reset configuration name Value Meaning (Binary) cfg_mem_debug 0 Debug information from the enhanced local bus controller (eLBC) is driven on the MSRCID and MDVAL signals 1 Debug information from the DDR SDRAM controller is driven on the MSRCID and MDVAL signals (default). 4.5.3.13 DDR debug configuration The DDR debug configuration input, shown in the table below, enables a DDR memory controller debug mode in which the DDR SDRAM source ID field and data valid strobe are driven onto the ECC pins. ECC checking and generation are disabled in this case. ECC signals driven from the SDRAMs must be electrically disconnected from the ECC I/O pins of the device in this mode. Table 4-26. DDR debug configuration Functional signal Reset configuration name Value Meaning (Binary) CFG_DDR_DEBUG cfg_ddr_debug Default (1) 0 Debug information is driven on the ECC pins instead of normal ECC I/O. ECC signals from memory devices must be disconnected. 1 Debug information is not driven on ECC pins. ECC pins function in their normal mode (default). Note that the value latched on this signal during POR is accessible through the memorymapped PORDBGMSR (POR debug mode register) described in POR debug mode status register (GUTS_PORDBGMSR). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 138 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization 4.5.3.14 General-purpose POR configuration The LBC address/data bus inputs, shown in the table below, configure the value of the general-purpose POR configuration register defined in General-purpose POR configuration register (GUTS_GPPORCR). This register is intended to facilitate POR configuration of user systems. A value placed on LAD[0:15] during POR is captured and stored (read only) in the GPPORCR. Software can then use this value to inform the operating system about initial system configuration. Typical interpretations include circuit board type, board ID number, or a list of available peripherals. Table 4-27. General-purpose POR configuration Functional signals Reset configuration name Value (Binary) Meaning LAD[0:15] No Default cfg_gpinput[0:15] - General-purpose POR configuration vector to be placed in GPPORCR. 4.5.3.15 Engineering use POR configuration The POR configuration inputs shown in the table below may be used in the future to control functionality. It is advised that boards are built with the ability to pullup or pulldown these pins. Note that the value latched on these signals during POR are accessible through the PORDEVSR2, described in POR device status register 2 (GUTS_PORDEVSR2). Table 4-28. Engineering use Functional signals LA[20:22], UART_SOUT[0], MSRCID[4] Default (1_1111) Reset configuration name cfg_eng_use[0:2], cfg_eng_use[3],cfg_eng_use[6] Value Meaning (Binary) 1_1111 Default operation 0_0000-1_1110 Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 139 Functional description 4.5.3.16 eLBC ECC enable configuration The POR configuration input shown in the table below is used to enable eLBC ECC checking on the external local bus interface on boot. Table 4-29. eLBC ECC enable Functional signals Reset configuration name Value (Binary) Meaning MSRCID0 cfg_elbc_ecc 1 Default operation: eLBC ECC checking is enabled. Default (1) 0 eLBC ECC checking is disabled. 4.5.3.17 System speed The SYSCLK speed configuration input, shown in the table below, configures internal logic for proper operation with the SYSCLK clock frequencies in use. The default setting is appropriate for SYSCLK operating at or above 66 MHz. If this configuration is not set properly, behavior of the system may be unreliable. Note that the value latched on this signal during POR is accessible through the memory-mapped PORDEVSR2, described in POR device status register 2 (GUTS_PORDEVSR2). Table 4-30. System speed Functional signals Reset configuration name Value (Binary) Meaning LA28 cfg_sys_speed 0 Reserved Default (1) 1 SYSCLK frequency is at or above 66 MHz (default). 4.5.3.18 Platform speed The platform speed configuration input, shown in the table below, configures internal logic for proper operation with the platform clock frequencies in use. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 140 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization If this configuration is not set properly, behavior of the system may be unreliable. Note that the value latched on this signal during POR is accessible through the memorymapped PORDEVSR2, described in POR device status register 2 (GUTS_PORDEVSR2). Table 4-31. Platform speed Functional signals Reset configuration name Value (Binary) Meaning LA23 Default (1) cfg_plat_speed 0 Platform clock frequency is above 267 MHz and below 300 MHz. 1 Platform clock frequency is at or above 300 MHz (default). 4.5.3.19 Core 0 speed The core 0 speed configuration input, shown in the table below, configures internal logic for proper operation with the core 0 clock frequencies in use. The default setting is appropriate for core 0 operating at or above 500 MHz. For low speed operation (core 0 below 500 MHz) this POR configuration input should be low during HRESET. If this configuration is not set properly, behavior of the system may be unreliable. Note that the value latched on this signal during POR is accessible through the memory-mapped PORDEVSR2, described in POR device status register 2 (GUTS_PORDEVSR2). Table 4-32. Core 0 speed Functional signals Reset configuration name Value (Binary) Meaning LA24 cfg_core0_speed 0 Core 0 clock frequency is less than 500 MHz. Default (1) 1 Core 0 clock frequency is greater than or equal to 500 MHz (default). 4.5.3.20 Core 1 speed The core 1 speed configuration input, shown in the table below, configures internal logic for proper operation with the core 1 clock frequencies in use. The default setting is appropriate for core 1 operating at or above 500 MHz. For low speed operation (core 1 below 500 MHz) this POR configuration input should be low during HRESET. If this configuration is not set properly, behavior of the system may be P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 141 Functional description unreliable. Note that the value latched on this signal during POR is accessible through the memory-mapped PORDEVSR2, described in POR device status register 2 (GUTS_PORDEVSR2). Table 4-33. Core 1 speed Functional signals Reset configuration name Value (binary) Meaning LA25 cfg_core1_speed 0 Core 1 clock frequency is less than 500 MHz. Default (1) 1 Core 1 clock frequency is greater than or equal to 500 MHz (default). 4.5.3.21 DDR speed The DDR speed configuration input, shown in the table below, configures internal logic for proper operation with the DDR data rate in use. The default setting is appropriate for the DDR data rate operating at or above 500 MT/s. For low speed operation (DDR data rate below 500 MT/s), this POR configuration input should be low during HRESET. If this configuration is not set properly, behavior of the system may be unreliable. Note that the value latched on this signal during POR is accessible through the memory-mapped PORDEVSR2, described in POR device status register 2 (GUTS_PORDEVSR2). Table 4-34. DDR speed Functional signals LA26 Default (1) Reset configuration name Value (Binary) Meaning cfg_ddr_speed 0 DDR data rate is less than 500 MT/s. 1 DDR data rate is greater than or equal to 500 MT/s (default). 4.5.3.22 eSDHC card-detect polarity select The eSDHC card-detect polarity select pin sets the polarity of the eSDHC card-detect pin. Note that the value latched on this signal during POR is accessible through the memorymapped PORDEVSR2, described in POR device status register 2 (GUTS_PORDEVSR2). The table below shows the eSDHC card-detect polarity select. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 142 Freescale Semiconductor, Inc. Functional signals TSEC3_TX_EN Default (1) Chapter 4 Reset, Clocking, and Initialization Table 4-35. SDHC card detect polarity select Reset configuration Value name (binary) Meaning cfg_sdhc_cd_pol_sel 0 The eSDHC card-detect polarity is inverted. 1 The eSDHC card-detect polarity is not inverted.(default) 4.5.4 Voltage selection configuration This device supports multiple supply voltages on its I/O supplies. The signals used for these voltage selections are not POR configurations. This section describes the encoding used to select the voltage level for each I/O supply. NOTE Incorrect voltage select settings can lead to irreversible device damage. Follow this section carefully. For proper use, the voltage select device input signals LVDD_SEL, BVDD_VSEL[0:1], and CVDD_VSEL[0:1] must be statically tied to reflect the voltage applied on the LVDD, BVDD, and CVDD I/O supplies respectively. The table below defines the voltage select inputs. Table 4-36. I/O supply voltage select settings Voltage select input Voltage select setting1 LVDD_VSEL 0 1 BVDD_VSEL[0:1] 00 01 10 11 CVDD_VSEL[0:1] 00 01 10 11 Supply Voltage LVDD = 3.3 V LVDD = 2.5 V BVDD = 3.3 V BVDD = 2.5 V BVDD = 1.8 V BVDD = 3.3 V CVDD = 3.3 V CVDD = 2.5 V CVDD = 1.8 V CVDD = 3.3 V Interfaces effected eTSEC1, 3; Ethernet management; 1588 Local Bus, GPIO[8:15] USB, eSDHC, eSPI 1. Logic 0 corresponds with a static tie to GND, while a logic 1 corresponds with a static tie to OVDD (3.3 V). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 143 Functional description As an example, for local bus operation at 2.5 V, the BVDD_VSEL[0] and BVDD_VSEL[1] device inputs must be configured to 01 and thus be tied on the board to GND and OVDD respectively. For 2.5 V operation, tying BVDD_VSEL[0] and BVDD_VSEL[1] to anything except GND and OVDD respectively can lead to irreversible device damage. 4.5.5 Clocking The table below shows the operational frequency of various blocks. Table 4-37. Operational frequency L2 Cache Coherency module eTSEC MPIC eLBC DMA Performance monitor SEC Debug/watchpoint PCI Express I2C DUART GPIO USB controller1 USB controller2 eSDHC eSPI TDM Functional module CCB CCB CCB/2 CCB CCB CCB/2 CCB CCB/2 CCB CCB/2 CCB/2 CCB CCB/2 CCB/2 CCB/2 CCB/2 CCB/2 CCB/2 Operating frequency The following paragraphs describe the clocking within the device. 4.5.5.1 System clock and DDR controller complex clock This device takes a single input clock, SYSCLK, as its primary clock source for the e500 core and all of the devices and interfaces that operate synchronously with the core. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 144 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization As shown in Figure 4-6 , the SYSCLK input (frequency) is multiplied up using a phase lock loop (PLL) to create the core complex bus (CCB) clock (also called the platform clock). The CCB clock is used by virtually all of the synchronous system logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller. The CCB clock also feeds the PLLs in the e500 cores. Note that the divide-by-two CCB clock divider and the divide-by-n CCB clock divider, shown in Figure 4-6 , are located in the DDR and local bus blocks, respectively. The DDR memory controller complex may use the platform clock and thus have operation of both DDR interfaces be synchronous with the platform. Alternately, an independent clock, DDRCLK, may be multiplied up using a separate PLL to create a unique DDR memory controller complex clock. In this case, the DDR complex operates asynchronous with respect to the platform clock. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 145 Functional description div SYSCLK PLL (167MHz-400 MHz) (64MHz-100 MHz) L2 CCB clk TCK RTC LCK[0:1] 2 (10 MHz- 83 MHz) DDRCLK (66 MHz-166 MHz) COP div (267 MHz-667 MHz) PLL USB_CLK USBDR SDHC_CLK SPI_CLK IIC[1-2]_SCL eSDHC SPI I2C TDM_TX_CLK TDM_RX_CLK 2 TDM /n Other IPs PLL e500 Core Complex SAP e LBC /4, /8, /16 DDR SerDes (x4) PLL MCK[0:3] MCK_B[0:3] SD_REF_CLK (100 MHz or 125 MHz) SD_REF_CLK_B (100MHz or 125MHz) PCI Express eTSEC TSEC[1-3]_TX_CLK TSEC[1-3]_RX_CLK TSEC[1-3]_GTX_CLK EC_MDC EC_GTX_CLK125 TSEC_1588_CLK TSEC_1588_CLK_OUT Figure 4-6. Clock subsystem block diagram 4.5.5.2 PCI Express clock The clocks for the PCI Express interfaces are derived from a PLL in the SerDes block. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 146 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization This PLL is driven by a reference clock (SD_REF_CLK/SD_REF_CLK_B) whose input frequency is a function of the bit rate being used as shown in the table below. Table 4-38. High speed interface clocking Interfaces PCI Express 2.5 Gbps Bit Rate 100 MHz Reference clock frequency 4.5.5.2.1 Minimum frequency requirements I/O port selection, describes various high-speed interface configuration options. CCB clock frequency must be considered for proper operation of such interfaces as described below. For proper PCI Express operation, the CCB clock frequency must be greater than: See Link width, for PCI Express interface width details. 4.5.5.3 SGMII clocks Clocks for the SGMII high speed interfaces on this device are derived from a PLL in the SerDes block. This PLL is driven by a reference clock (SD_REF_CLK/SD_REF_CLK_B) whose input frequency may be either 100-MHz or 125-MHz to obtain the required 1.25-Gbaud rate for each lane. The configuration information of the speed of the reference clock must be set properly on the POR configuration pin cfg_srds_sgmii_refclk (see SerDes reference clock configuration). 4.5.5.4 Ethernet clocks The Ethernet blocks operate asynchronously with respect to the rest of the device. These blocks use receive and transmit clocks supplied by their respective PHY chips, plus a 125-MHz clock input for gigabit protocols. Data transfers are synchronized to the CCB clock internally. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 147 Functional description 4.5.5.5 Real time clock As shown in the figure below, the real time clock (RTC) input can optionally be used to clock the e500 core timer facilities. RTC can also be used (optionally) by the device programmable interrupt controller (PIC) global timer facilities. The RTC is separate from the e500 core clock and is intended to support relatively low frequency timing applications. The RTC frequency range is specified in the P1020 QorIQ Integrated Processor Hardware Specifications, but the maximum value should not exceed one-quarter of the CCB frequency. Before being distributed to the core time base, RTC is sampled and synchronized with the CCB clock. The clock source for the core time base is specified by two fields in HID0: time base enable (TBEN), and select time base clock (SEL_TBCLK). If the time base is enabled, (HID0[TBEN] is set), the clock source is determined as follows: • HID0[SEL_TBCLK] = 0, the time base is updated every 8 CCB clocks • HID0[SEL_TBCLK] = 1, the time base is updated on the rising edge of RTC The default source of the time base is the CCB clock divided by eight. For more details, see the PowerPC e500 Core Complex Reference Manual. Timer control register group n (PIC_TCRn), provides additional information on the use of the RTC signal to clock the global timers in the PIC unit. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 148 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization Figure 4-7. RTC and core timer facilities clocking options 4.6 Initialization/applications information Selecting on-chip ROM in boot ROM location, see Table 4-12 , causes the e500 CPU to fetch data from the on-chip ROM. The on-chip ROM is selected by configuring the POR config pins cfg_rom_loc[0:3]. Two different configurations are provided for boot from the on-chip ROM: boot from eSPI and boot from eSDHC. 4.6.1 eSDHC boot This section explains how to boot from eSDHC. It discusses the following: • eSDHC boot overview • eSDHC boot features • SD/MMC card data structure P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 149 Initialization/applications information • eSDHC controller initial configuration • eSDHC controller boot sequence • eSDHC boot error handling 4.6.1.1 eSDHC boot overview This device is capable of loading initialization code from a memory device that is connected to the eSDHC controller interface. This device can be either a SD card, or MMC card or other variants compatible with these devices. The term SD/MMC will be used when referring to the memory device. Boot from eSDHC is supported by the device using an on-chip ROM which contains the basic eSDHC device driver and the code to perform block copy from SD/MMC to any target memory. Selecting on-chip ROM in boot ROM location (see Table 4-12) causes the e500 CPU to fetch data from the on-chip ROM. The on-chip ROM is selected by configuring the POR config pins cfg_rom_loc[0:3]. Prior to boot, the user must ensure that the SD/MMC card to boot from is inserted. After the device has completed the reset sequence, if the ROM location selects the onchip ROM eSDHC Boot configuration, the e500 core starts to execute code from the internal on-chip ROM. The e500 core configures the eSDHC controller, enabling it to communicate with the external SD/MMC card. The SD/MMC card should contain a specific data structure with control words, device configuration information and initialization code. The on-chip ROM boot code uses the information from the SD/MMC card content to configure the device, and to copy the initialization code to a target memory device (for example, the DDR) through the eSDHC interface. After all the code has been copied, the e500 core starts to execute the code from the target memory device. There are several different ways a user may utilize the eSDHC boot feature. The simplest is for the on-chip ROM to copy an entire operating system boot image into system memory, and then jump to it to begin execution. However, this may be many megabytes and in some situations may be sub-optimal, since only 1-bit mode is used during booting. A more advanced option is for the on-chip ROM to only copy a small user-customized subroutine, which configures the eSDHC in an optimal way. The user-customised subroutine then copies the rest of the boot code potentially much faster than the on-chip ROM software can achieve. For example, the user-customised subroutine may utilize 4bit or 8-bit eSDHC interfaces, or support new SD or MMC format revisions, or increase the external clock frequency based on knowledge of the exact frequency that the device is operating at. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 150 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization 4.6.1.2 eSDHC boot features The main features are as follows: • Provides mechanism to load initialization code from the following external devices: • SD memory cards, including the memory portion of SD Combo cards (up to and including version 2.0) • MMC, RS-MMC and MMCplus (up to and including version 4.2) • SDHC cards (SD High Capacity, from 4 GByte to 32 GByte) • Boot from the following devices is not supported • SDIO and miniSDIO cards which are not SD Combo cards and consequently have no memory • Locked (password-protected) SD/MMC cards • Secured Mode of SD cards (SD Card Specification Part 3: Security Specification) • Simple data structure in SD/MMC card • BOOT signature will be checked to validate that the SD/MMC card contains valid code • Supports variable code length in SD/MMC card • Flexible target memory device • Supports target memory configuration controlled by the user • Only 1-bit operation is supported for boot (even if the SD/MMC card supports 4 or 8-bit parallel access). • Initial setting will use a serial clock below 400 kHz; the SD/MMC internal registers are read by initialization code and parsed to determine the optimal clock frequency supported by the SD/MMC card inserted. • High speed cards are supported (up to 50 MHz SD and 52 MHz MMC). • Control word will allow for user modification • There must be precisely one device connected on the eSDHC bus. In particular, multiple MMC devices sharing the one bus are not supported. • Compatible with FAT12/FAT16/FAT32 SD/MMC filesystems (provided ≤ 40 configuration words are used prior to copying user's code to system memory). • Redundancy to support SD/MMC bad blocks, by searching for the BOOT signature in up to 24 blocks, and trying the next block if the BOOT signature is not found, or if a read CRC error is found. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 151 Initialization/applications information 4.6.1.3 SD/MMC card data structure The SD/MMC card should contain the initialization code length in bytes, source address in the SD/MMC card, destination address in the target memory device, execution starting address, and multiple configuration words with pairs of target address and its respective data. The figure below shows the required SD/MMC card data structure. Figure 4-8. SD/MMC card data structure The table below describes the SD/MCC card data structure. Table 4-39. SD/MMC card data structure Address 0x00-0x3F 0x40-0x43 0x44-0x47 0x48-0x4B 0x4C-0x4F Data bits [0-31] Reserved. BOOT signature This location should contain the value 0x424F_4F54, which is the ascii code for BOOT. The boot loader code will search for this signature. If the value in this location doesn't match the BOOT signature, it means that the SD/MMC card doesn't contain a valid user code. In such case the boot loader code will disable the eSDHC and will issue a hardware reset request of the SoC by setting RSTCR[HRESET_REQ]. Reserved User's code length Number of bytes in the user's code to be copied. This must be a multiple of the SD/MMC card's block size (and the user's code zero-padded if necessary to achieve that length). User's code length ≤ 2 GBytes. Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 152 Freescale Semiconductor, Inc. Address 0x50-0x53 0x54-0x57 0x58-0x5B 0x5C-0x5F 0x60-0x63 0x64-0x67 0x68-0x6B 0x6C-0x7F 0x80-0x83 0x84-0x87 0x88-0x8B 0x8C-0x8F ... 0x80 + 8x(N-1) 0x80 + 8x(N-1)+4 ... Chapter 4 Reset, Clocking, and Initialization Table 4-39. SD/MMC card data structure (continued) Data bits [0-31] Source Address. Contains the starting address of the user's code as an offset from the SD/MMC card starting address. In Standard Capacity SD/MMC Cards, the 32-bit Source Address specifies the memory address in byte address format. This must be a multiple of the SD/MMC card's block size. In High Capacity SD Cards (> 2 GBytes), the 32-bit Source Address specifies the memory address in byte address format as well. However, it must be a multiple of block length, which is fixed to 512 bytes as stated in the SD High Capacity specification. Reserved Target Address Contains the target address in the system's local memory address space in which the user's code will be copied to. This is a 32-bit effective address. The core is configured in such a way that the 36-bit real address is equal to this (with 4 most significant bits zero). Reserved Execution Starting Address Contains the jump address in the system's local memory address space into the user's code first instruction to be executed. This is a 32-bit effective address. The core is configured in such a way that the 36-bit real address is equal to this (with 4 most significant bits zero). Reserved N. Number of Config Address/Data pairs. Must be 1≤ N≤ 1024 (but is recommended to be as small as possible). Reserved. Config Address 1 Config Data 1 Config Address 2 Config Data 2 Config Address N1 Config Data N (final Config Data N optional) User's code. Note that user's code must start on a 512-byte boundary. 1. N ≤ 40 if compatibility with FAT12/FAT16/FAT32 filesystems is required. Refer to Notes on compatibility with FAT12/ FAT16/FAT32 filesystems for details. 4.6.1.3.1 SD/MMC configuration words section The configuration words section is comprised of Config Address and Config Data pairs of adjacent 32-bit fields. These are typically used to configure the local access windows and the target memory controller's registers. They are therefore system-dependent, as they need to be aware of the type and configuration of memory in a particular system. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 153 Initialization/applications information The Config Address field has two modes that are selected by the least significant bit in the field (CNT). If the CNT bit is clear, then the 30 most significant bits are used to form the address pointer and the Config Data contains the data to be written to this address. If the CNT bit is set then the 30 most significant bits are used for control instruction. This flexible structure allows the user to configure any 4-byte aligned memory mapped register, perform control instructions, and specify the end of the configuration stage. Note that it is illegal to change the content of the CCSRBAR by using this mechanism. Any attempt to do so will cause the boot process to hang. The upper 4 most-significant address bits of the 36-bit address are always zero. Consequently the configuration words can only access memory in the lowest 4-GByte segment of memory. However, since by default CCSRBAR maps all memory mapped registers within the lowest 4-GByte segment of memory, and the user is prohibited from changing CCSRBAR with a configuration access, this is not an issue. The Config Address structure is shown in the table below. Table 4-40. Config address fields 01 2 CNT = 0 Address CNT = 1 EC DLY - 2 3 31 90 - CNT CNT Table 4-41 defines the Config Address bits when CNT = 0 (address mode), and Table 4-42 describes the Config Address bits when CNT = 1. Table 4-41. Config address field description, CNT = 0 Bits Name 0-29 Address 30 - 31 CNT Description Address bits 0-29. The data in the Config Data field is copied by the e500 core to this address. The two least significant bits of the address (30:31) are always considered to be zero, as are the upper 4 bits of the 36-bit address. Reserved. Must be zero. Control. Select between Address mode and Control mode. 0 Address mode 1 Control mode P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 154 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization Table 4-42. Config address field description, CNT = 1 Bits Name 0 EC 1 DLY 2-30 31 CNT Description End Configuration. Indicates the end of the configuration stage. Valid only if bit CNT is set. 0 Not the last Config Address field. 1 The Last Config Address field. The e500 core will stop the configuration stage and start to copy the user's code. This must be set for Config Address Word N, and not be set for Config Address words prior to Config Address Word N. Delay. Instruct the e500 core to perform delay according to the number that is specified in the adjacent Config Data field. The adjacent Config Data field provides the delay measured in terms of the number of 8 CCB clocks. Valid only if bit CNT is set. 0 No delay. 1 Delay. Reserved. Must be zero. Control. Select between Address mode and Control mode. (0 Address mode) 1 Control mode When CNT = 1, bits 0-29 select the control instruction. Only one bit in the range of bits 0-29 can be set at any specific control instruction. A control instruction with bits 0-29 all cleared is also illegal. 4.6.1.3.2 Notes on compatibility with FAT12/FAT16/FAT32 filesystems Depending upon application, compatibility may be desired between the SD/MMC Card data structure defined here and the FAT12, FAT16 or FAT32 filesystems (documented in SD Card Specifications Part 2 - File System Specification v2.0, among other places). This compatibility is possible, but imposes a limit on the number of Configuration Words that can be parsed by the processor prior to fetching the user's code. Compatibility is achieved by ensuring that the entire data structure of Control Words and Configuration Words is contained within the first 446-byte (0x1BE) Master Boot Record code area of the filesystem. Given that Configuration Words start at address 0x80, and all Configuration Words (except the last one with EC = 1 to end the configuration) occupy 8 bytes per Configuration Address/Data pair, this imposes the limit of a maximum of 40 Configuration Address words. More Configuration Words can be used in applications for which compatibility with the FAT Master Boot Record is not required. If exactly 40 Configuration Address words are used and FAT12/FAT16/FAT32 compatibility is required, then the final Configuration Data word must be omitted to ensure that the data structure fits in less than 446 bytes. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 155 Initialization/applications information Note that FAT12, FAT16 and FAT32 standards impose additional requirements on the data structures that must be present on the SD/MMC card, such as Partition Tables and a fixed Signature Word at the end of the Master Boot Record. These features are not interpreted or required by the eSDHC boot process, and are outside the scope of this document. Furthermore, FAT12 and FAT16 define a boot sector with defined fields in the first 0x36 addressable bytes (which does not conflict with the SD/MMC Card Data Structure for boot from SD/MMC defined in this document). Therefore FAT12 and FAT16 filesystems are completely compatible with the defined data structure, even if they also contain a FAT boot sector. However, FAT32 defines a boot sector with defined fields in the first 0x52 addressable bytes. Therefore, FAT32 filesystem compatibility is only possible if used in a system in which this boot sector information is not required. Also note that the user code is copied from one sequential area of SD/MMC card memory space specified by the Source Address. The boot ROM software does not look for or parse any File Allocation Table, and furthermore, the boot ROM software assumes that the User Code is in one contiguous range of memory addresses. 4.6.1.4 eSDHC controller initial configuration The eSDHC controller configuration is used by the boot ROM software. After the boot from eSDHC has finished, the user can change this configuration for other uses of the eSDHC interface. The boot ROM software also changes some of this configuration automatically depending upon the features supported by the SD/MMC card that is connected. The eSDHC controller is initially configured to operate in the following configuration: • Address Invariant Mode (eSDHC.PROTCTL[EMODE] = 10) • SDHC_DAT[3] does not monitor card insertion. The GPIO8/ SDHC_CD_B pin is used for card detect (eSDHC.PROTCTL[D3CD] = 0 and Global_Utilities.PMUXCR[SDHC_CD] = 1). • 1-bit Mode (eSDHC.PROTCTL[DTW] = 00) • SDCLK at 400 kHz or below, but higher than 100 kHz (for platform frequency up to 400 MHz, and therefore eSDHC base clock frequency up to 200 MHz). This is done with eSDHC.SYSCTL[SDCLKFS] = 0x20 and eSDHC.SYSCTL[DVS] = 0xC, for a divisor of 832. • There must be precisely one device connected on the eSDHC bus (and this device must be inserted prior to boot). Multiple MMC devices sharing the one bus are not supported. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 156 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization • The bus operates in push-pull mode (device pads drive both logic "0" and logic "1" as appropriate). If an MMC card is to be connected, then weak external pull-ups are required on the SDHC_CMD and SDHC_DAT[] pins in order to interface with the MMC open-drain mode during initialization. • The eSDHC DMA engine is not used for Control or Configuration Word accesses; instead, all eSDHC data transfers are initiated by the processor core polling eSDHC.PRSSTAT[BRR] and accessing data through the DATPORT register (XFERTYP[DMAEN] = 0). The eSDHC DMA engine is used for user code accesses. 4.6.1.5 eSDHC controller boot sequence The code in the eSDHC Boot ROM configuration performs the following sequence of events: 1. The eSDHC controller is configured as per eSDHC controller initial configuration. 2. Card-detect. 3. The SD/MMC card is reset. 4. SD/MMC card voltage validation is performed. 5. SD/MMC card identification. 6. With CMD9, the CSD (Card-Specific Data) register of the SD/MMC card is read. 7. Based on the values returned from the SD/MMC card's CSD register, the eSDHC's registers are updated to reflect the maximum clock frequency jointly supported by the eSDHC controller, and the SD/MMC card connected to it. 8. The eSDHC begins reading the SD/MMC data structure from the card. 9. The eSDHC begins fetching the User Code from the card. 10. If either the BOOT signature is not found at memory offset 0x40, or if when reading the Control and Configuration Words or the User's Code a read CRC error is detected, then it may be due to a bad block on the SD/MMC memory card. To counteract this and provide error resilience, if this occurs the eSDHC returns to step 8 , fetching data from an address 0x200 greater than the previously fetched address. For example, if there have been i failed attempts, then on the following try the BOOT signature is checked at offset 0x40 + i x 0x200. If this sequence fails 24 times, the system boot is deemed to have failed. 11. The processor core waits until the User Code DMA transfer is complete. 12. The processor core jumps to the Execution Starting Address to begin execution of the user's code. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 157 Initialization/applications information 4.6.1.6 eSDHC boot error handling If at any stage the boot loader code detects an error and cannot continue, it will disable the eSDHC and will issue a hardware reset request of the SoC by setting RSTCR[HRESET_REQ]. This may occur in any of the following scenarios: • BOOT signature not found at offset 0x40 or CRC error on any of the data read by the eSDHC 24 times. • Timeout while waiting for the SD/MMC card to respond at any stage. • No card inserted. • Incorrect type of card inserted that is not supported for boot (such as CE-ATA). • There is no common protocol, voltage or frequency mutually supported by the SD/ MMC card and the eSDHC. • The eSDHC reads as far as the source address (specified by the control word of the SD/MMC data structure) without seeing a EC = 1 configuration word. The boot loader code supports redundancy, which allows boot to succeed even in the presence of SD/MMC bad blocks. It does this by searching for the BOOT signature in up to 24 locations, and trying the next block if the BOOT signature is not found, or if a read CRC error is found. Each location tried is at a fixed offset of 512 bytes (0x200) from the previous (unsuccessful) offset, irrespective of the actual block size of the SD/MMC card. For reference, the figure below shows an example SD/MMC memory card data structure that can be used for maximum SD/MMC card data redundancy. Note that if 0x40 + 8 x (N - 1) + 4 ≥ 0x200 (where N is the number of configuration words), then care needs to be taken to ensure that the configuration words at 0x40 + i x 0x200 (for all 2 ≤ i ≤ 24) must not contain the BOOT signature. This ensures that the boot loader code does not mistakenly detect a BOOT signature. This also reduces the number of copies of boot code that can be used on one device. Each copy of the control/configuration words would generally be identical except for the pointer to the source address (offset 0x50) of the SD/MMC card, which may be different for each copy. If the user's code section is sufficiently large that 24 copies of it do not fit in the capacity of the SD/MMC card (or if the SD/MMC card capacity must also be utilized for functional features other than system boot), then it may still be desirable to still support up to 24 copies of the control/configuration words, but only have them reference a limited number of user's code sections. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 158 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization Figure 4-9. SD/MMC card data structure for maximum redundancy 4.6.2 eSPI boot ROM This section explains how to boot from eSPI. It discusses the following: • eSPI boot overview • Features • EEPROM data structure • eSPI controller configuration 4.6.2.1 eSPI boot overview This device is capable of loading initialization code from a memory device that is connected to the eSPI controller interface. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 159 Initialization/applications information This device can be either an EEPROM or a serial flash with an eSPI-compatible interface. The term EEPROM will be used when referring to the memory device. The eSPI controller supports RapidS full clock cycle operation and Winbond dual output read serial interface, but these modes are not enabled for boot by the on-chip ROM. Boot from eSPI is supported by the device using an on-chip ROM which contains the basic eSPI device driver and the code to perform block copy from eSPI EPROM to any target memory. Selecting on-chip ROM in boot ROM location, see Table 4-12, causes the e500 CPU to fetch data from the on-chip ROM. The on-chip ROM is selected by configuring the POR config pins cfg_rom_loc[0:3]. After the device has completed the reset sequence, if the ROM location selects the onchip ROM eSPI Boot configuration, the e500 core starts to execute code from the internal on-chip ROM. The e500 core configures the eSPI controller, enabling it to communicate with the external EEPROM. The EEPROM should contain a specific data structure with control words, device configuration information and initialization code. The on-chip ROM boot code uses the information from the EEPROM content to configure the device, and to copy the initialization code to a target memory device (for example, the DDR) through the eSPI interface. After all the code has been copied, the e500 core starts to execute the code from the target memory device. There are several different ways a user may utilize the eSPI boot feature. The simplest is for the on-chip ROM to copy an entire operating system boot image into system memory, and then jump to it to begin execution. However, this may be many megabytes and in some situations may sub-optimal. A more advanced option is for the on-chip ROM to only copy a small user-customised subroutine, which configures the eSPI in an optimal way. The user-customised subroutine then copies the rest of the boot code potentially much faster than the on-chip ROM software can achieve. For example, the user-customised subroutine may utilize Atmel RapidS or Winbond dual output eSPI modes. 4.6.2.2 Features The main features are as follows: • Provides mechanism to load initialization code from external eSPI EEPROM • Simple data structure in eSPI EEPROM • BOOT signature will be checked to validate that the EEPROM contains valid code • Supports variable code length in EEPROM • Flexible target memory device • Supports target memory configuration controlled by the user P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 160 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization • Supports standard eSPI interface EEPROMs with read instruction code 0x03 followed by a 2-byte address (16-bit addressable EEPROMs) or 3-byte address (24bit addressable EEPROMs). • Initial setting will generate a serial clock below 5 MHz; the control word will allow for user modification of clock frequency. 4.6.2.3 EEPROM data structure The EEPROM should contain the initialization code length in bytes, source address in the eSPI EEPROM, destination address in the target memory device, execution starting address, and multiple configuration words with pairs of target address and its respective data. The figure below shows the required eSPI EEPROM data structure. Figure 4-10. eSPI EEPROM data structure The table below describes the eSPI EEPROM data structure. Table 4-43. eSPI EEPROM data structure Address 0x00-0x3F 0x40-0x43 Data bits [0-31] Reserved. BOOT signature. This location should contain the value 0x424F0_4F54, which is the ASCII code for BOOT. The eSPI loader code will search for this signature, initially in 24-bit addressable mode. If the value in this location doesn't match the BOOT signature, then the EEPROM is accessed again, but in 16-bit mode. If the value in this location still does not match the BOOT signature, it means that the eSPI device doesn't contain a valid user code. In such case the eSPI loader code will disable the eSPI and will issue a hardware reset request of the SoC by setting RSTCR[HRESET_REQ]. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 161 Initialization/applications information Table 4-43. eSPI EEPROM data structure (continued) Address 0x44-0x47 0x48-0x4B 0x4C-0x4F 0x50-0x53 0x54-0x57 0x58-0x5B 0x5C-0x5F 0x60-0x63 0x64-0x67 0x68-0x6B 0x6C-0x7F 0x80-0x83 0x84-0x87 0x88-0x8B 0x8C-0x8F ... 0x80 + 8x(N-1) 0x80 + 8x(N-1) + 4 ... Data bits [0-31] Reserved User's code length. Number of bytes in the user's code to be copied. Must be a multiple of 4. 4 ≤ User's code length ≤ 2 Gbytes. Reserved Source Address. Contains the starting address of the user's code as an offset from the EEPROM starting address. In 24-bit addressing mode, the 8 most significant bits of this should be written to as zero, because the EEPROM is accessed with a 3-byte (24-bit) address. In 16-bit addressing mode, the 16 most significant bits of this should be written to as zero. Reserved Target Address. Contains the target address in the system's local memory address space in which the user's code will be copied to. This is a 32-bit effective address. The core is configured in such a way that the 36-bit real address is equal to this (with 4 most significant bits zero). Reserved Execution Starting Address. Contains the jump address in the system's local memory address space into the user's code first instruction to be executed. This is a 32-bit effective address. The core is configured in such a way that the 36-bit real address is equal to this (with 4 most significant bits zero). Reserved N. Number of Config Address/Data pairs. Must be 1≤N≤1024 (but is recommended to be as small as possible). Reserved. Config Address 1 Config Data 1 Config Address 2 Config Data 2 Config Address N Config Data N (Final Config Data N optional) User's Code 4.6.2.3.1 EEPROM configuration words section The configuration words section is comprised of Config Address and Config Data pairs of adjacent 32-bit fields. These are typically used to configure the local access windows and the target memory controller's registers. They are therefore system-dependent, as they need to be aware of the type and configuration of memory in a particular system. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 162 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization The config address field has two modes that are selected by the least significant bit in the field (CNT). If the CNT bit is clear, then the 30 most significant bits are used to form the address pointer and the Config Data contains the data to be written to this address. If the CNT bit is set then the 30 most significant bits are used for control instruction. This flexible structure allows the user to configure any 4-byte aligned memory mapped register, perform control instructions, and specify the end of the configuration stage. Note that it is illegal to change the content of the CCSRBAR by using this mechanism. Any attempt to do so will cause the boot process to hang. The upper 4 most-significant address bits of the 36-bit address are always zero. Consequently the configuration words can only access memory in the lowest 4-GByte segment of memory. However, since by default CCSRBAR maps all memory mapped registers within the lowest 4-GByte segment of memory, and the user is prohibited from changing CCSRBAR with a configuration access, this is not an issue. The Config Address structure is shown in the table below. Table 4-44. Config address fields 0123 C Address N T = 0 CEDC- NCL F T Y = 1 30 31 -C N T C N T Table 4-45 shows the config address field description, CNT = 0. Table 4-45. Config address field description, CNT = 0 Bits Name 0-29 Address 30 - 31 CNT Description Address bits 0-29. The data in the Config Data field is copied by the e500 core to this address. The two least significant bits of the address (30-31) are always considered to be zero, as are the upper 4 bits of the 36-bit address. Reserved. Must be zero. Control. Select between Address mode and Control mode. 0 Address mode 1 Control mode Table 4-46 shows the Config Address field description, CNT = 1. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 163 Initialization/applications information Table 4-46. Config address field description, CNT = 1 Bits 0 Name EC 1 DLY 2 CF Description End Configuration. Indicates the end of the configuration stage. Valid only if bit CNT is set. 0 Not the last Config Address field. 1 The Last Config Address field. The e500 core will stop the configuration stage and start to copy the user's code. This must be set for Config Address Word N, and not be set for Config Address words prior to Config Address Word N. Delay. Instruct the e500 core to perform delay according to the number that is specified in the adjacent Config Data field. The adjacent Config Data field provides the delay measured in terms of the number of 8 CCB clocks. Valid only if bit CNT is set. 0 No delay. 1 Delay. Change frequency. Instruct the e500 core to perform sequence of operations to setup the eSPI CS0 mode register with the frequency related (PM and DIV16) bits as defined by the user. The adjacent Config Data field will be written to the eSPI mode register. Software will use DIV16 and PM bits and mask all other bits such that they will not change. Software will perform the necessary steps which are required by the eSPI controller before and after changing the eSPI mode register. This only takes effect after all of the Configuration and Control words have been read. 3-30 31 CNT Reserved. Must be zero. Control. Select between Address mode and Control mode. 0 Address mode 1 Control mode NOTE: When CNT = 1, bits 0-29 select the control instruction. Only one bit in the range of bits 0-29 can be set at any specific control instruction. A control instruction with bits 0-29 all cleared is also illegal. 4.6.2.4 eSPI controller configuration The eSPI controller configuration is used by the eSPI boot ROM software. After the boot from eSPI has finished, the user can change this configuration for other uses of the eSPI interface. The eSPI controller is configured to operate in master mode. The eSPI chip select 0 (SPI_CS[0]) must be connected to the EEPROM CS_B and selectively enables the EEPROM. The figure below shows the external signal connection. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 164 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization SPIMOSI SPIMISO SPICLK SPI_CS[0] EEPROM D (Data In) Q (Data Out) C (Serial Clock) Vcc S_B (Chip Select) Vcc HOLD_B Figure 4-11. External signal connection The eSPI controller is configured by the on-chip ROM code. The controller is configured as follows: • Data is shifted out data on SPIMOSI during the falling edge of SPICLK. It samples data in from SPIMISO during the rising edge of SPICLK. • The clock is low when the line is idle. • It uses 8-bit length characters. • The platform clock is divided by 256. For example, when the platform clock is configured to 533 MHz, the SPICLK will run at 2.08 MHz. (Note that frequency setting can be changed by using the CF control word, as explained in the EEPROM configuration words section.) • The MSB is sent and received first. For default eSPI CS0 mode register (SPMODE0) configuration, see eSPI CS0 mode register (ESPI_SPMODE0). During ROM boot, the ROM code needs to change the reset value of eSPI CS0 mode register to 0x3117_2210. The ROM code will initially use the eSPI controller to generate standard read instruction code 0x03 followed by a 3-byte address for every non-sequential read operation (reading from a location which is not sequential to the last byte read). For sequential read operation, toggling the eSPI clock will cause the eSPI EEPROM to present the content of the next address location. The serial EEPROM must have an eSPI compatible interface with read instruction code 0x03 followed by a 2 or 3-byte address. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 165 Initialization/applications information 16-bit addressable EEPROM memories are supported and detected automatically by the boot code. This is accomplished by the boot code trying 16-bit mode if it fails to find the "BOOT" signature when in 24-bit mode. The figure below shows the read instruction timing diagram for normal (not Atmel RapidS or Winbond Dual Output) modes of operation with a 24-bit addressable eSPI memory. With 16-bit addressable eSPI memories, only a 16-bit address is transmitted, and valid data is received from the EEPROM on the 24th SPICLK cycle rather than the 32nd SPICLK cycle for 24-bit addressable memories. SPICLK 0 1 2 3 4 5 6 7 8 9 10 11 30 31 32 33 34 35 (Chip Select) S_B SPIMOSI SPIMISO 8-bit Instruction 24-bit Address 0x03 23 22 21 MSB High-Impedance 10 Data from EEPROM MSB Figure 4-12. Read instruction timing diagram (24-bit addressable eSPI memory) 4.6.3 Default e500 addressing during system boot During boot from the on-chip ROM (for boot targets of either eSPI or SD/MMC), the user specifies 32-bit addresses for several fields (Target Address for copying the user's code, and the Execution Starting Address). This section describes how these 32-bit effective addresses are translated into 36-bit real addresses and the associated address translation and mapping. The L2 cache remains disabled as per its power-on-reset state. The e500 Level 1 and Level 2 MMU configuration is left as per defaults, with the exception that the following TLB1 Entry 1 is also created (in addition to the default TLB1 Entry 0 4 kByte page at 0x0_FFFF_Fnnnn): • V = 1 (valid) P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 166 Freescale Semiconductor, Inc. Chapter 4 Reset, Clocking, and Initialization • TS = 0 (address space 0) • TID = 0x00 (global) • EPN[32:51] = 0x00000 • RPN[32:51] = 0x00000 • SIZE[0:3] = 1011 (4 GByte) • SX/SR/SW = 111 (Full supervisor mode access allowed) • UX/UR/UW = 000 (No user mode access allowed) • WIMGE = 01110 (Cache-inhibited, Memory coherency required, Guarded) • X0-X1 = 00 • U0-U3 = 0 • IPROT = 1 (Page is protected from invalidation) This configuration results in a 32-bit byte address with a 0-bit effective page number. Therefore the 36-bit real address is equal to the 32-bit effective address, with the 4 MSbits of the 36-bit real address equal to 0. The on-chip ROM code does not setup any Local Access Windows. Access to CCSR address space (and therefore by extension, also access to the on-chip ROM) does not require a Local Access Window. It is the user's responsibility to setup a local access window through a Control Word address/data pair for the desired Target Address and Execution Starting Address (which will typically be in either DDR or Local Bus memory space). Note that any such local access window configured at this time must have the 4 MSbits of the address equal to 0. This is due to the 32-bit addressing enabled by the e500 MMUs as described above. The user can reconfigure the system in the user code portion based on system requirements. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 167 Initialization/applications information P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 168 Freescale Semiconductor, Inc. Chapter 5 e500 Core Integration Details e500 core integration and the core complex bus (CCB) describes hardware aspects of that integration and provides links to chapters that discuss functionality in which core and SoC operations interact. 5.1 Overview This chapter describes how the core is integrated into the SoC. e500 core integration and the core complex bus (CCB) describes hardware aspects of that integration and provides links to chapters that discuss functionality in which core and SoC operations interact. Such topics include reset, power management, interrupt management, and debug. This chapter also lists SoC-specific details of the core's programming model. For example, the e500 programming model defines the processor version register (PVR), system version register (SVR), and special-purpose registers (SPRs) that respectively identify the version and revision of the core and of the integrated device. These values are provided in Summary of core integration details , and additional links are provided to other chapters that provide a context for a discussion of these registers. The section Register model integration details in Table 5-1 describes a few aspects of the core programming model that has SoC-specific behavior that cannot be fully understood by reading the e500 Reference Manual alone. General information about e500 core functionality can be found in this chapter and in the following documentation: • The PowerPC e500 Core Family Reference Manual (referred to here as the e500 Reference Manual) provides detailed information about the functions and features of the core. In particular, it describes details about how architecture-defined features are implemented. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 169 e500 core block diagram • The "e500 Core Complex Bus (CCB) and System Integration" chapter in the e500 Reference Manual describes core-to-SoC integration issues from the perspective of the e500 core. • The EREF: A Programmer's Reference Manual for Freescale Embedded Processors (Including the e200 and e500 Families) describes in detail features defined by the Power ISA and Freescale EIS (referred to generically as the architecture). Unless otherwise stated in the e500 Reference Manual, e500 features are implemented as defined by the architecture and described in the EREF. • How the integrated device implements e500 core features, including specific registers and register fields, is summarized in Summary of core integration details. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 170 Freescale Semiconductor, Inc. 5.2 e500 core block diagram The chip core complex block diagram shows how the functional units operate independently and in parallel. Note that this is a conceptual diagram that does not attempt to show how these features are physically implemented. Freescale Semiconductor, Inc. P1020 QFoirgIQurInete5g-1ra.teed50P0rocceosrseocr oRmefeprleenxcebMloacnkuadl,iaRgevra. 6m, 01/2013 Additional Features Time Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Power Management Performance Monitor One instruction issue to BIQ per clock Reservation Station Branch Unit Condition Register CR Field Rename Buffers (14) Reservation Station Simple Unit 1 (32-/64 Bit) Instruction Unit Fetch Stages Instruction Queue (12 instructions) Branch Prediction Unit CTR BTB LR 512 Entry 128-Bit (4 Instructions) Program order is maintained by passing instructions from the IQ to the CQ at dispatch. Branch Issue Queue (BIQ) Reservation Station Simple Unit 2 (32 Bit) Two Instruction Dispatch (1 BIQ, 2 GIQ) Two instructions issue to GIQ per clock General Issue Queue(GIQ) MAS Registers Reservation Station Multiple Unit 64-/32 Bit Each execution unit can accept one instruction per cycle. GPR File Rename Buffers (14) 32-/64-Bit Reservation Station Load Store Unit 64-/32-Bit Memory Unit 32-Kbyte I Cache Tags L1 Instruction MMU 4-entry I-L1VSP 64-entry I-L1TLB4K L2MMUs Unified 16-entry TLB array (TLB1) 256-entry TLB array (TLB0) L1 Data MMU 4-entry D-L1VSP 64-entry D-L1TLB4K Chapter 5 e500 Core Integration Details CRF Bus Completion Queue (14 Entry) Completion Bus GPR Operated Bus L1 Store Load Miss Queue Queue Data Line Data Write Fill Buffer Buffer Tags 32-Kbyte D Cache Instruction Line Fill Buffer Maximum Two Instructions Retire per Cycle Core Interface Unit Core Complex Bus 171 e500 core integration and the core complex bus (CCB) 5.3 e500 core integration and the core complex bus (CCB) The CCB is the hardware interface between the core and the SoC. With a few exceptions, the user cannot access these internal signals directly. This figure shows a selection of CCB signals that are discussed in various places in this manual and in the core reference manual, because understanding how they work helps to understand the functionality of this chip. Figure 5-2. e500 core integration Aspects of the e500 chip integration are summarized as follows: • Reset The core directs and coordinates device's hard and soft resets and the power-on reset (POR) sequence, power-on reset configuration, and initialization. Core integration of the reset signals shown in Figure 5-2 is described in the chapters Reset, Clocking, and Initialization and Global Utilities. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 172 Freescale Semiconductor, Inc. • Clocking and timers Chapter 5 e500 Core Integration Details Integration details of the CCB clocking signals are described in Reset, Clocking, and Initialization. Additional details regarding the timer configuration are described in Summary of core integration details. • Cache and memory-mapped SRAM The e500 cache implementation interacts with the SoC's L2 cache. In particular, the core implements a number of instructions that interact with the L2 cache implementation, which are described in the e500 Reference Manual and in the EREF. L2 Look-Aside Cache/SRAM describes the SoC's L2 cache. Figure 5-2 shows the e500 signals that interface with the L2 cache. • e500 coherency module (ECM) The ECM, described in e500 Coherency Module, facilitates communication between the core, the L2 cache, and the other blocks that comprise the coherent memory domain of the SoC. The ECM provides a mechanism for I/O-initiated transactions to snoop the core complex bus (CCB) of the core to maintain coherency across cacheable local memory. It also provides a flexible, easily expandable switch-type structure for coreand I/O-initiated transactions to be routed (dispatched) to target modules on the device. The CCB is described in the "Core Complex Bus (CCB) and System Integration" chapter of the e500 Reference Manual. • Interrupts The e500 core handles the hardware interrupts that are generated from SoC peripheral logic, typically by error conditions encountered from within blocks on the integrated device. Programmable Interrupt Controller (PIC) describes the programmable interrupt controller, which prioritizes interrupt requests to the core. Figure 5-2 shows the e500 signals that interface with the PIC. • Power management The core's HID0[NAP, DOZE,SLEEP] can be used to assert nap, doze, and sleep output signals to initiate power-saving modes at the integrated device level. Figure 5-2 shows the e500 signals, which interact with the SoC level power management logic described in Global Utilities. • System debug P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 173 Summary of core integration details The architecture defines many features for software and hardware debug that interact with the SoC. Debug Features and Watchpoint Facility describes the debug features and watchpoint monitor. Figure 5-2 shows the e500 signals that interface with the debug block. The core reference manual describes how the architecture-defined debug resources are implemented on the e500 core. The "Core Complex Bus (CCB) and System Integration" chapter of the core reference manual describes the signals that are shown in the figure above and other aspects of core integration. 5.4 Summary of core integration details The summary of core integration details is organized into two sections: General feature integration details and register model integration details. This table summarizes details of the QorIQ -specific implementation of the core, which is organized into the following sections: • General feature integration details summarizes integration-specific details by functionality. • Register model integration details summarizes how integration-specific details are reflected in the SoC's implementation of the core register model. Table 5-1. Differences between the e500 core and the QorIQ core implementation Feature QorIQ implementation General feature integration details Cache protocol The write-through L2 cache implemented on the SoC does not support MESI cache protocol. Clocking Internal clock multipliers ranging from 1 to 8 times the bus clock, including integer and half-mode multipliers. The integrated device supports multipliers of 2, 2.5, 3, and 3.5. See the table entry, HID1 Implementation, for further details. R1 and R2 data R1 and R2 data bus parity are disabled on QorIQ devices. HID1[R1DPE,R2DPE] are reserved. bus parity Dynamic bus snooping The QorIQ devices do not perform dynamic bus snooping as described here. That is, when the e500 core is in core-stopped state (which is the state of the core when the QorIQ device is in either the nap or sleep state), the core is not awakened to perform snoops on global transactions. Device specific QorIQ devices define values for 00, 01, 10, and 11, as described in Register Model Integration Details in definition for this table. TCR[WRC] Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 174 Freescale Semiconductor, Inc. Chapter 5 e500 Core Integration Details Table 5-1. Differences between the e500 core and the QorIQ core implementation (continued) Feature QorIQ implementation SPE and floating-point categories The SPE (which includes the embedded vector and scalar floating-point instructions) will not be implemented in the next generation of QorIQ devices. Freescale Semiconductor strongly recommends that use of these instructions be confined to libraries and device drivers. Customer software that uses these instructions at the assembly level or that uses SPE or floating-point intrinsics will require rewriting for upward compatibility with next generation QorIQ devices. The e500v2 core implements SPE double-precision floating-point instructions. Freescale Semiconductor offers a libcfsl_e500 library that uses SPE instructions. Freescale Semiconductor will also provide future libraries to support next generation QorIQ devices. Note that in the Power ISA, MSR[SPE] and ESR[SPE] are renamed to MSR[SPV] and ESR[SPV]. Register Model Integration Details HID0 SEL_TBCLK. Selects time base clock. If this bit is set and the time base is enabled, the time base is based implementation on the TBCLK input, which on the QorIQ devices is RTC. HID1 HID1[PLL_CFG] is implemented as two subfields: Implementation PLL_MODE (HID1[32-33]): Read-only for integrated devices. 1 1 Fixed value for this device PIR value PVR value PLL_CFG, (HID1[34-39]): The following clock ratios are supported: 0001_00 Ratio of 2:1 0001_01 Ratio of 5:2 (2.5:1) 0001_10 Ratio of 3:1 0001_11 Ratio of 7:2 (3.5:1) NEXEN, R1DPE, R2DPE, MPXTT, MSHARS, SSHAR, ATS, and MID are not implemented. On QorIQ devices, ABE must be set to ensure that cache and TLB management instructions operate properly on the L2 cache. HID1[RFXE]. If RFXE is 0, conditions that cause the assertion of core_fault_in_B cannot directly cause the e500 to generate a machine check; however, QorIQ devices must be configured to detect and enable such conditions. The following bullets describe how error bits should be configured: • ECM mapping errors: EEER[LAEE] must be set. See ECM error enable register (ECM_EEER). • L2 multiple-bit ECC errors: L2ERRDIS[MBECCDIS] must be cleared to ensure that error can be detected. L2ERRINTEN[MBECCINTEN] must be set. See L2 error registers. • DDR multiple-bit ECC errors: ERR_DISABLE[MBED] must be zero and ERR_INT_EN[MBEE] must be set and DDR_SDRAM_CFG[ECC_EN] must be one to ensure that an interrupt is generated. See DDR memory map/register definition. • PCI. The appropriate parity detect and master-abort bits in ERR_DR must be cleared and the corresponding enable bits in ERR_EN must be set to ensure that an interrupt is generated. • Local bus controller parity errors. LTEDR[PARD] must be cleared and LTEIR[PARI] must be set to ensure that an parity errors can generate an interrupt. See Transfer error interrupt register (eLBC_LTEIR), and Transfer error attributes register (eLBC_LTEATR). The PIR value corresponds to the core number on multicore QorIQ devices. The PVR reset value is 0x80nn_nnnn. See Table 5-2 for specific values. PVR[VERSION] = 0x80nn PVR[REVISION] = 0xnnnn Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 175 Summary of core integration details Table 5-1. Differences between the e500 core and the QorIQ core implementation (continued) Feature QorIQ implementation SVR value The SVR reset value is 0x80nn_nnnn. See Table 5-2 for specific values. TCR (timer TCR[WRC] is defined more specifically for the implementation of the core in the integrated device. control register) Watchdog timer reset control. This value is written into TSR[WRS] when a watchdog event occurs. WRC may be set by software but cannot be cleared by software, except by a software-induced reset. Once written to a non-zero value, WRC may no longer be altered by software. 00 No watchdog timer reset will occur 01 Second timeout generates machine check 10 Second timeout generates HRESET_REQ output externally 11 Second timeout automatically resets the given processor core 5.4.1 Processor version register (PVR) and system version register (SVR) The table below matches the revision codes in the processor version register (PVR) with the core revision and the SoC revision; it includes a cross-reference to the section in global utilities that contains the corresponding SVR values. Note that the SVR and PVR can be accessed both as SPRs through the e500 core (see the e500 Reference Manual) and as memory-mapped registers defined by the integrated device. Table 5-2. Device revision level cross-reference SoC revision Core revision Processor version register (PVR) 1.0 5.0 0x8021_2050 System version register (SVR) Processor version register (GUTS_PVR) P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 176 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM This chapter describes the organization of the on-chip L2/SRAM, cache coherency rules, cache line replacement algorithm, cache control instructions, and various cache operations. 6.1 Introduction This chapter describes the organization of the on-chip L2/SRAM, cache coherency rules, cache line replacement algorithm, cache control instructions, and various cache operations. It also describes the interaction between the L2/SRAM and the e500 core complex. 6.2 L2 cache overview The integrated 256 KB L2 cache is organized as 1024 eight-way sets of 32-byte cache lines based on 36-bit physical addresses. This figure shows the L2 cache/SRAM configuration. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 177 L2 cache overview Figure 6-1. L2 cache/SRAM configuration The SRAM can be configured with memory-mapped registers as externally accessible memory-mapped SRAM in addition to or instead of cache. The L2 cache can operate in the following modes, described in L2 cache and SRAM organization: • Full cache mode (256 KB cache). • Full memory-mapped SRAM mode (256 KB SRAM mapped as a single 256 KB block or two 128 KB blocks) • Partial SRAM and partial cache mode, in which 1/8, 1/4, or 1/2 the total on-chip memory can be allocated to 1 or 2 SRAM regions. 6.2.1 L2 cache and SRAM features The L2 cache includes the following characteristics: • Supports 36-bit address space • Write-through, front-side cache • Front-side design provides easier cache access for the I/O masters, such as Ethernet • Write-through design is more efficient on the processor bus for front-side caches • Valid, locked, and stale states (no modified state) • Two input data buses (64 and 128 bits wide) and one output data bus (128 bits wide) • All accesses are fully pipelined and non-blocking (allows hits under misses) • 256 -KB array organized as 1024 eight-way sets of 32-byte cache lines • Eight-way set associativity with a pseudo-LRU (7-bit) replacement algorithm. • High level of associativity yields good performance even with many lines locked or used as SRAM regions P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 178 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM • I/O devices can store data into the cache in a process called 'stashing.' • Stashing is indicated for global I/O writes either by a transaction attribute or by a programmable memory range • Regions of the cache can be reserved exclusively for stashing to prevent pollution of processor cache regions. • Processor L2 cache regions are configurable to allocate instructions, data, or both. • External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). • 1, 2, or 4 ways can be configured for stashing only • Data ECC on 64-bit boundaries (single-error correction, double-error detection) • Tag arrays use 21 tag bits and 1 tag parity bit per line. • Multiple cache locking methods supported • Individual line locks are set and cleared using e500 cache locking APU instructions-Data Cache Block Touch and Lock Set (dcbtls), Data Cache Block Touch for Store and Lock Set (dcbtstls), and Instruction Cache Block Touch and Lock Set (icbtls). • A lock attribute can be attached to write operations. • Individual line locks are set and cleared through core-initiated instructions, by external reads or writes, or by accesses to programmed memory ranges defined in L2 cache external write address registers (L2CEWARn). • The entire cache can be locked by setting configuration register appropriately. • Lock clearing methods • Individual locks can be cleared by cache-locking APU instructions-Data Cache Block Lock Clear (dcblc) and Instruction Cache Block Lock Clear (icblc)-or by a snooped flush unless entire cache is locked. • Flash clearing of all instruction and/or data locks is done by writes to configuration registers. • An unlock attribute can be attached to a read instruction. • Error injection modes supported for testing error handling SRAM features include the following: • SRAM regions are created by configuring 1, 2, 4 or 8 ways of each set to be reserved for memory-mapped SRAM. • Regions can reside at any location in the memory map aligned to the SRAM size. • SRAM memory is byte addressable; for accesses of less than a cache line, ECC is updated using read-modify-write transactions. • I/O devices access SRAM regions by marking transactions as snoopable (global). Table 6-1 lists the possible L2 cache/SRAM configurations. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 179 L2 cache and SRAM organization Table 6-1. Available L2 cache/SRAM configurations Cache 256 KB 224 KB 192 KB 160 KB 128 KB 96 KB 64 KB - Stash-only Region - 32 KB - 32 KB 64 KB 32 KB 64 KB - 64 KB 128 KB 32 KB 128 KB 64 KB 128 KB - 128 KB SRAM Region 1 - 32 KB - 64 KB 32 KB 32 KB 64 KB 32 KB 32 KB 128 KB 64 KB 64 KB 32 KB 128 KB 64 KB 32 KB 128 KB 64 KB 64 KB 32 KB 256 KB 128 KB 128 KB 64 KB SRAM Region 2 - 32 KB - 32 KB - 64 KB - 32 KB - 64 KB - 64 KB - 32 KB - 128 KB - 64 KB 6.3 L2 cache and SRAM organization The on-chip memory array has four banks, each containing 256 sets of eight cache blocks (or "ways"). Each block consists of 32 bytes of data and a tag. This figure shows the organization of the cache. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 180 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM Figure 6-2. Cache organization 6.3.1 Accessing the on-chip array as an L2 cache This figure shows how physical address bits are used to access the L2 cache. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 181 L2 cache and SRAM organization Figure 6-3. Physical address usage for L2 cache accesses Physical address bits 21 -30 identify the bank and set of the tag and data. Physical address bits 0-20 are compared against the tags of all eight ways. A match of a valid tag selects a 32-byte block of data (or way) within the set. Physical address bits 31-35 identify the byte or bytes of data within the block. 6.3.2 Accessing the on-chip array as an SRAM When all or part of the array is dedicated to memory mapped SRAM, individual ways of each set are reserved for that purpose. SRAM accesses use physical address bits 18-20 in conjunction with the SRAM mode to select a way of the indexed set. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 182 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM This figure shows the physical address usage for SRAM accesses. Figure 6-4. Physical address usage for SRAM accesses The mapping of address bits and SRAM mode to a way select is shown in this table. SRAM size is reflected in L2CTL[L2SIZ]. Table 6-2. Way selection for SRAM accesses Description No SRAM Entire Array is SRAM (single 256 KB SRAM if L2SIZ = 256 KB) L2SRAM 000 001 L2SRBAR 0 Hit 1 L2SRBAR 1 Hit Addr[18-20 ] - - 0 000 001 010 011 100 101 110 111 Way Select 0 1 2 3 4 5 6 7 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 183 L2 cache and SRAM organization Table 6-2. Way selection for SRAM accesses (continued) Description One-half of array is an SRAM (single 128 KB SRAM if L2SIZ = 256 KB) Both halves of array are SRAM (two 128 KB SRAM if L2SIZ = 256 KB) One quarter of the array is SRAM (single 64 KB SRAM if L2SIZ = 256 KB) L2SRAM 010 011 100 L2SRBAR 0 Hit 1 1 0 1 L2SRBAR 1 Hit Addr[18-20 ] 0 x00 x01 x10 x11 0 x00 x01 x10 x11 1 x00 x01 x10 x11 0 xx0 xx1 Two quarters of the array are SRAMs 101 1 (single 64 KB SRAM if L2SIZ = 256 KB) 0 One-eighth of the array is an SRAM 110 1 (single 32 KB SRAM if L2SIZ = 256 KB) 0 xx0 xx1 1 xx0 xx1 0 - Two-eighths of the array are SRAM 111 1 (single 32 KB SRAM if L2SIZ = 256 KB) 0 0 - 1 - Way Select 0 1 2 3 0 1 2 3 4 5 6 7 0 1 0 1 2 3 0 0 1 6.3.3 Connection of the on-chip memory to the system The e500 core connects to the L2 cache and the system interface through the high-speed core complex bus (CCB). The e500 core and the L2 cache connect to the rest of the integrated device through the e500 coherency module (ECM). This figure shows the data connections of the e500 core and L2/SRAM. The e500 core can simultaneously read 128 bits of data from the L2/ SRAM, read 64 bits of data from the system interface, and write 128 bits of data to the L2/SRAM and/or system interface. The L2/SRAM can be accessed by the e500 core or the system interface through the ECM. The L2 cache does not initiate transactions. Figure 6-5 shows the data bus connections of the e500 core and L2/SRAM. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 184 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM Figure 6-5. Data bus connection of CCB This figure shows address connections of the e500 core and L2/SRAM. Figure 6-6. Address bus connection of CCB In SRAM mode, if a non-cache-line read or write transaction is not preceded by a cacheline write, an ECC error occurs; such a non-cache-line write transaction cannot be allocated in the L2. 6.4 L2 cache external write registers The device supports allocating and locking L2 cache lines from external agents such as PCI. This functionality is called stashing. Four sets of registers are provided to support this feature; each set has three registers that specify a programmed memory range that can be locked with a snoop write transaction. All three registers in a set must be configured in order to use an external write address. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 185 L2 memory-mapped SRAM registers These registers are the L2 cache external write address registers 0-3 (L2CEWARn), the L2 cache external write address registers extended address 0-3 (L2CEWAREAn), and the L2 cache external write control registers 0-3 (L2CEWCRn). L2CEWARn contain the lower 24 bits of the external write base address and L2CEWAREAn contain the upper 4 bits. The base address specified in the address registers must be naturally aligned to the window size in the corresponding control register. Further details on the locations and fields of these registers are given in the following sections. 6.5 L2 memory-mapped SRAM registers The L2 memory-mapped SRAM base address registers 0-1 (L2SRBARn) and the L2 memory-mapped SRAM base address registers extended address 0-1 (L2SRBAREAn), control the memory-mapped SRAM mode functionality. Together, these two pairs of registers define memory blocks that can be mapped into the L2 cache. Specified SRAM base addresses must be aligned to the size of the SRAM region. If L2CTL[L2SRAM] specifies one memory-mapped SRAM block, its base address must be written to the pair L2SRBAR0 and L2SRBAREA0; if it specifies two memory-mapped SRAM blocks, L2SRBAR0 and L2SRBAREA0 are used for the first SRAM block and L2SRBAR1 and L2SRBAREA1 are used for the second block. 6.6 L2 error registers L2 error detection, reporting, and injection allow flexible handling of ECC and parity errors in the L2 data and tag arrays. When the device detects an L2 error, the appropriate bit in the error detect register (L2ERRDET) is set. Error detection is disabled by setting the corresponding bit in the error disable register (L2ERRDIS). The address and attributes of the first detected error are also saved in the error capture registers (L2ERRADDR, L2ERRATTR, L2CAPTDATAHI, L2CAPTDATALO, and L2CAPTACC). Subsequent errors set error bits in the error detection registers, but information is saved only for the first one. Error reporting (by generating an interrupt) is enabled by setting the corresponding bit in the error interrupt enable register (L2ERRINTEN). Note that the error detect bit is set regardless of the state of the interrupt enable bit. When an error is detected, if error detection is enabled the L2 cache/SRAM P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 186 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM always asserts an internal error signal with read data to prevent the L1 caches and architectural registers from being loaded with corrupt data. If error detection is disabled, the detected error bit is not set and no internal signal is asserted. The L2 error detect register (L2ERRDET) is implemented as a bit-reset type register. Reading from this register occurs normally; however, write operations can clear but not set bits. A bit is cleared whenever the register is written and the data in the corresponding bit location is a 1. For example, to clear bit 6 and not affect any other bits in the register, the value 0x0200_0000 is written to the register. Note that in SRAM mode, if a non-cache-line read or write transaction is not preceded by a cache-line write, an ECC error occurs; such a non-cache-line write transaction cannot be allocated in the L2. 6.7 L2_Cache memory map/register definition The following table shows the memory map for the L2/SRAM registers. Offset address (hex) 2_0000 2_0004 2_0010 2_0014 2_0018 2_0020 2_0024 2_0028 2_0030 2_0034 L2_Cache memory map Register name Width (in bits) Access Reset value L2 control register (L2_Cache_L2CTL) 32 L2 cache way allocation for processors (L2_Cache_L2CWAP) 32 L2 cache external write address register n (L2_Cache_L2CEWAR0) 32 L2 cache external write address register extended address n (L2_Cache_L2CEWAREA0) 32 L2 cache external write control register n (L2_Cache_L2CEWCR0) 32 L2 cache external write address register n (L2_Cache_L2CEWAR1) 32 L2 cache external write address register extended address n (L2_Cache_L2CEWAREA1) 32 L2 cache external write control register n (L2_Cache_L2CEWCR1) 32 L2 cache external write address register n (L2_Cache_L2CEWAR2) 32 L2 cache external write address register extended address n (L2_Cache_L2CEWAREA2) 32 Table continues on the next page... R/W 1000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h Section/ page 6.7.1/188 6.7.2/193 6.7.3/195 6.7.4/195 6.7.5/196 6.7.3/195 6.7.4/195 6.7.5/196 6.7.3/195 6.7.4/195 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 187 L2_Cache memory map/register definition L2_Cache memory map (continued) Offset address (hex) 2_0038 2_0040 2_0044 2_0048 2_0100 2_0104 2_0108 2_010C 2_0E00 2_0E04 2_0E08 2_0E20 2_0E24 2_0E28 2_0E40 2_0E44 2_0E48 2_0E4C 2_0E50 2_0E54 2_0E58 Register name Width (in bits) Access Reset value Section/ page L2 cache external write control register n (L2_Cache_L2CEWCR2) 32 L2 cache external write address register n (L2_Cache_L2CEWAR3) 32 L2 cache external write address register extended address n (L2_Cache_L2CEWAREA3) 32 L2 cache external write control register n (L2_Cache_L2CEWCR3) 32 L2 memory-mapped SRAM base address register n (L2_Cache_L2SRBAR0) 32 L2 memory-mapped SRAM base address register extended address n (L2_Cache_L2SRBAREA0) 32 L2 memory-mapped SRAM base address register n (L2_Cache_L2SRBAR1) 32 L2 memory-mapped SRAM base address register extended address n (L2_Cache_L2SRBAREA1) 32 L2 error injection mask high register (L2_Cache_L2ERRINJHI) 32 L2 error injection mask low register (L2_Cache_L2ERRINJLO) 32 L2 error injection tag/ECC control register (L2_Cache_L2ERRINJCTL) 32 L2 error data high capture register (L2_Cache_L2CAPTDATAHI) 32 L2 error data low capture register (L2_Cache_L2CAPTDATALO) 32 L2 error syndrome register (L2_Cache_L2CAPTECC) 32 L2 error detect register (L2_Cache_L2ERRDET) 32 L2 error disable register (L2_Cache_L2ERRDIS) 32 L2 error interrupt enable register (L2_Cache_L2ERRINTEN) 32 L2 error attributes capture register (L2_Cache_L2ERRATTR) 32 L2 error address capture register low (L2_Cache_L2ERRADDRL) 32 L2 error address capture register high (L2_Cache_L2ERRADDRH) 32 L2 error control register (L2_Cache_L2ERRCTL) 32 R/W 0000_0000h 6.7.5/196 R/W 0000_0000h 6.7.3/195 R/W 0000_0000h 6.7.4/195 R/W 0000_0000h 6.7.5/196 R/W 0000_0000h 6.7.6/197 R/W 0000_0000h 6.7.7/198 R/W 0000_0000h 6.7.6/197 R/W 0000_0000h 6.7.7/198 R/W 0000_0000h 6.7.8/199 R/W 0000_0000h 6.7.9/200 R/W 0000_0000h 6.7.10/200 R 0000_0000h 6.7.11/201 R 0000_0000h 6.7.12/202 R 0000_0000h 6.7.13/202 w1c 0000_0000h 6.7.14/204 R/W 0000_0000h 6.7.15/206 R/W 0000_0000h 6.7.16/208 R/W 0000_0000h 6.7.17/210 R 0000_0000h 6.7.18/212 R 0000_0000h 6.7.19/212 R/W 0000_0000h 6.7.20/213 6.7.1 L2 control register (L2_Cache_L2CTL) The L2 control register (L2CTL), shown in the figure below, controls configuration and operation of the L2/SRAM array. The sequence for modifying L2CTL is as follows: P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 188 Freescale Semiconductor, Inc. 1. mbar 2. isync 3. stw (WIMG = 01xx) CCSRBAR + 0x2_0000 4. lwz (WIMG = 01xx) CCSRBAR + 0x2_0000 5. mbar Chapter 6 L2 Look-Aside Cache/SRAM Address: 2_0000h base + 0h offset = 2_0000h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R L2SIZ L2E L2I W Reserved L2DO Reserved L2INTDIS L2IO L2SRAM Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 L2SLC Reserved L2LFR L2STASHDIS Reserved L2STASHCTL R Reserved L2LO W L2LFRID Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 189 L2_Cache memory map/register definition L2_Cache_L2CTL field descriptions Field 0 L2E Description L2 enable. Used to enable the L2 array (cache or memory-mapped SRAM). Note that L2I can be set regardless of the value of L2E. 0 The L2 SRAM (cache and memory-mapped SRAM) is disabled and is not accessed for reads, snoops, or writes. Setting the L2 flash invalidate bit (L2I) is allowed. 1 The L2 SRAM (cache or memory-mapped SRAM) is enabled. 1 L2 flash invalidate. L2I Data to memory-mapped SRAM are unaffected by the flash invalidate. The hardware automatically clears L2I when the invalidate is complete. 2–3 L2SIZ 0 The L2 status and LRU bits are not being cleared. 1 Setting L2I invalidates the L2 cache globally by clearing all the L2 status bits, as well as the LRU algorithm. Memory-mapped SRAM is unaffected. L2 SRAM size (read only). Indicates the total available size of on-chip memory array (to be configured as cache or memory-mapped SRAM). 4–8 - 9 L2DO 00 Reserved 01 256 KB 10 Reserved 11 Reserved This field is reserved. Reserved L2 data-only. Reserved in full memory-mapped SRAM mode. L2DO may be changed while the L2 is enabled or disabled. Note that if L2DO and L2IO are both set, no new lines are allocated into the L2 cache for any processor transactions, and processor writes and castouts that hit existing data in the cache invalidate those lines rather than updating them. 10 L2IO 0 The L2 cache allocates entries for instruction fetches that miss in the L2. 1 The L2 cache allocates entries for processor data loads that miss in the L2 and for processor L1 castouts but does not allocate entries for instruction fetches that miss in the L2. Instruction accesses that hit in the L2, data accesses, and accesses from the system (including I/O stash writes) are unaffected. L2 instruction-only. Reserved in full memory-mapped SRAM mode. Causes the L2 cache to allocate lines for instruction cache transactions only. L2IO may be changed while the L2 is enabled or disabled. Note that if L2DO and L2IO are both set, no new lines are allocated into the L2 cache for any processor transactions, and processor writes and castouts that hit existing data in the cache invalidate those lines rather than updating them. 11 - 12 L2INTDIS 0 The L2 cache entries are allocated for data loads that miss in the L2 and for processor L1 castouts. 1 The L2 cache allocates entries for instruction fetch misses, but does not allocate entries for processor data transactions. Data accesses that hit in the L2, instruction accesses, and accesses from the system (including I/O stash writes) are unaffected. This field is reserved. Reserved Cache read intervention disable. Reserved for full memory-mapped SRAM mode. Used to disable cache read intervention. May be changed while the L2 is enabled or disabled. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 190 Freescale Semiconductor, Inc. Field 13–15 L2SRAM 16–17 18 L2LO 19 L2SLC 20 21 L2LFR 22–23 L2LFRID Chapter 6 L2 Look-Aside Cache/SRAM L2_Cache_L2CTL field descriptions (continued) Description 0 Cache intervention is enabled. The ECM ensures that if a data read from another device hits in the L2 cache, it is serviced from the L2 cache. 1 Cache intervention is disabled L2 SRAM configuration. Determines the L2 cache/memory-mapped SRAM allocation of the on-chip memory array. SRAM size depends on the value of L2SIZ. Since L2SIZ is 256 KB, SRAM can have sizes from 32 KB to 256 KB. For one SRAM region L2SRBAR0 is used and for two SRAM regions L2SRBAR0 and L2SRBAR1 are used. Regions of the array that are not allocated to SRAMs are used as cache memory. To change these bits, the L2 must be disabled (L2CTL[L2E] = 0). Note that when setting L2SRAM after cache has been enabled, L2I should be set as well. The fields can be set simultaneously, and this step is not needed if SRAM size is getting smaller. 000 No SRAM. Entire array is cache. 001 Entire array is a single SRAM ( 256 -KB SRAM for L2SIZ = 256 KB) 010 One half of the array is an SRAM ( 128 -KB SRAM for L2SIZ = 256 KB) 011 Both halves of the array are SRAMs (two 128 -KB SRAMs for L2SIZ = 256 KB) 100 One quarter of the array is an SRAM (one 64 -KB SRAM for L2SIZ = 256 KB) 101 Two quarters of the array are SRAMs (two 64 -KB SRAMs for L2SIZ = 256 KB) 110 One eighth of the array is an SRAM (one 32 -KB SRAM for L2SIZ = 256 KB) 111 Two eighths of the array are SRAMs (two 32 -KB SRAMs for L2SIZ = 256 KB) This field is reserved. Reserved L2 cache lock overflow. Reserved in full memory-mapped SRAM mode. This sticky bit is set if an overlock condition is detected in the L2 cache. A lock overflow is triggered either by executing instruction or data cache block touch and lock set instructions or by performing L2 cache external writes with lock set. If all ways are locked and an attempt to stash is made, the stash is not allocated. 0 The L2 cache did not encounter a lock overflow. L2LO is cleared only by software. 1 The L2 cache encountered a lock overflow condition. L2 snoop lock clear. This sticky bit is set if a snoop invalidated a locked data cache line. Note that the lock bit for that line is cleared whenever the line is invalidated. L2SLC is reserved in full memory-mapped SRAM mode. 0 A snoop did not invalidate a locked L2 cache line. L2SLC is cleared only by software. 1 The L2 cache encountered a snoop that invalidated a locked line. This field is reserved. Reserved L2 cache lock bits flash reset. The L2 cache must be enabled (L2CTL[L2E] = 1) for reset to occur. This field is reserved in full memory-mapped SRAM mode. 0 The L2 cache lock bits are not cleared or the clear operation completed. 1 A reset operation is issued that clears each L2 cache line's lock bits. Depending on the L2LFRID value, data or instruction locks, or both, can be reset. Cache access is blocked during this time. After L2LFR is set, the L2 cache unit automatically clears L2LFR when the reset operation is complete (if L2CTL[L2E] is set). L2 cache lock bits flash reset select instruction or data. Indicates whether data or instruction lock bits or both are reset. 00 Not used Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 191 L2_Cache memory map/register definition L2_Cache_L2CTL field descriptions (continued) Field 24–27 28 L2STASHDIS Description 01 Reset data locks if L2LFR = 1. 10 Reset instruction locks if L2LFR = 1. 11 Reset both data and instruction locks if L2LFR = 1. This field is reserved. Reserved L2 stash allocate disable. Disables allocation of lines for stashing. This bit does NOT affect the updating of lines that are already resident in the cache and have the stash attribute set or hit a stash range. Such lines are updated even if this bit is set. NOTE: To change this bit, the L2 must be disabled (L2CTL[L2E] = 0). 29 - 30–31 L2STASHCTL 0 The L2 cache allocates lines for global writes that hit in a stash range or that have the stashing attribute set. 1 The L2 does not allocate lines for stashed writes. This field is reserved. Reserved L2 stash configuration. This field reserves regions of the cache for stash-only operation. That is, blocks of each cache set are reserved so that they can only be allocated for stash data. If such a region is created, processor reads and writes are not allocated into this region; it can only be populated by stash writes. Similarly, stash writes are only allocated into this region. This prevents processor and stashed I/O data from polluting one another. Like L2SRAM configuration, stash-only regions subtract from the amount of the on-chip memory that is available to the processor as cache. If the L2SRAM configuration uses the entire on-chip memory array as SRAM, then no stash-only region can be created. To change these bits, the L2 must be disabled (L2CTL[L2E] = 0). This field has no effect if the L2STASHDIS bit is set. 00 No stash-only region. Stashed writes are allocated across the entire cache and can evict processor data and can be evicted by processor data. 01 One half of the array is a stash-only cache (way4, way5, way6 & way7 of each set) 10 One quarter of the array is a stash-only cache (way6 & way7 of each set) 11 One eighth of the array is a stash-only cache (way7 of each set) P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 192 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM 6.7.2 L2 cache way allocation for processors (L2_Cache_L2CWAP) The L2 cache way allocation for processors (L2CWAP) register, shown in the figure below, allows the L2 cache to be programmed to distribute eight ways between two processor cores. A pointer is used to set the ways allocated between processor 0 and processor 1. Address: 2_0000h base + 4h offset = 2_0004h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R POINTER W Reserved ENABLE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W Reset 0 Field 0 ENABLE 1–3 POINTER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2CWAP field descriptions Description L2 cache way pointer enable. The L2 cache uses the pointer value only when ENABLE is set. 0 The L2 way pointer is disabled. No ways are allocated only for processor 0 or for processor 1. All ways (except ways allocated for SRAM and stashing) are shared between processors. 1 The L2 way pointer is enabled. Ways are allocated for processors based on way pointer. L2 cache way pointer. This pointer is used to allocate ways between processor 0 and processor 1. To change this field the L2 must be disabled (L2CTL[L2E] = 0). If ways have been allocated for SRAM (L2CTL[13-15]) or stashing (L2CTL[30-31]), way allocation is affected as noted in the following examples. In general, when allocating ways among SRAM, stashing, and processors, the controller gives SRAM first preference, then stashing, then processors. Suppose 2 ways are allocated for SRAM and 2 ways are allocated for stashing and POINTER = 100... Way0 -> SRAM Way1 -> SRAM Way2 -> Processor 0 Way3 -> Processor 0 Way4 -> Processor 1 Way5 -> Processor 1 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 193 L2_Cache memory map/register definition L2_Cache_L2CWAP field descriptions (continued) Field Way6 -> Stash Description Way7 -> Stash Suppose 4 ways are allocated for SRAM and 2 ways are allocated for stashing and POINTER = 100... Way0 -> SRAM Way1 -> SRAM Way2 -> SRAM Way3 -> SRAM Way4 -> Processor 1 Way5 -> Processor 1 Way6 -> Stash Way7 -> Stash Suppose 2 ways are allocated for SRAM and no ways are allocated for stashing and POINTER = 100... Way0 -> SRAM Way1 -> SRAM Way2 -> Processor 0/Stash Way3 -> Processor 0/Stash Way4 -> Processor 1/Stash Way5 -> Processor 1/Stash Way6 -> Processor 1/Stash Way7 -> Processor 1/Stash The following description for way pointer values assumes that no ways are allocated for L2SRAM (L2CTL[13-15]) and L2STASH (L2CTL[30-31]). 4–31 - 000 Way0-way7 are allocated for processor 1 and no ways are allocated for processor 0. 001 Way0 is allocated for processor 0 and way1-way7 are allocated for processor 1. 010 Way0-way1 are allocated for processor 0 and way2-way7 are allocated for processor 1. 011 Way0-way2 are allocated for processor 0 and way3- way7 are allocated for processor 1. 100 Way0-way3 are allocated for processor 0 and way4-way7 are allocated for processor 1. 101 Way0-way4 are allocated for processor 0 and way5-way7 are allocated for processor 1. 110 Way0-way5 are allocated for processor 0 and way6-way7 are allocated for processor 1. 111 Way0-way6 are allocated for processor 0 and way7 is allocated for processor 1. This field is reserved. Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 194 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM 6.7.3 L2 cache external write address register n (L2_Cache_L2CEWARn) The L2CEWAR n registers contain the lower 24 bits of the 28-bit L2 cache external write base address. Each of these registers has identical fields, as shown in the figure below. Address: 2_0000h base + 10h offset + (16d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W ADDR Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2CEWARn field descriptions Field 0–23 ADDR 24–31 - Description Contains the lower 24 bits of the 28-bit L2 cache external write base address. Note that the upper 4 bits of the base address are in L2CEWAREA n [ADDR]. This field is reserved. Reserved 6.7.4 L2 cache external write address register extended address n (L2_Cache_L2CEWAREAn) The L2 cache external write address registers extended address (L2CEWAREA n ), shown in the figure below, contain the upper 4 bits of the 28-bit L2 cache external write base address. Address: 2_0000h base + 14h offset + (16d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved ADDR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2CEWAREAn field descriptions Field 0–27 - 28–31 ADDR Description This field is reserved. Reserved Contains the upper 4 bits of the L2 cache external write base address. Note that the rest of the base address is in L2CEWAR n [ADDR]. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 195 L2_Cache memory map/register definition 6.7.5 L2 cache external write control register n (L2_Cache_L2CEWCRn) The L2CEWAR n /L2CEWAREA n address registers work with the L2 cache external write control registers 0-3 (L2CEWCR n ), shown in the figure below, to control cache external write functionality. Address: 2_0000h base + 18h offset + (16d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R E W LOCK Reserved SIZMASK Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SIZMASK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Field 0 E L2_Cache_L2CEWCRn field descriptions Description External write enable. An external write matching the address window defined by L2CEWAR n / L2CEWAREA n /L2CEWCR n is allocated or updated in the L2 cache. 1 LOCK 0 External writes for the L2CEWAR n /L2CEWAREA n /L2CEWCR n set are disabled. 1 External writes are enabled for the L2CEWAR n /L2CEWAREA n /L2CEWCR n set. Lock lines in the targeted cache. An external write matching the address window defined by L2CEWAR n / L2CEWAREA n /L2CEWCR n is locked in the L2 cache when it is allocated or updated. 2–3 - 4–31 SIZMASK 0 The locked bit is not set when a line is allocated unless explicitly specified by transaction attributes. 1 Cache lines are allocated as locked. A hit to a valid, unlocked line sets the lock. This field is reserved. Reserved Mask size. Defines the size of the naturally aligned address region for cache external writes. The address region must be aligned to a boundary that is a multiple of the mask size. Any value not listed below is illegal and produces boundedly undefined results. 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 256 bytes 1111 1111 1111 1111 1111 1110 512 bytes 1111 1111 1111 1111 1111 1100 1 KB 1111 1111 1111 1111 1111 1000 2 KB 1111 1111 1111 1111 1111 0000 4 KB Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 196 Freescale Semiconductor, Inc. Field Chapter 6 L2 Look-Aside Cache/SRAM L2_Cache_L2CEWCRn field descriptions (continued) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 1100 1000 0000 Description 1111 1111 1111 1111 1110 0000 8 KB 1111 1111 1111 1111 1100 0000 16 KB 1111 1111 1111 1111 1000 0000 32 KB 1111 1111 1111 1111 0000 0000 64 KB 1111 1111 1111 1110 0000 0000 128 KB 1111 1111 1111 1100 0000 0000 256 KB 1111 1111 1111 1000 0000 0000 512 KB 1111 1111 1111 0000 0000 0000 1 MB 1111 1111 1110 0000 0000 0000 2 MB 1111 1111 1100 0000 0000 0000 4 MB 1111 1111 1000 0000 0000 0000 8 MB 1111 1111 0000 0000 0000 0000 16 MB 1111 1110 0000 0000 0000 0000 32 MB 1111 1100 0000 0000 0000 0000 64 MB 1111 1000 0000 0000 0000 0000 128 MB 1111 0000 0000 0000 0000 0000 256 MB 1110 0000 0000 0000 0000 0000 512 MB 1100 0000 0000 0000 0000 0000 1 GB 1000 0000 0000 0000 0000 0000 2 GB 0000 0000 0000 0000 0000 0000 4 GB 0000 0000 0000 0000 0000 0000 8 GB 0000 0000 0000 0000 0000 0000 16 GB 0000 0000 0000 0000 0000 0000 32 GB 0000 0000 0000 0000 0000 0000 64 GB 6.7.6 L2 memory-mapped SRAM base address register n (L2_Cache_L2SRBARn) The L2 memory-mapped SRAM base address registers (L2SRBAR n ) contain the lower 18 bits of the 22 -bit SRAM base address. 64 KB 128 KB 256 KB SRAM Partition Bits Required for SRAM Offset 16 17 18 Bits Used for Actual Base Address 20 (0-19) 19 (0-18) 18 (0-17) When enabled, the windows defined in L2SRBAR n and L2SRBAREA n supersede all other mappings of these addresses for processor and global (snoopable) I/O transactions. Therefore, SRAM windows must never overlap configuration space as defined by CCSRBAR (see .) Overlapping SRAM and local access windows is discouraged because processor and snoopable I/O transactions would map to the SRAM while non-snooped I/ P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 197 L2_Cache memory map/register definition O transactions would be mapped by the local access windows. Only if all accesses to the SRAM address range are snoopable can results be consistent if SRAM and local access windows overlap. Address: 2_0000h base + 100h offset + (8d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W ADDR Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2SRBARn field descriptions Field 0–17 ADDR 18–31 - Description Contains the lower 18 bits of the 22-bit L2 memory-mapped SRAM base address; the upper 4 bits are contained in L2SRBAREA n [ADDR]. (Note that some of these bits may not be needed, depending on how the L2 cache is partitioned.) The combined base address from L2SRBAREA n [ADDR] || L2SRBAR n [ADDR] is used as shown in L2 memory-mapped SRAM base address register n (L2_Cache_L2SRBARn) Unused bits of the base address are masked off by the hardware This field is reserved. Reserved 6.7.7 L2 memory-mapped SRAM base address register extended address n (L2_Cache_L2SRBAREAn) The L2 memory-mapped SRAM base address registers extended address (L2SRBAREA n ), shown in the figure below, contain the upper 4 bits of the L2 cache SRAM base address. Address: 2_0000h base + 104h offset + (8d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved ADDR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2SRBAREAn field descriptions Field 0–27 - 28–31 ADDR Description This field is reserved. Reserved Contains the upper 4 bits of the L2 cache SRAM base address. Note that the 18 low-order bits of the base address are contained in L2SRBAR n [ADDR]. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 198 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM 6.7.8 L2 error injection mask high register (L2_Cache_L2ERRINJHI) The L2 cache includes support for injecting errors into the L2 data, data ECC, or tag. This may be used to test error recovery software by deterministically creating error scenarios. The preferred method for error injection is to set all data pages to cache-inhibited (MMU TLB entry I = 1) except a scratch page, set L2CTL[L2DO] to prevent allocation of instruction accesses, and invalidate the L2 by setting L2CTL[L2I] = 1. The following code sequence triggers an error, then detects it (A is an address in the scratch page): dcbz A | allocates the line in the L1 in the modified state dcbtls_L2 A | forces the line from the L1 and allocates the line in the L2 lwz A Data or tag errors are injected into the line, according to the error injection settings in L2ERRINJHI, L2ERRINJLO, and L2ERRINJCTL, at allocation. The final load detects and reports the error (if enabled) and allows software to examine the offending data, address, and attributes. Note that error injection enable bits in L2ERRINJCTL must be cleared by software and the L2 must be invalidated (by setting L2CTL[L2I]) before resuming L2 normal operation. The figure below shows the L2 error injection mask high register (L2ERRINJHI). Address: 2_0000h base + E00h offset = 2_0E00h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W EIMASKHI Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2ERRINJHI field descriptions Field 0–31 EIMASKHI Description Error injection mask/high word. A set bit corresponding to a data path bit causes that bit on the data path to be inverted on cache/SRAM writes if L2ERRINJCTL[DERRIEN] = 1. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 199 L2_Cache memory map/register definition 6.7.9 L2 error injection mask low register (L2_Cache_L2ERRINJLO) The figure below shows the L2 error injection mask low register (L2ERRINJLO). Address: 2_0000h base + E04h offset = 2_0E04h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W EIMASKLO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2ERRINJLO field descriptions Field 0–31 EIMASKLO Description Error injection mask/low word. A set bit corresponding to a data path bit causes that bit on the data path to be inverted on SRAM writes if L2ERRINJCTL[DERRIEN] = 1. ECCMB DERRIEN TERRIEN 6.7.10 L2 error injection tag/ECC control register (L2_Cache_L2ERRINJCTL) The figure below shows the L2 error injection mask control register (L2ERRINJCTL). Address: 2_0000h base + E08h offset = 2_0E08h Bit 0 1 2 3 4 5 R W 6 7 8 Reserved 9 10 11 12 13 14 15 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W ECCERRIM Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 200 Freescale Semiconductor, Inc. Field 0–14 15 TERRIEN 16–21 22 ECCMB 23 DERRIEN 24–31 ECCERRIM Chapter 6 L2 Look-Aside Cache/SRAM L2_Cache_L2ERRINJCTL field descriptions This field is reserved. Reserved L2 tag array error injection enable Description 0 No tag errors are injected. 1 All subsequent entries written to the L2 tag array have the parity bit inverted. This field is reserved. Reserved ECC mirror byte enable. 0 ECC byte mirroring is disabled 1 The most significant data path byte is mirrored onto the ECC byte if DERRIEN = 1. L2 data array error injection enable: NOTE: If both ECC mirror byte and data error injection are enabled, ECC mask error injection is performed on the mirrored ECC. 0 No data errors are injected. 1 Subsequent entries written to the L2 data array have data or ECC bits inverted as specified in the data and ECC error injection masks and/or data path byte mirrored onto ECC as specified by ECC mirror byte enable. Error injection mask for the ECC bits. A set bit corresponding to an ECC bit causes that bit to be inverted on SRAM writes if DERRIEN = 1. 6.7.11 L2 error data high capture register (L2_Cache_L2CAPTDATAHI) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error capture data high register (L2CAPTDATAHI). Address: 2_0000h base + E20h offset = 2_0E20h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R L2DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2CAPTDATAHI field descriptions Field 0–31 L2DATA L2 data high word Description P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 201 L2_Cache memory map/register definition 6.7.12 L2 error data low capture register (L2_Cache_L2CAPTDATALO) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error capture data low register (L2CAPTDATALO). Address: 2_0000h base + E24h offset = 2_0E24h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R L2DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2CAPTDATALO field descriptions Field 0–31 L2DATA L2 data low word Description 6.7.13 L2 error syndrome register (L2_Cache_L2CAPTECC) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error syndrome register (L2CAPTECC). Address: 2_0000h base + E28h offset = 2_0E28h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ECCSYND W Reserved ECCCHKSUM Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2CAPTECC field descriptions Field 0–7 ECCSYND Description The calculated ECC syndrome of the failing double word Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 202 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM L2_Cache_L2CAPTECC field descriptions (continued) Field 8–23 - 24–31 ECCCHKSUM Description This field is reserved. Reserved The data path ECC of the failing double word P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 203 L2_Cache memory map/register definition 6.7.14 L2 error detect register (L2_Cache_L2ERRDET) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error detect register (L2ERRDET). Address: 2_0000h base + E40h offset = 2_0E40h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MULL2ERR R W w1c Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 204 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TPARERR MBECCERR SBECCERR Reserved L2CFGERR R Reserved W w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2ERRDET field descriptions Field 0 MULL2ERR 1–26 27 TPARERR Multiple L2 errors (write 1 to clear) Description 0 Multiple L2 errors of the same type were not detected 1 Multiple L2 errors of the same type were detected This field is reserved. Reserved Tag parity error (write 1 to clear) Note that if an L2 cache tag parity error occurs on an attempt to write a new line, the L2 cache must be Flash invalidated. L2 functionality is not guaranteed if Flash invalidation is not performed after a tag parity error. 28 MBECCERR 29 SBECCERR 30 31 L2CFGERR 0 Tag parity error was not detected 1 Tag parity error was detected Multiple-bit ECC error (write 1 to clear) 0 Multiple-bit ECC errors were not detected 1 Multiple-bit ECC errors were detected Single-bit ECC error (write 1 to clear) 0 Single-bit ECC error was not detected 1 Single-bit ECC error was detected. This field is reserved. Reserved L2 configuration error (write 1 to clear) 0 L2 configuration errors were not detected 1 L2 illegal configuration error detected. Reports inconsistencies between the L2SRAM, L2STASHDIS and L2STASHCTL fields of the L2 control register (L2CTL) P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 205 L2_Cache memory map/register definition 6.7.15 L2 error disable register (L2_Cache_L2ERRDIS) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error disable register (L2ERRDIS). Address: 2_0000h base + E44h offset = 2_0E44h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TPARDIS MBECCDIS SBECCDIS Reserved L2CFGDIS R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2ERRDIS field descriptions Field 0–26 27 TPARDIS 28 MBECCDIS This field is reserved. Reserved Tag parity error disable Description 0 Tag parity error detection enabled 1 Tag parity error detection disabled Multiple-bit ECC error disable. Note that non-correctable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and this error occurs, MBECCDIS must be cleared and L2ERRINTEN[MBECCINTEN] must be set to ensure that an interrupt is generated. NOTE: In normal operation , ECC must be enabled. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 206 Freescale Semiconductor, Inc. Field 29 SBECCDIS 30 31 L2CFGDIS Chapter 6 L2 Look-Aside Cache/SRAM L2_Cache_L2ERRDIS field descriptions (continued) 0 Multiple-bit ECC error detection enabled 1 Multiple-bit ECC error detection disabled Single-bit ECC error disable Description NOTE: In normal operation , ECC must be enabled. 0 Single-bit ECC error detection enabled 1 Single-bit ECC error detection disabled This field is reserved. Reserved L2 configuration error disable 0 L2 configuration error detection enabled 1 L2 configuration error detection disabled P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 207 L2_Cache memory map/register definition 6.7.16 L2 error interrupt enable register (L2_Cache_L2ERRINTEN) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error interrupt enable register (L2ERRINTEN). When an enabled error condition exists, the L2 signals an interrupt to the core through the internal int signal. Address: 2_0000h base + E48h offset = 2_0E48h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TPARINTEN MBECCINTEN SBECCINTEN Reserved L2CFGINTEN R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2ERRINTEN field descriptions Field Description 0–26 27 TPARINTEN 28 MBECCINTEN This field is reserved. Reserved Tag parity error reporting enable 0 Tag parity error reporting disabled 1 Tag parity error reporting enabled Multiple-bit ECC error reporting enable. Note that non-correctable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 208 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM L2_Cache_L2ERRINTEN field descriptions (continued) Field Description clearing HID1[RFXE]). If RFXE is zero and this error occurs, L2ERRDIS[MBECCDIS] must be cleared and MBECCINTEN must be set to ensure that an interrupt is generated. 29 SBECCINTEN 30 31 L2CFGINTEN 0 Multiple-bit ECC error reporting disabled 1 Multiple-bit ECC error reporting enabled Single-bit ECC error reporting enable 0 Single-bit ECC error reporting disabled 1 Single-bit ECC error reporting enabled This field is reserved. Reserved L2 configuration error reporting enable 0 L2 configuration error reporting disabled 1 L2 configuration error reporting enabled P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 209 L2_Cache memory map/register definition 6.7.17 L2 error attributes capture register (L2_Cache_L2ERRATTR) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error attributes capture register (L2ERRATTR). Address: 2_0000h base + E4Ch offset = 2_0E4Ch Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved DWNUM W Reserved TRANSSIZ BURST Reserved TRANSSRC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W TRANSTYPE Reserved VALINFO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2ERRATTR field descriptions Field 0–1 - 2–3 DWNUM 4 - 5–7 TRANSSIZ Description This field is reserved. Reserved Double-word number of the detected error (data ECC errors only) This field is reserved. Reserved Transaction size for detected error Single-beat Burst Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 210 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM L2_Cache_L2ERRATTR field descriptions (continued) Field 8 BURST 9–10 - 11–15 TRANSSRC 16–17 - 18–19 TRANSTYPE 20–30 31 VALINFO 000 8 bytes Reserved 001 1 byte 16 bytes 010 2 bytes 32 bytes 011 3 bytes Reserved 100 4 bytes Reserved 101 5 bytes Reserved 110 6 bytes Reserved 111 7 bytes Reserved Burst transaction for detected error Description 0 Single-beat (≤ 64 bits) transaction 1 Burst transaction This field is reserved. Reserved Transaction source for detected error 00000 10000 10001 External (system logic) Processor (instruction) Processor (data) This field is reserved. Reserved Transaction type for detected error 00 Snoop (tag/status read) 01 Write 10 Read 11 Read-modify-write This field is reserved. Reserved L2 capture registers valid 0 L2 capture registers contain no valid information or no enabled errors were detected. 1 L2 capture registers contain information of the first detected error which has reporting enabled. Software must clear this bit to unfreeze error capture so error detection hardware can overwrite the capture address/data/attributes for a newly detected error. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 211 L2_Cache memory map/register definition 6.7.18 L2 error address capture register low (L2_Cache_L2ERRADDRL) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error address capture register low (L2ERRADDRL). Address: 2_0000h base + E50h offset = 2_0E50h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R L2ADDRL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2ERRADDRL field descriptions Field 0–31 L2ADDRL Description L2 address bits 4-35 corresponding to detected error 6.7.19 L2 error address capture register high (L2_Cache_L2ERRADDRH) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error address capture register high (L2ERRADDRH). Address: 2_0000h base + E54h offset = 2_0E54h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W L2ADDRH Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2ERRADDRH field descriptions Field 0–27 - This field is reserved. Reserved Description Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 212 Freescale Semiconductor, Inc. Field 28–31 L2ADDRH Chapter 6 L2 Look-Aside Cache/SRAM L2_Cache_L2ERRADDRH field descriptions (continued) Description L2 address bits 0-3 corresponding to detected error 6.7.20 L2 error control register (L2_Cache_L2ERRCTL) The error control and capture registers control detection and reporting of tag parity, ECC and L2 configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are detected when the L2 is enabled (L2CTL[L2E] = 1). The figure below shows the L2 error control register (L2ERRCTL). Address: 2_0000h base + E58h offset = 2_0E58h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved L2CTHRESH Reserved L2CCOUNT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2_Cache_L2ERRCTL field descriptions Field 0–7 8–15 L2CTHRESH 16–23 - 24–31 L2CCOUNT Description This field is reserved. Reserved L2 cache threshold Threshold value for the number of ECC single-bit errors that are detected before reporting an error condition. This field is reserved. Reserved L2 count Counts ECC single-bit errors detected. If L2CCOUNT equals the ECC single-bit error trigger threshold, an error is reported if single-bit error reporting is enabled. 6.8 External writes to the L2 cache (cache stashing) Data from an I/O master can be allocated into the L2 cache while simultaneously being written to memory. External (stashed) writes can be performed from any I/O master, such as the following: • Ethernet P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 213 L2 cache timing • PCI/PCI-Express • DMA Stashing is controlled either by an attribute from the initiator of a write or by address range registers in the L2 cache. New cache lines are allocated for full-cache-line writes (unless the line is already resident in the cache). Sub-cache-line write data is stashed only if the line is already valid in the cache. For these sub-cache-line writes, a read-modifywrite process is used to merge the write data with the valid data already in the cache. For information on how to initiate cache stashing from an I/O master, see the respective chapters for the I/O masters that support stashing. For address range based control of stashing, the L2 cache external write address registers 0-3 (L2CEWARn) and the L2 cache external write address registers extended address 0-3 (L2CEWAREAn) are used with the L2 cache external write control registers 0-3 (L2CEWCRn) to control the cache stashing functionality. Each register set (for example L2CEWAR0, L2CEWAREA0, and L2CEWCR0) specifies a programmed memory range that can be allocated and optionally locked with a global write transaction. The address register must be naturally aligned to the window size in the corresponding control register. For more information, see L2 cache external write registers. Note that stashing can occur regardless of whether the L1 cache is enabled or whether the cache-inhibited bit in the MMU is set for the page. 6.8.1 Stash-only cache regions In order to prevent stashed I/O data from polluting processor data in the L2 cache (and vice versa), it is possible to create stash-only regions. This is controlled by the L2STASHCTL field of L2CTL. See L2 control register (L2_Cache_L2CTL). If a stash-only region is created, then that region of the cache is only used for stashed I/O data, and stashed I/O data does not cause the eviction of processor data; they are kept in separate ways of each set. The processor may allocate data into the ways of the cache that are not allocated to SRAM or stash-only memory. Replacement within the stash-only region and the processor region is governed by a pseudo-LRU algorithm modified by masks that allow only applicable ways of a cache set to be considered for replacement. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 214 Freescale Semiconductor, Inc. 6.9 L2 cache timing Chapter 6 L2 Look-Aside Cache/SRAM Table 6-42 shows the timing of back-to-back loads that miss in the L1 data cache and hit in the L2 cache, assuming the core is running at 2 1/2 times the L2 cache frequency. The L2 returns the 128 bits containing the requested data (critical quad word) first. This data is forwarded to the result register before the full cache line reloads the L1. Table 6-42. Fastest read timing-hit in L2 Core clocks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 e500 core load 1 to D-cache D-cache miss to CIU CIU Q to CIU LSU LSU reads coDmLmFaBnd LSU reads out data Result bus Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 215 L2 cache and SRAM coherency Table 6-42. Fastest read timing-hit in L2 (continued) Core clocks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 e500 core load 2 to D-cache D-cache miss to CIU CIU Q to CIU LSU LSU reads coDmLmFaBnd LSU reads out data Result bus CCB <1 2 3 clocks CCB addr bus load 1 BG1 TS2 CCB addr bus load 2 CCB data bus load 1 CCB data bus load 2 1. BG-Bus grant 2. TS-Transfer start 3. AACK-Address acknowledge 4 5 6 7 8 9 10 11< AACK3 HIT DATACOMING BG TS AACK HIT DATACOMING DATA DATA DATA DATA 6.10 L2 cache and SRAM coherency This section explains the rules of cache and memory-mapped SRAM coherency. The term 'snoop transaction' refers to transactions initiated by the system logic or by I/O traffic, as opposed to e500 core-initiated transactions. 6.10.1 L2 cache coherency rules L2 cache coherency rules are as follows: • The L2 is non-inclusive of the L1-valid L1 lines may be valid or invalid in the L2. • The L2 cache holds no modified data. Data is in one of four states-invalid, exclusive, exclusive locked, and stale. • The L2 allocates entries for data cast out or pushed (non-global, non-write-through write with kill) from the L1 caches. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 216 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM • Lines for e500 core-initiated burst read transactions are allocated as exclusive in the L2. • The L2 supports I/O devices reading data from valid lines in the L2 cache (data intervention) if L2CTL[L2INTDIS] = 0. An optional unlock attribute causes I/O reads to clear a lock when the read is performed. • The L2 cache does not respond to cache-inhibited read transactions. • e500 core-initiated, cache-inhibited store transactions invalidate the line when they hit on a valid L2 line. If the line is locked, it goes to the stale state. For other write transactions the cache-inhibited bit is ignored. • Non-burst cacheable write transactions from the e500 core (generated by writethrough cacheable stores) update a valid L2 cache line through a read-modify-write operation. • e500 core cast out transactions that hit on a stale line in the L2 cache cause a data update of the line and a change to the valid locked state for that line. • An e500 core-initiated, cacheable, non-write-through store that misses in the L1 and hits on a line in the L2 invalidates that line in the L2. If the line is marked exclusive locked, the L2 marks the line as stale. • Transactions that hit a stale L2 cache line that would cause an allocate if they miss cause a data update of the line (when data arrives from memory) and a change to the line's valid locked state. Data is not supplied by the L2 cache for the read in this case. • The following transactions kill the data and the respective locks when they hit a valid L2 line: • dcbf • dcbi • The L2 cache supports mixed cache external writes and core-initiated writes to the same addresses if the core-initiated writes are marked coherency-required, caching allowed, not write-through (WIMG = 001x) and the external writes are marked coherency-required, caching-allowed. • The L2 cache supports writes to the L2 cache from peripheral devices or from I/O controllers through snoop write transactions with addresses that hit in a programmed memory range. Full cache line (32-byte) write transactions update the data for a valid line in the L2 and if the line is not valid in the L2, a line is allocated. Sub-cache line write transactions update the data only for valid L2 cache lines through read-modifywrite operations. • The L2 cache supports burst writes that lock an L2 cache line from peripheral devices or from I/O controllers through write transactions with addresses that hit in a programmed memory range that has the lock attribute set. • The L2 cache supports burst writes that allocate and/or lock an L2 cache line from peripheral devices or I/O controllers through a write allocate transaction. See the system logic programming model (for example, that of the DMA controller) for details on how to set the transaction type for cache external writes to the L2. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 217 L2 cache locking 6.10.2 Memory-mapped SRAM coherency rules Memory-mapped SRAM coherency rules are as follows: • External (non-core-initiated) accesses to memory-mapped SRAM must be marked coherency-required. External accesses to memory-mapped SRAM marked coherency-not-required may cause an address unavailable error. • Accesses to memory-mapped SRAM are cacheable only in the corresponding e500 L1 caches. External accesses must be marked cache-inhibited or be performed with non-caching transactions. 6.11 L2 cache locking The caches can be locked and cleared using the following methods: • Cache locking methods • Individual line locks are set and cleared using instructions defined by the e500 cache locking APU, which is part of the Freescale Embedded Implementation Standards (EIS). These instructions include Data Cache Block Touch and Lock Set (dcbtls), Data Cache Block Touch for Store and Lock Set (dcbtstls), and Instruction Cache Block Touch and Lock Set (icbtls). For detailed information about these instructions, see the PowerPC e500 Core Reference Manual. • A lock attribute can be attached to write operations. • Individual line locks are set and cleared through core-initiated instructions, by external reads or writes, or by accesses to programmed memory ranges defined in L2 cache external write address registers (L2CEWARn). • The entire cache can be locked by setting configuration registers appropriately • Methods for clearing locks • Individual locks can be cleared by cache locking APU instructions (Instruction Cache Block Lock Clear (icblc) and Data Cache Block Lock Clear (dcblc)) or by snooped flush unless the entire cache is locked. • Flash clearing of all instruction and/or data locks can be done by writes to configuration registers. • An unlock attribute can be attached to I/O read operations. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 218 Freescale Semiconductor, Inc. 6.11.1 Locking the entire L2 cache Chapter 6 L2 Look-Aside Cache/SRAM The entire L2 cache can be locked by setting L2CTL[L2DO] = 1 and L2CTL[L2IO] = 1. This has the effect of preventing any further allocation of new lines in the cache by core requests. If there are lines in the cache that are not valid, they cannot be used by core requests until the cache is unlocked. While the cache is locked, read requests are serviced as normal, and snooping continues as normal to maintain coherency. Lines invalidated to satisfy coherency requirements cannot be reallocated by core requests while the cache remains locked. The L2 cache can be unlocked by clearing L2CTL[L2IO] and/or L2CTL[L2DO]. Note that L2CTL[L2DO] and L2CTL[L2IO] have no effect on cache external write allocations or memory-mapped SRAM. Note that this form of cache locking does not use the lock bits of the cache and cannot be cleared by resetting the cache or lock bits. 6.11.2 Locking programmed memory ranges A programmed memory range can be locked with a snoop write transaction that matches a cache external write address range (specified by L2CEWARn/L2CEWAREAn and L2CEWCRn). There are no clearing of locks through the programmed address ranges. Locks can be cleared using clear lock instructions, flushes, read-and-clear-lock snoop (RWNITC with clear lock attribute), or flash clear locks. 6.11.3 Locking selected lines Individual lines are locked when the L2 receives one of the following burst transactions: • icbtls (CT = 1)-Instruction Cache Block Touch and Lock Set instruction • dcbtls (CT = 1)-Data Cache Block Touch and Lock Set instruction • dcbtstls (CT = 1)-Data Cache Block Touch for Store and Lock Set instruction • Snoop burst write-If the address hits on a programmed cache external write space with the lock attribute set, or if the write allocate transaction type is used • Snoop non-burst write-If the address hits on a programmed cache external write space with the lock attribute set P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 219 L2 cache locking Note that the core complex broadcasts these instructions to the L2 if the CT field in the instruction specifies the L2 cache (CT = 1). When the L2 cache is specified, data is not placed in the L1, only the L2. If the L1 cache is specified (CT = 0), the L2 does not lock the line, and the data is placed in the L1 (and locked). When the touch lock set L2 instruction (dcbtls or dcbtstls) hits are modified in the L1 cache, the modified data is allocated into the L2 cache (and written back to main memory) and a data lock is set. The L1 line state transitions to invalid. Note that if the L2 receives a request to allocate and lock a line, but all lines in the selected way are locked, the requested L2 line is not allocated and the L2 cache lock overflow bit (L2CTL[L2LO]) is set. Lines invalidated to satisfy coherency requirements cannot be reallocated while the cache remains locked. 6.11.4 Clearing locks on selected lines Individual locks in the L2 are cleared by a lock clear (icblc or dcblc, CT = 1) instruction. This directs the L2 cache to clear a lock on that line if it hits in the L2 cache. Both data and instruction locks are cleared by the icblc and dcblc instructions. Note that the lock on a line is cleared if the line is invalidated by a snooped flush transaction, and the line in the cache is available for allocation of a new line of instruction or data unless the entire cache is locked. 6.11.5 Flash clearing of instruction and data locks Locks for instructions and data are recorded separately in the L2 cache, and they can be flash cleared separately by writing the appropriate value to the L2 cache control register (L2CTL[L2LFR] and L2CTL[L2LFRID]). Flash invalidating of the L2 (setting L2CTL[L2I]) clears all locks on both instructions and data. Note that flash clearing is the only way to clear data locks without clearing instruction locks, or to clear instruction locks without clearing data locks. All instructions and snoop transactions that clear locks clear both data and instruction locks. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 220 Freescale Semiconductor, Inc. 6.11.6 Locks with stale data Chapter 6 L2 Look-Aside Cache/SRAM If data is locked in the L2 and either the e500 core performs a cacheable copyback store or a dcbtst misses in the L1, the L2 invalidates the line; however, the L2 clears the valid bit for the data, the lock remains, and the line cannot be victimized. If the e500 core casts out modified data or pushes it in response to a non-flush snoop, the L2 updates the data and sets the valid bit again, maintaining the lock and keeping the data in the cache hierarchy. 6.12 PLRU L2 replacement policy Line replacement is determined using a pseudo least-recently-used (PLRU) algorithm. There is a valid bit (V0-V7) for each line. To determine the replacement victim (the line to be cast out), there are seven PLRU bits (P0-P6) for each set. PLRU bits are updated every time a new line is allocated and every time an existing line is read by the processor, updated by a write, or invalidated. Figure 6-43 shows the binary decision tree used to generate the victim line. The eight ways of the L2 cache are labeled W0-W7; the seven PLRU bits are labeled P0-P6. Figure 6-43. L2 cache line replacement algorithm P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 221 PLRU L2 replacement policy 6.12.1 PLRU bit update considerations PLRU bit updates depend on which cache way was last accessed, as summarized in Table 6-43. Table 6-43. PLRU bit update algorithm Last Way Accessed PLRU Bits P0 P1 P2 P3 P4 P5 P6 0 1 1 - 1 - - - 1 1 1 - 0 - - - 2 1 0 - - 1 - - 3 1 0 - - 0 - - 4 0 - 1 - - 1 - 5 0 - 1 - - 0 - 6 0 - 0 - - - 1 7 0 - 0 - - - 0 When an L2 line is invalidated, the PLRU bits are updated, marking the corresponding way as least-recently used. This causes the invalidated way to be selected as the next victim. 6.12.2 Allocation of lines The general PLRU algorithm described above must be modified to take into account special features of the L2 cache; namely SRAM regions, line locking, and stash-only regions. Each of these features reserves ways within each cache set such that some ways are not eligible for allocation/victimization by the general LRU algorithm. To preserve the state of the ways that are set aside for other special functions, the PLRU pointers are modified by a mask that is a function of the L2 configuration registers, the lock bits in the cache status array, and initiator of the transaction. The mask effectively points the PLRU algorithm away from ways that are not to be considered for replacement. L2 cache lines are locked through the status array lock bits. There are two lock bits for each way of each set (1024 sets by eight ways). These bits are set or cleared through special L2 controller commands.There are two sets of lock bits, one for instructions (I0I7) and one for data (D0-D7) for every line. The lock bits act as a mask over the PLRU bits to determine victim selection. The PLRU bits are updated regardless of line locking. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 222 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM Lock bits are used at allocate time to steer the PLRU algorithm away from selecting locked victims. In the following discussion, the eight lock bits for a particular set are called L0-L7. Where Lock Way i: Li = Di | Ii, i=0...7 (Di = data lock, Ii = instruction lock) An effective value of each PLRU bit is calculated as follows: L7)) P0_eff = f(P0,L0,L1,L2,L3,L4,L5,L6,L7) = (L0 & L1 & L2 & L3) | (P0 & ~(L4 & L5 & L6 & P1_eff = f(P1,L0,L1,L2,L3) = (L0 & L1) | (P1 & ~(L2 & L3)) P2_eff = f(P2,L4,L5,L6,L7) = (L4 & L5) | (P2 & ~(L6 & L7)) P3_eff = f(P3,L0,L1) = L0 | (P3 & ~L1) P4_eff = f(P4,L2,L3) = L2 | (P4 & ~L3) P5_eff = f(P5,L4,L5) = L4 | (P5 & ~L5) P6_eff = f(P6,L6,L7) = L6 | (P6 & ~L7) These effective PLRU bits are used to select a victim, as indicated in Table 6-44. Table 6-44. PLRU-based victim selection mechanism Way selected W0 W1 W2 W3 W4 W5 W6 W7 Effective PLRU state (binary) 00x0xxx 00x1xxx 01xx0xx 01xx1xx 1x0xx0x 1x0xx1x 1x1xxx0 1x1xxx1 Reduced logic equation (using effective PLRU bits) ~P0 & ~P1 & ~P3 ~P0 & ~P1 & P3 ~P0 & P1 & ~P4 ~P0 & P1 & P4 P0 & ~P2 & ~P5 P0 & ~P2 & P5 P0 & P2 & ~P6 P0 & P2 & P6 6.13 L2 cache operation This section describes the behavior of the L1 and L2 cache in response to various operations and configurations. 6.13.1 Initialization This section describes L2 cache initialization and memory-mapped SRAM initialization. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 223 L2 cache operation 6.13.1.1 L2 cache initialization After power-on reset the valid bits in the L2 cache status array are in random states. Therefore, it is necessary to perform a flash invalidate before using the array as an L2 cache. This is done by writing a one to the L2I field of the L2 control register (L2CTL). This can be done before or simultaneously with the write that enables the L2 cache. That is, the L2E and L2I bits of L2CTL can be set simultaneously. The L2I bit clears automatically, so no further writes are necessary. 6.13.1.2 Memory-mapped SRAM initialization After power-on reset the contents of the data and ECC arrays are random, so all SRAM data must be initialized before it is read. If the cache is initialized by the processor or any other device that uses sub-cache-line transactions, ECC error checking should be disabled during the initialization process to avoid false ECC errors generated during the read-modify-write process used for subcache-line writes to the SRAM array. This is done by setting the multi- and single-bit ECC error disable bits of the L2 error disable register (L2ERRDIS[MBECCDIS, SBECCDIS]). See L2 error disable register (L2_Cache_L2ERRDIS). If the array is initialized by a DMA engine using cache-line writes, ECC checking can remain enabled during the initialization process. 6.13.2 Flash invalidation of the L2 cache The L2 cache may be completely invalidated by setting the L2I bit of the L2 control register (L2CTL). Note that no data is lost in this process because the L2 cache is a write-through cache and contains no modified data. Flash invalidation of the cache is necessary when the cache is initially enabled and may be necessary to recover from some error conditions such as a tag parity error. The invalidation process requires several cycles to complete. The L2I bit remains set during this procedure and is then cleared automatically when the procedure is complete. The L2 cache controller issues retries for all transactions on the e500 core complex bus while the flash invalidation process is in progress. Note that the contents of memory-mapped SRAM regions of the data array are unaffected by a flash invalidation of the L2 cache regions of the array. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 224 Freescale Semiconductor, Inc. 6.13.3 Managing errors This section describes ECC and tag parity errors. Chapter 6 L2 Look-Aside Cache/SRAM 6.13.3.1 ECC errors An individual soft error that causes a single- or multi-bit ECC error can be cleared from the L2 array simply by performing a dcbf instruction on the address captured in the L2ERRADDR register. This invalidates the line in the L2 cache. When the load that caused the ECC error is performed again, the data is reallocated into the L2 with ECC bits set properly again. If the threshold for single bit errors set in the L2ERRCTL register is exceeded, then the L2 cache should be flash invalidated to clear out all single-bit errors. Note that no data is lost by dcbfs or flash invalidates, since the L2 cache is write-through and contains no modified data. 6.13.3.2 Tag parity errors A tag parity error must be fixed by flash invalidating the L2 cache. Note that a dcbf operation to the address that caused the error to be reported is not sufficient since a tag parity error is seen as an L2 miss and does not cause invalidation of the bad tag. Proper L2 operation cannot be guaranteed if an L2 tag parity error is not repaired by a flash invalidation of the entire cache. 6.13.4 L2 cache states The L2 status array uses four bits for each line to determine the status of the line. Different combinations of these bits result in different L2 states. The status bits are as follows: • Valid (V) • Instruction locked (IL) • Data locked (DL) • Stale (T) P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 225 L2 cache operation Table 6-45 shows L2 cache states. Note that these conventions are also used in Table 6-46. Table 6-45. L2 cache states V T IL DL L2 states 0 x x x Invalid (I) 1 0 0 0 Exclusive (E) 1 0 0 1 Exclusive data locked (EDL) 1 0 1 0 Exclusive instruction locked (EIL) 1 0 1 1 Exclusive instruction and data locked (EL) 1 1 0 0 Stale (data invalid, locks invalid) (T) 1 1 0 1 Stale (data invalid, dlock valid) (TDL) 1 1 1 0 Stale (data invalid, ilock valid) (TIL) 1 1 1 1 Stale (data invalid, locks valid) (TL) 6.13.5 L2 state transitions Table 6-46 lists state transitions for all e500 core-initiated transactions that change the L2 cache state. Core-initiated transactions caused when the core executes msync, mbar, tlbivax, or tlbsync do not change the L2 cache state. The table does not list initial L1 states for transactions that hit in the L1 (iL1 or dL1) and are not sent to the L2. In the table, the heading 'L2 hit' indicates that the L2 provides (on a read) or captures (on a write) data for an existing line. Some entries list two final L1 states. L2 touch instructions never allocate into iL1 or dL1. Note that if the L2 SRAM is disabled, the L2 initial and final states are always invalid and the L2 never hits. Similarly, if the L2 SRAM is in full memory-mapped SRAM mode, the L2 initial and final states are always invalid and the L2 never hits for addresses not in the memory-mapped SRAM address range. The L2 always hits for addresses in the enabled memory-mapped SRAM address ranges. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 226 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM Table 6-46. State transitions due to core-initiated transactions Source of transaction Cacheable instruction fetch icbtls_L1 icbt_L2 icbtls_L2 Cache-inhibited instruction fetch Cacheable load (4-state) Cacheable lwarx (4-state) dcbt_L1 (4-state) dcbtls_L1 (4-state) Cache-inhibited load Cache-inhibited lwarx Writeback Store Writeback stwcx Initial states L2 Final states Comments Hit L1 L2 L1 L2 iL1 I/T No I/V Same L2CTL[L2DO] = 1. L2 touch instructions not I allocated in L1 I No I/V E L2CTL[L2DO] = 0 dL1 E/EL Yes I/V Same - I,E T No I/V EL L2CTL[L2DO] = 0. Restore locked line in L2 with valid data from bus dL1 I/T No I Same L2CTL[L2DO] = 1 I,E E Yes I I L2CTL[L2DO] = 1 EL Yes I T L2CTL[L2DO] = 1 I No I EL L2CTL[L2DO] = 0 E Yes I EL L2CTL[L2DO] = 0 EL Yes I Same L2CTL[L2DO] = 0 T No I EL L2CTL[L2DO] = 0. Restore locked line in L2 with valid data from bus N/A N/A No N/A N/A No L1/L2 effect dL1 I/T No E Same L2CTL[L2IO] = 1 I E Yes E I L2CTL[L2IO] = 1 EL Yes E T L2CTL[L2IO] = 1 I No E E L2CTL[L2IO] = 0 E/EL Yes E Same L2CTL[L2IO] = 0 T No EL EL L2CTL[L2IO] = 0. Restore locked line in L2 with valid data from bus N/A N/A No N/A N/A No L1/L2 effect N/A N/A No N/A N/A No L2 effect dL1 I/T No M Same L2 allocates when a line is cast out of L1. I E Yes M I- EL Yes M T- dL1 I/T No M Same - I E Yes M I- EL Yes M T- Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 227 L2 cache operation Table 6-46. State transitions due to core-initiated transactions (continued) Source of transaction Cacheable load (3-state) Cacheable lwarx (3-state) dcbt_L1 (3-state) dcbtls_L1 (3-state) dcbt_L2 dcbtst_L2 dcbtst_L1 dcbtstls_L1 dcbtls_L2 dcbtstls_L2 Write-through store Cache-inhibited store Cache-inhibited stwcx dcblc_L2 icblc_L2 Initial states L1 L2 dL1 I I L2 Final states Comments Hit L1 L2 No E/I Same L2CTL[L2IO] = 1 dL1 I,E dL1 I dL1 I,E dL1 I,E,M N/A N/A dL1 I,E,M T No E/I Same L2CTL[L2IO] = 1 E Yes E/I I L2CTL[L2IO] = 1 EL Yes E/I T L2CTL[L2IO] = 1 I No E/I E L2CTL[L2IO] = 0 E/EL Yes E/I Same L2CTL[L2IO] = 0 T No E/I EL L2CTL[L2IO] = 0. Restore locked line with valid data from bus I/T No E Same - E Yes E I- EL Yes E T- I No I Same L2CTL[L2IO] = 1 T E EL I E/EL T I/T No I Same L2CTL[L2IO] = 1 Yes I I L2CTL[L2IO] = 1 Yes I T L2CTL[L2IO] = 1 No I EL L2CTL[L2IO] = 0 Yes I EL L2CTL[L2IO] = 0 No I EL L2CTL[L2IO] = 0. Restore locked line with valid data from bus No same I - E/EL I/E EL/T I/E EL/T I/E Yes same Same Read-modify-write No N/A I Invalidate line No N/A T Invalidate data, keep lock No N/A I Invalidate line No N/A T Invalidate data, keep lock No same Same - EL No same E T No same I - Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 228 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM Table 6-46. State transitions due to core-initiated transactions (continued) Source of transaction Victim castout dcbt_L2 icbt_L2 dcbtst_L2 Initial states L1 L2 dL1 I/T M L2 Final states Comments Hit L1 L2 No I Same L2CTL[L2IO] = 1. If software sharing cache lines between instructions and data wishes to capture instruction lines in L2 with L2CTL[L2IO] = 1, it must perform dcbst to flush the line out of the dL1 before fetching it into L2. dcbtls_L2 icbtls_L2 dcbtstls_L2 Snoop push dcbf dcbst dcbz dcba dcbi dcbf dcbst icbi I No I E L2CTL[L2IO] = 0 E/EL No I I/T L2CTL[L2IO] = 1. Yes I Same L2CTL[L2IO] = 0. T Yes I EL L2CTL[L2IO = 0. dL1 I No I EL An icbtls_L2 that hits modified in L1 cannot be M distinguished from dcbtls_L2 and sets the L2 dlock bit. If software shares cache lines between instructions and data and wishes to set locks in L2, it must perform dcbst to flush the line out of the dL1 before locking it in L2. E/EL/T Yes I EL - dL1 I/E No I/E I- M EL/T No I/E T Invalidate data, keep lock dL1 I/E/EL No I I- M dL1 I/E No M I- I EL No M T- dL1 I/ No I I- I,E,M E/EL/T dL1 I/ No I I- I,E E/EL/T iL1 I/ No I I- I,V E/EL/T Table 6-47 lists L2 cache state transitions for all system-initiated (non-core) transactions that change the L2. The transaction types and attributes listed follow MPX bus nomenclature, with the addition of write allocate (burst write with L2 cache allocation). Table 6-47 accounts for changes caused by L1 snoop pushes triggered by snoops, listed in Table 6-46. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 229 L2 cache operation Table 6-47. State transitions due to system-initiated transactions Transaction type Clean IKill Flush Write allocate wt ci gbl Initial L2 state x x0 I/E/EL/T x x0 x 10 I/E/EL/T I/E/EL/T x 10 x 00 WWK x 32-byte WWF 32-byte WWF atomic 10 x 00 < 32-byte WWF x < 32-byte WWF atomic 10 I/E EL/T I/E EL/T I/E/EL/T I EL E T I/E EL/T I/E EL/T I/T EL E Read Read atomic RWNITC x 00 1 10 I/E EL/T I/T E EL x 00 N/A 1 10 I/T E EL 0 10 I EL T x 00 N/A Final L2 state Same I EL E EL I T I E/EL Same E/EL EL I T I T Same Same E/EL I T Same Same Same N/A Same Same Same Same E I N/A Comments - Allocate and lock regardless of cache external write (CEW) window Allocate regardless of CEW window No allocate if cache-inhibited Invalidate data, keep lock Miss in cache external write windows Hit in cache external write window Hit in cache external write window Hit in cache external write window Hit in cache external write window Invalidate line Invalidate data, keep lock Miss in cache external write windows Miss in cache external write windows. Hit in CEW window but need burst data Hit in cache external write window Hit in cache external write window. Set lock if CEW lock attribute set. Invalidate line Invalidate data, keep lock - No L1/L2 effect Read-and-clear-lock No L1/L2 effect Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 230 Freescale Semiconductor, Inc. Chapter 6 L2 Look-Aside Cache/SRAM Table 6-47. State transitions due to system-initiated transactions (continued) Transaction type Kill RWITM RWITM atomic RClaim wt ci gbl Initial L2 state x 10 I/E x 00 EL/T I/E/EL/T Final L2 state I T Same Comments - Invalidate data, keep lock - 6.14 Error checking and correcting (ECC) The L2 cache supports error checking and correcting (ECC) for the data path between the core master and system memory. It detects all double-bit errors, detects all multi-bit errors within a nibble, and corrects all single-bit errors. Other errors may be detected, but are not guaranteed to be corrected or detected. Multiple-bit errors are always reported when error reporting is enabled. When a single-bit error occurs, the single-bit error counter register is incremented, and its value compared to the single-bit error trigger register. An error is reported when these values are equal. The single-bit error registers can be programmed such that minor memory faults are corrected and ignored, but double- or multi-bit errors generate an interrupt. The syndrome encodings for the ECC code are shown in Table 6-48 and Table 6-49. Table 6-48. L2 cache ECC syndrome encoding Data Syndrome bit bit 0 1 2 3 4 5 6 7 0 • • • 1• • • 2• • • 3• • • 4 • • • 5• • • 6• • • 7• • • 8 • • • 9• • • 10 • • • Data Syndrome bit bit 0 1 2 3 4 5 6 7 32 • • • 33 • • • 34 • • • 35 • • • 36 • • • 37 • • • 38 • • • • • 39 • • • • • 40 • • • 41 • • • 42 • • • • • Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 231 Error checking and correcting (ECC) Table 6-48. L2 cache ECC syndrome encoding (continued) Data Syndrome bit bit 0 1 2 3 4 5 6 7 11 • • • 12 • • • • • 13 • • • • • 14 • • • • • 15 • • • • • 16 • • • 17 • • • 18 • • • 19 • • • 20 • • • 21 • • • 22 • • • 23 • • • • • 24 • • • 25 • • • 26 • • • 27 • • • • • 28 • • • • • 29 • • • • • 30 • • • • • 31 • • • • • Data Syndrome bit bit 0 1 2 3 4 5 6 7 43 • • • • • 44 • • • • • 45 • • • • • 46 • • • • • 47 • • • • • 48 • • • 49 • • • 50 • • • 51 • • • 52 • • • 53 • • • 54 • • • 55 • • • 56 • • • 57 • • • 58 • • • 59 • • • 60 • • • 61 • • • • • 62 • • • • • 63 • • • • • Table 6-49. L2 cache ECC syndrome encoding (check bits) Check bit 0 1 2 3 4 5 6 7 Syndrome bit 0 1 2 3 4 5 6 7 • • • • • • • • P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 232 Freescale Semiconductor, Inc. Chapter 7 e500 Coherency Module The e500 coherency module (ECM) provides a flexible switching structure for routing e500- and I/O-initiated transactions to target modules on the device. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 233 Introduction 7.1 Introduction The e500 coherency module (ECM) provides a flexible switching structure for routing e500- and I/O-initiated transactions to target modules on the device. Figure 7-1 shows a high-level block diagram of the ECM. Figure 7-1. e500 coherency module block diagram 7.1.1 Overview The ECM routes transactions initiated by the e500 cores to the appropriate target interface on the device. In a manner analogous to a bridging router in a local area network, the ECM forwards I/ O-initiated transactions that are tagged with the global attribute onto the core complex bus (CCB). This allows on-chip caches to snoop these transactions as if they were locally initiated and to take actions to maintain coherency across cacheable memory. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 234 Freescale Semiconductor, Inc. 7.1.2 Features Chapter 7 e500 Coherency Module The ECM includes these distinctive features: • Support for two e500 cores and an L2/SRAM on the CCB, including a CCB arbiter. • Sources a 64-bit data bus for returning read data from the ECM to the e500 cores and routing write data from the ECM to the L2/SRAM. It sinks a 128-bit data bus for receiving data from the L2/SRAM and two128-bit write data buses-one from each of the e500 cores. • Four connection points for I/O initiating (mastering into the device) interfaces. The ECM supports five connection points for I/O targets. The DDR memory controllers, enhanced local bus, OCeaN targets, and configuration register access block all have a target port connection to the ECM. • Split transaction support-separate address and data tenures allow for pipelining of transactions and out-of-order data tenures between initiators and targets. • Proper ordering of I/O-initiated transactions. • Speculative read bus for low-latency dispatch of reads to the DDR controllers. • Low-latency paths for returning read data from DDR to the e500 cores. • Error registers trap transactions with invalid addresses. Errors can be programmed to generate interrupts to the e500 core, as described in the following sections: • ECM error detect register (ECM_EEDR) • ECM error enable register (ECM_EEER) • ECM error attributes capture register (ECM_EEATR) • ECM error low address capture register (ECM_EELADR) • ECM error high address capture register (ECM_EEHADR) • Errors from reading I/O devices terminate with data sent to the master with a corrupt attribute. If the master is the e500 core, the ECM asserts core_fault_in to the core, which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and one of these errors occurs, appropriate interrupts must be enabled to ensure that an interrupt is generated. 7.2 ECM memory map/register definition The table below shows the register memory map for the ECM. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 235 ECM memory map/register definition ECM memory map Offset address (hex) 1000 1010 1BF8 1BFC 1E00 1E08 1E0C 1E10 1E14 Register name ECM CCB address configuration register (ECM_EEBACR) ECM CCB port configuration register (ECM_EEBPCR) ECM IP Block Revision Register 1 (ECM_EIPBRR1) ECM IP Block Revision Register 2 (ECM_EIPBRR2) ECM error detect register (ECM_EEDR) ECM error enable register (ECM_EEER) ECM error attributes capture register (ECM_EEATR) ECM error low address capture register (ECM_EELADR) ECM error high address capture register (ECM_EEHADR) Width (in bits) Access Reset value 32 R/W 0000_0003h 32 R/W See section 32 R 0001_0000h 32 R 0000_0000h 32 w1c 0000_0000h 32 R/W 0000_0000h 32 R 0000_0000h 32 R 0000_0000h 32 R 0000_0000h Section/ page 7.2.1/236 7.2.2/237 7.2.3/239 7.2.4/239 7.2.5/240 7.2.6/241 7.2.7/242 7.2.8/244 7.2.9/244 7.2.1 ECM CCB address configuration register (ECM_EEBACR) The ECM CCB address configuration register controls arbitration and streaming policies for the CCB. Address: 1000h base + 0h offset = 1000h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W A_STRM_ CNT A_STRM_DIS CORE_STRM_ DIS Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ECM_EEBACR field descriptions Field 0–27 - This field is reserved. Reserved Description Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 236 Freescale Semiconductor, Inc. Chapter 7 e500 Coherency Module ECM_EEBACR field descriptions (continued) Field Description 28 A_STRM_DIS Controls whether the ECM allows any streaming to occur. 0 Streaming is enabled. 1 Streaming is disabled. 29 With A_STRM_DIS, controls whether the e500 cores can stream commands onto the CCB . CORE_STRM_ A_STRM_DIS and CORE_STRM_DIS must both be cleared for the e500 cores to be enabled to stream DIS their address tenures that they master. 30–31 A_STRM_CNT 0 Stream address tenures initiated by the e500 cores , provided A_STRM_DIS is cleared. 1 Streaming of address tenures initiated by the e500 cores not allowed. Stream count. Specifies the maximum number of transactions that any master can stream (issue sequentially without preemption) on the CCB following an initial transaction. 00 Reserved 01 One transaction can be streamed with the initial transaction. 10 Two transactions can be streamed with the initial transaction. 11 Three transactions can be streamed with the initial transaction. Default. 7.2.2 ECM CCB port configuration register (ECM_EEBPCR) Address: 1000h base + 10h offset = 1010h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reserved CPU1_EN CPU0_EN Reserved CPU_RD_HI_DIS Reset 0 0 0 0 0 0 n n 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W CPU1_PRI CPU0_PRI Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 237 ECM memory map/register definition ECM_EEBPCR field descriptions Field 0–5 - 6 CPU1_EN Description This field is reserved. Reserved CPU1 port enable Controls boot holdoff mode when the device is an agent of an external host or when the other core is used to perform initialization prior to allowing this core to boot. Specifies whether the e500 core (CPU) port1 is enabled to run transactions on the CCB. The CPU boot configuration power-on reset signal (cfg_cpu1_boot) determines the initial value of this bit. If the signal is sampled as a logic 1 at the negation of reset, CPU1 is enabled to boot at the end of the POR sequence. Otherwise, CPU1 cannot fetch its boot vector until an external host or another core sets the CPU1_EN bit. After this bit is set, it should not be cleared by software. It is not intended to dynamically enable and disable CPU operation. It is only intended to end boot holdoff mode. See CPU boot configuration , for more information. The settings are as follows: 7 CPU0_EN 0 Boot holdoff mode. CPU1 arbitration is disabled on the CCB and no bus grants are issued. 1 CPU1 is enabled and receives bus grants in response to bus requests for the boot vector. CPU 0 port enable Controls boot holdoff mode when the device is an agent of an external host or when the other core is used to perform initialization prior to allowing this core to boot . Specifies whether the e500 core (CPU) port0 is enabled to run transactions on the CCB. The CPU boot configuration power-on reset pin (cfg_cpu0_boot) determines the initial value of this bit. If the pin is sampled as a logic 1 at the negation of reset,CPU0 is enabled to boot at the end of the POR sequence. Otherwise,CPU0 cannot fetch its boot vector until an external host or another coresets the CPU0_EN bit. After this bit is set, it should not be cleared by software. It is not intended to dynamically enable and disable CPU operation. It is only intended to end boot holdoff mode. See CPU boot configuration , for more information. The settings are as follows: 8–25 - 26–27 CPU1_PRI 0 Boot holdoff mode. CPU0 arbitration is disabled on the CCB and no bus grants are issued. 1 CPU0 is enabled and receives bus grants in response to bus requests for the boot vector. This field is reserved. Reserved Identifies the priority level of the e500 core 1 (CPU) port . This priority level is used to determine whether a particular port's bus request can cause the CCB Arbiter to terminate another port's streaming of address tenures. 00 Lowest priority level 01 Second lowest priority level 10 Highest priority level 11 Reserved 28 This field is reserved. - Reserved 29 Identifies which read queue of DDR targets is assigned to the e500 core (CPU) ports' read transactions (in CPU_RD_HI_DIS understressed system). 0 Read high queue (higher bandwidth DDR queue) is assigned for the e500 cores' read transactions 1 Read low queue (lower bandwidth DDR queue) is assigned for the e500 cores' read transactions Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 238 Freescale Semiconductor, Inc. Field 30–31 CPU0_PRI Chapter 7 e500 Coherency Module ECM_EEBPCR field descriptions (continued) Description Specifies the priority level of the e500 core 0 (CPU) port . This priority level is used to determine whether a particular port's bus request can cause the CCB arbiter to terminate another port's streaming of address tenures. 00 Lowest priority level 01 Second lowest priority level 10 Highest priority level 11 Reserved 7.2.3 ECM IP Block Revision Register 1 (ECM_EIPBRR1) Address: 1000h base + BF8h offset = 1BF8h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IP_ID IP_MJ IP_MN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECM_EIPBRR1 field descriptions Field 0–15 IP_ID 16–23 IP_MJ 24–31 IP_MN IP block ID Major revision Minor revision Description 7.2.4 ECM IP Block Revision Register 2 (ECM_EIPBRR2) Address: 1000h base + BFCh offset = 1BFCh Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W IP_INT Reserved IP_CFG Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECM_EIPBRR2 field descriptions Field 0–7 - This field is reserved. Reserved Description Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 239 ECM memory map/register definition ECM_EIPBRR2 field descriptions (continued) Field 8–15 IP_INT 16–23 - 24–31 IP_CFG IP block integration options This field is reserved. Reserved IP block configuration options Description 7.2.5 ECM error detect register (ECM_EEDR) Address: 1000h base + E00h offset = 1E00h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MULT_ERR R W w1c Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R LAE Reserved W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECM_EEDR field descriptions Field 0 MULT_ERR Description Multiple error Indicates the occurrence of multiple errors of the same type. Write 1 to clear. 0 Multiple errors of the same type were not detected. 1 Multiple errors of the same type were detected. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 240 Freescale Semiconductor, Inc. Field 1–30 - 31 LAE Chapter 7 e500 Coherency Module ECM_EEDR field descriptions (continued) Description This field is reserved. Reserved Local access error Write 1 to clear. The following two cases can generate LAEs: • Transaction does not map to any target. In this case the ECM injects read responses (with the corrupt attribute set) and write data is dropped. Note that a read that attempts to access an unmapped target causes the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and this error occurs, EEER[LAEE] must be set to ensure that an interrupt is generated. • Source and target IDs indicate that an OCN port initiated a transaction that targets an OCN port. This loopback behavior can result from programming errors where inbound ATMU window targets are inconsistent with targets configured in the local access windows for a given address range. For this type of LAE, the dispatch (to OCN target in this case) is not screened off; the LAE error is reported, but the transaction is still sent to its OCN target. 0 Local access error has not occurred. 1 Local access error occurred. 7.2.6 ECM error enable register (ECM_EEER) The ECM error enable register (EEER) enables the reporting of error conditions to the e500 core through the internal int interrupt signal. Address: 1000h base + E08h offset = 1E08h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0–30 31 LAEE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved LAEE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECM_EEER field descriptions Description This field is reserved. Reserved Local access error enable Note that a read that attempts to access an unmapped target causes the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If HID1[RFXE] is zero and this error occurs, LAEE must be set to ensure that an interrupt is generated. 0 Disable reporting local access errors as interrupts. 1 Enable reporting local access errors as interrupts . P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 241 ECM memory map/register definition 7.2.7 ECM error attributes capture register (ECM_EEATR) Address: 1000h base + E0Ch offset = 1E0Ch Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W BYTE_CNT Reserved SRC_ID Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TTYPE Reserved W VAL Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECM_EEATR field descriptions Field 0–2 - This field is reserved. Reserved Description Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 242 Freescale Semiconductor, Inc. Field 3–7 BYTE_CNT 8–10 - 11–15 SRC_ID 16 - Chapter 7 e500 Coherency Module ECM_EEATR field descriptions (continued) Description Byte count. Specifies the transaction byte count. 00000 00001 00010 00100 01000 10000 32 bytes 1 byte 2 bytes 4 bytes 8 bytes 16 bytes This field is reserved. Reserved Source ID. Specifies the source device mastering the transaction. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Reserved PCI Express 2 PCI Express 1 Reserved Reserved USB 1 Reserved Security Reserved Reserved Boot sequencer eSDHC Reserved Reserved Reserved DMA controller Processor 0 (instruction) Processor 0 (data) Processor 1 (instruction) Processor 1 (data) USB 2 DMA Reserved System access port (SAP) eTSEC 1 eTSEC 2 eTSEC 3 Reserved Reserved Reserved Reserved Reserved This field is reserved. Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 243 ECM memory map/register definition ECM_EEATR field descriptions (continued) Field 17–20 TTYPE Transaction type. Defined as follows: All other settings are reserved. Description 21–30 - 31 VAL 0000 0010 0011 0100 1000 1001 1100 1101 1110 1111 Write Write with allocate Write with allocate with lock Address only transaction Read Read with unlock Read with clear atomic Read with set atomic Read with decrement atomic Read with increment atomic This field is reserved. Reserved Register data valid. 0 ECM error attribute capture register does not contain valid information. 1 ECM error attribute capture register contains valid information. 7.2.8 ECM error low address capture register (ECM_EELADR) Address: 1000h base + E10h offset = 1E10h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ADDR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECM_EELADR field descriptions Field 0–31 ADDR Description Address. Specifies the lower-order 32 bits of the 36-bit address of the transaction. Qualified by EEATR[VAL]. 7.2.9 ECM error high address capture register (ECM_EEHADR) Address: 1000h base + E14h offset = 1E14h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W ADDR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 244 Freescale Semiconductor, Inc. Field 0–27 - 28–31 ADDR Chapter 7 e500 Coherency Module ECM_EEHADR field descriptions Description This field is reserved. Reserved Address. Specifies the high-order 4 bits of the 36-bit address of the transaction. Qualified by EEATR[VAL]. 7.3 Functional description The following is a general discussion of ECM operation. 7.3.1 I/O arbiter Figure 7-1 shows the I/O arbiter block that manages I/O-initiated address tenure requests arriving on the request buses. Four request buses compete for access to the ECM, which can only process one request at a time. The ECM uses two factors to select the winning request bus: the primary factor is requested bandwidth and the secondary factor is longest waiting/least recently granted status. By default all requesters start requesting low levels of bandwidth. A starvation avoidance algorithm ensures that low bandwidth requesters make forward progress in the presence of high bandwidth requesters. The transaction from the winning request bus competes with e500 core requests for the CCB and entry into the transaction queue. 7.3.2 CCB arbiter Figure 7-1 shows the CCB arbiter block coordinating the entry of new transactions into the ECM's transaction queue . It handles arbitration for requests to use the CCB from the e500 cores and the winning request bus and consequently controls when these new transactions can enter the transaction queue. Because the CCB bus operates most efficiently when it streams commands from one initiator, the CCB arbiter alternates grants between streams of transactions from the e500 cores and from the winner of the I/O arbiter. The length of a stream (number of back-toback transactions) is limited by the A_STRM_CNT field in the EEBACR register. However, the arbiter also uses the priority of the requests to limit streaming. If the P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 245 Functional description priority of a new request is higher than that of a stream in progress, then the higher priority transaction interrupts the other stream. The priority of e500 transactions is set by the CPU[0/1]_PRI field in EEBPCR register. Depending how the CPU_RD_HI_DIS field in EEBPCR register is set, read transactions from the e500 cores are initially assigned to either the higher- or lower-bandwidth queue of the DDR target. 7.3.3 Transaction queue The ECM's transaction queue performs four basic functions: arbitration across the e500 cores and I/O masters, target mapping and dispatching, enforcement of ordering, and enforcement of coherency. The address of each transaction is compared against each local access window, and the transaction is then routed to the appropriate target interface associated with the local access window that the address hits within. Even though the CCB and ECM allow the pipelining of transactions, the address tenures of all transactions issued from I/O masters (masters other than the e500 cores) may still be ordered. For those transactions accessing address space marked as snoopable, or space that may be cached by the e500 cores, the ECM enforces coherency, snooping those transactions on the CCB, and taking castouts from the e500 cores as is necessary. 7.3.4 Global data multiplexor The global data mux allows initiators of write transactions to route data to their targets and read targets to return data to the initiators. See Figure 7-1 for an illustration of how the global data multiplexor takes data bus connections and multiplexes them onto one 128-bit global data bus. 7.3.5 CCB interface This interface formats CCB address tenures for the ECM transaction queue. It also contains the queueing and buffering needed to manage outstanding CCB data tenures. The buffers receive e500 core-initiated write and I/O-initiated read data (that hit in the L2/SRAM module) from the e500 write (128-bit wide) and read (128-bit wide) data buses and route them through the global data mux to the global data bus. The buffers also receive e500 core-initiated read and I/O-initiated write data (that hit in the L2/SRAM module) from the global data bus and forward them onto the CCB data bus (64 bits). Figure 7-1 shows the CCB interface for both CCB address and data tenures. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 246 Freescale Semiconductor, Inc. Chapter 7 e500 Coherency Module 7.4 Initialization/application information If either e500 core is used to initialize the device, the applicable CPU boot configuration power-on reset pin should be pulled high to initially set EEBPCR[CPU0_EN] or EEBPCR[CPU1_EN]. See Reset, Clocking, and Initialization for more information on power-up reset initialization. If any device other than the e500 cores is used to initialize the device, the CPU boot configuration power-on reset pins should be pulled low to initially clear EEBPCR[CPU0_EN] and EEBPCR[CPU1_EN]. This prevents the e500 cores from accessing any configuration registers or local memory space during initialization. However, in any such system, one step near the end of the initialization routine must set EEBPCR[CPU0_EN] and EEBPCR[CPU1_EN] to re-enable the e500 cores. Note that for basic functionality, EEBPCR[CPU0/1_EN] is the only field that must be written (provided a device other than the e500 cores is used to initialize the device) in the ECM. EEBPCR[CPU0_PRI] and EEBPCR[CPU1_PRI] specify the priority level associated with all e500 core initiated transactions. These values allow users running time-critical applications to adjust the average response latency of transactions initiated by the cores compared to those initiated by I/O masters. These priority levels affect whether e500 core requests can interrupt the streaming of address tenures initiated by (the ECM on behalf of) I/O masters or the other e500 core. Only transactions with a priority greater than the current CCB transaction can interrupt streaming. The higher the core's priority, the lower the average latency needed for it to obtain bus grants from the ECM because it can interrupt lower priority streaming. The default value of zero gives all core-initiated transactions the lowest priority, which prevents the cores from interrupting I/O master transaction streams. EEBACR[A_STRM_CNT] allows users to balance response latency with throughput and should prove useful in tuning systems with multiple time-critical tasks. The default value of 0b11 causes the ECM to attempt to stream as many as four transactions initiated from the same CCB master. Decreasing this value decreases the maximum number of transactions that may be streamed together from any one CCB master. Decreasing this value can decrease throughput for high priority transactions, but may decrease latency for lower priority transactions from another CCB master. Note that the e500 cores must also have streaming enabled (through HID1[ASTME] in each core) for the CCB to stream. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 247 Initialization/application information P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 248 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers The fully programmable DDR SDRAM controller supports most JEDEC standard x8, x16, or x32 DDR2 and DDR3 memories available. In addition, unbuffered and registered DIMMs are supported. 8.1 Introduction The fully programmable DDR SDRAM controller supports most JEDEC standard x8, x16, or x32 DDR2 and DDR3 memories available. In addition, unbuffered and registered DIMMs are supported. However, mixing different memory types or unbuffered and registered DIMMs in the same system is not supported. Built-in error checking and correction (ECC) ensures very low bit-error rates for reliable high-frequency operation. Dynamic power management and auto-precharge modes simplify memory system design. A large set of special features, including ECC error injection, support rapid system debug. NOTE In this chapter, the word 'bank' refers to a physical bank specified by a chip select; 'logical bank' refers to one of the four or eight sub-banks in each SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank address (MBA) pins during a memory access. The figure below is a high-level block diagram of the DDR memory controller with its associated interfaces. Functional description contains detailed figures of the controller. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 249 Features Figure 8-1. DDR memory controller simplified block diagram 8.2 Features The DDR memory controller includes these distinctive features: • Support for DDR2 and DDR3 SDRAM • 32-/40-bit SDRAM data bus for DDR2 and DDR3 • Support for DRAM clocking asynchronously from the platform clock • Programmable settings for meeting all SDRAM timing parameters • Support for the following SDRAM configurations: • As many as two physical banks (chip selects), each bank independently addressable • 64-Mbit to 4-Gbit devices depending on internal device configuration with x8/x16/x32 data ports (no direct x4 support) • Unbuffered and registered DIMMs • Chip select interleaving support • Partial array self refresh support P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 250 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers • Support for data mask signals and read-modify-write for sub-double-word writes. Note that a read-modify-write sequence is only necessary when ECC is enabled. • Support for double-bit error detection and single-bit error correction ECC (8-bit check word across 32-bit data) • Support for address parity for registered DIMMs • Open page management (dedicated entry for each logical bank) • Automatic DRAM initialization sequence or software-controlled initialization sequence • Automatic DRAM data initialization • Write leveling supported for DDR3 memories • Support for up to eight posted refreshes • Memory controller clock frequency of two or four times the SDRAM clock with support for sleep power management • Support for error injection 8.2.1 Modes of operation The DDR memory controller supports the following modes: • Dynamic power management mode. The DDR memory controller can reduce power consumption by negating the SDRAM CKE signal when no transactions are pending to the SDRAM. • Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the memory controller to issue an auto-precharge command with every read or write transaction. Auto-precharge mode can be enabled for separate chip selects by setting CSn_CONFIG[AP_n_EN]. 8.3 External signal descriptions This section provides descriptions of the DDR memory controller's external signals. It describes each signal's behavior when the signal is asserted or negated and when the signal is an input or an output. 8.3.1 Signals overview Memory controller signals are grouped as follows: P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 251 External signal descriptions • Memory interface signals • Clock signals The table below shows all signals of DDR controller. The device hardware specification shows detailed multiplexing of these signal. Note that availability of all signals depends upon device configurations. Table 8-1. DDR memory interface signal summary Name Function/description MAPAR_ERR_B Address parity error MAPAR_OUT Address parity out MDQ[ 0:31 ] Data bus MDQS[0:3]+ MDQS[8] Data strobes MDQS_B[0:3]+ MDQS_B [8] Complement data strobes MECC[0:7] Error checking and correcting MCAS_B Column address strobe MA[15:0] Address bus MBA[2:0] Logical bank address MCS_B[ 0:1] Chip selects MWE_B Write enable MRAS_B Row address strobe MDM[0:3]+MDM[8] Data mask MCK [0:3] DRAM clock outputs MCK_B[0:3] DRAM clock outputs (complement) MCKE[ 0:1] DRAM clock enable MODT[ 0:1] DRAM on-die termination external control MDIC[0:1] Driver impedance calibration Reset One Zero All zeros All zeros Pins 1 1 32 5 I/O I O I/O I/O All ones 5 I/O All zeros 8 I/O One 1 O All zeros 16 O All zeros 3 O All ones 2 O One 1 O One 1 O All zeros 5 O All zeros 4 O All zeros 4 O All zeros 2 O All zeros 2 O 10 2 I/O This table shows the memory address signal mappings. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 252 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-2. Memory address signal mappings Signal name (Outputs) msb MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 lsb MA0 msb MBA2 MBA1 lsb MBA0 JEDEC DDR DIMM signals (Inputs) A15 A14 A13 A12 A11 A10 (AP for DDR)1 A9 A8 (alternate AP for DDR)2 A7 A6 A5 A4 A3 A2 A1 A0 MBA2 MBA1 MBA0 1. Auto-precharge for DDR signaled on A10 when DDR_SDRAM_CFG[PCHB8] = 0 2. Auto-precharge for DDR signaled on A8 when DDR_SDRAM_CFG[PCHB8] = 1 8.3.2 Detailed signal descriptions The following sections describe the DDR SDRAM controller input and output signals, the meaning of their different states, and relative timing information for assertion and negation. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 253 External signal descriptions 8.3.2.1 Memory interface signals This table describes the DDR controller memory interface signals. Table 8-3. Memory interface signals-detailed signal descriptions Signal MDQ[ 0:31 ] MDQS[0:3] +MDQS[8]/ MDQS_B[0:3] +MDQS_B[8] I/O Description I/O Data bus. Both input and output signals on the DDR memory controller. O As outputs for the bidirectional data bus, these signals operate as described below. State Asserted/Negated-Represent the value of data being driven by the DDR memory controller. meaning Timing Assertion/Negation-Driven coincident with corresponding data strobes (MDQS) signal. High impedance-No READ or WRITE command is in progress; data is not being driven by the memory controller or the DRAM. I As inputs for the bidirectional data bus, these signals operate as described below. State Asserted/Negated-Represents the state of data being driven by the external DDR Meaning SDRAMs. Timing Assertion/Negation-The DDR SDRAM drives data during a READ transaction. High impedance-No READ or WRITE command in progress; data is not being driven by the memory controller or the DRAM. I/O Data strobes. Inputs with read data, outputs with write data. The data strobes may be single ended or differential. O As outputs, the data strobes are driven by the DDR memory controller during a write transaction. The memory controller always drives these signals low unless a read has been issued and incoming data strobes are expected. This keeps the data strobes from floating high when there are no transactions on the DRAM interface. State Asserted/Negated-Driven high when positive capture data is transmitted and driven low Meaning when negative capture data is transmitted. Centered in the data "eye" for writes; coincident with the data eye for reads. Treated as a clock. Data is valid when signals toggle. See Table 8-58 for byte lane assignments. Timing Assertion/Negation-If a WRITE command is registered at clock edge n, and the latency is programmed in TIMING_CFG_2[WR_LAT] to be m clocks, data strobes at the DRAM assert coincident with the data on clock edge n + m. See the JEDEC DDR SDRAM specification for more information. I As inputs, the data strobes are driven by the external DDR SDRAMs during a read transaction. The data strobes are used by the memory controller to synchronize data latching. State Asserted/Negated-Driven high when positive capture data is received and driven low when Meaning negative capture data is received. Centered in the data eye for writes; coincident with the data eye for reads. Treated as a clock. Data is valid when signals toggle. See Table 8-58 for byte lane assignments. Timing Assertion/Negation-If a READ command is registered at clock edge n, and the latency is programmed in TIMING_CFG_1[CASLAT] to be m clocks, data strobes at the DRAM assert coincident with the data on clock edge n + m. See the JEDEC DDR SDRAM specification for more information. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 254 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-3. Memory interface signals-detailed signal descriptions (continued) Signal MECC[0:7] MA[15:0] MBA[2:0] I/O Description I/O Error checking and correcting codes. Input and output signals for the DDR controller's bidirectional ECC bus. MECC[0:5] function in both normal and debug modes. O As normal mode outputs, the ECC signals represent the state of ECC driven by the DDR controller on writes. As debug mode outputs MECC[0:5] provide source ID and data-valid information. See Error checking and correcting (ECC) and Debug information on debug pins for more details. State Asserted/Negated-Represents the state of ECC being driven by the DDR controller on Meaning writes. Timing Assertion/Negation-Same timing as MDQ High impedance-Same timing as MDQ I As inputs, the ECC signals represent the state of ECC driven by the SDRAM devices on reads. State Asserted/Negated-Represents the state of ECC being driven by the DDR SDRAMs on Meaning reads. Timing Assertion/Negation-Same timing as MDQ High impedance-Same timing as MDQ O Address bus. Memory controller outputs for the address to the DRAM. MA[15:0] carry 16 of the address bits for the DDR memory interface corresponding to the row and column address bits. MA0 is the lsb of the address output from the memory controller. State Asserted/Negated-Represents the address driven by the DDR memory controller. Contains Meaning different portions of the address depending on the memory size and the DRAM command being issued by the memory controller. See Table 8-4 for a complete description of the mapping of these signals. Timing Assertion/Negation-The address lines are only driven when the controller has a command scheduled to issue on the address/CMD bus; otherwise they will be at high-Z. It is valid when a transaction is driven to DRAM (when MCS_B n is active). High impedance-When the memory controller is disabled O Logical bank address. Outputs that drive the logical (or internal) bank address pins of the SDRAM. Each SDRAM supports four or eight addressable logical sub-banks. Bit zero of the memory controller's output bank address must be connected to bit zero of the SDRAM's input bank address. MBA0, the least-significant bit of the three bank address signals, is asserted during the mode register set command to specify the extended mode register. State Asserted/Negated-Selects the DDR SDRAM logical (or internal) bank to be activated Meaning during the row address phase and selects the SDRAM internal bank for the read or write operation during the column address phase of the memory access. Table 8-4 describes the mapping of these signals in all cases. Timing Assertion/Negation-Same timing as MAn High impedance-Same timing as MAn Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 255 External signal descriptions Table 8-3. Memory interface signals-detailed signal descriptions (continued) Signal MCAS_B MRAS_B MCS_B[ 0:1] MWE_B I/O Description O Column address strobe. Active-low SDRAM address multiplexing signal. MCAS_B is asserted for read or write transactions and for mode register set, refresh, and precharge commands. State Asserted-Indicates that a valid SDRAM column address is on the address bus for read and Meaning write transactions. See Table 8-66 for more information on the states required on MCAS_B for various other SDRAM commands. Negated-The column address is not guaranteed to be valid. Timing Assertion/Negation-Assertion and negation timing is directed by the values described in DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0), DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1), DDR SDRAM timing configuration 2 (DDR_TIMING_CFG_2), and DDR SDRAM timing configuration 3 (DDR_TIMING_CFG_3). High impedance-MCAS_B is tri-stated when memory controller is idle. O Row address strobe. Active-low SDRAM address multiplexing signal. Asserted for activate commands. In addition; used for mode register set commands and refresh commands. State Asserted-Indicates that a valid SDRAM row address is on the address bus for read and Meaning write transactions. See Table 8-66 for more information on the states required on MRAS_B for various other SDRAM commands. Negated-The row address is not guaranteed to be valid. Timing Assertion/Negation-Assertion and negation timing is directed by the values described in DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0), DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1), DDR SDRAM timing configuration 2 (DDR_TIMING_CFG_2), and DDR SDRAM timing configuration 3 (DDR_TIMING_CFG_3). High impedance-MRAS_B is tri-stated when memory controller is idle. O Chip selects. Two chip selects supported by the memory controller. State Asserted-Selects a physical SDRAM bank to perform a memory operation as described in Meaning Chip select n memory bounds (DDR_CSn_BNDS), and Chip select n configuration (DDR_CSn_CONFIG). The DDR controller asserts one of the MCS_B[ 0:1] signals to begin a memory cycle. Timing Negated-Indicates no SDRAM action during the current cycle. Assertion/Negation-Asserted to signal any new transaction to the SDRAM. The transaction must adhere to the timing constraints set in TIMING_CFG_0-TIMING_CFG_3. High impedance-Always driven unless the memory controller is disabled. O Write enable. Asserted when a write transaction is issued to the SDRAM. This is also used for mode registers set commands and precharge commands. State Asserted-Indicates a memory write operation. See Table 8-66 for more information on the Meaning states required on MWE_B for various other SDRAM commands. Negated-Indicates a memory read operation. Timing Assertion/Negation-Similar timing as MRAS_B and MCAS_B. Used for write commands. High impedance-MWE_B is tri-stated when memory controller is idle. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 256 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-3. Memory interface signals-detailed signal descriptions (continued) Signal I/O Description MDM[0:3] +MDM[8] O DDR SDRAM data output mask. Masks unwanted bytes of data transferred during a write. They are needed to support sub-burst-size transactions (such as single-byte writes) on SDRAM where all I/O occurs in multi-byte bursts. MDM[0] corresponds to the most significant byte (MSB) and MDM[3] corresponds to the LSB, while MDM[8] corresponds to the ECC byte. Table 8-58 shows byte lane encodings. State Asserted-Prevents writing to DDR SDRAM. Asserted when data is written to DRAM if the Meaning corresponding byte(s) should be masked for the write. Note that the MDMn signals are active-high for the DDR controller. MDMn is part of the DDR command encoding. Negated-Allows the corresponding byte to be read from or written to the SDRAM. Timing Assertion/Negation-Same timing as MDQx as outputs. High-impedance-Always driven unless the memory controller is disabled. MODT[ 0:1] O On-Die termination. Memory controller outputs for the ODT to the DRAM. MODT[ 0:1] represents the on-die termination for the associated data, data masks, ECC, and data strobes. State Asserted/Negated-Represents the ODT driven by the DDR memory controller. Meaning Timing Assertion/Negation-Driven in accordance with JEDEC DRAM specifications for on-die termination timings. It is configured through the CSn_CONFIG[ODT_RD_CFG] and CSn_CONFIG[ODT_WR_CFG] fields. High impedance-Always driven. MDIC[0:1] I/O Driver impedance calibration. Note that the MDIC signals require the use of resistors; MDIC0 must be pulled to GND, while MDIC1 must be pulled to GVDD. See DDR Control Driver Register 1 (DDR_DDRCDR_1) . State These pins are used for automatic calibration of the DDR IOs. Meaning Timing These are driven for four DRAM cycles at a time while the DDR controller is executing the automatic driver compensation. MAPAR_ERR_B I Address parity error. Reflects whether an address parity error has been detected by the DRAM. This signal is active low. State Asserted-An error has been detected. Meaning Negated-An error has not been detected. Timing Assertion/Negation-are driven by the registered DIMMs one DRAM cycle after the parity bit has been driven by the memory controller. This error signal should be held valid for two DRAM cycles. MAPAR_OUT_B O Address parity out. Driven by the memory controller as the parity bit calculated across the address and command bits. Even parity is used, and parity is not calculated for the MCKE[ 0:1], MODT[ 0:1], or MCS_B[ 0:1] signals. State Asserted-The parity bit is high. Meaning Negated-The parity bit is low. Timing Assertion/Negation-are issued one DRAM cycle after the chip select for each command. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 257 DDR memory map/register definition 8.3.2.2 Clock interface signals The table below contains the detailed descriptions of the clock signals of the DDR controller. Table 8-4. Clock signals-detailed signal descriptions Signal MCK [0:3] , MCK_B [0:3] MCKE[ 0:1] I/O Description O DRAM clock outputs and their complements. State Asserted/Negated-The JEDEC DDR SDRAM specifications require true and complement Meaning clocks. A clock edge is seen by the SDRAM when the true and complement cross. Timing Assertion/Negation-Timing is controlled by the DDR_CLK_CNTL register at offset 0x130. O Clock enable. Output signals used as the clock enables to the SDRAM. MCKE[ 0:1] can be negated to stop clocking the DDR SDRAM. The MCKE signals should be connected to the same rank of memory as the corresponding MCS_B and MODT signals. For example, MCKE[0] should be connected to the same rank of memory as MCS_B[0] and MODT[0]. State Asserted-Clocking to the SDRAM is enabled. Meaning Negated-Clocking to the SDRAM is disabled and the SDRAM should ignore signal transitions on MCK or MCK_B. MCK/MCK_B are don't cares while MCKE[ 0:1] are negated. Timing Assertion/Negation-Asserted when DDR_SDRAM_CFG[MEM_EN] is set. Can be negated when entering dynamic power management or self refresh. Are asserted again when exiting dynamic power management or self refresh. High impedance-Always driven. 8.4 DDR memory map/register definition The following table shows the register memory map for the DDR memory controller . Offset address (hex) 2000 2008 2080 2084 20C0 20C4 2100 2104 2108 DDR memory map Register name Width (in bits) Access Reset value Chip select n memory bounds (DDR_CS0_BNDS) 32 Chip select n memory bounds (DDR_CS1_BNDS) 32 Chip select n configuration (DDR_CS0_CONFIG) 32 Chip select n configuration (DDR_CS1_CONFIG) 32 Chip select n configuration 2 (DDR_CS0_CONFIG_2) 32 Chip select n configuration 2 (DDR_CS1_CONFIG_2) 32 DDR SDRAM timing configuration 3 (DDR_TIMING_CFG_3) 32 DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) 32 DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1) 32 Table continues on the next page... R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0000_0000h R/W 0011_0105h R/W 0000_0000h Section/ page 8.4.1/260 8.4.1/260 8.4.2/261 8.4.2/261 8.4.3/263 8.4.3/263 8.4.4/264 8.4.5/266 8.4.6/269 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 258 Freescale Semiconductor, Inc. Offset address (hex) 210C 2110 2114 2118 211C 2120 2124 2128 2130 2148 214C 2160 2164 2170 2174 217C 2180 2184 2190 2194 2B20 2B24 2B28 2B2C 2BF8 2BFC 2E00 2E04 2E08 Chapter 8 DDR Memory Controllers DDR memory map (continued) Register name Width (in bits) Access Reset value Section/ page DDR SDRAM timing configuration 2 (DDR_TIMING_CFG_2) 32 DDR SDRAM control configuration (DDR_DDR_SDRAM_CFG) 32 DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2) 32 DDR SDRAM mode configuration (DDR_DDR_SDRAM_MODE) 32 DDR SDRAM mode configuration 2 (DDR_DDR_SDRAM_MODE_2) 32 DDR SDRAM mode control (DDR_DDR_SDRAM_MD_CNTL) 32 DDR SDRAM interval configuration (DDR_DDR_SDRAM_INTERVAL) 32 DDR SDRAM data initialization (DDR_DDR_DATA_INIT) 32 DDR SDRAM clock control (DDR_DDR_SDRAM_CLK_CNTL) 32 DDR training initialization address (DDR_DDR_INIT_ADDR) 32 DDR training initialization extended address (DDR_DDR_INIT_EXT_ADDR) 32 DDR SDRAM timing configuration 4 (DDR_TIMING_CFG_4) 32 DDR SDRAM timing configuration 5 (DDR_TIMING_CFG_5) 32 DDR ZQ calibration control (DDR_DDR_ZQ_CNTL) 32 DDR write leveling control (DDR_DDR_WRLVL_CNTL) 32 DDR Self Refresh Counter (DDR_DDR_SR_CNTR) 32 DDR Register Control Words 1 (DDR_DDR_SDRAM_RCW_1) 32 DDR Register Control Words 2 (DDR_DDR_SDRAM_RCW_2) 32 DDR write leveling control 2 (DDR_DDR_WRLVL_CNTL_2) 32 DDR write leveling control 3 (DDR_DDR_WRLVL_CNTL_3) 32 DDR Debug Status Register 1 (DDR_DDRDSR_1) 32 DDR Debug Status Register 2 (DDR_DDRDSR_2) 32 DDR Control Driver Register 1 (DDR_DDRCDR_1) 32 DDR Control Driver Register 2 (DDR_DDRCDR_2) 32 DDR IP block revision 1 (DDR_DDR_IP_REV1) 32 DDR IP block revision 2 (DDR_DDR_IP_REV2) 32 Memory data path error injection mask high (DDR_DATA_ERR_INJECT_HI) 32 Memory data path error injection mask low (DDR_DATA_ERR_INJECT_LO) 32 Memory data path error injection mask ECC (DDR_ERR_INJECT) 32 Table continues on the next page... R/W 0000_0000h 8.4.7/273 R/W 0300_0000h 8.4.8/277 R/W 0000_0000h 8.4.9/280 R/W 0000_0000h 8.4.10/283 R/W 0000_0000h 8.4.11/284 R/W 0000_0000h 8.4.12/284 R/W 0000_0000h 8.4.13/288 R/W 0000_0000h 8.4.14/288 R/W 0200_0000h 8.4.15/289 R/W 0000_0000h 8.4.16/290 R/W 0000_0000h 8.4.17/291 R/W 0000_0000h 8.4.18/292 R/W 0000_0000h 8.4.19/295 R/W 0000_0000h 8.4.20/297 R/W 0000_0000h 8.4.21/299 R/W 0000_0000h 8.4.22/302 R/W 0000_0000h 8.4.23/303 R/W 0000_0000h 8.4.24/304 R/W 0000_0000h 8.4.25/305 R/W 0000_0000h 8.4.26/307 R 0000_0000h 8.4.27/310 R 0000_0000h 8.4.28/311 R/W 0000_0000h 8.4.29/311 R/W 0000_0000h 8.4.30/315 R See section 8.4.31/316 R 0000_0300h 8.4.32/316 R/W 0000_0000h 8.4.33/317 R/W 0000_0000h 8.4.34/317 R/W 0000_0000h 8.4.35/318 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 259 DDR memory map/register definition DDR memory map (continued) Offset address (hex) 2E20 2E24 2E28 2E40 2E44 2E48 2E4C 2E50 2E54 2E58 Register name Memory data path read capture high (DDR_CAPTURE_DATA_HI) Memory data path read capture low (DDR_CAPTURE_DATA_LO) Memory data path read capture ECC (DDR_CAPTURE_ECC) Memory error detect (DDR_ERR_DETECT) Memory error disable (DDR_ERR_DISABLE) Memory error interrupt enable (DDR_ERR_INT_EN) Memory error attributes capture (DDR_CAPTURE_ATTRIBUTES) Memory error address capture (DDR_CAPTURE_ADDRESS) Memory error extended address capture (DDR_CAPTURE_EXT_ADDRESS) Single-Bit ECC memory error management (DDR_ERR_SBE) Width (in bits) Access Reset value Section/ page 32 R/W 0000_0000h 8.4.36/319 32 R/W 0000_0000h 8.4.37/319 32 R/W 0000_0000h 8.4.38/320 32 w1c 0000_0000h 8.4.39/321 32 R/W 0000_0000h 8.4.40/323 32 R/W 0000_0000h 8.4.41/325 32 R/W 0000_0000h 8.4.42/327 32 R/W 0000_0000h 8.4.43/329 32 R/W 0000_0000h 8.4.44/329 32 R/W 0000_0000h 8.4.45/330 8.4.1 Chip select n memory bounds (DDR_CSn_BNDS) The chip select bounds registers (CS n _BNDS) define the starting and ending address of the memory space that corresponds to the individual chip selects. Note that the size specified in CS n _BNDS should equal the size of physical DRAM. Also, note that EA n must be greater than or equal to SA n . If chip select interleaving is enabled, all fields in the lower interleaved chip select are used, and the other chip selects' bounds registers are unused. For example, if chip selects 0 and 1 are interleaved, all fields in CS0_BNDS are used, and all fields in CS1_BNDS are unused. Address: 2000h base + 0h offset + (8d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved SAn Reserved EAn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_CSn_BNDS field descriptions Field 0–3 - This field is reserved. Reserved Description Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 260 Freescale Semiconductor, Inc. Field 4–15 SAn 16–19 - 20–31 EAn Chapter 8 DDR Memory Controllers DDR_CSn_BNDS field descriptions (continued) Description Starting address for chip select (bank) n . This value is compared against the 12 msbs of the 36-bit address. This field is reserved. Reserved Ending address for chip select (bank) n. This value is compared against the 12 msbs of the 36-bit address. 8.4.2 Chip select n configuration (DDR_CSn_CONFIG) The chip select configuration (CS n _CONFIG) registers enable the DDR chip selects and set the number of row and column bits used for each chip select. These registers should be loaded with the correct number of row and column bits for each SDRAM. Because CS n _CONFIG[ROW_BITS_CS_ n , COL_BITS_CS_ n ] establish address multiplexing, the user should take great care to set these values correctly. If chip select interleaving is enabled, then all fields in the lower interleaved chip select are used, and the other registers' fields are unused, with the exception of the ODT_RD_CFG and ODT_WR_CFG fields. For example, if chip selects 0 and 1 are interleaved, all fields in CS0_CONFIG are used, but only the ODT_RD_CFG and ODT_WR_CFG fields in CS1_CONFIG are used. Address: 2000h base + 80h offset + (4d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CS_n_EN R Reserved W AP_n_EN Reserved ODT_RD_CFG ODT_WR_CFG BA_BITS_CS_n Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved ROW_BITS_CS_n Reserved COL_BITS_CS_n W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 261 DDR memory map/register definition DDR_CSn_CONFIG field descriptions Field 0 CS_n_EN 1–7 8 AP_n_EN 9–11 ODT_RD_CFG Chip select n enable Description 0 Chip select n is not active 1 Chip select n is active and assumes the state set in CSn_BNDS. This field is reserved. Reserved Chip select n auto-precharge enable 0 Chip select n is only auto-precharged if global auto-precharge mode is enabled (DDR_SDRAM_INTERVAL[BSTOPRE] = 0). 1 Chip select n always issues an auto-precharge for read and write transactions. ODT for reads configuration. Note that CAS latency plus additive latency must be at least 3 cycles for ODT_RD_CFG to be enabled. ODT should only be used with DDR2or DDR3 memories. 000 001 010 011 100 101-111 Never assert ODT for reads Assert ODT only during reads to CSn Assert ODT only during reads to other chip selects Reserved Assert ODT for all reads Reserved 12 This field is reserved. - Reserved 13–15 ODT for writes configuration. Note that write latency plus additive latency must be at least 3 cycles for ODT_WR_CFG ODT _WR_CFG to be enabled. ODT should only be used with DDR2or DDR3 memories. 000 001 010 011 100 101-111 Never assert ODT for writes Assert ODT only during writes to CS n Assert ODT only during writes to other chip selects Reserved Assert ODT for all writes Reserved 16–17 Number of bank bits for SDRAM on chip select n . These bits correspond to the sub-bank bits driven on BA_BITS_CS_n MBA n in DDR SDRAM address multiplexing . 00 01 10-11 2 logical bank bits 3 logical bank bits Reserved 18–20 - This field is reserved. Reserved 21–23 Number of row bits for SDRAM on chip select n . See DDR SDRAM address multiplexing for details. ROW_BITS_CS_ n 000 12 row bits 001 13 row bits 010 14 row bits 011 15 row bits 100 16 row bits 101-111 Reserved 24–28 - This field is reserved. Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 262 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers DDR_CSn_CONFIG field descriptions (continued) Field Description 29–31 Number of column bits for SDRAM on chip select n. For DDR, the decoding is as follows: COL_BITS_CS_n 000 8 column bits 001 9 column bits 010 10 column bits 011 11 column bits 100-111 Reserved 8.4.3 Chip select n configuration 2 (DDR_CSn_CONFIG_2) The chip select configuration (CSn_CONFIG_2) registers enable the partial array self refresh address decode in each chip select. If chip select interleaving is enabled, then all fields in the lower interleaved chip select are used, and the other registers' fields are unused. Address: 2000h base + C0h offset + (4d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved PASR_ CFG Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_CSn_CONFIG_2 field descriptions Field 0–4 - 5–7 PASR_CFG Description This field is reserved. Reserved Partial array self refresh config. Controls the bits that are placed on MA[2:0] during the write to the EMRS(2) register when the automatic hardware DRAM initialization is used (DDR_SDRAM_CFG[BI] is cleared when DDR_SDRAM_CFG[MEM_EN] is set). If this field is a non-zero value, then it overrides the least significant 3 bits in DDR_SDRAM_MODE_2[ESDMODE2] during the automatic initialization for chip select n . In addition, if a non-zero value is programmed in this field, then the address decode for chip select n is optimized for partial array self refresh, as shown in DDR SDRAM address multiplexing 8–31 - 000 001-111 Partial array self refresh is disabled Partial array self refresh is enabled per JEDEC specifications. Overriding the least significant 3 bits of EMRS or EMRS(2) is only supported for DDR2and DDR3 memory types. This field is reserved. Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 263 DDR memory map/register definition 8.4.4 DDR SDRAM timing configuration 3 (DDR_TIMING_CFG_3) DDR SDRAM timing configuration register 3 sets the extended refresh recovery time, which is combined with TIMING_CFG_1[REFREC] to determine the full refresh recovery time. EXT_CASLAT EXT_ ACTTOPRE Address: 2000h base + 100h offset = 2100h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reserved EXT_REFREC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W Reserved CNTL_ADJ Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_TIMING_CFG_3 field descriptions Field 0–6 - 7 EXT_ ACTTOPRE Description This field is reserved. Reserved Extended Activate to precharge interval (t RAS ). Determines the number of clock cycles from an activate command until a precharge command is allowed. This field is concatenated with TIMING_CFG_1[ACTTOPRE] to obtain a 5-bit value for the total activate to precharge. Note that a 5-bit value of 0_0000 is the same as a 5-bit value of 1_0000. Both values represent 16 cycles. 8–11 - 12–15 EXT_REFREC 0 0 clocks 1 16 clocks This field is reserved. Reserved Extended refresh recovery time (t RFC ). Controls the number of clock cycles from a refresh command until an activate command is allowed. This field is concatenated with TIMING_CFG_1[REFREC] to obtain an 8bit value for the total refresh recovery. Note that hardware adds an additional 8 clock cycles to the final, 8bit value of the refresh recovery. t RFC = {EXT_REFREC || REFREC} + 8, such that t RFC is calculated as follows: 0000 0001 0010 0011 0 clocks 16 clocks 32 clocks 48 clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 264 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers DDR_TIMING_CFG_3 field descriptions (continued) Field 16–18 19 EXT_CASLAT Description 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 64 clocks 80 clocks 96 clocks 112 clocks 128 clocks 144 clocks 160 clocks 176 clocks 192 clocks 208 clocks 224 clocks 240 clocks This field is reserved. Reserved Extended MCAS latency from READ command. Number of clock cycles between registration of a READ command by the SDRAM and the availability of the first output data. If a READ command is registered at clock edge n and the latency is m clocks, data is available nominally coincident with clock edge n + m . This field is concatenated with TIMING_CFG_1[CASLAT] to obtain a 5-bit value for the total CAS latency. Note that if this bit is set, then 8 clocks are added to the programmed value in TIMING_CFG_1[CASLAT]. 20–28 - 29–31 CNTL_ADJ 0 0 clocks 1 8 clocks This field is reserved. Reserved Control Adjust. Controls the amount of delay to add to the lightly loaded control signals with respect to all other DRAM address and command signals. The signals affected by this field are MODT[ 0:1 ], MCS0:1 ], and MCKE[ 0:1 ] 000 001 010 011 100 101 110-111 MODT[ 0:1 ], MCS [ 0:1 ], and MCKE[ 0:1 ] are launched aligned with the other DRAM address and control signals. MODT[ 0:1 ], MCS [ 0:1 ], and MCKE[ 0:1 ] are launched 1/4 DRAM cycle later than the other DRAM address and control signals. MODT[ 0:1 ], MCS [ 0:1 ], and MCKE[ 0:1 ] are launched 1/2 DRAM cycle later than the other DRAM address and control signals. MODT[ 0:1 ], MCS [ 0:1 ], and MCKE[ 0:1 ] are launched 3/4 DRAM cycles later than the other DRAM address and control signals. MODT[ 0:1 ], MCS [ 0:1 ], and MCKE[ 0:1 ] are launched 1 DRAM cycles later than the other DRAM address and control signals. MODT[ 0:1 ], MCS [ 0:1 ], and MCKE[ 0:1 ] are launched 5/4 DRAM cycles later than the other DRAM address and control signals. Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 265 DDR memory map/register definition 8.4.5 DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) DDR SDRAM timing configuration register 0 sets the number of clock cycles between various SDRAM control commands. Address: 2000h base + 104h offset = 2104h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R RWT W WRT RRT WWT Reserved ACT_PD_EXIT PRE_PD_EXIT Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W ODT_PD_EXIT Reserved MRS_CYC Reset 0 Field 0–1 RWT 2–3 WRT 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 DDR_TIMING_CFG_0 field descriptions Description Read-to-write turnaround (tRTW ). Specifies how many extra cycles are added between a read to write turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the CAS latency and write latency. Choosing a value other than 0 adds extra cycles past this default calculation. As a default the DDR controller determines the read-to-write turnaround as CL - WL + BL ÷ 2 + 2. In this equation, CL is the CAS latency rounded up to the next integer, WL is the programmed write latency, and BL is the burst length. 00 0 clocks 01 1 clock 10 2 clocks 11 3 clocks Write-to-read turnaround. Specifies how many extra cycles are added between a write to read turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the, read latency, and write latency. Choosing a value other than 0 adds extra cycles past this default calculation. As a default, the DDR controller determines the write-to-read turnaround as WL - CL + BL ÷ 2 + 1. In this equation, CL is Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 266 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers DDR_TIMING_CFG_0 field descriptions (continued) Field Description the CAS latency rounded down to the next integer, WL is the programmed write latency, and BL is the burst length. 4–5 RRT 00 0 clocks 01 1 clock 10 2 clocks 11 3 clocks Read-to-read turnaround. Specifies how many extra cycles are added between reads to different chip selects. As a default, 3 cycles are required between read commands to different chip selects. Extra cycles may be added with this field. NOTE: If 8-beat bursts are enabled, then 5 cycles are the default.Note that DDR2 does not support 8beat bursts. 6–7 WWT 00 0 clocks 01 1 clock 10 2 clocks 11 3 clocks Write-to-write turnaround. Specifies how many extra cycles are added between writes to different chip selects. As a default, 2 cycles are required between write commands to different chip selects. Extra cycles may be added with this field. NOTE: If 8-beat bursts are enabled, then 4 cycles are the default. Note that DDR2 does not support 8beat bursts. 8 - 9–11 ACT_PD_EXIT 00 0 clocks 01 1 clock 10 2 clocks 11 3 clocks This field is reserved. Reserved Active powerdown exit timing ( DDR2: t XARD and t XARDS and DDR3 : t XP ). Specifies how many clock cycles to wait after exiting active powerdown before issuing any command. 12–15 PRE_PD_EXIT 000 Reserved 001 2 clocks 010 3 clocks 011 4 clocks 100 5 clocks 101 6 clocks 110 7 clocks 111 8 clocks Precharge powerdown exit timing (t XP ). Specifies how many clock cycles to wait after exiting precharge powerdown before issuing any command. 0000 0001 0010 0011 0100 Reserved 2 clocks 3 clocks 4 clocks 5 clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 267 DDR memory map/register definition DDR_TIMING_CFG_0 field descriptions (continued) Field Description 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks 16 clocks 16–19 - This field is reserved. Reserved 20–23 ODT powerdown exit timing ( DDR2: t AXPD , DDR3 : set to 1). Specifies how many clocks must pass after ODT_PD_EXIT exiting powerdown before ODT may be asserted. ODT_PD_EXIT must be greater than TIMING_CFG_5[RODT_ON] when using RODT_ON overrides and must be greater than TIMING_CFG_5[WODT_ON] when using WODT_ON overrides. 24–27 - 28–31 MRS_CYC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 clock 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks This field is reserved. Reserved Mode register set cycle time (t MRD ). Specifies the number of cycles that must pass after a Mode Register Set command until any other command. 0000 0001 0010 0011 0100 0101 0110 0111 Reserved 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 268 Freescale Semiconductor, Inc. Field Chapter 8 DDR Memory Controllers DDR_TIMING_CFG_0 field descriptions (continued) 1000 1001 1010 1011 1100 1101 1110 1111 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks Description 8.4.6 DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1) DDR SDRAM timing configuration register 1 sets the number of clock cycles between various SDRAM control commands. Address: 2000h base + 108h offset = 2108h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PRETOACT W ACTTOPRE ACTTORW CASLAT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R REFREC W WRREC Reserved Reserved ACTTOACT WRTORD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_TIMING_CFG_1 field descriptions Field 0–3 PRETOACT Description Precharge-to-activate interval (t RP ). Determines the number of clock cycles from a precharge command until an activate or refresh command is allowed. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 269 DDR memory map/register definition DDR_TIMING_CFG_1 field descriptions (continued) Field 4–7 ACTTOPRE Description 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks Activate to precharge interval (t RAS ). Determines the number of clock cycles from an activate command until a precharge command is allowed. This field is concatenated with TIMING_CFG_3[EXT_ACTTOPRE] to obtain a 5-bit value for the total activate to precharge time. Note that the decode of 0000-0011 is equal to 16-19 clocks when TIMING_CFG_3[EXT_ACTTOPRE] = 0, but it is equal to 0-3 clocks when TIMING_CFG_3[EXT_ACTTOPRE] = 1. 8–11 ACTTORW 0000 0001 0010 0011 0100 0101 0110 0111 16 clocks 17 clocks 18 clocks 19 clocks 4 clocks 5 clocks 6 clocks 7 clocks ... 1111 15 clocks Activate to read/write interval for SDRAM (t RCD ). Controls the number of clock cycles from an activate command until a read or write command is allowed. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Reserved 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 270 Freescale Semiconductor, Inc. Field 12–15 CASLAT 16–19 REFREC 20–23 WRREC Chapter 8 DDR Memory Controllers DDR_TIMING_CFG_1 field descriptions (continued) Description 1101 1110 1111 13 clocks 14 clocks 15 clocks MCAS latency from READ command. Number of clock cycles between registration of a READ command by the SDRAM and the availability of the first output data. If a READ command is registered at clock edge n and the latency is m clocks, data is available nominally coincident with clock edge n + m . This field is concatenated with TIMING_CFG_3[EXT_CASLAT] to obtain a 5-bit value for the total CAS latency. This value must be programmed at initialization as described in DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2) . 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved 1 clock 1.5 clocks 2 clocks 2.5 clocks 3 clocks 3.5 clocks 4 clocks 4.5 clocks 5 clocks 5.5 clocks 6 clocks 6.5 clocks 7 clocks 7.5 clocks 8 clocks Refresh recovery time (t RFC ). Controls the number of clock cycles from a refresh command until an activate command is allowed. This field is concatenated with TIMING_CFG_3[EXTREFREC] to obtain a 7bit value for the total refresh recovery. Note that hardware adds an additional 8 clock cycles to the final, 7bit value of the refresh recovery, such that t RFC is calculated as follows: t RFC = {EXT_REFREC || REFREC} + 8. 0000 0001 0010 0011 8 clocks 9 clocks 10 clocks 11 clocks ... 1111 23 clocks Last data to precharge minimum interval (t WR ). Determines the number of clock cycles from the last data associated with a write command until a precharge command is allowed. 0000 0001 0010 0011 0100 0101 0110 0111 Reserved 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 271 DDR memory map/register definition DDR_TIMING_CFG_1 field descriptions (continued) Field 24 25–27 ACTTOACT Description 1000 1001 1010 1011 1100 1101 1110 1111 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks This field is reserved. Reserved Activate-to-activate interval (t RRD ). Number of clock cycles from an activate command until another activate command is allowed for a different logical bank in the same physical bank (chip select). 28 - 29–31 WRTORD 000 Reserved 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks This field is reserved. Reserved Last write data pair to read command issue interval (t WTR ). Number of clock cycles between the last write data pair and the subsequent read command to the same physical bank. 000 Reserved 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 272 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.7 DDR SDRAM timing configuration 2 (DDR_TIMING_CFG_2) DDR SDRAM timing configuration 2 sets the clock delay to data for writes. Address: 2000h base + 10Ch offset = 210Ch Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R ADD_LAT W CPO WR_LAT Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RD_TO_PRE WR_DATA_DELAY W Reserved CKE_PLS FOUR_ACT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 273 DDR memory map/register definition DDR_TIMING_CFG_2 field descriptions Field 0–3 ADD_LAT Description Additive latency. The additive latency must be set to a value less than TIMING_CFG_1[ACTTORW]. (DDR2-specific) 4–8 CPO 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 clocks 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks MCAS -to-preamble override. Defines the number of DRAM cycles between when a read is issued and when the corresponding DQS preamble is valid for the memory controller. For these decodings, "READ_LAT" is equal to the CAS latency plus the additive latency. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 READ_LAT + 1 Reserved READ_LAT READ_LAT + 1/4 READ_LAT + 1/2 READ_LAT + 3/4 READ_LAT + 1 READ_LAT + 5/4 READ_LAT + 3/2 READ_LAT + 7/4 READ_LAT + 2 READ_LAT + 9/4 READ_LAT + 5/2 READ_LAT + 11/4 READ_LAT + 3 READ_LAT + 13/4 READ_LAT + 7/2 READ_LAT + 15/4 READ_LAT + 4 READ_LAT + 17/4 READ_LAT + 9/2 READ_LAT + 19/4 READ_LAT + 5 READ_LAT + 21/4 READ_LAT + 11/2 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 274 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers DDR_TIMING_CFG_2 field descriptions (continued) Field 9–12 WR_LAT Description 11001 11010 11011 11100 11101 11110 11111 READ_LAT + 23/4 READ_LAT + 6 READ_LAT + 25/4 READ_LAT +13/2 READ_LAT + 27/4 READ_LAT + 7 Automatic Calibration (recommended) Write latency. Note that the total write latency for DDR2/ DDR3 is equal to WR_LAT + ADD_LAT. If a write latency of 1 is desired, then the additive latency must also be set to at least 1 cycle. 13–15 - 16–18 RD_TO_PRE 19–21 WR_DATA_ DELAY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks This field is reserved. Reserved Read to precharge (t RTP ). For DDR2, with a non-zero ADD_LAT value, takes a minimum of ADD_LAT + t RTP cycles between read and precharge. 000 Reserved 001 1 cycle 010 2 cycles 011 3 cycles 100 4 cycles 101 5 cycles 110 6 cycles 111 7 cycles Write command to write data strobe timing adjustment. Controls the amount o delay applied to the data and data strobes for writes. See DDR SDRAM write timing adjustments , for details. The write preamble typically is driven high for 1/2 DRAM cycle, and then it is driven low for 1/2 DRAM cycle. However, for WR_DATA_DELAY settings of 0 clocks and 1/4 clocks, the write preamble is driven low for the entire DRAM cycle. If the preamble needs to switch high first (to meet DDR3 specifications), then these values should not be used. 000 0 clock delay 001 1/4 clock delay Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 275 DDR memory map/register definition DDR_TIMING_CFG_2 field descriptions (continued) Field 22 23–25 CKE_PLS 26–31 FOUR_ACT 010 1/2 clock delay 011 3/4 clock delay 100 1 clock delay 101 5/4 clock delay 110 3/2 clock delay 111 Reserved This field is reserved. Reserved Minimum CKE pulse width (t CKE ). Description 000 Reserved 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks Window for four activates (t FAW ). This is applied to DDR2/ DDR3 with eight logical banks only. 000000 000001 000010 000011 000100 011110 011111 100000 100001-111111 Reserved 1 cycle 2 cycles 3 cycles 4 cycles ... 30 cycles 31 cycles 32 cycles Reserved 1. For CPO decodings other than 00000 and 11111, READ_LAT is rounded up to the next integer value. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 276 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.8 DDR SDRAM control configuration (DDR_DDR_SDRAM_CFG) The DDR SDRAM control configuration register enables the interface logic and specifies certain operating features such as self refreshing, error checking and correcting, registered DIMMs, and dynamic power management. Address: 2000h base + 110h offset = 2110h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MEM_EN ECC_EN RD_EN Reserved R SREN W DYN_PWR Reserved SDRAM_TYPE Reserved DBW 8_BE 3T_ EN Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 2T_ EN W BA_INTLV_CTL x32_EN PCHB8 Reserved MEM_HALT Reserved HSE BI Reset 0 Field 0 MEM_EN 1 SREN 2 ECC_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_SDRAM_CFG field descriptions DDR SDRAM interface logic enable. Description 0 SDRAM interface logic is disabled. 1 SDRAM interface logic is enabled. Must not be set until all other memory configuration parameters have been appropriately configured by initialization code. Self refresh enable (during sleep). 0 SDRAM self refresh is disabled during sleep. Whenever self-refresh is disabled, the system is responsible for preserving the integrity of SDRAM during sleep. 1 SDRAM self refresh is enabled during sleep. ECC enable. Note that non-correctable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt unless it is disabled (by clearing HID1[RFXE]). If Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 277 DDR memory map/register definition DDR_DDR_SDRAM_CFG field descriptions (continued) Field Description RFXE is zero and this error occurs, ERR_DISABLE[MBED] must be zero, and ERR_INT_EN[MBEE] and ECC_EN must be one to ensure an interrupt is generated. 3 RD_EN 0 No ECC errors are reported. No ECC interrupts are generated. 1 ECC is enabled. Registered DIMM enable. Specifies the type of DIMM used in the system. NOTE: RD_EN and 2T_EN must not both be set at the same time. 4 - 5–7 SDRAM_TYPE 0 Indicates unbuffered DIMMs. 1 Indicates registered DIMMs. This field is reserved. Reserved Type of SDRAM device to be used. This field is used when issuing the automatic hardware initialization sequence to DRAM through Mode Register Set and Extended Mode Register Set commands. Patterns not shown are reserved. 8–9 10 DYN_PWR 11–12 DBW 13 8_BE 011 DDR2 SDRAM 111 DDR3 SDRAM This field is reserved. Reserved Dynamic power management mode 0 Dynamic power management mode is disabled. 1 Dynamic power management mode is enabled. If there is no ongoing memory activity, the SDRAM CKE signal is negated. DRAM data bus width. 00 Reserved 01 32-bit bus is used 10 16-bit bus is used 11 Reserved 8-beat burst enable. NOTE: DDR2 must use 4-beat bursts when using 32-bit bus mode NOTE: DDR3 must use 8-beat bursts when using 32-bit bus mode 14 - 15 3T_EN 0 4-beat bursts are used on the DRAM interface. 1 8-beat bursts are used on the DRAM interface. This field is reserved. Reserved Enable 3T timing. This field cannot be set if DDR_SDRAM_CFG[2T_EN] is also set. This field cannot be used with a 32-bit bus if 4-beat bursts are used. 16 2T_EN 0 1T timing is enabled if 2T_EN is cleared. The DRAM command/address are held for only 1 cycle on the DRAM bus. 1 3T timing is enabled. The DRAM command/address are held for 3 full cycles on the DRAM bus for every DRAM transaction. However, the chip select is only held for the third cycle. Enable 2T timing. This field should not be set if DDR_SDRAM_CFG[3T_EN] is set. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 278 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers DDR_DDR_SDRAM_CFG field descriptions (continued) Field Description NOTE: RD_EN and 2T_EN must not both be set at the same time. 0 1T timing is enabled if 3T_EN is cleared. The DRAM command/address is held for only 1 cycle on the DRAM bus. 1 2T timing is enabled. The DRAM command/address are held for 2 full cycles on the DRAM bus for every DRAM transaction. However, the chip select is only held for the second cycle. 17–23 Bank (chip select) interleaving control. Set this field only if you wish to use bank interleaving. BA_INTLV_CTL ( All unlisted field values are reserved.) 24–25 26 x32_EN 27 PCHB8 0000000 No external memory banks are interleaved 1000000 External memory banks 0 and 1 are interleaved This field is reserved. Reserved x32 enable. 0 Either x8 or x16 discrete DRAM chips are used. In this mode, each data byte has a dedicated corresponding data strobe. 1 x32 discrete DRAM chips are used. In this mode, DQS0 is used to capture DQ[0:31], DQS4 is used to capture DQ[32:63] and DQS8 is used to capture ECC[0:7]. Precharge bit 8 enable. 0 MA[10] is used to indicate the auto-precharge and precharge all commands. 1 MA[8] is used to indicate the auto-precharge and precharge all commands. If x32_EN is cleared, then PCHB8 should be cleared as well . 28 HSE Global half-strength override. Sets I/O driver impedance to half strength. This impedance is used by the MDIC, address/command, data, and clock impedance values, but only if automatic hardware calibration is disabled and the corresponding group's software override is disabled in the DDR control driver register(s) described in DDR Control Driver Register 1 (DDR_DDRCDR_1) . This bit should be cleared if using automatic hardware calibration. 29 - 30 MEM_HALT 0 I/O driver impedance is configured to full strength. 1 I/O driver impedance is configured to half strength. This field is reserved. Reserved DDR memory controller halt. When this bit is set, the memory controller does not accept any new data read/write transactions to DDR SDRAM until the bit is cleared again. This can be used when bypassing initialization and forcing MODE REGISTER SET commands through software. 0 DDR controller accepts new transactions. 1 DDR controller finishes any remaining transactions, and then it remains halted until this bit is cleared by software. 31 Bypass initialization BI 0 DDR controller cycles through initialization routine based on SDRAM_TYPE 1 Initialization routine is bypassed. Software is responsible for initializing memory through DDR_SDRAM_MODE2 register. If software is initializing memory, then the MEM_HALT bit can be set to prevent the DDR controller from issuing transactions during the initialization sequence. Note that the DDR controller does not issue a DLL reset to the DRAMs when bypassing the initialization routine, regardless of the value of DDR_SDRAM_CFG[DLL_RST_DIS]. If a DLL reset is required, then the controller should be forced to enter and exit self-refresh after the controller is enabled. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 279 DDR memory map/register definition DDR_DDR_SDRAM_CFG field descriptions (continued) Field Description See DDR training initialization address (DDR_DDR_INIT_ADDR) for details on avoiding ECC errors in this mode. FRC_SR SR_IE Reserved Reserved AP_EN D_INIT Reserved RCW_EN Reserved MD_EN 8.4.9 DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2) The DDR SDRAM control configuration register 2 provides more control configuration for the DDR controller. Address: 2000h base + 114h offset = 2114h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DLL_ RST_ DIS DQS_CFG Reserved ODT_CFG Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R NUM_PR W Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_SDRAM_CFG_2 field descriptions Field 0 FRC_SR 1 SR_IE Force self-refresh Description 0 DDR controller operates in normal mode. 1 DDR controller enters self-refresh mode. Self-refresh interrupt enable Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 280 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers DDR_DDR_SDRAM_CFG_2 field descriptions (continued) Field Description The DDR controller can be placed into self refresh mode by forcing the PIC to assert IRQ_OUT . This is considered a 'panic interrupt' by the DDR controller, and it enters self refresh as soon as possible. DDR_SDRAM_CFG[SREN] must also be set if the panic interrupt is used. 2 DLL_RST_DIS 0 DDR controller does not enter self-refresh mode if panic interrupt is asserted. 1 DDR controller enters self-refresh mode if panic interrupt is asserted. DLL reset disable. If self-refresh is to be used with DDR3 , this bit should be set The DDR controller typically issues a DLL reset to the DRAMs when exiting self refresh. However, this function may be disabled by setting this bit during initialization. 3 4–5 DQS_CFG 6–8 - 9–10 ODT_CFG 0 DDR controller issues a DLL reset to the DRAMs when exiting self refresh. 1 DDR controller does not issue a DLL reset to the DRAMs when exiting self refresh. This field is reserved. Reserved DQS configuration 00 Reserved 01 Differential DQS signals are used. 10 Reserved 11 Reserved This field is reserved. Reserved ODT configuration This field defines how ODT is driven to the on-chip IOs. See DDR Control Driver Register 1 (DDR_DDRCDR_1) , which defines the termination value that is used. 11–15 - 16–19 NUM_PR 20–24 - 00 Never assert ODT to internal IOs 01 Assert ODT to internal IOs only during writes to DRAM 10 Assert ODT to internal IOs only during reads to DRAM 11 Always keep ODT asserted to internal IOs This field is reserved. Reserved. Number of posted refreshes This determines how many posted refreshes, if any, can be issued at one time. Note that if posted refreshes are used, then this field, along with DDR_SDRAM_INTERVAL[REFINT], must be programmed such that the maximum t ras specification cannot be violated. 0000 0001 0010 0011 Reserved 1 refresh is issued at a time 2 refreshes is issued at a time 3 refreshes is issued at a time 1000 1001-1111 ... 8 refreshes is issued at a time Reserved This field is reserved. Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 281 DDR memory map/register definition DDR_DDR_SDRAM_CFG_2 field descriptions (continued) Field 25 - 26 AP_EN Description This field is reserved. Reserved Address Parity Enable Determines whether address parity is generated and checked for the address and control signals when using registered DIMMs. If address parity is used, the MAPAR_OUT and MAPAR_ERR pins are used to drive the parity bit and to receive errors from the open-drain parity error signal. Even parity is used, and parity is generated for the MA[15:0], MBA[2:0], MRAS , MCAS , MWE signals. Parity does not generate for the MCKE[ 0:1 ], MODT[ 0:1 ], or MCS [ 0:1 ] signals. Note that address parity should not be used for nonzero values of TIMING_CFG_3[CNTL_ADJ]. 27 D_INIT 0 Address parity is not used 1 Address parity is used DRAM data initialization This bit is set by software, and it is cleared by hardware. If software sets this bit before the memory controller is enabled, the controller automatically initializes DRAM after it is enabled. This bit is automatically cleared by hardware once the initialization is completed. This data initialization bit should only be set when the controller is idle. 28 - 29 RCW_EN 0 There is not data initialization in progress, and no data initialization is scheduled 1 The memory controller initializes memory once it is enabled. This bit remains asserted until the initialization is complete. The value in DDR_DATA_INIT register is used to initialize memory. This field is reserved. Reserved Register Control Word Enable If DDR3 registered DIMMs are used, it may be necessary to write the register control words before issuing commands to DRAM. If this bit is set, the controller will write the register control words after DDR_SDRAM_CFG[MEM_EN] is set, unless DDR_SDRAM_CFG[BI] is set. The register control words are written with the values in DDR_SDRAM_RCW_1 and DDR_SDRAM_RCW_2. 30 - 31 MD_EN 0 Register control words will not be automatically written during DRAM initialization 1 Register control words are automatically written during DRAM initialization. This bit should only be set if DDR3 registered DIMMs are used, and the default settings need to be modified. This field is reserved. Reserved Mirrored DIMM Enable Some DDR3 DIMMs are mirrored, where certain MA and MBA pins are mirrored on one side of the DIMM. When this bit is set, the controller will know to swap these signals before transmitting to the DRAM. The controller will assume that CS1 and CS3 are the 'mirrored' ranks of memory. The following signals are mirrored (MBA[0] vs MBA[1]; MA[3] vs MA[4]; MA[5] vs MA[6]; MA[7] vs MA[8]). 0 Mirrored DIMMs are not used 1 Mirrored DIMMs are used P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 282 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.10 DDR SDRAM mode configuration (DDR_DDR_SDRAM_MODE) The DDR SDRAM mode configuration register sets the values loaded into the DDR's mode registers. Address: 2000h base + 118h offset = 2118h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W ESDMODE SDMODE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_SDRAM_MODE field descriptions Field 0–15 ESDMODE 16–31 SDMODE Description Extended SDRAM mode Specifies the initial value loaded into the DDR SDRAM extended mode register. The range and meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb of ESDMODE, which, in the big-endian convention shown in DDR SDRAM mode configuration (DDR_DDR_SDRAM_MODE) , corresponds to ESDMODE[15]. The msb of the SDRAM extended mode register value must be stored at ESDMODE[0]. The value programmed into this field is also used for writing MR1 during write leveling for DDR3 , although the bits specifically related to the write leveling scheme are handled automatically by the DDR controller. Even if DDR_SDRAM_CFG[BI] is set, this field is still used during write leveling. The write leveling enable bit should be cleared by software in this field. SDRAM mode Specifies the initial value loaded into the DDR SDRAM mode register. The range of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the lsb of SDMODE, which, in the big-endian convention shown in DDR SDRAM mode configuration (DDR_DDR_SDRAM_MODE) , corresponds to SDMODE[15]. The msb of the SDRAM mode register value must be stored at SDMODE[0]. Because the memory controller forces SDMODE[7] to certain values depending on the state of the initialization sequence, (for resetting the SDRAM's DLL) the corresponding bits of this field are ignored by the memory controller. Note that SDMODE[7] is mapped to MA[8]. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 283 DDR memory map/register definition 8.4.11 DDR SDRAM mode configuration 2 (DDR_DDR_SDRAM_MODE_2) The DDR SDRAM mode 2 configuration register sets the values loaded into the DDR's extended mode 2 and 3 registers (for DDR2and DDR3 ). Address: 2000h base + 11Ch offset = 211Ch Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W ESDMODE2 ESDMODE3 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_SDRAM_MODE_2 field descriptions Field 0–15 ESDMODE2 16–31 ESDMODE3 Description Extended SDRAM mode 2 Specifies the initial value loaded into the DDR SDRAM extended 2 mode register. The range and meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of ESDMODE2, which, in the big-endian convention shown in DDR SDRAM mode configuration 2 (DDR_DDR_SDRAM_MODE_2) , corresponds to ESDMODE2[15]. The msb of the SDRAM extended mode 2 register value must be stored at ESDMODE2[0]. Extended SDRAM mode 3 Specifies the initial value loaded into the DDR SDRAM extended 3 mode register. The range of legal values of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the lsb of ESDMODE3, which, in the big-endian convention shown in DDR SDRAM mode configuration 2 (DDR_DDR_SDRAM_MODE_2) , corresponds to ESDMODE3[15]. The msb of the SDRAM extended mode 3 register value must be stored at ESDMODE3[0]. 8.4.12 DDR SDRAM mode control (DDR_DDR_SDRAM_MD_CNTL) The DDR SDRAM mode control register allows the user to carry out the following tasks: • Issue a mode register set command to a particular chip select • Issue an immediate refresh to a particular chip select • Issue an immediate precharge or precharge all command to a particular chip select • Force the CKE signals to a specific value P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 284 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Before issuing a command via the DDR_SDRAM_MD_CNTL register, the DDR interface should be idle. This can be done by setting DDR_SDRAM_CFG[MEM_HALT] and disabling refreshes by clearing DDR_INTERVAL[REFINT]. If there are memory contents that need to be preserved during this time, then software should also force any required refresh commands while DDR_INTERVAL[REFINT] is cleared. The following table shows how DDR_SDRAM_MD_CNTL fields should be set for each of the tasks described above: NOTE Note that MD_EN, SET_REF, and SET_PRE are mutually exclusive; only one of these fields can be set at a time. Table 8-23. Settings of DDR_SDRAM_MD_CNTL Fields Field MD_EN SET_REF SET_PRE CS_SEL MD_SEL MD_VALUE CKE_CNTL Mode Register Set 1 0 0 1 0 0 Chooses chip select (CS) Select mode register. See DDR SDRAM mode control (DDR_DDR_SDRAM_ MD_CNTL) . Value written to mode register Refresh 0 0 Precharge 0 0 1 Selects logical bank Clock Enable Signals Control - Only bit five is significant. See DDR SDRAM mode control (DDR_DDR_SDRAM_ MD_CNTL) . 0 - See DDR SDRAM mode control (DDR_DDR_SDRAM_ MD_CNTL) . Address: 2000h base + 120h offset = 2120h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MD_EN Reserved Reserved CS_SEL MD_SEL SET_ SET_ REF PRE CKE_CNTL Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 285 DDR memory map/register definition Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MD_VALUE W Reset 0 Field 0 MD_EN 1 2–3 CS_SEL 4 5–7 MD_SEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_SDRAM_MD_CNTL field descriptions Description Mode enable Setting this bit specifies that valid data in MD_VALUE is ready to be written to DRAM as one of the following commands: • MODE REGISTER SET • EXTENDED MODE REGISTER SET • EXTENDED MODE REGISTER SET 2 • EXTENDED MODE REGISTER SET 3 The specific command to be executed is selected by setting MD_SEL. In addition, the chip select must be chosen by setting CS_SEL. MD_EN is set by software and cleared by hardware once the command has been issued. 0 Indicates that no mode register set command needs to be issued. 1 Indicates that valid data contained in the register is ready to be issued as a mode register set command. This field is reserved. Reserved Select chip select Specifies the chip select that is driven active due to any command forced by software in DDR_SDRAM_MD_CNTL. 00 Chip select 0 is active 01 Chip select 1 is active 10 Reserved 11 Reserved This field is reserved. Reserved Mode register select MD_SEL specifies one of the following: • During a mode select command, selects the SDRAM mode register to be changed • During a precharge command, selects the SDRAM logical bank to be precharged. A precharge all command ignores this field. • During a refresh command, this field is ignored. NOTE: MD_SEL contains the value that is presented onto the memory bank address pins (MBAn) of the DDR controller. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 286 Freescale Semiconductor, Inc. Field 8 SET_REF 9 SET_PRE 10–11 CKE_CNTL 12–15 - 16–31 MD_VALUE Chapter 8 DDR Memory Controllers DDR_DDR_SDRAM_MD_CNTL field descriptions (continued) 000 MR 001 EMR 010 EMR2 011 EMR3 Description Set refresh Forces an immediate refresh to be issued to the chip select specified by DDR_SDRAM_MD_CNTL[CS_SEL]. This bit is set by software and cleared by hardware once the command has been issued. 0 Indicates that no refresh command needs to be issued. 1 Indicates that a refresh command is ready to be issued. Set precharge Forces a precharge or precharge all to be issued to the chip select specified by DDR_SDRAM_MD_CNTL[CS_SEL]. This bit is set by software and cleared by hardware once the command has been issued. 0 Indicates that no precharge all command needs to be issued. 1 Indicates that a precharge all command is ready to be issued. Clock enable control Allows software to globally clear or set all CKE signals issued to DRAM. Once software has forced the value driven on CKE, that value continues to be forced until software clears the CKE_CNTL bits. At that time, the DDR controller continues to drive the CKE signals to the same value forced by software until another event causes the CKE signals to change (such as, self refresh entry/exit, power down entry/exit). 00 CKE signals are not forced by software. 01 CKE signals are forced to a low value by software. 10 CKE signals are forced to a high value by software. 11 Reserved This field is reserved. Reserved Mode register value This field, which specifies the value that is presented on the memory address pins of the DDR controller during a mode register set command, is significant only when this register is used to issue a mode register set command or a precharge or precharge all command. For a mode register set command, this field contains the data to be written to the selected mode register. For a precharge command, only bit five is significant: 0 Issue a precharge command; MD_SEL selects the logical bank to be precharged 1 Issue a precharge all command; all logical banks are precharged P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 287 DDR memory map/register definition 8.4.13 DDR SDRAM interval configuration (DDR_DDR_SDRAM_INTERVAL) The DDR SDRAM interval configuration register sets the number of DRAM clock cycles between bank refreshes issued to the DDR SDRAMs. In addition, the number of DRAM cycles that a page is maintained after it is accessed is provided here. Address: 2000h base + 124h offset = 2124h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W REFINT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved BSTOPRE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_SDRAM_INTERVAL field descriptions Field 0–15 REFINT 16–17 - 18–31 BSTOPRE Description Refresh interval Represents the number of memory bus clock cycles between refresh cycles. Depending on DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each DDR SDRAM physical bank during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the interface clock frequency. Refreshes are not issued when the REFINT is set to all 0s. This field is reserved. Reserved Precharge interval Sets the duration (in memory bus clocks) that a page is retained after a DDR SDRAM access. If BSTOPRE is zero, the DDR memory controller uses auto-precharge read and write commands rather than operating in page mode. This is called global auto-precharge mode. 8.4.14 DDR SDRAM data initialization (DDR_DDR_DATA_INIT) The DDR SDRAM data initialization register provides the value that is used to initialize memory if DDR_SDRAM_CFG2[D_INIT] is set. Address: 2000h base + 128h offset = 2128h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W INIT_VALUE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 288 Freescale Semiconductor, Inc. Field 0–31 INIT_VALUE Chapter 8 DDR Memory Controllers DDR_DDR_DATA_INIT field descriptions Description Initialization value. Represents the value that DRAM is initialized with if DDR_SDRAM_CFG2[D_INIT] is set. 8.4.15 DDR SDRAM clock control (DDR_DDR_SDRAM_CLK_CNTL) The DDR SDRAM clock control configuration register provides a 1/8-cycle clock adjustment. Address: 2000h base + 130h offset = 2130h Bit 0 1 2 3 4 R W Reserved 5678 CLK_ ADJUST 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_SDRAM_CLK_CNTL field descriptions Field 0–4 5–8 CLK_ADJUST 9–31 - This field is reserved. Reserved Clock adjust Description 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001-1111 Clock is launched aligned with address/command Clock is launched 1/8 applied cycle after address/command Clock is launched 1/4 applied cycle after address/command Clock is launched 3/8 applied cycle after address/command Clock is launched 1/2 applied cycle after address/command Clock is launched 5/8 applied cycle after address/command Clock is launched 3/4 applied cycle after address/command Clock is launched 7/8 applied cycle after address/command Clock is launched 1 applied cycle after address/command Reserved This field is reserved. Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 289 DDR memory map/register definition 8.4.16 DDR training initialization address (DDR_DDR_INIT_ADDR) The DDR SDRAM initialization address register provides the address that is used for the data strobe to data skew adjustment and automatic CAS to preamble calibration after POR. NOTE After the skew adjustment, this address contains bad ECC data. This is not important at POR, as all of memory should be subsequently initialized if ECC is enabled (either by software or through the use of DDR_SDRAM_CFG_2[D_INIT]). NOTE If an HRESET has been issued after the DRAM is in selfrefresh mode, however, memory is not initialized, so this address should be written to using a 32-byte transaction to avoid possible ECC errors if this address could later be accessed. Address: 2000h base + 148h offset = 2148h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W INIT_ADDR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_INIT_ADDR field descriptions Field 0–31 INIT_ADDR Description Initialization address. Represents the address that is used for the data strobe to data skew adjustment and automatic CAS to preamble calibration at POR. This address is written to during the initialization sequence. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 290 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.17 DDR training initialization extended address (DDR_DDR_INIT_EXT_ADDR) The DDR SDRAM initialization extended address register provides the extended address that is used for the data strobe to data skew adjustment and automatic CAS to preamble calibration after POR. Address: 2000h base + 14Ch offset = 214Ch Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W UIA Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved INIT_EXT_ADDR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_INIT_EXT_ADDR field descriptions Field Description 0 Use initialization address UIA 0 Use the default address for training sequence as calculated by the controller. This is the first valid address in the first enabled chip select. 1 Use the initialization address programmed in DDR_INIT_ADDR and DDR_INIT_EXT_ADDR. 1–27 - This field is reserved. Reserved 28–31 Initialization extended address INIT_EXT_ADDR Represents the extended address that is used for the data strobe to data skew adjustment and automatic CAS to preamble calibration at POR. This extended address is written to during the initialization sequence. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 291 DDR memory map/register definition 8.4.18 DDR SDRAM timing configuration 4 (DDR_TIMING_CFG_4) The DDR SDRAM timing configuration 4 register provides additional timing fields required to support DDR3 memories. Address: 2000h base + 160h offset = 2160h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W RWT WRT RRT WWT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0–3 RWT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved DLL_LOCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_TIMING_CFG_4 field descriptions Description Read-to-write turnaround for same chip select Specifies how many cycles are added between a read to write turnaround for transactions to the same chip select. If a value of 0000 is chosen, then the DDR controller uses the value used for transactions to different chip selects, as defined in TIMING_CFG_0[RWT]. This field can be used to improve performance when operating in burst-chop mode by forcing transactions to the same chip select to use extra cycles, while transaction to different chip selects can utilize the tri-state time on the DRAM interface. Regardless of the value that is set in this field, the value defined by TIMING_CFG_0[RWT] also is met before issuing a write command. 4–7 WRT 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Default 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks Write-to-read turnaround for same chip select Specifies how many cycles are added between a write to read turnaround for transactions to the same chip select. If a value of 0000 is chosen, then the DDR controller uses the value used for transactions to different chip selects, as defined in TIMING_CFG_0[WRT]. This field can be used to improve performance Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 292 Freescale Semiconductor, Inc. Field 8–11 RRT 12–15 WWT Chapter 8 DDR Memory Controllers DDR_TIMING_CFG_4 field descriptions (continued) Description when operating in burst-chop mode by forcing transactions to the same chip select to use extra cycles, while transaction to different chip selects can utilize the tri-state time on the DRAM interface. Regardless of the value that is set in this field, the value defined by TIMING_CFG_0[WRT] also is met before issuing a read command. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Default 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks Read-to-read turnaround for same chip select Specifies how many cycles are added between reads to the same chip select. If a value of 0000 is chosen, then 2 cycles are required between read commands to the same chip select if 4-beat bursts are used (4 cycles are required if 8-beat bursts are used). Note that DDR3 does not support 4-beat bursts. However, this field may be used to add extra cycles when burst-chop mode is used, and the DDR controller must wait 4 cycles for read-to-read transactions to the same chip select. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 BL/2 clocks BL/2 + 1 clock BL/2 + 2 clocks BL/2 + 3 clocks BL/2 + 4 clocks BL/2 + 5 clocks BL/2 + 6 clocks BL/2 + 7 clocks BL/2 + 8 clocks BL/2 + 9 clocks BL/2 + 10 clocks BL/2 + 11 clocks BL/2 + 12 clocks BL/2 + 13 clocks BL/2 + 14 clocks BL/2 + 15 clocks Write-to-write turnaround for same chip select Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 293 DDR memory map/register definition DDR_TIMING_CFG_4 field descriptions (continued) Field Description Specifies how many cycles are added between writes to the same chip select. If a value of 0000 is chosen, then 2 cycles are required between write commands to the same chip select if 4-beat bursts are used (4 cycles are required if 8-beat bursts are used). Note that DDR3 does not support 4-beat bursts. However, this field may be used to add extra cycles when burst-chop mode is used, and the DDR controller must wait 4 cycles for write-to-write transactions to the same chip select. 16–29 - 30–31 DLL_LOCK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 BL/2 clocks BL/2 + 1 clock BL/2 + 2 clocks BL/2 + 3 clocks BL/2 + 4 clocks BL/2 + 5 clocks BL/2 + 6 clocks BL/2 + 7 clocks BL/2 + 8 clocks BL/2 + 9 clocks BL/2 + 10 clocks BL/2 + 11 clocks BL/2 + 12 clocks BL/2 + 13 clocks BL/2 + 14 clocks BL/2 + 15 clocks This field is reserved. Reserved DDR SDRAM DLL Lock Time. This provides the number of cycles that it takes for the DRAMs DLL to lock at POR and after exiting self refresh. The controller waits the specified number of cycles before issuing any commands after exiting POR or self refresh. 00 200 clocks 01 512 clocks 10 Reserved 11 Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 294 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.19 DDR SDRAM timing configuration 5 (DDR_TIMING_CFG_5) The DDR SDRAM timing configuration 5 register provides additional timing fields required to support DDR3 memories. Address: 2000h base + 164h offset = 2164h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Reserved R Reserved W RODT_ON RODT_OFF Reserved WOD T_ON Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R WODT_ON W WODT_OFF Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_TIMING_CFG_5 field descriptions Field 0–2 - 3–7 RODT_ON Description This field is reserved. Reserved Read to ODT on Specifies the number of cycles that passes from when a read command is placed on the DRAM bus until the assertion of the relevant ODT signal(s). The default case (00000) provides a decode of RL - 3 cycles to support legacy of past products. RL is the read latency, derived from CAS latency + additive latency. If 2T/3T timing is used, one/two extra cycle(s) is/are automatically added to the value selected in this field. 00000 00001 00010 00011 01111 RL 3 clocks 0 clocks 1 clocks 2 clocks ... 14 clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 295 DDR memory map/register definition DDR_TIMING_CFG_5 field descriptions (continued) Field 8 9–11 RODT_OFF Description 10000 10001 10011 15 clocks 16 clocks 18 clocks ... 11111 30 clocks This field is reserved. Reserved Read to ODT off Specifies the number of cycles that the relevant ODT signal(s) remains asserted for each read transaction. The default case (000) leaves the ODT signal(s) asserted for 3 DRAM cycles. 12–14 - 15–19 WODT_ON 000 3 clocks 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks This field is reserved. Reserved Write to ODT On Specifies the number of cycles that passes from when a write command is placed on the DRAM bus until the assertion of the relevant ODT signal(s). The default case (00000) provides a decode of WL - 3 cycles to support legacy of past products. WL is the write latency, derived from Write Latency + Additive Latency. If 2T/3T timing is used, one/two extra cycle(s) is/are automatically added to the value selected in this field. 20 - 21–23 WODT_OFF 00000 00001 00010 00011 WL - 3 clocks 0 clocks 1 clocks 2 clocks 01111 10000 10011 ... 14 clocks 15 clocks 18 clocks ... 11111 30 clocks This field is reserved. Reserved Write to ODT Off Specifies the number of cycles that the relevant ODT signal(s) remains asserted for each write transaction. The default case (000) leaves the ODT signal(s) asserted for 3 DRAM cycles. 000 3 clocks 001 1 clock 010 2 clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 296 Freescale Semiconductor, Inc. Field 24–31 - Chapter 8 DDR Memory Controllers DDR_TIMING_CFG_5 field descriptions (continued) 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks This field is reserved. Reserved Description 8.4.20 DDR ZQ calibration control (DDR_DDR_ZQ_CNTL) The DDR ZQ calibration control register provides the enable and controls required for ZQ calibration when using DDR3 SDRAM devices. There is a limitation for various DRAM timing parameters when ZQ calibration is used. The following factors are involved in this limitation: • DDR_ZQ_CNTL[ZQOPER] • DDR_ZQ_CNTL[ZQCS] • TIMING_CFG_1[PRETOACT] • TIMING_CFG_1[REFREC] • DDR_SDRAM_INTERVAL[REFINT] • the number of chip selects enabled If the following condition is true: [((DDR_ZQ_CNTL[ZQOPER] + DDR_ZQ_CNTL[ZQCS]) x (# enabled chip selects)) + TIMING_CFG_1[PRETOACT] + TIMING_CFG_1[REFREC] + 2t CK ] > (DDR_SDRAM_INTERVAL[REFINT]), Then it is possible that one refresh is skipped when the controller is exiting self refresh. If this is an issue, then posted refreshes could be used to extend the refresh interval. Another alternative is to use the DDR_SDRAM_MD_CNTL register to force an extra refresh to each chip select after exiting self refresh mode. However, DDR3 timing parameters for most devices/frequencies do not allow for a refresh to be missed. Address: 2000h base + 170h offset = 2170h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R ZQ_ W EN Reserved ZQINIT Reserved ZQOPER Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 297 DDR memory map/register definition Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved ZQCS Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_ZQ_CNTL field descriptions Field 0 ZQ_EN Description ZQ Calibration Enable. This bit determines if ZQ calibration is used. This bit should only be set if DDR3 memory is used (DDR_SDRAM_CFG[SDRAM_TYPE] = 3'b111). 1–3 - 4–7 ZQINIT 0 ZQ Calibration is not used. 1 ZQ Calibration is used. A ZQCL command is issued by the DDR controller after POR and anytime the DDR controller is exiting self refresh. A ZQCS command is issued every 32 refresh sequences to account for VT variations. This field is reserved. Reserved POR ZQ Calibration Time (t ZQinit ). Determines the number of cycles that must be allowed for DRAM ZQ calibration at POR. Each chip select is calibrated separately, and this time must elapse after the ZQCL command is issued for each chip select before a separate command may be issued. 8–11 - 12–15 ZQOPER 0000-0110 0111 1000 1001 1010 1011-1111 Reserved 128 clocks 256 clocks 512 clocks 1024 clocks Reserved This field is reserved. Reserved Normal Operation Full Calibration Time (t ZQoper ). Determines the number of cycles that must be allowed for DRAM ZQ calibration when exiting self refresh. Each chip select is calibrated separately, and this time must elapse after the ZQCL command is issued for each chip select before a separate command may be issued. 16–19 - 20–23 ZQCS 0000-0110 0111 1000 1001 1010 1011-1111 Reserved 128 clocks 256 clocks 512 clocks 1024 clocks Reserved This field is reserved. Reserved Normal Operation Short Calibration Time (t ZQCS ). Determines the number of cycles that must be allowed for DRAM ZQ calibration during dynamic calibration which is issued every 32 refresh cycles. Each chip select is calibrated separately, and this time must elapse after the ZQCS command is issued for each chip select before a separate command may be issued. 0000 0001 0010 0011 0100 1 clocks 2 clocks 4 clocks 8 clocks 16 clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 298 Freescale Semiconductor, Inc. Field 24–31 - Chapter 8 DDR Memory Controllers DDR_DDR_ZQ_CNTL field descriptions (continued) 0101 0110 0111 1000 1001 1010-1111 32 clocks 64 clocks 128 clocks 256 clocks 512 clocks Reserved This field is reserved. Reserved Description 8.4.21 DDR write leveling control (DDR_DDR_WRLVL_CNTL) The DDR write leveling control register provides controls for write leveling, as it is supported for DDR3 memory devices. Address: 2000h base + 174h offset = 2174h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved WRLVL_MRD WRLVL_ODTEN WRLVL_DQSEN W WRLVL_EN Reserved Reserved Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R WRLVL_SMPL W WRLVL_WLR Reserved WRLVL_START Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_WRLVL_CNTL field descriptions Field 0 WRLVL_EN Write Leveling Enable Description Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 299 DDR memory map/register definition DDR_DDR_WRLVL_CNTL field descriptions (continued) Field Description This bit determines if write leveling is used. If this bit is set, then the DDR controller performs write leveling immediately after initializing the DRAM. This bit should only be set if DDR3 memory is used (DDR_SDRAM_CFG[SDRAM_TYPE] = 3'b111). 1–4 - 5–7 WRLVL_MRD 0 Write leveling is not used 1 Write leveling is used This field is reserved. Reserved First DQS pulse rising edge after margining mode is programmed (t WL_MRD ). Determines how many cycles to wait after margining mode has been programmed before the first DQS pulse may be issued. This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set. 000 1 clocks 001 2 clocks 010 4 clocks 011 8 clocks 100 16 clocks 101 32 clocks 110 64 clocks 111 128 clocks 8 This field is reserved. - Reserved 9–11 ODT delay after margining mode is programmed (t WL_ODTEN ). Determines how many cycles to wait after WRLVL_ODTEN margining mode has been programmed until ODT may be asserted. This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set. 000 1 clocks 001 2 clocks 010 4 clocks 011 8 clocks 100 16 clocks 101 32 clocks 110 64 clocks 111 128 clocks 12 This field is reserved. - Reserved 13–15 DQS/ DQS delay after margining mode is programmed (t WL_DQSEN ). Determines how many cycles to wait WRLVL_DQSEN after margining mode has been programmed until DQS may be actively driven. This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set. 000 1 clocks 001 2 clocks 010 4 clocks 011 8 clocks 100 16 clocks 101 32 clocks 110 64 clocks 111 128 clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 300 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers DDR_DDR_WRLVL_CNTL field descriptions (continued) Field 16–19 WRLVL_SMPL Description Write leveling sample time Determines the number of cycles that must pass before the data signals are sampled after a DQS pulse during margining mode. This field should be programmed at least 6 cycles higher than t WLO to allow enough time for propagation delay and sampling of the prime data bits. This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set. 20 - 21–23 WRLVL_WLR 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved (if DDR_WRLVL_CNTL[WRLVL_EN] is set) 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks This field is reserved. Reserved Write leveling repetition time Determines the number of cycles that must pass between DQS pulses during write leveling. This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set. 000 1 clocks 001 2 clocks 010 4 clocks 011 8 clocks 100 16 clocks 101 32 clocks 110 64 clocks 111 128 clocks 24–27 - This field is reserved. Reserved, should be cleared. 28–31 Write leveling start time. Determines the value to use for the DQS_ADJUST for the first sample when write WRLVL_START leveling is enabled. 0000 0001 0010 0011 0100 0101 0110 0 clock delay 1/8 clock delay 1/4 clock delay 3/8 clock delay 1/2 clock delay 5/8 clock delay 3/4 clock delay Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 301 DDR memory map/register definition DDR_DDR_WRLVL_CNTL field descriptions (continued) Field 0111 1000 1001 1010 1011 1100 1101 1110 1111 7/8 clock delay 1 clock delay 9/8 clock delay 5/4 clock delay 11/8 clock delay 3/2 clock delay 13/8 clock delay 7/4 clock delay 15/8 clock delay Description 8.4.22 DDR Self Refresh Counter (DDR_DDR_SR_CNTR) The DDR self-refresh counter register can be programmed to force the DDR controller to enter self-refresh after a predefined period of idle time. Address: 2000h base + 17Ch offset = 217Ch Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved SR_IT Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_SR_CNTR field descriptions Field 0–11 - 12–15 SR_IT Description This field is reserved. Reserved Self Refresh Idle Threshold Defines the number of DRAM cycles that must pass while the DDR controller is idle before it will enter self refresh. Anytime a transaction is issued to the DDR controller, it will reset its internal counter. When a new transaction is received by the DDR controller, it will exit self refresh and reset its internal counter. If this field is zero, then the described power savings feature is disabled. In addition, if a non-zero value is programmed into this field, then the DDR controller will exit self refresh anytime a transaction is issued to the DDR controller, regardless of the reason self refresh was initially entered. If this field is set to a non-zero value, then DDR_SDRAM_CFG[SREN] must also be set. Patterns not shown are reserved. NOTE: The term 'clock' refers to the data rate rather than the clock frequency of the DDR interface. 0000 0001 0010 0011 0100 Automatic self refresh entry disabled 2^10 DRAM clocks (DDR2 only; reserved for DDR3) 2^12 DRAM clocks 2^14 DRAM clocks 2^16 DRAM clocks Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 302 Freescale Semiconductor, Inc. Field 16–31 - Chapter 8 DDR Memory Controllers DDR_DDR_SR_CNTR field descriptions (continued) 0101 0110 0111 1000 1001 1010 1011 2^18 DRAM clocks 2^20 DRAM clocks 2^22 DRAM clocks 2^24 DRAM clocks 2^26 DRAM clocks 2^28 DRAM clocks 2^30 DRAM clocks This field is reserved. Reserved Description 8.4.23 DDR Register Control Words 1 (DDR_DDR_SDRAM_RCW_1) The DDR register control word 1 register should be programmed with the intended values of the register control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 4-bit field represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during register control word writes. Address: 2000h base + 180h offset = 2180h Bit 0 1 2 3 R W RCW0 Reset 0 0 0 0 4567 RCW1 0000 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RCW2 RCW3 RCW4 RCW5 RCW6 RCW7 000000000000000000000000 DDR_DDR_SDRAM_RCW_1 field descriptions Field 0–3 RCW0 4–7 RCW1 8–11 RCW2 12–15 RCW3 16–19 RCW4 20–23 RCW5 24–27 RCW6 Description Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 0. Register Control Word 1. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 1. Register Control Word 2. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 2. Register Control Word 3. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 3. Register Control Word 4. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 4. Register Control Word 5. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 5. Register Control Word 6. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 6. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 303 DDR memory map/register definition DDR_DDR_SDRAM_RCW_1 field descriptions (continued) Field 28–31 RCW7 Description Register Control Word 7. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 7. 8.4.24 DDR Register Control Words 2 (DDR_DDR_SDRAM_RCW_2) The DDR register control word 2 register should be programmed with the intended values of the register control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 4-bit field represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during register control word writes. Address: 2000h base + 184h offset = 2184h Bit 0 1 2 3 R W RCW8 Reset 0 0 0 0 4567 RCW9 0000 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RCW10 RCW11 RCW12 RCW13 RCW14 RCW15 000000000000000000000000 DDR_DDR_SDRAM_RCW_2 field descriptions Field 0–3 RCW8 4–7 RCW9 8–11 RCW10 12–15 RCW11 16–19 RCW12 20–23 RCW13 24–27 RCW14 28–31 RCW15 Description Register Control Word 8. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 8. Register Control Word 9. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 9. Register Control Word 10. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 10. Register Control Word 11. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 11. Register Control Word 12. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 12. Register Control Word 13. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 13. Register Control Word 14. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 14. Register Control Word 15. Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 15. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 304 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.25 DDR write leveling control 2 (DDR_DDR_WRLVL_CNTL_2) The DDR write leveling control 2 register provides controls for write leveling, as it is supported for DDR3 memory devices. This register specifically defines the starting points for the individual data strobes. Address: 2000h base + 190h offset = 2190h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved WRLVL_START_ 1 Reserved WRLVL_START_ 2 Reserved WRLVL_START_ 3 Reserved WRLVL_START_ 4 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDR_WRLVL_CNTL_2 field descriptions Field Description 0–2 This field is reserved. - Reserved 3–7 Write leveling start time for DQS[1]. Determines the value to use for the DQS_ADJUST for the first sample WRLVL_START_ when write leveling is enabled. 1 00000 Use value from DDR_WRLVL_CNTL[WRLVL_START] 00001 1/8 clock delay 00010 1/4 clock delay 00011 3/8 clock delay 00100 1/2 clock delay 00101 5/8 clock delay 00110 3/4 clock delay 00111 7/8 clock delay 01000 1 clock delay 01001 9/8 clock delay 01010 5/4 clock delay 01011 11/8 clock delay 01100 3/2 clock delay 01101 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101-11111 Reserved 8–10 - This field is reserved. Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 305 DDR memory map/register definition DDR_DDR_WRLVL_CNTL_2 field descriptions (continued) Field Description 11–15 Write leveling start time for DQS[2]. Determines the value to use for the DQS_ADJUST for the first sample WRLVL_START_ when write leveling is enabled. 2 00000 Use value from DDR_WRLVL_CNTL[WRLVL_START] 00001 1/8 clock delay 00010 1/4 clock delay 00011 3/8 clock delay 00100 1/2 clock delay 00101 5/8 clock delay 00110 3/4 clock delay 00111 7/8 clock delay 01000 1 clock delay 01001 9/8 clock delay 01010 5/4 clock delay 01011 11/8 clock delay 01100 3/2 clock delay 01101 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101-11111 Reserved 16–18 - This field is reserved. Reserved 19–23 Write leveling start time for DQS[3]. Determines the value to use for the DQS_ADJUST for the first sample WRLVL_START_ when write leveling is enabled. 3 00000 Use value from DDR_WRLVL_CNTL[WRLVL_START] 00001 1/8 clock delay 00010 1/4 clock delay 00011 3/8 clock delay 00100 1/2 clock delay 00101 5/8 clock delay 00110 3/4 clock delay 00111 7/8 clock delay 01000 1 clock delay 01001 9/8 clock delay 01010 5/4 clock delay 01011 11/8 clock delay 01100 3/2 clock delay 01101 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 306 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers DDR_DDR_WRLVL_CNTL_2 field descriptions (continued) Field Description 10010 10011 10100 10101-11111 9/4 clock delay 19/8 clock delay 5/2 clock delay Reserved 24–26 - This field is reserved. Reserved 27–31 Write leveling start time for DQS[4]. Determines the value to use for the DQS_ADJUST for the first sample WRLVL_START_ when write leveling is enabled. 4 00000 Use value from DDR_WRLVL_CNTL[WRLVL_START] 00001 1/8 clock delay 00010 1/4 clock delay 00011 3/8 clock delay 00100 1/2 clock delay 00101 5/8 clock delay 00110 3/4 clock delay 00111 7/8 clock delay 01000 1 clock delay 01001 9/8 clock delay 01010 5/4 clock delay 01011 11/8 clock delay 01100 3/2 clock delay 01101 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101-11111 Reserved 8.4.26 DDR write leveling control 3 (DDR_DDR_WRLVL_CNTL_3) The DDR write leveling control 3 register provides controls for write leveling, as it is supported for DDR3 memory devices. This register specifically defines the starting points for the individual data strobes. Address: 2000h base + 194h offset = 2194h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved WRLVL_START_ 5 Reserved WRLVL_START_ 6 Reserved WRLVL_START_ 7 Reserved WRLVL_START_ 8 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 307 DDR memory map/register definition DDR_DDR_WRLVL_CNTL_3 field descriptions Field Description 0–2 This field is reserved. - Reserved 3–7 Write leveling start time for DQS[5]. Determines the value to use for the DQS_ADJUST for the first sample WRLVL_START_ when write leveling is enabled. 5 00000 Use value from DDR_WRLVL_CNTL[WRLVL_START] 00001 1/8 clock delay 00010 1/4 clock delay 00011 3/8 clock delay 00100 1/2 clock delay 00101 5/8 clock delay 00110 3/4 clock delay 00111 7/8 clock delay 01000 1 clock delay 01001 9/8 clock delay 01010 5/4 clock delay 01011 11/8 clock delay 01100 3/2 clock delay 01101 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101-11111 Reserved 8–10 - This field is reserved. Reserved 11–15 Write leveling start time for DQS[6]. Determines the value to use for the DQS_ADJUST for the first sample WRLVL_START_ when write leveling is enabled. 6 00000 Use value from DDR_WRLVL_CNTL[WRLVL_START] 00001 1/8 clock delay 00010 1/4 clock delay 00011 3/8 clock delay 00100 1/2 clock delay 00101 5/8 clock delay 00110 3/4 clock delay 00111 7/8 clock delay 01000 1 clock delay 01001 9/8 clock delay 01010 5/4 clock delay 01011 11/8 clock delay 01100 3/2 clock delay 01101 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 308 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers DDR_DDR_WRLVL_CNTL_3 field descriptions (continued) Field Description 16–18 - 10000 10001 10010 10011 10100 10101-11111 2 clock delay 17/8 clock delay 9/4 clock delay 19/8 clock delay 5/2 clock delay Reserved This field is reserved. Reserved 19–23 Write leveling start time for DQS[7]. Determines the value to use for the DQS_ADJUST for the first sample WRLVL_START_ when write leveling is enabled. 7 00000 Use value from DDR_WRLVL_CNTL[WRLVL_START] 00001 1/8 clock delay 00010 1/4 clock delay 00011 3/8 clock delay 00100 1/2 clock delay 00101 5/8 clock delay 00110 3/4 clock delay 00111 7/8 clock delay 01000 1 clock delay 01001 9/8 clock delay 01010 5/4 clock delay 01011 11/8 clock delay 01100 3/2 clock delay 01101 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101-11111 Reserved 24–26 - This field is reserved. Reserved 27–31 Write leveling start time for DQS[8]. Determines the value to use for the DQS_ADJUST for the first sample WRLVL_START_ when write leveling is enabled. 8 00000 Use value from DDR_WRLVL_CNTL[WRLVL_START] 00001 1/8 clock delay 00010 1/4 clock delay 00011 3/8 clock delay 00100 1/2 clock delay 00101 5/8 clock delay 00110 3/4 clock delay 00111 7/8 clock delay 01000 1 clock delay Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 309 DDR memory map/register definition DDR_DDR_WRLVL_CNTL_3 field descriptions (continued) Field 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101-11111 9/8 clock delay 5/4 clock delay 11/8 clock delay 3/2 clock delay 13/8 clock delay 7/4 clock delay 15/8 clock delay 2 clock delay 17/8 clock delay 9/4 clock delay 19/8 clock delay 5/2 clock delay Reserved Description 8.4.27 DDR Debug Status Register 1 (DDR_DDRDSR_1) The DDRDSR_1 register contains the DDR driver compensation input value and the current settings of the P and N FET impedance for MDICn, command/control, and data. Address: 2000h base + B20h offset = 2B20h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DDRDC W MDICPZ MDICNZ Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CPZ CNZ DPZ DNZ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDRDSR_1 field descriptions Field 0–1 DDRDC 2–5 MDICPZ 6–9 MDICNZ 10–15 - DDR driver compensation input value Description Current setting of PFET driver MDIC impedance Current setting of NFET driver MDIC impedance This field is reserved. Reserved, should be cleared. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 310 Freescale Semiconductor, Inc. Field 16–19 CPZ 20–23 CNZ 24–27 DPZ 28–31 DNZ Chapter 8 DDR Memory Controllers DDR_DDRDSR_1 field descriptions (continued) Description Current setting of PFET driver command impedance Current setting of NFET driver command impedance Current setting of PFET driver data impedance Current setting of NFET driver data impedance 8.4.28 DDR Debug Status Register 2 (DDR_DDRDSR_2) The DDRDSR_2 register contains the current settings of the P and N FET impedance for the DDR drivers for clocks. Address: 2000h base + B24h offset = 2B24h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CLKPZ W CLKNZ Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDRDSR_2 field descriptions Field 0–3 CLKPZ 4–7 CLKNZ 8–31 - Description Current setting of PFET driver clock impedance Current setting of NFET driver clock impedance This field is reserved. Reserved 8.4.29 DDR Control Driver Register 1 (DDR_DDRCDR_1) DDRCDR_1 sets the driver hardware compensation enable, the DDR MDIC driver P/N impedance, ODT termination value for IOs, driver software override enable for MDIC, driver software override enable for address/command, driver software override enable for data, the DDR address/command driver P/N impedance, and the DDR data driver P/N impedance. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 311 DDR memory map/register definition The fields in DDRCDR_1, other than DDRCDR_1[ODT], are used to enable driver calibration with the MDIC[0:1] pins. This can be used to calibrate the DDR drivers to the external calibration resistors on the MDIC pins. However, this should only be used for full-strength driver applications. Hardware DDR driver calibration is enabled by setting DDRCDR_1[DHC_EN]. NOTE All driver calibration, whether by software or hardware, should be done before the DDR controller is enabled (before DDR_SDRAM_CFG[MEM_EN] is set). Software can be used to calibrate the drivers instead of the automatic hardware calibration. If software calibration is used, the following steps should be taken: 1. Set DDRCDR_1[DSO_MDIC_EN] and ensure that DDRCDR_1[DHC_EN] is cleared 2. Set the highest impedance (value 0000) for DDRCDR_1[DSO_MDICPZ] 3. Set DDRCDR_1[DSO_MDIC_PZ_OE] to enable the output enable for MDIC[0] 4. After at least 4 cycles, read DDRDSR_1[0]. If the value is 0, then use the next lowest impedance, and read DDRDSR_1[0] again. Once a value of 1 is detected, then leave DDRCDR_1[DSO_MDICPZ] at the calibrated value 5. Clear DDRCDR_1[DSO_MDIC_PZ_OE] 6. After DDRCDR_1[DSO_MDICPZ} is calibrated, set a value of 0000 for DDRCDR_1[DSO_MDICNZ] 7. Set DDRCDR_1[DSO_MDIC_NZ_OE] to enable the output enable for MDIC[1] 8. After at least 4 cycles, read DDRDSR_1[1]. If the value is 1, then use the next lowest impedance, and read DDRDSR_1[1] again. Once a value of 0 is detected, then leave DDRCDR_1[DSO_MDICNZ] at the calibrated value 9. Clear DDRCDR_1[DSO_MDIC_NZ_OE] The table below lists the valid impedance override values from highest impedance (lowest drive strength) to lowest impedance (highest drive strength). Note that the drivers may be calibrated to either full-strength or half-strength. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 312 Freescale Semiconductor, Inc. Highest Lowest Chapter 8 DDR Memory Controllers Table 8-41. Valid Impedance Override Values Driver Impedance Impedance Override Values 0000 - 0001 - 0011 - 0010 - 0110 - 0111 1 0101 - 0100 - 1100 - 1101 - 1111 - 1110 - 1010 - 1011 2 1001 - 1000 3 Notes 1. 0111 provides the target for half-strength mode in both DDR2 (1.8 V) and DDR3 (1.5 V) modes when driver calibration is not used. 2. 1011 provides the target for full-strength mode in DDR2 (1.8 V) when driver calibration is not used. 3. 1000 provides the target for full-strength mode in DDR3 mode (1.5 V) when driver calibration is not used. Address: 2000h base + B28h offset = 2B28h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DSO_MDICPZ DSO_MDICNZ W ODT DHC_EN DSO_MDIC_EN DSO_MDIC_PZ_ OE DSO_MDIC_NZ_ OE DSO_C_EN DSO_D_EN Reset 0 0 0 0 Bit 16 17 18 19 R DSO_CPZ W Reset 0 0 0 0 0 0 0 0 20 21 22 23 DSO_CNZ 0 0 0 0 0 0 0 0 24 25 26 27 DSO_DPZ 0 0 0 0 0 0 0 0 28 29 30 31 DSO_DNZ 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 313 DDR memory map/register definition DDR_DDRCDR_1 field descriptions Field Description 0 DHC_EN DDR driver hardware compensation enable 1 Driver software override enable for MDIC DSO_MDIC_EN 2–5 DDR driver software MDIC p-impedance override DSO_MDICPZ 6–9 DDR driver software MDIC n-impedance override DSO_MDICNZ 10 Driver software override p-impedance output enable DSO_MDIC_PZ_ OE 11 Driver software override n-impedance output enable DSO_MDIC_NZ_ OE 12–13 ODT ODT termination value for IOs. This field is combined with DDRCDR_2[ODT] to determine the termination value. Below is the termination based on concatenating these two fields. Note that the order of concatenation is (from left to right) DDRCDR_1[ODT], DDRCDR_2[ODT] 14 DSO_C_EN 15 DSO_D_EN 16–19 DSO_CPZ 20–23 DSO_CNZ 24–27 DSO_DPZ 28–31 DSO_DNZ 000 75 O 001 55 O 010 60 O 011 50 O 100 150 O 101 43 O 110 120 O 111 Reserved Driver software override enable for address/command Driver software override enable for data DDR driver software command p-impedance override DDR driver software command n-impedance override Driver software data p-impedance override Driver software data n-impedance override 1. 0111 provides the target for half-strength mode in both DDR2 (1.8 V) and DDR3 (1.5 V) modes when driver calibration is not used. 2. 1011 provides the target for full-strength mode in DDR2 (1.8 V) when driver calibration is not used. 3. 1000 provides the target for full-strength mode in DDR3 mode (1.5 V) when driver calibration is not used. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 314 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.30 DDR Control Driver Register 2 (DDR_DDRCDR_2) The DDRCDR_2 sets the driver software override enable for clocks and the DDR clocks driver P/N impedance. DSO_CLK_EN Address: 2000h base + B2Ch offset = 2B2Ch Bit 0 1 2 3 4 5 6 7 R Reserved DSO_CLKPZ W 8 9 10 11 12 13 14 15 DSO_CLKNZ Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved ODT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DDRCDR_2 field descriptions Field 0 DSO_CLK_EN 1–3 - 4–7 DSO_CLKPZ 8–11 DSO_CLKNZ 12–30 - 31 ODT Driver software override enable for clocks Description This field is reserved. Reserved Driver software clocks p-impedance override Driver software clocks n-impedance override This field is reserved. Reserved ODT termination value for IOs. This field is combined with DDRCDR_1[ODT] to determine the termination value. Below is the termination based on concatenating these two fields. Note that the order of concatenation is (from left to right) DDRCDR_1[ODT], DDRCDR_2[ODT] 000 75 O 001 55 O 010 60 O 011 50 O 100 150 O 101 43 O 110 120 O 111 Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 315 DDR memory map/register definition 8.4.31 DDR IP block revision 1 (DDR_DDR_IP_REV1) The DDR IP block revision 1 register provides read-only fields with the IP block ID, along with major and minor revision information. Address: 2000h base + BF8h offset = 2BF8h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IP_ID IP_MJ IP_MN W Reset n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n DDR_DDR_IP_REV1 field descriptions Field 0–15 IP_ID 16–23 IP_MJ 24–31 IP_MN Description IP block ID. For the DDR controller, this value is 0x0002. Major revision. This is currently set to 0x04. Minor revision. This is currently set to 0x03. 8.4.32 DDR IP block revision 2 (DDR_DDR_IP_REV2) The DDR IP block revision 2 register provides read-only fields with the IP block integration and configuration options. Address: 2000h base + BFCh offset = 2BFCh Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W IP_INT Reserved IP_CFG Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 DDR_DDR_IP_REV2 field descriptions Field 0–7 - 8–15 IP_INT This field is reserved. Reserved IP block integration options Description Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 316 Freescale Semiconductor, Inc. Field 16–23 - 24–31 IP_CFG Chapter 8 DDR Memory Controllers DDR_DDR_IP_REV2 field descriptions (continued) This field is reserved. Reserved IP block configuration options Description 8.4.33 Memory data path error injection mask high (DDR_DATA_ERR_INJECT_HI) Address: 2000h base + E00h offset = 2E00h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W EIMH Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DATA_ERR_INJECT_HI field descriptions Field 0–31 EIMH Description Error injection mask high data path Used to test ECC by forcing errors on the high word of the data path. Setting a bit causes the corresponding data path bit to be inverted on memory bus writes. 8.4.34 Memory data path error injection mask low (DDR_DATA_ERR_INJECT_LO) Address: 2000h base + E04h offset = 2E04h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W EIML Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_DATA_ERR_INJECT_LO field descriptions Field 0–31 EIML Description Error injection mask low data path Used to test ECC by forcing errors on the low word of the data path. Setting a bit causes the corresponding data path bit to be inverted on memory bus writes. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 317 DDR memory map/register definition 8.4.35 Memory data path error injection mask ECC (DDR_ERR_INJECT) The memory data path error injection mask ECC register sets the ECC mask, enables errors to be written to ECC memory, and allows the ECC byte to mirror the most significant data byte.In addition, a single address parity error may be injected through this register. Address: 2000h base + E08h offset = 2E08h Bit 0 1 2 3 4 5 R W 6 7 8 Reserved 9 10 11 12 13 14 15 APIEN Reset 0 Bit 16 R W Reset 0 Field 0–14 15 APIEN 16–21 22 EMB 23 EIEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved EMB EIEN EEIM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_ERR_INJECT field descriptions Description This field is reserved. Reserved Address parity error injection enable. This bit is cleared by hardware after a single address parity error has been injected. 0 Address parity error injection disabled. 1 Address parity error injection enabled. This field is reserved. Reserved ECC mirror byte 0 Mirror byte functionality disabled. 1 Mirror the most significant data path byte onto the ECC byte. Error injection enable 0 Error injection disabled. 1 Error injection enabled. This applies to the data mask bits, the ECC mask bits, and the ECC mirror bit. Note that error injection should not be enabled until the memory controller has been enabled through DDR_SDRAM_CFG[MEM_EN]. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 318 Freescale Semiconductor, Inc. Field 24–31 EEIM Chapter 8 DDR Memory Controllers DDR_ERR_INJECT field descriptions (continued) Description ECC error injection mask. Setting a mask bit causes the corresponding ECC bit to be inverted on memory bus writes. 8.4.36 Memory data path read capture high (DDR_CAPTURE_DATA_HI) The memory data path read capture high register stores the high word of the read data path during error capture. Address: 2000h base + E20h offset = 2E20h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W ECHD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_CAPTURE_DATA_HI field descriptions Field 0–31 ECHD Description Error capture high data path. Captures the high word of the data path when errors are detected. 8.4.37 Memory data path read capture low (DDR_CAPTURE_DATA_LO) The memory data path read capture low register stores the low word of the read data path during error capture. Address: 2000h base + E24h offset = 2E24h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W ECLD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_CAPTURE_DATA_LO field descriptions Field 0–31 ECLD Description Error capture low data path. Captures the low word of the data path when errors are detected. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 319 DDR memory map/register definition 8.4.38 Memory data path read capture ECC (DDR_CAPTURE_ECC) The memory data path read capture ECC register stores the ECC syndrome bits that were on the data bus when an error was detected. Address: 2000h base + E28h offset = 2E28h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved ECE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_CAPTURE_ECC field descriptions Field 0–15 - 16–31 ECE Description This field is reserved. Reserved Error capture ECC. Captures the ECC bits on the data path whenever errors are detected. 16:23-8-bit ECC for the 32 bits in beats 0, 2, 4 and 6 in 32-bit bus mode 24:31-8-bit ECC for the 32 bits in beats 1, 3, 5, and 7 in 32-bit bus mode P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 320 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.39 Memory error detect (DDR_ERR_DETECT) The memory error detect register stores the detection bits for multiple memory errors, single- and multiple-bit ECC errors, and memory select errors. It is a read/write register. A bit can be cleared by writing a one to the bit. System software can determine the type of memory error by examining the contents of this register. If an error is disabled with ERR_DISABLE, the corresponding error is never detected or captured in ERR_DETECT. Address: 2000h base + E40h offset = 2E40h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MME R W w1c Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 321 DDR memory map/register definition Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MSE MBE R APE ACE SBE Reserved Reserved Reserved W w1c w1c w1c w1c w1c Reset 0 Field 0 MME 1–22 23 APE 24 ACE 25–27 28 MBE 29 SBE 30 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_ERR_DETECT field descriptions Description Multiple memory errors. This bit is cleared by software writing a 1. 0 Multiple memory errors of the same type were not detected. 1 Multiple memory errors of the same type were detected. This field is reserved. Reserved Address parity error. This bit is cleared by software writing a 1. 0 An address parity error has not been detected. 1 An address parity error has been detected. Automatic calibration error. This bit is cleared by software writing a 1. 0 An automatic calibration error has not been detected. 1 An automatic calibration error has been detected. This field is reserved. Reserved Multiple-bit error. This bit is cleared by software writing a 1. 0 A multiple-bit error has not been detected. 1 A multiple-bit error has been detected. Single-bit ECC error. This bit is cleared by software writing a 1. 0 The number of single-bit ECC errors detected has not crossed the threshold set in ERR_SBE[SBET]. 1 The number of single-bit ECC errors detected crossed the threshold set in ERR_SBE[SBET]. This field is reserved. Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 322 Freescale Semiconductor, Inc. Field 31 MSE Chapter 8 DDR Memory Controllers DDR_ERR_DETECT field descriptions (continued) Description Memory select error. This bit is cleared by software writing a 1. 0 A memory select error has not been detected. 1 A memory select error has been detected. 8.4.40 Memory error disable (DDR_ERR_DISABLE) The memory error disable register allows selective disabling of the DDR controller's error detection circuitry. Disabled errors are not detected or reported. Address: 2000h base + E44h offset = 2E44h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W Reserved SBED Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_ERR_DISABLE field descriptions Field 0–22 - 23 APED This field is reserved. Reserved Address parity error disable Description Table continues on the next page... APED ACED MBED Reserved MSED P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 323 DDR memory map/register definition DDR_ERR_DISABLE field descriptions (continued) Field 24 ACED 25–27 28 MBED 29 SBED 30 31 MSED Description 0 Address parity errors are detected if DDR_SDRAM_CFG_2[AP_EN] is set. They are reported if ERR_INT_EN[APEE] is set. 1 Address parity errors are not detected or reported. Automatic calibration error disable 0 Automatic calibration errors are enabled. 1 Automatic calibration errors are disabled. This field is reserved. Reserved Multiple-bit ECC error disable 0 Multiple-bit ECC errors are detected if DDR_SDRAM_CFG[ECC_EN] is set. They are reported if ERR_INT_EN[MBEE] is set. Note that non-correctable read errors cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and this error occurs, ERR_DISABLE[MBED] must be zero, and ERR_INT_EN[MBEE] and ECC_EN must be one to ensure that an interrupt is generated. 1 Multiple-bit ECC errors are not detected or reported. Single-bit ECC error disable 0 Single-bit ECC errors are enabled. 1 Single-bit ECC errors are disabled. This field is reserved. Reserved Memory select error disable 0 Memory select errors are enabled. 1 Memory select errors are disabled. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 324 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.41 Memory error interrupt enable (DDR_ERR_INT_EN) ACEE MBEE Reserved MSEE The memory error interrupt enable register enables ECC interrupts or memory select error interrupts. When an enabled interrupt condition occurs, the internal int signal is asserted to the programmable interrupt controller (PIC). Address: 2000h base + E48h offset = 2E48h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved APEE Reserved SBEE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_ERR_INT_EN field descriptions Field 0–22 23 APEE 24 ACEE 25–27 - This field is reserved. Reserved Address parity error interrupt enable Description 0 Address parity errors cannot generate interrupts. 1 Address parity errors generate interrupts. Automatic calibration error interrupt enable 0 Automatic calibration errors cannot generate interrupts. 1 Automatic calibration errors generate interrupts. This field is reserved. Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 325 DDR memory map/register definition DDR_ERR_INT_EN field descriptions (continued) Field 28 MBEE Description Multiple-bit ECC error interrupt enable. Note that non-correctable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and this error occurs, ERR_DISABLE[MBED] must be zero, and ERR_INT_EN[MBEE] and ECC_EN must be one to ensure that an interrupt is generated. 29 SBEE 30 31 MSEE 0 Multiple-bit ECC errors cannot generate interrupts. 1 Multiple-bit ECC errors generate interrupts. Single-bit ECC error interrupt enable 0 Single-bit ECC errors cannot generate interrupts. 1 Single-bit ECC errors generate interrupts. This field is reserved. Reserved Memory select error interrupt enable 0 Memory select errors do not cause interrupts. 1 Memory select errors generate interrupts. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 326 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.4.42 Memory error attributes capture (DDR_CAPTURE_ATTRIBUTES) The memory error attributes capture register sets attributes for errors including type, size, source, and others. Address: 2000h base + E4Ch offset = 2E4Ch Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Reserved R BNUM W TSIZ Reserved TSRC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W TTYP Reserved VLD Reset 0 Field 0 - 1–3 BNUM 4 5–7 TSIZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_CAPTURE_ATTRIBUTES field descriptions Description This field is reserved. Reserved Data beat number. Captures the double-word number for the detected error. Relevant only for ECC errors. This field is reserved. Reserved Transaction size for the error. Captures the transaction size in double words. Patterns not shown are reserved. 000 4 double words 001 1 double word 010 2 double words 011 3 double words Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 327 DDR memory map/register definition DDR_CAPTURE_ATTRIBUTES field descriptions (continued) Field 8–10 11–15 TSRC 16–17 - 18–19 TTYP 20–30 - Description This field is reserved. Reserved Source ID. Specifies the source device mastering the transaction. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Reserved PCI Express 2 PCI Express 1 Reserved Reserved USB 1 Reserved Security Reserved Reserved Boot sequencer eSDHC Reserved Reserved Reserved DMA controller (DMAC) Processor 0 (instruction) Processor 0 (data) Processor 1 (instruction) Processor 1 (data) USB 2 DMA Reserved Reserved eTSEC 1 eTSEC 2 eTSEC 3 Reserved Reserved Reserved Reserved Reserved This field is reserved. Reserved Transaction type for the error. 00 Reserved 01 Write 10 Read 11 Read-modify-write This field is reserved. Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 328 Freescale Semiconductor, Inc. Field 31 VLD Chapter 8 DDR Memory Controllers DDR_CAPTURE_ATTRIBUTES field descriptions (continued) Description Valid. Set as soon as valid information is captured in the error capture registers. 8.4.43 Memory error address capture (DDR_CAPTURE_ADDRESS) The memory error address capture register holds the 32 lsbs of a transaction when a DDR ECC error is detected. Address: 2000h base + E50h offset = 2E50h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W CADDR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_CAPTURE_ADDRESS field descriptions Field 0–31 CADDR Description Captured address. Captures the 32 lsbs of the transaction address when an error is detected. 8.4.44 Memory error extended address capture (DDR_CAPTURE_EXT_ADDRESS) The memory error extended address capture register holds the four most significant transaction bits when an error is detected. Address: 2000h base + E54h offset = 2E54h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved CEADDR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_CAPTURE_EXT_ADDRESS field descriptions Field 0–27 - This field is reserved. Reserved Description Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 329 Functional description DDR_CAPTURE_EXT_ADDRESS field descriptions (continued) Field 28–31 CEADDR Description Captured extended address. Captures the 4 msbs of the transaction address when an error is detected 8.4.45 Single-Bit ECC memory error management (DDR_ERR_SBE) The single-bit ECC memory error management register stores the threshold value for reporting single-bit errors and the number of single-bit errors counted since the last error report. When the counter field reaches the threshold, it wraps back to the reset value (0). If necessary, software must clear the counter after it has managed the error. Address: 2000h base + E58h offset = 2E58h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved SBET Reserved SBEC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDR_ERR_SBE field descriptions Field 0–7 - 8–15 SBET 16–23 - 24–31 SBEC Description This field is reserved. Reserved Single-bit error threshold. Establishes the number of single-bit errors that must be detected before an error condition is reported. This field is reserved. Reserved Single-bit error counter. Indicates the number of single-bit errors detected and corrected since the last error report. If single-bit error reporting is enabled, an error is reported and a regular or critical interrupt is generated when this value equals SBET. SBEC is automatically cleared when the threshold value is reached. 8.5 Functional description The DDR SDRAM controller controls processor and I/O interactions with system memory. It provides support for JEDEC-compliant DDR2 and DDR3 SDRAMs. The memory system allows a wide range of memory devices to be mapped to any arbitrary chip select, and support is provided for registered DIMMs and unbuffered DIMMs. However, P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 330 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers registered DIMMs cannot be mixed with unbuffered DIMMs. In addition, DDR3 DIMM module specifications allow for vendors to use mirrored DIMMs, where some address and bank address lines are mirrored on the DIMM. The figure below is a high-level block diagram of the DDR memory controller. Requests are received from the internal mastering device and the address is decoded to generate the physical bank, logical bank, row, and column addresses. The transaction is compared with values in the row open table to determine if the address maps to an open page. If the transaction does not map to an open page, an active command is issued. The memory interface supports the following configurations: • as many as two physical banks of 32-/40-bit wide memory • bank sizes up to 4 Gbytes Programmable parameters allow for a variety of memory organizations and timings. Optional error checking and correcting (ECC) protection is provided for the DDR SDRAM data bus. Using ECC, the DDR memory controller detects and corrects all single/double-bit errors within the data bus, and detects all errors within a nibble. The controller allows as many as 16 pages to be open simultaneously. The amount of time (in clock cycles) the pages remain open is programmable with DDR_SDRAM_INTERVAL[BSTOPRE]. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 331 Functional description Figure 8-53. DDR memory controller block diagram Read and write accesses to memory are burst oriented; accesses start at a selected location and continue for a programmed number of higher locations (4 or 8) in a programmed sequence. Accesses to closed pages start with the registration of an ACTIVE command followed by a READ or WRITE. (Accessing open pages does not require an ACTIVE command.) The address bits registered coincident with the activate command specifies the logical bank and row to be accessed. The address coincident with the READ or WRITE command specify the logical bank and starting column for the burst access. The data interface is source synchronous, meaning whatever sources the data also provides a clocking signal to synchronize data reception. These bidirectional data strobes (MDQS[0:3]+ MDQS[8]) are inputs to the controller during reads and outputs during writes. The DDR SDRAM specification requires the data strobe signals to be centered P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 332 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers within the data tenure during writes and to be offset by the controller to the center of the data tenure during reads. This delay is implemented in the controller for both reads and writes. When ECC is enabled, 1 clock cycle is added to the read path to check ECC and correct single-bit errors. ECC generation does not add a cycle to the write path. The address and command interface is also source synchronous, although 1/8 cycle adjustments are provided for adjusting the clock alignment. This figure shows an example of DDR SDRAM configuration with four logical banks. Figure 8-54. Typical dual data rate SDRAM internal organization This figure shows some typical signal connections. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 333 Functional description Figure 8-55. Typical DDR SDRAM interface signals Figure 8-56 shows an example DDR SDRAM configuration with two physical banks each comprised of four 8Mbyte x 8 DDR modules for a total of 128 Mbytes of system memory. One of the five modules is used for the memory's ECC checking function. Certain address and control lines may require buffering. Analysis of the device's AC timing specifications, desired memory operating frequency, capacitive loads, and board routing loads can assist the system designer in deciding signal buffering requirements. The DDR memory controller drives 16 address pins, but in this example the DDR SDRAM devices use only 12 bits. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 334 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Figure 8-56. Example 64-Mbyte DDR SDRAM configuration with ECC Error management explains how the DDR memory controller handles errors. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 335 Functional description 8.5.1 DDR SDRAM interface operation The DDR memory controller supports many different DDR SDRAM configurations. SDRAMs with different sizes can be used in the same system. Sixteen multiplexed address signals and three logical bank select signals support device densities from 32 Mbits to 8 Gbits. Two chip select (CS) signals support up to two DIMMs of memory. The DDR SDRAM physical banks can be built from standard memory modules or directly-attached memory devices. The data path to individual physical banks is up to 32-bits wide, 40 bits with ECC. The DDR memory controller supports physical bank sizes from 32 Mbytes to 4 Gbytes. The physical banks can be constructed using ×8, ×16, or ×32 memory devices. The memory densities supported are 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbit , 2 Gbits, 4 Gbits and 8Gbits.Five data mask (DM) signals provide byte selection for memory accesses. NOTE An 8-bit DDR SDRAM device has a DQM signal and eight data signals (DQ[0:7]). A 16-bit DDR SDRAM device has two DQM signals associated with specific halves of the 16 data signals (DQ[0:7] and DQ[8:15]). When ECC is enabled, all memory accesses are performed on double-word boundaries (that is, all DQM signals are set simultaneously). However, when ECC is disabled, the memory system uses the DQM signals for byte lane selection. The table below shows the DDR memory controller's relationships between data byte lane 0-3, MDM[0:3], MDQS[0:3], and MDQ[0:31] when DDR SDRAM memories are used with x8 or x16 devices. Table 8-58. Byte lane to data relationship Data byte lane 0 (MSB) 1 2 3 Data bus mask MDM[0] MDM[1] MDM[2] MDM[3] Data bus strobe MDQS[0] MDQS[1] MDQS[2] MDQS[3] Data bus MDQ[0:7] MDQ[8:15] MDQ[16:23] MDQ[24:31] P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 336 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 8.5.1.1 Supported DDR SDRAM organizations Although the DDR memory controller multiplexes row and column address bits onto 16 memory address signals and 3 logical bank select signals, a physical bank may be implemented with memory devices requiring fewer than 31 address bits. The physical bank may be configured to provide from 12 to 16 row address bits, plus 2 or 3 logical bank-select bits and from 8-11 column address bits. The following tables describe DDR SDRAM device configurations supported by the DDR memory controller. NOTE DDR SDRAM is limited to 30 total address bits. Table 8-59. Supported DDR2 SDRAM device configurations SDRAM device 256 Mbits 256 Mbits 512 Mbits 512 Mbits 1 Gbits 1 Gbits 2 Gbits 2 Gbits 4 Gbits 4 Gbits Device configuration Row x column x subbank bits 32-Bit bank size 32 Mbits x 8 13 x 10 x 2 128 Mbytes 16 Mbits x 16 13 x 9 x 2 64 Mbytes 64 Mbits x 8 14 x 10 x 2 256 Mbytes 32 Mbits x 16 13 x 10 x 2 128 Mbytes 128 Mbits x 8 14 x 10 x 3 512 Mbytes 64 Mbits x 16 13 x 10 x 3 256 Mbytes 256 Mbits x 8 15 x 10 x 3 1 Gbyte 128 Mbits x 16 14 x 10 x 3 512 Mbytes 512 Mbits x 8 15 x 11 x 3 2 Gbytes 256 Mbits x 16 15 x 10 x 3 1 Gbyte Two banks of memory 256 Mbytes 128 Mbytes 512 Mbytes 256 Mbytes 1 Gbyte 512 Mbytes 2 Gbytes 1 Gbyte 4 Gbytes 2 Gbytes Table 8-60. Supported DDR3 SDRAM device configurations (32-bit data) SDRAM device Device configuration 512 Mbits 512 Mbits 1 Gbits 1 Gbits 2 Gbits 2 Gbits 4 Gbits 4 Gbits 8 Gbits 8 Gbits 64 Mbits x 8 32 Mbits x 16 128 Mbits x 8 64 Mbits x 16 256 Mbits x 8 128 Mbits x 16 512 Mbits x 8 256 Mbits x 16 1 Gbit x 8 512 Mbits x 16 Row x column x sub-bank bits 32-bit bank size 13 x 10 x 3 256 Mbytes 12 x 10 x 2 128 Mbytes 14 x 10 x 3 512 Mbytes 13 x 10 x 3 256 Mbytes 15 x 10 x 3 1 Gbyte 14 x 10 x 3 512 Mbytes 16 x 10 x 3 2 Gbytes 15 x 10 x 3 1 Gbyte 16 x 11 x 3 4 Gbytes 16 x 10 x 3 2 Gbytes Two Banks of memory 512 Mbytes 256 Mbytes 1 Gbyte 512 Mbytes 2 Gbytes 1 Gbyte 4 Gbytes 2 Gbytes 8 Gbytes 4 Gbytes P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 337 Functional description If a transaction request is issued to the DDR memory controller and the address does not lie within any of the programmed address ranges for an enabled chip select, a memory select error is flagged. Errors are described in detail in Error management. Using a memory-polling algorithm at power-on reset or by querying the JEDEC serial presence detect capability of memory modules, system firmware uses the memoryboundary registers to configure the DDR memory controller to map the size of each bank in memory. The memory controller uses its bank map to assert the appropriate MCS_Bn signal for memory accesses according to the provided bank starting and ending addresses. The memory banks are not required to be mapped to a contiguous address space. 8.5.2 DDR SDRAM address multiplexing The following tables show the address bit encodings for each DDR SDRAM configuration. The address presented at the memory controller signals MA[15:0] use MA[15] as the msb and MA[0] as the lsb. Also, MA[10] is used as the auto-precharge bit in DDR2/DDR3 modes for reads and writes, so the column address can never use MA[10]. Table 8-61. DDR2/DDR3 Address multiplexing for 32-bit data bus with interleaving and partial array self-refresh disabled Row x Col 16 x MRA 10 x 3 S_B MBA MCA S_B 15 x MRA 10 x 3 S_B MBA MCA S_B 14 x MRA 10 x 3 S_B MBA MCA S_B ms Address from Core Master lsb b 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 34-3 012345678901234567890123 5 1 1 1 1 1 10 9 8 7 6 5 4 3 2 1 0 54321 210 9876543210 1 1 1 1 10 9 8 7 6 5 4 3 2 1 0 4321 210 9876543210 1 1 1 10 9 8 7 6 5 4 3 2 1 0 321 210 9876543210 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 338 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-61. DDR2/DDR3 Address multiplexing for 32-bit data bus with interleaving and partial array self-refresh disabled (continued) Row x Col 14 x MRA 10 x 2 S_B MBA MCA S_B 13 x MRA 10 x 3 S_B MBA MCA S_B 13 x MRA 10 x 2 S_B MBA MCA S_B 13 x 9 MRA x 2 S_B MBA MCA S_B ms Address from Core Master lsb b 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 34-3 012345678901234567890123 5 1 1 11 1 9 8 7 6 5 4 3 2 1 0 32 0 10 9876543210 1 1 10 9 8 7 6 5 4 3 2 1 0 21 210 9876543210 1 11 1 9 8 7 6 5 4 3 2 1 0 2 0 10 9876543210 12 1 1 9 8 7 6 5 4 3 2 1 0 10 10 876543210 Table 8-62. DDR2/DDR3 Address multiplexing for 16-bit data bus Row m Address from Core Master ls x s b b Col 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 01234567890123456789012345 15 M xR 10 A xS 3_ B 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M 210 B A M 9876543210 C A S _ B Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 339 Functional description Table 8-62. DDR2/DDR3 Address multiplexing for 16-bit data bus (continued) Row m Address from Core Master ls x s b b Col 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 01234567890123456789012345 14 M xR 10 A xS 3_ B 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M 210 B A M 9876543210 C A S _ B 14 M xR 10 A xS 2_ B 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M 10 B A M 9876543210 C A S _ B 13 M xR 10 A xS 3_ B 12 11 10 9 8 7 6 5 4 3 2 1 0 M 210 B A M 9876543210 C A S _ B Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 340 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-62. DDR2/DDR3 Address multiplexing for 16-bit data bus (continued) Row m Address from Core Master ls x s b b Col 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 01234567890123456789012345 13 M xR 10 A xS 2_ B 12 11 10 9 8 7 6 5 4 3 2 1 0 M 10 B A M 9876543210 C A S _ B 13 M xR 9A xS 2_ B 12 11 10 9 8 7 6 5 4 3 2 1 0 M 10 B A M 876543210 C A S _ B Chip select interleaving is supported for the memory controller, and is programmed in DDR_SDRAM_CFG[BA_INTLV_CTL]. Interleaving is supported between chip selects 0 and 1. When interleaving is enabled, the chip selects being interleaved must use the same size of memory. One extra bit in the address decode is used for the interleaving to determine which chip select to access. The following tables show examples of interleaving between chip selects. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 341 Functional description Table 8-63. Example of address multiplexing for 32-bit data bus interleaving between two banks with partial array self refresh disabled Row m Address from Core Master ls x s b b Col 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4- 3 5 14 M xR 10 A x 3 S_ B M B A 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C S S EL 210 M 9876543210 C A S_ B 14 M xR 10 A x 2 S_ B M B A 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C S S EL 10 M 9876543210 C A S_ B 13 M xR 10 A x 3 S_ B M B A 12 11 10 9 8 7 6 5 4 3 2 1 0 C S S EL 210 M 9876543210 C A S_ B Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 342 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-63. Example of address multiplexing for 32-bit data bus interleaving between two banks with partial array self refresh disabled (continued) Row m Address from Core Master ls x s b b Col 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4- 3 5 13 M xR 10 A x 2 S_ B M B A 12 11 10 9 8 7 6 5 4 3 2 1 0 C S S EL 10 M 9876543210 C A S_ B Partial array self-refresh (PASR) can be enabled for any chip select using the CSn_CONFIG_2[PASR_CFG] fields. If PASR is enabled for a given chip select, then the sub-bank and row decode is swapped, and the sub-bank is decoded as the most significant portion of the DRAM address, as shown in the table below. If chip select interleaving and PASR are enabled for a chip select, then the interleaved chip select bit is placed immediately to the left of the column decode, as shown in Table 8-65. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 343 Functional description Table 8-64. Address multiplexing with partial array self refresh Enabled Row m Address from Core Master ls x s b b Col 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4- 3 5 16 M xR 10 A x 3 S _ B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M 210 B A M 9876543210 C A S _ B 15 M xR 10 A x 3 S _ B 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M 210 B A M 9876543210 C A S _ B 14 M xR 10 A x 3 S _ B 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M 210 B A M 9876543210 C A S _ B Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 344 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-64. Address multiplexing with partial array self refresh Enabled (continued) Row m Address from Core Master ls x s b b Col 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4- 3 5 14 M xR 10 A x 2 S _ B 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M 10 B A M 9876543210 C A S _ B 13 M xR 10 A x 3 S _ B 12 11 10 9 8 7 6 5 4 3 2 1 0 M 210 B A M 9876543210 C A S _ B 13 M xR 10 A x 2 S _ B 12 11 10 9 8 7 6 5 4 3 2 1 0 M 10 B A M 9876543210 C A S _ B Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 345 Functional description Table 8-64. Address multiplexing with partial array self refresh Enabled (continued) Row m Address from Core Master ls x s b b Col 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4- 3 5 13 M xR 9A x 2 S _ B 12 11 10 9 8 7 6 5 4 3 2 1 0 M 10 B A M 876543210 C A S _ B Table 8-65. Example of address multiplexing for 32 -bit data bus interleaving between two banks with partial array self refresh enabled Row x Col 14 x MRAS 10 _B x3 MBA MCAS _B 14 x MRAS 10 _B x 2 MBA MCAS _B 13 x MRAS 10 _B x 3 MBA MCAS _B ms Address from Core Master lsb b 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 23 2 2 2 2 2 2 3 3 3 3 34-35 01234567890 1 2 4567890123 11 11987654321 32 10 210 0 CS SE L 9876543210 11 11987654321 32 10 10 0 CS SE L 9876543210 1 11987654321 2 10 210 0 CS SE L 9876543210 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 346 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-65. Example of address multiplexing for 32 -bit data bus interleaving between two banks with partial array self refresh enabled (continued) Row x Col ms Address from Core Master lsb b 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 23 2 2 2 2 2 2 3 3 3 3 34-35 01234567890 1 2 4567890123 13 x MRAS 10 _B x 2 MBA 1 11987654321 2 10 10 0 CS SE L MCAS _B 9876543210 8.5.3 JEDEC standard DDR SDRAM interface commands The following section describes the commands and timings the controller uses when operating in DDR3 or DDR2 modes. All read or write accesses to DDR SDRAM are performed by the DDR memory controller using JEDEC standard DDR SDRAM interface commands. The SDRAM device samples command and address inputs on rising edges of the memory clock; data is sampled using both the rising and falling edges of DQS. Data read from the DDR SDRAM is also sampled on both edges of DQS. The following DDR SDRAM interface commands (summarized in the table below) are provided by the DDR controller. All actions for these commands are described from the perspective of the SDRAM device. • Row activate-Latches row address and initiates memory read of that row. Row data is latched in SDRAM sense amplifiers and must be restored by a precharge command before another row activate occurs. • Precharge-Restores data from the sense amplifiers to the appropriate row. Also initializes the sense amplifiers in preparation for reading another row in the memory array (performing another activate command). Precharge must occur after read or write, if the row address changes on the next open page mode access. • Read-Latches column address and transfers data from the selected sense amplifier to the output buffer as determined by the column address. During each succeeding clock edge, additional data is driven without additional read commands. The amount of data transferred is determined by the burst size. • Write-Latches column address and transfers data from the data pins to the selected sense amplifier as determined by the column address. During each succeeding clock edge, additional data is transferred to the sense amplifiers from the data pins without P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 347 Functional description additional write commands. The amount of data transferred is determined by the data masks and the burst size. • Refresh (similar to MCAS_B before MRAS_B)-Causes a row to be read in all logical banks (JEDEC SDRAM) as determined by the refresh row address counter. This refresh row address counter is internal to the SDRAM. After being read, the row is automatically rewritten in the memory array. All logical banks must be in a precharged state before executing a refresh. The memory controller also supports posted refreshes, where several refreshes may be executed at once, and the refresh interval may be extended. • Mode register set (for configuration)-Allows setting of DDR SDRAM options. These options are: MCAS_B latency, additive latency (for DDR2/DDR3), write recovery (for DDR2/DDR3), burst type, and burst length. MCAS_B latency may be chosen as provided by the preferred SDRAM. Burst type is always sequential. This memory controller supports a burst length of 4 and 8. A burst length of 8 is supported for DDR3 memory only. For DDR2 in 32-bit bus mode, all 32-byte burst accesses from the platform are split into two 16-byte (that is, 4-beat) accesses to the SDRAMs in the memory controller. The mode register set command is performed by the DDR memory controller during system initialization. Parameters such as mode register data, MCAS_B latency, burst length, and burst type, are set by software in DDR_SDRAM_MODE[SDMODE] and transferred to the SDRAM array by the DDR memory controller after DDR_SDRAM_CFG[MEM_EN] is set. If DDR_SDRAM_CFG[BI] is set to bypass the automatic initialization, then the MODE registers can be configured through software through use of the DDR_SDRAM_MD_CNTL register. • Self refresh (for long periods of standby)-Used when the device is in standby for very long periods of time. Automatically generates internal refresh cycles to keep the data in all memory banks refreshed. Before execution of this command, the DDR controller places all logical banks in a precharged state. Table 8-66. DDR SDRAM command table Operation CKE CKE MCS MRAS MCAS MWE Prev. Current _B _B _B _B MBA Activate H H L L H H Logical bank select Precharge select H H logical bank L L H L Logical bank select Precharge all logical H H banks L L H L X Read H H L H L H Logical bank select Read with auto- H H precharge L H L H Logical bank select Write H H L H L L Logical bank select MA10 MA Row L Row X H X L Column H Column L Column Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 348 Freescale Semiconductor, Inc. Operation Write with autoprecharge Mode register set Auto refresh Self refresh Chapter 8 DDR Memory Controllers Table 8-66. DDR SDRAM command table (continued) CKE CKE MCS MRAS MCAS MWE Prev. Current _B _B _B _B MBA H H L H L L Logical bank select MA10 MA H Column H H H H H L L L L L Opcode L L L H X L L L H X Opcode Opcode and mode X X X X 8.5.4 DDR SDRAM interface timing The DDR memory controller supports four- (or eight-) beat bursts to SDRAM. For single-beat reads, the DDR memory controller performs a four- (or eight-) beat burst read, but ignores the last three (or seven) beats. Single-beat writes are performed by masking the last three (or seven) beats of the four- (or eight-) beat burst using the data mask MDM[0:3]. If ECC is disabled, writes smaller than double words are performed by appropriately activating the data mask. If ECC is enabled, the controller performs a readmodify write. NOTE If a second read or write is pending, reads shorter than four beats are not terminated early even if some data is irrelevant. To accommodate available memory technologies across a wide spectrum of operating frequencies, the DDR memory controller allows the setting of the intervals defined in the following table with granularity of one memory clock cycle. Table 8-67. DDR SDRAM interface timing intervals Timing intervals ACTTOACT ACTTOPRE ACTTORW BSTOPRE CASLAT Definition The number of clock cycles from a bank-activate command until another bank-activate command within a physical bank. This interval is listed in the AC specifications of the SDRAM as tRRD. The number of clock cycles from an activate command until a precharge command is allowed. This interval is listed in the AC specifications of the SDRAM as tRAS. The number of clock cycles from an activate command until a read or write command is allowed. This interval is listed in the AC specifications of the SDRAM as tRCD. The number of clock cycles to maintain a page open after an access. The page open duration counter is reloaded with BSTOPRE each time the page is accessed (including page hits). When the counter expires, the open page is closed with an SDRAM precharge bank command as soon as possible. Used in conjunction with additive latency to obtain the READ latency. The number of clock cycles between the registration of a READ command by the SDRAM and the availability of the first piece of output data. If a READ command is registered at clock edge n, and the read latency is m clocks, the data is available nominally coincident with clock edge n + m. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 349 Functional description Table 8-67. DDR SDRAM interface timing intervals (continued) Timing intervals PRETOACT REFINT REFREC WR_DATA_DELAY WRREC WRTORD Definition The number of clock cycles from a precharge command until an activate or a refresh command is allowed. This interval is listed in the AC specifications of the SDRAM as tRP. Refresh interval. Represents the number of memory bus clock cycles between refresh cycles. Depending on DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each SDRAM bank during each refresh cycle. The value of REFINT depends on the specific SDRAMs used and the frequency of the interface as tRP. The number of clock cycles from the refresh command until an activate command is allowed. This can be calculated by referring to the AC specification of the SDRAM device. The AC specification indicates a maximum refresh-to-activate interval in nanoseconds. Provides different options for the timing between a write command and the write data strobe. This allows write data to be sent later than the nominal time to meet the SDRAM timing requirement between the registration of a write command and the reception of a data strobe associated with the write command. The specification dictates that the data strobe may not be received earlier than 75% of a cycle, or later than 125% of a cycle, from the registration of a write command. This parameter is not defined in the SDRAM specification. It is implementation-specific, defined for the DDR memory controller in TIMING_CFG_2. The number of clock cycles from the last beat of a write until a precharge command is allowed. This interval, write recovery time, is listed in the AC specifications of the SDRAM as tWR. Last write pair to read command. Controls the number of clock cycles from the last write data pair to the subsequent read command to the same bank as tWTR. The value of the above parameters (in whole clock cycles) must be set by boot code at system start-up (as described in DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0), DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1), DDR SDRAM timing configuration 2 (DDR_TIMING_CFG_2), and DDR SDRAM timing configuration 3 (DDR_TIMING_CFG_3)) and be kept in the DDR memory controller configuration register space. The following figures show SDRAM timing for various types of accesses. System software is responsible (at reset) for optimally configuring SDRAM timing parameters. The programmable timing parameters apply to both read and write timing configuration. The configuration process must be completed and the DDR SDRAM initialized before any accesses to SDRAM are attempted. See Figure 8-57 for a single-beat read operation, Figure 8-58 for a single-beat write operation, and Figure 8-59 for a double-word write operation. Note that all signal transitions occur on the rising edge of the memory bus clock and that single-beat read operations are identical to burst-reads. These figures assume the CLK_ADJUST is set to 1/2 DRAM cycle, an additive latency of 0 DRAM cycles is used, and the write latency is 1 DRAM cycle. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 350 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Figure 8-57. DDR SDRAM burst read timing-ACTTORW = 3, MCAS Latency = 2 Figure 8-58. DDR SDRAM single-beat (double word) write timing-ACTTORW = 3 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 351 Functional description Figure 8-59. DDR SDRAM 4-beat burst write timing-ACTTORW = 4 8.5.5 DDR SDRAM registered DIMM mode To reduce loading, registered DIMMs latch the DDR SDRAM control signals internally before using them to access the array. Setting DDR_SDRAM_CFG[RD_EN] compensates for this delay on the DIMMs' control bus by delaying the data and data mask writes (on SDRAM buses) by an extra SDRAM clock cycle. NOTE Application system board must assert the reset signal on DDR memory devices until software is able to program the DDR memory controller configuration registers, and must deassert the reset signal on DDR memory devices before DDR_SDRAM_CFG[MEM_EN] is set. This ensures that the DDR memory devices are held in reset until a stable clock is provided and, further, that a stable clock is provided before memory devices are released from reset. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 352 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers The figure below shows the registered DDR SDRAM DIMM burst write timing. Figure 8-60. Registered DDR SDRAM DIMM burst write timing 8.5.6 DDR SDRAM write timing adjustments The DDR memory controller facilitates system design flexibility by providing a write timing adjustment parameter, write data delay, (TIMING_CFG_2[WR_DATA_DELAY]) for data and DQS. The DDR SDRAM specification requires DQS be received no sooner than 75% of an SDRAM clock period-and no later than 125% of a clock period-from the capturing clock edge of the command/address at the SDRAM. The WR_DATA_DELAY parameter may be used to meet this timing requirement for a variety of system configurations, ranging from a system with one DIMM to a fully populated system with two DIMMs. TIMING_CFG_2[WR_DATA_DELAY] specifies how much to delay the launching of DQS and data from the first clock edge occurring. The delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0. The figure below shows the use of the WR_DATA_DELAY parameter. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 353 Functional description Figure 8-61. Write timing adjustments example for write latency = 1 8.5.7 DDR SDRAM refresh The DDR memory controller supports auto-refresh and self-refresh. Auto-refresh is used during normal operation and is controlled by the DDR_SDRAM_INTERVAL[REFINT] value; self-refresh is used only when the DDR memory controller is set to enter a sleep power management state. The REFINT value, which represents the number of memory bus clock cycles between refresh cycles, must allow for possible outstanding transactions to complete before a refresh request is sent to the memory after the REFINT value is reached. If a memory transaction is in progress when the refresh interval is reached, the refresh cycle waits for the transaction to complete. In the worst case, the refresh cycle must wait the number of bus clock cycles required by the longest programmed access. To ensure that the latency caused by a memory transaction does not violate the device refresh period, it is recommended that the programmed value of REFINT be less than that required by the SDRAM. When a refresh cycle is required, the DDR memory controller does the following: 1. Completes all current memory requests. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 354 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers 2. Closes all open pages with a PRECHARGE-ALL command to each DDR SDRAM bank with an open page (as indicated by the row open table). 3. Issues one or more auto-refresh commands to each DDR SDRAM bank (as identified by its chip select) to refresh one row in each logical bank of the selected physical bank. The auto-refresh commands are staggered across the two possible banks to reduce the system's instantaneous power requirements. Three sets of auto refresh commands are issued on consecutive cycles when the memory is populated with one DIMMs. The initial PRECHARGE-ALL commands are also staggered in three groups for convenience. It is important to note that when entering self-refresh mode, only one refresh command is issued simultaneously to all physical banks. For this entire refresh sequence, no cycle optimization occurs for the usual case where fewer than two banks are installed. After the refresh sequence completes, any pending memory request is initiated after an inactive period specified by TIMING_CFG_1 [REFREC] and TIMING_CFG_3[EXT_REFREC]. In addition, posted refreshes are supported to allow the refresh interval to be set to a larger value. 8.5.7.1 DDR SDRAM refresh timing Refresh timing for the DDR SDRAM is controlled by the programmable timing parameter TIMING_CFG_1 [REFREC], which specifies the number of memory bus clock cycles from the refresh command until a logical bank activate command is allowed. The DDR memory controller implements bank staggering for refreshes, as shown in the figure below (TIMING_CFG_1 [REFREC] = 10 in this example). Figure 8-62. DDR SDRAM bank staggered auto refresh timing P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 355 Functional description System software is responsible for optimal configuration of TIMING_CFG_1 [REFREC] and TIMING_CFG_3[EXT_REFREC] at reset. Configuration must be completed before DDR SDRAM accesses are attempted. 8.5.7.2 DDR SDRAM refresh and power-saving modes In full-on mode, the DDR memory controller supplies the normal auto refresh to SDRAM. In sleep mode, the DDR memory controller can be configured to take advantage of selfrefreshing SDRAMs or to provide no refresh support. Self-refresh support is enabled with the SREN memory control parameter. The table below summarizes the refresh types available in each power-saving mode. Table 8-68. DDR SDRAM power-saving modes refresh configuration Sleep Power saving mode Self None Refresh type SREN 1 - Note that in the absence of refresh support, system software must preserve DDR SDRAM data (such as by copying the data to disk) before entering the power-saving mode. The dynamic power-saving mode uses the CKE DDR SDRAM pin to dynamically power down when there is no system memory activity. The CKE pin is negated when both of the following conditions are met: • No memory refreshes are scheduled • No memory accesses are scheduled CKE is reasserted when a new access or refresh is scheduled or the dynamic power mode is disabled. This mode is controlled with DDR_SDRAM_CFG[DYN_PWR_MGMT]. Dynamic power management mode offers tight control of the memory system's power consumption by trading power for performance through the use of CKE. Powering up the DDR SDRAM when a new memory reference is scheduled causes an access latency penalty, depending on whether active or precharge powerdown is used, along with the settings of TIMING_CFG_0[ACT_PD_EXIT] and TIMING_CFG_0[PRE_PD_EXIT]. For example, a penalty of 1 cycle is shown in the following figure. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 356 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Figure 8-63. DDR SDRAM power-down mode 8.5.7.2.1 Self-refresh in sleep mode The entry and exit timing for self-refreshing SDRAMs is shown in the following figures. Figure 8-64. DDR SDRAM self-refresh entry timing P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 357 Functional description Figure 8-65. DDR2 SDRAM self-refresh exit timing Figure 8-66. DDR3 SDRAM self-refresh exit timing NOTE Deep sleep mode is not supported for DDR3 registered DIMMS. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 358 Freescale Semiconductor, Inc. 8.5.8 DDR data beat ordering Chapter 8 DDR Memory Controllers Transfers to and from memory are always performed in four- or eight-beat bursts . For transfer sizes other than four or eight beats, the data transfers are still operated as four- or eight-beat bursts.If ECC is enabled and either the access is not double-word aligned or the size is not a multiple of a double word, a full read-modify-write is performed for a write to SDRAM. If ECC is disabled or both the access is double-word aligned with a size that is a multiple of a double word, the data masks MDM[0:3] and MDM[8] The DDR memory controller also uses data masks to prevent all unintended full double words from writing to SDRAM. For example, if a write transaction is desired with a size of one double word (8 bytes), then the second, third, and fourth beats of data are not written to DRAM, as the width of the data bus is 64 bits. The table below lists the data beat sequencing to and from the DDR SDRAM and the data queues for each of the possible transfer sizes with each of the possible starting doubleword offsets. All underlined double-word offsets are valid for the transaction. Transfer Size 1 double word 2 double words 3 double words Table 8-69. Memory controller-data beat ordering Starting double-word offset 0 1 2 3 0 1 2 0 1 Double-word sequence1 to/from DRAM and queues 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-2-3-0 2-3-0-1 0-1-2-3 1-2-3-0 1. All underlined double-word offsets are valid for the transaction. All writes are aligned to double-word 0 for DDR3 memories. 8.5.9 Page mode and logical bank retention The DDR memory controller supports an open/closed page mode with an allowable open page for each logical bank of DRAM used. In closed page mode for DDR SDRAMs, the DDR memory controller uses the SDRAM auto-precharge feature, which allows the controller to indicate that the page must be automatically closed by the DDR SDRAM after the READ or WRITE access. This is performed using MA[10] of the address during the COMMAND phase of the access to P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 359 Functional description enable auto-precharge. Auto-precharge is non-persistent in that it is either enabled or disabled for each individual READ or WRITE command. It can, however, be enabled or disabled separately for each chip select. When the DDR memory controller operates in open page mode, it retains the currently active SDRAM page by not issuing a precharge command. The page remains open until one of the following conditions occurs: • Refresh interval is met. • The user-programmable DDR_SDRAM_INTERVAL[BSTOPRE] value is exceeded. • There is a logical bank row collision with another transaction that must be issued. Page mode can dramatically reduce access latencies for page hits. Depending on the memory system design and timing parameters, using page mode can save two to three clock cycles for subsequent burst accesses that hit in an active page. Also, better performance can be obtained using more banks, especially in systems which use many different channels. Page mode is disabled by clearing DDR_SDRAM_INTERVAL[BSTOPRE] or setting CSn_CONFIG[AP_nEN]. 8.5.10 Error checking and correcting (ECC) The DDR memory controller supports error checking and correcting (ECC) for the data path between the core master and system memory. The memory detects all double-bit errors, detects all multi-bit errors within a nibble, and corrects all single-bit errors. Other errors may be detected, but are not guaranteed to be corrected or detected. Multi-bit errors are always reported when error reporting is enabled. When a single-bit error occurs, the single-bit error counter register is incremented, and its value compared to the single-bit error trigger register. An error is reported when these values are equal. The single-bit error registers can be programmed such that minor memory faults are corrected and ignored, but a catastrophic memory failure generates an interrupt. For writes that are smaller than 32 bits, the DDR memory controller performs a doubleword read from system memory of the address for the write (checking for errors), and merges the write data with the data read from memory. Then, a new ECC code is generated for the merged double word. The data and ECC code is then written to memory. If a multi-bit error is detected on the read, the transaction completes the readmodify-write to keep the DDR memory controller from hanging. However, the corrupt data is masked on the write, so the original contents in SDRAM remain unchanged. The syndrome encodings for the ECC code are shown in the following table. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 360 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-70. DDR SDRAM ECC syndrome encoding (check bits) Check bit 0 1 2 3 4 5 6 7 0 • 1 • 2 • Syndrome bit 3 4 5 • • • 6 • 7 • 8.5.11 Error management The DDR memory controller detects four different kinds of errors: training, single-bit, multi-bit, and memory select errors. The following discussion assumes all the relevant error detection, correction, and reporting functions are enabled as described in Memory error interrupt enable (DDR_ERR_INT_EN), Memory error disable (DDR_ERR_DISABLE), and Memory error detect (DDR_ERR_DETECT). Single-bit errors are counted and reported based on the ERR_SBE value. When a singlebit error is detected, the DDR memory controller does the following: • Corrects the data • Increments the single-bit error counter ERR_SBE[SBEC] • Generates an interrupt if the counter value ERR_SBE[SBEC] equals the programmable threshold ERR_SBE[SBET] • Completes the transaction normally If a multi-bit error is detected for a read, the DDR memory controller logs the error and generates the interrupt. Another error the DDR memory controller detects is a memory select error, which causes the DDR memory controller to log the error and generate an interrupt (if enabled, as described in Memory error detect (DDR_ERR_DETECT)). This error is detected if the address from the memory request does not fall into any of the enabled, programmed chip select address ranges. For all memory select errors, the DDR memory controller does not issue any transactions onto the pins after the first read has returned data strobes. If the DDR memory controller is not using sample points, then a dummy transaction is issued to DDR SDRAM with the first enabled chip select. In this case, the source port on the pins is forced to 0x1F to show the transaction is not real. The P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 361 Initialization/application information table below shows the errors with their descriptions. The final error the memory controller detects is the automatic calibration error. This error is set if the memory controller detects an error during its training sequence. Table 8-71. Memory controller errors Category Notification Access Error Error Single-bit ECC threshold Multi-bit ECC error Memory select error Descriptions The number of ECC errors has reached the threshold specified in the ERR_SBE. A multi-bit ECC error is detected during a read, or read-modify-write memory operation. Read, or write, address does not fall within the address range of any of the memory banks. Action Detect Register Regular or critical The error control interrupt (if enabled) register only logs Machine check for e500 core initiated read versus write, not full type reads (if enabled), or regular/critical interrupt (if enabled) 8.6 Initialization/application information System software must configure the DDR memory controller, using a memory polling algorithm at system start-up, to correctly map the size of each bank in memory. Then, the DDR memory controller uses its bank map to assert the appropriate MCSn signal for memory accesses according to the provided bank depths. System software must also configure the DDR memory controller at system start-up to appropriately multiplex the row and column address bits for each bank. Refer to row-address configuration in Chip select n configuration (DDR_CSn_CONFIG). Address multiplexing occurs according to these configuration bits. At system reset, initialization software (boot code) must set up the programmable parameters in the memory interface configuration registers. See DDR memory map/ register definition for more detailed descriptions of the configuration registers. These parameters are shown in the following table. Table 8-72. Memory interface configuration register initialization parameters Name Description Parameter CSn_BNDS Chip select memory bounds SAn EAn Table continues on the next page... Section/ page Chip select n memory bounds (DDR_CSn_B NDS) P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 362 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-72. Memory interface configuration register initialization parameters (continued) Name CSn_CONFIG CSn_CONFIG_2 TIMING_CFG_3 TIMING_CFG_0 TIMING_CFG_1 TIMING_CFG_2 DDR_SDRAM_CFG Description Chip select configuration Chip select configuration 2 Extended timing parameters for fields in TIMING_CFG_1 Timing configuration Timing configuration Timing configuration Control configuration Parameter Section/ page CS_n_EN AP_n_EN ODT_RD_CFG BA_BITS_CS_n ROW_BITS_CS_n COL_BITS_CS_n Chip select n configuration (DDR_CSn_C ONFIG) ODT_WR_CFG PASR_CFG Chip select n configuration 2 (DDR_CSn_C ONFIG_2) EXT_REFREC EXT_ACTTOPRE EXT_CASLAT CNTL_ADJ DDR SDRAM timing configuration 3 (DDR_TIMIN G_CFG_3) RWT WRT RRT WWT ACT_PD_EXIT PRE_PD_EXIT ODT_PD_EXIT MRS_CYC DDR SDRAM timing configuration 0 (DDR_TIMIN G_CFG_0) PRETOACT ACTTOPRE ACTTORW CASLAT REFREC WRREC ACTTOACT WRTORD DDR SDRAM timing configuration 1 (DDR_TIMIN G_CFG_1) ADD_LAT CPO WR_LAT RD_TO_PRE WR_DATA_DELAY DDR SDRAM CKE_PLS timing configuration FOUR_ACT 2 (DDR_TIMIN G_CFG_2) SREN ECC_EN RD_EN SDRAM_TYPE DYN_PWR 2T_EN 3T_EN BA_INTLV_CTL x32_EN HSE DDR SDRAM control configuration (DDR_DDR_ SDRAM_CFG ) 8_BE BI DBW MEM_EN MEM_HALT PCHB8 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 363 Initialization/application information Table 8-72. Memory interface configuration register initialization parameters (continued) Name DDR_SDRAM_CFG_2 Description Control configuration Parameter SR_IE DLL_RST_DIS DQS_CFG ODT_CFG FRC_SR NUM_PR AP_EN D_INIT RCW_EN MD_EN Section/ page DDR SDRAM control configuration 2 (DDR_DDR_ SDRAM_CFG _2) DDR_SDRAM_MODE Mode configuration DDR_SDRAM_MODE_2 Mode configuration ESDMODE SDMODE ESDMODE2 ESDMODE3 DDR_SDRAM_INTERVAL Interval configuration REFINT BSTOPRE DDR_DATA_INIT Data initialization configuration register INIT_VALUE DDR_SDRAM_CLK_CNTL Clock adjust CLK_ADJUST DDR_INIT_ADDR Initialization address INIT_ADDR TIMING_CFG_4 Timing configuration RWT WRT RRT WWT DLL_LOCK DDR SDRAM mode configuration (DDR_DDR_ SDRAM_MO DE) DDR SDRAM mode configuration 2 (DDR_DDR_ SDRAM_MO DE_2) DDR SDRAM interval configuration (DDR_DDR_ SDRAM_INT ERVAL) DDR SDRAM data initialization (DDR_DDR_ DATA_INIT) DDR SDRAM clock control (DDR_DDR_ SDRAM_CLK _CNTL) DDR training initialization address (DDR_DDR_I NIT_ADDR) DDR SDRAM timing configuration 4 (DDR_TIMIN G_CFG_4) Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 364 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-72. Memory interface configuration register initialization parameters (continued) Name TIMING_CFG_5 Description Timing configuration DDR_ZQ_CNTL ZQ calibration control DDR_WRLVL_CNTL Write leveling control DDR_WRLVL_CNTL_2 Write leveling control DDR_WRLVL_CNTL_3 Write leveling control DDR_SR_CNTR Self refresh control Parameter RODT_ON RODT_OFF WODT_ON WODT_OFF ZQ_EN ZQINIT ZQOPER ZQCS WRLVL_EN WRLVL_MRD WRLVL_ODTEN WRLVL_DQSEN WRLVL_SMPL WRLVL_WLR WRLVL_START WRLVL_START_1 WRLVL_START_2 WRLVL_START_3 WRLVL_START_4 WRLVL_START_5 WRLVL_START_6 WRLVL_START_7 WRLVL_START_8 SR_IT DDR_SDRAM_RCW_1 Register control words configuration RCW0 RCW1 RCW2 RCW3 RCW4 RCW5 RCW6 RCW7 Section/ page DDR SDRAM timing configuration 5 (DDR_TIMIN G_CFG_5) DDR ZQ calibration control (DDR_DDR_ ZQ_CNTL) DDR write leveling control (DDR_DDR_ WRLVL_CNT L) DDR write leveling control 2 (DDR_DDR_ WRLVL_CNT L_2) DDR write leveling control 3 (DDR_DDR_ WRLVL_CNT L_3) DDR Self Refresh Counter (DDR_DDR_ SR_CNTR) DDR Register Control Words 1 (DDR_DDR_ SDRAM_RC W_1) Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 365 Initialization/application information Table 8-72. Memory interface configuration register initialization parameters (continued) Name DDR_SDRAM_RCW_2 DDRCDR_1 DDRCDR_2 DDR_INIT_EXT_ADDR Description Parameter Register control words configuration RCW8 RCW9 RCW10 RCW11 RCW12 RCW13 RCW14 RCW15 Driver control DHC_EN ODT DSO_C_EN DSO_D_EN Driver control DSO_CLK_EN DSO_CLKPZ DSO_CLKNZ ODT Extended initialization address UIA INIT_EXT_ADDR DSO_CPZ DSO_CNZ DSO_DPZ DSO_DNZ Section/ page DDR Register Control Words 2 (DDR_DDR_ SDRAM_RC W_2) DDR Control Driver Register 1 (DDR_DDRC DR_1) DDR Control Driver Register 2 (DDR_DDRC DR_2) DDR training initialization extended address (DDR_DDR_I NIT_EXT_AD DR) 8.6.1 Programming differences between memory types Depending on the memory type used, certain fields must be programmed differently. The table below illustrates the differences in certain fields for different memory types. Note that this table does not list all fields that must be programmed. Table 8-73. Programming differences between memory types Parameter APn_EN Description Chip Select n Auto precharge enable Differences DDR2/DDR3 Can be used to place chip select n in auto precharge mode See also: Chip select n configuration (DDR_CSn_CONFIG) Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 366 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-73. Programming differences between memory types (continued) Parameter ODT_RD_CFG ODT_WR_CFG ODT_PD_EXIT PRETOACT ACTTOPRE ACTTORW CASLAT REFREC WRREC Description Chip Select ODT read configuration Chip Select ODT write configuration ODT powerdown exit Precharge to activate timing Activate to precharge timing Activate to read/write timing CAS latency Refresh recovery Write Recovery Differences DDR2/DDR3 Can be enabled to assert ODT if desired. This could be set differently depending on system topology. However, systems with only 1 chip select will typically not use ODT when issuing reads to the memory. See also: Chip select n configuration (DDR_CSn_CONFIG) DDR2/DDR3 Can be enabled to assert ODT if desired. This could be set differently depending on system topology. However, ODT is typically set to assert for the chip select that is getting written to (value would be set to 001). See also: Chip select n configuration (DDR_CSn_CONFIG) DDR2 Should be set according to the DDR2 specifications for the memory used. The JEDEC parameter this applies to is tAXPD. DDR3 Should be set to 0001 for DDR3. The powerdown times (tXP and tXPDLL) required for DDR3 are controlled via TIMING_CFG_0[ACT_PD_EXIT] and TIMING_CFG_0[PRE_PD_EXIT]. See also: DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) DDR2/DDR3 Should be set according to the specifications for the memory used (tRP) See also: DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1) DDR2/DDR3 Should be set, along with the Extended Activate to Precharge Timing, according to the specifications for the memory used (tRAS) See also: DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) DDR2/DDR3 Should be set according to the specifications for the memory used (tRCD) See also: DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) DDR2/DDR3 Should be set, along with the Extended CAS Latency, to the desired CAS latency See also: DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) DDR2/DDR3 Should be set, along with the Extended Refresh Recovery, to the specifications for the memory used (TRFC) See also: DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) DDR2 Should be set according to the specifications for the memory used (tWR) DDR3 Should be set according to the specifications for the memory used (tWR). See also: DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 367 Initialization/application information Table 8-73. Programming differences between memory types (continued) Parameter ACTTOACT WRTORD Description Activate A to Activate B Write to read timing Differences DDR2/DDR3 Should be set according to the specifications for the memory used (tRRD) See also: DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) DDR2 Should be set according to the specifications for the memory used (tWTR) DDR3 Should be set according to the specifications for the memory used (tWTR) ADD_LAT WR_LAT RD_TO_PRE CKE_PLS FOUR_ACT See also: DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) Additive latency DDR2/DDR3 Should be set to the desired additive latency. This must be set to a value less than TIMING_CFG_1[ACTTORW] See also: DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1) Write latency DDR2 Should be set to CAS latency - 1 cycle. For example, if the CAS latency if 5 cycles, then this field should be set to 100 (4 cycles). DDR3 Should be set to the desired write latency. Note that DDR3 SDRAMs do not necessarily require the write latency to equal the CAS latency minus 1 cycle. See also: DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1) Read to precharge timing DDR2 Should be set according to the specifications for the memory used (tRTP). Time between read and precharge for non-zero value of additive latency (AL) is a minimum of AL + tRTP cycles. DDR3 Should be set according to the specifications for the memory used (tRTP). Time between read and precharge for non-zero value of additive latency (AL) is a minimum of AL + tRTP cycles. See also: DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1) Minimum CKE pulse width DDR2/DDR3 Should be set according to the specifications for the memory used (tCKE) See also: DDR SDRAM timing configuration 1 (DDR_TIMING_CFG_1) Four activate window DDR2 Should be set according to the specifications for the memory used (tFAW). Only applies to eight logical banks. DDR3 Should be set according to the specifications for the memory used (tFAW). See also: DDR SDRAM timing configuration 0 (DDR_TIMING_CFG_0) Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 368 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-73. Programming differences between memory types (continued) Parameter RD_EN 8_BE 2T_EN DLL_RST_DIS DQS_CFG ODT_CFG Description Differences Registered DIMM enable DDR2/DDR3 If registered DIMMs are used, then this field should be set to 1 See also: DDR SDRAM control configuration (DDR_DDR_SDRAM_CFG) 8-beat burst enable DDR2 Should be set to 0 DDR3 For 32-bit, this may be set to 1 . If this is set to 0, then other requirements in TIMING_CFG_4 are needed to ensure tCCD is met. See also: DDR SDRAM control configuration (DDR_DDR_SDRAM_CFG) 2T timing enable DDR2/DDR3 In heavily loaded systems, this can be set to 1 to gain extra timing margin on the interface at the cost of address/command bandwidth. See also: DDR SDRAM control configuration (DDR_DDR_SDRAM_CFG) DLL reset disable DDR2 Should typically be set to 0, unless it is desired to bypass the DLL reset when exiting self refresh. DDR3 Should be set to 1 See also: DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2) DQS configuration DDR2 Should be set to 01 DDR3 Should be set to 01 See also: DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2) ODT configuration DDR2/DDR3 Can be set for termination at the IOs according to system topology. Typically, if ODT is enabled, then the internal IOs should be set up for termination only during reads to DRAM. See also: DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2) Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 369 Initialization/application information Table 8-73. Programming differences between memory types (continued) Parameter RWT WRT RRT WWT ZQ_EN Description Differences Read-to-write turnaround DDR2 for same chip select (in TIMING_CFG_4) Should typically be set to 0000 DDR3 This can be used to force a longer read-to-write turnaround time when accessing the same chip select. This is useful for burst chop mode, as there are some timing requirements to the same chip select that still must be met. See also: DDR SDRAM timing configuration 4 (DDR_TIMING_CFG_4) Write-to-read turnaround for same chip select (in TIMING_CFG_4) DDR2 Should typically be set to 0000 DDR3 This could be used to force a certain turnaround time between a write and read to the same chip select. This is useful for burst chop mode. However, it is expected that TIMING_CFG_1[WRTORD] is programmed appropriately such that TIMING_CFG_4[WRT] can be set to 0000. See also: DDR SDRAM timing configuration 4 (DDR_TIMING_CFG_4) Read-to-read turnaround for same chip select (in TIMING_CFG_4) DDR2 Should typically be set to 0000 DDR3 Should typically be set to 0010 in burst chop mode (on-the-fly or fixed) or set to 0000 in fixed 8-beat burst mode. See also: DDR SDRAM timing configuration 4 (DDR_TIMING_CFG_4) Write-to-write turnaround for same chip select (in TIMING_CFG_4) DDR2 Should typically be set to 0000 DDR3 Should typically be set to 0010 in burst chop mode (on-the-fly or fixed) or set to 0000 in fixed 8-beat burst mode. ZQ Calibration enable See also: DDR SDRAM timing configuration 4 (DDR_TIMING_CFG_4) DDR2 Should be set to 0 DDR3 Should be set to 1. The other fields in DDR_ZQ_CNTL should also be programmed appropriately based on the DRAM specifications. See also: DDR ZQ calibration control (DDR_DDR_ZQ_CNTL) Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 370 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Table 8-73. Programming differences between memory types (continued) Parameter WRLVL_EN BSTOPR Description Write leveling enable Burst To precharge interval Differences DDR2 Should be set to 0 DDR3 Can be set to 1 if write leveling is desired. Otherwise the value used in TIMING_CFG_2[WR_DATA_DELAY] is used to shift all bytes during writes to DRAM. If write leveling is used, all other fields in DDR_WRLVL_CNTL should be programmed appropriately based on the DRAM specifications. See also: DDR write leveling control (DDR_DDR_WRLVL_CNTL) DDR2/DDR3 Can be set to any value, depending on the application. Auto precharge can be enabled by setting this field to all 0s. See also: DDR SDRAM interval configuration (DDR_DDR_SDRAM_INTERVAL) 8.6.2 DDR SDRAM initialization sequence After configuration of all parameters is complete, system software must set DDR_SDRAM_CFG[MEM_EN] to enable the memory interface. Note that 200 μs (500 μs for DDR3) must elapse after DRAM clocks are stable (DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is set and any chip select is enabled) before MEM_EN can be set, so a delay loop in the initialization code may be necessary if software is enabling the memory controller. If DDR_SDRAM_CFG[BI] is not set, the DDR memory controller conducts an automatic initialization sequence to the memory, which follows the memory specifications. If the bypass initialization mode is used, then software can initialize the memory through the DDR_SDRAM_MD_CNTL register. 8.7 Using Forced Self-Refresh Mode to Implement a BatteryBacked RAM System This section describes the options offered by this device to support battery-backed main memory. The MRS commands to the DRAM are bypassed that is supported through DDR_SDRAM_CFG[BI]. The other training and calibrations run at POR still runs by the DDRC. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 371 Using Forced Self-Refresh Mode to Implement a Battery-Backed RAM System 8.7.1 Hardware Based Self-Refresh Scheme An external voltage sense device can be connected to this device through one of the external interrupt lines IRQn. The external interrupt from the voltage sensor would then be steered through the programmable interrupt controller (PIC) to the internal SoC interrupt event signal, sie0. Note that the sie0 signal must remain high until power is removed. Also note that sie0 is sent to both DDR controllers at the same time. If DDR_SDRAM_CFG_2[SR_IE] is set, the sie0 signal from the interrupt controller is then automatically detected by the DDR controller, which immediately causes main memory to enter self-refresh mode. See Chip select n configuration 2 (DDR_CSn_CONFIG_2), for further information on this bit. The EIVPRn[PRIORITY] must be set to 0xF (highest priority) for self refresh to function. See External interrupt n (IRQn) vector/priority register (PIC_EIVPRn), for description of this register. 8.7.2 Software Based Self-Refresh Scheme The DDR controller also has a software-programmable bit, DDR_SDRAM_CFG_2[FRC_SR], that immediately puts main memory into self-refresh mode. See DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2) for a description of this register. It is expected that a critical interrupt routine triggered by an external voltage sensing device will have time to set this bit. 8.7.3 Bypassing Re-initialization During Battery-Backed Operation The DDR controller offers an initialization bypass feature (DDR_SDRAM_CFG[BI]), which system designers may use to prevent re-initialization of main memory during system power-on following an abnormal shutdown. See DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2) for information on this bit and DDR training initialization address (DDR_DDR_INIT_ADDR) for a discussion of avoiding possible ECC errors in this mode. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 372 Freescale Semiconductor, Inc. Chapter 8 DDR Memory Controllers Note that the DDR controller will automatically wait 200 DRAM cycles before issuing any command after the assertion of MCKE[0:1] when this mode is used. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 373 Using Forced Self-Refresh Mode to Implement a Battery-Backed RAM System P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 374 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) This chapter describes the programmable interrupt controller (PIC) interrupt protocol, various types of interrupt sources controlled by the PIC, and the PIC registers with some programming guidelines. 9.1 Introduction This chapter describes the programmable interrupt controller (PIC) interrupt protocol, various types of interrupt sources controlled by the PIC, and the PIC registers with some programming guidelines. The PIC conforms to the OpenPIC architecture. The interrupt controller provides multiprocessor interrupt management, and is responsible for receiving hardwaregenerated interrupts from different sources (both internal and external), prioritizing them, delivering them to the appropriate destination for servicing. 9.1.1 Overview The figure below is a block diagram showing the relationship of the various functional blocks and how the signals external to the PIC are connected to other blocks on the device, including the cores. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 375 Introduction Figure 9-1. Interrupt sources block diagram features The PIC has the following features: • Support for the following interrupt sources: P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 376 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) • External-Off-chip signals, IRQ[0:11 ] • Internal-These are on-chip sources from peripheral logic within the integrated device signaling error conditions that need to be addressed by software. • Interrupts generated from within the PIC itself, which are as follows: • Global timers A and B internal to the PIC • Two groups of four global 32-bit timers clocked with the CCB clock or the RTC input. Timers within each group can be concatenated to time longer durations. • Interprocessor interrupts (IPI)-Intended for communication between different processor cores on the same device. (Can be used for self-interrupt in single-core devices.) • Message registers-From within the PIC. Triggered on register write, cleared on read. Used for interprocessor communication. • Shared message signaled registers-From within the PIC. Triggered on register write, cleared on read. Used for cross-program communication. • Eight 32-bit message interrupt channels. • Three types of programmable interrupt outputs: • External interrupt (int0 and int1). Any of the PIC interrupt sources can be programmed to direct interrupt requests to int0 and int1. Handling of such interrupt requests follows the OpenPIC specification, which guarantees that the highest priority interrupt supersedes lower priority interrupts. Interrupts routed to int, describes how the PIC logic handles these interrupts. • Critical interrupt (cint0 and cint1). Connected to the respective e500 core's critical interrupt input. • IRQ_OUT_B . Interrupts routed to cint or IRQ_OUT_B, describes how the PIC logic supports this interrupt. • Programming model compliant with the OpenPIC architecture. • Message, interprocessor and global timer interrupts. (Note that the interprocessor and global timer interrupts can only be routed to int.) • The following OpenPIC-defined features support only interrupts routed to the int signal: • Fully-nested interrupt delivery, guaranteeing that the interrupt source with the highest priority is given precedence over lower priority interrupts, including any that are in service. • 16 programmable interrupt priority levels • Support for identifying and handling spurious interrupts • Support for two processors P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 377 Introduction • Interrupts can be routed to processor core 0 or 1 • Multi-cast delivery mode for interprocessor and global timer interrupts allowing these interrupts to be routed to either core 0 or 1, or both cores • Processor core initialization control • Programmable resetting of the PIC through the global configuration register • Support for connection of external interrupt controller device such as an 8259 programmable interrupt controller. In 8259 mode, an interrupt causes assertion of a local (that is, internal to the integrated device) interrupt output signal IRQ_OUT_B. • Pass-through mode (PIC disabled) in which the PIC directs interrupts off-chip for external servicing. See Pass-through mode (GCR[M] = 0). 9.1.2 The PIC in multiple-processor implementations In a multiprocessor implementation, the PIC is replicated for each core, and where necessary, the duplicated resources are indicated with a 0 or a 1. For example, int0 identifies the int signal to processor 0 and int1 identifies the int signal to processor 1. Other resources associated with the cores are identified by the number. For example, setting PIR[P1] triggers a reset of core 1, and setting PIR[P0] triggers a reset of core 0. However, where the distinction is not necessary, none is made and such resources are referred to generically. For example, the int signal refers to the behavior of either int0 or int1. In a multiprocessor system, it is possible for the PIC to direct interrupts to the other processor. This functionality is supported by certain multiprocessor aspects to the programming model. For example, an interrupt source in processor 0 can be programmed to target int1 by setting the P1 bit in its destination register, xIDRn. Note that although they are part of the programming model, such resources are reserved in a single-processor device. 9.1.3 Interrupts to the e500 processor core The external interrupt signal, int, is the main interrupt output from the PIC to the processor core. The interrupt sources can also specify the critical interrupt output, cint0 or cint1, if the corresponding xIDRn[CI0] or xIDRn[CI1] is set. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 378 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) The PIC also defines the PIR, described in Processor core initialization register (PIC_PIR) which can be used to reset the core. Processor core interrupts generated by the PIC are described in the table below. Table 9-1. e500 processor interrupts generated outside the core-types and sources Core interrupt Signaled by type (input to core) Sources PIC-Programmable interrupts External interrupt int Generated by the PIC, as described in Interrupt sources. Critical interrupt cint Generated by the PIC, as described in Interrupt sources. Other interrupts generated outside the core Machine check coren_mcp • MCP • SRESET • Assertion of core_mcp by global utilities block Unconditional debug event coren_ude UDE. Asserting UDE generates an unconditional debug exception type debug interrupt and sets a bit in the debug status register, DBSR[UDE], as described in the e500 Core Family Reference Manual . Reset coren_hreset • HRESET assertion (and negation) • core_hreset_req. Output from core-caused by writing to the core DBCR0[RST], as described in the e500 Reference Manual. This condition is additionally qualified with MSR[DE] and DBCR0[IDM] bits. Note that assertion of this signal causes a hard reset of the core only. • core_reset. Output from PIC. See Processor core initialization register (PIC_PIR). 9.1.4 Modes of operation Mixed or pass-through mode of operation is chosen by setting or clearing GCR[M]. This is described in Global configuration register (PIC_GCR) . 9.1.4.1 Mixed mode (GCR[M] = 1) In mixed mode, external and internal interrupts are delivered using the normal priority and delivery mechanisms detailed in Flow of interrupt control. 9.1.4.2 Pass-through mode (GCR[M] = 0) The PIC provides a mechanism to support alternate external interrupt controllers such as the PC/AT-compatible 8259 interrupt controller architecture. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 379 Introduction After a hard reset, the PIC defaults to pass-through mode, in which active-high interrupts from external source IRQ0 are passed directly to core 0 as shown in the figure below; all other external interrupt signals are ignored. Thus, the interrupt signal from an external interrupt controller can be connected to IRQ0 and cause direct interrupts to the processor core 0. The PIC does not perform a vector fetch from an external interrupt controller. Figure 9-2. Pass-through mode example When pass-through mode is enabled, the internally-generated interrupts shown in Table 9-2 are not forwarded to core 0. Instead, the PIC passes the raw interrupts from the internal sources to IRQ_OUT_B . Note that when the PCI Express controller is configured as an endpoint (EP) device, the irq_out signal from the PIC may be used to automatically generate an outbound PCI Express MSI transaction toward the remote interrupt controller resource on the root complex (RC). See Hardware MSI generation. Note that in pass-through mode, interrupts generated within the PIC (global timers, interprocessor, and message register interrupts) are disabled. If internal or PIC-generated interrupts must be reported internally to the processor, mixed mode must be used. It is required that in pass-through mode the internal and external interrupt targets should be int, which is by default. 9.1.5 Interrupt sources The PIC can receive separate interrupts from the following sources: • External-Off-chip signals, IRQ[0:11 ] • Internal-On-chip sources from peripheral logic within the integrated device. See Table 9-2. • Global timers A and B internal to the PIC P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 380 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) • Interprocessor interrupts (IPI)-Intended for communication between different e500 processor cores on the same device. (Can be used for self-interrupt in single-core implementations.) • Message registers-From within the PIC. Triggered on register write, cleared on read. Used for interprocessor communication. • Shared message signaled registers-From within the PIC. Triggered on register write, cleared on read. Used for cross-program communication. 9.1.5.1 Interrupt routing-mixed mode When an interrupt request is delivered to the PIC, the corresponding interrupt destination register is checked to determine where the request should be routed, as follows: • If xIDRn[EP] = 1 (and all other destination bits are zero), the interrupt is routed offchip to the external IRQ_OUT_B signal. If the PCI Express controller is in EP mode (and the corresponding xIDRn[EP] = 1), the controller automatically generates a PCI Express MSI transaction. See Hardware MSI generation. • If either, but not both, xIDRn[CI0] or xIDRn[CI1] is set (and all other destination bits are zero), the interrupt is routed to cint0 or cint1. • If xIDRn[P0] is set (and all other destination bits are zero) the interrupt is routed to int0. Setting xIDRn[P1] likewise routs the interrupt to int1. In this case, the interrupt is latched by the interrupt pending register (IPR) and the interrupt flow is as described in Flow of interrupt control. Note that multicasting interrupts (global timer and interprocessor interrupts) can set both P0 and P1; other interrupt sources cannot. 9.1.5.2 Interrupt destinations Following its reset (by default), the PIC directs all timer, shared message signaled, and interrupts from external and internal sources to int output (connected to the int signal of the e500 processor core). Interprocessor and global timers interrupts can be programmed to be routed to either core's int signal or to both cores (multi-casting). All other interrupts have more destination options, but only one destination can be chosen for a single non-multi-casting interrupt. Instead of being routed to int, these interrupts can be routed to the core through cint or can be directed to IRQ_OUT_B. These options are selected by writing to the EP or CI fields in the appropriate destination register. Note that EP and CI are only supported for external and internal interrupts that does not support multi-casting. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 381 Introduction 9.1.5.3 Internal interrupt sources The table below shows the assignments of the internal interrupt sources and how they are mapped to the registers that control them. Only the internal interrupts used are listed; that is, the numbers are not consecutive. Table 9-2. Internal interrupt assignments Internal Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21-23 24 25 26 27 28 29 30 31 32-34 35 Interrupt Source ORed Error Interrupt. See Table 9-3 for individual assignments. eTSEC 1 group 1 transmit eTSEC 1 group 1 receive eLBC general interrupt DMA channel 1 DMA channel 2 DMA channel 3 DMA channel 4 eTSEC 1 group 1 error eTSEC 3 group 1 transmit eTSEC 3 group 1 receive eTSEC 3 group 1 error USB 1 eTSEC 1 group 0 transmit eTSEC 1 group 0 receive eTSEC 3 group 0 transmit eTSEC 3 group 0 receive eTSEC 3 group 0 error eTSEC 1 group 0 error eTSEC 2 group 0 transmit eTSEC 2 group 0 receive Reserved eTSEC 2 group 0 error Reserved DUART I2C controllers Performance monitor Security interrupt 1 USB 2 GPIO Reserved eTSEC 2 group 1 transmit Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 382 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) Table 9-2. Internal interrupt assignments (continued) Internal Interrupt Number 36 37-41 42 43 44 45 46 47 48-50 51 52 53 54 55 56 57-63 Interrupt Source eTSEC 2 group 1 receive Reserved Security interrupt 2 eSPI Reserved Reserved TDM (TDMTx, TDMRx, and DMAC) TDM error (TDM, DMAC error) Reserved eTSEC 2 group 1 error eTSEC 1 1588 timer eTSEC 2 1588 timer eTSEC 3 1588 timer Reserved eSDHC Reserved The ORed error interrupt summary is listed in the table below. Table 9-3. ORed Error Interrupt Sources L2 Cache Interrupt Source ECM (e500 coherency module) Memory Controller Error PCI Express controller 1 PCI Express controller 2 TDM Enhanced Local Bus Controller Section/Page L2 error detect register (L2_Cache_L2ERRDET) ECM error detect register (ECM_EEDR) Memory error detect (DDR_ERR_DETECT) PCI Express error detect register (PEX_PEX_ERR_DR) PCI Express error detect register (PEX_PEX_ERR_DR) TDM receive event register (TDM_SB_TDMRER), TDM transmit event register (TDM_SB_TDMTER) ,DMA Error Status Register (TDM_DMAC_DMAES), and Transfer error status register (eLBC_LTESR) P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 383 PIC external signal descriptions 9.2 PIC external signal descriptions The following sections describe the PIC signals. 9.2.1 Signal overview The PIC external interface signals are described in Table 9-4. There are distinct external interrupt request input signals and an interrupt request output signal IRQ_OUT_B . As Table 9-4 shows, the IRQ inputs are also used for delivering INTx signals for the PCI Express root complexes. 9.2.2 Detailed signal descriptions Table 9-4. Interrupt signals-detailed signal descriptions Signal I/ O Description IRQ[0:11 I Interrupt request 0-11. The polarity and sense of each of these signals is programmable. All of these inputs ] can be driven asynchronously. NOTE: Some interrupt request signals IRQn may share PIC external interrupt registers with PCI Express INTx signaling. See PCI Express INTx/IRQn sharing. State Meanin g Asserted-When an external interrupt signal is asserted (according to the programmed polarity), the PIC checks its priority and the interrupt is conditionally passed to the processor designated in the corresponding destination register. In pass-through mode, only interrupts detected on IRQ0 are passed directly to core 0. Negated-There is no incoming interrupt from that source. Timing Assertion-All of these inputs can be asserted asynchronously. Negation-Interrupts programmed as level-sensitive must remain asserted until serviced. Timing requirements for edge-sensitive interrupts can be found in the Hardware Specifications. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 384 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) Table 9-4. Interrupt signals-detailed signal descriptions (continued) Signal I/ O Description IRQ_OU O Interrupt request out. When the PIC is programmed in pass-through mode, this output reflects the raw T_B interrupts generated by on-chip sources. See Modes of operation. State Asserted-At least one interrupt is currently being signaled to the external system. Meanin g Negated-Indicates no interrupt source currently routed to IRQ_OUT_B . Timing Because external interrupts are asynchronous with respect to the system clock, both assertion and negation of IRQ_OUT_B occurs asynchronously with respect to the interrupt source. All timing given here is approximate. Assertion-Internal interrupt source: 2 CCB clock cycles after interrupt occurs. External interrupt source: 4 cycles after interrupt occurs. Message interrupts: 2 cycles after write to message register. Negation-Follows interrupt source negation with the following delay: Internal interrupt: 2 CCB clock cycles External interrupt: 4 cycles. Message interrupts: 2 cycles after message register cleared. MCP0_B I and MCP1_B Machine check processor n. Assertion causes a machine check interrupt to the corresponding core. Note that if the core is not configured to process machine check interrupts (MSR[ME] = 0), assertion of MCPn_B causes a core checkstop condition. Note that internal sources for the internal coren_mcp can also cause a machine check interrupt to the processor core as described in Machine check summary register (GUTS_MCPSUMR) and Table 9-1. State Meanin g Asserted-Integrated logic should direct the corresponding core to take a machine check interrupt or enter the checkstop state as directed by the MSR. Negated-Machine check handling is not being requested by the external system. Timing Assertion-May occur at any time, asynchronous to any clock. Negation-Because MCP_B n is edge-triggered, it can be negated one clock after its assertion. 9.3 PIC memory map/register definition The PIC programmable register map occupies 256 Kbytes of memory-mapped space. Reading undefined portions of the memory map returns all zeros; writing has no effect. All PIC registers are 32 bits wide and, although located on 128-bit address boundaries, should be accessed only as 32-bit quantities. The PIC address offset map is divided into three areas: • 0xnn4_0000-0xnn4_FFF0-Global registers • 0xnn5_0000-0xnn5_FFF0-Interrupt source configuration registers • 0xnn6_0000- 0xnn7_FFF0 -Per-CPU registers P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 385 PIC memory map/register definition PIC memory map Offset address (hex) 4_0000 4_0010 4_0040 4_0050 4_0060 4_0070 4_0080 4_0090 4_00A0 4_00B0 4_1000 4_1020 4_1080 4_1090 4_10A0 4_10B0 4_10C0 4_10D0 4_10E0 4_10F0 4_1100 4_1110 4_1120 4_1130 4_1140 4_1150 4_1160 4_1170 4_1180 4_1190 4_11A0 Register name Width (in bits) Access Reset value Section/ page Block revision register 1 (PIC_BRR1) 32 Block revision register 2 (PIC_BRR2) 32 Interprocessor n dispatch register (PIC_IPIDR0) 32 Interprocessor n dispatch register (PIC_IPIDR1) 32 Interprocessor n dispatch register (PIC_IPIDR2) 32 Interprocessor n dispatch register (PIC_IPIDR3) 32 Current task priority register (PIC_CTPR) 32 Who am I register (PIC_WHOAMI) 32 Interrupt acknowledge register (PIC_IACK) 32 End of interrupt register (PIC_EOI) 32 Feature reporting register (PIC_FRR) 32 Global configuration register (PIC_GCR) 32 Vendor identification register (PIC_VIR) 32 Processor core initialization register (PIC_PIR) 32 Interprocessor interrupt n vector/priority register (PIC_IPIVPR0) 32 Interprocessor interrupt n vector/priority register (PIC_IPIVPR1) 32 Interprocessor interrupt n vector/priority register (PIC_IPIVPR2) 32 Interprocessor interrupt n vector/priority register (PIC_IPIVPR3) 32 Spurious vector register (PIC_SVR) 32 Timer frequency reporting register group X (PIC_TFRRA) 32 Global timer n current count register group A (PIC_GTCCRA0) 32 Global timer n base count register group A (PIC_GTBCRA0) 32 Global timer n vector/priority register group A (PIC_GTVPRA0) 32 Global timer n destination register group A (PIC_GTDRA0) 32 Global timer n current count register group A (PIC_GTCCRA1) 32 Global timer n base count register group A (PIC_GTBCRA1) 32 Global timer n vector/priority register group A (PIC_GTVPRA1) 32 Global timer n destination register group A (PIC_GTDRA1) 32 Global timer n current count register group A (PIC_GTCCRA2) 32 Global timer n base count register group A (PIC_GTBCRA2) 32 Global timer n vector/priority register group A (PIC_GTVPRA2) 32 R 0040_0301h 9.3.1/395 R 0000_0001h 9.3.2/396 W 0000_0000h 9.3.3/397 W 0000_0000h 9.3.3/397 W 0000_0000h 9.3.3/397 W 0000_0000h 9.3.3/397 R/W 0000_000Fh 9.3.4/397 R See section 9.3.5/398 R 0000_0000h 9.3.6/399 W 0000_0000h 9.3.7/400 R See section 9.3.8/400 R/W 0000_0000h 9.3.9/402 R 0000_0000h 9.3.10/403 R/W 0000_0000h 9.3.11/403 R/W 8000_0000h 9.3.12/404 R/W 8000_0000h 9.3.12/404 R/W 8000_0000h 9.3.12/404 R/W 8000_0000h 9.3.12/404 R/W 0000_FFFFh 9.3.13/405 R/W 0000_0000h 9.3.14/405 R 0000_0000h 9.3.15/406 R/W 8000_0000h 9.3.16/407 R/W 8000_0000h 9.3.17/408 R/W 0000_0001h 9.3.18/409 R 0000_0000h 9.3.15/406 R/W 8000_0000h 9.3.16/407 R/W 8000_0000h 9.3.17/408 R/W 0000_0001h 9.3.18/409 R 0000_0000h 9.3.15/406 R/W 8000_0000h 9.3.16/407 R/W 8000_0000h 9.3.17/408 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 386 Freescale Semiconductor, Inc. Offset address (hex) 4_11B0 4_11C0 4_11D0 4_11E0 4_11F0 4_1300 4_1308 4_1310 4_1320 4_1324 4_1330 4_1340 4_1344 4_1350 4_1360 4_1364 4_1370 4_1380 4_1384 4_1390 4_13A0 4_13A4 4_13B0 4_13C0 4_13C4 4_1400 4_1410 4_1420 4_1430 4_1500 4_1510 4_1600 4_1610 4_1620 4_1630 4_1640 Chapter 9 Programmable Interrupt Controller (PIC) PIC memory map (continued) Register name Width (in bits) Access Reset value Section/ page Global timer n destination register group A (PIC_GTDRA2) 32 Global timer n current count register group A (PIC_GTCCRA3) 32 Global timer n base count register group A (PIC_GTBCRA3) 32 Global timer n vector/priority register group A (PIC_GTVPRA3) 32 Global timer n destination register group A (PIC_GTDRA3) 32 Timer control register group n (PIC_TCRA) 32 External interrupt summary register (PIC_ERQSR) 32 IRQ_OUT_B summary register 0 (PIC_IRQSR0) 32 IRQ_OUT_B summary register 1 (PIC_IRQSR1) 32 IRQ_OUT_B summary register 2 (PIC_IRQSR2) 32 Critical interrupt summary register 0 (PIC_CISR0) 32 Critical interrupt summary register 1 (PIC_CISR1) 32 Critical interrupt summary register 2 (PIC_CISR2) 32 Performance monitor n mask register 0 (PIC_PM0MR0) 32 Performance monitor n mask register 1 (PIC_PM0MR1) 32 Performance monitor n mask register 2 (PIC_PM0MR2) 32 Performance monitor n mask register 0 (PIC_PM1MR0) 32 Performance monitor n mask register 1 (PIC_PM1MR1) 32 Performance monitor n mask register 2 (PIC_PM1MR2) 32 Performance monitor n mask register 0 (PIC_PM2MR0) 32 Performance monitor n mask register 1 (PIC_PM2MR1) 32 Performance monitor n mask register 2 (PIC_PM2MR2) 32 Performance monitor n mask register 0 (PIC_PM3MR0) 32 Performance monitor n mask register 1 (PIC_PM3MR1) 32 Performance monitor n mask register 2 (PIC_PM3MR2) 32 Message register n (PIC_MSGR0) 32 Message register n (PIC_MSGR1) 32 Message register n (PIC_MSGR2) 32 Message register n (PIC_MSGR3) 32 Message enable register (PIC_MER) 32 Message status register (PIC_MSR) 32 Shared message signaled interrupt register n (PIC_MSIR0) 32 Shared message signaled interrupt register n (PIC_MSIR1) 32 Shared message signaled interrupt register n (PIC_MSIR2) 32 Shared message signaled interrupt register n (PIC_MSIR3) 32 Shared message signaled interrupt register n (PIC_MSIR4) 32 Table continues on the next page... R/W 0000_0001h 9.3.18/409 R 0000_0000h 9.3.15/406 R/W 8000_0000h 9.3.16/407 R/W 8000_0000h 9.3.17/408 R/W 0000_0001h 9.3.18/409 R/W 0000_0000h 9.3.19/409 R 0000_0000h 9.3.20/412 R 0000_0000h 9.3.21/412 R 0000_0000h 9.3.22/413 R 0000_0000h 9.3.23/413 R 0000_0000h 9.3.24/414 R 0000_0000h 9.3.25/414 R 0000_0000h 9.3.26/415 R/W FFFF_FFFFh 9.3.27/415 R/W FFFF_FFFFh 9.3.28/416 R/W FFFF_FFFFh 9.3.29/416 R/W FFFF_FFFFh 9.3.27/415 R/W FFFF_FFFFh 9.3.28/416 R/W FFFF_FFFFh 9.3.29/416 R/W FFFF_FFFFh 9.3.27/415 R/W FFFF_FFFFh 9.3.28/416 R/W FFFF_FFFFh 9.3.29/416 R/W FFFF_FFFFh 9.3.27/415 R/W FFFF_FFFFh 9.3.28/416 R/W FFFF_FFFFh 9.3.29/416 R/W 0000_0000h 9.3.30/417 R/W 0000_0000h 9.3.30/417 R/W 0000_0000h 9.3.30/417 R/W 0000_0000h 9.3.30/417 R/W 0000_0000h 9.3.31/417 R/W 0000_0000h 9.3.32/418 R 0000_0000h 9.3.33/418 R 0000_0000h 9.3.33/418 R 0000_0000h 9.3.33/418 R 0000_0000h 9.3.33/418 R 0000_0000h 9.3.33/418 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 387 PIC memory map/register definition PIC memory map (continued) Offset address (hex) 4_1650 4_1660 4_1670 4_1720 4_1740 4_20F0 4_2100 4_2110 4_2120 4_2130 4_2140 4_2150 4_2160 4_2170 4_2180 4_2190 4_21A0 4_21B0 4_21C0 4_21D0 4_21E0 4_21F0 4_2300 4_2400 4_2410 4_2420 4_2430 4_2500 4_2510 5_0000 Register name Width (in bits) Access Reset value Section/ page Shared message signaled interrupt register n (PIC_MSIR5) 32 Shared message signaled interrupt register n (PIC_MSIR6) 32 Shared message signaled interrupt register n (PIC_MSIR7) 32 Shared message signaled interrupt status register (PIC_MSISR) 32 Shared message signaled interrupt index register (PIC_MSIIR) 32 Timer frequency reporting register group X (PIC_TFRRB) 32 Global timer n current count register group B (PIC_GTCCRB0) 32 Global timer n base count register group B (PIC_GTBCRB0) 32 Global timer n vector/priority register group B (PIC_GTVPRB0) 32 Global timer n destination register group B (PIC_GTDRB0) 32 Global timer n current count register group B (PIC_GTCCRB1) 32 Global timer n base count register group B (PIC_GTBCRB1) 32 Global timer n vector/priority register group B (PIC_GTVPRB1) 32 Global timer n destination register group B (PIC_GTDRB1) 32 Global timer n current count register group B (PIC_GTCCRB2) 32 Global timer n base count register group B (PIC_GTBCRB2) 32 Global timer n vector/priority register group B (PIC_GTVPRB2) 32 Global timer n destination register group B (PIC_GTDRB2) 32 Global timer n current count register group B (PIC_GTCCRB3) 32 Global timer n base count register group B (PIC_GTBCRB3) 32 Global timer n vector/priority register group B (PIC_GTVPRB3) 32 Global timer n destination register group B (PIC_GTDRB3) 32 Timer control register group n (PIC_TCRB) 32 Message register n (PIC_MSGRa4) 32 Message register n (PIC_MSGRa5) 32 Message register n (PIC_MSGRa6) 32 Message register n (PIC_MSGRa7) 32 Message enable register (PIC_MERa) 32 Message status register (PIC_MSRa) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR0) 32 R 0000_0000h 9.3.33/418 R 0000_0000h 9.3.33/418 R 0000_0000h 9.3.33/418 R 0000_0000h 9.3.34/419 W 0000_0000h 9.3.35/420 R/W 0000_0000h 9.3.14/405 R 0000_0000h 9.3.36/421 R/W 8000_0000h 9.3.37/422 R/W 8000_0000h 9.3.38/423 R/W 0000_0001h 9.3.39/424 R 0000_0000h 9.3.36/421 R/W 8000_0000h 9.3.37/422 R/W 8000_0000h 9.3.38/423 R/W 0000_0001h 9.3.39/424 R 0000_0000h 9.3.36/421 R/W 8000_0000h 9.3.37/422 R/W 8000_0000h 9.3.38/423 R/W 0000_0001h 9.3.39/424 R 0000_0000h 9.3.36/421 R/W 8000_0000h 9.3.37/422 R/W 8000_0000h 9.3.38/423 R/W 0000_0001h 9.3.39/424 R/W 0000_0000h 9.3.19/409 R/W 0000_0000h 9.3.40/424 R/W 0000_0000h 9.3.40/424 R/W 0000_0000h 9.3.40/424 R/W 0000_0000h 9.3.40/424 R/W 0000_0000h 9.3.41/425 R/W 0000_0000h 9.3.42/426 R/W 8000_0000h 9.3.43/426 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 388 Freescale Semiconductor, Inc. Offset address (hex) 5_0010 5_0020 5_0030 5_0040 5_0050 5_0060 5_0070 5_0080 5_0090 5_00A0 5_00B0 5_00C0 5_00D0 5_00E0 5_00F0 5_0100 5_0110 5_0120 5_0130 5_0140 5_0150 5_0160 5_0170 5_0200 5_0210 5_0220 5_0230 5_0240 5_0250 Chapter 9 Programmable Interrupt Controller (PIC) PIC memory map (continued) Register name Width (in bits) Access Reset value Section/ page External interrupt n (IRQn) destination register (PIC_EIDR0) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR1) 32 External interrupt n (IRQn) destination register (PIC_EIDR1) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR2) 32 External interrupt n (IRQn) destination register (PIC_EIDR2) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR3) 32 External interrupt n (IRQn) destination register (PIC_EIDR3) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR4) 32 External interrupt n (IRQn) destination register (PIC_EIDR4) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR5) 32 External interrupt n (IRQn) destination register (PIC_EIDR5) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR6) 32 External interrupt n (IRQn) destination register (PIC_EIDR6) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR7) 32 External interrupt n (IRQn) destination register (PIC_EIDR7) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR8) 32 External interrupt n (IRQn) destination register (PIC_EIDR8) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR9) 32 External interrupt n (IRQn) destination register (PIC_EIDR9) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR10) 32 External interrupt n (IRQn) destination register (PIC_EIDR10) 32 External interrupt n (IRQn) vector/priority register (PIC_EIVPR11) 32 External interrupt n (IRQn) destination register (PIC_EIDR11) 32 Internal interrupt n vector/priority register (PIC_IIVPR0) 32 Internal interrupt n destination register (PIC_IIDR0) 32 Internal interrupt n vector/priority register (PIC_IIVPR1) 32 Internal interrupt n destination register (PIC_IIDR1) 32 Internal interrupt n vector/priority register (PIC_IIVPR2) 32 Internal interrupt n destination register (PIC_IIDR2) 32 Table continues on the next page... R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8000_0000h 9.3.43/426 R/W 0000_0001h 9.3.44/428 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 389 PIC memory map/register definition PIC memory map (continued) Offset address (hex) 5_0260 5_0270 5_0280 5_0290 5_02A0 5_02B0 5_02C0 5_02D0 5_02E0 5_02F0 5_0300 5_0310 5_0320 5_0330 5_0340 5_0350 5_0360 5_0370 5_0380 5_0390 5_03A0 5_03B0 5_03C0 5_03D0 5_03E0 5_03F0 5_0400 5_0410 5_0420 5_0430 5_0440 5_0450 5_0460 5_0470 5_0480 5_0490 5_04A0 5_04B0 Register name Internal interrupt n vector/priority register (PIC_IIVPR3) Internal interrupt n destination register (PIC_IIDR3) Internal interrupt n vector/priority register (PIC_IIVPR4) Internal interrupt n destination register (PIC_IIDR4) Internal interrupt n vector/priority register (PIC_IIVPR5) Internal interrupt n destination register (PIC_IIDR5) Internal interrupt n vector/priority register (PIC_IIVPR6) Internal interrupt n destination register (PIC_IIDR6) Internal interrupt n vector/priority register (PIC_IIVPR7) Internal interrupt n destination register (PIC_IIDR7) Internal interrupt n vector/priority register (PIC_IIVPR8) Internal interrupt n destination register (PIC_IIDR8) Internal interrupt n vector/priority register (PIC_IIVPR9) Internal interrupt n destination register (PIC_IIDR9) Internal interrupt n vector/priority register (PIC_IIVPR10) Internal interrupt n destination register (PIC_IIDR10) Internal interrupt n vector/priority register (PIC_IIVPR11) Internal interrupt n destination register (PIC_IIDR11) Internal interrupt n vector/priority register (PIC_IIVPR12) Internal interrupt n destination register (PIC_IIDR12) Internal interrupt n vector/priority register (PIC_IIVPR13) Internal interrupt n destination register (PIC_IIDR13) Internal interrupt n vector/priority register (PIC_IIVPR14) Internal interrupt n destination register (PIC_IIDR14) Internal interrupt n vector/priority register (PIC_IIVPR15) Internal interrupt n destination register (PIC_IIDR15) Internal interrupt n vector/priority register (PIC_IIVPR16) Internal interrupt n destination register (PIC_IIDR16) Internal interrupt n vector/priority register (PIC_IIVPR17) Internal interrupt n destination register (PIC_IIDR17) Internal interrupt n vector/priority register (PIC_IIVPR18) Internal interrupt n destination register (PIC_IIDR18) Internal interrupt n vector/priority register (PIC_IIVPR19) Internal interrupt n destination register (PIC_IIDR19) Internal interrupt n vector/priority register (PIC_IIVPR20) Internal interrupt n destination register (PIC_IIDR20) Internal interrupt n vector/priority register (PIC_IIVPR21) Internal interrupt n destination register (PIC_IIDR21) Width (in bits) Access Reset value Section/ page 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 390 Freescale Semiconductor, Inc. Offset address (hex) 5_04C0 5_04D0 5_04E0 5_04F0 5_0500 5_0510 5_0520 5_0530 5_0540 5_0550 5_0560 5_0570 5_0580 5_0590 5_05A0 5_05B0 5_05C0 5_05D0 5_05E0 5_05F0 5_0600 5_0610 5_0620 5_0630 5_0640 5_0650 5_0660 5_0670 5_0680 5_0690 5_06A0 5_06B0 5_06C0 5_06D0 5_06E0 5_06F0 5_0700 5_0710 Chapter 9 Programmable Interrupt Controller (PIC) PIC memory map (continued) Register name Width (in bits) Access Reset value Section/ page Internal interrupt n vector/priority register (PIC_IIVPR22) 32 Internal interrupt n destination register (PIC_IIDR22) 32 Internal interrupt n vector/priority register (PIC_IIVPR23) 32 Internal interrupt n destination register (PIC_IIDR23) 32 Internal interrupt n vector/priority register (PIC_IIVPR24) 32 Internal interrupt n destination register (PIC_IIDR24) 32 Internal interrupt n vector/priority register (PIC_IIVPR25) 32 Internal interrupt n destination register (PIC_IIDR25) 32 Internal interrupt n vector/priority register (PIC_IIVPR26) 32 Internal interrupt n destination register (PIC_IIDR26) 32 Internal interrupt n vector/priority register (PIC_IIVPR27) 32 Internal interrupt n destination register (PIC_IIDR27) 32 Internal interrupt n vector/priority register (PIC_IIVPR28) 32 Internal interrupt n destination register (PIC_IIDR28) 32 Internal interrupt n vector/priority register (PIC_IIVPR29) 32 Internal interrupt n destination register (PIC_IIDR29) 32 Internal interrupt n vector/priority register (PIC_IIVPR30) 32 Internal interrupt n destination register (PIC_IIDR30) 32 Internal interrupt n vector/priority register (PIC_IIVPR31) 32 Internal interrupt n destination register (PIC_IIDR31) 32 Internal interrupt n vector/priority register (PIC_IIVPR32) 32 Internal interrupt n destination register (PIC_IIDR32) 32 Internal interrupt n vector/priority register (PIC_IIVPR33) 32 Internal interrupt n destination register (PIC_IIDR33) 32 Internal interrupt n vector/priority register (PIC_IIVPR34) 32 Internal interrupt n destination register (PIC_IIDR34) 32 Internal interrupt n vector/priority register (PIC_IIVPR35) 32 Internal interrupt n destination register (PIC_IIDR35) 32 Internal interrupt n vector/priority register (PIC_IIVPR36) 32 Internal interrupt n destination register (PIC_IIDR36) 32 Internal interrupt n vector/priority register (PIC_IIVPR37) 32 Internal interrupt n destination register (PIC_IIDR37) 32 Internal interrupt n vector/priority register (PIC_IIVPR38) 32 Internal interrupt n destination register (PIC_IIDR38) 32 Internal interrupt n vector/priority register (PIC_IIVPR39) 32 Internal interrupt n destination register (PIC_IIDR39) 32 Internal interrupt n vector/priority register (PIC_IIVPR40) 32 Internal interrupt n destination register (PIC_IIDR40) 32 Table continues on the next page... R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 391 PIC memory map/register definition PIC memory map (continued) Offset address (hex) 5_0720 5_0730 5_0740 5_0750 5_0760 5_0770 5_0780 5_0790 5_07A0 5_07B0 5_07C0 5_07D0 5_07E0 5_07F0 5_0800 5_0810 5_0820 5_0830 5_0840 5_0850 5_0860 5_0870 5_0880 5_0890 5_08A0 5_08B0 5_08C0 5_08D0 5_08E0 5_08F0 5_0900 5_0910 5_0920 5_0930 5_0940 5_0950 5_0960 5_0970 Register name Internal interrupt n vector/priority register (PIC_IIVPR41) Internal interrupt n destination register (PIC_IIDR41) Internal interrupt n vector/priority register (PIC_IIVPR42) Internal interrupt n destination register (PIC_IIDR42) Internal interrupt n vector/priority register (PIC_IIVPR43) Internal interrupt n destination register (PIC_IIDR43) Internal interrupt n vector/priority register (PIC_IIVPR44) Internal interrupt n destination register (PIC_IIDR44) Internal interrupt n vector/priority register (PIC_IIVPR45) Internal interrupt n destination register (PIC_IIDR45) Internal interrupt n vector/priority register (PIC_IIVPR46) Internal interrupt n destination register (PIC_IIDR46) Internal interrupt n vector/priority register (PIC_IIVPR47) Internal interrupt n destination register (PIC_IIDR47) Internal interrupt n vector/priority register (PIC_IIVPR48) Internal interrupt n destination register (PIC_IIDR48) Internal interrupt n vector/priority register (PIC_IIVPR49) Internal interrupt n destination register (PIC_IIDR49) Internal interrupt n vector/priority register (PIC_IIVPR50) Internal interrupt n destination register (PIC_IIDR50) Internal interrupt n vector/priority register (PIC_IIVPR51) Internal interrupt n destination register (PIC_IIDR51) Internal interrupt n vector/priority register (PIC_IIVPR52) Internal interrupt n destination register (PIC_IIDR52) Internal interrupt n vector/priority register (PIC_IIVPR53) Internal interrupt n destination register (PIC_IIDR53) Internal interrupt n vector/priority register (PIC_IIVPR54) Internal interrupt n destination register (PIC_IIDR54) Internal interrupt n vector/priority register (PIC_IIVPR55) Internal interrupt n destination register (PIC_IIDR55) Internal interrupt n vector/priority register (PIC_IIVPR56) Internal interrupt n destination register (PIC_IIDR56) Internal interrupt n vector/priority register (PIC_IIVPR57) Internal interrupt n destination register (PIC_IIDR57) Internal interrupt n vector/priority register (PIC_IIVPR58) Internal interrupt n destination register (PIC_IIDR58) Internal interrupt n vector/priority register (PIC_IIVPR59) Internal interrupt n destination register (PIC_IIDR59) Width (in bits) Access Reset value Section/ page 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 32 R/W 8080_0000h 9.3.45/429 32 R/W 0000_0001h 9.3.46/430 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 392 Freescale Semiconductor, Inc. Offset address (hex) 5_0980 5_0990 5_09A0 5_09B0 5_09C0 5_09D0 5_09E0 5_09F0 5_1600 5_1610 5_1620 5_1630 5_1640 5_1650 5_1660 5_1670 5_1680 5_1690 5_16A0 5_16B0 5_16C0 5_16D0 5_16E0 5_16F0 5_1C00 Chapter 9 Programmable Interrupt Controller (PIC) PIC memory map (continued) Register name Width (in bits) Access Reset value Section/ page Internal interrupt n vector/priority register (PIC_IIVPR60) 32 Internal interrupt n destination register (PIC_IIDR60) 32 Internal interrupt n vector/priority register (PIC_IIVPR61) 32 Internal interrupt n destination register (PIC_IIDR61) 32 Internal interrupt n vector/priority register (PIC_IIVPR62) 32 Internal interrupt n destination register (PIC_IIDR62) 32 Internal interrupt n vector/priority register (PIC_IIVPR63) 32 Internal interrupt n destination register (PIC_IIDR63) 32 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPR0) 32 Messaging interrupt n (MSGn) destination register (PIC_MIDR0) 32 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPR1) 32 Messaging interrupt n (MSGn) destination register (PIC_MIDR1) 32 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPR2) 32 Messaging interrupt n (MSGn) destination register (PIC_MIDR2) 32 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPR3) 32 Messaging interrupt n (MSGn) destination register (PIC_MIDR3) 32 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPR4) 32 Messaging interrupt n (MSGn) destination register (PIC_MIDR4) 32 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPR5) 32 Messaging interrupt n (MSGn) destination register (PIC_MIDR5) 32 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPR6) 32 Messaging interrupt n (MSGn) destination register (PIC_MIDR6) 32 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPR7) 32 Messaging interrupt n (MSGn) destination register (PIC_MIDR7) 32 Shared message signaled interrupt vector/priority register n (PIC_MSIVPR0) 32 Table continues on the next page... R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8080_0000h 9.3.45/429 R/W 0000_0001h 9.3.46/430 R/W 8000_0000h 9.3.47/431 R/W 0000_0001h 9.3.48/432 R/W 8000_0000h 9.3.47/431 R/W 0000_0001h 9.3.48/432 R/W 8000_0000h 9.3.47/431 R/W 0000_0001h 9.3.48/432 R/W 8000_0000h 9.3.47/431 R/W 0000_0001h 9.3.48/432 R/W 8000_0000h 9.3.47/431 R/W 0000_0001h 9.3.48/432 R/W 8000_0000h 9.3.47/431 R/W 0000_0001h 9.3.48/432 R/W 8000_0000h 9.3.47/431 R/W 0000_0001h 9.3.48/432 R/W 8000_0000h 9.3.47/431 R/W 0000_0001h 9.3.48/432 R/W 8000_0000h 9.3.49/433 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 393 PIC memory map/register definition PIC memory map (continued) Offset address (hex) 5_1C10 5_1C20 5_1C30 5_1C40 5_1C50 5_1C60 5_1C70 5_1C80 5_1C90 5_1CA0 5_1CB0 5_1CC0 5_1CD0 5_1CE0 5_1CF0 6_0040 6_0050 6_0060 6_0070 6_0080 6_0090 6_00A0 6_00B0 Register name Width (in bits) Access Reset value Section/ page Shared message signaled interrupt destination register n (PIC_MSIDR0) 32 Shared message signaled interrupt vector/priority register n (PIC_MSIVPR1) 32 Shared message signaled interrupt destination register n (PIC_MSIDR1) 32 Shared message signaled interrupt vector/priority register n (PIC_MSIVPR2) 32 Shared message signaled interrupt destination register n (PIC_MSIDR2) 32 Shared message signaled interrupt vector/priority register n (PIC_MSIVPR3) 32 Shared message signaled interrupt destination register n (PIC_MSIDR3) 32 Shared message signaled interrupt vector/priority register n (PIC_MSIVPR4) 32 Shared message signaled interrupt destination register n (PIC_MSIDR4) 32 Shared message signaled interrupt vector/priority register n (PIC_MSIVPR5) 32 Shared message signaled interrupt destination register n (PIC_MSIDR5) 32 Shared message signaled interrupt vector/priority register n (PIC_MSIVPR6) 32 Shared message signaled interrupt destination register n (PIC_MSIDR6) 32 Shared message signaled interrupt vector/priority register n (PIC_MSIVPR7) 32 Shared message signaled interrupt destination register n (PIC_MSIDR7) 32 Processor core 0 interprocessor n dispatch register (PIC_IPIDR_CPU00) 32 Processor core 0 interprocessor n dispatch register (PIC_IPIDR_CPU01) 32 Processor core 0 interprocessor n dispatch register (PIC_IPIDR_CPU02) 32 Processor core 0 interprocessor n dispatch register (PIC_IPIDR_CPU03) 32 Processor core current task priority register 0 Processor core (PIC_CTPR_CPU0) 32 Processor core 0 who am I register (PIC_WHOAMI_CPU0) 32 Processor core 0 interrupt acknowledge register (PIC_IACK_CPU0) 32 Processor core 0 end of interrupt register (PIC_EOI_CPU0) 32 R/W See section 9.3.50/434 R/W 8000_0000h 9.3.49/433 R/W See section 9.3.50/434 R/W 8000_0000h 9.3.49/433 R/W See section 9.3.50/434 R/W 8000_0000h 9.3.49/433 R/W See section 9.3.50/434 R/W 8000_0000h 9.3.49/433 R/W See section 9.3.50/434 R/W 8000_0000h 9.3.49/433 R/W See section 9.3.50/434 R/W 8000_0000h 9.3.49/433 R/W See section 9.3.50/434 R/W 8000_0000h 9.3.49/433 R/W See section 9.3.50/434 W 0000_0000h 9.3.51/435 W 0000_0000h 9.3.51/435 W 0000_0000h 9.3.51/435 W 0000_0000h 9.3.51/435 R/W 0000_000Fh 9.3.52/435 R See section 9.3.53/436 R 0000_0000h 9.3.54/437 W 0000_0000h 9.3.55/438 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 394 Freescale Semiconductor, Inc. Offset address (hex) 6_1040 6_1050 6_1060 6_1070 6_1080 6_1090 6_10A0 6_10B0 Chapter 9 Programmable Interrupt Controller (PIC) PIC memory map (continued) Register name Width (in bits) Access Reset value Section/ page Processor core 1 interprocessor n dispatch register (PIC_IPIDR_CPU10) 32 Processor core 1 interprocessor n dispatch register (PIC_IPIDR_CPU11) 32 Processor core 1 interprocessor n dispatch register (PIC_IPIDR_CPU12) 32 Processor core 1 interprocessor n dispatch register (PIC_IPIDR_CPU13) 32 Processor core 1 current task priority register (PIC_CTPR_CPU1) 32 Processor core 1 who am I register (PIC_WHOAMI_CPU1) 32 Processor core 1 interrupt acknowledge register (PIC_IACK_CPU1) 32 Processor core 1 end of interrupt register (PIC_EOI_CPU1) 32 W 0000_0000h 9.3.56/439 W 0000_0000h 9.3.56/439 W 0000_0000h 9.3.56/439 W 0000_0000h 9.3.56/439 R/W 0000_000Fh 9.3.57/439 R See section 9.3.58/440 R 0000_0000h 9.3.59/441 W 0000_0000h 9.3.60/442 9.3.1 Block revision register 1 (PIC_BRR1) BRR1 provides information about the PIC IP block. Address: 4_0000h base + 0h offset = 4_0000h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IPID IPMJ IPMN W Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 PIC_BRR1 field descriptions Field 0–15 IPID 16–23 IPMJ 24–31 IPMN IP block ID. The major revision of the IP block. The minor revision of the IP block. Description P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 395 PIC memory map/register definition 9.3.2 Block revision register 2 (PIC_BRR2) BRR2 provides information about the IP block integration option and IP block configuration options. Address: 4_0000h base + 10h offset = 4_0010h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W IPINTO Reserved IPCFGO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PIC_BRR2 field descriptions Field 0–7 - 8–15 IPINTO 16–23 - 24–31 IPCFGO This field is reserved. Reserved IP block integration options This field is reserved. Reserved IP block configuration options Description P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 396 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.3.3 Interprocessor n dispatch register (PIC_IPIDRn) The figure below shows the four IPIDRs, one for each interprocessor interrupt channel. Writing to an IPIDR with a bit set causes a self interrupt for a single-core device. Because external bus masters can write to these registers, this feature can serve as a doorbell type interrupt. Address: 4_0000h base + 40h offset + (16d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0–29 30 P1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved P1 P0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_IPIDRn field descriptions Description This field is reserved. Reserved Processor core 1. Specifies if processor core 1 receives the interrupt. This interrupt is multicasting, so both P0 and P1 can be set. NOTE: Reserved in single-processor implementations. 0 Processor core 1 does not receive the interrupt 1 Directs the interrupt to processor core 1 31 Processor core 0 . Determines if processor core 0 receives the interrupt. P0 0 Processor core 0 does not receive the interrupt. 1 Directs the interrupt to processor core 0. 9.3.4 Current task priority register (PIC_CTPR) There is one CTPR per processor core on this device. NOTE CTPR has meaning only for interrupts routed to int . P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 397 PIC memory map/register definition Software must write the priority of the current processor core task in the CTPR for each core. The PIC uses this value for comparison with the priority of incoming interrupts. Given several concurrent incoming interrupts, the highest priority interrupt is asserted to that core if the following apply: • The interrupt is not masked. • The priority of the interrupt is higher than the values in the corresponding CTPR[TASKP] and ISR. Address: 4_0000h base + 80h offset = 4_0080h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved TASKP Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 PIC_CTPR field descriptions Field 0–27 - 28–31 TASKP Description This field is reserved. Reserved Task priority. Indicates the threshold that individual interrupt priorities must exceed for the interrupt request to be serviced. 0000-1111 0000 1111 xVPRn[PRIORITY] must exceed this value for the interrupt request to be serviced. Note the following special cases: Lowest priority. All interrupts except those whose priority are 0 can be serviced. Highest priority. No interrupts are signaled to that processor core. Hardware selects this value on a device hard reset or when the corresponding PIR[Pn] is set. 9.3.5 Who am I register (PIC_WHOAMI) The processor core WHOAMI n register can be read by a processor core to determine its physical connection to the PIC. The value returned when reading this register may be used to determine the value for the destination masks used for dispatching interrupts. Address: 4_0000h base + 90h offset = 4_0090h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ID Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n n n n n P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 398 Freescale Semiconductor, Inc. Field 0–26 - 27–31 ID Chapter 9 Programmable Interrupt Controller (PIC) PIC_WHOAMI field descriptions Description This field is reserved. Reserved Returns the ID of the processor core reading this register. Does not always return zero. 0_0000 0_0001 1_1111 Processor core 0 Processor core 1. (Value not supported in single-processor implementations.) All other devices 9.3.6 Interrupt acknowledge register (PIC_IACK) NOTE IACK has meaning only for interrupts routed to int and should not be accessed for interrupts routed to cint or IRQ_OUT_B . In systems based on processors built on Power Architecture technology, the interrupt acknowledge function occurs as an explicit read operation to a memory-mapped interrupt acknowledge register (IACK). Each processor core has an IACK register assigned to it. Reading IACK returns the interrupt vector corresponding to the highest priority pending interrupt. Reading IACK also has the following side effects: • The associated field in the corresponding interrupt pending register (IPR) is cleared for edge-sensitive interrupts. See Interrupts routed to int . • The corresponding in-service register (ISR) is updated. • The corresponding int output signal from the PIC is negated. Reading IACK when no interrupt is pending returns the spurious vector value, as described in Spurious vector register (PIC_SVR) . Address: 4_0000h base + A0h offset = 4_00A0h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W VECTOR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_IACK field descriptions Field 0–15 - 16–31 VECTOR Description This field is reserved. Reserved Interrupt vector. Vector of the highest pending interrupt P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 399 PIC memory map/register definition 9.3.7 End of interrupt register (PIC_EOI) NOTE EOI has meaning only for interrupts routed to int and should not be accessed for interrupts routed to cint or IRQ_OUT_B. Each core is assigned an EOI register. Writing to EOI signals the end of processing for the highest-priority interrupt (routed to int ) currently in service. It also updates the corresponding ISR n by retiring the highest priority interrupt. Data values written to EOI are ignored, and zero is assumed. Address: 4_0000h base + B0h offset = 4_00B0h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W EOI_CODE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_EOI field descriptions Field 0–27 - 28–31 EOI_CODE This field is reserved. Reserved 0000 (write only) Description 9.3.8 Feature reporting register (PIC_FRR) FRR provides information about interrupt and e500 processor core configurations. It also informs the programming environment of the controller version. Address: 4_0000h base + 1000h offset = 4_1000h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W NIRQ NCPU VID Reserved Reset 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0* 0* 0* 0* n* 0 0 0 0 0 0 1 0 * Notes: • NCPU field: See description for NCPU for reset value. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 400 Freescale Semiconductor, Inc. Field 0–4 - 5–15 NIRQ Chapter 9 Programmable Interrupt Controller (PIC) PIC_FRR field descriptions Description This field is reserved. Reserved Number of interrupts. Holds the binary value of the number of the highest interrupt source supported minus one. 16–18 - 19–23 NCPU 24–31 VID The value is 107 (0x6B or 0b000_0110_1011), because this device supports 108 interrupts: 12 external sources, 64 internal sources (see Table 9-4 ), 8 timer sources, 8 interprocessor sources, 8 messaging sources, and 8 shared message signaled sources. A zero in this field corresponds to one source. This field is reserved. Reserved, should be cleared Number of CPUs. The number of the highest physical CPUs (or e500 processor cores) supported minus one. 00000 Single core-core0 00001 Two cores-core0 and core1 Version ID. Reports the OpenPIC specification revision level supported by this interrupt controller implementation. The VID field's value of two (0x02) corresponds to revision 1.2 which is the revision level currently supported. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 401 PIC memory map/register definition 9.3.9 Global configuration register (PIC_GCR) GCR controls the PIC's operating mode, and allows software to reset the PIC. Address: 4_0000h base + 1020h offset = 4_1020h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved RST M W Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W Reset 0 Field 0 RST 1 2 M 3–31 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_GCR field descriptions Description Reset. Setting RST forces the PIC to be reset. Cleared automatically when the reset sequence is complete. See Resetting the PIC for more information. This field is reserved. Reserved Mode. PIC operating mode. Modes of operation provides details about these modes. 0 Pass-through mode. On-chip PIC is disabled and interrupts detected on IRQ0 are passed directly to core 0. 1 Mixed mode. Interrupts are handled by the normal priority and delivery mechanisms of the PIC. This field is reserved. Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 402 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.3.10 Vendor identification register (PIC_VIR) VIR is defined by the OpenPIC specifications and is provided for compliance. The zero value for VIR[VENDORID] indicates a generic OpenPIC-compliant device, which makes the other VIR fields meaningless. Address: 4_0000h base + 1080h offset = 4_1080h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W STEP DEVICE_ID VENDOR_ID Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_VIR field descriptions Field 0–7 - 8–15 STEP 16–23 DEVICE_ID 24–31 VENDOR_ID Description This field is reserved. Reserved Stepping. Indicates the silicon revision for this device. Has no meaning if VENDOR_ID value is zero. Device identification. Vendor-specified identifier for this device. Has no meaning if VENDOR_ID is zero. Vendor identification. Specifies the manufacturer of this part. A value of zero implies a generic OpenPICcompliant device. 9.3.11 Processor core initialization register (PIC_PIR) PIR provides a way for software to generate a core reset. Setting P1 or P0 causes the respective core 0 _hreset orcore1_hreset signal to assert. Note that after requesting a core reset using this register the applicable bit should not be cleared until the requested core reset has occurred.However, if one core is used to reset another one, the core being reset can effectively be held off indefinitely from issuing its initial boot vector fetch to the platform by leaving its appropriate PIR[Px] bit asserted. Clearing it releases the core to fetch. Note that although the OpenPIC architecture was defined to support up to 32 processing cores, only fields corresponding to the number of cores on the device are implemented. Address: 4_0000h base + 1090h offset = 4_1090h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 403 PIC memory map/register definition Bit 16 R W Reset 0 Field 0–29 30 P1 31 P0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved P1 P0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_PIR field descriptions Description This field is reserved. Reserved Processor core 1 reset. Setting this bit causes the PIC to assert the core1_hreset signal. Reserved in single-processor implementations. Processor core 0 reset. Setting this bit causes the PIC to assert the core0_hreset signal. 9.3.12 Interprocessor interrupt n vector/priority register (PIC_IPIVPRn) IPIVPRs contain the interrupt vector and priority fields for the four interprocessor interrupt channels. There is one vector/priority register per channel. The VECTOR and PRIORITY values should not be changed while IPIVPR n [A] is set. See Flow of interrupt control for information on IPR and ISR. Address: 4_0000h base + 10A0h offset + (16d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R A MSK W Reserved PRIORITY Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0 MSK 1 A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VECTOR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_IPIVPRn field descriptions Description Mask. Mask interrupts to int from this source. 0 An interrupt request is generated if the corresponding IPR bit is set. 1 Further interrupts from this source are disabled. Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values should not be changed while this bit is set. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 404 Freescale Semiconductor, Inc. Field 2–11 - 12–15 PRIORITY 16–31 VECTOR Chapter 9 Programmable Interrupt Controller (PIC) PIC_IPIVPRn field descriptions (continued) Description 0 No current interrupt activity associated with this source. 1 The interrupt field for this source is set in the IPR or ISR. This field is reserved. Reserved Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of 0 inhibits signaling of this interrupt to the core. Affects only interrupts routed to int. Vector (Affects only interrupts routed to int). Contains the value returned when IACK is read and this interrupt resides in the corresponding interrupt request register (IRR) for that core, as shown in Figure 9-331 . 9.3.13 Spurious vector register (PIC_SVR) SVR contains the 16-bit vector returned to the e500 processor core when the corresponding IACK register is read for a spurious interrupt. Address: 4_0000h base + 10E0h offset = 4_10E0h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved VECTOR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PIC_SVR field descriptions Field 0–15 - 16–31 VECTOR Description This field is reserved. Reserved Spurious interrupt vector. Value returned when IACK is read during a spurious vector fetch. Spurious vector generation gives information about the conditions that may cause a spurious vector fetch. 9.3.14 Timer frequency reporting register group X (PIC_TFRRn) The TFRRs are written by software to report the clocking frequency of the PIC timers. Note that although TFRRs are read/write, the PIC ignores the register values. Address: 4_0000h base + 10F0h offset + (4096d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W FREQ Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 405 PIC memory map/register definition PIC_TFRRn field descriptions Field 0–31 FREQ Description Timer frequency (in ticks/second (Hz)). Used to communicate the frequency of the global timers' clock source, (either the CCB clock or the frequency of the RTC signal), to user software. TFRRx is set only by software for later use by other applications and its value in no way affects the operating frequency of the global timers. The timers operate at a ratio of this clock frequency, as set by TCRx[CLKR]. See Timer control register group n (PIC_TCRn) . 9.3.15 Global timer n current count register group A (PIC_GTCCRAn) The GTCCRs contain the current count for each of the four PIC timers in each of the two groups. Address: 4_0000h base + 1100h offset + (64d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 R TOG COUNT 10 11 12 13 14 15 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R COUNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_GTCCRAn field descriptions Field 0 TOG 1–31 COUNT Description Toggle. Toggles when the current count decrements to zero. Cleared when GTBCR xn [CI] goes from 1 to 0. Current count. Decremented while GTBCR xn [CI] is zero. When the timer count reaches zero, an interrupt is generated (provided it is not masked), the toggle bit is inverted, and the count is reloaded. For noncascaded timers, the reload value is the contents of the corresponding GTBCR xn . Cascaded timers are reloaded with either all ones, or the GTBCR xn contents, depending on the value of TCRn[ROVR]. See Timer control register group n (PIC_TCRn) , for more details. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 406 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.3.16 Global timer n base count register group A (PIC_GTBCRAn) The GTBCRs contain the base counts for each of the four PIC timers in each of the two groups. This value is reloaded into the corresponding GTCCR xn when the current count reaches zero. Note that when zero is written to the base count field, (and GTCCR xn [CI] = 0), the timer generates an interrupt on every timer cycle. Address: 4_0000h base + 1110h offset + (64d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W CI BASE_CNT Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W BASE_CNT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_GTBCRAn field descriptions Field 0 CI 1–31 BASE_CNT Count inhibit. Always set following reset Description 0 Counting enabled 1 Counting inhibited Base count. When CI transitions from 1 to 0, this value is copied into the corresponding GTCCR xn and the toggle bit is cleared. If CI is already cleared (counting is in progress), the base count is copied to the GTCCR xn at the next zero crossing of the current count. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 407 PIC memory map/register definition 9.3.17 Global timer n vector/priority register group A (PIC_GTVPRAn) The GTVPRs contain the interrupt vector and the interrupt priority values for the timers. They also contain the mask and activity fields for all the timers. See Flow of interrupt control for information on IPR and ISR. Address: 4_0000h base + 1120h offset + (64d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R A MSK W Reserved PRIORITY Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0 MSK 1 A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VECTOR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_GTVPRAn field descriptions Description Mask. Mask interrupts to int from this source. 0 An interrupt request is generated if the corresponding IPR bit is set. 1 Further interrupts from this source are disabled. Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values should not be changed while this bit is set. 2–11 - 12–15 PRIORITY 16–31 VECTOR 0 No current interrupt activity associated with this source. 1 The interrupt field for this source is set in the IPR or ISR. This field is reserved. Reserved Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of 0 inhibits signaling of this interrupt to the core. Affects only interrupts routed to int. Vector (Affects only interrupts routed to int). Contains the value returned when IACK is read and this interrupt resides in the corresponding interrupt request register (IRR) for that core, as shown in Figure 9-331 . P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 408 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.3.18 Global timer n destination register group A (PIC_GTDRAn) The GTDR xn registers control the destination (core) to which each timer's interrupt is directed. Note that GTDR xn bits can be set independent of each other and that either P1 or P0 or both can be set for this type of interrupt . Address: 4_0000h base + 1130h offset + (64d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved P1 P0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PIC_GTDRAn field descriptions Field 0–29 - 30 P1 Description This field is reserved. Reserved Processor core 1. This interrupt is multicasting, so both P0 and P1 can be set. NOTE: Reserved in single-processor implementations. 0 Processor core 1 does not receive this interrupt 1 Directs the timer interrupt to processor core 1 31 Processor core 0 . Default destination after PIC is reset. Both P0 and P1 can be set. P0 0 Processor core 0 does not receive this interrupt. 1 Directs the timer interrupt to processor core 0 . 9.3.19 Timer control register group n (PIC_TCRn) The TCR n registers provide various configuration options such as count frequency and roll-over behavior for the timers. There are two choices for the clock source for the timers: a selectable frequency ratio from the CCB bus clock, or the RTC signal. TCRs can be cascaded to create timers larger than the default 31-bit global timers. Timer cascade fields allow configuration of up to two 63-bit timers, one 95-bit timer, or one 127-bit timer (within each group). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 409 PIC memory map/register definition With one exception mentioned below, the value reloaded into a timer is determined by its roll-over control field, TCR n [ROVR]. Setting TCR n [ROVR] causes its GTCCR xn to roll over to all ones when the count reaches zero. This is equivalent to reloading the count register with 0xFFFF_FFFF instead of its base count value. Clearing a timer's associated ROVR bit ensures the timer always reloads with its base count value. When timers are cascaded, the last (most significant) counter in the cascade also affects their roll-over behavior. Cascaded timers always reload their base count when the most significant counter has decremented to zero, regardless of the TCR n [ROVR] settings. For example, timers 0-2 can be cascaded to generate one interrupt per hour. Given a CCB clock frequency of 333 MHz, letting the timer clock frequency default to 1/8 th the system clock, (TCR n [CLKR] = 0 sets a clock ratio of 8), provides a basic input of 41.625 MHz to timer 0. Setting timer 0 to count 41,625,000 (0x27B_25A8) timer clock cycles generates one output per second. Setting both timers 1 and 2 to 59, and cascading all three timers, generates one interrupt every hour from timer 2. Table 9-49. Parameters for Hourly Interrupt Timer Cascade Example System Clock Clock Ratio 333 MHz 1/8 Timer Clock 41.625 MHz Timer 0 Count 41.625 x 10 6 (0x027B_25A8) Timer 1 Count Timer 2 Count 59 1 (0x0000_0036) 59 (0x0000_0036) 1. Counting down from 59 through 0 requires 60 ticks. 1. Counting down from 59 through 0 requires 60 ticks. 1. Counting down from 59 through 0 requires 60 ticks. Figure 9-47. Example Calculation for Cascaded Timers Address: 4_0000h base + 1300h offset + (4096d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W Reserved ROVR Reserved RTM Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0–4 5–7 ROVR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved CLKR Reserved CASC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_TCRn field descriptions Description This field is reserved. Reserved Roll-over control for cascaded timers only. Specifies behavior when count reaches zero by identifying the source of the reload value. Cascaded timers are always reloaded with their base count value when the Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 410 Freescale Semiconductor, Inc. Field 8–14 15 RTM 16–21 - 22–23 CLKR 24–28 - 29–31 CASC Chapter 9 Programmable Interrupt Controller (PIC) PIC_TCRn field descriptions (continued) Description more significant timer in the cascade (the upstream timer) is zero. Bits 5-7 correspond to timers 2-0. Note that global timer 3 always reloads with its GTBCR xn . 0 The timer does not roll over. When the count reaches zero, GTCCR xn is reloaded with the GTBCR xn value. 1 Timer rolls over at zero to all ones. (When the count reaches zero, GTCCR xn is reloaded with 0xFFFF_FFFF.) 000 All timers reload with base count. 001 Timers 1 and 2 reload with base count, timer 0 rolls over (reloads with 0xFFFF_FFFF). 010 Timers 0 and 2 reload with base count, timer 1 rolls over (reloads with 0xFFFF_FFFF). 011 Timer 2 reloads with base count, timers 0 and 1 roll over (reload with 0xFFFF_FFFF). 100 Timers 0 and 1 reload with base count, timer 2 rolls over (reloads with 0xFFFF_FFFF). 101 Timer 1 reloads with base count, timers 0 and 2 roll over (reload with 0xFFFF_FFFF). 110 Timer 0 reloads with base count, timers 1 and 2 roll over (reload with 0xFFFF_FFFF). 111 Timers 0, 1, and 2 roll over (reload with 0xFFFF_FFFF). This field is reserved. Reserved Real time mode. Specifies the clock source for the PIC timers. 0 Timer clock frequency is a ratio of the frequency of the CCB clock as determined by the CLKR field. This is the default value. 1 The RTC signal is used to clock the PIC timers. If this bit is set, the CLKR field has no meaning. This field is reserved. Reserved Clock ratio. Specifies the ratio of the timer frequency to the CCB clock. The following are supported: 00 Default. Divide by 8 01 Divide by 16 10 Divide by 32 11 Divide by 64 This field is reserved. Reserved Cascade timers. Specifies the output of particular global timers as input to others. 000 Default. Timers not cascaded 001 Cascade timers 0 and 1 010 Cascade timers 1 and 2 011 Cascade timers 0, 1, and 2 100 Cascade timers 2 and 3 101 Cascade timers 0 and 1; timers 2 and 3 110 Cascade timers 1, 2, and 3 111 Cascade timers 0, 1, 2, and 3 1. Counting down from 59 through 0 requires 60 ticks. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 411 PIC memory map/register definition 9.3.20 External interrupt summary register (PIC_ERQSR) NOTE ERQSR fields report only the current logic level of IRQ0IRQ11 pins. These fields were designed to work with levelsensitive interrupts; values returned for edge-sensitive interrupts may be unreliable. Address: 4_0000h base + 1308h offset = 4_1308h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EINTn W Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_ERQSR field descriptions Field 0–11 EINTn 12–31 - Description External interrupts signal 0-11 status. Bit 0 represents EINT0. Bit 11 represents EINT 11. 0 The corresponding external interrupt signal is at a low logic level . 1 The corresponding external interrupt signal is at a high logic level . This field is reserved. Reserved 9.3.21 IRQ_OUT_B summary register 0 (PIC_IRQSR0) Address: 4_0000h base + 1310h offset = 4_1310h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W EXTn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_IRQSR0 field descriptions Field 0–19 - 20–31 EXTn Description This field is reserved. Reserved External interrupts 0-11 . Each bit corresponds to a unique interrupt according to the following: Bit Interrupt 20 IRQ0 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 412 Freescale Semiconductor, Inc. Field Chapter 9 Programmable Interrupt Controller (PIC) PIC_IRQSR0 field descriptions (continued) 21 IRQ1 … 31 IRQ11 Description 0 The corresponding interrupt is not active or not routed to IRQ_OUT_B. 1 The corresponding interrupt is active and routed to IRQ_OUT_B (if the corresponding x IDRn[EP] is set). 9.3.22 IRQ_OUT_B summary register 1 (PIC_IRQSR1) Address: 4_0000h base + 1320h offset = 4_1320h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R INTn W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_IRQSR1 field descriptions Field 0–31 INTn Description Internal interrupts 0-31 status. Bit 0 represents INT0. Bit 31 represents INT31. 0 The corresponding interrupt is not active or not routed to IRQ_OUT_B . 1 The corresponding interrupt is active and is routed to IRQ_OUT_B (that is, if the corresponding x IDRn[EP] is set). 9.3.23 IRQ_OUT_B summary register 2 (PIC_IRQSR2) Address: 4_0000h base + 1324h offset = 4_1324h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R INTn W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_IRQSR2 field descriptions Field 0–31 INTn Description Internal interrupts 32-63 status. Bit 0 represents INT32. Bit 31 represents INT63. 0 The corresponding interrupt is not active or not routed to IRQ_OUT_B . 1 The corresponding interrupt is active and is routed to IRQ_OUT_B , if the corresponding x IDRn[EP] is set. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 413 PIC memory map/register definition 9.3.24 Critical interrupt summary register 0 (PIC_CISR0) Address: 4_0000h base + 1330h offset = 4_1330h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W EXTn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_CISR0 field descriptions Field 0–19 - 20–31 EXTn Description This field is reserved. Reserved External interrupts 0-11. Bit 20 represents IRQ0. Bit 31 represents IRQ11. 0 The corresponding interrupt is not active or not routed to cint 0 or cint1 . 1 The corresponding interrupt is active and is routed to cint 0 or cint1 (if the corresponding x IDRn[CI] is set). 9.3.25 Critical interrupt summary register 1 (PIC_CISR1) Address: 4_0000h base + 1340h offset = 4_1340h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R INTn W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_CISR1 field descriptions Field 0–31 INTn Description Internal interrupts 0-31. Bit 0 represents INT0. Bit 31 represents INT31. 0 Corresponding interrupt is not active or not routed to cint 0 or cint1 . 1 The corresponding interrupt is active and is routed to the cint 0 or cint1 (if the corresponding x IDRn[CI] is set). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 414 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.3.26 Critical interrupt summary register 2 (PIC_CISR2) Address: 4_0000h base + 1344h offset = 4_1344h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R INTn W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_CISR2 field descriptions Field 0–31 INTn Description Internal interrupts 32-63. Bit 0 represents INT32. Bit 31 represents INT63. 0 Corresponding interrupt is not active or not routed to cint 0 or cint1 . 1 The corresponding interrupt is active and is routed to the cint 0 or cint1 , if the corresponding x IDRn[CI] is set. 9.3.27 Performance monitor n mask register 0 (PIC_PMnMR0) Each PM n MR0 register is matched with a PM n MR1 and a PM n MR2 register. Because each unreserved bit in the 96-bit vector (PM n MR0/1/2) specifies a different interrupt, only one bit in the 96-bit vector can be unmasked at a time. Unmasking more than 1 bit per set is considered a programming error and results in unpredictable behavior. Address: 4_0000h base + 1350h offset + (32d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W MShI IPI TIMER MSG EXT Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PIC_PMnMR0 field descriptions Field 0–7 MShI 8–11 IPI Shared message signaled interrupts 0-7 Description 0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 The corresponding interrupt does not generate a performance monitor event. Interprocessor interrupts 0-3 0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 The corresponding interrupt does not generate a performance monitor event. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 415 PIC memory map/register definition PIC_PMnMR0 field descriptions (continued) Field 12–15 TIMER Description Timer interrupts 0-3 (Group A and Group B: Each bit represents an OR of the event for the correspondingly numbered timer in Group A and that in Group B). 16–19 MSG 0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 The corresponding interrupt does not generate a performance monitor event. Message interrupts 0-7 Bit 0 is used for MSG0 and MSG4 Bit 1 is used for MSG1 and MSG5 Bit 2 is used for MSG2 and MSG6 Bit 3 is used for MSG3 and MSG7 20–31 EXT 0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 The corresponding interrupt does not generate a performance monitor event. External interrupts IRQ[0:11 ] 0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 The corresponding interrupt does not generate a performance monitor event. 9.3.28 Performance monitor n mask register 1 (PIC_PMnMR1) Address: 4_0000h base + 1360h offset + (32d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W INT Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PIC_PMnMR1 field descriptions Field 0–31 INT Internal interrupts 0-31 Description 0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 The corresponding interrupt does not generate a performance monitor event. 9.3.29 Performance monitor n mask register 2 (PIC_PMnMR2) Address: 4_0000h base + 1364h offset + (32d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W INT Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 416 Freescale Semiconductor, Inc. Field 0–31 INT Chapter 9 Programmable Interrupt Controller (PIC) PIC_PMnMR2 field descriptions Internal interrupts 32-63 Description 0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 The corresponding interrupt does not generate a performance monitor event. 9.3.30 Message register n (PIC_MSGRn) The message registers (MSGR0-MSGR 7 ) can contain a 32-bit message. For (MSGR4MSGR7), see Message register n (PIC_MSGRan) Address: 4_0000h base + 1400h offset + (16d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W MSG Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_MSGRn field descriptions Field 0–31 MSG Description Message. Contains the 32-bit message data. 9.3.31 Message enable register (PIC_MER) The MER contains the enable bits for each message register. The enable bit must be set to enable interrupt generation when the corresponding message register is written. When bits in MER are set to mask message interrupts, an interrupt is not generated if the message register is written while it is masked in MER and the MER bit is then cleared. To mask the interrupt without loss, set MIVPR n [MSK] (See Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPRn) ). MER should be set to 0x0000_000F at reset and then left unchanged during normal operation. Address: 4_0000h base + 1500h offset = 4_1500h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved En Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 417 PIC memory map/register definition PIC_MER field descriptions Field 0–27 - 28–31 En Description This field is reserved. Reserved Enable 3-enable 0 . Used to enable interrupt generation for MSGRn (where n = 0- 3 ). 0 Interrupt generation for MSGRn disabled. 1 Interrupt generation for MSGRn enabled. 9.3.32 Message status register (PIC_MSR) The message status register (MSR) contains status bits for each message register. A status bit is set when the corresponding messaging interrupt is active. Writing a 1 to a status bit clears the corresponding message interrupt and the status bit. Address: 4_0000h base + 1510h offset = 4_1510h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved Sn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_MSR field descriptions Field 0–27 - 28–31 Sn Description This field is reserved. Reserved Status 3-status 0 . Reports status of messaging interrupt n . Writing a 1 clears this field. 0 Messaging interrupt n is not active. 1 Messaging interrupt n is active. 9.3.33 Shared message signaled interrupt register n (PIC_MSIRn) The eight MSIRs indicate which of the up to 32 interrupt sources sharing the message register have pending interrupts. These registers are cleared when read. A write to these registers has no effect. NOTE After soft reset, read the MSIRs to ensure that any interrupts previously pending are cleared. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 418 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) Address: 4_0000h base + 1600h offset + (16d × i), where i=0d to 7d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SHn W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_MSIRn field descriptions Field 0–31 SHn Message sharer n has a pending interrupt. Description 9.3.34 Shared message signaled interrupt status register (PIC_MSISR) MSISR contains the status bits for the shared message signaled interrupts. A status bit is set when the corresponding MSIR has an active interrupt. The status bit is 0 if all the corresponding shared interrupt sources are cleared for that MSIR. Address: 4_0000h base + 1720h offset = 4_1720h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Sn Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_MSISR field descriptions Field 0–23 - 24–31 Sn This field is reserved. Reserved Status n. 0 MSIRn is not active. 1 MSIRn has an active interrupt. Description P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 419 PIC memory map/register definition 9.3.35 Shared message signaled interrupt index register (PIC_MSIIR) MSIIR provides the mechanism for setting an interrupt in the MSIRs. When MSIIR is written, MSIIR[SRS] selects the register in which an interrupt bit is to be set; MSIIR[IBS] selects the shared interrupt field in the selected MSIR register to be set. MSIIR is primarily intended to support PCI Express MSIs. Address: 4_0000h base + 1740h offset = 4_1740h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W SRS IBS Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_MSIIR field descriptions Field 0–2 SRS Description Shared interrupt register select. Selects the MSIR to be written Example settings: 000 MSIR 0 001 MSIR 1 010 MSIR 2 ... 111 MSIR 7 3–7 Interrupt bit select-Selects the bit to set in the MSIR IBS Example settings: 8–31 - 00000 00001 00010 Set field SH0 (bit 31) Set field SH1 (bit 30) Set field SH2 (bit 29) ... 11111 Set field SH31 (bit 0) This field is reserved. Reserved P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 420 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.3.36 Global timer n current count register group B (PIC_GTCCRBn) The GTCCRs contain the current count for each of the four PIC timers in each of the two groups. Address: 4_0000h base + 2100h offset + (64d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 R TOG COUNT 10 11 12 13 14 15 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0 TOG 1–31 COUNT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_GTCCRBn field descriptions Description Toggle. Toggles when the current count decrements to zero. Cleared when GTBCR xn [CI] goes from 1 to 0. Current count. Decremented while GTBCR xn [CI] is zero. When the timer count reaches zero, an interrupt is generated (provided it is not masked), the toggle bit is inverted, and the count is reloaded. For noncascaded timers, the reload value is the contents of the corresponding GTBCR xn . Cascaded timers are reloaded with either all ones, or the GTBCR xn contents, depending on the value of TCRn[ROVR]. See Timer control register group n (PIC_TCRn) for more details. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 421 PIC memory map/register definition 9.3.37 Global timer n base count register group B (PIC_GTBCRBn) The GTBCRs contain the base counts for each of the four PIC timers in each of the two groups. This value is reloaded into the corresponding GTCCR xn when the current count reaches zero. Note that when zero is written to the base count field, (and GTCCR xn [CI] = 0), the timer generates an interrupt on every timer cycle. Address: 4_0000h base + 2110h offset + (64d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W CI BASE_CNT Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W BASE_CNT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_GTBCRBn field descriptions Field 0 CI 1–31 BASE_CNT Count inhibit. Always set following reset Description 0 Counting enabled 1 Counting inhibited Base count. When CI transitions from 1 to 0, this value is copied into the corresponding GTCCR xn and the toggle bit is cleared. If CI is already cleared (counting is in progress), the base count is copied to the GTCCR xn at the next zero crossing of the current count. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 422 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.3.38 Global timer n vector/priority register group B (PIC_GTVPRBn) The GTVPRs contain the interrupt vector and the interrupt priority values for the timers. They also contain the mask and activity fields for all the timers. See Flow of interrupt control for information on IPR and ISR. Address: 4_0000h base + 2120h offset + (64d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R A MSK W Reserved PRIORITY Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0 MSK 1 A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VECTOR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_GTVPRBn field descriptions Description Mask. Mask interrupts to int from this source. 0 An interrupt request is generated if the corresponding IPR bit is set. 1 Further interrupts from this source are disabled. Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values should not be changed while this bit is set. 2–11 - 12–15 PRIORITY 16–31 VECTOR 0 No current interrupt activity associated with this source. 1 The interrupt field for this source is set in the IPR or ISR. This field is reserved. Reserved Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of 0 inhibits signaling of this interrupt to the core. Affects only interrupts routed to int. Vector (Affects only interrupts routed to int). Contains the value returned when IACK is read and this interrupt resides in the corresponding interrupt request register (IRR) for that core, as shown in Figure 9-331 . P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 423 PIC memory map/register definition 9.3.39 Global timer n destination register group B (PIC_GTDRBn) The GTDR xn registers control the destination (core) to which each timer's interrupt is directed. Note that GTDR xn bits can be set independently of each other and that either P1 or P0 or both can be set for this type of interrupt . Address: 4_0000h base + 2130h offset + (64d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved P1 P0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PIC_GTDRBn field descriptions Field 0–29 - 30 P1 Description This field is reserved. Reserved Processor core 1. This interrupt is multicasting, so both P0 and P1 can be set. NOTE: Reserved in single-processor implementations. 0 Processor core 1 does not receive this interrupt 1 Directs the timer interrupt to processor core 1 31 Processor core 0 . Default destination after PIC is reset. Both P0 and P1 can be set. P0 0 Processor core 0 does not receive this interrupt. 1 Directs the timer interrupt to processor core 0 . 9.3.40 Message register n (PIC_MSGRan) The message registers (MSGR0-MSGR 7 ) can contain a 32-bit message. For (MSGR0MSGR3), see Message register n (PIC_MSGRn) Address: 4_0000h base + 2400h offset + (16d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W MSG Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 424 Freescale Semiconductor, Inc. Field 0–31 MSG Chapter 9 Programmable Interrupt Controller (PIC) PIC_MSGRan field descriptions Description Message. Contains the 32-bit message data. 9.3.41 Message enable register (PIC_MERa) The MER contains the enable bits for each message register. The enable bit must be set to enable interrupt generation when the corresponding message register is written. When bits in MER are set to mask message interrupts, an interrupt is not generated if the message register is written while it is masked in MER and the MER bit is then cleared. To mask the interrupt without loss, set MIVPR n [MSK]. (See Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPRn) .) MER should be set to 0x0000_000F at reset and then left unchanged during normal operation. Address: 4_0000h base + 2500h offset = 4_2500h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved En Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_MERa field descriptions Field 0–27 - 28–31 En Description This field is reserved. Reserved Enable 3-enable 0 . Used to enable interrupt generation for MSGRn (where n = 0-3 ). 0 Interrupt generation for MSGRn disabled. 1 Interrupt generation for MSGRn enabled. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 425 PIC memory map/register definition 9.3.42 Message status register (PIC_MSRa) The message status register (MSR) contains status bits for each message register. A status bit is set when the corresponding messaging interrupt is active. Writing a 1 to a status bit clears the corresponding message interrupt and the status bit. Address: 4_0000h base + 2510h offset = 4_2510h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved Sn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_MSRa field descriptions Field 0–27 - 28–31 Sn Description This field is reserved. Reserved Status 3-status 0 . Reports status of messaging interrupt n . Writing a 1 clears this field. 0 Messaging interrupt n is not active. 1 Messaging interrupt n is active. 9.3.43 External interrupt n (IRQn) vector/priority register (PIC_EIVPRn) The EIVPRs contain polarity and sense fields for the external interrupts, that is, those caused by the assertion of any of IRQ[ 0:11 ]. See Flow of interrupt control for information on IPR and ISR. Address: 4_0000h base + 1_0000h offset + (32d × i), where i=0d to 11d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R A MSK W Reserved P S Reserved PRIORITY Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R VECTOR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 426 Freescale Semiconductor, Inc. Field 0 MSK 1 A 2–7 8 P 9 S 10–11 - 12–15 PRIORITY 16–31 VECTOR Chapter 9 Programmable Interrupt Controller (PIC) PIC_EIVPRn field descriptions Description Mask. Mask interrupts from this source. MSK affects only interrupts routed to int. 0 An interrupt request is generated if the corresponding IPR bit is set. 1 Further interrupts from this source are disabled. Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values should not be changed while this bit is set. Affects only interrupts routed to int. 0 No current interrupt activity associated with this source. 1 The interrupt field for this source is set in the IPR or ISR. This field is reserved. Reserved Polarity. Specifies the polarity for the external interrupt. 0 Polarity is active-low or negative edge-triggered. 1 Polarity is active-high or positive edge-triggered. Sense. Specifies the sense for external interrupts. NOTE: If an IRQ n signal is used to receive INT x signals from one of the PCI Express ports as a root complex, S must be set to be level-sensitive. 0 The external interrupt is edge sensitive. 1 The external interrupt is level sensitive. This setting must be used to direct the interrupt to IRQ_OUT_B or cint. This field is reserved. Reserved Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of 0 inhibits signaling of this interrupt to the core. Affects only interrupts routed to int. Vector (Affects only interrupts routed to int). Contains the value returned when IACK is read and this interrupt resides in the corresponding interrupt request register (IRR) for that core, as shown in Figure 9-331 . P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 427 PIC memory map/register definition 9.3.44 External interrupt n (IRQn) destination register (PIC_EIDRn) The EIDRs control the destination of external interrupts caused by the assertion of any of IRQ[ 0:11 ]. Only one destination bit may be set; otherwise, behavior is undefined. Address: 4_0000h base + 1_0010h offset + (32d × i), where i=0d to 11d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W EP CI0 CI1 Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0 EP 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved P1 P0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PIC_EIDRn field descriptions Description External signal. Allows interrupt to be serviced externally. EP should be set only for level-sensitive external interrupts (EIVPRn[S]= 1). Setting for edge-sensitive does not provide reliable interrupt response. 0 Interrupt is not routed to IRQ_OUT_B . 1 Interrupt is routed to IRQ_OUT_B for external service. 1 Critical interrupt 0. Cin fields should be set only for level-sensitive external interrupts (EIVPRn[S]= 1). CI0 Setting them for edge-sensitive does not provide reliable interrupt response. 0 Processor core 0 does not receive this interrupt. 1 Directs the external interrupt to processor core 0 by causing the cint0 output signal from the PIC to assert. See Interrupts to the e500 processor core . 2 Critical interrupt 1. Cin fields should be set only for level-sensitive external interrupts (EIVPRn[S]= 1). CI1 Setting them for edge-sensitive does not provide reliable interrupt response. Reserved in single-processor implementations. 3–29 - 30 P1 0 Processor core 1 does not receive this interrupt. 1 Directs the external interrupt to processor core 1 by causing the cint1 output signal from the PIC to assert. See Interrupts to the e500 processor core . This field is reserved. Reserved Processor core 1. Indicates whether processor core 1 receives the interrupt through int. NOTE: Reserved in single-processor implementations. 0 Processor core 1 does not receive this interrupt. 1 Directs the interrupt to processor core 1 through the assertion of int1 . 31 Processor core 0 . Indicates whether processor core 0 receives the interrupt. P0 The default destination is for processor core 0 to receive this external interrupt after the PIC is reset. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 428 Freescale Semiconductor, Inc. Field Chapter 9 Programmable Interrupt Controller (PIC) PIC_EIDRn field descriptions (continued) Description 0 Processor core 0 does not receive this interrupt. 1 Directs the interrupt to processor core 0 through the assertion of int0 . 9.3.45 Internal interrupt n vector/priority register (PIC_IIVPRn) The IIVPRs have the same fields and format as the GTVPRs, except that they apply to the internal interrupt sources listed in Table 9-4 . These interrupts are all level-sensitive. See Flow of interrupt control for information on IPR and ISR. NOTE Because all internal interrupts are active-high, clearing the polarity field, IIVPR n [P], disables that interrupt. Care should be taken to ensure this field is set during initialization and that it is not inadvertently corrupted when loading or reloading IIVPRs with priority, mask, or vector data. Address: 4_0000h base + 1_0200h offset + (32d × i), where i=0d to 63d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R A MSK W Reserved P Reserved PRIORITY Reset 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0 MSK 1 A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VECTOR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_IIVPRn field descriptions Description Mask. Mask interrupts from this source. MSK affects only interrupts routed to int. 0 An interrupt request is generated if the corresponding IPR bit is set. 1 Further interrupts from this source are disabled. Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values should not be changed while this bit is set. Affects only interrupts routed to int. 0 No current interrupt activity associated with this source. 1 The interrupt field for this source is set in the IPR or ISR. 2–7 This field is reserved. - Reserved Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 429 PIC memory map/register definition PIC_IIVPRn field descriptions (continued) Field 8 P Description Polarity. Specifies the polarity for the internal interrupt. Note: Because all internal interrupts are activehigh, clearing this bit disables the interrupt. 9–11 - 12–15 PRIORITY 16–31 VECTOR 0 Interrupt polarity is active-low. This value disables the interrupt. 1 Interrupt polarity is active-high. This field is reserved. Reserved Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of 0 inhibits signaling of this interrupt to the core. Affects only interrupts routed to int. Vector (Affects only interrupts routed to int). Contains the value returned when IACK is read and this interrupt resides in the corresponding interrupt request register (IRR) for that core, as shown in Figure 9-331 . 9.3.46 Internal interrupt n destination register (PIC_IIDRn) The IIDRs have the same fields and format as EIVDRs, except that they apply to the internal interrupt sources listed in Table 9-4 . Only one destination bit may be set; otherwise, behavior is undefined. Address: 4_0000h base + 1_0210h offset + (32d × i), where i=0d to 63d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W EP CI0 CI1 Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved P1 P0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Field 0 EP 1 CI0 2 CI1 PIC_IIDRn field descriptions Description External signal. Allows internal interrupt to be serviced externally. 0 Interrupt is not routed to IRQ_OUT_B . 1 Interrupt is routed to IRQ_OUT_B for external service. Critical interrupt 0. See Interrupts to the e500 processor core for more information. 0 Processor core 0 does not receive this interrupt. 1 Directs the internal interrupt to processor core 0 by causing the cint0 output signal from the PIC to assert. Critical interrupt 1. See Interrupts to the e500 processor core , for more information. Reserved in singleprocessor implementations. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 430 Freescale Semiconductor, Inc. Field 3–29 30 P1 31 P0 Chapter 9 Programmable Interrupt Controller (PIC) PIC_IIDRn field descriptions (continued) Description 0 Processor core 1 does not receive this interrupt. 1 Directs the internal interrupt to processor core 1 by causing the cint1 output signal from the PIC to assert. This field is reserved. Reserved Processor core 1. Indicates whether processor core 1 receives the interrupt through int. NOTE: Reserved in single-processor implementations. 0 Processor core 1 does not receive this interrupt. 1 Directs the interrupt to processor core 1 through the assertion of int1 . Processor core 0 . Indicates whether processor core 0 receives the interrupt. The default destination is for processor core 0 to receive this external interrupt after the PIC is reset. 0 Processor core 0 does not receive this interrupt. 1 Directs the interrupt to processor core 0 through the assertion of int0 . 9.3.47 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPRn) The MIVPRs have the same fields and format as the GTVPRs, except they apply to messaging interrupts. See Flow of interrupt control for information on IPR and ISR. Address: 4_0000h base + 1_1600h offset + (32d × i), where i=0d to 7d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R A MSK W Reserved PRIORITY Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R VECTOR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_MIVPRn field descriptions Field 0 MSK Description Mask. Mask interrupts from this source. MSK affects only interrupts routed to int. 0 An interrupt request is generated if the corresponding IPR bit is set. 1 Further interrupts from this source are disabled. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 431 PIC memory map/register definition PIC_MIVPRn field descriptions (continued) Field 1 A Description Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values should not be changed while this bit is set. Affects only interrupts routed to int. 2–11 - 12–15 PRIORITY 16–31 VECTOR 0 No current interrupt activity associated with this source. 1 The interrupt field for this source is set in the IPR or ISR. This field is reserved. Reserved Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of 0 inhibits signaling of this interrupt to the core. Affects only interrupts routed to int. Vector (Affects only interrupts routed to int). Contains value returned when IACK is read and this interrupt resides in the corresponding interrupt request register (IRR) for that core, as shown in Figure 9-331 . 9.3.48 Messaging interrupt n (MSGn) destination register (PIC_MIDRn) The messaging interrupt destination registers (MIDRs) control the destination for the messaging interrupts. Only one destination bit may be set; otherwise, behavior is undefined. Address: 4_0000h base + 1_1610h offset + (32d × i), where i=0d to 7d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved P1 P0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PIC_MIDRn field descriptions Field 0–29 - 30 P1 Description This field is reserved. Reserved Processor core 1. Indicates whether processor core 1 receives the interrupt through int. NOTE: Reserved in single-processor implementations. 0 Processor core 1 does not receive this interrupt. 1 Directs the interrupt to processor core 1 through the assertion of int1 . 31 Processor core 0 . Indicates whether processor core 0 receives the interrupt. P0 The default destination is for processor core 0 to receive this external interrupt after the PIC is reset. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 432 Freescale Semiconductor, Inc. Field Chapter 9 Programmable Interrupt Controller (PIC) PIC_MIDRn field descriptions (continued) Description 0 Processor core 0 does not receive this interrupt. 1 Directs the interrupt to processor core 0 through the assertion of int0 . 9.3.49 Shared message signaled interrupt vector/priority register n (PIC_MSIVPRn) The MSIVPRs have the same fields and format as the GTVPRs. See Flow of interrupt control for information on IPR and ISR. Address: 4_0000h base + 1_1C00h offset + (32d × i), where i=0d to 7d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R A MSK W Reserved PRIORITY Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 R W Reset 0 Field 0 MSK 1 A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VECTOR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_MSIVPRn field descriptions Description Mask. Mask interrupts from this source. MSK affects only interrupts routed to int. 0 An interrupt request is generated if the corresponding IPR bit is set. 1 Further interrupts from this source are disabled. Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values should not be changed while this bit is set. Affects only interrupts routed to int. 2–11 - 12–15 PRIORITY 16–31 VECTOR 0 No current interrupt activity associated with this source. 1 The interrupt field for this source is set in the IPR or ISR. This field is reserved. Reserved Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of 0 inhibits signaling of this interrupt to the core. Affects only interrupts routed to int. Vector (Affects only interrupts routed to int). Contains the value returned when IACK is read and this interrupt resides in the corresponding interrupt request register (IRR) for that core, as shown in Figure 9-331 . P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 433 PIC memory map/register definition 9.3.50 Shared message signaled interrupt destination register n (PIC_MSIDRn) The MSIDRs contain the destination bits for the shared message signaled interrupt. A shared message signaled interrupt can be directed to one of the processors by setting the appropriate bit in the shared message signaled interrupt destination register. Only one of the bits corresponding to destination processors may be set. The behavior if more than one bit is set is not defined. This register also contains the external pin and critical interrupt field s that can be programmed to direct the interrupt to the external pin or critical interrupt pin of the processor, respectively . Address: 4_0000h base + 1_1C10h offset + (32d × i), where i=0d to 7d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved P1 P0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 1 * Notes: • P1 field: Reserved in single-processor implementations. Field 0–29 30 P1 31 P0 PIC_MSIDRn field descriptions Description This field is reserved. Reserved Processor core 1. Indicates whether processor core 1 receives the interrupt through int. NOTE: Reserved in single-processor implementations. 0 Processor core 1 does not receive this interrupt. 1 Directs the interrupt to processor core 1 through the assertion of int1 . Processor core 0 . Indicates whether processor core 0 receives the interrupt. The default destination is for processor core 0 to receive this shared message signaled interrupt after the PIC is reset. 0 Processor core 0 does not receive this interrupt. 1 Directs the interrupt to processor core 0 through the assertion of int0 . P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 434 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.3.51 Processor core 0 interprocessor n dispatch register (PIC_IPIDR_CPU0n) The figure below shows the four IPIDRs, one for each interprocessor interrupt channel. Writing to an IPIDR with a bit set causes a self interrupt for a single-core device. Because external bus masters can write to these registers, this feature can serve as a doorbell type interrupt. Address: 4_0000h base + 2_0040h offset + (16d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W P1 P0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Field 0–29 - 30 P1 PIC_IPIDR_CPU0n field descriptions Description This field is reserved. Reserved Processor core 1. Specifies if processor core 1 receives the interrupt. This interrupt is multicasting, so both P0 and P1 can be set. NOTE: Reserved in single-processor implementations. 0 Processor core 1 does not receive the interrupt 1 Directs the interrupt to processor core 1 31 Processor core 0 . Determines if processor core 0 receives the interrupt. P0 0 Processor core 0 does not receive the interrupt. 1 Directs the interrupt to processor core 0. 9.3.52 Processor core current task priority register 0 Processor core (PIC_CTPR_CPU0) There is one CTPR per processor core on this device. NOTE CTPR has meaning only for interrupts routed to int . P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 435 PIC memory map/register definition Software must write the priority of the current processor core task in the CTPR for each core. The PIC uses this value for comparison with the priority of incoming interrupts. Given several concurrent incoming interrupts, the highest priority interrupt is asserted to that core if the following apply: • The interrupt is not masked. • The priority of the interrupt is higher than the values in the corresponding CTPR[TASKP] and ISR. Address: 4_0000h base + 2_0080h offset = 6_0080h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved TASKP Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 PIC_CTPR_CPU0 field descriptions Field 0–27 - 28–31 TASKP Description This field is reserved. Reserved Task priority. Indicates the threshold that individual interrupt priorities must exceed for the interrupt request to be serviced. 0000-1111 0000 1111 xVPRn[PRIORITY] must exceed this value for the interrupt request to be serviced. Note the following special cases: Lowest priority. All interrupts except those whose priority are 0 can be serviced. Highest priority. No interrupts are signaled to that processor core. Hardware selects this value on a device hard reset or when the corresponding PIR[Pn] is set. 9.3.53 Processor core 0 who am I register (PIC_WHOAMI_CPU0) The processor core WHOAMI n register can be read by a processor core to determine its physical connection to the PIC. The value returned when reading this register may be used to determine the value for the destination masks used for dispatching interrupts. Address: 4_0000h base + 2_0090h offset = 6_0090h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ID Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n n n n n P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 436 Freescale Semiconductor, Inc. Field 0–26 - 27–31 ID Chapter 9 Programmable Interrupt Controller (PIC) PIC_WHOAMI_CPU0 field descriptions Description This field is reserved. Reserved Returns the ID of the processor core reading this register. Does not always return zero. 0_0000 0_0001 1_1111 Processor core 0 Processor core 1. (Value not supported in single-processor implementations.) All other devices 9.3.54 Processor core 0 interrupt acknowledge register (PIC_IACK_CPU0) NOTE IACK has meaning only for interrupts routed to int and should not be accessed for interrupts routed to cint or IRQ_OUT_B . In systems based on processors built on Power Architecture technology, the interrupt acknowledge function occurs as an explicit read operation to a memory-mapped interrupt acknowledge register (IACK). Each processor core has an IACK register assigned to it. Reading IACK returns the interrupt vector corresponding to the highest priority pending interrupt. Reading IACK also has the following side effects: • The associated field in the corresponding interrupt pending register (IPR) is cleared for edge-sensitive interrupts. See Interrupts routed to int . • The corresponding in-service register (ISR) is updated. • The corresponding int output signal from the PIC is negated. Reading IACK when no interrupt is pending returns the spurious vector value, as described in Spurious vector register (PIC_SVR) . Address: 4_0000h base + 2_00A0h offset = 6_00A0h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W VECTOR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_IACK_CPU0 field descriptions Field 0–15 - 16–31 VECTOR Description This field is reserved. Reserved Interrupt vector. Vector of the highest pending interrupt P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 437 PIC memory map/register definition 9.3.55 Processor core 0 end of interrupt register (PIC_EOI_CPU0) NOTE EOI has meaning only for interrupts routed to int and should not be accessed for interrupts routed to cint or IRQ_OUT_B . Each core is assigned an EOI register. Writing to EOI signals the end of processing for the highest-priority interrupt (routed to int ) currently in service. It also updates the corresponding ISR n by retiring the highest priority interrupt. Data values written to EOI are ignored, and zero is assumed. Address: 4_0000h base + 2_00B0h offset = 6_00B0h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W EOI_CODE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_EOI_CPU0 field descriptions Field 0–27 - 28–31 EOI_CODE This field is reserved. Reserved 0000 (write only) Description P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 438 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.3.56 Processor core 1 interprocessor n dispatch register (PIC_IPIDR_CPU1n) The figure below shows the four IPIDRs, one for each interprocessor interrupt channel. Writing to an IPIDR with a bit set causes a self interrupt for a single-core device. Because external bus masters can write to these registers, this feature can serve as a doorbell type interrupt. Address: 4_0000h base + 2_1040h offset + (16d × i), where i=0d to 3d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W P1 P0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Field 0–29 - 30 P1 PIC_IPIDR_CPU1n field descriptions Description This field is reserved. Reserved Processor core 1. Specifies if processor core 1 receives the interrupt. This interrupt is multicasting, so both P0 and P1 can be set. NOTE: Reserved in single-processor implementations. 0 Processor core 1 does not receive the interrupt 1 Directs the interrupt to processor core 1 31 Processor core 0 . Determines if processor core 0 receives the interrupt. P0 0 Processor core 0 does not receive the interrupt. 1 Directs the interrupt to processor core 0. 9.3.57 Processor core 1 current task priority register (PIC_CTPR_CPU1) There is one CTPR per processor core on this device. NOTE CTPR has meaning only for interrupts routed to int . P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 439 PIC memory map/register definition Software must write the priority of the current processor core task in the CTPR for each core. The PIC uses this value for comparison with the priority of incoming interrupts. Given several concurrent incoming interrupts, the highest priority interrupt is asserted to that core if the following apply: • The interrupt is not masked. • The priority of the interrupt is higher than the values in the corresponding CTPR[TASKP] and ISR. Address: 4_0000h base + 2_1080h offset = 6_1080h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reserved TASKP Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 PIC_CTPR_CPU1 field descriptions Field 0–27 - 28–31 TASKP Description This field is reserved. Reserved Task priority. Indicates the threshold that individual interrupt priorities must exceed for the interrupt request to be serviced. 0000-1111 0000 1111 xVPRn[PRIORITY] must exceed this value for the interrupt request to be serviced. Note the following special cases: Lowest priority. All interrupts except those whose priority are 0 can be serviced. Highest priority. No interrupts are signaled to that processor core. Hardware selects this value on a device hard reset or when the corresponding PIR[Pn] is set. 9.3.58 Processor core 1 who am I register (PIC_WHOAMI_CPU1) The processor core WHOAMI n register can be read by a processor core to determine its physical connection to the PIC. The value returned when reading this register may be used to determine the value for the destination masks used for dispatching interrupts. Address: 4_0000h base + 2_1090h offset = 6_1090h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ID Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n n n n n P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 440 Freescale Semiconductor, Inc. Field 0–26 - 27–31 ID Chapter 9 Programmable Interrupt Controller (PIC) PIC_WHOAMI_CPU1 field descriptions Description This field is reserved. Reserved Returns the ID of the processor core reading this register. Does not always return zero. 0_0000 0_0001 1_1111 Processor core 0 Processor core 1. (Value not supported in single-processor implementations.) All other devices 9.3.59 Processor core 1 interrupt acknowledge register (PIC_IACK_CPU1) NOTE IACK has meaning only for interrupts routed to int and should not be accessed for interrupts routed to cint or IRQ_OUT_B . In systems based on processors built on Power Architecture technology, the interrupt acknowledge function occurs as an explicit read operation to a memory-mapped interrupt acknowledge register (IACK). Each processor core has an IACK register assigned to it. Reading IACK returns the interrupt vector corresponding to the highest priority pending interrupt. Reading IACK also has the following side effects: • The associated field in the corresponding interrupt pending register (IPR) is cleared for edge-sensitive interrupts. See Interrupts routed to int . • The corresponding in-service register (ISR) is updated. • The corresponding int output signal from the PIC is negated. Reading IACK when no interrupt is pending returns the spurious vector value, as described in Spurious vector register (PIC_SVR) . Address: 4_0000h base + 2_10A0h offset = 6_10A0h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W VECTOR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_IACK_CPU1 field descriptions Field 0–15 - 16–31 VECTOR Description This field is reserved. Reserved Interrupt vector. Vector of the highest pending interrupt P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 441 Functional description 9.3.60 Processor core 1 end of interrupt register (PIC_EOI_CPU1) NOTE EOI has meaning only for interrupts routed to int and should not be accessed for interrupts routed to cint or IRQ_OUT_B . Each core is assigned an EOI register. Writing to EOI signals the end of processing for the highest-priority interrupt (routed to int ) currently in service. It also updates the corresponding ISR n by retiring the highest priority interrupt. Data values written to EOI are ignored, and zero is assumed. Address: 4_0000h base + 2_10B0h offset = 6_10B0h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Reserved W EOI_CODE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIC_EOI_CPU1 field descriptions Field 0–27 - 28–31 EOI_CODE This field is reserved. Reserved 0000 (write only) Description 9.4 Functional description This section is a functional description of the PIC. 9.4.1 Programming model considerations 9.4.1.1 Global registers Although most PIC registers have one address, some are replicated for each e500 processor core in a multiprocessor device. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 442 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) For such registers, each core accesses its separate registers using the same address, the address decoding being sensitive to the processor core ID. A copy of the per-CPU registers is available to each e500 processor core at the same physical address, that is, in a private access address space that acts like an alias to a processor's own copy of the perCPU registers. As shown in Figure 9-330, the ID of the core initiating the read/write transaction determines which processor's per-CPU registers to access. For more information, see Per-CPU (private access) registers. NOTE Register fields designated as write-1-to-clear are cleared only by writing ones to them. Writing zeros to them has no effect. 9.4.1.2 Global timer registers The two independent groups of global timer registers, group A and group B, are identical in their functionality, except that they appear at different locations within the PIC register map. Note that each of the four timers within an x group have four individual configuration registers (GTCCRxn, GTBCRxn, GTVPRxn, and GTDRxn), but they are only shown once in this section. These two groups of timers cannot be cascaded together. 9.4.1.3 IRQ_OUT_B and critical interrupt summary registers The summary registers indicate the specific interrupt sources routed to the IRQ_OUT_B or cint0/cint1 PIC outputs. Summary register bits are cleared when the corresponding interrupt that caused a bit to be set is negated. Note that only level-sensitive interrupts can be routed to IRQ_OUT_B or cint0 and cint1. The IRQ_OUT_B summary registers, shown in IRQ_OUT_B summary register 0 (PIC_IRQSR0) through IRQ_OUT_B summary register 2 (PIC_IRQSR2) contain one bit for each interrupt source that can be routed to IRQ_OUT_B . The corresponding bit is set if the interrupt is active and is routed to IRQ_OUT_B (that is, if the corresponding xIDRn[EP] is set). The critical interrupt summary registers, shown in Critical interrupt summary register 0 (PIC_CISR0) through Critical interrupt summary register 2 (PIC_CISR2), contain one bit for each interrupt source that can be designated as a critical interrupt. The corresponding bit is set if the interrupt is active and is routed to either the cint0 or cint1 outputs of the PIC (if xIDRn[CIn] = 1 in its corresponding destination register). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 443 Functional description 9.4.1.4 Performance monitor mask registers (PMMRs) The twelve performance monitor mask registers consist of four sets of three 32-bit registers, PMnMR0, PMnMR1, and PMnMR2. Each set can be configured to select one interrupt source (interprocessor, timer, message, shared message signaled, external, or internal) to generate a performance monitor event. The performance monitor can be configured to track this event in the performance monitor local control registers. See Performance monitor local control register A0 (PERFMON_PMLCA0) and Performance monitor local control register B0 (PERFMON_PMLCB0) . 9.4.1.5 Message registers The following registers support the message register interrupts: • Message register n (PIC_MSGRn) • Message enable register (PIC_MER) • Message status register (PIC_MSR) • Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPRn) • Messaging interrupt n (MSGn) destination register (PIC_MIDRn) Writing to one of the eight message registers (MSGR0-MSGR7) causes a messaging interrupt as directed by the other message registers listed above. Reading a message register clears the messaging interrupt. Note that a messaging interrupt can also be cleared by writing a one to the corresponding status field of the PIC message status register (MSR), shown in Message status register (PIC_MSR). 9.4.1.6 Shared message signaled registers This section contains description the shared message signaled interrupt registers (MSIRs). The shared message signaled interrupt structure allows programs to interrupt each other by simply writing to these shared memory-mapped registers in the PIC. Each of the eight MSIRs can be thought of as collecting interrupts from 32 different memory-mapped writes that can cause interrupts. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 444 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.4.1.7 Interrupt source configuration registers The interrupt source configuration registers control the source and destinations of interrupts, specifying parameters such as the interrupting event, signal polarity, and relative priority. Table 9-332 shows the destination registers. Table 9-332. Destination register summary Interrupt source 01 2 3 External (External interrupt n (IRQn) R EP CI0 CI1 - destination register (PIC_EIDRn) W Internal (Internal interrupt n destination register (PIC_IIDRn) Message signaled (Shared message R - signaled interrupt destination register n (PIC_MSIDRn) W Messaging (Messaging Interrupt Destination Registers) Global timer (Global timer n destination register group A (PIC_GTDRAn) interprocessor ( Processor core 0 interprocessor n dispatch register (PIC_IPIDR_CPU0n) 2 30 31 9 P1 P0 P1 P0 Note the following: • The global timer, messaging interrupt and interprocessor destination register support only the P0 and P1 options. That is, they cannot be routed to cint or to IRQ_OUT_B. • Only the global timer and interprocessor interrupts are multicasting, so only these interrupts allow more than one destination bit to be specified. Table 9-333 shows the vector/priority registers. Table 9-333. Vector/priority register summary Interrupt Source 01 67 8 9 1 1 11 3 01 45 1 Global timer (Global timer n vector/ priority register group A (PIC_GTVPRAn) R MSK A W PRIORIT VECTOR Y Message signaled (Shared message signaled interrupt vector/priority register n (PIC_MSIVPRn) Messaging ( Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 445 Functional description Table 9-333. Vector/priority register summary (continued) Internal (Internal interrupt n vector/ priority register (PIC_IIVPRn) R MSK A W External (External interrupt n (IRQn) R MSK A vector/priority register (PIC_EIVPRn) W PPS- PRIORIT VECTOR Y PRIORIT VECTOR Y Note the following: • The MSK, A, PRIORITY, and VECTOR fields have meaning only for interrupts routed to the int signal. • The polarity field, P, is provided to indicate whether the signals from the corresponding source are active high or low. • The sense field, S, is provided to allow external interrupt sources to be configured as level-sensitive so they can be routed to either cint or IRQ_OUT_B. 9.4.1.8 Per-CPU (private access) registers The OpenPIC programming model supports multiprocessor systems of up to 32 separate processors. As such, the OpenPIC interface specification provides for coordinating both the requesting and servicing of interrupts among several processor cores within a single integrated device. To comply with the OpenPIC specification, the PIC incorporates several of these multiprocessor capabilities. NOTE Note that these registers are meaningful only for interrupts routed to int. The registers in the table below are called per-CPU registers because they are duplicated for each core in a multi-core device. The OpenPIC interface specifies that a copy of these registers be available to each core at the same physical address by using the ID of the processor core that initiates the transaction to determine the set of per-CPU registers to access. Table 9-334. Per-CPU registers-private access address offsets Register name Interprocessor 0 dispatch register (IPIDR0) Interprocessor 1 dispatch register (IPIDR1) Interprocessor 2 dispatch register (IPIDR2) Interprocessor 3 dispatch register (IPIDR3) Table continues on the next page... 0x0040 0x0050 0x0060 0x0070 Offset P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 446 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) Table 9-334. Per-CPU registers-private access address offsets (continued) Register name Current task priority register (CTPR) Who am I register (WHOAMI0) Interrupt acknowledge register (IACK) End of interrupt register (EOI) 0x0080 0x0090 0x00A0 0x00B0 Offset These addresses, shown in Table 9-334, appear in the memory map at the same offset for every processor in what is called the private access space. This duplication allows user code to execute correctly in an multiprocessor environment without needing to know which core it is running on. On a single-core device, each register has two addresses, one in the normal address space and one in the private access space. It is included on even single-core devices to simplify the porting of such code. Figure 9-330 shows how the duplicated registers are addressed in a four-core device. Note that when accessing a register normally, each core sources a different address. However, when accessing the same register using the per-CPU address space, each core sources the same address. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 447 Functional description Figure 9-330. Per-CPU register address decoding in a four-core device 9.4.2 Flow of interrupt control Figure 9-331 shows the flow of interrupts directed by the PIC to the int, cint, and IRQ_OUT_B outputs. Note that this diagram describes a conceptual model of an PIC on a single processor. This logic is replicated for each implemented processor. This conceptual diagram does not fully represent all internal circuitry of the implementation. This figure focusses especially on the OpenPIC-defined logic and shows how the PIC controls interrupt requests that target the int signal. The flow in Figure 9-331 is from the bottom to the top, and shows at the bottom how the destination register associated with each source determines the path. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 448 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.4.2.1 Interrupts routed to cint or IRQ_OUT_B Interrupt requests routed to cint or IRQ_OUT_B bypass the logic that is dedicated to interrupt sources that compete for int. That is, if xIDRn[CIn] or xIDRn[EP] = 1, corresponding xIVPR field settings have no hardware effects; however, an interrupt handler may be able to make use of some of those fields. cint signals are connected to the respective core's critical interrupt input. NOTE Because interrupt sources routed to cint or IRQ_OUT_B must be level sensitive, EIVPR[S] should be set. See External interrupt n (IRQn) vector/priority register (PIC_EIVPRn). Because these interrupts bypass the OpenPIC logic, it is especially important that handlers do not read IACK. Doing so causes a spurious interrupt. Likewise, they should not write EOI. 9.4.2.2 Interrupts routed to int As shown in the figure below, the PIC receives interrupt requests from external and internal sources and from within the PIC itself. As the figure shows, all of these interrupt sources can be routed to int; the global timer and timer processor interrupts can be directed only to int. The sources' mask bits (xVPRn[MSK]) are tracked in the internal mask register. If a source's MSK bit is set, the mask register prevents the PIC from asserting int on its behalf. Unmasked interrupt requests are qualified and latched in the interrupt pending register (IPR), an internal interrupt summary register with a bit for each source. If an interrupt request is multi-cast, a bit is set in the IPR for each targeted processor. Although the IPR cannot be read by software, when an IPR bit is set, the corresponding source's activity bit (xVPRn[A]) is automatically set. The interrupt selector monitors the IPR and the in-service register (ISR), which tracks previously taken interrupts that were superseded by a higher-priority interrupt before the interrupt handler finished. The interrupt selector recognizes the highest priority unmasked interrupt request and latches it into the interrupt request register (IRR). The source's vector (xVPRn[VECTOR]) is copied to IACK[VECTOR], which the interrupt handler retrieves by reading IACK. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 449 Functional description If the priority (xVPRn[PRIORITY]) of an interrupt latched in the IRR is higher than the value in the target processor's CTPR[TASKP], the interrupt router asserts the external interrupt signal (int), causing that processor core to vector to its external interrupt handler. Note that like IPR, ISR and IRR cannot be read by software. Figure 9-331. PIC interrupt processing flow diagram for each core (n) The interrupt handler must acknowledge the interrupt by explicitly reading the corresponding IACK registers, described in Processor core 0 interrupt acknowledge register and Processor core 0 interrupt acknowledge register. The PIC interprets this read P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 450 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) as an interrupt acknowledge (IACK) cycle. The IACK cycle not only returns the source's vector, it also negates the int signal to the processor (making it possible for a higher priority interrupt to assert int) and sets the source's bit in the ISR, indicating that this interrupt has been put in service. An interrupt remains in service from the time until the corresponding end-of-interrupt register (EOI) is written, generating what the PIC considers an EOI signal. 9.4.2.2.1 Interrupt source priority Each interrupt source routed to int is assigned a value through its xVPRn[PRIORITY] field. Priority values range from 0 to 15, where 15 is the highest. Interrupts are delivered only when the priority of the source is greater than the destination processor's CTPR[TASKP]. Therefore, setting xVPRn[PRIORITY] to zero inhibits that interrupt. Likewise, setting TASKP to 15 prevents the PIC from delivering interrupts to that core through the int signal. Note that this is the reset value, preventing the PIC from asserting int before the PIC is configured. The PIC services simultaneous interrupts occurring with the same priority according to the following order: 1. MSG0-MSG 7 2. MSI0-MSI7 3. IPI0-IPI3 4. Group A timer0-timer3 5. Group B timer0-timer3 6. IRQ[0:11]/PCIINTx 7. Internal0-internal 63 For example, if MSG0, MSG2, and IPI0 are all assigned the same priority and receive simultaneous interrupts, they are serviced in the following order: 1. MSG0 2. MSG2 3. IPI0 9.4.2.2.2 Interrupt acknowledge When the PIC causes int to be asserted, the external interrupt service routine acknowledges the request by reading that core's IACK register, which at this point holds the 16-bit vector value for the interrupt source that generated the request. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 451 Functional description This is the value programmed in that source's xVPRn[VECTOR]. Reading IACK has the following effects: • The int signal for that core is negated, making it possible for another interrupt source to signal an external interrupt to the core, and more particularly, allowing the PIC to signal a higher-priority interrupt, as described in Nesting of interrupts. • The source that caused that resource is represented in the internal in-service register (ISR). The interrupt is then considered to be in service. It remains so until the processor core performs a write to the corresponding EOI. Writing to EOI is referred to as an EOI cycle. 9.4.2.2.3 Spurious vector generation Under certain circumstances, the PIC has no valid vector to return to a processor core during an interrupt acknowledge cycle. In these cases, the spurious vector from the spurious vector register is returned. The following cases cause a spurious vector fetch: • int is asserted in response to an externally or internally-sourced interrupt which is activated with level-sensitive logic, and the asserted level is negated before the interrupt is acknowledged. • int is asserted for an interrupt source that is later masked (using the mask bit in the vector/priority register corresponding to that source) before the interrupt is acknowledged. • int is asserted for an interrupt source that is later masked by an increase in the task priority level before the interrupt is acknowledged. • An interrupt acknowledge cycle is performed by the processor core in spite of the fact that the int signal has not been asserted by the PIC. In all cases, a spurious vector is returned only if no pending interrupt has sufficient priority to signal an interrupt, otherwise, the vector for that interrupt source is returned. NOTE EOI should not be written in response to a spurious vector. Otherwise, a previously accepted interrupt might be cleared unintentionally. 9.4.2.2.4 Nesting of interrupts While an interrupt is being handled, if an interrupt request arrives with a higher xVPRn[PRIORITY] value, the interrupt being serviced is superseded. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 452 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) As described in Interrupts routed to int, the PIC asserts int, and the newer, higher priority interrupt is handled. This happens even if software, as part of its interrupt service routine, updates the corresponding CTPR with a lower value. Thus, although several interrupts can be in service simultaneously (and tracked by the ISR), the highest priority interrupt by that processor is always the one actively handled. When the interrupt routine completes, it performs a write EOI cycle, a side effect of which is to take the current highest priority interrupt out of service (removes it from the ISR). At this point, the interrupt selector chooses the new highest priority interrupt request, and, assuming CTPR[TASKP] has not been updated to a value higher than the new interrupt, the PIC asserts int on its behalf. The next write EOI cycle takes the current highest priority interrupt out of service. An interrupt with lower priority than those in service is not started until all higher priority interrupts complete even if its priority is greater than the CTPR value. 9.4.3 Interprocessor interrupts Processors 0 and 1 can generate interprocessor interrupts that target either or both processors. A self interrupt occurs when a core dispatches an interprocessor interrupt event to itself. Interrupts are initiated by writing either or both of the POn bits in an interprocessor interrupt dispatch register (IPIDR0-IPIDR3) of one of the four IPI channels. If subsequent interprocessor interrupts from a given channel to a given target processor are initiated before the first is acknowledged, only one interrupt is generated. 9.4.4 Message interrupts The eight MSGRs described in Message register n (PIC_MSGRn), can be used to send 32-bit messages to one or more processors. A messaging interrupt is generated by writing an MSGR if the corresponding MER bit is set and the interrupt is not masked. Reading a MSGR or writing a 1 to the status bit clears the interrupt. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 453 Functional description 9.4.5 Shared message signaled interrupts There are eight shared MSIRs, Shared message signaled interrupt register n (PIC_MSIRn), that indicate which of the interrupt sources sharing the MSI register have pending interrupts. Up to 32 sources can share any individual MSI register. A shared message signaled interrupt is generated by writing to Shared Message Signaled Interrupt Index Register (MSIIR) fields SRS and IBS. This register is primarily intended to support inbound PCI Express message signaled interrupts (MSIs) when the PCI Express controller is configured as a root complex (RC). MSIIR[SRS] selects the associated MSIR and MSIIR[IBS] selects the interrupt flag/bit in that register that is to be set. The corresponding interrupt needs to be unmasked for the interrupt to occur. A read to an MSIR clears the all of its flags. 9.4.6 PCI Express INTx/IRQn sharing Whenever the PCI Express controller is in root complex mode and it receives an inbound INTx asserted or negated message transaction, it asserts or negates an equivalent internal INTx signal to the PIC. This INTx virtual-wire interrupt signaling mechanism replaces the PCI standard sideband interrupts (INTA, INTB, INTC, and INTD) that historically were connected to the IRQn external interrupt inputs. The internal INTx signals from the PCI Express controller are logically combined with the interrupt request (IRQn) signals so that they share the same OpenPIC external interrupt controlled by the associated EIVPRn and EIDRn registers. Table 9-335. PCI Express INTx/IRQn sharing PCI Express number PCI Express 1 PCI Express 2 INTA INTB INTC INTD INTA INTB INTC INTD INTx IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQn P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 454 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) In general, these signals should be considered mutually exclusive. If a PCI Express INTx signal is being used, the PIC must be configured so that external interrupts are level sensitive (EIVPRn[S] = 1). If an IRQn signal is being used as edge-triggered (EIVPRn[S] = 0), the system must not allow inbound PCI Express INTx transactions. Note that it is possible to share IRQn and INTx if the external interrupt is level sensitive; however, if an interrupt occurs, the interrupt service routine must poll both the external sources connected to the IRQn input and the PCI Express INTx sources to determine from which path the external interrupt came. In any case, IRQn should be pulled to the negated state as determined by the associated polarity setting in EIVPRn[P]. 9.4.7 Global timers There are appropriate clock prescalers and synchronizers to provide a time base for the internal PIC timers. These 8 timers are organized as 2 groups of 4 timers each. The timers can be individually programmed to generate a processor core interrupt when they count down to zero and can be used to generate regular periodic interrupts. Each timer has the following four configuration and control registers: • Global timer current count register (GTCCRxn) • Global timer base count register (GTBCRxn) • Global timer vector-priority register (GTVPRxn) • Global timer destination register (GTDRxn) The timer frequency should be written to the TFRRxn, described in Timer frequency reporting register group X (PIC_TFRRn). Timer interrupts are all edge-triggered interrupts. If a timer period expires while a previous interrupt from the same source is pending or in service, the subsequent interrupt is lost. The timer control register (TCR) provides users with the ability to create timers larger than the 31-bit global timers. The timer frequency can also be changed by setting the appropriate TCR fields, as described in Timer control register group n (PIC_TCRn). 9.4.8 Resets This section describes the behavior of the PIC at reset and the PIC's ability to initiate processor resets. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 455 Initialization/application information 9.4.9 Resetting the PIC The PIC is reset by a device power-on reset (POR) or by software that sets GCR[RST], either of which causes the following: • All pending and in-service interrupts are cleared. • All interrupt mask bits are set. • Polarity, sense, external signal, critical interrupt, and activity fields are reset to default values. • PIR, TFRR, TCR, MER, MSR, and MSGR0-MSGR 7 are cleared. • MSG and timer destination fields are set. • The interprocessor dispatch registers are cleared. • All timer base count values are reset to zero with count inhibited. • CTPR[TASKP] is reset to 0x000F, disabling delivery of interrupts that target int. • The spurious interrupt vector resets to 0xFFFF. • The PMnMRs are reset to 0xFFFF. • The PIC defaults to the pass-through mode (GCR[M] = 0). • All other registers remain at their pre-reset programmed values. GCR[RST] is automatically cleared when the reset sequence is complete. 9.4.9.1 Processor core initialization A software reset can be routed to either of the cores by writing to the processor core initialization register (PIR). This causes the assertion of the corresponding core_hreset output signal from the PIC. When this occurs, the corresponding CTPR also gets written to 0x000F to prevent delivery of any interrupts to int. 9.5 Initialization/application information This section contains initialization and application information for the PIC. 9.5.1 Programming guidelines The following subsections contain information about programming PIC registers. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 456 Freescale Semiconductor, Inc. Chapter 9 Programmable Interrupt Controller (PIC) 9.5.1.1 PIC registers Most PIC control and status registers are readable and return the last value written. The exceptions to this rule are as follows: • Interprocessor dispatch and EOI registers, which return zeros on reads. • Activity bits (A) of the vector/priority registers reflect the status of the corresponding interrupt source. • IACK, which returns the vector of the highest priority pending interrupt or the spurious vector (SVR[VECTOR]) if none is pending. • Reserved fields always return 0. When the PIC is in mixed mode (GCR[M] = 1), the following guidelines are recommended: • All PIC registers must be located in a cache-inhibited, guarded area (configured through the core's MMU). • The PIC portion of the address map must be set up appropriately. In addition, the following initialization sequence is recommended: 1. Write the vector, priority, and polarity values in each interrupt's vector/priority register, leaving their MSK (mask) bit set. This is required only if interrupts are used. 2. Clear CTPR (CTPR = all zeros). 3. Program the PIC to mixed mode by setting GCR[M]. 4. Clear the MSK bit in the vector/priority registers to be used. 5. Perform a software loop to clear all pending interrupts: • Load counter with FRR[NIRQ]. • While counter > 0, read IACK and write EOI to guarantee all the IPR and ISR bits are cleared. 6. Set the processor core CTPR values to the desired values. 7. Set MER to 0x0000_000F. See Message enable register (PIC_MER), for more information. Depending on the interrupt system configuration, the PIC may generate spurious interrupts to clear interrupts latched during power-up. A spurious or non-spurious vector is returned for an interrupt acknowledge cycle in this case. See the programming note below for the non-spurious case. NOTE Because the default polarity/sense for external interrupts is edge-sensitive, and edge-sensitive interrupts are not cleared until they are acknowledged, it is possible for the PIC to store P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 457 Initialization/application information spurious edges detected during power-up as pending external interrupts. If software permanently configures an external interrupt source to be edge-sensitive, it may receive the vector for the interrupt source and not a spurious interrupt vector when software clears the mask bit. This can occur once for any edgesensitive interrupt when its mask bit is first cleared and the PIC is in mixed mode. To avoid a false interrupt for this case, software can clear the IPR of these spurious edge detections by first configuring the polarity/sense of external interrupt sources to be level-sensitive: high-level if the input is a positive-edge source and low-level if it is a negative-edge source (while the mask bit remains set). After this is complete, configuring the external interrupt source as edge-sensitive does not cause a false interrupt. 9.5.1.2 Changing interrupt source configuration To change the vector, priority, polarity, sense, or destination of an active (unmasked) interrupt source, the following steps should be taken: 1. Mask the source using the mask (MSK) bit in the vector/priority register. 2. Wait for the activity (A) bit for that source to be cleared. 3. Make the desired changes. 4. Unmask the source. Note that changing the destination from int to cint or IRQ_OUT_B makes the A, MSK, and PRIORITY fields meaningless. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 458 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces This chapter describes the dual inter-integrated circuit (I2C) bus modules implemented on this device. 10.1 Overview This chapter describes the dual inter-integrated circuit (I2C) bus modules implemented on this device and covers the following topics: • Introduction to I2C • I2C external signal descriptions • I2C memory map/register definition • Functional description • Initialization/application information 10.2 Introduction to I2C This section presents the following topics: • What is the I2C module? • I2C module block diagram • Features • Advantages of the I2C bus • Modes of operation • I2C-specific conditions P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 459 Introduction to I2C 10.2.1 What is the I2C module? The I2C module is a two-wire-serial data (SDA) and serial clock (SCL)-bidirectional serial bus that provides a simple efficient method of data exchange between this device and other devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. 10.2.2 I2C module block diagram Address and Control Interrupt Data Addr Decode Data Mux l2CDSRR l2CADR l2CFDR l2CCR l2CSR l2CDR Clock and Control Input Sync and Digital Filter START/ STOP/ Restart and Arbitration Control arb_lost In/Out Data Shift Register Address Compare SDA SCL Figure 10-1. I2C block diagram 10.2.3 Features The I2C interface includes the following features: • Two-wire interface • Multiple-master operation P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 460 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection • Acknowledge bit generation/detection • Bus busy detection • Software-programmable clock frequency • Software-selectable acknowledge bit • On-chip filtering for spikes on the bus 10.2.4 Advantages of the I2C bus The two-wire I2C bus minimizes interconnections between devices. The synchronous, multiple-master I2C bus allows the connection of additional devices to the bus for expansion and system development. The bus includes collision detection and arbitration that prevent data corruption if two or more masters attempt to control the bus simultaneously. 10.2.5 Modes of operation The I2C units on this device can operate in one of the following modes: • Master mode-The I2C is the driver of the SDA line. It cannot use its own slave address as a calling address. The I2C cannot be a master and a slave simultaneously. • Slave mode-The I2C is not the driver of the SDA line. The module must be enabled before a START condition from a non-I2C master is detected. • Interrupt-driven byte-to-byte data transfer-When successful slave addressing is achieved (and SCL returns to zero), the data transfer can proceed on a byte-to-byte basis in the direction specified by the R/W_B bit sent by the calling master. Each byte of data must be followed by an acknowledge bit, which is signaled from the receiving device. Several bytes can be transferred during a data transfer session. • Boot sequencer mode-This mode can be used to initialize the configuration registers in the device after the I2C1 module is initialized. Note that the device powers up with boot sequencer mode disabled as a default, but this mode can be selected with the cfg_boot_seq[0:1] power-on reset (POR) configuration signals that are located on the LGPL3 and LGPL5 signals. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 461 I2C external signal descriptions 10.2.6 I2C-specific conditions The following three conditions are defined for the I2C interface: • START condition-This condition denotes the beginning of a new data transfer (each data transfer contains several bytes of data) and awakens all slaves. • Repeated START condition-A START condition that is generated without a STOP condition to terminate the previous transfer. • STOP condition-The master can terminate the transfer by generating a STOP condition to free the bus. 10.3 I2C external signal descriptions The following sections give an overview of signals and provide detailed signal descriptions. 10.3.1 Signal overview The I2C interface uses the SDA and SCL signals, described in the table below for data transfer. Note that the signal patterns driven on SDA represent address, data, or read/write information at different stages of the protocol. Table 10-1. I2C interface signal descriptions Signal name Idle state I/O State meaning Serial clock (IICn_SCL) HIGH I When the I2C module is idle or acts as a slave, SCL defaults as an input. The unit uses SCL to synchronize incoming data on SDA. The bus is assumed to be busy when SCL is detected low. O As a master, the I2C module drives SCL along with SDA when transmitting. As a slave, the I2C module drives SCL low for data pacing. Serial data (IICn_SDA) HIGH I When the I2C module is idle or in a receiving mode, SDA defaults as an input. The unit receives data from other I2C devices on SDA. The bus is assumed to be busy when SDA is detected low. O When writing as a master or slave, the I2C module drives data on SDA synchronous to SCL. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 462 Freescale Semiconductor, Inc. 10.3.2 Detailed signal descriptions Chapter 10 I2C Interfaces SDA and SCL, described in the table below, serve as a communication interconnect with other devices. All devices connected to these two signals must have open-drain or opencollector outputs. The logic AND function is performed on both of these signals with external pull-up resistors. Refer to the device hardware specifications for the electrical characteristics of these signals. Table 10-2. I2C interface signal-detailed signal descriptions Signal IICn_SCL IICn_SDA I/O Description I/O Serial clock. Performs as an input when the device is programmed as an I2C slave. SCL also performs as an output when the device is programmed as an I2C master. O As outputs for the bidirectional serial clock, these signals operate as described below. State Asserted/Negated-Driven along with SDA as the clock for the data. meaning I As inputs for the bidirectional serial clock, these signals operate as described below. State Asserted/Negated-The I2C unit uses this signal to synchronize incoming data on SDA. The bus Meaning is assumed to be busy when this signal is detected low. I/O Serial data. Performs as an input when the device is in a receiving mode. SDA also performs as an output signal when the device is transmitting (as an I2C master or a slave). O As outputs for the bidirectional serial data, these signals operate as described below. State Asserted/Negated- Data is driven. meaning I As inputs for the bidirectional serial data, these signals operate as described below. State Asserted/Negated-Used to receive data from other devices. The bus is assumed to be busy meaning when SDA is detected low. 10.4 I2C memory map/register definition The following table lists the I2C-specific registers and their offsets. It lists the offset, name, and a cross-reference to the complete description of each register. Note that the full register address is comprised of CCSRBAR together with the block base address and offset listed in the table below. The offsets to the memory map table are defined for both I2C interfaces. That is, I2C1 starts at address offset 0x000, and I2C2 starts at address offset 0x100. Note that the registers are the same for I2C2 except that the offsets change from 0x0nn to 0x1nn. All I2C registers are one byte wide. Reads and writes to these registers must be byte-wide operations. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 463 I2C memory map/register definition NOTE Reserved bits should always be written with the value they returned when read. That is, the register should be programmed by reading the value, modifying appropriate fields, and writing back the value. The return value of the reserved fields should not be assumed, even though the reserved fields return zero. This note does not apply to the I2C data register (I2CDR). I2C memory map Offset address (hex) 3000 3004 3008 300C 3010 3014 3100 3104 3108 310C 3110 3114 Register name I2C address register (I2C1_I2CADR) I2C frequency divider register (I2C1_I2CFDR) I2C control register (I2C1_I2CCR) I2C status register (I2C1_I2CSR) I2C data register (I2C1_I2CDR) I2C digital filter sampling rate register (I2C1_I2CDFSRR) I2C address register (I2C2_I2CADR) I2C frequency divider register (I2C2_I2CFDR) I2C control register (I2C2_I2CCR) I2C status register (I2C2_I2CSR) I2C data register (I2C2_I2CDR) I2C digital filter sampling rate register (I2C2_I2CDFSRR) Width (in bits) Access Reset value Section/ page 8 R/W 8 R/W 8 R/W 8 R/W 8 R/W 8 R/W 8 R/W 8 R/W 8 R/W 8 R/W 8 R/W 8 R/W 00h 10.4.1/464 00h 10.4.2/465 00h 10.4.3/467 81h 10.4.4/468 00h 10.4.5/469 10h 10.4.6/470 00h 10.4.1/464 00h 10.4.2/465 00h 10.4.3/467 81h 10.4.4/468 00h 10.4.5/469 10h 10.4.6/470 10.4.1 I2C address register (I2Cx_I2CADR) The figure below shows the I2CADR register, which contains the address to which the I2C interface responds when addressed as a slave. Note that this is not the address that is sent on the bus during the address-calling cycle when the I2C module is in master mode. Address: Base address + 0h offset Bit 0 1 2 3 4 5 6 7 Read Write ADDR Reserved Reset 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 464 Freescale Semiconductor, Inc. Field 0–6 ADDR 7 - I2Cx_I2CADR field descriptions Chapter 10 I2C Interfaces Description Slave address. Contains the specific slave address that is used by the I2C interface. Note that the default mode of the I2C interface is slave mode for an address match. Note that an address match is one of the conditions that can cause I2CSR[MIF] to be set, signaling an interrupt pending condition. This field is reserved. 10.4.2 I2C frequency divider register (I2Cx_I2CFDR) Refer to application note AN2919, "Determining the I2C Frequency Divider Ratio for SCL," for additional guidance regarding the proper use of I2CFDR and I2CDFSRR. Address: Base address + 4h offset Bit 0 1 2 3 4 5 6 7 Read Write Reserved FDR Reset 0 0 0 0 0 0 0 0 I2Cx_I2CFDR field descriptions Field 0–1 - 2–7 FDR This field is reserved. Description Frequency divider ratio. Used to prescale the clock for bit rate selection. The serial bit clock frequency of SCL is equal to one half the platform ( CCB ) clock divided by the designated divider . Note that the frequency divider value can be changed at any point in a program. The serial bit clock frequency divider selections are described as follows: FDRDivider (Decimal) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 384 416 480 576 640 704 832 1024 1152 1280 1536 1920 2304 2560 3072 3840 Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 465 I2C memory map/register definition I2Cx_I2CFDR field descriptions (continued) Field 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 4608 5120 6144 7680 9216 10240 12288 15360 18432 20480 24576 30720 36864 40960 49152 61440 256 288 320 352 384 448 512 576 640 768 896 1024 1280 1536 1792 2048 2560 3072 3584 4096 5120 6144 7168 8192 10240 12288 14336 16384 20480 24576 28672 32768 Description P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 466 Freescale Semiconductor, Inc. 10.4.3 I2C control register (I2Cx_I2CCR) Chapter 10 I2C Interfaces Address: Base address + 8h offset Bit 0 1 Read Write MEN MIEN Reset 0 0 2 MSTA 0 3 MTX 0 4 TXAK 0 5 RSTA 0 6 Reserved 0 7 BCST 0 I2Cx_I2CCR field descriptions Field 0 MEN 1 MIEN 2 MSTA 3 MTX Description Module enable. This bit controls the software reset of the I2C module. 0 The module is reset and disabled. When low, the interface is held in reset but the registers can still be accessed. 1 The I2C module is enabled. This bit must be set before any other control register bits have any effect. All I2C registers for slave receive or master START can be initialized before setting this bit. Module interrupt enable 0 Interrupts from the I2C module are disabled. This does not clear any pending interrupt conditions. 1 Interrupts from the I2C module are enabled. An interrupt occurs provided I2CSR[MIF] is also set. Master/slave mode START 0 When this bit is changed from one to zero, a STOP condition is generated and the mode changes from master to slave. 1 Cleared without generating a STOP condition when the master loses arbitration. When this bit is changed from zero to one, a START condition is generated on the bus, and master mode is selected. Transmit/receive mode select. This bit selects the direction of the master and slave transfers. When configured as a slave, this bit should be set by software according to I2CSR[SRW]. In master mode, the bit should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high. The MTX bit is cleared when the master loses arbitration. 4 TXAK 0 Receive mode 1 Transmit mode Transfer acknowledge. This bit specifies the value driven onto the SDA line during acknowledge cycles for both master and slave receivers. The value of this bit only applies when the I2C module is configured as a receiver, not a transmitter. It also does not apply to address cycles; when the device is addressed as a slave, an acknowledge is always sent. 5 RSTA 0 An acknowledge signal (low value on SDA) is sent out to the bus at the 9th clock after receiving one byte of data. 1 No acknowledge signal response (high value on SDA) is sent. Repeated START. Setting this bit always generates a repeated START condition on the bus, provides the device with the current bus master. Attempting a repeated START at the wrong time (or if the bus is owned by another master), results in loss of arbitration. Note that this bit is not readable, which means if a read is performed to I2CCR[RSTA], a zero value is returned. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 467 I2C memory map/register definition I2Cx_I2CCR field descriptions (continued) Field 6 7 BCST 0 No START condition is generated 1 Generates repeated START condition This field is reserved. Description Broadcast 0 Disables the broadcast accept capability 1 Enables the I 2 C to accept broadcast messages at address zero 10.4.4 I2C status register (I2Cx_I2CSR) The I2C status register is read only with the exception of the MIF and MAL bits, which can be cleared by software. The MCF and RXAK bits are set at reset; all other I2CSR bits are cleared on reset. Address: Base address + Ch offset Bit 0 1 2 3 4 5 6 7 Read Write MCF MAAS MBB MAL BCSTM SRW RXAK MIF Reset 1 0 0 0 0 0 0 1 I2Cx_I2CSR field descriptions Field 0 MCF Description Data transfer. When one byte of data is transferred, the bit is cleared. It is set by the falling edge of the 9th clock of a byte transfer. 1 MAAS 0 Byte transfer in progress. MCF is cleared under either of the following conditions: When I2CDR is read in receive mode, When I2CDR is written in transmit mode 1 Byte transfer is completed Addressed as a slave. When the value in I2CDR matches with the calling address, this bit is set. The processor is interrupted, if I2CCR[MIEN] is set. Next, the processor must check the SRW bit and set I2CCR[MTX] accordingly. Writing to the I2CCR automatically clears this bit. 2 MBB 0 Not addressed as a slave 1 Addressed as a slave Bus busy. Indicates the status of the bus. When a START condition is detected, MBB is set. If a STOP condition is detected, it is cleared. 3 MAL 0 I2C bus is idle 1 I2C bus is busy Arbitration lost. Automatically set when the arbitration procedure is lost. Note that the device does not automatically retry a failed transfer attempt. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 468 Freescale Semiconductor, Inc. Field 4 BCSTM 5 SRW 6 MIF 7 RXAK I2Cx_I2CSR field descriptions (continued) Chapter 10 I2C Interfaces Description 0 Arbitration is not lost. Can only be cleared by software 1 Arbitration is lost Broadcast match 0 There has not been a broadcast match. 1 The calling address matches with the broadcast address instead of the programmed slave address. This also sets if this I2C drives an address of all 0s and broadcast mode is enabled. Slave read/write. When MAAS is set, SRW indicates the value of the R/W command bit of the calling address, which is sent from the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave. This bit is valid only when both of the following conditions are true: A complete transfer occurred and no other transfers have been initiated. The I2C interface is configured as a slave and has an address match. By checking this bit, the processor can select slave transmit/receive mode according to the command of the master. Module interrupt. The MIF bit is set when an interrupt is pending, causing a processor interrupt request (provided I2CCR[MIEN] is set). The interrupts for I2C1 and I2C2 are combined into one interrupt, which is sourced by the dual I2C controller. 0 No interrupt is pending. Can be cleared only by software. 1 Interrupt is pending. MIF is set when one of the following events occurs: One byte of data is transferred (set at the falling edge of the 9th clock). The value in I2CADR matches with the calling address in slave-receive mode. Arbitration is lost. Received acknowledge. The value of SDA during the reception of acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicates that an acknowledge signal has been received after the completion of eight bits of data transmission on the bus. If RXAK is high, it means no acknowledge signal has been detected at the 9th clock. 0 Acknowledge received 1 No acknowledge received 10.4.5 I2C data register (I2Cx_I2CDR) Address: Base address + 10h offset Bit 0 1 2 3 4 5 6 7 Read Write DATA Reset 0 0 0 0 0 0 0 0 I2Cx_I2CDR field descriptions Field 0–7 DATA Description Transmission starts when an address and the R/W bit are written to the data register and the I2C interface performs as the master. A data transfer is initiated when data is written to the I2CDR. The most significant bit is sent first in both cases. In master receive mode, reading the data register allows the read to occur, but also allows the I2C module to receive the next byte of data on the I2C interface. In slave mode, the same function is available after it is addressed. Note that in both master receive and slave receive modes, the very first read is always a dummy read. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 469 Functional description 10.4.6 I2C digital filter sampling rate register (I2Cx_I2CDFSRR) The digital filter sampling rate register (I2CDFSRR) is shown in the figure below. Refer to application note AN2919, "Determining the I2C Frequency Divider Ratio for SCL," for additional guidance regarding the proper use of I2CFDR and I2CDFSRR. Address: Base address + 14h offset Bit 0 1 2 3 4 5 6 7 Read Write Reserved DFSR Reset 0 0 0 1 0 0 0 0 I2Cx_I2CDFSRR field descriptions Field 0–1 - 2–7 DFSR This field is reserved. Description Digital filter sampling rate. To assist in filtering out signal noise, the sample rate is programmed. This field is used to prescale the frequency at which the digital filter takes samples from the I2C bus. The resulting sampling rate is calculated by dividing one half the platform (CCBclock) frequency by the non-zero value of DFSR. 10.5 Functional description The I2C unit always performs as a slave receiver as a default, unless explicitly programmed to be a master or slave transmitter. After the boot sequencer has completed (when powered up in boot sequencer mode), the I2C interface performs as a slave receiver. Note that the boot sequencer only functions from the I2C1 interface; the I2C2 interface cannot be used for this purpose. 10.5.1 Transaction protocol A standard I2C transfer consists of the following: • START condition • Slave target address transmission • Data transfer • STOP condition P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 470 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces The following figure shows the interaction of these four parts with the calling address, data byte, and new calling address components of the I2C protocol. The details of the protocol are described in the following sections. SCL 12 34 5 6 78 9 12 34 5 6 78 9 SDA A0 A1 A2 A3 A4 A5 A6 R/W XX XX D0 D1 D2 D3 D4 D5 D6 D7 START Calling address Read/ Write Ack Data byte No ack STOP SCL 12 34 5 6 78 9 12 34 5 6 78 9 SDA A0 A1 A2 A3 A4 A5 A6 R/W A0 A1 A2 A3 A4 A5 A6 R/W START Calling address Read/ Write Ack Repeated START New calling address Figure 10-20. I2C interface transaction protocol No ack STOP 10.5.1.1 START condition When the I2C bus is not engaged (both SDA and SCL lines are at logic high), a master can initiate a transfer by sending a START condition. As shown in Figure 10-20, a START condition is defined as a high-to-low transition of SDA while SCL is high. This condition denotes the beginning of a new data transfer. Each data transfer can contain several bytes and awakens all slaves. The START condition is initiated by a software write that sets I2CCR[MSTA]. 10.5.1.2 Slave address transmission The first byte of data is transferred by the master immediately after the START condition is the slave address. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 471 Functional description This is a seven-bit calling address followed by a R/W_B bit, which indicates the direction of the data being transferred to the slave. Each slave in the system has a unique address. In addition, when the I2C module is operating as a master, it must not transmit an address that is the same as its slave address. An I2C device cannot be master and slave at the same time; if this is attempted, the results are boundedly undefined. Only the slave with a calling address that matches the one transmitted by the master responds by returning an acknowledge bit (pulling the SDA signal low at the 9th clock) as shown in Figure 10-20. If no slave acknowledges the address, the master should generate a STOP condition or a repeated START condition. When slave addressing is successful (and SCL returns to zero), the data transfer can proceed on a byte-to-byte basis in the direction specified by the R/W_B bit sent by the calling master. The I2C module responds to a general call (broadcast) command when I2CCR[BCST] is set. A broadcast address is always zero; however the I2C module does not check the R/ W_B bit. The second byte of the broadcast message is the master address. Because the second byte is automatically acknowledged by hardware, the receiver device software must verify that the broadcast message is intended for itself by reading the second byte of the message. If the master address is for another receiver device and the third byte is a write command, software can ignore the third byte during the broadcast. If the master address is for another receiver device and the third byte is a read command, software must write 0xFF to I2CDR with I2CCR[TXAK] = 1, so that it does not interfere with the data written from the addressed device. Each data byte is 8 bits long. Data bits can be changed only while SCL is low and must be held stable while SCL is high, as shown in Figure 10-20. There is one clock pulse on SCL for each data bit, and the most significant bit (msb) is transmitted first. Each byte of data must be followed by an acknowledge bit, which is signaled from the receiving device by pulling the SDA line low at the 9th clock. Therefore, one complete data byte transfer takes 9 clock pulses. Several bytes can be transferred during a data transfer session. If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The master can then generate a stop condition to abort the data transfer or a START condition (repeated START) to begin a new calling. If the master receiver does not acknowledge the slave transmitter after a byte of transmission, the slave interprets that the end-of-data has been reached. Then the slave releases the SDA line for the master to generate a STOP or a START condition. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 472 Freescale Semiconductor, Inc. 10.5.1.3 Repeated START condition Chapter 10 I2C Interfaces Figure 10-20 shows a repeated START condition, which is generated without a STOP condition that can terminate the previous transfer. The master uses this method to communicate with another slave or with the same slave in a different mode (transmit/ receive mode) without releasing the bus. 10.5.1.4 STOP condition The master can terminate the transfer by generating a STOP condition to free the bus. A STOP condition is defined as a low-to-high transition of the SDA signal while SCL is high. For more information, see Figure 10-20. Note that a master can generate a STOP even if the slave has transmitted an acknowledge bit, at which point the slave must release the bus. The STOP condition is initiated by a software write that clears I2CCR[MSTA]. As described in Repeated START condition, the master can generate a START condition followed by a calling address without generating a STOP condition for the previous transfer. This is called a repeated START condition. 10.5.1.5 Protocol implementation details The following sections provide details about how aspects of the protocol are implemented in this I2C module. 10.5.1.5.1 Transaction monitoring-implementation details The different conditions of the I2C data transfers are monitored as follows: • START conditions are detected when an SDA fall occurs while SCL is high. • STOP conditions are detected when an SDA rise occurs while SCL is high. • Data transfers in progress are canceled when a STOP condition is detected or if there is a slave address mismatch. Cancellation of data transactions resets the clock module. • The bus is detected to be busy upon the detection of a START condition, and idle upon the detection of a STOP condition. 10.5.1.5.2 Control transfer-implementation details The I2C module contains logic that controls the output to the serial data (SDA) and serial clock (SCL) lines of the I2C. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 473 Functional description The SCL output is pulled low as determined by the internal clock generated in the clock module. The SDA output can only change at the midpoint of a low cycle of the SCL, unless it is performing a START, STOP, or restart condition. Otherwise, the SDA output is held constant. The SDA signal is pulled low when one or more of the following conditions are true in either master or slave mode: • Master mode • Data bit (transmit) • Ack bit (receive) • START condition • STOP condition • Restart condition • Slave mode • Acknowledging address match • Data bit (transmit) • Ack bit (receive) The SCL signal corresponds to the internal SCL signal when one or more of the following conditions are true in either master or slave mode: • Master mode • Bus owner • Lost arbitration • START condition • STOP condition • Restart condition begin • Restart condition end • Slave mode • Address cycle • Transmit cycle • Ack cycle 10.5.1.6 Address compare-implementation details Address compare block determines if a slave has been properly addressed, either by its slave address or by the general broadcast address (which addresses all slaves). The three performed address comparisons are described as follows: • Whether a broadcast message has been received, to update the I2CSR P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 474 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces • Whether the module has been addressed as a slave, to update the I2CSR and to generate an interrupt • If the address transmitted by the current master matches the general broadcast address 10.5.2 Arbitration procedure The I2C interface is a true multiple-master bus that allows more than one master device to be connected on it. If two or more masters simultaneously try to control the bus, each master's clock synchronization procedure (including the I2C module) determines the bus clock-the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. A bus master loses arbitration if it transmits a logic 1 on SDA while another master transmits a logic 0. The losing masters immediately switch to slavereceive mode and stop driving the SDA line. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, the I2C unit sets the I2CSR[MAL] status bit to indicate the loss of arbitration and, as a slave, services the transaction if it is directed to itself. If the I2C module is enabled in the middle of an ongoing byte transfer, the interface behaves as follows: • Slave mode-The I2C module ignores the current transfer on the bus and starts operating whenever a subsequent START condition is detected. • Master mode-The I2C module cannot tell whether the bus is busy; therefore, if a START condition is initiated, the current bus cycle can be corrupted. This ultimately results in the current bus master of the I2C interface losing arbitration, after which bus operations return to normal. 10.5.2.1 Arbitration control The arbitration control block controls the arbitration procedure of the master mode. A loss of arbitration occurs whenever the master detects a 0 on the external SDA line while attempting to drive a 1, tries to generate a START or restart at an inappropriate time, or detects an unexpected STOP request on the line. In master mode, arbitration by the master is lost (and I2CSR[MAL] is set) under the following conditions: P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 475 Functional description • SDA samples low when the master drives high during an address or data-transmit cycle (transmit). • SDA samples low when the master drives high during a data-receive cycle of the acknowledge (Ack) bit (receive). • A START condition is attempted when the bus is busy. • A repeated START condition is requested in slave mode. • A start condition is attempted when the requesting device is not the bus owner • Unexpected STOP condition detected Note that the I2C module does not automatically retry a failed transfer attempt. 10.5.3 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices can hold SCL low after completion of a 1-byte transfer (9 bits). In such cases, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 10.5.4 Clock control The clock control block handles requests from the clock signal for transferring and controlling data for multiple tasks. A 9-cycle data transfer clock is requested for the following conditions: • Master mode • Transmit slave address after START condition • Transmit slave address after restart condition • Transmit data • Receive data • Slave mode • Transmit data • Receive data • Receive slave address after START or restart condition 10.5.4.1 Clock synchronization Due to the wire AND logic on the SCL line, a high-to-low transition on the SCL line affects all devices connected on the bus. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 476 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces The devices begin counting their low period when the master drives the SCL line low. After a device has driven SCL low, it holds the SCL line low until the clock high state is reached. However, the change of low-to-high in a device clock may not change the state of the SCL line if another device is still within its low period. Therefore, the synchronized clock signal, SCL, is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time. When all devices concerned have counted off their low period, the synchronized SCL line is released and pulled high. Then there is no difference between the devices' clocks and the state of the SCL line, and all the devices begin counting their high periods. The first device to complete its high period pulls the SCL line low again. 10.5.4.2 Input synchronization and digital filter The following sections describes the synchronizing of the input signals and the filtering of the SCL and SDA lines in detail. 10.5.4.2.1 Input signal synchronization The input synchronization block synchronizes the input SCL and SDA signals to the system clock and detects transitions of these signals. 10.5.4.2.2 Filtering of SCL and SDA lines The SCL and SDA inputs are filtered to eliminate noise. Three consecutive samples of the SCL and SDA lines are compared to a pre-determined sampling rate. If they are all high, the output of the filter is high. If they are all low, the output is low. If they are any combination of highs and lows, the output is whatever the value of the line was in the previous clock cycle. The sampling rate is equal to a binary value stored in the frequency register I2CDFSRR. The duration of the sampling cycle is controlled by a down counter. This allows a software write to the frequency register to control the filtered sampling rate. 10.5.4.3 Clock stretching Slaves can use the clock synchronization mechanism to slow down the transfer bit rate. After the master has driven the SCL line low, the slave can drive SCL low for the required period and then release it. If the slave SCL low period is greater than the master SCL low period, then the resulting SCL bus signal low period is stretched. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 477 Functional description 10.5.5 Boot sequencer mode If boot sequencer mode is selected on POR (by the settings on the cfg_boot_seq[0:1] reset configuration signals, as described in Boot sequencer configuration), the I2C1 module communicates with one or more EEPROMs through the I2C interface on IIC1_SCL and IIC1_SDA. The boot sequencer accesses the I2C1 serial ROM device at a serial bit clock frequency equal to the platform ( CCB) clock frequency divided by 2560. The EEPROM(s) can be programmed to initialize one or more configuration registers of this integrated device. If the boot sequencer is enabled for normal I2C addressing mode, the I2C interface initiates the following sequence during reset: 1. Generate RESET sequence (START then 9 SCL cycles) to the EEPROM twice. This clears any transactions that may have been in progress prior to the reset. 2. Generate START 3. Transmit 0xA0 which is the 7-bit calling address (0b101_0000) with a write command appended (0 as the least significant bit). 4. Transmit 0x00 which is the 8-bit starting address 5. Generate a repeated START 6. Transmit 0xA1 which is the 7-bit calling address (0b101_0000) with a read command appended (1 as the least significant bit). 7. Receive 256 bytes of data from the EEPROM (unless the CONT bit is cleared in the data structure). 8. Generate a repeated START 9. Transmit 0xA2 which is the 7-bit calling address of the second target (0b101_0001) with a write command appended (0 as the least significant bit). 10. Transmit 0x00 which is the 8-bit starting address for the second target. 11. Generate a repeated START 12. Transmit 0xA3 which is the 7-bit calling address (0b101_0001) with a read command appended (1 as the least significant bit). 13. Receive another 256 bytes of data from the second EEPROM (unless the CONT bit is cleared in the data structure). The sequence repeats with successive targets until the CONT bit in the data structure is cleared and the CRC check is executed. If the last register is not detected (that is, the CONT bit is never cleared) before wrapping back to the first address, an error condition is detected, causing the device to hang and the HRESET_REQ_B signal to assert externally. The I2C module continues to read from the EEPROM(s) as long as the P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 478 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces continue (CONT) bit is set in the EEPROM(s). The CONT bit resides in the address/ attributes field that is transferred from the EEPROM, as described in EEPROM calling address. There should be no other I2C traffic when the boot sequencer is active. The boot sequencer mode also supports an extension of the standard I2C interface that uses more address bits to allow for EEPROM devices that have more than 256 bytes, and this extended addressing mode is selectable during POR with a different encoding on the cfg_boot_seq[0:1] reset configuration signals. In this mode, only one EEPROM device may be used, and the maximum number of registers is limited by the size of the EEPROM. If the boot sequencer is enabled for extended I2C addressing mode, the I2C interface initiates the following sequence during reset: 1. Generate RESET sequence (START then 9 SCL cycles) to the EEPROM twice. This clears any transactions that may have been in progress prior to the reset. 2. Generate START 3. Transmit 0xA0 which is the 7-bit calling address (0b101_0000) with a write command appended (0 as the least significant bit). 4. Transmit 0x00 which is the high-order starting address 5. Transmit 0x00 which is the low-order starting address 6. Generate a repeated START 7. Transmit 0xA1 which is the 7-bit calling address (0b101_0000) with a read command appended (1 as the least significant bit). 8. Receive data continuously from the EEPROM until the CONT bit is cleared and the CRC check is executed. See EEPROM data format, for more information. Note that as described in Boot sequencer configuration, the default value for the cfg_boot_seq[0:1] reset configuration pins is 0b11, which corresponds to the I2C boot sequencer being disabled at power-up. 10.5.5.1 EEPROM calling address The device uses 0b101_0000 for the EEPROM calling address. The first EEPROM to be addressed must be programmed to respond to this address, or an error is generated. If more EEPROMs are used, they are addressed in sequential order. 10.5.5.2 EEPROM data format The I2C module expects that a particular data format be used for data in the EEPROM. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 479 Functional description A preamble should be the first 3 bytes programmed into the EEPROM. It should have a value of 0xAA_55AA. The I2C module checks to ensure that this preamble is correctly detected before proceeding further. Following the preamble, there should be a series of configuration registers (known as register preloads) programmed into the EEPROM. Each configuration register should be programmed according to a particular format, as shown in Table 10-21. The first 3 bytes hold the attributes and address offset, as follows. The attributes contained are alternate configuration space (ACS), byte enables, and continue (CONT). The boot sequencer expects the address offset to be a 32-bit (word) offset, that is, the 2 low-order bits are not included in the boot sequencer command. For example, to access LAWBAR0 (byte offset of 0x00C08), the boot sequencer ADDR[0:17] should be set to 0x00302. After the first 3 bytes, 4 bytes of data should hold the desired value of the configuration register, regardless of the size of the transaction. Byte enables should be asserted for any byte that is written to the configuration register, and they should be asserted contiguously, creating a 1-, 2-, or 4-byte write to a register. The boot sequencer assumes that a big-endian address is stored in the EEPROM. In addition, byte enable bit 0 (bit 1 of the byte) corresponds to the most-significant byte of data (data[0:7]), and byte enable bit 3 (bit 4 of the byte) corresponds to the LSB of data (data[24:31]). By setting ACS, an alternate configuration space address is prepended to the write request from the boot sequencer. Otherwise, CCSRBAR is prepended to the EEPROM address. If CONT is cleared, the first 3 bytes, including ACS, the byte enables, and the address, must also be cleared. Also, the data contains the final cyclic redundancy check (CRC). A CRC-32 algorithm is used to check the integrity of the data. The polynomial used is: 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32 CRC values are calculated using the above polynomial with a start value of 0xFFFF_FFFF and an XOR with 0x0000_0000. The CRC should cover all bytes stored in the EEPROM prior to the CRC. This includes the preamble, all register preloads, and the first 3 bytes of the last 7-byte preload (which should be all zeros). If a preamble or CRC fail is detected, the device hangs and the external HRESET_REQ_B signal asserts. If there is a preamble fail, the boot sequencer may continue to pull I2C pins low until a hard reset occurs. Table 10-21. EEPROM data format for one register preload command 0 1 ACS BYTE_EN 4 ADDR[2-9] ADDR[10-17] 5 CONT 6 7 ADDR[0-1] Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 480 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces Table 10-21. EEPROM data format for one register preload command (continued) DATA[0-7] DATA[8-15] DATA[16-23] DATA[24-31] Table 10-22 shows an example of the EEPROM contents, including the preamble, data format, and CRC. Table 10-22. EEPROM contents 0 1 1 0 0 1 1 0 ACS ACS ACS 0 0 0 0 0 0 2 3 4 1 0 1 0 1 0 1 0 1 BYTE_EN ADDR[2-9] ADDR[10-17] DATA[0-7] DATA[8-15] DATA[16-23] DATA[24-31] BYTE_EN ADDR[2-9] ADDR[10-17] DATA[0-7] DATA[8-15] DATA[16-23] DATA[24-31] BYTE_EN ADDR[2-9] ADDR[10-17] DATA[0-7] DATA[8-15] DATA[16-23] DATA[24-31] 0 0 0 0 0 0 0 0 0 5 6 7 0 1 0 1 0 1 0 1 0 1 ADDR[0-1] 1 ADDR[0-1] . . . 1 ADDR[0-1] 0 0 0 0 0 0 0 0 0 Preamble First configuration Preload command Second configuration Preload command Last configuration Preload command End command Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 481 Initialization/application information Table 10-22. EEPROM contents (continued) 0 1 2 3 4 5 6 7 CRC[0-7] Cyclic Redundancy Check CRC[8-15] CRC[16-23] CRC[24-31] 10.6 Initialization/application information This section describes some programming guidelines recommended for the I2C interface. See Figure 10-21 for a recommended flowchart for I2C interrupt service routines. The I2C registers in this chapter are shown in big-endian format. If the system is in littleendian mode, software must swap the bytes appropriately. This appropriate byte swapping is needed as I2C registers are byte registers. Also, an msync assembly instruction must be executed after each I2C register read/write access to guarantee inorder execution. The I2C controller does not guarantee its recovery from all illegal I2C bus activity. In addition, a malfunctioning device may hold the bus captive. A good programming practice is for software to rely on a watchdog timer to help recover from I2C bus hangs. The recovery routine should also handle the case when the status bits returned after an interrupt are not consistent with what was expected due to illegal I2C bus protocol behavior. 10.6.1 Initialization sequence A hard reset initializes all the I2C registers to their default states. The following initialization sequence initializes the I2C unit: 1. All I2C registers must be located in a cache-inhibited page. 2. Update I2CFDR[FDR] and select the required division ratio to obtain the SCL frequency from the CCB (platform) clock. Note that the platform frequency must first be divided by two; see I2C frequency divider register (I2C_I2CFDR), for more details. 3. Update I2CADR to define the slave address for this device. 4. Modify I2CCR to select master/slave mode, transmit/receive mode, and interruptenable or disable. 5. Set the I2CCR[MEN] to enable the I2C interface. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 482 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces 10.6.2 Generation of START After initialization, the following sequence can be used to generate START: 1. If the device is connected to a multimaster I2C system, test the state of I2CSR[MBB] to check whether the serial bus is free (I2CSR[MBB] = 0) before switching to master mode. 2. Select master mode (set I2CCR[MSTA]) to transmit serial data and select transmit mode (set I2CCR[MTX]) for the address cycle. 3. Write the slave address being called into I2CDR. The data written to I2CDR[0-6] comprises the slave calling address. I2CCR[MTX] indicates the direction of transfer (transmit/receive) required from the slave. The scenario above assumes that the I2C interrupt bit (I2CSR[MIF]) is cleared. If MIF is set at any time, an I2C interrupt is generated (provided interrupt reporting is enabled with I2CCR[MIEN] =1) so that the I2C interrupt handler can handle the interrupt. Note that the interrupts for I2C1 and I2C2 are combined into one interrupt, which is sourced by the dual I2C controller. 10.6.3 Post-transfer software response Transmission or reception of a byte automatically sets the data transferring bit (I2CSR[MCF]), which indicates that one byte has been transferred. The I2C interrupt bit (I2CSR[MIF]) is also set and an interrupt is generated to the processor if the interrupt function is enabled during the initialization sequence (I2CCR[MIEN] is set).In the interrupt handler, software must take the following steps: 1. Clear I2CSR[MIF]. 2. Read the contents of the I2C data register (I2CDR) in receive mode or write to I2CDR in transmit mode. Note that this causes I2CSR[MCF] to be cleared. See Interrupt service routine flowchart. When an interrupt occurs at the end of the address cycle, the master remains in transmit mode. If master receive mode is required, I2CCR[MTX] must be toggled at this stage. See Interrupt service routine flowchart. If the interrupt function is disabled, software can service the I2CDR in the main program by monitoring I2CSR[MIF]. In this case, I2CSR[MIF] must be polled rather than I2CSR[MCF] because MCF behaves differently when arbitration is lost. Note that P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 483 Initialization/application information interrupt or other bus conditions may be detected before the I2C signals have time to settle. Thus, when polling I2CSR[MIF] (or any other I2CSR bits), software delays may be needed in order to give the I2C signals sufficient time to settle. During slave-mode address cycles (I2CSR[MAAS] is set), I2CSR[SRW] should be read to determine the direction of the subsequent transfer and I2CCR[MTX] should be programmed accordingly. For slave-mode data cycles (MAAS is cleared), I2CSR[SRW] is not valid and I2CCR[MTX] must be read to determine the direction of the current transfer. See Interrupt service routine flowchart, for more details. 10.6.4 Generation of STOP A data transfer ends with a STOP condition generated by the master device. A master transmitter can generate a STOP condition after all the data has been transmitted. If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data (by setting the transmit acknowledge bit (I2CCR[TXAK])) before reading the next-to-last byte of data. At this time, the next-tolast byte of data has already been transferred on the I2C interface, so the last byte does not receive the data acknowledge (because I2CCR[TXAK] is set). Before the interrupt service routine reads the last byte of data, a STOP condition must first be generated. I2CCR[TXAK] must be set before allowing the I2C module to receive the last data byte on the I2C bus. Eventually, I2CCR[TXAK] must be cleared again for subsequent I2C transactions. This can be accomplished when setting up the I2CCR for the next transfer. 10.6.5 Generation of repeated START At the end of a data transfer, if the master still wants to communicate on the bus, it can generate another START condition followed by another slave address without first generating a STOP condition. This is accomplished by setting I2CCR[RSTA]. 10.6.6 Generation of SCL when SDA low It is sometimes necessary to force the I2C module to become the I2C bus master out of reset and drive SCL (even though SDA may already be driven, which indicates that the bus is busy). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 484 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces This can occur when a system reset does not cause all I2C devices to be reset. Thus, SDA can be driven low by another I2C device while this I2C module is coming out of reset and stays low indefinitely. The following procedure can be used to force this I2C module to generate SCL so that the device driving SDA can finish its transaction: 1. Disable the I2C module and set the master bit by setting I2CCR to 0x20 2. Enable the I2C module by setting I2CCR to 0xA0 3. Read the I2CDR 4. Return the I2C module to slave mode by setting I2CCR to 0x80 10.6.7 Slave mode interrupt service routine In the slave interrupt service routine, the module addressed as a slave should be tested to check if a calling of its own address has been received. If I2CSR[MAAS] is set, software should set the transmit/receive mode select bit (I2CCR[MTX]) according to the R/W_B command bit (I2CSR[SRW]). Writing to I2CCR clears MAAS automatically. MAAS is read as set only in the interrupt handler at the end of that address cycle where an address match occurred; interrupts resulting from subsequent data transfers clear MAAS. A data transfer can then be initiated by writing to I2CDR for slave transmits or dummy reading from I2CDR in slave-receive mode. The slave drives SCL low between byte transfers. SCL is released when the I2CDR is accessed in the required mode. 10.6.7.1 Slave transmitter and received acknowledge In the slave transmitter routine, the received acknowledge bit (I2CSR[RXAK]) must be tested before sending the next byte of data. The master signals an end-of-data by not acknowledging the data transfer from the slave. When no acknowledge is received (I2CSR[RXAK] is set), the slave transmitter interrupt routine must clear I2CCR[MTX] to switch the slave from transmitter to receiver mode. A dummy read of I2CDR then releases SCL so that the master can generate a STOP condition. See Interrupt service routine flowchart. 10.6.7.2 Loss of arbitration and forcing of slave mode When a master loses arbitration the following conditions all occur: • I2CSR[MAL] is set P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 485 Initialization/application information • I2CCR[MSTA] is cleared (changing the master to slave mode) • An interrupt occurs (if enabled) at the falling edge of the 9th clock of this transfer Thus, the slave interrupt service routine should first test I2CSR[MAL] and software should clear it if it is set. See Arbitration control, for more information. 10.6.8 Interrupt service routine flowchart The following figure shows an example algorithm for an I2C interrupt service routine. Deviation from the flowchart may result in unpredictable I2C bus behavior. However, in the slave receive mode the interrupt service routine may need to set I2CCR[TXAK] when the next-to-last byte is to be accepted. It is recommended that an msync instruction follow each I2C register read or write to guarantee in-order instruction execution. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 486 Freescale Semiconductor, Inc. Chapter 10 I2C Interfaces Clear I2CSR[MIF] ==1 I2CCR[MSTA] ==0 I2CCR[MTX] ==0 A Master Xmit ==1 Y Last byte? N ==1 I2CSR[MAL] ==0 ==1 I2CSR[RXAK] Generate Stop ==0 N End of address phase for master receive mode? Y Write next byte to I2CDR Y Set I2CCR[TXAK] Only one byte to recieve? N Clear I2CCR[MTX] Read I2CDR (dummy read) Clear I2CSR[MAL] I2CSR[MAAS] ==0 ==1 B EOI Slave Data Cycle ==1 Slave Xmit ==1 I2C SR[RXAK] ==0 Clear I2CCR[MTX] I2CSR[MAAS] ==0 ==1 B I2CCR[MTX] ==0 Slave Recieve Read I2CDR and store Read I2CDR (dummy read) Write next byte to I2CDR N All done Y Set I2CCR[TXAK] EOI A Master Receive N Last byte? Y Y Next-to-last N byte? Set I2CCR[TXAK] Generate STOP Read I2CDR and store EOI Slave Addr. Phase ==1 B I2CSR[SRW] ==0 Set I2CCR[MTX] Clear I2CCR[MTX] Write I2CDR Dummy read EOI EOI FiPg1u0r2e0 1Q0o-r2IQ1.InEtexgarmatepdlePrIo2CcesinstoerrRruefpetresnecrevMicaenuraolu, Rtienve. 6f,lo01w/2c0h1a3rt Freescale Semiconductor, Inc. 487 Initialization/application information P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 488 Freescale Semiconductor, Inc. Chapter 11 DUART This chapter describes the dual universal asynchronous receiver/transmitters (DUART). It describes the functional operation, the initialization sequence, and the programming details for the DUART registers and features. 11.1 Introduction This chapter describes the dual universal asynchronous receiver/transmitters (DUART). It describes the functional operation, the initialization sequence, and the programming details for the DUART registers and features. 11.1.1 Overview The DUART consists of two universal asynchronous receiver/transmitters (UARTs). The UARTs act independently; all references to UART refer to one of these receiver/ transmitters. Each UART is clocked by the platform (CCB) clock. The DUART programming model is compatible with the PC16552D. The UART interface is point to point, meaning that only two UART devices are attached to the connecting signals. As shown in Figure 11-1, each UART module consists of the following: • Receive and transmit buffers • Clear to send (CTS_B) input port and request to send (RTS_B) output port for data flow control • 16-bit counter for baud rate generation • Interrupt control logic P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 489 Introduction Data Address Bus Control Control Logic inint t Interrupt Control HRESET_B platform clock UART Module Internal Bus SIN Receive Buffer Transmit Buffer SOUT Input Port CTS_B Output Port RTS_B 16-Bit Counter/ Baud Rate Generator Figure 11-1. UART block diagram 11.1.1.1 Features The DUART includes these distinctive features: • Full-duplex operation • Programming model compatible with original PC16450 UART and PC16550D (improved version of PC16450 that also operates in FIFO mode) • PC16450 register reset values • FIFO mode for both transmitter and receiver, providing 16-byte FIFOs • Serial data encapsulation and decapsulation with standard asynchronous communication bits (START, STOP, and parity) • Maskable transmit, receive, line status, and modem status interrupts • Software-programmable baud generators that divide the platform clock by 1 to (216 - 1) and generate a 16x clock for the transmitter and receiver engines • Clear to send (CTS_B and ready to send (RTS_B) modem control functions • Software-selectable serial interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate) • Line and modem status registers • Line-break detection and generation P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 490 Freescale Semiconductor, Inc. • Internal diagnostic support, local loopback, and break functions • Prioritized interrupt reporting • Overrun, parity, and framing error detection Chapter 11 DUART 11.1.1.2 Modes of operation The communication channel provides a full-duplex asynchronous receiver and transmitter using an operating frequency derived from the platform clock. The transmitter accepts parallel data from a write to the transmitter holding register (UTHR). In FIFO mode, the data is placed directly into an internal transmitter shift register of the transmitter FIFO. The transmitter converts the data to a serial bit stream inserting the appropriate start, stop, and optional parity bits. Finally, it outputs a composite serial data stream on the channel transmitter serial data output signal (SOUT). The transmitter status may be polled or interrupt driven. The receiver accepts serial data bits on the channel receiver serial data input signal (SIN), converts it to parallel format, checks for a start bit, parity (if any), stop bits, and transfers the assembled character (with start, stop, parity bits removed) from the receiver buffer (or FIFO) in response to a read of the UART's receiver buffer register (URBR). The receiver status may be polled or interrupt driven. 11.2 DUART external signal descriptions The DUART signals are described in Table 11-1. Note that although the actual device signal names are prepended with the UART_ prefix as shown in the table, the functional (abbreviated) signal names are often used throughout this chapter. Table 11-1. DUART signals-detailed signal descriptions Signal UART_SIN[0:1 ] I/O Description I Serial data in. Data is received on the receivers of UART0 and UART1 through the respective serial data input signal, with the least-significant bit received first. State Asserted/Negated-Represents the data being received on the UART interface. meaning Timing Assertion/Negation-An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to sample the data on SIN. Table continues on the next page... P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 491 DUART memory map/register definition Table 11-1. DUART signals-detailed signal descriptions (continued) Signal I/O Description UART_SOUT[0:1 ] O Serial data out. The serial data output signals for the UART0 and UART1 are set ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on these signals, with the least significant bit transmitted first. State Asserted/Negated-Represents the data being transmitted on the respective UART meaning interface. Timing Assertion/Negation- An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to update and drive the data on SOUT. UART_CTS_B[0:1 I ] Clear to send. These active-low inputs are the clear-to-send inputs. They are connected to the respective RTS_B outputs of the other UART devices on the bus. They can be programmed to generate an interrupt on change-of-state of the signal. State Asserted/Negated-Represent the clear to send condition for their respective UART. meaning Timing Assertion/Negation-Sampled at the rising edge of every platform clock. UART_RTS_B[0:1 O ] Request to send. UART_RTS_Bx are active-low output signals that can be programmed to be automatically negated and asserted by either the receiver or transmitter. When connected to the clear-to-send (CTS_B) input of a transmitter, this signal can be used to control serial data flow. State Asserted/Negated-Represents the data being transmitted on the respective UART meaning interface. Timing Assertion/Negation-Updated and driven at the rising edge of every platform clock. 11.3 DUART memory map/register definition The table below lists the DUART registers and their offsets. It lists the address, name, and a cross-reference to the complete description of each register. Note that the full register address is comprised of CCSRBAR together with the block base address and offset listed in the table below. There are two complete sets of DUART registers (one for each UART). The two UARTs on the device are identical, except that the registers for each UART are located at different offsets. Throughout this chapter, the registers are described by a singular acronym: for example, LCR represents the line control register for either UART0 or UART1 . The registers in each UART interface are used for configuration, control, and status. The divisor latch access bit, ULCR[DLAB], is used to access the divisor latch least- and most-significant bit registers and the alternate function register. Refer to Line Control Registers (DUART_ULCRn) , for more information on ULCR[DLAB]. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 492 Freescale Semiconductor, Inc. Chapter 11 DUART All the DUART registers are one-byte wide. Reads and writes to these registers must be byte-wide operations. The table below provides a register summary with references to the section and page that contains detailed information about each register. Undefined byte address spaces within offset 0x000-0xFFF are reserved. DUART memory map Offset address (hex) 4500 4500 4500 4501 4501 4502 4502 4502 4503 4504 4505 4506 4507 4510 4600 4600 4600 4601 4601 4602 4602 4602 4603 4604 4605 4606 4607 4610 Register name Receiver Buffer Registers (DUART_URBR1) Transmitter Holding Registers (DUART_UTHR1) Divisor Least Significant Byte Registers (DUART_UDLB1) Divisor Most Significant Byte Registers (DUART_UDMB1) Interrupt Enable Register (DUART_UIER1) Interrupt ID Registers (DUART_UIIR1) FIFO Control Registers (DUART_UFCR1) Alternate Function Registers (DUART_UAFR1) Line Control Registers (DUART_ULCR1) Modem Control Registers (DUART_UMCR1) Line Status Registers (DUART_ULSR1) Modem Status Registers (DUART_UMSR1) Scratch Registers (DUART_USCR1) DMA Status Registers (DUART_UDSR1) Receiver Buffer Registers (DUART_URBR2) Transmitter Holding Registers (DUART_UTHR2) Divisor Least Significant Byte Registers (DUART_UDLB2) Divisor Most Significant Byte Registers (DUART_UDMB2) Interrupt Enable Register (DUART_UIER2) Interrupt ID Registers (DUART_UIIR2) FIFO Control Registers (DUART_UFCR2) Alternate Function Registers (DUART_UAFR2) Line Control Registers (DUART_ULCR2) Modem Control Registers (DUART_UMCR2) Line Status Registers (DUART_ULSR2) Modem Status Registers (DUART_UMSR2) Scratch Registers (DUART_USCR2) DMA Status Registers (DUART_UDSR2) Width (in bits) Access Reset value Section/ page 8 R 8 W 8 R/W 8 R/W 8 R/W 8 R 8 W 8 R/W 8 R/W 8 R/W 8 R 8 R 8 R/W 8 R 8 R 8 W 8 R/W 8 R/W 8 R/W 8 R 8 W 8 R/W 8 R/W 8 R/W 8 R 8 R 8 R/W 8 R 00h 11.3.1/493 00h 11.3.2/494 00h 11.3.3/495 00h 11.3.4/496 00h 11.3.5/497 01h 11.3.6/497 00h 11.3.7/499 00h 11.3.8/500 00h 11.3.9/501 00h 11.3.10/503 60h 11.3.11/503 00h 11.3.12/505 00h 11.3.13/505 01h 11.3.14/506 00h 11.3.1/493 00h 11.3.2/494 00h 11.3.3/495 00h 11.3.4/496 00h 11.3.5/497 01h 11.3.6/497 00h 11.3.7/499 00h 11.3.8/500 00h 11.3.9/501 00h 11.3.10/503 60h 11.3.11/503 00h 11.3.12/505 00h 11.3.13/505 01h 11.3.14/506 11.3.1 Receiver Buffer Registers (DUART_URBRn) This register is accessible when ULCR[DLAB] = 0. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 493 DUART memory map/register definition These registers contain the data received from the transmitter on the UART buses. In FIFO mode, when read, they return the first byte received. For FIFO status information, refer to the UDSR[RXRDY] description. Except for the case when there is an overrun, URBR returns the data in the order it was received from the transmitter. Refer to the ULSR[OE] description, Line Status Registers (DUART_ULSRn) . Note that these registers have same offset as the UTHRs. Address: 4000h base + 500h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 Read DATA Write Reset 0 0 0 0 0 0 0 0 DUART_URBRn field descriptions Field 0–7 DATA Description Data received from the transmitter on the UART bus (read only) 11.3.2 Transmitter Holding Registers (DUART_UTHRn) This register is accessible when ULCR[DLAB] = 0. A write to these 8-bit registers causes the UART devices to transfer 5-8 data bits on the UART bus in the format set up in the ULCR (line control register). In FIFO mode, data written to UTHR is placed into the FIFO. The data written to UTHR is the data sent onto the UART bus, and the first byte written to UTHR is the first byte onto the bus. UDSR[TXRDY_B] indicates when the FIFO is full. Refer to the tables in DMA Status Registers (DUART_UDSRn) for more details. Address: 4000h base + 500h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 Read Write DATA Reset 0 0 0 0 0 0 0 0 DUART_UTHRn field descriptions Field 0–7 DATA Data that is written to UTHR (write only) Description P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 494 Freescale Semiconductor, Inc. Chapter 11 DUART 11.3.3 Divisor Least Significant Byte Registers (DUART_UDLBn) This register is accessible when ULCR[DLAB] = 1. The divisor least significant byte register (UDLB) is concatenated with the divisor most significant byte register (UDMB) to create the divisor used to divide the input clock into the DUART. The output frequency of the baud generator is 16 times the baud rate; therefore the desired baud rate = platform clock frequency ÷ (16 x [UDMB||UDLB]). Equivalently, [UDMB||UDLB:0b0000] = platform clock frequency ÷ desired baud rate. Baud rates that can be generated by specific input clock frequencies are shown in the table below. The following table shows examples of baud rate generation based on common input clock frequencies. Many other target baud rates are also possible. Note that because only integer values can be used as divisors, the actual baud rate differs slightly from the desired (target) baud rate; for this reason, both target and actual baud rates are given, along with the percentage of error. Table 11-7. Baud Rate Examples Target Baud Rate (Decimal) 9,600 19,200 38,400 57,600 115,200 230,400 9,600 19,200 38,400 57,600 115,200 230,400 9,600 19,200 38,400 57,600 115,200 230,400 Divisor Decimal Hex 1736 6C8 868 364 434 1B2 289 121 145 91 72 48 2170 87A 1085 43D 543 21F 362 16A 181 B5 90 5A 3472 D90 1736 6C8 868 364 579 243 289 121 145 91 Platform Clock ( CCB ) Frequency (MHz) 266 266 266 266 266 266 333 333 333 333 333 333 533 533 533 533 533 533 Actual Baud Rate (Decimal) 9600.61444 19,201.22888 38,402.45776 57,670.12673 114,942.52844 231,481.48090 9600.61444 19,201.22888 38,367.09638 57,550.64457 115,101.28913 231,481.48148 9600.61444 19,201.22888 38,402.45776 57,570.52389 115,340.25375 229,885.05747 Table continues on the next page... Percent Error (Decimal) 0.0064 0.0064 0.0064 0.1217 0.2235 0.4694 0.0064 0.0064 0.0858 0.0857 0.0857 0.4694 0.0064 0.0064 0.0064 0.0512 0.1217 0.2235 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 495 DUART memory map/register definition Table 11-7. Baud Rate Examples (continued) Target Baud Rate (Decimal) 9,600 19,200 38,400 57,600 115,200 230,400 Divisor Decimal Hex 3906 F42 1953 7A1 977 3D1 651 28B 326 146 163 A3 Platform Clock ( CCB ) Frequency (MHz) 600 600 600 600 600 600 Actual Baud Rate (Decimal) 9600.6144 19,201.2288 38382.8045 57603.6866 115030.6748 230061.3497 Percent Error (Decimal) 0.0064 0.0064 0.0448 0.0064 0.1470 0.1470 Address: 4000h base + 500h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 Read Write UDLB Reset 0 0 0 0 0 0 0 0 DUART_UDLBn field descriptions Field 0–7 UDLB Description Divisor least significant byte. This is concatenated with UDMB. 11.3.4 Divisor Most Significant Byte Registers (DUART_UDMBn) This register is accessible when ULCR[DLAB] = 1. The divisor least significant byte register (UDLB) is concatenated with the divisor most significant byte register (UDMB) to create the divisor used to divide the input clock into the DUART. The output frequency of the baud generator is 16 times the baud rate; therefore the desired baud rate = platform clock frequency ÷ (16 x [UDMB||UDLB]). Equivalently, [UDMB||UDLB:0b0000] = platform clock frequency ÷ desired baud rate. Baud rates that can be generated by specific input clock frequencies are shown in the table in Divisor Least Significant Byte Registers (DUART_UDLBn) . Address: 4000h base + 501h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 Read Write UDMB Reset 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 496 Freescale Semiconductor, Inc. Field 0–7 UDMB DUART_UDMBn field descriptions Divisor most significant byte Description Chapter 11 DUART 11.3.5 Interrupt Enable Register (DUART_UIERn) This register is accessible when ULCR[DLAB] = 0. The UIER gives the user the ability to mask specific UART interrupts to the programmable interrupt controller (PIC). Address: 4000h base + 501h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 Read Write Reserved Reset 0 0 0 0 4 EMSI 0 5 ERLSI 0 6 ETHREI 0 7 ERDAI 0 DUART_UIERn field descriptions Field 0–3 4 EMSI 5 ERLSI 6 ETHREI 7 ERDAI This field is reserved. Reserved. Enable modem status interrupt. Description 0 Mask interrupts caused by UMSR[DCTS] being set 1 Enable and assert interrupts when the clear-to-send bit in the UART modem status register (UMSR) changes state Enable receiver line status interrupt. 0 Mask interrupts when ULSR's overrun, parity error, framing error or break interrupt bits are set 1 Enable and assert interrupts when ULSR's overrun, parity error, framing error or break interrupt bits are set Enable transmitter holding register empty interrupt. 0 Mask interrupt when ULSR[THRE] is set 1 Enable and assert interrupts when ULSR[THRE] is set Enable received data available interrupt. 0 Mask interrupt when new receive data is available or receive data time out has occurred 1 Enable and assert interrupts when a new data character is received from the external device and/or a time-out interrupt occurs in the FIFO mode 11.3.6 Interrupt ID Registers (DUART_UIIRn) This register is accessible when ULCR[DLAB] = 0. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 497 DUART memory map/register definition The UIIRs indicate when an interrupt is pending from the corresponding UART and what type of interrupt is active. They also indicate if the FIFOs are enabled. The DUART prioritizes interrupts into four levels and records these in the corresponding UIIR. The four levels of interrupt conditions in order of priority are: 1. Receiver line status 2. Received data ready/character time-out 3. Transmitter holding register empty 4. Modem status When the UIIR is read, the associated DUART serial channel freezes all interrupts and indicates the highest priority pending interrupt. While this read transaction is occurring, the associated DUART serial channel records new interrupts, but does not change the contents of UIIR until the read access is complete. Table 11-15. UIIR IID Bits Summary IID Bits IID[3-0] 0b0001 0b0110 Priority Level Highest 0b0100 Second 0b1100 Second 0b0010 0b0000 Third Fourth Interrupt Type Interrupt Description How To Reset Interrupt - - - Receiver line status Overrun error, parity error, framing error, or break interrupt Read the line status register. Received data available Receiver data available Read the receiver or trigger level reached buffer register or in FIFO mode interrupt is automatically reset if the number of bytes in the receiver FIFO drops below the trigger level. Character time-out No characters have been removed from or input to the receiver FIFO during the last 4 character times and there is at least one character in the receiver FIFO during this time. Read the receiver buffer register. UTHR empty Transmitter holding register is empty Read the UIIR or write to the UTHR. Modem status CTS_B input value Read the UMSR. changed since last read of UMSR P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 498 Freescale Semiconductor, Inc. Chapter 11 DUART Address: 4000h base + 502h offset + (256d × i), where i=0d to 1d Bit Read Write 0 1 FE 2 3 Reserved 4 5 6 7 IID3 IID2 IID1 IID0 Reset 0 0 0 0 0 0 0 1 DUART_UIIRn field descriptions Field 0–1 FE 2–3 - 4 IID3 5 IID2 6 IID1 7 IID0 Description FIFOs enabled. Reflects the setting of UFCR[FEN] This field is reserved. Reserved Interrupt ID bits identify the highest priority interrupt that is pending as indicated in Table 11-15 . IID3 is set along with IID2 only when a timeout interrupt is pending for FIFO mode. Interrupt ID bits identify the highest priority interrupt that is pending as indicated in Table 11-15 . Interrupt ID bits identify the highest priority interrupt that is pending as indicated in Table 11-15 . IID0 indicates when an interrupt is pending. 0 The UART has an active interrupt ready to be serviced. 1 No interrupt is pending. 11.3.7 FIFO Control Registers (DUART_UFCRn) This register is accessible when ULCR[DLAB] = 0. The UFCR, a write-only register, is used to enable and clear the receiver and transmitter FIFOs, set a receiver FIFO trigger level to control the received data available interrupt, and select the type of DMA signaling. When the UFCR bits are written, the FIFO enable bit must also be set or else the UFCR bits are not programmed. When changing from FIFO mode to 16450 mode (non-FIFO mode) and vice versa, data is automatically cleared from the FIFOs. After all the bytes in the receiver FIFO are cleared, the receiver internal shift register is not cleared. Similarly, the bytes are cleared in the transmitter FIFO, but the transmitter internal shift register is not cleared. Both TFR and RFR are self-clearing bits. Address: 4000h base + 502h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 Read Write RTL Reserved Reset 0 0 0 0 4 DMS 0 5 TFR 0 6 RFR 0 7 FEN 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 499 DUART memory map/register definition DUART_UFCRn field descriptions Field 0–1 RTL Description Receiver trigger level. A received data available interrupt occurs when UIER[ERDAI] is set and the number of bytes in the receiver FIFO equals the designated interrupt trigger level as follows: 2–3 4 DMS 5 TFR 6 RFR 7 FEN 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes This field is reserved. Reserved DMA mode select. See DMA mode select for more information. 0 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 0. 1 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 1 if UFCR[FEN] = 1. Transmitter FIFO reset 0 No action 1 Clears all bytes in the transmitter FIFO and resets the FIFO counter/pointer to 0 Receiver FIFO reset 0 No action 1 Clears all bytes in the receiver FIFO and resets the FIFO counter/pointer to 0 FIFO enable 0 FIFOs are disabled and cleared 1 Enables the transmitter and receiver FIFOs 11.3.8 Alternate Function Registers (DUART_UAFRn) This register is accessible when ULCR[DLAB] = 1. The UAFRs give software the ability to gate off the baud clock and write to both UART0/UART1 registers simultaneously with the same write operation. Address: 4000h base + 502h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 4 5 Read Write Reserved Reset 0 0 0 0 0 0 DUART_UAFRn field descriptions Field 0–5 - 6 BO This field is reserved. Reserved. Baud clock select. Description Table continues on the next page... 6 7 BO CW 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 500 Freescale Semiconductor, Inc. Field 7 CW DUART_UAFRn field descriptions (continued) Chapter 11 DUART 0 The baud clock is not gated off. 1 The baud clock is gated off. Concurrent write enable. Description 0 Disables writing to both UART0 and UART1 1 Enables concurrent writes to corresponding UART registers. A write to a register in UART0 is also a write to the corresponding register in UART1 and vice versa . The user needs to ensure that the LCR[DLAB] of both UARTs are in the same state before executing a concurrent write to register addresses 0x n 00, 0x n 01 and 0x n 02, where n is the offset of the corresponding UART. 11.3.9 Line Control Registers (DUART_ULCRn) This register is accessible when ULCR[DLAB] = x. The ULCRs specify the data format for the UART bus and set the divisor latch access bit ULCR[DLAB], which controls the ability to access the divisor latch least and most significant bit registers and the alternate function register. After initializing the ULCR, the software should not re-write the ULCR when valid transfers on the UART bus are active. The software should not re-write the ULCR until the last STOP bit has been received and there are no new characters being transferred on the bus. The stick parity bit, ULCR[SP], assigns a set parity value for the parity bit time slot sent on the UART bus. The set value is defined as mark parity (logic 1) or space parity (logic 0). ULCR[PEN] and ULCR[EPS] help determine the set parity value. See Table 11-23 for more information. ULCR[NSTB], defines the number of STOP bits to be sent at the end of the data transfer. The receiver only checks the first STOP bit, regardless of the number of STOP bits selected. The word length select bits (1 and 0) define the number of data bits that are transmitted or received as a serial character. The word length does not include START, parity, and STOP bits. Table 11-23. Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS] PEN 0 0 0 0 1 1 SP 0 0 1 1 0 0 EPS 0 1 0 1 0 1 Table continues on the next page... Parity Selected No parity No parity No parity No parity Odd parity Even parity P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 501 DUART memory map/register definition Table 11-23. Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS] (continued) PEN 1 1 SP 1 1 EPS 0 1 Parity Selected Mark parity Space parity Address: 4000h base + 503h offset + (256d × i), where i=0d to 1d Bit 0 1 Read Write DLAB SB Reset 0 0 2 3 SP EPS 0 0 4 PEN 0 5 NSTB 0 6 7 WLS 0 0 DUART_ULCRn field descriptions Field 0 DLAB 1 SB 2 SP 3 EPS 4 PEN 5 NSTB 6–7 WLS Divisor latch access bit. Description 0 Access to all registers except UDLB, UAFR, and UDMB 1 Ability to access divisor latch least and most significant byte registers and alternate function register (UAFR) Set break. 0 Send normal UTHR data onto the serial output (SOUT) signal 1 Force logic 0 to be on the SOUT signal. Data in the UTHR is not affected Stick parity. 0 Stick parity is disabled. 1 If PEN = 1 and EPS = 1, space parity is selected. And if PEN = 1 and EPS = 0, mark parity is selected. Even parity select. See Table 11-23 for more information. 0 If PEN = 1 and SP = 0, odd parity is selected. 1 If PEN = 1 and SP = 0, even parity is selected. Parity enable. 0 No parity generation and checking 1 Generate parity bit as a transmitter, and check parity as a receiver Number of STOP bits. 0 One STOP bit is generated in the transmitted data. 1 When a 5-bit data length is selected, 1½ STOP bits are generated. When either a 6-, 7-, or 8-bit word length is selected, two STOP bits are generated. Word length select. Number of bits that comprise the character length. The word length select values are as follows: 00 5 bits 01 6 bits 10 7 bits 11 8 bits P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 502 Freescale Semiconductor, Inc. Chapter 11 DUART 11.3.10 Modem Control Registers (DUART_UMCRn) This register is accessible when ULCR[DLAB] = x. The UMCRs control the interface with the external peripheral device on the UART bus. Address: 4000h base + 504h offset + (256d × i), where i=0d to 1d Bit 0 1 2 Read Write Reserved Reset 0 0 0 3 LOOP 0 4 5 Reserved 0 0 6 RTS 0 7 Reserved 0 DUART_UMCRn field descriptions Field 0–2 3 LOOP 4–5 6 RTS 7 - This field is reserved. Reserved. Local loopback mode. Description 0 Normal operation 1 Functionally, the data written to UTHR can be read from URBR of the same UART , and UMCR[RTS] is tied to UMSR[CTS] . This field is reserved. Reserved. Ready to send. 0 Negates corresponding RTS_B output 1 Assert corresponding RTS_B output. Informs external modem or peripheral that the UART is ready for sending/receiving data This field is reserved. Reserved. 11.3.11 Line Status Registers (DUART_ULSRn) This register is accessible when ULCR[DLAB] = x. The ULSRs are read-only registers that monitor the status of the data transfer on the UART buses. To isolate the status bits from the proper character received through the UART bus, software should read the ULSR and then the URBR. Address: 4000h base + 505h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 Read RFE TEMT THRE BI FE PE OE DR Write Reset 0 1 1 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 503 DUART memory map/register definition DUART_ULSRn field descriptions Field 0 RFE 1 TEMT 2 THRE 3 BI 4 FE 5 PE 6 OE 7 DR Receiver FIFO error. Description 0 This bit is cleared when there are no errors in the receiver FIFO or on a read of the ULSR with no remaining receiver FIFO errors. 1 Set to one when one of the characters in the receiver FIFO encounters an error (framing, parity, or break interrupt) Transmitter empty. 0 Either or both the UTHR or the internal transmitter shift register has a data character. In FIFO mode, a data character is in the transmitter FIFO or the internal transmitter shift register. 1 Both the UTHR and the internal transmitter shift register are empty. In FIFO mode, both the transmitter FIFO and the internal transmitter shift register are empty. Transmitter holding register empty. 0 The UTHR is not empty. 1 A data character has transferred from the UTHR into the internal transmitter shift register. In FIFO mode, the transmitter FIFO contains no data character. Break interrupt. 0 This bit is cleared when the ULSR is read or when a valid data transfer is detected (that is, STOP bit is received). 1 Received data of logic 0 for more than START bit + Data bits + Parity bit + one STOP bits length of time. A new character is not loaded until SIN returns to the mark state (logic 1) and a valid START is detected. In FIFO mode, a zero character is encountered in the FIFO (the zero character is at the top of the FIFO). In FIFO mode, only one zero character is stored. Framing error. 0 This bit is cleared when ULSR is read or when a new character is loaded into the URBR from the receiver shift register. 1 Invalid STOP bit for receive data (only the first STOP bit is checked). In FIFO mode, this bit is set when the character that detected a framing error is encountered in the FIFO (that is the character at the top of the FIFO). An attempt to resynchronize occurs after a framing error. The UART assumes that the framing error (due to a logic 0 being read when a logic 1 (STOP) was expected) was due to a STOP bit overlapping with the next START bit, so it assumes this logic 0 sample is a true START bit and then receives the following new data. Parity error. 0 This bit is cleared when ULSR is read or when a new character is loaded into the URBR. 1 Unexpected parity value encountered when receiving data. In FIFO mode, the character with the error is at the top of the FIFO . Overrun error. 0 This bit is cleared when ULSR is read. 1 Before the URBR is read, the URBR was overwritten with a new character. The old character is loss. In FIFO mode, the receiver FIFO is full (regardless of the receiver FIFO trigger level setting) and a new character has been received into the internal receiver shift register. The old character was overwritten by the new character. Data in the receiver FIFO was not overwritten. Data ready. 0 This bit is cleared when URBR is read or when all of the data in the receiver FIFO is read. 1 A character has been received in the URBR or the receiver FIFO. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 504 Freescale Semiconductor, Inc. Chapter 11 DUART 11.3.12 Modem Status Registers (DUART_UMSRn) This register is accessible when ULCR[DLAB] = x. The UMSRs track the status of the modem (or external peripheral device) clear to send ( CTS_B ) signal for the corresponding UART . Address: 4000h base + 506h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 Read Write Reserved CTS Reset 0 0 0 0 4 5 6 Reserved 0 0 0 7 DCTS 0 DUART_UMSRn field descriptions Field 0–2 3 CTS 4–6 7 DCTS Description This field is reserved. Reserved. Clear to send. Represents the inverted value of the CTS_B input pin from the external peripheral device 0 Corresponding CTS_B n is negated 1 Corresponding CTS_B n is asserted. The modem or peripheral device is ready for data transfers. This field is reserved. Reserved. Clear to send. 0 No change on the corresponding CTS_B n signal since the last read of UMSR[CTS] 1 The CTS_B n value has changed, since the last read of UMSR[CTS]. Causes an interrupt if UIER[EMSI] is set to detect this condition 11.3.13 Scratch Registers (DUART_USCRn) This register is accessible when ULCR[DLAB] = x. The USCR registers are for debugging software or the DUART hardware. The USCRs do not affect the operation of the DUART. Address: 4000h base + 507h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 Read Write DATA Reset 0 0 0 0 0 0 0 0 P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 505 DUART memory map/register definition DUART_USCRn field descriptions Field 0–7 DATA Data Description 11.3.14 DMA Status Registers (DUART_UDSRn) This register is accessible when ULCR[DLAB] = x. The DMA status registers (UDSRs) are read-only registers that return transmitter and receiver FIFO status. UDSRs also provide the ability to assist DMA data operations to and from the FIFOs. Table 11-35. UDSR[TXRDY] Set Conditions DMS 0 0 1 1 FEN 0 1 0 1 DMA Mode 0 0 0 1 Meaning TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR. TXRDY is set when the transmitter FIFO is full. Table 11-36. UDSR[TXRDY] Cleared Conditions DMS 0 0 1 1 FEN 0 1 0 1 DMA Mode 0 0 0 1 Meaning TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR. TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR. TXRDY remains clear when the transmitter FIFO is not yet full. DMS 0 0 1 1 Table 11-37. UDSR[RXRDY] Set Conditions FEN 0 1 0 1 DMA Mode 0 0 0 1 Meaning RXRDY is set when there are no characters in the receiver FIFO or URBR. RXRDY is set when the trigger level has not been reached and there has been no time out. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 506 Freescale Semiconductor, Inc. Chapter 11 DUART Table 11-38. UDSR[RXRDY] Cleared Conditions DMS 0 0 1 1 FEN 0 1 0 1 DMA Mode 0 0 0 1 Meaning RXRDY is cleared when there is at least one character in the receiver FIFO or URBR. RXRDY is cleared when the trigger level or a time-out has been reached. RXRDY remains cleared until the receiver FIFO is empty. Address: 4000h base + 510h offset + (256d × i), where i=0d to 1d Bit 0 1 2 3 4 Read Write Reserved Reset 0 0 0 0 0 5 6 7 TXRDY RXRDY 0 0 1 DUART_UDSRn field descriptions Field 0–5 - 6 TXRDY Description This field is reserved. Reserved Transmitter ready. This read-only bit reflects the status of the transmitter FIFO or the UTHR. The status depends on the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR. 7 RXRDY 0 This bit is cleared, as shown in Table 11-36 . 1 This bit is set, as shown in Table 11-35 . Receiver ready. This read-only bit reflects the status of the receiver FIFO or URBR. The status depends on the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR. 0 This bit is cleared, as shown in Table 11-38 . 1 This bit is set, as shown in Table 11-37 . 11.4 Functional description The communication channel provides a full-duplex asynchronous receiver and transmitter using an operating frequency derived from the platform clock signal. The transmitter accepts parallel data with a write access to the transmitter holding register (UTHR). In FIFO mode, the data is placed directly into an internal transmitter shift register, or into the transmitter FIFO-see FIFO mode. The transmitting registers convert the data to a serial bit stream, by inserting the appropriate START, STOP, and optional P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 507 Functional description parity bits. Finally, the registers output a composite serial data stream on the channel transmitter serial data output (SOUT). The transmitter status may be polled or interruptdriven. The receiver accepts serial data on the channel receiver serial data input (SIN), converts the data into parallel format, and checks for START, STOP, and parity bits. In FIFO mode, the receiver removes the START, STOP, and parity bits and then transfers the assembled character from the receiver buffer, or receiver FIFO. This transfer occurs in response to a read of the UART receiver buffer register (URBR). The receiver status may be polled or interrupt driven. 11.4.1 Serial interface The UART bus is a serial, full-duplex, point-to-point bus as shown in Figure 11-44. Therefore, only two devices are attached to the same signals and there is no need for address or arbitration bus cycles. Figure 11-44. UART bus interface transaction protocol example A standard UART bus transfer is composed of either three or four parts: • START bit • Data transfer bits (least-significant bit is first data bit on the bus) • Parity bit (optional) • STOP bits An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to drive the bits on SOUT. The following sections describe the four components of the serial interface, the baud-rate generator, local loopback mode, different errors, and FIFO mode. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 508 Freescale Semiconductor, Inc. 11.4.1.1 START bit Chapter 11 DUART A write to the transmitter holding register (UTHR) generates a START bit on the SOUT signal. Figure 11-44 shows that the START bit is defined as a logic 0. The START bit denotes the beginning of a new data transfer which is limited to the bit length programmed in the UART line control register (ULCR). When the bus is idle, SOUT is high. 11.4.1.2 Data transfer Each data transfer contains 5-8 bits of data. The ULCR data bit length for the transmitter and receiver UART devices must agree before a transfer begins; otherwise, a parity or framing error may occur. A transfer begins when UTHR is written. At that time a START bit is generated followed by 5-8 of the data bits previously written to the UTHR. The data bits are driven from the least significant to the most significant bits. After the parity and STOP bits, a new data transfer can begin if new data is written to the UTHR. 11.4.1.3 Parity bit The user has the option of using even, odd, no parity, or stick parity. See Line Control Registers (DUART_ULCRn). Both the receiver and transmitter parity definition must agree before attempting to transfer data. When receiving data a parity error can occur if an unexpected parity value is detected. See Line Status Registers (DUART_ULSRn). 11.4.1.4 STOP bit The transmitter device ends the write transfer by generating a STOP bit. The STOP bit is always high. The user can program the length of the STOP bit(s) in the ULCR. Both the receiver and transmitter STOP bit length must agree before attempting to transfer data. A framing error can occur if an invalid STOP bit is detected. P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 Freescale Semiconductor, Inc. 509 Functional description 11.4.2 Baud-rate generator logic Each UART contains an independent programmable baud-rate generator, that is capable of taking the platform clock input and dividing the input by any divisor from 1 to 216 - 1. The baud rate is defined as the number of bits per second that can be sent over the UART bus. The formula for calculating baud rate is as follows: Baud rate = (1/16) x (platform clock frequency ÷ divisor value) Therefore, the output frequency of the baud-rate generator is 16 times the baud rate. The divisor value is determined by the following two 8-bit registers to form a 16-bit binary number: • UART divisor most significant byte register (UDMB) • UART divisor least significant byte register (UDLB) Upon loading either of the divisor latches, a 16-bit baud-rate counter is loaded. The divisor latches must be loaded during initialization to ensure proper operation of the baud-rate generator. Both UART devices on the same bus must be programmed for the same baud-rate before starting a transfer. The baud clock can be passed to the performance monitor by enabling the UAFR[BO] bit. This can be used to determine baud rate errors. 11.4.3 Local loopback mode Local loopback mode is provided for diagnostic testing. The data written to UTHR can be read from the receiver buffer register (URBR) of the same UART. In this mode, the modem control register UMCR[RTS] is internally tied to the modem status register UMSR[CTS]. The transmitter SOUT is set to a logic 1 and the receiver SIN is disconnected. The output of the transmitter shift register is looped back into the receiver shift register input. The CTS_B (input signal) is disconnected, RTS_B is internally connected to CTS_B, and the RTS_B (output signal) becomes inactive. In this diagnostic mode, data that is transmitted is immediately received. In local loopback mode the transmit and receive data paths of the DUART can be verified. Note that in local loopback mode, the transmit/receive interrupts are fully operational and can be controlled by the interrupt enable register (UIER). P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013 510 Freescale Semiconductor, Inc. 11.4.4 Errors Chapter 11 DUART The following sections describe framing, parity, and overrun errors which may occur while data is transferred on the UART bus. Each of the error bits are usually cleared, as described below, when the line status register (ULSR) is read. 11.4.4.1 Framing error When an i