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Cypress Usb Power Delivery datasheet

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    Cypress USB Power Delivery控制器手册

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    PRELIMINARY CCG1 Datasheet USB Type-C Port Controller with Power Delivery General Description CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The scalable and reconfigurable core architecture of CCG1 enables a base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode mux support. CCG1 is also a Type-C cable ID IC for active and passive cables. The ARM® Cortex®-M0 CPU based core can use common open source firmware or custom solutions developed with common libraries and APIs. CCG1 is the CC controller that detects connector insert, plug orientation, and VCONN switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides the control signals to manage external VBUS and VCONN power management solutions as well as external mux controls for most single cable-docking solutions. CCG1's packaging options, and programmability, enables any USB Type-C and USB Power Delivery solution. Applications Type-C Support ■ Notebooks, tablets, monitors, docking stations ■ Power adapters, USB Type-C cables Features ■ Integrated transceiver (BB PHY) ■ Supports up to two USB ports with PD ■ Supports routing of all protocols through an external mux PD Support 32-bit MCU Subsystem ■ 48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB SRAM ■ Supports Provider and Consumer roles ■ Supports all power profiles Low power operation Integrated analog blocks ■ 1.8-V to 5.5-V operation ■ 12-bit, 1-Msps ADC for VBUS voltage and current monitoring ■ Sleep 1.3 mA, Deep Sleep 1.3 uA ■ Dynamic overcurrent and overvoltage protection Packages Integrated digital blocks ■ 40-pin QFN ■ Two configurable 16-bit TCPWM blocks ■ One I2C master or slave ■ 16-pin SOIC ■ 28-pin SSOP ■ 35-ball wafer-level CSP (WLCSP) Figure 1. CCG1 Block Diagram [1, 2, 3, 4, 5, 6] Advanced High-Performance Bus (AHB) Programmable Interconnect and Routing CCG1: USB Type-C Port Controller with PD MCU Subsystem Integrated Analog Blocks IDAC ADC CORTEX-M0 48 MHz Flash (32KB) SRAM (4KB) Serial Wire Debug Comparators Integrated Digital Blocks TCPWM1 SCB2 (I2C, SPI, UART) Profiles and Configurations BB3 MAC BB3 PHY I/O Subsystem CC Rp4, Rd5, Ra6 Control VBUS Control VCONN Control Voltage Select MUX Control Current Control Device Detect VBUS Sense VCONN Sense GPIO Port Notes 1. Timer, counter, pulse-width modulation block. 2. Serial communication block configurable as UART, SPI, or I2C. 3. Base band. 4. Termination resistor denoting a Downstream Facing Port (DFP). 5. Termination resistor denoting a Upstream Facing Port (UFP). 6. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA). Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-93639 Rev. *C • San Jose, CA 95134-1709 • 408-943-2600 Revised December 14, 2014 PRELIMINARY CCG1 Datasheet Contents Functional Definition ........................................................ 3 CPU and Memory Subsystem ..................................... 3 System Resources ...................................................... 3 GPIO ........................................................................... 3 Pin Definitions .................................................................. 4 Pinouts ............................................................................ 11 Power ............................................................................... 13 Electrical Specifications ................................................ 15 Absolute Maximum Ratings ...................................... 15 Device Level Specifications ....................................... 15 Digital Peripherals ..................................................... 18 Memory ..................................................................... 19 System Resources .................................................... 19 Applications in Detail ..................................................... 21 Ordering Information ...................................................... 29 Ordering Code Definitions ......................................... 29 Packaging ........................................................................ 30 Acronyms ........................................................................ 33 Document Conventions ................................................. 34 Units of Measure ....................................................... 34 Revision History ............................................................. 35 Sales, Solutions, and Legal Information ...................... 36 Worldwide Sales and Design Support ....................... 36 Products .................................................................... 36 PSoC® Solutions ...................................................... 36 Cypress Developer Community ................................. 36 Technical Support ..................................................... 36 Document Number: 001-93639 Rev. *C Page 2 of 36 PRELIMINARY CCG1 Datasheet Functional Definition CPU and Memory Subsystem CPU The Cortex-M0 CPU in the CCG1 is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and a Wakeup Interrupt Controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a 2-wire form of JTAG; the debug configuration used for CCG1 has four break-point (address) comparators and two watchpoint (data) comparators. Flash The CCG1 device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 1 wait-state (WS) access time at 48 MHz and 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. SROM A supervisory ROM that contains boot and configuration routines is provided. System Resources Power System The power system is described in detail in the section Power on page 13. It provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (Brown-Out Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). The CCG1 operates with a single external supply over the range of 1.8 to 5.5 V and has three different power modes: Active, Sleep, and Deep Sleep; transitions between modes are managed by the power system. Serial Communication Blocks (SCB) The CCG1 has one SCB, which can implement an I2C interface. The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZ-I2C that creates a mailbox address range in the memory of the CCG1 and effectively reduces I2C communication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices, as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. The CCG1 is not completely compliant with the I2C spec in the following respects: ■ GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. ■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a VOL maximum of 0.6 V. ■ Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the Bus Load. ■ When the SCB between NACK is an I2C Master, it interposes an and Repeated Start; the I2C spec IDLE state defines Bus free as following a Stop condition so other Active Masters do not intervene but a Master that has just become activated may start an Arbitration cycle. ■ When the SCB is in the I2C Slave mode, and Address Match on External Clock is enabled (EC_AM = 1) along with operation in the internally clocked mode (EC_OP = 0), then its I2C address must be even. GPIO The CCG1 has 34 GPIOs, which are configured for various functions. Refer to the pinout tables for the definitions. The GPIO block implements the following: ■ Eight drive strength modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL). ■ Individual control of input and output buffer enabling/disabling in addition to the drive strength modes. ■ Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode). ■ Selectable slew rates for dV/dt related noise control to improve EMI. During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network, known as a high-speed I/O matrix, is used to multiplex between various signals that may connect to an I/O pin. Document Number: 001-93639 Rev. *C Page 3 of 36 PRELIMINARY CCG1 Datasheet Pin Definitions Following is the pin definition #1 for 35-Ball WLCSP for the Cable/EMCA application. Refer to Table 24 for part numbers to package mapping. Table 1. Pin Definitions for 35-ball WLCSP for EMCA Cable Application Functional Pin Name 35-WLCSP#1 Balls Type Description CC1_RX C4 I CC1 control 0: TX enabled z: RX sense CC1_TX D7 O Configuration Channel 1 SWD_IO D1 I/O SWD I/O SWD_CLK I2C_SCL I2C_SDA C1 I SWD clock B1 I/O I2C clock signal B2 I/O I2C data signal XRES B6 I Reset VCCD A7 POWER Regulated digital supply output. Connect a 1 to 1.6-μF capacitor. No external source should be connected VDDD C7 POWER Power supply for both analog and digital sections VSSA B7 GND Analog ground CC_VREF C5 I Data reference signal for CC lines TX_U B3 O Signals for internal use only. The TX_U output signal should be connected to the TX_M signal TX_M B5 I TX_REF_IN D3 I Reference signal for internal use. Connect to TX_REF output via a 2.4K 1% resistor TX_GND A3 I Connect to GND via 2K 1% resistor TX_REF_OUT D4 O Reference signal generated by connecting internal current source to two 1K external resistors RA_DISCONNECT E4 O Optional control signal to remove RA after assertion of VCONN 0: RA disconnected 1: RA connected VCONN_DET C6 I Local VCONN detection signal 0: VCONN is not locally applied 1: VCONN is locally applied CC1_LPREF A5 I Reference signal for internal use. Connect to the output of resistor divider from VDDD. RA_FAR_DISCONNECT E5 O Optional control signal to remove RA after assertion of VCONN (NC for 2 chip/cable) 0: RA disconnected 1: RA connected BYPASS D5 I Bypass capacitor for internal analog circuits CC1_LPRX C3 I Configuration channel 1 RX signal for Low Power States GPIO A1, A2, A4, A6, B4, C2, D2, D6, E1, E2, E3, E6, E7 – General-purpose I/Os Document Number: 001-93639 Rev. *C Page 4 of 36 PRELIMINARY CCG1 Datasheet Following is the pin definition for 28-pin SSOP for the Power Adapter application. Refer to Table 24 for part numbers to package mapping. Table 2. Pin Definitions for 28-pin SSOP for Power Adapter Application Functional Pin Name 28-pin SSOP Pin # Type Description CC_RD 1 O Open Drain signal to connect RD to CC 1 line z: RD not connected 0: RD connected NC 2 I No Connect VBUS_P_CTRL 3 O Full rail control signal for enabling/disabling Provider load FET GPIO_1 4 I General Purpose IOs NC 5 O No Connect CC_RP 6 I Open Source signal to connect RP to CC 1 line z: RP not connected 1: RP connected GPIO_3 7 I General Purpose IOs VREF_5V 8 O Open drain reference control signal for VBUS value of 5 V 0: VBUS_VREF is a reference for VBUS = 5 V z: VBUS_VREF is NOT a reference for VBUS = 5 V CS_P 9 I Low Side Current Sense GPIO_2 10 I General Purpose IOs CC_TX 11 O Configuration Channel TX VREF_12V 12 I/O Open drain reference control signal for VBUS value of 12 V 0: VBUS_VREF is a reference for VBUS = 12 V z: VBUS_VREF is NOT a reference for VBUS = 12 V SWD_IO 13 I/O SWD IO SWD_CLK 14 I SWD Clock VREF_20V 15 I/O Open drain reference control signal for VBUS value of 20 V 0: VBUS_VREF is a reference for VBUS = 20 V z: VBUS_VREF is NOT a reference for VBUS = 20 V VSEL1 16 I/O Voltage Select signal 1 for selecting the output voltage / PWM signal for AC power adapters. Can provide 0%, 33%, 66%, or 100% duty cycle VSEL2 17 I/O Voltage Select signal 2 for selecting output voltage CC_TXEN 18 O Open Drain signal to enable TX function on the CC 1 line 0: TX enabled z: TX disabled CC_RX 19 I Configuration Channel RX CC_VREF 20 I Data reference signal for CC line (0.55 V) VBUS_VMON 21 I VBUS Over-voltage Protection monitoring signal VBUS_VREF 22 I Data reference signal for CC lines VBUS_OK 23 O VBUS_OK = 1-VBUS Voltage ok VBUS_OK = 0-VBUS Over voltage detected VBUS_DISCHARGE 24 O Signal used for discharging VBUS line during voltage change XRES 25 I Reset VCCD 26 POWER Connect 1 µF Capacitor between VCCD and Ground VDDD 27 POWER 3.3 V Supply VSSA 28 GND Ground Document Number: 001-93639 Rev. *C Page 5 of 36 PRELIMINARY CCG1 Datasheet Following is the pin definitions for 40-pin QFN and 35-ball WLCSP for the notebook, tablet, smartphone, and monitor applications. Refer to Table 24 for part numbers to package mapping. Table 3. Pin Definitions for 40-pin QFN and 35-ball WLCSP for Notebook (DRP), Tablet, Smartphone and Monitor Applications Functional Pins 40-QFN#1 Pins 40-QFN#2 Pins 35-WLCSP#2 Balls Type Description MUXSEL_1 1 1 D5 O External Data Mux Select signal 1 MUXSEL_2 2 2 D6 O External Data Mux Select signal 2 CC1_CTRL 3 3 D3 I/O CC1 control 0: TX enabled z: RX sense CC2_CTRL 4 4 E4 I/O CC2 control 0: TX enabled z: RX sense MUXSEL_3 5 5 E5 O External Data Mux Select signal 3 MUXSEL_4 6 6 E6 O External Data Mux Select signal 4 CS_P 7 7 E3 I Current Sensing Plus input CS_M 8 8 E2 I Current Sensing Minus input VSS 9 9 – GND Ground CC1 10 10 E1 I/O Configuration Channel 1 MUXSEL_5 11 11 D2 O External Data Mux Select signal 5 SWD_IO 12 12 D1 I/O SWD I/O SWD_CLK 13 13 C1 I SWD Clock HOTPLUG_DET 14 14 C2 I/O HotPlug Detection for Display Port Alternate Mode VSEL2 15 15 – O Voltage Select signal 2 for selecting output voltage C_SEL 16 16 – I Configuration Select signal IFAULT I2C_SCL I2C_SDA I2C_INT 17 17 – I Current Fault Indication 0: No fault 1: Current fault 18 18 B1 I/O I2C Clock signal 19 19 B2 I/O I2C Data signal 20 20 A2 O I2C Interrupt DEV_DET 21 21 A1 O Device detection signal indicating the attached device type CC1_RD 22 22 C3 O Open Drain signal to connect RD to CC 1 line z: RD not connected 0: RD connected CC1_RP 23 23 A5 O Open Source signal to connect RP to CC 1 line z: RP not connected 1: RP connected CC1_VCONN_CTRL 24 24 A4 O Open Drain signal to control a PFET power switch for VCONN on CC 1 line 0: VCONN switch closed z: VCONN switch open VBUS_DISCHARGE 25 25 A3 O Signal used for discharging VBUS line during voltage change CC2 26 26 B3 O Configuration Channel 2 CC2_RD 27 27 A6 O Open Drain signal to connect RD to CC 2 line z: RD not connected 0: RD connected Document Number: 001-93639 Rev. *C Page 6 of 36 PRELIMINARY CCG1 Datasheet Table 3. Pin Definitions for 40-pin QFN and 35-ball WLCSP for Notebook (DRP), Tablet, Smartphone and Monitor Applications Functional Pins 40-QFN#1 Pins 40-QFN#2 Pins 35-WLCSP#2 Balls Type Description CC2_RP 28 28 B4 O Open Source signal to connect RP to CC 2 line z: RP not connected 1: RP connected CC2_VCONN_CTRL 29 29 B5 O Open Drain signal to control a PFET power switch for VCONN on CC 2 line 0: VCONN switch closed z: VCONN switch open XRES 30 30 B6 I Reset VCCD 31 31 A7 POWER Regulated digital supply output. Connect a 1 to 1.6-μF capacitor. No external source should be connected VDDD 32 32 C7 POWER Power supply for digital sections VDDA 33 33 C7 POWER Power supply for analog sections VSSA 34 34 B7 GND Analog ground pin VBUS_VMON 35 35 C4 I VBUS overvoltage protection monitoring signal VBUS_VREF 36 36 C5 I VBUS reference signal for overvoltage protection detection VSEL1 – 37 – O Voltage Select signal 1 for selecting the output voltage CUR_LIM 37 – C6 Current Limit Indicator per the Power Delivery Contract VBUS_C_CTRL 38 – D7 O Full rail control signal for enabling/disabling Consumer load FET VBUS_OK – 38 – VBUS_OK = 1 - VBUS Voltage ok VBUS_OK = 0 - VBUS Over voltage detected CC_VREF 39 39 D4 I Data reference signal for CC lines VBUS_P_CTRL 40 40 E7 O Full rail control signal for enabling/disabling Provider load FET Document Number: 001-93639 Rev. *C Page 7 of 36 PRELIMINARY CCG1 Datasheet Following is the pin definition for 40-pin QFN for Notebook (DFP) application. Refer to Table 24 for part numbers to package mapping. Table 4. Pin Definitions for 40-pin QFN for Notebook (DFP) Functional Pin Name 40-QFN #3 Pins Type Description MUXSEL_1 1 O External Data Mux Select signal 1 MUXSEL_2 2 O External Data Mux Select signal 2 CC1_CTRL 3 I CC1 control 0: Tx enabled z: RX sense CC2_CTRL 4 I CC2 control 0: TX enabled z: RX sense MUXSEL_3 5 O External Data Mux Select signal 3 MUXSEL_4 6 O External Data Mux Select signal 4 CS_P 7 I Current Sensing Plus input CS_M 8 I Current Sensing Minus input VSS 9 GND Ground CC1 10 O Configuration Channel 1 CC1_RP_1.5 11 O Open Drain signal to connect RP to CC1 line (1.5 A current) z: RP not connected 1: RP connected SWD_IO 12 IO SWD IO SWD_CLK 13 I SWD Clock CC1_RP_3.0 14 O Open Source signal to connect RP to CC1 line (3A current) z: RP not connected 1: RP connected CC1_RP_DEF 15 O Open Drain signal to connect RP to CC1 line (Default current) z: RP not connected 1: RP connected CC2_RP_DEF 16 O Open Drain signal to connect RP to CC2 line (Default current) z: RP not connected 1: RP connected CC2_RP_1.5 17 O Open Drain signal to connect RP to CC2 line (1.5 A current) z: RP not connected 1: RP connected I2C_SCL 18 IO I2C Clock signal I2C_SDA 19 IO I2C Data signal I2C_INT 20 O I2C Interrupt CC2_RP_3.0 21 O Open Source signal to connect RP to CC2 line (3 A current) z: RP not connected 1: RP connected CC1_LPRX 22 I Configuration channel 1 RX signal for Low Power States CC1_LPREF 23 I Reference signal for internal use. CC2_LPRX 24 I Configuration channel 2 RX signal for Low Power States CC2_LPREF 25 I Reference signal for internal use. CC2 26 O Configuration Channel 2 CC1_VCONN_CTRL 27 O Open Drain signal to control a PFET power switch for VCONN on CC1 line 0: VCONN switch closed z: VCONN switch open Document Number: 001-93639 Rev. *C Page 8 of 36 PRELIMINARY CCG1 Datasheet Table 4. Pin Definitions for 40-pin QFN for Notebook (DFP) Functional Pin Name 40-QFN #3 Pins Type Description CC2_VCONN_CTRL 28 O Open Drain signal to control a PFET power switch for VCONN on CC2 line 0: VCONN switch closed z: VCONN switch open IFAULT 29 I Current Fault Indication on VBUS 0: No fault 1: Over Current fault XRES 30 I Reset VCCD 31 POWER Connect 1 µF Capacitor between VCCD and Ground VDDD 32 POWER 5 V Supply VDDA 33 POWER 5 V Supply VSSA 34 GND E-PAD E-PAD GND VBUS_VMON 35 I VBUS Over-voltage Protection monitoring signal VBUS_VREF 36 I VBUS reference signal for Over-voltage Protection detection VBUS_P_CTRL 37 O Full rail control signal for enabling/disabling Provider load FET HOTPLUG_DET 38 IO HotPlug Detection for Display Port Alternate Mode CC_VREF/VBUS_DISCHARGE 39 IO Data reference signal for CC lines / Signal used for discharging VBUS line during voltage change MUXSEL_5 40 O External Data Mux Select signal 5 Document Number: 001-93639 Rev. *C Page 9 of 36 PRELIMINARY CCG1 Datasheet Following is the pin definition for 16-pin SOIC for the Power Adapter application. Refer to Table 24 for part numbers to package mapping Table 5. Pin Definitions for 16-pin SOIC for Power Adapter Application Functional Pin Name 16-pin SOIC Pins Type Description SWD_CLK 1 I SWD Clock VBUS_P_CTRL 2 O Full rail control signal for enabling/disabling provider load FET VBUS_VMON 3 I VBUS over-voltage protection monitoring signal VBUS_VREF 4 I VBUS reference signal for over-voltage protection detection XRES 5 – Active Low Reset VCCD 6 – Connect 1 µF capacitor between VCCD and GROUND VSSD 7 – Ground VDDD 8 – Power 3.3 V/5 V VSSA 9 – Ground CC_VREF/VBUS_DISCHARG 10 E I/O Data reference signal for CC line (0.55 Volt) / Signal used for discharging VBUS line during voltage decrease CC_CTRL 11 I/O CC1 control 0: TX enabled z: RX sense CS 12 I Low Side Current Sense VSEL1 13 O Voltage select signal for selecting the output voltage 5/12/20 V VSEL2 14 O Voltage select signal for selecting the output voltage 5/12/20 V CC 15 I/O Configuration Channel TX/RX SWD_IO 16 I/O SWD I/O Document Number: 001-93639 Rev. *C Page 10 of 36 Pinouts PRELIMINARY Figure 2. 40-pin QFN Pinout CCG1 Datasheet 40 VBUS_P_CTRL 39 CC_VREF 38 VBUS_C_CTRL/VBUS_OK 37 VSEL1/CUR_LIM 36 VBUS_VREF 35 VBUS_VMON 34 VSSA 33 VDDD 32 VDDD 31 VCCD MUXSEL_1 1 MUXSEL_2 2 CC1_CTRL 3 CC2_CTRL 4 MUXSEL_3 5 MUXSEL_4 6 CS_P 7 CS_M 8 VSS 9 CC1 10 QFN (Top View) 30 XRES 29 CC2_VCONN_CTRL 28 CC2_RP 27 CC2_RD 26 CC2 25 VBUS_DISCHARGE 24 CC1_VCONN_CTRL 23 CC1_RP 22 CC1_RD 21 DEV_DET MUXSEL_5 11 SWD_IO 12 SWD_CLK 13 HOTPLUG_DET 14 VSEL2 15 C_SEL 16 IFAULT 17 I2C_SCL 18 I2C_SDA 19 I2C_INT 20 Figure 3. 16-pin SOIC Pinout SWD_CLK 1 VBUS_P_CTRL 2 VBUS_VMON 3 VBUS_VREF 4 XRES 5 VCCD 6 VSSD 7 VDDD 8 SOIC (Top View) 16 SWD_IO 15 CC 14 VSEL2 13 VSEL1 12 CS 11 CC_CTRL 10 CC_VREF/VBUS_DISCHARGE 9 VSSA Figure 4. 28-pin SSOP Pinout CC_RD 1 NC 2 VBUS_P_CTRL 3 GPIO_1 4 NC 5 CC_RP 6 GPIO_3 7 VREF_5V 8 CS_P 9 GPIO_2 10 CC_TX 11 VREF_12V 12 SWD_IO 13 SWD_CLK 14 SSOP (Top View) 28 VSSA 27 VDDD 26 VCCD 25 XRES 24 VBUS_DISCHARGE 23 VBUS_OK 22 VBUS_VREF 21 VBUS_VMON 20 CC_VREF 19 CC_RX 18 CC_TXEN 17 VSEL2 16 VSEL1 15 VREF_20V Document Number: 001-93639 Rev. *C Page 11 of 36 PRELIMINARY CCG1 Datasheet Figure 5. 35-Ball WLCSP Pinout 7 6 5 4 3 2 1 VCCD GPIO CC1_LPRE F CC1_TXE N TX_GND GPIO GPIO A VSSA XRES TX_M GPIO TX_U I2C_SDA I2C_SCL B VDDD/ VDDA VCONN_D ET CC_VREF CC1_RX CC1_LPRX GPIO SWD_CLK C CC1_TX GPIO BYPASS TX_REF_O UT TX_REF_IN GPIO SWD_IO D GPIO GPIO RA_FAR_D ISCONNEC T RA_DISCO NNECT GPIO GPIO GPIO E Document Number: 001-93639 Rev. *C Page 12 of 36 PRELIMINARY CCG1 Datasheet Power The following power system diagram shows the minimum set of power supply pins as implemented for the CCG1. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the VDDA input. There is a separate regulator for the Deep Sleep mode. There is a separate low-noise regulator for the bandgap. The supply voltage range is 1.8 to 5.5 V with all functions and circuits operating over that range. The CCG1 is powered by an external power supply that can be anywhere in the range of 1.8 to 5.5 V. This range is also designed for battery-powered operation.For example, the chip can be powered from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the CCG1 supplies the internal logic and the VCCD output of the CCG1 must be bypassed to ground via an external capacitor (in the range of 1 to 1.6 µF; X5R ceramic or better). No voltage source should be applied to this pin. VDDA and VDDD must be shorted together; the grounds, VSSA and VSS must also be shorted together. Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range in parallel with a smaller capacitor (0.1 µF, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. Examples of bypass schemes follow. Figure 6. 40-pin QFN Example 0.1 µF C4 C3 1 µF VDDA VDDD 1 µF C1 C2 0.1 µF VSS VSS VSS VBUS_P_CTRL CC_VREF VBUS_C_CTRL/VBUS_OK VSEL1/CUR_LIM VBUS_VREF VBUS_VMON 40 39 38 37 36 35 VSSA 34 VDDD 33 VDDD 32 VCCD 31 VSS MUXSEL_1 MUXSEL_2 CC1_CTRL CC2_CTRL MUXSEL_3 MUXSEL_4 CS_P CS_M CC1 1 2 3 4 5 6 7 8 9 VSS 10 QFN (Top View) 30 XRES 29 CC2_VCONN_CTRL 28 CC2_RP 27 CC2_RD 26 CC2 25 VBUS_DISCHARGE 24 CC1_VCONN_CTRL 23 CC1_RP 22 CC1_RD 21 DEV_DET C5 1 µF VSS MUXSEL_5 11 SWD_IO 12 SWD_CLK 13 HOTPLUG_DET 14 VSEL2 15 C_SEL 16 IFAULT 17 I2C_SCL 18 I2C_SDA 19 I2C_INT 20 Figure 7. 16-pin SOIC Example C3 1 µF VSS 0.1 µF C2 SWD_CLK VBUS_P_CTRL VBUS_VMON VBUS_VREF XRES VSS 1 2 3 SOIC 4 (Top View) 5 6 VCCD 7 VSSD 8 VDDD 16 SWD_IO 15 CC 14 VSEL2 13 VSEL1 12 CS 11 CC_CTRL 10 CC_VREF/VBUS_DISCHARGE 9 VSSA VSS C1 1 µF Document Number: 001-93639 Rev. *C Page 13 of 36 PRELIMINARY CCG1 Datasheet Figure 8. 28-pin SSOP Example VSS 0.1 µF C2 VDDD CC_RD 1 NC 2 VBUS_P_CTRL 3 GPIO_1 4 NC 5 CC_RP 6 GPIO_3 7 VREF_5V 8 CS_P 9 GPIO_2 10 CC_TX 11 VREF_12V 12 SWD_IO 13 SWD_CLK 14 SSOP (Top View) VSSA 28 VDDD 27 VCCD 26 25 24 23 22 21 20 19 18 17 16 15 XRES VBUS_DISCHARGE VBUS_OK VBUS_VREF VBUS_VMON CC_VREF CC_RX CC_TXEN VSEL2 VSEL1 VREF_20V VSS C1 1 µF C3 1 µF VSS Figure 9. 35-ball WLCSP Example C3 1 µF VCCD GPIO CC1_LP REF CC1_T XEN TX_GN D GPIO GPIO A VSS VSS VSSA XRES TX_M GPIO TX_U I2C_SD A I2C_SC L B 0.1 µF C2 VDDD/VDDA C1 1 µF VDDD/ VDDA VCONN _DET CC_VR EF CC1_R X CC1_LP RX GPIO SWD_C LK C VSS CC1_TX GPIO BYPAS S TX_REF _OUT TX_REF _IN GPIO SWD_I O D GPIO GPIO RA_FA R_DISC ONNEC T RA_DIS CONNE CT GPIO GPIO GPIO E Document Number: 001-93639 Rev. *C Page 14 of 36 PRELIMINARY CCG1 Datasheet Electrical Specifications Absolute Maximum Ratings Table 6. Absolute Maximum Ratings[7] Spec ID# Parameter Description Min SID1 SID2 SID3 SID4 SID5 VDDD_ABS VCCD_ABS VGPIO_ABS IGPIO_ABS IGPIO_injection Digital supply relative to VSSD Direct digital core voltage input relative to VSSD GPIO voltage Maximum current per GPIO GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS –0.5 –0.5 –0.5 –25.0 –0.50 BID44 BID45 BID46 ESD_HBM ESD_CDM LU Electrostatic discharge human body model Electrostatic discharge charged device model Pin current for latch-up 2200 500 –200 Typ Max Units Details/ Conditions – 6.0 V Absolute max – 1.95 V Absolute max – VDDD+0.5 V Absolute max – 25.0 mA Absolute max – 0.5 mA Absolute max, current injected per pin – – V – – V – 200 mA Device Level Specifications All specifications are valid for -40 °C  TA  105 °C and TJ  120 °C, except where noted. Specifications are valid for 1.8 V to 5.5 V, except where noted. Table 7. DC Specifications Spec ID# Parameter Description Details/ Min Typ Max Units Conditions SID53 VDDD Power supply input voltage 1.8 – 5.5 V With regulator enabled SID54 SID55 VCCD CEFC Output voltage (for core logic) External regulator voltage bypass – 1.8 – 1.0 1.3 1.6 V µF X5R ceramic or better SID56 CEXC Power supply decoupling capacitor – 1.0 – µF X5R ceramic or better Active Mode, VDDD = 1.8 to 5.5 V. Typical values measured at VDD = 3.3 V. SID19 IDD14 Execute from flash; CPU at 48 MHz – SID20 IDD15 Execute from flash; CPU at 48 MHz – Sleep Mode, VDDD = 1.8 to 5.5 V SID25A IDD20A I2C wakeup and comparators on – Deep Sleep Mode, VDDD = 1.8 to 3.6 V (Regulator on) SID31 IDD26 I2C wakeup on – SID32 IDD27 I2C wakeup on – Deep Sleep Mode, VDDD = 3.6 to 5.5 V SID34 IDD29 I2C wakeup – 12.8 – – 13.8 1.7 2.2 1.3 – – 50.0 15.0 – mA T = 25 °C mA mA µA T = 25 °C, 3.6 V µA T = 85 °C µA T = 25 °C, 5.5 V Note 7. Usage above the absolute maximum conditions listed in Table 6 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 001-93639 Rev. *C Page 15 of 36 PRELIMINARY CCG1 Datasheet Table 7. DC Specifications (continued) Spec ID# Parameter XRES Current SID307 IDD_XR Description Supply current while XRES asserted Details/ Min Typ Max Units Conditions – 2.0 5.0 mA Table 8. AC Specifications Spec ID# SID48 SID49 Parameter FCPU TSLEEP Description CPU frequency Wakeup from sleep mode SID50 TDEEPSLEEP Wakeup from Deep Sleep mode SID52 TRESETWIDTH External reset pulse width I/O Table 9. I/O DC Specifications Spec ID# SID57 Parameter VIH[8] Description Input voltage high threshold SID58 SID241 VIL VIH[8] Input voltage low threshold LVTTL input, VDDD < 2.7 V SID242 SID243 SID244 SID59 VIL VIH[8] VIL VOH LVTTL input, VDDD < 2.7 V LVTTL input, VDDD  2.7 V LVTTL input, VDDD  2.7 V Output voltage high level SID60 VOH Output voltage high level SID61 VOL Output voltage low level SID62 VOL Output voltage low level SID62A VOL Output voltage low level SID63 SID64 SID65 RPULLUP RPULLDOWN IIL Pull-up resistor Pull-down resistor Input leakage current (absolute value) Details/ Min Typ Max Units Conditions DC – – 0 48.0 MHz 1.8 VDD 5.5 – µs Guaranteed by characterization – – 25.0 µs 24 MHz IMO. Guaranteed by characterization 1.0 – – µs Guaranteed by characterization Min Typ Max Units Details/ Conditions 0.7 × – – VDDD – – 0.3 × VDDD 0.7× – – VDDD – – 0.3 × VDDD 2.0 – – V CMOS Input V CMOS Input V V V – – 0.8 V VDDD – – –0.6 VDDD – – –0.5 – – 0.6 – – 0.6 – – 0.4 3.5 5.6 8.5 V IOH = 4 mA at 3 V VDDD V IOH = 1 mA at 1.8 V VDDD V IOL = 4 mA at 1.8 V VDDD V IOL = 8 mA at 3 V VDDD V IOL = 3 mA at 3 V VDDD kΩ 3.5 5.6 8.5 kΩ – – 2.0 nA 25 °C, VDDD = 3.0 V Note 8. VIH must not exceed VDDD + 0.2 V. Document Number: 001-93639 Rev. *C Page 16 of 36 PRELIMINARY CCG1 Datasheet Table 9. I/O DC Specifications (continued) Spec ID# SID65A Parameter IIL_CTBM SID66 SID67 CIN VHYSTTL Description Input leakage current (absolute value) for analog pins Input capacitance Input hysteresis LVTTL SID68 VHYSCMOS Input hysteresis CMOS SID69 SID69A IDIODE ITOT_GPIO Current through protection diode to VDD/VSS Maximum Total Source or Sink Chip Current Table 10. I/O AC Specifications (Guaranteed by Characterization) Spec ID# Parameter SID70 TRISEF Rise time SID71 TFALLF Fall time Description XRES Table 11. XRES DC Specifications Spec ID# Parameter SID77 VIH Description Input voltage high threshold SID78 VIL Input voltage low threshold SID79 SID80 SID81 RPULLUP CIN VHYSXRES Pull-up resistor Input capacitance Input voltage hysteresis SID82 IDIODE Current through protection diode to VDDD/VSS Min Typ Max – – 4.0 – – 7.0 15.0 40.0 – 200.0 – – – – 100.0 – – 200.0 Min Typ Max 2.0 – 12.0 2.0 – 12.0 Min 0.7 × VDDD – 3.5 – – Typ – – 5.6 3.0 100.0 Max – 0.3 × VDDD 8.5 – – – – 100.0 Units nA Details/ Conditions pF mV VDDD  2.7 V. Guaranteed by characterization mV VDDD  4.5 V. Guaranteed by characterization µA Guaranteed by characterization mA Guaranteed by characterization Units ns ns Details/ Conditions 3.3 V VDDD, Cload = 25 pF 3.3 V VDDD, Cload = 25 pF Units V Details/ Conditions CMOS input V CMOS input kΩ pF mV Guaranteed by characterization µA Guaranteed by characterization Document Number: 001-93639 Rev. *C Page 17 of 36 PRELIMINARY CCG1 Datasheet Digital Peripherals The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode. Pulse Width Modulation (PWM) for VSEL and CUR_LIM Pins Table 12. PWM AC Specifications (Guaranteed by Characterization) Spec ID SID140 SID141 SID142 SID143 SID144 SID145 SID146 SID147 SID148 Parameter TPWMFREQ TPWMPWINT TPWMEXT TPWMKILLINT TPWMKILLEXT TPWMEINT TPWMENEXT TPWMRESWINT TPWMRESWEXT Description Operating frequency Pulse width (internal) Pulse width (external) Kill pulse width (internal) Kill pulse width (external) Enable pulse width (internal) Enable pulse width (external) Reset pulse width (internal) Reset pulse width (external) Min Typ Max – – 48.0 42.0 – – 42.0 – – 42.0 – – 42.0 – – 42.0 – – 42.0 – – 42.0 – – 42.0 – – I2C Table 13. Fixed I2C DC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min SID149 SID150 SID151 SID152 II2C1 II2C2 II2C3 II2C4 Block current consumption at 100 kHz – Block current consumption at 400 kHz – Block current consumption at 1 Mbps – I2C enabled in Deep Sleep mode – Typ Max – 10.5 – 135.0 – 310.0 – 1.4 Units MHz ns ns ns ns ns ns ns ns Details/Conditions Units µA µA µA µA Details/Conditions Table 14. Fixed I2C AC Specifications (Guaranteed by Characterization) Spec ID Parameter SID153 FI2C1 Bit rate Description Min Typ Max Units Details/Conditions – – 1.0 Mbps Document Number: 001-93639 Rev. *C Page 18 of 36 PRELIMINARY CCG1 Datasheet Memory Table 15. Flash DC Specifications Spec ID SID173 Parameter VPE Description Erase and program voltage Min Typ Max 1.8 – 5.5 Units V Details/Conditions Table 16. Flash AC Specifications Spec ID Parameter Description Min Typ SID174 TROWWRITE[9] Row (block) write time (erase – – and program) SID175 TROWERASE[9] Row erase time – – SID176 TROWPROGRAM[9] Row program time after erase – – SID178 TBULKERASE[9] Bulk erase time (32 KB) – – SID180 TDEVPROG[9] Total device program time – – SID181 SID182 FEND FRET[10] Flash endurance Flash retention. TA  55 °C, 100 K P/E cycles 100 K – 20 – SID182A Flash retention. TA  85 °C, 10 K P/E cycles 10 – SID182B Flash retention. 85 °C < TA < 3 – 105 °C, 10K P/E cycles Max Units Details/Conditions 20.0 ms Row (block) = 128 bytes 13.0 ms 7.0 ms 35 ms 7.0 seconds Guaranteed by characterization – cycles Guaranteed by characterization – years Guaranteed by characterization – years Guaranteed by characterization – years Guaranteed by characterization System Resources Power-on-Reset (POR) with Brown Out Table 17. Imprecise Power On Reset (PRES) Spec ID Parameter SID185 SID186 SID187 VRISEIPOR VFALLIPOR VIPORHYST Description Rising trip voltage Falling trip voltage Hysteresis Min Typ Max Units Details/Conditions 0.80 – 1.45 V Guaranteed by characterization 0.75 – 1.40 V Guaranteed by characterization 15.0 – 200.0 mV Guaranteed by characterization Table 18. Precise Power On Reset (POR) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID190 VFALLPPOR BOD trip voltage in active and 1.64 – – V Guaranteed by characterization sleep modes SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.40 – – V Guaranteed by characterization Note 9. It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. 10. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105 °C ambient temperature range. Contact customercare@cypress.com. Document Number: 001-93639 Rev. *C Page 19 of 36 PRELIMINARY CCG1 Datasheet SWD Interface Table 19. SWD Interface Specifications Spec ID Parameter SID213 F_SWDCLK1 Description 3.3 V  VDDD  5.5 V SID214 F_SWDCLK2 1.8 V  VDDD  3.3 V SID215 T_SWDI_SETUP T = 1/f SWDCLK SID216 T_SWDI_HOLD T = 1/f SWDCLK SID217 T_SWDO_VALID T = 1/f SWDCLK SID217A T_SWDO_HOLD T = 1/f SWDCLK Min Typ – – – – 0.25*T – 0.25*T – – – 1 – Max 14.0 7.0 – – 0.5*T – Units Details/Conditions MHz SWDCLK ≤ 1/3 CPU clock frequency MHz SWDCLK ≤ 1/3 CPU clock frequency ns Guaranteed by characterization ns Guaranteed by characterization ns Guaranteed by characterization ns Guaranteed by characterization Internal Main Oscillator Table 20. IMO DC Specifications (Guaranteed by Design) Spec ID Parameter SID218 IIMO1 Description Min IMO operating current at 48 MHz – Typ Max Units – 1000.0 µA Details/Conditions Table 21. IMO AC Specifications Spec ID Parameter SID223 SID226 SID229 FIMOTOL1 TSTARTIMO TJITRMSIMO3 Description Frequency variation IMO startup time RMS Jitter at 48 MHz Min Typ Max – – ±2.0 – – 12.0 – 139.0 – Units % µs ps Details/Conditions With API-called calibration Internal Low-Speed Oscillator Table 22. ILO DC Specifications (Guaranteed by Design) Spec ID Parameter Description Min Typ Max SID231 IILO1 SID233 IILOLEAK ILO operating current at 32 kHz – ILO leakage current – 0.30 1.05 2.0 15.0 Units µA nA Details/Conditions Guaranteed by characterization Guaranteed by design Table 23. ILO AC Specifications Spec ID Parameter SID234 SID236 SID237 TSTARTILO1 TILODUTY FILOTRIM1 Description ILO startup time ILO duty cycle 32-kHz trimmed frequency Min Typ Max – – 2.0 40.0 50.0 60.0 15.0 32.0 50.0 Units ms % kHz Details/Conditions Guaranteed by characterization Guaranteed by characterization ±60% with trim. Document Number: 001-93639 Rev. *C Page 20 of 36 PRELIMINARY CCG1 Datasheet Applications in Detail Figure 10. Single Chip/Cable, Component Count =19, Power from VCONN = 1.3 mA 7\SH&3OXJ 7\SH&3OXJ 9%86 9&211 N:  ' * 6. 6 N:  5D && %$79 $ & %$79 & $ 9&211 N:N: X) N:  ' * 6. 6 N:  5DB)DU $ & &&B/35() 9''' $$$$%&' *3,2 '((((( & 9&211B'(7 ( 5$B',6&211(&7 ( 5$B)$5B',6&211(&7 ' 7;B5()B287 &&B95() & N: QI % ;5(6 S) ' %<3$66 X) $ 9&&' CYPD1103-35FNXI 7;B*1' $ N: 35CSP 7;B5()B,1 ' 7;B0 % 7;B8 % &&B7; ' N: : N: % 966$ ,&B ,&B 6:'B 6:'B 6&/ 6'$ ,2 &/. % % ' & &&B5; & &&B/35; & 6 * 17161= ' && 6XSHU6SHHGDQG+LJK6SHHG/LQHV *1' Document Number: 001-93639 Rev. *C Page 21 of 36 PRELIMINARY CCG1 Datasheet Figure 11. Single Chip/Cable, Component Count = 13, Power from VCONN = 6.3 mA 7\SH&3OXJ 7\SH&3OXJ 9%86 9&211 N: 5D && %$79 $ & %$79 & $ 9&211 X) N: 5DB)DU $ & &&B/35() 9''' $$$$%&' *3,2 '((((( & 9&211B'(7 ( 5$B',6&211(&7 ' 7;B5()B287 ( 5$B)$5B',6&211(&7 &&B95() & % ;5(6 S) ' %<3$66 X) $ 9&&' CYPD1103-35FNXI 7;B*1' $ N: 35CSP 7;B5()B,1 ' 7;B0 % 7;B8 % &&B7; ' N: QI N: : N: % 966$ ,&B ,&B 6:'B 6:'B 6&/ 6'$ ,2 &/. % % ' & &&B5; & &&B/35; & 6 * 17161= ' && 6XSHU6SHHGDQG+LJK6SHHG/LQHV *1' Document Number: 001-93639 Rev. *C Page 22 of 36 PRELIMINARY CCG1 Datasheet 7\SH&3OXJ 9%86 Figure 12. Two Chip/Cable, Component Count = 15/paddle, Power from VCONN = 1.3 mA 7\SH&3OXJ 9%86 9&211 N:  ' * 6. 6 N:  5D && N:N: X) $ & &&B/35() 9''' $$$$%&' *3,2 '((((( & 9&211B'(7 ' ( 5$B',6&211(&7 7;B5()B287 ( 5$B)$5B',6&211(&7 &&B95() & % ;5(6 CYPD1103-35FNXI 7;B*1' $ N: 35CSP 7;B5()B,1 ' S)' %<3$66 X) $ 9&&' 7;B0 % 7;B8 % &&B7; ' N: QI N: : % 966$ ,&B ,&B 6:'B 6:'B 6&/ 6'$ ,2 &/. % % ' & & &&B5; &&B/35; & N: 6 * 17161= ' 6XSHU6SHHGDQG+LJK6SHHG/LQHV *1' 9&211 N:N: X) N:  ' * 6. 6 N:  5D $ & &&B/35() 9''' $$$$%&' *3,2 '((((( & 9&211B'(7 ( 5$B',6&211(&7 ' 7;B5()B287 ( 5$B)$5B',6&211(&7 &&B95() & % ;5(6 CYPD1103-35FNXI 7;B*1' $ N: 35CSP 7;B5()B,1 ' N: QI N: S)' %<3$66 X) $ 9&&' 7;B0 % 7;B8 % &&B7; ' : % 966$ ,&B ,&B 6:'B 6:'B 6&/ 6'$ ,2 &/. % % ' & &&B5; & &&B/35; & N: 6 * 17161= ' && 6XSHU6SHHGDQG+LJK6SHHG/LQHV *1' 7\SH&3OXJ 9%86 Figure 13. Two Chip/Cable, Component Count = 11/paddle, Power from VCONN = 6.3 mA 7\SH&3OXJ 9%86 9&211 N:  5D && X) $ & &&B/35() 9''' $$$$%&' *3,2 '((((( & 9&211B'(7 ' ( 5$B',6&211(&7 7;B5()B287 ( 5$B)$5B',6&211(&7 &&B95() & % ;5(6 CYPD1103-35FNXI 7;B*1' $ N: 35CSP 7;B5()B,1 ' S)' %<3$66 X) $ 9&&' 7;B0 % 7;B8 % &&B7; ' N: QI N: : % 966$ ,&B ,&B 6:'B 6:'B 6&/ 6'$ ,2 &/. % % ' & &&B7;(1 $ & &&B5; &&B/35; & N: 6 * 17161= ' 6XSHU6SHHGDQG+LJK6SHHG/LQHV *1' 9&211 N:  5D X) $ & &&B/35() 9''' $$$$%&' *3,2 '((((( & 9&211B'(7 ( 5$B',6&211(&7 ' 7;B5()B287 ( 5$B)$5B',6&211(&7 &&B95() & % ;5(6 S)' %<3$66 X) $ 9&&' CYPD1103-35FNXI 7;B*1' $ N: 35CSP 7;B5()B,1 ' 7;B0 % 7;B8 % &&B7; ' N: QI N: : % 966$ ,&B ,&B 6:'B 6:'B 6&/ 6'$ ,2 &/. % % ' & $ &&B7;(1 &&B5; & &&B/35; & N: 6 * 17161= ' && 6XSHU6SHHGDQG+LJK6SHHG/LQHV *1' Document Number: 001-93639 Rev. *C Page 23 of 36 PRELIMINARY CCG1 Datasheet Sense Resistor on the return path of Secondary Rsense 0.01, 1%, 1W Figure 14. 28-pin SSOP Power Adapter Application Diagram 5-20 Volts From Secondary Side PFET D S S D G 50k G 5% 100k 1% 0.1uF 1uF 3.3v MGSF1N03L D G S 100k 5% 26 27 3 1uF 10k 1% 0.1uF 3.3v 21.5k 1% 38.2k 1% 14.3k 1% 4.7k 1% 21 22 8 12 15 VBUS 100, 1%, 1W D G S NFET MGSF1N03L VCCD VDDD VBUS_P_CTRL VBUS_VMON VBUS_VREF VREF_5V VREF_12V VREF_20V 9 CS_P VBUS VSEL1 VSEL2 VSEL1 PWM 10 GPIO_2 5V 0 0 0% 12V 0 1 33% 19.6V 1 0 67% 0V 1 1 100% 7 GPIO_3 2 NC 5 NC 4 GPIO_1 VBUS_DISCHARGE 24 CC_RP 6 CYPD1134-28PVXI Rp 4.7k 5% CC 330pF 17 VSEL2 28SSOP CC_RD 1 To Primary Side 16 VSEL1 3.3v 21.5k 1% VBUS_OK = 1 – VBUS overvoltage detected VBUS_OK = 0 – VBUS voltage ok 23 VBUS_OK CC_VREF 20 0.55 Volts 4.3k 5% 13 14 SWD_IO SWD_CLK 25 XRES VSS 28 CC_RX 19 CC_TX 11 CC_TXEN 18 265 1% 150 1% 1.5nF Document Number: 001-93639 Rev. *C Page 24 of 36 PRELIMINARY CCG1 Datasheet Sense Resistor on the return path of Secondary Rsense 0.01:, 1%, 1W Figure 15. 16-pin SOIC Power Adapter Application Diagram 5-20 Volts From Secondary Side VBUS_DISCHARGE 100:   W PFET DMG7401SFG-7 100k:, 5% S D G 3.3v NFET MGSF1N03L 0.1uF 1uF D G MGSF1N03LT1G S 100k: 5% 10k:, 1% NFET MGSF1N03L 57k: 1% 100k: 1% 10uF 10k: 1% 0.1uF VBUS VBUS 5V 12V 19.6V 0V VSEL1 0 VSEL2 0 VSEL1 PWM 0% 0 1 33% 1 0 67% 1 1 100% VCCD VDDD VBUS_P_CTRL VBUS_VMON VBUS_VREF 68 2 1uF 3 4 VBUS_DISCHARGE 3.3v To Primary Side 0.1uF 12 CS 13 VSEL1 14 VSEL2 16 SWD_IO 1 SWD_CLK 5 XRES VBUS_DISCHARGE/ 10 CC_VREF 0.55 Volts CYPD1132-16SXI 16SOIC 21.5k: 1% 4.3k: 1% VSSD VSSA 7 9 CC 15 CC_CTRL 11 265: 1% 150: 1% 1.5nF 3.3v Rp 4.7k: 5% 330pF CC Document Number: 001-93639 Rev. *C Page 25 of 36 PRELIMINARY CCG1 Datasheet Embedded Controller USB Chipset DisplayPort Chipset Figure 16. Notebook (DRP) Application Diagram To System PFET D S S D G 50k: G 5% From System 5V PFET D S S D G 50k: G 5% NFET D G S D G S 100k: 1% 10k: 1% 3.9k: 1% 5 Volts CS_P 0.2: 1% CS_M VBUS 0.02: 1% Current Monitor + Comparator iFAULT 100: 1% 1W D G NFET VBUS_DISCHARGE S VDDD = 5V 0.1uF 1uF 10k: 1% S G PFET D 1uF 31 33 32 40 38 35 36 24 VCCD VDDA VDDD VBUS_P_CTRL VBUS_C_CTRL/VBUS_OK VBUS_VMON VBUS_VREF CC1_VCONN_CTRL CS_P CS_M iFAULT VBUS_DISCHARGE HPD 7 CS_P 8 CS_M 15 VSEL2 16 C_SEL 17 iFAULT 25 VBUS_DISCHARGE 23 Rp CC1_RP 22 CC1_RD 10k: 5% 390: 1% CC1 10 120: 1% 1.7nF 1 MUXSEL_1 2 MUXSEL_2 3 CC1_CTRL 10k: 1% 5 MUXSEL_3 6 MUXSEL_4 11 MUXSEL_5 CYPD1122-40LQXI 40QFN S G 14 HOTPLUG_DET 29 D CC2_VCONN_CTRL 37 CUR_LIM/ 390: 1% VSEL1 CC2 26 21 DEV_DET 12 SWD_IO 13 SWD_CLK 120: 1% 1.7nF CC2_CTRL 4 18 I2C_SCL 19 I2C_SDA 20 I2C_INT CC2_RP 28 Rp 10k: 5% VSS VSSA CC_VREF HS SS HPD DP0/1/2/3 AUX+/- 30 XRES 0.1uF 9 34 27 CC2_RD 39 5 Volts 0.55 Volts 21.5k: 1% 2.65k: 1% NFET SD G VDDD 330pF NFET SD G VDDD 1M:, 5% Rd 5.1k: 10% D G NFET S CC1 PFET NFET SD G VDDD 330pF 1M:, 5% CC2 Rd D G 5.1k: 10% NFET S Type C Receptacle NFET SD G VDDD SS/DP0/1 DP2/3 AUX+/- HS MUXSEL_x HS/SS/DP Mux HS/SS/ DP/SBU Lines Document Number: 001-93639 Rev. *C Page 26 of 36 PRELIMINARY CCG1 Datasheet Embedded Controller USB Chipset DisplayPort Chipset Figure 17. Notebook (DFP) Application Diagram From System 5V PFET D S S D G 50k: G 5% NFET D G S 100k: 1% 10k: 1% 3.9k: 1% 5 Volts CS_P 0.2: 1% CS_M VBUS 0.02: 1% Current Monitor + Comparator iFAULT 100: 1% 1W D G NFET VBUS_DISCHARGE S HS SS HPD DP0/1/2/3 AUX+/- VDDD = 5V 0.1uF 1uF 10k: 1% S G PFET D 1uF CS_P CS_M iFAULT HPD 0.1uF VCCD VDDA VDDD VBUS_P_CTRL VBUS_VMON VBUS_VREF CC1_VCONN_CTRL 31 33 32 7 CS_P 8 CS_M 29 iFAULT 1 MUXSEL_1 2 MUXSEL_2 5 MUXSEL_3 6 MUXSEL_4 40 MUXSEL_5 37 35 36 27 CC1_RP_DEF 15 56k: 5% CC1_RP_1.5 11 22k: 5% CC1_RP_3.0 14 10k: 5% 22 CC1_LPRX 390: 1% CC1 10 120: 1% CC1_CTRL 3 CC2_VCONN_CTRL 28 CYPD1134-40LQXI 40QFN 24 CC2_LPRX 1.6nF 10k: 1% S G PFET D 38 HOTPLUG_DET 390: 1% CC2 26 12 SWD_IO 13 SWD_CLK 18 I2C_SCL 19 I2C_SDA 20 I2C_INT 30 XRES 120: 1% 1.6nF CC2_CTRL 4 16 CC2_RP_DEF CC2_RP_1.5 17 CC2_RP_3.0 21 56k: 5% 22k: 5% 10k: 5% CC1_LPREF CC2_LPREF VSS VSSA CC_VREF/ VBUS_DISCHARGE 23 25 9 34 39 5 Volts NFET SD G VDDD NFET SD G VDDD 390pF 390pF VBUS_DISCHARGE 0.55 Volts 21.5k: 1% 2.65k: 1% SS/DP0/1 DP2/3 AUX+/- CC1 CC2 Type C Receptacle HS MUXSEL_x HS/SS/DP Mux HS/SS/ DP/SBU Lines Document Number: 001-93639 Rev. *C Page 27 of 36 PRELIMINARY CCG1 Datasheet Figure 18. Monitor Application Block Diagram DC Input DC/DC 5/12/20V D G PFET S 50k: 5% S D G 100k: 1% 10k: 1% 5 Volts VBUS 5V 12V 19.6V 0V VSEL1 0 VSEL2 0 VSEL1 PWM 0% 0 1 33% 1 0 67% 1 1 100% Embedded Controller USB Chipset DisplayPort Chipset HS SS HPD DP0/1/2/3 AUX+/- REG D G NFET S 3.9k: 1% CS_P 0.2: 1% CS_M VDDD = 5V 10k: 1% 0.1uF 1uF VBUS_ DISCHARGE 1uF 31 33 32 40 25 35 36 24 S G PFET D VCCD VDDA VDDD VBUS_P_CTRL VBUS_DISCHARGE VBUS_VMON VBUS_VREF CC1_VCONN_CTRL CS_P CS_M HPD 0.1uF 7 CS_P 8 CS_M 37 VSEL1/CUR_LIM 15 VSEL2 16 17 C_SEL iFAULT 38 VBUS_C_CTRL/VBUS_OK 23 CC1_RP Rp 10k: 5% 22 CC1_RD Rd 5.1k: 10% 390: 1% CC1 10 120: 1% 1.7nF 1 MUXSEL_1 3 CC1_CTRL 2 MUXSEL_2 10k:  5 MUXSEL_3 6 MUXSEL_4 CYPD1122-40LQXI S 11 MUXSEL_5 14 HOTPLUG_DET 40QFN 29 CC2_VCONN_CTRL 390: 1% G D CC2 26 21 DEV_DET 12 SWD_IO 13 SWD_CLK 120: 1% 1.7nF CC2_CTRL 4 18 I2C_SCL 19I2C_SDA 20 I2C_INT 28 CC2_RP Rp 10k: 5% 30 XRES 27 CC2_RD Rd 5.1k: 10% VSS VSSA CC_VREF 9 34 39 5 Volts PFET 0.55 Volts 21.50k: 1% 2.65k: 1% VBUS 100: 1%, 1W D G NFET VBUS_DISCHARGE S NFET SD G 330pF VDDD NFET SD G 330pF VDDD CC1 CC2 Type C Receptacle SS/DP0/1 DP2/3 AUX+/- HS MUXSEL_x HS/SS/DP Mux HS/SS/ DP/SBU Lines Document Number: 001-93639 Rev. *C Page 28 of 36 PRELIMINARY CCG1 Datasheet Ordering Information The CCG1 part numbers and features are listed in the following table. Table 24. CCG1 Ordering Information Part Number[11] CYPD1103-35FNXI CYPD1131-35FNXI CYPD1122-40LQXI CYPD1134-28PVXI CYPD1134-40LQXI CYPD1132-16SXI Application PToyrptse[-1C2] Overcurrent Protection Cable, EMCA 1 No Notebook, 1 Yes Tablet, Smartphone Notebook, 1 Yes Monitor Power Adapter 1 Yes Notebook, 1 Yes Desktop Power Adapter 1 Yes Overvoltage Protection No Yes Yes Yes Yes Yes TReersmisintoarti[1o3n] Ra[15] Rd[17] Rp[19] Rd[17] Rp[19] Rp[19] Role[14] Cable DRP[20] DRP[20] DFP[23] DFP[23] DFP[23] Ordering Code Definitions Package 35-WLCSP[16] 35-WLCSP[18] 40-QFN[21] 28-SSOP 40-QFN[22] 16-SOIC Si ID 0490 0491 048A 0481 048B 0498 CY PD X X X X - XX XX X X Temperature Range: I = Industrial Lead: X = Lead-free Package Type: LQ = QFN, FN = CSP, PV = SSOP Number of pins in the package Device Role: Unique combination of role and termination Feature: Unique combination of OCP, OVP Number of Type-C Ports: 1 = 1 Port, 2 = 2 Port Product Type: 1 = First-generation product family, CCG1 Marketing Code: PD = Power delivery product family Company ID: CY = Cypress Notes 11. All part numbers support: Industrial temperature (-40ºC to +105ºC) and input voltage range from 1.8 to 5.5 V. 12. Number of USB Type-C Ports Supported . 13. 14. PDDefaRuoltleV. CONN Termination. 15. Type-C Cable Termination. 16. 35-WLCSP#1 pinout. 17. USB Device Termination. 18. 35-WLCSP#2 pinout. 19. USB Host Termination. 20. Dual Role Port. 21. 40-QFN#1, 2 pinout. 22. 40-QFN#3 pinout. 23. Downstream Facing Port. Document Number: 001-93639 Rev. *C Page 29 of 36 PRELIMINARY CCG1 Datasheet Packaging Table 25. Package Characteristics Parameter TA TJ TJA TJA TJA TJA TJC TJC TJC TJC Description Operating ambient temperature Operating junction temperature Package JA (16-pin SOIC) Package JA (28-pin SSOP) Package JA (40-pin QFN) Package JA (35-ball WLCSP) Package JC (16-pin SOIC) Package JC (28-pin SSOP) Package JC (40-pin QFN) Package JC (35-ball WLCSP) Table 26. Solder Reflow Peak Temperature Package 16-pin SOIC 28-pin SSOP 40-pin QFN 35-ball WLCSP Maximum Peak Temperature 260 °C 260 °C 260 °C 260 °C Conditions Min Typ –40 25.00 –40 – – 85.00 – 66.58 – 15.34 – 28.00 – 49.00 – 26.28 – 2.50 – 0.40 Maximum Time at Peak Temperature 30 seconds 30 seconds 30 seconds 30 seconds Max Units 100 °C 120 °C – °C/Watt – °C/Watt – °C/Watt – °C/Watt – °C/Watt – °C/Watt – °C/Watt – °C/Watt Table 27. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package 16-pin SOIC 28-pin SSOP 40-pin QFN 35-ball WLCSP MSL MSL 3 MSL 3 MSL 3 MSL 1 Document Number: 001-93639 Rev. *C Page 30 of 36 PRELIMINARY CCG1 Datasheet Figure 19. 28-pin (210-mil) SSOP Package Outline, 51-85079 51-85079 *F Figure 20. 40-pin QFN Package Outline, 001-80659 001-80659 ** The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floating and not connected to any other signal. Document Number: 001-93639 Rev. *C Page 31 of 36 PRELIMINARY CCG1 Datasheet TOP VIEW 123 456 7 A B C D E Figure 21. 35-Ball WLCSP Package Outline, 001-93741 SIDE VIEW BOTTOM VIEW 7 6 54 3 2 1 A B C D E NOTES: 1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18 2. ALL DIMENSIONS ARE IN MILLIMETERS Figure 22. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068 001-93741 ** Document Number: 001-93639 Rev. *C 51-85068 *E Page 32 of 36 PRELIMINARY CCG1 Datasheet Acronyms Table 28. Acronyms Used in this Document Acronym ADC API ARM® CC CPU CRC CS DIO EEPROM EMI ESD FPB FS GPIO IC IDE I2C, or IIC ILO IMO I/O LVD LVTTL MCU NC NMI NVIC Description analog-to-digital converter application programming interface advanced RISC machine, a CPU architecture Configuration Channel central processing unit cyclic redundancy check, an error-checking protocol Current Sense digital input/output, GPIO with only digital capabilities, no analog. See GPIO. electrically erasable programmable read-only memory electromagnetic interference electrostatic discharge flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin integrated circuit integrated development environment Inter-Integrated Circuit, a communications protocol internal low-speed oscillator, see also IMO internal main oscillator, see also ILO input/output, see also GPIO, DIO, SIO, USBIO low-voltage detect low-voltage transistor-transistor logic microcontroller unit no connect nonmaskable interrupt nested vectored interrupt controller Table 28. Acronyms Used in this Document (continued) Acronym opamp OCP OVP PCB PGA PHY POR PRES PSoC® PWM RAM RISC RMS RTC RX SAR SCL SDA S/H SPI SRAM SWD TX UART USB USBIO XRES Description operational amplifier Overcurrent protection Overvoltage protection printed circuit board programmable gain amplifier physical layer power-on reset precise power-on reset Programmable System-on-Chip™ pulse-width modulator random-access memory reduced-instruction-set computing root-mean-square real-time clock receive successive approximation register I2C serial clock I2C serial data sample and hold Serial Peripheral Interface, a communications protocol static random access memory serial wire debug, a test protocol transmit Universal Asynchronous Transmitter Receiver, a communications protocol Universal Serial Bus USB input/output, PSoC pins used to connect to a USB port external reset I/O pin Document Number: 001-93639 Rev. *C Page 33 of 36 PRELIMINARY Document Conventions Units of Measure Table 29. Units of Measure Symbol Unit of Measure °C degrees Celsius Hz hertz KB 1024 bytes kHz kilohertz k Mbps MHz kilo ohm megabits per second megahertz M Msps µA mega-ohm megasamples per second microampere µF microfarad µs microsecond µV microvolt µW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond  ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second V volt CCG1 Datasheet Document Number: 001-93639 Rev. *C Page 34 of 36 PRELIMINARY CCG1 Datasheet Revision History Description Title: CCG1 Datasheet USB Type-C Port Controller with Power Delivery Document Number: 001-93639 Revision ECN Orig. of Submission Change Date Description of Change ** 4520316 MSMI 09/30/2014 New data sheet *A 4531795 SJH 10/13/2014 Updated Functional Definition Updated Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 16 Added Figure 18 Updated Pinouts Updated Power: Updated Figure 6, Figure 8 Updated Ordering Information Added Note 21 and referred the same note in 40-pin QFN corresponding to CYPD1122-40LQXI Added Note 22 and referred the same note in 40-pin QFN corresponding to CYPD1134-40LQXI *B 4569912 SJH 11/21/2014 Updated Features Added 16-pin SOIC related information Updated Functional Definition Updated Pin Definitions Added Table 4 Updated Pinouts Updated Figure 2, Figure 4 Added Figure 3 Updated Power Updated Figure 6, Figure 8 Added Figure 7 Updated Electrical Specifications Updated Device Level Specifications Updated Memory Added Note 10 and referred the same note in FRET parameter Added details corresponding to spec ID SID182B under FRET parameter Updated Figure 14, Figure 16, Figure 18. Added Figure 15 and Figure 17 Updated Ordering Information Updated part numbers. Added a column “Si ID” Updated Packaging Updated Table 25 Updated details in maximum value column corresponding to TA and TJ parameters Added 16-pin SOIC related information Updated Table 26 *C 4596141 SJH 12/14/2014 Updated Figure 7, Figure 14, Figure 19 Updated Table 9, Table 24 Document Number: 001-93639 Rev. *C Page 35 of 36 PRELIMINARY CCG1 Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Automotive Clocks & Buffers Interface Power Control Memory PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless © Cypress Semiconductor Corporation, 2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-93639 Rev. *C Revised December 14, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 36 of 36

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