**标 签：**MixedSignalCircuitDesign2ed

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Complemented with practical examples and discussions, CMOS Mixed-Signal Circuit Design, Second Edition is an ideal textbook for graduate students in mixed-signal circuit design courses. It is also an equally valuable reference for professionals who want to improve their skills in this area. R. JACOB (JAKE) BAKER, PHD, is an engineer, educator, and inventor. He has more than twenty years of engineering experience and holds over 200 granted or pending patents in integrated circuit design. Jake is the author of several circuit design books. For a detailed biography, please visit: http://CMOSedu.com/jbakerljbaker.htm. • IEEE IEEE PRESS Subscribe to our free Electrical Engineering eNewsletter at wiley.com /enewsletters I I Visit www.wiley.com/ieee ~WILEY wiley.com ISBN 978-0-470-29026-2 90000 9780470 290262 CMOS Mixed-Signal Circuit Design Second Edition R. Jacob Baker IEEE Press Series on Microelectronic Systems Stuart K. Tewksbury and Joe E. Brewer, Series Editors +IEEE IEEE PRESS ~ I WILEY A JOHN WILEY & SONS, INC., PUBLICATION I Brief Contents Chapter 1 Signals, Filters, and Tools 1 Chapter 2 Sampling and Aliasing 27 Chapter 3 Analog Filters 73 Chapter 4 Digital Filters 119 Chapter 5 Data Converter SNR 163 Chapter 6 Data Converter Design Basics 203 Chapter 7 Noise-Shaping Data Converters 233 Chapter 8 Bandpass Data Converters 285 Chapter 9 A High-Speed Data Converter 301 vi Contents Preface xv Chapter 1 Signals, Filters, and Tools 1 1.1 Sinusoidal Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 The Pendulum Analogy 1 Describing Amplitude in the x-y Plane 3 In-Phase and Quadrature Signals 4 1.1.2 The Complex (z-) Plane 6 1.2 Comb Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.1 The Digital Comb Filter 11 1.2.2 The Digital Differentiator 14 1.2.3 An Intuitive Discussion of the z-Plane 15 1.2.4 Comb Filters with Multiple Delay Elements 17 1.2.5 The Digital Integrator 19 The Delaying Integrator 20 An Important Note 21 1.3 Representing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.1 Exponential Fourier Series 22 1.3.2 Fourier Transform 23 Dirac Delta Function (Unit Impulse Response) 23 vii viii Contents Chapter 2 Sampling and Aliasing 27 2.1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.1.1 Impulse Sampling 28 A Note Concerning the AAF and the RCF 30 Time Domain Description of Reconstruction 31 An Important Note 33 2.1.2 Decimation 33 2.1.3 The Sample-and-Hold (S/H) 35 S/H Spectral Response 35 The Reconstruction Filter (RCF) 39 Circuit Concerns for Implementing the S/H 39 An Example 40 2.1.4 The Track-and-Hold (T/H) 41 2.1.5 Interpolation 43 Zero Padding 44 Hold Register 46 Linear Interpolation 49 2.1.6 K-Path Sampling 50 Switched-Capacitor Circuits 51 Non-Overlapping Clock Generation 53 2.2 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.2.1 Implementing the S/H 54 Finite Op-Amp Gain-Bandwidth Product 55 Autozeroing 57 Correlated Double Sampling (CDS) 59 Selecting Capacitor Sizes 61 2.2.2 The S/H with Gain 61 Implementing Subtraction in the S/H 63 A Single-Ended to Differential Output S/H 65 2.2.3 The Discrete Analog Integrator (DAI) 66 A Note Concerning Block Diagrams 68 Fully-Differential DAI 69 DAI Noise Performance 70 Chapter 3 Analog Filters 73 3.1 Integrator Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.1.1 Lowpass Filters 73 3.1.2 Active-RC Integrators 75 Contents ix Effects of Finite Op-Amp Gain Bandwidth Product, fun 78 Active-RC SNR 82 3.1.3 MOSFET-C Integrators 83 Why Use an Active Circuit (an Op-Amp)? 85 3.1.4 gm-C (Transconductor-C) Integrators 86 Common-Mode Feedback Considerations 88 A High-Frequency Transconductor 89 3.1.5 Discrete-Time Integrators 90 An Important Note 94 Exact Frequency Response of an Ideal Discrete-Time 94 Filter 3.2 Filtering Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.2.1 The Bilinear Transfer Function 95 Active-RC Implementation 97 Transconductor-C Implementation 97 Switched-Capacitor Implementation 98 3.2.2 The Biquadratic Transfer Function 99 Active-RC Implementation 101 Switched-Capacitor Implementation 106 High Q 107 Q Peaking and Instability 112 Transconductor-C Implementation 114 Chapter 4 Digital Filters 119 4.1 SPICE Models for DACs and ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.1.1 The Ideal DAC 119 SPICE Modeling the Ideal DAC 120 4.1.2 The Ideal ADC 121 4.1.3 Number Representation 123 Increasing Word Size (Extending the Sign-Bit) 124 Adding Numbers and Overflow 125 Subtracting Numbers in Two's Complement Format 126 4.2 Sinc-Shaped Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.2.1 The Counter 126 Aliasing 127 The Accumulate-and-Dump 129 4.2.2 Lowpass Sinc Filters 129 Averaging without Decimation: A Review 132 x Contents Cascading Sinc Filters 132 Finite and Infinite Impulse Response Filters 133 4.2.3 Bandpass and Highpass Sinc Filters 134 Canceling Zeroes to Create Highpass and Bandpass 134 Filters Frequency Sampling Filters 138 4.2.4 Interpolation using Sinc Filters 139 Additional Control 142 Cascade of Integrators and Combs 142 4.2.5 Decimation using Sinc Filters 143 4.3 Filtering Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.3.1 FIR Filters 145 4.3.2 Stability and Overflow 146 Overflow 147 4.3.3 The Bilinear Transfer Function 148 The Canonic Form (or Standard Form) of a Digital 151 Filter General Canonic Form of a Recursive Filter 154 4.3.4 The Biquadratic Transfer Function 155 Comparing Biquads to Sinc-Shaped Filters 157 A Comment Concerning Multiplications 158 Chapter 5 Data Converter SNR 163 5.1 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.1.1 Viewing the Quantization Noise Spectrum Using 164 Simulations Bennett's Criteria 165 An Important Note 166 RMS Quantization Noise Voltage 166 Treating Quantization Noise as a Random Variable 168 5.1.2 Quantization Noise Voltage Spectral Density 169 Calculating Quantization Noise from a SPICE 171 Spectrum Power Spectral Density 172 5.2 Signal-to-Noise Ratio (SNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Effective Number of Bits 173 Coherent Sampling 175 Signal-to-Noise Plus Distortion Ratio 176 Spurious Free Dynamic Range 177 Contents xi Dynamic Range 177 Specifying SNR and SNDR 178 5.2.1 Clock Jitter 178 Using Oversampling to Reduce Sampling Clock Jitter 181 Stability Requirements A Practical Note 182 5.2.2 A Tool: The Spectral Density 182 The Spectral Density of Deterministic Signals: An 183 Overview The Spectral Density of Random Signals: An Overview 185 Specifying Phase Noise from Measured Data 189 5.3 Improving SNR using Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 An Important Note 191 5.3.1 Using Averaging to Improve SNR 192 Ideal Signal-to-Noise Ratio 194 5.3.2 Linearity Requirements 194 5.3.3 Adding a Noise Dither 195 5.3.4 Jitter 198 5.3.5 Anti-Aliasing Filter 198 5.4 Using Feedback to Improve SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Chapter 6 Data Converter Design Basics 203 The One-Bit ADC and DAC 204 6.1 Passive Noise-Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.1.1 Signal-to-Noise Ratio 208 6.1.2 Decimating and Filtering the Modulator's Output 209 SNR Calculation using a Sinc Filter 211 6.1.3 Offset, Matching, and Linearity 212 Resistor Mismatch 213 The Feedback DAC 213 DAC Offset 214 Linearity of the First-Order Modulator 214 Dead Zones 215 6.2 Improving SNR and Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.2.1 Second-Order Passive Noise-Shaping 216 6.2.2 Passive Noise-Shaping Using Switched-Capacitors 218 6.2.3 Increasing SNR using K-Paths 220 Revisiting Switched-Capacitor Implementations 224 xii Contents Effects of the Added Amplifier on Linearity 224 6.2.4 Improving Linearity Using an Active Circuit 225 Second-Order Noise-Shaping 227 Signal-to-Noise Ratio 229 Discussion 230 Chapter 7 Noise-Shaping Data Converters 233 7.1 First-Order Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 A Digital First-Order NS Demodulator 235 7.1.1 Modulation Noise in First-Order NS Modulators 236 7.1.2 RMS Quantization Noise in a First-Order Modulator 237 7.1.3 Decimating and Filtering the Output of a NS 239 Modulator 7.1.4 Pattern Noise from DC Inputs (Limit Cycle 241 Oscillations) 7.1.5 Integrator and Forward Modulator Gain 243 7.1.6 Comparator Gain, Offset, Noise, and Hysteresis 246 7.1.7 Op-Amp Gain (Integrator Leakage) 247 7.1.8 Op-Amp Settling Time 248 7.1.9 Op-Amp Offset 250 7.1.10 Op-Amp Input-Referred Noise 250 7.1.11 Practical Implementation of the First-Order NS 251 Modulator 7.2 Second-Order Noise-Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 7.2.1 Second-Order Modulator Topology 253 7.2.2 Integrator Gain 257 Implementing Feedback Gains in the DAI 260 Using Two Delaying Integrators to Implement the 263 Second-Order Modulator 7.2.3 Selecting Modulator (Integrator) Gains 264 7.3 Noise-Shaping Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 7.3.1 Higher-Order Modulators 265 M th-Order Modulator Topology 265 7.3.2 Filtering the Output of an M th-Order NS Modulator 266 7.3.3 Implementing Higher-Order, Single-Stage 267 Modulators 7.3.4 Multi-Bit Modulators 269 Simulating a Multibit NS Modulator Using SPICE 269 7.3.5 Error Feedback 271 Contents xiii Implementation Concerns 274 7.3.6 Cascaded Modulators 275 Second-Order (1-1) Modulators 275 Third-Order (1-1-1) Modulators 277 Third-Order (2-1) Modulators 277 Implementing the Additional Summing Input 279 Chapter 8 Bandpass Data Converters 285 8.1 Continuous-Time Bandpass Noise-Shaping . . . . . . . . . . . . . . . . . . . . 287 8.1.1 Passive-Component Bandpass Modulators 287 An Important Note 289 8.1.2 Active-Component Bandpass Modulators 289 Signal-to-Noise Ratio 290 8.1.3 Modulators for Conversion at Radio Frequencies 291 8.2 Switched-Capacitor Bandpass Noise-Shaping . . . . . . . . . . . . . . . . . 292 8.2.1 Switched-Capacitor Resonators 292 8.2.2 Second-Order Modulators 294 8.2.3 Fourth-Order Modulators 296 A Common Error 297 A Comment about 1/f Noise 297 8.2.4 Digital I/Q Extraction to Baseband 297 Chapter 9 A High-Speed Data Converter 301 9.1 The Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 9.1.1 Clock Signals 301 Path Settling Time 302 9.1.2 Implementation 303 9.1.3 Filtering 306 Examples 307 Direction 312 9.1.4 Discussion 312 9.1.5 Understanding the Clock Signals 315 9.2 Practical Implemenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 9.2.1 Generating the Clock Signals 316 9.2.2 The Components 318 The Switched-Capacitors 318 The Amplifier 318 The Clocked Comparator 319 9.2.3 The ADC 320 xiv 9.3 Conclusion Index Contents 322 325 Preface Designs that combine analog circuits with digital signal processing, DSP, are called mixed-signal designs, MSDs. Designs that use both digital and analog circuits but no DSP, like a 555 timer or a pipeline ADC, are not, by this definition, MSDs. These mixed-mode or mixed analog/digital circuits aren't as robust as circuits designed using MSD techniques because they require precise components and often calibrations or tuning. The use of DSP in a mixed-signal circuit relaxes the requirements placed on the analog components (important) by overcoming the shortcomings, like low transistor gain and poor matching, found in nanometer CMOS. This book provides a tutorial introduction to MSD techniques. The content is suitable for use in a senior/graduate electrical engineering course or as a reference for a working engineer doing MSD. The assumed background of the reader is a course in signals/systems, and courses in digital and analog integrated circuit design in CMOS technology. Chapter I covers basic signals, filters, and tools. The reader may be inclined to skip this material; however, the author would recommend against it unless the reader can: 1) Give an example of an imaginary signal (answer using words and without math or equations). 2) Explain why imaginary numbers are used. 3) Explain why I/Q signals are used. 4) Describe the differences between delaying and non-delaying integrators. While we could keep listing questions, even the most seasoned systems person will likely benefit from reading and thinking about the material in Ch. 1. Don't skip it! Make an attempt to understand what is going on in the discussions and not just to understand the math. Once the reader feels they have mastered this material they should try to provide physical metaphors to describe a concept or equation (for example, use a cup, water, and a bucket to describe Eq. [1.56]). Remember that math is easy. Understanding what's going on is tough. XVI Preface Simulation examples are used throughout the book to provide an additional avenue towards understanding the book's content. In Ch. 1, for example, simulations are available at CMOSedu.com that aren't present or discussed in the book. An important part of learning is modifying a simulation, thinking about what should happen and why, then running the simulation to verify your understanding. Chapter 2 covers sampling and aliasing. These are key topics because sampling is required in any MSD system. Further, decimation (down-sampling) and interpolation (up-sampling) are commonly used in digital signal processing and thus MSD. In addition, circuits used for sampling are presented. Chapters 3 and 4 cover analog and digital filtering. The focus is on practical and useful circuits that can be used in MSD. Chapter 5 covers noise and signal-to-noise ratio. The remaining chapters in the book describe the design of data converters using MSD techniques and the associated trade-offs. An attempt has been made to present circuits and information with the goal of answering the reader's questions and provoking thought. Hopefully, this will lead the reader towards creative solutions to their circuit design problems. For example, the delta-sigma data converters presented in Ch. 7 use an active integrator. Why? Why can't a passive integrator be used? Chapter 6 develops data converters using passive elements. Both the benefits and problems associated with passive topologies are discussed leading up to answering why an active integrator is used in most delta-sigma data converters. Finally, one of the main (perceived) limitations of MSD techniques is speed. Often, in a MSD, time is traded-off for precision. The results are circuits that are precise, but slow. The pipeline ADC mentioned earlier is an example of a fast circuit that needs to be precise. Since the pipeline ADC doesn't use MSD techniques, its design can be more than challenging, especially for a production-worthy design, requiring special layout attention or extensive calibrations. The last chapter in the book, Ch. 9, presents a high-speed topology, the K-Delta-1-Sigma topology, that uses MSD techniques that may prove useful in ultimately replacing the pipeline ADC in nanometer CMOS technology nodes. The design procedures used in this topology also provide a good summary of the MSD techniques presented in the book. Acknowledgments I would like to thank and acknowledge the reviewers, students, colleagues, and friends that have helped to make this book a possibility: Jenn Ambrose, Hemanth Ande, Jeanne Audino, Kyri Baker, Mahesh Balasubramanian, Amine Bermak, Bertan Bakkaloglu, Joe Brewer, Prashanth Busa, Kris Campbell, Mike Engelhardt, Gilda Garret6n, Shantanu Gupta, Bob Hay, Bahar Jalali-Farahani, Kaijun Li, Richard G. Lyons, Pui-In Mak, Brittany Rotert, Steven Rubin, Vishal Saxena, Stu Tewksbury, Donna Welch, Thad Welch, and Aruna Vadla. R. Jacob (Jake) Baker Chapter 1 Signals, Filters, and Tools Mixed-signal circuit design requires a fundamental knowledge of signals, signal processing, and circuit design. In this chapter we provide an overview of signals, filtering, and the mathematical tools. The chapter may be a review for the reader; however, we use it to ensure a good foundation to build on in the coming chapters and to provide a quick reference for the mathematical formulas we'll use throughout the book. 1.1 Sinusoidal Signals Let's take a fundamental look at the sinewave. While there are many ways (equations and formulas) of representing a sinewave, we must remember it is an empirically determined function. Naturally occurring signals, shapes, or constants are determined or described through empirical measurements or observations. For example, rt is determined by dividing the circumference of a circle by its diameter circumference rr= (1.1) diameter The goal of this section is to provide intuitive discussions that will help create a deeper understanding of what's going on in a circuit or system. 1.1.1 The Pendulum Analogy Consider the (ideal, that is, lossless) moving pendulum seen in Fig. 1.1a. In this figure the pendulum is moving back and forth between Points I and 3 repeatedly over time. As the pendulum leaves Point I it starts out slow, gaining maximum speed as it passes Point 2, and finally reaching Point 3. At Point 3 it stops and reverses direction. The time it takes to make this complete journey back to the starting point, Point I in this discussion, is the period, T. In Fig. LIb we plot the movement of the pendulum along the arched path. We record the position to define a function, j(t), that indicates the pendulum's position at a specific time Position =j(t) =j(t + nT), where n is an integer ( 1.2) This signal, we should all recognize, is a sinusoid or sinewave which repeats its position with a frequency.j, of liT. 2 CMOS Mixed-Signal Circuit Design Point I. "~ Point 3 Point 2 ~pendulum (a) Ideal (never stops or deviates from same path) swinging pendulum in motion. The time it takes to swing from Point I to Point 3 and back to Point I is the period T. Position (along the arc) = jet) Point 3 ( Point__---2-f------~----_1f_-----'~--.---_+----~ t, time Point 1_ (b) Movement of pendulum along the arc in (a) over time. Figure 1.1 Physical interpretation of a sinewave. Next, consider the circle seen in Fig. 1.2. One complete rotation around this circle (360 degrees or 2n) is analogous to one complete movement (swing) of our pendulum. We started plotting the pendulum's position at Point 2 in Fig. 1.1b (Point 2, t = 0, in Fig. 1.2). After TI4 we reach Point 3 in Fig. 1.1b. This corresponds to a 90 degree, or n12, movement in our circle. After another TI4 seconds we pass back through Point 2. In the circle we've moved 180 degrees. This continues with each swing of the pendulum corresponding to a complete revolution around the circle. Note that we do have some -. t = T14, T + T14, ... Point 3 / t = Tl2, T + Tl2, ... » > Point I t = 3T14, T + 3TI4, ... -.Point 2 t=O, T, 2T, ... Figure 1.2 Using a circle to describe the movement of the pendulum in Fig. 1.1. Chapter I Signals, Filters, and Tools 3 limitations when representing the movement of the pendulum with this circle. For example, what is the amplitude of the sinewave (what is the relative position of the pendulum along the arched path)? We'll address these concerns in a moment. For now let's write, assuming we are using radian angular units, t) Position = sin (211' = sin(211/o • t) (1.3) This function, the sine function, tells us our relative position along the arc (the argument of this function is the angle which relates to the position on the circle in Fig. 1.2). Point 2 corresponds to the function having a value of 0 (and times, t = 0, T/2, T, 3T/2, 2T, ...), Point 3 to a value of +I, and Point 1 corresponds to -1. Finally, remember that the values of the sine function in Fig. I.l.b, and Eq. (1.3), are determined empirically from measured data (e.g., plotting the pendulum's position along the arched path against time). Describing Amplitude in the x-y Plane Examine the sinewave in Fig. 1.3a. For the moment we won't concern ourselves with the actual distance the pendulum swings. In Fig. 1.3b we represent the sinewave, at Point i (and Point vi), as a zero length vector along the x-axis (the amplitude of the sinewave is 0 at this point in time). As we move towards Point ii in Fig. 1.3a the length of the vector 4Y ~Oo (a) Portion of the sinewave 2 from Fig. 1.lb. +1 '.. - -180° 'Ii :111 y t= 0 time :l3. 0 or 211 2 0° or 360° 2700 y t= Tl8 ---~--~x ~ Length of 0 and angle of 0 (b) Point i y t= TI4 -----¥'---"~~x Length of 0.707 and angle of 45 degrees (c) Point ii y t= Tl2 ----+----"~~x Length of 1 and angle of 90 degrees (d) Point iii y t = 3TI4 -----«---~ x Length of 0 and angle of 180 degrees (e) Point iv ----i----~ X Length of 1 and angle of270 degrees (f) Point v Figure 1.3 A vector swinging around the x-y plane changing both length and angle is used to represent a sinewave. 4 CMOS Mixed-Signal Circuit Design increases (here indicating an increase in both the x and y directions), Fig. 1.3c. At T!4 we are at Point iii in Fig. 1.3a. As seen in Fig. 1.3d the length of the vector is 1 and the angle is 90 degrees. Continuing on towards TI2 (Point iv) in Fig. 1.3a the vector is shrinking once again finally reaching a length of 0 and an angle of 180 degrees, Fig. 1.3e. In Fig. 1.3f, Point v, the length is I and the angle is 270 degrees. The key point here is that a sinewave is represented in the x-y plane by a vector that is changing length and rotating around in a circle. Knowing this we can simply represent the sinewave by its peak value and the associated angle between the x-axis and the vector as indicated in Fig. 1.3. For example, as seen in Fig. 1.3d, the peak value of the sinewave occurs when the angle is 90 degrees (TI4) so we could write sin2n/o ' t ~ lL90° ~x O,y= 1 (104) knowing the vector representing the sinewave is actually rotating around in the x-y plane with time (and a frequency J;, ). Note that we could plot the sinewave more accurately by adding a third axis, time (the z-axis), and showing the corresponding, corkscrew looking, 3-dimensional plot. In-Phase and Quadrature Signals Consider moving the sinusoid in Fig. 1.3a a quarter of a cycle (90 degrees, rrJ2, or a delay, tdela)" of T14) earlier in time, Fig. lAa. We write, for this time-shifted signal, sm. (2Tn· t +2n ') =sm. (T 360' l + 90) =sm. (2Tn' ( 1+'4T))' =sm. (2n. rjo'I+2n) (1.5) As the reader probably already knows, this signal function is called cosinusoidal or simply a cosine signal and is described using I sin (2n/0' t+ ~2) cos (2n/o . t) (1.6) We can say that the cosine signal in Fig. lAa lead~ the sine signal in Fig. l.3a by a phase shift, 0, of 90 degrees (= TI4 nI2). We could also say that the sine signal lags the cosine signal by a phase shift of -90 degrees. Note that when we talk about phase shift it's assumed that the frequencies of the two signals are equaL It doesn't make sense to talk about the phase shift between two sinusoids at different frequencies. Finally note that the phase shift is given by T = tde/av 0= 2n . 2n/o . tdelay (1.7) where tdelo/T X 100 % is the percentage the delay is of the period. Figure lAb shows the x-y plane plot for a cosine signal. The peak value of the cosine signal occurs when the angle is 0 degrees so we could write cos 2n/o . t ~ 1LO° ~ x = I, y = 0 (1.8) to represent the signal and not show the rotating vector with time. Note that we can say the cosine signal is in-phase (l) since we are representing it above with a zero degree phase shift. We could also say that the sine signal, since it's shifted in time by a quarter cycle, Eq. (1.4), has a quadrature (Q) phase shift. Note what happens, looking at the vector representations of the sinusoids in Figs. 1.3b-f and lAb, if we create a signal by adding a sine signal to a cosine signal or Chapter I Signals, Filters, and Tools 5 SIQ(t) cos 21".:/0 . t + sin 211:fo . t (1.9) The resulting signal, when plotted in the x-y plane (Fig. 1.5), results in a vector J2 (sinewave) with a length (peak amplitude) of Jl2;li or that simply rotates around in a circle with a frequency of liT (=10 ). In more general terms, 1.6, +A~ SIQ(t) = AI' cos 211:fo . t+ AQ' sin2yifo . t = JA; . cos (21if" . t+tan- 1 Al (1.10) where we define the magnitude and phase as ISIQ(t) I LSIQ(t) = I2 2 JA I +AQ Ltan-I AI (1.11) (a) Shifting the sinewave in +1 Fig. 1.3a earlier by Ti4. y time \" t= TI2 '. unit circle _~_.......:;;ii.:a·Ir'~.~ x ~ ii~"" i '. . t 0 (b) Vectors representing the sinewave in (a). Figure 1.4 Shifting the sinewave in Fig. L3a earlier in time by T/4. Before going too much further, we should ask why we would want to add I and Q signals? The answer is that since the IIQ sinusoids are at the same frequency, shifted in time by a quarter cycle, we can transmit them with, for example, changes in their respective amplitudes and increase the information sent for a given bandwidth. Note that we can't shift the sinewave seen in Fig. 1.3a by 180 degrees, or Tl2, and add it to an unshifted sinewave since we would get no signal at all! y Angle is 45° Figure 1.5 Showing how an I/Q signal can be represented in the x-y plane. Notiee that the signals here are very simple. What happens when we start mUltiplying them together and shifting them in time (changing the phase shift)? We need 6 CMOS Mixed-Signal Circuit Design SIQ(t) AI' cos 2rc/o • t + A Q' sin 2rc/o . t ,v y-Iength is A Q I ~ Angle is tan-1~~ Figure 1.6 Again, showing how an I1Q signal can be represented in the x-y plane. to simplify the math!, To move towards this goal we'll develop the complex, or z-, plane and the frequency-domain representation of signals. 1.1.2 The Complex (z-) Plane Let's attempt (and fail using the x-y plane) to simplify our mathematical description of the IQ signal given in Eq. (1.10). Recall the following Taylor series expansions -k6+ 6! 8! (1.12) (U3) 7! + 9! - ... (1.14) We can now write cosk+sink l + k -k2!2- -k-3!3+ -J4(4!+ 5! _ k6 61 e-7!+k8-!8+k9-19 - ... ( 1.15) Comparing Eq. (LIS) to Eq. (1.12) we see that we are close to writing the Taylor's series for ek • Why is this important? Perhaps the simplest explanation is that if we can represent sinewaves using exponentiation, then mUltiplying two sinewaves, or shifting a sinewave in time, can be performed using simple addition (of exponents). The question now is how do we modify things to ensure that all terms are added so that Eq. (1.15) matches Eq. (1.l2)? Let's look at the first discrepancy (-1)· ~. The only way to change the polarity of this term is take the square root of -1 and move it R inside with k2 • As the reader may know instead of writing for all of these terms we simplify things and write }=R (1.16) Numbers using} (or i) are called imaginary or complex numbers (the reason for using the name imaginary will be explained in Ex. 1.1). Tmaginary numbers are invaluable for time-shifting and scaling sinusoidal signals. We now rewrite Eq. (1.12) using) as .ks k6 .e 3!+4!+J5T 6!-J"7T+'" (1.17) Chapter 1 Signals, Filters, and Tools 7 or Euler's formula elk == cosk+}· sink ( 1.18) where the cosine term is a real number and the sine term is the imaginary component of the complex number. Sometimes the following notation is used Re{ elk} == cos k and lm{ elk} == sink ( 1.19) Further, with a little algebraic manipulation we can also write elk + e-jk. ejk _ e -jk cosk= 2 ,smk 2} ( 1.20) The next thing we have to discuss is plotting complex numbers. Examine Fig. 1.7. Plotting the real component, x, of a complex number, x + }y, follows the same methods we've always used. To plot the imaginary component, we now use the y-axis. Note that the factor } in the complex number simply indicates the imaginary component and jx2 shouldn't be included when finding the magnitUde of the number, + y2 or the phase, 8, of the complex number, tan-If. z - plane z=x+}y im,y y x Figure 1.7 The complex plane, plotting the imaginary number Example 1.1 In the complex plane, plot the signal ej21t!ot . Comment on the resulting plot. As seen in Fig. 1.8 the magnitude is lel2"!o,! = 1 and phase shift is = Lei21r/ o'/ 2n/o . t. The signal simply swings around and around in the complex im,y /cos 2(2n/o . t) + sin2 (2rifo . t) ' .r. ·.~___e ___ == -1 tan sin2rifo ,r . t = 2d njo' t ~ cos2njo' t \ 1 -·---·---I"'-'-ri..·. -:----~ Re, x el2"!.,, =cos 2n/o . t +} , sin 2n/o . t \ cos 2rifo . t Figure 1.8 Plotting Euler's formula in the z-plane. 8 CMOS Mixed-Signal Circuit Design plane, on the unit circle, without changing amplitude (both the real and the imaginary components oscillate back and forth between +1 and -1). One complete rotation takes lifo, or T seconds. We need to pause a moment and ask "If the magnitude of ej2nfo-t is a constant value of 1 isn't it a DC signal?" (answer: no) When a DC signal is represented in the x-y plane it doesn't rotate or change amplitude like a sinewave does. (Well, since the frequency of a DC signal,/, is 0, you could say it does rotate around the x-y plane just like a sinewave but since T == 00 (= llf) it never leaves the x-axis). What this, eJ2rr!o'/, imaginary signal can be used for is to introduce or represent delay (phase shift). To understand this last statement in more detail let's write A . cos 2rr./o . t Re{A . el2"J" , } --1> AL.O (1.21 ) Suppose we want to delay this signal by td' We can represent a delay at a particular frequency, 1" using ej2rj~'(-/d) --1> 1L.2rc/o . (-td) --1> 1L.2rr.· -:.;: (1.22) The delayed cosine signal can be written as A . cos 2rrf· (t td) == Re{A . ej2nfr • ej2nfHd )} == Re{A . ej2,,;fU-IJ)} (1.23) To simplify the notation we can drop the real indication, Re {}. We could also describe the delayed cosine signal in terms of angle notation as AL.0.IL.2rr.'-:';:=A.IAO+2rr..-:.;:J AL.(-2rrfo·td) (1.24) Again noting that when we use angle notation, the x-y plane, or the complex plane, we need to know the frequency,l" of the input signal since this information isn't present in these representations. 1.2 Comb Filters A delay can be used to construct a simple, but very useful, filter called a comb filter, Fig. 1.9. Before deriving the equations that characterize this filter let's discuss notation. If our input signal is a sinusoid we can represent it using Vinet) = A cos 2rcf- t (1.25) If we were to keep the frequency fixed, / = 1" and vary time, which we've done up to this point, the output signal of a circuit will simply repeat itself (at the same frequency as the input signal). What's more useful is varying the input signal's frequency,!, and looking at the output of the circuit or system (how the amplitude and phase shift vary). To move vinCi) . e-j2rftd delay ~ 1-1~ Vin(f)--3ft-)o..... v,,,(J) Figure 1.9 A comb filter. Chapter I - - - _.. Signals, Filters, and Tools _------- - - - - - - - - - - - - - - 9 towards this method of characterization let's write the frequency domain description of Eq. (1.25) as vin(f) or simply v,n' Representing a signal in the frequency domain will be discussed in the next section. Returning to our comb filter in Fig. 1.9 we can write (1.26) or, using Euler's formula, Real Imaginary r- ..~ ~..--------., l+cos2nj-(-ld) + j·sin2rrf·(-ld) ( 1.27) The magnitude response of this filter is J(l I~:I I +cos2rrf· (-td»2 + (sin2rrf· (-td»)2 b(l +cos2nj- td) ( 1.28) or using I+cosx 2COS2~ ( 1.29) simply ( 1.30) The phase response is given by tan-l [ sin2rrf· (-td) ] 1 +cos2nj- (-ld) (1.31) Notice at 1/(2td) the phase is tan- 1(010), which evaluates to ± 90 degrees. Using Eq, (1.29) and sin x 2 sin E. cos E 22 ( 1.32) the phase response is LVVO.UI = n(-td) I for J< l/(2t d) In (1.33) Note that the phase response is linear indicating constant delay through the filter, important for distortionless filtering. Figure 1.10 shows the magnitude and frequency response for a comb filter (at this point the reason the filter is called a comb filter should be obvious). Example 1.2 Figure 1.11 shows one possible implementation of a comb filter. A 50 Q characteristic impedance co-ax transmission line with an electrical length of 5 ns (delay) is used for the delay element (note how the transmission line is terminated with a 50 ohm resistor and it is assumed that 50 n « 5ill so that the 5ill resistors don't load the output of the transmission line). Determine the comb filter's characteristics (transfer function, vojvin). Verify your answer with SPICE. 10 CMOS Mixed-Signal Circuit Design L VOU ( Vi" degrees 2 ,. - 45- - - 90 - . _1 l 4td 2td td 2td f(Hz) _1 -12 t d 4td 3 2td Figure 1.10 Magnitude and phase response of the comb filter in Fig. 1.9. In order to perform the addition operation seen in Fig. 1.9 we use the two 5k resistors seen in Fig. 1.11. The current through the top resistor must equal the current through the bottom resistor or Vinej2n{(-ldl 5k VOIlI VollI - Vin 5k (1.34) and thus Vout is the average of the signals on the top and bottom of the resistors (1.35) The result is our derivation of the comb filter's magnitude response in Eq. (1.30) is scaled by 2 or I I I~:f I=Icos nJ- tdI= cos n 200~Hz (1.36) The phase response is still given by Eq. (1.31). SPICE simulation results showing the filter's frequency response, magnitude and phase, are seen in Fig. 1.12. Note how the filter eliminates from its output, input signals at frequencies that are multiples of 1I2td. This filter can be very useful in communication systems where it's used to isolate, and prevent crosstalk between, transmission channels. In order to ensure that we can sketch time-domain signals from frequency domain plots consider the case when the input has I V peak amplitude and a frequency of 50 MHz. We can see from these plots, and the equations, that the Transmission line Figure 1.11 Implementation of an analog comb filter. Chapter 1 Signals, Filters, and Tools 11 ---------------------------------------------------------- 60' 20' -20' -60' 1.0V T"""'<:,...--r-.-..,.---~/~;;:_'_'c:..c..:"'--,---__:"....,..~--__, 0.9V O.8V 0.7Y O.sv O.SY O.4V D.3Y O.2V D.W O.OV-'---i--4-----i--------¥----i------4 50 MHz Figure 1.12 Simulating the operation of the comb tilter in Fig. 1.11. output will have an amplitude of 0.707 V and a phase shift of -45 degrees (or the output is lagging the input by 2.5 ns). Time domain simulation results are seen in Fig. 1.13. Note, in this figure, that there is a start-up time, the time it takes the signal to propagate through the transmission line (note the kink at 5 ns), before the filter's behavior follows the equations we derived.• Figure 1.13 Time domain input and output (50 MHz) for the comb filter seen in Fig. 1.11. 1.2.1 The Digital Comb Filter Notice how, when discussing the comb filter, it was more useful to vary the input signal frequency, j, and look at the output (Fig. 1.12) of the circuit rather than attempting to change the input with time and plot the output. In our comb filter the input signal was delayed by td' We represented this time delay in the complex plane using eil1tfHd). In a digital system we can implement the delay line seen in Figs. 1.9 and 1.11 with a register, Fig. 1.14a. The contents of the register change, in Fig. 1.14a, every Ts seconds 12 CMOS Mixed-Signal Circuit Design Time domain In~Out T /s=~ Ts (a) A register that is clocked atls that delays the input signal byTs • Frcquency domain Vin(f)-t--i;:-}+- Vin(f) =Z-I . Vout(f) (b) Representing a delay in the eomplex plane. Figure 1.14 A digital delay. (so this would correspond to ta in Fig. 1.1l). To simplify the notation, since delays are so common in a digital system that processes signals, we can use = = z e j2T"/T, e j2n'(r, or, for a delay, z-I e j2rrf(-T,) e (1.37) This representation for a delay, in the frequency domain, is seen in Fig. 1.14b (some authors use Z-1 to indicate a delay, e j2n(-(-T,), and to differentiate behveen the general i situation where z x +jy). Figure 1.15 shows how Eq. (1.37) is plotted in the z-plane (the dashed circle). The magnitude of e j2rrfT, is one and its phase shift is 2rcj- T5 or 2rc· (plotting eIlrfT, in the z-plane simply plots the unit circle). Note that plotting a delay, Z-I or e j2nf(-T.• ), also results in a magnitude of one but the phase shift is now -2rc/- Ts. As we move through the book we will regularly use Eq. (1.37) to evaluate the frequency response 0/ a discrete-time system, see Fig. 1.21 and the associated discussion, and to relate the complex number, z to the/requency,.f 2nf 2nf: = t 14 Js , 5; t 'ls i14~ 9lt 14t. 1m, Y Pl ot t i n g e J' o - n£ f, cos /~ I . / z x-"-jy +j . sin i -~-.-~="----+---t:---~ Re, x / == /sI2, 3Js12, 5/5 12, 0, j" 21s, 31s, ... 3Js14, 7/5 /4, 11/514, ... Figure 1.15 Plotting a delay in the complex plane. Figure 1.16 shows the digital implementation of the comb filter. We can write (1.38) and thus the transfer function is (1.39) or, after reviewing Eqs. (1.27) to (1.33), we get Chapter 1 Signals, Filters, and Tools 13 Vin~VO"t Figure 1.16 A digital comb filter using one delay. Note how the output is the average (sum) of consecutive inputs. I I / I voull Vm 2 . cos 1Its- artd L -VoU,l Vm -rr . -/ "lor / ~ ou~u: I. ,, In ~t I Sampler yet) = x(t) . 8(t- nTs) Sampling impulses: 8(t- nTs) Figure 2.2 Impulse sampling a signa\. Chapter 2 Sampling and Aliasing 29 IY(f)1 Volts In Ts (2is-fm) is \2fs (a) Input spectrum / (2is +lin) (b) Output spectrum after sampling Figure 2.3 One-sided spectrum of a sinewave (a) before and (b) after sampling. sampler is connected to an ideal LPF) with a bandwidth greater than /;n (and lower than In [the Nyquist frequency]), then the higher-order frequency components can be removed so that only /;n remains (this is our smoothing or reconstruction filter shown in Fig. 2.1). Example 2.1 A sampling gate is strobed with an impulse train running at a frequency of 100 MHz (is = 100 MHz and the time in between the impulses, Ts, is 10 ns). Sketch the resulting output frequency spectrum if a 60 MHz sinewave is applied to the sampler. Also, sketch the time domain input and output of the sampler. The resulting frequency spectrum is shown in Fig. 2.4. Notice how connecting the output of the sampler through an LPF, with an ideal abrupt cutoff frequency of In, results in an output sinewave with a frequency of 40 MHz. In order to avoid this situation, that is, to avoid ending up with the wrong, or alias, signal after sampling and reconstructing, we need to ensure that the signal frequencies applied to the sampler are less than Isl2 (the Nyquist frequency, again, In). Reviewing Fig. 2.1, we see that this is the purpose of the antialiasing filter (AAF). Notice how, ideally, both the AAF and RCF (reconstruction filter) in Fig. 2.1 are both ideal LPFs with a cutoff frequency equal to half the sample frequency (the Nyquist frequency). Figure 2.5 shows the time domain sketch of the sampler's output. • Aliased signal 40 60 50 100 Itn 12..:. Jt S 140 160 150 200 2j~ I 240 ' 250 )0 MHz f Figure 2.4 Spectrum of a 60 MHz sinewave sampled at 100 MHz. It should be clear from the preceding discussion that: (1) sampling a signal results in a reproduction of the sampled signal's spectrum at DC,/s, 2/s, 3/s, etc., (2) the input signal's spectrum should have no significant spectral content above J" in order to avoid 30 CMOS Mixed-Signal Circuit Design Sampler outputs ~ Alias 40 MHz sinewave \~ Figure 2.5 Time domain input and output for Ex. 2.1. 100 ns aliasing, (3) to avoid aliasing both filtering the input signal using an AAF and increasing the sampling frequency should be used, and (4) to reproduce the sampled signal from the output of the sampler (which is nonzero only during the sampling impulse times) a lowpass RCF should be used. Note that our discussion illustrates the operation of a sampling gate driven with impulse signals. As shown in Fig. 2.1, a practical system would have other building blocks. We would rarely, if ever, sample a signal and then reconstruct it without processing it first. A Note Concerning the AAF and the RCF Before going any further, we should discuss the ideal characteristics of the AAF and the RCF. The ideal characteristics of these filters are shown in Fig. 2.6. Note that both of these filters must be analog by design. The ideal cutoff frequency for the filters can be no greater than In (assuming the sampling rate on the input of the system is the same as the sampling rate on the system's output) and the filters should ideally have linear phase. Let's discuss these two ideal characteristics. /= IH(jro) I = I for AAF Ills for RCF A ! r----, LH(jro) ~n=fs!2 o ; ~ ) f : slope ;-2TClo In =fs!2 f (a) (b) Figure 2.6 (a) Ideal magnitude and (b) phase responses for the AAF and RCF. Chapter 2 Sampling and Aliasing 31 ------~--------------------------------------------------- The ideal magnitude response, shown in Fig. 2.6a, passes all spectral content below the Nyquist frequency while removing all signals above this frequency. The ideal phase response, shown in Fig. 2.6b, provides a constant delay, to' to all signals below I.. In other words, the filters remove all unwanted signals while not distorting the wanted signals. Time Domain Description olReconstroction In this section we show why the filter shown in Fig. 2.6, an ideal brick walliowpass filter with linear phase response, is the ideal RCF on the output of our impulse sampler. Shown in Fig. 2.7 is a 20 MHz sinewave sampled at 100 MHz. Suppose we want to reconstruct the original input 20 MHz sinewave from the sampler output (the weighted impulse functions). After reconstruction, the output of the RCF should be a single-tone, 20 MHz sinewave (it should be an exact replica of the sampler input). To determine what happens when the output of our sampler is applied to the ideal RCF, we need to determine the time-domain response of the RCF when its input signal is an impUlse. J Sampler input, 20 MHz /SrunPI"outP~ 10 ns Figure 2.7 Impulse sampling, at 100 MHz, a sinewave at 20 MHz. The transfer function of a system is the Fourier transform of the system's time domain impulse response (what we are trying to find here). In other words, to determine the transfer function of the system, we apply an impulse to the input of the system (a very large amplitude, very short time duration pulse, Fig. 2.8). We then look at the system's output in the time domain. Taking the Fourier transform of this output gives the system's 1 Impulse input to t LIdeal ReF ReF - ti~e_ - - t I l l s 10 . ~ 11 ~+-.~ tI.me o 1 - - - - - t=O In f Figure 2.8 Time domain impulse response of the ideal ReF. 32 CMOS Mixed-Signal Circuit Design transfer function. Therefore (in the reverse order), to determine the time-domain impulse response of the ideal RCF, given the transfer function, we take the inverse Fourier transform of the transfer function. The ideal RCF's transfer function (Fig. 2.6) can be defined by IH(j)1 Ills for IfI time Figure 2.10 Reconstructing the 20 MHz sinewave of Fig. 2.7. An Important Note It is important to note that our impulse sampler quantizes I the input signal in time but not amplitude (unlike an analog-to-digital converter which quantizes the input in both time and amplitude). The amplitude out of the ideal impulse sampler is exactly the same as the amplitude input to the sampler at the sampling impulse times. The z-transform can be used to describe systems using both quantization in time as well as in amplitude. In other words, whether we are discussing digital words, in a binary format, or sampled-analog waveforms with amplitudes of volts, amps, or coulombs, we can use the z-transform to represent the discrete-time systems that process the signals. Laplace-transforms are used for continuous-time systems. 2.1.2 Decimation In the last section we focused on sampling analog signals. We can apply the same concepts to digital signals. When a digital signal is "down sampled" its sample rate goes fromis to a lower rate ofislK where K is generally, but not necessarily, a power of2 (e.g., 2, 4, 8, 16, etc.). This reduction in the effective sampling frequency is termed decimation and is illustrated with the block diagram shown in Fig. 2.11. The term decimation (or x[nTd I Decimate (reduce sample rate) y(Ki· Ts] I ~K ~I.n:.:..-_-++--_ _ - I'> / ); Out Input word rate, Is Output word rate,f,IK Figure 2.11 Block diagram of a decimation block. I Quantize: to limit the possible values of a quantity to a discrete set of values. Quantizing in time, for example, means that the output amplitude is only defined at certain discrete times (such as the sampling impulse times for the ideal impulse sampler) or that the amplitude is unchanging during certain discrete time intervals (such as seen in the output of the ideal sample-and-hold discussed in the next section). 34 CMOS Mixed-Signal Circuit Design decimate) can be confusing since, among other uses, the dictionary definition "to select by lot and kill one in every ten." The origin of the word comes from a method of punishing military troops by selecting one in every ten for execution. Our much more kind-hearted definition will mean that we are passing the input word through a lowpass digital filter and then down-sampling the result (discarding samples). This procedure is effectively passing the digital data through an anti aliasing filter and then resampling the result at a lower rate, Fig. 2.12. Note that the sampling gate is simply a register so it is trivial to implement decimation. Input JlJ1JUl Sampling gate : Out y[Ki· Ts] f..----'-I-_+_- Output word rate,/sIK Clock divider,!, .;- K ~~ •• elk ••• Output clock ,~ Figure 2.12 Components of a decimation block. To illustrate the aliasing concerns when using decimation, and K 8, examine Fig. 2.13. The input spectrum of the digital data, in (a), repeats every f,. The digital input data in (a) is first passed through a digital lowpass filter that is used as an anti-aliasing filter, Fig. 2.13b. The input and output of the digital filter is clocked atf, in both (a) and (b). In (c) we re-time the input signal at the slower rate. Decimation is used to lower power (because of the reduced clock frequency), simplify circuitry (e.g., serial multipliers can be used), and to lower the amount of data storage required (fewer words to store). Note that to use decimation the wanted input spectral content can't extend beyond /s12K. A :/s116 /,/2 (a) (b) (c) /clk .fs/8 fsl2 Desired sig;al spectrumS; /s/16 /s signal spectrum aftcr AAF: j, Assuming K = 8 ••• @/s f ••• @/s f ••• @j;./8 f Figure 2.13 Example spectrums when decimation is employed. > .; C' Chapter 2 Sampling and Aliasing 35 < 2.1.3 The Sample-and-Hold (S/H) Understanding the operation of the impulse sampler in Sec. 2.1.1 is important in understanding the concepts of aliasing and reconstruction. However, as seen in Fig. 2.1, most mixed-signal systems employ a sample-and-hold (SiH) rather than an impulse sampler so that the sampled waveform is available at times other than the sampling impulse times. Having the samples "held" in between the sampling impulse times is important for proper ADC operation. The disadvantage of using the S/H, as we shall shortly see, is that it will introduce distortion into our signaL hVin j;n / ' \ ~ ~ ~lC_n ___4> Sample and hold (SIR) in, A IV V ti.m)e ~y(t) clock l'igure 2.14 Sampling and holding an input sinewave. Sill Spectral Response Consider the application of a sinewave, at a frequency In' to thc ideal S/H shown in Fig. 2.14. To make the discussion as general as possible, assume that the output ofthe SIR can return-to-zero (RZ) as shown in Fig. 2.15 (which shows coarse time quantization for a simpler figure and illustration of the concept ofRZ). Notc that as T approaches 1~ we get the operation of the S/H in Fig. 2.14. The output of the ideal SIR is given by y(t) L'" [Vpsin (2rrf,n . nTs) . [u(t nTs) u(t - nTs - T)]] n=~(1) (2.S) As depicted in this equation the input is sampled at the instants nT and then held at the sampled value v;n(nTs) for a pulse length of T. We can represent the resulting signal using convolution, see Fig. 2.l6a, as y(t) II< time > S/H out Figure 2.15 Sample-and-hold output with return to zero format. 36 CMOS Mixed-Signal Circuit Design vm(nTs) IX; r""·----~--·· yet) 2: [Vp sin(21tfin·t)·o(t-nT,)]®[u(t)-__1 switch turning off is independent of the input signal. When the 4>2 switch turns off its charge will, ideally, be injected into the low-impedance input, vin , since the impedance looking into the right of the 4>2 switch is large. This leaves the voltage across the hold capacitor unaffected. The sequence of turning off the switch to the right of CH (the top plate) followed by turning off the switch connecting vin to CH (the bottom plate) is often called bottom plate sampling. Bottom plate sampling is illustrated in its simplest form in Fig. 2.21. In this figure the switch connected to the bottom plate of the capacitor, the 4>] switch, is turned off first. When this happens the charge is injected into the eircuit independent of the input signal (each side of the switch is at ground). When the <1>2 switch turns off, its charge can be injected into the low-impedance node, the input v", , or into the series combination of Cll and the off <1>1 switch. Again, the charge takes the lowest impedance path to ground and thus most of the charge injection resulting from the 4>2 switch turning off flows through vin' leaving the voltage across the hold capacitor unaffeeted. The name "bottom plate sampling" can be confusing. Reviewing Fig. 2.20, we see that the (physical) top plate of the hold capacitor is connected to the <1>: switch while, in Fig. 2.21, the (schematic representation) bottom plate of the hold capacitor is connected to the 4>1 switch. ,I. Turns off last 'l'2~ It:~lCH :!' the lowest impedance path to ground. <1>J I~ 7 Turns off first Figure 2.21 Bottom plate sampling. An Example Before leaving this section let's give an example of the speetrums associated with (ideal) sampling and reconstruction using a S/H, Figs. 2.1 and 2.22. In Fig. 2.22a we represent an input signal as a continuous spectrum that is not bandlimited (that is, the speetrum is completely occupied). In a real spectrum the spectral components don't have a constant amplitude (e.g. noise at high frequencies may be considerably smaller than desired content at low frequencies) but here, to simplify things, we assume a constant amplitude. The first step in our example is to pass the input signal through an ideal AAF to limit the spectral content to the Nyquist frequency, //2, Fig. 2.22b. At this point the spectrum hasn't been sampled so it doesn't repeat at multiples off;. The output of the AAF is then passed through the S/H. In Fig. 2.22c we show the Sinc weighting from the sample-and-hold process but we don't show the effects of sampling. Note the droop in the response at frequencies approaching//2. In (d) the output of the S/H is seen. Note how the cntire spectrum is occupied. Finally (e) shows the output after passing the S/H's output through an ideal RCF, Fig. 2.19. Note that the spectrum is no longer periodic. Chapter 2 Sampling and Aliasing 41 (a) ~ ~) (b) +1____________________ ____s_p_e_ct_ru__m_a_fi_e_r_id_e_al_A__A_F_:_____._._.__ --------____-= A Note droop ______ : Spectrum showing weighting : f (c) ~~_: J-f-r-o-m--S-IH--b_ut. n_o-t-s-h-o-w--i-n-g-effe_ c>ts-o f sampling ••• ) t ~f (d) -t-!_ _ _ _ _ _---+_ _ Spe_ ctrum_aft_ er id_ eal S_ /H '--_••_ • ) ReF response ~ f (e) Spectrum after ideal ReF, same as (b) ••• > fsl2 f Is Figure 2.22 Example spectrums when ideal, AAF, S/H, and ReF are used. 2.1.4 The Track-and-Hold (T/H) Another sampling circuit that is useful in mixed-signal circuits, especially those employing both analog- and digital-signal processing, is the track-and-hold, Fig. 2.23. The T/H is implemented using a sampling gate, here a MOSFET, and a storage capacitor. When the gate of the MOSFET is driven high it turns on and allows the input signal to directly drive the capacitor (the T/H's output). In the following discussion, we are assuming that the product of the MOSFET's on resistance and the hold capacitor, Rch . CH, is much smaller than the period ofthe input signal. Track Track ~ Sinewave in Vinet) ~""Ui0Jt: ~~ o ! •I ut yet) :.e T :( T! > time Track Figure 2.23 Track-and-hold output. 42 CMOS Mixed-Signal Circuit Design To determine how the TIH affects a sampled signal let's first notice that the hold portion of the output is exactly thc samc as the SIH with RZ format seen in Fig. 2.15, Eq. (2.15). Knowing this we can focus on the track portion of the output and then sum the responses to get the overall TIH response. For the track portion of the ideal T/H we can write, sce Eq. (2.8), lr YI(t)=n~oc Vp sin(2rt/in· t)· h,ul [u(t-nTs-T}-u(t-nTs Ts n~ro Vp sin(2rt/i1l' t) . {hl(t)@ O(t- nTs)l (2.17) Knowing 00 00 L 8(t nTs) has a Fourier transform of!s L o(f- kis) n=-oo k=-XJ we can write (2.18) (2.19) Reviewing Eqs. (2.12) and (2.13) we can write . (Ts T). Sinc(rr; I (T, T) (2.20) and so, since!, = 1ITs' HI(f)-j, ~00 8(f-kfsT)=~T·.~'" k~-oo s k-··~ro . Sinc(rr;· kj,' (T, T»· 8(f- kf,) The track portion ofthe T/H's output spectrum for an input signal, vmC!), is k~m fl(f) =Vin(f)@l TSTs T. j . Sine(rt· kf, . (T, - T). 8(f- kf,,) (2.21 ) For the single-tone input sinusoid used in Eq. (2.17) YIU) = Vp(2TsT T) . ~ £..., (. Smc(rt . kfs . (Ts T). [8(f-.fin kfs) - 8(f+fin - kfs)] . ) '.), k=···", or (2.23) en Ifl(f)1 L k=-oo Weighting from ht(t) -T)·Sinc(rt·kj,·(Ts Ideal impulse sampler response 2;, .V T»· [8(f-fin-kfs)-8(f+fin (2.24) Chapter 2 Sampling and Aliasing 43 The total T/R output spectrum, YTIH(/), for a general input signal VinCI), is the sum of Eqs. (2.15) and (2.22) or YT!H(f) = Ts ·Sinc(n IT)· T e-j ·2rr.f-; . k~00OO vm(f-kfs) + f Ts-T. Ts k=-oo IfT= TsJ2 = 112/s then we can write this equation as L00 1 ( { f 1\ YT!H(f) = I -. SincllI· -) . e k=-oo \. 2 2 Is (2.25) We know from Fig. 2.17 that a sinewave at nearlyJ;, will see an attenuation of 0.64 (-3.9 dB) when using a SIR with T = Ts. Using the T/H with T = T,/2 the attenuation the sinewave sees at nearlyJ;, (f~ /,/2) where k = 0 (the frequencies from DC to1/2) is !I I IYTlJ{(f)I = Sinc(~) . + 1 . eO (2.27) or (2.28) We know we can't directly add the polar representation of these numbers so let's rewrite this equation, noting 0.9 cos (-~) = 0.636 and 0.9 sin (-~) = -0.636, using the Cartesian representation as IYl'lJ{(f) I = ~ 10.636 +j(-0.636) + I +jOI = 0.877 ~ -1.1 dB (2.29) Note that if we are sampling an analog waveform for Nyquist-rate, analog to-digital conversion then we have to use a S/H (or the hold portion of the T/H). In this situation we don't want the input to our quantizer (ADC) to vary, as it does in the T/H during the track portion, since this will cause an error called aperture uncertainty (discussed in Sec. 5.2.1). 2.1.5 Interpolation One of the main assumptions when reconstructing the output signals, in the preceding discussions, is that an RCF is available with a brickwall like shape (Figs. 2.9 and 2.19) and a cutoff frequency of 1/2 (the Nyquist frequency). This, however, is a very challenging analog filter design problem. To make the design of the RCF less challenging we can increase f, while keeping the desired spectrum limited in bandwidth. In other words, by increasin8.f, the effective Nyquist frequency becomes larger than the maximum wanted frequency of interest. This is called oversampling. Decreasing the clock frequency (decimation) was covered in Sec. 2.l.2. Here we cover increasing the clock frequency (call interpolation). Both decimation and interpolation can be used in discrete-time analog signal processing. Here, in this introductory seetion, we foeus on digital signals. When a digital signal is "up sampled" its rate goes from J, to a higher rate of K -/s. As with decimation, K is generally, but not necessarily, a power of2. Interpolation is represented as seen in Fig. 2.24. 44 CMOS Mixed-Signal Circuit Design Interpolate (increase sample rate) i x[nTs] I _In_---.,f-;I>11'__---11 K ;' ) Y[l.' Kr'l Out Input word rate,is L~ _ _~ Output word rate, K is Figure 2.24 Block diagram of an interpolation block. There are three basic interpolation schemes (ways of increasing the sampling, or clocking, frequency): zero padding, using a hold register, and linear interpolation, Fig. 2.25. Figure 2.25a shows an example input to an interpolator. In (b)-(d) we show interpolation with K 4. Zero Padding The benefit of using zero padding, Figs. 2.25b and 2.26, is that the desired spectrum remains unchanged. We'll discuss this more in a moment. The drawback of zero padding is that the amplitude of the output signal drops by K. If our input is a constant value of 1 and we insert 3 zeroes (K 4) then our output has an average value of 0.25 (average of 1, 0, 0, 0). This is normally not a problem for a digital signal since we can simply increase x[nTs] (a) input signal ~ • •I • • • i I+-_-'-_-'-_! --'-_.-L~_---,-_ • I 2 ___,--'---,~--'----+) n...~L. Y[/.. KTI] !... I... " (b) zero padding T•••,•••I...i.......r...t•••,••• >1' Kt 12 4 ' Ts ""IIIIIIII 1m tiTr~m Y[I.' t T,] K tllli .ll.llil ~,. (c) hold register ttTt,,,, Kt y[i'~] • ~1"~' • .1'T . ['::"''" ~ll." Ts Figure 2.25 Types of interpolation. Chapter 2 Sampling and Aliasing In (a) ---f/~)-----i~ I ... Input sample rate,x[nT,] clk! ..§ ' o Is o ;:s OUe:)>CJ Sel 45 (c) or (d) y[ i . I------,f--_ .-----~KIs Kis Figure 2.26 A zero-padding interpolation block, see spectrums in Fig. 2.27. the word size and shift each nonzero sample towards the MSB by log2K (assuming K is a power of 2). For the present example we would shift the constant value of I to the left two places resulting in 4. When we average the 4 samples (4, 0, 0, 0) we get 1 (our original input). In the following, and in Fig. 2.26, we won't explicitly show the shifting in the input or output words to compensate for the signal reduction when using zero padding. Returning to Fig. 2.26, we see that our input signal changes every Ts seconds and has the assumed spectrum seen in Fig. 2.27a (marked (a) in Fig. 2.26). A log2K size counter and AND gate are used to select the input signal one of K times so we get the zero padded waveform seen in Fig. 2.25b (spectrum shown in Fig. 2.27b). Note that the Nyquist frequency has moved from 1/2 to Kj;/2. The problem is that the images are still (a) I, New ~uist frequen~y K=4 ••• f (b) ••• f removal filter' (c) Cd) K·fs/2 K·1s ••• 2K·1s f Figure 2.27 Example spectrums when zero padding interpolation is employed. 46 CMOS Mixed-Signal Circuit Design present in the wavefonn and thus need to be removed. This is the point of using the image removal filter seen in Fig. 2.26. Figure 2.27c shows the spectrum after increasing the sample rate and passing the signal through an ideal image removal filter. Also seen in this figure is the response of the RCF. It now starts rolling off at is 12 and can extend up to Kf, - f,/2. Note that the RCF's response seen in Fig. 2.27a must cut off abruptly at is 12. Finally, Fig. 2.27d shows the spectrums when a non-ideal digital image removal filter is used. The figure shows the nonzero spectral content remaining in the spectrum after filtering. Hold Register Figure 2.28 shows the block diagram of interpolation using an input hold register (which may simply be the input of a digital filter). The benefit of this topology is simplicity. We simply clock the input word K times faster into a register to increase the clocking frequency as seen in Fig. 2.25c. Note how the wavefonn seen in Fig. 2.25c looks similar to the output of the S/H discussed earlier in the chapter (so we should be expecting some sort of Sinc response effect on our input signal as seen in Eq. [2.16]).In order to quantify this last comment we can write the output of the hold register in tenns of its input using r L T ] Yu i·..2. r_ K = K·(n+ 1)-1 i~Kn -1 · K x ~ T i·..2. K ] =x[nTs] (2.30) noting, K· n :::; i ~ K . (n + 1) I , or J J J J ~ K -yu(nTs} == x[Kn· +X[(Kn+ l)~ +X[(Kn+2)~ + ... +X[[K' (n+ 1) 1]~ (2.31 ) Writing the z-domain representation (using the input clock as the reference for the delays, or, z e j2v.fT,) of this equation gives Yu(z)· zn . K == [l + Z11K + z21K + ... + z(K-l}/K} . zn . X(z) (2.32) or, where the zn represents a shift in time of nT" Yu(z) ==.1. [1 + zllK + + ... + z(K-l)IK] X(z) K (2.33) In UpsampJed output ~Yu [. I- KTs] Digital filter -----.~--~DQ~+-~----~ Input word rate,x[nTs ] elk @is Figure 2.28 An interpolation block using a hold register, see spectrums in Fig. 2.32. Chapter 2 Sampling and Aliasing 47 Ifwe multiply the top and bottom of this equation by I H (z) = Yu(z) u X(z) or we get (2.34) (2.35) Knowing 11 1(1 cosx)-jsinxl = I-cosx 2 8in 2", we 2 =J2(1-cosx) and 1 (2.36) K Ifwe label the interpolator's output frequency Is,new K·1s then 1 sin (rc. IHu(f)1 =K-. sm. 1 Sine(rcfsK.nf~) Sine ( rcf,~J (2.37) This equation is sketched in Fig. 2.29. This isn't exactly a Sine response, Fig. 2.17, but a similar-shaped response. We'll find that this equation also comes up when discussing Sine response digital filters so let's spend a moment characterizing it. The ratio of the main lobe to the first sidelobe can be determined by evaluating the response at 1.51s,new1K or (urc'\ I Main lobe IFirst sidelobe K. . sm K) (2.38) This equation is plotted in Fig. 2.30 for varying K. Note how the maximum amount of attenuation approaches 13.5 dB (the same as the Sinc response seen in Fig. 2.17). IHu(f)I Desired sl"""~"""-_ f K K K is,new 2K Is,new K·1s Figure 2.29 Frequency response interpolated data sees using a hold register. It's also of intcrest to determine how much droop the filter will introduce into the signal frequencies of interest at the Nyquist frequency. Figure 2,31 shows the droop 48 CMOS Mixed-Signal Circuit Design (attenuation) at the maximum desirable input frequency of j,/2 or j"npw/(2K). We can calculate the amount of droop, again using Eq, (2.37) when ls,new/(2K), as Droop == . (1t) K,sln UK (2.39) This equation is plotted in Fig. 2.31. Note that as K gets large the amount of droop approaches 3.9 dB (= 0.64) or the same as the Sinc response seen in Fig. 2.17. dB 4 13.5 dB I:! . I Main lobe IFirst sidelobe -tlill-i-I 346 8 1 !~ 10 K Figure 2.30 Attenuation versus K. Figure 2.32 shows some example spectrums when K = 4 and using an input hold register for interpolation. In (a) we see a representative input spectrum that repeats every is. In (b) the input is upsampled to a clocking ratc of K -j,. The effects of the input holding register's Sinc response are seen. At this point we have distorted our desired information with the drooping response seen in Fig. 2.31. In (c) the signal's spectrum, after passing through an ideal image removal filter to remove the undesired frequency components, is seen (see also Fig. 2.28). The RCF can have a slow roll-off ultimately passing negligible content at frequencies above K·1s - I sl2 where the image around the new clocking frequency, K·j" exists. Finally, in (d) we show what the spectrums may look like with a non-ideal image removal filter. The design of the RCF depends on the allowed amount of unwanted spectral content that can be tolerated in the final output spectrum. IHu(f) I I~Dmop :::t·Droop, dB ~-.-----:- --.--.--.~ !s,new/2K ! or f,/2 -3.8 -1 -4,0 t--t--t-+-+ +-+-1-+--+I~ 3 4 6 8 10 K J<'igure 2,31 Droop at edge of signal bandwidth. Chapter 2 Sampling and Aliasing 49 K=4 f (b) (c) (d) fsl2 . After (ideal) image removal filter f ••• f ... f Kf, 2K·1s Figure 2.32 Example spectrums when interpolation using a hold register is employed. Linear Interpolation The final interpolation scheme we'll look at is linear interpolation, adding samples in between the interpolator's inputs that linearly change with time, Figs, 2.25 and 2.33. We can describe linear interpolation mathematically using Yu [C ' 1+ \ ) . TK s ] _- Yu [ .. 1 TKs] + x[(n+l)TsKl x[n·Ts] (2.40) where K·n:5,i__1 switch opens at (n 1/2)Ts the charge on the capacitor is (2.44) and when the 4>2 switch opens at nT, the charge on the capacitor is Q2 vout[nTs]' (C[+ CF) = vin[(n lI2)Ts] , Ct+vout[(n-l)Ts]' CF Writing this equation in the z-domain we get (2.45) (2.46) or VOUI(Z) Vln(;;;) == Ct+CF CF'Z-I (2.47) If we input a DC voltage, f = 0 or z I, then the output is equal to the input (the magnitude of Eq. (2.47) is one). This circuit behaves, for input frequencies «fs like a simple RC circuit (as seen in Fig. 2.35). To prove this let's write is z ej2n.f1t~ "" 1+}2rcZ 1+ for f«/S (2.48) and, knowing the ;;;-112 term in the numerator is simply a phase shift of one-half clock cycle (which is negligible for input frequencies «D, (2.49) or Equivalent for input frequencies i 1 rS~l VO"t(t) R,,- f,C, ~ CF (n ,'0)0 time (n+ 1I2)Ts Figure 2.35 Switched-capacitor lowpass filter. 52 CMOS Mixed-Signal Circuit Design (2.50) where we've defined _ Ts - C/ (2.51 ) We can also write the exact frequency response, Eq. (2.47), of this switched-capacitor circuit (~~ + I - cos 2rr.flf,) +j(-sin 2rr.f/fs) (2.52) or (2.53) Note that for f «fs the cosine terms is approximately one and the sine term is approximately 2rr.flf, so this equation simplifies to Eq. (2.50). Next let's examine the two-path version of Fig. 2.35 shown in Fig. 2.36. The effect of using two paths is to double the output sampling rate, fs.new =2fs. Using Eq. (2.47) we can write (2.54) At the new sampling rate we can write 'Z-l H2-path(Z) = C/+ C F C -2 F'Z (2.55) or, in generic terms of K, replace Z in the transfer function of the single-path topology with zK to get the transfer function in the K-path topology, (2.56) Figure 2.36 Switched-capacitor 2-path lowpass filter. Chapter 2 Sampling and Aliasing 53 Figure 2.37 shows K-paths and the equivalent single path topology, a time interleaved topology. Note that at this point there are several important topics we can discuss including path matching and the effects of clock jitter (more later). ~~~.----------:~ n ~~--------~--- ~3 : _ _ _ _- - ' _ _ ~4 LnL______T-__ ••• Non-overlapping docks (b) Equivalent circuit z ej21tjl(Kj,) :~ Ts/K Figure 2.37 A K-patb topology and its equivalent circuit. Non-Overlapping Clock Generation Figure 2.38 shows a circuit useful for generating four-phase, non-overlapping, clock signals. A shift register is preset so that only one bit is high. The logic block seen in the figure is used to detect ifmore than one output is high. Note the clear and set inputs of the flip-flops. The amount of non-overlap, or dead time, between pulses is set by the delay through the two inverters connected to the outputs of the NAND gates. elk Shift register Figure 2.38 Generating a four-phase non-overlapping clock signal. 54 CMOS Mixed-Signal Circuit Design 2.2 Circuits In this section we discuss the implementation of the S/H and discrete analog integrators (DAIs). The focus is on developing equations and block diagrams for the circuits that will be useful as building blocks in the coming chapters. It's assumed, in this section, that the reader is familiar with the bottom-plate sampling technique seen in Fig. 2.20 and the associated discussion. 2.2.1 Implementing the 5tH A fully-differential mixed-signal S/H based on the topology seen in Fig. 2.20 is seen below in Fig. 2.39. The sample portion of the SIB occurs when the~! and ~2 switches are closed and the ~3 switches are open. When the ~3 switches are closed the ~! and ~2 switches open and the value of the input signal at this instance is "held" until the next time the ~3 switches are closed. We can determine the relationship between the input of the S/B and its output by writing the charge stored on C, when the ~! and ~2 switches are closed (the ~3 switches are open) as (2.57) where Vas is the offset voltage of the op-amp. When the op-amp is in the follower configuration, the ~! switches are closed, and the input/output voltages of the op-amp go to VeM ± Vas (assuming infinite op-amp gain). When the 1, 000. We can write this equation in a more useful form as AOLDC> VDD. ResolutIon (2.63) We can estimate the required op-amp gain-bandwidth product (unity-gain frequency ~m) Aowcf3dB' for a SIH by substituting Eq. (2.59) into Eq. (2.60) with ~ = I (noting that this assumes the op-amp doesn't experience slew-rate limitations and its response is first-order) ACL = --'==- 1+j. (2.64) or ACL '" ---'---::: I +j . --"-- (2.65) This first-order system has a time-domain response given by VallI == VinCI e-I.21t f,m) For a given resolution we can write Resolution (2.66) (2.67) If the settling time must be faster than half of the sampling clock period Ts (=11fs ), as seen in Fig. 2.40 during ~3' then we can write tsettling < 2is Ts 2 (2.68) The minimum gain-bandwidth product of an op-amp used in a SIH is determined using f,un == A f OLDC' JdB > -is . In (Resolution) rc (2.69) If the VDD in a mixed-signal system is I-V, the desired resolution of the SIH is 1 mV, and the sampling frequency is 100 "NlHz then the unity-gain frequency,fun' must be greater than 210 MHz. If the required DC gain, from Eq. (2.63), is 1,000, then the hdB of the op-amp is 210kHz. Of course, the actual DC gain and fun should be much higher than these minimums. Autozeroing A single-ended version of the SIB in Fig. 2.39 is seen in Fig. 2.41 including the input referred noise, Vi~oise(f), power spectral density (PSD with units of V2/Hz) and op-amp offset voltage. We'll represent the input-referred noise in the time-domain using Vinoise(t). We've already shown in Ex. 2.3, Eqs. (2.57), and (2.58) that this topology "autozeroes" or removes the offset voltage. When the ~I switches are closed the op-amp is in the unity-follower configuration and its inputs move to VC,~f + Vos + Vino/se(t). When the ~J switches close the voltage on the inputs of the op-amp is VCl..f + Vos + Vino/se(tJ)' lJsing Eq. (2.57) we can write, assuming tl "" lJ, (2.70) 58 CMOS Mixed-Signal Circuit Design ~3 Vou! to t I t2 h ~ ~I ~2 ~3 I Figure 2.41 SiH with input-referred offset and noise shown. At a time T/2 later, thc ~3 switches open and the ~I switches close again to sample the input signal and the noise. Writing the charge on CF between t3 and t] +T)2 (2.71 ) Qualitatively, we can see that if the noise is moving slowly (e.g., Flicker noise) it is removed from the output signaL However, fast moving noise isn't subtractcd out during the autozero process. Ultimately the bandwidth of the circuit (say switch resistances and capacitors) and op-amp finite bandwidth limit the frequency content of the noise. To get a quantitative idea for how the autozero process affects noise in the S/H's output signal we can write = vout(t) + Vin(t3) Vinoise(t) - Vinoise(h) for t3 :s; t:S; t3 + Tsl2 (2.72) Focusing on the noise and taking the Fourier Transform of each side of this equation gives Vonoise(f) := Vinoise(f) . (e /2rr!(t-lj) - 1) (2.73) Note that when t is close to t3 the output has little noise. The worst case situation is right before the ~3 switches open at a time t3 +TJ2 (the ~3 switches are on for T)2 seconds). If we look at this worst-case situation only, then (2.74) which is the transfer function of a differentiator, Sec. 1.2.2. Note how it would be straightforward to extend this derivation to any arbitrary time that the ~3 switches are on. Borrowing the results seen in Eq. (1.46) we get a noise transfer function, NTF, of NTF (2.75) This equation is plotted in Fig. 2.42 along with the response of the SIH. Note that at DC (where the op-amp's offset voltage is located) the output of the S/H is noise free. As alluded to earlier, autozeroing works well for reducing the effects of Flicker noise (a low frequency noise that is common in CMOS integrated circuits). Chapter 2 Sampling and Aliasing 59 _.-_._--------------------- i-.".. NOise. Transfer Function ! I I Vono;se = 2 ·Isin 1l I Ts Vlnolse 2 assuming clock signals have I a near 50% duty cycle. ~~.~ Sample-and-hold with T = Ts ) 2 Figure 2.42 The noise transfer function ofa SIH. In the preceding discussion we didn't include the effects of sampling on the output noise spectrum. However, at this point, replicating the noise spectrum at multiples off, and weighting the output noise by the S/H response should be straightforward, Fig. 2.43. Having said this, however, note that if our op-amp's input-referred noise PSD isn't bandlimited to the Nyquist frequency, //2, as it is in Fig. 2.43 then noise will alias into DC to//2 range (the desired range). (a) Bandlimited op-amp input-referred noise spectrum f . After autozero process Desired spectrum Figure 2.43 Example spectrums when 51H in Fig. 2.39 is used. Correlated Double Sampling (CDS) Correlated Double Sampling (CDS) is a name used for describing the autozero process followed by a SIR The S/H in Fig. 2.39 thus employs CDS. Both the input signal and the noise/offset are sampled (double sample). Then the offset/noise is subtracted from the output signal (the correlation) to give an output signal with less noise and ideally no offset. As an example of CDS, Fig. 2.44 shows an input-referred noise signal and offset along with a S/H input and output. The op-amp's input referred offset is about -220 mV and the input-referred noise has a peak-to-peak variation of about 80 mY. (Remember offset and noise are always measured on the output of a circuit and referred back to its input.) While we can see noise in the S/H's output it is clear that it has been reduced. 60 CMOS Mixed-Signal Circuit Design Noise and offset. Figure 2.44 Showing how CDS reduces noise and offset in the SfH in Fig. 2.39. Figure 2.45 shows a S/H that doesn't employ CDS. This topology is used to help ensure the CMFB circuits and biasing in the op-amp are more tolerant to offsets. When the 4>1 switches are on, the inputs of the op-amp are shorted to the common-mode voltage, VeM' and the outputs are shorted together. Note that the op-amp settling time isn't a factor in the design during this hold portion of the S/H process. At this point in time we can write (2.76) When the 4>3 switches turn on, the op-amp moves into the follower configuration and the op-amp inputs move to VCM± Vas. During this time we can write, see Eq. (2.58), (2.77) Since charge must be conserved = V oul V in ± Vas (2.78) 4>2 CF Vin:+:/ _ _-ir---- VOU1 1 +_C_, CF Figure 2.47 Block diagram for the SIH of Fig. 2.46. Example 2.4 Simulate the operation of the data converter S/H building block shown in Fig. 2,46. Assume C1 = CF = 1 pF and Is 100 MHz. The simulation results are shown in Fig. 2,48. The gain, as we would expect, is 2. It may be useful at this point to simulate this circuit with an offset or noise like we did in Ex. 2.3.• Chapter 2 Sampling and Aliasing 63 Figure 2.48 Simulating the SIR seen in Fig. 2.46 with a gain of2. Implementing Subtraction in the SIH We'll see later, when covering Nyquist-rate data converters, that it is useful to implement subtraction in the SiR. Consider what would happen if instead of connecting the bottom plates of the C1 capacitors in Fig. 2.46 to VCM we connect them to VCl+ and VCl_ (see Fig. 2.49). Doing this results in Qt3 = CI' (VCI+ VCM± Vos) (2.85) or, after reviewing Eqs. (2.82) - (2.63) Vou!+ (~ 1+ CCI) • Vjn+ - C • VCI+ F F The differential output voltage is then given by (1 Voul = Vuu/+ Vout = + (2.86) (2.87) Figure 2.49 implementing subtraction in the S/H. 64 CMOS Mixed-Signal Circuit Design Rearranging the block diagram seen in Fig. 2.49 results in the topology seen in Fig. 2.50. Vow Figure 2.50 Block diagram of Fig. 2.49 with bottom plates ofC/ tied toVC/. Example 2.5 Simulate the operation of the SIH shown in Fig. 2.51 i(t; 100 MHz, CF = C1 = I pF, VCl+ = 1.5VCM> and VC1_ is O.5VCM (VCM= 500 mY). Comment on the resulting output. Vin+ VCl+ VCIVin Vout+ Vout- Figure 2.51 S/H used in Ex. 2.5. The simulation results are shown in Fig. 2.52. We only show the situation when we would want to subtract Vc",/2 from the differential input signal. The inputs are fully-differential, swinging around the common-mode voltage of 500 mV with an amplitude of 100 mV (so they swing between 600 mV and 400 mY). The largest differential voltage is 600 mV ~ 400 mV or +200 mV while the smallest differential signal is 400 mV 600 mV or ~200 mV (so the differential signal swings around ground with an amplitude of 200 mY). Reviewing the block diagram in Fig. 2.50 with the values in this problem shows that the circuit takes this input signal, sample-and-holds it, subtract VCM!2 (250 mY) then multiplies it by 2. We've scaled the output in Fig. 2.52 to show that this sequence of events is indeed what is happening. Note that if we were to switch VCl_ and VCI_ we would add VCM!2 to the input signal. • Chapter 2 Sampling and Aliasing 65 V/VootpJNfvoutmJ Ons 50ns lOOns 15005 lOnns 25005 :mOns 350ns 4000s 4500s 500ns Figure 2.52 Simulation results for Ex. 2.5. A Single-Ended to Differential Output SIH Many input signals are single-ended, meaning the (one) input signal swings around VCM• It is desirable in the first stage of the mixed-signal circuit to SIH the signal and then to change it into a fully-differential signal for further processing. A good single-to differential converter will hold the op-amp's input common-mode voltage at VCM for low distortion (important). In order to meet this goal consider the modified, from Fig. 2.46, SIH seen in Fig. 2.53. Again, we can write, (noting the CF capacitors are uncharged when the ~I switches are on) Qi,~.tolal=CI+·(Vin VCMtVOS)+Cf~·(VCM VCMtVOS) (2.88) When the ~l switches turn on the charge on these two input capacitors is Q1 J =2C/.(v2n VCMtVOS) (2.89) noting that the charge on the C[ capacitors (half ofEq. [2.89]) redistributes through the capacitors. The charge on the feedback capacitors is then Q~J 2CF'(Vo!lI-VC~ftVOS) (2.90) Vin+ ~~2-----r----I Cf+ V CM ./ ~. ~2 ;~3 • C~ + :1 _1--_.._---1 I <----'----"'"~I Vout+ ---...>---- VOUI~ Figure 2.53 S/H for single-ended to differential conversion. 66 CMOS Mixed-Signal Circuit Design Equating the redistributed charge through CF and C1 C1+· (Vin+ VCM ± Vos) C F • (VOllf+ - VCM ± Vos) + C1+· (v;+ - VC\f± Vas) (2.91 ) or 1+'2 CF'(VOUf+- VCM± Vos) == C Vin+ (2.92) Assuming C1+ = C1_ and taking the difference in the SIR outputs gives (2.93) Note that this topology doesn't employ correlated double sampling (CDS). Also note that if we model the op-amp's offset with a single voltage source in series with the non-inverting input of the op-amp then one of the inputs will go to VCM + Vos 12 while the other input will go to VCM - Vosl2 (we've just indicated the inputs of the op-amp are at a potential of VCM ± Vos). Rence the factor of two in Eq. (2.93). In other words, if we re-write all of the equations in this chapter by replacing Vas with Vas 12 then the factor of two in Eq. (2.93) will go away. Simulations at CMOSedu.com are invaluable to understanding the operation of the circuits in this chapter. For example, see the simulation for Fig. 2.53. 2.2.3 The Discrete Analog Integrator (DAI) The final sampling circuit we'll discuss in this chapter is an analog building block that we will find useful in implementing our data converters using feedback. The discrete analog integrator, DAI, is shown in Fig. 2.54. The two clocks signals, ~J and ~2' form ; nonoverlapping clock signals. The common mode voltage, VCM ' falls halfway between the mixed-signal system's high- and low-reference voltages (generally VDD and ground). Note that the parasitic capacitance to ground associated with the bottom-plate of C1 is charged back and forth between v] and v2 but doesn't affect the amount of charge transferred to the feedback capacitor, Cr For this reason this DAr is often called a parasitic-insensitive integrator. Table 2.2 shows the various relationships between the possible inputs and outputs for the DAI of Fig. 2.54. Let's derive the input/output relationships for the most general situations where both v] and v2 are the inputs. Table 2.2 Discrete analog integrator (DAI) input/output relationships. Input = VI input and V2 == VCM Chapter 2 Sampling and Aliasing 67 VI V2------------------~ VCM ) n-l n t n-1/2 Vout -1kBottom plate (the plate closest to the substrate) Figure 2.54 Schematic diagram of a discrete analog integrator (DAl). To begin, let's assume the output of the DAr is connected to the op-amp through the ~I switch. When the ~I switches are closed (~l is high) at n 1 (the instance when the switches shut off), the charge stored on C, is (2.94) and the output of the integrator is vout[(n -l)Ts]. When the ~2 switches turn on the charge stored on C1 becomes (2.95) remembering that the op-amp holds its noninverting input terminal at VCM' The difference in these charges, Q2 Ql, is transferred to the op-amp's feedback capacitor resulting in an output voltage change. This change can be written as (vouf[nTs]-vOI/([(n-l)TsDCF== C,(vl[(n l)Ts] v2[(n 1I2)]Ts) (2.96) or writing this equation in the z-domain results in VoutCz)(l-zl)== ~~(VI(Z)'Z-I V2(Z)' (2.97) The transfer function of the DAr with the output connected to the ~I switches is then VOl/f(Z) == (2.98) Similarly, if we connect the output through the ~2 switches (the edges we label n in Fig. 2.54 shift in time by Ts12) we can write QJ = C/(VCM vl[(n 1I2)Ts]) (2.99) Q2 CICVCM - v2[nTs]) (2.100) and 68 CMOS Mixed-Signal Circuit Design (2.101) The transfer function of the DAI with the output connected to the <\12 switches is then _C1.VJ(z), -V2(Z) VOlll(z) - C. 1 __-I 'r ~ (2.102) Note that ifv2(z) VCM , this equation can be written as H(z) = VOl/feZ) •~ vJ(z) CF l-z-J (2.103) which has a frequency response, IH(!)I, shown in Fig. 1.27. Note that the factor C1ICF simply scales the amplitude response. If this factor is unity then the magnitude response, as shown in Fig. 1.27, is 0.5 at 1s12. The Z-1I2 term in the numerator simply modifies the phase response of the DAI (delaying the output by Tsl2 or -180 degrees) and has no effect on the magnitude response. Note that at this point we could discuss the frequency responses of the transfer functions given in Table 2.2. However, we would see that the discussions and results given in Ch.l for the digital integrator would apply to the DAT with little, or no, modifications. Example 2.6 Determine the transfer function of the DAI of Fig. 2.54 without the switches on the output of the op-amp. Reviewing Fig. 2.54 we see that charge is transferred to the feedback capacitor only when the <\12 switches are closed. Therefore, the output only changes states during the time interval when the <\12 switches are closed. The transfer function of the DAI, when no switches are used on the output of the op-amp, is given by Eq. (2.102). Using the <\11 switches simply adds a half clock cycle delay, Z·112 , to the integrator's transfer function (instead of the output changing with the rising edge of <\12' the output changes one-half cycle later on the rising edge of <\11)' • A Note Concerning Block Diagrams As we draw block diagrams describing our modulator topologies in this chapter and the next we often show a circuit like the one shown in Fig. 2.55. The summation, gain, and integrating blocks are implemented with a single switched-capacitor DAI having the transfer function given by Eq. (2.102). The gain, G, of the DAI is set by the ratio of Di_screte analog integrator Figure 2.55 Block diagram of a DAI. Chapter 2 Sampling and Aliasing 69 capacitors as indicated in the figure. It's important to realize that this circuit is entirely analog and is interfaced to, in general, both ADCs (vout[z] is connected to the input of an ADC) and DACs (v2[z] is eonneeted to the output of a DAC). It should be clear from both Fig. 2.S4 and Table 2.2 that many different combinations of discrete analog building bloeks are possible. Figure 2.S6 shows two other possibilities. In part (a) the capacitors used have the same parasitic capacitance on each plate so there is no benefit to using a parasitic insensitive topology. The transfer function of this DAI is VOU1(Z) = C· -J . (V2(Z)- VI (z)) F l-z (2.1 04) noting each input signal sees the same delay, i.e., Z-I when the outputs are connected through CPI controlled switches and delay when no switches or CP2 controlled switches are used. If the integrator inputs must see the same delay and the capacitors available have asymmetric parasitic capacitance, the topology of Fig. 2.S6b can be used. Its transfer function is . (Cll . VI(Z)+ Cn . V2(Z)) Cp CF (2.1OS) noting the input signals can be scaled independently (a useful feature in filter design and discussed further in the next chapter). Fully-Differential DAJ While we've derived the equations governing the operation of the DAI using a single ended topology, in most practical cireuits we'll use fully-differential implementations. The same equations apply to both configurations. Figure 2.S7 shows the schematie for the fully-differential DAI. Note how we keep the bottom plates of the capacitors away from the op-amp's inputs. (a) Figure 2.56 Other fonns of DAIs. 70 CMOS Mixed-Signal Circuit Design V2+ I ;J ~1 Vl+--/ - t:CI T /" VCM ; ~ ::r 'CI ~ VI_--~ V2 CF Vou/ CF VOUI(Z) C1 . v I (z) . z1I2 - V2(Z) CF l-z-1 Figure 2.57 Fully-differential discrete-analog integrator (OAI) implementation. DAI Noise Performance Figure 2.58 shows the DAI with kTIC noise sources shown (see Table 2.1). The mean squared input- referred noise is given by (2.106) in series with both VI and v1. A total of 2kTICI is sampled onto C1 during each clock cycle. If the input signal can swing from VDD to ground (peak value of the input is VDDI2 while the RMS value of this input is VDD!(2.fi ) ), then we can estimate the SNR using VDD/~f 2.fi \ ) SNR = 20 log -;::::===- (2.107) This equation is useful for determining the capacitor values used in a DAI. ~1 Sampled onto C1 when ~l switches close. Sampled onto C1 when ~2 switches close Figure 2.58 Noise performance of the OAI. Chapter 2 Sampling and Aliasing 71 ADDITIONAL READING [l] R. 1. Baker, OvIOS: Circuit Design, Layout, and Simulation, Revised Second Edition, Wiley-IEEE, 2008. ISBN 978-0470229415 [2] c. C. Enz and G. C. Temes, "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlatcd Double Sampling, and Chopper Stabilization," Proceedings of the IEEE, Vol. 84, No. 11, pp. 1584-1614, November 1996. [3] L W. Couch, Modern Communication Systems: Principles and Applications, Prentice-Hall, 1995. ISBN 978-0023252860 QUESTIONS 2.1 Qualitatively, using figures, show how impulse sampling a sinewave can result in an alias of the sampled sinewave at a different frequency. 2.2 Re-sketch 2.12 and 2.13 when decimating by 5. hint: use a counter and some logic to implement the divide by 5 clock divider. 2.3 Explain why returning the output of the S/H reduces the distortion introduced into a signal. What is the cost for the reduced distortion in a practical circuit? 2.4 Sketch the input and output spectmm for the following block diagram. Assume the DC component of the input is 0.5 V while the AC component is a sinewave at 4 MHz with a peak amplitude of 100 mV. Assume the clock frequency is 100 MHz. In Sample and hold (SIB) Sample and hold (SIB) clock Sample and Out hold (SIH) Figure 2.59 Figure used in Question 2.2. 2.5 Repeat Ex. 2.2 with an input sinewave at 30 MHz. 2.6 Re-sketch Fig. 2.22 if the input signal is a sinewave at 10 MHz (no other spectral content). 2.7 Suppose we are interpolating, with K = 8, digital data with!, = 100 MHz. Prior to interpolation what is the frequency range of the desired spectmm? After interpolation what is the frequency range of the desired spectmm? What is the interpolator's output clock rate? 2.8 Verify, with simulations, that the topologies seen in Fig. 2.34 are equivalent. 2.9 Determine the transfer function, and verify with simulations, the behavior of 4 paths of the switched-capacitor topology seen in Fig. 2.36. 72 CMOS Mixed-Signal Circuit Design 2.1 0 In your own words discuss why the ~2 switches are shut off after the ~, switches in the S/H seen in Fig. 2.39. 2.11 Sketch the op-amp's open loop response, both magnitude and phase, specified by Eq. (2.59). 2.12 What is the voltage across CH in Fig. 2.41 in terms of the input-referred offset and noise? Verify your answer with simulations commenting on the deviation of the frequency behavior of the input-referred noise to the frequency response of the voltage across the capacitor. 2.13 Provide a quantitative description of how capacitor mismatch will affect the operation of the StH seen in Fig. 2.46. Verify your descriptions with simulations. 2.14 Is it possible to design a SIH with a gain of 0.57 How can this be done or why can't it be done? Use simulations to verify your answer. 2.15 For the first entry (v, input, v2 = VCM) in Table 2.2 derive the frequency response, magnitude and phase, of the DAr. Use simulations at a few frequencies to verify your derivations. 2.16 Repeat Question 2.15 for the second entry. 2.17 Repeat Question 2.15 for the third entry. 2.18 Does the DAr use CDS? Why or why not? Use simulations to support your answers. Analog Filters Chapter 3 In the last chapter we discussed that analog anti-aliasing filters (AAFs) and reconstruction filters (RCFs) are an important component of a mixed-signal system. While we can perform signal processing and filtering in the digital domain, as seen in Fig. 2.1, AAFs and RCFs are still required in our system. Analog continuous-time filters can be faster (have wider bandwidths) and take up less area than their analog discrete-time (e.g., switched-capacitor) counterparts. However, unlike discrete-time filters, continuous- time filters cannot be fabricated with precise transfer functions and must be tuned. This is especially true if passive resistors and capacitors are used. Each one can have a variation of ± 20%. By using active CMOS integrators in the filter implementations instead of passive elements, we can electrically tune the filters. Also, we can more easily implement higher order filters while minimizing the effects of loading. In this chapter we discuss analog filters made using continuous-time analog integrators (CArs or active-RC integrators), MOSFET-C integrators, trans conductor capacitor (gm-C) integrators, and discrete-time analog integrators (DAIs). Our focus is on practical analog filters for mixed-signal AAFs and RCFs. These filters may have fully-differential inputs and outputs so the common-mode voltage of the op-amp used in the active filter remains constant (important for noise and distortion). Further, inverting a signal using fully-differential topologies is trivial since we simply swap the filter's outputs. Single-ended topologies where the op-amp's common mode voltage can vary, such as Sailen-Key, and topologies that require separate amplifiers to generate an inversion such as Tow-Thomas biquad, are covered in the excellent books by Franco [1] and Schaumann [2]. 3.1 Integrator Building Blocks 3.1.1 Lowpass Filters In order to methodically develop our understanding of CMOS filters, consider the lowpass filter shown in Fig. 3.1. The transfer function of this filter is Voul(J) = _--"'-_ Vin(J) 1 +j(f)RC (3.1) 74 CMOS Mixed-Signal Circuit Design 1m s plane s cr +jro f3dB ~ 2rrRC o f dB -+----'--- 1) in the passband, see Eq. (3.8), we can modifY this equation to read Undesired ~--"---, (3.22) For a higher order filter we would multiply the desired frequency response by the undesired term's (the op-amp's) response for each op-amp used in the circuit. Clearly, this limits the order of the filter (limits the number of op-amps used in a circuit; a first-order filter uses one op-amp, a second-order filter uses two op-amps, etc.). This is especially true if the filter has a passband approaching the h" of the op-amps used. Active-RC SNR Consider the single-ended active-RC filter shown in Fig. 3.11. Let's assume an ideal op-amp with a maximum RMS output voltage of VDDI(2/2). The RMS input-referred noise of the filter, assuming thermal noise dominates over the bandwidth of interest, is simply j kTIC . The filter's SNR can then be written as VDDI(2/2) VDD 2/8 SNR = 20 . log jkTIC = 10 . log kTIC (3.23) Chapter 3 Analog Filters 83 c 1"--"'1 R . VDD V~_-----J+ I VCM Vout /I. VDD ___ _ VDDi2- -- Figure 3.11 Estimating maximum possible SNR of an active-RC filter. The size of the integrating capacitor fundamentally sets the SNR in integrator-based data converters or modulators. But consider the following: the maximum electrical energy stored in the capacitor used in an integrator is !c. ( Maximum electrical energy V~D) 2 (3.24) Equation (3.23) can then be rewritten as \2 !C VDD) . SNR 10 .10 VDD 2/8 == 10 . Iocr 2 ( 2 == 10 .10 Electrical energy (3.25) g kTIC e kT g Thennal energy This equation can also be used to estimate the fundamental dynamic range, DR, of a filter. Practically, DRs approaching 90 dB (IS bits) can be attained using active-RC filters with good polysilicon resistors (to avoid the large nonlinear voltage coefficient associated with diffused or implanted resistors) and linear capacitors. Bandwidths approaching 50 MHz, assuming 500 MHz!.. op-amps are used, can be attained (at, of course, lower DRs). 3.1.3 MOSFET-C Integrators Let's now look at a variation of the active-RC filter where the resistors are replaced with MOSFETs. Figure 3.12 shows a MOSFET-C filter. In order for the MOSFETs to behave as resistors they must remain in the triode region. Using long length devices helps ensure triode operation. Because the MOSFETs are operating as resistors, their speed is not governed directly by their gate-source voltage (overdrive voltage) or channel length. However, the linearity of the MOSFET resistors is still very important, as is the possibility that the MOSFETs will introduce a parasitic pole into the filter's frequency response because of the distributed resistance/capacitance of the channel (Fig. 3.12). For large input signals, the active MOSFET resistors become nonlinear, resulting in filters with DRs ofaround only 40 dB. The bandwidth of the MOSFET-C filters parallels that of the active-RC filters. We might be questioning the usefulness of the MOSFET-C filter with a DR of only 40 dB. Clearly this filter will only find use in data conversion systems using six bits of resolution or less (36 dB DR) or in systems that process continuous-time signals. The big benefit of this filter over the active-RC filter is its ability to be tuned. Tuning the active-RC filter required adding or removing, via switches or fuses, resistors or capacitors in parallel or series with the existing resistors and capacitors. Tuning the MOSFET-C 84 CMOS Mixed-Signal Circuit Design Vtul1e MOSFET-C filter Vin+----' One over the slope of this line is the MOSFETs resistance ~.~--.-~-~-.-~ ) Drain-source voltage Inverted channel resistance Figure 3.12 A first-order MOSFET-C filter. Parasitic channel capacitance filter shown in Fig. 3.12 can be accomplished by adjusting ~une' If we assume long-channel behavior, we can write the resistance of the MOSFETs in terms of VIII"e (assuming the input common-mode voltage of the op-amp is 0) as ~l Rn= / KP \' lv,"", -VmN - (3.26) The current through MI in Fig. 3.12 is Ii";; L • Vin+ = Vin+ KP . . W ( Ulune - V THN - ) Vin+ (3.27) Some improvement in the linearity of the MOSFET resistors, say 10 dB (resulting in a DR of 50 dB), can be achieved by utilizing the fully-balanced signals available in the circuit. Consider replacing MI in Fig. 3.12 with the pair of MOSFETs, MIA and MlB, shown in Fig. 3.13. The resulting current is now -ViR n+ +V-inR- = KP . -WL [ Vin+' (V lune+ nlA niB (3.28) Chapter 3 Analog Filters 85 Vin------....l MIB Figure 3.13 Linearizing MOSFET resistors. Knowing Vin+ = -Vin and letting Vtune current through MIas Vtune+ - Vrune -, we can write the equivalent L . Vin+ . KP· W Vwne (3.29) The result is that the nonlinear behavior of the MOSFET's channel resistance due to the changing drain-source voltage cancels to a first order. Figure 3.14 shows the implementation of a first-order MOSFET-C filter using linearized MOSFETs. Figure 3.14 First-order MOSFET-C filter using linearized MOSFET resistors. Why Use an Active Circuit (an Op-Amp)? Before going any further, let's realize that we can get the exact same frequency performance using a simple resistor/capacitor or MOSFET/capacitor as we get when we use these elements with an op-amp. So, "Why use the op-amp?" The answer to this question comes when we realize that when a capacitive or resistive load is connected to the output of the filter (without an active element), the frequency behavior changes. Using 86 CMOS Mixed-Signal Circuit Design the op-amp allows us to drive an arbitrary (within reason) capacitive or resistive load. Using an active element will also allow us to cascade first-order sections to implement higher order filters. 3.1.4 gm-C (Transconductor-C) Integrators The operational-transconductance amplifiers, aTA, is an amplifier that has only two high-impedance nodes: the amplifier's input and its output. Figure 3.15 shows a schematic symbol, transfer curves, and a possible implementation for an OTA (based on a fully-differential diff-amp). Transconductor-C, or g",-C, filters use a circuit, a transconductor, that provides a linear voltage-current transfer curve. Our aTA in Fig. 3.15 does behave like a transconductor over a portion of the input voltage range but becomes nonlinear for large input voltage differences, Vin+ - Vin-. By increasing the lengths of the NMOS diff-pairs used in the aTA, we can increase the linear common-mode range of the aTA, making it appear as though it were a transconductor. The fundamental problems with increasing the lengths of the diff-pair MOSFETs are the increase in the OTA's input capacitance (affecting the location of the filter's poles and zeroes) and, perhaps more fundamentally, the inherent reduction in the MOSFET's/r- Vin+ Vin ( Vin+ - Vin (a) Schematic symbol of an OTA or transconductor. Vin+ (b) Transfer curves for an OTA. VDD T-=r~ ! '1 ~s;io.ut+ Voul+ r------~ t-- Vin- L--+---'~-"---+--+--- Vout({) Figure 3.29 Implementation of a bilinear transfer function using an integrator. Chapter 3 Analog Filters 97 while the filter's zero is located at !ldB.zero = 2rcG 3 The filter's gain at DC, in all cases, is (3.54) (3.55) Active-RC Implementation The active-RC implementation of the bilinear transfer function is seen in Fig. 3.30. Again, as mentioned earlier, the resulting active-RC transfer function suffers from poor repeatability from one process run to the next. The RC time constants must be tuned, on-chip, with fuses (or switches) and adding/removing resistors or capacitors. Note how the summation is implemented by changing the input/output voltages to currents. The currents are summed at the inputs of the op-amp (which remain, ideally, at the common-mode voltage, VCM)' This is important to note in both the active-RC and switched-capacitor implementations. We won't discuss the implementation of the MOSFET-C-based bilinear transfer function. It should be obvious that replacing the resistors in Fig. 3.30 with MOSFETs or linearized MOSFETs (see Figs. 3_12-3.14) provides a MOSFET-C implementation. RF CI RI Vin+ +~,----- V Olll V in- VVv" - -__--1+ ·-Vout+ RI G =_1_ j I RICF CI G2 =:: RI RF G3 RICI Figure 3.30 Implementation of an active-RC bilinear transfer function filter. Transconductor-C Implementation Figure 3.31 shows the implementation of the bilinear transfer function using transconductor stages. Again, as with the active-RC filter, signals are summed using currents. Summing the currents at the output nodes results in 98 CMOS Mixed-Signal Circuit Design gml ( Vin+ V m ) - gm2 ( Vout+ - Vout ) + V.,,+ Vout+ l/s2C _ Voul+ l/s2Cz 0 l where we know Vout+ = -Vout- and Vin+ = -Vin-. It will be helpful to write ~ I/s2C) IIsC) I/sC) Using this expression, we can write Eq. (3.56) as or finally (VO!lf+ Vout-)' (s(C) + C2)+ gm2) = (Vin+ Vin-)' (gml +sCJ) (3.56) (3.57) (3.58) Vaut+ - VoutVin+ - Vin (3.59) It's important to note that when looking at this equation, the location of the pole and zero can be adjusted by changing each transconductor's gm independently. The ability to adjust one variable in a filter's transfer function and only change the position of a single pole or zero is called orthogonal tuning. G1 = gmd(C) + Cz) Gz gm2 gml Vin+ Vin~ ]---\,_---*---- V out- G3 =gCm)) Figure 3.31 Impiemention ofa bilinear filter using transconductors. Switched-Capacitor implementation The switched-capacitor, SC, implementation of the bilinear filter is seen in Fig. 3.32. This filter is directly derived from the active-RC filter of Fig. 3.30. From Eq. (3.42) we can write R 1 = -1C{' 1 a n d R F = - C{' 1) 'JS 12 'JS (3.60) and so and G3 C 11 (3.61) Note how, in this discrete-time filter, the passband gain is CI3 ICF when the filter is designed for a highpass response (and the filter no longer behaves like a discrete-time filter). The gain at DC in all situations is Cn/Cn. Chapter 3 Analog Filters 99 ~l CMr ' v;n-L- '"-'"--1---<10-- U C121 !' ~:::-i'--..o-- VOUI /'""~---Voul+ Figure 3.32 lmplemention of a bilinear filter using switched capacitors. 3.2.2 The Biquadratic Transfer Function As we briefly indicated in the last section, higher order filters can be implemented by cascading first-order sections. However, because the pole and zero locations in these first-order filters are restricted to real values, the performance of these cascades is poorer than filters with complex pole and zero locations. For example, cascading two identical lowpass filters having hdB frequencies of 1.59 MHz would result in a filter that has an attenuation of 6 dB at 1.59 MHz and a 40 dB/decade roll off at higher frequencies. Using a second-order filter, we can design a filter to have a sharper transition at 1.59 MHz so that the attenuation is less than 6 dB at 1.59 MHz (however, the roll off remains -40 dB/decade). Further, we can use these sections to implement higher order filters using Butterworth, Chebyshev, Elliptic (Cauer), or Bessel responses. The biquadratic, or "biquad" for short, filter transfer function (a ratio of two quadratic equations) is given by Voul 1 Vin S 2 + (2Qnfo)s+(2;ifo) 2 (3.62) where 2rt/o coo. The complex-conjugate poles are located at (3.63) or rt/o, 1(1\12 PhP2 == - Q ±). 2rt/o V.11 ,2Q/ (3.64) 100 CMOS Mixed-Signal Circuit Design In order to move toward the goal of implementing a biquad, consider the block diagram in Fig. 3.33. This block diagram is essentially the cascade of two first-order blocks (as seen in Fig. 3.29) except that instead of feeding the output of the second stage back to its input, we feed it back to the input of the first stage. We can determine the transfer function of this filter by writing Voul' (3.65) or (s Voull + ~' G2 ) =Vin (I +S~3)GI _ Voui GlSGS (3.66) Further, we can relate voWI to the output using Using Eq. (3.66) with Eq. (3.67) gives V out ( i\ Vin (1 +SG3)G 1 • S+ G I G2 - GIGS ) Vout S+ G G 12 . (1 + sG6)GS 4 or III VOUI + GIG4G5(l+SG6)) -_ '1/(I+SG3)G,(l+SG6)G4) Vm 2 "SZ+sG1Gz \ s +SGIG2 Finally, the transfer function of the biquad is given by Voul = s2G IG3G4 G6 +S(GI G3G4 + GIG4 G6)+ G1 G4 Vin S2 +S(G l G2 + G 1G4GSG6 ) + G 1G4 G5 Equating terms in Eqs. (3.62) and (3.70) gives a2 G 1G3G4G6 a1 = G, G3 G4 + G 1G4G6 aO=G 1G4 Q 211./0= G, G2 +G ,G4GSG6 (3.67) (3.68) (3.69) (3.70) (3.71) (3.72) (3.73) (3.74) (21t/d G, G4GS (3.75) Vou!1 Figure 3.33 Implementation of a biquadratic transfer function using two integrators. Chapter 3 Analog Filters 101 Active-RC Implementation Figure 3.34 shows the active-RC implementation of the biquad filter along with the associated design equations. It should be noted that this is the general design schematic. If, for example, a lowpass filter needs to be implemented, the filter can be greatly simplified. Cn Cl2 + + ('------.----1 Rn Voutl V ou tl+ Rl2 + + ('------.----1 Cl2 Cn Vout+ Vout- a 2 = Cn-C-l2CFICn -(00= -2n-[0= - -1- + Cl2 Q Q RFICFl CFlRnCn 1 ao=--~-Rn CFl Rl2 Cn Figure 3.34 Implementation ofthe active-RC biquadratic transfer function filter. Figure 3.35 shows the frequency response, pole-zero locations in the s-plane, and transfer function for a second-order lowpass circuit made using an inductor (L), capacitor (C), and resistor (R). This LRC circuit has the same frequency response shape as a lowpass biquad filter. However, the DC gain of the LRC circuit must be unity while the DC gain of the biquad filter can be set to ao/(2n[0)2 . Note that if the pole quality factor, Q, is greater than 1I.j2 the response will show peaking. Setting Q to 0.707 results in the Butterworth or maximally flat response. 102 CMOS Mixed-Signal Circuit Design /0 =-2.- 2rc!iC Q=*ff Imjro COo zeroes at infinity ----;---"'r-----+ Re,cr s plane s cr +jco I Vout(J) IVin(j) OdB~--~~~4---~ t - : II /rnax =/0' 2Q2 Figure 3.35 Second-order lowpass filter. Example 3.8 Design an LRC circuit with a Q of 0.707 and a cutoff frequency (10) of 1.59 MHz. From Fig. 3.35 we have two equations we need to solve /0 = 1.59 }';{Hz -+ LC = lOx 10-15 and Q 2rc!iC We can set C 100 pF, then L = 100 IlH, and R 1.4l4k (definitely not practical values if the circuit is going to be purely integrated). The response of the resulting LRC circuit is shown in Fig. 3.36. Note how the cutoff frequency is set by the IdS OdS -7dB -l~dB -21 dB -2adB -35dB -42dS -49dB -56dB ·63dB ·lOdS ·77dB 10KHz 100KHz lMH> 40' 20' 3 dB down atio o· -20' - 40 dB/decade -40' O' -80' -100' -120' '140' 10MHz -200' 100MHz Figure 3.36 Second-order magnitude response for the circuit described in Ex. 3.8. Chapter 3 Analog Filters lO3 inductor and capacitor, while the Q of the circuit is set by all three elements (variations in the resistance having the largest effect on the circuit's Q). Higher Q indicates the poles are moving toward the imaginary axis (keeping in mind that a system with right-half plane poles is unstable [oscillates]) and more peaking, Fig. 3.37. • 5 M-+-'-++i-i"+---i--i--i-~ii--- Q +--:---:--:+:+~~~~ ~~~=i=i~#T--Q = 1 Q 0.707 Q = 0.5 Figure 3.37 The effect ofQ on the frequency response of a second-order lowpass filter. Example 3.9 Simulate the design of an active-RC filter that has frequency characteristics similar to Fig. 3.36. Using the basic topology of Fig. 3.34, we see that for a lowpass filter, ClI = Cn 0 and therefore G3 = G6 0. Further 10 = 1.59 MHz = 2rr. I C 'Fl Rn C' Fl R Fl which we shall use to set Rn = RFl = lOk and CFl CFl lO pF. The Q of the filter is given by Q= 2rt/o . RFI CF1 -+ RFI = 7.07 kO. Knowing a 2 = a l = 0, the gain at DC is ao/(2rr/o)2 or RFl/RIl (lIGs), which is I here. The simulation results are shown in Fig. 3.38.• Notice that at DC, when used in the lowpass configuration, the outputs of the first integrator, v outl + and vouil_ , must be equal. If not, the difference is integrated by the second section. As the frequency increases, so does the difference in these voltages. Figure 3.39 shows the second-order bandpass response. Again, as with the second-order lowpass response, the center frequency (resonant frequency) is set by the values of the inductor and capacitor. The Q of the filter indicates how narrow the bandpass response is; higher Q indicates a narrower response. Note how the response eventually rolls off at -20 dB/decade. At low frequencies the capacitor can be thought of as an open (resulting in a first-order RL circuit response), while at high frequencies the inductor can be thought of as an open (resulting in a first-order RC circuit response). 104 CMOS Mixed-Signal Circuit Design OdB -7dB -14dB -21dB -ZOdB -35dB -42dB -49dB -SodB -ti3dB -7UdB -77dB 1KHz 10KHz 100KHz It.tHz 10t.tHz 20' o· -20' -40' -60' -80' -100' -120' -140' -160' -180' -200' 100MHz Figure 3.38 Magnitude and phase responses for the active-RC filter of Ex. 3.9. I -Vow= sliC Vin S2 +s...L + RC fo/Q o dB -+-_ _ _ _'~o(.......")-'_ _ _-----+ Im,iro One zero at infinity and one at the origin --'---'m----';loo- Re,cr 3 dB - .!£Q. X2Q s plane s =cr +jro 20 dB/decade /0 Figure 3.39 Second-order bandpass filter. Example 3.10 Repeat Ex. 3.8 for the bandpass LRC circuit. Again, we can set C = 100 pF and L = 100 /IF. Solving for Q using the equation in Fig. 3.39 results in Q=R/¥ =0.707 RJ~~~~ ~R=707 The simulation results are seen in Fig, 3.40.• Chapter 3 Analog Filters 105 Figure 3.40 Bandpass response of a second-order circuit with a Q of 0.707. Example 3.11 Repeat Ex. 3.10 if the Q is increased to 20. Figure 3.41 shows the simulation results. To attain a Q of20, we use a resistor of 20k with the inductor and capacitor values remaining unchanged.• Figure 3.41 Bandpass response of a second-order circuit with a Q of20. Example 3.12 Use an active-RC filter to implement a filter with the response shown in Fig. 3.41. Let's begin by writing the filter's transfer function Vout Vin Looking at this equation, Eq. (3.62), and Fig. 3.34 we see that a2 = ao = 0 and so Cn. 0 and RlI 00, Further then 106 CMOS Mixed-Signal Circuit Design al = - -C' -ll' - RnCFlCn _1-J Jio - 271: 1 == 1.59 MHz CFIRnCnRn 2n{o 271: . 1.59 MHz Q 20 The passband gain (the maximum gain) occurs atfo and is calculated by replacing s in the transfer function above with j2n{o . It is given by alQ Apassband =:: 271:fo If, again, we set CFl = Cn = 10 pF and Rn = Rn = 10k, we get anfo of 1.59 MHz. Further then, with a Q of 20, we can set RFJ to 200k. Finally, setting the passband gain to unity results in 2n{o al = - - = Cn ~ Cll 0.5pF Q R12 CF1 Cn While these values do result in a biquad with the shape seen in Fig. 3.41, the values are not practical. Redoing the calculations while trying to minimize the component spread gives another possible solution: RI2 = lOOk, CFl 20p, RFI lOOk, Cn = 5p, ClI = 5p, and Rn = lk. The simulation results are seen in 3.42 . • 1KHz 10KHz 100KHz 1MHz 10MHz 120' 100' 80' 60' 40' 20' 0' ,20' ·40' ·60' -liD' -100' 100MHz Figure 3.42 Outputs ofthe biquad of Ex. 35.12 using active-RC elements. Switched-Capacitor Implementation The switched-capacitor implementation of the biquad circuit is shown in Fig. 3.43. Note how this circuit is a simple translation of the active-RC circuit of Fig. 3.34. Again, if the filter designed using this section has a lowpass or bandpass response, it can be simplified. For example, from Figs. 3.35 and 3.39 (the implementation of lowpass and bandpass filters), we see that a2 is zero. This indicates that G6 can be set to zero (removing Cn in Figs. 3.34 or 3.43). The resulting second-order filter response can be written as Vout =:: als+aO Vin s2+e~o)s+(271:1o) SGIG3G4+GIG4 (3.76) Chapter 3 Analog Filters 107 Technically, the filter is no longer biquadratic, so we will refer to it as a second-order filter. 4>1 --:I Cn ! v~ '~~~-4- Voul+ Vout- ·is Gs Cn Cf12 ·is Figure 3.43 Implementing a biquad filter using switched capacitors. The biquad in Fig. 3.43 can look confusing until we start to dissect it. If we understand the topology of Fig. 3.32, we see that the switched-capacitor biquad is nothing more than two bilinear filters connected in cascade. The only difference is that the switched capacitance, Cm' is fed back to the input of the first op-amp to simulate the feedback resistance, Rn , in Fig. 3.34. This circuit, for the general lowpass or bandpass filter implementation, gets much simpler when the unused components are removed. HighQ We have a major concern alluded to in Ex. 3.12 when using either of the topologies of Fig. 3.34 or 3.43 with a large Q. As we saw in this example the capacitor values were within a factor of 4 of each other (20p and 5p) but the resistors used were two orders of magnitude different (lOOk and 1k). This large difference can be traced to, again assuming G6 0, (3.77) This equation shows that RFI has the largest direct dependence on Q. Using a large value of RFI results in a smaller feedback signal (a smaller amount of current is fed back to the input of the first op-amp). In other words G2 in Fig. 3.33 is small. 108 CMOS Mixed-Signal Circuit Design In order to minimize the amount of signal, V QutP fed back and summed with the input signal, while at the same time forcing the components to have similar values, consider the modified, from Fig. 3.33, biquad block diagram shown in Fig. 3.44. All we have done here is added a separate signal path in parallel with the G2 path. Instead of subtracting, though, we are now adding the signal to the input summing block. Equation (3.70) can be rewritten, assuming G6 is zero (a bandpass or lowpass response), as Voul s(G1G3G4) + Gl G4 Vin s2+SGl(G2-G2Q)+GIG4GS (3.78) or, equating the coefficient of s in the denominator of this equation with the coefficient of s in the denominator ofEq. (3.62), results in (3.79) The implementation of the "high-Q" biquad is seen in Fig. 3.45 (with G6 included). The additional gain from the figure is G2Q=-R-Qn RFi Q-1 (3.80) Rewriting Eq. (3.79) results in 2n/o Q G1G2 Q (3.81 ) Let's use this result in the following example. In VourV> Figure 3.44 Implementation of a "high-Q" biquadratic transfer function. Example 3.13 Repeat Ex. 3.12 using the high-Q circuit of Fig. 3.45. The passband gain is I so we know that OJ ~ Gl= Q = GjG3G4 =G 1(G2 G 2Q)=G=1GQ2 or 2n/o 10 x 106 = GI G2 == lIRFI CF1 . We also know that Chapter 3 Analog Filters 109 and In an attempt to minimize component spread let's set RFI to 5k, Rfl. to 20k, CII to 4p, to 20p, CF] = 20p, Rn = l.25k, and finally RFIQ = 5.25k (roughly). The simulation results and schematic are shown in Fig. 3A6.• RFI CIl :£ j Vin+ RF2 Vout+ ~c--_-++- V(}ut ~=G2' I Q RFI Q_1 Q Figure 3.45 Implementation of the "high-Q" active-RC biquadratic transfer function filter. The bold lines indicate the added components. Example 3.14 Repeat Ex. 3.13 using a switched-capacitor implementation. Assume that the filter is clocked at 100 MHz. To implement the filter, we need to replace the resistors in Fig. 3.46 with switched capacitors. However, we notice in the gain equations that the resistors are all ratios of capacitors. This means we can reduce the size of the filter by scaling the values in Fig. 3.46. In order to do this let's divide all capacitors by 10 and multiply all resistors by 10. Therefore, we can write C'l OAp, CFI 2p, and Cn = 2p. The resistors can be calculated using = RFI 50k-). Cm =. O.2p C/2l'1s 52.5k -). C121Q =. 0.190p 110 5k ~ 5.25k --1 Vin- r -' _ - i CMOS Mixed-Signal Circuit Design 1.25k 20p ~--+H-- Voul+ I.25k 5k 9da-..,.....,..,.....,.,.."---,-,-.~~~~L--,-,-~.,--:-:-,..,..,.,,CT 120' 100' 80' SO· 40' 20' o' '20' .+.l-j.:.,,:i1- -.40' -no' ,..;.; ~.~~:~I- ·80' ·100' Figure 3.46 Bandpass filter discussed in Ex. 3.13. R12 -C !l12-1-s == 200k -+ Cm == 0.05p (!) Rn == C I" == 12.5k -+ Cm == O.Sp 122 'Js Looking at the value of Cm, we see it may be too smaIL Let's change its scale factor from 10 to 4. This means R12 == C I" -= SOk -+ Cm -= 0.125p 112 •J S We have to scale Cn as well (so that G4 remains constant). Now Cn = 5 pF. Chapter 3 Analog Filters III Figure 3.47 shows the implementation of the filter. Note how easy it was to implement the high-Q circuitry. All we did was add two capacitors to the circuit. Also note how the circuit is simplified after removing the unused components (Rn and Cl2 ). ~l 2p (O.16p) Figure 3.47 Switched-capacitor implementation of a high-Q filter; see Ex. 35.14. Again, as in Ex. 3.6, because this circuit can only be simulated using a transient analysis, we will input a sinewave at a known frequency and verify that we get the correct output. Looking at Fig. 3.46, we see that if we apply a I V signal to the filter at 1.59 MHz we should get a 1 V signal out at 1.59 MHz. However, as seen in Fig. 3.48, the filter is unstable and oscillates. Using simulations it's easy to show that even if we ground the inputs of the filter, the outputs oscillate atfo(1.59 MHz). To understand why, remember in Fig. 3.39 that as the Q of the bandpass filter is increased, the poles move closer to the right-half plane. If, for some reason, the poles move into the right-half plane, the filter will t become an oscillator (unstable). It's important to remember that when we designed the filter we approximated our discrete-time variable z as 1 + = I (when f cos "" 1and sin ~; "" ~J). We could be more exact and write z "" c o s2 n-f+ j, j s. m2Isn-f (3.82) which clearly will not follow 1 + ~:for frequencies f approaching the sampling frequency J;. As we discussed in Ch. 2, sampled signals will have spectral content in excess of the sampling frequency. Practically, the spectral content is limited by the combination of the switches "on" resistance and the capacitors in the circuit. 112 Input-_..:.:c:.:~ CMOS Mixed-Signal Circuit Design Output Figure 3.48 Output of the filter in Fig. 3.47 showing instability. Asf gets larger, the cosine term will decrease from one, causing the real portion to get smaller. A decrease in the real component, as seen in the complex plane in Fig. 3.39, causes the pole to move closer to the right-half plane (causing the Q to increase). Practically, the maximum Q we can design for (but not attain) is in the neighborhood of 5. If we redesign the biquad of Fig. 3.47 to have a Q of 5, we see that all we need to change is CII (from O.4p to O.8p) and CI21Q (from O.19p to O.16p). The simulation results are seen in Fig. 3.49. In this figure, we adjusted the input frequency until we reached a 3 dB point (the filter's center frequency was 1.59 MHz, as expected). This occurred at 1.52 MHz and 1.66 MHz. The Q of the circuit is not 5, but is, from Fig. 3.39, 1.59/(1.66 - 1.52) or 11.36.• 0.8V n.sv 0.4V Input O.2V o.ov -,uv Output ·1.llV Figure 3.49 Output ofthe filter in Fig. 3.47 after lowering the Q to maintain stability. Q Peaking and Instability While it would appear the active-RC circuit is the best choice for high-Q filter implementations, we must remember that the discussion neglected the effects of the finite Chapter 3 Analog Filters 113 gain-bandwidth product U;m) of the op-amps. We can model these effects by replacing the ideal integrator gain of lis with l~ 1 s s ( 1+_'_1\ 2tt/un I (3.83) Using this result, we can rewrite the pole locations of Eq. (3.62) (see Eqs. [3.63] and [3.64]) as (3.84) or, looking at a single term, Unwanted ~ (2nf)2 s( l+_2) nS/u_n +Pl=S+Pl 2nJ,.m (3.85) This subtraction results in a shift in the pole toward the right-half plane, increasing the Q of the circuit; Fig. 3.50. Reviewing Eq. (3.64), we can subtract the unwanted term in Eq. (3.85) to estimate the shift in the Q or 2 - n/o-(- 2nf- ) oratf•=10 we can wn•ten/o l( -1 -2-/0) Q 2n/un Q fun (3.86) The shifted Q is then 1 = -Q J2,/.0- ~ QShifl Qshijt lin (3.87) So, for the filter Q to remain finite, we require «I fun Let's use this result in the following example. (3.88) 1m, Poles move towards right-half plane due to finite op-amp gain-bandwidth. The result is an increase in the filter's Q. ' l -------~--~~*_---------~~ splane Re ~ ~ I ~ ~ X Ideal distance is Figure 3.50 Showing Q peaking resulting from the op-amp finite gain bandwidth product. 114 CMOS Mixed-Signal Circuit Design Example 3.15 Resimulate the filter in Ex. 3.13 using op-amps that have anfu" of 100 MHz. The center frequency,lo, of this filter is 1.59 MHz and the Q is 20. Using Eqs. (3.87) and (3.88), we can estimate the increase in Q due to op-amp finite gain-bandwidth product as Q2fo fun 0.636 ---? Qshift 55 Practically, this is too high of a Q (the poles are too close to the right-half plane), and the filter will be unstable (noise in the circuit, or simulation noise in the simulation, will push the poles into the right-half plane). Figure 3.51 shows the simulation results (see also Ex. 3.4). The inputs to the filter are grounded. The unstable oscillation frequency is close to the ideal,lo, but is shifted by a small amount. • Figure 3.51 Showing how the filter of Ex. 3.13 becomes unstable due to finite op-amp bandwidth. Transconductor-C Implementation Let's redraw the bilinear filter in Fig. 3.31 as seen in Fig. 3.52. We redraw it like this to show how the feedback gain, G2, is implemented. In the block diagram of the biquad filter ShO\\* VREF-. When a digital input of 000 is applied to the DAC, the output voltage becomes V REF-. When the input code is increased to 001, the output of the DAC (an analog voltage defined at discrete amplitude levels) increases by one least significant bit (LSB). If the DAC has an input code with a number of bits, N, then we can define an LSB as = = 1 LSB .:.....!-"""-'--:-~c..=- VLSB for N? 2 (4.1 ) If, for example, VREF+ 1.25 V and V REF- 0.25 V and N = 3, then our LSB, the vertical distance between adjacent points in Fig. 4.1, is 0.125 V. Note that in our discussion of an ideal DAC we are assuming that the output of the DAC ranges from VREF- up to V REF+ - 1 LSB. We could just as easily have assumed that the output ranged from V REF- + I LSB up to V REF+. The important thing to notice is that the DAC output range is 1 LSB smaller than the difference between the positive and negative reference voltages. For the DAC developed in this chapter, we will assume VREF+ = VDD = 1.0 V and VREF- 0 V. Selection of the power supply rails, which are noise free in a SPICE 120 CMOS Mixed-Signal Circuit Design VREF+ VREF 1 VRE~ 8/8 VREF+ - 1 ~~ 7/8 6/8 • 5/8 • 4/8 • -J-_" I LSB 3/8 2/8 • 118 .'" VRE~ 0 II 000 001 010 011 100 101 IJO III bO----1 1 - - - - - - VOUT Figure 4.1 An idea13-bit DAC simulation, allow the maximum output range for the DAC (assuming the reference voltages are indeed the maximum and minimum voltages in the system, i.e., no charge pumps or external, larger, power supply voltages). Ifwe need more resolution when using our ideal DAC, we will simply increase the number of bits, N, used and thus decrease the value of the DAC's LSB. SPICE Modeling the Ideal DAC We can write the output of the ideal DAC in terms of the reference voltages and digital input codes b" (which are logic "0" or "I "), and assuming that an input code of all zeroes results in an output voltage of VREF-, as Y 22 VOUT (VREF+ - V REF-)· ( bl"l-l + bN-2 + ... + bl 21"1-1 + bo) 2N + V REF- (4.2) or Chapter 4 Digital Filters 121 = TrJO" UT (VREF+ VRE)F-' 21N ' (bN-I 2N- 1 + b N-2 2N- 2 + ... + b l ' ~')1 + b0) + VREF- (4.3) We can implement this equation, in SPICE, using a nonlinear dependent source (a B source). For a 3-bit, ideal DAC, the statement that implements this equation may look like *Nonlinear dependent source, B, for generating the 3-bit DAC output Boul Voul 0 V=( (v(vrefp)-v(vrefm »/B)*(v(B2L)*4+v(B1 L)*2+v(BOL))+v(vrefm) The terms BXL correspond to logic signals that have a value of I V or 0 V. Example 4.1 Write the nonlinear dependent SPICE source statement for an ideal 12-bit DAC. The statement follows: Bout Voul 0 V=«v(vrefp)-v(vrefm»/4096)* +(v(B11 L)*204B)+v(B1 OL)*1 024+v(B9L)*512+v(BBL)*256+ +v(B7L)*12B+v(B6L)*64+v(85L)*32+v(B4L)*16+v(B3L)*B+ +v(B2L)*4+v(B1L}*2+v(BOL))+v(vrefm) remembering that a "+" in the first column of a line indicates that the text on the remainder of the line behaves as if it were typed at the end of the previous line. It doesn't indicate addition.• The next thing we need to concern ourselves with is the digital logic levels. We want to use our ideal DAC with real circuits where the logic voltage levels may not be well defined. We need to determine and use a switehing-point voltage based on the power-supply voltage VDD. We will assume the input logic code is a valid logic "1 II if its amplitude is greater than VDDI2 and a logic "0" if its amplitude is less than VDDI2. The switch implementation used to generate the logic signals (l V and 0 V) used in our dependent source from real signals is shown in Fig. 4.2. VDD blP 1;OOMEG ~ lOOMEG ~ IV CI.'" wh", B"> 1<], _) BX is the logic input with a, possibly, poorly defined amplitude. -----:::;:.;..:.. ( Close4. \V~en BX; < triQ v Figure 4.2 Generating logic levels using voltage-controlled switches. 4.1.2 The Ideal ADC The characteristics of our ideal ADC are shown in Fig. 4.3. Notice that the transfer curve is shifted to the left. If we were to flip the curve on its side and mark, with black dots, the intersection of the analog input voltage with the ADC transfer curve, we would have the DAC transfer curve of Fig. 4.1. Again, 1 LSB is given by Eq. (4.1). Notice how 122 CMOS Mixed-Signal Circuit Design converting a (normalized) input voltage of 0.1 V will result in an output code of 000 which is the same output code resulting from converting 0 V. Unlike the ideal DAC, the ideal ADC quantizes its input with the practical result of adding noise to the input signal. This noise is called quantization noise. Digital output code, b2 b 1bo I LSB ~ 111 110 101 100 011 010 001 000 ~O V REF- 1/8 2/8 3/8 4/8 5/8 6/8 7/8~8/8 Analog input voltage "" VREF+ -1 LSB 1 - - - - - bo Figure 4.3 An ideal 3-bit ADC. The implementation of the ideal ADC consists of an ideal S/H followed by passing the output ofthe S/H (the held signal) through an algorithm to generate the output bits. The algorithm we use is based on a pipeline ADC and follows: 1. The input signal is sampled and held. 2. This held signal is input to a comparator that compares the input value to a reference voltage. 3. If the input signal is greater than the reference voltage, the output bit is set to a high, and the reference signal is subtracted from the input. The difference is multiplied by two and passed to the output of the stage. Chapter 4 Digital Filters 123 4. If the input signal is less than the reference voltage, the output bit is set low. The input signal is multiplied by two and passed to the output of the stage. 5. This output is used as the input to the next stage and steps 2, 3, and 4 above are repeated. This continues for N stages (where N is the number of bits in the ADC). The reference voltage, or common mode voltage VCM ' can be determined by calculating the midpoint between VREF+ and V REF- followed by subtracting so that the VCM is referenced to 0 V. This can be written as = VCM VREF+ +2 V REF -t V CA10 = VREF+ +2 V REF - V REF- (4.4) We also want to level-shift the input signal so that it is referenced to 0 V. In addition, we want to shift the transfer curves to the left by 112 LSB as seen in Fig. 4.3. In order to do this we use the following SPICE statement (for an 8-bit ADC where V(OUTSH) is the output voltage of the ideal SIH [the input to the pipeline algorithm above]) • Level shift by VREFM and 112LSB BPIP PIPIN 0 V=V(OUTSH)-V(VREFM)+«V(VREFP)-V(VREFM»12A9) The last term in this statement is 112 LSB, which is given by 112 LSB= ~""-'---"''''-- assuming V REF+ > V REF ~ 0 (4.5) We are level-shifting the input and common-mode voltage because we want to make the model as flexible as possible. For example, we want the ADC model to function if VREF~ = 0.5 V and V REF = 0.25 V. Note that if V REF 0 and V REF+ = VDD, the model can be simplified. 4.1.3 Number Representation Suppose we have an ideal ADC and DAC each with a resolution of 8-bits, a V REF+ = 1 V and a V REF of ground. Using Eq. (4.1) the data converter's LSB is 3.906 mY. The minimum output of the DAC, Fig. 4.1, is ground and the maximum output is VDD 1 LSB or 0.9961 V. An input sinewave swinging from ground to VDD and centered around the common-mode voltage, VCM ' of 500 mV is seen in Fig. 4.4. Also seen are the corresponding digital codes and voltages. This number format is referred to as binary offset format. The output of our ideal ADC and the input of our ideal DAC are in this format. A more useful format, for adding and subtracting digital numbers, is the two's complement format, Fig. 4.5. We get this format by complementing the MSB of a word in 1111 1111 (0.9961 V) (255) 1000 0000 (0.5 V) ---f-----'r-~ (128) time 0000 0000 (0 V) - (0) Figure 4.4 Representing a sinusoid in binary offset format. 124 CMOS Mixed-Signal Circuit Design 0111 1111 (0.9961 V) (+127) 0000 0000 (0.5 V) --f---~---f------>,;------'--ld~'-r':;':'::"ti-m-e~ 1111 1111 (0.496IV/T (-1) 7 1000 0000 (0 V) VCM 128· VLSB (-128) Figure 4.5 Representing a sinusoid in two's complement format. binary offset (and thus to go back-and-forth between two's complement and binary offset we simply complement the MSB). Note, in Fig. 4.5, that -] is represented using 1111 1111, -2 is represented using 1111 1110, etc. Also note that the MSB corresponds to the word's sign-bit. An MSB of 0 indicates a positive value (or the common-mode voltage, VCM> 0000 0000) while an MSB of 1 indicates a negative value (a code or voltage below VCM)' Increasing Word Size (Extending the Sign-Bit) Often as we design digital filters we'll need to increase the word size to increase the resolution of the signal or to avoid register overflow. Figure 4.6 shows how we would increase the binary offset representation of the output of a 3-bit ADC to 8-bits while changing the format to two's complement representation. The MSB of the ADC's output is extended and inverted. Notice what would happen if our ADC's input signal were VCM' The ADC's output is then 100. This is changed into 0000 0000. The common-mode signal, as seen in Fig. 4.5, can be thought of as a reference, or zero, level. Since we'll be using two's complement numbers throughout the rest of the book the reader should spend some time reviewing, and ensuring they understand, Figs. 4.4, 4.5, and 4.6. ;l Ideal - - - - - I 3-bit ADC felk I ADC Output 000 (0) 001 (I) 010 (2) 011 (3) 100 (4) 101 (5) 110 (6) 111 (7) After extension 1111 1100 (-4) 11111101(-3) Ill! 1110 (-2) 11111111 (-1) 0000 0000 (O) 0000 0001 (1 ) 000000 10 (2) 0000 DOll (3) ADC Output Two's complement word is binary offset with sign extension Figure 4.6 Showing how to change the output of an ADC to two's complement and how to extend the sign bit. Chapter 4 Digital Filters 125 Example 4.2 Show how to convert a I-bit binary offset number into 2-bit and 4-bit two's complement numbers. A I-bit binary offset number has values of 0 or I (common for the output of a noise-shaping ADC). To change this into a 2-bit two's complement number we'll represent 0 as -I and I as +I or O~II(-I) 1~01(+1) For 4-bit representations we can write 0 ~ 1111 (-I) and I ~ 0001 1) . We'll use these results frequently when discussing noise-shaping (delta-sigma) data converters. • A comparator is an example of an ADC (or quantizer) that will generate the I-bit number used in this example. Reviewing Eq. (4.1) we see that this equation doesn't work for determining the LSB of a I-bit ADC. We can modify Eq. (4.1) for this situation 1 LSB VREF+ - VREF "" VLSB for N 1 (4.6) Adding Numbers and Overflow Figure 4.7 shows how two's complement numbers are added. Note that the first thing we do, when adding two digital signals, is to extend our sign bit to avoid harmful overflow (see the allowable overflow examples in the figure). This increases the word size and allows the final output word size to always be large enough to accommodate the sum of the inputs. Note that this is important. In filters employing feedback, like the digital integrator seen in Fig. 1.26, we may increase the word size even more to avoid, or delay, harmful overflow. For an integrator a DC input will always, after some time, result in overflow (unless the integrator's input is always zeroes). Also note that harmful overflow is easy to detect since it will only occur when the two inputs are the same polarity (positive or negative). If the MSB of the two input words is a 0 (I) then the output word's MSB must be 0 (l) . If it's a I (0) then we know overflow occurred. In simpler terms, if the two inputs are positive (negative) then the output must be positive (negative). Adding two's complement numbers A (3-bits) ---'---3I>---l 1-----"...... (4-bits) B (3-bits) , -'--i--)-----' Extend the sign-bit A 0011 (+3) 1100(-4) 1111(-1) 0011 (+3) 0001 (1) 0011 1100 (-4) 0001 (+ 1) Illl (-1) 1100 (-4) Out (A+B) 0110 (+6) 1000 (-8) OF! 0000 (0) OF! 0110 (+2) 1101 (-3) 1100 + 1100 VOOO (-8) 1111 +0001 ~1 0000 (0) Overflow (OF!), toss into the bit bucket (ignore). Figure 4.7 Showing how two's complement numbers are added. 126 CMOS Mixed-Signal Circuit Design Subtracting Numbers in Two's Complement Format Figure 4.8 shows how two's complement numbers are subtracted. Here we are subtracting the input B from the input A. In order to do this we complement B (run the N-bit word through N inverters). We then tie the carry input of the adder high. Shown in Fig. 4.8 are several examples of subtraction. Note, again, how we extended the sign bit to ensure no harmful overflow occurs. Subtracting two's complement numbers A (3-bits) --'--:-~---I B (3-bits) -:...,~.-~~~ , Extend the sign-bit Invert the word we are subtracting A 0011 (+3) 1100(-4) 1111(-1) 0011 (+3) 0010 (+2) B 1100(-4) 1100 (-4) 0001 (+1) 1111 (-1) 0001 (+1) B+ 1 0100 (+4) 0100 (+4) 1111 (-1) 0001 (+1) 1111(-1) Out {A-B) 0111 (+7) 0000 (0) OF! 1110 (-2) OF! 0100 (+4) 0001 (-1) Figure 4.8 Showing how two's complement numbers are subtracted. 4.2 Sine-Shaped Digital Filters Perhaps the most useful digital filters that we'll encounter when doing mixed-signal circuit design have Sine-shaped responses. Let's start this section by discussing one ofthe simplest of these filters. 4.2.1 The Counter Figure 4.9 shows how a counter can be used as a digital filter with a I-bit input. If we assume the clock frequency is Is (= IIT,) and the counter is read out and reset every KTs seconds then a constant input of Os (-1 in two's complement, see Fig. 6.3» will result in a counter output of 0 (-K) at the end of the time interval KTs seconds. A constant input of logic Is results in a counter output of K. An input of alternating Is and Os (the input is a 50% duty cycle squarewave with a frequency ofls 12) results in an output of KI2 (0 for two's complement numbers). The output of the counter is related to its inputs using K-H y[Ki· Tsl = L x[n· TsJ n=K(i-l ) (4.7) This equation simply indicates that we are taking K inputs, adding them together, and the result is the output of the filter (so we can think of this filter, like any lowpass filter, as an averaging filter). Rewriting Eq. (4.7) in the z-domain, U(_) 11'L. Y(z) X(z) K-J Lz-n=l+z-1 =0 + ... +Zl-K (4.8) Chapter 4 Digital Filters 127 I-bitinp x[nTs) Input clo"":"--:=-=_ _ _--i j,...fl.IUL Counter , - _ - , y[Ki· Ts] h Y - K-bits Output fslK Reset every K clock cycles so counter can count from 0 to K. :Figure 4.9 Using the counter as a digital filter. H(z) ~1 ·(-II+z-1 l-z-1 + ... (4.9) The transfer function for the counter is then H(z) = I-z-K 1-z-I (4.10) We'll see this equation frequently so let's spend some time on it. Note that the counter employs decimation, see Sec. 2.1.2, since the input word rate is K times faster than the output word rate. More on this in a moment (since aliasing will be a concern). The magnitude of the frequency response ofEq. (4.10) is given by IH(j) I . (K sm 1t 'Xi\), (4.11 ) Sine(1t¥) 1tf;) IH(j)I=K. Sine ( (4.12) Figure 4.10 shows the frequency response of the counter (see, also, Fig. 2.29). Note that for large K and small frequencies this equation can be approximated using (4.13) Figures 2.30 and 2.31 in Ch. 2 relate the amount of attenuation and droop we can expect from a Sinc response filter for various values of K. Again, these equations can be used to characterize all of the Sinc filters in this section. Note, again, if we input a DC value of constant 1s then the counter's output is K (see Fig. 4.10). If our input is 101010... or 11001100... or 111000111000 etc. then the counter output is K/2. However, looking at the filter response seen in 4.10 and knowing an input of 10 10 lOis a squarewave with a frequency off)2, we would expect the counter's 128 CMOS Mixed-Signal Circuit Design /H(f)/ A K See Fig. 2.30 /H(f)/ Sinc(Kn .f,) sinin· L) " Is K~ K ••• KK 2K Counter's output word rate Figure 4.10 Frequency response of a Sine-shaped digital filter. output to be zero (and it is if we think in terms of two's complement numbers). However, let's look at the operation in terms of binary offset numbers. Let's assume K is 8 and the counter is clocked at a frequency of 100 MHz. The I-bit word rate coming into the counter is at 100 MHz while the counter is read out every 12.5 MHz (decimation by 8). Figure 4.11a shows the frequency response of the counter and the first-harmonic of the input of 1010101... or a squarewave at 50 MHz. We only concern ourselves with the first harmonic of the squarewave to keep the figures from getting too cluttered. A sinewave at 50 MHz, see Eqs. (1.85), having a peak-to-peak amplitude of I, or a peak amplitude of 0.5, is represented at ± 50 MHz with dirac-delta functions having amplitudes of 0.25. Figure 4.11 b shows the input signal spectrum after resampling at the output rate of 12.5 MHz (note the aliasing of the sampled signal at DC). In (c) we see that after including the counter's Sine-shape response all of the tones disappear except for the aliased tone at DC (and tones at 100 MHz, 200 MHz, etc.) The output of the counter, which is read out as the counter is reset every KTs seconds, (that is we don't look at the output of the counter while it's changing) is a constant value of 4 (that never changes) even though the input is a 50 MHz squarewave. Counter's frequency response (a) Counter's response and input signal. 8 Input, 10101...,50 MHz Input signal 37-5 0.25/ I,MHz (b) Sampled input spectrum 0.5 (c) Counter's output spectrum. 4 Tones at 100, 200, etc. MHz not shown. I,MHz ·~/,MHz Figure 4.11 Showing how decimating using a counter results in aliasing. Chapter 4 Digital Filters 129 Using a counter as a digital filter, as we've just seen, has limited uses because of the significant amount of aliasing that occurs with the inherent decimation. Note that we didn't discuss problems that occur when the input signal contains noise. One of the counter's uses, however, is in applications where the desired signal is constant (DC) such as some sensing applications. By using really large values of K the bandwidth can be shrunk down to limit the effects of noise while at the same time amplifying signals at DC (review Fig. 4.l0). The Accumulate-and-Dump The counter's input was a I-bit word. For N-bit input words the accumulate-and-dump can be used, Fig. 4.12, in place of a counter. The input signal is summed in a register for K clock cycles (note that this is the non-delaying integrator, also known as an accumulator, seen in Fig. 1.26). At the end of this time the sum is clocked into an output hold register and the summing register is reset (the integrator is reset). The equations and filtering behavior of the accumulate-and-dump are exactly the same as the counter. The maximum input word's value is 2N - I (all N bits high). In order to accommodate the summation of K, N-bit, input words the register size used must be at least N + log2K bits wide (rounding up to the nearest integer). The frequency response of the accumulate-and-dump filter or the counter at DC is K. : Accumulator or . non-delaying : integrator Input, N-bits x[nTs]: + }--~--t-~--l Input clockJ1Sl.fL· Is . Dump sum into this register. Res-et-e-v-e-ry-K-=-=c=lo=c=k=-c..r..-:yL=:c.=..le:.=.s:=...~: .>-------!.ls!i-K~4. -.-~ Figure 4.12 The accumulate and dump. 4.2.2 Lowpass Sine Filters Reviewing Eq. (4.10) one may wonder if we could implement this lowpass Sinc-response filter without the decimation inherent in a counter or an accumulate-and-dump. Figure 4.13 shows how cascading a comb filter with an integrator implements Eq. (4.10). Also seen in this figure are several z-plane plots and frequency responses for varying values of K. Note how, to get the lowpass response, we simply cancel the zero at DC (if this doesn't intuitively make sense review Sec. ] .2.3). We'll show that to implement bandpass or highpass Sinc-response filters all we do is cancel a zero using a pole at some other point on the unit circle. Notice in Fig. 4.13 that we've defined the bandwidth of the desired signal (where the droop is -3.9 dB, see Figs. 2.31 or 4.10) using B= 2K (4.14) 130 CMOS Mixed-Signal Circuit Design Integrator, Fig. 1.26 Y(z) Comb filter, Fig. 1.25 IH(f)1 i, Is K=2 'C?v: ••• » fin (Hz) ~ 4 • , , , L087~~~ ••• K=4 Bfsl4 fsl2 3.!s14 : ) I z-plane H(z) = I-z1 K8 ••• H(z) ) Is B Figure 4.13 Lowpass Sine-response filters with varying values ofK. Example 4.3 Assuming an 8-bit input word sketch the implementation of the Sine-shaped filter I _Z-8 l-Z-l What is the output word size? Using SPICE verify that the filter's frequency response is given by Eq. (4.13) with K = 8. Assume]; == 100 MHz. The output of the filter is the sum of K, N-bit, words so the filter's output word size must grow to Output word size == N + log2K (4.15) For this example where K = 8 and the input word size is 8-bits the final output word must grow to II-bits. The filter is sketched in Fig. 4.14. Figure 4.15 shows the filter's input and output when the input frequency is 6.25 MHz (==f,l2K). As seen in Figs. 4.10 and 2.31 the filter's attenuation is -3.9 dB or 0.638. The phase shift is 78.75 degrees (see Eqs. [1.54] and [1.63]).• Chapter 4 Digital Filters 131 Change into two's complement and extend sign bit b L Extend the .. SSfn-bIt by 2 == log2K 1~biCnhaarnygeobffascekt to format. ~ Integrator Figure 4.14 Digital filter sketeh for Ex. 4.3. 810mV 720mV :::::1/::. 36omVr::: 270mV- .......... .. 180mvi-............ : 90mV4... . omv+ Oos i 1000' I 200ns i 300m; I .400ns 500ns Figure 4.15 Input and output of the filter in Fig. 4.14 at a frequeney of6.25 MHz. Example 4.4 Determine, and sketch, the time-domain impulse response of an averaging filter withK= 8. The transfer function of the filter is given by Eq. (4.1 0) or H(z) = 1 I+Z~1+z-2+ l-z + + z·5 The time domain relationship between the input and the output is then y[nTsJ x[nTsJ+x[(n I)TsJ+x[(n-2)TsJ+ ... +x[(n-7)TsJ Note that the output is simply a sum of the inputs over time, KTs' as seen in Eq. (4.7). The time-domain impulse response of the first-order averaging filter is shown in Fig. 4.16. Note the rectangular shape.• x[ n Tsl 1• Impulse input -++-+-1-11-+1""'IH-I-+-I-11-+1""'IH-I-+-I-II-~) time, niTs o y[nTsJ ! o::u; 1 TTTTTTT• • )0 time, niTs o 1 2 3 4 5 6 7 8 9 10 II Figure 4.16 Impulse response of a K = 8 averaging filter. 132 CMOS Mixed-Signal Circuit Design Averaging without Decimation: A Review The counter and the accumulate-and-dump discussed in Sec. 4.2.1 performed averaging and decimation in one stage. In other words, for example with K 4, it summed four input samples, as shown in the sequence below, and passed the result to the output: First output Second output ~---'-----~, ~,-------~, x(l) + x(2) + x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ... (4.16) where the output clocking frequency is, as seen in Fig. 4.9, J.JK. For the lowpass Sinc-response (averaging) filters discussed in this section Finst output x(l) + x(2) + x(3) + x(4) + x(5) +x(6) + x(7) + x(8) + x(9) + ... Second output I , x(l)+ x(2) +x(3) +x(4) + x(5) + x(6)+x(7)+x(8)+ x(9) + ... Third output x(l)+x(2)+ x(3)+x(4)+ x(5)+x(6) + x(7) +x(8) + x(9)+ ... Fourth output ~---~---~ x(1)+x(2)+x(3) + x(4) + x(5)+x(6)+x(7)+x(8)+ x(9)+ ... (4.17) where the outputs of the averaging filter occur at the same rate as the inputs, J,. The z-domain representation of the Sine filter in Fig. 4.13 is the same as the counter or the accumulate-and-dump's transfer function y(nTs) x[nTs]+x[(n-1)Ts]+x[(n-2)Ts]+ ... ~Y(z) X(z)(l+ +z-2+ ... + z 1-K) (4.18) or, again, a filter response given by Eq. (4.10) Cascading Sine Filters The transfer function of a cascade of L of these Sine-response filters can be written as =:-1 1 -KJL H(z) = [ 1 (4.19) nf) IHU)I KL. rSinc(KnfJ ]L _ Sinc( (4.20) The attenuation through a cascade of L Sinc lowpass filters, see Eqs. (2.38) and (2.39) is I !=K Mainlobe First sidelobe L .sinL (1.5n)""L.13dBforK>8 (4.21) "K while the droop at !s/2K, see Fig. 4.17, is TL Droop = [K. sin (2~) ""L· (-3.9) dB for K':2. 8 (4.22) Chapter 4 Digital Filters 133 IH(f)I B = 0.5(1s1K) L ·3.9 dB ~.~~ -" L· 13 dB , fslK 2(fslK) 3(j,1K) f is/(2K) Figure 4.17 General frequency response ofa lowpass Sine (averaging) filter. Example 4.5 Repeat Ex. 4.4 ifanL = 2 averaging filter is used. The transfer function of the filter is J2 H(z) [ I - z-8 = 1 + 2z-1 + l-z-I + 4z-3 + 5z-4 + ... + 3Z-1 2 + 2Z- 13 The time domain relationship is y[nTsl x[nTs]+2x[(n 1)Tsl+3x[(n-2)Tsl+ ... +2x[(n-13)Ts]+x[(n 14)TsJ The impulse response of the L 2 lowpass Sinc filter is shown in Fig. 4.18. Note the triangular shape of the curve and how the impulse response of the L == 2 filter lasts twice as long as the L = 1 filter's response in Fig. 4.16.• y[nTsl 8 ..l-f-t-+--+-+-f-t-+--+-+-f-t--'--'-.-.t~ time, nITs o 1 2 3 4 5 6 7 8 9 101112 13 14 15 16 Figure 4.18 Impulse response of an L = 2 averaging filter with K = 8. Finite and Infinite Impulse Response Filters At this point a short note concerning digital fiIter names is in order. The comb filter seen in Fig. 1.24 (or Fig. 4.14), or the differentiator in Fig. 1.19, is an example of a finite impulse response (FIR) digital filter. Applying a unit amplitude impulse to the input of the comb filter causes the output of the comb filter to go to a 1 at the moment the impulse is applied and a -1 KTs seconds later. The output is zero at all other times. In other words, the impulse response of the filter has a finite duration. The comb filter and differentiator are also called non-recursive filters since their outputs are only a function of their inputs (the output isn't fed back and used in the filter). 134 CMOS Mixed-Signal Circuit Design The integrator (also sometimes called an accumulator) shown in Figs. 1.26, 1.28, and 4.14 is an example of an infinite impulse response (IIR) digital filter. Applying a unit amplitude impulse to the input of the digital integrator, with zeroes the remaining times, causes the output of the integrator to increase to one and remain at one indefinitely. In other words, the output response of the integrator is of infinite duration. The integrator is also called a recursive filter since its current output value is a function of previous output values. Any digital filter with a denominator is a recursive filter. While the averaging filters seen in Figs. 4.13 and 4.14 use an integrator (IIR section) and a comb filter (FIR section), overall, as seen in the previous two examples, it exhibits FIR behavior. Further, since the averaging filter's output is only a function of its inputs, as seen in Eq. (4.17), it is a non-recursive filter. 4.2.3 Bandpass and Highpass Sine Filters So far we've focused on lowpass filters. There are many situations, especially in communication systems, where we may want to filter or perform data conversion on a range of frequencies that doesn't extend from DC to B (= j,/2K). Bandpass ADCs and DACs, for example, are popular in communication systems. In this section, we introduce bandpass and highpass sine-shaped filters. Canceling Zeroes to Create Highpass and Bandpass Filters In Fig. 4.13 we saw that we can generate a lowpass filter by canceling the zero at DC in a comb filter. We can generate a highpass, or differencing, filter by canceling a comb filter zero at is12 , as seen in the example shown in Fig. 4.19 with K 8. The same equations, Eqs. (4.21) and (4.22), can be used to describe the behavior of this filter where, in the highpass response, the main lobe has shifted to j,/2. Also, when looking at Fig. 4.19, remember that the frequency response of a digital filter is periodic with periodIs. l-z-8 ", Z8 -I 8 1 +z-l z7(z+ 1) is14 3j,/8 ••• t Is f fsl2 Figure 4.19 A highpass filter implementation using a comb filter. We can generate a bandpass filter by canceling the zeroes at j,/4 and 3/s14, or some other frequencies, using a digital resonator. The general topology of the bandpass digital filter is shown in Fig. 4.20. Keeping in mind that the digital resonator is used to cancel the zeroes ofthe comb filter, we can write (4.23) Chapter 4 Digital Filters Comb filter In 135 Out Figure 4.20 Implementing a sine-shaped bandpass filter. The time-domain representation of this equation is 2 l21tZJ . y[nTsl = cos y[(n l)Tsl - y[(n 2)Tsl + x[nTsl (4.24) It's desirable to determine at which frequencies the cosine term is an integer, zero, or a value that results in a trivial multiplication, that is, a shift so that we can implement the bandpass filter with trivial multiplications. In other words, we want a filter that uses only delays and additions so that its implementation is simple. The first frequency we will investigate is /s/4. At this frequency the cosine term is zero and the digital-resonator/ comb filter transfer function (the bandpass transfer function in Fig. 4.20) reduces to 1 -K H(z) := -=L 1+z-2 (4.25) The magnitude and z-plane response of this filter, for K 8, is shown in Fig. 4.21. I +z-2 Z8 - I Z6(Z2 + 1) f '\ DC Figure 4.21 A bandpass filter implementation using a comb filter and digital resonator. We can determine the magnitude response of Eq. (4.25) following the same procedure used to determine Eq. (2.38). The result, for the f,/4 resonator, is (4.26) At the center of the passband, that is f,/4, IHU)I = K/2. The ratio of the main lobe to the first side lobe, on either side, is plotted in Fig. 4.22 along with the lowpass Sinc filter response and is calculated using 31t Main lobe IFirst side lobe I = 'K2 .sm. K (4.27) 136 CMOS Mixed-Signal Circuit Design dB Low pass resp?nse 13t 11 T I Main lobe I T First sidelobe 9-1 +7 1 ., Bandpass response when I:: /,/6 orl,./3 Ii;;,dP~' .ttenn.tion whenf =/,/4 st 3I I ~ 3 4 6 8 \0 12 I) 16 K Figure 4.22 Lowpass and bandpass filter attenuation versus number of comb filer zeroes, K. The cosine term in Eq. (4.24) can be set to ±l when 1=Is 16 or 1s13 resulting in a bandpass filter. It should be clear that with the appropriate choice of sampling frequency, number of zeroes K used in the comb filter, and value of the cosine term, many different combinations of simple bandpass filters can be implemented using these techniques. There are, however, only a few resonators that can be implemented using binary numbers. The resonators' coefficients must be such that the poles perfectly lie on the unit circle and cancel the comb filter's zeroes on the unit circle. The ratio of the main lobe to the first sidelobe for 1=1s16 or/,/3 IS given, assuming K = 12,24, ... , by U;) i;) Main lobe I IFirst side lobe - K sin sin ----si-n-=----:: 1.15Ksin (~~)sin (~- (4.28) which is approximately l3.5 dB for K = 24,36,48 ... and 10.15 dB for K = 12, 4.22. In order to increase the amount of attenuation between the main lobe and the first side lobe in a bandpass filter implementation, we can cascade filter sections (as we did in the lowpass filter implementations discussed earlier). For example, cascading five 1s14 bandpass filters with K == 8 will result in an attenuation of 57 dB. Also, note that by changing the sampling, or filter clock frequency J.. , we can easily change the bandpass filter's center frequency. A change in the clock frequency, and its selection, can easily be implemented using a counter and some control logic. Example 4.6 Sketch the block level circuit diagram for an 1s14 digital resonator. From Eq. (4.24) the time domain representation of the 1,/4 resonator can be written as Chapter 4 Digital Filters 137 y[nTsJ = x[nTsJ - y[(n 2)T,J The implementation is shown in Fig. 4.23 .• x[nTsl -+--+--1 I----+---~-.--- y[nTs l H(z) I 1+Z-2 1,/4 resonator Figure 4.23 Implementation ofa digital resonator. Example 4.7 Assuming an 8-bit input word, sketch the implementation of the Sinc-shaped bandpass filter L£: 1+z-2 What is the output word size? Using SPICE verify that the filter's frequency response is given by Eq, (4.26) with K = 8. Assumej~ = 100 MHz. The sketch of the filter is seen in Fig. 4.24 (note the similarity to Fig. 4.14). Again, the word size grows by log2K from the input to the output Here, where K is 8, the word grows 3-bits, to an output word size of II-bits, (I-bit in the comb filter and 2-bits in the resonator). Figure 4.25 shows the output of the resonator when the input is 25 MHz (=J,J4). It can be useful to vary the input frequency and verify that Eq. (4.26) is correct. For example, if we change the input frequency to 12.5 MHz the filter's output is zero (this is the first adjacent zero point in the frequency response). When the input frequency is 15 MHz, the output of the filter is sin (Knf,) sin (8n&) IH(f) I cos (2n:f,) = cos (2nl1~o) - 00.5.588881 = 1 -) 0.25 (scaled by 4) 1 where, since we normalize the filter's output so that passband gain is I (the input equals the output), the output of the filter is 0.25 the input. In the next chapter we'll see that we can throwaway some of the lower bits in the output word since they don't contribute to an increase in the SNR.• Change into two's complement and extend sign bit b . 1. ~ ,, Change back to Extend the SIgn-bit by 2 = \og2 K 1 binary offset format ~ JC" Resonator Figure 4.24 Digital filter sketch for Ex, 4,7. 138 CMOS Mixed-Signal Circuit Design Figure 4.25 Input and output of the filter in Ex. 4.7 at Is14. Frequency Sampling Filters Consider the topology of a comb filter and resonators shown in Fig. 4.26. We are feeding the output of the comb filter through the resonators (with different center frequencies) and then using the combined sum of the resulting bandpass filter responses (the Sinc shapes) to build a bandpass filter. This is exactly the same as reconstructing a waveform in the time domain using an ideal RCF, as discussed in Ch. 2, except now we are using the Digital resonators Comb filter In Out Sinc responses Sidclobes not shown Figure 4.26 A frequency sampling filter. Chapter 4 Digital Filters 139 summation of the frequency domain Sinc responses to generate a bandpass filter with a variable width. Note that every other digital resonator is subtracted rather than added to the final result. This is to account for the phase reversal between adjacent resonator outputs. 4.2.4 Interpolation using Sine Filters We saw back in Sec. 2.1.5 that an interpolator is a circuit that increases the clocking rate of the digital data. This was useful for, among other things, reducing the requirements placed on the reconstruction filter. The simplest interpolator was the input hold register, Fig. 2.28. Before we discuss interpolation using Sine filters let's answer the question "Why can't we use an input hold register for interpolation here?" Examine the block diagram in Fig. 4.27. The ADC is clocked at a rate ofls so the anti-aliasing filter (AAF) limits the ADC's input spectrum to /,/2. On the input of the ADC is a sample-and-hold (SIR) with a Sinc-shaped spectral response (-3.9 dB attenuation at the Nyquist frequency of1s12, see Fig. 2.17). We might expect, based on Fig. 2.29 and the associated discussion, that the hold register seen in Fig. 4.27 would provide an additional Sinc-shaped response in the signal path. Rowever, remember (see Ex. 2.2) repetitively sampling and holding a signal results in only one SIR attenuation. Since the input signal in Fig. 4.27 sees this response when it passes through the SIR it isn't affected by another Sine-shaped response as it passes through the hold register. =/s,new 1-+-'10-- Out Figure 4.27 Interpolation using a hold register (see Sec. 2.1.5). Note that because of this assumption that the data has passed through a SIR and experienced the associated Sinc-shaped filtering, we won't use zeroes padding in the discussions in this section. It should be straightforward to extend the discussions to designs that do use zeroes padding. Also note that if the digital data hasn't passed through a Sinc-response filter then passing it through a hold register, as discussed in Sec. 2.1.5, does introduce a Sinc-response (which, as we'll fmd out now, may often be desirable when performing interpolation). The next question is "Why would we want the signal to see additional filtering?" The answer to this comes from reviewing Fig. 2.26. The image removal filter is an important component of an interpolator. We can implement this filter using JL H(z}= [ _1 _z-_K l-z-l (4.29) 140 CMOS Mixed-Signal Circuit Design The benefit, for an interpolator, comes from realizing that if we clock the comb filter with a slower clock, fJK, then one clock delay is KTs so we can simplify the comb sections using I-z-K -* 1 (4.30) Figure 4.28 shows an interpolator implemented using a cascade of Sinc Filters. The attenuation through the interpolator is given, see Eq. (2.37), by Sinc(K1tf'~"") L IH(/) I == Sinc(1tf,~J (4.31) Larger attenuation can be achieved by cascading more stages, L. Again, the word size grows by I-bit through each comb filter and by log2K - 1 through each integrator. Also note that if we were to use zeroes padding instead of the inherent hold register present in the topology (see discussion on previous page) a selector, see Fig. 2.26, would be added in between the comb filters and integrators to introduce K - 1 zeroes. (it:'" T In I :ot"'or Out d ret')I . Input word rate, Is Output word rate,KIs ==Is.new L sections L sections ... ... ~ / ~ ~~' " ~ /=. : ~ ~ r=Ll.o" ut )~ ~mm Clocked atfs / ,,~~~~_ _ _ _ _ _~/ Clocked at Kfs = is",,,,,,, Figure 4.28 Interpolating using Sine filters for image removaL Example 4.8 Using an 8-bit word, an input clock rate of 12.5 MHz, an input frequency of 1.1 MHz, and K = 8 determine the output word size, magnitude, and output clock rate for interpolators with L = 1 and 2. Also determine the attenuation between the passband and the first sidelobe, see Fig. 2.29. Verify your results with SPICE, The Nyquist frequency is 6.25 MHz (the spectral content on the input of the ADC should be < 6.25 MHz to avoid aliasing). The output clock rate is 100 MHz. For the case when L = 1 the word grows I-bit through the comb filter and 2-bits through the integrators so the output word size is II-bits. When L = 2 the output word size is I4·bits. We'll see in the next chapter that the signal-to-noise ratio sets the number of bits we keep on the output of the filter or in between adjacent stages. Chapter 4 Digital Filters 141 The attenuation through the filter is I . ( J L Smc\Krc1;.new) IH(f)1 = SinircL ) \ /S.Hew Sinc(8rc;o~) L I Sm' e(niOIIO; "" sm. (\.8rc]OIOI ) 8nU100 L =(O.988)L or, for L = 1, - 0.107 dB and for L = 2, 0.214 dB. We can estimate the attenuation between the passband and first sidelobe using information seen in Fig. 2.30. For L = 1 the attenuation is roughly 13 dB and for L = 2 the attenuation is 26 dB. Figure 4.29 shows the simulation results. Looking closely we see that for L the interpolator's output is simply a linear change between adjacent output points. For L 2 we see additional phase shift (more delay through the filter) and a more "rounded" behavior indicating a better representation of the original signaL It can be instructive to vary the input frequency in these simulations and look at the resulting output signals (especially showing how the output signal amplitude drops as the input signal moves closer to the Nyquist frequency of 6.25 MHz). • V{vout_interpolated] L=l 0.2115 0.411S 0.611' 0.8115 1.01ls 1.211s 1.4110 V!vout_no_lnterpotadonl 960mV,---=+=::.::.:::;..:::=::.c..,.--.---,--.--_--, 880mV aOOmV 720mV 640mV 560mV .•. 4BOmV 400mV 320mV 240mV-· 160mV 80mV+---t---i---"r---i---r---i---r--' O.Olls O.2~s 0.411s 0.611s 0.8ps 1.0\10 1.2115 lAps L=2 Figure 4.29 Interpolation using one- and two-stage Sine filters. 142 CMOS Mixed-Signal Circuit Design Additional Control In order to have an additional parameter for adjusting the image removal filter characteristics, Eqs. (4.29) and (4.31), consider adding delay to our comb filter sections as seen in Fig. 4.30. L sections L sections Clocked atis Figure 4.30 General interpolation using Sinc filters. Using this topology we can describe the filter's characteristics using _KM]L H(z) -= [ l-z I Z-I (4.32) and r f \, L SinclKM· n;;:;;:) f,:J IH(f)1 -= Sinc(1t (4.33) Figure 4.31 plots this equation. Note that the Nyquist frequency J/2) remains unchanged since it's set by the sampling in the ADC. By using the factor M we can achieve a narrower bandwidth but at the cost of more droop at the Nyquist frequency. The word size, in this filter, still grows by I-bit in every comb section and by log2K - 1bits in the integrator sections. iH(f)i Desired spe:illJb!lI!._ f) Sinc(Mn . \H(f)1 =. j' smc(n· K-jJ o £ M 2M f h,ne'1' = K .Is lvl Figure 4.31 Frequency response image removal tilter using a Sine interpolator, Fig. 4.30. Cascade ojIntegrators and Combs A quick note before leaving this section. The filters we presented are often labeled CIC filters since they are formed by cascading integrators and comb filters. We'll continue to avoid using this tenn for reasons that will become clear in the next section. Chapter 4 Digital Filters 143 4.2.5 Decimation using Sinc Filters As seen in Fig. 2.12, resampling digital data at a lower frequency (decimation) consists of passing the data through a digital anti-aliasing filter followed by resampling. In this section we discuss using a Sinc filter, (4.10) and (4.12), with a response seen in Fig. 4.1 O. The output word rate of the decimator is I/K and the input desired spectrum is limited to DC tofsl2K (as seen in Fig. 4.10). Notice that, in the filters we've covered so far in this chapter, we've put the comb filter or differentiator before the integrators or resonators. This was to eliminate unwanted overflow problems in the latter (which are recursive filters). After reviewing Fig. 4.28 we might try putting the integrators before the comb filters. While this may work for small signals, or by using very wide registers in the integrators, it would be better to avoid overflow problems altogether. In order to move towards this goal lets write Eq. (4.8) and (4.29) H(z) r = [K~-zl -n =[I+z-1+ + ... +z !-K]L =[(1 + . (1 + z-2) ..... (1 + )Y (1 + . (1 + z-2)L ..... (1 + )L (4.34) or we can implement decimation using only non-recursive averagers (see Fig. 1.16 and the associated discussion). The word size increases by I-bit through each averager. Note that we are assuming the decimation is a factor of 2 here. Figure 4.32 shows the implementation of the decimator. The registers are used to re-sample the data. The higher factors of delay are implemented by clocking the registers with the slower clock (clocking an averager, I +z-I, with a clock of IsIK implements 1 + z-K). This topology is called, by some authors, a CIC filter (see comment at the bottom of previous page) even though there aren't any integrators present in the topology. Figure 4.33 shows example spectrums when using this decimator. Note that the sidelobes alias into the desired spectrum. By increasing the order of the filter L, we can reduce the effects of aliasing. Decimate (reduce word rate) ~ 1 - - o-u+/t-pu-il~ w-o-r-~-~:te,.fsI Input wo-:-r-a-te-,-f,+:-iI')......--I1 K ... K ...~ (1 +Z.-1)L H?out ~ .& K Figure 4.32 Decimation using Sinc anti-aliasing filters. 144 CMOS Mixed-Signal Circuit Design /,/16 /./2 Assuming K = 8 ••• @ (' (a) Input signal spectrum :7 J' -·--------''''''''''----------------'»f (b) Spectrum after AAF (c) \' h~=h~ hn h Notice how the sidelobes alias into the desired spectrum after resampling ••• @/sIK f Figure 4.33 Spectrums when decimating and a Sinc anti-aliasing filter used. Example 4.8 Using an 8-bit word, an input clock rate of 100 MHz, an input frequency of 1.1 MHz, and K == 8 determine the output word size, magnitude, and output clock rate for Sinc-decimators with L 1 and 2. Verify your results with SPICE. The transfer function of the anti-aliasing filter inherent in the decimator is given by Eq. (4.34) with K 8 and L 1 or 2. The output word rate is 12.5 MHz. The simulation results are seen in Fig. 4.34. Note that the decimated output with L 1 looks essentially the same as the output with L = 2 (except for more delay when L 2). This (the shape of the outputs being more or less the same) wasn't the case for the interpolator outputs seen in Fig. 4.29. For the interpolator, where aliasing isn't a concern, increasing L results in a reduction in the aliased signals present on the output of the interpolator. Increasing L allows the interpolator output to move closer to the original input (in the extreme, L ~ ct:), and we get the original analog waveform). By increasing the order, L, in the decimation filter we reduce the aliased signals present in our desired spectrum, Fig. 4.34.• V(vout_no_decimation) Figure 4.34 Decimating by 8, an example. Chapter 4 Digital Filters 145 4.3 Filtering Topologies The Sinc filters discussed in the last section are very useful for general mixed-signal circuit design, especially when interpolating or decimating, since they don't employ complicated multiplications. Unfortunately, they also don't have sharp filtering characteristics and there isn't a lot of flexibility when selecting the filter's frequency response. In this section we'll present some additional filtering topologies mostly based on the integrator. Most of these topologies are directly related to topologies discussed in the last chapter covering analog filters. 4.3.1 FIR Filters Towards understanding the reason for this approach, consider the non-recursive FIR filter topology seen in Fig. 4.35. The transfer function of the filter is H(z)=Ao+A (4.35) If, for example, we set all of the filter's coefficients to 1 then we can write, as seen in Eqs. (4.9) and (4.10), l-z-4 H(z) l-z-I (4.36) or, again, a Sinc-shaped lowpass comb filter. When compared to the comb filters used earlier, Figure 1.24, this topology has more adders. In~_.---I Out Figure 4.35 A four-stage FIR filter. As another example consider setting all of the coefficients to 0.25. This is done by shifting the word left two bits or by extending the sign-bit by two bits. Extending the sign bit increases the word size and ensures we don't lose resolution (but results in more hardware). Figure 4.36 shows the resulting filter's step response. Note the similarity to a first-order RC circuits step response. Also note that the impulse response for this filter simply reveals the filter's coefficients (here all 0.25). Based on a desired step response a heuristic approach can be used to design the filter. The benefits of using FIR filters are that they are inherently stable (they are non recursive so no feedback is used) and they can have linear phase (constant delay). The drawback is that they, for a given number of delays, aren't as good at filtering as the recursive structures we'll talk about in the rest of this section. Unfortunately, recursive structures are subject to instability. In addition, topologies using integrators are subject to overflow. Let's discuss these two issues before going any further. 146 CMOS Mixed-Signal Circuit Design Ao =AI A2 A3 =: 0.25 x[nTs] II .... !!!!!!!! o y[nTs] /t.. 11 •••• 'TT!!!!! o I 2 3 4 5 6 7 8 9 1011 Step input > time, niTs Output ) time,nlTs Figure 4.36 Step response of a 4-stage FIR filter "With all coefficients set to 0.25. 4.3.2 Stability and Overflow A weighted integrating filter is seen in Fig. 4.37. The output of the circuit is fed back to the input after it is multiplied by a. The output of the circuit in the time-domain may be written as y[nTs]=:x[(n-I)Ts]+a·y[(n l)Ts] (4.37) or y[nTs] x[(n 1)Ts] + a· x[(n 2)Ts] + a2 • x[(n 3)Ts] + a3 • x[(n 4)Ts] + ... , (4.38) which will obviously blow up if a> I. X(z) y(nTs) = a .y[(n 1)Ts] + x[(n 1)Ts] Y(z) Y(z) = [aY(z)+X(z)]z-1 U( ) = Y(z) Jl!Z X(z) Figure 4.37 A weighted integrating filter. The z-domain representation ofEq. (4.37) is 1 H(z) =: z-a (4.39) Figure 4.38 shows the z-plane and magnitude plots for this equation. If a > 1 then H(z) becomes unstable. So for a stable system we must require our poles to reside within the unit circle. (There are no restrictions on the location of zeroes.) This sounds simple enough; however, notice that we have, in most of the previously discussed digital filters, placed poles right on the unit circle. If there is rounding in our digital numbers, we could be faced with an unstable digital filter. This would be a very common occurrence in a digital filter implemented using software, if care was not taken to avoid rounding errors. Since we use integer numbers in our hardware implementations, instability shouldn't be a problem unless we start to try to round numbers to decrease hardware complexity (performing divisions or multiplications) without being careful. Chapter 4 Digital Filters H(z) = = _I_ I az-I z-a z-plane 147 IH(f)1 .~ a .. l+a _ ____ I , _ ___ L____ ••• _ ____ _ . ) 1s12 Is 3!s12 f Figure 4.38 The z-plane representation and magnitude response for a weighted integrating filter. Overflow Recall that when we used integrators with comb filters earlier in the chapter we increased the input/output word size of the integrators by log2K 1 while the comb filter outputs increased by I-bit for an overall increase of log2K. We calculated these values by determining the register size required to sum K words. In a recursive filter the output is fed back and summed at various points in the filter, so determining the exact register size required can be challenging. Figure 4.39a shows how an integrator overflows causing the output to wrap around (go from the most positive value to the most negative value or vice-versa). In Fig. 4.39b we show the more desirable situation where the output saturates. This keeps the filter from becoming unstable; however, it will introduce nonlinearities in the filter's response. Nonlinearity at some extreme is usually better than instability. The question is, "How do we determine overflow?" We know that we can't look at the carry out bit because, as we saw in Figs. 4.7 and 4.8, the adder overflowing is a normal occurrence when adding two's complement numbers. What we do know is that if the input sign bits are both 0 then the output sign bit must be 0 (if both inputs are positive then the output must be positive). The same can be said for adding negative numbers. Figure 4.40 shows how we can modify an integrator to avoid overflow. Olill time time OOOOO-!L---------~ 1000 - t--- (a) Integrator overflow lOOO-t- (b) Clamping the output when overflow occurs. Figure 4.39 Integrator overflow and clamping the integrator's output. 148 CMOS Mixed-Signal Circuit Design X(z) - __--i-~ I--I-~-..- Y(z) Figure 4.40 Modifying the integrator to avoid overflow. 4.3.3 The Bilinear Transfer Function The bilinear transfer function and its implementation using an integrator and differentiator were presented back in Sec. 3.2.1. Figure 4.41 shows the digital implementation of the bilinear filter seen in Fig. 3.29. It's important, at this point, to see how the continuous-time implementation in Fig. 3.29 is directly implemented in Fig. 4.41. In particular we note that (4.40) and so The location of the pole is given by _~-'- = _1_ . _1_+_1_'",-,-,-,--,-"",, G2 1+j . --'-- (4.41 ) while the location of the zero is at (4.42) /3dB.zero (4.43) In Integmtor - - . - - . Out . Vout(f) Differentiater Figure 4.41 Digital implementation of the bilinear transfer function. . Chapter 4 Digital Filters 149 Note that in order for our filter to be useful the frequencies of interest must be much lower than the filter's clocking frequency, 1,. In other words, the frequencies where the pole and zero are located must be much less than 1,. This means, assuming G2 1, that GlD« 1 and G)D» I. Let's attempt to simplify this tilter. If we look at the transfer function, Eq. (4.41), we see that the feedback gain, Gz, simply scales the amplitude of the transfer function and can be used to further adjust the location of the filter's pole. Because we can scale the amplitude of the signal either before or after the filter, and independent of the filter's operation, and we can precisely set the pole of the filter using GiD, we ean, without loss of functionality, set G2 to 1. We can then rearrange the summing, delaying, and multiplying blocks, as seen in Fig. 4.43. Using these results we can write the z-domain representation of the transfer function, Eq. (4.41), as VOltt(z) G lD(1 +G 3D ) Z-G3D/(l +GJD) Vin(Z) == z-(l GlD)' z (4.44) Before attempting to simplify the filter implementation seen in Fig. 4.43 further, let's show that, indeed, Eq. (4.44) is equivalent to Eq. (4.41) whenl«f,. It will be helpful to remember that ::::: 1 - §.. if 1 «Is or z "" 1 + §.. "" _1-s "" h h 1h if J? "" 0 (4.45) 1 ·ll (1 -7 where s == jm ==j2rrf. Rewriting Eq. (4.44) in the s-domain results in = Vout(f) Gl~( + G3D) ) G3D/(l + G3D)J Vjn(f) 1+ f, 1+ GlD J's (4.46) 1+ (4.47) 1+ which is clearly the same as Eq. (4.41) when G2 = 1. Example 4.9 Sketch, and determine the transfer function for, the digital filter equivalent of the following RC circuit. Assume the digital filter is clocked at 100 MHz. 10k VOllt(f) 1 1 +jro· lOOns =2" Vin(f) l+jm·50ns Figure 4.42 A simple first-order RC circuit. 150 CMOS Mixed-Signal Circuit Design In Out Out Out Out GlD z-(1 G ID ) Figure 4:43 Simplif}1ng the digital implementation of the bilinear filter. Chapter 4 Digital Filters 151 Comparing the transfer function in Fig. 4,42 to Eq. (4,47), we see that if is = 100 ns -+ G 3D 10 and f =50 ns -+ GlD = 0.2 Gw ' s then we can use any of the filters in Fig. 4.43. The sketch of the digital filter is seen in Fig. 4.44. The multiplication of the transfer function by 112 is nulled by the mUltiplication by GlDG3D 2), To verify that the filter in Fig. 4.44 functions as desired at DC, we see that the output of the first stage is 0.5 when the input is 0.1, and the output of the second stage is 0.05 (with a 0,5 on its input).• t::J0,8 ----"'--- . (1 . 10/11) Figure 4.44 Digital filter from Ex. 4.9. The Canonic Form (or Standard Form) ofa Digital Filter Studying Fig. 4.44, we might wonder if we can further reduce the size of the digital filter. We see in this figure that it may be possible to eliminate the second delay element (which, of course, is a register) and use only a single delay. The result of this modification is seen in Fig. 4.45. Intuitively we would think that the phase response of the filter will change because, now, there is less delay in series with input of the second adder. We can II write the output as - V011- f(Z): G lD G3D + G3D . 1 Vin(Z) G3D 1 Z-l (1- GlD) 1 (4.48) or - VOI- "(Z): G ID (1 + G·3D ) . _z_G-,3:o:D....;/C,-1_+_G_3:.:;D,-) VinCZ) z-(l-GlD) C4.49) which is clearly the same response as derived in Fig. 4.43 or Eq. (4.44) except that the output is one clock cycle, z, earlier. This reduced delay has no effect on the magnitude response of the filter and little effect, assumingf«f" on the phase response of the filter. 152 CMOS Mixed-Signal Circuit Design Out Vout(Z) f-"+--- Figure 4.45 Canonic form of a first-order digital filter. The general form ofthis first-order canonic (or standard form) filter is seen in Fig. 4.46. The filter is termed canonic because the minimum number of delays are used. One delay is used for each pole. Remember that in order for a digital filter to be realizable in hardware there must be fewer or an equal number of zeroes than poles in a filter's transfer function. Change to addition and negate B I ~~ AJ==I-G lD Bo == GlD(l + G3D) Bl =-GlDG3D H(z) = Bo+!i~-I=Bo' ~ z+!!J. I AlZ-I Z-Al Figure 4.46 General canonic form of a first-order digital filter, We can, again, derive the transfer function for the first-order bilinear digital filter. This time, however, let's use the variables in Fig. 4.46. Again, assuming!« Is, and using Eq. (4.45) results in 1+ H(f) = Bo +BI , _ _--"_ I-Al (4.50) where /,(l-A d /3d8,pole =: 2rr (4,51) and Chapter 4 Digital Filters 153 and the gain at DC is ADC (4.53) Example 4.10 Using the canonic form of the first-order digital filter, repeat Ex. 4.9. Comparing Eq. (4.50) with the transfer function in Fig. 4.42, we can write I 2rcj3dB,pole == 50 ns ADC=l=~..:.-;;;;;....!.. 2 I-AI Bo+Bl 1-0.8 ~Bo+Bl 0.1 (I ~~) 2rcj3dB,zero 100 ns =Is· + 100YIHZ(~~) ~ Bo and thus B 1 -0.9. The filter's sketch is seen in Fig. 4.47, We will discuss how to implement the multipliers later. Let's do a quick check to see if the filter functions as desired at DC. If we apply 0.1 to the input of the filter then, according to the transfer function in Fig. 4.42, the output of the filter should be 0.05 or one-half the input. Because the input to the filter is a DC signal, both sides of the delay will have the same value. According to 4.38, this value will be 0.5 (the output of the weighted integrator is 1/[ I 0.8] times the input signal, here 0.1, at DC). The output will then be 0.5 0.45 or 0.05 (as we would expect), • Figure 4.47 Canonic form ()fthe first-order digital filter in Ex. 4.10. Example 4.11 Sketch the digital filter implementation of the lowpass filter in Ex. 3.1 from the last chapter that has a DC gain of 1 and a 3 dB frequency of 1.59 YIHz. Assume the filter is clocked at 100 MHz. The filter's continuous-time frequency response is given by H(j) =----"-- I +j. Using Eqs. (4.50) to (4.53), we begin by calculating AI 154 CMOS Mixed-Signal Circuit Design f3dB,pole 1,59 MHz 10 0M 2n H z( I_ A 1) - ?A 1 09 . and then ADC. = -BIo--+ABII = 1 = -BIo-+0B,9) -? Bo +B) 0.1 Let's put the zero at infinity so it doesn't affect the transfer function +!!J..) f 3dB,zero = 00 2fsn l(1 Bo ~ BoO and B I = 0,1 A sketch of the filter is seen in Fig. 4.48.• Figure 4.48 First-order digital filter in Ex, 4.1 L General Canonic Form ofa Recursive Filter Before leaving this section, let's show in Fig. 4.49 the general form of an nih-order canonic digital filter (where n indicates the number of poles in the transfer function), The z-domain transfer function of the filter is given by m LBjz-i H(z) = --,-i=O-'--n_ _ I LA;[i 1=1 Lm B1Zn-1 i~O zn - Ln Ajzn-j ;=1 (4,54) Ifwe want to write the frequency domain transfer function, we write, again assumingf« Is and using Eq, (4.45), (4.55) or (4,56) While we can design higher-order digital filters using the topology of Fig. 4.49, we will restrict our analysis to first- and second-order filters where hand calculations are relatively easy to perform. Note that we can increase the attenuation of a filter by using several of these sections in cascade, Chapter 4 Digital Filters 155 ••• ••• Number of poles n?: number of zeroes. Figure 4.49 General canonic fonn of a digital filter. 4.3.4 The Biquadratic Transfer Function The digital biquad filter based on the canonic fonn seen in Fig. 4.49 is shown in Fig. 4.50. The transfer function of this filter is ~~~ H(z) Bo + B IZ-I + B2Z-2 BOZ2 + BIZ+B2 l-A1z-1 -A 2z-2 z2 -A Iz-A2 (4.57) Figure 4.50 The digital biquad filter (see Fig. 4.49). 156 CMOS Mixed-Signal Circuit Design In order to translate this transfer function into the frequency domain, we use Eq. (4.45) and assume our frequencies of interest are much less than the sampling frequency (4.58) After some algebraic manipulation we can put this equation in the form seen in Eq. (3.62) ~= Bo . S2 + ';;(2Bo j. +BI)' S +f.l(Bo + BI + B2) s2+!s(2-AI)·s+f?(l-A I A2) ~m where (4.60) 01 .fs(2Bo +Bd (4.61) 00 =f}(Bo+Bl +B2) (4.62) 21Qrlo =.fs(2 - A J) (4.63) and finally, (4.64) Example 4.12 Repeat Ex. 3.8 using the digital biquad clocked at 100 MHz. In this example a lowpass filter is designed withfo 1.59 MHz and Q 0.707. Reviewing Fig. 3.35, we see that for a lowpass filter O 2 and al are zero. This means, in Eq. (4.59), Bo and BI are zero. Further, Q 6 2n· 1.59 x 10 0.707 ~ Al = 1.859 100x 106(2-Ad and Ts) l-AI-A2= 2rr1o ,\2 ( ~A2=-0.869 and finally, because the gain at DC is 1, B2 l-A I -A2=O.OI Note that if a scaling in the amplitude is allowable, we can remove this mUltiplication or approximate it with shifts in the digital word. The simulation results are seen in Fig. 4.51. In order to implement this simulation in SPICE, we used transmission lines for the delay elements and voltage- controlled voltage sources for both the multiplications and the adders. This method allows us to simulate the filter's frequency response. Note that the frequency response is periodic with the filter's clocking frequency.• Chapter 4 Digital Filters 157 Figure 4.51 Simulating the digital filter in Ex. 4.12 Comparing Biquads to Sine-Shaped Filters Consider the frequency response of the Sine-shaped lowpass filter shown in This filter uses a clocking frequency of 100 MHz and a K of 16 or 3 = IH(z) I 1 l-z-1 1 4.52. (4.65) Note the significant droop in the filter's response. It's desirable to design a filter that doesn't have this droop or, even more desirable, contains a small amount of peaking to compensate for a Sinc-shaped attenuation from a SIH, decimation filter, etc. Using (4.59) - (4.64) we can set, for a digital biquad equivalent of this filter, B2 0.03 Al 1.75, A2 = -0.78125 (there are several other solutions, depending on the desired complexity or performance of the filter). The simulation results comparing the Sinc and biquad filters are seen in Fig. 4.53. The transfer function of the biquad filter is H(z) =: ----"'-'-=--"='-- (4.66) The block diagram of the filter is seen in Fig. 4.54. Od!!-,.-_ _~_ _ _-,--_VfY,-.-=• .:!..q--,----~--_n -lOd!! ··· . ',--,---------------,... -~Od!! -SOd!! -BOrlB -IOOdB 20MHz 40MHz 60MHz 8DMHz 100MHz Figure 4.52 Frequency response of a third-order Sinc filter with K = 16. 158 CMOS Mixed-Signal Circuit Design 20dB~----'-"-==~-,-----~- OdB ·20dB .. ·40dB .;·6:0:d:B:r:: :: .. ;." • • ·t·.• • ~~\r ·..l!••.••••!••.•• ·.1'··•.••••••••• -24OdB·l iii 20MH. 40MH. 60MHz 1---- 80MHz IOOMHz Figure 4.53 Comparing a third-order Jowpass Sinc filter to a third-order biquad. In Out \AdjUst as needed to nonnalize output word size. Figure 4.54 The digital biquad filter described by Eq. (4.66). Example 4.13 Redesign the filter in Fig. 4.54 so that the response has a small amount of peaking at 3.125 MHz. Compare, with simulations, the biquad's response to the Sinc filter's response seen in Fig. 4.52. Reviewing Eq. (4.63), we see that to increase the Q we need to increase Aj • Keeping in mind that we want to have simple multiplications relying heavily on shifts, let's try increasing Aj to 1.78125 and Az to 0.8125. The simulation results are seen in Fig. 4.55. In this figure we compare the modified filter response to the response of the Sinc filter. Note that we have a couple of dB peaking in the cascaded biquad filter's output. _ A Comment Concerning Multiplications While discussing the implementation of digital multipliers is outside the scope of this book a comment is in order about simple mUltiplier implementations. While, in some filtering applications, simple shifts can prove very useful, we can implement more useful multipliers using adders. Figure 4.56 shows one possible implementation using a single adder along with the associated multiplication factors. We could implement the coefficients in Ex. 4.13 using a similar scheme. For example, Aj = 1.78125 2 - 0.25 + 0.03125 and A2 = 0.8125 I - 0.25 + 0.0625 (both requiring two adders). Other creative ways can be used to implement multipliers. For example, a multiplication of 0.5625 by cascading two simple mUltipliers with multiplication factors 0.875. Chapter 4 Digital Filters 159 Figure 4.55 Designing a biquad filter with peaking, see Ex. 4.13. B= I 0.5 0.25 0.125 0.0625 0.03125 Multiply by o 0.5 0.75 0.875 0.9375 0.96875 Figure 4.56 A simple multiplier using a single adder. ADDITIONAL READING [1] M. Weeks, Digital Signal Processing Using MATLAB and Wavelets, Infinity Science Press, 2007. ISBN 978-0977858200 [2] T. B. Welch, C. H. G. Wright, M. G. Morrow, Real-Time Digital Signal Processing from Matlab to C with the TMS320C6x DSK, CRC, 2006. ISBN 978-0849373824 [3] S. Haykin and M. Moher, An Introduction to Analog and Digital Communications, Second Edition, John Wiley and Sons, 2006. ISBN 978 0471432227 [4] R. G. Lyons, Understanding Digital Signal Processing, Second Edition, Prentice-Hall, 2004. ISBN 978-0131089891 [5] P. A. Lynn and W. Fuerst, Introductory Digital Signal Processing, Second Edition, John Wiley and Sons, 1998. ISBN 978-0471976318 [6] L. W. Couch, Modern Communication Systems: Principles and Applications, Prentice-Hall, 1995. ISBN 978-0023252860 [7] E. P. Cunningham, Digital Filtering: An Introduction, John Wiley and Sons, 1995. ISBN 978-0471124757 160 CMOS Mixed-Signal Circuit Design QUESTIONS 4.1 If V REF+ 1.0 V and VIII::F_ = 0 regenerate Fig. 4.1 using SPICE. (Design a 3-bit ideal DAC model in SPICE.) The y-axis will be voltages in decimal form. 4.2 If, again, V REF+ = 1.0 V and VII£F_ = 0, sketch Fig. 4.1 for a I-bit DAC. Note that the digital input code will either be a 0 or a I and the analog voltage out of the DAC will be either 0 or 1.0 V. Using Eq. (4.1) what is the voltage value of I LSB? How does this compare to the value of I LSB we get from the sketch? Is Eq. (4.1) valid for a I-bit DAC? Why? The I-bit DAC will be a ubiquitous component in our noise-shaping modulators later in the book (see Fig. 7.15). 4.3 Why do the transfer curves of Fig. 4.3 show a shift of 1/2 LSB to the left? How do we implement this shift in SPICE? 4.4 Use SPICE to implement 4-bit ADC and DAC. If the converters are clocked at 100 MHz (and the outputs of the ADC are connected to the inputs of the DAC), apply an input sinewave (to the ADC) that has an amplitude of 500 mV peak centered around 500 mV DC with a frequency of 5 MHz. Again, use VREF+ 1.0 V and VRI::F_ O. Show the DAC's analog output. 4.5 Using SPICE generate the spectrums of the input and output signals in question 4.4. 4.6 Suppose we think of the I-bit input, 0 or I, in Fig. 4.9 as +1 or -1 (two's complement numbers). What is the output of the digital filter when the input is always O? Is the magnitude response seen in Fig. 4.10 correct? Why? 4.7 Suppose the I-bit input signal seen in Fig. 4.9 is an alternating sequence of 1010 I0... In terms of two's complement numbers, what is the output of the digital filter (what is the output of the counter)? What is the frequency of the input signal? Is the frequency response seen in Fig. 4.10 correct? 4.8 Repeat Ex. 4.3 for a filter with a transfer function of Also, plot the location of the filter's poles and zeroes in the z-plane. 4.9 Repeat question 4.3 for a filter with a transfer function of 4.10 Repeat Ex. 4.5 if L is increased to 3. 4.11 Sketch the impulse response of the filter seen in Fig. 4.19. 4.12 What are the transfer functions of the bandpass filters, indicated in Fig. 4.22, with center frequencies off/6 andf)3? Sketch the frequency responses and the location of their poles and zeroes in the z-plane. 4.13 Simulate, using an ideal 8-bit ADC on the input, and an ideal DAC on the output (calculate the size of the DAC), the operation of the digital resonator seen in Fig. 4.23. Chapter 4 Digital Filters 161 4.14 Qualitatively explain why the desired spectrum of an input signal can't be increased by passing data through an interpolator. Using the simulations given in Ex. 4.8, verify that this is indeed the case. 4.15 In Fig. 4.32, which blocks serve as the AM and which serve as the S/H? 4.16 For the FIR filter seen in Fig. 4.35 with all coefficients set to 0.25, sketch the filter's frequency response. 4.17 For the filter seen in Fig. 4.57 determine the range of values for a and b where the filter will be stable. What is the filter's transfer function? Sketch the location of the filter's poles and zeroes. X(z) Figure 4.57 A weighted integrating filter. 4.18 Repeat Ex. 4.9 for a filter with a transfer function of V 0111 == _I +_j.--'-"':.:.=_ 4.19 Repeat Question 4.18 using the canonic form of the first-order digital filter. 4.20 Repeat Ex. 4.12 if the Q is increased to 1. 4.21 Show that the filter shown in Fig. 4.58 can be implemented using a single multiplier. Figure 4.58 Filter used for question 4.21. 4.22 Show that if the values ofA and B are restricted to 1,0.5,0.25,0.125, etc. that the circuit of Fig. 4.59 can be used to implement multiplication by coefficients that aren't directly powers of two. How would a multiply by 0.75 be implemented? a multiply-by-0.9375? a multiply-by-0.5625? 162 CMOS Mixed-Signal Circuit Design In ----...-~40--~~)_____ Out Figure 4.59 A simple multiplier where A and B simply shift the data. Chapter 5 Data Converter SNR After studying Chs. 1-4 we should understand the sampling process, including analog sampling, decimation, and interpolation, the operation of the ideal ADC and DAC, and the basics of filtering. In this chapter we turn our attention towards quantization noise. Quantization noise is the effective noise added to a signal after it passes through an ADC (aka quantizer), a comparator (a I-bit ADC or quantizer)), or, for digital signals, a circuit that reduces the word size (removes the LSBs of the word). One of the key things we'll focus on is the shape of the quantization noise spectrum and how it's added to the spectrum of an input analog or digital signal. 5.1 Quantization Noise Examine the clocked comparator seen in Fig. 5.1. In this ehapter, like the rest of the book, we'll use a VDD of 1 V and a common-mode voltage, VCM ' of 500 mY. When the input to the comparator, the non-inverting input, is 600 mV then, since the inverting input is held at VCM' the output goes to I V on the rising edge of the clock signal. The difference between the input and output of the comparator is 400 mY. Note that we've gone from an analog signal, the input, to a digital signal, the output. However, while doing this we added noise to our input signal. It's useful to think of this analog-to-digital (quantization) process, from a block diagram point of view, as simply adding noise to our signal. This model is shown in 5.2. Notice that we've assumed that the noise we added to our VDD 1.0 ~ In,analog i Out, digital 5I 0~0m clockv~ Is In 600mV IV 800mV IV 200mV OV 450mV OV 950mV IV Added noise +400mV +200 mV -200 mV -450mV +50mV Figure 5.1 How a comparator adds noise to an input signal. 164 CMOS Mixed-Signal Circuit Design Analog vin_ _ _ _-I Digital I i T Anal~ital 'm VQe(f) (added noise) Figure 5.2 Modeling ADC quantization noise. input signal has a spectrum of VQe( f). Determining the shape and range of this noise spectrum is one of the goals of this chapter. Finally, while a good portion of our studies will focus on the quantization noise introduced during the analog-to-digital process we can also apply the same results when truncating a digital word's size, Fig. 5.3. Nbits " ) N-Fbits ;I ) I fez) ! Drop lower F bits. Nbits VQe(Z) (added noise) Out fez) Out N-Fbits Quantizer Figure 5.3 Quantizing a digital word and modeling the added noise. 5.1.1 Viewing the Quantization Noise Spectrum Using Simulations Consider the simple connection of an ideal 8-bit ADC to an ideal 8-bit DAC seen in Fig. SA. If we apply a 7 MHz sinewave to the ADC with an amplitude of 004 V and an offset of 0.5 V (so the sinewave swings from 100 mV to 900 mY]) and clock the ADC at 100 MHz we get the signals seen in Fig. 5.5. Note that the output of the DAC looks very similar to the output of an ideal SIR (see Fig. 2.14). Now, however, the amplitude of the DAC output signal is quantized, that is, within 1 LSB (= 1.0/256 or 3.906 mY, see Eq. [4.1], for the present simulation) of the ADC input. This quantization is not obvious after looking at Fig. 5.5 (the time domain response). However, looking at the spectrums of the Analog VDD = 1.0 I Vjn Is :I 8-lbr:tO' C I Digital 8 I I VDD l.0 --~ lldelli 8-bItDAC .~ Analog Vout Figure 5.4 Passing a signal through an ADC and then through a DAC. Chapter 5 Data Converter SNR 165 Iclk =Is = 100 MHz Figure 5.5 Seven MHz ADC input and the corresponding DAC output. ADC input and the DAC output reveals the difference in the noise floor between the two, Fig. 5.6. The inherent noise floor in the simulation that is associated with the input signal is approximately -80 dB (0.1 mY, RMS.) The noise floor associated with the DAC's output (the signal + quantization noise) is approximately -70 dB (0.316 mY, RMS). It is desirable to determine what sets this value and its spectral content. Again, note that the ADC quantizes the signal which results in the quantization noise (an ideal S/H and DAC don't introduce quantization noise). fu.\1S -90d~M+H-z--41--TI.!-Ht - - 81 MHz 121 MHz Is 161MHz Figure 5.6 ADC input and output spectrums for Fig. 5.4 with signals seen in Fig. 5.5. Bennett's Criteria In order to characterize the spectral characteristics of the quantization noise let's make the following assumptions (Bennett's criteria) concerning the signal we are converting: 1. The input (to the ADC) signal's amplitude variation falls between VREF+ and VREF- so that no saturation of the digital output code occurs. Exceeding the normal operating range of the ADC affects the quantization noise spectrum by adding spurs or spikes to the output spectrum. 166 CMOS Mixed-Signal Circuit Design 2. The ADC's LSB is much smaller than the input signal amplitude. When this isn't the case, the output of the ADC can appear squarewave-like (when converted back into an analog waveform) and result in a spectrum, once again, that contains spikes or spurs. We'll see later in the book that adding or subtracting a fed-back signal (from the output based on the expected or past quantization noise) to the input modifies this requirement. 3. The input signal is busy (not DC or a low frequency input). We define busy, for the moment, as meaning that no two consecutive outputs of the ADC have the same digital code. For the ideal ADC in Fig. 5.4 1 LSB 3.906 mV and Ts 10 ns so that the input must change at least 3.906 mV every 10 ns. We'll see that adding a high-frequency dither or pseudorandom noise signal to the input, which can be filtered out later (either using a digital filter or when we pass the output through the reconstruction filter), can make the requirement on the input of being busy practical in an actual circuit. We use these assumptions (Bennett'S criteria) in the following discussion unless otherwise indicated. An Important Note It's important to note that simply sampling an input waveform, using a SIH, does not result in quantization noise. The amplitude into the ideal SIH, at the sampling instant, is exactly the same as the amplitude out of the ideal S/H. In order to understand why this is important, consider the test setup shown in Fig. 5.7. If we apply a 3 MHz sinewave centered around the common-mode voltage with a 400 mV amplitude we get the outputs seen in Fig. 5.8. Clearly there is a difference between the SiR's input and its output. However, this difference has nothing to do with noise, an unwanted signal, since passing the output of the SIH, VanIsh' through the ideal reconstruction filter of Fig. 2.19 results in an exact replica of the SIH input Vi" . --~) Vout Figure 5.7 Taking the difference between the SIR input and output. RMS Quantization Noise Voltage If we were to set up a test configuration similar to that shown in Fig. 5.7 (see Fig. 5.9), where the input to the ADC is subtracted from the DAC output, the resulting output waveform would have little to do, in every case, with the quantization noise. This is true when the input to the ADC contains a broad frequency spectrum extending from DC to the Nyquist frequency,J,; = 1/2. However, if we apply a slow linear ramp to this test setup (to limit the input frequency spectrum) we can (1) see the reSUlting quantization noise over a wide frequency spectrum and (2) observe the transfer curve, in the time domain. Note that this input violates Bennett's criteria (which, as we'll see, means the noise power spectral density is flat from DC to the Nyquist frequency). Chapter 5 Data Converter SNR 167 Difference between S/H input and output in Fig. 5.7. S/H input and ...... output in Fig. 5.7. Difference spectrum 31MHz 61MHz 91MHz 121MHz 151MHz 181MHz Figure 5.8 Time-domain difference between S/H input and output along with the spectrum. A section of the input and output, using the test setup of Fig. 5.9, is shown in Fig. 5.lOa. It's important to understand the input/output relationship between the ideal ADC and DAC shown in this figure. (Note that clocking the ADC too slow or putting in a ramp that rises too quickly will distort this waveform.) As an example, when the ADC input is slightly above 482 mY, in this figure, the ADC output code (input to the DAC) changes. The ADC output code can be calculated as 482 mVIl LSB ( 1 LSB 11256 = 3.906 mV for the present simulation) or changing from 123 to 124. Looking at the transfer curves in this figure it appears as though the output changes when the ADC code is 123 or 480.4 }----~Voutd Figure 5.9 Taking the difference between an ADC input and the DAC output. 168 CMOS Mixed-Signal Circuit Design Figure 5.10 Difference between an ADC input and DAC output. mVIl LSB. This, as seen in Fig. 5.lOb and discussed below, results in centering the quantization error around the input. This is the reason we shifted the ADC transfer curves by 1/2 LSB when we developed our ideal ADC model. The difference output, between the two signals of Fig. 5.IOa, is shown in Fig. 5.IOb. Some points to note about this sawtooth waveform are that I) its average value is zero, 2) the waveform contains an abrupt transition (and so we expect a wideband output spectrum similar to that which occurs after sampling a waveform), and 3) its peak-to-peak amplitude is I LSB. Like a sinewave, which also has zero average value, we can characterize this quantization error waveform by looking at its root-mean-square (RMS) value. This value can be calculated using I 1 = ~ T V VQe.RMS (0.5 LSB This value is the RMS quantization noise voltage for a specific data converter. Note that the value of the period for this sawtooth waveform, T , doesn't appear in the evaluated result of this equation. Also note that the sampling frequency, Is ' isn't present in this equation. For our present discussion where I LSB is 3.906 mY, VQe.RNI.S = 1.13 mV or -59 dB (RI\1S). Treating Quantization Noise as a Random Variable If Bennett's criteria hold, then the quantization noise voltage can be thought of as a random variable falling in the range of ±0.5 LSB, as seen in Fig. 5.11. The probability that the quantization error is -0.2 LSB is the same as the probability that the error is 0.4 LSB. In other words, there is no reason why the quantization error should have one value more often than another value. The quantization error noise power is the variance of the probability density function. The RMS quantization error voltage is the square root of the quantization noise power. The variance of the probability density function (the quantization noise power, PQJ is given, knowing the average of the quantization error, Qe, is zero, by Chapter 5 Data Converter SNR 169 Probability density function, p 1I2LSB f p' dQe= 1 -II2LSB J ( -112 LSB 1 LSB = VLSB I ) Qe 112 LSB Figure 5.11 Probability density function for the quantization error in an ADC assuming Bennett's criteria hold. f!l2LSB V2 PQe= p·(Qe)2·dQe= LSB -!l2LSB 12 (5.2) so that, once again, the RMS quantization noise voltage is JT2 = VLSB VQe,RMS (5.3) Again, if our LSB voltage is 3.096 mY, then, once again, VQe,RMS = 1.13 mV or -59 dB (RMS). If we look at Fig. 5.6, we see that the RMS noise voltage varies essentially over the entire spectrum (white noise) and has a value ranging from around -70 dB down to less than -80 dB. Note that although the entire spectrum contains quantization noise it is not because of the sampling process used in the ADC (and so quantization noise doesn't experience aliasing). Quantization noise is added to the signal after the sampling process during the analog-to-digital conversion process. In order to qualitatively understand why the quantization error spectrum is white, in Fig. 5.6, we remember that there are abrupt transitions in the DAC output, and if the quantization error is truly random, the times between the changes have varying periods. We might speculate that by simulating a longer time or using a multiple frequency input so as to "exercise" the ADC, the resulting quantization errors are further randomized and the resulting error spectrum will be flatter than what is seen in Fig. 5.6. 5.1.2 Quantization Noise Voltage Spectral Density If the quantization noise voltage spectrum is truly flat (Bennett's criteria hold) we can determine the noise power spectral density of VQe.RMS, V8e(f) with units of V 21Hz, or the noise voltage spectral density, VQe(f) with units of VI/Hz by solving f V 2 /,12 t~B = 2 V8e(f)· df (SA) o where the factor of 2 accounts for the power in the negative frequencies of the spectrum. Notice that we assumed a spectrum from DC to the Nyquist frequencY,isI2. Assuming all of the quantization noise falls below the Nyquist frequency is the worse-case situation. Solving this equation yields J J = = V e(f) VLSB VREF+ - VREF Q 12!s 2N 12!s (5.5) 170 CMOS Mixed-Signal Circuit Design with units of VI jii;. Note that the quantization noise spectral density is inversely proportional to the sampling frequency. Figure 5.2 shows how we can model the ADC as a summation of the input signal and the quantization noise. After looking at Eq. 5.5 we might think that by simply increasing the sampling frequency we can reduce the amount of quantization noise an ADC introduces into an analog input signal. While increasing the sampling frequency spreads the quantization noise spectral density out over a wider range of frequencies (see Fig. 5.12) with a corresponding reduction in amplitude, the sampling frequency doesn't affect the total RMS quantization noise voltage. However, bandlimiting the spectrum using a filter reduces the amount of quantization noise introduced into an input signal (this is important and the reason mixed-signal design is so powerful). In the simplest case a lowpass filter is used on the output of the ADC to reduce the amount of quantization noise introduced into the signal. We can write the amount of noise introduced into an input signal over a range of frequencies using JIH V~e.RMS = 2 V~e(f) . dl where IL m 0 -To/2 (5.38) The spectrum of the average value of a function can be found by taking the Fourier transform of the autocorrelation function. The result is called the power spectral density function (PSD) and is given by 1 Pin(f) = Rin(t)· e-i2rrjl . dt (units, y2/Hz or y2 . s) (5.39) The power spectral density function of Eq. (5.33) is then, with the help ofEq. (5.38), ~ Piif) ; . [&(f+Jin )+8(f-Jin)] (units, y2/Hz) (5.40) This is simply two impUlses in the frequency spectrum located at ±hn with an amplitude of V;/4 (y2/Hz). The total average power of this signal is given by 184 CMOS Mixed-Signal Circuit Design J J "" cc PAVG = Pin(f)' dJ 2· Pin(f)' dJ (units, V 2/Q or watts) o (5.41) assuming a l-Q (normalized) load, which, for Eq. (5.33), is Vp2 (V2). The voltage spectral density, with units of VI jHz , is simply the square root of Eq. (5.39) (that is, the square root of the PSD Jpin(f) D. The root mean square (R.\1S) voltage of a signal is given by VRMS=JPAVG = 21Pin(f).dJ= !21(voltagespectraldensity)2.dJ (5.42) o ,0 Ii. The RMS value of Eq. (5.33) is simply, as one would expect for a sinewave, Vpl Note the similarity between Eq. (5.42) and Eq. (5.7). Example 5.10 Determine the ACF, PSD, average power, and RMS value of a signal Vet) made up of three sine waves with peak amplitudes of V1 ' V2 , and V3 with frequencies of ft, J;, and J;. Using Eqs. (5.34) and (5.38), the ACF is T -t R(t) = V2 cos 2rrJI t + V2 cos 2rr/2t+ V2 ; cos 2nJ3t (units, V2) The PSD (positive frequencies) is determined using Eqs. (5.39) and (5.40) vi vi vf P(f) 4,o(f-JI)+4·o(j-J2)+4·Us:(J-j3)(um.ts, V 21Hz) The average power, using Eq. (5.41), is PAVG vl + vi + vi 2 Finally, the RMS value of the signal is given by (units, watts) (units, V) Note that if we added phase shifts to OUf signals the results would be the same; the phase shift doesn't change the signal's average value, so we get the same results whether sines or cosines are used in our original spectrum.• Next, suppose that the sinewave specified by Eq. (5.33) is sampled at a rate ofls Vin(nT.,) = Vp sin(2nf;n' nTs) (5.43) The ACF for a sampled signal can be written as 2: . 1 N Rin(nTs) =hm (2V 1) vin(kTs )' vin(kTs + nT.,) N-.oo , + k~-N (5.44) which results in Chapter 5 Data Converter SNR 185 fV2 Rin(nTs) = cos 2n/in . nTs (units, y2) (5.45) The PSD is the Fourier transform of this equation, V2 00 Pin(f) = 4;s k"'foo [8(f-.fin + kfs) + 8(f+/in + kfs)] (5.46) The RMS value of the sampled sinewave, Eq. (5.43), assuming we have passed the signal through an ideal reconstruction filter (RCF) with a bandwidth of fs/2, is simply, once f i . again, Vpl The PSD of the signal, after passing through the RCF, has an amplitude of Vp4 at frequencies of±/;". The Spectral Density ofRandom Signals: An Overview Let's use our jitter discussion of the last section to illustrate how to look at the spectrum of a random signal. We'll do this in two parts: (1) we'll begin by assuming the jitter is a random variable that falls between two limits and has equal probability of lying anywhere in the region (just as was assumed for the quantization error probability density function when calculating the RMS quantization noise voltage in the last chapter), and (2) then assume the jitter has a Gaussian distribution around some average value (the more practical and realistic situation) and determine how the output of the ADC is affected. Consider the representations of clock jitter shown in Fig. 5.20. Trace I in this figure shows the ideal position of the rising edge of a clock signal. This point is represented on the probability density function (PDF), p(t) , at time zero. On the next rising edge of the clock, trace 2, the edge is a little too early and is represented on the PDF as shown. We are assuming, probably incorrectly for most practical situations, that the rising edge of the clock is falling within the peak-to-peak boundaries with the equal probability of being in the correct position (as shown in trace 1) or at the edge of a boundary (as shown in trace 4). We also know that the area under the PDF curve in Fig. Trace : Ideal clock edge position 2~tooearlY 3~toolate 4_...;_ _-'~ at the boundary 5~ Edge close to boundary :< ); Peak-to-peak jitter, t!.Ts p(t) Probability density function, PDF 5 1 34 ~ / ~I o t!.Ts time 2 Figure 5.20 Clock jitter assuming the edge falls with the same probability anywhere within the peak-to-peak limits. 186 CMOS Mixed-Signal Circuit Design 5.20 must equal unity, and the average value (also known as the mean or the expected value and denoted by < y > or y) of a PDF is given by 00 Average value, y, ft. pet) . dt (5.47) Example 5.11 Detennine the average value of the jitter with the PDF shown in Fig. 5.20. We can use Eq. (5.47) to detennine the average value of any PDF. Applying this equation to the PDF shown in Fig. 5.20 results in flT.,!2 Average value, y, == ft. /:iT . dt = 0 -flT,2 s This somewhat obvious result means that the average position of the clock rising edge is the ideal position indicated by trace 1 in Fig. 5.20. Any PDF that is symmetrical about some center point will have an average equal to the center point. • The variance of the PDF is defined as the average of the square of the signal's departure fTOm its average value. For a random signal this can be written as f(x" (y_y)2 ·p(y)·dy (5.48) where (J is the standard deviation of the PDF (the square root of Eq. [5.48]). For our purposes, in this book, we can think of variance as the average power of a random (voltage) signal and the standard deviation as the RMS value of the signal (see Eqs. [5.41] and [5.42]). Example random signals include the time difference between the actual edge of a clock and the ideal edge location (jitter), the voltage difference between the input of an ADC and the ADC's reconstructed output (quantization noise), and the random fluctuations of electrons due to thennal motion in a resistor (thennal noise). Example 5.12 Detennine the RMS value of the jitter when the jitter has a probability density function, PDF, as shown in Fig. 5.20. Using Eq. (5.48) the variance of the jitter PDF is flTd? f t2 . /:iT . df = 3 . /1:iT . t 3 jflT/2 -flTi2 -flT,i2 s s and thus the RMS jitter is (J = ~ RMS jitter, (seconds) ~12 where /:iTs is the peak-to-peak jitter in the sampling clock rising edge. Note the similarity to the derivation of VQc.RMS in Sec. 5.1.1 . • A more useful discussion of jitter can be constructed if we assume the jitter has a Gaussian PDF, as shown in Fig. 5.21, and attempt to describe how the jitter in the Chapter 5 Data Converter SNR p(t) RMS " J1tter !J.Ts cr"'6 Probability density function, PDF t Peak-to-peak jitter'" !J.Ts pet) = 187 . e x p l2-cLr 2J o cr 2cr Time Figure 5.21 Sarnplingjitter with a Gaussian probability distribution. sampling clock affects an ADC output spectrum with a single-tone input. Using Eqs. (5.20), (5.21), and (5.22), we can write the sampling error voltage (review Fig. 5.19), at a given time, as !J.Vs(t) 0:= oTs(t)· Vp ·2rr.Jin . cos 2rr.Jint (5.49) where oTs(t) is a random variable indicating the jitter in the sampling clock at a given time. (The variable oTs(t) is the time difference between the actual clock transition time and the expected transition times that are spaced by Ts [see Fig. 5.20].) The peak-to-peak value of oTs(t) is !J.Ts, while its average value is zero. Again, we assume that the jitter probability distribution function is Gaussian, as seen in Fig. 5.21. Rewriting Eq. (5.49) using a discrete time step nT" the sampling error can be written as Sampling error amplitude . Carrier term , !J. Vs(nTs) = oTs{nTs)' Vp ·2rr.Jin· COS 2rr.JinnTs (5.50) We're interested in the spectrum of this error signal as it will add to our RMS quantization noise plus distortion voltage, effectively lowering the data converter's SNDR. Notice that the spectrum of Eq. (5.50) will have aliased components (and so will the sampled signal) so we need to filter out these components above Is 12 (with the reconstruction filter.) Also note that multiplying the sampling error by the cosine term in Eq. (5.50) simply shifts the error spectrum to a frequency1;•. The cosine terms act like a carrier in an amplitude-modulated signal. This is illustrated in Fig. 5.22. Example 5.13 Repeat Ex. 5.8 assuming the clock jitter has a Gaussian PDF. In this example the peak amplitude of the input signal, Vp ' is 0.5 V, the input frequency, 1;., is 25 MHz, and the peak-to-peak jitter is 100 ps. The average power in the sampling error amplitude spectrum is =( 2 cr PAVGJiller = 2 • -,--,,---:-=-....,;.... ..... \. !J6.Ts \) 2 • (Vp . 22rr.Jin) (5.51) 188 CMOS Mixed-Signal Circuit Design Sampling error amplitude spectrum ~4) o f Data converter output spectral content resulting from jitter l.--~ ) o f Figure 5.22 Modulating sampling error with an input sinewave frequency. or PAVGJilter 1006Ps]2 . (0.5 . 2n '225 MHz)2 [ 0.858 X 10-6 V2 while the RMS voltage associated with this error is 0.926 mY. The quantization noise associated with this 8-bit data converter is VREF+ - VREF 1.3 mV 2NjIT. The RMS noise voltage due to clock jitter and quantization effects is then given by JO.858 2 + 1.3 2 mV = 1.56 mV We can calculate the SNR using r::; SNR=20.1 0.5/,,2 og 1.56 mV 47.1 dB giving an effective number of bits, from Eq. (514), equal to 7.53. Note that this is a significant improvement over what was calculated in Ex. 5.8, where the jitter variation was always the peak-to-peak value.• The PSD of the sampling error amplitude, described by Eq. (5.50), can be determined with the help ofEq. (5.4l) 2 2 Cf • --'..-V( -,,-P_'22-::-n.::..if,:...,;11):- JoCJ 2 Pjitter(f) . d/ o (5.52) If the spectrum of the phase noise due to jitter is narrow, as seen in Fig. 5.22, then the spectral density of the sampling error, Pjit/.,.(/), is concentrated around the frequency of the input sinusoid. However, if we assume the phase noise spectrum is white and evenly distributed throughout the base spectrum (so that we integrate Eq. [5.52] from DC to//2), we can write Cf2 (Vp' 2rrjin)2 Pjiller(f) = /s . 2 (5.53) The power spectral density of the sampling error voltage, assuming even distribution of the noise throughout the base spectrum, is shown in Fig. 5.23. Chapter 5 Data Converter S:t- coming out of the averaging circuit. Improvement in resolution,NIne (bits added) SNRideal =- 6.02(N +NIne) + 1.76 soot 3.33! 1.67 o -+-.--+---f---+I·----~> 10 100 lk K Number of points averaged Figure 5.31 Using averaging to improve data converter resolution. 5.3.2 Linearity Requirements Examine the cases for averaging ADC outputs shown in Fig. 5.32. In part (a) we show the ideal situation where the black dots indicate two consecutive outputs spaced by one LSB (time is not shown in this figure). The ADC outputs in part (a) are located on the ideal levels, while the averaged output falls exactly in the middle of these levels (and hence our increased resolution). Part (b) of this figure shows the situation where the ADC outputs are shifted downwards by 0.5 LSBs from their ideal levels. Following this offset, the averaged point shifts downwards as well. In Palt (c) the top output of the ADC (the top Chapter 5 Data Converter SNR 195 ADC output I .} • It i:.~Averaged point E 1 L S B C 1 LSB ~ Ideal level ~.~ ~ ~ 1 LSB ~ Averaged point 0.5 LSB /DJ>.L ~tf· ~ 0 t ADC output 2 -. Averaging two points (nonideaJ) DNL of 0.5 Averaging two points (ideal) (c) (a) Averaging two points (nonideal) offset of 0.5 (b) Figure 5.32 Linearity requirements when averaging. blaek dot} is shifted downwards by 0.5 LSBs and so the averaged point shows a 0.25 LSB offset from its ideal position. While we used a single LSB difference to show averaging, we could use any number of LSBs to show that the ADC accuracy must be equal to or better than the desired final digital filter output accuracy. The number of bits in the ADC (its resolution) N, and the number of bits improvement in resolution after filtering, N/ne ' are used with the final, total number of bits (the number of bits eoming out ofthe digital filter) to give N Final = N + N fnc (5.60) The ADC output should ideally ehange in increments of the exact LSB voltage. In reality, the changes will be different from the ideal output levels (as just diseussed). In order to aehieve an increase in the number of final bits, the output of the ADC must be aceurate (its aetuallevels must be spaced from the ideal levels) to within + V Rli"F+ VREF- ~ 2NFi"ul+ 1 ± (0.5 LSB) . 1 -N 2 J~ (5.61 ) where no averaging (NIne 0 and K = 1) means the ADC is at least 0.5 LSBs accurate. This is a significant limitation when using averaging to increase the resolution of an ADC. This is especially true when a resolution greater than 10 bits is desired with INL and DNL less than ±0.5 LSBs. In the next seetion, and in the next chapter, we will look at feedbaek topologies that may relax the accuracy requirements plaeed on the ADC and allow averaging to more effeetively remove quantization noise. 5.3.3 Adding a Noise Dither Our assumption, when diseussing the benefits of averaging or calculating the spectral density of the quantization noise, falls apart for DC or slow-moving signals (the ADC input is not "busy"). In order to help with this problem consider adding a noise signal to the ADC input that has a frequency content that falls within the range is < f 2K~ 2 (5.62) 196 CMOS Mixed-Signal Circuit Design so that it can be filtered out with the averaging filter (see Fig, 4.10). This noise is often called dither (a state of indecision or agitation) because it helps to randomize the spectral content of the quantization noise, making it white. Fignre 5.33 shows the basic idea. In part (a) a DC signal is applied to the ADC that falls halfWay between two ADC transition codes spaced apart by 1 LSB. The output code of the ADC remains unchanged with time. In part (b) a noise signal is added to the DC input which has two benefits: (I) the quantization noise (the difference between the input signal and the reconstructed ADC output code) changes with time, and (2) the output of the ADC has some variation which makes it "possible to determine the DC voltage after averaging, ADC Output code N co til DC Input signal ....J ADC Output code N-l (a) Figure 5.33 (a) DC input signal and (b) DC input signal with dither added. We can add the noise signal to our desired input signal with a circuit similar to that shown in Fig. 5.34. Simple resistors add and reduce the noise signal applied to the ADC input. The noise signal source is, most easily, derived from some sort of asynchronous logic circuit and has a peak amplitude (before reduction) of VDD I V in this book). In this figure note that we have indicated that the dither signal amplitude should be approximately 0.5 LSB RMS (remembering the signal is, ideally, random and band limited as specified by Eq. [5.62]). This number, 0.5 LSB RMS, is subjective, and no exact rules as to its selection can be given othcr than the desirc that the peak-to-peak Input with dither ~ Y ~ I: ~ ,In.p~ut "l ADC Input with dither It,ooo I - Inpu~t -5r 0 ~----LI ADC --~ Ir Dlth;l nois;' I I s.'ource i -- Approximately 0.5 LSB RMS dither 0 toiY Dither generating Id!git~l l:lrcUit Block diagram Circuit implementation Figure 5.34 Adding dither to an ADC input signal. Chapter 5 Data Converter SNR 197 amplitude be greater than I LSB. One disadvantage of adding the dither is that the allowable range of input signals shrinks. A DC signal at VDD - 1 LSB will not benefit from dithering since the ADC will be at its full-scale output. Before we discuss the implementation of a dither source, consider one possibility (a Gaussian PDF) for the desired probability density function (PDF) of the dither signal and DC input shown in Fig. 5.35 (the input to the ADC). [fwe average this signal over a long time, we get the average or DC input signal since the dither averages to zero. This would also mean that we can have some dither spectral content below f/2K as long as we average enough ADC output samples to make its contribution to the SNDR small. It is generally a good idea to use Eq. (5.62) as a gnide for allowable dither spectral content. Finally, it's important that any dither signal we generate has a symmetrical PDF (the dither signal must average to VDDI2 before amplitude reduction). If not, an unknown DC offset (the known DC offset is the VDD/2 attenuated by the resistive divider in Fig. 5.34) in the data converter's (actually the filter's) output will result. p(t) Probability density function, PDF RMS dither = (J = 0.5 LSB pCt) ~ .exp [ a,,2n: Amplitude variation ,\lith time Volts DC in, Vin Figure 5.35 Input to the ADC, dither and DC, with a Gaussian probability distribution. An example of an implementation of a dither noise source is shown in Fig. 5.36. The outputs of the rows of inverters, which are tied together, will occur asynchronously and fight against each other causing the amplitude of the dither signal to occupy levels Dither out }'igure 5.36 One possible implementation of a dither circuit. 198 CMOS Mixed-Signal Circuit Design other than the nonnal logic levels of VDD and ground for significant amounts of time. The dither signal can be made more random by adding more rows of inverters. The challenge to this design is setting the number of inverters used in each row so that the spectral content falls within the desired range (which may require a large number of inverters) and keeping the output of the dither circuit uncorrelated with the sampling clock. Other techniques for generating random noise, such as using linear serial feedback registers, can be found in most books covering communication systems. 5.3.4 Jitter We can apply the averaging discussion just developed directly to the jitter discussion presented earlier in the chapter and answer the question, "How does averaging effect the sampling amplitude error power (resulting fromjitter) in a data conversion system?" Ifwe assume that the jitter has a Gaussian PDF, then the average power in the sampling error tz . r amplitude, from Ex. 5.13, is P AVG,jiller '" [ cr· 2TC/in (5.63) where cr is the standard deviation of the jitter (see Fig. 5.2 J). It may be helpful to rewrite Eq. (5.57) in tenns of the quantization error power as visB 2 1 K ' 1 2 PQe,AVG = (VQe.RMS) = (5.64) and apply the same derivation to Eq. (5.63) to give [vp K' PAVGJiller = 1 cr· ,fi ·2rif;nJ2 (5.65) This equation shows that the sampling error amplitude power, PAVG,jiller' introduced into the data converter's output spectrum decreases with averaging. Averaging two samples causes the sampling error amplitude power to decrease by 3 dB. This effectively reduces the jitter requirements placed on the sampling clock. While this may not appear to be very significant at first glance, consider what happens if, for example, 256 samples are averaged (K 256). The sampling error power decreases by 24 dB, making clock jitter, when using a reasonably stable oscillator, almost not an issue. Also note that a doubling in the jitter's standard deviation, cr, results in a 6 dB increase in sampling error amplitude power. 5.3.5 Anti-Aliasing Filter The use of averaging will also lead to relaxed requirements of the anti-aliasing filter (AAF). Figure 5.37a shows the requirements placed on the AAF without averaging. As we saw in Ch. 2, ideally, the transition from the 3 dB frequency to the "stop frequency" or Nyquist frequency should be infinitely sharp (the filter should abruptly change from a gain of unity to a gain of zero [something small]). When using averaging, Fig. 5.37b, we have to limit our desired input signal bandwidth to B. The rolloff of the filter in part (b) of the figure can be much more gradual and in many cases a simple, single pole, RC filter is all that's needed for an AAF. Also, our averaging filter will attenuate the ADC output spectrum, as seen in Fig. 1.17, and help to remove input signal power above f/2K. The Chapter 5 Data Converter SNR IH(f) I 199 IH(f) I B =fsI(2K) ,/ In =fsl2 f (a) In =fsl2 f (b) Figure 5.37 (a) AAF requirements without averaging, and (b) AAF requirements with averaging. significance of this will be easier to see as the number of points averaged increases and our averaging filter's response gets sharper with more attenuation (see Fig. 4.10). Of course, the penalty for the relaxed requirements of the AAF is reduced signal bandwidth for a fixed sampling frequency. 5.4 Using Feedback to Improve SNR By averaging the outputs of an ADC, or interpolating between inputs of a DAC, the effective data converter resolution can be increased. As specified by Eq. (5.58), every doubling in (octave increase in) K (where K is the number of points averaged) results in a 0.5-bit increase in effective resolution. An effective ADC resolution increase of 6-bits requires averaging 4,096 samples. If a 1 MHz signal bandwidth is of interest, our sampling clock frequencY,h, will have to be 8.192 GHz! In this section we briefly introduce the idea that feedback can be used with data converters (ADCs and DACs) to improve overall data conversion system performance (lower the amount of averaging or oversampling needed to attain a given resolution over a certain bandwidth). A topology of this nature is called a modulator or coder (for analog-to-digital conversion) or a demodulator or decoder (for digital-to-analog conversion). The complete analog-to-digital interface (a circuit block that functions as an ADC) would be made up of a modulator and a lowpass (decimating) filter, while the digital-to-analog interface (a circuit block that functions as a DAC) would consist of an interpolating filter and a demodulator. This can be confusing since, for example, a modulator will contain a low-resolution ADC in a feedback configuration which, together with the decimating filter, behaves like a high-resolution ADC. The basic topology of a feedback modulator or coder is shown in Fig. 5.38. Depending on the circuit blocks used for A( I) and B( I) feedback modulators can be separated into two categories: predictive modulators and noise-shaping modulators. Predictive modulators (a.k.a. predictive coders), such as delta-modulation, attempt to feed back an analog signal with the same value as the input signal. This drives the output of the summer to zero, reducing the required input range of the ADC and, possibly, the quantization error introduced by the ADC. Predictive modulators effectively output the change in the input signal over time. Noise-shaping modulators, an example being delta-sigma-modulation, also known as sigma-delta-modulation, on the other hand, 200 CMOS Mixed-Signal Circuit Design Vout(f) Out (to digital filtering.) Figure 5.38 Block diagram of a feedback modulator. feed back, and output, the average value of the input signal. This signal can be filtered (averaged) to reduce the accuracy required of the analog circuit components. Noise-shaping modulators effectively output the average of the input signal over time. In a noise-shaping data converter the averaging and decimating filter, as discussed earlier, is connected to the output of the modulator. Because of the averaging used in noise-shaping modulators, the analog components, in the forward path of Fig. 5.38, require less accuracy. However, the DAC's output, in the feedback path (which is subtracted from the input), doesn't experience the averaging so, once again, the DAC must be linear to the final desired resolution of the data converter. DAC linearity concerns have led to the use of a single-bit DAC (an inverter), in many noise-shaping data converter applications. The one-bit DAC is inherently linear. (Two output points determine a line!) Because of the relaxed requirements placed on the analog circuit components, we will concentrate the next chapters, in detail, on noise-shaping topologies for both ADCs and DACs. Notice that both predictive and noise-shaping modulators utilize oversampling. In order to understand these statements in more detail, let's use the additive quantization noise model for the ADC developed in this chapter, Fig. 5.2. Figure 5.39 shows Fig. 5.38 redrawn using this model where the quantization noise is represented in the frequency domain by VQeCf). We can relate the inputs (the wanted input signal and the unwanted quantization noise) to the output of the feedback modulator by Signal transfer function, STF(f) ~ A(f) I +A(f) . B(f) Noise transfer function, NTF(f) 1+A(f)· B(f) (5.66) In a predictive modulator the feedback filter, B( f), has a large gain so that, ideally, the fed back signal equals the input signal. If A(f) = 1 (a wire), then both the STF (signal transfer function) and the NTF (noise transfer function) have a value of, approximately, IIB( f). Recovering the input signal requires passing the output of the predictive modulator through an analog filter with a transfer function of precisely B(f) (noting that B[f] is a digital filter in the modulator of Fig. 5.39). The required precision of the analog filter (the matching between the filter in the modulator and the filter in the demodulator) limits the attainable resolution when using predictive modulators. Notice that both the input signal and the quantization noise experience the same spectral shaping (spectral discrimination is absent in a predictive modulator). Also note that the name "predictive" comes from the modulator attempting to predict the input signal in order to drive the output of the summer to zero. If the prediction is perfect, the signal that is fed back exactly matches the input signal. Chapter 5 Data Converter SNR 201 Analog Vout(f) Out Figure 5.39 Block diagram of a feedback modulator. In a noise-shaping modulator the gain of the forward path, A( f), is large in the signal bandwidth so that the STF is approximately unity (assuming B[f] I). The NTF, on the other hand, will approach zero, ideally, in the bandwidth of interest. Note that the signal spectrum passes through the modulator essentially unchanged, while the quantization noise spectrum is shaped (and thus the name noise-shaping). No precision filter or analog components are required, as discussed earlier, except, perhaps, for the DAC in the feedback path of the modulator. We'll see in the next chapter that if A( /) is an integrator, the quantization noise is pushed to higher frequencies so that it can be removed with the averaging filter. This is a very important concept, as a noise-shaping modulator does not reduce the quantization noise to attain higher resolutions, but rather pushes the noise to frequencies outside of the signal bandwidth of interest. ADDITIONAL READING [1] R. 1. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, Springer, 2007. ISBN 978-1402075001 [2] Engineering Staff Analog Devices Inc., Data Conversion Handbook (Analog Devices), Newnes, 2005. ISBN 978-0750678414 [3] M. Gustavsson, J. J. Wikner, and N. Tan, CMOS Data Converters for Communications, Springer, 2000. ISBN 978-079237780 I [4] S. R. Norsworthy, R. Schreier, and G. C. Temes (eds.), Delta-Sigma Data Converters: Theory, Design. and Simulation, Wiley-IEEE Press, 1997. ISBN 978-0780310452 [5] J. C. Candy and G. C. Temes (eds.), Oversampling Delta-Sigma Data Converters, Wiley-IEEE Press, 1992. ISBN 978-0879422851 [6] S. K. Tewksbury and R. W. Hallock, Oversampled, Linear Predictive and Noise-Shaping Coders of Order N>I, IEEE Trans. Circuits and Sys., Vol. CAS-25, pp. 436-447, July 1978. [7] W. R. Bennett, "Spectra of Quantized Signals," Bell System Technical Journal, Vol. 27, pp. 446-472, July 1948. 202 CMOS Mixed-Signal Circuit Design QUESTIONS 5.1 Develop an expression for the effective number of bits in terms of the measured signal-to-noise ratio if the input sinewave has a peak amplitude of SO% of (VREF+ VREFJ· 5.2 When using Eq. (S.14) what is the assumed ADC input signal? Put your answer in terms of the ADC reference voltages. 5.3 Describe, in your own words, the difference between specifying SNR and SNDR. 5.4 Using SPICE simulations with an ideal ADC and DAC, show how coherent sampling can result in an RMS value of quantization noise larger than what is specified by Eq. (S.3). Comment on the shape of the quantization noise's spectrum. 5.5 Suppose a perfectly stable clock is available (AT., is zero in Eq. [S.2l D. Would we still have a finite aperture window if the clock has a finite rise time? Describe why or why not? 5.6 How do the number of bits lost because of aperture jitter change with the frequency of an ADC input sinewave? If the ADC input is a DC signal, is aperture jitter a concern? Why? 5.7 Why must Bennett's criteria be valid for the averaging filter in Fig. S.29 to reduce the quantization noise in the digital output signal? Give an example input signal where averaging will not reduce quantization noise. 5.8 Assuming Eq. (S.S7) is valid, rederive Eq. (S.13) including the effects of averaging K ADC output samples. Is Eq. (S.13) or the equation derived here valid for a slow or DC input signal? Comment on why or why not. 5.9 If Bennett's criteria are valid, does averaging ADC outputs (or DAC inputs) put any restrictions on the bandwidth of the input signal? Why? Give an example. 5.10 How accurate does an 8-bit ADC have to be in order to use a digital filter to average 16 output samples for a final output resolution of lO-bits (see Eq. (S.59])? Assume the ideal LSB of the 8-bit converter is 10 mY. Your answer should be given in both mV and % of the full-scale. 5.11 Show the detailed derivation ofEq. (S.66). 5.12 Summarize, and compare, the advantages and disadvantages of predictive and noise-shaping data converters. Chapter 6 Data Converter Design Basics Mixed-signal design is powerful because it combines digital-signal processing (DSP) with analog circuit design. Using DSP, as we'll show in this chapter, reduces the required precision of the analog circuits. Perhaps a different, yet appropriate, name for this chapter is "Analog Design without using Analog Components!" In the past five chapters, we covered topics we'll frequently use in the design of mixed-signal circuits. For example, Fig. 6.1 shows how we'll design an analog-to-digital converter (ADC) using mixed-signal circuit design techniques. Our analog input is passed through an anti-aliasing filter (AAF) to a noise-shaping (NS) modulator. The noise shaping modulator, as discussed in Sec. 5.4, uses a low-resolution quantizer (a fancy name for an ADC with 1 to a few bits resolution, like the comparator seen in Fig. 5.1) in a feedback loop to get a running average of the analog input signal. The desired digital output is extracted using a moving average filter, the lowpass filters in Sec. 4.2, and decimated. In simple words, the modulator's digital output signal is averaged to get a representation of the analog input signaL Figure 6.2 shows example modulator outputs for various DC input signals. Note that this type of data converter is often called an oversampled ADC since the sampling frequency,fs, must be much larger than the input frequencies of interest. We'll also see that these types of data converters are called noise-shaping ADCs or, depending on the topology used, delta-sigma (or sigma-delta) ADCs (these names are discussed in greater detail later). I-bit r H Analog inp-u--t--JIAM ~ ~NSd~l NS modulator ~ L-..J . f.!........_. _'r=~ Clock input Digital Filter l Digital Output "Decimation filter Figure 6.1 An ADC using a NS modulator and digital filter. 204 CMOS Mixed-Signal Circuit Design A ! 1.0 0 1.0 [0 ::i 0.... 2 ;ro; -0 0 ::E 1.0 oi to10 ~- 1.0 . -- ~I Average = I~O 0.25 nJ1JlJL Average = = 0.5 UUU~ ~. . 8 (Repeats every 32) U~ ~~u_U~n .~ .... 16 ~~ ~ 24 _~U_ ~ .. .. 32 Average (31)·(10) 32 ~ _U Average (7)-(1.0) 8 ~ Average = 180 .. Average =0 V ) 40 Figure 6.2 Modulator outputs and their corresponding DC averages. The One-Bit ADC and DAC In this chapter we'll use, exclusively, a one-bit ADC and DAC. To understand why, let's review Fig. 5.28 and 5.32. In all cases, unless the spacing of the codes is perfect in these data converters, averaging the codes will result in non-linearity. However, by using an ADC or DAC with only two output codes in our NS modulator we are guaranteed linearity (two points determine a line!). If one of the reference voltages in the ADC or DAC is offset from its ideal value then we'll get a gain error but no nonlinearity error. In Chs. 4 and 5 we treated the clocked comparator as a I-bit quantizer (ADC) with an LSB given by I LSB VREF+ VREF- = VLSE (6.1) as an added noise source, Fig. 5.2. The PSD of the added noise, see Eq. (5.5), is 2 vISE VQe(f) == 12/ (6.2) s In this chapter we'll set VREF+ = VDD I V and VREF- == 0 V so that VDDI2 or 500 mV. We can think of the output of the comparator (the output of the NS modulator) as a binary offset number with a value of 1 or O. After a simple conversion to two's complement numbers, the output can be changed to +1 (01) or -I (II). Since our input signals are referenced, or swing around, VCM it's useful to think in terms of two's complement numbers. For example, in Fig. 6.2, if we apply 500 mV to the input of our NS modulator we get 1010101... (second sketch) or an average of 500 mV (= VCM). Since all signals are referenced to VCM it may be more useful to say that we aren't applying a signal (meaning just the common-mode voltage is present at the input) and thus we get a sequence of +1, -J , +I, -1, etc. that averages to zero (Vcu)' Figure 6.3 shows how we think about this in more detail. If we pass a signal through an inverter we are multiplying it by -1 when we think in terms of two's complement numbers. Chapter 6 Data Converter Design Basics 205 A one-bit DAC VREF+ Binary offset Two's complement ,.-'-.. ,.-'-.. VDD - - - - - ~ 01 or+ 1 Two's complement ,.-'-.. ······-······OOorO VREF- Binary offset Two's complement ,.-'-.. ,.-'-.. 0 ----- 0 ~ II or-I Figure 6.3 Thinking about the inverter in terms of the common-mode voltage. 6.1 Passive Noise-Shaping Figure 6.4 shows a schematic and block diagram of a passive NS modulator. Reviewing 5.38, we see that this is a modulator topology with 8U) = I. To calculate AU) let's write the output of the summing block (the resistors), or the input to the A(f) block, as R R Vi" - Vint -Voul - + Vinl =I' ~ (6.3) noting that we are assuming all voltages are referenced to VCM' The output of the A(f) block is (6.4) so, and therefore Vin - Vout Vtnl' UmCR + 2) (6.5) A(f) 2 +jroRC (6.6) This is nearly the transfer function of an RC circuit, see Eq, (3.1). We can also think of this response as integrating for frequencies above 1I21tRC. We'll come back to this in a moment. Using Eq. (5.66) we can write VoutU) = , STF(f) I 2 3 +J.mRC 'Vin(f) + . 3 +J.mRC . VQ e ( f ) (6.7) Notice that the AAF is built-in to this topology via the STF. At DC the noise transfer function appears to be 2/3. However, we know that at DC, as seen in Fig. 6.2, we can average the modulator's outputs and recover, exactly, the analog input signal (see dead zone issues for a passive modulator on page 215). This means that VQe(O) ~ O. Let's try to get a better representation for the output of the modulator. In order to begin notice that (6.8) Next, let's write + (Vin-Vint -VOUl-Villl). + V (f) \R R jmC Qe Vout (6.9) 206 CMOS Mixed-Signal Circuit Design Vin - Vim Analog DAC -Vaul Digital >-----.r--- Vout Is (a) Circuit implementation of a passive NS modulator VQeCf) Vin l---,--VOUI ~_-_V;;.;.OU,,-I--1- 1 (b) Block diagram model of a passive NS modulator. Figure 6.4 A passive-integrator NS modulator. and Vio Voul - 2Vinl + VQe ·jwRC == jwRC· VoUl (6.10) Vin - 2V;nl + VQe )wRC == Voul • (1 +jwRC) (6.11 ) so finally Vow = STF(f) NTF(f) r---"-----. jwRC V -2· Viol 1 +jwRC 'Vin + 1 +jwRC . Qe + 1 +jwRC ~~ Extf'd noisc/distortion (6.12) The key things to note are: I) that if we can keep ViOl from varying we eliminate this extra distortion term (this is why we use an active integrator in later chapters), 2) the signal sees a lowpass response (so we have, as already mentioned, a built-in AAF that limits input spectral content), and 3) the noise is shaped towards the higher frequencies (the noise is high passed filtered). If our quantization noise is flat, as seen in Fig. 5.12, then high-pass filtering the noise gives the PSD seen in Fig. 6.5. Quantization noise that has been shaped in this way is called modulation noise. Note that the faster we clock the comparator (the larger I) the less variation we'll get in Vim' Also note, again, that the (digital) output of the modulator is the average of the (analog) input signal. Chapter 6 Data Converter Design Basics 207 In =fsl2 I Figure 6.5 Modulation noise spectral density. Example 6.1 Simulate the operation of the NS modulator seen in Fig. 6.4 when R is 10k, C is 10 pF, and the clocking frequency is 100 MHz. Comment on the resulting simulation results and the operation/limitations ofthe circuit. Figure 6.6 shows the input (a sinewave at 500 kHz) and (digital) output of the circuit. Notice that as the input signal moves towards ground the output signal stays low more often. As the input signal moves towards VDD the output is high, or a logic I, more often. While we can use a digital filter to change this one-bit code into an N-bit word (and we will!) let's show that a simple RC filter can be used to get our original signal back from the digital data, Fig. 6.7. The STF starts to roll-off at 1I2nRC or 1.59 MHz. While the circuit will continue to operate at higher frequencies the SNR of the data converter will suffer. We'll see that for proper operation the comparator's gain becomes very important. Here we are using an ideal comparator. Finally, it's interesting to look at how Vint changes with time for various inputs. Remember, as seen in Eq. (6.12), that this term adds distortion and noise to our input signal. At high-frequencies this term is small because of the pole at 1/2nRC and at low frequencies the contributions are small since the feedback loop responds faster than the input signal changes. What's of concern is the moderate frequencies and how the SNR is degraded.• Figure 6.6 Simulating the operation of the passive NS modulator seen in Fig. 6.4. 208 CMOS Mixed-Signal Circuit Design Figure 6.7 Using an RC circuit to filter the digital output in Fig. 6.6. 6.1.1 Signal-to-Noise Ratio Let's calculate the SNR for the first-order noise-shaping modulator seen in Fig. 6.4 and characterized by Eq. (6.12). In the following we'll ignore the extra noise/distortion resulting from variations in Vim' Further note that the pole associated with both the STF and NTF won't affect the SNR since it's common to both. We know the output of the modulator is passed through a lowpass filter with a bandwidth B to remove the modulation noise, Fig. 6.8. The smaller B the lower the noise in the final digital output word and the larger the SNR. Again, the trade-off with using smaller lowpass filter bandwidth is that the frequency range of the allowable input signals shrinks. Let's calculate the RMS noise in the filter's output using f f ~~~ B 2B = V;Oise,RMS 2 INTF(f)l21 V Qe(f)12 . df=2· . (2nj- RC)2 . df o 1s 0 (6.13) or 3 2 Vnoise.RMS =2· ViSB 12fs 2 . (2nRC) B3 . (6.14) again noting that using a smaller digitallowpass filter bandwidth, B, reduces the noise. Figure 6.8 Filtering out modulation noise to calculate SNR. Chapter 6 Data Converter Design Basics We spent a great deal of time in Ch. 4 using Sinc-shaped lowpass filters for decimation. Let's use these filters here for filtering and decimating the output of the NS modulator. Let's set the bandwidth of the filter, see Fig. 4.17, to B j, 2K (6.15) noting that we assumed, when deriving Eq. (6.14), a brickwall-shaped lowpass filter response. We can reduce the noise further, after decimation, by passing the digital data through additional lowpass filtering (perhaps using the biquad filters discussed in Ch. 4 with peaking to account for the droop introduced with the Sinc filter). Making the substitution gives V;oise,RMS = 12 (6.16) The value of RC must be much longer (at least five times) than the period ofthe sampling clock, Ts, to keep Vim from varying too much. Following the procedures used to derive Eqs. (5.10) to (5.13) we get SNRideal = 20 . log 6.02N + 1.76 20 --::::::~ + 20 logK3/2 Vnoise.RMS (6.17) Ifwe set RC 4.4if, 4.4T, then we can write SNRideal = 20 . log Vp / ,fi . 6.02N + 1.76 - 18.06 + 30 10gK Vnoise,RMS (6.18) For K = 4 this equation is the same as Eq. (5.13). However, for every doubling of K beyond 4 we get an increase in resolution, Nine' of 1.5 bits or an increase in SNRideai of 9 dB 18.06 (6.19) SNRideal 6.02(N + Nine) + 1.76 (6.20) Fignre 6.9 compares the first-order NS modulator to simple oversampling, Fig. 5.31 and Eq. (5.58). It's important to note that Bennett's criteria need not be valid using the oversampling feedback modulator discussed in this section (e.g. the input doesn't have to be busy). 6.1.2 Decimating and Filtering the Modulator's Output It's important to note that Eq. (6.17) was derived assuming the output of the modulator was passed through a perfect lowpass filter with a bandwidth of B, fl2K. Passing the output through a Sinc averaging filter, see Fig. 4.14, will result in a poorer SNR because the higher frequency noise components will not be entirely filtered out. In this section we want to answer two questions: (1) what order, L (sec Eq. [4.19]), of Sine lowpass filter should be used in the digital filter on the output of the NS modulator, and (2) assuming we use only this filter (no additional filtering), how will the ideal SNR of the first-order NS modulator be affected? 210 CMOS Mixed-Signal Circuit Design Improvement in resolution,Nlnc (bits added) First-order noise shaping using a passive ~ modulator and neglecting the noise/distortion term in Eq, (6,12), 5.00 3.33 , Simple oversampling \.67 o - - I -____-+---I--+----~.~ 10 100 Ik K Number of points averaged Figure 6.9 Comparing first-{)fder noise-shaping to simple oversampling (Fig. 5,29), We begin to answer the first question by noting that the increase in the number of bits, Nine' was specified by Eq. (6.19). If our NS modulator uses a I-bit ADC, then the final, after the digital filter, resolution of the resulting data converter is Nine + 1 bits. (An NS modulator using a 5-bit ADC [often called a multibit NS modulator] would ideally have an output resolution of Nine + 5 bits.) Further, we saw in Ex. 4.3 and Fig. 4.14 that the word size increased by 10gzK bits in each Sinc filter stage, For a cascade of L filters we can require 30 10gK - 18.06 L . Iog2K~ 6.02 (6.21 ) For K:S: 256 we only need one lowpass Sinc filter or L = 1. Example 6.2 Sketch the implementation of a K 16 decimating filter for the NS modulator discussed in Ex. 6.1. Simulate the operation of the resulting ADC (modulator and filter). Estimate the SNR, number of final bits, and Nyquist frequency. The decimating filter's transfer function is (6.22) and seen in Fig. 6.10 (see Sec. 4.2.5). The filter's output clock rate is 100 MHzl16 or 6.25 MHz so the Nyquist frequency is half of this or 3.125 MHz. The increase in the number of bits is 3, using Eq. (6.19), so the final output word size, based on Figure 6.10 Lowpass and decimating filter used in Ex. 6.2, Chapter 6 Data Converter Design Basics 211 the SNR (= 25.78 dB), is 4-bits. Our filter causes the word size to increase by I-bit through each of the 4 stages so that our final output word size is 5-bits. We can throw the LSB of this word out; however, notice that the largest word we get out of the filter is when the filter's input remains a 1 at all times. In this case the filter's output (the output of the ADC made using the NS modulator and filter) is 16 or 1 0000. When the filter's input is a 0 at all times our filter's output is 0 0000. The output can swing from I 0000 to 0 0000 around the common-mode code of 0 1000 (8). By removing the MSB we can make the output swing from 1111 (15) to 0000 (0) around 1000 (8). However if the NS modulator's input moves close to VREF+ (here VDD) then the output of the filter can overflow. Figure 6.11 shows the simulation results. The input frequency, as in Ex. 6.1, is 500 kHz. Looking at the frequency response of our filter, Eq. (4.20) and Fig. 4.17, we should only see a minor amount of attenuation through the filter. However, looking at Fig. 6.11 we see more than a minor amount of output signal reduction. We've, up to this point, ignored the extra distortion/noise term seen in Fig. 6.12. In the next section we'll discuss this term in more detail and how matching and offsets effect the performance of the modulator.• 960mV..,--,..-"=---....,--'-'?--,---,--~=:!....,.---, 880mV 800mV .. 120mV MOmV 560mV 480mV 400mV 320mV 240mV 160mV i 80mV I I-~--t--r----i--i---i---+----l 0.0115 0.7115 1.4115 2.1115 2.0ps 3.5115 4.2115 4.9ps 5.611' 6.3115 Figure 6.11 Simulating the ADC (modulator and filter) discussed in Ex. 6.2. SNR Calculation using a Sine Filter Let's now consider how filtering with a Sinc filter instead of the ideal lowpass filter effects the SNR of the modulator/filter implementation of a data converter. Remember the SNRideal was calculated in Eq. (6.18) assuming the modulation noise was strictly bandlimited to B. Figure 6.12 shows the PSD of the NTF2(f) and IVQe(f)12 (the modulation noise) in a first-order passive NS modulator. Also shown in this figure is the shape of the averaging filter's magnitude response squared that is normalized to unity by dividing by K, see Eq. (4.20). Here we are showing the shape of a filter with K = 16 and a range ofJJ2 (see Fig. 5.12). We can calculate the RMS quantization noise resulting from a cascade of a first order modulator and an averaging filter, L I, using J/,/2 V~e.RMS 2 INTF(f)12 . IvQe(f)12 . IH(f)12 . df o (6.23) 212 CMOS Mixed-Signal Circuit Design . \ IVQe(f) I2 • INTF(f) I2 = Vl~2f. (2nj- RC)2 +=T-~---~--~--~:··--~==~-=~--~~f ~~ ~n B = {~ , Ideal maximum input frequency Figure 6.12 Showing modulation noise and filter response. or (6.24) For the frequency range of interestf«fs so sinx "" x and we get I 2 VQe.RMS = 2· V1L22S~B . (21s 2 . RC) . I ·(,/2 K2 ' . 2( f ) Sill Kn1s . df f, Let's let 6 = n . so -", ,r-·~---.. f2 sin2K6· d6 o and u ' VQ2e,RMS = viSB ( 2nR C)2 . fl 2n2K3 (6.25) (6.26) (6.27) Comparing this result to what we got in Eq. (6.16) we see that using the Sinc lowpass filter is nearly ideal for removing modulation noise. The more important concern, when using the Sine lowpass filter, is the droop that the desired signal undergoes. 6.1.3 Offset, Matching, and Linearity Examine the passive NS-modulator with offsets and mismatched resistors seen in Fig. 6.l3. In this section we want to discuss how non-ideal behavior affects the performance of the modulator. To begin, notice that a comparator offset has the effect of causing the average value of vint to be VCM ± Vas and thus the offset passes directly to the output of the modulator. This means that if we apply the common-mode voltage to the input the average of the output voltage is VCM ± Vas. Chapter 6 Data Converter Design Basics 213 Ri 0---~------~------------~+ Figure 6.13 Passive modulator with mismatch and offsets, Resistor Mismatch In order to determine the effects of resistor mismatch we can re-write Eqs. (6.9) to (6.12), neglecting the effects ofthe offset voltage, as ~__:..!.2!.. + -VOURI Vim) .. lC + VQe(f) Vout f Jro (6.28) Rj' (Vin Vim) - Ri . (VOUI + Vinl) +jroRiRr C, VQe =jroRiRj" C· Vout (6.29) Rj" Vin - Vmt . (R, + Rf) + VQe -jroRjRr C· VQe = (jroR,Rj" C + Ri )· VOlll (6.30) jroCRj -Vim' Vout = 1 +jroCRJ . Vjn + 1 +jroCRf ' VQe + 1 +jroCRj (6.31 ) The effect of mismatched resistors is a gain error (but no non-linearity, and thus, distortion). Note that the absolute value of the capacitor isn't critical or important for precision operation, The Feedback DAC The feedback DAC is the most critical component in the modulator for precision operation, Consider the waveforms seen in Fig. 6.14. In this figure we show the ideal shapes of the DAC's output (remember our DAC here is a simple inverter so we get Ideal shape (ideal area is shaded) Shape with under and overshoot (c) Wider, ideal, pulse shape (a) (b) (d) Increasing pulse width (going slower) to minimize nonideal pulse characteristics, Figure 6.14 Comparator output pulse shapes, input to the integrator. 214 CMOS Mixed-Signal Circuit Design perfect linearity, Fig. 6.15). As seen in the figure, the shape of the pulse affects the amount of charge, or current, we send back to the capacitor. In part (a) we see the ideal pulse shape and the ideal area under the pulse (the shaded area). In part (b) we see how the finite rise time and fall time can affect the actual area under the curve and thus the output of the integrator. In order to minimize these unwanted effects we can use wider pulses as shown in parts (c) and (d), which means we run the modulator at a slower clocking frequency. Increasing the width of the pulses minimizes the percentage of the area affected by the transition times. Note that the feedback signal directly subtracts from the input signal so that any noise or unwanted variation in the fed back signal, such as an amplitude variation, can be considered as adding noise to the input (and thus degrading the modulator's SNR). This is important. In the coming chapters we will use switched capacitor circuits that simply have to fully-discharge in order to make the shape of the feedback pulse less important. :> 1.0 ,;:f £I- ::I 0 0 0 Ideal / \ Nonideal 0.5 1.0 Comparator input, V Figure 6.15 Ideal and nonideal transfer curves for a l-bit DAC. DACOjJ,et Notice, in Fig. 6.15, that if our DAC's reference voltages are offset from their ideal values of VREF+ and V REF- that, like mismatched resistors, all we get is a gain error (no non-linearity). Possibly the most important concern when using a single-bit inverter topology DAC is the on-resistance of the transistors used to drive the feedback resistors. The drive strength of the MOSFETs should be so high that little voltage is dropped across them (so the output of the DAC swings between V REF+ and V REF-). This (limited DAC drive) is, again, another reason we'll soon start to focus on switched-capacitor implementations of NS modulators. Linearity ofthe First-Order Modulator We've ignored the effects of the extra noise/distortion term seen in Eq. (6.12) because it's a nonlinear error highly dependent on the input signal's characteristics (and thus hard to quantify). Let's use simulations to look at the linearity of the first-order NS modulator and digital filter seen in Fig. 6.1 0 (with a DAC connected to the output of the digital filter to show the digital data as an analog wavefonn). Figure 6.16 shows the input/output of Fig. 6.10 with a slow ramp applied to the modulator's input. Note that when the input ramp voltage is close to the power supply rails the digital output becomes nonlinear (too high when the input is close to ground and to low when the input is close to VDD). Also seen in this figure, as mentioned in Ex. 6.2, is the digital filter overflowing. In order to avoid this situation we can use a selector, like the one seen in Fig. 4.40, with the Set input connected to the MSB of the filter (remember we do a mUltiply by 2 by removing the filter's MSB to scale the filter's output to full scale as discussed in Ex. 6.2). When the Chapter 6 Data Converter Design Basics 215 Overflow Figure 6.16 Simulating the linearity of the first-order NS modulator. MSB of the filter's output is a 0 we simply pass the multiplied-by-2 output of the filter through the selector to the final output. When the MSB of the filter's output is a I, we use the selector to clamp the final output to 1111 and thus avoid overflow. Dead Zones Besides the nonlinearity seen in Fig. 6.16, notice that for some ranges of input voltages the output doesn't move or, rather, the output is dead. A simple example of a dead output is seen when the input signal is close to the common-mode voltage, 500 mY. These dead zones are the result of a repeating modulator output code (e.g., 010 10 I, 110110, 0000100001, etc.). The question is why does the modulator output code repeat for a relatively wide range of input voltages (e.g. 460 mV < Vi" < 540 mV)? In order to answer this question examine the modulator seen in 6.13. With an input voltage of 500 mV the output of the modulator is 101010... so that the average of the output is 500 mV. Now suppose the input voltage is increased to 510 mY. Because the voltage Vim varies with time, it's possible for the average current supplied from the input, [vm-V;nt(t)]IR; to equal the fed back current [-vout-Vint(t)]IR/ when the modulator's output is 1010101... By using an active integrator, Sec. 6.2.4, we can hold Vin/ constant and eliminate dead zones. 6.2 Improving SNR and Linearity In this section we discuss techniques for improving signal-to-noise ratio and linearity. We'll start out by discussing the second-order passive (uses two capacitors) noise-shaping modulator. This topology is considerably more useful than the first-order topology discussed in the last section because it has better linearity, randomizes the output code (to avoid dead zones), and lower modulation noise in the signal bandwidth of interest. Then we'll discuss using switched-capacitors instead of resistors in the feedback paths. The big benefit of switched-capacitor circuits over continuous-time circuits is that, Fig. 6.14, we remove the effects of non-ideal pulse shapes. The drawback is the need for a non-overlapping clock generator (which consumes power and layout area). Next we'll discuss putting NS modulators in parallel. This is useful for increasing SNR while not lowering the final output clocking frequency (at all or as much). Finally, we'll end the section by showing how an active circuit, e.g. an op-amp, can be used to improve linearity and noise by removing the extra term seen, for example, in (6.12). 216 CMOS Mixed-Signal Cireuit Design 6.2.1 Second-Order Passive Noise-Shaping After examining the first-order modulator seen in Fig. 6.4 we might wonder if we can get better perfonnance by double filtering the input signal and removing the comparator's connection to VCM' Figure 6.17 shows the resulting circuit. In this circuit we have two feedback paths. We've connected the largest amount of feedback to the inverting input of the comparator to ensure ncgative, overall, feedback. Note that, because the output is fed back to both integrating nodes v) and v2' the circuit will act to drive these nodes to the same value and thus attempt to keep them equal to each other. Figure 6.1 7 Second-order passive modulator. To attempt to describe the operation of the circuit let's write ( - - Vin---V+j -=V" o,,1--V~I lR R ~1. R ) jmC - VI (6.32) and ---.<- Vl-V2 (R ' Vat/I-V2) R ·j-m -I =Cv·, (6.33) = If the quantization noise added to VI and v2 is VQel and VQe2 then VJ + VQel Vo"ll and = V2 + VQe2 V out2. We can then write Vin - 3Vl +V2 +jmRC· VQe1 == voutl(jmRC-I) (6.34) VI 2V2 +jmRC· VQe2 = v oul2(jmRC -1) (6.35) Adding these two equations gives Vin - 2vI - V2 +jmRC. (VQel + VQe2) = (vaul] + vat/a)' (jmRC - I) (6.36) As a quick check to ensure that this equation is correct, notice that if we pass the output signal through a 100vpass filter with a bandwidth approaching 0, 0) -) 0 and we use a large RC then for a DC input, Vin "" Vj "" V2 and Vin - 2Vl - V2 -2Vout (so Vau! "" Vi")' Next, adding the random signal powers together (see, for example, Eq. [5.55] and the associated discussion) gives 2) ( 2 2 (mRC) 2 . ("V2Qel + VQe2 = mRC )2 . VQe (6.37) Chapter 6 Data Converter Design Basics 217 and Finally, we can write 2 (roRc)2 V . oul,nOlse '= 1 + (roRC)2 2 (6.39) 2 VOut,signal 1 ·v·2 1+ (roRC)2 In (6.40) noting the quantization noise power is cut in half. Equation (6.18) can be rewritten for the second-order passive noise-shaping topology as SNRideal 20'10g VPlj2 =6.02N+1.76 15.13+3010gK VnOlse,RMS (6.41) The modest increase in SNR, however, is not the big benefit of this topology. Rather the better linearity and reduction in dead zones are the major benefits of the topology. The extra noise/distortion term can be written as 2vI + V2 1 + (roRC)2 (6.42) Note that this topology attempts to drive VI and V2 to the same value, that is Vi.' The drawback of this is that the comparator must operate with an input range extending from VDD to ground. Figure 6.18 shows the simulation results where we repeated the simulation seen in Fig. 6.16 but used the second-order modulator. Clearly both the linearity and extent of dead-zones are much better using the second-order modulator. 5~s 1O~s 15"s 2n~s 25~s 3n~s 35"s 40"s 45~s 50\ls Figure 6.18 Repeating the simulation seen in 6.16 but with a second-order modulation. Example 6.3 Repeat the simulation seen m Fig. 6.11 and Ex. 6.2 using the second-order modulator seen in Fig. 6.17. The simulation results are seen in Fig. 6.19. The output amplitude more closely resembles the input amplitude.• 218 CMOS Mixed-Signal Circuit Design Figure 6.19 Repeating the simulation seen in Fig. 6.11 but with a second-order modulation. 6.2.2 Passive Noise-Shaping Using Switched-Capacitors Figure 6.20 shows the first-order modulator seen in Fig. 6.4 implemented using switched capacitor (SC) resistors, Fig. 2.35 (the resistors in Fig. 6.4 are replaced with SC resistors). Figure 6.21 shows the simulation results similar to Fig. 6.7 but using this new implementation. Again the benefit of this implementation over the continuous-time implementation seen in Fig. 6.4a is that the shape of pulse coming out of the feedback DAC, here an inverter, isn't important as long as the capacitors fully charge and discharge. To characterize the operation of this topology let's write, again see Fig. 2.35, Rsc =I,1C (6.43) Digital n-l n n 112 Figure 6.20 First-order passive modulator using switched-capacitors. Chapter 6 Data Converter Design Basics 219 :Figure 6.21 Regenerating Fig. 6.7 using a passive switched-capacitor modulator. The operation of this topology can be described by simply substituting Eq. (6.43) into Eq. (6.31). The signal gain can then be written as Rj == C; R, (6.44) If C, isn't exactly equal to Cj then the input signal undergoes a gain error. In order to eliminate this gain error, and to simplify the implementation of the modulator, consider sharing the feedback and input capacitors, Fig. 6.22. Simulations showing the operation of this circuit are found at CMOSedu.com. Reviewing the derivations in Sec. 2.2.3, we see that the input signal, in Fig. 6.22, is subtracted from the fed back signal and summed together using Clm• The inputs of the comparator are swapped, from Fig. 6.20, to ensure the polarity of the output signal matches the input signal's polarity. Notice that we connected the input and fed back signal's to the bottom plate of C/. Remember that this is the plate with the largest parasitic capacitance. When the ~I switches are closed, the bottom plate of C and its parasitic, are charged to VI•• Noise coupled into this bottom plate, from the sub"strate, sees the low-impedance input so that ideally none of the noise passes through to Ctnt" When the <1>2 switches close the bottom plate of C/ charges to vow!" Since the bottom-plate parasitic charges back and forth between Vi. and VO"', none of the charge from this parasitic is transferred to C,.,. VCM >----tr--- Vout Figure 6.22 Switched-capacitor implemenation of the passive modulator without gain error. 220 CMOS Mixed-Signal Circuit Design 6.2.3 Increasing SNR using K·Paths By increasing the sampling rate,J;, we can spread the quantization noise out over a wider frequency range, Figs. 5.12 and 5.26. Thus, for a fixed digital averaging filter bandwidth (see Fig. 6.1), the amount of noise in a digital output signal can be reduced. As discussed earlier in Secs. 2.1.6 and 5.3 we can increase the effective sampling frequency by using K-paths (putting K modulators in parallel). Since we've used the same variable, K, for both the number of points averaged in the digital filter on the output of a modulator, Sec. 4.2, and the number of paths used, Sec. 2.1.6, let's, in this section, use variables with differentiating subscripts to describe the operation of a modulator implemented with K-paths and oversampling Kavg '" number of samples averaged in the digital filter (6.45) and Kpa•h = number of paths used in the modulator (6.46) The digital filter connected to the output of the modulator can then be described using 1- z-K",g JL H(z) -= [ I _z-1 (6.47) By using K-paths our sampling frequency changes fromJ; to Kpalh Is so that the PSD of the quantization noise, Fig. 5.26, gets spread out over a wider frequency range VQ2e(J ) = 12 . KVipSaBth .Jr.Y (6 .48) For the noise-shaping topologies we would replace K (for example, see Eq. [6.18]) with Kavg' Kpalh while the bandwidth of our desired signal spectrum ranges from DC to B when decimation is used where B= 2Kavg (6.49) The next question that we need to answer is "Is it practical to implement parallel paths of noise-shaping modulators or Nyquist-rate data converters?" Clearly there will be an increase in layout area using this approach. Is the increase in SNR worth the increase in chip size, power draw, or complexity? Well, let's not spend any time on Nyquist-rate converters (e.g., flash or pipeline) in a K-path configuration (called a time-interleaved converter) since the input signal would have to meet Bennett's criteria (pages 165-166, consider problems with a DC input). Reviewing Fig. 2.37 we see that using a SC modulator like the one seen in Fig. 6.22 may be a possibility. However, notice that we need to multiply up the clock frequency from!, to KJ; then pass the resulting signal through the non-overlapping clock generator seen in Fig. 2.38. Further, the SC modulators would have to settle (fully charge/discharge their capacitors) within TjK seconds (an even bigger concern if the modulator uses an active element like an op-amp). If this is possible why not simply use a single path clocked at the higher rate, KJ; (or better yet two paths clocked at KJI2 like the topology seen in Fig. 2.36)? We get the same performance as the K-paths but with a much simpler implementation. Since we have to direct, and process, the input signal to the various paths, again Fig. 2.37, at a high-rate limits the use of K-paths in SC circuits (more on this in a moment and in Ch. 9). Chapter 6 Data Converter Design Basics 221 What about using the modulator seen in Fig. 6.4 in a K-path implementation? Figure 6.23 shows a 2-path, or time-interleaved, implementation. There are several benefits to this topology including: 1) the input can be continuously connected to the K-paths of modulators, 2) no active device (e.g. an op-amp) with settling time issues, and 3) the comparator's are triggered on the rising edge of a clock signal (so the feedback operation can occur over the entire clock period, Ts for each path). The drawback of this topology is the mismatched gains through each path. Notice that we've combined the digital outputs of the modulator into a two-bit word (so the possible outputs are 00, 01, and 10). This addition, we should recognize, is a filter with a transfer function = H(z) I +Z-l I - Z-Kpath " 'I- -_=z --l- - where /s,new = Kpafh ',Is, =e _j2n,_f_ /s,treW (6.50) or an average of two filter. Ifwe were to use 8-paths we would get a 4-bit output ranging from 0000 to 1000 (which may result in the same overflow problems we saw in Figs. 6.16 and 6.18 when the input of the topology is near or VDD, here). A simple solution to the overflow problem, other than using a selector to keep overflow from occurring as discussed earlier, is to use only 7-paths (instead of 8) so the final output code ranges from 000 to Ill. >---1"'=VO::U"'l;l Output (2-bits) @2/s Carry voual Figure 6.23 Two-path, time-interleaved, passive modulator with mismatch and offsets. Note that each path, in Fig. 6.23, will attempt to hold the input of each comparator at a different voltage, dependent on the offset voltage of the comparator, (6.51 ) so combining the input resistors and capacitors into a single path and the comparators and feedback paths into K-paths, to simplify the circuit and to reduce the effects of path mismatch, requires some thought. Consider the 4-path topology seen in Fig. 6.24. Here we've added an amplifier, with a gain of G, in series with the input path. Each comparator's offset is referred back to the integrating capacitor by dividing by this gain. If G = 100, for example, the differing offsets will have little effect on the circuit's operation. 222 CMOS Mixed-Signal Circuit Design Reduces the effects of varYing comparator offsets. Path filter -.~---~ T';C v:l~. H(z) '" 1-z4 4R~ r~ 1-z-1 L_ _ __ ~ ~_ . ___4_>1 __~--' + Note that decimation is not used here or in Fig. 6.25, while it is used in Figs. 6.26 and 6.27. Kpath = 4, only two clock phases shown. Figure 6.24 Four-path passive modulator. No longer time-interleaved since the integrator is common to all feedback paths (we'll call this the K-Delta-I-Sigma topology) Another design concern, when using this topology, is the delay around each feedback path. If there is excessive phase shift through the forward or feedback paths, the modulator will be unstable. Using an open-loop (no feedback) amplifier, like a diff-amp, will ensure minimum delay (again noting the gain, and thus frequency response, of this amplifier aren't important as long as the gain is high enough to eliminate the offset effects of the comparators and the delay through the amplifier is comparable to TsIKpath). Using an op-amp, in a feedback configuration, can ultimately limit the maximum speed of this topology. Figure 6.25 shows the output of the modulator in Fig. 6.24 with the same input signals and values used to generate Figs. 6.7 and 6.21. In Fig. 6.25 we've displayed the digital output word in analog form. Notice that the RC filtered output of this circuit is much smoother (contains less noise) than the outputs seen in Fig. 6.7 and 6.21. The extra smoothing from the inherent filtering when adding the outputs of the modulators together, (see filter transfer function in Fig. 6.24), helps to reduce the noise in the signal. Because of this inherent filtering it's easy to perform decimation directly on the output of the modulator. Figure 6.26 shows adding a register to re-time the output of the modulator (decimate) back down to /,. Also seen in this figure is the digital filter seen in Fig. 6.1 that is used to remove the modulation noise. Regenerating the simulation results in Fig. 6.25 Chapter 6 Data Converter Design Basics 223 1.0V-.--""",nrri O.9V O.BV O.7V O.6V O.5V O.4V ..........•......... O.3V ..........•......... V(out) V!dou~ . . , , , , , <-.----------,----------,----------,---------- ..- - , , , , , . --.o,,,,,,, -·--_-_-_-_-_-_--_,,,,,,,,,-_-_-_-_-_-_-_-_-_-_,-•,,,,,,,-__-_-_-_-_-_-_.-_,_-,,,,,,,I-_-_-_-_-_-_-_-_-_._.,,,,,- - O.2V O.1V o.oV'+---i---j-.LLLLLlU.tw'-WlllJ.lilljLlULJb...-T---'''''-"..1UfiWllllJlJW.Df'-".J.IJ o.o~s O.2~s O.4~s O.6~s O.B~s 1.0~s 1.2~s 1.4~s Figure 6.25 Simulating the operation of the 4-path modulator in Fig. 6.24. K-bI·tS,, I _ Z-Kpa1h log2 K path + 1 I _ Z-Ka"g ]L bits: 1 - Z-I I---b-cif-ts---I · . ! [ 1-z-1 Figure 4.32 j,' K a", I-*---'----"-~-----l-c-Kpath I Final output clock rate: : + Decimator: + Decimator: , I , Kpath Kavg l 1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____________________ I Path filter Averaging filter Figure 6.26 Performing decimation on the output of the modulator. using decimation of 4 we get the results seen in Fig. 6.27. The rate of the digital word output by the path filter is fs (just as it is when using a Nyquist-rate converter). Further, the path filter in Fig. 6.26 has the same frequency response as the SIR used in a Nyquist-rate ADC (a droop of -3.9 dB atfsl2, Fig. 2.17). Thus, with some thought, we can use this topology to implement high-speed Nyquist-rate ADCs. l.OV-,--""-n-nrrVcm!v,;;,in,,.).",,-----,r-,_V-,-!o_ut.,..)- - c ._ _-,,~!c:cdO=-=ut,,-)_ : - - ' O.9V .. .•.......•;..........•.•••...•.. ;..........;..•......•~..... O.BV .. O.7V ..........•..•. O.6V ..........•.... O.5V ..........•..•• O.4V •••.......•.........••.... O_3V ------------------- .• --. -,----------,----------,-.--------,----------.,---- , , , , , , ,,,, ,,,, ,,,, ,,,, • ______ 4 __________ • __________ • __________ .. ___ _ .. --------,,,,_.- ... ,, -.--.,,--------_ ,,,,-----------,,,,--- - --.,,,----------....----------....---- . .. --.··----------...----------.---- .- ·, . · ___ • ___ • . · · . , , _ _ _ _ _ _ • _ _ _ _ _ _ _ _ _ _ 4 _ _ _ _ _ , O.2V O.W O.OV+-----r---r- O.O~s O.2~s O.4~s O.6~s O.8~s 1.0~s 1.2~s 1.4~s Figure 6.27 Regenerating the signals seen in Fig. 6.25 with a decimation of 4. 224 CMOS Mixed-Signal Circuit Design Revisiting Switched-Capacitor Implementations At the beginning of the section, we dismissed the option of using switched-capacitor noise-shaping topologies in a K-path configuration, Fig. 2.3 7, because the capacitors would have to charge or discharge within T,IK seconds (comparator delay < To IK is a challenge). We said that if this were possible why not use two paths, clocked on opposite phases of a clock (Fig. 2.36), but at the higher clock frequency of K·Is? In the next chapter we'll show that a first-order noise-shaping delta-sigma modulator implemented using switched-capacitors has an input/output relationship given, see Eq. (7.2), by STF(f) NTF(f) ,--A--" ~.---.. vout(z) == Z-l 'Vin(Z) + (I _Z-I) .VQe(z) (6.52) The signal-transfer-function (STF) is simply one clock cycle delay, Z-l while the quantization noise is differentiated, Fig. 1.20. In other words the noise-transfer-function (NTF) is that of a differentiator, (1 - z-I). Note the similarity to the differentiation, jroRC, the quantization noise sees at low frequencies, 1 » jroRC, in the continuous-time passive NS modulator, Eq. (6.12). If we put K of these switched-capacitor topologies described by the above equation in parallel, Fig. 2.37, we can write the corresponding output of the topology, see Eq. (2.56), as STF(fl NTF(f) ~ r----"----. Vout(z) Z-K'V;n(z)+(I-z-K).VQe(z) (6.53) Note that the data is changing, on the output of this topology, at a rate of K Is =!,.new, so that z = ej2rcfljs.n,~. While the quantization noise PSD, as indicated in Eq. (6.48), will be spread out over a wider frequency range the fact that our NTF has the shape of a comb filter, Fig. 1.25, instead of differentiation limits the use ofSC modulators in K-path ADCs using clock signals like those seen in Fig. 2.37 for high-speed conversion. One may wonder why the STF is Z-K or such a long delay? Looking at the timing of the clock signals in Fig. 2.37 we see that each path is only activated every To seconds. If z == ej2rcfljs.new or z = e j2rcfl(K/.) then to represent a single path delay of T, seconds we have to use Z-K. In this scenario, Fig. 2.37 where H(z) represents the transfer function of a modulator, each of the modulators is independent, that is, not sharing the integrating capacitor (integrator) as we did in the topology seen in Fig. 6.24. With some thought we can implement a practical K-path ADC using SC circuits sharing a common integrator, Fig. 6.24, with clock signals. also seen in Fig. 6.24. having a width of Ts and leading edge spacing ofT/K seconds so that the effective samplingfrequency is K Is (Ch. 9). Effects ofthe Added Amplifier on Linearity We added the amplifier with a gain, G, in Fig. 6.24 in order to reduce the effects of comparator offset and make combining K-paths of quantizers sharing a common integrating capacitor a practical analog-to-digital converter topology. We haven't analyzed how this added amplifier can affect the linearity and performance of the topology. Let's do that here. Rewriting Eqs. (6.8) to (6.12) with this gain included we get VQe(f) + G· Vint(f) =Vout(f) (6.54) (6.55) Chapter 6 Data Converter Design Basics 225 Vin - Volil 2Vil11 + VQe -jO)R~ =jO)R~ . VOUI Vin 2Vint + VQe -jO)R~ = Voul' (1 +j(J)Rg) (6.56) (6.57) and finally STF(f) VOU! = NTF(/l j(J)R£ c I .G +J(J)R c ·VQe + -2· Vim 1+j(J)R~ \....-~~ Extra noise/distortion (6.58) It would appear that by using a very large gain, G, we can eliminate the lowpass filtering effect of the input signal (and thus pass very wideband signals to the modulator'S output, useful for Nyquist-rate analog-to-digital conversion) and remove the modulation noise from the output of the modulator. The extra noise/distortion term, however, remains in the modulator's output. Again, the only way to get rid of the noise/distortion term is to hold Vinl fixed so that it doesn't vary. This can be accomplished using relatively large 1. or an active element discussed next. Before getting too excited about removing the modulation noise we'll find out, in the next chapter, that we can think of the comparator as also having a gain, Gc ' in series with the added amplifier that varies keeping the forward gain of the modulator (a feedback system) equal to unity. In other words, if we increase the amplifier gain G we get an effective decrease in the comparator's gain Gc' 6.2.4 Improving Linearity Using an Active Circuit Figure 6.28a shows the integrating topology we've used in our passive modulator. The input to the comparator, Vinl , in this circuit can be written as .1 lin' j(J)C (6.59) In (b) we've replaced the passive integrator (the capacitor) with an active integrator. We can write - G. Vim and · lin = Vin( Vc Jij(J)C (6.60) If the amplifier's gain, G, is big we can write .1 Vc "" -lin' j(f)C (6.61) ~f :t? iin Comparator (a) ~>- c . I ~ Vim" .comparator _~ Vc· ~ (b) .Figure 6.28 Replacing the passive integrator (a) with an active integrator (b). 226 CMOS Mixed-Signal Circuit Design where we've switched the inputs of the comparator to account for the inversion. Remember our goal is to keep v;nl constant so that we reduce the noise/distortion term in, for example, Eq. (6.58). We can then write Vi"''''f'.roC . G (6.62) As G -; -___-V"-2--; + Vout Vow Figure 6.33 Second-order noise-shaping modulator with a single feedback path (bad). Consider the single-feedback path modulator seen in Fig. 6.34. We've added a resistor in series with the feedback capacitor in the first integrator. We can now write Vi =_(Vin~vour) 'C~C+R) (6.69) I) V2 -(~) 'jroC == (Vin -Vout) 'jro~C' Cro~C+ (6.70) Voul = STP ~-~ , jroRC + 1 . NTF ~--~ 2 (jroRC) V 'Vm + 2 . Qe (jroRC)2 +jroRC + I (jroRC) +jroRC + I (6.71) The benefits of this topology, other than the better SNR and only a single feedback loop, are that we can select RC so that the STF is closer to one over a wider bandwidth and there is smaller delay between the input and output of the modulator (which is of critical importance in a K-path topology). Setting, for example, RC 2Ts 2!fs (6.72) Chapter 6 Data Converter Design Basics 229 Figure 6.34 Second-order noise-shaping modulator, version II. this equation reduces to, for frequencies of interest much less than the Nyquist frequency of1,12, (6.73) Signal-la-Noise Ratio Following the procedure for calculating SNR seen in Sec. 6.1.1 B B V;oise,RMS 2 f INTFU)l2IVQeU)12 ·df=2· 12F . f(21t/-RC)4 .df o :Is 0 (6.74) V;Oise,RMS = 2 . . (2rcRC)4 . 12ls 5 Again with B =f sl2K we get Vn2<)l,se,Rm"S, == 12 • (2'T.rRC)4 . ~ 80. K5 SNRideal V Ifi 20 . log V p == 6.02N + 1.76 20 log (21tR!8C0-/,)2 + 20 logK5/2 noise,RMS 80 (6.75) (6.76) (6.77) Setting RC 2.69/fs (noting that we might have to increase the RC to avoid saturating the integrators, discussed in more detail in the next chapter) SNRideai 6.02N+ 1.76-30.10+5010gK 30.10 (6.78) (6.79) SNRideal:::: 6.02(N + Nine) + 1.76 (6.80) For every doubling in K above K = 4 we get 2.5 bits increase in resolution or 15 dB increase in SNRideQI' To estimate the order, L, of the decimating filter let's write, see Eq. (6.21), (6.81) For 16 :s; K:S; 1024 we can use a second-order filter, L 2. 230 CMOS Mixed-Signal Circuit Design Example 6.5 Simulate the operation of the second-order NS modulator in Fig. 6.34 clocked at 100 MHz, with RC = 20 ns, and decimated with a filter having a transfer function [11 ~:-~16r Estimate the bandwidth, B, of the output signal, the increase in the number of bits, ;¥mc' and SlVR,deor The simulation results are seen in Fig. 6.35. The final output clock frequency is 6.25 MHz and the bandwidth of the desired signal, B, is 3.125 MHz. Using Eq. (6.79) we estimate the increase in the number of bits as 5. Using Eq. (6.80) the ideal SNR is 37.88 dB. Note that the number of bits coming out of the filter is 9 bits, the input I-bit word size increases 8-bits. We can throw the lower 5-bits out or throw the MSB out to divide by 2 and throw the lower 4-bits out Gust not continue to pass them along in the system since they are simply noise).• 960mV I V(vin] Vlout] VI"utt] anOmV 800mV 720mV 640mV 560mV 4aOmV 400mV 320mV 240mV 160mV OOmV , o.o~s O.7ps lAps 2.1ps 2.0ps 3.5ps 4.2p. 4.9ps 5.6ps 6.3ps Figure 6.35 Simulation results for Ex. 6.5. Discussion The second-order active NS modulator is the workhorse for analog-to-digital converters using noise-shaping. The increase in resolution of 2.5 bits for evety doubling in K is significant. This topology can also be used in a K-path configuration, Fig. 6.24, replacing the capacitor and amplifier (see simulation examples at CMOSedu.com). The challenge is keeping the forward delay through the modulator small (so the modulator remains stable). This dictates using simple op-amp topologies that are vety fast with moderate gains, e.g., self-biased diff-amps. Finally. for high-speed we focused on using K-path topologies. The drawback of this approach is the need for several clock phases whose rising edges are spaced by T/K. A delay-locked loop (DLL) can be used for generating these clocks and is straightforward to design. The benefits of the K-path approach are that the matching of the resistors undergoes averaging via the K feedback paths, the pulse rising/falling edges are made less important since relatively wide pulses are used in each feedback path, and there is an inherent filtering when we combine the outputs of the paths together. Clearly further research in the design of these topologies is warranted; however, we leave this work to the refereed literature and continue to focus on the fundamentals. Chapter 6 Data Converter Design Basics 231 ADDITIONAL READING [1] J. C. Candy and G. C. Ternes (eds.), Oversampling Delta-Sigma Data Converters, IEEE Press, 1992. ISBN 0-87942-285-8 [2] S. K. Tewksbury and R. W. Hallock, Oversampled, Linear Predictive and NOise-Shaping Coders of Order N> I, IEEE Trans. Circuits and Sys., Vol. CAS-25, pp. 436-447, July 1978. [3] H. Inose, Y. Yasuda, A Unity Bit Coding Method by Negative Feedback, Proc. IEEE, Vol. 51, pp. 1524-1535, November 1963 QUESTIONS 6.1 Suggest a topology for a passive-integrator NS modulator where the input and fed back signals are currents. Derive a transfer function for your design. Does your topology have the extra noise/distortion term seen in Eq. (6.12)? Why or why not? Simulate the operation of your design. 6.2 Simulate the operation of the NS modulator seen in Fig. 6.4a but using a 4-bit quantizer (ADC). Use a 100 MHz clock frequency and an input sinewave at 500 kHz (as used to generate Fig. 6.7). 6.3 Using Eqs. (6.14) and (6.17) compare the noise performance of passive NS modulators using a I-bit quantizer to those using a 4-bit quantizer. 6.4 Repeat Ex. 6.2 if C is changed to I pF and a 1 GHz clock frequency is used. Estimate the frequency where the output of the digital filter is -3 dB (0.707) from the input signal. Verify your answer with simulations. 6.5 Suppose the comparator used in the NS modulator and filter used in Ex. 6.2 has a 50 mV input-referred offset voltage. How will this offset voltage affect the conversion from analog to digital? Verify your answer with SPICE simulations. 6.6 Figure 6.36 shows the implementation of an op-amp using mixed-signal design techniques. Assuming the comparator is powered with a 1 V supply, simulate the circuit in the inverting op-amp confignration with the non-inverting input held at 0.5 V, a 10k resistor connected from the inverting input to the input source, and a feedback resistor of lOOk from the op-amp's output back to the inverting input (for a closed loop gain of -10). Set the input source to have a DC offset of 500 mV, and a peak-to-peak amplitude of 20 mV at 500 kHz. Explain how the circuit operates. Note that using an active integrator, instead of the passive integrator results in more ideal behavior (less variation on the op-amp's inputs). inverting input 100 pF I non-inverting input 1 GHz Op-amp's output Figure 6.36 An op-amp implemented using mixed-signal techniques . 232 CMOS Mixed-Signal Circuit Design 6.7 In your own words explain why dead zones in the second-order passive modulator seen in Fig. 6.17 are less of a problem than the first-order modulator seen in Fig. 6.4a. 6.8 Verify, using simulations, that the modulator seen in Fig. 6.20 suffers from capacitor mismatch while the one in Fig. 6.22 does not. 6.9 What is a time-interleaved data converter? Why is a time-interleaved converter different from the converter seen in Fig. 6.24? 6.10 Show the details of how to derive the transfer function of the path filter seen in Fig. 6.24. 6.11 Repeat question 6.7 if an active integrator, Fig. 6.28, is used in place of the passive integrator. 6.12 Repeat Ex. 6.5 if K is changed from 16 to 8. Chapter 7 Noise-Shaping Data Converters In this chapter we continue our discussion of first-order noise-shaping data converters. We start out discussing first-order topologies and then move on to higher-order topologies including second-order noise-shaping and cascaded modulators. 7.1 First-Order Noise Shaping The block diagram of a NS feedback modulator is shown in Fig. 7.1. At the end of Ch. 5 we showed, but in the s domain, that the output of the modulator, voulz), can be related to the input, vin(z), and the ADC's quantization noise, VQe(z), by NTF(z) A(z) r---'--, 1 Vout(z) = 1 + A(z) 'Vin(Z) + 1+ A(z) .VQe(z) (7.1) where, as in the last chapter, STF(z) is the signal's transfer function and NTF(z) is the noise's transfer function. Delta ! In Vin(Z) + Analog~ Sigma Integrator DAC Vaut(z) Out Digital Figure 7.1 Block diagram of a noise-shaping (NS) modulator. Consider what happens if A(z) is an integrator (implemented using a DAI, Sec. 2.2.3) as shown in the figure. Equation 7.1 becomes voul(z)=Z-lVin(z)+(1 Z-l),VQe(Z) (7.2) 234 CMOS Mixed-Signal Circuit Design This equation is important! It shows that the input signal simply passes through the modulator with a delay while the quantization noise is differentiated (see Fig. 1.20 for the magnitude response of a digital differentiator with a transfer function 1- Z-I). We can think of the noise differentiation as pushing the quantization noise to higher frequencies. We'll come back to how NS affects the quantization noise spectral density, VQe( f), in a moment. But first let's attempt to understand what's happening here. In Fig. 7.1 the summer takes the difference (Delta) between the input signal and the fed back signaL The integrator accumulates or sums (Sigma) this difference and feeds the result back, via the ADC and DAC, to the summer. This forces the output of the modulator to track the average of the input. Sometimes the fed back signal will have a value greater than the input signal, while at other times the fed back signal will be less than the input signal. The average signal fed back, however, should ideally be the same as the input signal. Note that this type of NS modulator is often called a Delta-Sigma or Sigma-Delta modulator. Also, at this point, we should see the need for the averaging filters discussed earlier. A circuit implementation of a first-order NS modulator is shown in Fig. 7.2. For the moment we use a single-bit ADC and DAC (both implemented using the clocked comparator) for gain linearity reasons (discussed in more detail later). The analog voltage coming out of the integrator is compared to the common-mode voltage (this is our I-bit ADC) using the comparator. For the I-bit DAC a logic-O has an analog voltage of 0 V, while a logic-I has an analog voltage of VDD I V here) so that the comparator's output can be used directly (fed back to the DAI). - - - - * - - - - - - 1 ' :1 + Clod"d 00""'''''0' Figure 7.2 Circuit implementation of a first-order NS modulator. The comparator is clocked on the rising edge of og2 - 3010gK 6.02 5.17 (7.16) Solving this equation results in L being greater than or equal to 2. In general, we ean write L= l+M (7.17) where M is the order of the modulator. For a first-order modulator we use two stages in the averaging filter, or, -KJ2 H(z) = [ _1-I=-.L. K l-z-1 (7.18) In the next section we discuss second-order NS modulators (M= 2). For these modulators we use a Sinc averaging filter with L = 3. Example 7.2 Comment on the implementation of the digital decimation filter for the modulator described in Ex. 7.1. Assume the final output clocking frequency is 100 MHzll6 or 6.25 MHz. The transfer function of the digital filter is H(z)= [ _1 z-_16J2 1-z·l 240 CMOS Mixed-Signal Circuit Design The block diagram of the filter is seen in Fig. 4.32 using 4 stages and L = 2. The increase in resolution through each (I +z-I)2stage is 2 bits (see Fig. 6.10 for the filter when L = I). The resolution calculated in Ex. 7.1 was 6.14 bits, which we round up to 7-bits. Because the output of the digital filter is 9-bits (8-bits through the four stages plus the I-bit coming out of the modulator), we drop the lower two bits (divide by 4) to get our final 7-bit resolution.• Next let's examine how filtering with a Sinc filter affects the SNR of the data converter. Remember the SNRideal was calculated in Eq. (7.14) assuming the modulation noise was strictly bandlimited to B. Figure 7.8 shows the PSD of the NTF2(f)·1 VQe(f)12 (the modulation noise) of the first order NS modulator. Also shown in this figure is the shape of the averaging filter's magnitude response squared, Eq. (4.20). Here we are showing the shape of a filter with L 2 (set by Eq. [7.17] for a first-order modulator) and K = 16. We limit our range to /, 12. 4 / f) 111(f)12 = sin ( Krr) .L l. f, "" [ K . ( ] ,(. fslK B, Ideal maximum input frequency Figure 7.8 Showing modulation noise and filter response. We can calculate the R..\1S quantization noise on the output of the Sinc filter in a cascade of a first-order modulator and an averaging filter using (see Sec. 6.1.2) Ifwe let S ff,l2 V~e,RMS = 2 INTF(f)l2·1 VQe(f) 12 • 111(f)12 • d/ o (KnL) f,l2 sin4 f nt/)' . V~,RMS == 12/8 8 • K4 ' 0 sin2( d/ nt, then this equation can be written as (7.19) (7.20) V2 Qe,RMS ,, S4 sin (KS) de o sin2S (7.21) Chapter 7 Noise-Shaping Data Converters 241 and finally, VLSB (7.22) JT2 This equation should be compared to Eq. (7.12), which was derived assuming the digital filter was ideal with a bandwidth of B. The SNR resulting from using a first-order (M = I) NS modulator and a second-order (L = 2) Sinc averaging filter is SNR sinc = 6.02N + 1.76 - 3.01 + 30 10gK (in dB) (7.23) Comparing this to SNRideal given in Eq. (7.14), we see that using a Sinc filter for averaging results in only a 2.16 dB difference (increase) in SNR over the ideal filter. If we remember that using a Sine filter results in a droop in the desired signal, Fig. 2.31, the SNR will be lower than what is predicted by Eq. (7.23). (Note that an analysis of higher order modulators using Sinc averaging filters would show that as long as Eq. [7.17] is valid the deviation from SNRidea/ is negligible.) 7.1.4 Pattern Noise from DC Inputs (Limit Cycle Oscillations) In the ideal Nyquist-rate ADC, a DC input signal results in a single output code. In other words the output code doesn't vary. In a NS-based ADC the output code varies as seen in Fig. 7.3 (the average of the output is equal to the input signal). When this code is applied to a digital filter the output of the filter shows a ripple or variation. Unfortunately, this ripple on the output of the filter can cause noise in the spectrum of interest. The frequency of the ripple and the amplitude of the ripple depend on the DC input value. Figure 7.9 shows an example of this ripple. The input signal for the modulator in Fig. 7.2 is 0.5 V (the common-mode Voltage) while the modulator is clocked at 100 MHz. The modulator's output is a square wave of alternating ones and zeroes. The first harmonic of this signal is at half the clocking frequency or, in this example, 50 MHz. Since the ripple frequency lies outside our base spectrum (which, from Ex. 7.2, is from DC to 3.125 MHz) it will not, in a significant way, affect the SNR. (The digital filter will likely have a zero in its transfer function that falls at half the clocking frequency eliminating the ripple altogether and resulting in a constant filter output value.) If we increase the input signal to 510 mV we get the digital filter output ripple seen in Fig. 7.10. A component of the ripple is at a 600mV,----,--,----,.--,----.:..c:;:.::L---,--~___:_-__,____, 550mV .......~ ...... . 4oomvl...~+_-t--+-+--i___;_-_T_-,___;_-....J Ons 10ns ZOns JO~s 40n5 SOns 60ns 70ns 80ns 90ns Figure 7.9 Showing how filtering the output of a modulator results in ripple. 242 CMOS Mixed-Signal Circuit Design S~OmV-,---_ _ _ _ _ _---,------,-V!::[o:::utf),,------,---_ _ _,----_ _---, : . S20mV :·::::::::::t.~~~.~s ::j:::::::·::::: SOOmV ,,, ,,, 580mV , , ---------~---------------,------------ , ---------------.-- ---------------.--------------- ' 5S0mV .. fit!IIII!!!I!!/ •. 5~OmV 520mV ·mmlj.·I·..:·..:·..: .... ~m~mjJ~l:it 500mV ..... . i ~80mV ~SOmV ~~OmV On. 200ns 400n6 600ns 800ns Figure 7.10 Showing a lower frequency ripple in the modulator's output frequency that is roughly 1/500 ns or 2 MHz, which is well within our base spectrum. The resulting tone will lower the SFDR and the SNR of the data converter. The question now becomes, "How do we minimize the possibility of unwanted tones appearing in the data converter's output spectrum?" Looking at the digital output ofthe modulator we see that it would be better to spread or flatten the repeating data out so that we don't get repeating tones (as discussed in the dead zone discussion in Sec. 6.1.3). Although we may still have a tone, or repeating sequence, at a frequency in the base spectrum, the amplitude of the tone will be well below the VQe,RMS of the data converter (and so it won't affect the SFDR of the data converter). In order to accomplish this spread or randomization we can add a noise dither source (see Sec. 5.3.3) to our basic NS modulator, as seen in Fig. 7.11. By applying the dither to the input of the comparator (quantizer) the dither will be noise-shaped like the quantization noise (the spectral content of the dither, Eq. [5.62], is less important). ~l , VCM\ ~~~lP-f-- Dither Source Ip VCM ~l VoUI VCM >------1+ + Figure 7.11 Adding a dither source to a first-order NS modulator. Finally, note that unwanted tones are usually not a problem if the input signal is busy and random (not DC as discussed in this section). Later in the chapter, we discuss second-order modulators that utilize two integrators. The second integration helps to spread the repeating sequences out over a longer period of time so that, hopefully, negligible unwanted tone energy is present in the base spectrum. Chapter 7 Noise-Shaping Data Converters 243 7.1.5 Integrator and Forward Modulator Gain So far we haven't discussed the shape or amplitude of the integrator's output. Because we are using near-ideal components in our simulations, we haven't seen any limitations due to the fmite op-amp output swing. Figure 7.12 shows the integrator's output for the input and output signals shown in Fig. 7.3 (using the modulator of Fig. 7.2). Clearly the output swing of the op-amp is beyond the power supply rails. If the transistor-level model of the op-amp were to replace the ideal op-amp, the integrator's output would saturate at voltages less than VDD (= 1.0 V here) or greater than ground. While in some situations op-amp saturation is not necessarily bad (the gain of the integrator goes to zero), it is desirable to understand how decreasing fonvard loop gain affects the performance of the modulator. Note also, in Fig. 7.12, that the output of the integrator makes the largest change when it passes through the comparator reference voltage, VCM = 0.5 V, since the fed back signal, the comparator output (a full-scale signal), is input to the integrator. Power supply range. Figure 7.12 Output swing limitations in the op-amp (integrator). Consider the linearized model of our first-order NS modulator shown in Fig. 7.13. The gain of the integrator, see Eq. (2.103) or Fig. 2.55, is given by GI= CF (7.24) We have also drawn the comparator with a gain. Up until this point we have assumed the gain of the comparator is unity. We'll comment on this more in a moment. Let's define the modulator's forward gain as (7.25) We can rewrite Eq. (7.2) using this gain as VOli/(Z) --=--=---1-) . VQe(Z) (7.26) If GF approaches zero (the integrator saturates while the comparator gain stays finite), then the output of the modulator is the sum of the integrated input and the quantization noise. (This is bad.) Since the quantization noise is not spectrally shaped it will be difficult to filter the modulator's output to recover the input signal. If the forward gain is 244 In .x(z) CMOS Mixed-Signal Circuit Design Y(z) Out Figure 7.13 Block diagram of a NS modulator showing forward gains. greater than two, then, as seen in Fig. 4.38 and the associated discussion, the poles of the transfer function reside outside the unit circle and the modulator will be unstable. We can restrict the values of the forward gain to (7.27) Ideally, however, the gain is one. Example 7.3 Show, using SPICE simulations and the modulator of Fig. 7.2, that an integrator gain of 0.4 will result in an op-amp output range well within the power supply range. Figure 7.14a shows a schematic of the modulator with G1 0.4. Figure 7.14b shows the output of the integrator (the output of the op-amp) in the modulator of part (a) with the input sinewave shown in Fig. 7.3. The output swing is limited to roughly 80% of the supply range. For general design it is desirable to set our integrator gain to 0.4. This ensures our integrator doesn't saturate unless the input to the modulator goes outside the supply voltage range. It's interesting to note that in both modulators, Fig. 7.2 and Fig. 7.14a, the forward gain is unity. This is a result of the effective gain of the comparator changing forcing the forward gain, controlled by the fed back signal, to unity. What this means is that our modulator functions as expected with a signal gain of one (Eq. [7.2] is valid) whether G1 is 1 or 0.4. Next we discuss how this change in comparator gain occurs.• Figure 7.15 shows the transfer curves for the comparator. The x-axis, the comparator input, is the output of the integrator in our modulator. Shrinking the integrator's output swing while holding the output swing of the comparator at the supply rails (1 V) results in an increase in effective comparator gain. This gain variation, with the integrator output swing, helps to set the forward gain of the modulator to precisely I. We can write this using equations as Integrator gain, G I Comparator gain, Gc '-'''~' , Integrator output Comparator(modulator) output Modulator input Integrator output Modulator output Modulator input (7.28) If the modulator is functioning properly, then the average value of the modulator output will be equal to the modulator input and thus GF = I. It's interesting to note that this result Chapter 7 Noise-Shaping Data Converters 245 4>1 Ip I VeM Vaut >--+----,------1 + Clocked comparator (a) (b) Figure 7.14 (a) First-order NS modulator with an integrator gain of 0.4, and (b) the output of the op-amp. (precise integrator gain isn't important) will apply to any integrator that is directly followed by an ADC. Before leaving this section, let's point out a couple of problems with a noise shaping modulator that uses a multibit ADC, Fig. 7,16. Since the output of the integrator is the input signal to the ADC, the limited integrator output swing will directly effect the range of ADC output codes. Limiting the range of ADC output codes will then limit the allowable range of modulator inputs unless scaling is used (shifting the output codes or :> 1.0 Gain is the slope ofthese lines. o +=-~----'--+-----1- o 0.5 1.0 Input signal :> Comparator input, V Figure 7.15 Comparator gain as a function of input voltage. 246 CMOS Mixed-Signal Circuit Design Digital output code 111 110 101 100 Dashed lines indicate ADC gain 011 010 001 OOO~>~--------------------~ o lI8 2/8 3/8 4/8 5/8 6/8 7/8 8/8 Analog input voltage (integrator output) Figure 7.16 A 3-bit ADC. sizing of capacitors in the DAI). Next, notice in Fig. 7.16 that the variation in the gain of the ADC, with input signal, is more limited than the gains attainable with the simple comparator seen in Fig. 7.15. Limiting the range of ADC gains can result in modulator forward gains that are not exactly unity. This is especially true at high input frequencies where the gain of the integrator is low. However, if the integrator gain is high, the effective gain of the ADC is not important. The point here is that using a multibit ADC will increase the open-loop gain requirements of the op-amp used in the integrator. 7.1.6 Comparator Gain, Offset, Noise, and HystereSiS It's of interest to determine how the performance of the comparator influences the operation of the modulator. Both the comparator's offset and input-referred noise, Fig. 7.17a, can be referred back to the modulator's input, Fig. 7.17b. By doing so we can determine how they effectively change the input signal seen by the modulator. As seen in Fig. 7.17, the high gain of the integrator, A( f), reduces the effect of the comparator's noise and offset on the input signal. For example, if the gain of the integrator at DC is 1,000 and the offset voltage of the comparator is 50 mV, then the input-referred offset is only 50 !-lV. Comparator's input-referred . noise and offset, Vn,comp (f) Input-referred nOIse and offset, Vn,comp(f)/A(f) I~nm~p~~afria\t/ou r t Comparator Integrator Integrator (a) (b) Figure 7.17 (a) Referring the comparator offset and noise to (b) the input ofthe modulator. Chapter 7 Noise-Shaping Data Converters 247 In order to determine the minimum gain and maximum allowable hysteresis requirements of the comparator, let's review Fig. 7.14. We see that when the output of the comparator changes states, the output of the integrator changes by at least Change in integrator output G/·(VDD VC,I1)=~~' VREF+;VREF (7.29) For the modulator of Fig. 7.14 this equation can be evaluated as 0.2 V. As long as the hysteresis is much less than this value and the gain of the comparator (110.2 or 5) is large enough so that the comparator can make a full output transition with this input difference, then the modulator will function properly. Very simple, low-performance comparator designs can be used while not affecting the modulator's performance. 7.1.7 Op-Amp Gain (Integrator Leakage) Now that we've discussed the gain of the comparator, let's determine how high the open-loop gain of the op-amp must be for proper integrator action. With low op-amp gain, some of the charge stored on the integrator's input capacitor, C1 , is not transferred to the feedback capacitor, CF • This loss of charge is sometimes referred to as integrator leakage. The charge on the input capacitance effectively leaks off when it is transferred to the feedback capacitance. We can write the open-loop, frequency-dependent gain of the op-amp as Aoi f). The output voltage of the op-amp is then Vout=AOL(f)(v+-v_), where v+ is our common-mode voltage VCM (the noninverting terminal of the op-amp), see Fig. 2.54, and v_ is the op-amp's inverting input terminal. Following the procedure to derive Eq. (2.1 02), we can rewrite Eq. (2.100) with finite op-amp gain as (v Q2 C/ CM- vAouOt[LnT(fs)1 - V 2 [nT ] s ) (7.30) or, rewrite Eq. (2.1 02) to include the effects of finite op-amp gain to get Cl . VI (z) . V2(Z) (I CF C, I ) +Cr.AOLU) -z-I (7.31 ) Using this result in Eq. (7.1) and, as discussed in the last section, assuming the forward gain of the modulator, GF , is one gives (7.32) The gain error term ._1_ f.gain CF AoL(f) (7.33) is ideally zero so that Eq. (7.32) reduces to Eq. (7.2). Note that reducing the integrators gain, CllCn reduces the gain error while increasing the gain required of the comparator. Note also that the denominator term is common in both the signal and the noise. This term results in a data converter gain error (it behaves as if it were an op-amp offset voltage that is a function of the integrator's output amplitude [which results in the gain error] and frequency), but it will not affect the modulator's SNR. In order to determine the 248 CMOS Mixed-Signal Circuit Design increase in the modulator's output noise (the change in the shape of the modulation noise) we need to look at the noise transfer function including the effects of the gain error (7.34) or, in the frequency domain, (7.35) Following the same procedure used to arrive at Eq. (7.12) and assuming constant op-amp gain, AoL(f), from DC to B, results in 1 (Is 2 ViSB [ ,,2 1 3 + 2 f, ] 3" VQe,RMS 2· 121s . 4(1 +egain)f; . \2KJ Egain ' 2K (7.36) noting that if egain 0, this equation reduces to Eq. (7.12). If we assume the contribution to the noise from the error term squared, e;ain, is small, which is valid for op-amp gain AoL(f) > K (the oversampling ratio) (7.37) over the frequency range of DC to B, then we can rewrite Eq. (7.13), to include the effects of finite op-amp gain, as fi = SNRgerr 6.02N + 1.76 - 20 log + 20 logK312 10 log(l + egain) (7.38) The largest degradation in the SNR, resulting from integrator leakage, can be estimated as 0.5 dB if K:?: 8 (egain '" 1/8 neglecting GJ ). The minimum gain· bandwidth product of the op-amp is estimated as Op-amp unity gain frequencY'!un = K· B =Is 12 (7.39) assuming the op-amp is rolling off at 20 dB/decade at B (a dominant pole compensated op-amp). Otherwise, the minimum gain of the op-amp can be estimated simply as the oversampling ratio, K. In order to illustrate typical op-amp requirements, let's consider the modulator of Fig. 7.14 with K = 16 and B = 3.125 MHz (see Ex. 7.1). The fun of the op-amp is estimated, using Eq. (7.39), as 50 MHz. If the open-loop response of the op-amp starts to roll off at 10kHz, then the DC gain of the op-amp must be at least 5,000. However, we could also use an op-amp with a DC gain of 100 (remembering low integrator gain increases the undesirable effects [noise and offset] of the comparator on the performance ofthe modulator) that rolls off at 500 kHz. 7.1.8 Op-Amp Settling Time Equation (7.39) can be used, for the moment, to provide an estimate for the settling time requirements of the op-amp in a first-order modulator. Assuming the settling time is linear, and not slew-rate limited, we can write the change in the op-amp's output assuming a dominant pole compensated op-amp as Vaul == Vaulfinal(] _1_ 2rrfu . ~ (7.40) Chapter 7 Noise-Shaping Data Converters 249 where, for the DAI (see Fig. 7.18), the feedback factor is ~= CF CF+CI (7.41 ) The feedback factor is 0.714 in the modulator of Fig. 7.14. The output of the DAI, vaUl' must settle in a time, t « Ts 12), to some percentage of an ideal value, VaUl/inG'. Solving for this percentage using Eqs. (7.39), (7.40), and (7.41) and assuming Tsl2 = t results in (7.42) The output will only reach 67% of its ideal final value in the modulator of Fig. 7.14 when the op-amp used has a unity gain frequency of/, 12. V out Figure 7.18 The feedback factor in the DAI. In deriving Eq. (7.42), we used an op-amp unity gain frequency specified by Eq. (7.39) to determine the settling response of the integrator. If the settling is linear then incomplete settling will result in a constant DAI gain error (0.67 above). Every time the output changes it will change by some constant percentage of its ideal value. Rewriting the transfer function of our DAI to include this constant gain error results in Settling gain error, Gs Vout(Z) = CI -C . ' 1 _~A.(f, jI")' ( - e P uni') VI (z) . z-1/2 - . 1-1 V2(z) F -z (7.43) Full, or complete, settling requires that the op-amp's unity gain frequency, fun , be much larger than the sampling frequency, /, (in other words we can't use Eq. [7.39] to specify the required bandwidth of the op-amp if settling time is important). The constant gain error, resulting from incomplete settling, can be tolerated in the first-order modulator because the integrator is directly followed by a comparator, as discussed earlier. In some of the modulator topologies, though, the integrator is not followed by a comparator so settling time becomes more important. In order to determine to what percentage the integrator output must settle in these topologies, a gain term, say Gs' is added to the linearized block diagram of the modulator (integrator). The transfer function of the modulator is then evaluated to determine the allowable values of Gs for the application. It's important to realize that we are assuming the op-amp doesn't experience slew-rate limitations. If slewing is present, then the added gain term, in Eq. (7.43), will not be a constant and will introduce distortion into the modulator's output spectrum (whether a comparator follows the integrator or not). 250 CMOS Mixed-Signal Circuit Design 7.1.9 Op-Amp Offset The operation of the DAI is subject to the op-amp's offset. It can be shown that this offset will effectively add (or subtract) from the common-mode voltage, VeAl' and thus effectively shift the input signals upwards or downwards. The resulting modulator output will then show an offset equal to the op-amp's offset. In order to circumvent this problem, offset storage can be used in the integrator. 7.1.10 Op-Amp Input-Referred Noise Here we discuss how the DAl's unwanted noise contributions affect the SNR of the modulator, assuming we know the DAl's input-referred noise PSD V;,DAl!). Figure 7.19 shows the modulator's input-referred noise source, Vn,ckt(!), in series with the input JHz , signa\. This noise source, with units of VI includes both the integrator's and the comparator's contributions. However, as discussed earlier, the noise contributions from the comparator are usually negligible because of the high-gain of the integrator. J Modulator's input-referred noise, Vn,ckt(f) =: V;,DAI(f) + V;,comp(f)IA 2(f) \ . In ~ Integrator Comparator Figure 7.19 The modulator's input-referred noise contributions from both the comparator and the integrator. Because the modulator's input-referred noise adds directly to the input signal, we can use the derivations developed earlier in the chapter. As specified in Eq. (7.2), the modulator's input, and thus its input-referred noise, pass through the modulator with a delay of Z-l, If we assume the modulator's input-referred noise is white and bandlimited to Is 12 such that Ji Vn,ckt(f) =: for!-=--:---.,---,--,----,~.::.:!.;-__:-__, O.9V D.8V D.N O.6V O.5V 0.411 O.3V O.2V D.1V O.OV - - i - i - - + - - + - - i - - - r - - t j -- - r - - - - j 0.0115 0.2115 0.4115 0.61/5 1.6115 Figure 7.22 Outputs of the fully-differential first-order modulator after RC filtering. Chapter 7 Noise-Shaping Data Converters 253 7.2 Second-Order Noise-Shaping If we review Eq. (7.2), we might wonder if further filtering of the quantization noise, VQe(Z) , can result in an improvement in the data converter's SNR over an input signal bandwidth B. The second-order modulator's output shows a double differentiation of the quantization noise = Vollt(Z) Z-IVin(Z) + (1 - z-J)2 VQe(Z) (7.49) The modulation noise may then be written, see Eq. (7.8), as nZ INTF(f)i2 . IVQe(f) I2 = ~~2f. .16sin4 (7.50) Figure 7.23 shows a comparison between the modulation noise of first- and second-order NS modulators. Notice that the modulation noise is "flatter" in the bandwidth of interest. 1.0n"',.--,----,="--,--,---,---"'="-~__, O.9:,.v ..........--~ "".,' •.••v·Seeond-order moduiatio~ no·ise..l I.UinV fJ.. ~ ~ .: .,..' VCM Vout f':~: '\; Vin + Figure 7.28 Implementation of the second-order modulator of Fig. 7.27c. 7.2.2 Integrator Gain As we showed in Eq. (7.28) for the first-order modulator, the forward gain of a second order modulator will also be unity when the modulator is functioning properly. We now need to discuss how to select the integrator gains to avoid hamaful integrator saturation. If noise and offsets were not a concern, as shown in Fig. 7.17 and the associated discussions, then we could make our integrator gains very small (ultimately limited by imperfections in the switches such as clock feedthrough and charge injection). In a practical modulator, integrator saturation (the integrator's gain going to zero) can also lead to modulator instability, as shown in Eq. (7.27), and the associated discussion. Figure 7.29 shows the integrator outputs for the modulator of Fig. 7.28 if both integrator gains are set to OA. Notice that both outputs go outside the supply voltage range. If we replace the ideal op-amps in the simulation with transistor-based op-amps, the integrator outputs will saturate at some voltage within the supply range. This saturation can be thought of as noise and ultimately limits the data converter's SNR. Integrator saturation can be avoided by limiting the input signal range, designing with small integrator gain, and using op-amps that have a wide output swing. Supply range Figure 7.29 Showing integrator outputs in a second-order modulator with the integrator gains both set to 0.4. 258 CMOS Mixed-Signal Circuit Design For a more quantitative view of how the gains in a second-order NS modulator affect performance, let's consider a couple of different topologies. Figure 7.30 shows the block diagram of the second-order NS modulator topology of Fig. 7.25, with an integrator gain coefficient, Gp and a comparator gain, Gc ' added. Deriving the transfer function of this linearized model with GF = GI • Gc results in (7.58) The poles of this transfer function are located at J{l- = Zpl,pZ (1- GF) ± GF)2 (1- Gp) (7.59) We know that for the modulator to remain stable the poles must reside within the unit circle. This means that our values of forward gain are restricted to (7.60) Again, if the modulator is functioning properly, GF = I (because of the comparator's gain variation as seen in Fig. 7.15 and the associated discussion). Vvut(Z) Out Figure 7.30 Block diagram of a second-order feedback modulator with gains. We should make some observations at this point. Reviewing Eq. (7.27), we see that the allowable range of forward gain, in the first-order modulator, is larger than the allowable range in the second-order modulator. However, as long as the integrators don't saturate (Gj doesn't approach zero), stability for either modulator is easy to attain. An analysis of the stability of higher-order modulators show that the range of allowable forward gains decreases with the order of the modulator. For example, a third-order modulator can have a forward gain of at most 1.15. Finally, notice that the input signal range is more restricted for the second-order modulator, in order to avoid integrator saturation, as seen in Fig. 7.29. We'll discuss methods to attain wider input signal range and more robust stability criteria by adjusting the feedback gains later. Notice that we are treating our modulator as a linear system even though it isn't linear; the comparator gain is a nonlinear variable. The linear approximation is useful in order to give an idea of the stability of the modulator under certain operating conditions. Generally, a DC input is applied to the modulator in the simulation, while lowpass filters Chapter 7 Noise-Shaping Data Converters 259 are added to determine the average eomparator gain, Gc' Figure 7.31 shows this schematically. Assuming we know GJ (the gain coefficient ofthe integrators), we ean then look at the stability and forward gain of the modulator for varying DC input signal voltages. Vine Voutc Figure 7.31 Simulating the gain of the comparator. Next, consider the more generic block diagram of the second-order NS modulator shown in Fig. 7.32. In a moment we'll discuss how to implement the feedbaek gain, G3, using the DAr. The transfer function ofthis topology can be written as vou/(z) G G G = _ _ _ _ _ ~ t ~ 2~c ' ---2.~~_ _~~::':"':"-'-_ _ 1+ ·(GIG2Gc+G2G3Gc-2)+ (7.61) }-....-+-...v.:oAz) Out Figure 7.32 Generic block diagram of a second-order NS modulator. Notice that if G 1 = Gz G3 Gc = 1 (where G 1G2Gc Gp), then this equation reduees to Eq. (7.49). The poles of this equation are loeated at = 2 - GI GzGc Zpl,p2 G2G3Gc ± J(2 - Gl GzGc - GzG3Gc)2 -4(1- GZG3Gc} 2 (7.62) When the modulator is funetioning properly we require the (linearized) coefficient of the input, vm{z) in Eq. (7.61), to be unity 1-1 I G (z Zpl )(z Zp2) (7.63) 260 CMOS Mixed-Signal Circuit Design Again, if we set Gl ::: G2 ::: G3 ::: 1 (and Gc = 1), then the poles are located at DC, that is, Zpl,p2 0 (7.64) Equation (7.62) is useful to estimate the modulator's stability when scaling amplitudes by adjusting the integrator gain coefficients, Gj , G2, and G3• implementing Feedback Gains in the DAf Consider the modified DAI shown in Fig. 7.33. Notice that if Cn Cn, this topology reduces to the DAI shown in Fig. 2.54. Also note that some of the switches can be combined to simplify the circuitry. Assuming that the output is connected. through the 1) quantizer in a NS modulator are increased SNR (see Eq. 7.73), better stability (the modulator behaves closer to the linearized theory developed in this chapter), fewer spectral tones, and simpler digital-decimation filter. The drawbacks of using multibit topologies, are the increase in ADC complexity (the ADC must be a flash converter) and the need for the DAC to be accurate to the final accuracy of the modulator. The ADC errors, like gain errors in the integrators, are less important since they are in the forward, high-gain path of the modulator. Simulating a Multibit NS Modulator Using SPICE Figure 7.44 shows a circuit-level implementation of a first-order, multibit, NS modulator using a 4-bit ADC and DAC. Figure 7.45 shows the SPICE simulation outputs of this modulator. Most of the design effort, when developing multi-bit modulators, goes into the design of the feedback DAC. Because it is nearly impossible to design highly accurate (say l2-bits resolution or better) DACs without trimming, or some sort of error correction, methods have been developed that attempt to randomize DAC errors. If the errors appear as a random variable, they may appear as white noise in the output spectrum and not affect the SNR of the data converter. Figure 7.46 shows one possible implementation of a DAC. This DAC utilizes resistive unit elements, resistors laid out in a square that connect, on one side, between VDD and ground while the other side connects to a rotating switch connected to the analog output. In other words, in one case we connect VDD to one comer of the resistor 270 CMOS Mixed-Signal Circuit Design ~l ~2 _\ ~ Jp f \VCM I T~ O.4p Is == 100 MHz VREF+ == VDD ~lClk ~ VallI In VREF =: 0 In '-------' Figure 7.44 Circuit implementation ofa first-order multi-bit NS modulator. cube and ground to the opposite corner (assuming VREF+ = VDD and VREF 0). There exist two voltage dividers along each of the sides of the resistor square. The output of the DAC can change from zero, to (l/8)VDD, to (2/8)VDD, ... up to (8/8)VDD. Depending on the output of the decoder, one tap from each side is fed to the analog output. Because there are two sides, the outputs from each side are combined and effectively averaged. 990mV'~-,-------,:..!.:-"""-,.---,---:--........,,----,--=""T---,.---, 900mV 810mV 720mV .. tilOmV 450mV OmV+---~-+---r-4--~~---+-~--'-~ o.Ops O.4ps O.Bps l.Zp. 1.6ps 2.0ps 2.4ps 2.8115 3.2p.s l.6ps 4.0p. Figure 7.45 Output of the multi-bit modulator in Fig. 7.44. The purpose of the counter is to vary the connections of VDD and ground around the outside of the resistive divider to randomize variations in the output voltage due to resistor mismatch. In order to understand this in more detail, consider a constant DAC output voltage of VDDI2. As the counter changes output values, so do the connections to VDD and ground in the resistor string. In order to keep a constant output voltage of VDDI2 the switches in the center of the DAC move accordingly based on the output of the counter and the input to the decoder. In this way variations in the resistors, hopefully, average out to a constant value. With a little thought the reader can think of other schemes to attempt to randomize the errors that are fed back and subtracted from the input. In all cases it's presumed, for these techniques to work correctly, that the DAC errors average to zero or a very small value. Chapter 7 Noise-Shaping Data Converters 271 Connected to VDD when counter output is 8 and connected to ground when counter output 0 Analog Output Switch Connected to VDD when counter output is 0 and connected to ground when counter output is 8 VDDbus Ground bus Figure 7.46 Implementation of a DAC for use in a multibit NS modulator. 7.3.5 Error Feedback The NS topologies we've discussed so far are sometimes called interpolative modulators since the signal fed back is the average of the input signal interpolated between known values of the modulator output (the average of the modulator outputs is the input signal). However, NS modulators were first introduced (see C. C. Cutler, "Transmission systems employing quantization," 1960, U.S. Patent No. 2,927,962 [filed 1954]) using the error feedback topology shown in Fig. 7.47. Error feedback topologies are not used in analog input modulators because errors in the analog subtraction directly add to the input signaL We can use this topology, however, in the implementation of a digital input demodulator (sometimes also called a modulator), as the subtraction is digital. Looking at Fig. 7.47 we note that by definition the difference between the input and the output of the quantizer is the quantization noise, VQ.(z). This noise is subtracted from the input after a delay (for a first-order modulator) resulting in (7.94) Note that the signal transfer function for an error feedback-based modulator is simply one; that is, STF(f) 1. For a first-order NS modulator we set F( z ) == Z-l (a register), which results in 272 CMOS Mixed-Signal Circuit Design Out VOIl'(Z) Out Quantizer Figure 7.47 Block diagram of an error feedback modulator. (7.95) A second-order modulator with a NTF(f) (I_Z-I)2 would use a feedback filter, noticing from Eq. (7.94) that NTF(f) = 1 - F(z) , of F(z) = 1-(1 (7.96) Implementation of a second-order NS modulator is shown in Fig. 7.48. Note that when trying to implement higher-order modulators using error feedback we run into the same problem we encountered when using an interpolative modulator, namely. instability resulting from a NTF that is too large at higher-frequencies. As with interpolative modulators, we can design the NTF to have a highpass response. In Vin(Z) VOIlI(Z) Out Quantizer Figure 7.48 Block diagram ofa second-order error feedback modulator. We've introduced the error feedback topology with the idea that it can be used in a modulator (demodulator) that performs digital-to-analog conversion. We first introduced a modulator for use in a DAC back in Fig. 7.5. At this point we need to answer the question, "Why is the NS topology of Fig. 7.47 a better choice for DAC implementation, in general, then the topologies of Figs. 7.5 and 7.41?" The answer to this comes from the realization that the quantizer and difference block in Fig. 7.47 can be implemented by simply removing lower bits from the digital input words. This is illustrated in Fig. 7.49. The resulting error feedback modulator will be simpler to implement than the modulators based on interpolative topologies. Figure 7.50 shows Fig. 7.47 redrawn to show the simpler implementation. Chapter 7 Noise-Shaping Data Converters 273 Nbits Out voutCz) Out N-Fbits Quantizer N bits N F bits vou/(z) F__b_it_S---t:~'-)- to 0.4 to avoid integrator saturation, as discussed earlier, we must set GIl as close to unity as possible. Using a unity gain coefficient results in a reduction in the modulator's overall dynamic range (see Fig. 7.12 and the associated discussion). Note that the input signal appears in the unwanted term in Eq. (7.106). It should be obvious at this point that we can add scaling parameters at various points in the modulator to attempt to maximize the modulator's dynamic range. Also note that the number of bits in the 1-1 modulator's output will be more than one bit (two bits if comparators are used in each first-order modulator). Chapter 7 Noise-Shaping Data Converters 277 Third-Order (1-1-1) Modulators By adding a third first-order modulator to our I-I modulator of Fig. 7.53, we get a 1-1-1 or third order modulator, Fig. 7.54. The output of the added third modulator can be written as V3(Z)=-z- IVQdz)+(l Z-I)VQe3(Z) (7.107) while the ideal output of the 1-1-1 cascade is given by vout(z) VI(Z)+ V2(Z) + V3(Z) Z-3Vin(z)+(I-z-I)3VQe3(Z) (7.1 08) Again, as we saw in Eq. (7.106), noise from the first modulator can leak through to the output and spoil the overall cascade's SNR. Indeed, if the leakage from the first modulator is large enough, we get no benefit from adding the third modulator. Notice, in Eq. (7.106), that the unwanted term exhibits first-order differentiation, (l-z-1). We might expect better overall performance, that is, less leakage if the first modulator is second order. The unwanted term would then exhibit second-order differentiation. Figure 7.54 Third-order (1-1-1) cascaded modulator. Third-Order (2-1) Modulators A third-order modulator formed by using a second-order modulator followed by a first order modulator is shown in Fig. 7.55. The output of the first modulator is given by (7.1 09) . _ _.. _.._ - - - - - - - - - - - - - - - - - - 278 CMOS Mixed-Signal Circuit Design Figure 7.55 Third-order (2-1) cascaded modulator. while the output of the second modulator is (7.11 0) The output of the 2-1 modulator is then, ideally, vout{z) VI(Z)z··1 +(1 z-I)2 v2 (z) z-2 Vin (z)+(l-z-J/ VQdz) (7.1 II) Let's attempt to characterize the leakage to the output by first determining the output of the second integrator 01(Z) (the input to the comparator). We'll use the topology shown in Fig. 7.32, with GJ = 1, to define our gains. The output, 01(Z), is (assuming that GF G1G2Gc I) GIGZ·Z·I Vin (Z)-[(G 1G2+G2) G2Z-1]. VQel(Z) I +Z-I ·(G2Gc -l)+Z-z(l-GzG c) (7.112) Again, writing the input to the second modulator as (using Eq. [7.61]) VQelout(Z)=Vl(Z) 01(Z) (l G 1G2)'Z-l vin(Z)+ Z-I)2+(G]G2+GZ)' 1+Z-1 '(G2Gc -l) noting that if GI = G2 = Gc I then VQelout(Z) = VQel (z). If we write the output of the cascade as then Desired output ----~, VOUl(z) = Z-2 Vin (Z) + (1 - Z-I)3 VQe2(Z) + Undesired term 2 1(I_Z-I)2[(1 G 1G2) . Z-l Vin(Z) + [(1 G2) (G 2Gc - G2)Z-I]. 1 +Z-I . (G 2Gc 1)+z-2(1 G2Gc) VQel(Z) ] (7.114) (7.115) Chapter 7 Noise-Shaping Data Converters 279 When this equation is compared to Eq. (7.106), we see that the undesired term is second order differentiated. Also, we have more control over the integrator gains. Third-order modulators using the 2-\ topology are much more robust than the I-I-I-based topology and can provide output signals free of unwanted tones. Again, if integrator saturation (and thus dynamic range) isn't a concern, then we can set GI G2 = I . One of the interesting uses of the 2-1 modulator is the configuration where the first (second-order) modulator utilizes a I-bit ADC and DAC, while the second (first-order) modulator utilizes a multibit ADC and DAC. The overall linearity of this topology is dominated by the second-order modulator, while the multibit modulator provides an enhancement in dynamic range for a given oversampling ratio. These very interesting data converters are discussed in greater detail in [7]. Implementing the Additional Summing Input Before leaving our introduction to cascaded converters, let's discuss the implementation of the extra summing block used to generate the quantization noise, VQ.(z). Figure 7.56 shows the topology ofthe two summing blocks and how they can be combined. One way to implement the extra subtracting input and the integrator is shown in VI (z) I--~-- Out to integrator '---1 switches are closed and discharged to VeM when the <1>2 switches are closed. The difference between these voltages combined with the value of the unwanted parasitic capacitance to ground on the top plate causes unwanted charge to transfer to the feedback capacitor and a gain error. This by itself isn't too bad. However, the unwanted capacitance can have a large depletion capacitance component, resulting in a voltage-dependent capacitance and thus nonlinear gain. Nevertheless, in some applications this topology may still prove useful. VI (z) Figure 7.58 Implementation ofa 2-1 NS modulator. Chapter 7 Noise-Shaping Data Converters 281 Vt(Z) - - - Ot (z) Figure 7.59 Implementing the dual summing block with a single capacitor results in sensitivity to the top plate parasitic capacitance. ADDITIONAL READING [1] R. Schreier and O. C. Temes, Understanding Delta-Sigma Data Converters, Wiley-IEEE Press, 2005. ISBN 978-0471465850 [2] S. K. Dunlap and T.S. Fiez, "A Noise-Shaped Switching Power Supply using a Delta-Sigma Modulator," IEEE Transactions on Circuits and Systems 1: Regular Papers, Vol. 51, No.6, pp. 1051 - 1061, June 2004 [3] A. Eshraghi and T.S. Fiez, "A Comparative Analysis of Parallel Delta-Sigma ADC Architectures," IEEE Transactions on Circuits and Systems 1: Fundamental Theory and Applications, Vol. 51, No.3, pp. 450 458, March 2004 [4] S. R. Norsworthy, R. Schreier, and O. C. Temes (eds.), Delta-Sigma Data Converters: Theory, Design, and Simulation, Wiley-IEEE Press, 1997. ISBN 978-0780310452 [5] R. T. Baird and T. S. Fiez, "Linearity Enhancement of Multibit ~L AJD and DIA Converters using Data Weighted Averaging," IEEE Transactions on Circuits and Systems 11: Analog and Digital Signal Processing, Vol. 42, No. 12, pp. 753 - 762, December 1995 [6] 1. C. Candy and O. C. Temes (eds.), Oversampling Delta-Sigma Data Converters, Wiley-IEEE Press, 1992. ISBN 978-0879422851 [7] B. P. Brandt and B. A. Wooley, A 50-MHz Multibit Sigma-Delta Modulator for 12-b 2-MHz AJD Conversion," IEEE Journal o/Solid-State Circuits, Vol. 26, No. 12, pp. 1746 1756, December 1991 QUESTIONS 7.1 Show how to derive Eqs. (7.1) and (7.2) from the block diagram seen in Fig. 7.1. 7.2 After reviewing Sec. 2.2.3, would it be possible to replace the delaying integrator seen in 7.2 with a non-delaying integrator? If so, what is the NTF and STF of the modulator? Is the modulator stable? 7.3 Using SPICE simulations, show how passing the digital signal seen in Fig. 7.3 through an RC lowpass filter will reduce the modulation noise in the signal and help to recover the original analog input signal. What happens to the original signal's amplitude if it's filtered, by the added RC filter, too much? 282 7.4 Show the spectrums (modulator input, digital output, and analog output after filtering) of the signals in question 7.3. Discuss what the spectrums indicate. 7.5 If an extra delay, Z~l, was added to the forward path of the modulator in Fig. 7.2 would the resulting topology be stable? Why or why not? 7.6 Show, using timing diagrams, how Eq. (7.3) is correct. 7.7 For the NS modulator shown in Fig. 7.5 used for digital to analog conversion, what component serves as the ADC? What component serves as the DAC? 7.8 Explain how the quantizer in Fig. 7.5 functions. 7.9 What are we assuming about an input signal if the modulation noise follows Eq. (7.5)? 7.10 What is the magnitude ofEq. (7.5) (plot it against frequency)? 7.11 What is the difference between quantization noise and modulation noise? 7.12 Show the steps and assumptions leading to Eq. (7.12). 7.13 Is the statement on page 238 that "every doubling in the oversampling ratio results in 1.5 bits increase in resolution" really true if K is small? Explain. 7.14 Does noise-shaping work for DC input signals? If so, how? 7.15 Show the steps leading up to Eq. (7.22). 7.16 What is the difference between a NS ADC and a Nyquist ADC? 7.17 In your own words, describe ripple in the output of a digital filter connected to an NS modulator. 7.18 Does adding a dither signal to the input of a NS modulator help reduce the peak-to-peak ripple in the digital filter output? Does it help to break up tones in the filter's output? 7.19 Derive Eq. (7.26). 7.20 Repeat Ex. 7.3 if the integrator's gain is set to 0.5. 7.21 Estimate the range of Gc for the quantizer seen in Fig. 7.16. How does this compare to the range of G, for the I-bit quantizer seen in Fig. 7.15? Name two benefits of the I-bit quantizer over multi-bit quantizers. 7.22 Verify that Eq. 7.30 is correct. Use pictures if needed. 7.23 In your own words, and without equations, describe integrator leakage. How would you relate integrator leakage, found in integrators that use an active element as seen in the NS modulators found in this chapter, to the passive integrators used in the NS modulators discussed in the last chapter? 7.24 Would large parasitic op-amp input capacitance affect the settling time of a DAI? Verify your answer using simulations with ideal op-amps (infinite open-loop gain) and non-ideal op-amps (open-loop gains around the oversampling ratio, K). Chapter 7 Noise-Shaping Data Converters 283 7.25 In your own words, how does oversampling affect input-referred offset/noise and the effects of a jittery clock on an NS data converter? 7.26 Determine the transfer function of the DAr shown in 7.20. 7.27 Derive Eq. (7.51). 7.28 Sketch the implementation of the full-differential second-order NS modulator. 7.29 Derive Eq. (7.61) 7.30 Sketch the fully-differential equivalent of Fig. 7.33. 7.31 Resimulate the modulator in Ex. 7.4 if the gains are set to one. Comment on the stability of the resulting circuit. 7.32 Resimulate the modulator in Ex. 7.4 if the input is only 50 mY. Comment on the stability of the resulting circuit. 7.33 Regenerate Fig. 7.40 by selecting integrator gains so that the maximum output swing of any op-amp is 800 mV peak-to-peak. 7.34 Comment, in your own words, on why the actual SNR of a NS-based data converter can be worse than the ideal values calculated in the chapter. 7.35 Derive Eq. (7.75). Make sure each step of the derivation includes comments. 7.36 Resimulate Fig. 7.44 using two-bit ADC and DAC. 7.37 Sketch a possible implementation of a quantizer for the crror feedback modulator shown in Fig. 7.48. 7.38 What transfer function does the following block diagram implement? shift left X(z) Y(z) Figure 7.60 Circuit for question 7.38. 7.39 In Fig. 7.54 sketch the block diagram implementation of the circuit in series with the Yiz) output. 7.40 Derive the transfer function of the topology seen in Fig. 7.61 (show details of your derivation). What is the input common-mode voltage of the op-amp? Is this a concern when not using a negative supply voltage? If the input signals have a common-mode of VDDI2, does this affect the common-mode voltage of the circuit's output (remember that the op-amp is part of an integrator). Would it be a good idea, now that the inputs of the op-amp and the top plates of the capacitors are tied to ground or the virtual ground of the op-amp, to swap the bottom and top plates of the capacitors? Why or why not? Use SPICE to support your answers. 284 CMOS Mixed-Signal Cireuit Design Figure 7.61 Circuit used in question 7.40. 7.41 Repeat question 7.40 for the op-amp circuit seen in Fig. 7.62. V1(Z) 01(Z) --+-V:...;2'--i VCM Figure 8.8 Fom1:h-order bandpass noise-shaping modulator. 8.1.3 Modulators for Conversion at Radio Frequencies One area, at the time of this writing, that still has substantial room for development is the use of bandpass data converters for wireless (narrowband or radio frequency [RF]) communications. Currently mixing (down converting the transmitted information centered around some carrier frequency) into an intermediate frequency (or to baseband) is performed using a multiplier. A multiplier is an analog circuit (e.g., a Gilbert multiplier) with both continuous-time inputs and output. By using a bandpass converter for mixing we can go directly to digital format (the bandpass converter's input is analog, its output is digital, and it is clocked with a local oscillator). The key to a successful modulator design at high operating frequencies is minimizing the delay in both the forward and feedback paths of the converter (to ensure a stable converter). Thus the topology seen in Fig. 8.2 is more likely to be successful at the high conversion rates required in an RF circuit than the topologies seen in Figs. 8.6 and 8.8. Figure 8.9 shows a topology built from the concepts used in the simple passive modulator in Fig. 8.2. The low-noise amplifier (LNA) isn't part of the modulator and is used to provide gain and isolation for the RF input signal (the noise performance of the receiver is dominated by the perfonnance of this first stage). The output of the LNA is a current, gm Vin (this is the input to the modulator). A portion of the current fed back, I flJ , must, on average, equal this input current. The output of the modulator, even though a digital voltage value, can be thought of as the current fed back, iout, to the resonator (which is equal, on average, to N ·hB where N is the number of times the comparator output goes low). Deriving the STF and NTF, similar to (8.12) (but with an input current, iin =gmVin, output current, io"" and quantization noise current, IQe(f)) would show that we don't get an extra noise/distortion term. Note that increases in the SNR must employ K-path sampling, Fig. 6.24, rather than topologies that result in an increase in the modulator's forward delay. The use of K-path sampling is also required to ensure that an adequate oversampling ratio can be achieved when the carrier frequency is large. In addition, it's used to ensure the inherent lowpass filtering we get (the path filter seen in 6.24) when combining the comparator's outputs doesn't affect the desired signal (of course we can combine the comparator outputs so that they have a bandpass response, as discussed in Sec. 4.2.3, rather than a lowpass Sine response). We leave the detailed implementations of these topologies to the refereed literature. 292 CMOS Mixed-Signal Circuit Design Must be capable of supplying current. ~ Vbiasn Antenna L L -_ _ _ _~~------~+ ADC >---<>---- Digital LNA is Figure 8.9 Design of a bandpass modulator for data conversion at RF. 8.2 Switched-Capacitor Bandpass Noise-Shaping In Sec. 4.2.3 we discussed the idea that we can implement a Sinc-shaped averaging bandpass filter centered aroundj)4 (oris 16) having a transfer function, Eq. (4.25), of H(z) = ~ 1 -K 1 +Z-2 (8.14) Comparing this equation to the equation for the equivalent lowpass averaging filter, Eq. (4.10), we see that transforming our lowpass modulator topologies into bandpass modulator topologies with bandpass responses centered atisl4 can be accomplished by Substituting Z-2 for -Z-I (8.15) The discrete-analog integrator (DAI) discussed in Sec. 2.2.3 is the basic building block used in lowpass, switched-capacitor, modulator implementations. In order to implement a bandpass modulator at is 14 we need to replace the DAI used in the lowpass topologies with an isl4 resonator, an analog implementation of Fig. 4.23, or RepIace 1 -----I W.ith 1 -----2 l-z- 1 +z (8.16) or, when we can't avoid a delay in the implementation of the building block, z-I . Z-I Replace -1---z---I with -1-+--z-2 (8.17) 8.2.1 Switched-Capacitor Resonators In order to move towards implementing a switched-capacitor is 14 resonator, consider the circuit in Fig. 8.10. The top portion of the circuit is simply the DAI discussed in Sec. 2.2.3 (Fig. 2.54). The bottom portion provides the positive feedback needed for the addition (instead of subtraction) of the delayed output. The transfer function of this circuit IS (8.18) Chapter 8 Bandpass Data Converters 293 VeM "----------------<- 1 r-------.J Figure S.lO Implementing anls12 resonator for use in a bandpass modulator. or an /,/2 resonator (the pole is located atfsI2). In order to implement an 1s14 resonator we'll need to use two delays in the feedback path. Implementing two (analog) delays, with any reasonable level of precision, in the feedback path is challenging. In order to implement an 1s14 resonator, we'll take two 1s12 resonators, put them in parallel (see Eq. [2.56] in the K-path sampling discussion found in Sec. 2.1.6), and switch the phases of the clocks in each topology. So, for example, if we clock two of the resonators in Fig. 8.10 connected in parallel (see Fig. 2.37) at 50 MHz then the output word rate is 100 MHz (the output of the topology changes each time either ~I or ~2 goes high). Reviewing Eq. (2.56) for two paths, Z --7 Z2 , we can then re-write Eq. (8.18) as (8.19) or our desiredfs 14 resonator transfer function. Note that in this equation the VI input is delayed by a full clock cycle (see Fig. 2.55 to see how this is modeled for the DAI). We'll see that this delay means that we can't design a two stage bandpass modulator (a fourth-order modulator) using two non-delaying resonators. This shouldn't be a surprise since we also couldn't design a second-order lowpass modulator, Fig. 7.27c, with two non-delaying DAIs. Example 8.2 Simulate the operation of the resonator in Fig. 8.10, clocked at 50 MHz, if C1 = CF = 1 pF. Comment on the stability of the resonator. Verify your comments using a SPICE simulation. The pole of the resonator is located at z -I, right on the unit circle (located at a frequency offs/2). We know, from Sec. 4.3.1, that for a discrete-time circuit to be stable its poles must lie inside the unit circle. We, therefore, expeet the resonator to oscillate (become unstable), Fig. 8.11. • 294 CMOS Mixed-Signal Circuit Design 20V'--,-_ _--,-:v-'-'(v.::..:ou'-'-I]__ _ _ _-'-'V1v.:ci.n:;,:s-"'p]...:.-V"-lv"'-ins::..::m2] - - - , 16V ·······(····t······~······: ···;······T·······;········: 12V ...•... ; ....... 1""......:........:.......,.......;............~ ..... BV ....... : ..•.... ; ....... .'.......... . ...... ; ............, .•• (V OV-=-~'Th.J -(V -1IV ·12V ·16V ••.••.. : ••••••. ; .•......:.......•••••..•..•.. ; ............••••......•. , , , ,"" , , ,,, , - - - - - _ . - - - - - - - j . - - . - .'. - - - - - " . - - -_ • • - - ' - - - -~- . . " ., . , , ." " - - - - - - - .' - - -- - - - - , - - - - - - , - - - - - - j . - - - - - - ' - - - ---~ - - - - - _ . - - - - - - ' . - - - - - . ' . - - - - _ . ' - - - - -- -- - - -- ·2OV Dns 50ns 1DOns 15Dns 200ns 250ns 300ns 350"s 400n5 450ns 500ns Output Input = V2 VCM VI (Z) . Z-1I2 = Vout(Z) 1 +Z-I Figure 8.11 Simulating the operation of the resonator in Fig. 8.10. Example 8.3 Suggest a modification to the resonator in Fig. 8.10 to eliminate the need for the gain of -1 block. Verify your circuit modification with SPICE. Reviewing Fig. 2.56 we see that if we connect the fed back output signal to the top plate of the 2CF capacitor, Fig. 8.12, then the signal is inverted when it's transferred to the output of the resonator. Simulation files for this circuit verifying correct operation are available at CMOSedu.com. Note that we'll use the topology seen in Fig. 8.10 since it is more tolerant of charge injection errors on the 2CF capacitor than the topology seen in Fig. 8.12.• <1>1 <1>2 , Vc~,\ ~--l>---- VI (z) '\~---iT>--C_J_~,' V2(Z)_ _ _ _+-_____~-'-----.J VCM + Figure 8.12 Implementing a resonator for use in a bandpass modulator. 8.2.2 Second-Order Modulators Figure 8.13 shows the implementation of a second-order modulator based on the first-order lowpass topology seen in Fig. 7.1. Remembering, from page 290, that a second-order bandpass modulator's SNR is similar to (calculated in the same way as) the first-order lowpass modulator's SNR we can write Chapter 8 Bandpass Data Converters 295 (8.20) or, assuming G1 = I (as discussed in Sec. 7.1.5), STF NTF (8.21 ) Note the inversion in the signal transfer function. This is trivial to remove; for an analog signal see Fig. 3.6 and, for a digital signal, see Fig. 6.3. The noise transfer function, 1+ ,has the shape seen in Fig. 8.7. Atfsl4 the modulation noise is zero increasing as we move away from j~ 14. Note that this topology is second-order because the number of poles in the NTF is two (a first-order lowpass modulator has one pole in its NTF). Vout(Z) Out Figure 8.13 Block diagram of a second-order bandpass modulator. Example 8.4 Simulate the operation of the second-order modulator seen in Fig. 8.13 (show the modulator's output spectrum) with a clocking frequency of 50 MHz (data eoming out of the modulator at a rate of 100 MHz because of the 2-paths used) and an input frequency of25.1 MHz. If the digital output of the modulator is run through an ideal digital bandpass filter with a pass frequency range of 25 MHz ± 390 kHz then estimate the final SNRideol' Figure 8.14 shows the modulator's output spectrum. Notice how the modulation noise increases as the frequency moves away from fs 14 (25 MHz here). The oversampling ratio, K, can be calculated using, once again, I.?-L-.-.....i---;----:t-- Desired output tone at25.l MHz. -60dBr---i----i-----i---'-'+-''----.---·······-r---r' O.lMHz Figure 8.14 Spectrum of the modulator's output discussed in Ex. 8.4. 296 CMOS Mixed-Signal Circuit Design K= .!S 2B For the present example is 100 MHz and B 390 kHz so K (7.14) the SNR,denl is 66 dB.. (8.22) 128. From Eq. 8.2.3 Fourth-Order Modulators Figure 8.15 shows the block diagram of a fourth-order bandpass modulator formed by transforming the lowpass second-order modulator seen in Fig. 7.26c. Again, the bandpass topology is now called a fourth-order modulator because the number of poles in the NTF is four. The transfer function for this, is 14, bandpass modulator (sometimes called a quadrature modulator) is STF NTF (8.23) Again, as discussed in Sec. 8.1 the fourth-order bandpass modulator's SNR can be estimated using the same approach that we used for the second-order lowpass modulator discussed in Sec. 7.2. 1 I +Z-2 Comparator gain not shown. I so/is Is 21s'200 2 Figure 9.14 Another filter; however, this topology has problems removing the modulation noise. On. 1DOns 150n8 200ns 250ns 300n. 350n. 400n. 450n. 500ns Figure 9.15 Simulating Fig. 9.14 with a 6.25 MHz input signal. Note the the nonlinearity in the output. In order to move towards answering these questions, notice the nonlinearity in both Figs. 9.15 and 9.17. We implemented the filter by focusing on only increasing the output word size to 8-bits. We didn't concern ourselves with removing the modulation noise and thus we see noise and nonlinearity in our output signal. Reviewing Sec. 7.1.3, we can remove the modulation noise by using the filter seen in Fig. 9.1 0 but without the decimation (noting that if L 2 then only the path filter and one Sinc filter are used for a 7-bit output). This also helps us move closer towards the design goals. Figure 9.18 shows the simulation results when a 50 MHz input is applied to the topology seen in Fig. 9.l0 without decimation. The input signal undergoes 3-Sinc filter responses (0.64)3 0.262. Chapter 9 A High-Speed Data Converter 3 II 8f, MUltiply output by 2. 8f, Figure 9.16 Filtering without decimation. This filter won't do a good job removing the modulation noise but it does increase the output word size to 8-bits. Figure 9.17 Simulating Fig. 9.16 with a 6.25 MHz input signal. Again, note the the nonlinearity in the output. Figure 9.18 Using the filter seen in Fig. 9.10 without decimation. Attenuation is due to 3-Sine stages. The input signal frequency is 50 MHz. 312 CMOS Mixed-Signal Circuit Design Direction In order to move towards our design goals we can use the filter seen in Fig. 9.12 but with an additional averaging, I + z I , stage on the filter'S output. This increases the word size to 8-bits. The penalty is an extra 3 dB attenuation at 50 MHz (so the total attenuation at 50 MHz is 10.S dB or 0.2S8). The practical issue with this topology, for very high-speed operation, is avoiding timing errors in the stages clocked at Sis. For a general design, we'll use the topology seen in 9.10. Timing errors are straightforward to minimize. The drawback is the reduction in signal bandwidth. An area that should be investigated further is the use of biquad filters for removing the modulation noise, as discussed in Sec. 4.3.4. 9.1.4 Discussion If the NS modulator seen in Fig. 7.2 is clocked at 100 MHz we get the noise transfer function, NTF, shape seen in Fig. 9.l9a (out to 800 MHz or Sis). While we are used to focusing on the spectral content between DC andls (= 100 MHz here), we know that any discrete-time system's frequency response repeats with the sampling frequency, Is. The signal bandwidth, as seen in the figure, is 6.25 MHz, assuming Kavg = S. Note that we are not showing the frequency response of the digital filter used for removing the modulation noise (which is where Kavg is used, Eq. [6.47] and Fig. 7.8). Figure 9.19b shows the assumed spectrum of the quantization noise while Fig. 9.19c shows the single path clocked at 100 MHz (noting we are not showing the non-overlapping clock signals). INTF(f) I2 : 50 100 200 400 500 600 700 800 MHz 6.25 (a) NTF ofa noise-shaping topology clocked at 100 MHz, 7.6. i . I I VQe(f) 2, V 2/Hz visB 12fs~ V;n-(Z')-iIModu Iator. H () Z Vin(Z)' , elk NTFer) + (l-Z-l) ,VQe(f) 50 100 MHz ~IOOMHz (b) Quantization noise PSD, Fig. 5.12. (c) Modulator clocked at 100 MHz. Figure 9.19 NTF and quantization noisc spectrums of a first-order NS modulator clocked at 100 MHz with 8. Next, examine the S-path topology of modulators seen in 9.20 (modified from Fig. 2.37 for this discussion). In (a) of the figure each modulator is clocked at!" the same as in Fig. 9.19c, but with time-shifted clock signals. In (b) we show the equivalent circuit, see discussion on page 224 for details, noting the equivalent circuit's output changes with a frequency of Kporh ·Is. By using an effectively higher clock frequency we spread the Chapter 9 A High-Speed Data Converter 313 ~~ ~ H(z) r;-~ '0 ~~ H(z) •• ~.~~) ~8 8 ~l ~~~.--------~~ ~~~------~--- n...___ ~3 : ---'-7--_ ~~4_,~~n~----~- ••• .:. Ca) 8 modulators in parallel Kpath 8 H(z) Vin(Z)·z-l+ (l-z-I). VQe(f) ~lK JL..h--.SLS ~2K~ ~ TsIKpafh (b) Equivalent circuit H(ZKpd'h) =Vin(Z) . Z-Kpdlh + (1 - Z-Kpalh) . VQe(/) 2 /VQe(f)1 , V21Hz -+I 100 12ls,new 121s . Kpalh I I I l- 200 300 400 500 is "" 100 }'fHz Is,new = 800 kfHz I I I ) 600 700 800 MHz (c) Quantization noise for an 8-path topology clocked 100 MHz, compare to Fig. 9.19b. INTF(f) I2 • 8. i21s L..k ~ ~ O"i"d 'p,,!rum ??1 I I i ~-t--I---+I---+I---II----+I-~)o : 50 100 200 300 400 500 600 700 800 MHz 6.25 (d) Modulation noise of 8-path topology above. Figure 9.20 Eight moduLators in parallel (a time-interLeaved topology). quantization noise out over a wider range of frequencies, (c). This reduces the modulation noise added to our signal in the bandwidth from DC to 6.25 MHz as seen in Fig. 9.20d. If our desired signal bandwidth remains at 6.25 MHz then we will 'clearly get an improvement in SNR. Note that the output of the topology is I-bit changing at a rate of 800 MHz. 314 CMOS Mixed-Signal Circuit Design Suppose we want to use this topology for high-speed data conversion where we use the fact that our effective output clock frequency is 800 MHz (and so the Nyquist frequency is 400 MHz)? Is this possible or does it make sense? This is a good point to remember the fundamentals. As mentioned on page 201, using noise-shaping does not result in a reduction in quantization noise. Rather, noise-shaping topologies push the quantization noise to frequencies outside the region of interest. Reviewing Fig. 9.20d we see that (all of) our quantization noise is still present in the spectrum from DC to 400 MHz (see example below). It's impossible to reduce this noise with a digital filter without effecting the desired signal in this same frequency range. Example 9.3 Estimate the RMS value of the quantization noise for the 8-path topology clocked at 100 MHz seen in Fig. 9.20d. I I (f) V~e,RMs == 4/, INTF(f) I2 • 8~~2~Is . df == 4(, 4· 2 sin 1; 11: .8V. 2~~Is . df == ViSB .J[I-COS(211:.L)].df == ViSB 4·12Is 0 Is 12 Jl2 , or VQe,RMS == VLSB/ no reduction in quantization noise. While this result was derived for the case Kpolh == 8 the reader should see that the result is valid for any value of K po1h' • Example 9.4 Estimate SNR;deal for the topology seen in Fig. 9.20a. The procedure for calculating SNR was given in Sec. 5.2. Since we just calculated the quantization noise, all that's left is to calculate the desired output signal power. If we apply a sinusoid to the topology with a peak amplitude of Vp , then adding the output signal powers from each path results in Kpalh . V')I2. We can then write ~.Vp/J2 SNRideal == 20 . log ~ VLSB/" 12 or (see Fig. 5.31) SNRideal == 6.02N + l.76 + 10 log Kpalh (9.4) For every doubling in the number of paths we get a 3-dB (0.5 bits) increase in the SNR. Such a modest increase in SNR is, generally, too insignificant for the hardware costs so this approach isn't used.• The virtues of the topology seen in Fig. 9.4 should be clearer. Using a single integrator (I-sigma) with K feedback paths (K-deltas) we can attain conversion bandwidths approachingf)2 with reasonable resolutions. Since a single integrator is used, common information is applied to the input of each quantizer. This allows the quantization noise to be pushed to very high frequencies. In other terms, we get fast sampling by using K feedback paths while we are able to push the quantization noise to higher frequencies using a single integrator common to all quantizers. Chapter 9 A High-Speed Data Converter 315 9.1.5 Understanding the Clock Signals Notice that in Fig. 7.2 we used q,] to clock both the input switches and the comparator. In our high-speed topology seen in Fig. 9.4, however, we used an earlier clock signal to strobe the comparator. For example, examining the top path in Fig. 9.4, the input switches are clocked with q, I-I while the comparator is clocked with q,Z-I. The input signal is captured on Ci at the falling edge time of q, I-I. A very short time later, T)Kparlt' we clock the comparator. Since near-ideal components are used in our simulations the delay associated with transferring the charge on Ci to the integrator's output is nearly zero. When the comparator makes a decision it is immediately fed back to the integrator, again with minimal delay, so that the next path's decision is directly dependent on the previous path's decision. The result is the topology behaves like a single, first-order, noise-shaping topology clocked at Kpath Is. In a practical implementation of the modulator, however, the delay through the integrator and comparator is finite and so the information fed back to the integrator experiences a delay. The result is a built-in instability. Figure 9.21 shows an example of this instability. In this example, the input signal is the DC common-mode voltage, 500 mV here, and the clock signals are selected so that, as in Fig. 7.2, the same clock signal is used for both the input pair of switches and the comparator (the near-worst case situation when using ideal components). The average value of the output signal does, indeed, equal the input signal; however, we have the unwanted oscillation seen in the figure. As we've ShOW11, the oscillation is minimized (ideally removed) by proper selection of the clock signals to minimize the delay feeding back the output signals. Since this oscillation always occurs at a high frequency, a multiple of the clock frequency, the digital filter on the output of the modulator removes it. Another example, but with an AC input signal, is seen in Fig. 9.22. Notice, again, that the average of the output does equal the input signal. It can be instructive to change the clock signals applied to the comparators in the modulator to show how this oscillation grows and shrinks. In the practical implementation the finite delay through the comparator or through the switches charging or discharging the capacitors must be taken into account when selecting the clock phases for the comparators. Another practical concern is the increase in the output swing of the integrator because of this instability (which can be reduced by increasing the size of the integrator's feedback capacitor). Figure 9.21 Showing built-in instability in the high-speed modulator. 316 CMOS Mixed-Signal Circuit Design 1.0V-,,--...,.,....-n-~=------,r-T---,-·~-~-····--+--'-=---:- D.SY D.7V O.SV D.SY OAV O.3V O.ZV O.W O.OV+----+---jL-L-.lj---+-.JL--i--···-r----r----'---'t--'------r--'-----'-'l Ons JOns 60ns 90ns 120ns 150no 180ns 210ns 240n5 270ns JOOns Figure 9.22 Showing built-in instability with a sinewave input signal. 9.2 Practical Implementation In this section we'll discuss the practical implementation of the high-speed topology proposed in this book. The goal of this section is to provide discussions and provoke thought that should prove helpful when designing a converter using this topology. The goal is not to provide definitive solutions for specific applications. This endeavor is left for discovery by the engineers and researchers doing mixed-signal circuit design. 9.2.1 Generating the Clock Signals Generating the 16 clock signals needed for the topology seen in Fig. 9.4 can be challenging. We could use a delay-locked loop (DLL) that takes an input clock signal and generates the 16 clock signals (but that adds complexity). Here we use a ring oscillator that runs asynchronously with an external clock signal. Figure 9.23 shows the basic delay stage schematic and icon used in thc oscillator. Figure 9.24 shows the complete ring oscillator while Fig. 9.25 shows some simulation results in a 500 nm, 5-V, CMOS Figure 9.23 Delay stage used in the ring oscillator, schematic and icon. Chapter 9 A High-Speed Data Converter 317 Figure 9.24 oscillator, schematic and icon, for use with the data converter. process. Note that the frequency of the oscillator can be adjusted by adding or removing inverters in the delay stage. Also notice that the simulated oscillation frequency is around 200 MHz (lower for a simulation with layout parasitics). The analog input signal is sampled at a rate ofIs.new or 1.6 GHz. The 8 path outputs are added together, Fig. 9.4, and then decimated, Fig. 9.7a. Figure 9.25 Simulating the oscillator in a 500 nm process. Figure 9.26 shows how the external (synchronous) and internal (asynchronous) clocks can be interfaced using a synchronizer. We are assuming that the internal clock is running faster than the external clock (so the output is decimated). Note that the synchronizer doesn't introduce aperture jitter as discussed in Sec. 5.2.1 since it only proeesses digital signals. After reviewing this section, however, we might wonder if the ring oscillator is a practical choice for providing the clock signals to the data converter. Ring oscillators are certainly not as stable as crystal-controlled oscillators. However, notice that by combining the Kpalh outputs together we reduce the variance of the aperture jitter by K,""lh' see, for example, Eq. (5.30). Further filtering reduces the effects of a jittery clock signal. Slow variations in VDD, ground, or temperature will also have essentially no affect on the data converter's performance (via the ring oscillator) since these changes simply vary the sampling rate (the internal clock frequency). Note that for large differences in the internal and external cloek frequencies aliasing concerns, when decimating, should be taken into consideration in the synchronizer (as should metastability concerns, e.g., the external clock (not) going low just after the internal clock goes high resulting in a glitch on the output of the AND in Fig. 9.26). 1 318 CMOS Mixed-Signal Circuit Design In Analog Digital Filter Internal clock, clocked with ring oscillator, Fig. 9.24. Synchronizer ~.DQ Out T External clock External clock (not) Internal clock Figure 9.26 Synchronizing the external and internal clock signals. 9.2.2 The Components The Switched-Capacitors Figure 9.27 shows the schematic and the icon for the switched-capacitors used in the modulator. The concerns, when selecting the widths of the MOSFETs, as discussed on n. pages 302 and 307, are that the capacitors can be charged/discharged within T/Kpafh' The effective resistances of each MOSFET in Fig. 9.27 is 500 Since two MOSFETs are in parallel with switches on each side of the 100 fF capacitor, the time constant is 50 ps. Finally, the size of the capacitors used in this circuit, as discussed on page 307, is set by thermal noise considerations. Figure 9.27 Schematic and icon of the switched-capacitors used in the modulator. The Amplflier Figure 9.28 shows the schematic and icon for a self-biased amplifier. This topology was picked because it's simple and fast. Further, for the comparator discussed next, the outputs are complementary and generated from NMOS devices (which interface nicely with the comparator's inputs). Simulation results are seen in Fig. 9.29. The non-inverting amplifier input is held at 2.5 V while the inverting input is pulsed from 2.45 to 2.55 V (100 mV change). The output changes from roughly 2.8 to 0.8 (2 V change) so the gain is 20 (which should be larger than Kpafh or 8 here). Both outputs of the amplifier are loaded, in the simulation, with 400fF capacitors. Our concern, Sec. 7.1.8, is that we don't see slewing in the response. The amplifier sizes picked here are larger than required for our final design (so power is wasted). Chapter 9 A High-Speed Data Converter 319 Inpf~tP Inffl~tm Figure .9.28 Self-biased amplifier and icon. Amplifier outputs Amplifier inputs Figure 9.29 Simulating the operation ofthe amplifier in Fig. 9.28 with 400 if loads. The Clocked Comparator The schematic and icon of the clocked comparator used in the design is seen in Fig. 9.30. The input clock signal is sharpened and buffered up so that the input capacitance of the comparator is reduced and the edges in the comparator are fast (so that a good, reliable, decision can be made). The basic latch is formed with cross-coupled inverters (as usual). No DC current flows in the comparator. Current is pulled from VDD when the clock signal changes states. The NAND gates are used to ensure that the comparator output changes states (only) on the rising edge of the input clock signal. The outputs of the NAND gates are buffered up to ensure that they can drive the switched-capacitors. If these outputs don't fully charge the switched-capacitors or the VDD/ground connected to these gates droops or bounces, the feedback signal will be affected causing noise and nonlinearity. Finally, the inputs to the comparator should be above the threshold voltage of the NMOS device but not so large that the input devices are pushed into deep triode. Note, as discussed already, that we need to be careful to ensure minimal forward delay through the comparator (and, of course, the integrator). 1 320 CMOS Mixed-Signal Circuit Design I elk Inp~ t.c""", InN _ . bar Figure 9.30 Clocked comparator and icon. input input Figure 9.31 Simulating the operation of the comparator in Fig. 9.30. 9.2.3 The ADC Figure 9.32 shows the schematic of the high-speed ADC (minus the digital filter) we designed in this section using a 500 nm CMOS process with a VDD of 5 V. The resistors are used (for SPICE simulations) to provide a simple method of summing the digital outputs for ease of viewing. While they are useful for speeding up the simulation, they are not useful for looking at the performance of the converter. The finite transition times, glitches, etc. in the digital data limit their usefulness when viewing analog data. Figure 9.33 shows the results of simulating the ADC with a 10 MHz input signal. At this point, in order to characterize the behavior of the ADC, we need to add the digital filter to the modulator's output. Ideally the K-delta-I-sigma topology seen in Fig. 9.4 behaves like a single, first-order, noise-shaping modulator clocked atrs,new • Kpath or 1.6 GHz here) with a I-bit output (we selectively connect each path's output to the overall topology's output every TsIKputh seconds). Let's use the decimator and filter seen in Fig. 9.10, but with, as discussed in Sec. 7J .3, L = 2 (the adder and only one Sinc filter). The final output word size is 7-bits, the effective I-bit output by the modulator and then 3-bits (each) for the addition and the Sinc filter. We won't Chapter 9 A High-Speed Data Converter 321 Figure 9.32 K-delta-l-sigma modulator. synchronize the output data to an external clock. This means that the output will change at the rate of the ring oscillator (roughly every 5 ns or 200 MHz). An input signal frequency of (roughly) 200 MHz/16 or 12.5 MHz will be attenuated by -3.9 dB. Figure 9.34 shows the simulation results for the ADC (modulator and filter) when the input signal is 10 MHz (same as Fig. 9.33 but showing the output of the digital filter). These conversion rates are comparable to any high-speed converter topology implemented in a 500 nm CMOS process (even faster if we use less decimation early in the digital filter) . S.Sv·~_~_......"V(v.:.:i:.:!.nl_ _ _ _ _ _ _ _V""(s:.:u.::.:m,,,,_d=l-I_ _ _~ S.OV 4.SV 4.0V 3.SV 3.0V 2.SV 2.0V 1.SV 1.0V O.SV O.OV -O.svr+---i---i---i---i---i---i---i---i--';-- Ons 30n5 60ns 90ns 120n5 150n5 180ns 210ns 240n5 270n5 JOOns Figure 9.33 Simulating the ADC in Fig. 9.32 with a 10 MHz input signal. Figure 9.35 shows a simulation where the ADC's input is a ramp signal that transitions from 0 to VDD in 1 )..ls. The delay through the filter is 50 ns so the input signal should be shifted 50 ns later in time when comparing the ADC's input to its output. Of course, the ADC's output will then be valid only after this delay (so we neglect the start-up transient). We can estimate the minimum step size in the output of the ADC as VDD!2 6 or 78 mY. We use 26 instead of27 (the exponent is the number of bits coming out of the filter) because in order for the output signal to swing rail-to-rail we have to 1 322 CMOS Mixed-Signal Circuit Design ~.OV 3.5V 3.0V 2.5V 2.0V 1.5V 1.0V ------+-- 0.5V O.OV-t---i---i---i---i---i---;---i---;---;------1 Dns 30n5 60ns 90ns 120n5 150n5 180ns 210ns 2040n5 270n5 300n5 Figure 9.34 Same as Fig. 9.33 (l0 MHz input) but looking at the output of the digital filter. . . . 5.0V,--_-,----_...,..-'-'VI=oU"'IJ-,---_-,---_-,---_--,--_--,--:-VI"-vi""nJ'-;-_--,------::?l ~.5V -- --- --j,- -. -----;"- --- -. --~ ---- --. ~ ------- -" ;- --. ----~ --, -----j-------; :::FFt'j.'."L :: ·····,·····'"iiFI :::~ --- ---1-'-::::T::-::::t:::::::::::::::::::::::::t:::::::::::::::I:::::::t::::::: o.ov--jL--i---i---i---i---i---i---i---i----r---i o.o~s 0.1 ~s 0.2~s 0.3~s O.~~s 0.5~s 0.6~s 0.7~s 0.8~s 0.9~s 1.0~s Figure 9.35 Simulating the modulator with a ramp input signal. Shift input later in time by 50 ns to compare to output. multiply it by two before applying it to the ideal DAC used to display the digital data as an analog output voltage (as discussed earlier). Remember that increasing the output word size (increasing resolution) requires additional filtering. Also, again, recall that to increase the signal conversion bandwidth we need to reduce the amount of decimation used immediately following the modulator and prior to the adder that sums the Kpa'h outputs together (see Fig. 9.7b for the decimate by Kpa'hl2 example). 9.3 Conclusion This chapter has proposed a new topology for high-speed analog-to-digital conversion using the mixed-signal circuit design techniques presented in this book. The topology should prove useful when designing high-speed ADCs in nanometer CMOS. Future work can be focused in many areas including, but not limited to: fully-differential signal paths, the integrator (amplifier) design, higher-order (perhaps passive, Sec. 6.2.1) topologies, bandpass converters, segmenting feedback paths, digital calibration (e.g. for offset, Sec. 7.1.9) and the design of the digital filter (including the decimating stage). Chapter 9 A High-Speed Data Converter 323 QUESTIONS 9.1 What is a time-interleaved data converter? Why is a time-interleaved converter different from the K-Delta-l-Sigma converter seen in Fig. 9.4? Sketch the implementation of a time-interleaved data converter implemented with Delta-Sigma modulators. Also sketch the clock signals used in the topology. 9.2 Using the modulator from Ex. 9.1 show that capacitor matching isn't important in the K-Delta-l-Sigma topology. 9.3 Repeat question 9.2 but show that thc opcn-Ioop gain of the amplifier used in the integrator isn't critical (compare, using simulations, the performance of the converter using different gains). 9.4 Show the details of (derive from the time-domain outputs of the K-Delta-l-Sigma modulator) how the path filter seen in Fig. 9.4 has a z-domain transfer function of 1 Z-8 I Explain how this filter performs a moving-average filtering of the modulator's outputs. Does this filter decimate the K-Delta-l-Sigma outputs? Why or why not? 9.5 Sketch the decimate by Ki4 topology similar to the topologies seen in 9.7. Ensure the proper clock signals are used in your sketch. 9.6 Explain, in your own words, why oversampling (averaging the outputs) using a 3-bit Flash converter (eight comparators), won't result in as significant improvement in SNR as the K-Delta-I-Sigma topology. 9.7 What is the frequency response (an equation) of the filter seen in Fig. 9.1 0'1 9.8 What is the frequency response (an equation) of the filter seen in Fig. 9.12'1 9.9 What is the frequency response (an equation) ofthe filter seen in Fig. 9.14? 9.10 What is the frequency response (an equation) of the filter seen in Fig. 9.16? 9.11 Show how the switches on the inputs and outputs of the 8 modulators in parallel seen in Fig. 9.20 can be described using the unit matrix and delays or 10000000 o1 0 0 0 0 0 0 Z-118 001 0 0 0 0 0 z·218 000 I 0 000 z-3/8 o 000 I 000 Z-4/8 o0 0 0 0 I 0 0 0000001 0 o0 0 0 0 0 0 I where z = . Using these relationships show how to relate the inputs of the K paths in parallel, Fig. 9.20, to the transfer function H(z) and the resulting topology's outputs. 324 CMOS Mixed-Signal Circuit Design 9.12 In the previous question we showed that we can think of the switches on the input or output of the K-path topology as multiplying the signals by I or O. Let's take this a step further and ask "What can we accomplish if we multiply the signals by I, 0, or -I (the analog multiplication by -I is implemented by swapping the fully-differential amplifier's inputs)?" Reviewing Fig. 8.19 from the last chapter we see that proper selection and sequence of these multiplying terms can result in modulating or demodulating our signals. Remembering that our (desired) analog input spectrum extends from DC to some frequency B (lowpass data conversion) we see that this movement of the spectrum is undesirable since it moves our desired input signal spectrum directly up into the larger-amplitude modulation noise after it's passed through the modulator (again assuming a lowpass modulator is used). This makes the signal difficult to recover and lowers the topology's SNR. Perform a literature search and comment on these problems ensuring that your understanding of the issues is clear and that you've referenced the literature used to formulate your ideas. 9.13 The effective sampling frequency of the K-Delta-l-Sigma ADC discussed in Sec. 9.2 is roughly 1.6 GHz. Can any component of the ADC operate at, or be clocked at, 1.6 GHz? Verify your answers using SPICE and the 500 nm, 5 V, CMOS models used to generate these figures. What is the most critical component then, from a timing perspective, (the DFF used to capture the eight bits coming out of the modulators) and what is critical in that component (the DFF's setup and hold times)? What happens if an error is made in the most critical component? (The wrong count is captured. For example, we should capture 6 logic Is but we actually capture 5 or 7 logic Is. Since we have a significant amount of averaging in the digital filter the effects should be small. If an equal number of positive and negative errors are made the errors average to zero and don't affect the converter's performance. ) Index Averaging (continued), interpolating filter, 43-50, 71, 139-142, 199, 235, 273 limiting bandwidth, 13-14 linearity requirements, 194-195 noise, 250 quantization noise, 202, 211 without decimation, 132-133 A AAF. See Antialiasing filter. Accumulate-and-dump circuit, 129, 132 Accumulator, 19, 129, 134, 235-236 Accuracy, 195, 200, 269 Active-RC Integrator, 73, 75, filter, 80, 82-83, 87-88, 97-98, 101, 103-106, 109, 112, 116 Adaptive filtering, 93 ADC. See Analog-to-digital converter. Adder, 94, 126, 145, 147, 151, 156, 158-159, 273, 309, 320, 322 Aliasing, 21, 27-72, 93, 127-129, 140, 143-144, 306, 317 quantization noise, 169 Amplitude modulation, 187, 207, 285, 288, 315 Analog RC filter, 80, 82-83, 87-88, 97-98, 101, 103-106, 109, 112, 116 Analog Sinc averaging filter, 10-11 Analog-to-digital converter (ADC), 21, 27, 94, 164-224, 225-284 1-bit, 236 bandpass, 134, 287-300 gain, 246 high-speed, 301-324 Nyquist-rate, 43, 63, 220-225, 241, 306-308 pipeline, 38 SPICE models for, 119-123, 160, 176 Antenna, 292 Antialiasing filter (AAF), 27-40, 73, 93, 139, 144, 198-199, 203, 205-206, 302 Aperture jitter, 179, 202, 317 Autocorrelation function (ACF), 183 Autozeroing, 57-58, 62, 71 Average power, 183-187, 198 Average value, 44, 168, 183-187, 200, 212, 244, 315 Averaging, bandpass filter, 19, 134-139, 160, 290-292 clock jitter, 198 decimation, 209-211 filter, 13-14, 126, 131, 133-134, 201, 220, 223, 234, 239-241, 266-267 highpass filter, 19, 129, 134 improving signal-to-noise ratio (SNR), 13, 190-194 B B, bandwidth of the input signal, 129-130, 133-134, 182, 198-199, 208-209, 212, 220, 229, 237-241, 248, 250, 267, 285, 290, 296, 324 B device. See Nonlinear-dependent source. Bandpass filter, 19, 96, 103-111, 129, 134-139, 160 Bandpass modulators, 263, 285-298, 301, 324 Bennett’s criteria, 165-166 Bilinear transfer function, 95 Binary offset, 123-125, 204-205, 274 Biquad filters, 73, 99-101 Biquadratic transfer function, 99 Bottom plate of a capacitor, 67 Bottom plate sampling, 39-40, 54, 219 C CAI, See continuous-time analog integrator. Calibration, 322 Canonic digital filter, See Digital filter. Capacitance, bottom plate, 54 input, 86, 93, 247, 282, 319 load, 88-89 noise calculation, 307 parasitic, 66, 69, 83-84, 219, 279-281 Capacitive feedthrough, 39, 251, 257 Cascade of integrators and combs filters (CIC filters), 142 Cascaded modulators, 233, 264, 275-280 Charge injection, 39-40, 251, 257, 294 Charge pump, 120 Chopper stabilization, 71 CIC filters, see Cascade of integrators and combs filters Clock generation, 53, 316-318 Clock jitter, 178-189 Coherent sampling, 175-176, 202 Comb filter, 8-21, 25, 129-131, 133-143, 224 Common-mode feedback (CMFB), 60-61, 88-89 Common-mode rejection ratio (CMRR), 87, 252 Common-mode voltage, VCM = 500 mV in this book Comparator, clocked, 163, 319-320 gain, 244-246, 259, 262-263, 295 hysteresis, 246-247 326 Index Comparator (continued), LSB, 204 noise, 163, 246-247, 250 offset, 246-247 placement, 261 Constant delay, 10, 31, 145, 171 Continuous-time analog integrator (CAI), 73, 75, 95 Continuous-time comb filter, 10-11 Continuous-time Fourier transform, 23 Convolution, 35, 175 Correlated double sampling (CDS), 59, 66, 71 Cosine window. See Hanning window. Counter, 45, 126-129, 130, 270-271 D DAC. See Digital-to-analog converter. DAI. See Discrete analog integrator. dBc (decibels with respect to the carrier), 177, 189 Dead zones, 215, 217, 232 Decimation, 33-34, 127-129, 132, 222-223, 306-312, 321-322 bandwidth limitations, 34 decimating filter, 143-144, 157, 203, 239 Delta modulation, 199 Delta-sigma modulation, 199, 233-234 See noise-shaping. Demodulator, 199-200, 235-236, 271-272 Diff-amp, 61, 86, 89, 222 Differentiator, 14-15, 119, 275-276 Digital averaging filter, 192, 220 Digital comb filter, 11-18 Digital filter, 119-162 biquad, 155-159 canonic, 151-155 finite impulse response (FIR), 133-134, 145-146, 161 infinite impulse response (IIR), 134 stability, 146-147 Digital integrator, 19-21, 235 Digital I/Q extraction to baseband, 297-298 Digital resonator, 134-139, 160 Digital signal processing (DSP), 27, 32, 203 Digital-to-analog converter (DAC), 69, 119-123, 204-205, 213-214, 235-236, 272-275 Dirac delta impulse, 23, 28 Discrete analog integrator (DAI), 66-70, 90-93, 233, 251, 260 Discrete-time integrator, 90-95 Distortion, 35, 37, 49, 65, 71, 176-178, 187, 206-208, 213-214, 225-226, 249, 251-252, 269, 273, 288-289 Dither, 166, 195-198, 242, 282 Droop, 37, 39-41, 47-48, 127, 129, 132, 142, 157, 209, 212, 223, 241, 267 DSP. See Digital signal processing. Dynamic range, 83, 177, 251, 276, 279 E Effective number of bits, Neff , 173, 176, 179, 181-182, 188, 202 Error feedback, 235, 271-275, 283 Expected value, 186 F Feedback gains in a DAI, 260 Filters, active-RC, 75 accumulate and dump, 129 bandpass, 19, 96, 103-111, 129, 134-139, 160 bilinear, 95 biquad, 73, 99-101 comb filter, 8-21, 25, 129-131, 133-143, 224 decimating filters, 143-144, 157, 203, 239 digital. See Digital filter. exact frequency response of discrete-time filter, 94 finite impulse response (FIR), 133-134, 145-146, 161 gm-C filters. See transconductor-C filter. highpass, 19, 129, 134 in a higher-order modulator, 267 infinite impulse response (IIR), 134 integrating filters, 73-118 interpolating filters, 139-142 ladder filter, 117-118 lowpass, 75 MOSFET-C, 83 Q peaking and instability, 112 Sinc, 133 SNR, 82-83, 87 stability in digital filters, 146 switched-capacitor, 90-95 transconductor-C filter, 97 tuning, 80, 83, 86, 93, 98 Finite impulse response (FIR) filter, 133-134, 145-146, 161 Finite op-amp gain-bandwidth product, 55-57, 78-79 First-order noise shaping, 208, 210, 224, 233, 238, 254 FIR. See Finite impulse response. Forward modulator gain, 243 Fourier series, 23 Fourier transform, 24 G Gain error term, 176-177, 204, 213-214, 219, 247-249, 280 gm-C (transconductor-C) integrators, 86-90 Gaussian probability distribution, 187, 197 Index 327 H Hanning window, 175 Harmonics, square wave, 189 High-frequency transconductor, 89-90 Highpass filter, 19, 129, 134 Higher order modulators, 267 Hold register, 46-50 Hysteresis, 246-247 I I, in phase or real component, 4-6, 285-286, 297-299 IIR. See Infinite impulse response filter. Impulse sampling, 28-31 Infinite impulse response (IIR) filter, 134 Integrator, analog. See Continuous-time analog integrator. digital, 19-21, 235 discrete analog integrator (DAI), 66-70, 90-93, 233, 251 gain, 113, 244-246, 248, 255, 257-260, 264, 276, 303 leakage, 247-248, 282 Interpolation, 32, 43-46, 48-50, 71, 139-142, 235, 273 Interpolative modulators, 271-272 Inverse Fourier transform, 23 J Jitter. See Clock jitter. K K, oversampling ratio, averaging factor, or interpolation increase, 33, 43-50 clock jitter, 181-182 K-Delta-1-Sigma, xvi, 222, 303-304, 320-324 K-path, Kpath, 50-53, 220-224, 228, 230, 301-302, 317 L Ladder filter, 117-118 Least significant bit (LSB), 119, 204 Limit cycle oscillations, 241, 315 Linear phase, 25, 30-31, 145 Linearity, 212, 214 Linearity requirements for averaging, 191-195 Lowpass filters, 73-74 LSB. See Least significant bit. M MASH modulator. See Noise-shaping Matching, 53, 55, 94, 200, 211, 212, 230, 279, 323 Matlab, 171 Mean, 186 Miller integrator, 75 Mixed-signal system block diagram, 27 Modulation noise, 206-208, 212, 237 Modulator, bandpass, 287-297 cascaded, 275 first-order, 233 gain, 243 higher-order, 265-269 interpolative, 271-272 multibit, 269 noise-shaping, 199-201, 233 predictive, 200 second-order, 253 MOSFET-C Integrators, 83-85 Multibit modulators, 269 Multiplexer (MUX), 236, 297 Multipliers, 34, 64, 94, 291, 297-298 Multistage noise shaping modulator (MASH), 275 MUX. See Multiplexer. N Noise, averaging, 190 clock jitter, correlated double sampling (CDS), 59, 66, 71 modulation, 206-208, 212 quantization noise, See Quantization noise. Noise transfer function (NTF), 200-201, 205-208, 224, 233, 253-254 Noise-shaping (NS), 199-201, 233, 253 Non-overlapping clock generation, 51, 53, 304, 317 Nonrecursive filters, 133 Number representation, 123-126 Nyquist, differences between noise-shaping converters, 241 frequency, 17, 21, 27, 29, 31, 37-40 rate ADC, 43, 63, 220-225, 241, 306-308 O Offset, autozero, 57-59, 62 comparator, 221-222, 224, 246 DAC, 214 op-amp, 54-55, 58-62, 66, 72, 212, 247-250 Offset binary format, 123-125, 204-205, 274 328 Index Overflow, 124-126, 143, 145-148, 211, 214-215, 221, 273 Oversampling, Oversampling ratio. See K, oversampling ratio or averaging factor. P Passive noise-shaping, 205-207, 216-219 Path settling time, 302 Pattern noise, 241 PDF, probability density function, 185 average value (mean or expected value), 186 Gaussian, 186-187, 197-198 standard deviation, 186 variance, 186 Phase-delay relationship, 4 Phase, discrete analog integrator (DAI), digital filter, 10-11, 13-15, 17-21, 130, 151 linear, 9, 30-31, 145, 171 noise, 188-189 response, 76, 79-81, 88, 104 shift, 4-5, 8, 95-96, 141 Phase-locked loop, 180 Pipeline ADC, 38, 122, 176, 220, 307 PLL. See Phase-locked loop. Power average, 183-184, 186-187 Power spectral density (PSD), 166, 172, 183, 188, 190, 193 jitter, 186-189, 198 quantization noise, 166, 168, 193 Predictive coder. See Predictive modulator. Predictive modulator, 199-200 Probability density function, See PDF. PSD. See Power spectral density. Q Q (pole quality factor), 99-106 high Q, 107-114, 117 peaking and instability, 112-113 QAM, See Quadrature amplitude modulation. Quadrature amplitude modulation, 285 Quadrature or imaginary component, 4-6, 285-290, 297-299 Quantization noise, 122, 163-178, 185-196, 211, 224, 233-234, 237, 240, 242-243, 251, 253, 266, 273-276, 279, 312-314 Quantize, 33 Quantizer, 43, 125, 163-164, 203-204, 235-239, 269, 271-274, 314 R Random signals, 185, 196, 216 quantization noise, 168-169 spectral density, 190 standard deviation, 186 variance, 186 RCF. See Reconstruction filter. Reconstruction filter (RCF), 27, 29, 32, 39, 87, 166, 139, 185, 187, 235, 273 Resolution, 13, 56-57, 83, 176, 191, 194-195, 199-200, 203, 209-210, 215, 230, 237-240, 253-254, 265, 269, 273, 306-307, 322 loss because of jitter, 178-181 Return-to-zero (RZ), 35, 37, 39, 42 Ripple, 241-242, 282, 288-289 RMS quantization noise voltage, 166, 168-170, 211, 237, 249, 253, 266-267 calculating from a spectrum, 185, 187, 193 Root mean square (RMS) voltage, 168 RZ. See Return-to-zero. S Sample and hold (S/H), 27, 35-43, 54-66 matching of the capacitors used, single-ended to differential, 65 subtraction, 63 Sample frequency reduction. See Decimation. Sampler, 28-35 Sampling and Aliasing, coherent. See coherent sampling. Sampling gate, 28 Second-order noise-shaping, 227-229, 253 Settling time, 57, 60-61, 221, 248-249, 302 SFDR. See Spurious-free-dynamic range. SFFM. See Single frequency frequency modulation. S/H. See Sample and hold. Side lobes, 47-48 Sigma-delta modulation, See noise-shaping Signal-to-noise and distortion ratio(SINAD). See Signal-to-noise plus distortion ratio (SNDR). Signal-to-noise plus distortion ratio (SNDR), 93, 176-178, 187, 197, 202 Signal-to-noise ratio (SNR), 70, 82-83, 87, 137, 163-202, 208-229, 238-242, 247-248, 250-253, 265 Signal transfer function (STF), 200-201, 205-206 Sinc filter, See digital averaging filter. Sinc function, 32, 36-39, 47-49 Sinc-shaped digital filter, 126-144 Slew-rate, 57, 179, 248-249 Smoothing filter, See reconstruction filter. SNR. See Signal-to-noise ratio. SNDR. See Signal-to-noise plus distortion ratio. Spike, 177 Index 329 Spurious free dynamic range (SFDR), 177, 242 Squarewave, 22, 25, 126-128, 166, 175 Stability, digital filter, 146 filter, 112 noise-shaping modulator, 258-264, 269, 275, 293 Standard deviation, 186, 198 Subtraction, 63, 126, 271 Switched-capacitor filters, 91-95, 98-99, 106-111 Switches, capacitive feedthrough, 39, 251 charge injection, 39-40, 251, 257, 294 MOSFET, 318 Z z defined, 7, 12 domain, 6-8 to s-transform (practical), 51, 149 z-plane, 7, 15 Zero-Order Hold (ZOH), 27 Zero padding, 44-45 T Taylor series, 6 T/H, See Track-and-hold. Thermometer code, 308 Time-domain description of reconstruction, 31-33 Time-interleaved ADC, 220-222, 232, 313, 323 Track-and-hold, 41-43 Transconductor-C filters, 86 bilinear, 97 biquad, 114 Triangular response, 133 Tuning, 80, 83, 86 orthogonal tuning, 98 Two’s complement, 123-126, 131, 137, 147, 204-205 subtraction, 126 U Unit step function. See u(t). u(t), 35-36 V Variance, 168, 186 VCM , (VDD/2 or 0.5 V in this book) VDD, (1.0 V in this book) Von Hann window. See Hanning window. W White noise, 169, 172, 269 Windowing, 175-176 Wireless, 285, 291 I/Q extraction, 297-298

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